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Merge branches 'pm-cpuidle', 'pm-cpufreq' and 'pm-sleep'
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_i915_private *dev_priv,
119 struct intel_crtc *crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
617 !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
622 !IS_BROXTON(dev_priv)) {
623 if (clock->p < limit->p.min || limit->p.max < clock->p)
624 INTELPllInvalid("p out of range\n");
625 if (clock->m < limit->m.min || limit->m.max < clock->m)
626 INTELPllInvalid("m out of range\n");
627 }
628
629 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
630 INTELPllInvalid("vco out of range\n");
631 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
632 * connector, etc., rather than just a single range.
633 */
634 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
635 INTELPllInvalid("dot out of range\n");
636
637 return true;
638 }
639
640 static int
641 i9xx_select_p2_div(const struct intel_limit *limit,
642 const struct intel_crtc_state *crtc_state,
643 int target)
644 {
645 struct drm_device *dev = crtc_state->base.crtc->dev;
646
647 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648 /*
649 * For LVDS just rely on its current settings for dual-channel.
650 * We haven't figured out how to reliably set up different
651 * single/dual channel state, if we even can.
652 */
653 if (intel_is_dual_link_lvds(dev))
654 return limit->p2.p2_fast;
655 else
656 return limit->p2.p2_slow;
657 } else {
658 if (target < limit->p2.dot_limit)
659 return limit->p2.p2_slow;
660 else
661 return limit->p2.p2_fast;
662 }
663 }
664
665 /*
666 * Returns a set of divisors for the desired target clock with the given
667 * refclk, or FALSE. The returned values represent the clock equation:
668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669 *
670 * Target and reference clocks are specified in kHz.
671 *
672 * If match_clock is provided, then best_clock P divider must match the P
673 * divider from @match_clock used for LVDS downclocking.
674 */
675 static bool
676 i9xx_find_best_dpll(const struct intel_limit *limit,
677 struct intel_crtc_state *crtc_state,
678 int target, int refclk, struct dpll *match_clock,
679 struct dpll *best_clock)
680 {
681 struct drm_device *dev = crtc_state->base.crtc->dev;
682 struct dpll clock;
683 int err = target;
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688
689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 clock.m1++) {
691 for (clock.m2 = limit->m2.min;
692 clock.m2 <= limit->m2.max; clock.m2++) {
693 if (clock.m2 >= clock.m1)
694 break;
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 i9xx_calc_dpll_params(refclk, &clock);
702 if (!intel_PLL_is_valid(to_i915(dev),
703 limit,
704 &clock))
705 continue;
706 if (match_clock &&
707 clock.p != match_clock->p)
708 continue;
709
710 this_err = abs(clock.dot - target);
711 if (this_err < err) {
712 *best_clock = clock;
713 err = this_err;
714 }
715 }
716 }
717 }
718 }
719
720 return (err != target);
721 }
722
723 /*
724 * Returns a set of divisors for the desired target clock with the given
725 * refclk, or FALSE. The returned values represent the clock equation:
726 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
727 *
728 * Target and reference clocks are specified in kHz.
729 *
730 * If match_clock is provided, then best_clock P divider must match the P
731 * divider from @match_clock used for LVDS downclocking.
732 */
733 static bool
734 pnv_find_best_dpll(const struct intel_limit *limit,
735 struct intel_crtc_state *crtc_state,
736 int target, int refclk, struct dpll *match_clock,
737 struct dpll *best_clock)
738 {
739 struct drm_device *dev = crtc_state->base.crtc->dev;
740 struct dpll clock;
741 int err = target;
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748 clock.m1++) {
749 for (clock.m2 = limit->m2.min;
750 clock.m2 <= limit->m2.max; clock.m2++) {
751 for (clock.n = limit->n.min;
752 clock.n <= limit->n.max; clock.n++) {
753 for (clock.p1 = limit->p1.min;
754 clock.p1 <= limit->p1.max; clock.p1++) {
755 int this_err;
756
757 pnv_calc_dpll_params(refclk, &clock);
758 if (!intel_PLL_is_valid(to_i915(dev),
759 limit,
760 &clock))
761 continue;
762 if (match_clock &&
763 clock.p != match_clock->p)
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 }
771 }
772 }
773 }
774 }
775
776 return (err != target);
777 }
778
779 /*
780 * Returns a set of divisors for the desired target clock with the given
781 * refclk, or FALSE. The returned values represent the clock equation:
782 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
783 *
784 * Target and reference clocks are specified in kHz.
785 *
786 * If match_clock is provided, then best_clock P divider must match the P
787 * divider from @match_clock used for LVDS downclocking.
788 */
789 static bool
790 g4x_find_best_dpll(const struct intel_limit *limit,
791 struct intel_crtc_state *crtc_state,
792 int target, int refclk, struct dpll *match_clock,
793 struct dpll *best_clock)
794 {
795 struct drm_device *dev = crtc_state->base.crtc->dev;
796 struct dpll clock;
797 int max_n;
798 bool found = false;
799 /* approximately equals target * 0.00585 */
800 int err_most = (target >> 8) + (target >> 9);
801
802 memset(best_clock, 0, sizeof(*best_clock));
803
804 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
805
806 max_n = limit->n.max;
807 /* based on hardware requirement, prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809 /* based on hardware requirement, prefere larger m1,m2 */
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
818 i9xx_calc_dpll_params(refclk, &clock);
819 if (!intel_PLL_is_valid(to_i915(dev),
820 limit,
821 &clock))
822 continue;
823
824 this_err = abs(clock.dot - target);
825 if (this_err < err_most) {
826 *best_clock = clock;
827 err_most = this_err;
828 max_n = clock.n;
829 found = true;
830 }
831 }
832 }
833 }
834 }
835 return found;
836 }
837
838 /*
839 * Check if the calculated PLL configuration is more optimal compared to the
840 * best configuration and error found so far. Return the calculated error.
841 */
842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
843 const struct dpll *calculated_clock,
844 const struct dpll *best_clock,
845 unsigned int best_error_ppm,
846 unsigned int *error_ppm)
847 {
848 /*
849 * For CHV ignore the error and consider only the P value.
850 * Prefer a bigger P value based on HW requirements.
851 */
852 if (IS_CHERRYVIEW(to_i915(dev))) {
853 *error_ppm = 0;
854
855 return calculated_clock->p > best_clock->p;
856 }
857
858 if (WARN_ON_ONCE(!target_freq))
859 return false;
860
861 *error_ppm = div_u64(1000000ULL *
862 abs(target_freq - calculated_clock->dot),
863 target_freq);
864 /*
865 * Prefer a better P value over a better (smaller) error if the error
866 * is small. Ensure this preference for future configurations too by
867 * setting the error to 0.
868 */
869 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
870 *error_ppm = 0;
871
872 return true;
873 }
874
875 return *error_ppm + 10 < best_error_ppm;
876 }
877
878 /*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
883 static bool
884 vlv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
888 {
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 struct dpll clock;
892 unsigned int bestppm = 1000000;
893 /* min update 19.2 MHz */
894 int max_n = min(limit->n.max, refclk / 19200);
895 bool found = false;
896
897 target *= 5; /* fast clock */
898
899 memset(best_clock, 0, sizeof(*best_clock));
900
901 /* based on hardware requirement, prefer smaller n to precision */
902 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
903 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
905 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
906 clock.p = clock.p1 * clock.p2;
907 /* based on hardware requirement, prefer bigger m1,m2 values */
908 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
909 unsigned int ppm;
910
911 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
912 refclk * clock.m1);
913
914 vlv_calc_dpll_params(refclk, &clock);
915
916 if (!intel_PLL_is_valid(to_i915(dev),
917 limit,
918 &clock))
919 continue;
920
921 if (!vlv_PLL_is_optimal(dev, target,
922 &clock,
923 best_clock,
924 bestppm, &ppm))
925 continue;
926
927 *best_clock = clock;
928 bestppm = ppm;
929 found = true;
930 }
931 }
932 }
933 }
934
935 return found;
936 }
937
938 /*
939 * Returns a set of divisors for the desired target clock with the given
940 * refclk, or FALSE. The returned values represent the clock equation:
941 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
942 */
943 static bool
944 chv_find_best_dpll(const struct intel_limit *limit,
945 struct intel_crtc_state *crtc_state,
946 int target, int refclk, struct dpll *match_clock,
947 struct dpll *best_clock)
948 {
949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
950 struct drm_device *dev = crtc->base.dev;
951 unsigned int best_error_ppm;
952 struct dpll clock;
953 uint64_t m2;
954 int found = false;
955
956 memset(best_clock, 0, sizeof(*best_clock));
957 best_error_ppm = 1000000;
958
959 /*
960 * Based on hardware doc, the n always set to 1, and m1 always
961 * set to 2. If requires to support 200Mhz refclk, we need to
962 * revisit this because n may not 1 anymore.
963 */
964 clock.n = 1, clock.m1 = 2;
965 target *= 5; /* fast clock */
966
967 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
968 for (clock.p2 = limit->p2.p2_fast;
969 clock.p2 >= limit->p2.p2_slow;
970 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971 unsigned int error_ppm;
972
973 clock.p = clock.p1 * clock.p2;
974
975 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
976 clock.n) << 22, refclk * clock.m1);
977
978 if (m2 > INT_MAX/clock.m1)
979 continue;
980
981 clock.m2 = m2;
982
983 chv_calc_dpll_params(refclk, &clock);
984
985 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
986 continue;
987
988 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
989 best_error_ppm, &error_ppm))
990 continue;
991
992 *best_clock = clock;
993 best_error_ppm = error_ppm;
994 found = true;
995 }
996 }
997
998 return found;
999 }
1000
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002 struct dpll *best_clock)
1003 {
1004 int refclk = 100000;
1005 const struct intel_limit *limit = &intel_limits_bxt;
1006
1007 return chv_find_best_dpll(limit, crtc_state,
1008 target_clock, refclk, NULL, best_clock);
1009 }
1010
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013 /* Be paranoid as we can arrive here with only partial
1014 * state retrieved from the hardware during setup.
1015 *
1016 * We can ditch the adjusted_mode.crtc_clock check as soon
1017 * as Haswell has gained clock readout/fastboot support.
1018 *
1019 * We can ditch the crtc->primary->fb check as soon as we can
1020 * properly reconstruct framebuffers.
1021 *
1022 * FIXME: The intel_crtc->active here should be switched to
1023 * crtc->state->active once we have proper CRTC states wired up
1024 * for atomic.
1025 */
1026 return crtc->active && crtc->base.primary->state->fb &&
1027 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031 enum pipe pipe)
1032 {
1033 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034
1035 return crtc->config->cpu_transcoder;
1036 }
1037
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040 i915_reg_t reg = PIPEDSL(pipe);
1041 u32 line1, line2;
1042 u32 line_mask;
1043
1044 if (IS_GEN2(dev_priv))
1045 line_mask = DSL_LINEMASK_GEN2;
1046 else
1047 line_mask = DSL_LINEMASK_GEN3;
1048
1049 line1 = I915_READ(reg) & line_mask;
1050 msleep(5);
1051 line2 = I915_READ(reg) & line_mask;
1052
1053 return line1 == line2;
1054 }
1055
1056 /*
1057 * intel_wait_for_pipe_off - wait for pipe to turn off
1058 * @crtc: crtc whose pipe to wait for
1059 *
1060 * After disabling a pipe, we can't wait for vblank in the usual way,
1061 * spinning on the vblank interrupt status bit, since we won't actually
1062 * see an interrupt when the pipe is disabled.
1063 *
1064 * On Gen4 and above:
1065 * wait for the pipe register state bit to turn off
1066 *
1067 * Otherwise:
1068 * wait for the display line value to settle (it usually
1069 * ends up stopping at the start of the next frame).
1070 *
1071 */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1077
1078 if (INTEL_GEN(dev_priv) >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
1085 WARN(1, "pipe_off wait timed out\n");
1086 } else {
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1090 }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 u32 val;
1098 bool cur_state;
1099
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110 u32 val;
1111 bool cur_state;
1112
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1116
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 } else {
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1171 return;
1172
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 u32 val;
1181 bool cur_state;
1182
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192 i915_reg_t pp_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (WARN_ON(HAS_DDI(dev_priv)))
1198 return;
1199
1200 if (HAS_PCH_SPLIT(dev_priv)) {
1201 u32 port_sel;
1202
1203 pp_reg = PP_CONTROL(0);
1204 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205
1206 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208 panel_pipe = PIPE_B;
1209 /* XXX: else fix for eDP */
1210 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211 /* presumably write lock depends on pipe, not port select */
1212 pp_reg = PP_CONTROL(pipe);
1213 panel_pipe = pipe;
1214 } else {
1215 pp_reg = PP_CONTROL(0);
1216 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217 panel_pipe = PIPE_B;
1218 }
1219
1220 val = I915_READ(pp_reg);
1221 if (!(val & PANEL_POWER_ON) ||
1222 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223 locked = false;
1224
1225 I915_STATE_WARN(panel_pipe == pipe && locked,
1226 "panel assertion failure, pipe %c regs locked\n",
1227 pipe_name(pipe));
1228 }
1229
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, bool state)
1232 {
1233 bool cur_state;
1234
1235 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1236 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237 else
1238 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239
1240 I915_STATE_WARN(cur_state != state,
1241 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242 pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
1249 {
1250 bool cur_state;
1251 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252 pipe);
1253 enum intel_display_power_domain power_domain;
1254
1255 /* if we need the pipe quirk it must be always on */
1256 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258 state = true;
1259
1260 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263 cur_state = !!(val & PIPECONF_ENABLE);
1264
1265 intel_display_power_put(dev_priv, power_domain);
1266 } else {
1267 cur_state = false;
1268 }
1269
1270 I915_STATE_WARN(cur_state != state,
1271 "pipe %c assertion failure (expected %s, current %s)\n",
1272 pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276 enum plane plane, bool state)
1277 {
1278 u32 val;
1279 bool cur_state;
1280
1281 val = I915_READ(DSPCNTR(plane));
1282 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283 I915_STATE_WARN(cur_state != state,
1284 "plane %c assertion failure (expected %s, current %s)\n",
1285 plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int i;
1295
1296 /* Primary planes are fixed to pipes on gen4+ */
1297 if (INTEL_GEN(dev_priv) >= 4) {
1298 u32 val = I915_READ(DSPCNTR(pipe));
1299 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300 "plane %c assertion failure, should be disabled but not\n",
1301 plane_name(pipe));
1302 return;
1303 }
1304
1305 /* Need to check both planes against the pipe */
1306 for_each_pipe(dev_priv, i) {
1307 u32 val = I915_READ(DSPCNTR(i));
1308 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309 DISPPLANE_SEL_PIPE_SHIFT;
1310 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312 plane_name(i), pipe_name(pipe));
1313 }
1314 }
1315
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318 {
1319 int sprite;
1320
1321 if (INTEL_GEN(dev_priv) >= 9) {
1322 for_each_sprite(dev_priv, pipe, sprite) {
1323 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326 sprite, pipe_name(pipe));
1327 }
1328 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329 for_each_sprite(dev_priv, pipe, sprite) {
1330 u32 val = I915_READ(SPCNTR(pipe, sprite));
1331 I915_STATE_WARN(val & SP_ENABLE,
1332 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333 sprite_name(pipe, sprite), pipe_name(pipe));
1334 }
1335 } else if (INTEL_GEN(dev_priv) >= 7) {
1336 u32 val = I915_READ(SPRCTL(pipe));
1337 I915_STATE_WARN(val & SPRITE_ENABLE,
1338 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339 plane_name(pipe), pipe_name(pipe));
1340 } else if (INTEL_GEN(dev_priv) >= 5) {
1341 u32 val = I915_READ(DVSCNTR(pipe));
1342 I915_STATE_WARN(val & DVS_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 }
1346 }
1347
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351 drm_crtc_vblank_put(crtc);
1352 }
1353
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 u32 val;
1358 bool enabled;
1359
1360 val = I915_READ(PCH_TRANSCONF(pipe));
1361 enabled = !!(val & TRANS_ENABLE);
1362 I915_STATE_WARN(enabled,
1363 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364 pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370 if ((val & DP_PORT_EN) == 0)
1371 return false;
1372
1373 if (HAS_PCH_CPT(dev_priv)) {
1374 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, i915_reg_t reg,
1439 u32 port_sel)
1440 {
1441 u32 val = I915_READ(reg);
1442 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444 i915_mmio_reg_offset(reg), pipe_name(pipe));
1445
1446 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447 && (val & DP_PIPEB_SELECT),
1448 "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, i915_reg_t reg)
1453 {
1454 u32 val = I915_READ(reg);
1455 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457 i915_mmio_reg_offset(reg), pipe_name(pipe));
1458
1459 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460 && (val & SDVO_PIPE_B_SELECT),
1461 "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe)
1466 {
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 val = I915_READ(PCH_ADPA);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1476 pipe_name(pipe));
1477
1478 val = I915_READ(PCH_LVDS);
1479 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489 const struct intel_crtc_state *pipe_config)
1490 {
1491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492 enum pipe pipe = crtc->pipe;
1493
1494 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495 POSTING_READ(DPLL(pipe));
1496 udelay(150);
1497
1498 if (intel_wait_for_register(dev_priv,
1499 DPLL(pipe),
1500 DPLL_LOCK_VLV,
1501 DPLL_LOCK_VLV,
1502 1))
1503 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507 const struct intel_crtc_state *pipe_config)
1508 {
1509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510 enum pipe pipe = crtc->pipe;
1511
1512 assert_pipe_disabled(dev_priv, pipe);
1513
1514 /* PLL is protected by panel, make sure we can write it */
1515 assert_panel_unlocked(dev_priv, pipe);
1516
1517 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518 _vlv_enable_pll(crtc, pipe_config);
1519
1520 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521 POSTING_READ(DPLL_MD(pipe));
1522 }
1523
1524
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526 const struct intel_crtc_state *pipe_config)
1527 {
1528 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529 enum pipe pipe = crtc->pipe;
1530 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531 u32 tmp;
1532
1533 mutex_lock(&dev_priv->sb_lock);
1534
1535 /* Enable back the 10bit clock to display controller */
1536 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537 tmp |= DPIO_DCLKP_EN;
1538 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539
1540 mutex_unlock(&dev_priv->sb_lock);
1541
1542 /*
1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544 */
1545 udelay(1);
1546
1547 /* Enable PLL */
1548 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549
1550 /* Check PLL is locked */
1551 if (intel_wait_for_register(dev_priv,
1552 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553 1))
1554 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558 const struct intel_crtc_state *pipe_config)
1559 {
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1562
1563 assert_pipe_disabled(dev_priv, pipe);
1564
1565 /* PLL is protected by panel, make sure we can write it */
1566 assert_panel_unlocked(dev_priv, pipe);
1567
1568 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569 _chv_enable_pll(crtc, pipe_config);
1570
1571 if (pipe != PIPE_A) {
1572 /*
1573 * WaPixelRepeatModeFixForC0:chv
1574 *
1575 * DPLLCMD is AWOL. Use chicken bits to propagate
1576 * the value from DPLLBMD to either pipe B or C.
1577 */
1578 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580 I915_WRITE(CBR4_VLV, 0);
1581 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582
1583 /*
1584 * DPLLB VGA mode also seems to cause problems.
1585 * We should always have it disabled.
1586 */
1587 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588 } else {
1589 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590 POSTING_READ(DPLL_MD(pipe));
1591 }
1592 }
1593
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596 struct intel_crtc *crtc;
1597 int count = 0;
1598
1599 for_each_intel_crtc(&dev_priv->drm, crtc) {
1600 count += crtc->base.state->active &&
1601 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602 }
1603
1604 return count;
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610 i915_reg_t reg = DPLL(crtc->pipe);
1611 u32 dpll = crtc->config->dpll_hw_state.dpll;
1612
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615 /* PLL is protected by panel, make sure we can write it */
1616 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617 assert_panel_unlocked(dev_priv, crtc->pipe);
1618
1619 /* Enable DVO 2x clock on both PLLs if necessary */
1620 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621 /*
1622 * It appears to be important that we don't enable this
1623 * for the current pipe before otherwise configuring the
1624 * PLL. No idea how this should be handled if multiple
1625 * DVO outputs are enabled simultaneosly.
1626 */
1627 dpll |= DPLL_DVO_2X_MODE;
1628 I915_WRITE(DPLL(!crtc->pipe),
1629 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630 }
1631
1632 /*
1633 * Apparently we need to have VGA mode enabled prior to changing
1634 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635 * dividers, even though the register value does change.
1636 */
1637 I915_WRITE(reg, 0);
1638
1639 I915_WRITE(reg, dpll);
1640
1641 /* Wait for the clocks to stabilize. */
1642 POSTING_READ(reg);
1643 udelay(150);
1644
1645 if (INTEL_GEN(dev_priv) >= 4) {
1646 I915_WRITE(DPLL_MD(crtc->pipe),
1647 crtc->config->dpll_hw_state.dpll_md);
1648 } else {
1649 /* The pixel multiplier can only be updated once the
1650 * DPLL is enabled and the clocks are stable.
1651 *
1652 * So write it again.
1653 */
1654 I915_WRITE(reg, dpll);
1655 }
1656
1657 /* We do this three times for luck */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664 I915_WRITE(reg, dpll);
1665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
1667 }
1668
1669 /**
1670 * i9xx_disable_pll - disable a PLL
1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe PLL to disable
1673 *
1674 * Disable the PLL for @pipe, making sure the pipe is off first.
1675 *
1676 * Note! This is for pre-ILK only.
1677 */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681 enum pipe pipe = crtc->pipe;
1682
1683 /* Disable DVO 2x clock on both PLLs if necessary */
1684 if (IS_I830(dev_priv) &&
1685 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686 !intel_num_dvo_pipes(dev_priv)) {
1687 I915_WRITE(DPLL(PIPE_B),
1688 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689 I915_WRITE(DPLL(PIPE_A),
1690 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691 }
1692
1693 /* Don't disable pipe or pipe PLLs if needed */
1694 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696 return;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702 POSTING_READ(DPLL(pipe));
1703 }
1704
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707 u32 val;
1708
1709 /* Make sure the pipe isn't still relying on us */
1710 assert_pipe_disabled(dev_priv, pipe);
1711
1712 val = DPLL_INTEGRATED_REF_CLK_VLV |
1713 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714 if (pipe != PIPE_A)
1715 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716
1717 I915_WRITE(DPLL(pipe), val);
1718 POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724 u32 val;
1725
1726 /* Make sure the pipe isn't still relying on us */
1727 assert_pipe_disabled(dev_priv, pipe);
1728
1729 val = DPLL_SSC_REF_CLK_CHV |
1730 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731 if (pipe != PIPE_A)
1732 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733
1734 I915_WRITE(DPLL(pipe), val);
1735 POSTING_READ(DPLL(pipe));
1736
1737 mutex_lock(&dev_priv->sb_lock);
1738
1739 /* Disable 10bit clock to display controller */
1740 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741 val &= ~DPIO_DCLKP_EN;
1742 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743
1744 mutex_unlock(&dev_priv->sb_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748 struct intel_digital_port *dport,
1749 unsigned int expected_mask)
1750 {
1751 u32 port_mask;
1752 i915_reg_t dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 expected_mask <<= 4;
1763 break;
1764 case PORT_D:
1765 port_mask = DPLL_PORTD_READY_MASK;
1766 dpll_reg = DPIO_PHY_STATUS;
1767 break;
1768 default:
1769 BUG();
1770 }
1771
1772 if (intel_wait_for_register(dev_priv,
1773 dpll_reg, port_mask, expected_mask,
1774 1000))
1775 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780 enum pipe pipe)
1781 {
1782 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783 pipe);
1784 i915_reg_t reg;
1785 uint32_t val, pipeconf_val;
1786
1787 /* Make sure PCH DPLL is enabled */
1788 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789
1790 /* FDI must be feeding us bits for PCH ports */
1791 assert_fdi_tx_enabled(dev_priv, pipe);
1792 assert_fdi_rx_enabled(dev_priv, pipe);
1793
1794 if (HAS_PCH_CPT(dev_priv)) {
1795 /* Workaround: Set the timing override bit before enabling the
1796 * pch transcoder. */
1797 reg = TRANS_CHICKEN2(pipe);
1798 val = I915_READ(reg);
1799 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800 I915_WRITE(reg, val);
1801 }
1802
1803 reg = PCH_TRANSCONF(pipe);
1804 val = I915_READ(reg);
1805 pipeconf_val = I915_READ(PIPECONF(pipe));
1806
1807 if (HAS_PCH_IBX(dev_priv)) {
1808 /*
1809 * Make the BPC in transcoder be consistent with
1810 * that in pipeconf reg. For HDMI we must use 8bpc
1811 * here for both 8bpc and 12bpc.
1812 */
1813 val &= ~PIPECONF_BPC_MASK;
1814 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815 val |= PIPECONF_8BPC;
1816 else
1817 val |= pipeconf_val & PIPECONF_BPC_MASK;
1818 }
1819
1820 val &= ~TRANS_INTERLACE_MASK;
1821 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822 if (HAS_PCH_IBX(dev_priv) &&
1823 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824 val |= TRANS_LEGACY_INTERLACED_ILK;
1825 else
1826 val |= TRANS_INTERLACED;
1827 else
1828 val |= TRANS_PROGRESSIVE;
1829
1830 I915_WRITE(reg, val | TRANS_ENABLE);
1831 if (intel_wait_for_register(dev_priv,
1832 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833 100))
1834 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838 enum transcoder cpu_transcoder)
1839 {
1840 u32 val, pipeconf_val;
1841
1842 /* FDI must be feeding us bits for PCH ports */
1843 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845
1846 /* Workaround: set timing override bit. */
1847 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850
1851 val = TRANS_ENABLE;
1852 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853
1854 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855 PIPECONF_INTERLACED_ILK)
1856 val |= TRANS_INTERLACED;
1857 else
1858 val |= TRANS_PROGRESSIVE;
1859
1860 I915_WRITE(LPT_TRANSCONF, val);
1861 if (intel_wait_for_register(dev_priv,
1862 LPT_TRANSCONF,
1863 TRANS_STATE_ENABLE,
1864 TRANS_STATE_ENABLE,
1865 100))
1866 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870 enum pipe pipe)
1871 {
1872 i915_reg_t reg;
1873 uint32_t val;
1874
1875 /* FDI relies on the transcoder */
1876 assert_fdi_tx_disabled(dev_priv, pipe);
1877 assert_fdi_rx_disabled(dev_priv, pipe);
1878
1879 /* Ports must be off as well */
1880 assert_pch_ports_disabled(dev_priv, pipe);
1881
1882 reg = PCH_TRANSCONF(pipe);
1883 val = I915_READ(reg);
1884 val &= ~TRANS_ENABLE;
1885 I915_WRITE(reg, val);
1886 /* wait for PCH transcoder off, transcoder state */
1887 if (intel_wait_for_register(dev_priv,
1888 reg, TRANS_STATE_ENABLE, 0,
1889 50))
1890 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891
1892 if (HAS_PCH_CPT(dev_priv)) {
1893 /* Workaround: Clear the timing override chicken bit again. */
1894 reg = TRANS_CHICKEN2(pipe);
1895 val = I915_READ(reg);
1896 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897 I915_WRITE(reg, val);
1898 }
1899 }
1900
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903 u32 val;
1904
1905 val = I915_READ(LPT_TRANSCONF);
1906 val &= ~TRANS_ENABLE;
1907 I915_WRITE(LPT_TRANSCONF, val);
1908 /* wait for PCH transcoder off, transcoder state */
1909 if (intel_wait_for_register(dev_priv,
1910 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911 50))
1912 DRM_ERROR("Failed to disable PCH transcoder\n");
1913
1914 /* Workaround: clear timing override bit. */
1915 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923
1924 WARN_ON(!crtc->config->has_pch_encoder);
1925
1926 if (HAS_PCH_LPT(dev_priv))
1927 return TRANSCODER_A;
1928 else
1929 return (enum transcoder) crtc->pipe;
1930 }
1931
1932 /**
1933 * intel_enable_pipe - enable a pipe, asserting requirements
1934 * @crtc: crtc responsible for the pipe
1935 *
1936 * Enable @crtc's pipe, making sure that various hardware specific requirements
1937 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938 */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941 struct drm_device *dev = crtc->base.dev;
1942 struct drm_i915_private *dev_priv = to_i915(dev);
1943 enum pipe pipe = crtc->pipe;
1944 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945 i915_reg_t reg;
1946 u32 val;
1947
1948 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949
1950 assert_planes_disabled(dev_priv, pipe);
1951 assert_cursor_disabled(dev_priv, pipe);
1952 assert_sprites_disabled(dev_priv, pipe);
1953
1954 /*
1955 * A pipe without a PLL won't actually be able to drive bits from
1956 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1957 * need the check.
1958 */
1959 if (HAS_GMCH_DISPLAY(dev_priv)) {
1960 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961 assert_dsi_pll_enabled(dev_priv);
1962 else
1963 assert_pll_enabled(dev_priv, pipe);
1964 } else {
1965 if (crtc->config->has_pch_encoder) {
1966 /* if driving the PCH, we need FDI enabled */
1967 assert_fdi_rx_pll_enabled(dev_priv,
1968 (enum pipe) intel_crtc_pch_transcoder(crtc));
1969 assert_fdi_tx_pll_enabled(dev_priv,
1970 (enum pipe) cpu_transcoder);
1971 }
1972 /* FIXME: assert CPU port conditions for SNB+ */
1973 }
1974
1975 reg = PIPECONF(cpu_transcoder);
1976 val = I915_READ(reg);
1977 if (val & PIPECONF_ENABLE) {
1978 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980 return;
1981 }
1982
1983 I915_WRITE(reg, val | PIPECONF_ENABLE);
1984 POSTING_READ(reg);
1985
1986 /*
1987 * Until the pipe starts DSL will read as 0, which would cause
1988 * an apparent vblank timestamp jump, which messes up also the
1989 * frame count when it's derived from the timestamps. So let's
1990 * wait for the pipe to start properly before we call
1991 * drm_crtc_vblank_on()
1992 */
1993 if (dev->max_vblank_count == 0 &&
1994 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997
1998 /**
1999 * intel_disable_pipe - disable a pipe, asserting requirements
2000 * @crtc: crtc whose pipes is to be disabled
2001 *
2002 * Disable the pipe of @crtc, making sure that various hardware
2003 * specific requirements are met, if applicable, e.g. plane
2004 * disabled, panel fitter off, etc.
2005 *
2006 * Will wait until the pipe has shut down before returning.
2007 */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012 enum pipe pipe = crtc->pipe;
2013 i915_reg_t reg;
2014 u32 val;
2015
2016 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017
2018 /*
2019 * Make sure planes won't keep trying to pump pixels to us,
2020 * or we might hang the display.
2021 */
2022 assert_planes_disabled(dev_priv, pipe);
2023 assert_cursor_disabled(dev_priv, pipe);
2024 assert_sprites_disabled(dev_priv, pipe);
2025
2026 reg = PIPECONF(cpu_transcoder);
2027 val = I915_READ(reg);
2028 if ((val & PIPECONF_ENABLE) == 0)
2029 return;
2030
2031 /*
2032 * Double wide has implications for planes
2033 * so best keep it disabled when not needed.
2034 */
2035 if (crtc->config->double_wide)
2036 val &= ~PIPECONF_DOUBLE_WIDE;
2037
2038 /* Don't disable pipe or pipe PLLs if needed */
2039 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041 val &= ~PIPECONF_ENABLE;
2042
2043 I915_WRITE(reg, val);
2044 if ((val & PIPECONF_ENABLE) == 0)
2045 intel_wait_for_pipe_off(crtc);
2046 }
2047
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050 return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054 uint64_t fb_modifier, unsigned int cpp)
2055 {
2056 switch (fb_modifier) {
2057 case DRM_FORMAT_MOD_NONE:
2058 return cpp;
2059 case I915_FORMAT_MOD_X_TILED:
2060 if (IS_GEN2(dev_priv))
2061 return 128;
2062 else
2063 return 512;
2064 case I915_FORMAT_MOD_Y_TILED:
2065 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066 return 128;
2067 else
2068 return 512;
2069 case I915_FORMAT_MOD_Yf_TILED:
2070 switch (cpp) {
2071 case 1:
2072 return 64;
2073 case 2:
2074 case 4:
2075 return 128;
2076 case 8:
2077 case 16:
2078 return 256;
2079 default:
2080 MISSING_CASE(cpp);
2081 return cpp;
2082 }
2083 break;
2084 default:
2085 MISSING_CASE(fb_modifier);
2086 return cpp;
2087 }
2088 }
2089
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091 uint64_t fb_modifier, unsigned int cpp)
2092 {
2093 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094 return 1;
2095 else
2096 return intel_tile_size(dev_priv) /
2097 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102 unsigned int *tile_width,
2103 unsigned int *tile_height,
2104 uint64_t fb_modifier,
2105 unsigned int cpp)
2106 {
2107 unsigned int tile_width_bytes =
2108 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109
2110 *tile_width = tile_width_bytes / cpp;
2111 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116 uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120
2121 return ALIGN(height, tile_height);
2122 }
2123
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126 unsigned int size = 0;
2127 int i;
2128
2129 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131
2132 return size;
2133 }
2134
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137 const struct drm_framebuffer *fb,
2138 unsigned int rotation)
2139 {
2140 if (drm_rotation_90_or_270(rotation)) {
2141 *view = i915_ggtt_view_rotated;
2142 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2143 } else {
2144 *view = i915_ggtt_view_normal;
2145 }
2146 }
2147
2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2149 {
2150 if (INTEL_INFO(dev_priv)->gen >= 9)
2151 return 256 * 1024;
2152 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2153 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2154 return 128 * 1024;
2155 else if (INTEL_INFO(dev_priv)->gen >= 4)
2156 return 4 * 1024;
2157 else
2158 return 0;
2159 }
2160
2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2162 uint64_t fb_modifier)
2163 {
2164 switch (fb_modifier) {
2165 case DRM_FORMAT_MOD_NONE:
2166 return intel_linear_alignment(dev_priv);
2167 case I915_FORMAT_MOD_X_TILED:
2168 if (INTEL_INFO(dev_priv)->gen >= 9)
2169 return 256 * 1024;
2170 return 0;
2171 case I915_FORMAT_MOD_Y_TILED:
2172 case I915_FORMAT_MOD_Yf_TILED:
2173 return 1 * 1024 * 1024;
2174 default:
2175 MISSING_CASE(fb_modifier);
2176 return 0;
2177 }
2178 }
2179
2180 struct i915_vma *
2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2182 {
2183 struct drm_device *dev = fb->dev;
2184 struct drm_i915_private *dev_priv = to_i915(dev);
2185 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2186 struct i915_ggtt_view view;
2187 struct i915_vma *vma;
2188 u32 alignment;
2189
2190 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2191
2192 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2193
2194 intel_fill_fb_ggtt_view(&view, fb, rotation);
2195
2196 /* Note that the w/a also requires 64 PTE of padding following the
2197 * bo. We currently fill all unused PTE with the shadow page and so
2198 * we should always have valid PTE following the scanout preventing
2199 * the VT-d warning.
2200 */
2201 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2202 alignment = 256 * 1024;
2203
2204 /*
2205 * Global gtt pte registers are special registers which actually forward
2206 * writes to a chunk of system memory. Which means that there is no risk
2207 * that the register values disappear as soon as we call
2208 * intel_runtime_pm_put(), so it is correct to wrap only the
2209 * pin/unpin/fence and not more.
2210 */
2211 intel_runtime_pm_get(dev_priv);
2212
2213 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2214 if (IS_ERR(vma))
2215 goto err;
2216
2217 if (i915_vma_is_map_and_fenceable(vma)) {
2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219 * fence, whereas 965+ only requires a fence if using
2220 * framebuffer compression. For simplicity, we always, when
2221 * possible, install a fence as the cost is not that onerous.
2222 *
2223 * If we fail to fence the tiled scanout, then either the
2224 * modeset will reject the change (which is highly unlikely as
2225 * the affected systems, all but one, do not have unmappable
2226 * space) or we will not be able to enable full powersaving
2227 * techniques (also likely not to apply due to various limits
2228 * FBC and the like impose on the size of the buffer, which
2229 * presumably we violated anyway with this unmappable buffer).
2230 * Anyway, it is presumably better to stumble onwards with
2231 * something and try to run the system in a "less than optimal"
2232 * mode that matches the user configuration.
2233 */
2234 if (i915_vma_get_fence(vma) == 0)
2235 i915_vma_pin_fence(vma);
2236 }
2237
2238 i915_vma_get(vma);
2239 err:
2240 intel_runtime_pm_put(dev_priv);
2241 return vma;
2242 }
2243
2244 void intel_unpin_fb_vma(struct i915_vma *vma)
2245 {
2246 lockdep_assert_held(&vma->vm->dev->struct_mutex);
2247
2248 if (WARN_ON_ONCE(!vma))
2249 return;
2250
2251 i915_vma_unpin_fence(vma);
2252 i915_gem_object_unpin_from_display_plane(vma);
2253 i915_vma_put(vma);
2254 }
2255
2256 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2257 unsigned int rotation)
2258 {
2259 if (drm_rotation_90_or_270(rotation))
2260 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2261 else
2262 return fb->pitches[plane];
2263 }
2264
2265 /*
2266 * Convert the x/y offsets into a linear offset.
2267 * Only valid with 0/180 degree rotation, which is fine since linear
2268 * offset is only used with linear buffers on pre-hsw and tiled buffers
2269 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2270 */
2271 u32 intel_fb_xy_to_linear(int x, int y,
2272 const struct intel_plane_state *state,
2273 int plane)
2274 {
2275 const struct drm_framebuffer *fb = state->base.fb;
2276 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2277 unsigned int pitch = fb->pitches[plane];
2278
2279 return y * pitch + x * cpp;
2280 }
2281
2282 /*
2283 * Add the x/y offsets derived from fb->offsets[] to the user
2284 * specified plane src x/y offsets. The resulting x/y offsets
2285 * specify the start of scanout from the beginning of the gtt mapping.
2286 */
2287 void intel_add_fb_offsets(int *x, int *y,
2288 const struct intel_plane_state *state,
2289 int plane)
2290
2291 {
2292 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2293 unsigned int rotation = state->base.rotation;
2294
2295 if (drm_rotation_90_or_270(rotation)) {
2296 *x += intel_fb->rotated[plane].x;
2297 *y += intel_fb->rotated[plane].y;
2298 } else {
2299 *x += intel_fb->normal[plane].x;
2300 *y += intel_fb->normal[plane].y;
2301 }
2302 }
2303
2304 /*
2305 * Input tile dimensions and pitch must already be
2306 * rotated to match x and y, and in pixel units.
2307 */
2308 static u32 _intel_adjust_tile_offset(int *x, int *y,
2309 unsigned int tile_width,
2310 unsigned int tile_height,
2311 unsigned int tile_size,
2312 unsigned int pitch_tiles,
2313 u32 old_offset,
2314 u32 new_offset)
2315 {
2316 unsigned int pitch_pixels = pitch_tiles * tile_width;
2317 unsigned int tiles;
2318
2319 WARN_ON(old_offset & (tile_size - 1));
2320 WARN_ON(new_offset & (tile_size - 1));
2321 WARN_ON(new_offset > old_offset);
2322
2323 tiles = (old_offset - new_offset) / tile_size;
2324
2325 *y += tiles / pitch_tiles * tile_height;
2326 *x += tiles % pitch_tiles * tile_width;
2327
2328 /* minimize x in case it got needlessly big */
2329 *y += *x / pitch_pixels * tile_height;
2330 *x %= pitch_pixels;
2331
2332 return new_offset;
2333 }
2334
2335 /*
2336 * Adjust the tile offset by moving the difference into
2337 * the x/y offsets.
2338 */
2339 static u32 intel_adjust_tile_offset(int *x, int *y,
2340 const struct intel_plane_state *state, int plane,
2341 u32 old_offset, u32 new_offset)
2342 {
2343 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2344 const struct drm_framebuffer *fb = state->base.fb;
2345 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2346 unsigned int rotation = state->base.rotation;
2347 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2348
2349 WARN_ON(new_offset > old_offset);
2350
2351 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2352 unsigned int tile_size, tile_width, tile_height;
2353 unsigned int pitch_tiles;
2354
2355 tile_size = intel_tile_size(dev_priv);
2356 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2357 fb->modifier, cpp);
2358
2359 if (drm_rotation_90_or_270(rotation)) {
2360 pitch_tiles = pitch / tile_height;
2361 swap(tile_width, tile_height);
2362 } else {
2363 pitch_tiles = pitch / (tile_width * cpp);
2364 }
2365
2366 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2367 tile_size, pitch_tiles,
2368 old_offset, new_offset);
2369 } else {
2370 old_offset += *y * pitch + *x * cpp;
2371
2372 *y = (old_offset - new_offset) / pitch;
2373 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2374 }
2375
2376 return new_offset;
2377 }
2378
2379 /*
2380 * Computes the linear offset to the base tile and adjusts
2381 * x, y. bytes per pixel is assumed to be a power-of-two.
2382 *
2383 * In the 90/270 rotated case, x and y are assumed
2384 * to be already rotated to match the rotated GTT view, and
2385 * pitch is the tile_height aligned framebuffer height.
2386 *
2387 * This function is used when computing the derived information
2388 * under intel_framebuffer, so using any of that information
2389 * here is not allowed. Anything under drm_framebuffer can be
2390 * used. This is why the user has to pass in the pitch since it
2391 * is specified in the rotated orientation.
2392 */
2393 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2394 int *x, int *y,
2395 const struct drm_framebuffer *fb, int plane,
2396 unsigned int pitch,
2397 unsigned int rotation,
2398 u32 alignment)
2399 {
2400 uint64_t fb_modifier = fb->modifier;
2401 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2402 u32 offset, offset_aligned;
2403
2404 if (alignment)
2405 alignment--;
2406
2407 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2408 unsigned int tile_size, tile_width, tile_height;
2409 unsigned int tile_rows, tiles, pitch_tiles;
2410
2411 tile_size = intel_tile_size(dev_priv);
2412 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2413 fb_modifier, cpp);
2414
2415 if (drm_rotation_90_or_270(rotation)) {
2416 pitch_tiles = pitch / tile_height;
2417 swap(tile_width, tile_height);
2418 } else {
2419 pitch_tiles = pitch / (tile_width * cpp);
2420 }
2421
2422 tile_rows = *y / tile_height;
2423 *y %= tile_height;
2424
2425 tiles = *x / tile_width;
2426 *x %= tile_width;
2427
2428 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2429 offset_aligned = offset & ~alignment;
2430
2431 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2432 tile_size, pitch_tiles,
2433 offset, offset_aligned);
2434 } else {
2435 offset = *y * pitch + *x * cpp;
2436 offset_aligned = offset & ~alignment;
2437
2438 *y = (offset & alignment) / pitch;
2439 *x = ((offset & alignment) - *y * pitch) / cpp;
2440 }
2441
2442 return offset_aligned;
2443 }
2444
2445 u32 intel_compute_tile_offset(int *x, int *y,
2446 const struct intel_plane_state *state,
2447 int plane)
2448 {
2449 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2450 const struct drm_framebuffer *fb = state->base.fb;
2451 unsigned int rotation = state->base.rotation;
2452 int pitch = intel_fb_pitch(fb, plane, rotation);
2453 u32 alignment;
2454
2455 /* AUX_DIST needs only 4K alignment */
2456 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2457 alignment = 4096;
2458 else
2459 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2460
2461 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2462 rotation, alignment);
2463 }
2464
2465 /* Convert the fb->offset[] linear offset into x/y offsets */
2466 static void intel_fb_offset_to_xy(int *x, int *y,
2467 const struct drm_framebuffer *fb, int plane)
2468 {
2469 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2470 unsigned int pitch = fb->pitches[plane];
2471 u32 linear_offset = fb->offsets[plane];
2472
2473 *y = linear_offset / pitch;
2474 *x = linear_offset % pitch / cpp;
2475 }
2476
2477 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2478 {
2479 switch (fb_modifier) {
2480 case I915_FORMAT_MOD_X_TILED:
2481 return I915_TILING_X;
2482 case I915_FORMAT_MOD_Y_TILED:
2483 return I915_TILING_Y;
2484 default:
2485 return I915_TILING_NONE;
2486 }
2487 }
2488
2489 static int
2490 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2491 struct drm_framebuffer *fb)
2492 {
2493 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2494 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2495 u32 gtt_offset_rotated = 0;
2496 unsigned int max_size = 0;
2497 uint32_t format = fb->pixel_format;
2498 int i, num_planes = drm_format_num_planes(format);
2499 unsigned int tile_size = intel_tile_size(dev_priv);
2500
2501 for (i = 0; i < num_planes; i++) {
2502 unsigned int width, height;
2503 unsigned int cpp, size;
2504 u32 offset;
2505 int x, y;
2506
2507 cpp = drm_format_plane_cpp(format, i);
2508 width = drm_format_plane_width(fb->width, format, i);
2509 height = drm_format_plane_height(fb->height, format, i);
2510
2511 intel_fb_offset_to_xy(&x, &y, fb, i);
2512
2513 /*
2514 * The fence (if used) is aligned to the start of the object
2515 * so having the framebuffer wrap around across the edge of the
2516 * fenced region doesn't really work. We have no API to configure
2517 * the fence start offset within the object (nor could we probably
2518 * on gen2/3). So it's just easier if we just require that the
2519 * fb layout agrees with the fence layout. We already check that the
2520 * fb stride matches the fence stride elsewhere.
2521 */
2522 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2523 (x + width) * cpp > fb->pitches[i]) {
2524 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2525 i, fb->offsets[i]);
2526 return -EINVAL;
2527 }
2528
2529 /*
2530 * First pixel of the framebuffer from
2531 * the start of the normal gtt mapping.
2532 */
2533 intel_fb->normal[i].x = x;
2534 intel_fb->normal[i].y = y;
2535
2536 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2537 fb, 0, fb->pitches[i],
2538 DRM_ROTATE_0, tile_size);
2539 offset /= tile_size;
2540
2541 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2542 unsigned int tile_width, tile_height;
2543 unsigned int pitch_tiles;
2544 struct drm_rect r;
2545
2546 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2547 fb->modifier, cpp);
2548
2549 rot_info->plane[i].offset = offset;
2550 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2551 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2552 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2553
2554 intel_fb->rotated[i].pitch =
2555 rot_info->plane[i].height * tile_height;
2556
2557 /* how many tiles does this plane need */
2558 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2559 /*
2560 * If the plane isn't horizontally tile aligned,
2561 * we need one more tile.
2562 */
2563 if (x != 0)
2564 size++;
2565
2566 /* rotate the x/y offsets to match the GTT view */
2567 r.x1 = x;
2568 r.y1 = y;
2569 r.x2 = x + width;
2570 r.y2 = y + height;
2571 drm_rect_rotate(&r,
2572 rot_info->plane[i].width * tile_width,
2573 rot_info->plane[i].height * tile_height,
2574 DRM_ROTATE_270);
2575 x = r.x1;
2576 y = r.y1;
2577
2578 /* rotate the tile dimensions to match the GTT view */
2579 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2580 swap(tile_width, tile_height);
2581
2582 /*
2583 * We only keep the x/y offsets, so push all of the
2584 * gtt offset into the x/y offsets.
2585 */
2586 _intel_adjust_tile_offset(&x, &y,
2587 tile_width, tile_height,
2588 tile_size, pitch_tiles,
2589 gtt_offset_rotated * tile_size, 0);
2590
2591 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2592
2593 /*
2594 * First pixel of the framebuffer from
2595 * the start of the rotated gtt mapping.
2596 */
2597 intel_fb->rotated[i].x = x;
2598 intel_fb->rotated[i].y = y;
2599 } else {
2600 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2601 x * cpp, tile_size);
2602 }
2603
2604 /* how many tiles in total needed in the bo */
2605 max_size = max(max_size, offset + size);
2606 }
2607
2608 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2609 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2610 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2611 return -EINVAL;
2612 }
2613
2614 return 0;
2615 }
2616
2617 static int i9xx_format_to_fourcc(int format)
2618 {
2619 switch (format) {
2620 case DISPPLANE_8BPP:
2621 return DRM_FORMAT_C8;
2622 case DISPPLANE_BGRX555:
2623 return DRM_FORMAT_XRGB1555;
2624 case DISPPLANE_BGRX565:
2625 return DRM_FORMAT_RGB565;
2626 default:
2627 case DISPPLANE_BGRX888:
2628 return DRM_FORMAT_XRGB8888;
2629 case DISPPLANE_RGBX888:
2630 return DRM_FORMAT_XBGR8888;
2631 case DISPPLANE_BGRX101010:
2632 return DRM_FORMAT_XRGB2101010;
2633 case DISPPLANE_RGBX101010:
2634 return DRM_FORMAT_XBGR2101010;
2635 }
2636 }
2637
2638 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2639 {
2640 switch (format) {
2641 case PLANE_CTL_FORMAT_RGB_565:
2642 return DRM_FORMAT_RGB565;
2643 default:
2644 case PLANE_CTL_FORMAT_XRGB_8888:
2645 if (rgb_order) {
2646 if (alpha)
2647 return DRM_FORMAT_ABGR8888;
2648 else
2649 return DRM_FORMAT_XBGR8888;
2650 } else {
2651 if (alpha)
2652 return DRM_FORMAT_ARGB8888;
2653 else
2654 return DRM_FORMAT_XRGB8888;
2655 }
2656 case PLANE_CTL_FORMAT_XRGB_2101010:
2657 if (rgb_order)
2658 return DRM_FORMAT_XBGR2101010;
2659 else
2660 return DRM_FORMAT_XRGB2101010;
2661 }
2662 }
2663
2664 static bool
2665 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2666 struct intel_initial_plane_config *plane_config)
2667 {
2668 struct drm_device *dev = crtc->base.dev;
2669 struct drm_i915_private *dev_priv = to_i915(dev);
2670 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2671 struct drm_i915_gem_object *obj = NULL;
2672 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2673 struct drm_framebuffer *fb = &plane_config->fb->base;
2674 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2675 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2676 PAGE_SIZE);
2677
2678 size_aligned -= base_aligned;
2679
2680 if (plane_config->size == 0)
2681 return false;
2682
2683 /* If the FB is too big, just don't use it since fbdev is not very
2684 * important and we should probably use that space with FBC or other
2685 * features. */
2686 if (size_aligned * 2 > ggtt->stolen_usable_size)
2687 return false;
2688
2689 mutex_lock(&dev->struct_mutex);
2690
2691 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2692 base_aligned,
2693 base_aligned,
2694 size_aligned);
2695 if (!obj) {
2696 mutex_unlock(&dev->struct_mutex);
2697 return false;
2698 }
2699
2700 if (plane_config->tiling == I915_TILING_X)
2701 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2702
2703 mode_cmd.pixel_format = fb->pixel_format;
2704 mode_cmd.width = fb->width;
2705 mode_cmd.height = fb->height;
2706 mode_cmd.pitches[0] = fb->pitches[0];
2707 mode_cmd.modifier[0] = fb->modifier;
2708 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2709
2710 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2711 &mode_cmd, obj)) {
2712 DRM_DEBUG_KMS("intel fb init failed\n");
2713 goto out_unref_obj;
2714 }
2715
2716 mutex_unlock(&dev->struct_mutex);
2717
2718 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2719 return true;
2720
2721 out_unref_obj:
2722 i915_gem_object_put(obj);
2723 mutex_unlock(&dev->struct_mutex);
2724 return false;
2725 }
2726
2727 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2728 static void
2729 update_state_fb(struct drm_plane *plane)
2730 {
2731 if (plane->fb == plane->state->fb)
2732 return;
2733
2734 if (plane->state->fb)
2735 drm_framebuffer_unreference(plane->state->fb);
2736 plane->state->fb = plane->fb;
2737 if (plane->state->fb)
2738 drm_framebuffer_reference(plane->state->fb);
2739 }
2740
2741 static void
2742 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2743 struct intel_initial_plane_config *plane_config)
2744 {
2745 struct drm_device *dev = intel_crtc->base.dev;
2746 struct drm_i915_private *dev_priv = to_i915(dev);
2747 struct drm_crtc *c;
2748 struct drm_i915_gem_object *obj;
2749 struct drm_plane *primary = intel_crtc->base.primary;
2750 struct drm_plane_state *plane_state = primary->state;
2751 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2752 struct intel_plane *intel_plane = to_intel_plane(primary);
2753 struct intel_plane_state *intel_state =
2754 to_intel_plane_state(plane_state);
2755 struct drm_framebuffer *fb;
2756
2757 if (!plane_config->fb)
2758 return;
2759
2760 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2761 fb = &plane_config->fb->base;
2762 goto valid_fb;
2763 }
2764
2765 kfree(plane_config->fb);
2766
2767 /*
2768 * Failed to alloc the obj, check to see if we should share
2769 * an fb with another CRTC instead
2770 */
2771 for_each_crtc(dev, c) {
2772 struct intel_plane_state *state;
2773
2774 if (c == &intel_crtc->base)
2775 continue;
2776
2777 if (!to_intel_crtc(c)->active)
2778 continue;
2779
2780 state = to_intel_plane_state(c->primary->state);
2781 if (!state->vma)
2782 continue;
2783
2784 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2785 fb = c->primary->fb;
2786 drm_framebuffer_reference(fb);
2787 goto valid_fb;
2788 }
2789 }
2790
2791 /*
2792 * We've failed to reconstruct the BIOS FB. Current display state
2793 * indicates that the primary plane is visible, but has a NULL FB,
2794 * which will lead to problems later if we don't fix it up. The
2795 * simplest solution is to just disable the primary plane now and
2796 * pretend the BIOS never had it enabled.
2797 */
2798 to_intel_plane_state(plane_state)->base.visible = false;
2799 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2800 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2801 intel_plane->disable_plane(primary, &intel_crtc->base);
2802
2803 return;
2804
2805 valid_fb:
2806 mutex_lock(&dev->struct_mutex);
2807 intel_state->vma =
2808 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2809 mutex_unlock(&dev->struct_mutex);
2810 if (IS_ERR(intel_state->vma)) {
2811 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2812 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2813
2814 intel_state->vma = NULL;
2815 drm_framebuffer_unreference(fb);
2816 return;
2817 }
2818
2819 plane_state->src_x = 0;
2820 plane_state->src_y = 0;
2821 plane_state->src_w = fb->width << 16;
2822 plane_state->src_h = fb->height << 16;
2823
2824 plane_state->crtc_x = 0;
2825 plane_state->crtc_y = 0;
2826 plane_state->crtc_w = fb->width;
2827 plane_state->crtc_h = fb->height;
2828
2829 intel_state->base.src = drm_plane_state_src(plane_state);
2830 intel_state->base.dst = drm_plane_state_dest(plane_state);
2831
2832 obj = intel_fb_obj(fb);
2833 if (i915_gem_object_is_tiled(obj))
2834 dev_priv->preserve_bios_swizzle = true;
2835
2836 drm_framebuffer_reference(fb);
2837 primary->fb = primary->state->fb = fb;
2838 primary->crtc = primary->state->crtc = &intel_crtc->base;
2839 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2840 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2841 &obj->frontbuffer_bits);
2842 }
2843
2844 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2845 unsigned int rotation)
2846 {
2847 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2848
2849 switch (fb->modifier) {
2850 case DRM_FORMAT_MOD_NONE:
2851 case I915_FORMAT_MOD_X_TILED:
2852 switch (cpp) {
2853 case 8:
2854 return 4096;
2855 case 4:
2856 case 2:
2857 case 1:
2858 return 8192;
2859 default:
2860 MISSING_CASE(cpp);
2861 break;
2862 }
2863 break;
2864 case I915_FORMAT_MOD_Y_TILED:
2865 case I915_FORMAT_MOD_Yf_TILED:
2866 switch (cpp) {
2867 case 8:
2868 return 2048;
2869 case 4:
2870 return 4096;
2871 case 2:
2872 case 1:
2873 return 8192;
2874 default:
2875 MISSING_CASE(cpp);
2876 break;
2877 }
2878 break;
2879 default:
2880 MISSING_CASE(fb->modifier);
2881 }
2882
2883 return 2048;
2884 }
2885
2886 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2887 {
2888 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2889 const struct drm_framebuffer *fb = plane_state->base.fb;
2890 unsigned int rotation = plane_state->base.rotation;
2891 int x = plane_state->base.src.x1 >> 16;
2892 int y = plane_state->base.src.y1 >> 16;
2893 int w = drm_rect_width(&plane_state->base.src) >> 16;
2894 int h = drm_rect_height(&plane_state->base.src) >> 16;
2895 int max_width = skl_max_plane_width(fb, 0, rotation);
2896 int max_height = 4096;
2897 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2898
2899 if (w > max_width || h > max_height) {
2900 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2901 w, h, max_width, max_height);
2902 return -EINVAL;
2903 }
2904
2905 intel_add_fb_offsets(&x, &y, plane_state, 0);
2906 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2907
2908 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2909
2910 /*
2911 * AUX surface offset is specified as the distance from the
2912 * main surface offset, and it must be non-negative. Make
2913 * sure that is what we will get.
2914 */
2915 if (offset > aux_offset)
2916 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2917 offset, aux_offset & ~(alignment - 1));
2918
2919 /*
2920 * When using an X-tiled surface, the plane blows up
2921 * if the x offset + width exceed the stride.
2922 *
2923 * TODO: linear and Y-tiled seem fine, Yf untested,
2924 */
2925 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2926 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2927
2928 while ((x + w) * cpp > fb->pitches[0]) {
2929 if (offset == 0) {
2930 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2931 return -EINVAL;
2932 }
2933
2934 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2935 offset, offset - alignment);
2936 }
2937 }
2938
2939 plane_state->main.offset = offset;
2940 plane_state->main.x = x;
2941 plane_state->main.y = y;
2942
2943 return 0;
2944 }
2945
2946 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2947 {
2948 const struct drm_framebuffer *fb = plane_state->base.fb;
2949 unsigned int rotation = plane_state->base.rotation;
2950 int max_width = skl_max_plane_width(fb, 1, rotation);
2951 int max_height = 4096;
2952 int x = plane_state->base.src.x1 >> 17;
2953 int y = plane_state->base.src.y1 >> 17;
2954 int w = drm_rect_width(&plane_state->base.src) >> 17;
2955 int h = drm_rect_height(&plane_state->base.src) >> 17;
2956 u32 offset;
2957
2958 intel_add_fb_offsets(&x, &y, plane_state, 1);
2959 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2960
2961 /* FIXME not quite sure how/if these apply to the chroma plane */
2962 if (w > max_width || h > max_height) {
2963 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2964 w, h, max_width, max_height);
2965 return -EINVAL;
2966 }
2967
2968 plane_state->aux.offset = offset;
2969 plane_state->aux.x = x;
2970 plane_state->aux.y = y;
2971
2972 return 0;
2973 }
2974
2975 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2976 {
2977 const struct drm_framebuffer *fb = plane_state->base.fb;
2978 unsigned int rotation = plane_state->base.rotation;
2979 int ret;
2980
2981 if (!plane_state->base.visible)
2982 return 0;
2983
2984 /* Rotate src coordinates to match rotated GTT view */
2985 if (drm_rotation_90_or_270(rotation))
2986 drm_rect_rotate(&plane_state->base.src,
2987 fb->width << 16, fb->height << 16,
2988 DRM_ROTATE_270);
2989
2990 /*
2991 * Handle the AUX surface first since
2992 * the main surface setup depends on it.
2993 */
2994 if (fb->pixel_format == DRM_FORMAT_NV12) {
2995 ret = skl_check_nv12_aux_surface(plane_state);
2996 if (ret)
2997 return ret;
2998 } else {
2999 plane_state->aux.offset = ~0xfff;
3000 plane_state->aux.x = 0;
3001 plane_state->aux.y = 0;
3002 }
3003
3004 ret = skl_check_main_surface(plane_state);
3005 if (ret)
3006 return ret;
3007
3008 return 0;
3009 }
3010
3011 static void i9xx_update_primary_plane(struct drm_plane *primary,
3012 const struct intel_crtc_state *crtc_state,
3013 const struct intel_plane_state *plane_state)
3014 {
3015 struct drm_i915_private *dev_priv = to_i915(primary->dev);
3016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3017 struct drm_framebuffer *fb = plane_state->base.fb;
3018 int plane = intel_crtc->plane;
3019 u32 linear_offset;
3020 u32 dspcntr;
3021 i915_reg_t reg = DSPCNTR(plane);
3022 unsigned int rotation = plane_state->base.rotation;
3023 int x = plane_state->base.src.x1 >> 16;
3024 int y = plane_state->base.src.y1 >> 16;
3025
3026 dspcntr = DISPPLANE_GAMMA_ENABLE;
3027
3028 dspcntr |= DISPLAY_PLANE_ENABLE;
3029
3030 if (INTEL_GEN(dev_priv) < 4) {
3031 if (intel_crtc->pipe == PIPE_B)
3032 dspcntr |= DISPPLANE_SEL_PIPE_B;
3033
3034 /* pipesrc and dspsize control the size that is scaled from,
3035 * which should always be the user's requested size.
3036 */
3037 I915_WRITE(DSPSIZE(plane),
3038 ((crtc_state->pipe_src_h - 1) << 16) |
3039 (crtc_state->pipe_src_w - 1));
3040 I915_WRITE(DSPPOS(plane), 0);
3041 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3042 I915_WRITE(PRIMSIZE(plane),
3043 ((crtc_state->pipe_src_h - 1) << 16) |
3044 (crtc_state->pipe_src_w - 1));
3045 I915_WRITE(PRIMPOS(plane), 0);
3046 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3047 }
3048
3049 switch (fb->pixel_format) {
3050 case DRM_FORMAT_C8:
3051 dspcntr |= DISPPLANE_8BPP;
3052 break;
3053 case DRM_FORMAT_XRGB1555:
3054 dspcntr |= DISPPLANE_BGRX555;
3055 break;
3056 case DRM_FORMAT_RGB565:
3057 dspcntr |= DISPPLANE_BGRX565;
3058 break;
3059 case DRM_FORMAT_XRGB8888:
3060 dspcntr |= DISPPLANE_BGRX888;
3061 break;
3062 case DRM_FORMAT_XBGR8888:
3063 dspcntr |= DISPPLANE_RGBX888;
3064 break;
3065 case DRM_FORMAT_XRGB2101010:
3066 dspcntr |= DISPPLANE_BGRX101010;
3067 break;
3068 case DRM_FORMAT_XBGR2101010:
3069 dspcntr |= DISPPLANE_RGBX101010;
3070 break;
3071 default:
3072 BUG();
3073 }
3074
3075 if (INTEL_GEN(dev_priv) >= 4 &&
3076 fb->modifier == I915_FORMAT_MOD_X_TILED)
3077 dspcntr |= DISPPLANE_TILED;
3078
3079 if (rotation & DRM_ROTATE_180)
3080 dspcntr |= DISPPLANE_ROTATE_180;
3081
3082 if (rotation & DRM_REFLECT_X)
3083 dspcntr |= DISPPLANE_MIRROR;
3084
3085 if (IS_G4X(dev_priv))
3086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3087
3088 intel_add_fb_offsets(&x, &y, plane_state, 0);
3089
3090 if (INTEL_GEN(dev_priv) >= 4)
3091 intel_crtc->dspaddr_offset =
3092 intel_compute_tile_offset(&x, &y, plane_state, 0);
3093
3094 if (rotation & DRM_ROTATE_180) {
3095 x += crtc_state->pipe_src_w - 1;
3096 y += crtc_state->pipe_src_h - 1;
3097 } else if (rotation & DRM_REFLECT_X) {
3098 x += crtc_state->pipe_src_w - 1;
3099 }
3100
3101 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3102
3103 if (INTEL_GEN(dev_priv) < 4)
3104 intel_crtc->dspaddr_offset = linear_offset;
3105
3106 intel_crtc->adjusted_x = x;
3107 intel_crtc->adjusted_y = y;
3108
3109 I915_WRITE(reg, dspcntr);
3110
3111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3112 if (INTEL_GEN(dev_priv) >= 4) {
3113 I915_WRITE(DSPSURF(plane),
3114 intel_plane_ggtt_offset(plane_state) +
3115 intel_crtc->dspaddr_offset);
3116 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3117 I915_WRITE(DSPLINOFF(plane), linear_offset);
3118 } else {
3119 I915_WRITE(DSPADDR(plane),
3120 intel_plane_ggtt_offset(plane_state) +
3121 intel_crtc->dspaddr_offset);
3122 }
3123 POSTING_READ(reg);
3124 }
3125
3126 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3127 struct drm_crtc *crtc)
3128 {
3129 struct drm_device *dev = crtc->dev;
3130 struct drm_i915_private *dev_priv = to_i915(dev);
3131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3132 int plane = intel_crtc->plane;
3133
3134 I915_WRITE(DSPCNTR(plane), 0);
3135 if (INTEL_INFO(dev_priv)->gen >= 4)
3136 I915_WRITE(DSPSURF(plane), 0);
3137 else
3138 I915_WRITE(DSPADDR(plane), 0);
3139 POSTING_READ(DSPCNTR(plane));
3140 }
3141
3142 static void ironlake_update_primary_plane(struct drm_plane *primary,
3143 const struct intel_crtc_state *crtc_state,
3144 const struct intel_plane_state *plane_state)
3145 {
3146 struct drm_device *dev = primary->dev;
3147 struct drm_i915_private *dev_priv = to_i915(dev);
3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3149 struct drm_framebuffer *fb = plane_state->base.fb;
3150 int plane = intel_crtc->plane;
3151 u32 linear_offset;
3152 u32 dspcntr;
3153 i915_reg_t reg = DSPCNTR(plane);
3154 unsigned int rotation = plane_state->base.rotation;
3155 int x = plane_state->base.src.x1 >> 16;
3156 int y = plane_state->base.src.y1 >> 16;
3157
3158 dspcntr = DISPPLANE_GAMMA_ENABLE;
3159 dspcntr |= DISPLAY_PLANE_ENABLE;
3160
3161 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3162 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3163
3164 switch (fb->pixel_format) {
3165 case DRM_FORMAT_C8:
3166 dspcntr |= DISPPLANE_8BPP;
3167 break;
3168 case DRM_FORMAT_RGB565:
3169 dspcntr |= DISPPLANE_BGRX565;
3170 break;
3171 case DRM_FORMAT_XRGB8888:
3172 dspcntr |= DISPPLANE_BGRX888;
3173 break;
3174 case DRM_FORMAT_XBGR8888:
3175 dspcntr |= DISPPLANE_RGBX888;
3176 break;
3177 case DRM_FORMAT_XRGB2101010:
3178 dspcntr |= DISPPLANE_BGRX101010;
3179 break;
3180 case DRM_FORMAT_XBGR2101010:
3181 dspcntr |= DISPPLANE_RGBX101010;
3182 break;
3183 default:
3184 BUG();
3185 }
3186
3187 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3188 dspcntr |= DISPPLANE_TILED;
3189
3190 if (rotation & DRM_ROTATE_180)
3191 dspcntr |= DISPPLANE_ROTATE_180;
3192
3193 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3194 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3195
3196 intel_add_fb_offsets(&x, &y, plane_state, 0);
3197
3198 intel_crtc->dspaddr_offset =
3199 intel_compute_tile_offset(&x, &y, plane_state, 0);
3200
3201 /* HSW+ does this automagically in hardware */
3202 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3203 rotation & DRM_ROTATE_180) {
3204 x += crtc_state->pipe_src_w - 1;
3205 y += crtc_state->pipe_src_h - 1;
3206 }
3207
3208 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3209
3210 intel_crtc->adjusted_x = x;
3211 intel_crtc->adjusted_y = y;
3212
3213 I915_WRITE(reg, dspcntr);
3214
3215 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3216 I915_WRITE(DSPSURF(plane),
3217 intel_plane_ggtt_offset(plane_state) +
3218 intel_crtc->dspaddr_offset);
3219 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3220 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3221 } else {
3222 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3223 I915_WRITE(DSPLINOFF(plane), linear_offset);
3224 }
3225 POSTING_READ(reg);
3226 }
3227
3228 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3229 uint64_t fb_modifier, uint32_t pixel_format)
3230 {
3231 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3232 return 64;
3233 } else {
3234 int cpp = drm_format_plane_cpp(pixel_format, 0);
3235
3236 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3237 }
3238 }
3239
3240 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3241 {
3242 struct drm_device *dev = intel_crtc->base.dev;
3243 struct drm_i915_private *dev_priv = to_i915(dev);
3244
3245 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3246 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3247 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3248 }
3249
3250 /*
3251 * This function detaches (aka. unbinds) unused scalers in hardware
3252 */
3253 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3254 {
3255 struct intel_crtc_scaler_state *scaler_state;
3256 int i;
3257
3258 scaler_state = &intel_crtc->config->scaler_state;
3259
3260 /* loop through and disable scalers that aren't in use */
3261 for (i = 0; i < intel_crtc->num_scalers; i++) {
3262 if (!scaler_state->scalers[i].in_use)
3263 skl_detach_scaler(intel_crtc, i);
3264 }
3265 }
3266
3267 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3268 unsigned int rotation)
3269 {
3270 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3271 u32 stride = intel_fb_pitch(fb, plane, rotation);
3272
3273 /*
3274 * The stride is either expressed as a multiple of 64 bytes chunks for
3275 * linear buffers or in number of tiles for tiled buffers.
3276 */
3277 if (drm_rotation_90_or_270(rotation)) {
3278 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3279
3280 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3281 } else {
3282 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3283 fb->pixel_format);
3284 }
3285
3286 return stride;
3287 }
3288
3289 u32 skl_plane_ctl_format(uint32_t pixel_format)
3290 {
3291 switch (pixel_format) {
3292 case DRM_FORMAT_C8:
3293 return PLANE_CTL_FORMAT_INDEXED;
3294 case DRM_FORMAT_RGB565:
3295 return PLANE_CTL_FORMAT_RGB_565;
3296 case DRM_FORMAT_XBGR8888:
3297 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3298 case DRM_FORMAT_XRGB8888:
3299 return PLANE_CTL_FORMAT_XRGB_8888;
3300 /*
3301 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3302 * to be already pre-multiplied. We need to add a knob (or a different
3303 * DRM_FORMAT) for user-space to configure that.
3304 */
3305 case DRM_FORMAT_ABGR8888:
3306 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3307 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3308 case DRM_FORMAT_ARGB8888:
3309 return PLANE_CTL_FORMAT_XRGB_8888 |
3310 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3311 case DRM_FORMAT_XRGB2101010:
3312 return PLANE_CTL_FORMAT_XRGB_2101010;
3313 case DRM_FORMAT_XBGR2101010:
3314 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3315 case DRM_FORMAT_YUYV:
3316 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3317 case DRM_FORMAT_YVYU:
3318 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3319 case DRM_FORMAT_UYVY:
3320 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3321 case DRM_FORMAT_VYUY:
3322 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3323 default:
3324 MISSING_CASE(pixel_format);
3325 }
3326
3327 return 0;
3328 }
3329
3330 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3331 {
3332 switch (fb_modifier) {
3333 case DRM_FORMAT_MOD_NONE:
3334 break;
3335 case I915_FORMAT_MOD_X_TILED:
3336 return PLANE_CTL_TILED_X;
3337 case I915_FORMAT_MOD_Y_TILED:
3338 return PLANE_CTL_TILED_Y;
3339 case I915_FORMAT_MOD_Yf_TILED:
3340 return PLANE_CTL_TILED_YF;
3341 default:
3342 MISSING_CASE(fb_modifier);
3343 }
3344
3345 return 0;
3346 }
3347
3348 u32 skl_plane_ctl_rotation(unsigned int rotation)
3349 {
3350 switch (rotation) {
3351 case DRM_ROTATE_0:
3352 break;
3353 /*
3354 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3355 * while i915 HW rotation is clockwise, thats why this swapping.
3356 */
3357 case DRM_ROTATE_90:
3358 return PLANE_CTL_ROTATE_270;
3359 case DRM_ROTATE_180:
3360 return PLANE_CTL_ROTATE_180;
3361 case DRM_ROTATE_270:
3362 return PLANE_CTL_ROTATE_90;
3363 default:
3364 MISSING_CASE(rotation);
3365 }
3366
3367 return 0;
3368 }
3369
3370 static void skylake_update_primary_plane(struct drm_plane *plane,
3371 const struct intel_crtc_state *crtc_state,
3372 const struct intel_plane_state *plane_state)
3373 {
3374 struct drm_device *dev = plane->dev;
3375 struct drm_i915_private *dev_priv = to_i915(dev);
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3377 struct drm_framebuffer *fb = plane_state->base.fb;
3378 int pipe = intel_crtc->pipe;
3379 u32 plane_ctl;
3380 unsigned int rotation = plane_state->base.rotation;
3381 u32 stride = skl_plane_stride(fb, 0, rotation);
3382 u32 surf_addr = plane_state->main.offset;
3383 int scaler_id = plane_state->scaler_id;
3384 int src_x = plane_state->main.x;
3385 int src_y = plane_state->main.y;
3386 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3387 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3388 int dst_x = plane_state->base.dst.x1;
3389 int dst_y = plane_state->base.dst.y1;
3390 int dst_w = drm_rect_width(&plane_state->base.dst);
3391 int dst_h = drm_rect_height(&plane_state->base.dst);
3392
3393 plane_ctl = PLANE_CTL_ENABLE |
3394 PLANE_CTL_PIPE_GAMMA_ENABLE |
3395 PLANE_CTL_PIPE_CSC_ENABLE;
3396
3397 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3398 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3399 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3400 plane_ctl |= skl_plane_ctl_rotation(rotation);
3401
3402 /* Sizes are 0 based */
3403 src_w--;
3404 src_h--;
3405 dst_w--;
3406 dst_h--;
3407
3408 intel_crtc->dspaddr_offset = surf_addr;
3409
3410 intel_crtc->adjusted_x = src_x;
3411 intel_crtc->adjusted_y = src_y;
3412
3413 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3414 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3415 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3416 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3417
3418 if (scaler_id >= 0) {
3419 uint32_t ps_ctrl = 0;
3420
3421 WARN_ON(!dst_w || !dst_h);
3422 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3423 crtc_state->scaler_state.scalers[scaler_id].mode;
3424 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3425 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3426 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3427 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3428 I915_WRITE(PLANE_POS(pipe, 0), 0);
3429 } else {
3430 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3431 }
3432
3433 I915_WRITE(PLANE_SURF(pipe, 0),
3434 intel_plane_ggtt_offset(plane_state) + surf_addr);
3435
3436 POSTING_READ(PLANE_SURF(pipe, 0));
3437 }
3438
3439 static void skylake_disable_primary_plane(struct drm_plane *primary,
3440 struct drm_crtc *crtc)
3441 {
3442 struct drm_device *dev = crtc->dev;
3443 struct drm_i915_private *dev_priv = to_i915(dev);
3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445 int pipe = intel_crtc->pipe;
3446
3447 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3448 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3449 POSTING_READ(PLANE_SURF(pipe, 0));
3450 }
3451
3452 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3453 static int
3454 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3455 int x, int y, enum mode_set_atomic state)
3456 {
3457 /* Support for kgdboc is disabled, this needs a major rework. */
3458 DRM_ERROR("legacy panic handler not supported any more.\n");
3459
3460 return -ENODEV;
3461 }
3462
3463 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3464 {
3465 struct intel_crtc *crtc;
3466
3467 for_each_intel_crtc(&dev_priv->drm, crtc)
3468 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3469 }
3470
3471 static void intel_update_primary_planes(struct drm_device *dev)
3472 {
3473 struct drm_crtc *crtc;
3474
3475 for_each_crtc(dev, crtc) {
3476 struct intel_plane *plane = to_intel_plane(crtc->primary);
3477 struct intel_plane_state *plane_state =
3478 to_intel_plane_state(plane->base.state);
3479
3480 if (plane_state->base.visible)
3481 plane->update_plane(&plane->base,
3482 to_intel_crtc_state(crtc->state),
3483 plane_state);
3484 }
3485 }
3486
3487 static int
3488 __intel_display_resume(struct drm_device *dev,
3489 struct drm_atomic_state *state)
3490 {
3491 struct drm_crtc_state *crtc_state;
3492 struct drm_crtc *crtc;
3493 int i, ret;
3494
3495 intel_modeset_setup_hw_state(dev);
3496 i915_redisable_vga(to_i915(dev));
3497
3498 if (!state)
3499 return 0;
3500
3501 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3502 /*
3503 * Force recalculation even if we restore
3504 * current state. With fast modeset this may not result
3505 * in a modeset when the state is compatible.
3506 */
3507 crtc_state->mode_changed = true;
3508 }
3509
3510 /* ignore any reset values/BIOS leftovers in the WM registers */
3511 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3512
3513 ret = drm_atomic_commit(state);
3514
3515 WARN_ON(ret == -EDEADLK);
3516 return ret;
3517 }
3518
3519 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3520 {
3521 return intel_has_gpu_reset(dev_priv) &&
3522 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3523 }
3524
3525 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3526 {
3527 struct drm_device *dev = &dev_priv->drm;
3528 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3529 struct drm_atomic_state *state;
3530 int ret;
3531
3532 /*
3533 * Need mode_config.mutex so that we don't
3534 * trample ongoing ->detect() and whatnot.
3535 */
3536 mutex_lock(&dev->mode_config.mutex);
3537 drm_modeset_acquire_init(ctx, 0);
3538 while (1) {
3539 ret = drm_modeset_lock_all_ctx(dev, ctx);
3540 if (ret != -EDEADLK)
3541 break;
3542
3543 drm_modeset_backoff(ctx);
3544 }
3545
3546 /* reset doesn't touch the display, but flips might get nuked anyway, */
3547 if (!i915.force_reset_modeset_test &&
3548 !gpu_reset_clobbers_display(dev_priv))
3549 return;
3550
3551 /*
3552 * Disabling the crtcs gracefully seems nicer. Also the
3553 * g33 docs say we should at least disable all the planes.
3554 */
3555 state = drm_atomic_helper_duplicate_state(dev, ctx);
3556 if (IS_ERR(state)) {
3557 ret = PTR_ERR(state);
3558 state = NULL;
3559 DRM_ERROR("Duplicating state failed with %i\n", ret);
3560 goto err;
3561 }
3562
3563 ret = drm_atomic_helper_disable_all(dev, ctx);
3564 if (ret) {
3565 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3566 goto err;
3567 }
3568
3569 dev_priv->modeset_restore_state = state;
3570 state->acquire_ctx = ctx;
3571 return;
3572
3573 err:
3574 drm_atomic_state_put(state);
3575 }
3576
3577 void intel_finish_reset(struct drm_i915_private *dev_priv)
3578 {
3579 struct drm_device *dev = &dev_priv->drm;
3580 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3581 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3582 int ret;
3583
3584 /*
3585 * Flips in the rings will be nuked by the reset,
3586 * so complete all pending flips so that user space
3587 * will get its events and not get stuck.
3588 */
3589 intel_complete_page_flips(dev_priv);
3590
3591 dev_priv->modeset_restore_state = NULL;
3592
3593 /* reset doesn't touch the display */
3594 if (!gpu_reset_clobbers_display(dev_priv)) {
3595 if (!state) {
3596 /*
3597 * Flips in the rings have been nuked by the reset,
3598 * so update the base address of all primary
3599 * planes to the the last fb to make sure we're
3600 * showing the correct fb after a reset.
3601 *
3602 * FIXME: Atomic will make this obsolete since we won't schedule
3603 * CS-based flips (which might get lost in gpu resets) any more.
3604 */
3605 intel_update_primary_planes(dev);
3606 } else {
3607 ret = __intel_display_resume(dev, state);
3608 if (ret)
3609 DRM_ERROR("Restoring old state failed with %i\n", ret);
3610 }
3611 } else {
3612 /*
3613 * The display has been reset as well,
3614 * so need a full re-initialization.
3615 */
3616 intel_runtime_pm_disable_interrupts(dev_priv);
3617 intel_runtime_pm_enable_interrupts(dev_priv);
3618
3619 intel_pps_unlock_regs_wa(dev_priv);
3620 intel_modeset_init_hw(dev);
3621
3622 spin_lock_irq(&dev_priv->irq_lock);
3623 if (dev_priv->display.hpd_irq_setup)
3624 dev_priv->display.hpd_irq_setup(dev_priv);
3625 spin_unlock_irq(&dev_priv->irq_lock);
3626
3627 ret = __intel_display_resume(dev, state);
3628 if (ret)
3629 DRM_ERROR("Restoring old state failed with %i\n", ret);
3630
3631 intel_hpd_init(dev_priv);
3632 }
3633
3634 if (state)
3635 drm_atomic_state_put(state);
3636 drm_modeset_drop_locks(ctx);
3637 drm_modeset_acquire_fini(ctx);
3638 mutex_unlock(&dev->mode_config.mutex);
3639 }
3640
3641 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3642 {
3643 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3644
3645 if (i915_reset_in_progress(error))
3646 return true;
3647
3648 if (crtc->reset_count != i915_reset_count(error))
3649 return true;
3650
3651 return false;
3652 }
3653
3654 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3655 {
3656 struct drm_device *dev = crtc->dev;
3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658 bool pending;
3659
3660 if (abort_flip_on_reset(intel_crtc))
3661 return false;
3662
3663 spin_lock_irq(&dev->event_lock);
3664 pending = to_intel_crtc(crtc)->flip_work != NULL;
3665 spin_unlock_irq(&dev->event_lock);
3666
3667 return pending;
3668 }
3669
3670 static void intel_update_pipe_config(struct intel_crtc *crtc,
3671 struct intel_crtc_state *old_crtc_state)
3672 {
3673 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3674 struct intel_crtc_state *pipe_config =
3675 to_intel_crtc_state(crtc->base.state);
3676
3677 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3678 crtc->base.mode = crtc->base.state->mode;
3679
3680 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3681 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3682 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3683
3684 /*
3685 * Update pipe size and adjust fitter if needed: the reason for this is
3686 * that in compute_mode_changes we check the native mode (not the pfit
3687 * mode) to see if we can flip rather than do a full mode set. In the
3688 * fastboot case, we'll flip, but if we don't update the pipesrc and
3689 * pfit state, we'll end up with a big fb scanned out into the wrong
3690 * sized surface.
3691 */
3692
3693 I915_WRITE(PIPESRC(crtc->pipe),
3694 ((pipe_config->pipe_src_w - 1) << 16) |
3695 (pipe_config->pipe_src_h - 1));
3696
3697 /* on skylake this is done by detaching scalers */
3698 if (INTEL_GEN(dev_priv) >= 9) {
3699 skl_detach_scalers(crtc);
3700
3701 if (pipe_config->pch_pfit.enabled)
3702 skylake_pfit_enable(crtc);
3703 } else if (HAS_PCH_SPLIT(dev_priv)) {
3704 if (pipe_config->pch_pfit.enabled)
3705 ironlake_pfit_enable(crtc);
3706 else if (old_crtc_state->pch_pfit.enabled)
3707 ironlake_pfit_disable(crtc, true);
3708 }
3709 }
3710
3711 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3712 {
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = to_i915(dev);
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716 int pipe = intel_crtc->pipe;
3717 i915_reg_t reg;
3718 u32 temp;
3719
3720 /* enable normal train */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 if (IS_IVYBRIDGE(dev_priv)) {
3724 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3725 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3726 } else {
3727 temp &= ~FDI_LINK_TRAIN_NONE;
3728 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3729 }
3730 I915_WRITE(reg, temp);
3731
3732 reg = FDI_RX_CTL(pipe);
3733 temp = I915_READ(reg);
3734 if (HAS_PCH_CPT(dev_priv)) {
3735 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3736 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3737 } else {
3738 temp &= ~FDI_LINK_TRAIN_NONE;
3739 temp |= FDI_LINK_TRAIN_NONE;
3740 }
3741 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3742
3743 /* wait one idle pattern time */
3744 POSTING_READ(reg);
3745 udelay(1000);
3746
3747 /* IVB wants error correction enabled */
3748 if (IS_IVYBRIDGE(dev_priv))
3749 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3750 FDI_FE_ERRC_ENABLE);
3751 }
3752
3753 /* The FDI link training functions for ILK/Ibexpeak. */
3754 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3755 {
3756 struct drm_device *dev = crtc->dev;
3757 struct drm_i915_private *dev_priv = to_i915(dev);
3758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759 int pipe = intel_crtc->pipe;
3760 i915_reg_t reg;
3761 u32 temp, tries;
3762
3763 /* FDI needs bits from pipe first */
3764 assert_pipe_enabled(dev_priv, pipe);
3765
3766 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3767 for train result */
3768 reg = FDI_RX_IMR(pipe);
3769 temp = I915_READ(reg);
3770 temp &= ~FDI_RX_SYMBOL_LOCK;
3771 temp &= ~FDI_RX_BIT_LOCK;
3772 I915_WRITE(reg, temp);
3773 I915_READ(reg);
3774 udelay(150);
3775
3776 /* enable CPU FDI TX and PCH FDI RX */
3777 reg = FDI_TX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3780 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3781 temp &= ~FDI_LINK_TRAIN_NONE;
3782 temp |= FDI_LINK_TRAIN_PATTERN_1;
3783 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3784
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 temp &= ~FDI_LINK_TRAIN_NONE;
3788 temp |= FDI_LINK_TRAIN_PATTERN_1;
3789 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3790
3791 POSTING_READ(reg);
3792 udelay(150);
3793
3794 /* Ironlake workaround, enable clock pointer after FDI enable*/
3795 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3796 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3797 FDI_RX_PHASE_SYNC_POINTER_EN);
3798
3799 reg = FDI_RX_IIR(pipe);
3800 for (tries = 0; tries < 5; tries++) {
3801 temp = I915_READ(reg);
3802 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3803
3804 if ((temp & FDI_RX_BIT_LOCK)) {
3805 DRM_DEBUG_KMS("FDI train 1 done.\n");
3806 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3807 break;
3808 }
3809 }
3810 if (tries == 5)
3811 DRM_ERROR("FDI train 1 fail!\n");
3812
3813 /* Train 2 */
3814 reg = FDI_TX_CTL(pipe);
3815 temp = I915_READ(reg);
3816 temp &= ~FDI_LINK_TRAIN_NONE;
3817 temp |= FDI_LINK_TRAIN_PATTERN_2;
3818 I915_WRITE(reg, temp);
3819
3820 reg = FDI_RX_CTL(pipe);
3821 temp = I915_READ(reg);
3822 temp &= ~FDI_LINK_TRAIN_NONE;
3823 temp |= FDI_LINK_TRAIN_PATTERN_2;
3824 I915_WRITE(reg, temp);
3825
3826 POSTING_READ(reg);
3827 udelay(150);
3828
3829 reg = FDI_RX_IIR(pipe);
3830 for (tries = 0; tries < 5; tries++) {
3831 temp = I915_READ(reg);
3832 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3833
3834 if (temp & FDI_RX_SYMBOL_LOCK) {
3835 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3836 DRM_DEBUG_KMS("FDI train 2 done.\n");
3837 break;
3838 }
3839 }
3840 if (tries == 5)
3841 DRM_ERROR("FDI train 2 fail!\n");
3842
3843 DRM_DEBUG_KMS("FDI train done\n");
3844
3845 }
3846
3847 static const int snb_b_fdi_train_param[] = {
3848 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3849 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3850 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3851 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3852 };
3853
3854 /* The FDI link training functions for SNB/Cougarpoint. */
3855 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3856 {
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = to_i915(dev);
3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3860 int pipe = intel_crtc->pipe;
3861 i915_reg_t reg;
3862 u32 temp, i, retry;
3863
3864 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3865 for train result */
3866 reg = FDI_RX_IMR(pipe);
3867 temp = I915_READ(reg);
3868 temp &= ~FDI_RX_SYMBOL_LOCK;
3869 temp &= ~FDI_RX_BIT_LOCK;
3870 I915_WRITE(reg, temp);
3871
3872 POSTING_READ(reg);
3873 udelay(150);
3874
3875 /* enable CPU FDI TX and PCH FDI RX */
3876 reg = FDI_TX_CTL(pipe);
3877 temp = I915_READ(reg);
3878 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3879 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3880 temp &= ~FDI_LINK_TRAIN_NONE;
3881 temp |= FDI_LINK_TRAIN_PATTERN_1;
3882 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3883 /* SNB-B */
3884 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3885 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3886
3887 I915_WRITE(FDI_RX_MISC(pipe),
3888 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3889
3890 reg = FDI_RX_CTL(pipe);
3891 temp = I915_READ(reg);
3892 if (HAS_PCH_CPT(dev_priv)) {
3893 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3894 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3895 } else {
3896 temp &= ~FDI_LINK_TRAIN_NONE;
3897 temp |= FDI_LINK_TRAIN_PATTERN_1;
3898 }
3899 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3900
3901 POSTING_READ(reg);
3902 udelay(150);
3903
3904 for (i = 0; i < 4; i++) {
3905 reg = FDI_TX_CTL(pipe);
3906 temp = I915_READ(reg);
3907 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3908 temp |= snb_b_fdi_train_param[i];
3909 I915_WRITE(reg, temp);
3910
3911 POSTING_READ(reg);
3912 udelay(500);
3913
3914 for (retry = 0; retry < 5; retry++) {
3915 reg = FDI_RX_IIR(pipe);
3916 temp = I915_READ(reg);
3917 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3918 if (temp & FDI_RX_BIT_LOCK) {
3919 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3920 DRM_DEBUG_KMS("FDI train 1 done.\n");
3921 break;
3922 }
3923 udelay(50);
3924 }
3925 if (retry < 5)
3926 break;
3927 }
3928 if (i == 4)
3929 DRM_ERROR("FDI train 1 fail!\n");
3930
3931 /* Train 2 */
3932 reg = FDI_TX_CTL(pipe);
3933 temp = I915_READ(reg);
3934 temp &= ~FDI_LINK_TRAIN_NONE;
3935 temp |= FDI_LINK_TRAIN_PATTERN_2;
3936 if (IS_GEN6(dev_priv)) {
3937 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3938 /* SNB-B */
3939 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3940 }
3941 I915_WRITE(reg, temp);
3942
3943 reg = FDI_RX_CTL(pipe);
3944 temp = I915_READ(reg);
3945 if (HAS_PCH_CPT(dev_priv)) {
3946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3947 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3948 } else {
3949 temp &= ~FDI_LINK_TRAIN_NONE;
3950 temp |= FDI_LINK_TRAIN_PATTERN_2;
3951 }
3952 I915_WRITE(reg, temp);
3953
3954 POSTING_READ(reg);
3955 udelay(150);
3956
3957 for (i = 0; i < 4; i++) {
3958 reg = FDI_TX_CTL(pipe);
3959 temp = I915_READ(reg);
3960 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3961 temp |= snb_b_fdi_train_param[i];
3962 I915_WRITE(reg, temp);
3963
3964 POSTING_READ(reg);
3965 udelay(500);
3966
3967 for (retry = 0; retry < 5; retry++) {
3968 reg = FDI_RX_IIR(pipe);
3969 temp = I915_READ(reg);
3970 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3971 if (temp & FDI_RX_SYMBOL_LOCK) {
3972 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3973 DRM_DEBUG_KMS("FDI train 2 done.\n");
3974 break;
3975 }
3976 udelay(50);
3977 }
3978 if (retry < 5)
3979 break;
3980 }
3981 if (i == 4)
3982 DRM_ERROR("FDI train 2 fail!\n");
3983
3984 DRM_DEBUG_KMS("FDI train done.\n");
3985 }
3986
3987 /* Manual link training for Ivy Bridge A0 parts */
3988 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3989 {
3990 struct drm_device *dev = crtc->dev;
3991 struct drm_i915_private *dev_priv = to_i915(dev);
3992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3993 int pipe = intel_crtc->pipe;
3994 i915_reg_t reg;
3995 u32 temp, i, j;
3996
3997 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3998 for train result */
3999 reg = FDI_RX_IMR(pipe);
4000 temp = I915_READ(reg);
4001 temp &= ~FDI_RX_SYMBOL_LOCK;
4002 temp &= ~FDI_RX_BIT_LOCK;
4003 I915_WRITE(reg, temp);
4004
4005 POSTING_READ(reg);
4006 udelay(150);
4007
4008 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4009 I915_READ(FDI_RX_IIR(pipe)));
4010
4011 /* Try each vswing and preemphasis setting twice before moving on */
4012 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4013 /* disable first in case we need to retry */
4014 reg = FDI_TX_CTL(pipe);
4015 temp = I915_READ(reg);
4016 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4017 temp &= ~FDI_TX_ENABLE;
4018 I915_WRITE(reg, temp);
4019
4020 reg = FDI_RX_CTL(pipe);
4021 temp = I915_READ(reg);
4022 temp &= ~FDI_LINK_TRAIN_AUTO;
4023 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4024 temp &= ~FDI_RX_ENABLE;
4025 I915_WRITE(reg, temp);
4026
4027 /* enable CPU FDI TX and PCH FDI RX */
4028 reg = FDI_TX_CTL(pipe);
4029 temp = I915_READ(reg);
4030 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4031 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4032 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4033 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4034 temp |= snb_b_fdi_train_param[j/2];
4035 temp |= FDI_COMPOSITE_SYNC;
4036 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4037
4038 I915_WRITE(FDI_RX_MISC(pipe),
4039 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4040
4041 reg = FDI_RX_CTL(pipe);
4042 temp = I915_READ(reg);
4043 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4044 temp |= FDI_COMPOSITE_SYNC;
4045 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4046
4047 POSTING_READ(reg);
4048 udelay(1); /* should be 0.5us */
4049
4050 for (i = 0; i < 4; i++) {
4051 reg = FDI_RX_IIR(pipe);
4052 temp = I915_READ(reg);
4053 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4054
4055 if (temp & FDI_RX_BIT_LOCK ||
4056 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4057 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4058 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4059 i);
4060 break;
4061 }
4062 udelay(1); /* should be 0.5us */
4063 }
4064 if (i == 4) {
4065 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4066 continue;
4067 }
4068
4069 /* Train 2 */
4070 reg = FDI_TX_CTL(pipe);
4071 temp = I915_READ(reg);
4072 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4073 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4074 I915_WRITE(reg, temp);
4075
4076 reg = FDI_RX_CTL(pipe);
4077 temp = I915_READ(reg);
4078 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4079 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4080 I915_WRITE(reg, temp);
4081
4082 POSTING_READ(reg);
4083 udelay(2); /* should be 1.5us */
4084
4085 for (i = 0; i < 4; i++) {
4086 reg = FDI_RX_IIR(pipe);
4087 temp = I915_READ(reg);
4088 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4089
4090 if (temp & FDI_RX_SYMBOL_LOCK ||
4091 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4092 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4093 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4094 i);
4095 goto train_done;
4096 }
4097 udelay(2); /* should be 1.5us */
4098 }
4099 if (i == 4)
4100 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4101 }
4102
4103 train_done:
4104 DRM_DEBUG_KMS("FDI train done.\n");
4105 }
4106
4107 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4108 {
4109 struct drm_device *dev = intel_crtc->base.dev;
4110 struct drm_i915_private *dev_priv = to_i915(dev);
4111 int pipe = intel_crtc->pipe;
4112 i915_reg_t reg;
4113 u32 temp;
4114
4115 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4116 reg = FDI_RX_CTL(pipe);
4117 temp = I915_READ(reg);
4118 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4119 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4120 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4121 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4122
4123 POSTING_READ(reg);
4124 udelay(200);
4125
4126 /* Switch from Rawclk to PCDclk */
4127 temp = I915_READ(reg);
4128 I915_WRITE(reg, temp | FDI_PCDCLK);
4129
4130 POSTING_READ(reg);
4131 udelay(200);
4132
4133 /* Enable CPU FDI TX PLL, always on for Ironlake */
4134 reg = FDI_TX_CTL(pipe);
4135 temp = I915_READ(reg);
4136 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4137 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4138
4139 POSTING_READ(reg);
4140 udelay(100);
4141 }
4142 }
4143
4144 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4145 {
4146 struct drm_device *dev = intel_crtc->base.dev;
4147 struct drm_i915_private *dev_priv = to_i915(dev);
4148 int pipe = intel_crtc->pipe;
4149 i915_reg_t reg;
4150 u32 temp;
4151
4152 /* Switch from PCDclk to Rawclk */
4153 reg = FDI_RX_CTL(pipe);
4154 temp = I915_READ(reg);
4155 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4156
4157 /* Disable CPU FDI TX PLL */
4158 reg = FDI_TX_CTL(pipe);
4159 temp = I915_READ(reg);
4160 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4161
4162 POSTING_READ(reg);
4163 udelay(100);
4164
4165 reg = FDI_RX_CTL(pipe);
4166 temp = I915_READ(reg);
4167 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4168
4169 /* Wait for the clocks to turn off. */
4170 POSTING_READ(reg);
4171 udelay(100);
4172 }
4173
4174 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4175 {
4176 struct drm_device *dev = crtc->dev;
4177 struct drm_i915_private *dev_priv = to_i915(dev);
4178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179 int pipe = intel_crtc->pipe;
4180 i915_reg_t reg;
4181 u32 temp;
4182
4183 /* disable CPU FDI tx and PCH FDI rx */
4184 reg = FDI_TX_CTL(pipe);
4185 temp = I915_READ(reg);
4186 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4187 POSTING_READ(reg);
4188
4189 reg = FDI_RX_CTL(pipe);
4190 temp = I915_READ(reg);
4191 temp &= ~(0x7 << 16);
4192 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4193 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4194
4195 POSTING_READ(reg);
4196 udelay(100);
4197
4198 /* Ironlake workaround, disable clock pointer after downing FDI */
4199 if (HAS_PCH_IBX(dev_priv))
4200 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4201
4202 /* still set train pattern 1 */
4203 reg = FDI_TX_CTL(pipe);
4204 temp = I915_READ(reg);
4205 temp &= ~FDI_LINK_TRAIN_NONE;
4206 temp |= FDI_LINK_TRAIN_PATTERN_1;
4207 I915_WRITE(reg, temp);
4208
4209 reg = FDI_RX_CTL(pipe);
4210 temp = I915_READ(reg);
4211 if (HAS_PCH_CPT(dev_priv)) {
4212 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4213 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4214 } else {
4215 temp &= ~FDI_LINK_TRAIN_NONE;
4216 temp |= FDI_LINK_TRAIN_PATTERN_1;
4217 }
4218 /* BPC in FDI rx is consistent with that in PIPECONF */
4219 temp &= ~(0x07 << 16);
4220 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4221 I915_WRITE(reg, temp);
4222
4223 POSTING_READ(reg);
4224 udelay(100);
4225 }
4226
4227 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4228 {
4229 struct drm_i915_private *dev_priv = to_i915(dev);
4230 struct intel_crtc *crtc;
4231
4232 /* Note that we don't need to be called with mode_config.lock here
4233 * as our list of CRTC objects is static for the lifetime of the
4234 * device and so cannot disappear as we iterate. Similarly, we can
4235 * happily treat the predicates as racy, atomic checks as userspace
4236 * cannot claim and pin a new fb without at least acquring the
4237 * struct_mutex and so serialising with us.
4238 */
4239 for_each_intel_crtc(dev, crtc) {
4240 if (atomic_read(&crtc->unpin_work_count) == 0)
4241 continue;
4242
4243 if (crtc->flip_work)
4244 intel_wait_for_vblank(dev_priv, crtc->pipe);
4245
4246 return true;
4247 }
4248
4249 return false;
4250 }
4251
4252 static void page_flip_completed(struct intel_crtc *intel_crtc)
4253 {
4254 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4255 struct intel_flip_work *work = intel_crtc->flip_work;
4256
4257 intel_crtc->flip_work = NULL;
4258
4259 if (work->event)
4260 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4261
4262 drm_crtc_vblank_put(&intel_crtc->base);
4263
4264 wake_up_all(&dev_priv->pending_flip_queue);
4265 trace_i915_flip_complete(intel_crtc->plane,
4266 work->pending_flip_obj);
4267
4268 queue_work(dev_priv->wq, &work->unpin_work);
4269 }
4270
4271 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4272 {
4273 struct drm_device *dev = crtc->dev;
4274 struct drm_i915_private *dev_priv = to_i915(dev);
4275 long ret;
4276
4277 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4278
4279 ret = wait_event_interruptible_timeout(
4280 dev_priv->pending_flip_queue,
4281 !intel_crtc_has_pending_flip(crtc),
4282 60*HZ);
4283
4284 if (ret < 0)
4285 return ret;
4286
4287 if (ret == 0) {
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289 struct intel_flip_work *work;
4290
4291 spin_lock_irq(&dev->event_lock);
4292 work = intel_crtc->flip_work;
4293 if (work && !is_mmio_work(work)) {
4294 WARN_ONCE(1, "Removing stuck page flip\n");
4295 page_flip_completed(intel_crtc);
4296 }
4297 spin_unlock_irq(&dev->event_lock);
4298 }
4299
4300 return 0;
4301 }
4302
4303 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4304 {
4305 u32 temp;
4306
4307 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4308
4309 mutex_lock(&dev_priv->sb_lock);
4310
4311 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4312 temp |= SBI_SSCCTL_DISABLE;
4313 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4314
4315 mutex_unlock(&dev_priv->sb_lock);
4316 }
4317
4318 /* Program iCLKIP clock to the desired frequency */
4319 static void lpt_program_iclkip(struct drm_crtc *crtc)
4320 {
4321 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4322 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4323 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4324 u32 temp;
4325
4326 lpt_disable_iclkip(dev_priv);
4327
4328 /* The iCLK virtual clock root frequency is in MHz,
4329 * but the adjusted_mode->crtc_clock in in KHz. To get the
4330 * divisors, it is necessary to divide one by another, so we
4331 * convert the virtual clock precision to KHz here for higher
4332 * precision.
4333 */
4334 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4335 u32 iclk_virtual_root_freq = 172800 * 1000;
4336 u32 iclk_pi_range = 64;
4337 u32 desired_divisor;
4338
4339 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4340 clock << auxdiv);
4341 divsel = (desired_divisor / iclk_pi_range) - 2;
4342 phaseinc = desired_divisor % iclk_pi_range;
4343
4344 /*
4345 * Near 20MHz is a corner case which is
4346 * out of range for the 7-bit divisor
4347 */
4348 if (divsel <= 0x7f)
4349 break;
4350 }
4351
4352 /* This should not happen with any sane values */
4353 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4354 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4355 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4356 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4357
4358 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4359 clock,
4360 auxdiv,
4361 divsel,
4362 phasedir,
4363 phaseinc);
4364
4365 mutex_lock(&dev_priv->sb_lock);
4366
4367 /* Program SSCDIVINTPHASE6 */
4368 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4369 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4370 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4371 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4372 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4373 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4374 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4375 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4376
4377 /* Program SSCAUXDIV */
4378 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4379 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4380 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4381 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4382
4383 /* Enable modulator and associated divider */
4384 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4385 temp &= ~SBI_SSCCTL_DISABLE;
4386 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4387
4388 mutex_unlock(&dev_priv->sb_lock);
4389
4390 /* Wait for initialization time */
4391 udelay(24);
4392
4393 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4394 }
4395
4396 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4397 {
4398 u32 divsel, phaseinc, auxdiv;
4399 u32 iclk_virtual_root_freq = 172800 * 1000;
4400 u32 iclk_pi_range = 64;
4401 u32 desired_divisor;
4402 u32 temp;
4403
4404 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4405 return 0;
4406
4407 mutex_lock(&dev_priv->sb_lock);
4408
4409 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4410 if (temp & SBI_SSCCTL_DISABLE) {
4411 mutex_unlock(&dev_priv->sb_lock);
4412 return 0;
4413 }
4414
4415 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4416 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4417 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4418 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4419 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4420
4421 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4422 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4423 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4424
4425 mutex_unlock(&dev_priv->sb_lock);
4426
4427 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4428
4429 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4430 desired_divisor << auxdiv);
4431 }
4432
4433 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4434 enum pipe pch_transcoder)
4435 {
4436 struct drm_device *dev = crtc->base.dev;
4437 struct drm_i915_private *dev_priv = to_i915(dev);
4438 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4439
4440 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4441 I915_READ(HTOTAL(cpu_transcoder)));
4442 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4443 I915_READ(HBLANK(cpu_transcoder)));
4444 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4445 I915_READ(HSYNC(cpu_transcoder)));
4446
4447 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4448 I915_READ(VTOTAL(cpu_transcoder)));
4449 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4450 I915_READ(VBLANK(cpu_transcoder)));
4451 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4452 I915_READ(VSYNC(cpu_transcoder)));
4453 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4454 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4455 }
4456
4457 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4458 {
4459 struct drm_i915_private *dev_priv = to_i915(dev);
4460 uint32_t temp;
4461
4462 temp = I915_READ(SOUTH_CHICKEN1);
4463 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4464 return;
4465
4466 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4467 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4468
4469 temp &= ~FDI_BC_BIFURCATION_SELECT;
4470 if (enable)
4471 temp |= FDI_BC_BIFURCATION_SELECT;
4472
4473 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4474 I915_WRITE(SOUTH_CHICKEN1, temp);
4475 POSTING_READ(SOUTH_CHICKEN1);
4476 }
4477
4478 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4479 {
4480 struct drm_device *dev = intel_crtc->base.dev;
4481
4482 switch (intel_crtc->pipe) {
4483 case PIPE_A:
4484 break;
4485 case PIPE_B:
4486 if (intel_crtc->config->fdi_lanes > 2)
4487 cpt_set_fdi_bc_bifurcation(dev, false);
4488 else
4489 cpt_set_fdi_bc_bifurcation(dev, true);
4490
4491 break;
4492 case PIPE_C:
4493 cpt_set_fdi_bc_bifurcation(dev, true);
4494
4495 break;
4496 default:
4497 BUG();
4498 }
4499 }
4500
4501 /* Return which DP Port should be selected for Transcoder DP control */
4502 static enum port
4503 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4504 {
4505 struct drm_device *dev = crtc->dev;
4506 struct intel_encoder *encoder;
4507
4508 for_each_encoder_on_crtc(dev, crtc, encoder) {
4509 if (encoder->type == INTEL_OUTPUT_DP ||
4510 encoder->type == INTEL_OUTPUT_EDP)
4511 return enc_to_dig_port(&encoder->base)->port;
4512 }
4513
4514 return -1;
4515 }
4516
4517 /*
4518 * Enable PCH resources required for PCH ports:
4519 * - PCH PLLs
4520 * - FDI training & RX/TX
4521 * - update transcoder timings
4522 * - DP transcoding bits
4523 * - transcoder
4524 */
4525 static void ironlake_pch_enable(struct drm_crtc *crtc)
4526 {
4527 struct drm_device *dev = crtc->dev;
4528 struct drm_i915_private *dev_priv = to_i915(dev);
4529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4530 int pipe = intel_crtc->pipe;
4531 u32 temp;
4532
4533 assert_pch_transcoder_disabled(dev_priv, pipe);
4534
4535 if (IS_IVYBRIDGE(dev_priv))
4536 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4537
4538 /* Write the TU size bits before fdi link training, so that error
4539 * detection works. */
4540 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4541 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4542
4543 /* For PCH output, training FDI link */
4544 dev_priv->display.fdi_link_train(crtc);
4545
4546 /* We need to program the right clock selection before writing the pixel
4547 * mutliplier into the DPLL. */
4548 if (HAS_PCH_CPT(dev_priv)) {
4549 u32 sel;
4550
4551 temp = I915_READ(PCH_DPLL_SEL);
4552 temp |= TRANS_DPLL_ENABLE(pipe);
4553 sel = TRANS_DPLLB_SEL(pipe);
4554 if (intel_crtc->config->shared_dpll ==
4555 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4556 temp |= sel;
4557 else
4558 temp &= ~sel;
4559 I915_WRITE(PCH_DPLL_SEL, temp);
4560 }
4561
4562 /* XXX: pch pll's can be enabled any time before we enable the PCH
4563 * transcoder, and we actually should do this to not upset any PCH
4564 * transcoder that already use the clock when we share it.
4565 *
4566 * Note that enable_shared_dpll tries to do the right thing, but
4567 * get_shared_dpll unconditionally resets the pll - we need that to have
4568 * the right LVDS enable sequence. */
4569 intel_enable_shared_dpll(intel_crtc);
4570
4571 /* set transcoder timing, panel must allow it */
4572 assert_panel_unlocked(dev_priv, pipe);
4573 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4574
4575 intel_fdi_normal_train(crtc);
4576
4577 /* For PCH DP, enable TRANS_DP_CTL */
4578 if (HAS_PCH_CPT(dev_priv) &&
4579 intel_crtc_has_dp_encoder(intel_crtc->config)) {
4580 const struct drm_display_mode *adjusted_mode =
4581 &intel_crtc->config->base.adjusted_mode;
4582 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4583 i915_reg_t reg = TRANS_DP_CTL(pipe);
4584 temp = I915_READ(reg);
4585 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4586 TRANS_DP_SYNC_MASK |
4587 TRANS_DP_BPC_MASK);
4588 temp |= TRANS_DP_OUTPUT_ENABLE;
4589 temp |= bpc << 9; /* same format but at 11:9 */
4590
4591 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4592 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4593 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4594 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4595
4596 switch (intel_trans_dp_port_sel(crtc)) {
4597 case PORT_B:
4598 temp |= TRANS_DP_PORT_SEL_B;
4599 break;
4600 case PORT_C:
4601 temp |= TRANS_DP_PORT_SEL_C;
4602 break;
4603 case PORT_D:
4604 temp |= TRANS_DP_PORT_SEL_D;
4605 break;
4606 default:
4607 BUG();
4608 }
4609
4610 I915_WRITE(reg, temp);
4611 }
4612
4613 ironlake_enable_pch_transcoder(dev_priv, pipe);
4614 }
4615
4616 static void lpt_pch_enable(struct drm_crtc *crtc)
4617 {
4618 struct drm_device *dev = crtc->dev;
4619 struct drm_i915_private *dev_priv = to_i915(dev);
4620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4621 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4622
4623 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4624
4625 lpt_program_iclkip(crtc);
4626
4627 /* Set transcoder timing. */
4628 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4629
4630 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4631 }
4632
4633 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4634 {
4635 struct drm_i915_private *dev_priv = to_i915(dev);
4636 i915_reg_t dslreg = PIPEDSL(pipe);
4637 u32 temp;
4638
4639 temp = I915_READ(dslreg);
4640 udelay(500);
4641 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4642 if (wait_for(I915_READ(dslreg) != temp, 5))
4643 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4644 }
4645 }
4646
4647 static int
4648 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4649 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4650 int src_w, int src_h, int dst_w, int dst_h)
4651 {
4652 struct intel_crtc_scaler_state *scaler_state =
4653 &crtc_state->scaler_state;
4654 struct intel_crtc *intel_crtc =
4655 to_intel_crtc(crtc_state->base.crtc);
4656 int need_scaling;
4657
4658 need_scaling = drm_rotation_90_or_270(rotation) ?
4659 (src_h != dst_w || src_w != dst_h):
4660 (src_w != dst_w || src_h != dst_h);
4661
4662 /*
4663 * if plane is being disabled or scaler is no more required or force detach
4664 * - free scaler binded to this plane/crtc
4665 * - in order to do this, update crtc->scaler_usage
4666 *
4667 * Here scaler state in crtc_state is set free so that
4668 * scaler can be assigned to other user. Actual register
4669 * update to free the scaler is done in plane/panel-fit programming.
4670 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4671 */
4672 if (force_detach || !need_scaling) {
4673 if (*scaler_id >= 0) {
4674 scaler_state->scaler_users &= ~(1 << scaler_user);
4675 scaler_state->scalers[*scaler_id].in_use = 0;
4676
4677 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4678 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4679 intel_crtc->pipe, scaler_user, *scaler_id,
4680 scaler_state->scaler_users);
4681 *scaler_id = -1;
4682 }
4683 return 0;
4684 }
4685
4686 /* range checks */
4687 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4688 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4689
4690 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4691 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4692 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4693 "size is out of scaler range\n",
4694 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4695 return -EINVAL;
4696 }
4697
4698 /* mark this plane as a scaler user in crtc_state */
4699 scaler_state->scaler_users |= (1 << scaler_user);
4700 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4701 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4702 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4703 scaler_state->scaler_users);
4704
4705 return 0;
4706 }
4707
4708 /**
4709 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4710 *
4711 * @state: crtc's scaler state
4712 *
4713 * Return
4714 * 0 - scaler_usage updated successfully
4715 * error - requested scaling cannot be supported or other error condition
4716 */
4717 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4718 {
4719 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4720
4721 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4722 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4723 state->pipe_src_w, state->pipe_src_h,
4724 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4725 }
4726
4727 /**
4728 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4729 *
4730 * @state: crtc's scaler state
4731 * @plane_state: atomic plane state to update
4732 *
4733 * Return
4734 * 0 - scaler_usage updated successfully
4735 * error - requested scaling cannot be supported or other error condition
4736 */
4737 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4738 struct intel_plane_state *plane_state)
4739 {
4740
4741 struct intel_plane *intel_plane =
4742 to_intel_plane(plane_state->base.plane);
4743 struct drm_framebuffer *fb = plane_state->base.fb;
4744 int ret;
4745
4746 bool force_detach = !fb || !plane_state->base.visible;
4747
4748 ret = skl_update_scaler(crtc_state, force_detach,
4749 drm_plane_index(&intel_plane->base),
4750 &plane_state->scaler_id,
4751 plane_state->base.rotation,
4752 drm_rect_width(&plane_state->base.src) >> 16,
4753 drm_rect_height(&plane_state->base.src) >> 16,
4754 drm_rect_width(&plane_state->base.dst),
4755 drm_rect_height(&plane_state->base.dst));
4756
4757 if (ret || plane_state->scaler_id < 0)
4758 return ret;
4759
4760 /* check colorkey */
4761 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4762 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4763 intel_plane->base.base.id,
4764 intel_plane->base.name);
4765 return -EINVAL;
4766 }
4767
4768 /* Check src format */
4769 switch (fb->pixel_format) {
4770 case DRM_FORMAT_RGB565:
4771 case DRM_FORMAT_XBGR8888:
4772 case DRM_FORMAT_XRGB8888:
4773 case DRM_FORMAT_ABGR8888:
4774 case DRM_FORMAT_ARGB8888:
4775 case DRM_FORMAT_XRGB2101010:
4776 case DRM_FORMAT_XBGR2101010:
4777 case DRM_FORMAT_YUYV:
4778 case DRM_FORMAT_YVYU:
4779 case DRM_FORMAT_UYVY:
4780 case DRM_FORMAT_VYUY:
4781 break;
4782 default:
4783 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4784 intel_plane->base.base.id, intel_plane->base.name,
4785 fb->base.id, fb->pixel_format);
4786 return -EINVAL;
4787 }
4788
4789 return 0;
4790 }
4791
4792 static void skylake_scaler_disable(struct intel_crtc *crtc)
4793 {
4794 int i;
4795
4796 for (i = 0; i < crtc->num_scalers; i++)
4797 skl_detach_scaler(crtc, i);
4798 }
4799
4800 static void skylake_pfit_enable(struct intel_crtc *crtc)
4801 {
4802 struct drm_device *dev = crtc->base.dev;
4803 struct drm_i915_private *dev_priv = to_i915(dev);
4804 int pipe = crtc->pipe;
4805 struct intel_crtc_scaler_state *scaler_state =
4806 &crtc->config->scaler_state;
4807
4808 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4809
4810 if (crtc->config->pch_pfit.enabled) {
4811 int id;
4812
4813 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4814 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4815 return;
4816 }
4817
4818 id = scaler_state->scaler_id;
4819 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4820 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4821 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4822 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4823
4824 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4825 }
4826 }
4827
4828 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4829 {
4830 struct drm_device *dev = crtc->base.dev;
4831 struct drm_i915_private *dev_priv = to_i915(dev);
4832 int pipe = crtc->pipe;
4833
4834 if (crtc->config->pch_pfit.enabled) {
4835 /* Force use of hard-coded filter coefficients
4836 * as some pre-programmed values are broken,
4837 * e.g. x201.
4838 */
4839 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4840 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4841 PF_PIPE_SEL_IVB(pipe));
4842 else
4843 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4844 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4845 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4846 }
4847 }
4848
4849 void hsw_enable_ips(struct intel_crtc *crtc)
4850 {
4851 struct drm_device *dev = crtc->base.dev;
4852 struct drm_i915_private *dev_priv = to_i915(dev);
4853
4854 if (!crtc->config->ips_enabled)
4855 return;
4856
4857 /*
4858 * We can only enable IPS after we enable a plane and wait for a vblank
4859 * This function is called from post_plane_update, which is run after
4860 * a vblank wait.
4861 */
4862
4863 assert_plane_enabled(dev_priv, crtc->plane);
4864 if (IS_BROADWELL(dev_priv)) {
4865 mutex_lock(&dev_priv->rps.hw_lock);
4866 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4867 mutex_unlock(&dev_priv->rps.hw_lock);
4868 /* Quoting Art Runyan: "its not safe to expect any particular
4869 * value in IPS_CTL bit 31 after enabling IPS through the
4870 * mailbox." Moreover, the mailbox may return a bogus state,
4871 * so we need to just enable it and continue on.
4872 */
4873 } else {
4874 I915_WRITE(IPS_CTL, IPS_ENABLE);
4875 /* The bit only becomes 1 in the next vblank, so this wait here
4876 * is essentially intel_wait_for_vblank. If we don't have this
4877 * and don't wait for vblanks until the end of crtc_enable, then
4878 * the HW state readout code will complain that the expected
4879 * IPS_CTL value is not the one we read. */
4880 if (intel_wait_for_register(dev_priv,
4881 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4882 50))
4883 DRM_ERROR("Timed out waiting for IPS enable\n");
4884 }
4885 }
4886
4887 void hsw_disable_ips(struct intel_crtc *crtc)
4888 {
4889 struct drm_device *dev = crtc->base.dev;
4890 struct drm_i915_private *dev_priv = to_i915(dev);
4891
4892 if (!crtc->config->ips_enabled)
4893 return;
4894
4895 assert_plane_enabled(dev_priv, crtc->plane);
4896 if (IS_BROADWELL(dev_priv)) {
4897 mutex_lock(&dev_priv->rps.hw_lock);
4898 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4899 mutex_unlock(&dev_priv->rps.hw_lock);
4900 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4901 if (intel_wait_for_register(dev_priv,
4902 IPS_CTL, IPS_ENABLE, 0,
4903 42))
4904 DRM_ERROR("Timed out waiting for IPS disable\n");
4905 } else {
4906 I915_WRITE(IPS_CTL, 0);
4907 POSTING_READ(IPS_CTL);
4908 }
4909
4910 /* We need to wait for a vblank before we can disable the plane. */
4911 intel_wait_for_vblank(dev_priv, crtc->pipe);
4912 }
4913
4914 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4915 {
4916 if (intel_crtc->overlay) {
4917 struct drm_device *dev = intel_crtc->base.dev;
4918 struct drm_i915_private *dev_priv = to_i915(dev);
4919
4920 mutex_lock(&dev->struct_mutex);
4921 dev_priv->mm.interruptible = false;
4922 (void) intel_overlay_switch_off(intel_crtc->overlay);
4923 dev_priv->mm.interruptible = true;
4924 mutex_unlock(&dev->struct_mutex);
4925 }
4926
4927 /* Let userspace switch the overlay on again. In most cases userspace
4928 * has to recompute where to put it anyway.
4929 */
4930 }
4931
4932 /**
4933 * intel_post_enable_primary - Perform operations after enabling primary plane
4934 * @crtc: the CRTC whose primary plane was just enabled
4935 *
4936 * Performs potentially sleeping operations that must be done after the primary
4937 * plane is enabled, such as updating FBC and IPS. Note that this may be
4938 * called due to an explicit primary plane update, or due to an implicit
4939 * re-enable that is caused when a sprite plane is updated to no longer
4940 * completely hide the primary plane.
4941 */
4942 static void
4943 intel_post_enable_primary(struct drm_crtc *crtc)
4944 {
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_i915_private *dev_priv = to_i915(dev);
4947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948 int pipe = intel_crtc->pipe;
4949
4950 /*
4951 * FIXME IPS should be fine as long as one plane is
4952 * enabled, but in practice it seems to have problems
4953 * when going from primary only to sprite only and vice
4954 * versa.
4955 */
4956 hsw_enable_ips(intel_crtc);
4957
4958 /*
4959 * Gen2 reports pipe underruns whenever all planes are disabled.
4960 * So don't enable underrun reporting before at least some planes
4961 * are enabled.
4962 * FIXME: Need to fix the logic to work when we turn off all planes
4963 * but leave the pipe running.
4964 */
4965 if (IS_GEN2(dev_priv))
4966 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4967
4968 /* Underruns don't always raise interrupts, so check manually. */
4969 intel_check_cpu_fifo_underruns(dev_priv);
4970 intel_check_pch_fifo_underruns(dev_priv);
4971 }
4972
4973 /* FIXME move all this to pre_plane_update() with proper state tracking */
4974 static void
4975 intel_pre_disable_primary(struct drm_crtc *crtc)
4976 {
4977 struct drm_device *dev = crtc->dev;
4978 struct drm_i915_private *dev_priv = to_i915(dev);
4979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980 int pipe = intel_crtc->pipe;
4981
4982 /*
4983 * Gen2 reports pipe underruns whenever all planes are disabled.
4984 * So diasble underrun reporting before all the planes get disabled.
4985 * FIXME: Need to fix the logic to work when we turn off all planes
4986 * but leave the pipe running.
4987 */
4988 if (IS_GEN2(dev_priv))
4989 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4990
4991 /*
4992 * FIXME IPS should be fine as long as one plane is
4993 * enabled, but in practice it seems to have problems
4994 * when going from primary only to sprite only and vice
4995 * versa.
4996 */
4997 hsw_disable_ips(intel_crtc);
4998 }
4999
5000 /* FIXME get rid of this and use pre_plane_update */
5001 static void
5002 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5003 {
5004 struct drm_device *dev = crtc->dev;
5005 struct drm_i915_private *dev_priv = to_i915(dev);
5006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007 int pipe = intel_crtc->pipe;
5008
5009 intel_pre_disable_primary(crtc);
5010
5011 /*
5012 * Vblank time updates from the shadow to live plane control register
5013 * are blocked if the memory self-refresh mode is active at that
5014 * moment. So to make sure the plane gets truly disabled, disable
5015 * first the self-refresh mode. The self-refresh enable bit in turn
5016 * will be checked/applied by the HW only at the next frame start
5017 * event which is after the vblank start event, so we need to have a
5018 * wait-for-vblank between disabling the plane and the pipe.
5019 */
5020 if (HAS_GMCH_DISPLAY(dev_priv)) {
5021 intel_set_memory_cxsr(dev_priv, false);
5022 dev_priv->wm.vlv.cxsr = false;
5023 intel_wait_for_vblank(dev_priv, pipe);
5024 }
5025 }
5026
5027 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5028 {
5029 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5030 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5031 struct intel_crtc_state *pipe_config =
5032 to_intel_crtc_state(crtc->base.state);
5033 struct drm_plane *primary = crtc->base.primary;
5034 struct drm_plane_state *old_pri_state =
5035 drm_atomic_get_existing_plane_state(old_state, primary);
5036
5037 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5038
5039 crtc->wm.cxsr_allowed = true;
5040
5041 if (pipe_config->update_wm_post && pipe_config->base.active)
5042 intel_update_watermarks(crtc);
5043
5044 if (old_pri_state) {
5045 struct intel_plane_state *primary_state =
5046 to_intel_plane_state(primary->state);
5047 struct intel_plane_state *old_primary_state =
5048 to_intel_plane_state(old_pri_state);
5049
5050 intel_fbc_post_update(crtc);
5051
5052 if (primary_state->base.visible &&
5053 (needs_modeset(&pipe_config->base) ||
5054 !old_primary_state->base.visible))
5055 intel_post_enable_primary(&crtc->base);
5056 }
5057 }
5058
5059 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5060 {
5061 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5062 struct drm_device *dev = crtc->base.dev;
5063 struct drm_i915_private *dev_priv = to_i915(dev);
5064 struct intel_crtc_state *pipe_config =
5065 to_intel_crtc_state(crtc->base.state);
5066 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5067 struct drm_plane *primary = crtc->base.primary;
5068 struct drm_plane_state *old_pri_state =
5069 drm_atomic_get_existing_plane_state(old_state, primary);
5070 bool modeset = needs_modeset(&pipe_config->base);
5071 struct intel_atomic_state *old_intel_state =
5072 to_intel_atomic_state(old_state);
5073
5074 if (old_pri_state) {
5075 struct intel_plane_state *primary_state =
5076 to_intel_plane_state(primary->state);
5077 struct intel_plane_state *old_primary_state =
5078 to_intel_plane_state(old_pri_state);
5079
5080 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5081
5082 if (old_primary_state->base.visible &&
5083 (modeset || !primary_state->base.visible))
5084 intel_pre_disable_primary(&crtc->base);
5085 }
5086
5087 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5088 crtc->wm.cxsr_allowed = false;
5089
5090 /*
5091 * Vblank time updates from the shadow to live plane control register
5092 * are blocked if the memory self-refresh mode is active at that
5093 * moment. So to make sure the plane gets truly disabled, disable
5094 * first the self-refresh mode. The self-refresh enable bit in turn
5095 * will be checked/applied by the HW only at the next frame start
5096 * event which is after the vblank start event, so we need to have a
5097 * wait-for-vblank between disabling the plane and the pipe.
5098 */
5099 if (old_crtc_state->base.active) {
5100 intel_set_memory_cxsr(dev_priv, false);
5101 dev_priv->wm.vlv.cxsr = false;
5102 intel_wait_for_vblank(dev_priv, crtc->pipe);
5103 }
5104 }
5105
5106 /*
5107 * IVB workaround: must disable low power watermarks for at least
5108 * one frame before enabling scaling. LP watermarks can be re-enabled
5109 * when scaling is disabled.
5110 *
5111 * WaCxSRDisabledForSpriteScaling:ivb
5112 */
5113 if (pipe_config->disable_lp_wm) {
5114 ilk_disable_lp_wm(dev);
5115 intel_wait_for_vblank(dev_priv, crtc->pipe);
5116 }
5117
5118 /*
5119 * If we're doing a modeset, we're done. No need to do any pre-vblank
5120 * watermark programming here.
5121 */
5122 if (needs_modeset(&pipe_config->base))
5123 return;
5124
5125 /*
5126 * For platforms that support atomic watermarks, program the
5127 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5128 * will be the intermediate values that are safe for both pre- and
5129 * post- vblank; when vblank happens, the 'active' values will be set
5130 * to the final 'target' values and we'll do this again to get the
5131 * optimal watermarks. For gen9+ platforms, the values we program here
5132 * will be the final target values which will get automatically latched
5133 * at vblank time; no further programming will be necessary.
5134 *
5135 * If a platform hasn't been transitioned to atomic watermarks yet,
5136 * we'll continue to update watermarks the old way, if flags tell
5137 * us to.
5138 */
5139 if (dev_priv->display.initial_watermarks != NULL)
5140 dev_priv->display.initial_watermarks(old_intel_state,
5141 pipe_config);
5142 else if (pipe_config->update_wm_pre)
5143 intel_update_watermarks(crtc);
5144 }
5145
5146 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5147 {
5148 struct drm_device *dev = crtc->dev;
5149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5150 struct drm_plane *p;
5151 int pipe = intel_crtc->pipe;
5152
5153 intel_crtc_dpms_overlay_disable(intel_crtc);
5154
5155 drm_for_each_plane_mask(p, dev, plane_mask)
5156 to_intel_plane(p)->disable_plane(p, crtc);
5157
5158 /*
5159 * FIXME: Once we grow proper nuclear flip support out of this we need
5160 * to compute the mask of flip planes precisely. For the time being
5161 * consider this a flip to a NULL plane.
5162 */
5163 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5164 }
5165
5166 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5167 struct intel_crtc_state *crtc_state,
5168 struct drm_atomic_state *old_state)
5169 {
5170 struct drm_connector_state *old_conn_state;
5171 struct drm_connector *conn;
5172 int i;
5173
5174 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5175 struct drm_connector_state *conn_state = conn->state;
5176 struct intel_encoder *encoder =
5177 to_intel_encoder(conn_state->best_encoder);
5178
5179 if (conn_state->crtc != crtc)
5180 continue;
5181
5182 if (encoder->pre_pll_enable)
5183 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5184 }
5185 }
5186
5187 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5188 struct intel_crtc_state *crtc_state,
5189 struct drm_atomic_state *old_state)
5190 {
5191 struct drm_connector_state *old_conn_state;
5192 struct drm_connector *conn;
5193 int i;
5194
5195 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5196 struct drm_connector_state *conn_state = conn->state;
5197 struct intel_encoder *encoder =
5198 to_intel_encoder(conn_state->best_encoder);
5199
5200 if (conn_state->crtc != crtc)
5201 continue;
5202
5203 if (encoder->pre_enable)
5204 encoder->pre_enable(encoder, crtc_state, conn_state);
5205 }
5206 }
5207
5208 static void intel_encoders_enable(struct drm_crtc *crtc,
5209 struct intel_crtc_state *crtc_state,
5210 struct drm_atomic_state *old_state)
5211 {
5212 struct drm_connector_state *old_conn_state;
5213 struct drm_connector *conn;
5214 int i;
5215
5216 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5217 struct drm_connector_state *conn_state = conn->state;
5218 struct intel_encoder *encoder =
5219 to_intel_encoder(conn_state->best_encoder);
5220
5221 if (conn_state->crtc != crtc)
5222 continue;
5223
5224 encoder->enable(encoder, crtc_state, conn_state);
5225 intel_opregion_notify_encoder(encoder, true);
5226 }
5227 }
5228
5229 static void intel_encoders_disable(struct drm_crtc *crtc,
5230 struct intel_crtc_state *old_crtc_state,
5231 struct drm_atomic_state *old_state)
5232 {
5233 struct drm_connector_state *old_conn_state;
5234 struct drm_connector *conn;
5235 int i;
5236
5237 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5238 struct intel_encoder *encoder =
5239 to_intel_encoder(old_conn_state->best_encoder);
5240
5241 if (old_conn_state->crtc != crtc)
5242 continue;
5243
5244 intel_opregion_notify_encoder(encoder, false);
5245 encoder->disable(encoder, old_crtc_state, old_conn_state);
5246 }
5247 }
5248
5249 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5250 struct intel_crtc_state *old_crtc_state,
5251 struct drm_atomic_state *old_state)
5252 {
5253 struct drm_connector_state *old_conn_state;
5254 struct drm_connector *conn;
5255 int i;
5256
5257 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5258 struct intel_encoder *encoder =
5259 to_intel_encoder(old_conn_state->best_encoder);
5260
5261 if (old_conn_state->crtc != crtc)
5262 continue;
5263
5264 if (encoder->post_disable)
5265 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5266 }
5267 }
5268
5269 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5270 struct intel_crtc_state *old_crtc_state,
5271 struct drm_atomic_state *old_state)
5272 {
5273 struct drm_connector_state *old_conn_state;
5274 struct drm_connector *conn;
5275 int i;
5276
5277 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5278 struct intel_encoder *encoder =
5279 to_intel_encoder(old_conn_state->best_encoder);
5280
5281 if (old_conn_state->crtc != crtc)
5282 continue;
5283
5284 if (encoder->post_pll_disable)
5285 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5286 }
5287 }
5288
5289 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5290 struct drm_atomic_state *old_state)
5291 {
5292 struct drm_crtc *crtc = pipe_config->base.crtc;
5293 struct drm_device *dev = crtc->dev;
5294 struct drm_i915_private *dev_priv = to_i915(dev);
5295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5296 int pipe = intel_crtc->pipe;
5297 struct intel_atomic_state *old_intel_state =
5298 to_intel_atomic_state(old_state);
5299
5300 if (WARN_ON(intel_crtc->active))
5301 return;
5302
5303 /*
5304 * Sometimes spurious CPU pipe underruns happen during FDI
5305 * training, at least with VGA+HDMI cloning. Suppress them.
5306 *
5307 * On ILK we get an occasional spurious CPU pipe underruns
5308 * between eDP port A enable and vdd enable. Also PCH port
5309 * enable seems to result in the occasional CPU pipe underrun.
5310 *
5311 * Spurious PCH underruns also occur during PCH enabling.
5312 */
5313 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5314 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5315 if (intel_crtc->config->has_pch_encoder)
5316 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5317
5318 if (intel_crtc->config->has_pch_encoder)
5319 intel_prepare_shared_dpll(intel_crtc);
5320
5321 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5322 intel_dp_set_m_n(intel_crtc, M1_N1);
5323
5324 intel_set_pipe_timings(intel_crtc);
5325 intel_set_pipe_src_size(intel_crtc);
5326
5327 if (intel_crtc->config->has_pch_encoder) {
5328 intel_cpu_transcoder_set_m_n(intel_crtc,
5329 &intel_crtc->config->fdi_m_n, NULL);
5330 }
5331
5332 ironlake_set_pipeconf(crtc);
5333
5334 intel_crtc->active = true;
5335
5336 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5337
5338 if (intel_crtc->config->has_pch_encoder) {
5339 /* Note: FDI PLL enabling _must_ be done before we enable the
5340 * cpu pipes, hence this is separate from all the other fdi/pch
5341 * enabling. */
5342 ironlake_fdi_pll_enable(intel_crtc);
5343 } else {
5344 assert_fdi_tx_disabled(dev_priv, pipe);
5345 assert_fdi_rx_disabled(dev_priv, pipe);
5346 }
5347
5348 ironlake_pfit_enable(intel_crtc);
5349
5350 /*
5351 * On ILK+ LUT must be loaded before the pipe is running but with
5352 * clocks enabled
5353 */
5354 intel_color_load_luts(&pipe_config->base);
5355
5356 if (dev_priv->display.initial_watermarks != NULL)
5357 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5358 intel_enable_pipe(intel_crtc);
5359
5360 if (intel_crtc->config->has_pch_encoder)
5361 ironlake_pch_enable(crtc);
5362
5363 assert_vblank_disabled(crtc);
5364 drm_crtc_vblank_on(crtc);
5365
5366 intel_encoders_enable(crtc, pipe_config, old_state);
5367
5368 if (HAS_PCH_CPT(dev_priv))
5369 cpt_verify_modeset(dev, intel_crtc->pipe);
5370
5371 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5372 if (intel_crtc->config->has_pch_encoder)
5373 intel_wait_for_vblank(dev_priv, pipe);
5374 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5375 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5376 }
5377
5378 /* IPS only exists on ULT machines and is tied to pipe A. */
5379 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5380 {
5381 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5382 }
5383
5384 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5385 struct drm_atomic_state *old_state)
5386 {
5387 struct drm_crtc *crtc = pipe_config->base.crtc;
5388 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5390 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5391 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5392 struct intel_atomic_state *old_intel_state =
5393 to_intel_atomic_state(old_state);
5394
5395 if (WARN_ON(intel_crtc->active))
5396 return;
5397
5398 if (intel_crtc->config->has_pch_encoder)
5399 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5400 false);
5401
5402 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5403
5404 if (intel_crtc->config->shared_dpll)
5405 intel_enable_shared_dpll(intel_crtc);
5406
5407 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5408 intel_dp_set_m_n(intel_crtc, M1_N1);
5409
5410 if (!transcoder_is_dsi(cpu_transcoder))
5411 intel_set_pipe_timings(intel_crtc);
5412
5413 intel_set_pipe_src_size(intel_crtc);
5414
5415 if (cpu_transcoder != TRANSCODER_EDP &&
5416 !transcoder_is_dsi(cpu_transcoder)) {
5417 I915_WRITE(PIPE_MULT(cpu_transcoder),
5418 intel_crtc->config->pixel_multiplier - 1);
5419 }
5420
5421 if (intel_crtc->config->has_pch_encoder) {
5422 intel_cpu_transcoder_set_m_n(intel_crtc,
5423 &intel_crtc->config->fdi_m_n, NULL);
5424 }
5425
5426 if (!transcoder_is_dsi(cpu_transcoder))
5427 haswell_set_pipeconf(crtc);
5428
5429 haswell_set_pipemisc(crtc);
5430
5431 intel_color_set_csc(&pipe_config->base);
5432
5433 intel_crtc->active = true;
5434
5435 if (intel_crtc->config->has_pch_encoder)
5436 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5437 else
5438 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5439
5440 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5441
5442 if (intel_crtc->config->has_pch_encoder)
5443 dev_priv->display.fdi_link_train(crtc);
5444
5445 if (!transcoder_is_dsi(cpu_transcoder))
5446 intel_ddi_enable_pipe_clock(intel_crtc);
5447
5448 if (INTEL_GEN(dev_priv) >= 9)
5449 skylake_pfit_enable(intel_crtc);
5450 else
5451 ironlake_pfit_enable(intel_crtc);
5452
5453 /*
5454 * On ILK+ LUT must be loaded before the pipe is running but with
5455 * clocks enabled
5456 */
5457 intel_color_load_luts(&pipe_config->base);
5458
5459 intel_ddi_set_pipe_settings(crtc);
5460 if (!transcoder_is_dsi(cpu_transcoder))
5461 intel_ddi_enable_transcoder_func(crtc);
5462
5463 if (dev_priv->display.initial_watermarks != NULL)
5464 dev_priv->display.initial_watermarks(old_intel_state,
5465 pipe_config);
5466 else
5467 intel_update_watermarks(intel_crtc);
5468
5469 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5470 if (!transcoder_is_dsi(cpu_transcoder))
5471 intel_enable_pipe(intel_crtc);
5472
5473 if (intel_crtc->config->has_pch_encoder)
5474 lpt_pch_enable(crtc);
5475
5476 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5477 intel_ddi_set_vc_payload_alloc(crtc, true);
5478
5479 assert_vblank_disabled(crtc);
5480 drm_crtc_vblank_on(crtc);
5481
5482 intel_encoders_enable(crtc, pipe_config, old_state);
5483
5484 if (intel_crtc->config->has_pch_encoder) {
5485 intel_wait_for_vblank(dev_priv, pipe);
5486 intel_wait_for_vblank(dev_priv, pipe);
5487 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5488 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5489 true);
5490 }
5491
5492 /* If we change the relative order between pipe/planes enabling, we need
5493 * to change the workaround. */
5494 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5495 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5496 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5497 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5498 }
5499 }
5500
5501 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5502 {
5503 struct drm_device *dev = crtc->base.dev;
5504 struct drm_i915_private *dev_priv = to_i915(dev);
5505 int pipe = crtc->pipe;
5506
5507 /* To avoid upsetting the power well on haswell only disable the pfit if
5508 * it's in use. The hw state code will make sure we get this right. */
5509 if (force || crtc->config->pch_pfit.enabled) {
5510 I915_WRITE(PF_CTL(pipe), 0);
5511 I915_WRITE(PF_WIN_POS(pipe), 0);
5512 I915_WRITE(PF_WIN_SZ(pipe), 0);
5513 }
5514 }
5515
5516 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5517 struct drm_atomic_state *old_state)
5518 {
5519 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5520 struct drm_device *dev = crtc->dev;
5521 struct drm_i915_private *dev_priv = to_i915(dev);
5522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5523 int pipe = intel_crtc->pipe;
5524
5525 /*
5526 * Sometimes spurious CPU pipe underruns happen when the
5527 * pipe is already disabled, but FDI RX/TX is still enabled.
5528 * Happens at least with VGA+HDMI cloning. Suppress them.
5529 */
5530 if (intel_crtc->config->has_pch_encoder) {
5531 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5532 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5533 }
5534
5535 intel_encoders_disable(crtc, old_crtc_state, old_state);
5536
5537 drm_crtc_vblank_off(crtc);
5538 assert_vblank_disabled(crtc);
5539
5540 intel_disable_pipe(intel_crtc);
5541
5542 ironlake_pfit_disable(intel_crtc, false);
5543
5544 if (intel_crtc->config->has_pch_encoder)
5545 ironlake_fdi_disable(crtc);
5546
5547 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5548
5549 if (intel_crtc->config->has_pch_encoder) {
5550 ironlake_disable_pch_transcoder(dev_priv, pipe);
5551
5552 if (HAS_PCH_CPT(dev_priv)) {
5553 i915_reg_t reg;
5554 u32 temp;
5555
5556 /* disable TRANS_DP_CTL */
5557 reg = TRANS_DP_CTL(pipe);
5558 temp = I915_READ(reg);
5559 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5560 TRANS_DP_PORT_SEL_MASK);
5561 temp |= TRANS_DP_PORT_SEL_NONE;
5562 I915_WRITE(reg, temp);
5563
5564 /* disable DPLL_SEL */
5565 temp = I915_READ(PCH_DPLL_SEL);
5566 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5567 I915_WRITE(PCH_DPLL_SEL, temp);
5568 }
5569
5570 ironlake_fdi_pll_disable(intel_crtc);
5571 }
5572
5573 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5574 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5575 }
5576
5577 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5578 struct drm_atomic_state *old_state)
5579 {
5580 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5581 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5583 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5584
5585 if (intel_crtc->config->has_pch_encoder)
5586 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5587 false);
5588
5589 intel_encoders_disable(crtc, old_crtc_state, old_state);
5590
5591 drm_crtc_vblank_off(crtc);
5592 assert_vblank_disabled(crtc);
5593
5594 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5595 if (!transcoder_is_dsi(cpu_transcoder))
5596 intel_disable_pipe(intel_crtc);
5597
5598 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5599 intel_ddi_set_vc_payload_alloc(crtc, false);
5600
5601 if (!transcoder_is_dsi(cpu_transcoder))
5602 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5603
5604 if (INTEL_GEN(dev_priv) >= 9)
5605 skylake_scaler_disable(intel_crtc);
5606 else
5607 ironlake_pfit_disable(intel_crtc, false);
5608
5609 if (!transcoder_is_dsi(cpu_transcoder))
5610 intel_ddi_disable_pipe_clock(intel_crtc);
5611
5612 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5613
5614 if (old_crtc_state->has_pch_encoder)
5615 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5616 true);
5617 }
5618
5619 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5620 {
5621 struct drm_device *dev = crtc->base.dev;
5622 struct drm_i915_private *dev_priv = to_i915(dev);
5623 struct intel_crtc_state *pipe_config = crtc->config;
5624
5625 if (!pipe_config->gmch_pfit.control)
5626 return;
5627
5628 /*
5629 * The panel fitter should only be adjusted whilst the pipe is disabled,
5630 * according to register description and PRM.
5631 */
5632 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5633 assert_pipe_disabled(dev_priv, crtc->pipe);
5634
5635 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5636 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5637
5638 /* Border color in case we don't scale up to the full screen. Black by
5639 * default, change to something else for debugging. */
5640 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5641 }
5642
5643 static enum intel_display_power_domain port_to_power_domain(enum port port)
5644 {
5645 switch (port) {
5646 case PORT_A:
5647 return POWER_DOMAIN_PORT_DDI_A_LANES;
5648 case PORT_B:
5649 return POWER_DOMAIN_PORT_DDI_B_LANES;
5650 case PORT_C:
5651 return POWER_DOMAIN_PORT_DDI_C_LANES;
5652 case PORT_D:
5653 return POWER_DOMAIN_PORT_DDI_D_LANES;
5654 case PORT_E:
5655 return POWER_DOMAIN_PORT_DDI_E_LANES;
5656 default:
5657 MISSING_CASE(port);
5658 return POWER_DOMAIN_PORT_OTHER;
5659 }
5660 }
5661
5662 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5663 {
5664 switch (port) {
5665 case PORT_A:
5666 return POWER_DOMAIN_AUX_A;
5667 case PORT_B:
5668 return POWER_DOMAIN_AUX_B;
5669 case PORT_C:
5670 return POWER_DOMAIN_AUX_C;
5671 case PORT_D:
5672 return POWER_DOMAIN_AUX_D;
5673 case PORT_E:
5674 /* FIXME: Check VBT for actual wiring of PORT E */
5675 return POWER_DOMAIN_AUX_D;
5676 default:
5677 MISSING_CASE(port);
5678 return POWER_DOMAIN_AUX_A;
5679 }
5680 }
5681
5682 enum intel_display_power_domain
5683 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5684 {
5685 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5686 struct intel_digital_port *intel_dig_port;
5687
5688 switch (intel_encoder->type) {
5689 case INTEL_OUTPUT_UNKNOWN:
5690 /* Only DDI platforms should ever use this output type */
5691 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5692 case INTEL_OUTPUT_DP:
5693 case INTEL_OUTPUT_HDMI:
5694 case INTEL_OUTPUT_EDP:
5695 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5696 return port_to_power_domain(intel_dig_port->port);
5697 case INTEL_OUTPUT_DP_MST:
5698 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5699 return port_to_power_domain(intel_dig_port->port);
5700 case INTEL_OUTPUT_ANALOG:
5701 return POWER_DOMAIN_PORT_CRT;
5702 case INTEL_OUTPUT_DSI:
5703 return POWER_DOMAIN_PORT_DSI;
5704 default:
5705 return POWER_DOMAIN_PORT_OTHER;
5706 }
5707 }
5708
5709 enum intel_display_power_domain
5710 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5711 {
5712 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5713 struct intel_digital_port *intel_dig_port;
5714
5715 switch (intel_encoder->type) {
5716 case INTEL_OUTPUT_UNKNOWN:
5717 case INTEL_OUTPUT_HDMI:
5718 /*
5719 * Only DDI platforms should ever use these output types.
5720 * We can get here after the HDMI detect code has already set
5721 * the type of the shared encoder. Since we can't be sure
5722 * what's the status of the given connectors, play safe and
5723 * run the DP detection too.
5724 */
5725 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5726 case INTEL_OUTPUT_DP:
5727 case INTEL_OUTPUT_EDP:
5728 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5729 return port_to_aux_power_domain(intel_dig_port->port);
5730 case INTEL_OUTPUT_DP_MST:
5731 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5732 return port_to_aux_power_domain(intel_dig_port->port);
5733 default:
5734 MISSING_CASE(intel_encoder->type);
5735 return POWER_DOMAIN_AUX_A;
5736 }
5737 }
5738
5739 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5740 struct intel_crtc_state *crtc_state)
5741 {
5742 struct drm_device *dev = crtc->dev;
5743 struct drm_encoder *encoder;
5744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5745 enum pipe pipe = intel_crtc->pipe;
5746 unsigned long mask;
5747 enum transcoder transcoder = crtc_state->cpu_transcoder;
5748
5749 if (!crtc_state->base.active)
5750 return 0;
5751
5752 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5753 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5754 if (crtc_state->pch_pfit.enabled ||
5755 crtc_state->pch_pfit.force_thru)
5756 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5757
5758 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5759 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5760
5761 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5762 }
5763
5764 if (crtc_state->shared_dpll)
5765 mask |= BIT(POWER_DOMAIN_PLLS);
5766
5767 return mask;
5768 }
5769
5770 static unsigned long
5771 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5772 struct intel_crtc_state *crtc_state)
5773 {
5774 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5776 enum intel_display_power_domain domain;
5777 unsigned long domains, new_domains, old_domains;
5778
5779 old_domains = intel_crtc->enabled_power_domains;
5780 intel_crtc->enabled_power_domains = new_domains =
5781 get_crtc_power_domains(crtc, crtc_state);
5782
5783 domains = new_domains & ~old_domains;
5784
5785 for_each_power_domain(domain, domains)
5786 intel_display_power_get(dev_priv, domain);
5787
5788 return old_domains & ~new_domains;
5789 }
5790
5791 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5792 unsigned long domains)
5793 {
5794 enum intel_display_power_domain domain;
5795
5796 for_each_power_domain(domain, domains)
5797 intel_display_power_put(dev_priv, domain);
5798 }
5799
5800 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5801 {
5802 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5803
5804 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5805 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5806 return max_cdclk_freq;
5807 else if (IS_CHERRYVIEW(dev_priv))
5808 return max_cdclk_freq*95/100;
5809 else if (INTEL_INFO(dev_priv)->gen < 4)
5810 return 2*max_cdclk_freq*90/100;
5811 else
5812 return max_cdclk_freq*90/100;
5813 }
5814
5815 static int skl_calc_cdclk(int max_pixclk, int vco);
5816
5817 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5818 {
5819 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5820 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5821 int max_cdclk, vco;
5822
5823 vco = dev_priv->skl_preferred_vco_freq;
5824 WARN_ON(vco != 8100000 && vco != 8640000);
5825
5826 /*
5827 * Use the lower (vco 8640) cdclk values as a
5828 * first guess. skl_calc_cdclk() will correct it
5829 * if the preferred vco is 8100 instead.
5830 */
5831 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5832 max_cdclk = 617143;
5833 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5834 max_cdclk = 540000;
5835 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5836 max_cdclk = 432000;
5837 else
5838 max_cdclk = 308571;
5839
5840 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5841 } else if (IS_BROXTON(dev_priv)) {
5842 dev_priv->max_cdclk_freq = 624000;
5843 } else if (IS_BROADWELL(dev_priv)) {
5844 /*
5845 * FIXME with extra cooling we can allow
5846 * 540 MHz for ULX and 675 Mhz for ULT.
5847 * How can we know if extra cooling is
5848 * available? PCI ID, VTB, something else?
5849 */
5850 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5851 dev_priv->max_cdclk_freq = 450000;
5852 else if (IS_BDW_ULX(dev_priv))
5853 dev_priv->max_cdclk_freq = 450000;
5854 else if (IS_BDW_ULT(dev_priv))
5855 dev_priv->max_cdclk_freq = 540000;
5856 else
5857 dev_priv->max_cdclk_freq = 675000;
5858 } else if (IS_CHERRYVIEW(dev_priv)) {
5859 dev_priv->max_cdclk_freq = 320000;
5860 } else if (IS_VALLEYVIEW(dev_priv)) {
5861 dev_priv->max_cdclk_freq = 400000;
5862 } else {
5863 /* otherwise assume cdclk is fixed */
5864 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5865 }
5866
5867 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5868
5869 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5870 dev_priv->max_cdclk_freq);
5871
5872 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5873 dev_priv->max_dotclk_freq);
5874 }
5875
5876 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5877 {
5878 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5879
5880 if (INTEL_GEN(dev_priv) >= 9)
5881 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5882 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5883 dev_priv->cdclk_pll.ref);
5884 else
5885 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5886 dev_priv->cdclk_freq);
5887
5888 /*
5889 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5890 * Programmng [sic] note: bit[9:2] should be programmed to the number
5891 * of cdclk that generates 4MHz reference clock freq which is used to
5892 * generate GMBus clock. This will vary with the cdclk freq.
5893 */
5894 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5895 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5896 }
5897
5898 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5899 static int skl_cdclk_decimal(int cdclk)
5900 {
5901 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5902 }
5903
5904 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5905 {
5906 int ratio;
5907
5908 if (cdclk == dev_priv->cdclk_pll.ref)
5909 return 0;
5910
5911 switch (cdclk) {
5912 default:
5913 MISSING_CASE(cdclk);
5914 case 144000:
5915 case 288000:
5916 case 384000:
5917 case 576000:
5918 ratio = 60;
5919 break;
5920 case 624000:
5921 ratio = 65;
5922 break;
5923 }
5924
5925 return dev_priv->cdclk_pll.ref * ratio;
5926 }
5927
5928 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5929 {
5930 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5931
5932 /* Timeout 200us */
5933 if (intel_wait_for_register(dev_priv,
5934 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5935 1))
5936 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5937
5938 dev_priv->cdclk_pll.vco = 0;
5939 }
5940
5941 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5942 {
5943 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5944 u32 val;
5945
5946 val = I915_READ(BXT_DE_PLL_CTL);
5947 val &= ~BXT_DE_PLL_RATIO_MASK;
5948 val |= BXT_DE_PLL_RATIO(ratio);
5949 I915_WRITE(BXT_DE_PLL_CTL, val);
5950
5951 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5952
5953 /* Timeout 200us */
5954 if (intel_wait_for_register(dev_priv,
5955 BXT_DE_PLL_ENABLE,
5956 BXT_DE_PLL_LOCK,
5957 BXT_DE_PLL_LOCK,
5958 1))
5959 DRM_ERROR("timeout waiting for DE PLL lock\n");
5960
5961 dev_priv->cdclk_pll.vco = vco;
5962 }
5963
5964 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5965 {
5966 u32 val, divider;
5967 int vco, ret;
5968
5969 vco = bxt_de_pll_vco(dev_priv, cdclk);
5970
5971 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5972
5973 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5974 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5975 case 8:
5976 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5977 break;
5978 case 4:
5979 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5980 break;
5981 case 3:
5982 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5983 break;
5984 case 2:
5985 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5986 break;
5987 default:
5988 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5989 WARN_ON(vco != 0);
5990
5991 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5992 break;
5993 }
5994
5995 /* Inform power controller of upcoming frequency change */
5996 mutex_lock(&dev_priv->rps.hw_lock);
5997 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5998 0x80000000);
5999 mutex_unlock(&dev_priv->rps.hw_lock);
6000
6001 if (ret) {
6002 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6003 ret, cdclk);
6004 return;
6005 }
6006
6007 if (dev_priv->cdclk_pll.vco != 0 &&
6008 dev_priv->cdclk_pll.vco != vco)
6009 bxt_de_pll_disable(dev_priv);
6010
6011 if (dev_priv->cdclk_pll.vco != vco)
6012 bxt_de_pll_enable(dev_priv, vco);
6013
6014 val = divider | skl_cdclk_decimal(cdclk);
6015 /*
6016 * FIXME if only the cd2x divider needs changing, it could be done
6017 * without shutting off the pipe (if only one pipe is active).
6018 */
6019 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6020 /*
6021 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6022 * enable otherwise.
6023 */
6024 if (cdclk >= 500000)
6025 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6026 I915_WRITE(CDCLK_CTL, val);
6027
6028 mutex_lock(&dev_priv->rps.hw_lock);
6029 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6030 DIV_ROUND_UP(cdclk, 25000));
6031 mutex_unlock(&dev_priv->rps.hw_lock);
6032
6033 if (ret) {
6034 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6035 ret, cdclk);
6036 return;
6037 }
6038
6039 intel_update_cdclk(dev_priv);
6040 }
6041
6042 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6043 {
6044 u32 cdctl, expected;
6045
6046 intel_update_cdclk(dev_priv);
6047
6048 if (dev_priv->cdclk_pll.vco == 0 ||
6049 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6050 goto sanitize;
6051
6052 /* DPLL okay; verify the cdclock
6053 *
6054 * Some BIOS versions leave an incorrect decimal frequency value and
6055 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6056 * so sanitize this register.
6057 */
6058 cdctl = I915_READ(CDCLK_CTL);
6059 /*
6060 * Let's ignore the pipe field, since BIOS could have configured the
6061 * dividers both synching to an active pipe, or asynchronously
6062 * (PIPE_NONE).
6063 */
6064 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6065
6066 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6067 skl_cdclk_decimal(dev_priv->cdclk_freq);
6068 /*
6069 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6070 * enable otherwise.
6071 */
6072 if (dev_priv->cdclk_freq >= 500000)
6073 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6074
6075 if (cdctl == expected)
6076 /* All well; nothing to sanitize */
6077 return;
6078
6079 sanitize:
6080 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6081
6082 /* force cdclk programming */
6083 dev_priv->cdclk_freq = 0;
6084
6085 /* force full PLL disable + enable */
6086 dev_priv->cdclk_pll.vco = -1;
6087 }
6088
6089 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6090 {
6091 bxt_sanitize_cdclk(dev_priv);
6092
6093 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6094 return;
6095
6096 /*
6097 * FIXME:
6098 * - The initial CDCLK needs to be read from VBT.
6099 * Need to make this change after VBT has changes for BXT.
6100 */
6101 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6102 }
6103
6104 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6105 {
6106 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6107 }
6108
6109 static int skl_calc_cdclk(int max_pixclk, int vco)
6110 {
6111 if (vco == 8640000) {
6112 if (max_pixclk > 540000)
6113 return 617143;
6114 else if (max_pixclk > 432000)
6115 return 540000;
6116 else if (max_pixclk > 308571)
6117 return 432000;
6118 else
6119 return 308571;
6120 } else {
6121 if (max_pixclk > 540000)
6122 return 675000;
6123 else if (max_pixclk > 450000)
6124 return 540000;
6125 else if (max_pixclk > 337500)
6126 return 450000;
6127 else
6128 return 337500;
6129 }
6130 }
6131
6132 static void
6133 skl_dpll0_update(struct drm_i915_private *dev_priv)
6134 {
6135 u32 val;
6136
6137 dev_priv->cdclk_pll.ref = 24000;
6138 dev_priv->cdclk_pll.vco = 0;
6139
6140 val = I915_READ(LCPLL1_CTL);
6141 if ((val & LCPLL_PLL_ENABLE) == 0)
6142 return;
6143
6144 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6145 return;
6146
6147 val = I915_READ(DPLL_CTRL1);
6148
6149 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6150 DPLL_CTRL1_SSC(SKL_DPLL0) |
6151 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6152 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6153 return;
6154
6155 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6156 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6157 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6158 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6159 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6160 dev_priv->cdclk_pll.vco = 8100000;
6161 break;
6162 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6163 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6164 dev_priv->cdclk_pll.vco = 8640000;
6165 break;
6166 default:
6167 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6168 break;
6169 }
6170 }
6171
6172 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6173 {
6174 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6175
6176 dev_priv->skl_preferred_vco_freq = vco;
6177
6178 if (changed)
6179 intel_update_max_cdclk(dev_priv);
6180 }
6181
6182 static void
6183 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6184 {
6185 int min_cdclk = skl_calc_cdclk(0, vco);
6186 u32 val;
6187
6188 WARN_ON(vco != 8100000 && vco != 8640000);
6189
6190 /* select the minimum CDCLK before enabling DPLL 0 */
6191 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6192 I915_WRITE(CDCLK_CTL, val);
6193 POSTING_READ(CDCLK_CTL);
6194
6195 /*
6196 * We always enable DPLL0 with the lowest link rate possible, but still
6197 * taking into account the VCO required to operate the eDP panel at the
6198 * desired frequency. The usual DP link rates operate with a VCO of
6199 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6200 * The modeset code is responsible for the selection of the exact link
6201 * rate later on, with the constraint of choosing a frequency that
6202 * works with vco.
6203 */
6204 val = I915_READ(DPLL_CTRL1);
6205
6206 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6207 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6208 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6209 if (vco == 8640000)
6210 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6211 SKL_DPLL0);
6212 else
6213 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6214 SKL_DPLL0);
6215
6216 I915_WRITE(DPLL_CTRL1, val);
6217 POSTING_READ(DPLL_CTRL1);
6218
6219 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6220
6221 if (intel_wait_for_register(dev_priv,
6222 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6223 5))
6224 DRM_ERROR("DPLL0 not locked\n");
6225
6226 dev_priv->cdclk_pll.vco = vco;
6227
6228 /* We'll want to keep using the current vco from now on. */
6229 skl_set_preferred_cdclk_vco(dev_priv, vco);
6230 }
6231
6232 static void
6233 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6234 {
6235 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6236 if (intel_wait_for_register(dev_priv,
6237 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6238 1))
6239 DRM_ERROR("Couldn't disable DPLL0\n");
6240
6241 dev_priv->cdclk_pll.vco = 0;
6242 }
6243
6244 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6245 {
6246 u32 freq_select, pcu_ack;
6247 int ret;
6248
6249 WARN_ON((cdclk == 24000) != (vco == 0));
6250
6251 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6252
6253 mutex_lock(&dev_priv->rps.hw_lock);
6254 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6255 SKL_CDCLK_PREPARE_FOR_CHANGE,
6256 SKL_CDCLK_READY_FOR_CHANGE,
6257 SKL_CDCLK_READY_FOR_CHANGE, 3);
6258 mutex_unlock(&dev_priv->rps.hw_lock);
6259 if (ret) {
6260 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6261 ret);
6262 return;
6263 }
6264
6265 /* set CDCLK_CTL */
6266 switch (cdclk) {
6267 case 450000:
6268 case 432000:
6269 freq_select = CDCLK_FREQ_450_432;
6270 pcu_ack = 1;
6271 break;
6272 case 540000:
6273 freq_select = CDCLK_FREQ_540;
6274 pcu_ack = 2;
6275 break;
6276 case 308571:
6277 case 337500:
6278 default:
6279 freq_select = CDCLK_FREQ_337_308;
6280 pcu_ack = 0;
6281 break;
6282 case 617143:
6283 case 675000:
6284 freq_select = CDCLK_FREQ_675_617;
6285 pcu_ack = 3;
6286 break;
6287 }
6288
6289 if (dev_priv->cdclk_pll.vco != 0 &&
6290 dev_priv->cdclk_pll.vco != vco)
6291 skl_dpll0_disable(dev_priv);
6292
6293 if (dev_priv->cdclk_pll.vco != vco)
6294 skl_dpll0_enable(dev_priv, vco);
6295
6296 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6297 POSTING_READ(CDCLK_CTL);
6298
6299 /* inform PCU of the change */
6300 mutex_lock(&dev_priv->rps.hw_lock);
6301 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6302 mutex_unlock(&dev_priv->rps.hw_lock);
6303
6304 intel_update_cdclk(dev_priv);
6305 }
6306
6307 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6308
6309 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6310 {
6311 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6312 }
6313
6314 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6315 {
6316 int cdclk, vco;
6317
6318 skl_sanitize_cdclk(dev_priv);
6319
6320 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6321 /*
6322 * Use the current vco as our initial
6323 * guess as to what the preferred vco is.
6324 */
6325 if (dev_priv->skl_preferred_vco_freq == 0)
6326 skl_set_preferred_cdclk_vco(dev_priv,
6327 dev_priv->cdclk_pll.vco);
6328 return;
6329 }
6330
6331 vco = dev_priv->skl_preferred_vco_freq;
6332 if (vco == 0)
6333 vco = 8100000;
6334 cdclk = skl_calc_cdclk(0, vco);
6335
6336 skl_set_cdclk(dev_priv, cdclk, vco);
6337 }
6338
6339 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6340 {
6341 uint32_t cdctl, expected;
6342
6343 /*
6344 * check if the pre-os intialized the display
6345 * There is SWF18 scratchpad register defined which is set by the
6346 * pre-os which can be used by the OS drivers to check the status
6347 */
6348 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6349 goto sanitize;
6350
6351 intel_update_cdclk(dev_priv);
6352 /* Is PLL enabled and locked ? */
6353 if (dev_priv->cdclk_pll.vco == 0 ||
6354 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6355 goto sanitize;
6356
6357 /* DPLL okay; verify the cdclock
6358 *
6359 * Noticed in some instances that the freq selection is correct but
6360 * decimal part is programmed wrong from BIOS where pre-os does not
6361 * enable display. Verify the same as well.
6362 */
6363 cdctl = I915_READ(CDCLK_CTL);
6364 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6365 skl_cdclk_decimal(dev_priv->cdclk_freq);
6366 if (cdctl == expected)
6367 /* All well; nothing to sanitize */
6368 return;
6369
6370 sanitize:
6371 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6372
6373 /* force cdclk programming */
6374 dev_priv->cdclk_freq = 0;
6375 /* force full PLL disable + enable */
6376 dev_priv->cdclk_pll.vco = -1;
6377 }
6378
6379 /* Adjust CDclk dividers to allow high res or save power if possible */
6380 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6381 {
6382 struct drm_i915_private *dev_priv = to_i915(dev);
6383 u32 val, cmd;
6384
6385 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6386 != dev_priv->cdclk_freq);
6387
6388 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6389 cmd = 2;
6390 else if (cdclk == 266667)
6391 cmd = 1;
6392 else
6393 cmd = 0;
6394
6395 mutex_lock(&dev_priv->rps.hw_lock);
6396 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6397 val &= ~DSPFREQGUAR_MASK;
6398 val |= (cmd << DSPFREQGUAR_SHIFT);
6399 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6400 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6401 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6402 50)) {
6403 DRM_ERROR("timed out waiting for CDclk change\n");
6404 }
6405 mutex_unlock(&dev_priv->rps.hw_lock);
6406
6407 mutex_lock(&dev_priv->sb_lock);
6408
6409 if (cdclk == 400000) {
6410 u32 divider;
6411
6412 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6413
6414 /* adjust cdclk divider */
6415 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6416 val &= ~CCK_FREQUENCY_VALUES;
6417 val |= divider;
6418 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6419
6420 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6421 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6422 50))
6423 DRM_ERROR("timed out waiting for CDclk change\n");
6424 }
6425
6426 /* adjust self-refresh exit latency value */
6427 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6428 val &= ~0x7f;
6429
6430 /*
6431 * For high bandwidth configs, we set a higher latency in the bunit
6432 * so that the core display fetch happens in time to avoid underruns.
6433 */
6434 if (cdclk == 400000)
6435 val |= 4500 / 250; /* 4.5 usec */
6436 else
6437 val |= 3000 / 250; /* 3.0 usec */
6438 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6439
6440 mutex_unlock(&dev_priv->sb_lock);
6441
6442 intel_update_cdclk(dev_priv);
6443 }
6444
6445 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6446 {
6447 struct drm_i915_private *dev_priv = to_i915(dev);
6448 u32 val, cmd;
6449
6450 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6451 != dev_priv->cdclk_freq);
6452
6453 switch (cdclk) {
6454 case 333333:
6455 case 320000:
6456 case 266667:
6457 case 200000:
6458 break;
6459 default:
6460 MISSING_CASE(cdclk);
6461 return;
6462 }
6463
6464 /*
6465 * Specs are full of misinformation, but testing on actual
6466 * hardware has shown that we just need to write the desired
6467 * CCK divider into the Punit register.
6468 */
6469 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6470
6471 mutex_lock(&dev_priv->rps.hw_lock);
6472 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6473 val &= ~DSPFREQGUAR_MASK_CHV;
6474 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6475 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6476 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6477 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6478 50)) {
6479 DRM_ERROR("timed out waiting for CDclk change\n");
6480 }
6481 mutex_unlock(&dev_priv->rps.hw_lock);
6482
6483 intel_update_cdclk(dev_priv);
6484 }
6485
6486 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6487 int max_pixclk)
6488 {
6489 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6490 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6491
6492 /*
6493 * Really only a few cases to deal with, as only 4 CDclks are supported:
6494 * 200MHz
6495 * 267MHz
6496 * 320/333MHz (depends on HPLL freq)
6497 * 400MHz (VLV only)
6498 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6499 * of the lower bin and adjust if needed.
6500 *
6501 * We seem to get an unstable or solid color picture at 200MHz.
6502 * Not sure what's wrong. For now use 200MHz only when all pipes
6503 * are off.
6504 */
6505 if (!IS_CHERRYVIEW(dev_priv) &&
6506 max_pixclk > freq_320*limit/100)
6507 return 400000;
6508 else if (max_pixclk > 266667*limit/100)
6509 return freq_320;
6510 else if (max_pixclk > 0)
6511 return 266667;
6512 else
6513 return 200000;
6514 }
6515
6516 static int bxt_calc_cdclk(int max_pixclk)
6517 {
6518 if (max_pixclk > 576000)
6519 return 624000;
6520 else if (max_pixclk > 384000)
6521 return 576000;
6522 else if (max_pixclk > 288000)
6523 return 384000;
6524 else if (max_pixclk > 144000)
6525 return 288000;
6526 else
6527 return 144000;
6528 }
6529
6530 /* Compute the max pixel clock for new configuration. */
6531 static int intel_mode_max_pixclk(struct drm_device *dev,
6532 struct drm_atomic_state *state)
6533 {
6534 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6535 struct drm_i915_private *dev_priv = to_i915(dev);
6536 struct drm_crtc *crtc;
6537 struct drm_crtc_state *crtc_state;
6538 unsigned max_pixclk = 0, i;
6539 enum pipe pipe;
6540
6541 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6542 sizeof(intel_state->min_pixclk));
6543
6544 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6545 int pixclk = 0;
6546
6547 if (crtc_state->enable)
6548 pixclk = crtc_state->adjusted_mode.crtc_clock;
6549
6550 intel_state->min_pixclk[i] = pixclk;
6551 }
6552
6553 for_each_pipe(dev_priv, pipe)
6554 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6555
6556 return max_pixclk;
6557 }
6558
6559 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6560 {
6561 struct drm_device *dev = state->dev;
6562 struct drm_i915_private *dev_priv = to_i915(dev);
6563 int max_pixclk = intel_mode_max_pixclk(dev, state);
6564 struct intel_atomic_state *intel_state =
6565 to_intel_atomic_state(state);
6566
6567 intel_state->cdclk = intel_state->dev_cdclk =
6568 valleyview_calc_cdclk(dev_priv, max_pixclk);
6569
6570 if (!intel_state->active_crtcs)
6571 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6572
6573 return 0;
6574 }
6575
6576 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6577 {
6578 int max_pixclk = ilk_max_pixel_rate(state);
6579 struct intel_atomic_state *intel_state =
6580 to_intel_atomic_state(state);
6581
6582 intel_state->cdclk = intel_state->dev_cdclk =
6583 bxt_calc_cdclk(max_pixclk);
6584
6585 if (!intel_state->active_crtcs)
6586 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6587
6588 return 0;
6589 }
6590
6591 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6592 {
6593 unsigned int credits, default_credits;
6594
6595 if (IS_CHERRYVIEW(dev_priv))
6596 default_credits = PFI_CREDIT(12);
6597 else
6598 default_credits = PFI_CREDIT(8);
6599
6600 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6601 /* CHV suggested value is 31 or 63 */
6602 if (IS_CHERRYVIEW(dev_priv))
6603 credits = PFI_CREDIT_63;
6604 else
6605 credits = PFI_CREDIT(15);
6606 } else {
6607 credits = default_credits;
6608 }
6609
6610 /*
6611 * WA - write default credits before re-programming
6612 * FIXME: should we also set the resend bit here?
6613 */
6614 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6615 default_credits);
6616
6617 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6618 credits | PFI_CREDIT_RESEND);
6619
6620 /*
6621 * FIXME is this guaranteed to clear
6622 * immediately or should we poll for it?
6623 */
6624 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6625 }
6626
6627 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6628 {
6629 struct drm_device *dev = old_state->dev;
6630 struct drm_i915_private *dev_priv = to_i915(dev);
6631 struct intel_atomic_state *old_intel_state =
6632 to_intel_atomic_state(old_state);
6633 unsigned req_cdclk = old_intel_state->dev_cdclk;
6634
6635 /*
6636 * FIXME: We can end up here with all power domains off, yet
6637 * with a CDCLK frequency other than the minimum. To account
6638 * for this take the PIPE-A power domain, which covers the HW
6639 * blocks needed for the following programming. This can be
6640 * removed once it's guaranteed that we get here either with
6641 * the minimum CDCLK set, or the required power domains
6642 * enabled.
6643 */
6644 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6645
6646 if (IS_CHERRYVIEW(dev_priv))
6647 cherryview_set_cdclk(dev, req_cdclk);
6648 else
6649 valleyview_set_cdclk(dev, req_cdclk);
6650
6651 vlv_program_pfi_credits(dev_priv);
6652
6653 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6654 }
6655
6656 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6657 struct drm_atomic_state *old_state)
6658 {
6659 struct drm_crtc *crtc = pipe_config->base.crtc;
6660 struct drm_device *dev = crtc->dev;
6661 struct drm_i915_private *dev_priv = to_i915(dev);
6662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663 int pipe = intel_crtc->pipe;
6664
6665 if (WARN_ON(intel_crtc->active))
6666 return;
6667
6668 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6669 intel_dp_set_m_n(intel_crtc, M1_N1);
6670
6671 intel_set_pipe_timings(intel_crtc);
6672 intel_set_pipe_src_size(intel_crtc);
6673
6674 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6675 struct drm_i915_private *dev_priv = to_i915(dev);
6676
6677 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6678 I915_WRITE(CHV_CANVAS(pipe), 0);
6679 }
6680
6681 i9xx_set_pipeconf(intel_crtc);
6682
6683 intel_crtc->active = true;
6684
6685 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6686
6687 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6688
6689 if (IS_CHERRYVIEW(dev_priv)) {
6690 chv_prepare_pll(intel_crtc, intel_crtc->config);
6691 chv_enable_pll(intel_crtc, intel_crtc->config);
6692 } else {
6693 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6694 vlv_enable_pll(intel_crtc, intel_crtc->config);
6695 }
6696
6697 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6698
6699 i9xx_pfit_enable(intel_crtc);
6700
6701 intel_color_load_luts(&pipe_config->base);
6702
6703 intel_update_watermarks(intel_crtc);
6704 intel_enable_pipe(intel_crtc);
6705
6706 assert_vblank_disabled(crtc);
6707 drm_crtc_vblank_on(crtc);
6708
6709 intel_encoders_enable(crtc, pipe_config, old_state);
6710 }
6711
6712 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6713 {
6714 struct drm_device *dev = crtc->base.dev;
6715 struct drm_i915_private *dev_priv = to_i915(dev);
6716
6717 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6718 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6719 }
6720
6721 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6722 struct drm_atomic_state *old_state)
6723 {
6724 struct drm_crtc *crtc = pipe_config->base.crtc;
6725 struct drm_device *dev = crtc->dev;
6726 struct drm_i915_private *dev_priv = to_i915(dev);
6727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6728 enum pipe pipe = intel_crtc->pipe;
6729
6730 if (WARN_ON(intel_crtc->active))
6731 return;
6732
6733 i9xx_set_pll_dividers(intel_crtc);
6734
6735 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6736 intel_dp_set_m_n(intel_crtc, M1_N1);
6737
6738 intel_set_pipe_timings(intel_crtc);
6739 intel_set_pipe_src_size(intel_crtc);
6740
6741 i9xx_set_pipeconf(intel_crtc);
6742
6743 intel_crtc->active = true;
6744
6745 if (!IS_GEN2(dev_priv))
6746 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6747
6748 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6749
6750 i9xx_enable_pll(intel_crtc);
6751
6752 i9xx_pfit_enable(intel_crtc);
6753
6754 intel_color_load_luts(&pipe_config->base);
6755
6756 intel_update_watermarks(intel_crtc);
6757 intel_enable_pipe(intel_crtc);
6758
6759 assert_vblank_disabled(crtc);
6760 drm_crtc_vblank_on(crtc);
6761
6762 intel_encoders_enable(crtc, pipe_config, old_state);
6763 }
6764
6765 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6766 {
6767 struct drm_device *dev = crtc->base.dev;
6768 struct drm_i915_private *dev_priv = to_i915(dev);
6769
6770 if (!crtc->config->gmch_pfit.control)
6771 return;
6772
6773 assert_pipe_disabled(dev_priv, crtc->pipe);
6774
6775 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6776 I915_READ(PFIT_CONTROL));
6777 I915_WRITE(PFIT_CONTROL, 0);
6778 }
6779
6780 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6781 struct drm_atomic_state *old_state)
6782 {
6783 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6784 struct drm_device *dev = crtc->dev;
6785 struct drm_i915_private *dev_priv = to_i915(dev);
6786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6787 int pipe = intel_crtc->pipe;
6788
6789 /*
6790 * On gen2 planes are double buffered but the pipe isn't, so we must
6791 * wait for planes to fully turn off before disabling the pipe.
6792 */
6793 if (IS_GEN2(dev_priv))
6794 intel_wait_for_vblank(dev_priv, pipe);
6795
6796 intel_encoders_disable(crtc, old_crtc_state, old_state);
6797
6798 drm_crtc_vblank_off(crtc);
6799 assert_vblank_disabled(crtc);
6800
6801 intel_disable_pipe(intel_crtc);
6802
6803 i9xx_pfit_disable(intel_crtc);
6804
6805 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6806
6807 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6808 if (IS_CHERRYVIEW(dev_priv))
6809 chv_disable_pll(dev_priv, pipe);
6810 else if (IS_VALLEYVIEW(dev_priv))
6811 vlv_disable_pll(dev_priv, pipe);
6812 else
6813 i9xx_disable_pll(intel_crtc);
6814 }
6815
6816 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6817
6818 if (!IS_GEN2(dev_priv))
6819 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6820 }
6821
6822 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6823 {
6824 struct intel_encoder *encoder;
6825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6826 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6827 enum intel_display_power_domain domain;
6828 unsigned long domains;
6829 struct drm_atomic_state *state;
6830 struct intel_crtc_state *crtc_state;
6831 int ret;
6832
6833 if (!intel_crtc->active)
6834 return;
6835
6836 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6837 WARN_ON(intel_crtc->flip_work);
6838
6839 intel_pre_disable_primary_noatomic(crtc);
6840
6841 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6842 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6843 }
6844
6845 state = drm_atomic_state_alloc(crtc->dev);
6846 if (!state) {
6847 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6848 crtc->base.id, crtc->name);
6849 return;
6850 }
6851
6852 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6853
6854 /* Everything's already locked, -EDEADLK can't happen. */
6855 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6856 ret = drm_atomic_add_affected_connectors(state, crtc);
6857
6858 WARN_ON(IS_ERR(crtc_state) || ret);
6859
6860 dev_priv->display.crtc_disable(crtc_state, state);
6861
6862 drm_atomic_state_put(state);
6863
6864 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6865 crtc->base.id, crtc->name);
6866
6867 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6868 crtc->state->active = false;
6869 intel_crtc->active = false;
6870 crtc->enabled = false;
6871 crtc->state->connector_mask = 0;
6872 crtc->state->encoder_mask = 0;
6873
6874 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6875 encoder->base.crtc = NULL;
6876
6877 intel_fbc_disable(intel_crtc);
6878 intel_update_watermarks(intel_crtc);
6879 intel_disable_shared_dpll(intel_crtc);
6880
6881 domains = intel_crtc->enabled_power_domains;
6882 for_each_power_domain(domain, domains)
6883 intel_display_power_put(dev_priv, domain);
6884 intel_crtc->enabled_power_domains = 0;
6885
6886 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6887 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6888 }
6889
6890 /*
6891 * turn all crtc's off, but do not adjust state
6892 * This has to be paired with a call to intel_modeset_setup_hw_state.
6893 */
6894 int intel_display_suspend(struct drm_device *dev)
6895 {
6896 struct drm_i915_private *dev_priv = to_i915(dev);
6897 struct drm_atomic_state *state;
6898 int ret;
6899
6900 state = drm_atomic_helper_suspend(dev);
6901 ret = PTR_ERR_OR_ZERO(state);
6902 if (ret)
6903 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6904 else
6905 dev_priv->modeset_restore_state = state;
6906 return ret;
6907 }
6908
6909 void intel_encoder_destroy(struct drm_encoder *encoder)
6910 {
6911 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6912
6913 drm_encoder_cleanup(encoder);
6914 kfree(intel_encoder);
6915 }
6916
6917 /* Cross check the actual hw state with our own modeset state tracking (and it's
6918 * internal consistency). */
6919 static void intel_connector_verify_state(struct intel_connector *connector)
6920 {
6921 struct drm_crtc *crtc = connector->base.state->crtc;
6922
6923 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6924 connector->base.base.id,
6925 connector->base.name);
6926
6927 if (connector->get_hw_state(connector)) {
6928 struct intel_encoder *encoder = connector->encoder;
6929 struct drm_connector_state *conn_state = connector->base.state;
6930
6931 I915_STATE_WARN(!crtc,
6932 "connector enabled without attached crtc\n");
6933
6934 if (!crtc)
6935 return;
6936
6937 I915_STATE_WARN(!crtc->state->active,
6938 "connector is active, but attached crtc isn't\n");
6939
6940 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6941 return;
6942
6943 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6944 "atomic encoder doesn't match attached encoder\n");
6945
6946 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6947 "attached encoder crtc differs from connector crtc\n");
6948 } else {
6949 I915_STATE_WARN(crtc && crtc->state->active,
6950 "attached crtc is active, but connector isn't\n");
6951 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6952 "best encoder set without crtc!\n");
6953 }
6954 }
6955
6956 int intel_connector_init(struct intel_connector *connector)
6957 {
6958 drm_atomic_helper_connector_reset(&connector->base);
6959
6960 if (!connector->base.state)
6961 return -ENOMEM;
6962
6963 return 0;
6964 }
6965
6966 struct intel_connector *intel_connector_alloc(void)
6967 {
6968 struct intel_connector *connector;
6969
6970 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6971 if (!connector)
6972 return NULL;
6973
6974 if (intel_connector_init(connector) < 0) {
6975 kfree(connector);
6976 return NULL;
6977 }
6978
6979 return connector;
6980 }
6981
6982 /* Simple connector->get_hw_state implementation for encoders that support only
6983 * one connector and no cloning and hence the encoder state determines the state
6984 * of the connector. */
6985 bool intel_connector_get_hw_state(struct intel_connector *connector)
6986 {
6987 enum pipe pipe = 0;
6988 struct intel_encoder *encoder = connector->encoder;
6989
6990 return encoder->get_hw_state(encoder, &pipe);
6991 }
6992
6993 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6994 {
6995 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6996 return crtc_state->fdi_lanes;
6997
6998 return 0;
6999 }
7000
7001 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7002 struct intel_crtc_state *pipe_config)
7003 {
7004 struct drm_i915_private *dev_priv = to_i915(dev);
7005 struct drm_atomic_state *state = pipe_config->base.state;
7006 struct intel_crtc *other_crtc;
7007 struct intel_crtc_state *other_crtc_state;
7008
7009 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7010 pipe_name(pipe), pipe_config->fdi_lanes);
7011 if (pipe_config->fdi_lanes > 4) {
7012 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7013 pipe_name(pipe), pipe_config->fdi_lanes);
7014 return -EINVAL;
7015 }
7016
7017 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7018 if (pipe_config->fdi_lanes > 2) {
7019 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7020 pipe_config->fdi_lanes);
7021 return -EINVAL;
7022 } else {
7023 return 0;
7024 }
7025 }
7026
7027 if (INTEL_INFO(dev_priv)->num_pipes == 2)
7028 return 0;
7029
7030 /* Ivybridge 3 pipe is really complicated */
7031 switch (pipe) {
7032 case PIPE_A:
7033 return 0;
7034 case PIPE_B:
7035 if (pipe_config->fdi_lanes <= 2)
7036 return 0;
7037
7038 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7039 other_crtc_state =
7040 intel_atomic_get_crtc_state(state, other_crtc);
7041 if (IS_ERR(other_crtc_state))
7042 return PTR_ERR(other_crtc_state);
7043
7044 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7045 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7046 pipe_name(pipe), pipe_config->fdi_lanes);
7047 return -EINVAL;
7048 }
7049 return 0;
7050 case PIPE_C:
7051 if (pipe_config->fdi_lanes > 2) {
7052 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7053 pipe_name(pipe), pipe_config->fdi_lanes);
7054 return -EINVAL;
7055 }
7056
7057 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7058 other_crtc_state =
7059 intel_atomic_get_crtc_state(state, other_crtc);
7060 if (IS_ERR(other_crtc_state))
7061 return PTR_ERR(other_crtc_state);
7062
7063 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7064 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7065 return -EINVAL;
7066 }
7067 return 0;
7068 default:
7069 BUG();
7070 }
7071 }
7072
7073 #define RETRY 1
7074 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7075 struct intel_crtc_state *pipe_config)
7076 {
7077 struct drm_device *dev = intel_crtc->base.dev;
7078 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7079 int lane, link_bw, fdi_dotclock, ret;
7080 bool needs_recompute = false;
7081
7082 retry:
7083 /* FDI is a binary signal running at ~2.7GHz, encoding
7084 * each output octet as 10 bits. The actual frequency
7085 * is stored as a divider into a 100MHz clock, and the
7086 * mode pixel clock is stored in units of 1KHz.
7087 * Hence the bw of each lane in terms of the mode signal
7088 * is:
7089 */
7090 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7091
7092 fdi_dotclock = adjusted_mode->crtc_clock;
7093
7094 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7095 pipe_config->pipe_bpp);
7096
7097 pipe_config->fdi_lanes = lane;
7098
7099 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7100 link_bw, &pipe_config->fdi_m_n);
7101
7102 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7103 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7104 pipe_config->pipe_bpp -= 2*3;
7105 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7106 pipe_config->pipe_bpp);
7107 needs_recompute = true;
7108 pipe_config->bw_constrained = true;
7109
7110 goto retry;
7111 }
7112
7113 if (needs_recompute)
7114 return RETRY;
7115
7116 return ret;
7117 }
7118
7119 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7120 struct intel_crtc_state *pipe_config)
7121 {
7122 if (pipe_config->pipe_bpp > 24)
7123 return false;
7124
7125 /* HSW can handle pixel rate up to cdclk? */
7126 if (IS_HASWELL(dev_priv))
7127 return true;
7128
7129 /*
7130 * We compare against max which means we must take
7131 * the increased cdclk requirement into account when
7132 * calculating the new cdclk.
7133 *
7134 * Should measure whether using a lower cdclk w/o IPS
7135 */
7136 return ilk_pipe_pixel_rate(pipe_config) <=
7137 dev_priv->max_cdclk_freq * 95 / 100;
7138 }
7139
7140 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7141 struct intel_crtc_state *pipe_config)
7142 {
7143 struct drm_device *dev = crtc->base.dev;
7144 struct drm_i915_private *dev_priv = to_i915(dev);
7145
7146 pipe_config->ips_enabled = i915.enable_ips &&
7147 hsw_crtc_supports_ips(crtc) &&
7148 pipe_config_supports_ips(dev_priv, pipe_config);
7149 }
7150
7151 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7152 {
7153 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7154
7155 /* GDG double wide on either pipe, otherwise pipe A only */
7156 return INTEL_INFO(dev_priv)->gen < 4 &&
7157 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7158 }
7159
7160 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7161 struct intel_crtc_state *pipe_config)
7162 {
7163 struct drm_device *dev = crtc->base.dev;
7164 struct drm_i915_private *dev_priv = to_i915(dev);
7165 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7166 int clock_limit = dev_priv->max_dotclk_freq;
7167
7168 if (INTEL_GEN(dev_priv) < 4) {
7169 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7170
7171 /*
7172 * Enable double wide mode when the dot clock
7173 * is > 90% of the (display) core speed.
7174 */
7175 if (intel_crtc_supports_double_wide(crtc) &&
7176 adjusted_mode->crtc_clock > clock_limit) {
7177 clock_limit = dev_priv->max_dotclk_freq;
7178 pipe_config->double_wide = true;
7179 }
7180 }
7181
7182 if (adjusted_mode->crtc_clock > clock_limit) {
7183 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7184 adjusted_mode->crtc_clock, clock_limit,
7185 yesno(pipe_config->double_wide));
7186 return -EINVAL;
7187 }
7188
7189 /*
7190 * Pipe horizontal size must be even in:
7191 * - DVO ganged mode
7192 * - LVDS dual channel mode
7193 * - Double wide pipe
7194 */
7195 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7196 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7197 pipe_config->pipe_src_w &= ~1;
7198
7199 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7200 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7201 */
7202 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7203 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7204 return -EINVAL;
7205
7206 if (HAS_IPS(dev_priv))
7207 hsw_compute_ips_config(crtc, pipe_config);
7208
7209 if (pipe_config->has_pch_encoder)
7210 return ironlake_fdi_compute_config(crtc, pipe_config);
7211
7212 return 0;
7213 }
7214
7215 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7216 {
7217 u32 cdctl;
7218
7219 skl_dpll0_update(dev_priv);
7220
7221 if (dev_priv->cdclk_pll.vco == 0)
7222 return dev_priv->cdclk_pll.ref;
7223
7224 cdctl = I915_READ(CDCLK_CTL);
7225
7226 if (dev_priv->cdclk_pll.vco == 8640000) {
7227 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7228 case CDCLK_FREQ_450_432:
7229 return 432000;
7230 case CDCLK_FREQ_337_308:
7231 return 308571;
7232 case CDCLK_FREQ_540:
7233 return 540000;
7234 case CDCLK_FREQ_675_617:
7235 return 617143;
7236 default:
7237 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7238 }
7239 } else {
7240 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7241 case CDCLK_FREQ_450_432:
7242 return 450000;
7243 case CDCLK_FREQ_337_308:
7244 return 337500;
7245 case CDCLK_FREQ_540:
7246 return 540000;
7247 case CDCLK_FREQ_675_617:
7248 return 675000;
7249 default:
7250 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7251 }
7252 }
7253
7254 return dev_priv->cdclk_pll.ref;
7255 }
7256
7257 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7258 {
7259 u32 val;
7260
7261 dev_priv->cdclk_pll.ref = 19200;
7262 dev_priv->cdclk_pll.vco = 0;
7263
7264 val = I915_READ(BXT_DE_PLL_ENABLE);
7265 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7266 return;
7267
7268 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7269 return;
7270
7271 val = I915_READ(BXT_DE_PLL_CTL);
7272 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7273 dev_priv->cdclk_pll.ref;
7274 }
7275
7276 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7277 {
7278 u32 divider;
7279 int div, vco;
7280
7281 bxt_de_pll_update(dev_priv);
7282
7283 vco = dev_priv->cdclk_pll.vco;
7284 if (vco == 0)
7285 return dev_priv->cdclk_pll.ref;
7286
7287 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7288
7289 switch (divider) {
7290 case BXT_CDCLK_CD2X_DIV_SEL_1:
7291 div = 2;
7292 break;
7293 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7294 div = 3;
7295 break;
7296 case BXT_CDCLK_CD2X_DIV_SEL_2:
7297 div = 4;
7298 break;
7299 case BXT_CDCLK_CD2X_DIV_SEL_4:
7300 div = 8;
7301 break;
7302 default:
7303 MISSING_CASE(divider);
7304 return dev_priv->cdclk_pll.ref;
7305 }
7306
7307 return DIV_ROUND_CLOSEST(vco, div);
7308 }
7309
7310 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7311 {
7312 uint32_t lcpll = I915_READ(LCPLL_CTL);
7313 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7314
7315 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7316 return 800000;
7317 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7318 return 450000;
7319 else if (freq == LCPLL_CLK_FREQ_450)
7320 return 450000;
7321 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7322 return 540000;
7323 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7324 return 337500;
7325 else
7326 return 675000;
7327 }
7328
7329 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7330 {
7331 uint32_t lcpll = I915_READ(LCPLL_CTL);
7332 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7333
7334 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7335 return 800000;
7336 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7337 return 450000;
7338 else if (freq == LCPLL_CLK_FREQ_450)
7339 return 450000;
7340 else if (IS_HSW_ULT(dev_priv))
7341 return 337500;
7342 else
7343 return 540000;
7344 }
7345
7346 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7347 {
7348 return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
7349 CCK_DISPLAY_CLOCK_CONTROL);
7350 }
7351
7352 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7353 {
7354 return 450000;
7355 }
7356
7357 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7358 {
7359 return 400000;
7360 }
7361
7362 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7363 {
7364 return 333333;
7365 }
7366
7367 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7368 {
7369 return 200000;
7370 }
7371
7372 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7373 {
7374 struct pci_dev *pdev = dev_priv->drm.pdev;
7375 u16 gcfgc = 0;
7376
7377 pci_read_config_word(pdev, GCFGC, &gcfgc);
7378
7379 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7380 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7381 return 266667;
7382 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7383 return 333333;
7384 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7385 return 444444;
7386 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7387 return 200000;
7388 default:
7389 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7390 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7391 return 133333;
7392 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7393 return 166667;
7394 }
7395 }
7396
7397 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7398 {
7399 struct pci_dev *pdev = dev_priv->drm.pdev;
7400 u16 gcfgc = 0;
7401
7402 pci_read_config_word(pdev, GCFGC, &gcfgc);
7403
7404 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7405 return 133333;
7406 else {
7407 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7408 case GC_DISPLAY_CLOCK_333_MHZ:
7409 return 333333;
7410 default:
7411 case GC_DISPLAY_CLOCK_190_200_MHZ:
7412 return 190000;
7413 }
7414 }
7415 }
7416
7417 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7418 {
7419 return 266667;
7420 }
7421
7422 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7423 {
7424 struct pci_dev *pdev = dev_priv->drm.pdev;
7425 u16 hpllcc = 0;
7426
7427 /*
7428 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7429 * encoding is different :(
7430 * FIXME is this the right way to detect 852GM/852GMV?
7431 */
7432 if (pdev->revision == 0x1)
7433 return 133333;
7434
7435 pci_bus_read_config_word(pdev->bus,
7436 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7437
7438 /* Assume that the hardware is in the high speed state. This
7439 * should be the default.
7440 */
7441 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7442 case GC_CLOCK_133_200:
7443 case GC_CLOCK_133_200_2:
7444 case GC_CLOCK_100_200:
7445 return 200000;
7446 case GC_CLOCK_166_250:
7447 return 250000;
7448 case GC_CLOCK_100_133:
7449 return 133333;
7450 case GC_CLOCK_133_266:
7451 case GC_CLOCK_133_266_2:
7452 case GC_CLOCK_166_266:
7453 return 266667;
7454 }
7455
7456 /* Shouldn't happen */
7457 return 0;
7458 }
7459
7460 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7461 {
7462 return 133333;
7463 }
7464
7465 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
7466 {
7467 static const unsigned int blb_vco[8] = {
7468 [0] = 3200000,
7469 [1] = 4000000,
7470 [2] = 5333333,
7471 [3] = 4800000,
7472 [4] = 6400000,
7473 };
7474 static const unsigned int pnv_vco[8] = {
7475 [0] = 3200000,
7476 [1] = 4000000,
7477 [2] = 5333333,
7478 [3] = 4800000,
7479 [4] = 2666667,
7480 };
7481 static const unsigned int cl_vco[8] = {
7482 [0] = 3200000,
7483 [1] = 4000000,
7484 [2] = 5333333,
7485 [3] = 6400000,
7486 [4] = 3333333,
7487 [5] = 3566667,
7488 [6] = 4266667,
7489 };
7490 static const unsigned int elk_vco[8] = {
7491 [0] = 3200000,
7492 [1] = 4000000,
7493 [2] = 5333333,
7494 [3] = 4800000,
7495 };
7496 static const unsigned int ctg_vco[8] = {
7497 [0] = 3200000,
7498 [1] = 4000000,
7499 [2] = 5333333,
7500 [3] = 6400000,
7501 [4] = 2666667,
7502 [5] = 4266667,
7503 };
7504 const unsigned int *vco_table;
7505 unsigned int vco;
7506 uint8_t tmp = 0;
7507
7508 /* FIXME other chipsets? */
7509 if (IS_GM45(dev_priv))
7510 vco_table = ctg_vco;
7511 else if (IS_G4X(dev_priv))
7512 vco_table = elk_vco;
7513 else if (IS_CRESTLINE(dev_priv))
7514 vco_table = cl_vco;
7515 else if (IS_PINEVIEW(dev_priv))
7516 vco_table = pnv_vco;
7517 else if (IS_G33(dev_priv))
7518 vco_table = blb_vco;
7519 else
7520 return 0;
7521
7522 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7523
7524 vco = vco_table[tmp & 0x7];
7525 if (vco == 0)
7526 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7527 else
7528 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7529
7530 return vco;
7531 }
7532
7533 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7534 {
7535 struct pci_dev *pdev = dev_priv->drm.pdev;
7536 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7537 uint16_t tmp = 0;
7538
7539 pci_read_config_word(pdev, GCFGC, &tmp);
7540
7541 cdclk_sel = (tmp >> 12) & 0x1;
7542
7543 switch (vco) {
7544 case 2666667:
7545 case 4000000:
7546 case 5333333:
7547 return cdclk_sel ? 333333 : 222222;
7548 case 3200000:
7549 return cdclk_sel ? 320000 : 228571;
7550 default:
7551 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7552 return 222222;
7553 }
7554 }
7555
7556 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7557 {
7558 struct pci_dev *pdev = dev_priv->drm.pdev;
7559 static const uint8_t div_3200[] = { 16, 10, 8 };
7560 static const uint8_t div_4000[] = { 20, 12, 10 };
7561 static const uint8_t div_5333[] = { 24, 16, 14 };
7562 const uint8_t *div_table;
7563 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7564 uint16_t tmp = 0;
7565
7566 pci_read_config_word(pdev, GCFGC, &tmp);
7567
7568 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7569
7570 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7571 goto fail;
7572
7573 switch (vco) {
7574 case 3200000:
7575 div_table = div_3200;
7576 break;
7577 case 4000000:
7578 div_table = div_4000;
7579 break;
7580 case 5333333:
7581 div_table = div_5333;
7582 break;
7583 default:
7584 goto fail;
7585 }
7586
7587 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7588
7589 fail:
7590 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7591 return 200000;
7592 }
7593
7594 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7595 {
7596 struct pci_dev *pdev = dev_priv->drm.pdev;
7597 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7598 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7599 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7600 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7601 const uint8_t *div_table;
7602 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
7603 uint16_t tmp = 0;
7604
7605 pci_read_config_word(pdev, GCFGC, &tmp);
7606
7607 cdclk_sel = (tmp >> 4) & 0x7;
7608
7609 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7610 goto fail;
7611
7612 switch (vco) {
7613 case 3200000:
7614 div_table = div_3200;
7615 break;
7616 case 4000000:
7617 div_table = div_4000;
7618 break;
7619 case 4800000:
7620 div_table = div_4800;
7621 break;
7622 case 5333333:
7623 div_table = div_5333;
7624 break;
7625 default:
7626 goto fail;
7627 }
7628
7629 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7630
7631 fail:
7632 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7633 return 190476;
7634 }
7635
7636 static void
7637 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7638 {
7639 while (*num > DATA_LINK_M_N_MASK ||
7640 *den > DATA_LINK_M_N_MASK) {
7641 *num >>= 1;
7642 *den >>= 1;
7643 }
7644 }
7645
7646 static void compute_m_n(unsigned int m, unsigned int n,
7647 uint32_t *ret_m, uint32_t *ret_n)
7648 {
7649 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7650 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7651 intel_reduce_m_n_ratio(ret_m, ret_n);
7652 }
7653
7654 void
7655 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7656 int pixel_clock, int link_clock,
7657 struct intel_link_m_n *m_n)
7658 {
7659 m_n->tu = 64;
7660
7661 compute_m_n(bits_per_pixel * pixel_clock,
7662 link_clock * nlanes * 8,
7663 &m_n->gmch_m, &m_n->gmch_n);
7664
7665 compute_m_n(pixel_clock, link_clock,
7666 &m_n->link_m, &m_n->link_n);
7667 }
7668
7669 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7670 {
7671 if (i915.panel_use_ssc >= 0)
7672 return i915.panel_use_ssc != 0;
7673 return dev_priv->vbt.lvds_use_ssc
7674 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7675 }
7676
7677 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7678 {
7679 return (1 << dpll->n) << 16 | dpll->m2;
7680 }
7681
7682 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7683 {
7684 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7685 }
7686
7687 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7688 struct intel_crtc_state *crtc_state,
7689 struct dpll *reduced_clock)
7690 {
7691 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7692 u32 fp, fp2 = 0;
7693
7694 if (IS_PINEVIEW(dev_priv)) {
7695 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7696 if (reduced_clock)
7697 fp2 = pnv_dpll_compute_fp(reduced_clock);
7698 } else {
7699 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7700 if (reduced_clock)
7701 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7702 }
7703
7704 crtc_state->dpll_hw_state.fp0 = fp;
7705
7706 crtc->lowfreq_avail = false;
7707 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7708 reduced_clock) {
7709 crtc_state->dpll_hw_state.fp1 = fp2;
7710 crtc->lowfreq_avail = true;
7711 } else {
7712 crtc_state->dpll_hw_state.fp1 = fp;
7713 }
7714 }
7715
7716 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7717 pipe)
7718 {
7719 u32 reg_val;
7720
7721 /*
7722 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7723 * and set it to a reasonable value instead.
7724 */
7725 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7726 reg_val &= 0xffffff00;
7727 reg_val |= 0x00000030;
7728 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7729
7730 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7731 reg_val &= 0x8cffffff;
7732 reg_val = 0x8c000000;
7733 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7734
7735 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7736 reg_val &= 0xffffff00;
7737 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7738
7739 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7740 reg_val &= 0x00ffffff;
7741 reg_val |= 0xb0000000;
7742 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7743 }
7744
7745 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7746 struct intel_link_m_n *m_n)
7747 {
7748 struct drm_device *dev = crtc->base.dev;
7749 struct drm_i915_private *dev_priv = to_i915(dev);
7750 int pipe = crtc->pipe;
7751
7752 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7753 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7754 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7755 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7756 }
7757
7758 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7759 struct intel_link_m_n *m_n,
7760 struct intel_link_m_n *m2_n2)
7761 {
7762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7763 int pipe = crtc->pipe;
7764 enum transcoder transcoder = crtc->config->cpu_transcoder;
7765
7766 if (INTEL_GEN(dev_priv) >= 5) {
7767 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7768 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7769 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7770 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7771 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7772 * for gen < 8) and if DRRS is supported (to make sure the
7773 * registers are not unnecessarily accessed).
7774 */
7775 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
7776 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
7777 I915_WRITE(PIPE_DATA_M2(transcoder),
7778 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7779 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7780 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7781 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7782 }
7783 } else {
7784 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7785 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7786 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7787 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7788 }
7789 }
7790
7791 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7792 {
7793 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7794
7795 if (m_n == M1_N1) {
7796 dp_m_n = &crtc->config->dp_m_n;
7797 dp_m2_n2 = &crtc->config->dp_m2_n2;
7798 } else if (m_n == M2_N2) {
7799
7800 /*
7801 * M2_N2 registers are not supported. Hence m2_n2 divider value
7802 * needs to be programmed into M1_N1.
7803 */
7804 dp_m_n = &crtc->config->dp_m2_n2;
7805 } else {
7806 DRM_ERROR("Unsupported divider value\n");
7807 return;
7808 }
7809
7810 if (crtc->config->has_pch_encoder)
7811 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7812 else
7813 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7814 }
7815
7816 static void vlv_compute_dpll(struct intel_crtc *crtc,
7817 struct intel_crtc_state *pipe_config)
7818 {
7819 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7820 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7821 if (crtc->pipe != PIPE_A)
7822 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7823
7824 /* DPLL not used with DSI, but still need the rest set up */
7825 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7826 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7827 DPLL_EXT_BUFFER_ENABLE_VLV;
7828
7829 pipe_config->dpll_hw_state.dpll_md =
7830 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7831 }
7832
7833 static void chv_compute_dpll(struct intel_crtc *crtc,
7834 struct intel_crtc_state *pipe_config)
7835 {
7836 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7837 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7838 if (crtc->pipe != PIPE_A)
7839 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7840
7841 /* DPLL not used with DSI, but still need the rest set up */
7842 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7843 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7844
7845 pipe_config->dpll_hw_state.dpll_md =
7846 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7847 }
7848
7849 static void vlv_prepare_pll(struct intel_crtc *crtc,
7850 const struct intel_crtc_state *pipe_config)
7851 {
7852 struct drm_device *dev = crtc->base.dev;
7853 struct drm_i915_private *dev_priv = to_i915(dev);
7854 enum pipe pipe = crtc->pipe;
7855 u32 mdiv;
7856 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7857 u32 coreclk, reg_val;
7858
7859 /* Enable Refclk */
7860 I915_WRITE(DPLL(pipe),
7861 pipe_config->dpll_hw_state.dpll &
7862 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7863
7864 /* No need to actually set up the DPLL with DSI */
7865 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7866 return;
7867
7868 mutex_lock(&dev_priv->sb_lock);
7869
7870 bestn = pipe_config->dpll.n;
7871 bestm1 = pipe_config->dpll.m1;
7872 bestm2 = pipe_config->dpll.m2;
7873 bestp1 = pipe_config->dpll.p1;
7874 bestp2 = pipe_config->dpll.p2;
7875
7876 /* See eDP HDMI DPIO driver vbios notes doc */
7877
7878 /* PLL B needs special handling */
7879 if (pipe == PIPE_B)
7880 vlv_pllb_recal_opamp(dev_priv, pipe);
7881
7882 /* Set up Tx target for periodic Rcomp update */
7883 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7884
7885 /* Disable target IRef on PLL */
7886 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7887 reg_val &= 0x00ffffff;
7888 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7889
7890 /* Disable fast lock */
7891 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7892
7893 /* Set idtafcrecal before PLL is enabled */
7894 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7895 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7896 mdiv |= ((bestn << DPIO_N_SHIFT));
7897 mdiv |= (1 << DPIO_K_SHIFT);
7898
7899 /*
7900 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7901 * but we don't support that).
7902 * Note: don't use the DAC post divider as it seems unstable.
7903 */
7904 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7905 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7906
7907 mdiv |= DPIO_ENABLE_CALIBRATION;
7908 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7909
7910 /* Set HBR and RBR LPF coefficients */
7911 if (pipe_config->port_clock == 162000 ||
7912 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7913 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7914 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7915 0x009f0003);
7916 else
7917 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7918 0x00d0000f);
7919
7920 if (intel_crtc_has_dp_encoder(pipe_config)) {
7921 /* Use SSC source */
7922 if (pipe == PIPE_A)
7923 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7924 0x0df40000);
7925 else
7926 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7927 0x0df70000);
7928 } else { /* HDMI or VGA */
7929 /* Use bend source */
7930 if (pipe == PIPE_A)
7931 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7932 0x0df70000);
7933 else
7934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7935 0x0df40000);
7936 }
7937
7938 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7939 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7940 if (intel_crtc_has_dp_encoder(crtc->config))
7941 coreclk |= 0x01000000;
7942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7943
7944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7945 mutex_unlock(&dev_priv->sb_lock);
7946 }
7947
7948 static void chv_prepare_pll(struct intel_crtc *crtc,
7949 const struct intel_crtc_state *pipe_config)
7950 {
7951 struct drm_device *dev = crtc->base.dev;
7952 struct drm_i915_private *dev_priv = to_i915(dev);
7953 enum pipe pipe = crtc->pipe;
7954 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7955 u32 loopfilter, tribuf_calcntr;
7956 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7957 u32 dpio_val;
7958 int vco;
7959
7960 /* Enable Refclk and SSC */
7961 I915_WRITE(DPLL(pipe),
7962 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7963
7964 /* No need to actually set up the DPLL with DSI */
7965 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7966 return;
7967
7968 bestn = pipe_config->dpll.n;
7969 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7970 bestm1 = pipe_config->dpll.m1;
7971 bestm2 = pipe_config->dpll.m2 >> 22;
7972 bestp1 = pipe_config->dpll.p1;
7973 bestp2 = pipe_config->dpll.p2;
7974 vco = pipe_config->dpll.vco;
7975 dpio_val = 0;
7976 loopfilter = 0;
7977
7978 mutex_lock(&dev_priv->sb_lock);
7979
7980 /* p1 and p2 divider */
7981 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7982 5 << DPIO_CHV_S1_DIV_SHIFT |
7983 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7984 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7985 1 << DPIO_CHV_K_DIV_SHIFT);
7986
7987 /* Feedback post-divider - m2 */
7988 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7989
7990 /* Feedback refclk divider - n and m1 */
7991 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7992 DPIO_CHV_M1_DIV_BY_2 |
7993 1 << DPIO_CHV_N_DIV_SHIFT);
7994
7995 /* M2 fraction division */
7996 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7997
7998 /* M2 fraction division enable */
7999 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8000 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8001 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8002 if (bestm2_frac)
8003 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8004 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8005
8006 /* Program digital lock detect threshold */
8007 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8008 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8009 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8010 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8011 if (!bestm2_frac)
8012 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8013 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8014
8015 /* Loop filter */
8016 if (vco == 5400000) {
8017 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8018 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8019 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8020 tribuf_calcntr = 0x9;
8021 } else if (vco <= 6200000) {
8022 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8023 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8024 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8025 tribuf_calcntr = 0x9;
8026 } else if (vco <= 6480000) {
8027 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8028 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8029 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8030 tribuf_calcntr = 0x8;
8031 } else {
8032 /* Not supported. Apply the same limits as in the max case */
8033 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8034 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8035 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8036 tribuf_calcntr = 0;
8037 }
8038 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8039
8040 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8041 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8042 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8043 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8044
8045 /* AFC Recal */
8046 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8047 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8048 DPIO_AFC_RECAL);
8049
8050 mutex_unlock(&dev_priv->sb_lock);
8051 }
8052
8053 /**
8054 * vlv_force_pll_on - forcibly enable just the PLL
8055 * @dev_priv: i915 private structure
8056 * @pipe: pipe PLL to enable
8057 * @dpll: PLL configuration
8058 *
8059 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8060 * in cases where we need the PLL enabled even when @pipe is not going to
8061 * be enabled.
8062 */
8063 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8064 const struct dpll *dpll)
8065 {
8066 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8067 struct intel_crtc_state *pipe_config;
8068
8069 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8070 if (!pipe_config)
8071 return -ENOMEM;
8072
8073 pipe_config->base.crtc = &crtc->base;
8074 pipe_config->pixel_multiplier = 1;
8075 pipe_config->dpll = *dpll;
8076
8077 if (IS_CHERRYVIEW(dev_priv)) {
8078 chv_compute_dpll(crtc, pipe_config);
8079 chv_prepare_pll(crtc, pipe_config);
8080 chv_enable_pll(crtc, pipe_config);
8081 } else {
8082 vlv_compute_dpll(crtc, pipe_config);
8083 vlv_prepare_pll(crtc, pipe_config);
8084 vlv_enable_pll(crtc, pipe_config);
8085 }
8086
8087 kfree(pipe_config);
8088
8089 return 0;
8090 }
8091
8092 /**
8093 * vlv_force_pll_off - forcibly disable just the PLL
8094 * @dev_priv: i915 private structure
8095 * @pipe: pipe PLL to disable
8096 *
8097 * Disable the PLL for @pipe. To be used in cases where we need
8098 * the PLL enabled even when @pipe is not going to be enabled.
8099 */
8100 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8101 {
8102 if (IS_CHERRYVIEW(dev_priv))
8103 chv_disable_pll(dev_priv, pipe);
8104 else
8105 vlv_disable_pll(dev_priv, pipe);
8106 }
8107
8108 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8109 struct intel_crtc_state *crtc_state,
8110 struct dpll *reduced_clock)
8111 {
8112 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8113 u32 dpll;
8114 struct dpll *clock = &crtc_state->dpll;
8115
8116 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8117
8118 dpll = DPLL_VGA_MODE_DIS;
8119
8120 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8121 dpll |= DPLLB_MODE_LVDS;
8122 else
8123 dpll |= DPLLB_MODE_DAC_SERIAL;
8124
8125 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
8126 dpll |= (crtc_state->pixel_multiplier - 1)
8127 << SDVO_MULTIPLIER_SHIFT_HIRES;
8128 }
8129
8130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8131 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8132 dpll |= DPLL_SDVO_HIGH_SPEED;
8133
8134 if (intel_crtc_has_dp_encoder(crtc_state))
8135 dpll |= DPLL_SDVO_HIGH_SPEED;
8136
8137 /* compute bitmask from p1 value */
8138 if (IS_PINEVIEW(dev_priv))
8139 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8140 else {
8141 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8142 if (IS_G4X(dev_priv) && reduced_clock)
8143 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8144 }
8145 switch (clock->p2) {
8146 case 5:
8147 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8148 break;
8149 case 7:
8150 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8151 break;
8152 case 10:
8153 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8154 break;
8155 case 14:
8156 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8157 break;
8158 }
8159 if (INTEL_GEN(dev_priv) >= 4)
8160 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8161
8162 if (crtc_state->sdvo_tv_clock)
8163 dpll |= PLL_REF_INPUT_TVCLKINBC;
8164 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8165 intel_panel_use_ssc(dev_priv))
8166 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8167 else
8168 dpll |= PLL_REF_INPUT_DREFCLK;
8169
8170 dpll |= DPLL_VCO_ENABLE;
8171 crtc_state->dpll_hw_state.dpll = dpll;
8172
8173 if (INTEL_GEN(dev_priv) >= 4) {
8174 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8175 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8176 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8177 }
8178 }
8179
8180 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8181 struct intel_crtc_state *crtc_state,
8182 struct dpll *reduced_clock)
8183 {
8184 struct drm_device *dev = crtc->base.dev;
8185 struct drm_i915_private *dev_priv = to_i915(dev);
8186 u32 dpll;
8187 struct dpll *clock = &crtc_state->dpll;
8188
8189 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8190
8191 dpll = DPLL_VGA_MODE_DIS;
8192
8193 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8194 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8195 } else {
8196 if (clock->p1 == 2)
8197 dpll |= PLL_P1_DIVIDE_BY_TWO;
8198 else
8199 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8200 if (clock->p2 == 4)
8201 dpll |= PLL_P2_DIVIDE_BY_4;
8202 }
8203
8204 if (!IS_I830(dev_priv) &&
8205 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8206 dpll |= DPLL_DVO_2X_MODE;
8207
8208 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8209 intel_panel_use_ssc(dev_priv))
8210 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8211 else
8212 dpll |= PLL_REF_INPUT_DREFCLK;
8213
8214 dpll |= DPLL_VCO_ENABLE;
8215 crtc_state->dpll_hw_state.dpll = dpll;
8216 }
8217
8218 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8219 {
8220 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8221 enum pipe pipe = intel_crtc->pipe;
8222 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8223 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8224 uint32_t crtc_vtotal, crtc_vblank_end;
8225 int vsyncshift = 0;
8226
8227 /* We need to be careful not to changed the adjusted mode, for otherwise
8228 * the hw state checker will get angry at the mismatch. */
8229 crtc_vtotal = adjusted_mode->crtc_vtotal;
8230 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8231
8232 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8233 /* the chip adds 2 halflines automatically */
8234 crtc_vtotal -= 1;
8235 crtc_vblank_end -= 1;
8236
8237 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8238 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8239 else
8240 vsyncshift = adjusted_mode->crtc_hsync_start -
8241 adjusted_mode->crtc_htotal / 2;
8242 if (vsyncshift < 0)
8243 vsyncshift += adjusted_mode->crtc_htotal;
8244 }
8245
8246 if (INTEL_GEN(dev_priv) > 3)
8247 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8248
8249 I915_WRITE(HTOTAL(cpu_transcoder),
8250 (adjusted_mode->crtc_hdisplay - 1) |
8251 ((adjusted_mode->crtc_htotal - 1) << 16));
8252 I915_WRITE(HBLANK(cpu_transcoder),
8253 (adjusted_mode->crtc_hblank_start - 1) |
8254 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8255 I915_WRITE(HSYNC(cpu_transcoder),
8256 (adjusted_mode->crtc_hsync_start - 1) |
8257 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8258
8259 I915_WRITE(VTOTAL(cpu_transcoder),
8260 (adjusted_mode->crtc_vdisplay - 1) |
8261 ((crtc_vtotal - 1) << 16));
8262 I915_WRITE(VBLANK(cpu_transcoder),
8263 (adjusted_mode->crtc_vblank_start - 1) |
8264 ((crtc_vblank_end - 1) << 16));
8265 I915_WRITE(VSYNC(cpu_transcoder),
8266 (adjusted_mode->crtc_vsync_start - 1) |
8267 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8268
8269 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8270 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8271 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8272 * bits. */
8273 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8274 (pipe == PIPE_B || pipe == PIPE_C))
8275 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8276
8277 }
8278
8279 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8280 {
8281 struct drm_device *dev = intel_crtc->base.dev;
8282 struct drm_i915_private *dev_priv = to_i915(dev);
8283 enum pipe pipe = intel_crtc->pipe;
8284
8285 /* pipesrc controls the size that is scaled from, which should
8286 * always be the user's requested size.
8287 */
8288 I915_WRITE(PIPESRC(pipe),
8289 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8290 (intel_crtc->config->pipe_src_h - 1));
8291 }
8292
8293 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8294 struct intel_crtc_state *pipe_config)
8295 {
8296 struct drm_device *dev = crtc->base.dev;
8297 struct drm_i915_private *dev_priv = to_i915(dev);
8298 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8299 uint32_t tmp;
8300
8301 tmp = I915_READ(HTOTAL(cpu_transcoder));
8302 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8303 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8304 tmp = I915_READ(HBLANK(cpu_transcoder));
8305 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8306 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8307 tmp = I915_READ(HSYNC(cpu_transcoder));
8308 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8309 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8310
8311 tmp = I915_READ(VTOTAL(cpu_transcoder));
8312 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8313 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8314 tmp = I915_READ(VBLANK(cpu_transcoder));
8315 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8316 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8317 tmp = I915_READ(VSYNC(cpu_transcoder));
8318 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8319 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8320
8321 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8322 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8323 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8324 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8325 }
8326 }
8327
8328 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8329 struct intel_crtc_state *pipe_config)
8330 {
8331 struct drm_device *dev = crtc->base.dev;
8332 struct drm_i915_private *dev_priv = to_i915(dev);
8333 u32 tmp;
8334
8335 tmp = I915_READ(PIPESRC(crtc->pipe));
8336 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8337 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8338
8339 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8340 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8341 }
8342
8343 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8344 struct intel_crtc_state *pipe_config)
8345 {
8346 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8347 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8348 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8349 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8350
8351 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8352 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8353 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8354 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8355
8356 mode->flags = pipe_config->base.adjusted_mode.flags;
8357 mode->type = DRM_MODE_TYPE_DRIVER;
8358
8359 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8360 mode->flags |= pipe_config->base.adjusted_mode.flags;
8361
8362 mode->hsync = drm_mode_hsync(mode);
8363 mode->vrefresh = drm_mode_vrefresh(mode);
8364 drm_mode_set_name(mode);
8365 }
8366
8367 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8368 {
8369 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8370 uint32_t pipeconf;
8371
8372 pipeconf = 0;
8373
8374 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8375 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8376 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8377
8378 if (intel_crtc->config->double_wide)
8379 pipeconf |= PIPECONF_DOUBLE_WIDE;
8380
8381 /* only g4x and later have fancy bpc/dither controls */
8382 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8383 IS_CHERRYVIEW(dev_priv)) {
8384 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8385 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8386 pipeconf |= PIPECONF_DITHER_EN |
8387 PIPECONF_DITHER_TYPE_SP;
8388
8389 switch (intel_crtc->config->pipe_bpp) {
8390 case 18:
8391 pipeconf |= PIPECONF_6BPC;
8392 break;
8393 case 24:
8394 pipeconf |= PIPECONF_8BPC;
8395 break;
8396 case 30:
8397 pipeconf |= PIPECONF_10BPC;
8398 break;
8399 default:
8400 /* Case prevented by intel_choose_pipe_bpp_dither. */
8401 BUG();
8402 }
8403 }
8404
8405 if (HAS_PIPE_CXSR(dev_priv)) {
8406 if (intel_crtc->lowfreq_avail) {
8407 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8408 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8409 } else {
8410 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8411 }
8412 }
8413
8414 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8415 if (INTEL_GEN(dev_priv) < 4 ||
8416 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8417 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8418 else
8419 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8420 } else
8421 pipeconf |= PIPECONF_PROGRESSIVE;
8422
8423 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8424 intel_crtc->config->limited_color_range)
8425 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8426
8427 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8428 POSTING_READ(PIPECONF(intel_crtc->pipe));
8429 }
8430
8431 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8432 struct intel_crtc_state *crtc_state)
8433 {
8434 struct drm_device *dev = crtc->base.dev;
8435 struct drm_i915_private *dev_priv = to_i915(dev);
8436 const struct intel_limit *limit;
8437 int refclk = 48000;
8438
8439 memset(&crtc_state->dpll_hw_state, 0,
8440 sizeof(crtc_state->dpll_hw_state));
8441
8442 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8443 if (intel_panel_use_ssc(dev_priv)) {
8444 refclk = dev_priv->vbt.lvds_ssc_freq;
8445 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8446 }
8447
8448 limit = &intel_limits_i8xx_lvds;
8449 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8450 limit = &intel_limits_i8xx_dvo;
8451 } else {
8452 limit = &intel_limits_i8xx_dac;
8453 }
8454
8455 if (!crtc_state->clock_set &&
8456 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8457 refclk, NULL, &crtc_state->dpll)) {
8458 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8459 return -EINVAL;
8460 }
8461
8462 i8xx_compute_dpll(crtc, crtc_state, NULL);
8463
8464 return 0;
8465 }
8466
8467 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8468 struct intel_crtc_state *crtc_state)
8469 {
8470 struct drm_device *dev = crtc->base.dev;
8471 struct drm_i915_private *dev_priv = to_i915(dev);
8472 const struct intel_limit *limit;
8473 int refclk = 96000;
8474
8475 memset(&crtc_state->dpll_hw_state, 0,
8476 sizeof(crtc_state->dpll_hw_state));
8477
8478 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8479 if (intel_panel_use_ssc(dev_priv)) {
8480 refclk = dev_priv->vbt.lvds_ssc_freq;
8481 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8482 }
8483
8484 if (intel_is_dual_link_lvds(dev))
8485 limit = &intel_limits_g4x_dual_channel_lvds;
8486 else
8487 limit = &intel_limits_g4x_single_channel_lvds;
8488 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8489 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8490 limit = &intel_limits_g4x_hdmi;
8491 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8492 limit = &intel_limits_g4x_sdvo;
8493 } else {
8494 /* The option is for other outputs */
8495 limit = &intel_limits_i9xx_sdvo;
8496 }
8497
8498 if (!crtc_state->clock_set &&
8499 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8500 refclk, NULL, &crtc_state->dpll)) {
8501 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8502 return -EINVAL;
8503 }
8504
8505 i9xx_compute_dpll(crtc, crtc_state, NULL);
8506
8507 return 0;
8508 }
8509
8510 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8511 struct intel_crtc_state *crtc_state)
8512 {
8513 struct drm_device *dev = crtc->base.dev;
8514 struct drm_i915_private *dev_priv = to_i915(dev);
8515 const struct intel_limit *limit;
8516 int refclk = 96000;
8517
8518 memset(&crtc_state->dpll_hw_state, 0,
8519 sizeof(crtc_state->dpll_hw_state));
8520
8521 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8522 if (intel_panel_use_ssc(dev_priv)) {
8523 refclk = dev_priv->vbt.lvds_ssc_freq;
8524 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8525 }
8526
8527 limit = &intel_limits_pineview_lvds;
8528 } else {
8529 limit = &intel_limits_pineview_sdvo;
8530 }
8531
8532 if (!crtc_state->clock_set &&
8533 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8534 refclk, NULL, &crtc_state->dpll)) {
8535 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8536 return -EINVAL;
8537 }
8538
8539 i9xx_compute_dpll(crtc, crtc_state, NULL);
8540
8541 return 0;
8542 }
8543
8544 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8545 struct intel_crtc_state *crtc_state)
8546 {
8547 struct drm_device *dev = crtc->base.dev;
8548 struct drm_i915_private *dev_priv = to_i915(dev);
8549 const struct intel_limit *limit;
8550 int refclk = 96000;
8551
8552 memset(&crtc_state->dpll_hw_state, 0,
8553 sizeof(crtc_state->dpll_hw_state));
8554
8555 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8556 if (intel_panel_use_ssc(dev_priv)) {
8557 refclk = dev_priv->vbt.lvds_ssc_freq;
8558 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8559 }
8560
8561 limit = &intel_limits_i9xx_lvds;
8562 } else {
8563 limit = &intel_limits_i9xx_sdvo;
8564 }
8565
8566 if (!crtc_state->clock_set &&
8567 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8568 refclk, NULL, &crtc_state->dpll)) {
8569 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8570 return -EINVAL;
8571 }
8572
8573 i9xx_compute_dpll(crtc, crtc_state, NULL);
8574
8575 return 0;
8576 }
8577
8578 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8579 struct intel_crtc_state *crtc_state)
8580 {
8581 int refclk = 100000;
8582 const struct intel_limit *limit = &intel_limits_chv;
8583
8584 memset(&crtc_state->dpll_hw_state, 0,
8585 sizeof(crtc_state->dpll_hw_state));
8586
8587 if (!crtc_state->clock_set &&
8588 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8589 refclk, NULL, &crtc_state->dpll)) {
8590 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8591 return -EINVAL;
8592 }
8593
8594 chv_compute_dpll(crtc, crtc_state);
8595
8596 return 0;
8597 }
8598
8599 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8600 struct intel_crtc_state *crtc_state)
8601 {
8602 int refclk = 100000;
8603 const struct intel_limit *limit = &intel_limits_vlv;
8604
8605 memset(&crtc_state->dpll_hw_state, 0,
8606 sizeof(crtc_state->dpll_hw_state));
8607
8608 if (!crtc_state->clock_set &&
8609 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8610 refclk, NULL, &crtc_state->dpll)) {
8611 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8612 return -EINVAL;
8613 }
8614
8615 vlv_compute_dpll(crtc, crtc_state);
8616
8617 return 0;
8618 }
8619
8620 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8621 struct intel_crtc_state *pipe_config)
8622 {
8623 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8624 uint32_t tmp;
8625
8626 if (INTEL_GEN(dev_priv) <= 3 &&
8627 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
8628 return;
8629
8630 tmp = I915_READ(PFIT_CONTROL);
8631 if (!(tmp & PFIT_ENABLE))
8632 return;
8633
8634 /* Check whether the pfit is attached to our pipe. */
8635 if (INTEL_GEN(dev_priv) < 4) {
8636 if (crtc->pipe != PIPE_B)
8637 return;
8638 } else {
8639 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8640 return;
8641 }
8642
8643 pipe_config->gmch_pfit.control = tmp;
8644 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8645 }
8646
8647 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8648 struct intel_crtc_state *pipe_config)
8649 {
8650 struct drm_device *dev = crtc->base.dev;
8651 struct drm_i915_private *dev_priv = to_i915(dev);
8652 int pipe = pipe_config->cpu_transcoder;
8653 struct dpll clock;
8654 u32 mdiv;
8655 int refclk = 100000;
8656
8657 /* In case of DSI, DPLL will not be used */
8658 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8659 return;
8660
8661 mutex_lock(&dev_priv->sb_lock);
8662 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8663 mutex_unlock(&dev_priv->sb_lock);
8664
8665 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8666 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8667 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8668 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8669 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8670
8671 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8672 }
8673
8674 static void
8675 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8676 struct intel_initial_plane_config *plane_config)
8677 {
8678 struct drm_device *dev = crtc->base.dev;
8679 struct drm_i915_private *dev_priv = to_i915(dev);
8680 u32 val, base, offset;
8681 int pipe = crtc->pipe, plane = crtc->plane;
8682 int fourcc, pixel_format;
8683 unsigned int aligned_height;
8684 struct drm_framebuffer *fb;
8685 struct intel_framebuffer *intel_fb;
8686
8687 val = I915_READ(DSPCNTR(plane));
8688 if (!(val & DISPLAY_PLANE_ENABLE))
8689 return;
8690
8691 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8692 if (!intel_fb) {
8693 DRM_DEBUG_KMS("failed to alloc fb\n");
8694 return;
8695 }
8696
8697 fb = &intel_fb->base;
8698
8699 if (INTEL_GEN(dev_priv) >= 4) {
8700 if (val & DISPPLANE_TILED) {
8701 plane_config->tiling = I915_TILING_X;
8702 fb->modifier = I915_FORMAT_MOD_X_TILED;
8703 }
8704 }
8705
8706 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8707 fourcc = i9xx_format_to_fourcc(pixel_format);
8708 fb->pixel_format = fourcc;
8709 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8710
8711 if (INTEL_GEN(dev_priv) >= 4) {
8712 if (plane_config->tiling)
8713 offset = I915_READ(DSPTILEOFF(plane));
8714 else
8715 offset = I915_READ(DSPLINOFF(plane));
8716 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8717 } else {
8718 base = I915_READ(DSPADDR(plane));
8719 }
8720 plane_config->base = base;
8721
8722 val = I915_READ(PIPESRC(pipe));
8723 fb->width = ((val >> 16) & 0xfff) + 1;
8724 fb->height = ((val >> 0) & 0xfff) + 1;
8725
8726 val = I915_READ(DSPSTRIDE(pipe));
8727 fb->pitches[0] = val & 0xffffffc0;
8728
8729 aligned_height = intel_fb_align_height(dev, fb->height,
8730 fb->pixel_format,
8731 fb->modifier);
8732
8733 plane_config->size = fb->pitches[0] * aligned_height;
8734
8735 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8736 pipe_name(pipe), plane, fb->width, fb->height,
8737 fb->bits_per_pixel, base, fb->pitches[0],
8738 plane_config->size);
8739
8740 plane_config->fb = intel_fb;
8741 }
8742
8743 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8744 struct intel_crtc_state *pipe_config)
8745 {
8746 struct drm_device *dev = crtc->base.dev;
8747 struct drm_i915_private *dev_priv = to_i915(dev);
8748 int pipe = pipe_config->cpu_transcoder;
8749 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8750 struct dpll clock;
8751 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8752 int refclk = 100000;
8753
8754 /* In case of DSI, DPLL will not be used */
8755 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8756 return;
8757
8758 mutex_lock(&dev_priv->sb_lock);
8759 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8760 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8761 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8762 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8763 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8764 mutex_unlock(&dev_priv->sb_lock);
8765
8766 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8767 clock.m2 = (pll_dw0 & 0xff) << 22;
8768 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8769 clock.m2 |= pll_dw2 & 0x3fffff;
8770 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8771 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8772 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8773
8774 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8775 }
8776
8777 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8778 struct intel_crtc_state *pipe_config)
8779 {
8780 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8781 enum intel_display_power_domain power_domain;
8782 uint32_t tmp;
8783 bool ret;
8784
8785 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8786 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8787 return false;
8788
8789 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8790 pipe_config->shared_dpll = NULL;
8791
8792 ret = false;
8793
8794 tmp = I915_READ(PIPECONF(crtc->pipe));
8795 if (!(tmp & PIPECONF_ENABLE))
8796 goto out;
8797
8798 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8799 IS_CHERRYVIEW(dev_priv)) {
8800 switch (tmp & PIPECONF_BPC_MASK) {
8801 case PIPECONF_6BPC:
8802 pipe_config->pipe_bpp = 18;
8803 break;
8804 case PIPECONF_8BPC:
8805 pipe_config->pipe_bpp = 24;
8806 break;
8807 case PIPECONF_10BPC:
8808 pipe_config->pipe_bpp = 30;
8809 break;
8810 default:
8811 break;
8812 }
8813 }
8814
8815 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8816 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8817 pipe_config->limited_color_range = true;
8818
8819 if (INTEL_GEN(dev_priv) < 4)
8820 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8821
8822 intel_get_pipe_timings(crtc, pipe_config);
8823 intel_get_pipe_src_size(crtc, pipe_config);
8824
8825 i9xx_get_pfit_config(crtc, pipe_config);
8826
8827 if (INTEL_GEN(dev_priv) >= 4) {
8828 /* No way to read it out on pipes B and C */
8829 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8830 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8831 else
8832 tmp = I915_READ(DPLL_MD(crtc->pipe));
8833 pipe_config->pixel_multiplier =
8834 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8835 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8836 pipe_config->dpll_hw_state.dpll_md = tmp;
8837 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8838 IS_G33(dev_priv)) {
8839 tmp = I915_READ(DPLL(crtc->pipe));
8840 pipe_config->pixel_multiplier =
8841 ((tmp & SDVO_MULTIPLIER_MASK)
8842 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8843 } else {
8844 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8845 * port and will be fixed up in the encoder->get_config
8846 * function. */
8847 pipe_config->pixel_multiplier = 1;
8848 }
8849 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8850 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8851 /*
8852 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8853 * on 830. Filter it out here so that we don't
8854 * report errors due to that.
8855 */
8856 if (IS_I830(dev_priv))
8857 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8858
8859 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8860 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8861 } else {
8862 /* Mask out read-only status bits. */
8863 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8864 DPLL_PORTC_READY_MASK |
8865 DPLL_PORTB_READY_MASK);
8866 }
8867
8868 if (IS_CHERRYVIEW(dev_priv))
8869 chv_crtc_clock_get(crtc, pipe_config);
8870 else if (IS_VALLEYVIEW(dev_priv))
8871 vlv_crtc_clock_get(crtc, pipe_config);
8872 else
8873 i9xx_crtc_clock_get(crtc, pipe_config);
8874
8875 /*
8876 * Normally the dotclock is filled in by the encoder .get_config()
8877 * but in case the pipe is enabled w/o any ports we need a sane
8878 * default.
8879 */
8880 pipe_config->base.adjusted_mode.crtc_clock =
8881 pipe_config->port_clock / pipe_config->pixel_multiplier;
8882
8883 ret = true;
8884
8885 out:
8886 intel_display_power_put(dev_priv, power_domain);
8887
8888 return ret;
8889 }
8890
8891 static void ironlake_init_pch_refclk(struct drm_device *dev)
8892 {
8893 struct drm_i915_private *dev_priv = to_i915(dev);
8894 struct intel_encoder *encoder;
8895 int i;
8896 u32 val, final;
8897 bool has_lvds = false;
8898 bool has_cpu_edp = false;
8899 bool has_panel = false;
8900 bool has_ck505 = false;
8901 bool can_ssc = false;
8902 bool using_ssc_source = false;
8903
8904 /* We need to take the global config into account */
8905 for_each_intel_encoder(dev, encoder) {
8906 switch (encoder->type) {
8907 case INTEL_OUTPUT_LVDS:
8908 has_panel = true;
8909 has_lvds = true;
8910 break;
8911 case INTEL_OUTPUT_EDP:
8912 has_panel = true;
8913 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8914 has_cpu_edp = true;
8915 break;
8916 default:
8917 break;
8918 }
8919 }
8920
8921 if (HAS_PCH_IBX(dev_priv)) {
8922 has_ck505 = dev_priv->vbt.display_clock_mode;
8923 can_ssc = has_ck505;
8924 } else {
8925 has_ck505 = false;
8926 can_ssc = true;
8927 }
8928
8929 /* Check if any DPLLs are using the SSC source */
8930 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8931 u32 temp = I915_READ(PCH_DPLL(i));
8932
8933 if (!(temp & DPLL_VCO_ENABLE))
8934 continue;
8935
8936 if ((temp & PLL_REF_INPUT_MASK) ==
8937 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8938 using_ssc_source = true;
8939 break;
8940 }
8941 }
8942
8943 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8944 has_panel, has_lvds, has_ck505, using_ssc_source);
8945
8946 /* Ironlake: try to setup display ref clock before DPLL
8947 * enabling. This is only under driver's control after
8948 * PCH B stepping, previous chipset stepping should be
8949 * ignoring this setting.
8950 */
8951 val = I915_READ(PCH_DREF_CONTROL);
8952
8953 /* As we must carefully and slowly disable/enable each source in turn,
8954 * compute the final state we want first and check if we need to
8955 * make any changes at all.
8956 */
8957 final = val;
8958 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8959 if (has_ck505)
8960 final |= DREF_NONSPREAD_CK505_ENABLE;
8961 else
8962 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8963
8964 final &= ~DREF_SSC_SOURCE_MASK;
8965 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8966 final &= ~DREF_SSC1_ENABLE;
8967
8968 if (has_panel) {
8969 final |= DREF_SSC_SOURCE_ENABLE;
8970
8971 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8972 final |= DREF_SSC1_ENABLE;
8973
8974 if (has_cpu_edp) {
8975 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8976 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8977 else
8978 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8979 } else
8980 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8981 } else if (using_ssc_source) {
8982 final |= DREF_SSC_SOURCE_ENABLE;
8983 final |= DREF_SSC1_ENABLE;
8984 }
8985
8986 if (final == val)
8987 return;
8988
8989 /* Always enable nonspread source */
8990 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8991
8992 if (has_ck505)
8993 val |= DREF_NONSPREAD_CK505_ENABLE;
8994 else
8995 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8996
8997 if (has_panel) {
8998 val &= ~DREF_SSC_SOURCE_MASK;
8999 val |= DREF_SSC_SOURCE_ENABLE;
9000
9001 /* SSC must be turned on before enabling the CPU output */
9002 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9003 DRM_DEBUG_KMS("Using SSC on panel\n");
9004 val |= DREF_SSC1_ENABLE;
9005 } else
9006 val &= ~DREF_SSC1_ENABLE;
9007
9008 /* Get SSC going before enabling the outputs */
9009 I915_WRITE(PCH_DREF_CONTROL, val);
9010 POSTING_READ(PCH_DREF_CONTROL);
9011 udelay(200);
9012
9013 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9014
9015 /* Enable CPU source on CPU attached eDP */
9016 if (has_cpu_edp) {
9017 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9018 DRM_DEBUG_KMS("Using SSC on eDP\n");
9019 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9020 } else
9021 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9022 } else
9023 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9024
9025 I915_WRITE(PCH_DREF_CONTROL, val);
9026 POSTING_READ(PCH_DREF_CONTROL);
9027 udelay(200);
9028 } else {
9029 DRM_DEBUG_KMS("Disabling CPU source output\n");
9030
9031 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9032
9033 /* Turn off CPU output */
9034 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9035
9036 I915_WRITE(PCH_DREF_CONTROL, val);
9037 POSTING_READ(PCH_DREF_CONTROL);
9038 udelay(200);
9039
9040 if (!using_ssc_source) {
9041 DRM_DEBUG_KMS("Disabling SSC source\n");
9042
9043 /* Turn off the SSC source */
9044 val &= ~DREF_SSC_SOURCE_MASK;
9045 val |= DREF_SSC_SOURCE_DISABLE;
9046
9047 /* Turn off SSC1 */
9048 val &= ~DREF_SSC1_ENABLE;
9049
9050 I915_WRITE(PCH_DREF_CONTROL, val);
9051 POSTING_READ(PCH_DREF_CONTROL);
9052 udelay(200);
9053 }
9054 }
9055
9056 BUG_ON(val != final);
9057 }
9058
9059 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9060 {
9061 uint32_t tmp;
9062
9063 tmp = I915_READ(SOUTH_CHICKEN2);
9064 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9065 I915_WRITE(SOUTH_CHICKEN2, tmp);
9066
9067 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9068 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9069 DRM_ERROR("FDI mPHY reset assert timeout\n");
9070
9071 tmp = I915_READ(SOUTH_CHICKEN2);
9072 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9073 I915_WRITE(SOUTH_CHICKEN2, tmp);
9074
9075 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9076 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9077 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9078 }
9079
9080 /* WaMPhyProgramming:hsw */
9081 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9082 {
9083 uint32_t tmp;
9084
9085 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9086 tmp &= ~(0xFF << 24);
9087 tmp |= (0x12 << 24);
9088 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9089
9090 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9091 tmp |= (1 << 11);
9092 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9093
9094 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9095 tmp |= (1 << 11);
9096 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9097
9098 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9099 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9100 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9101
9102 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9103 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9104 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9105
9106 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9107 tmp &= ~(7 << 13);
9108 tmp |= (5 << 13);
9109 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9110
9111 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9112 tmp &= ~(7 << 13);
9113 tmp |= (5 << 13);
9114 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9115
9116 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9117 tmp &= ~0xFF;
9118 tmp |= 0x1C;
9119 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9120
9121 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9122 tmp &= ~0xFF;
9123 tmp |= 0x1C;
9124 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9125
9126 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9127 tmp &= ~(0xFF << 16);
9128 tmp |= (0x1C << 16);
9129 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9130
9131 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9132 tmp &= ~(0xFF << 16);
9133 tmp |= (0x1C << 16);
9134 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9135
9136 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9137 tmp |= (1 << 27);
9138 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9139
9140 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9141 tmp |= (1 << 27);
9142 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9143
9144 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9145 tmp &= ~(0xF << 28);
9146 tmp |= (4 << 28);
9147 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9148
9149 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9150 tmp &= ~(0xF << 28);
9151 tmp |= (4 << 28);
9152 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9153 }
9154
9155 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9156 * Programming" based on the parameters passed:
9157 * - Sequence to enable CLKOUT_DP
9158 * - Sequence to enable CLKOUT_DP without spread
9159 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9160 */
9161 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9162 bool with_fdi)
9163 {
9164 struct drm_i915_private *dev_priv = to_i915(dev);
9165 uint32_t reg, tmp;
9166
9167 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9168 with_spread = true;
9169 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9170 with_fdi, "LP PCH doesn't have FDI\n"))
9171 with_fdi = false;
9172
9173 mutex_lock(&dev_priv->sb_lock);
9174
9175 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9176 tmp &= ~SBI_SSCCTL_DISABLE;
9177 tmp |= SBI_SSCCTL_PATHALT;
9178 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9179
9180 udelay(24);
9181
9182 if (with_spread) {
9183 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9184 tmp &= ~SBI_SSCCTL_PATHALT;
9185 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9186
9187 if (with_fdi) {
9188 lpt_reset_fdi_mphy(dev_priv);
9189 lpt_program_fdi_mphy(dev_priv);
9190 }
9191 }
9192
9193 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9194 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9195 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9196 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9197
9198 mutex_unlock(&dev_priv->sb_lock);
9199 }
9200
9201 /* Sequence to disable CLKOUT_DP */
9202 static void lpt_disable_clkout_dp(struct drm_device *dev)
9203 {
9204 struct drm_i915_private *dev_priv = to_i915(dev);
9205 uint32_t reg, tmp;
9206
9207 mutex_lock(&dev_priv->sb_lock);
9208
9209 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9210 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9211 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9212 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9213
9214 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9215 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9216 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9217 tmp |= SBI_SSCCTL_PATHALT;
9218 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9219 udelay(32);
9220 }
9221 tmp |= SBI_SSCCTL_DISABLE;
9222 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9223 }
9224
9225 mutex_unlock(&dev_priv->sb_lock);
9226 }
9227
9228 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9229
9230 static const uint16_t sscdivintphase[] = {
9231 [BEND_IDX( 50)] = 0x3B23,
9232 [BEND_IDX( 45)] = 0x3B23,
9233 [BEND_IDX( 40)] = 0x3C23,
9234 [BEND_IDX( 35)] = 0x3C23,
9235 [BEND_IDX( 30)] = 0x3D23,
9236 [BEND_IDX( 25)] = 0x3D23,
9237 [BEND_IDX( 20)] = 0x3E23,
9238 [BEND_IDX( 15)] = 0x3E23,
9239 [BEND_IDX( 10)] = 0x3F23,
9240 [BEND_IDX( 5)] = 0x3F23,
9241 [BEND_IDX( 0)] = 0x0025,
9242 [BEND_IDX( -5)] = 0x0025,
9243 [BEND_IDX(-10)] = 0x0125,
9244 [BEND_IDX(-15)] = 0x0125,
9245 [BEND_IDX(-20)] = 0x0225,
9246 [BEND_IDX(-25)] = 0x0225,
9247 [BEND_IDX(-30)] = 0x0325,
9248 [BEND_IDX(-35)] = 0x0325,
9249 [BEND_IDX(-40)] = 0x0425,
9250 [BEND_IDX(-45)] = 0x0425,
9251 [BEND_IDX(-50)] = 0x0525,
9252 };
9253
9254 /*
9255 * Bend CLKOUT_DP
9256 * steps -50 to 50 inclusive, in steps of 5
9257 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9258 * change in clock period = -(steps / 10) * 5.787 ps
9259 */
9260 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9261 {
9262 uint32_t tmp;
9263 int idx = BEND_IDX(steps);
9264
9265 if (WARN_ON(steps % 5 != 0))
9266 return;
9267
9268 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9269 return;
9270
9271 mutex_lock(&dev_priv->sb_lock);
9272
9273 if (steps % 10 != 0)
9274 tmp = 0xAAAAAAAB;
9275 else
9276 tmp = 0x00000000;
9277 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9278
9279 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9280 tmp &= 0xffff0000;
9281 tmp |= sscdivintphase[idx];
9282 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9283
9284 mutex_unlock(&dev_priv->sb_lock);
9285 }
9286
9287 #undef BEND_IDX
9288
9289 static void lpt_init_pch_refclk(struct drm_device *dev)
9290 {
9291 struct intel_encoder *encoder;
9292 bool has_vga = false;
9293
9294 for_each_intel_encoder(dev, encoder) {
9295 switch (encoder->type) {
9296 case INTEL_OUTPUT_ANALOG:
9297 has_vga = true;
9298 break;
9299 default:
9300 break;
9301 }
9302 }
9303
9304 if (has_vga) {
9305 lpt_bend_clkout_dp(to_i915(dev), 0);
9306 lpt_enable_clkout_dp(dev, true, true);
9307 } else {
9308 lpt_disable_clkout_dp(dev);
9309 }
9310 }
9311
9312 /*
9313 * Initialize reference clocks when the driver loads
9314 */
9315 void intel_init_pch_refclk(struct drm_device *dev)
9316 {
9317 struct drm_i915_private *dev_priv = to_i915(dev);
9318
9319 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9320 ironlake_init_pch_refclk(dev);
9321 else if (HAS_PCH_LPT(dev_priv))
9322 lpt_init_pch_refclk(dev);
9323 }
9324
9325 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9326 {
9327 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9329 int pipe = intel_crtc->pipe;
9330 uint32_t val;
9331
9332 val = 0;
9333
9334 switch (intel_crtc->config->pipe_bpp) {
9335 case 18:
9336 val |= PIPECONF_6BPC;
9337 break;
9338 case 24:
9339 val |= PIPECONF_8BPC;
9340 break;
9341 case 30:
9342 val |= PIPECONF_10BPC;
9343 break;
9344 case 36:
9345 val |= PIPECONF_12BPC;
9346 break;
9347 default:
9348 /* Case prevented by intel_choose_pipe_bpp_dither. */
9349 BUG();
9350 }
9351
9352 if (intel_crtc->config->dither)
9353 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9354
9355 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9356 val |= PIPECONF_INTERLACED_ILK;
9357 else
9358 val |= PIPECONF_PROGRESSIVE;
9359
9360 if (intel_crtc->config->limited_color_range)
9361 val |= PIPECONF_COLOR_RANGE_SELECT;
9362
9363 I915_WRITE(PIPECONF(pipe), val);
9364 POSTING_READ(PIPECONF(pipe));
9365 }
9366
9367 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9368 {
9369 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9372 u32 val = 0;
9373
9374 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9375 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9376
9377 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9378 val |= PIPECONF_INTERLACED_ILK;
9379 else
9380 val |= PIPECONF_PROGRESSIVE;
9381
9382 I915_WRITE(PIPECONF(cpu_transcoder), val);
9383 POSTING_READ(PIPECONF(cpu_transcoder));
9384 }
9385
9386 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9387 {
9388 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9390
9391 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9392 u32 val = 0;
9393
9394 switch (intel_crtc->config->pipe_bpp) {
9395 case 18:
9396 val |= PIPEMISC_DITHER_6_BPC;
9397 break;
9398 case 24:
9399 val |= PIPEMISC_DITHER_8_BPC;
9400 break;
9401 case 30:
9402 val |= PIPEMISC_DITHER_10_BPC;
9403 break;
9404 case 36:
9405 val |= PIPEMISC_DITHER_12_BPC;
9406 break;
9407 default:
9408 /* Case prevented by pipe_config_set_bpp. */
9409 BUG();
9410 }
9411
9412 if (intel_crtc->config->dither)
9413 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9414
9415 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9416 }
9417 }
9418
9419 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9420 {
9421 /*
9422 * Account for spread spectrum to avoid
9423 * oversubscribing the link. Max center spread
9424 * is 2.5%; use 5% for safety's sake.
9425 */
9426 u32 bps = target_clock * bpp * 21 / 20;
9427 return DIV_ROUND_UP(bps, link_bw * 8);
9428 }
9429
9430 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9431 {
9432 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9433 }
9434
9435 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9436 struct intel_crtc_state *crtc_state,
9437 struct dpll *reduced_clock)
9438 {
9439 struct drm_crtc *crtc = &intel_crtc->base;
9440 struct drm_device *dev = crtc->dev;
9441 struct drm_i915_private *dev_priv = to_i915(dev);
9442 u32 dpll, fp, fp2;
9443 int factor;
9444
9445 /* Enable autotuning of the PLL clock (if permissible) */
9446 factor = 21;
9447 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9448 if ((intel_panel_use_ssc(dev_priv) &&
9449 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9450 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
9451 factor = 25;
9452 } else if (crtc_state->sdvo_tv_clock)
9453 factor = 20;
9454
9455 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9456
9457 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9458 fp |= FP_CB_TUNE;
9459
9460 if (reduced_clock) {
9461 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9462
9463 if (reduced_clock->m < factor * reduced_clock->n)
9464 fp2 |= FP_CB_TUNE;
9465 } else {
9466 fp2 = fp;
9467 }
9468
9469 dpll = 0;
9470
9471 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9472 dpll |= DPLLB_MODE_LVDS;
9473 else
9474 dpll |= DPLLB_MODE_DAC_SERIAL;
9475
9476 dpll |= (crtc_state->pixel_multiplier - 1)
9477 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9478
9479 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9480 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9481 dpll |= DPLL_SDVO_HIGH_SPEED;
9482
9483 if (intel_crtc_has_dp_encoder(crtc_state))
9484 dpll |= DPLL_SDVO_HIGH_SPEED;
9485
9486 /*
9487 * The high speed IO clock is only really required for
9488 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9489 * possible to share the DPLL between CRT and HDMI. Enabling
9490 * the clock needlessly does no real harm, except use up a
9491 * bit of power potentially.
9492 *
9493 * We'll limit this to IVB with 3 pipes, since it has only two
9494 * DPLLs and so DPLL sharing is the only way to get three pipes
9495 * driving PCH ports at the same time. On SNB we could do this,
9496 * and potentially avoid enabling the second DPLL, but it's not
9497 * clear if it''s a win or loss power wise. No point in doing
9498 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9499 */
9500 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9501 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9502 dpll |= DPLL_SDVO_HIGH_SPEED;
9503
9504 /* compute bitmask from p1 value */
9505 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9506 /* also FPA1 */
9507 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9508
9509 switch (crtc_state->dpll.p2) {
9510 case 5:
9511 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9512 break;
9513 case 7:
9514 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9515 break;
9516 case 10:
9517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9518 break;
9519 case 14:
9520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9521 break;
9522 }
9523
9524 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9525 intel_panel_use_ssc(dev_priv))
9526 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9527 else
9528 dpll |= PLL_REF_INPUT_DREFCLK;
9529
9530 dpll |= DPLL_VCO_ENABLE;
9531
9532 crtc_state->dpll_hw_state.dpll = dpll;
9533 crtc_state->dpll_hw_state.fp0 = fp;
9534 crtc_state->dpll_hw_state.fp1 = fp2;
9535 }
9536
9537 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9538 struct intel_crtc_state *crtc_state)
9539 {
9540 struct drm_device *dev = crtc->base.dev;
9541 struct drm_i915_private *dev_priv = to_i915(dev);
9542 struct dpll reduced_clock;
9543 bool has_reduced_clock = false;
9544 struct intel_shared_dpll *pll;
9545 const struct intel_limit *limit;
9546 int refclk = 120000;
9547
9548 memset(&crtc_state->dpll_hw_state, 0,
9549 sizeof(crtc_state->dpll_hw_state));
9550
9551 crtc->lowfreq_avail = false;
9552
9553 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9554 if (!crtc_state->has_pch_encoder)
9555 return 0;
9556
9557 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9558 if (intel_panel_use_ssc(dev_priv)) {
9559 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9560 dev_priv->vbt.lvds_ssc_freq);
9561 refclk = dev_priv->vbt.lvds_ssc_freq;
9562 }
9563
9564 if (intel_is_dual_link_lvds(dev)) {
9565 if (refclk == 100000)
9566 limit = &intel_limits_ironlake_dual_lvds_100m;
9567 else
9568 limit = &intel_limits_ironlake_dual_lvds;
9569 } else {
9570 if (refclk == 100000)
9571 limit = &intel_limits_ironlake_single_lvds_100m;
9572 else
9573 limit = &intel_limits_ironlake_single_lvds;
9574 }
9575 } else {
9576 limit = &intel_limits_ironlake_dac;
9577 }
9578
9579 if (!crtc_state->clock_set &&
9580 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9581 refclk, NULL, &crtc_state->dpll)) {
9582 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9583 return -EINVAL;
9584 }
9585
9586 ironlake_compute_dpll(crtc, crtc_state,
9587 has_reduced_clock ? &reduced_clock : NULL);
9588
9589 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9590 if (pll == NULL) {
9591 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9592 pipe_name(crtc->pipe));
9593 return -EINVAL;
9594 }
9595
9596 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9597 has_reduced_clock)
9598 crtc->lowfreq_avail = true;
9599
9600 return 0;
9601 }
9602
9603 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9604 struct intel_link_m_n *m_n)
9605 {
9606 struct drm_device *dev = crtc->base.dev;
9607 struct drm_i915_private *dev_priv = to_i915(dev);
9608 enum pipe pipe = crtc->pipe;
9609
9610 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9611 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9612 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9613 & ~TU_SIZE_MASK;
9614 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9615 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9616 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9617 }
9618
9619 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9620 enum transcoder transcoder,
9621 struct intel_link_m_n *m_n,
9622 struct intel_link_m_n *m2_n2)
9623 {
9624 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9625 enum pipe pipe = crtc->pipe;
9626
9627 if (INTEL_GEN(dev_priv) >= 5) {
9628 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9629 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9630 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9631 & ~TU_SIZE_MASK;
9632 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9633 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9634 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9635 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9636 * gen < 8) and if DRRS is supported (to make sure the
9637 * registers are not unnecessarily read).
9638 */
9639 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
9640 crtc->config->has_drrs) {
9641 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9642 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9643 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9644 & ~TU_SIZE_MASK;
9645 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9646 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9647 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9648 }
9649 } else {
9650 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9651 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9652 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9653 & ~TU_SIZE_MASK;
9654 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9655 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9656 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9657 }
9658 }
9659
9660 void intel_dp_get_m_n(struct intel_crtc *crtc,
9661 struct intel_crtc_state *pipe_config)
9662 {
9663 if (pipe_config->has_pch_encoder)
9664 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9665 else
9666 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9667 &pipe_config->dp_m_n,
9668 &pipe_config->dp_m2_n2);
9669 }
9670
9671 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9672 struct intel_crtc_state *pipe_config)
9673 {
9674 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9675 &pipe_config->fdi_m_n, NULL);
9676 }
9677
9678 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9679 struct intel_crtc_state *pipe_config)
9680 {
9681 struct drm_device *dev = crtc->base.dev;
9682 struct drm_i915_private *dev_priv = to_i915(dev);
9683 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9684 uint32_t ps_ctrl = 0;
9685 int id = -1;
9686 int i;
9687
9688 /* find scaler attached to this pipe */
9689 for (i = 0; i < crtc->num_scalers; i++) {
9690 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9691 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9692 id = i;
9693 pipe_config->pch_pfit.enabled = true;
9694 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9695 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9696 break;
9697 }
9698 }
9699
9700 scaler_state->scaler_id = id;
9701 if (id >= 0) {
9702 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9703 } else {
9704 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9705 }
9706 }
9707
9708 static void
9709 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9710 struct intel_initial_plane_config *plane_config)
9711 {
9712 struct drm_device *dev = crtc->base.dev;
9713 struct drm_i915_private *dev_priv = to_i915(dev);
9714 u32 val, base, offset, stride_mult, tiling;
9715 int pipe = crtc->pipe;
9716 int fourcc, pixel_format;
9717 unsigned int aligned_height;
9718 struct drm_framebuffer *fb;
9719 struct intel_framebuffer *intel_fb;
9720
9721 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9722 if (!intel_fb) {
9723 DRM_DEBUG_KMS("failed to alloc fb\n");
9724 return;
9725 }
9726
9727 fb = &intel_fb->base;
9728
9729 val = I915_READ(PLANE_CTL(pipe, 0));
9730 if (!(val & PLANE_CTL_ENABLE))
9731 goto error;
9732
9733 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9734 fourcc = skl_format_to_fourcc(pixel_format,
9735 val & PLANE_CTL_ORDER_RGBX,
9736 val & PLANE_CTL_ALPHA_MASK);
9737 fb->pixel_format = fourcc;
9738 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9739
9740 tiling = val & PLANE_CTL_TILED_MASK;
9741 switch (tiling) {
9742 case PLANE_CTL_TILED_LINEAR:
9743 fb->modifier = DRM_FORMAT_MOD_NONE;
9744 break;
9745 case PLANE_CTL_TILED_X:
9746 plane_config->tiling = I915_TILING_X;
9747 fb->modifier = I915_FORMAT_MOD_X_TILED;
9748 break;
9749 case PLANE_CTL_TILED_Y:
9750 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9751 break;
9752 case PLANE_CTL_TILED_YF:
9753 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9754 break;
9755 default:
9756 MISSING_CASE(tiling);
9757 goto error;
9758 }
9759
9760 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9761 plane_config->base = base;
9762
9763 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9764
9765 val = I915_READ(PLANE_SIZE(pipe, 0));
9766 fb->height = ((val >> 16) & 0xfff) + 1;
9767 fb->width = ((val >> 0) & 0x1fff) + 1;
9768
9769 val = I915_READ(PLANE_STRIDE(pipe, 0));
9770 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
9771 fb->pixel_format);
9772 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9773
9774 aligned_height = intel_fb_align_height(dev, fb->height,
9775 fb->pixel_format,
9776 fb->modifier);
9777
9778 plane_config->size = fb->pitches[0] * aligned_height;
9779
9780 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9781 pipe_name(pipe), fb->width, fb->height,
9782 fb->bits_per_pixel, base, fb->pitches[0],
9783 plane_config->size);
9784
9785 plane_config->fb = intel_fb;
9786 return;
9787
9788 error:
9789 kfree(intel_fb);
9790 }
9791
9792 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9793 struct intel_crtc_state *pipe_config)
9794 {
9795 struct drm_device *dev = crtc->base.dev;
9796 struct drm_i915_private *dev_priv = to_i915(dev);
9797 uint32_t tmp;
9798
9799 tmp = I915_READ(PF_CTL(crtc->pipe));
9800
9801 if (tmp & PF_ENABLE) {
9802 pipe_config->pch_pfit.enabled = true;
9803 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9804 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9805
9806 /* We currently do not free assignements of panel fitters on
9807 * ivb/hsw (since we don't use the higher upscaling modes which
9808 * differentiates them) so just WARN about this case for now. */
9809 if (IS_GEN7(dev_priv)) {
9810 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9811 PF_PIPE_SEL_IVB(crtc->pipe));
9812 }
9813 }
9814 }
9815
9816 static void
9817 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9818 struct intel_initial_plane_config *plane_config)
9819 {
9820 struct drm_device *dev = crtc->base.dev;
9821 struct drm_i915_private *dev_priv = to_i915(dev);
9822 u32 val, base, offset;
9823 int pipe = crtc->pipe;
9824 int fourcc, pixel_format;
9825 unsigned int aligned_height;
9826 struct drm_framebuffer *fb;
9827 struct intel_framebuffer *intel_fb;
9828
9829 val = I915_READ(DSPCNTR(pipe));
9830 if (!(val & DISPLAY_PLANE_ENABLE))
9831 return;
9832
9833 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9834 if (!intel_fb) {
9835 DRM_DEBUG_KMS("failed to alloc fb\n");
9836 return;
9837 }
9838
9839 fb = &intel_fb->base;
9840
9841 if (INTEL_GEN(dev_priv) >= 4) {
9842 if (val & DISPPLANE_TILED) {
9843 plane_config->tiling = I915_TILING_X;
9844 fb->modifier = I915_FORMAT_MOD_X_TILED;
9845 }
9846 }
9847
9848 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9849 fourcc = i9xx_format_to_fourcc(pixel_format);
9850 fb->pixel_format = fourcc;
9851 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9852
9853 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9854 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9855 offset = I915_READ(DSPOFFSET(pipe));
9856 } else {
9857 if (plane_config->tiling)
9858 offset = I915_READ(DSPTILEOFF(pipe));
9859 else
9860 offset = I915_READ(DSPLINOFF(pipe));
9861 }
9862 plane_config->base = base;
9863
9864 val = I915_READ(PIPESRC(pipe));
9865 fb->width = ((val >> 16) & 0xfff) + 1;
9866 fb->height = ((val >> 0) & 0xfff) + 1;
9867
9868 val = I915_READ(DSPSTRIDE(pipe));
9869 fb->pitches[0] = val & 0xffffffc0;
9870
9871 aligned_height = intel_fb_align_height(dev, fb->height,
9872 fb->pixel_format,
9873 fb->modifier);
9874
9875 plane_config->size = fb->pitches[0] * aligned_height;
9876
9877 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9878 pipe_name(pipe), fb->width, fb->height,
9879 fb->bits_per_pixel, base, fb->pitches[0],
9880 plane_config->size);
9881
9882 plane_config->fb = intel_fb;
9883 }
9884
9885 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9886 struct intel_crtc_state *pipe_config)
9887 {
9888 struct drm_device *dev = crtc->base.dev;
9889 struct drm_i915_private *dev_priv = to_i915(dev);
9890 enum intel_display_power_domain power_domain;
9891 uint32_t tmp;
9892 bool ret;
9893
9894 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9895 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9896 return false;
9897
9898 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9899 pipe_config->shared_dpll = NULL;
9900
9901 ret = false;
9902 tmp = I915_READ(PIPECONF(crtc->pipe));
9903 if (!(tmp & PIPECONF_ENABLE))
9904 goto out;
9905
9906 switch (tmp & PIPECONF_BPC_MASK) {
9907 case PIPECONF_6BPC:
9908 pipe_config->pipe_bpp = 18;
9909 break;
9910 case PIPECONF_8BPC:
9911 pipe_config->pipe_bpp = 24;
9912 break;
9913 case PIPECONF_10BPC:
9914 pipe_config->pipe_bpp = 30;
9915 break;
9916 case PIPECONF_12BPC:
9917 pipe_config->pipe_bpp = 36;
9918 break;
9919 default:
9920 break;
9921 }
9922
9923 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9924 pipe_config->limited_color_range = true;
9925
9926 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9927 struct intel_shared_dpll *pll;
9928 enum intel_dpll_id pll_id;
9929
9930 pipe_config->has_pch_encoder = true;
9931
9932 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9933 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9934 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9935
9936 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9937
9938 if (HAS_PCH_IBX(dev_priv)) {
9939 /*
9940 * The pipe->pch transcoder and pch transcoder->pll
9941 * mapping is fixed.
9942 */
9943 pll_id = (enum intel_dpll_id) crtc->pipe;
9944 } else {
9945 tmp = I915_READ(PCH_DPLL_SEL);
9946 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9947 pll_id = DPLL_ID_PCH_PLL_B;
9948 else
9949 pll_id= DPLL_ID_PCH_PLL_A;
9950 }
9951
9952 pipe_config->shared_dpll =
9953 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9954 pll = pipe_config->shared_dpll;
9955
9956 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9957 &pipe_config->dpll_hw_state));
9958
9959 tmp = pipe_config->dpll_hw_state.dpll;
9960 pipe_config->pixel_multiplier =
9961 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9962 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9963
9964 ironlake_pch_clock_get(crtc, pipe_config);
9965 } else {
9966 pipe_config->pixel_multiplier = 1;
9967 }
9968
9969 intel_get_pipe_timings(crtc, pipe_config);
9970 intel_get_pipe_src_size(crtc, pipe_config);
9971
9972 ironlake_get_pfit_config(crtc, pipe_config);
9973
9974 ret = true;
9975
9976 out:
9977 intel_display_power_put(dev_priv, power_domain);
9978
9979 return ret;
9980 }
9981
9982 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9983 {
9984 struct drm_device *dev = &dev_priv->drm;
9985 struct intel_crtc *crtc;
9986
9987 for_each_intel_crtc(dev, crtc)
9988 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9989 pipe_name(crtc->pipe));
9990
9991 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9992 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9993 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9994 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9995 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9996 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9997 "CPU PWM1 enabled\n");
9998 if (IS_HASWELL(dev_priv))
9999 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10000 "CPU PWM2 enabled\n");
10001 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10002 "PCH PWM1 enabled\n");
10003 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10004 "Utility pin enabled\n");
10005 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10006
10007 /*
10008 * In theory we can still leave IRQs enabled, as long as only the HPD
10009 * interrupts remain enabled. We used to check for that, but since it's
10010 * gen-specific and since we only disable LCPLL after we fully disable
10011 * the interrupts, the check below should be enough.
10012 */
10013 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10014 }
10015
10016 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10017 {
10018 if (IS_HASWELL(dev_priv))
10019 return I915_READ(D_COMP_HSW);
10020 else
10021 return I915_READ(D_COMP_BDW);
10022 }
10023
10024 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10025 {
10026 if (IS_HASWELL(dev_priv)) {
10027 mutex_lock(&dev_priv->rps.hw_lock);
10028 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10029 val))
10030 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10031 mutex_unlock(&dev_priv->rps.hw_lock);
10032 } else {
10033 I915_WRITE(D_COMP_BDW, val);
10034 POSTING_READ(D_COMP_BDW);
10035 }
10036 }
10037
10038 /*
10039 * This function implements pieces of two sequences from BSpec:
10040 * - Sequence for display software to disable LCPLL
10041 * - Sequence for display software to allow package C8+
10042 * The steps implemented here are just the steps that actually touch the LCPLL
10043 * register. Callers should take care of disabling all the display engine
10044 * functions, doing the mode unset, fixing interrupts, etc.
10045 */
10046 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10047 bool switch_to_fclk, bool allow_power_down)
10048 {
10049 uint32_t val;
10050
10051 assert_can_disable_lcpll(dev_priv);
10052
10053 val = I915_READ(LCPLL_CTL);
10054
10055 if (switch_to_fclk) {
10056 val |= LCPLL_CD_SOURCE_FCLK;
10057 I915_WRITE(LCPLL_CTL, val);
10058
10059 if (wait_for_us(I915_READ(LCPLL_CTL) &
10060 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10061 DRM_ERROR("Switching to FCLK failed\n");
10062
10063 val = I915_READ(LCPLL_CTL);
10064 }
10065
10066 val |= LCPLL_PLL_DISABLE;
10067 I915_WRITE(LCPLL_CTL, val);
10068 POSTING_READ(LCPLL_CTL);
10069
10070 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10071 DRM_ERROR("LCPLL still locked\n");
10072
10073 val = hsw_read_dcomp(dev_priv);
10074 val |= D_COMP_COMP_DISABLE;
10075 hsw_write_dcomp(dev_priv, val);
10076 ndelay(100);
10077
10078 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10079 1))
10080 DRM_ERROR("D_COMP RCOMP still in progress\n");
10081
10082 if (allow_power_down) {
10083 val = I915_READ(LCPLL_CTL);
10084 val |= LCPLL_POWER_DOWN_ALLOW;
10085 I915_WRITE(LCPLL_CTL, val);
10086 POSTING_READ(LCPLL_CTL);
10087 }
10088 }
10089
10090 /*
10091 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10092 * source.
10093 */
10094 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10095 {
10096 uint32_t val;
10097
10098 val = I915_READ(LCPLL_CTL);
10099
10100 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10101 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10102 return;
10103
10104 /*
10105 * Make sure we're not on PC8 state before disabling PC8, otherwise
10106 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10107 */
10108 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10109
10110 if (val & LCPLL_POWER_DOWN_ALLOW) {
10111 val &= ~LCPLL_POWER_DOWN_ALLOW;
10112 I915_WRITE(LCPLL_CTL, val);
10113 POSTING_READ(LCPLL_CTL);
10114 }
10115
10116 val = hsw_read_dcomp(dev_priv);
10117 val |= D_COMP_COMP_FORCE;
10118 val &= ~D_COMP_COMP_DISABLE;
10119 hsw_write_dcomp(dev_priv, val);
10120
10121 val = I915_READ(LCPLL_CTL);
10122 val &= ~LCPLL_PLL_DISABLE;
10123 I915_WRITE(LCPLL_CTL, val);
10124
10125 if (intel_wait_for_register(dev_priv,
10126 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10127 5))
10128 DRM_ERROR("LCPLL not locked yet\n");
10129
10130 if (val & LCPLL_CD_SOURCE_FCLK) {
10131 val = I915_READ(LCPLL_CTL);
10132 val &= ~LCPLL_CD_SOURCE_FCLK;
10133 I915_WRITE(LCPLL_CTL, val);
10134
10135 if (wait_for_us((I915_READ(LCPLL_CTL) &
10136 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10137 DRM_ERROR("Switching back to LCPLL failed\n");
10138 }
10139
10140 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10141 intel_update_cdclk(dev_priv);
10142 }
10143
10144 /*
10145 * Package states C8 and deeper are really deep PC states that can only be
10146 * reached when all the devices on the system allow it, so even if the graphics
10147 * device allows PC8+, it doesn't mean the system will actually get to these
10148 * states. Our driver only allows PC8+ when going into runtime PM.
10149 *
10150 * The requirements for PC8+ are that all the outputs are disabled, the power
10151 * well is disabled and most interrupts are disabled, and these are also
10152 * requirements for runtime PM. When these conditions are met, we manually do
10153 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10154 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10155 * hang the machine.
10156 *
10157 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10158 * the state of some registers, so when we come back from PC8+ we need to
10159 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10160 * need to take care of the registers kept by RC6. Notice that this happens even
10161 * if we don't put the device in PCI D3 state (which is what currently happens
10162 * because of the runtime PM support).
10163 *
10164 * For more, read "Display Sequences for Package C8" on the hardware
10165 * documentation.
10166 */
10167 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10168 {
10169 struct drm_device *dev = &dev_priv->drm;
10170 uint32_t val;
10171
10172 DRM_DEBUG_KMS("Enabling package C8+\n");
10173
10174 if (HAS_PCH_LPT_LP(dev_priv)) {
10175 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10176 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10177 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10178 }
10179
10180 lpt_disable_clkout_dp(dev);
10181 hsw_disable_lcpll(dev_priv, true, true);
10182 }
10183
10184 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10185 {
10186 struct drm_device *dev = &dev_priv->drm;
10187 uint32_t val;
10188
10189 DRM_DEBUG_KMS("Disabling package C8+\n");
10190
10191 hsw_restore_lcpll(dev_priv);
10192 lpt_init_pch_refclk(dev);
10193
10194 if (HAS_PCH_LPT_LP(dev_priv)) {
10195 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10196 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10197 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10198 }
10199 }
10200
10201 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10202 {
10203 struct drm_device *dev = old_state->dev;
10204 struct intel_atomic_state *old_intel_state =
10205 to_intel_atomic_state(old_state);
10206 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10207
10208 bxt_set_cdclk(to_i915(dev), req_cdclk);
10209 }
10210
10211 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10212 int pixel_rate)
10213 {
10214 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10215
10216 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10217 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10218 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10219
10220 /* BSpec says "Do not use DisplayPort with CDCLK less than
10221 * 432 MHz, audio enabled, port width x4, and link rate
10222 * HBR2 (5.4 GHz), or else there may be audio corruption or
10223 * screen corruption."
10224 */
10225 if (intel_crtc_has_dp_encoder(crtc_state) &&
10226 crtc_state->has_audio &&
10227 crtc_state->port_clock >= 540000 &&
10228 crtc_state->lane_count == 4)
10229 pixel_rate = max(432000, pixel_rate);
10230
10231 return pixel_rate;
10232 }
10233
10234 /* compute the max rate for new configuration */
10235 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10236 {
10237 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10238 struct drm_i915_private *dev_priv = to_i915(state->dev);
10239 struct drm_crtc *crtc;
10240 struct drm_crtc_state *cstate;
10241 struct intel_crtc_state *crtc_state;
10242 unsigned max_pixel_rate = 0, i;
10243 enum pipe pipe;
10244
10245 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10246 sizeof(intel_state->min_pixclk));
10247
10248 for_each_crtc_in_state(state, crtc, cstate, i) {
10249 int pixel_rate;
10250
10251 crtc_state = to_intel_crtc_state(cstate);
10252 if (!crtc_state->base.enable) {
10253 intel_state->min_pixclk[i] = 0;
10254 continue;
10255 }
10256
10257 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10258
10259 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10260 pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10261 pixel_rate);
10262
10263 intel_state->min_pixclk[i] = pixel_rate;
10264 }
10265
10266 for_each_pipe(dev_priv, pipe)
10267 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10268
10269 return max_pixel_rate;
10270 }
10271
10272 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10273 {
10274 struct drm_i915_private *dev_priv = to_i915(dev);
10275 uint32_t val, data;
10276 int ret;
10277
10278 if (WARN((I915_READ(LCPLL_CTL) &
10279 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10280 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10281 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10282 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10283 "trying to change cdclk frequency with cdclk not enabled\n"))
10284 return;
10285
10286 mutex_lock(&dev_priv->rps.hw_lock);
10287 ret = sandybridge_pcode_write(dev_priv,
10288 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10289 mutex_unlock(&dev_priv->rps.hw_lock);
10290 if (ret) {
10291 DRM_ERROR("failed to inform pcode about cdclk change\n");
10292 return;
10293 }
10294
10295 val = I915_READ(LCPLL_CTL);
10296 val |= LCPLL_CD_SOURCE_FCLK;
10297 I915_WRITE(LCPLL_CTL, val);
10298
10299 if (wait_for_us(I915_READ(LCPLL_CTL) &
10300 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10301 DRM_ERROR("Switching to FCLK failed\n");
10302
10303 val = I915_READ(LCPLL_CTL);
10304 val &= ~LCPLL_CLK_FREQ_MASK;
10305
10306 switch (cdclk) {
10307 case 450000:
10308 val |= LCPLL_CLK_FREQ_450;
10309 data = 0;
10310 break;
10311 case 540000:
10312 val |= LCPLL_CLK_FREQ_54O_BDW;
10313 data = 1;
10314 break;
10315 case 337500:
10316 val |= LCPLL_CLK_FREQ_337_5_BDW;
10317 data = 2;
10318 break;
10319 case 675000:
10320 val |= LCPLL_CLK_FREQ_675_BDW;
10321 data = 3;
10322 break;
10323 default:
10324 WARN(1, "invalid cdclk frequency\n");
10325 return;
10326 }
10327
10328 I915_WRITE(LCPLL_CTL, val);
10329
10330 val = I915_READ(LCPLL_CTL);
10331 val &= ~LCPLL_CD_SOURCE_FCLK;
10332 I915_WRITE(LCPLL_CTL, val);
10333
10334 if (wait_for_us((I915_READ(LCPLL_CTL) &
10335 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10336 DRM_ERROR("Switching back to LCPLL failed\n");
10337
10338 mutex_lock(&dev_priv->rps.hw_lock);
10339 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10340 mutex_unlock(&dev_priv->rps.hw_lock);
10341
10342 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10343
10344 intel_update_cdclk(dev_priv);
10345
10346 WARN(cdclk != dev_priv->cdclk_freq,
10347 "cdclk requested %d kHz but got %d kHz\n",
10348 cdclk, dev_priv->cdclk_freq);
10349 }
10350
10351 static int broadwell_calc_cdclk(int max_pixclk)
10352 {
10353 if (max_pixclk > 540000)
10354 return 675000;
10355 else if (max_pixclk > 450000)
10356 return 540000;
10357 else if (max_pixclk > 337500)
10358 return 450000;
10359 else
10360 return 337500;
10361 }
10362
10363 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10364 {
10365 struct drm_i915_private *dev_priv = to_i915(state->dev);
10366 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10367 int max_pixclk = ilk_max_pixel_rate(state);
10368 int cdclk;
10369
10370 /*
10371 * FIXME should also account for plane ratio
10372 * once 64bpp pixel formats are supported.
10373 */
10374 cdclk = broadwell_calc_cdclk(max_pixclk);
10375
10376 if (cdclk > dev_priv->max_cdclk_freq) {
10377 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10378 cdclk, dev_priv->max_cdclk_freq);
10379 return -EINVAL;
10380 }
10381
10382 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10383 if (!intel_state->active_crtcs)
10384 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10385
10386 return 0;
10387 }
10388
10389 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10390 {
10391 struct drm_device *dev = old_state->dev;
10392 struct intel_atomic_state *old_intel_state =
10393 to_intel_atomic_state(old_state);
10394 unsigned req_cdclk = old_intel_state->dev_cdclk;
10395
10396 broadwell_set_cdclk(dev, req_cdclk);
10397 }
10398
10399 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10400 {
10401 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10402 struct drm_i915_private *dev_priv = to_i915(state->dev);
10403 const int max_pixclk = ilk_max_pixel_rate(state);
10404 int vco = intel_state->cdclk_pll_vco;
10405 int cdclk;
10406
10407 /*
10408 * FIXME should also account for plane ratio
10409 * once 64bpp pixel formats are supported.
10410 */
10411 cdclk = skl_calc_cdclk(max_pixclk, vco);
10412
10413 /*
10414 * FIXME move the cdclk caclulation to
10415 * compute_config() so we can fail gracegully.
10416 */
10417 if (cdclk > dev_priv->max_cdclk_freq) {
10418 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10419 cdclk, dev_priv->max_cdclk_freq);
10420 cdclk = dev_priv->max_cdclk_freq;
10421 }
10422
10423 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10424 if (!intel_state->active_crtcs)
10425 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10426
10427 return 0;
10428 }
10429
10430 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10431 {
10432 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10433 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10434 unsigned int req_cdclk = intel_state->dev_cdclk;
10435 unsigned int req_vco = intel_state->cdclk_pll_vco;
10436
10437 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10438 }
10439
10440 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10441 struct intel_crtc_state *crtc_state)
10442 {
10443 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10444 if (!intel_ddi_pll_select(crtc, crtc_state))
10445 return -EINVAL;
10446 }
10447
10448 crtc->lowfreq_avail = false;
10449
10450 return 0;
10451 }
10452
10453 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10454 enum port port,
10455 struct intel_crtc_state *pipe_config)
10456 {
10457 enum intel_dpll_id id;
10458
10459 switch (port) {
10460 case PORT_A:
10461 id = DPLL_ID_SKL_DPLL0;
10462 break;
10463 case PORT_B:
10464 id = DPLL_ID_SKL_DPLL1;
10465 break;
10466 case PORT_C:
10467 id = DPLL_ID_SKL_DPLL2;
10468 break;
10469 default:
10470 DRM_ERROR("Incorrect port type\n");
10471 return;
10472 }
10473
10474 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10475 }
10476
10477 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10478 enum port port,
10479 struct intel_crtc_state *pipe_config)
10480 {
10481 enum intel_dpll_id id;
10482 u32 temp;
10483
10484 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10485 id = temp >> (port * 3 + 1);
10486
10487 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10488 return;
10489
10490 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10491 }
10492
10493 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10494 enum port port,
10495 struct intel_crtc_state *pipe_config)
10496 {
10497 enum intel_dpll_id id;
10498 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10499
10500 switch (ddi_pll_sel) {
10501 case PORT_CLK_SEL_WRPLL1:
10502 id = DPLL_ID_WRPLL1;
10503 break;
10504 case PORT_CLK_SEL_WRPLL2:
10505 id = DPLL_ID_WRPLL2;
10506 break;
10507 case PORT_CLK_SEL_SPLL:
10508 id = DPLL_ID_SPLL;
10509 break;
10510 case PORT_CLK_SEL_LCPLL_810:
10511 id = DPLL_ID_LCPLL_810;
10512 break;
10513 case PORT_CLK_SEL_LCPLL_1350:
10514 id = DPLL_ID_LCPLL_1350;
10515 break;
10516 case PORT_CLK_SEL_LCPLL_2700:
10517 id = DPLL_ID_LCPLL_2700;
10518 break;
10519 default:
10520 MISSING_CASE(ddi_pll_sel);
10521 /* fall through */
10522 case PORT_CLK_SEL_NONE:
10523 return;
10524 }
10525
10526 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10527 }
10528
10529 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10530 struct intel_crtc_state *pipe_config,
10531 unsigned long *power_domain_mask)
10532 {
10533 struct drm_device *dev = crtc->base.dev;
10534 struct drm_i915_private *dev_priv = to_i915(dev);
10535 enum intel_display_power_domain power_domain;
10536 u32 tmp;
10537
10538 /*
10539 * The pipe->transcoder mapping is fixed with the exception of the eDP
10540 * transcoder handled below.
10541 */
10542 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10543
10544 /*
10545 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10546 * consistency and less surprising code; it's in always on power).
10547 */
10548 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10549 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10550 enum pipe trans_edp_pipe;
10551 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10552 default:
10553 WARN(1, "unknown pipe linked to edp transcoder\n");
10554 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10555 case TRANS_DDI_EDP_INPUT_A_ON:
10556 trans_edp_pipe = PIPE_A;
10557 break;
10558 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10559 trans_edp_pipe = PIPE_B;
10560 break;
10561 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10562 trans_edp_pipe = PIPE_C;
10563 break;
10564 }
10565
10566 if (trans_edp_pipe == crtc->pipe)
10567 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10568 }
10569
10570 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10571 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10572 return false;
10573 *power_domain_mask |= BIT(power_domain);
10574
10575 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10576
10577 return tmp & PIPECONF_ENABLE;
10578 }
10579
10580 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10581 struct intel_crtc_state *pipe_config,
10582 unsigned long *power_domain_mask)
10583 {
10584 struct drm_device *dev = crtc->base.dev;
10585 struct drm_i915_private *dev_priv = to_i915(dev);
10586 enum intel_display_power_domain power_domain;
10587 enum port port;
10588 enum transcoder cpu_transcoder;
10589 u32 tmp;
10590
10591 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10592 if (port == PORT_A)
10593 cpu_transcoder = TRANSCODER_DSI_A;
10594 else
10595 cpu_transcoder = TRANSCODER_DSI_C;
10596
10597 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10598 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10599 continue;
10600 *power_domain_mask |= BIT(power_domain);
10601
10602 /*
10603 * The PLL needs to be enabled with a valid divider
10604 * configuration, otherwise accessing DSI registers will hang
10605 * the machine. See BSpec North Display Engine
10606 * registers/MIPI[BXT]. We can break out here early, since we
10607 * need the same DSI PLL to be enabled for both DSI ports.
10608 */
10609 if (!intel_dsi_pll_is_enabled(dev_priv))
10610 break;
10611
10612 /* XXX: this works for video mode only */
10613 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10614 if (!(tmp & DPI_ENABLE))
10615 continue;
10616
10617 tmp = I915_READ(MIPI_CTRL(port));
10618 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10619 continue;
10620
10621 pipe_config->cpu_transcoder = cpu_transcoder;
10622 break;
10623 }
10624
10625 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10626 }
10627
10628 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10629 struct intel_crtc_state *pipe_config)
10630 {
10631 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10632 struct intel_shared_dpll *pll;
10633 enum port port;
10634 uint32_t tmp;
10635
10636 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10637
10638 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10639
10640 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
10641 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10642 else if (IS_BROXTON(dev_priv))
10643 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10644 else
10645 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10646
10647 pll = pipe_config->shared_dpll;
10648 if (pll) {
10649 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10650 &pipe_config->dpll_hw_state));
10651 }
10652
10653 /*
10654 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10655 * DDI E. So just check whether this pipe is wired to DDI E and whether
10656 * the PCH transcoder is on.
10657 */
10658 if (INTEL_GEN(dev_priv) < 9 &&
10659 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10660 pipe_config->has_pch_encoder = true;
10661
10662 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10663 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10664 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10665
10666 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10667 }
10668 }
10669
10670 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10671 struct intel_crtc_state *pipe_config)
10672 {
10673 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10674 enum intel_display_power_domain power_domain;
10675 unsigned long power_domain_mask;
10676 bool active;
10677
10678 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10679 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10680 return false;
10681 power_domain_mask = BIT(power_domain);
10682
10683 pipe_config->shared_dpll = NULL;
10684
10685 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10686
10687 if (IS_BROXTON(dev_priv) &&
10688 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10689 WARN_ON(active);
10690 active = true;
10691 }
10692
10693 if (!active)
10694 goto out;
10695
10696 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10697 haswell_get_ddi_port_state(crtc, pipe_config);
10698 intel_get_pipe_timings(crtc, pipe_config);
10699 }
10700
10701 intel_get_pipe_src_size(crtc, pipe_config);
10702
10703 pipe_config->gamma_mode =
10704 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10705
10706 if (INTEL_GEN(dev_priv) >= 9) {
10707 skl_init_scalers(dev_priv, crtc, pipe_config);
10708
10709 pipe_config->scaler_state.scaler_id = -1;
10710 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10711 }
10712
10713 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10714 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10715 power_domain_mask |= BIT(power_domain);
10716 if (INTEL_GEN(dev_priv) >= 9)
10717 skylake_get_pfit_config(crtc, pipe_config);
10718 else
10719 ironlake_get_pfit_config(crtc, pipe_config);
10720 }
10721
10722 if (IS_HASWELL(dev_priv))
10723 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10724 (I915_READ(IPS_CTL) & IPS_ENABLE);
10725
10726 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10727 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10728 pipe_config->pixel_multiplier =
10729 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10730 } else {
10731 pipe_config->pixel_multiplier = 1;
10732 }
10733
10734 out:
10735 for_each_power_domain(power_domain, power_domain_mask)
10736 intel_display_power_put(dev_priv, power_domain);
10737
10738 return active;
10739 }
10740
10741 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10742 const struct intel_plane_state *plane_state)
10743 {
10744 struct drm_device *dev = crtc->dev;
10745 struct drm_i915_private *dev_priv = to_i915(dev);
10746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10747 uint32_t cntl = 0, size = 0;
10748
10749 if (plane_state && plane_state->base.visible) {
10750 unsigned int width = plane_state->base.crtc_w;
10751 unsigned int height = plane_state->base.crtc_h;
10752 unsigned int stride = roundup_pow_of_two(width) * 4;
10753
10754 switch (stride) {
10755 default:
10756 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10757 width, stride);
10758 stride = 256;
10759 /* fallthrough */
10760 case 256:
10761 case 512:
10762 case 1024:
10763 case 2048:
10764 break;
10765 }
10766
10767 cntl |= CURSOR_ENABLE |
10768 CURSOR_GAMMA_ENABLE |
10769 CURSOR_FORMAT_ARGB |
10770 CURSOR_STRIDE(stride);
10771
10772 size = (height << 12) | width;
10773 }
10774
10775 if (intel_crtc->cursor_cntl != 0 &&
10776 (intel_crtc->cursor_base != base ||
10777 intel_crtc->cursor_size != size ||
10778 intel_crtc->cursor_cntl != cntl)) {
10779 /* On these chipsets we can only modify the base/size/stride
10780 * whilst the cursor is disabled.
10781 */
10782 I915_WRITE(CURCNTR(PIPE_A), 0);
10783 POSTING_READ(CURCNTR(PIPE_A));
10784 intel_crtc->cursor_cntl = 0;
10785 }
10786
10787 if (intel_crtc->cursor_base != base) {
10788 I915_WRITE(CURBASE(PIPE_A), base);
10789 intel_crtc->cursor_base = base;
10790 }
10791
10792 if (intel_crtc->cursor_size != size) {
10793 I915_WRITE(CURSIZE, size);
10794 intel_crtc->cursor_size = size;
10795 }
10796
10797 if (intel_crtc->cursor_cntl != cntl) {
10798 I915_WRITE(CURCNTR(PIPE_A), cntl);
10799 POSTING_READ(CURCNTR(PIPE_A));
10800 intel_crtc->cursor_cntl = cntl;
10801 }
10802 }
10803
10804 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10805 const struct intel_plane_state *plane_state)
10806 {
10807 struct drm_device *dev = crtc->dev;
10808 struct drm_i915_private *dev_priv = to_i915(dev);
10809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10810 int pipe = intel_crtc->pipe;
10811 uint32_t cntl = 0;
10812
10813 if (plane_state && plane_state->base.visible) {
10814 cntl = MCURSOR_GAMMA_ENABLE;
10815 switch (plane_state->base.crtc_w) {
10816 case 64:
10817 cntl |= CURSOR_MODE_64_ARGB_AX;
10818 break;
10819 case 128:
10820 cntl |= CURSOR_MODE_128_ARGB_AX;
10821 break;
10822 case 256:
10823 cntl |= CURSOR_MODE_256_ARGB_AX;
10824 break;
10825 default:
10826 MISSING_CASE(plane_state->base.crtc_w);
10827 return;
10828 }
10829 cntl |= pipe << 28; /* Connect to correct pipe */
10830
10831 if (HAS_DDI(dev_priv))
10832 cntl |= CURSOR_PIPE_CSC_ENABLE;
10833
10834 if (plane_state->base.rotation & DRM_ROTATE_180)
10835 cntl |= CURSOR_ROTATE_180;
10836 }
10837
10838 if (intel_crtc->cursor_cntl != cntl) {
10839 I915_WRITE(CURCNTR(pipe), cntl);
10840 POSTING_READ(CURCNTR(pipe));
10841 intel_crtc->cursor_cntl = cntl;
10842 }
10843
10844 /* and commit changes on next vblank */
10845 I915_WRITE(CURBASE(pipe), base);
10846 POSTING_READ(CURBASE(pipe));
10847
10848 intel_crtc->cursor_base = base;
10849 }
10850
10851 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10852 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10853 const struct intel_plane_state *plane_state)
10854 {
10855 struct drm_device *dev = crtc->dev;
10856 struct drm_i915_private *dev_priv = to_i915(dev);
10857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10858 int pipe = intel_crtc->pipe;
10859 u32 base = intel_crtc->cursor_addr;
10860 u32 pos = 0;
10861
10862 if (plane_state) {
10863 int x = plane_state->base.crtc_x;
10864 int y = plane_state->base.crtc_y;
10865
10866 if (x < 0) {
10867 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10868 x = -x;
10869 }
10870 pos |= x << CURSOR_X_SHIFT;
10871
10872 if (y < 0) {
10873 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10874 y = -y;
10875 }
10876 pos |= y << CURSOR_Y_SHIFT;
10877
10878 /* ILK+ do this automagically */
10879 if (HAS_GMCH_DISPLAY(dev_priv) &&
10880 plane_state->base.rotation & DRM_ROTATE_180) {
10881 base += (plane_state->base.crtc_h *
10882 plane_state->base.crtc_w - 1) * 4;
10883 }
10884 }
10885
10886 I915_WRITE(CURPOS(pipe), pos);
10887
10888 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
10889 i845_update_cursor(crtc, base, plane_state);
10890 else
10891 i9xx_update_cursor(crtc, base, plane_state);
10892 }
10893
10894 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
10895 uint32_t width, uint32_t height)
10896 {
10897 if (width == 0 || height == 0)
10898 return false;
10899
10900 /*
10901 * 845g/865g are special in that they are only limited by
10902 * the width of their cursors, the height is arbitrary up to
10903 * the precision of the register. Everything else requires
10904 * square cursors, limited to a few power-of-two sizes.
10905 */
10906 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
10907 if ((width & 63) != 0)
10908 return false;
10909
10910 if (width > (IS_845G(dev_priv) ? 64 : 512))
10911 return false;
10912
10913 if (height > 1023)
10914 return false;
10915 } else {
10916 switch (width | height) {
10917 case 256:
10918 case 128:
10919 if (IS_GEN2(dev_priv))
10920 return false;
10921 case 64:
10922 break;
10923 default:
10924 return false;
10925 }
10926 }
10927
10928 return true;
10929 }
10930
10931 /* VESA 640x480x72Hz mode to set on the pipe */
10932 static struct drm_display_mode load_detect_mode = {
10933 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10934 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10935 };
10936
10937 struct drm_framebuffer *
10938 __intel_framebuffer_create(struct drm_device *dev,
10939 struct drm_mode_fb_cmd2 *mode_cmd,
10940 struct drm_i915_gem_object *obj)
10941 {
10942 struct intel_framebuffer *intel_fb;
10943 int ret;
10944
10945 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10946 if (!intel_fb)
10947 return ERR_PTR(-ENOMEM);
10948
10949 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10950 if (ret)
10951 goto err;
10952
10953 return &intel_fb->base;
10954
10955 err:
10956 kfree(intel_fb);
10957 return ERR_PTR(ret);
10958 }
10959
10960 static struct drm_framebuffer *
10961 intel_framebuffer_create(struct drm_device *dev,
10962 struct drm_mode_fb_cmd2 *mode_cmd,
10963 struct drm_i915_gem_object *obj)
10964 {
10965 struct drm_framebuffer *fb;
10966 int ret;
10967
10968 ret = i915_mutex_lock_interruptible(dev);
10969 if (ret)
10970 return ERR_PTR(ret);
10971 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10972 mutex_unlock(&dev->struct_mutex);
10973
10974 return fb;
10975 }
10976
10977 static u32
10978 intel_framebuffer_pitch_for_width(int width, int bpp)
10979 {
10980 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10981 return ALIGN(pitch, 64);
10982 }
10983
10984 static u32
10985 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10986 {
10987 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10988 return PAGE_ALIGN(pitch * mode->vdisplay);
10989 }
10990
10991 static struct drm_framebuffer *
10992 intel_framebuffer_create_for_mode(struct drm_device *dev,
10993 struct drm_display_mode *mode,
10994 int depth, int bpp)
10995 {
10996 struct drm_framebuffer *fb;
10997 struct drm_i915_gem_object *obj;
10998 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10999
11000 obj = i915_gem_object_create(dev,
11001 intel_framebuffer_size_for_mode(mode, bpp));
11002 if (IS_ERR(obj))
11003 return ERR_CAST(obj);
11004
11005 mode_cmd.width = mode->hdisplay;
11006 mode_cmd.height = mode->vdisplay;
11007 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11008 bpp);
11009 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11010
11011 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11012 if (IS_ERR(fb))
11013 i915_gem_object_put(obj);
11014
11015 return fb;
11016 }
11017
11018 static struct drm_framebuffer *
11019 mode_fits_in_fbdev(struct drm_device *dev,
11020 struct drm_display_mode *mode)
11021 {
11022 #ifdef CONFIG_DRM_FBDEV_EMULATION
11023 struct drm_i915_private *dev_priv = to_i915(dev);
11024 struct drm_i915_gem_object *obj;
11025 struct drm_framebuffer *fb;
11026
11027 if (!dev_priv->fbdev)
11028 return NULL;
11029
11030 if (!dev_priv->fbdev->fb)
11031 return NULL;
11032
11033 obj = dev_priv->fbdev->fb->obj;
11034 BUG_ON(!obj);
11035
11036 fb = &dev_priv->fbdev->fb->base;
11037 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11038 fb->bits_per_pixel))
11039 return NULL;
11040
11041 if (obj->base.size < mode->vdisplay * fb->pitches[0])
11042 return NULL;
11043
11044 drm_framebuffer_reference(fb);
11045 return fb;
11046 #else
11047 return NULL;
11048 #endif
11049 }
11050
11051 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11052 struct drm_crtc *crtc,
11053 struct drm_display_mode *mode,
11054 struct drm_framebuffer *fb,
11055 int x, int y)
11056 {
11057 struct drm_plane_state *plane_state;
11058 int hdisplay, vdisplay;
11059 int ret;
11060
11061 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11062 if (IS_ERR(plane_state))
11063 return PTR_ERR(plane_state);
11064
11065 if (mode)
11066 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11067 else
11068 hdisplay = vdisplay = 0;
11069
11070 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11071 if (ret)
11072 return ret;
11073 drm_atomic_set_fb_for_plane(plane_state, fb);
11074 plane_state->crtc_x = 0;
11075 plane_state->crtc_y = 0;
11076 plane_state->crtc_w = hdisplay;
11077 plane_state->crtc_h = vdisplay;
11078 plane_state->src_x = x << 16;
11079 plane_state->src_y = y << 16;
11080 plane_state->src_w = hdisplay << 16;
11081 plane_state->src_h = vdisplay << 16;
11082
11083 return 0;
11084 }
11085
11086 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11087 struct drm_display_mode *mode,
11088 struct intel_load_detect_pipe *old,
11089 struct drm_modeset_acquire_ctx *ctx)
11090 {
11091 struct intel_crtc *intel_crtc;
11092 struct intel_encoder *intel_encoder =
11093 intel_attached_encoder(connector);
11094 struct drm_crtc *possible_crtc;
11095 struct drm_encoder *encoder = &intel_encoder->base;
11096 struct drm_crtc *crtc = NULL;
11097 struct drm_device *dev = encoder->dev;
11098 struct drm_i915_private *dev_priv = to_i915(dev);
11099 struct drm_framebuffer *fb;
11100 struct drm_mode_config *config = &dev->mode_config;
11101 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11102 struct drm_connector_state *connector_state;
11103 struct intel_crtc_state *crtc_state;
11104 int ret, i = -1;
11105
11106 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11107 connector->base.id, connector->name,
11108 encoder->base.id, encoder->name);
11109
11110 old->restore_state = NULL;
11111
11112 retry:
11113 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11114 if (ret)
11115 goto fail;
11116
11117 /*
11118 * Algorithm gets a little messy:
11119 *
11120 * - if the connector already has an assigned crtc, use it (but make
11121 * sure it's on first)
11122 *
11123 * - try to find the first unused crtc that can drive this connector,
11124 * and use that if we find one
11125 */
11126
11127 /* See if we already have a CRTC for this connector */
11128 if (connector->state->crtc) {
11129 crtc = connector->state->crtc;
11130
11131 ret = drm_modeset_lock(&crtc->mutex, ctx);
11132 if (ret)
11133 goto fail;
11134
11135 /* Make sure the crtc and connector are running */
11136 goto found;
11137 }
11138
11139 /* Find an unused one (if possible) */
11140 for_each_crtc(dev, possible_crtc) {
11141 i++;
11142 if (!(encoder->possible_crtcs & (1 << i)))
11143 continue;
11144
11145 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11146 if (ret)
11147 goto fail;
11148
11149 if (possible_crtc->state->enable) {
11150 drm_modeset_unlock(&possible_crtc->mutex);
11151 continue;
11152 }
11153
11154 crtc = possible_crtc;
11155 break;
11156 }
11157
11158 /*
11159 * If we didn't find an unused CRTC, don't use any.
11160 */
11161 if (!crtc) {
11162 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11163 goto fail;
11164 }
11165
11166 found:
11167 intel_crtc = to_intel_crtc(crtc);
11168
11169 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11170 if (ret)
11171 goto fail;
11172
11173 state = drm_atomic_state_alloc(dev);
11174 restore_state = drm_atomic_state_alloc(dev);
11175 if (!state || !restore_state) {
11176 ret = -ENOMEM;
11177 goto fail;
11178 }
11179
11180 state->acquire_ctx = ctx;
11181 restore_state->acquire_ctx = ctx;
11182
11183 connector_state = drm_atomic_get_connector_state(state, connector);
11184 if (IS_ERR(connector_state)) {
11185 ret = PTR_ERR(connector_state);
11186 goto fail;
11187 }
11188
11189 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11190 if (ret)
11191 goto fail;
11192
11193 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11194 if (IS_ERR(crtc_state)) {
11195 ret = PTR_ERR(crtc_state);
11196 goto fail;
11197 }
11198
11199 crtc_state->base.active = crtc_state->base.enable = true;
11200
11201 if (!mode)
11202 mode = &load_detect_mode;
11203
11204 /* We need a framebuffer large enough to accommodate all accesses
11205 * that the plane may generate whilst we perform load detection.
11206 * We can not rely on the fbcon either being present (we get called
11207 * during its initialisation to detect all boot displays, or it may
11208 * not even exist) or that it is large enough to satisfy the
11209 * requested mode.
11210 */
11211 fb = mode_fits_in_fbdev(dev, mode);
11212 if (fb == NULL) {
11213 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11214 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11215 } else
11216 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11217 if (IS_ERR(fb)) {
11218 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11219 goto fail;
11220 }
11221
11222 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11223 if (ret)
11224 goto fail;
11225
11226 drm_framebuffer_unreference(fb);
11227
11228 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11229 if (ret)
11230 goto fail;
11231
11232 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11233 if (!ret)
11234 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11235 if (!ret)
11236 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11237 if (ret) {
11238 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11239 goto fail;
11240 }
11241
11242 ret = drm_atomic_commit(state);
11243 if (ret) {
11244 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11245 goto fail;
11246 }
11247
11248 old->restore_state = restore_state;
11249 drm_atomic_state_put(state);
11250
11251 /* let the connector get through one full cycle before testing */
11252 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11253 return true;
11254
11255 fail:
11256 if (state) {
11257 drm_atomic_state_put(state);
11258 state = NULL;
11259 }
11260 if (restore_state) {
11261 drm_atomic_state_put(restore_state);
11262 restore_state = NULL;
11263 }
11264
11265 if (ret == -EDEADLK) {
11266 drm_modeset_backoff(ctx);
11267 goto retry;
11268 }
11269
11270 return false;
11271 }
11272
11273 void intel_release_load_detect_pipe(struct drm_connector *connector,
11274 struct intel_load_detect_pipe *old,
11275 struct drm_modeset_acquire_ctx *ctx)
11276 {
11277 struct intel_encoder *intel_encoder =
11278 intel_attached_encoder(connector);
11279 struct drm_encoder *encoder = &intel_encoder->base;
11280 struct drm_atomic_state *state = old->restore_state;
11281 int ret;
11282
11283 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11284 connector->base.id, connector->name,
11285 encoder->base.id, encoder->name);
11286
11287 if (!state)
11288 return;
11289
11290 ret = drm_atomic_commit(state);
11291 if (ret)
11292 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11293 drm_atomic_state_put(state);
11294 }
11295
11296 static int i9xx_pll_refclk(struct drm_device *dev,
11297 const struct intel_crtc_state *pipe_config)
11298 {
11299 struct drm_i915_private *dev_priv = to_i915(dev);
11300 u32 dpll = pipe_config->dpll_hw_state.dpll;
11301
11302 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11303 return dev_priv->vbt.lvds_ssc_freq;
11304 else if (HAS_PCH_SPLIT(dev_priv))
11305 return 120000;
11306 else if (!IS_GEN2(dev_priv))
11307 return 96000;
11308 else
11309 return 48000;
11310 }
11311
11312 /* Returns the clock of the currently programmed mode of the given pipe. */
11313 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11314 struct intel_crtc_state *pipe_config)
11315 {
11316 struct drm_device *dev = crtc->base.dev;
11317 struct drm_i915_private *dev_priv = to_i915(dev);
11318 int pipe = pipe_config->cpu_transcoder;
11319 u32 dpll = pipe_config->dpll_hw_state.dpll;
11320 u32 fp;
11321 struct dpll clock;
11322 int port_clock;
11323 int refclk = i9xx_pll_refclk(dev, pipe_config);
11324
11325 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11326 fp = pipe_config->dpll_hw_state.fp0;
11327 else
11328 fp = pipe_config->dpll_hw_state.fp1;
11329
11330 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11331 if (IS_PINEVIEW(dev_priv)) {
11332 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11333 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11334 } else {
11335 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11336 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11337 }
11338
11339 if (!IS_GEN2(dev_priv)) {
11340 if (IS_PINEVIEW(dev_priv))
11341 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11342 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11343 else
11344 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11345 DPLL_FPA01_P1_POST_DIV_SHIFT);
11346
11347 switch (dpll & DPLL_MODE_MASK) {
11348 case DPLLB_MODE_DAC_SERIAL:
11349 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11350 5 : 10;
11351 break;
11352 case DPLLB_MODE_LVDS:
11353 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11354 7 : 14;
11355 break;
11356 default:
11357 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11358 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11359 return;
11360 }
11361
11362 if (IS_PINEVIEW(dev_priv))
11363 port_clock = pnv_calc_dpll_params(refclk, &clock);
11364 else
11365 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11366 } else {
11367 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11368 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11369
11370 if (is_lvds) {
11371 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11372 DPLL_FPA01_P1_POST_DIV_SHIFT);
11373
11374 if (lvds & LVDS_CLKB_POWER_UP)
11375 clock.p2 = 7;
11376 else
11377 clock.p2 = 14;
11378 } else {
11379 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11380 clock.p1 = 2;
11381 else {
11382 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11383 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11384 }
11385 if (dpll & PLL_P2_DIVIDE_BY_4)
11386 clock.p2 = 4;
11387 else
11388 clock.p2 = 2;
11389 }
11390
11391 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11392 }
11393
11394 /*
11395 * This value includes pixel_multiplier. We will use
11396 * port_clock to compute adjusted_mode.crtc_clock in the
11397 * encoder's get_config() function.
11398 */
11399 pipe_config->port_clock = port_clock;
11400 }
11401
11402 int intel_dotclock_calculate(int link_freq,
11403 const struct intel_link_m_n *m_n)
11404 {
11405 /*
11406 * The calculation for the data clock is:
11407 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11408 * But we want to avoid losing precison if possible, so:
11409 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11410 *
11411 * and the link clock is simpler:
11412 * link_clock = (m * link_clock) / n
11413 */
11414
11415 if (!m_n->link_n)
11416 return 0;
11417
11418 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11419 }
11420
11421 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11422 struct intel_crtc_state *pipe_config)
11423 {
11424 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11425
11426 /* read out port_clock from the DPLL */
11427 i9xx_crtc_clock_get(crtc, pipe_config);
11428
11429 /*
11430 * In case there is an active pipe without active ports,
11431 * we may need some idea for the dotclock anyway.
11432 * Calculate one based on the FDI configuration.
11433 */
11434 pipe_config->base.adjusted_mode.crtc_clock =
11435 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11436 &pipe_config->fdi_m_n);
11437 }
11438
11439 /** Returns the currently programmed mode of the given pipe. */
11440 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11441 struct drm_crtc *crtc)
11442 {
11443 struct drm_i915_private *dev_priv = to_i915(dev);
11444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11445 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11446 struct drm_display_mode *mode;
11447 struct intel_crtc_state *pipe_config;
11448 int htot = I915_READ(HTOTAL(cpu_transcoder));
11449 int hsync = I915_READ(HSYNC(cpu_transcoder));
11450 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11451 int vsync = I915_READ(VSYNC(cpu_transcoder));
11452 enum pipe pipe = intel_crtc->pipe;
11453
11454 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11455 if (!mode)
11456 return NULL;
11457
11458 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11459 if (!pipe_config) {
11460 kfree(mode);
11461 return NULL;
11462 }
11463
11464 /*
11465 * Construct a pipe_config sufficient for getting the clock info
11466 * back out of crtc_clock_get.
11467 *
11468 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11469 * to use a real value here instead.
11470 */
11471 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11472 pipe_config->pixel_multiplier = 1;
11473 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11474 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11475 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11476 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11477
11478 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11479 mode->hdisplay = (htot & 0xffff) + 1;
11480 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11481 mode->hsync_start = (hsync & 0xffff) + 1;
11482 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11483 mode->vdisplay = (vtot & 0xffff) + 1;
11484 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11485 mode->vsync_start = (vsync & 0xffff) + 1;
11486 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11487
11488 drm_mode_set_name(mode);
11489
11490 kfree(pipe_config);
11491
11492 return mode;
11493 }
11494
11495 static void intel_crtc_destroy(struct drm_crtc *crtc)
11496 {
11497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11498 struct drm_device *dev = crtc->dev;
11499 struct intel_flip_work *work;
11500
11501 spin_lock_irq(&dev->event_lock);
11502 work = intel_crtc->flip_work;
11503 intel_crtc->flip_work = NULL;
11504 spin_unlock_irq(&dev->event_lock);
11505
11506 if (work) {
11507 cancel_work_sync(&work->mmio_work);
11508 cancel_work_sync(&work->unpin_work);
11509 kfree(work);
11510 }
11511
11512 drm_crtc_cleanup(crtc);
11513
11514 kfree(intel_crtc);
11515 }
11516
11517 static void intel_unpin_work_fn(struct work_struct *__work)
11518 {
11519 struct intel_flip_work *work =
11520 container_of(__work, struct intel_flip_work, unpin_work);
11521 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11522 struct drm_device *dev = crtc->base.dev;
11523 struct drm_plane *primary = crtc->base.primary;
11524
11525 if (is_mmio_work(work))
11526 flush_work(&work->mmio_work);
11527
11528 mutex_lock(&dev->struct_mutex);
11529 intel_unpin_fb_vma(work->old_vma);
11530 i915_gem_object_put(work->pending_flip_obj);
11531 mutex_unlock(&dev->struct_mutex);
11532
11533 i915_gem_request_put(work->flip_queued_req);
11534
11535 intel_frontbuffer_flip_complete(to_i915(dev),
11536 to_intel_plane(primary)->frontbuffer_bit);
11537 intel_fbc_post_update(crtc);
11538 drm_framebuffer_unreference(work->old_fb);
11539
11540 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11541 atomic_dec(&crtc->unpin_work_count);
11542
11543 kfree(work);
11544 }
11545
11546 /* Is 'a' after or equal to 'b'? */
11547 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11548 {
11549 return !((a - b) & 0x80000000);
11550 }
11551
11552 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11553 struct intel_flip_work *work)
11554 {
11555 struct drm_device *dev = crtc->base.dev;
11556 struct drm_i915_private *dev_priv = to_i915(dev);
11557
11558 if (abort_flip_on_reset(crtc))
11559 return true;
11560
11561 /*
11562 * The relevant registers doen't exist on pre-ctg.
11563 * As the flip done interrupt doesn't trigger for mmio
11564 * flips on gmch platforms, a flip count check isn't
11565 * really needed there. But since ctg has the registers,
11566 * include it in the check anyway.
11567 */
11568 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11569 return true;
11570
11571 /*
11572 * BDW signals flip done immediately if the plane
11573 * is disabled, even if the plane enable is already
11574 * armed to occur at the next vblank :(
11575 */
11576
11577 /*
11578 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11579 * used the same base address. In that case the mmio flip might
11580 * have completed, but the CS hasn't even executed the flip yet.
11581 *
11582 * A flip count check isn't enough as the CS might have updated
11583 * the base address just after start of vblank, but before we
11584 * managed to process the interrupt. This means we'd complete the
11585 * CS flip too soon.
11586 *
11587 * Combining both checks should get us a good enough result. It may
11588 * still happen that the CS flip has been executed, but has not
11589 * yet actually completed. But in case the base address is the same
11590 * anyway, we don't really care.
11591 */
11592 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11593 crtc->flip_work->gtt_offset &&
11594 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11595 crtc->flip_work->flip_count);
11596 }
11597
11598 static bool
11599 __pageflip_finished_mmio(struct intel_crtc *crtc,
11600 struct intel_flip_work *work)
11601 {
11602 /*
11603 * MMIO work completes when vblank is different from
11604 * flip_queued_vblank.
11605 *
11606 * Reset counter value doesn't matter, this is handled by
11607 * i915_wait_request finishing early, so no need to handle
11608 * reset here.
11609 */
11610 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11611 }
11612
11613
11614 static bool pageflip_finished(struct intel_crtc *crtc,
11615 struct intel_flip_work *work)
11616 {
11617 if (!atomic_read(&work->pending))
11618 return false;
11619
11620 smp_rmb();
11621
11622 if (is_mmio_work(work))
11623 return __pageflip_finished_mmio(crtc, work);
11624 else
11625 return __pageflip_finished_cs(crtc, work);
11626 }
11627
11628 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11629 {
11630 struct drm_device *dev = &dev_priv->drm;
11631 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11632 struct intel_flip_work *work;
11633 unsigned long flags;
11634
11635 /* Ignore early vblank irqs */
11636 if (!crtc)
11637 return;
11638
11639 /*
11640 * This is called both by irq handlers and the reset code (to complete
11641 * lost pageflips) so needs the full irqsave spinlocks.
11642 */
11643 spin_lock_irqsave(&dev->event_lock, flags);
11644 work = crtc->flip_work;
11645
11646 if (work != NULL &&
11647 !is_mmio_work(work) &&
11648 pageflip_finished(crtc, work))
11649 page_flip_completed(crtc);
11650
11651 spin_unlock_irqrestore(&dev->event_lock, flags);
11652 }
11653
11654 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11655 {
11656 struct drm_device *dev = &dev_priv->drm;
11657 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11658 struct intel_flip_work *work;
11659 unsigned long flags;
11660
11661 /* Ignore early vblank irqs */
11662 if (!crtc)
11663 return;
11664
11665 /*
11666 * This is called both by irq handlers and the reset code (to complete
11667 * lost pageflips) so needs the full irqsave spinlocks.
11668 */
11669 spin_lock_irqsave(&dev->event_lock, flags);
11670 work = crtc->flip_work;
11671
11672 if (work != NULL &&
11673 is_mmio_work(work) &&
11674 pageflip_finished(crtc, work))
11675 page_flip_completed(crtc);
11676
11677 spin_unlock_irqrestore(&dev->event_lock, flags);
11678 }
11679
11680 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11681 struct intel_flip_work *work)
11682 {
11683 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11684
11685 /* Ensure that the work item is consistent when activating it ... */
11686 smp_mb__before_atomic();
11687 atomic_set(&work->pending, 1);
11688 }
11689
11690 static int intel_gen2_queue_flip(struct drm_device *dev,
11691 struct drm_crtc *crtc,
11692 struct drm_framebuffer *fb,
11693 struct drm_i915_gem_object *obj,
11694 struct drm_i915_gem_request *req,
11695 uint32_t flags)
11696 {
11697 struct intel_ring *ring = req->ring;
11698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11699 u32 flip_mask;
11700 int ret;
11701
11702 ret = intel_ring_begin(req, 6);
11703 if (ret)
11704 return ret;
11705
11706 /* Can't queue multiple flips, so wait for the previous
11707 * one to finish before executing the next.
11708 */
11709 if (intel_crtc->plane)
11710 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11711 else
11712 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11713 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11714 intel_ring_emit(ring, MI_NOOP);
11715 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11716 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11717 intel_ring_emit(ring, fb->pitches[0]);
11718 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11719 intel_ring_emit(ring, 0); /* aux display base address, unused */
11720
11721 return 0;
11722 }
11723
11724 static int intel_gen3_queue_flip(struct drm_device *dev,
11725 struct drm_crtc *crtc,
11726 struct drm_framebuffer *fb,
11727 struct drm_i915_gem_object *obj,
11728 struct drm_i915_gem_request *req,
11729 uint32_t flags)
11730 {
11731 struct intel_ring *ring = req->ring;
11732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11733 u32 flip_mask;
11734 int ret;
11735
11736 ret = intel_ring_begin(req, 6);
11737 if (ret)
11738 return ret;
11739
11740 if (intel_crtc->plane)
11741 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11742 else
11743 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11744 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11745 intel_ring_emit(ring, MI_NOOP);
11746 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11747 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11748 intel_ring_emit(ring, fb->pitches[0]);
11749 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11750 intel_ring_emit(ring, MI_NOOP);
11751
11752 return 0;
11753 }
11754
11755 static int intel_gen4_queue_flip(struct drm_device *dev,
11756 struct drm_crtc *crtc,
11757 struct drm_framebuffer *fb,
11758 struct drm_i915_gem_object *obj,
11759 struct drm_i915_gem_request *req,
11760 uint32_t flags)
11761 {
11762 struct intel_ring *ring = req->ring;
11763 struct drm_i915_private *dev_priv = to_i915(dev);
11764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11765 uint32_t pf, pipesrc;
11766 int ret;
11767
11768 ret = intel_ring_begin(req, 4);
11769 if (ret)
11770 return ret;
11771
11772 /* i965+ uses the linear or tiled offsets from the
11773 * Display Registers (which do not change across a page-flip)
11774 * so we need only reprogram the base address.
11775 */
11776 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11777 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11778 intel_ring_emit(ring, fb->pitches[0]);
11779 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11780 intel_fb_modifier_to_tiling(fb->modifier));
11781
11782 /* XXX Enabling the panel-fitter across page-flip is so far
11783 * untested on non-native modes, so ignore it for now.
11784 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11785 */
11786 pf = 0;
11787 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11788 intel_ring_emit(ring, pf | pipesrc);
11789
11790 return 0;
11791 }
11792
11793 static int intel_gen6_queue_flip(struct drm_device *dev,
11794 struct drm_crtc *crtc,
11795 struct drm_framebuffer *fb,
11796 struct drm_i915_gem_object *obj,
11797 struct drm_i915_gem_request *req,
11798 uint32_t flags)
11799 {
11800 struct intel_ring *ring = req->ring;
11801 struct drm_i915_private *dev_priv = to_i915(dev);
11802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11803 uint32_t pf, pipesrc;
11804 int ret;
11805
11806 ret = intel_ring_begin(req, 4);
11807 if (ret)
11808 return ret;
11809
11810 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11811 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11812 intel_ring_emit(ring, fb->pitches[0] |
11813 intel_fb_modifier_to_tiling(fb->modifier));
11814 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11815
11816 /* Contrary to the suggestions in the documentation,
11817 * "Enable Panel Fitter" does not seem to be required when page
11818 * flipping with a non-native mode, and worse causes a normal
11819 * modeset to fail.
11820 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11821 */
11822 pf = 0;
11823 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11824 intel_ring_emit(ring, pf | pipesrc);
11825
11826 return 0;
11827 }
11828
11829 static int intel_gen7_queue_flip(struct drm_device *dev,
11830 struct drm_crtc *crtc,
11831 struct drm_framebuffer *fb,
11832 struct drm_i915_gem_object *obj,
11833 struct drm_i915_gem_request *req,
11834 uint32_t flags)
11835 {
11836 struct drm_i915_private *dev_priv = to_i915(dev);
11837 struct intel_ring *ring = req->ring;
11838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11839 uint32_t plane_bit = 0;
11840 int len, ret;
11841
11842 switch (intel_crtc->plane) {
11843 case PLANE_A:
11844 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11845 break;
11846 case PLANE_B:
11847 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11848 break;
11849 case PLANE_C:
11850 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11851 break;
11852 default:
11853 WARN_ONCE(1, "unknown plane in flip command\n");
11854 return -ENODEV;
11855 }
11856
11857 len = 4;
11858 if (req->engine->id == RCS) {
11859 len += 6;
11860 /*
11861 * On Gen 8, SRM is now taking an extra dword to accommodate
11862 * 48bits addresses, and we need a NOOP for the batch size to
11863 * stay even.
11864 */
11865 if (IS_GEN8(dev_priv))
11866 len += 2;
11867 }
11868
11869 /*
11870 * BSpec MI_DISPLAY_FLIP for IVB:
11871 * "The full packet must be contained within the same cache line."
11872 *
11873 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11874 * cacheline, if we ever start emitting more commands before
11875 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11876 * then do the cacheline alignment, and finally emit the
11877 * MI_DISPLAY_FLIP.
11878 */
11879 ret = intel_ring_cacheline_align(req);
11880 if (ret)
11881 return ret;
11882
11883 ret = intel_ring_begin(req, len);
11884 if (ret)
11885 return ret;
11886
11887 /* Unmask the flip-done completion message. Note that the bspec says that
11888 * we should do this for both the BCS and RCS, and that we must not unmask
11889 * more than one flip event at any time (or ensure that one flip message
11890 * can be sent by waiting for flip-done prior to queueing new flips).
11891 * Experimentation says that BCS works despite DERRMR masking all
11892 * flip-done completion events and that unmasking all planes at once
11893 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11894 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11895 */
11896 if (req->engine->id == RCS) {
11897 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11898 intel_ring_emit_reg(ring, DERRMR);
11899 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11900 DERRMR_PIPEB_PRI_FLIP_DONE |
11901 DERRMR_PIPEC_PRI_FLIP_DONE));
11902 if (IS_GEN8(dev_priv))
11903 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11904 MI_SRM_LRM_GLOBAL_GTT);
11905 else
11906 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11907 MI_SRM_LRM_GLOBAL_GTT);
11908 intel_ring_emit_reg(ring, DERRMR);
11909 intel_ring_emit(ring,
11910 i915_ggtt_offset(req->engine->scratch) + 256);
11911 if (IS_GEN8(dev_priv)) {
11912 intel_ring_emit(ring, 0);
11913 intel_ring_emit(ring, MI_NOOP);
11914 }
11915 }
11916
11917 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11918 intel_ring_emit(ring, fb->pitches[0] |
11919 intel_fb_modifier_to_tiling(fb->modifier));
11920 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11921 intel_ring_emit(ring, (MI_NOOP));
11922
11923 return 0;
11924 }
11925
11926 static bool use_mmio_flip(struct intel_engine_cs *engine,
11927 struct drm_i915_gem_object *obj)
11928 {
11929 /*
11930 * This is not being used for older platforms, because
11931 * non-availability of flip done interrupt forces us to use
11932 * CS flips. Older platforms derive flip done using some clever
11933 * tricks involving the flip_pending status bits and vblank irqs.
11934 * So using MMIO flips there would disrupt this mechanism.
11935 */
11936
11937 if (engine == NULL)
11938 return true;
11939
11940 if (INTEL_GEN(engine->i915) < 5)
11941 return false;
11942
11943 if (i915.use_mmio_flip < 0)
11944 return false;
11945 else if (i915.use_mmio_flip > 0)
11946 return true;
11947 else if (i915.enable_execlists)
11948 return true;
11949
11950 return engine != i915_gem_object_last_write_engine(obj);
11951 }
11952
11953 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11954 unsigned int rotation,
11955 struct intel_flip_work *work)
11956 {
11957 struct drm_device *dev = intel_crtc->base.dev;
11958 struct drm_i915_private *dev_priv = to_i915(dev);
11959 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11960 const enum pipe pipe = intel_crtc->pipe;
11961 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11962
11963 ctl = I915_READ(PLANE_CTL(pipe, 0));
11964 ctl &= ~PLANE_CTL_TILED_MASK;
11965 switch (fb->modifier) {
11966 case DRM_FORMAT_MOD_NONE:
11967 break;
11968 case I915_FORMAT_MOD_X_TILED:
11969 ctl |= PLANE_CTL_TILED_X;
11970 break;
11971 case I915_FORMAT_MOD_Y_TILED:
11972 ctl |= PLANE_CTL_TILED_Y;
11973 break;
11974 case I915_FORMAT_MOD_Yf_TILED:
11975 ctl |= PLANE_CTL_TILED_YF;
11976 break;
11977 default:
11978 MISSING_CASE(fb->modifier);
11979 }
11980
11981 /*
11982 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11983 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11984 */
11985 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11986 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11987
11988 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11989 POSTING_READ(PLANE_SURF(pipe, 0));
11990 }
11991
11992 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11993 struct intel_flip_work *work)
11994 {
11995 struct drm_device *dev = intel_crtc->base.dev;
11996 struct drm_i915_private *dev_priv = to_i915(dev);
11997 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11998 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11999 u32 dspcntr;
12000
12001 dspcntr = I915_READ(reg);
12002
12003 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12004 dspcntr |= DISPPLANE_TILED;
12005 else
12006 dspcntr &= ~DISPPLANE_TILED;
12007
12008 I915_WRITE(reg, dspcntr);
12009
12010 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12011 POSTING_READ(DSPSURF(intel_crtc->plane));
12012 }
12013
12014 static void intel_mmio_flip_work_func(struct work_struct *w)
12015 {
12016 struct intel_flip_work *work =
12017 container_of(w, struct intel_flip_work, mmio_work);
12018 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12020 struct intel_framebuffer *intel_fb =
12021 to_intel_framebuffer(crtc->base.primary->fb);
12022 struct drm_i915_gem_object *obj = intel_fb->obj;
12023
12024 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
12025
12026 intel_pipe_update_start(crtc);
12027
12028 if (INTEL_GEN(dev_priv) >= 9)
12029 skl_do_mmio_flip(crtc, work->rotation, work);
12030 else
12031 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12032 ilk_do_mmio_flip(crtc, work);
12033
12034 intel_pipe_update_end(crtc, work);
12035 }
12036
12037 static int intel_default_queue_flip(struct drm_device *dev,
12038 struct drm_crtc *crtc,
12039 struct drm_framebuffer *fb,
12040 struct drm_i915_gem_object *obj,
12041 struct drm_i915_gem_request *req,
12042 uint32_t flags)
12043 {
12044 return -ENODEV;
12045 }
12046
12047 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12048 struct intel_crtc *intel_crtc,
12049 struct intel_flip_work *work)
12050 {
12051 u32 addr, vblank;
12052
12053 if (!atomic_read(&work->pending))
12054 return false;
12055
12056 smp_rmb();
12057
12058 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12059 if (work->flip_ready_vblank == 0) {
12060 if (work->flip_queued_req &&
12061 !i915_gem_request_completed(work->flip_queued_req))
12062 return false;
12063
12064 work->flip_ready_vblank = vblank;
12065 }
12066
12067 if (vblank - work->flip_ready_vblank < 3)
12068 return false;
12069
12070 /* Potential stall - if we see that the flip has happened,
12071 * assume a missed interrupt. */
12072 if (INTEL_GEN(dev_priv) >= 4)
12073 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12074 else
12075 addr = I915_READ(DSPADDR(intel_crtc->plane));
12076
12077 /* There is a potential issue here with a false positive after a flip
12078 * to the same address. We could address this by checking for a
12079 * non-incrementing frame counter.
12080 */
12081 return addr == work->gtt_offset;
12082 }
12083
12084 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12085 {
12086 struct drm_device *dev = &dev_priv->drm;
12087 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12088 struct intel_flip_work *work;
12089
12090 WARN_ON(!in_interrupt());
12091
12092 if (crtc == NULL)
12093 return;
12094
12095 spin_lock(&dev->event_lock);
12096 work = crtc->flip_work;
12097
12098 if (work != NULL && !is_mmio_work(work) &&
12099 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
12100 WARN_ONCE(1,
12101 "Kicking stuck page flip: queued at %d, now %d\n",
12102 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
12103 page_flip_completed(crtc);
12104 work = NULL;
12105 }
12106
12107 if (work != NULL && !is_mmio_work(work) &&
12108 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
12109 intel_queue_rps_boost_for_request(work->flip_queued_req);
12110 spin_unlock(&dev->event_lock);
12111 }
12112
12113 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12114 struct drm_framebuffer *fb,
12115 struct drm_pending_vblank_event *event,
12116 uint32_t page_flip_flags)
12117 {
12118 struct drm_device *dev = crtc->dev;
12119 struct drm_i915_private *dev_priv = to_i915(dev);
12120 struct drm_framebuffer *old_fb = crtc->primary->fb;
12121 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12123 struct drm_plane *primary = crtc->primary;
12124 enum pipe pipe = intel_crtc->pipe;
12125 struct intel_flip_work *work;
12126 struct intel_engine_cs *engine;
12127 bool mmio_flip;
12128 struct drm_i915_gem_request *request;
12129 struct i915_vma *vma;
12130 int ret;
12131
12132 /*
12133 * drm_mode_page_flip_ioctl() should already catch this, but double
12134 * check to be safe. In the future we may enable pageflipping from
12135 * a disabled primary plane.
12136 */
12137 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12138 return -EBUSY;
12139
12140 /* Can't change pixel format via MI display flips. */
12141 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12142 return -EINVAL;
12143
12144 /*
12145 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12146 * Note that pitch changes could also affect these register.
12147 */
12148 if (INTEL_GEN(dev_priv) > 3 &&
12149 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12150 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12151 return -EINVAL;
12152
12153 if (i915_terminally_wedged(&dev_priv->gpu_error))
12154 goto out_hang;
12155
12156 work = kzalloc(sizeof(*work), GFP_KERNEL);
12157 if (work == NULL)
12158 return -ENOMEM;
12159
12160 work->event = event;
12161 work->crtc = crtc;
12162 work->old_fb = old_fb;
12163 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12164
12165 ret = drm_crtc_vblank_get(crtc);
12166 if (ret)
12167 goto free_work;
12168
12169 /* We borrow the event spin lock for protecting flip_work */
12170 spin_lock_irq(&dev->event_lock);
12171 if (intel_crtc->flip_work) {
12172 /* Before declaring the flip queue wedged, check if
12173 * the hardware completed the operation behind our backs.
12174 */
12175 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12176 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12177 page_flip_completed(intel_crtc);
12178 } else {
12179 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12180 spin_unlock_irq(&dev->event_lock);
12181
12182 drm_crtc_vblank_put(crtc);
12183 kfree(work);
12184 return -EBUSY;
12185 }
12186 }
12187 intel_crtc->flip_work = work;
12188 spin_unlock_irq(&dev->event_lock);
12189
12190 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12191 flush_workqueue(dev_priv->wq);
12192
12193 /* Reference the objects for the scheduled work. */
12194 drm_framebuffer_reference(work->old_fb);
12195
12196 crtc->primary->fb = fb;
12197 update_state_fb(crtc->primary);
12198
12199 work->pending_flip_obj = i915_gem_object_get(obj);
12200
12201 ret = i915_mutex_lock_interruptible(dev);
12202 if (ret)
12203 goto cleanup;
12204
12205 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12206 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12207 ret = -EIO;
12208 goto unlock;
12209 }
12210
12211 atomic_inc(&intel_crtc->unpin_work_count);
12212
12213 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12214 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12215
12216 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
12217 engine = dev_priv->engine[BCS];
12218 if (fb->modifier != old_fb->modifier)
12219 /* vlv: DISPLAY_FLIP fails to change tiling */
12220 engine = NULL;
12221 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
12222 engine = dev_priv->engine[BCS];
12223 } else if (INTEL_GEN(dev_priv) >= 7) {
12224 engine = i915_gem_object_last_write_engine(obj);
12225 if (engine == NULL || engine->id != RCS)
12226 engine = dev_priv->engine[BCS];
12227 } else {
12228 engine = dev_priv->engine[RCS];
12229 }
12230
12231 mmio_flip = use_mmio_flip(engine, obj);
12232
12233 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12234 if (IS_ERR(vma)) {
12235 ret = PTR_ERR(vma);
12236 goto cleanup_pending;
12237 }
12238
12239 work->old_vma = to_intel_plane_state(primary->state)->vma;
12240 to_intel_plane_state(primary->state)->vma = vma;
12241
12242 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
12243 work->rotation = crtc->primary->state->rotation;
12244
12245 /*
12246 * There's the potential that the next frame will not be compatible with
12247 * FBC, so we want to call pre_update() before the actual page flip.
12248 * The problem is that pre_update() caches some information about the fb
12249 * object, so we want to do this only after the object is pinned. Let's
12250 * be on the safe side and do this immediately before scheduling the
12251 * flip.
12252 */
12253 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12254 to_intel_plane_state(primary->state));
12255
12256 if (mmio_flip) {
12257 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12258 queue_work(system_unbound_wq, &work->mmio_work);
12259 } else {
12260 request = i915_gem_request_alloc(engine, engine->last_context);
12261 if (IS_ERR(request)) {
12262 ret = PTR_ERR(request);
12263 goto cleanup_unpin;
12264 }
12265
12266 ret = i915_gem_request_await_object(request, obj, false);
12267 if (ret)
12268 goto cleanup_request;
12269
12270 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12271 page_flip_flags);
12272 if (ret)
12273 goto cleanup_request;
12274
12275 intel_mark_page_flip_active(intel_crtc, work);
12276
12277 work->flip_queued_req = i915_gem_request_get(request);
12278 i915_add_request_no_flush(request);
12279 }
12280
12281 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12282 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12283 to_intel_plane(primary)->frontbuffer_bit);
12284 mutex_unlock(&dev->struct_mutex);
12285
12286 intel_frontbuffer_flip_prepare(to_i915(dev),
12287 to_intel_plane(primary)->frontbuffer_bit);
12288
12289 trace_i915_flip_request(intel_crtc->plane, obj);
12290
12291 return 0;
12292
12293 cleanup_request:
12294 i915_add_request_no_flush(request);
12295 cleanup_unpin:
12296 to_intel_plane_state(primary->state)->vma = work->old_vma;
12297 intel_unpin_fb_vma(vma);
12298 cleanup_pending:
12299 atomic_dec(&intel_crtc->unpin_work_count);
12300 unlock:
12301 mutex_unlock(&dev->struct_mutex);
12302 cleanup:
12303 crtc->primary->fb = old_fb;
12304 update_state_fb(crtc->primary);
12305
12306 i915_gem_object_put(obj);
12307 drm_framebuffer_unreference(work->old_fb);
12308
12309 spin_lock_irq(&dev->event_lock);
12310 intel_crtc->flip_work = NULL;
12311 spin_unlock_irq(&dev->event_lock);
12312
12313 drm_crtc_vblank_put(crtc);
12314 free_work:
12315 kfree(work);
12316
12317 if (ret == -EIO) {
12318 struct drm_atomic_state *state;
12319 struct drm_plane_state *plane_state;
12320
12321 out_hang:
12322 state = drm_atomic_state_alloc(dev);
12323 if (!state)
12324 return -ENOMEM;
12325 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12326
12327 retry:
12328 plane_state = drm_atomic_get_plane_state(state, primary);
12329 ret = PTR_ERR_OR_ZERO(plane_state);
12330 if (!ret) {
12331 drm_atomic_set_fb_for_plane(plane_state, fb);
12332
12333 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12334 if (!ret)
12335 ret = drm_atomic_commit(state);
12336 }
12337
12338 if (ret == -EDEADLK) {
12339 drm_modeset_backoff(state->acquire_ctx);
12340 drm_atomic_state_clear(state);
12341 goto retry;
12342 }
12343
12344 drm_atomic_state_put(state);
12345
12346 if (ret == 0 && event) {
12347 spin_lock_irq(&dev->event_lock);
12348 drm_crtc_send_vblank_event(crtc, event);
12349 spin_unlock_irq(&dev->event_lock);
12350 }
12351 }
12352 return ret;
12353 }
12354
12355
12356 /**
12357 * intel_wm_need_update - Check whether watermarks need updating
12358 * @plane: drm plane
12359 * @state: new plane state
12360 *
12361 * Check current plane state versus the new one to determine whether
12362 * watermarks need to be recalculated.
12363 *
12364 * Returns true or false.
12365 */
12366 static bool intel_wm_need_update(struct drm_plane *plane,
12367 struct drm_plane_state *state)
12368 {
12369 struct intel_plane_state *new = to_intel_plane_state(state);
12370 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12371
12372 /* Update watermarks on tiling or size changes. */
12373 if (new->base.visible != cur->base.visible)
12374 return true;
12375
12376 if (!cur->base.fb || !new->base.fb)
12377 return false;
12378
12379 if (cur->base.fb->modifier != new->base.fb->modifier ||
12380 cur->base.rotation != new->base.rotation ||
12381 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12382 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12383 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12384 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12385 return true;
12386
12387 return false;
12388 }
12389
12390 static bool needs_scaling(struct intel_plane_state *state)
12391 {
12392 int src_w = drm_rect_width(&state->base.src) >> 16;
12393 int src_h = drm_rect_height(&state->base.src) >> 16;
12394 int dst_w = drm_rect_width(&state->base.dst);
12395 int dst_h = drm_rect_height(&state->base.dst);
12396
12397 return (src_w != dst_w || src_h != dst_h);
12398 }
12399
12400 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12401 struct drm_plane_state *plane_state)
12402 {
12403 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12404 struct drm_crtc *crtc = crtc_state->crtc;
12405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12406 struct drm_plane *plane = plane_state->plane;
12407 struct drm_device *dev = crtc->dev;
12408 struct drm_i915_private *dev_priv = to_i915(dev);
12409 struct intel_plane_state *old_plane_state =
12410 to_intel_plane_state(plane->state);
12411 bool mode_changed = needs_modeset(crtc_state);
12412 bool was_crtc_enabled = crtc->state->active;
12413 bool is_crtc_enabled = crtc_state->active;
12414 bool turn_off, turn_on, visible, was_visible;
12415 struct drm_framebuffer *fb = plane_state->fb;
12416 int ret;
12417
12418 if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12419 ret = skl_update_scaler_plane(
12420 to_intel_crtc_state(crtc_state),
12421 to_intel_plane_state(plane_state));
12422 if (ret)
12423 return ret;
12424 }
12425
12426 was_visible = old_plane_state->base.visible;
12427 visible = to_intel_plane_state(plane_state)->base.visible;
12428
12429 if (!was_crtc_enabled && WARN_ON(was_visible))
12430 was_visible = false;
12431
12432 /*
12433 * Visibility is calculated as if the crtc was on, but
12434 * after scaler setup everything depends on it being off
12435 * when the crtc isn't active.
12436 *
12437 * FIXME this is wrong for watermarks. Watermarks should also
12438 * be computed as if the pipe would be active. Perhaps move
12439 * per-plane wm computation to the .check_plane() hook, and
12440 * only combine the results from all planes in the current place?
12441 */
12442 if (!is_crtc_enabled)
12443 to_intel_plane_state(plane_state)->base.visible = visible = false;
12444
12445 if (!was_visible && !visible)
12446 return 0;
12447
12448 if (fb != old_plane_state->base.fb)
12449 pipe_config->fb_changed = true;
12450
12451 turn_off = was_visible && (!visible || mode_changed);
12452 turn_on = visible && (!was_visible || mode_changed);
12453
12454 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12455 intel_crtc->base.base.id,
12456 intel_crtc->base.name,
12457 plane->base.id, plane->name,
12458 fb ? fb->base.id : -1);
12459
12460 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12461 plane->base.id, plane->name,
12462 was_visible, visible,
12463 turn_off, turn_on, mode_changed);
12464
12465 if (turn_on) {
12466 pipe_config->update_wm_pre = true;
12467
12468 /* must disable cxsr around plane enable/disable */
12469 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12470 pipe_config->disable_cxsr = true;
12471 } else if (turn_off) {
12472 pipe_config->update_wm_post = true;
12473
12474 /* must disable cxsr around plane enable/disable */
12475 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12476 pipe_config->disable_cxsr = true;
12477 } else if (intel_wm_need_update(plane, plane_state)) {
12478 /* FIXME bollocks */
12479 pipe_config->update_wm_pre = true;
12480 pipe_config->update_wm_post = true;
12481 }
12482
12483 /* Pre-gen9 platforms need two-step watermark updates */
12484 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12485 INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
12486 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12487
12488 if (visible || was_visible)
12489 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12490
12491 /*
12492 * WaCxSRDisabledForSpriteScaling:ivb
12493 *
12494 * cstate->update_wm was already set above, so this flag will
12495 * take effect when we commit and program watermarks.
12496 */
12497 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
12498 needs_scaling(to_intel_plane_state(plane_state)) &&
12499 !needs_scaling(old_plane_state))
12500 pipe_config->disable_lp_wm = true;
12501
12502 return 0;
12503 }
12504
12505 static bool encoders_cloneable(const struct intel_encoder *a,
12506 const struct intel_encoder *b)
12507 {
12508 /* masks could be asymmetric, so check both ways */
12509 return a == b || (a->cloneable & (1 << b->type) &&
12510 b->cloneable & (1 << a->type));
12511 }
12512
12513 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12514 struct intel_crtc *crtc,
12515 struct intel_encoder *encoder)
12516 {
12517 struct intel_encoder *source_encoder;
12518 struct drm_connector *connector;
12519 struct drm_connector_state *connector_state;
12520 int i;
12521
12522 for_each_connector_in_state(state, connector, connector_state, i) {
12523 if (connector_state->crtc != &crtc->base)
12524 continue;
12525
12526 source_encoder =
12527 to_intel_encoder(connector_state->best_encoder);
12528 if (!encoders_cloneable(encoder, source_encoder))
12529 return false;
12530 }
12531
12532 return true;
12533 }
12534
12535 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12536 struct drm_crtc_state *crtc_state)
12537 {
12538 struct drm_device *dev = crtc->dev;
12539 struct drm_i915_private *dev_priv = to_i915(dev);
12540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12541 struct intel_crtc_state *pipe_config =
12542 to_intel_crtc_state(crtc_state);
12543 struct drm_atomic_state *state = crtc_state->state;
12544 int ret;
12545 bool mode_changed = needs_modeset(crtc_state);
12546
12547 if (mode_changed && !crtc_state->active)
12548 pipe_config->update_wm_post = true;
12549
12550 if (mode_changed && crtc_state->enable &&
12551 dev_priv->display.crtc_compute_clock &&
12552 !WARN_ON(pipe_config->shared_dpll)) {
12553 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12554 pipe_config);
12555 if (ret)
12556 return ret;
12557 }
12558
12559 if (crtc_state->color_mgmt_changed) {
12560 ret = intel_color_check(crtc, crtc_state);
12561 if (ret)
12562 return ret;
12563
12564 /*
12565 * Changing color management on Intel hardware is
12566 * handled as part of planes update.
12567 */
12568 crtc_state->planes_changed = true;
12569 }
12570
12571 ret = 0;
12572 if (dev_priv->display.compute_pipe_wm) {
12573 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12574 if (ret) {
12575 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12576 return ret;
12577 }
12578 }
12579
12580 if (dev_priv->display.compute_intermediate_wm &&
12581 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12582 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12583 return 0;
12584
12585 /*
12586 * Calculate 'intermediate' watermarks that satisfy both the
12587 * old state and the new state. We can program these
12588 * immediately.
12589 */
12590 ret = dev_priv->display.compute_intermediate_wm(dev,
12591 intel_crtc,
12592 pipe_config);
12593 if (ret) {
12594 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12595 return ret;
12596 }
12597 } else if (dev_priv->display.compute_intermediate_wm) {
12598 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12599 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12600 }
12601
12602 if (INTEL_GEN(dev_priv) >= 9) {
12603 if (mode_changed)
12604 ret = skl_update_scaler_crtc(pipe_config);
12605
12606 if (!ret)
12607 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12608 pipe_config);
12609 }
12610
12611 return ret;
12612 }
12613
12614 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12615 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12616 .atomic_begin = intel_begin_crtc_commit,
12617 .atomic_flush = intel_finish_crtc_commit,
12618 .atomic_check = intel_crtc_atomic_check,
12619 };
12620
12621 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12622 {
12623 struct intel_connector *connector;
12624
12625 for_each_intel_connector(dev, connector) {
12626 if (connector->base.state->crtc)
12627 drm_connector_unreference(&connector->base);
12628
12629 if (connector->base.encoder) {
12630 connector->base.state->best_encoder =
12631 connector->base.encoder;
12632 connector->base.state->crtc =
12633 connector->base.encoder->crtc;
12634
12635 drm_connector_reference(&connector->base);
12636 } else {
12637 connector->base.state->best_encoder = NULL;
12638 connector->base.state->crtc = NULL;
12639 }
12640 }
12641 }
12642
12643 static void
12644 connected_sink_compute_bpp(struct intel_connector *connector,
12645 struct intel_crtc_state *pipe_config)
12646 {
12647 const struct drm_display_info *info = &connector->base.display_info;
12648 int bpp = pipe_config->pipe_bpp;
12649
12650 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12651 connector->base.base.id,
12652 connector->base.name);
12653
12654 /* Don't use an invalid EDID bpc value */
12655 if (info->bpc != 0 && info->bpc * 3 < bpp) {
12656 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12657 bpp, info->bpc * 3);
12658 pipe_config->pipe_bpp = info->bpc * 3;
12659 }
12660
12661 /* Clamp bpp to 8 on screens without EDID 1.4 */
12662 if (info->bpc == 0 && bpp > 24) {
12663 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12664 bpp);
12665 pipe_config->pipe_bpp = 24;
12666 }
12667 }
12668
12669 static int
12670 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12671 struct intel_crtc_state *pipe_config)
12672 {
12673 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12674 struct drm_atomic_state *state;
12675 struct drm_connector *connector;
12676 struct drm_connector_state *connector_state;
12677 int bpp, i;
12678
12679 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12680 IS_CHERRYVIEW(dev_priv)))
12681 bpp = 10*3;
12682 else if (INTEL_GEN(dev_priv) >= 5)
12683 bpp = 12*3;
12684 else
12685 bpp = 8*3;
12686
12687
12688 pipe_config->pipe_bpp = bpp;
12689
12690 state = pipe_config->base.state;
12691
12692 /* Clamp display bpp to EDID value */
12693 for_each_connector_in_state(state, connector, connector_state, i) {
12694 if (connector_state->crtc != &crtc->base)
12695 continue;
12696
12697 connected_sink_compute_bpp(to_intel_connector(connector),
12698 pipe_config);
12699 }
12700
12701 return bpp;
12702 }
12703
12704 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12705 {
12706 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12707 "type: 0x%x flags: 0x%x\n",
12708 mode->crtc_clock,
12709 mode->crtc_hdisplay, mode->crtc_hsync_start,
12710 mode->crtc_hsync_end, mode->crtc_htotal,
12711 mode->crtc_vdisplay, mode->crtc_vsync_start,
12712 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12713 }
12714
12715 static inline void
12716 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
12717 unsigned int lane_count, struct intel_link_m_n *m_n)
12718 {
12719 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12720 id, lane_count,
12721 m_n->gmch_m, m_n->gmch_n,
12722 m_n->link_m, m_n->link_n, m_n->tu);
12723 }
12724
12725 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12726 struct intel_crtc_state *pipe_config,
12727 const char *context)
12728 {
12729 struct drm_device *dev = crtc->base.dev;
12730 struct drm_i915_private *dev_priv = to_i915(dev);
12731 struct drm_plane *plane;
12732 struct intel_plane *intel_plane;
12733 struct intel_plane_state *state;
12734 struct drm_framebuffer *fb;
12735
12736 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12737 crtc->base.base.id, crtc->base.name, context);
12738
12739 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12740 transcoder_name(pipe_config->cpu_transcoder),
12741 pipe_config->pipe_bpp, pipe_config->dither);
12742
12743 if (pipe_config->has_pch_encoder)
12744 intel_dump_m_n_config(pipe_config, "fdi",
12745 pipe_config->fdi_lanes,
12746 &pipe_config->fdi_m_n);
12747
12748 if (intel_crtc_has_dp_encoder(pipe_config)) {
12749 intel_dump_m_n_config(pipe_config, "dp m_n",
12750 pipe_config->lane_count, &pipe_config->dp_m_n);
12751 if (pipe_config->has_drrs)
12752 intel_dump_m_n_config(pipe_config, "dp m2_n2",
12753 pipe_config->lane_count,
12754 &pipe_config->dp_m2_n2);
12755 }
12756
12757 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12758 pipe_config->has_audio, pipe_config->has_infoframe);
12759
12760 DRM_DEBUG_KMS("requested mode:\n");
12761 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12762 DRM_DEBUG_KMS("adjusted mode:\n");
12763 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12764 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12765 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12766 pipe_config->port_clock,
12767 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12768
12769 if (INTEL_GEN(dev_priv) >= 9)
12770 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12771 crtc->num_scalers,
12772 pipe_config->scaler_state.scaler_users,
12773 pipe_config->scaler_state.scaler_id);
12774
12775 if (HAS_GMCH_DISPLAY(dev_priv))
12776 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12777 pipe_config->gmch_pfit.control,
12778 pipe_config->gmch_pfit.pgm_ratios,
12779 pipe_config->gmch_pfit.lvds_border_bits);
12780 else
12781 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12782 pipe_config->pch_pfit.pos,
12783 pipe_config->pch_pfit.size,
12784 enableddisabled(pipe_config->pch_pfit.enabled));
12785
12786 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12787 pipe_config->ips_enabled, pipe_config->double_wide);
12788
12789 if (IS_BROXTON(dev_priv)) {
12790 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12791 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12792 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12793 pipe_config->dpll_hw_state.ebb0,
12794 pipe_config->dpll_hw_state.ebb4,
12795 pipe_config->dpll_hw_state.pll0,
12796 pipe_config->dpll_hw_state.pll1,
12797 pipe_config->dpll_hw_state.pll2,
12798 pipe_config->dpll_hw_state.pll3,
12799 pipe_config->dpll_hw_state.pll6,
12800 pipe_config->dpll_hw_state.pll8,
12801 pipe_config->dpll_hw_state.pll9,
12802 pipe_config->dpll_hw_state.pll10,
12803 pipe_config->dpll_hw_state.pcsdw12);
12804 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
12805 DRM_DEBUG_KMS("dpll_hw_state: "
12806 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12807 pipe_config->dpll_hw_state.ctrl1,
12808 pipe_config->dpll_hw_state.cfgcr1,
12809 pipe_config->dpll_hw_state.cfgcr2);
12810 } else if (HAS_DDI(dev_priv)) {
12811 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12812 pipe_config->dpll_hw_state.wrpll,
12813 pipe_config->dpll_hw_state.spll);
12814 } else {
12815 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12816 "fp0: 0x%x, fp1: 0x%x\n",
12817 pipe_config->dpll_hw_state.dpll,
12818 pipe_config->dpll_hw_state.dpll_md,
12819 pipe_config->dpll_hw_state.fp0,
12820 pipe_config->dpll_hw_state.fp1);
12821 }
12822
12823 DRM_DEBUG_KMS("planes on this crtc\n");
12824 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12825 struct drm_format_name_buf format_name;
12826 intel_plane = to_intel_plane(plane);
12827 if (intel_plane->pipe != crtc->pipe)
12828 continue;
12829
12830 state = to_intel_plane_state(plane->state);
12831 fb = state->base.fb;
12832 if (!fb) {
12833 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12834 plane->base.id, plane->name, state->scaler_id);
12835 continue;
12836 }
12837
12838 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12839 plane->base.id, plane->name,
12840 fb->base.id, fb->width, fb->height,
12841 drm_get_format_name(fb->pixel_format, &format_name));
12842 if (INTEL_GEN(dev_priv) >= 9)
12843 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12844 state->scaler_id,
12845 state->base.src.x1 >> 16,
12846 state->base.src.y1 >> 16,
12847 drm_rect_width(&state->base.src) >> 16,
12848 drm_rect_height(&state->base.src) >> 16,
12849 state->base.dst.x1, state->base.dst.y1,
12850 drm_rect_width(&state->base.dst),
12851 drm_rect_height(&state->base.dst));
12852 }
12853 }
12854
12855 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12856 {
12857 struct drm_device *dev = state->dev;
12858 struct drm_connector *connector;
12859 unsigned int used_ports = 0;
12860 unsigned int used_mst_ports = 0;
12861
12862 /*
12863 * Walk the connector list instead of the encoder
12864 * list to detect the problem on ddi platforms
12865 * where there's just one encoder per digital port.
12866 */
12867 drm_for_each_connector(connector, dev) {
12868 struct drm_connector_state *connector_state;
12869 struct intel_encoder *encoder;
12870
12871 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12872 if (!connector_state)
12873 connector_state = connector->state;
12874
12875 if (!connector_state->best_encoder)
12876 continue;
12877
12878 encoder = to_intel_encoder(connector_state->best_encoder);
12879
12880 WARN_ON(!connector_state->crtc);
12881
12882 switch (encoder->type) {
12883 unsigned int port_mask;
12884 case INTEL_OUTPUT_UNKNOWN:
12885 if (WARN_ON(!HAS_DDI(to_i915(dev))))
12886 break;
12887 case INTEL_OUTPUT_DP:
12888 case INTEL_OUTPUT_HDMI:
12889 case INTEL_OUTPUT_EDP:
12890 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12891
12892 /* the same port mustn't appear more than once */
12893 if (used_ports & port_mask)
12894 return false;
12895
12896 used_ports |= port_mask;
12897 break;
12898 case INTEL_OUTPUT_DP_MST:
12899 used_mst_ports |=
12900 1 << enc_to_mst(&encoder->base)->primary->port;
12901 break;
12902 default:
12903 break;
12904 }
12905 }
12906
12907 /* can't mix MST and SST/HDMI on the same port */
12908 if (used_ports & used_mst_ports)
12909 return false;
12910
12911 return true;
12912 }
12913
12914 static void
12915 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12916 {
12917 struct drm_crtc_state tmp_state;
12918 struct intel_crtc_scaler_state scaler_state;
12919 struct intel_dpll_hw_state dpll_hw_state;
12920 struct intel_shared_dpll *shared_dpll;
12921 bool force_thru;
12922
12923 /* FIXME: before the switch to atomic started, a new pipe_config was
12924 * kzalloc'd. Code that depends on any field being zero should be
12925 * fixed, so that the crtc_state can be safely duplicated. For now,
12926 * only fields that are know to not cause problems are preserved. */
12927
12928 tmp_state = crtc_state->base;
12929 scaler_state = crtc_state->scaler_state;
12930 shared_dpll = crtc_state->shared_dpll;
12931 dpll_hw_state = crtc_state->dpll_hw_state;
12932 force_thru = crtc_state->pch_pfit.force_thru;
12933
12934 memset(crtc_state, 0, sizeof *crtc_state);
12935
12936 crtc_state->base = tmp_state;
12937 crtc_state->scaler_state = scaler_state;
12938 crtc_state->shared_dpll = shared_dpll;
12939 crtc_state->dpll_hw_state = dpll_hw_state;
12940 crtc_state->pch_pfit.force_thru = force_thru;
12941 }
12942
12943 static int
12944 intel_modeset_pipe_config(struct drm_crtc *crtc,
12945 struct intel_crtc_state *pipe_config)
12946 {
12947 struct drm_atomic_state *state = pipe_config->base.state;
12948 struct intel_encoder *encoder;
12949 struct drm_connector *connector;
12950 struct drm_connector_state *connector_state;
12951 int base_bpp, ret = -EINVAL;
12952 int i;
12953 bool retry = true;
12954
12955 clear_intel_crtc_state(pipe_config);
12956
12957 pipe_config->cpu_transcoder =
12958 (enum transcoder) to_intel_crtc(crtc)->pipe;
12959
12960 /*
12961 * Sanitize sync polarity flags based on requested ones. If neither
12962 * positive or negative polarity is requested, treat this as meaning
12963 * negative polarity.
12964 */
12965 if (!(pipe_config->base.adjusted_mode.flags &
12966 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12967 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12968
12969 if (!(pipe_config->base.adjusted_mode.flags &
12970 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12971 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12972
12973 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12974 pipe_config);
12975 if (base_bpp < 0)
12976 goto fail;
12977
12978 /*
12979 * Determine the real pipe dimensions. Note that stereo modes can
12980 * increase the actual pipe size due to the frame doubling and
12981 * insertion of additional space for blanks between the frame. This
12982 * is stored in the crtc timings. We use the requested mode to do this
12983 * computation to clearly distinguish it from the adjusted mode, which
12984 * can be changed by the connectors in the below retry loop.
12985 */
12986 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12987 &pipe_config->pipe_src_w,
12988 &pipe_config->pipe_src_h);
12989
12990 for_each_connector_in_state(state, connector, connector_state, i) {
12991 if (connector_state->crtc != crtc)
12992 continue;
12993
12994 encoder = to_intel_encoder(connector_state->best_encoder);
12995
12996 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12997 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12998 goto fail;
12999 }
13000
13001 /*
13002 * Determine output_types before calling the .compute_config()
13003 * hooks so that the hooks can use this information safely.
13004 */
13005 pipe_config->output_types |= 1 << encoder->type;
13006 }
13007
13008 encoder_retry:
13009 /* Ensure the port clock defaults are reset when retrying. */
13010 pipe_config->port_clock = 0;
13011 pipe_config->pixel_multiplier = 1;
13012
13013 /* Fill in default crtc timings, allow encoders to overwrite them. */
13014 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13015 CRTC_STEREO_DOUBLE);
13016
13017 /* Pass our mode to the connectors and the CRTC to give them a chance to
13018 * adjust it according to limitations or connector properties, and also
13019 * a chance to reject the mode entirely.
13020 */
13021 for_each_connector_in_state(state, connector, connector_state, i) {
13022 if (connector_state->crtc != crtc)
13023 continue;
13024
13025 encoder = to_intel_encoder(connector_state->best_encoder);
13026
13027 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13028 DRM_DEBUG_KMS("Encoder config failure\n");
13029 goto fail;
13030 }
13031 }
13032
13033 /* Set default port clock if not overwritten by the encoder. Needs to be
13034 * done afterwards in case the encoder adjusts the mode. */
13035 if (!pipe_config->port_clock)
13036 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13037 * pipe_config->pixel_multiplier;
13038
13039 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13040 if (ret < 0) {
13041 DRM_DEBUG_KMS("CRTC fixup failed\n");
13042 goto fail;
13043 }
13044
13045 if (ret == RETRY) {
13046 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13047 ret = -EINVAL;
13048 goto fail;
13049 }
13050
13051 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13052 retry = false;
13053 goto encoder_retry;
13054 }
13055
13056 /* Dithering seems to not pass-through bits correctly when it should, so
13057 * only enable it on 6bpc panels. */
13058 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13059 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13060 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13061
13062 fail:
13063 return ret;
13064 }
13065
13066 static void
13067 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13068 {
13069 struct drm_crtc *crtc;
13070 struct drm_crtc_state *crtc_state;
13071 int i;
13072
13073 /* Double check state. */
13074 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13075 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13076
13077 /* Update hwmode for vblank functions */
13078 if (crtc->state->active)
13079 crtc->hwmode = crtc->state->adjusted_mode;
13080 else
13081 crtc->hwmode.crtc_clock = 0;
13082
13083 /*
13084 * Update legacy state to satisfy fbc code. This can
13085 * be removed when fbc uses the atomic state.
13086 */
13087 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13088 struct drm_plane_state *plane_state = crtc->primary->state;
13089
13090 crtc->primary->fb = plane_state->fb;
13091 crtc->x = plane_state->src_x >> 16;
13092 crtc->y = plane_state->src_y >> 16;
13093 }
13094 }
13095 }
13096
13097 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13098 {
13099 int diff;
13100
13101 if (clock1 == clock2)
13102 return true;
13103
13104 if (!clock1 || !clock2)
13105 return false;
13106
13107 diff = abs(clock1 - clock2);
13108
13109 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13110 return true;
13111
13112 return false;
13113 }
13114
13115 static bool
13116 intel_compare_m_n(unsigned int m, unsigned int n,
13117 unsigned int m2, unsigned int n2,
13118 bool exact)
13119 {
13120 if (m == m2 && n == n2)
13121 return true;
13122
13123 if (exact || !m || !n || !m2 || !n2)
13124 return false;
13125
13126 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13127
13128 if (n > n2) {
13129 while (n > n2) {
13130 m2 <<= 1;
13131 n2 <<= 1;
13132 }
13133 } else if (n < n2) {
13134 while (n < n2) {
13135 m <<= 1;
13136 n <<= 1;
13137 }
13138 }
13139
13140 if (n != n2)
13141 return false;
13142
13143 return intel_fuzzy_clock_check(m, m2);
13144 }
13145
13146 static bool
13147 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13148 struct intel_link_m_n *m2_n2,
13149 bool adjust)
13150 {
13151 if (m_n->tu == m2_n2->tu &&
13152 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13153 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13154 intel_compare_m_n(m_n->link_m, m_n->link_n,
13155 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13156 if (adjust)
13157 *m2_n2 = *m_n;
13158
13159 return true;
13160 }
13161
13162 return false;
13163 }
13164
13165 static bool
13166 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
13167 struct intel_crtc_state *current_config,
13168 struct intel_crtc_state *pipe_config,
13169 bool adjust)
13170 {
13171 bool ret = true;
13172
13173 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13174 do { \
13175 if (!adjust) \
13176 DRM_ERROR(fmt, ##__VA_ARGS__); \
13177 else \
13178 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13179 } while (0)
13180
13181 #define PIPE_CONF_CHECK_X(name) \
13182 if (current_config->name != pipe_config->name) { \
13183 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13184 "(expected 0x%08x, found 0x%08x)\n", \
13185 current_config->name, \
13186 pipe_config->name); \
13187 ret = false; \
13188 }
13189
13190 #define PIPE_CONF_CHECK_I(name) \
13191 if (current_config->name != pipe_config->name) { \
13192 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13193 "(expected %i, found %i)\n", \
13194 current_config->name, \
13195 pipe_config->name); \
13196 ret = false; \
13197 }
13198
13199 #define PIPE_CONF_CHECK_P(name) \
13200 if (current_config->name != pipe_config->name) { \
13201 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13202 "(expected %p, found %p)\n", \
13203 current_config->name, \
13204 pipe_config->name); \
13205 ret = false; \
13206 }
13207
13208 #define PIPE_CONF_CHECK_M_N(name) \
13209 if (!intel_compare_link_m_n(&current_config->name, \
13210 &pipe_config->name,\
13211 adjust)) { \
13212 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13213 "(expected tu %i gmch %i/%i link %i/%i, " \
13214 "found tu %i, gmch %i/%i link %i/%i)\n", \
13215 current_config->name.tu, \
13216 current_config->name.gmch_m, \
13217 current_config->name.gmch_n, \
13218 current_config->name.link_m, \
13219 current_config->name.link_n, \
13220 pipe_config->name.tu, \
13221 pipe_config->name.gmch_m, \
13222 pipe_config->name.gmch_n, \
13223 pipe_config->name.link_m, \
13224 pipe_config->name.link_n); \
13225 ret = false; \
13226 }
13227
13228 /* This is required for BDW+ where there is only one set of registers for
13229 * switching between high and low RR.
13230 * This macro can be used whenever a comparison has to be made between one
13231 * hw state and multiple sw state variables.
13232 */
13233 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13234 if (!intel_compare_link_m_n(&current_config->name, \
13235 &pipe_config->name, adjust) && \
13236 !intel_compare_link_m_n(&current_config->alt_name, \
13237 &pipe_config->name, adjust)) { \
13238 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13239 "(expected tu %i gmch %i/%i link %i/%i, " \
13240 "or tu %i gmch %i/%i link %i/%i, " \
13241 "found tu %i, gmch %i/%i link %i/%i)\n", \
13242 current_config->name.tu, \
13243 current_config->name.gmch_m, \
13244 current_config->name.gmch_n, \
13245 current_config->name.link_m, \
13246 current_config->name.link_n, \
13247 current_config->alt_name.tu, \
13248 current_config->alt_name.gmch_m, \
13249 current_config->alt_name.gmch_n, \
13250 current_config->alt_name.link_m, \
13251 current_config->alt_name.link_n, \
13252 pipe_config->name.tu, \
13253 pipe_config->name.gmch_m, \
13254 pipe_config->name.gmch_n, \
13255 pipe_config->name.link_m, \
13256 pipe_config->name.link_n); \
13257 ret = false; \
13258 }
13259
13260 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13261 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13262 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13263 "(expected %i, found %i)\n", \
13264 current_config->name & (mask), \
13265 pipe_config->name & (mask)); \
13266 ret = false; \
13267 }
13268
13269 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13270 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13271 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13272 "(expected %i, found %i)\n", \
13273 current_config->name, \
13274 pipe_config->name); \
13275 ret = false; \
13276 }
13277
13278 #define PIPE_CONF_QUIRK(quirk) \
13279 ((current_config->quirks | pipe_config->quirks) & (quirk))
13280
13281 PIPE_CONF_CHECK_I(cpu_transcoder);
13282
13283 PIPE_CONF_CHECK_I(has_pch_encoder);
13284 PIPE_CONF_CHECK_I(fdi_lanes);
13285 PIPE_CONF_CHECK_M_N(fdi_m_n);
13286
13287 PIPE_CONF_CHECK_I(lane_count);
13288 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13289
13290 if (INTEL_GEN(dev_priv) < 8) {
13291 PIPE_CONF_CHECK_M_N(dp_m_n);
13292
13293 if (current_config->has_drrs)
13294 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13295 } else
13296 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13297
13298 PIPE_CONF_CHECK_X(output_types);
13299
13300 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13301 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13302 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13303 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13304 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13305 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13306
13307 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13308 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13309 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13310 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13311 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13312 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13313
13314 PIPE_CONF_CHECK_I(pixel_multiplier);
13315 PIPE_CONF_CHECK_I(has_hdmi_sink);
13316 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13317 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13318 PIPE_CONF_CHECK_I(limited_color_range);
13319 PIPE_CONF_CHECK_I(has_infoframe);
13320
13321 PIPE_CONF_CHECK_I(has_audio);
13322
13323 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13324 DRM_MODE_FLAG_INTERLACE);
13325
13326 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13327 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13328 DRM_MODE_FLAG_PHSYNC);
13329 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13330 DRM_MODE_FLAG_NHSYNC);
13331 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13332 DRM_MODE_FLAG_PVSYNC);
13333 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13334 DRM_MODE_FLAG_NVSYNC);
13335 }
13336
13337 PIPE_CONF_CHECK_X(gmch_pfit.control);
13338 /* pfit ratios are autocomputed by the hw on gen4+ */
13339 if (INTEL_GEN(dev_priv) < 4)
13340 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13341 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13342
13343 if (!adjust) {
13344 PIPE_CONF_CHECK_I(pipe_src_w);
13345 PIPE_CONF_CHECK_I(pipe_src_h);
13346
13347 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13348 if (current_config->pch_pfit.enabled) {
13349 PIPE_CONF_CHECK_X(pch_pfit.pos);
13350 PIPE_CONF_CHECK_X(pch_pfit.size);
13351 }
13352
13353 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13354 }
13355
13356 /* BDW+ don't expose a synchronous way to read the state */
13357 if (IS_HASWELL(dev_priv))
13358 PIPE_CONF_CHECK_I(ips_enabled);
13359
13360 PIPE_CONF_CHECK_I(double_wide);
13361
13362 PIPE_CONF_CHECK_P(shared_dpll);
13363 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13364 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13365 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13366 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13367 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13368 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13369 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13370 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13371 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13372
13373 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13374 PIPE_CONF_CHECK_X(dsi_pll.div);
13375
13376 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13377 PIPE_CONF_CHECK_I(pipe_bpp);
13378
13379 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13380 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13381
13382 #undef PIPE_CONF_CHECK_X
13383 #undef PIPE_CONF_CHECK_I
13384 #undef PIPE_CONF_CHECK_P
13385 #undef PIPE_CONF_CHECK_FLAGS
13386 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13387 #undef PIPE_CONF_QUIRK
13388 #undef INTEL_ERR_OR_DBG_KMS
13389
13390 return ret;
13391 }
13392
13393 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13394 const struct intel_crtc_state *pipe_config)
13395 {
13396 if (pipe_config->has_pch_encoder) {
13397 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13398 &pipe_config->fdi_m_n);
13399 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13400
13401 /*
13402 * FDI already provided one idea for the dotclock.
13403 * Yell if the encoder disagrees.
13404 */
13405 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13406 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13407 fdi_dotclock, dotclock);
13408 }
13409 }
13410
13411 static void verify_wm_state(struct drm_crtc *crtc,
13412 struct drm_crtc_state *new_state)
13413 {
13414 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13415 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13416 struct skl_pipe_wm hw_wm, *sw_wm;
13417 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13418 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13420 const enum pipe pipe = intel_crtc->pipe;
13421 int plane, level, max_level = ilk_wm_max_level(dev_priv);
13422
13423 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
13424 return;
13425
13426 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
13427 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
13428
13429 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13430 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13431
13432 /* planes */
13433 for_each_universal_plane(dev_priv, pipe, plane) {
13434 hw_plane_wm = &hw_wm.planes[plane];
13435 sw_plane_wm = &sw_wm->planes[plane];
13436
13437 /* Watermarks */
13438 for (level = 0; level <= max_level; level++) {
13439 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13440 &sw_plane_wm->wm[level]))
13441 continue;
13442
13443 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13444 pipe_name(pipe), plane + 1, level,
13445 sw_plane_wm->wm[level].plane_en,
13446 sw_plane_wm->wm[level].plane_res_b,
13447 sw_plane_wm->wm[level].plane_res_l,
13448 hw_plane_wm->wm[level].plane_en,
13449 hw_plane_wm->wm[level].plane_res_b,
13450 hw_plane_wm->wm[level].plane_res_l);
13451 }
13452
13453 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13454 &sw_plane_wm->trans_wm)) {
13455 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13456 pipe_name(pipe), plane + 1,
13457 sw_plane_wm->trans_wm.plane_en,
13458 sw_plane_wm->trans_wm.plane_res_b,
13459 sw_plane_wm->trans_wm.plane_res_l,
13460 hw_plane_wm->trans_wm.plane_en,
13461 hw_plane_wm->trans_wm.plane_res_b,
13462 hw_plane_wm->trans_wm.plane_res_l);
13463 }
13464
13465 /* DDB */
13466 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
13467 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
13468
13469 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13470 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13471 pipe_name(pipe), plane + 1,
13472 sw_ddb_entry->start, sw_ddb_entry->end,
13473 hw_ddb_entry->start, hw_ddb_entry->end);
13474 }
13475 }
13476
13477 /*
13478 * cursor
13479 * If the cursor plane isn't active, we may not have updated it's ddb
13480 * allocation. In that case since the ddb allocation will be updated
13481 * once the plane becomes visible, we can skip this check
13482 */
13483 if (intel_crtc->cursor_addr) {
13484 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
13485 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13486
13487 /* Watermarks */
13488 for (level = 0; level <= max_level; level++) {
13489 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13490 &sw_plane_wm->wm[level]))
13491 continue;
13492
13493 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13494 pipe_name(pipe), level,
13495 sw_plane_wm->wm[level].plane_en,
13496 sw_plane_wm->wm[level].plane_res_b,
13497 sw_plane_wm->wm[level].plane_res_l,
13498 hw_plane_wm->wm[level].plane_en,
13499 hw_plane_wm->wm[level].plane_res_b,
13500 hw_plane_wm->wm[level].plane_res_l);
13501 }
13502
13503 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13504 &sw_plane_wm->trans_wm)) {
13505 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13506 pipe_name(pipe),
13507 sw_plane_wm->trans_wm.plane_en,
13508 sw_plane_wm->trans_wm.plane_res_b,
13509 sw_plane_wm->trans_wm.plane_res_l,
13510 hw_plane_wm->trans_wm.plane_en,
13511 hw_plane_wm->trans_wm.plane_res_b,
13512 hw_plane_wm->trans_wm.plane_res_l);
13513 }
13514
13515 /* DDB */
13516 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13517 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13518
13519 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13520 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13521 pipe_name(pipe),
13522 sw_ddb_entry->start, sw_ddb_entry->end,
13523 hw_ddb_entry->start, hw_ddb_entry->end);
13524 }
13525 }
13526 }
13527
13528 static void
13529 verify_connector_state(struct drm_device *dev,
13530 struct drm_atomic_state *state,
13531 struct drm_crtc *crtc)
13532 {
13533 struct drm_connector *connector;
13534 struct drm_connector_state *old_conn_state;
13535 int i;
13536
13537 for_each_connector_in_state(state, connector, old_conn_state, i) {
13538 struct drm_encoder *encoder = connector->encoder;
13539 struct drm_connector_state *state = connector->state;
13540
13541 if (state->crtc != crtc)
13542 continue;
13543
13544 intel_connector_verify_state(to_intel_connector(connector));
13545
13546 I915_STATE_WARN(state->best_encoder != encoder,
13547 "connector's atomic encoder doesn't match legacy encoder\n");
13548 }
13549 }
13550
13551 static void
13552 verify_encoder_state(struct drm_device *dev)
13553 {
13554 struct intel_encoder *encoder;
13555 struct intel_connector *connector;
13556
13557 for_each_intel_encoder(dev, encoder) {
13558 bool enabled = false;
13559 enum pipe pipe;
13560
13561 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13562 encoder->base.base.id,
13563 encoder->base.name);
13564
13565 for_each_intel_connector(dev, connector) {
13566 if (connector->base.state->best_encoder != &encoder->base)
13567 continue;
13568 enabled = true;
13569
13570 I915_STATE_WARN(connector->base.state->crtc !=
13571 encoder->base.crtc,
13572 "connector's crtc doesn't match encoder crtc\n");
13573 }
13574
13575 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13576 "encoder's enabled state mismatch "
13577 "(expected %i, found %i)\n",
13578 !!encoder->base.crtc, enabled);
13579
13580 if (!encoder->base.crtc) {
13581 bool active;
13582
13583 active = encoder->get_hw_state(encoder, &pipe);
13584 I915_STATE_WARN(active,
13585 "encoder detached but still enabled on pipe %c.\n",
13586 pipe_name(pipe));
13587 }
13588 }
13589 }
13590
13591 static void
13592 verify_crtc_state(struct drm_crtc *crtc,
13593 struct drm_crtc_state *old_crtc_state,
13594 struct drm_crtc_state *new_crtc_state)
13595 {
13596 struct drm_device *dev = crtc->dev;
13597 struct drm_i915_private *dev_priv = to_i915(dev);
13598 struct intel_encoder *encoder;
13599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13600 struct intel_crtc_state *pipe_config, *sw_config;
13601 struct drm_atomic_state *old_state;
13602 bool active;
13603
13604 old_state = old_crtc_state->state;
13605 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13606 pipe_config = to_intel_crtc_state(old_crtc_state);
13607 memset(pipe_config, 0, sizeof(*pipe_config));
13608 pipe_config->base.crtc = crtc;
13609 pipe_config->base.state = old_state;
13610
13611 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13612
13613 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13614
13615 /* hw state is inconsistent with the pipe quirk */
13616 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13617 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13618 active = new_crtc_state->active;
13619
13620 I915_STATE_WARN(new_crtc_state->active != active,
13621 "crtc active state doesn't match with hw state "
13622 "(expected %i, found %i)\n", new_crtc_state->active, active);
13623
13624 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13625 "transitional active state does not match atomic hw state "
13626 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13627
13628 for_each_encoder_on_crtc(dev, crtc, encoder) {
13629 enum pipe pipe;
13630
13631 active = encoder->get_hw_state(encoder, &pipe);
13632 I915_STATE_WARN(active != new_crtc_state->active,
13633 "[ENCODER:%i] active %i with crtc active %i\n",
13634 encoder->base.base.id, active, new_crtc_state->active);
13635
13636 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13637 "Encoder connected to wrong pipe %c\n",
13638 pipe_name(pipe));
13639
13640 if (active) {
13641 pipe_config->output_types |= 1 << encoder->type;
13642 encoder->get_config(encoder, pipe_config);
13643 }
13644 }
13645
13646 if (!new_crtc_state->active)
13647 return;
13648
13649 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13650
13651 sw_config = to_intel_crtc_state(crtc->state);
13652 if (!intel_pipe_config_compare(dev_priv, sw_config,
13653 pipe_config, false)) {
13654 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13655 intel_dump_pipe_config(intel_crtc, pipe_config,
13656 "[hw state]");
13657 intel_dump_pipe_config(intel_crtc, sw_config,
13658 "[sw state]");
13659 }
13660 }
13661
13662 static void
13663 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13664 struct intel_shared_dpll *pll,
13665 struct drm_crtc *crtc,
13666 struct drm_crtc_state *new_state)
13667 {
13668 struct intel_dpll_hw_state dpll_hw_state;
13669 unsigned crtc_mask;
13670 bool active;
13671
13672 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13673
13674 DRM_DEBUG_KMS("%s\n", pll->name);
13675
13676 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13677
13678 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13679 I915_STATE_WARN(!pll->on && pll->active_mask,
13680 "pll in active use but not on in sw tracking\n");
13681 I915_STATE_WARN(pll->on && !pll->active_mask,
13682 "pll is on but not used by any active crtc\n");
13683 I915_STATE_WARN(pll->on != active,
13684 "pll on state mismatch (expected %i, found %i)\n",
13685 pll->on, active);
13686 }
13687
13688 if (!crtc) {
13689 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13690 "more active pll users than references: %x vs %x\n",
13691 pll->active_mask, pll->config.crtc_mask);
13692
13693 return;
13694 }
13695
13696 crtc_mask = 1 << drm_crtc_index(crtc);
13697
13698 if (new_state->active)
13699 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13700 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13701 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13702 else
13703 I915_STATE_WARN(pll->active_mask & crtc_mask,
13704 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13705 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13706
13707 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13708 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13709 crtc_mask, pll->config.crtc_mask);
13710
13711 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13712 &dpll_hw_state,
13713 sizeof(dpll_hw_state)),
13714 "pll hw state mismatch\n");
13715 }
13716
13717 static void
13718 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13719 struct drm_crtc_state *old_crtc_state,
13720 struct drm_crtc_state *new_crtc_state)
13721 {
13722 struct drm_i915_private *dev_priv = to_i915(dev);
13723 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13724 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13725
13726 if (new_state->shared_dpll)
13727 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13728
13729 if (old_state->shared_dpll &&
13730 old_state->shared_dpll != new_state->shared_dpll) {
13731 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13732 struct intel_shared_dpll *pll = old_state->shared_dpll;
13733
13734 I915_STATE_WARN(pll->active_mask & crtc_mask,
13735 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13736 pipe_name(drm_crtc_index(crtc)));
13737 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13738 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13739 pipe_name(drm_crtc_index(crtc)));
13740 }
13741 }
13742
13743 static void
13744 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13745 struct drm_atomic_state *state,
13746 struct drm_crtc_state *old_state,
13747 struct drm_crtc_state *new_state)
13748 {
13749 if (!needs_modeset(new_state) &&
13750 !to_intel_crtc_state(new_state)->update_pipe)
13751 return;
13752
13753 verify_wm_state(crtc, new_state);
13754 verify_connector_state(crtc->dev, state, crtc);
13755 verify_crtc_state(crtc, old_state, new_state);
13756 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13757 }
13758
13759 static void
13760 verify_disabled_dpll_state(struct drm_device *dev)
13761 {
13762 struct drm_i915_private *dev_priv = to_i915(dev);
13763 int i;
13764
13765 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13766 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13767 }
13768
13769 static void
13770 intel_modeset_verify_disabled(struct drm_device *dev,
13771 struct drm_atomic_state *state)
13772 {
13773 verify_encoder_state(dev);
13774 verify_connector_state(dev, state, NULL);
13775 verify_disabled_dpll_state(dev);
13776 }
13777
13778 static void update_scanline_offset(struct intel_crtc *crtc)
13779 {
13780 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13781
13782 /*
13783 * The scanline counter increments at the leading edge of hsync.
13784 *
13785 * On most platforms it starts counting from vtotal-1 on the
13786 * first active line. That means the scanline counter value is
13787 * always one less than what we would expect. Ie. just after
13788 * start of vblank, which also occurs at start of hsync (on the
13789 * last active line), the scanline counter will read vblank_start-1.
13790 *
13791 * On gen2 the scanline counter starts counting from 1 instead
13792 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13793 * to keep the value positive), instead of adding one.
13794 *
13795 * On HSW+ the behaviour of the scanline counter depends on the output
13796 * type. For DP ports it behaves like most other platforms, but on HDMI
13797 * there's an extra 1 line difference. So we need to add two instead of
13798 * one to the value.
13799 */
13800 if (IS_GEN2(dev_priv)) {
13801 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13802 int vtotal;
13803
13804 vtotal = adjusted_mode->crtc_vtotal;
13805 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13806 vtotal /= 2;
13807
13808 crtc->scanline_offset = vtotal - 1;
13809 } else if (HAS_DDI(dev_priv) &&
13810 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13811 crtc->scanline_offset = 2;
13812 } else
13813 crtc->scanline_offset = 1;
13814 }
13815
13816 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13817 {
13818 struct drm_device *dev = state->dev;
13819 struct drm_i915_private *dev_priv = to_i915(dev);
13820 struct intel_shared_dpll_config *shared_dpll = NULL;
13821 struct drm_crtc *crtc;
13822 struct drm_crtc_state *crtc_state;
13823 int i;
13824
13825 if (!dev_priv->display.crtc_compute_clock)
13826 return;
13827
13828 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13830 struct intel_shared_dpll *old_dpll =
13831 to_intel_crtc_state(crtc->state)->shared_dpll;
13832
13833 if (!needs_modeset(crtc_state))
13834 continue;
13835
13836 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13837
13838 if (!old_dpll)
13839 continue;
13840
13841 if (!shared_dpll)
13842 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13843
13844 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13845 }
13846 }
13847
13848 /*
13849 * This implements the workaround described in the "notes" section of the mode
13850 * set sequence documentation. When going from no pipes or single pipe to
13851 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13852 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13853 */
13854 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13855 {
13856 struct drm_crtc_state *crtc_state;
13857 struct intel_crtc *intel_crtc;
13858 struct drm_crtc *crtc;
13859 struct intel_crtc_state *first_crtc_state = NULL;
13860 struct intel_crtc_state *other_crtc_state = NULL;
13861 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13862 int i;
13863
13864 /* look at all crtc's that are going to be enabled in during modeset */
13865 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13866 intel_crtc = to_intel_crtc(crtc);
13867
13868 if (!crtc_state->active || !needs_modeset(crtc_state))
13869 continue;
13870
13871 if (first_crtc_state) {
13872 other_crtc_state = to_intel_crtc_state(crtc_state);
13873 break;
13874 } else {
13875 first_crtc_state = to_intel_crtc_state(crtc_state);
13876 first_pipe = intel_crtc->pipe;
13877 }
13878 }
13879
13880 /* No workaround needed? */
13881 if (!first_crtc_state)
13882 return 0;
13883
13884 /* w/a possibly needed, check how many crtc's are already enabled. */
13885 for_each_intel_crtc(state->dev, intel_crtc) {
13886 struct intel_crtc_state *pipe_config;
13887
13888 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13889 if (IS_ERR(pipe_config))
13890 return PTR_ERR(pipe_config);
13891
13892 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13893
13894 if (!pipe_config->base.active ||
13895 needs_modeset(&pipe_config->base))
13896 continue;
13897
13898 /* 2 or more enabled crtcs means no need for w/a */
13899 if (enabled_pipe != INVALID_PIPE)
13900 return 0;
13901
13902 enabled_pipe = intel_crtc->pipe;
13903 }
13904
13905 if (enabled_pipe != INVALID_PIPE)
13906 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13907 else if (other_crtc_state)
13908 other_crtc_state->hsw_workaround_pipe = first_pipe;
13909
13910 return 0;
13911 }
13912
13913 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13914 {
13915 struct drm_crtc *crtc;
13916 struct drm_crtc_state *crtc_state;
13917 int ret = 0;
13918
13919 /* add all active pipes to the state */
13920 for_each_crtc(state->dev, crtc) {
13921 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13922 if (IS_ERR(crtc_state))
13923 return PTR_ERR(crtc_state);
13924
13925 if (!crtc_state->active || needs_modeset(crtc_state))
13926 continue;
13927
13928 crtc_state->mode_changed = true;
13929
13930 ret = drm_atomic_add_affected_connectors(state, crtc);
13931 if (ret)
13932 break;
13933
13934 ret = drm_atomic_add_affected_planes(state, crtc);
13935 if (ret)
13936 break;
13937 }
13938
13939 return ret;
13940 }
13941
13942 static int intel_modeset_checks(struct drm_atomic_state *state)
13943 {
13944 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13945 struct drm_i915_private *dev_priv = to_i915(state->dev);
13946 struct drm_crtc *crtc;
13947 struct drm_crtc_state *crtc_state;
13948 int ret = 0, i;
13949
13950 if (!check_digital_port_conflicts(state)) {
13951 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13952 return -EINVAL;
13953 }
13954
13955 intel_state->modeset = true;
13956 intel_state->active_crtcs = dev_priv->active_crtcs;
13957
13958 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13959 if (crtc_state->active)
13960 intel_state->active_crtcs |= 1 << i;
13961 else
13962 intel_state->active_crtcs &= ~(1 << i);
13963
13964 if (crtc_state->active != crtc->state->active)
13965 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13966 }
13967
13968 /*
13969 * See if the config requires any additional preparation, e.g.
13970 * to adjust global state with pipes off. We need to do this
13971 * here so we can get the modeset_pipe updated config for the new
13972 * mode set on this crtc. For other crtcs we need to use the
13973 * adjusted_mode bits in the crtc directly.
13974 */
13975 if (dev_priv->display.modeset_calc_cdclk) {
13976 if (!intel_state->cdclk_pll_vco)
13977 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13978 if (!intel_state->cdclk_pll_vco)
13979 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13980
13981 ret = dev_priv->display.modeset_calc_cdclk(state);
13982 if (ret < 0)
13983 return ret;
13984
13985 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13986 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13987 ret = intel_modeset_all_pipes(state);
13988
13989 if (ret < 0)
13990 return ret;
13991
13992 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13993 intel_state->cdclk, intel_state->dev_cdclk);
13994 } else {
13995 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13996 }
13997
13998 intel_modeset_clear_plls(state);
13999
14000 if (IS_HASWELL(dev_priv))
14001 return haswell_mode_set_planes_workaround(state);
14002
14003 return 0;
14004 }
14005
14006 /*
14007 * Handle calculation of various watermark data at the end of the atomic check
14008 * phase. The code here should be run after the per-crtc and per-plane 'check'
14009 * handlers to ensure that all derived state has been updated.
14010 */
14011 static int calc_watermark_data(struct drm_atomic_state *state)
14012 {
14013 struct drm_device *dev = state->dev;
14014 struct drm_i915_private *dev_priv = to_i915(dev);
14015
14016 /* Is there platform-specific watermark information to calculate? */
14017 if (dev_priv->display.compute_global_watermarks)
14018 return dev_priv->display.compute_global_watermarks(state);
14019
14020 return 0;
14021 }
14022
14023 /**
14024 * intel_atomic_check - validate state object
14025 * @dev: drm device
14026 * @state: state to validate
14027 */
14028 static int intel_atomic_check(struct drm_device *dev,
14029 struct drm_atomic_state *state)
14030 {
14031 struct drm_i915_private *dev_priv = to_i915(dev);
14032 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14033 struct drm_crtc *crtc;
14034 struct drm_crtc_state *crtc_state;
14035 int ret, i;
14036 bool any_ms = false;
14037
14038 ret = drm_atomic_helper_check_modeset(dev, state);
14039 if (ret)
14040 return ret;
14041
14042 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14043 struct intel_crtc_state *pipe_config =
14044 to_intel_crtc_state(crtc_state);
14045
14046 /* Catch I915_MODE_FLAG_INHERITED */
14047 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14048 crtc_state->mode_changed = true;
14049
14050 if (!needs_modeset(crtc_state))
14051 continue;
14052
14053 if (!crtc_state->enable) {
14054 any_ms = true;
14055 continue;
14056 }
14057
14058 /* FIXME: For only active_changed we shouldn't need to do any
14059 * state recomputation at all. */
14060
14061 ret = drm_atomic_add_affected_connectors(state, crtc);
14062 if (ret)
14063 return ret;
14064
14065 ret = intel_modeset_pipe_config(crtc, pipe_config);
14066 if (ret) {
14067 intel_dump_pipe_config(to_intel_crtc(crtc),
14068 pipe_config, "[failed]");
14069 return ret;
14070 }
14071
14072 if (i915.fastboot &&
14073 intel_pipe_config_compare(dev_priv,
14074 to_intel_crtc_state(crtc->state),
14075 pipe_config, true)) {
14076 crtc_state->mode_changed = false;
14077 to_intel_crtc_state(crtc_state)->update_pipe = true;
14078 }
14079
14080 if (needs_modeset(crtc_state))
14081 any_ms = true;
14082
14083 ret = drm_atomic_add_affected_planes(state, crtc);
14084 if (ret)
14085 return ret;
14086
14087 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14088 needs_modeset(crtc_state) ?
14089 "[modeset]" : "[fastset]");
14090 }
14091
14092 if (any_ms) {
14093 ret = intel_modeset_checks(state);
14094
14095 if (ret)
14096 return ret;
14097 } else {
14098 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14099 }
14100
14101 ret = drm_atomic_helper_check_planes(dev, state);
14102 if (ret)
14103 return ret;
14104
14105 intel_fbc_choose_crtc(dev_priv, state);
14106 return calc_watermark_data(state);
14107 }
14108
14109 static int intel_atomic_prepare_commit(struct drm_device *dev,
14110 struct drm_atomic_state *state)
14111 {
14112 struct drm_i915_private *dev_priv = to_i915(dev);
14113 struct drm_crtc_state *crtc_state;
14114 struct drm_crtc *crtc;
14115 int i, ret;
14116
14117 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14118 if (state->legacy_cursor_update)
14119 continue;
14120
14121 ret = intel_crtc_wait_for_pending_flips(crtc);
14122 if (ret)
14123 return ret;
14124
14125 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14126 flush_workqueue(dev_priv->wq);
14127 }
14128
14129 ret = mutex_lock_interruptible(&dev->struct_mutex);
14130 if (ret)
14131 return ret;
14132
14133 ret = drm_atomic_helper_prepare_planes(dev, state);
14134 mutex_unlock(&dev->struct_mutex);
14135
14136 return ret;
14137 }
14138
14139 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14140 {
14141 struct drm_device *dev = crtc->base.dev;
14142
14143 if (!dev->max_vblank_count)
14144 return drm_accurate_vblank_count(&crtc->base);
14145
14146 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14147 }
14148
14149 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14150 struct drm_i915_private *dev_priv,
14151 unsigned crtc_mask)
14152 {
14153 unsigned last_vblank_count[I915_MAX_PIPES];
14154 enum pipe pipe;
14155 int ret;
14156
14157 if (!crtc_mask)
14158 return;
14159
14160 for_each_pipe(dev_priv, pipe) {
14161 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14162 pipe);
14163
14164 if (!((1 << pipe) & crtc_mask))
14165 continue;
14166
14167 ret = drm_crtc_vblank_get(&crtc->base);
14168 if (WARN_ON(ret != 0)) {
14169 crtc_mask &= ~(1 << pipe);
14170 continue;
14171 }
14172
14173 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
14174 }
14175
14176 for_each_pipe(dev_priv, pipe) {
14177 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
14178 pipe);
14179 long lret;
14180
14181 if (!((1 << pipe) & crtc_mask))
14182 continue;
14183
14184 lret = wait_event_timeout(dev->vblank[pipe].queue,
14185 last_vblank_count[pipe] !=
14186 drm_crtc_vblank_count(&crtc->base),
14187 msecs_to_jiffies(50));
14188
14189 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14190
14191 drm_crtc_vblank_put(&crtc->base);
14192 }
14193 }
14194
14195 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14196 {
14197 /* fb updated, need to unpin old fb */
14198 if (crtc_state->fb_changed)
14199 return true;
14200
14201 /* wm changes, need vblank before final wm's */
14202 if (crtc_state->update_wm_post)
14203 return true;
14204
14205 /*
14206 * cxsr is re-enabled after vblank.
14207 * This is already handled by crtc_state->update_wm_post,
14208 * but added for clarity.
14209 */
14210 if (crtc_state->disable_cxsr)
14211 return true;
14212
14213 return false;
14214 }
14215
14216 static void intel_update_crtc(struct drm_crtc *crtc,
14217 struct drm_atomic_state *state,
14218 struct drm_crtc_state *old_crtc_state,
14219 unsigned int *crtc_vblank_mask)
14220 {
14221 struct drm_device *dev = crtc->dev;
14222 struct drm_i915_private *dev_priv = to_i915(dev);
14223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14224 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14225 bool modeset = needs_modeset(crtc->state);
14226
14227 if (modeset) {
14228 update_scanline_offset(intel_crtc);
14229 dev_priv->display.crtc_enable(pipe_config, state);
14230 } else {
14231 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14232 }
14233
14234 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14235 intel_fbc_enable(
14236 intel_crtc, pipe_config,
14237 to_intel_plane_state(crtc->primary->state));
14238 }
14239
14240 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14241
14242 if (needs_vblank_wait(pipe_config))
14243 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14244 }
14245
14246 static void intel_update_crtcs(struct drm_atomic_state *state,
14247 unsigned int *crtc_vblank_mask)
14248 {
14249 struct drm_crtc *crtc;
14250 struct drm_crtc_state *old_crtc_state;
14251 int i;
14252
14253 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14254 if (!crtc->state->active)
14255 continue;
14256
14257 intel_update_crtc(crtc, state, old_crtc_state,
14258 crtc_vblank_mask);
14259 }
14260 }
14261
14262 static void skl_update_crtcs(struct drm_atomic_state *state,
14263 unsigned int *crtc_vblank_mask)
14264 {
14265 struct drm_i915_private *dev_priv = to_i915(state->dev);
14266 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14267 struct drm_crtc *crtc;
14268 struct intel_crtc *intel_crtc;
14269 struct drm_crtc_state *old_crtc_state;
14270 struct intel_crtc_state *cstate;
14271 unsigned int updated = 0;
14272 bool progress;
14273 enum pipe pipe;
14274 int i;
14275
14276 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
14277
14278 for_each_crtc_in_state(state, crtc, old_crtc_state, i)
14279 /* ignore allocations for crtc's that have been turned off. */
14280 if (crtc->state->active)
14281 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
14282
14283 /*
14284 * Whenever the number of active pipes changes, we need to make sure we
14285 * update the pipes in the right order so that their ddb allocations
14286 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14287 * cause pipe underruns and other bad stuff.
14288 */
14289 do {
14290 progress = false;
14291
14292 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14293 bool vbl_wait = false;
14294 unsigned int cmask = drm_crtc_mask(crtc);
14295
14296 intel_crtc = to_intel_crtc(crtc);
14297 cstate = to_intel_crtc_state(crtc->state);
14298 pipe = intel_crtc->pipe;
14299
14300 if (updated & cmask || !cstate->base.active)
14301 continue;
14302
14303 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
14304 continue;
14305
14306 updated |= cmask;
14307 entries[i] = &cstate->wm.skl.ddb;
14308
14309 /*
14310 * If this is an already active pipe, it's DDB changed,
14311 * and this isn't the last pipe that needs updating
14312 * then we need to wait for a vblank to pass for the
14313 * new ddb allocation to take effect.
14314 */
14315 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
14316 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
14317 !crtc->state->active_changed &&
14318 intel_state->wm_results.dirty_pipes != updated)
14319 vbl_wait = true;
14320
14321 intel_update_crtc(crtc, state, old_crtc_state,
14322 crtc_vblank_mask);
14323
14324 if (vbl_wait)
14325 intel_wait_for_vblank(dev_priv, pipe);
14326
14327 progress = true;
14328 }
14329 } while (progress);
14330 }
14331
14332 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14333 {
14334 struct drm_device *dev = state->dev;
14335 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14336 struct drm_i915_private *dev_priv = to_i915(dev);
14337 struct drm_crtc_state *old_crtc_state;
14338 struct drm_crtc *crtc;
14339 struct intel_crtc_state *intel_cstate;
14340 bool hw_check = intel_state->modeset;
14341 unsigned long put_domains[I915_MAX_PIPES] = {};
14342 unsigned crtc_vblank_mask = 0;
14343 int i;
14344
14345 drm_atomic_helper_wait_for_dependencies(state);
14346
14347 if (intel_state->modeset)
14348 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14349
14350 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14352
14353 if (needs_modeset(crtc->state) ||
14354 to_intel_crtc_state(crtc->state)->update_pipe) {
14355 hw_check = true;
14356
14357 put_domains[to_intel_crtc(crtc)->pipe] =
14358 modeset_get_crtc_power_domains(crtc,
14359 to_intel_crtc_state(crtc->state));
14360 }
14361
14362 if (!needs_modeset(crtc->state))
14363 continue;
14364
14365 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14366
14367 if (old_crtc_state->active) {
14368 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14369 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14370 intel_crtc->active = false;
14371 intel_fbc_disable(intel_crtc);
14372 intel_disable_shared_dpll(intel_crtc);
14373
14374 /*
14375 * Underruns don't always raise
14376 * interrupts, so check manually.
14377 */
14378 intel_check_cpu_fifo_underruns(dev_priv);
14379 intel_check_pch_fifo_underruns(dev_priv);
14380
14381 if (!crtc->state->active) {
14382 /*
14383 * Make sure we don't call initial_watermarks
14384 * for ILK-style watermark updates.
14385 */
14386 if (dev_priv->display.atomic_update_watermarks)
14387 dev_priv->display.initial_watermarks(intel_state,
14388 to_intel_crtc_state(crtc->state));
14389 else
14390 intel_update_watermarks(intel_crtc);
14391 }
14392 }
14393 }
14394
14395 /* Only after disabling all output pipelines that will be changed can we
14396 * update the the output configuration. */
14397 intel_modeset_update_crtc_state(state);
14398
14399 if (intel_state->modeset) {
14400 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14401
14402 if (dev_priv->display.modeset_commit_cdclk &&
14403 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14404 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14405 dev_priv->display.modeset_commit_cdclk(state);
14406
14407 /*
14408 * SKL workaround: bspec recommends we disable the SAGV when we
14409 * have more then one pipe enabled
14410 */
14411 if (!intel_can_enable_sagv(state))
14412 intel_disable_sagv(dev_priv);
14413
14414 intel_modeset_verify_disabled(dev, state);
14415 }
14416
14417 /* Complete the events for pipes that have now been disabled */
14418 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14419 bool modeset = needs_modeset(crtc->state);
14420
14421 /* Complete events for now disable pipes here. */
14422 if (modeset && !crtc->state->active && crtc->state->event) {
14423 spin_lock_irq(&dev->event_lock);
14424 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14425 spin_unlock_irq(&dev->event_lock);
14426
14427 crtc->state->event = NULL;
14428 }
14429 }
14430
14431 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14432 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14433
14434 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14435 * already, but still need the state for the delayed optimization. To
14436 * fix this:
14437 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14438 * - schedule that vblank worker _before_ calling hw_done
14439 * - at the start of commit_tail, cancel it _synchrously
14440 * - switch over to the vblank wait helper in the core after that since
14441 * we don't need out special handling any more.
14442 */
14443 if (!state->legacy_cursor_update)
14444 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14445
14446 /*
14447 * Now that the vblank has passed, we can go ahead and program the
14448 * optimal watermarks on platforms that need two-step watermark
14449 * programming.
14450 *
14451 * TODO: Move this (and other cleanup) to an async worker eventually.
14452 */
14453 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14454 intel_cstate = to_intel_crtc_state(crtc->state);
14455
14456 if (dev_priv->display.optimize_watermarks)
14457 dev_priv->display.optimize_watermarks(intel_state,
14458 intel_cstate);
14459 }
14460
14461 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14462 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14463
14464 if (put_domains[i])
14465 modeset_put_power_domains(dev_priv, put_domains[i]);
14466
14467 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
14468 }
14469
14470 if (intel_state->modeset && intel_can_enable_sagv(state))
14471 intel_enable_sagv(dev_priv);
14472
14473 drm_atomic_helper_commit_hw_done(state);
14474
14475 if (intel_state->modeset)
14476 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14477
14478 mutex_lock(&dev->struct_mutex);
14479 drm_atomic_helper_cleanup_planes(dev, state);
14480 mutex_unlock(&dev->struct_mutex);
14481
14482 drm_atomic_helper_commit_cleanup_done(state);
14483
14484 drm_atomic_state_put(state);
14485
14486 /* As one of the primary mmio accessors, KMS has a high likelihood
14487 * of triggering bugs in unclaimed access. After we finish
14488 * modesetting, see if an error has been flagged, and if so
14489 * enable debugging for the next modeset - and hope we catch
14490 * the culprit.
14491 *
14492 * XXX note that we assume display power is on at this point.
14493 * This might hold true now but we need to add pm helper to check
14494 * unclaimed only when the hardware is on, as atomic commits
14495 * can happen also when the device is completely off.
14496 */
14497 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14498 }
14499
14500 static void intel_atomic_commit_work(struct work_struct *work)
14501 {
14502 struct drm_atomic_state *state =
14503 container_of(work, struct drm_atomic_state, commit_work);
14504
14505 intel_atomic_commit_tail(state);
14506 }
14507
14508 static int __i915_sw_fence_call
14509 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14510 enum i915_sw_fence_notify notify)
14511 {
14512 struct intel_atomic_state *state =
14513 container_of(fence, struct intel_atomic_state, commit_ready);
14514
14515 switch (notify) {
14516 case FENCE_COMPLETE:
14517 if (state->base.commit_work.func)
14518 queue_work(system_unbound_wq, &state->base.commit_work);
14519 break;
14520
14521 case FENCE_FREE:
14522 {
14523 struct intel_atomic_helper *helper =
14524 &to_i915(state->base.dev)->atomic_helper;
14525
14526 if (llist_add(&state->freed, &helper->free_list))
14527 schedule_work(&helper->free_work);
14528 break;
14529 }
14530 }
14531
14532 return NOTIFY_DONE;
14533 }
14534
14535 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14536 {
14537 struct drm_plane_state *old_plane_state;
14538 struct drm_plane *plane;
14539 int i;
14540
14541 for_each_plane_in_state(state, plane, old_plane_state, i)
14542 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14543 intel_fb_obj(plane->state->fb),
14544 to_intel_plane(plane)->frontbuffer_bit);
14545 }
14546
14547 /**
14548 * intel_atomic_commit - commit validated state object
14549 * @dev: DRM device
14550 * @state: the top-level driver state object
14551 * @nonblock: nonblocking commit
14552 *
14553 * This function commits a top-level state object that has been validated
14554 * with drm_atomic_helper_check().
14555 *
14556 * RETURNS
14557 * Zero for success or -errno.
14558 */
14559 static int intel_atomic_commit(struct drm_device *dev,
14560 struct drm_atomic_state *state,
14561 bool nonblock)
14562 {
14563 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14564 struct drm_i915_private *dev_priv = to_i915(dev);
14565 int ret = 0;
14566
14567 ret = drm_atomic_helper_setup_commit(state, nonblock);
14568 if (ret)
14569 return ret;
14570
14571 drm_atomic_state_get(state);
14572 i915_sw_fence_init(&intel_state->commit_ready,
14573 intel_atomic_commit_ready);
14574
14575 ret = intel_atomic_prepare_commit(dev, state);
14576 if (ret) {
14577 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14578 i915_sw_fence_commit(&intel_state->commit_ready);
14579 return ret;
14580 }
14581
14582 drm_atomic_helper_swap_state(state, true);
14583 dev_priv->wm.distrust_bios_wm = false;
14584 intel_shared_dpll_commit(state);
14585 intel_atomic_track_fbs(state);
14586
14587 if (intel_state->modeset) {
14588 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14589 sizeof(intel_state->min_pixclk));
14590 dev_priv->active_crtcs = intel_state->active_crtcs;
14591 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14592 }
14593
14594 drm_atomic_state_get(state);
14595 INIT_WORK(&state->commit_work,
14596 nonblock ? intel_atomic_commit_work : NULL);
14597
14598 i915_sw_fence_commit(&intel_state->commit_ready);
14599 if (!nonblock) {
14600 i915_sw_fence_wait(&intel_state->commit_ready);
14601 intel_atomic_commit_tail(state);
14602 }
14603
14604 return 0;
14605 }
14606
14607 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14608 {
14609 struct drm_device *dev = crtc->dev;
14610 struct drm_atomic_state *state;
14611 struct drm_crtc_state *crtc_state;
14612 int ret;
14613
14614 state = drm_atomic_state_alloc(dev);
14615 if (!state) {
14616 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14617 crtc->base.id, crtc->name);
14618 return;
14619 }
14620
14621 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14622
14623 retry:
14624 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14625 ret = PTR_ERR_OR_ZERO(crtc_state);
14626 if (!ret) {
14627 if (!crtc_state->active)
14628 goto out;
14629
14630 crtc_state->mode_changed = true;
14631 ret = drm_atomic_commit(state);
14632 }
14633
14634 if (ret == -EDEADLK) {
14635 drm_atomic_state_clear(state);
14636 drm_modeset_backoff(state->acquire_ctx);
14637 goto retry;
14638 }
14639
14640 out:
14641 drm_atomic_state_put(state);
14642 }
14643
14644 /*
14645 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14646 * drm_atomic_helper_legacy_gamma_set() directly.
14647 */
14648 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14649 u16 *red, u16 *green, u16 *blue,
14650 uint32_t size)
14651 {
14652 struct drm_device *dev = crtc->dev;
14653 struct drm_mode_config *config = &dev->mode_config;
14654 struct drm_crtc_state *state;
14655 int ret;
14656
14657 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14658 if (ret)
14659 return ret;
14660
14661 /*
14662 * Make sure we update the legacy properties so this works when
14663 * atomic is not enabled.
14664 */
14665
14666 state = crtc->state;
14667
14668 drm_object_property_set_value(&crtc->base,
14669 config->degamma_lut_property,
14670 (state->degamma_lut) ?
14671 state->degamma_lut->base.id : 0);
14672
14673 drm_object_property_set_value(&crtc->base,
14674 config->ctm_property,
14675 (state->ctm) ?
14676 state->ctm->base.id : 0);
14677
14678 drm_object_property_set_value(&crtc->base,
14679 config->gamma_lut_property,
14680 (state->gamma_lut) ?
14681 state->gamma_lut->base.id : 0);
14682
14683 return 0;
14684 }
14685
14686 static const struct drm_crtc_funcs intel_crtc_funcs = {
14687 .gamma_set = intel_atomic_legacy_gamma_set,
14688 .set_config = drm_atomic_helper_set_config,
14689 .set_property = drm_atomic_helper_crtc_set_property,
14690 .destroy = intel_crtc_destroy,
14691 .page_flip = intel_crtc_page_flip,
14692 .atomic_duplicate_state = intel_crtc_duplicate_state,
14693 .atomic_destroy_state = intel_crtc_destroy_state,
14694 };
14695
14696 /**
14697 * intel_prepare_plane_fb - Prepare fb for usage on plane
14698 * @plane: drm plane to prepare for
14699 * @fb: framebuffer to prepare for presentation
14700 *
14701 * Prepares a framebuffer for usage on a display plane. Generally this
14702 * involves pinning the underlying object and updating the frontbuffer tracking
14703 * bits. Some older platforms need special physical address handling for
14704 * cursor planes.
14705 *
14706 * Must be called with struct_mutex held.
14707 *
14708 * Returns 0 on success, negative error code on failure.
14709 */
14710 int
14711 intel_prepare_plane_fb(struct drm_plane *plane,
14712 struct drm_plane_state *new_state)
14713 {
14714 struct intel_atomic_state *intel_state =
14715 to_intel_atomic_state(new_state->state);
14716 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14717 struct drm_framebuffer *fb = new_state->fb;
14718 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14719 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14720 int ret;
14721
14722 if (!obj && !old_obj)
14723 return 0;
14724
14725 if (old_obj) {
14726 struct drm_crtc_state *crtc_state =
14727 drm_atomic_get_existing_crtc_state(new_state->state,
14728 plane->state->crtc);
14729
14730 /* Big Hammer, we also need to ensure that any pending
14731 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14732 * current scanout is retired before unpinning the old
14733 * framebuffer. Note that we rely on userspace rendering
14734 * into the buffer attached to the pipe they are waiting
14735 * on. If not, userspace generates a GPU hang with IPEHR
14736 * point to the MI_WAIT_FOR_EVENT.
14737 *
14738 * This should only fail upon a hung GPU, in which case we
14739 * can safely continue.
14740 */
14741 if (needs_modeset(crtc_state)) {
14742 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14743 old_obj->resv, NULL,
14744 false, 0,
14745 GFP_KERNEL);
14746 if (ret < 0)
14747 return ret;
14748 }
14749 }
14750
14751 if (new_state->fence) { /* explicit fencing */
14752 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14753 new_state->fence,
14754 I915_FENCE_TIMEOUT,
14755 GFP_KERNEL);
14756 if (ret < 0)
14757 return ret;
14758 }
14759
14760 if (!obj)
14761 return 0;
14762
14763 if (!new_state->fence) { /* implicit fencing */
14764 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14765 obj->resv, NULL,
14766 false, I915_FENCE_TIMEOUT,
14767 GFP_KERNEL);
14768 if (ret < 0)
14769 return ret;
14770
14771 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
14772 }
14773
14774 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14775 INTEL_INFO(dev_priv)->cursor_needs_physical) {
14776 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
14777 ret = i915_gem_object_attach_phys(obj, align);
14778 if (ret) {
14779 DRM_DEBUG_KMS("failed to attach phys object\n");
14780 return ret;
14781 }
14782 } else {
14783 struct i915_vma *vma;
14784
14785 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14786 if (IS_ERR(vma)) {
14787 DRM_DEBUG_KMS("failed to pin object\n");
14788 return PTR_ERR(vma);
14789 }
14790
14791 to_intel_plane_state(new_state)->vma = vma;
14792 }
14793
14794 return 0;
14795 }
14796
14797 /**
14798 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14799 * @plane: drm plane to clean up for
14800 * @fb: old framebuffer that was on plane
14801 *
14802 * Cleans up a framebuffer that has just been removed from a plane.
14803 *
14804 * Must be called with struct_mutex held.
14805 */
14806 void
14807 intel_cleanup_plane_fb(struct drm_plane *plane,
14808 struct drm_plane_state *old_state)
14809 {
14810 struct i915_vma *vma;
14811
14812 /* Should only be called after a successful intel_prepare_plane_fb()! */
14813 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
14814 if (vma)
14815 intel_unpin_fb_vma(vma);
14816 }
14817
14818 int
14819 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14820 {
14821 int max_scale;
14822 int crtc_clock, cdclk;
14823
14824 if (!intel_crtc || !crtc_state->base.enable)
14825 return DRM_PLANE_HELPER_NO_SCALING;
14826
14827 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14828 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14829
14830 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14831 return DRM_PLANE_HELPER_NO_SCALING;
14832
14833 /*
14834 * skl max scale is lower of:
14835 * close to 3 but not 3, -1 is for that purpose
14836 * or
14837 * cdclk/crtc_clock
14838 */
14839 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14840
14841 return max_scale;
14842 }
14843
14844 static int
14845 intel_check_primary_plane(struct drm_plane *plane,
14846 struct intel_crtc_state *crtc_state,
14847 struct intel_plane_state *state)
14848 {
14849 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14850 struct drm_crtc *crtc = state->base.crtc;
14851 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14852 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14853 bool can_position = false;
14854 int ret;
14855
14856 if (INTEL_GEN(dev_priv) >= 9) {
14857 /* use scaler when colorkey is not required */
14858 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14859 min_scale = 1;
14860 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14861 }
14862 can_position = true;
14863 }
14864
14865 ret = drm_plane_helper_check_state(&state->base,
14866 &state->clip,
14867 min_scale, max_scale,
14868 can_position, true);
14869 if (ret)
14870 return ret;
14871
14872 if (!state->base.fb)
14873 return 0;
14874
14875 if (INTEL_GEN(dev_priv) >= 9) {
14876 ret = skl_check_plane_surface(state);
14877 if (ret)
14878 return ret;
14879 }
14880
14881 return 0;
14882 }
14883
14884 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14885 struct drm_crtc_state *old_crtc_state)
14886 {
14887 struct drm_device *dev = crtc->dev;
14888 struct drm_i915_private *dev_priv = to_i915(dev);
14889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14890 struct intel_crtc_state *intel_cstate =
14891 to_intel_crtc_state(crtc->state);
14892 struct intel_crtc_state *old_intel_cstate =
14893 to_intel_crtc_state(old_crtc_state);
14894 struct intel_atomic_state *old_intel_state =
14895 to_intel_atomic_state(old_crtc_state->state);
14896 bool modeset = needs_modeset(crtc->state);
14897
14898 /* Perform vblank evasion around commit operation */
14899 intel_pipe_update_start(intel_crtc);
14900
14901 if (modeset)
14902 goto out;
14903
14904 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14905 intel_color_set_csc(crtc->state);
14906 intel_color_load_luts(crtc->state);
14907 }
14908
14909 if (intel_cstate->update_pipe)
14910 intel_update_pipe_config(intel_crtc, old_intel_cstate);
14911 else if (INTEL_GEN(dev_priv) >= 9)
14912 skl_detach_scalers(intel_crtc);
14913
14914 out:
14915 if (dev_priv->display.atomic_update_watermarks)
14916 dev_priv->display.atomic_update_watermarks(old_intel_state,
14917 intel_cstate);
14918 }
14919
14920 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14921 struct drm_crtc_state *old_crtc_state)
14922 {
14923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14924
14925 intel_pipe_update_end(intel_crtc, NULL);
14926 }
14927
14928 /**
14929 * intel_plane_destroy - destroy a plane
14930 * @plane: plane to destroy
14931 *
14932 * Common destruction function for all types of planes (primary, cursor,
14933 * sprite).
14934 */
14935 void intel_plane_destroy(struct drm_plane *plane)
14936 {
14937 drm_plane_cleanup(plane);
14938 kfree(to_intel_plane(plane));
14939 }
14940
14941 const struct drm_plane_funcs intel_plane_funcs = {
14942 .update_plane = drm_atomic_helper_update_plane,
14943 .disable_plane = drm_atomic_helper_disable_plane,
14944 .destroy = intel_plane_destroy,
14945 .set_property = drm_atomic_helper_plane_set_property,
14946 .atomic_get_property = intel_plane_atomic_get_property,
14947 .atomic_set_property = intel_plane_atomic_set_property,
14948 .atomic_duplicate_state = intel_plane_duplicate_state,
14949 .atomic_destroy_state = intel_plane_destroy_state,
14950 };
14951
14952 static struct intel_plane *
14953 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14954 {
14955 struct intel_plane *primary = NULL;
14956 struct intel_plane_state *state = NULL;
14957 const uint32_t *intel_primary_formats;
14958 unsigned int supported_rotations;
14959 unsigned int num_formats;
14960 int ret;
14961
14962 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14963 if (!primary) {
14964 ret = -ENOMEM;
14965 goto fail;
14966 }
14967
14968 state = intel_create_plane_state(&primary->base);
14969 if (!state) {
14970 ret = -ENOMEM;
14971 goto fail;
14972 }
14973
14974 primary->base.state = &state->base;
14975
14976 primary->can_scale = false;
14977 primary->max_downscale = 1;
14978 if (INTEL_GEN(dev_priv) >= 9) {
14979 primary->can_scale = true;
14980 state->scaler_id = -1;
14981 }
14982 primary->pipe = pipe;
14983 /*
14984 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14985 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14986 */
14987 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14988 primary->plane = (enum plane) !pipe;
14989 else
14990 primary->plane = (enum plane) pipe;
14991 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14992 primary->check_plane = intel_check_primary_plane;
14993
14994 if (INTEL_GEN(dev_priv) >= 9) {
14995 intel_primary_formats = skl_primary_formats;
14996 num_formats = ARRAY_SIZE(skl_primary_formats);
14997
14998 primary->update_plane = skylake_update_primary_plane;
14999 primary->disable_plane = skylake_disable_primary_plane;
15000 } else if (HAS_PCH_SPLIT(dev_priv)) {
15001 intel_primary_formats = i965_primary_formats;
15002 num_formats = ARRAY_SIZE(i965_primary_formats);
15003
15004 primary->update_plane = ironlake_update_primary_plane;
15005 primary->disable_plane = i9xx_disable_primary_plane;
15006 } else if (INTEL_GEN(dev_priv) >= 4) {
15007 intel_primary_formats = i965_primary_formats;
15008 num_formats = ARRAY_SIZE(i965_primary_formats);
15009
15010 primary->update_plane = i9xx_update_primary_plane;
15011 primary->disable_plane = i9xx_disable_primary_plane;
15012 } else {
15013 intel_primary_formats = i8xx_primary_formats;
15014 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15015
15016 primary->update_plane = i9xx_update_primary_plane;
15017 primary->disable_plane = i9xx_disable_primary_plane;
15018 }
15019
15020 if (INTEL_GEN(dev_priv) >= 9)
15021 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15022 0, &intel_plane_funcs,
15023 intel_primary_formats, num_formats,
15024 DRM_PLANE_TYPE_PRIMARY,
15025 "plane 1%c", pipe_name(pipe));
15026 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15027 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15028 0, &intel_plane_funcs,
15029 intel_primary_formats, num_formats,
15030 DRM_PLANE_TYPE_PRIMARY,
15031 "primary %c", pipe_name(pipe));
15032 else
15033 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
15034 0, &intel_plane_funcs,
15035 intel_primary_formats, num_formats,
15036 DRM_PLANE_TYPE_PRIMARY,
15037 "plane %c", plane_name(primary->plane));
15038 if (ret)
15039 goto fail;
15040
15041 if (INTEL_GEN(dev_priv) >= 9) {
15042 supported_rotations =
15043 DRM_ROTATE_0 | DRM_ROTATE_90 |
15044 DRM_ROTATE_180 | DRM_ROTATE_270;
15045 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15046 supported_rotations =
15047 DRM_ROTATE_0 | DRM_ROTATE_180 |
15048 DRM_REFLECT_X;
15049 } else if (INTEL_GEN(dev_priv) >= 4) {
15050 supported_rotations =
15051 DRM_ROTATE_0 | DRM_ROTATE_180;
15052 } else {
15053 supported_rotations = DRM_ROTATE_0;
15054 }
15055
15056 if (INTEL_GEN(dev_priv) >= 4)
15057 drm_plane_create_rotation_property(&primary->base,
15058 DRM_ROTATE_0,
15059 supported_rotations);
15060
15061 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15062
15063 return primary;
15064
15065 fail:
15066 kfree(state);
15067 kfree(primary);
15068
15069 return ERR_PTR(ret);
15070 }
15071
15072 static int
15073 intel_check_cursor_plane(struct drm_plane *plane,
15074 struct intel_crtc_state *crtc_state,
15075 struct intel_plane_state *state)
15076 {
15077 struct drm_framebuffer *fb = state->base.fb;
15078 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15079 enum pipe pipe = to_intel_plane(plane)->pipe;
15080 unsigned stride;
15081 int ret;
15082
15083 ret = drm_plane_helper_check_state(&state->base,
15084 &state->clip,
15085 DRM_PLANE_HELPER_NO_SCALING,
15086 DRM_PLANE_HELPER_NO_SCALING,
15087 true, true);
15088 if (ret)
15089 return ret;
15090
15091 /* if we want to turn off the cursor ignore width and height */
15092 if (!obj)
15093 return 0;
15094
15095 /* Check for which cursor types we support */
15096 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
15097 state->base.crtc_h)) {
15098 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15099 state->base.crtc_w, state->base.crtc_h);
15100 return -EINVAL;
15101 }
15102
15103 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15104 if (obj->base.size < stride * state->base.crtc_h) {
15105 DRM_DEBUG_KMS("buffer is too small\n");
15106 return -ENOMEM;
15107 }
15108
15109 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
15110 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15111 return -EINVAL;
15112 }
15113
15114 /*
15115 * There's something wrong with the cursor on CHV pipe C.
15116 * If it straddles the left edge of the screen then
15117 * moving it away from the edge or disabling it often
15118 * results in a pipe underrun, and often that can lead to
15119 * dead pipe (constant underrun reported, and it scans
15120 * out just a solid color). To recover from that, the
15121 * display power well must be turned off and on again.
15122 * Refuse the put the cursor into that compromised position.
15123 */
15124 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
15125 state->base.visible && state->base.crtc_x < 0) {
15126 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15127 return -EINVAL;
15128 }
15129
15130 return 0;
15131 }
15132
15133 static void
15134 intel_disable_cursor_plane(struct drm_plane *plane,
15135 struct drm_crtc *crtc)
15136 {
15137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15138
15139 intel_crtc->cursor_addr = 0;
15140 intel_crtc_update_cursor(crtc, NULL);
15141 }
15142
15143 static void
15144 intel_update_cursor_plane(struct drm_plane *plane,
15145 const struct intel_crtc_state *crtc_state,
15146 const struct intel_plane_state *state)
15147 {
15148 struct drm_crtc *crtc = crtc_state->base.crtc;
15149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15150 struct drm_i915_private *dev_priv = to_i915(plane->dev);
15151 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15152 uint32_t addr;
15153
15154 if (!obj)
15155 addr = 0;
15156 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
15157 addr = intel_plane_ggtt_offset(state);
15158 else
15159 addr = obj->phys_handle->busaddr;
15160
15161 intel_crtc->cursor_addr = addr;
15162 intel_crtc_update_cursor(crtc, state);
15163 }
15164
15165 static struct intel_plane *
15166 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15167 {
15168 struct intel_plane *cursor = NULL;
15169 struct intel_plane_state *state = NULL;
15170 int ret;
15171
15172 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15173 if (!cursor) {
15174 ret = -ENOMEM;
15175 goto fail;
15176 }
15177
15178 state = intel_create_plane_state(&cursor->base);
15179 if (!state) {
15180 ret = -ENOMEM;
15181 goto fail;
15182 }
15183
15184 cursor->base.state = &state->base;
15185
15186 cursor->can_scale = false;
15187 cursor->max_downscale = 1;
15188 cursor->pipe = pipe;
15189 cursor->plane = pipe;
15190 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15191 cursor->check_plane = intel_check_cursor_plane;
15192 cursor->update_plane = intel_update_cursor_plane;
15193 cursor->disable_plane = intel_disable_cursor_plane;
15194
15195 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15196 0, &intel_plane_funcs,
15197 intel_cursor_formats,
15198 ARRAY_SIZE(intel_cursor_formats),
15199 DRM_PLANE_TYPE_CURSOR,
15200 "cursor %c", pipe_name(pipe));
15201 if (ret)
15202 goto fail;
15203
15204 if (INTEL_GEN(dev_priv) >= 4)
15205 drm_plane_create_rotation_property(&cursor->base,
15206 DRM_ROTATE_0,
15207 DRM_ROTATE_0 |
15208 DRM_ROTATE_180);
15209
15210 if (INTEL_GEN(dev_priv) >= 9)
15211 state->scaler_id = -1;
15212
15213 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15214
15215 return cursor;
15216
15217 fail:
15218 kfree(state);
15219 kfree(cursor);
15220
15221 return ERR_PTR(ret);
15222 }
15223
15224 static void skl_init_scalers(struct drm_i915_private *dev_priv,
15225 struct intel_crtc *crtc,
15226 struct intel_crtc_state *crtc_state)
15227 {
15228 struct intel_crtc_scaler_state *scaler_state =
15229 &crtc_state->scaler_state;
15230 int i;
15231
15232 for (i = 0; i < crtc->num_scalers; i++) {
15233 struct intel_scaler *scaler = &scaler_state->scalers[i];
15234
15235 scaler->in_use = 0;
15236 scaler->mode = PS_SCALER_MODE_DYN;
15237 }
15238
15239 scaler_state->scaler_id = -1;
15240 }
15241
15242 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15243 {
15244 struct intel_crtc *intel_crtc;
15245 struct intel_crtc_state *crtc_state = NULL;
15246 struct intel_plane *primary = NULL;
15247 struct intel_plane *cursor = NULL;
15248 int sprite, ret;
15249
15250 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15251 if (!intel_crtc)
15252 return -ENOMEM;
15253
15254 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15255 if (!crtc_state) {
15256 ret = -ENOMEM;
15257 goto fail;
15258 }
15259 intel_crtc->config = crtc_state;
15260 intel_crtc->base.state = &crtc_state->base;
15261 crtc_state->base.crtc = &intel_crtc->base;
15262
15263 /* initialize shared scalers */
15264 if (INTEL_GEN(dev_priv) >= 9) {
15265 if (pipe == PIPE_C)
15266 intel_crtc->num_scalers = 1;
15267 else
15268 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15269
15270 skl_init_scalers(dev_priv, intel_crtc, crtc_state);
15271 }
15272
15273 primary = intel_primary_plane_create(dev_priv, pipe);
15274 if (IS_ERR(primary)) {
15275 ret = PTR_ERR(primary);
15276 goto fail;
15277 }
15278
15279 for_each_sprite(dev_priv, pipe, sprite) {
15280 struct intel_plane *plane;
15281
15282 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15283 if (IS_ERR(plane)) {
15284 ret = PTR_ERR(plane);
15285 goto fail;
15286 }
15287 }
15288
15289 cursor = intel_cursor_plane_create(dev_priv, pipe);
15290 if (IS_ERR(cursor)) {
15291 ret = PTR_ERR(cursor);
15292 goto fail;
15293 }
15294
15295 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15296 &primary->base, &cursor->base,
15297 &intel_crtc_funcs,
15298 "pipe %c", pipe_name(pipe));
15299 if (ret)
15300 goto fail;
15301
15302 intel_crtc->pipe = pipe;
15303 intel_crtc->plane = primary->plane;
15304
15305 intel_crtc->cursor_base = ~0;
15306 intel_crtc->cursor_cntl = ~0;
15307 intel_crtc->cursor_size = ~0;
15308
15309 intel_crtc->wm.cxsr_allowed = true;
15310
15311 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15312 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15313 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
15314 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
15315
15316 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15317
15318 intel_color_init(&intel_crtc->base);
15319
15320 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15321
15322 return 0;
15323
15324 fail:
15325 /*
15326 * drm_mode_config_cleanup() will free up any
15327 * crtcs/planes already initialized.
15328 */
15329 kfree(crtc_state);
15330 kfree(intel_crtc);
15331
15332 return ret;
15333 }
15334
15335 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15336 {
15337 struct drm_encoder *encoder = connector->base.encoder;
15338 struct drm_device *dev = connector->base.dev;
15339
15340 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15341
15342 if (!encoder || WARN_ON(!encoder->crtc))
15343 return INVALID_PIPE;
15344
15345 return to_intel_crtc(encoder->crtc)->pipe;
15346 }
15347
15348 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15349 struct drm_file *file)
15350 {
15351 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15352 struct drm_crtc *drmmode_crtc;
15353 struct intel_crtc *crtc;
15354
15355 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15356 if (!drmmode_crtc)
15357 return -ENOENT;
15358
15359 crtc = to_intel_crtc(drmmode_crtc);
15360 pipe_from_crtc_id->pipe = crtc->pipe;
15361
15362 return 0;
15363 }
15364
15365 static int intel_encoder_clones(struct intel_encoder *encoder)
15366 {
15367 struct drm_device *dev = encoder->base.dev;
15368 struct intel_encoder *source_encoder;
15369 int index_mask = 0;
15370 int entry = 0;
15371
15372 for_each_intel_encoder(dev, source_encoder) {
15373 if (encoders_cloneable(encoder, source_encoder))
15374 index_mask |= (1 << entry);
15375
15376 entry++;
15377 }
15378
15379 return index_mask;
15380 }
15381
15382 static bool has_edp_a(struct drm_i915_private *dev_priv)
15383 {
15384 if (!IS_MOBILE(dev_priv))
15385 return false;
15386
15387 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15388 return false;
15389
15390 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15391 return false;
15392
15393 return true;
15394 }
15395
15396 static bool intel_crt_present(struct drm_i915_private *dev_priv)
15397 {
15398 if (INTEL_GEN(dev_priv) >= 9)
15399 return false;
15400
15401 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15402 return false;
15403
15404 if (IS_CHERRYVIEW(dev_priv))
15405 return false;
15406
15407 if (HAS_PCH_LPT_H(dev_priv) &&
15408 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15409 return false;
15410
15411 /* DDI E can't be used if DDI A requires 4 lanes */
15412 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15413 return false;
15414
15415 if (!dev_priv->vbt.int_crt_support)
15416 return false;
15417
15418 return true;
15419 }
15420
15421 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15422 {
15423 int pps_num;
15424 int pps_idx;
15425
15426 if (HAS_DDI(dev_priv))
15427 return;
15428 /*
15429 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15430 * everywhere where registers can be write protected.
15431 */
15432 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15433 pps_num = 2;
15434 else
15435 pps_num = 1;
15436
15437 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15438 u32 val = I915_READ(PP_CONTROL(pps_idx));
15439
15440 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15441 I915_WRITE(PP_CONTROL(pps_idx), val);
15442 }
15443 }
15444
15445 static void intel_pps_init(struct drm_i915_private *dev_priv)
15446 {
15447 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15448 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15449 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15450 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15451 else
15452 dev_priv->pps_mmio_base = PPS_BASE;
15453
15454 intel_pps_unlock_regs_wa(dev_priv);
15455 }
15456
15457 static void intel_setup_outputs(struct drm_device *dev)
15458 {
15459 struct drm_i915_private *dev_priv = to_i915(dev);
15460 struct intel_encoder *encoder;
15461 bool dpd_is_edp = false;
15462
15463 intel_pps_init(dev_priv);
15464
15465 /*
15466 * intel_edp_init_connector() depends on this completing first, to
15467 * prevent the registeration of both eDP and LVDS and the incorrect
15468 * sharing of the PPS.
15469 */
15470 intel_lvds_init(dev);
15471
15472 if (intel_crt_present(dev_priv))
15473 intel_crt_init(dev);
15474
15475 if (IS_BROXTON(dev_priv)) {
15476 /*
15477 * FIXME: Broxton doesn't support port detection via the
15478 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15479 * detect the ports.
15480 */
15481 intel_ddi_init(dev, PORT_A);
15482 intel_ddi_init(dev, PORT_B);
15483 intel_ddi_init(dev, PORT_C);
15484
15485 intel_dsi_init(dev);
15486 } else if (HAS_DDI(dev_priv)) {
15487 int found;
15488
15489 /*
15490 * Haswell uses DDI functions to detect digital outputs.
15491 * On SKL pre-D0 the strap isn't connected, so we assume
15492 * it's there.
15493 */
15494 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15495 /* WaIgnoreDDIAStrap: skl */
15496 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15497 intel_ddi_init(dev, PORT_A);
15498
15499 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15500 * register */
15501 found = I915_READ(SFUSE_STRAP);
15502
15503 if (found & SFUSE_STRAP_DDIB_DETECTED)
15504 intel_ddi_init(dev, PORT_B);
15505 if (found & SFUSE_STRAP_DDIC_DETECTED)
15506 intel_ddi_init(dev, PORT_C);
15507 if (found & SFUSE_STRAP_DDID_DETECTED)
15508 intel_ddi_init(dev, PORT_D);
15509 /*
15510 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15511 */
15512 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
15513 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15514 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15515 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15516 intel_ddi_init(dev, PORT_E);
15517
15518 } else if (HAS_PCH_SPLIT(dev_priv)) {
15519 int found;
15520 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
15521
15522 if (has_edp_a(dev_priv))
15523 intel_dp_init(dev, DP_A, PORT_A);
15524
15525 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15526 /* PCH SDVOB multiplex with HDMIB */
15527 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15528 if (!found)
15529 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15530 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15531 intel_dp_init(dev, PCH_DP_B, PORT_B);
15532 }
15533
15534 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15535 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15536
15537 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15538 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15539
15540 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15541 intel_dp_init(dev, PCH_DP_C, PORT_C);
15542
15543 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15544 intel_dp_init(dev, PCH_DP_D, PORT_D);
15545 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15546 bool has_edp, has_port;
15547
15548 /*
15549 * The DP_DETECTED bit is the latched state of the DDC
15550 * SDA pin at boot. However since eDP doesn't require DDC
15551 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15552 * eDP ports may have been muxed to an alternate function.
15553 * Thus we can't rely on the DP_DETECTED bit alone to detect
15554 * eDP ports. Consult the VBT as well as DP_DETECTED to
15555 * detect eDP ports.
15556 *
15557 * Sadly the straps seem to be missing sometimes even for HDMI
15558 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15559 * and VBT for the presence of the port. Additionally we can't
15560 * trust the port type the VBT declares as we've seen at least
15561 * HDMI ports that the VBT claim are DP or eDP.
15562 */
15563 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
15564 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15565 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15566 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15567 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15568 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15569
15570 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
15571 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15572 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15573 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15574 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15575 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15576
15577 if (IS_CHERRYVIEW(dev_priv)) {
15578 /*
15579 * eDP not supported on port D,
15580 * so no need to worry about it
15581 */
15582 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15583 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15584 intel_dp_init(dev, CHV_DP_D, PORT_D);
15585 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15586 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15587 }
15588
15589 intel_dsi_init(dev);
15590 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
15591 bool found = false;
15592
15593 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15594 DRM_DEBUG_KMS("probing SDVOB\n");
15595 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15596 if (!found && IS_G4X(dev_priv)) {
15597 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15598 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15599 }
15600
15601 if (!found && IS_G4X(dev_priv))
15602 intel_dp_init(dev, DP_B, PORT_B);
15603 }
15604
15605 /* Before G4X SDVOC doesn't have its own detect register */
15606
15607 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15608 DRM_DEBUG_KMS("probing SDVOC\n");
15609 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15610 }
15611
15612 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15613
15614 if (IS_G4X(dev_priv)) {
15615 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15616 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15617 }
15618 if (IS_G4X(dev_priv))
15619 intel_dp_init(dev, DP_C, PORT_C);
15620 }
15621
15622 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15623 intel_dp_init(dev, DP_D, PORT_D);
15624 } else if (IS_GEN2(dev_priv))
15625 intel_dvo_init(dev);
15626
15627 if (SUPPORTS_TV(dev_priv))
15628 intel_tv_init(dev);
15629
15630 intel_psr_init(dev);
15631
15632 for_each_intel_encoder(dev, encoder) {
15633 encoder->base.possible_crtcs = encoder->crtc_mask;
15634 encoder->base.possible_clones =
15635 intel_encoder_clones(encoder);
15636 }
15637
15638 intel_init_pch_refclk(dev);
15639
15640 drm_helper_move_panel_connectors_to_head(dev);
15641 }
15642
15643 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15644 {
15645 struct drm_device *dev = fb->dev;
15646 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15647
15648 drm_framebuffer_cleanup(fb);
15649 mutex_lock(&dev->struct_mutex);
15650 WARN_ON(!intel_fb->obj->framebuffer_references--);
15651 i915_gem_object_put(intel_fb->obj);
15652 mutex_unlock(&dev->struct_mutex);
15653 kfree(intel_fb);
15654 }
15655
15656 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15657 struct drm_file *file,
15658 unsigned int *handle)
15659 {
15660 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15661 struct drm_i915_gem_object *obj = intel_fb->obj;
15662
15663 if (obj->userptr.mm) {
15664 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15665 return -EINVAL;
15666 }
15667
15668 return drm_gem_handle_create(file, &obj->base, handle);
15669 }
15670
15671 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15672 struct drm_file *file,
15673 unsigned flags, unsigned color,
15674 struct drm_clip_rect *clips,
15675 unsigned num_clips)
15676 {
15677 struct drm_device *dev = fb->dev;
15678 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15679 struct drm_i915_gem_object *obj = intel_fb->obj;
15680
15681 mutex_lock(&dev->struct_mutex);
15682 if (obj->pin_display && obj->cache_dirty)
15683 i915_gem_clflush_object(obj, true);
15684 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15685 mutex_unlock(&dev->struct_mutex);
15686
15687 return 0;
15688 }
15689
15690 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15691 .destroy = intel_user_framebuffer_destroy,
15692 .create_handle = intel_user_framebuffer_create_handle,
15693 .dirty = intel_user_framebuffer_dirty,
15694 };
15695
15696 static
15697 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15698 uint64_t fb_modifier, uint32_t pixel_format)
15699 {
15700 u32 gen = INTEL_INFO(dev_priv)->gen;
15701
15702 if (gen >= 9) {
15703 int cpp = drm_format_plane_cpp(pixel_format, 0);
15704
15705 /* "The stride in bytes must not exceed the of the size of 8K
15706 * pixels and 32K bytes."
15707 */
15708 return min(8192 * cpp, 32768);
15709 } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
15710 !IS_CHERRYVIEW(dev_priv)) {
15711 return 32*1024;
15712 } else if (gen >= 4) {
15713 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15714 return 16*1024;
15715 else
15716 return 32*1024;
15717 } else if (gen >= 3) {
15718 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15719 return 8*1024;
15720 else
15721 return 16*1024;
15722 } else {
15723 /* XXX DSPC is limited to 4k tiled */
15724 return 8*1024;
15725 }
15726 }
15727
15728 static int intel_framebuffer_init(struct drm_device *dev,
15729 struct intel_framebuffer *intel_fb,
15730 struct drm_mode_fb_cmd2 *mode_cmd,
15731 struct drm_i915_gem_object *obj)
15732 {
15733 struct drm_i915_private *dev_priv = to_i915(dev);
15734 unsigned int tiling = i915_gem_object_get_tiling(obj);
15735 int ret;
15736 u32 pitch_limit, stride_alignment;
15737 struct drm_format_name_buf format_name;
15738
15739 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15740
15741 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15742 /*
15743 * If there's a fence, enforce that
15744 * the fb modifier and tiling mode match.
15745 */
15746 if (tiling != I915_TILING_NONE &&
15747 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15748 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15749 return -EINVAL;
15750 }
15751 } else {
15752 if (tiling == I915_TILING_X) {
15753 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15754 } else if (tiling == I915_TILING_Y) {
15755 DRM_DEBUG("No Y tiling for legacy addfb\n");
15756 return -EINVAL;
15757 }
15758 }
15759
15760 /* Passed in modifier sanity checking. */
15761 switch (mode_cmd->modifier[0]) {
15762 case I915_FORMAT_MOD_Y_TILED:
15763 case I915_FORMAT_MOD_Yf_TILED:
15764 if (INTEL_GEN(dev_priv) < 9) {
15765 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15766 mode_cmd->modifier[0]);
15767 return -EINVAL;
15768 }
15769 case DRM_FORMAT_MOD_NONE:
15770 case I915_FORMAT_MOD_X_TILED:
15771 break;
15772 default:
15773 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15774 mode_cmd->modifier[0]);
15775 return -EINVAL;
15776 }
15777
15778 /*
15779 * gen2/3 display engine uses the fence if present,
15780 * so the tiling mode must match the fb modifier exactly.
15781 */
15782 if (INTEL_INFO(dev_priv)->gen < 4 &&
15783 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15784 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15785 return -EINVAL;
15786 }
15787
15788 stride_alignment = intel_fb_stride_alignment(dev_priv,
15789 mode_cmd->modifier[0],
15790 mode_cmd->pixel_format);
15791 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15792 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15793 mode_cmd->pitches[0], stride_alignment);
15794 return -EINVAL;
15795 }
15796
15797 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
15798 mode_cmd->pixel_format);
15799 if (mode_cmd->pitches[0] > pitch_limit) {
15800 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15801 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15802 "tiled" : "linear",
15803 mode_cmd->pitches[0], pitch_limit);
15804 return -EINVAL;
15805 }
15806
15807 /*
15808 * If there's a fence, enforce that
15809 * the fb pitch and fence stride match.
15810 */
15811 if (tiling != I915_TILING_NONE &&
15812 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15813 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15814 mode_cmd->pitches[0],
15815 i915_gem_object_get_stride(obj));
15816 return -EINVAL;
15817 }
15818
15819 /* Reject formats not supported by any plane early. */
15820 switch (mode_cmd->pixel_format) {
15821 case DRM_FORMAT_C8:
15822 case DRM_FORMAT_RGB565:
15823 case DRM_FORMAT_XRGB8888:
15824 case DRM_FORMAT_ARGB8888:
15825 break;
15826 case DRM_FORMAT_XRGB1555:
15827 if (INTEL_GEN(dev_priv) > 3) {
15828 DRM_DEBUG("unsupported pixel format: %s\n",
15829 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15830 return -EINVAL;
15831 }
15832 break;
15833 case DRM_FORMAT_ABGR8888:
15834 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
15835 INTEL_GEN(dev_priv) < 9) {
15836 DRM_DEBUG("unsupported pixel format: %s\n",
15837 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15838 return -EINVAL;
15839 }
15840 break;
15841 case DRM_FORMAT_XBGR8888:
15842 case DRM_FORMAT_XRGB2101010:
15843 case DRM_FORMAT_XBGR2101010:
15844 if (INTEL_GEN(dev_priv) < 4) {
15845 DRM_DEBUG("unsupported pixel format: %s\n",
15846 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15847 return -EINVAL;
15848 }
15849 break;
15850 case DRM_FORMAT_ABGR2101010:
15851 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
15852 DRM_DEBUG("unsupported pixel format: %s\n",
15853 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15854 return -EINVAL;
15855 }
15856 break;
15857 case DRM_FORMAT_YUYV:
15858 case DRM_FORMAT_UYVY:
15859 case DRM_FORMAT_YVYU:
15860 case DRM_FORMAT_VYUY:
15861 if (INTEL_GEN(dev_priv) < 5) {
15862 DRM_DEBUG("unsupported pixel format: %s\n",
15863 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15864 return -EINVAL;
15865 }
15866 break;
15867 default:
15868 DRM_DEBUG("unsupported pixel format: %s\n",
15869 drm_get_format_name(mode_cmd->pixel_format, &format_name));
15870 return -EINVAL;
15871 }
15872
15873 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15874 if (mode_cmd->offsets[0] != 0)
15875 return -EINVAL;
15876
15877 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15878 intel_fb->obj = obj;
15879
15880 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15881 if (ret)
15882 return ret;
15883
15884 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15885 if (ret) {
15886 DRM_ERROR("framebuffer init failed %d\n", ret);
15887 return ret;
15888 }
15889
15890 intel_fb->obj->framebuffer_references++;
15891
15892 return 0;
15893 }
15894
15895 static struct drm_framebuffer *
15896 intel_user_framebuffer_create(struct drm_device *dev,
15897 struct drm_file *filp,
15898 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15899 {
15900 struct drm_framebuffer *fb;
15901 struct drm_i915_gem_object *obj;
15902 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15903
15904 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15905 if (!obj)
15906 return ERR_PTR(-ENOENT);
15907
15908 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15909 if (IS_ERR(fb))
15910 i915_gem_object_put(obj);
15911
15912 return fb;
15913 }
15914
15915 static const struct drm_mode_config_funcs intel_mode_funcs = {
15916 .fb_create = intel_user_framebuffer_create,
15917 .output_poll_changed = intel_fbdev_output_poll_changed,
15918 .atomic_check = intel_atomic_check,
15919 .atomic_commit = intel_atomic_commit,
15920 .atomic_state_alloc = intel_atomic_state_alloc,
15921 .atomic_state_clear = intel_atomic_state_clear,
15922 };
15923
15924 /**
15925 * intel_init_display_hooks - initialize the display modesetting hooks
15926 * @dev_priv: device private
15927 */
15928 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15929 {
15930 if (INTEL_INFO(dev_priv)->gen >= 9) {
15931 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15932 dev_priv->display.get_initial_plane_config =
15933 skylake_get_initial_plane_config;
15934 dev_priv->display.crtc_compute_clock =
15935 haswell_crtc_compute_clock;
15936 dev_priv->display.crtc_enable = haswell_crtc_enable;
15937 dev_priv->display.crtc_disable = haswell_crtc_disable;
15938 } else if (HAS_DDI(dev_priv)) {
15939 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15940 dev_priv->display.get_initial_plane_config =
15941 ironlake_get_initial_plane_config;
15942 dev_priv->display.crtc_compute_clock =
15943 haswell_crtc_compute_clock;
15944 dev_priv->display.crtc_enable = haswell_crtc_enable;
15945 dev_priv->display.crtc_disable = haswell_crtc_disable;
15946 } else if (HAS_PCH_SPLIT(dev_priv)) {
15947 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15948 dev_priv->display.get_initial_plane_config =
15949 ironlake_get_initial_plane_config;
15950 dev_priv->display.crtc_compute_clock =
15951 ironlake_crtc_compute_clock;
15952 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15953 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15954 } else if (IS_CHERRYVIEW(dev_priv)) {
15955 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15956 dev_priv->display.get_initial_plane_config =
15957 i9xx_get_initial_plane_config;
15958 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15959 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15960 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15961 } else if (IS_VALLEYVIEW(dev_priv)) {
15962 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15963 dev_priv->display.get_initial_plane_config =
15964 i9xx_get_initial_plane_config;
15965 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15966 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15967 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15968 } else if (IS_G4X(dev_priv)) {
15969 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15970 dev_priv->display.get_initial_plane_config =
15971 i9xx_get_initial_plane_config;
15972 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15973 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15974 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15975 } else if (IS_PINEVIEW(dev_priv)) {
15976 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15977 dev_priv->display.get_initial_plane_config =
15978 i9xx_get_initial_plane_config;
15979 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15980 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15981 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15982 } else if (!IS_GEN2(dev_priv)) {
15983 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15984 dev_priv->display.get_initial_plane_config =
15985 i9xx_get_initial_plane_config;
15986 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15987 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15988 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15989 } else {
15990 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15991 dev_priv->display.get_initial_plane_config =
15992 i9xx_get_initial_plane_config;
15993 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15994 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15995 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15996 }
15997
15998 /* Returns the core display clock speed */
15999 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
16000 dev_priv->display.get_display_clock_speed =
16001 skylake_get_display_clock_speed;
16002 else if (IS_BROXTON(dev_priv))
16003 dev_priv->display.get_display_clock_speed =
16004 broxton_get_display_clock_speed;
16005 else if (IS_BROADWELL(dev_priv))
16006 dev_priv->display.get_display_clock_speed =
16007 broadwell_get_display_clock_speed;
16008 else if (IS_HASWELL(dev_priv))
16009 dev_priv->display.get_display_clock_speed =
16010 haswell_get_display_clock_speed;
16011 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16012 dev_priv->display.get_display_clock_speed =
16013 valleyview_get_display_clock_speed;
16014 else if (IS_GEN5(dev_priv))
16015 dev_priv->display.get_display_clock_speed =
16016 ilk_get_display_clock_speed;
16017 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
16018 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16019 dev_priv->display.get_display_clock_speed =
16020 i945_get_display_clock_speed;
16021 else if (IS_GM45(dev_priv))
16022 dev_priv->display.get_display_clock_speed =
16023 gm45_get_display_clock_speed;
16024 else if (IS_CRESTLINE(dev_priv))
16025 dev_priv->display.get_display_clock_speed =
16026 i965gm_get_display_clock_speed;
16027 else if (IS_PINEVIEW(dev_priv))
16028 dev_priv->display.get_display_clock_speed =
16029 pnv_get_display_clock_speed;
16030 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16031 dev_priv->display.get_display_clock_speed =
16032 g33_get_display_clock_speed;
16033 else if (IS_I915G(dev_priv))
16034 dev_priv->display.get_display_clock_speed =
16035 i915_get_display_clock_speed;
16036 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
16037 dev_priv->display.get_display_clock_speed =
16038 i9xx_misc_get_display_clock_speed;
16039 else if (IS_I915GM(dev_priv))
16040 dev_priv->display.get_display_clock_speed =
16041 i915gm_get_display_clock_speed;
16042 else if (IS_I865G(dev_priv))
16043 dev_priv->display.get_display_clock_speed =
16044 i865_get_display_clock_speed;
16045 else if (IS_I85X(dev_priv))
16046 dev_priv->display.get_display_clock_speed =
16047 i85x_get_display_clock_speed;
16048 else { /* 830 */
16049 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16050 dev_priv->display.get_display_clock_speed =
16051 i830_get_display_clock_speed;
16052 }
16053
16054 if (IS_GEN5(dev_priv)) {
16055 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16056 } else if (IS_GEN6(dev_priv)) {
16057 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16058 } else if (IS_IVYBRIDGE(dev_priv)) {
16059 /* FIXME: detect B0+ stepping and use auto training */
16060 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16061 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16062 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16063 }
16064
16065 if (IS_BROADWELL(dev_priv)) {
16066 dev_priv->display.modeset_commit_cdclk =
16067 broadwell_modeset_commit_cdclk;
16068 dev_priv->display.modeset_calc_cdclk =
16069 broadwell_modeset_calc_cdclk;
16070 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16071 dev_priv->display.modeset_commit_cdclk =
16072 valleyview_modeset_commit_cdclk;
16073 dev_priv->display.modeset_calc_cdclk =
16074 valleyview_modeset_calc_cdclk;
16075 } else if (IS_BROXTON(dev_priv)) {
16076 dev_priv->display.modeset_commit_cdclk =
16077 bxt_modeset_commit_cdclk;
16078 dev_priv->display.modeset_calc_cdclk =
16079 bxt_modeset_calc_cdclk;
16080 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16081 dev_priv->display.modeset_commit_cdclk =
16082 skl_modeset_commit_cdclk;
16083 dev_priv->display.modeset_calc_cdclk =
16084 skl_modeset_calc_cdclk;
16085 }
16086
16087 if (dev_priv->info.gen >= 9)
16088 dev_priv->display.update_crtcs = skl_update_crtcs;
16089 else
16090 dev_priv->display.update_crtcs = intel_update_crtcs;
16091
16092 switch (INTEL_INFO(dev_priv)->gen) {
16093 case 2:
16094 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16095 break;
16096
16097 case 3:
16098 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16099 break;
16100
16101 case 4:
16102 case 5:
16103 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16104 break;
16105
16106 case 6:
16107 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16108 break;
16109 case 7:
16110 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16111 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16112 break;
16113 case 9:
16114 /* Drop through - unsupported since execlist only. */
16115 default:
16116 /* Default just returns -ENODEV to indicate unsupported */
16117 dev_priv->display.queue_flip = intel_default_queue_flip;
16118 }
16119 }
16120
16121 /*
16122 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16123 * resume, or other times. This quirk makes sure that's the case for
16124 * affected systems.
16125 */
16126 static void quirk_pipea_force(struct drm_device *dev)
16127 {
16128 struct drm_i915_private *dev_priv = to_i915(dev);
16129
16130 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16131 DRM_INFO("applying pipe a force quirk\n");
16132 }
16133
16134 static void quirk_pipeb_force(struct drm_device *dev)
16135 {
16136 struct drm_i915_private *dev_priv = to_i915(dev);
16137
16138 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16139 DRM_INFO("applying pipe b force quirk\n");
16140 }
16141
16142 /*
16143 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16144 */
16145 static void quirk_ssc_force_disable(struct drm_device *dev)
16146 {
16147 struct drm_i915_private *dev_priv = to_i915(dev);
16148 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16149 DRM_INFO("applying lvds SSC disable quirk\n");
16150 }
16151
16152 /*
16153 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16154 * brightness value
16155 */
16156 static void quirk_invert_brightness(struct drm_device *dev)
16157 {
16158 struct drm_i915_private *dev_priv = to_i915(dev);
16159 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16160 DRM_INFO("applying inverted panel brightness quirk\n");
16161 }
16162
16163 /* Some VBT's incorrectly indicate no backlight is present */
16164 static void quirk_backlight_present(struct drm_device *dev)
16165 {
16166 struct drm_i915_private *dev_priv = to_i915(dev);
16167 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16168 DRM_INFO("applying backlight present quirk\n");
16169 }
16170
16171 struct intel_quirk {
16172 int device;
16173 int subsystem_vendor;
16174 int subsystem_device;
16175 void (*hook)(struct drm_device *dev);
16176 };
16177
16178 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16179 struct intel_dmi_quirk {
16180 void (*hook)(struct drm_device *dev);
16181 const struct dmi_system_id (*dmi_id_list)[];
16182 };
16183
16184 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16185 {
16186 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16187 return 1;
16188 }
16189
16190 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16191 {
16192 .dmi_id_list = &(const struct dmi_system_id[]) {
16193 {
16194 .callback = intel_dmi_reverse_brightness,
16195 .ident = "NCR Corporation",
16196 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16197 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16198 },
16199 },
16200 { } /* terminating entry */
16201 },
16202 .hook = quirk_invert_brightness,
16203 },
16204 };
16205
16206 static struct intel_quirk intel_quirks[] = {
16207 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16208 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16209
16210 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16211 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16212
16213 /* 830 needs to leave pipe A & dpll A up */
16214 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16215
16216 /* 830 needs to leave pipe B & dpll B up */
16217 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16218
16219 /* Lenovo U160 cannot use SSC on LVDS */
16220 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16221
16222 /* Sony Vaio Y cannot use SSC on LVDS */
16223 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16224
16225 /* Acer Aspire 5734Z must invert backlight brightness */
16226 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16227
16228 /* Acer/eMachines G725 */
16229 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16230
16231 /* Acer/eMachines e725 */
16232 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16233
16234 /* Acer/Packard Bell NCL20 */
16235 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16236
16237 /* Acer Aspire 4736Z */
16238 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16239
16240 /* Acer Aspire 5336 */
16241 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16242
16243 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16244 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16245
16246 /* Acer C720 Chromebook (Core i3 4005U) */
16247 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16248
16249 /* Apple Macbook 2,1 (Core 2 T7400) */
16250 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16251
16252 /* Apple Macbook 4,1 */
16253 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16254
16255 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16256 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16257
16258 /* HP Chromebook 14 (Celeron 2955U) */
16259 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16260
16261 /* Dell Chromebook 11 */
16262 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16263
16264 /* Dell Chromebook 11 (2015 version) */
16265 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16266 };
16267
16268 static void intel_init_quirks(struct drm_device *dev)
16269 {
16270 struct pci_dev *d = dev->pdev;
16271 int i;
16272
16273 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16274 struct intel_quirk *q = &intel_quirks[i];
16275
16276 if (d->device == q->device &&
16277 (d->subsystem_vendor == q->subsystem_vendor ||
16278 q->subsystem_vendor == PCI_ANY_ID) &&
16279 (d->subsystem_device == q->subsystem_device ||
16280 q->subsystem_device == PCI_ANY_ID))
16281 q->hook(dev);
16282 }
16283 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16284 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16285 intel_dmi_quirks[i].hook(dev);
16286 }
16287 }
16288
16289 /* Disable the VGA plane that we never use */
16290 static void i915_disable_vga(struct drm_i915_private *dev_priv)
16291 {
16292 struct pci_dev *pdev = dev_priv->drm.pdev;
16293 u8 sr1;
16294 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16295
16296 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16297 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16298 outb(SR01, VGA_SR_INDEX);
16299 sr1 = inb(VGA_SR_DATA);
16300 outb(sr1 | 1<<5, VGA_SR_DATA);
16301 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16302 udelay(300);
16303
16304 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16305 POSTING_READ(vga_reg);
16306 }
16307
16308 void intel_modeset_init_hw(struct drm_device *dev)
16309 {
16310 struct drm_i915_private *dev_priv = to_i915(dev);
16311
16312 intel_update_cdclk(dev_priv);
16313
16314 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16315
16316 intel_init_clock_gating(dev_priv);
16317 }
16318
16319 /*
16320 * Calculate what we think the watermarks should be for the state we've read
16321 * out of the hardware and then immediately program those watermarks so that
16322 * we ensure the hardware settings match our internal state.
16323 *
16324 * We can calculate what we think WM's should be by creating a duplicate of the
16325 * current state (which was constructed during hardware readout) and running it
16326 * through the atomic check code to calculate new watermark values in the
16327 * state object.
16328 */
16329 static void sanitize_watermarks(struct drm_device *dev)
16330 {
16331 struct drm_i915_private *dev_priv = to_i915(dev);
16332 struct drm_atomic_state *state;
16333 struct intel_atomic_state *intel_state;
16334 struct drm_crtc *crtc;
16335 struct drm_crtc_state *cstate;
16336 struct drm_modeset_acquire_ctx ctx;
16337 int ret;
16338 int i;
16339
16340 /* Only supported on platforms that use atomic watermark design */
16341 if (!dev_priv->display.optimize_watermarks)
16342 return;
16343
16344 /*
16345 * We need to hold connection_mutex before calling duplicate_state so
16346 * that the connector loop is protected.
16347 */
16348 drm_modeset_acquire_init(&ctx, 0);
16349 retry:
16350 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16351 if (ret == -EDEADLK) {
16352 drm_modeset_backoff(&ctx);
16353 goto retry;
16354 } else if (WARN_ON(ret)) {
16355 goto fail;
16356 }
16357
16358 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16359 if (WARN_ON(IS_ERR(state)))
16360 goto fail;
16361
16362 intel_state = to_intel_atomic_state(state);
16363
16364 /*
16365 * Hardware readout is the only time we don't want to calculate
16366 * intermediate watermarks (since we don't trust the current
16367 * watermarks).
16368 */
16369 intel_state->skip_intermediate_wm = true;
16370
16371 ret = intel_atomic_check(dev, state);
16372 if (ret) {
16373 /*
16374 * If we fail here, it means that the hardware appears to be
16375 * programmed in a way that shouldn't be possible, given our
16376 * understanding of watermark requirements. This might mean a
16377 * mistake in the hardware readout code or a mistake in the
16378 * watermark calculations for a given platform. Raise a WARN
16379 * so that this is noticeable.
16380 *
16381 * If this actually happens, we'll have to just leave the
16382 * BIOS-programmed watermarks untouched and hope for the best.
16383 */
16384 WARN(true, "Could not determine valid watermarks for inherited state\n");
16385 goto put_state;
16386 }
16387
16388 /* Write calculated watermark values back */
16389 for_each_crtc_in_state(state, crtc, cstate, i) {
16390 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16391
16392 cs->wm.need_postvbl_update = true;
16393 dev_priv->display.optimize_watermarks(intel_state, cs);
16394 }
16395
16396 put_state:
16397 drm_atomic_state_put(state);
16398 fail:
16399 drm_modeset_drop_locks(&ctx);
16400 drm_modeset_acquire_fini(&ctx);
16401 }
16402
16403 static void intel_atomic_helper_free_state(struct work_struct *work)
16404 {
16405 struct drm_i915_private *dev_priv =
16406 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
16407 struct intel_atomic_state *state, *next;
16408 struct llist_node *freed;
16409
16410 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
16411 llist_for_each_entry_safe(state, next, freed, freed)
16412 drm_atomic_state_put(&state->base);
16413 }
16414
16415 int intel_modeset_init(struct drm_device *dev)
16416 {
16417 struct drm_i915_private *dev_priv = to_i915(dev);
16418 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16419 enum pipe pipe;
16420 struct intel_crtc *crtc;
16421
16422 drm_mode_config_init(dev);
16423
16424 dev->mode_config.min_width = 0;
16425 dev->mode_config.min_height = 0;
16426
16427 dev->mode_config.preferred_depth = 24;
16428 dev->mode_config.prefer_shadow = 1;
16429
16430 dev->mode_config.allow_fb_modifiers = true;
16431
16432 dev->mode_config.funcs = &intel_mode_funcs;
16433
16434 INIT_WORK(&dev_priv->atomic_helper.free_work,
16435 intel_atomic_helper_free_state);
16436
16437 intel_init_quirks(dev);
16438
16439 intel_init_pm(dev_priv);
16440
16441 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16442 return 0;
16443
16444 /*
16445 * There may be no VBT; and if the BIOS enabled SSC we can
16446 * just keep using it to avoid unnecessary flicker. Whereas if the
16447 * BIOS isn't using it, don't assume it will work even if the VBT
16448 * indicates as much.
16449 */
16450 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16451 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16452 DREF_SSC1_ENABLE);
16453
16454 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16455 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16456 bios_lvds_use_ssc ? "en" : "dis",
16457 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16458 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16459 }
16460 }
16461
16462 if (IS_GEN2(dev_priv)) {
16463 dev->mode_config.max_width = 2048;
16464 dev->mode_config.max_height = 2048;
16465 } else if (IS_GEN3(dev_priv)) {
16466 dev->mode_config.max_width = 4096;
16467 dev->mode_config.max_height = 4096;
16468 } else {
16469 dev->mode_config.max_width = 8192;
16470 dev->mode_config.max_height = 8192;
16471 }
16472
16473 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
16474 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
16475 dev->mode_config.cursor_height = 1023;
16476 } else if (IS_GEN2(dev_priv)) {
16477 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16478 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16479 } else {
16480 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16481 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16482 }
16483
16484 dev->mode_config.fb_base = ggtt->mappable_base;
16485
16486 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16487 INTEL_INFO(dev_priv)->num_pipes,
16488 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16489
16490 for_each_pipe(dev_priv, pipe) {
16491 int ret;
16492
16493 ret = intel_crtc_init(dev_priv, pipe);
16494 if (ret) {
16495 drm_mode_config_cleanup(dev);
16496 return ret;
16497 }
16498 }
16499
16500 intel_update_czclk(dev_priv);
16501 intel_update_cdclk(dev_priv);
16502 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16503
16504 intel_shared_dpll_init(dev);
16505
16506 if (dev_priv->max_cdclk_freq == 0)
16507 intel_update_max_cdclk(dev_priv);
16508
16509 /* Just disable it once at startup */
16510 i915_disable_vga(dev_priv);
16511 intel_setup_outputs(dev);
16512
16513 drm_modeset_lock_all(dev);
16514 intel_modeset_setup_hw_state(dev);
16515 drm_modeset_unlock_all(dev);
16516
16517 for_each_intel_crtc(dev, crtc) {
16518 struct intel_initial_plane_config plane_config = {};
16519
16520 if (!crtc->active)
16521 continue;
16522
16523 /*
16524 * Note that reserving the BIOS fb up front prevents us
16525 * from stuffing other stolen allocations like the ring
16526 * on top. This prevents some ugliness at boot time, and
16527 * can even allow for smooth boot transitions if the BIOS
16528 * fb is large enough for the active pipe configuration.
16529 */
16530 dev_priv->display.get_initial_plane_config(crtc,
16531 &plane_config);
16532
16533 /*
16534 * If the fb is shared between multiple heads, we'll
16535 * just get the first one.
16536 */
16537 intel_find_initial_plane_obj(crtc, &plane_config);
16538 }
16539
16540 /*
16541 * Make sure hardware watermarks really match the state we read out.
16542 * Note that we need to do this after reconstructing the BIOS fb's
16543 * since the watermark calculation done here will use pstate->fb.
16544 */
16545 sanitize_watermarks(dev);
16546
16547 return 0;
16548 }
16549
16550 static void intel_enable_pipe_a(struct drm_device *dev)
16551 {
16552 struct intel_connector *connector;
16553 struct drm_connector *crt = NULL;
16554 struct intel_load_detect_pipe load_detect_temp;
16555 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16556
16557 /* We can't just switch on the pipe A, we need to set things up with a
16558 * proper mode and output configuration. As a gross hack, enable pipe A
16559 * by enabling the load detect pipe once. */
16560 for_each_intel_connector(dev, connector) {
16561 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16562 crt = &connector->base;
16563 break;
16564 }
16565 }
16566
16567 if (!crt)
16568 return;
16569
16570 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16571 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16572 }
16573
16574 static bool
16575 intel_check_plane_mapping(struct intel_crtc *crtc)
16576 {
16577 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
16578 u32 val;
16579
16580 if (INTEL_INFO(dev_priv)->num_pipes == 1)
16581 return true;
16582
16583 val = I915_READ(DSPCNTR(!crtc->plane));
16584
16585 if ((val & DISPLAY_PLANE_ENABLE) &&
16586 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16587 return false;
16588
16589 return true;
16590 }
16591
16592 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16593 {
16594 struct drm_device *dev = crtc->base.dev;
16595 struct intel_encoder *encoder;
16596
16597 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16598 return true;
16599
16600 return false;
16601 }
16602
16603 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16604 {
16605 struct drm_device *dev = encoder->base.dev;
16606 struct intel_connector *connector;
16607
16608 for_each_connector_on_encoder(dev, &encoder->base, connector)
16609 return connector;
16610
16611 return NULL;
16612 }
16613
16614 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16615 enum transcoder pch_transcoder)
16616 {
16617 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16618 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16619 }
16620
16621 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16622 {
16623 struct drm_device *dev = crtc->base.dev;
16624 struct drm_i915_private *dev_priv = to_i915(dev);
16625 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16626
16627 /* Clear any frame start delays used for debugging left by the BIOS */
16628 if (!transcoder_is_dsi(cpu_transcoder)) {
16629 i915_reg_t reg = PIPECONF(cpu_transcoder);
16630
16631 I915_WRITE(reg,
16632 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16633 }
16634
16635 /* restore vblank interrupts to correct state */
16636 drm_crtc_vblank_reset(&crtc->base);
16637 if (crtc->active) {
16638 struct intel_plane *plane;
16639
16640 drm_crtc_vblank_on(&crtc->base);
16641
16642 /* Disable everything but the primary plane */
16643 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16644 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16645 continue;
16646
16647 plane->disable_plane(&plane->base, &crtc->base);
16648 }
16649 }
16650
16651 /* We need to sanitize the plane -> pipe mapping first because this will
16652 * disable the crtc (and hence change the state) if it is wrong. Note
16653 * that gen4+ has a fixed plane -> pipe mapping. */
16654 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
16655 bool plane;
16656
16657 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16658 crtc->base.base.id, crtc->base.name);
16659
16660 /* Pipe has the wrong plane attached and the plane is active.
16661 * Temporarily change the plane mapping and disable everything
16662 * ... */
16663 plane = crtc->plane;
16664 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16665 crtc->plane = !plane;
16666 intel_crtc_disable_noatomic(&crtc->base);
16667 crtc->plane = plane;
16668 }
16669
16670 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16671 crtc->pipe == PIPE_A && !crtc->active) {
16672 /* BIOS forgot to enable pipe A, this mostly happens after
16673 * resume. Force-enable the pipe to fix this, the update_dpms
16674 * call below we restore the pipe to the right state, but leave
16675 * the required bits on. */
16676 intel_enable_pipe_a(dev);
16677 }
16678
16679 /* Adjust the state of the output pipe according to whether we
16680 * have active connectors/encoders. */
16681 if (crtc->active && !intel_crtc_has_encoders(crtc))
16682 intel_crtc_disable_noatomic(&crtc->base);
16683
16684 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
16685 /*
16686 * We start out with underrun reporting disabled to avoid races.
16687 * For correct bookkeeping mark this on active crtcs.
16688 *
16689 * Also on gmch platforms we dont have any hardware bits to
16690 * disable the underrun reporting. Which means we need to start
16691 * out with underrun reporting disabled also on inactive pipes,
16692 * since otherwise we'll complain about the garbage we read when
16693 * e.g. coming up after runtime pm.
16694 *
16695 * No protection against concurrent access is required - at
16696 * worst a fifo underrun happens which also sets this to false.
16697 */
16698 crtc->cpu_fifo_underrun_disabled = true;
16699 /*
16700 * We track the PCH trancoder underrun reporting state
16701 * within the crtc. With crtc for pipe A housing the underrun
16702 * reporting state for PCH transcoder A, crtc for pipe B housing
16703 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16704 * and marking underrun reporting as disabled for the non-existing
16705 * PCH transcoders B and C would prevent enabling the south
16706 * error interrupt (see cpt_can_enable_serr_int()).
16707 */
16708 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16709 crtc->pch_fifo_underrun_disabled = true;
16710 }
16711 }
16712
16713 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16714 {
16715 struct intel_connector *connector;
16716
16717 /* We need to check both for a crtc link (meaning that the
16718 * encoder is active and trying to read from a pipe) and the
16719 * pipe itself being active. */
16720 bool has_active_crtc = encoder->base.crtc &&
16721 to_intel_crtc(encoder->base.crtc)->active;
16722
16723 connector = intel_encoder_find_connector(encoder);
16724 if (connector && !has_active_crtc) {
16725 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16726 encoder->base.base.id,
16727 encoder->base.name);
16728
16729 /* Connector is active, but has no active pipe. This is
16730 * fallout from our resume register restoring. Disable
16731 * the encoder manually again. */
16732 if (encoder->base.crtc) {
16733 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16734
16735 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16736 encoder->base.base.id,
16737 encoder->base.name);
16738 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16739 if (encoder->post_disable)
16740 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16741 }
16742 encoder->base.crtc = NULL;
16743
16744 /* Inconsistent output/port/pipe state happens presumably due to
16745 * a bug in one of the get_hw_state functions. Or someplace else
16746 * in our code, like the register restore mess on resume. Clamp
16747 * things to off as a safer default. */
16748
16749 connector->base.dpms = DRM_MODE_DPMS_OFF;
16750 connector->base.encoder = NULL;
16751 }
16752 /* Enabled encoders without active connectors will be fixed in
16753 * the crtc fixup. */
16754 }
16755
16756 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16757 {
16758 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16759
16760 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16761 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16762 i915_disable_vga(dev_priv);
16763 }
16764 }
16765
16766 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16767 {
16768 /* This function can be called both from intel_modeset_setup_hw_state or
16769 * at a very early point in our resume sequence, where the power well
16770 * structures are not yet restored. Since this function is at a very
16771 * paranoid "someone might have enabled VGA while we were not looking"
16772 * level, just check if the power well is enabled instead of trying to
16773 * follow the "don't touch the power well if we don't need it" policy
16774 * the rest of the driver uses. */
16775 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16776 return;
16777
16778 i915_redisable_vga_power_on(dev_priv);
16779
16780 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16781 }
16782
16783 static bool primary_get_hw_state(struct intel_plane *plane)
16784 {
16785 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16786
16787 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16788 }
16789
16790 /* FIXME read out full plane state for all planes */
16791 static void readout_plane_state(struct intel_crtc *crtc)
16792 {
16793 struct drm_plane *primary = crtc->base.primary;
16794 struct intel_plane_state *plane_state =
16795 to_intel_plane_state(primary->state);
16796
16797 plane_state->base.visible = crtc->active &&
16798 primary_get_hw_state(to_intel_plane(primary));
16799
16800 if (plane_state->base.visible)
16801 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16802 }
16803
16804 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16805 {
16806 struct drm_i915_private *dev_priv = to_i915(dev);
16807 enum pipe pipe;
16808 struct intel_crtc *crtc;
16809 struct intel_encoder *encoder;
16810 struct intel_connector *connector;
16811 int i;
16812
16813 dev_priv->active_crtcs = 0;
16814
16815 for_each_intel_crtc(dev, crtc) {
16816 struct intel_crtc_state *crtc_state = crtc->config;
16817
16818 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16819 memset(crtc_state, 0, sizeof(*crtc_state));
16820 crtc_state->base.crtc = &crtc->base;
16821
16822 crtc_state->base.active = crtc_state->base.enable =
16823 dev_priv->display.get_pipe_config(crtc, crtc_state);
16824
16825 crtc->base.enabled = crtc_state->base.enable;
16826 crtc->active = crtc_state->base.active;
16827
16828 if (crtc_state->base.active)
16829 dev_priv->active_crtcs |= 1 << crtc->pipe;
16830
16831 readout_plane_state(crtc);
16832
16833 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16834 crtc->base.base.id, crtc->base.name,
16835 enableddisabled(crtc->active));
16836 }
16837
16838 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16839 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16840
16841 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16842 &pll->config.hw_state);
16843 pll->config.crtc_mask = 0;
16844 for_each_intel_crtc(dev, crtc) {
16845 if (crtc->active && crtc->config->shared_dpll == pll)
16846 pll->config.crtc_mask |= 1 << crtc->pipe;
16847 }
16848 pll->active_mask = pll->config.crtc_mask;
16849
16850 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16851 pll->name, pll->config.crtc_mask, pll->on);
16852 }
16853
16854 for_each_intel_encoder(dev, encoder) {
16855 pipe = 0;
16856
16857 if (encoder->get_hw_state(encoder, &pipe)) {
16858 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16859
16860 encoder->base.crtc = &crtc->base;
16861 crtc->config->output_types |= 1 << encoder->type;
16862 encoder->get_config(encoder, crtc->config);
16863 } else {
16864 encoder->base.crtc = NULL;
16865 }
16866
16867 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16868 encoder->base.base.id, encoder->base.name,
16869 enableddisabled(encoder->base.crtc),
16870 pipe_name(pipe));
16871 }
16872
16873 for_each_intel_connector(dev, connector) {
16874 if (connector->get_hw_state(connector)) {
16875 connector->base.dpms = DRM_MODE_DPMS_ON;
16876
16877 encoder = connector->encoder;
16878 connector->base.encoder = &encoder->base;
16879
16880 if (encoder->base.crtc &&
16881 encoder->base.crtc->state->active) {
16882 /*
16883 * This has to be done during hardware readout
16884 * because anything calling .crtc_disable may
16885 * rely on the connector_mask being accurate.
16886 */
16887 encoder->base.crtc->state->connector_mask |=
16888 1 << drm_connector_index(&connector->base);
16889 encoder->base.crtc->state->encoder_mask |=
16890 1 << drm_encoder_index(&encoder->base);
16891 }
16892
16893 } else {
16894 connector->base.dpms = DRM_MODE_DPMS_OFF;
16895 connector->base.encoder = NULL;
16896 }
16897 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16898 connector->base.base.id, connector->base.name,
16899 enableddisabled(connector->base.encoder));
16900 }
16901
16902 for_each_intel_crtc(dev, crtc) {
16903 int pixclk = 0;
16904
16905 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16906
16907 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16908 if (crtc->base.state->active) {
16909 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16910 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16911 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16912
16913 /*
16914 * The initial mode needs to be set in order to keep
16915 * the atomic core happy. It wants a valid mode if the
16916 * crtc's enabled, so we do the above call.
16917 *
16918 * At this point some state updated by the connectors
16919 * in their ->detect() callback has not run yet, so
16920 * no recalculation can be done yet.
16921 *
16922 * Even if we could do a recalculation and modeset
16923 * right now it would cause a double modeset if
16924 * fbdev or userspace chooses a different initial mode.
16925 *
16926 * If that happens, someone indicated they wanted a
16927 * mode change, which means it's safe to do a full
16928 * recalculation.
16929 */
16930 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16931
16932 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16933 pixclk = ilk_pipe_pixel_rate(crtc->config);
16934 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16935 pixclk = crtc->config->base.adjusted_mode.crtc_clock;
16936 else
16937 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16938
16939 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16940 if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
16941 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16942
16943 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16944 update_scanline_offset(crtc);
16945 }
16946
16947 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16948
16949 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16950 }
16951 }
16952
16953 /* Scan out the current hw modeset state,
16954 * and sanitizes it to the current state
16955 */
16956 static void
16957 intel_modeset_setup_hw_state(struct drm_device *dev)
16958 {
16959 struct drm_i915_private *dev_priv = to_i915(dev);
16960 enum pipe pipe;
16961 struct intel_crtc *crtc;
16962 struct intel_encoder *encoder;
16963 int i;
16964
16965 intel_modeset_readout_hw_state(dev);
16966
16967 /* HW state is read out, now we need to sanitize this mess. */
16968 for_each_intel_encoder(dev, encoder) {
16969 intel_sanitize_encoder(encoder);
16970 }
16971
16972 for_each_pipe(dev_priv, pipe) {
16973 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16974
16975 intel_sanitize_crtc(crtc);
16976 intel_dump_pipe_config(crtc, crtc->config,
16977 "[setup_hw_state]");
16978 }
16979
16980 intel_modeset_update_connector_atomic_state(dev);
16981
16982 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16983 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16984
16985 if (!pll->on || pll->active_mask)
16986 continue;
16987
16988 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16989
16990 pll->funcs.disable(dev_priv, pll);
16991 pll->on = false;
16992 }
16993
16994 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16995 vlv_wm_get_hw_state(dev);
16996 else if (IS_GEN9(dev_priv))
16997 skl_wm_get_hw_state(dev);
16998 else if (HAS_PCH_SPLIT(dev_priv))
16999 ilk_wm_get_hw_state(dev);
17000
17001 for_each_intel_crtc(dev, crtc) {
17002 unsigned long put_domains;
17003
17004 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
17005 if (WARN_ON(put_domains))
17006 modeset_put_power_domains(dev_priv, put_domains);
17007 }
17008 intel_display_set_init_power(dev_priv, false);
17009
17010 intel_fbc_init_pipe_state(dev_priv);
17011 }
17012
17013 void intel_display_resume(struct drm_device *dev)
17014 {
17015 struct drm_i915_private *dev_priv = to_i915(dev);
17016 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17017 struct drm_modeset_acquire_ctx ctx;
17018 int ret;
17019
17020 dev_priv->modeset_restore_state = NULL;
17021 if (state)
17022 state->acquire_ctx = &ctx;
17023
17024 /*
17025 * This is a cludge because with real atomic modeset mode_config.mutex
17026 * won't be taken. Unfortunately some probed state like
17027 * audio_codec_enable is still protected by mode_config.mutex, so lock
17028 * it here for now.
17029 */
17030 mutex_lock(&dev->mode_config.mutex);
17031 drm_modeset_acquire_init(&ctx, 0);
17032
17033 while (1) {
17034 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17035 if (ret != -EDEADLK)
17036 break;
17037
17038 drm_modeset_backoff(&ctx);
17039 }
17040
17041 if (!ret)
17042 ret = __intel_display_resume(dev, state);
17043
17044 drm_modeset_drop_locks(&ctx);
17045 drm_modeset_acquire_fini(&ctx);
17046 mutex_unlock(&dev->mode_config.mutex);
17047
17048 if (ret)
17049 DRM_ERROR("Restoring old state failed with %i\n", ret);
17050 if (state)
17051 drm_atomic_state_put(state);
17052 }
17053
17054 void intel_modeset_gem_init(struct drm_device *dev)
17055 {
17056 struct drm_i915_private *dev_priv = to_i915(dev);
17057
17058 intel_init_gt_powersave(dev_priv);
17059
17060 intel_modeset_init_hw(dev);
17061
17062 intel_setup_overlay(dev_priv);
17063 }
17064
17065 int intel_connector_register(struct drm_connector *connector)
17066 {
17067 struct intel_connector *intel_connector = to_intel_connector(connector);
17068 int ret;
17069
17070 ret = intel_backlight_device_register(intel_connector);
17071 if (ret)
17072 goto err;
17073
17074 return 0;
17075
17076 err:
17077 return ret;
17078 }
17079
17080 void intel_connector_unregister(struct drm_connector *connector)
17081 {
17082 struct intel_connector *intel_connector = to_intel_connector(connector);
17083
17084 intel_backlight_device_unregister(intel_connector);
17085 intel_panel_destroy_backlight(connector);
17086 }
17087
17088 void intel_modeset_cleanup(struct drm_device *dev)
17089 {
17090 struct drm_i915_private *dev_priv = to_i915(dev);
17091
17092 flush_work(&dev_priv->atomic_helper.free_work);
17093 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
17094
17095 intel_disable_gt_powersave(dev_priv);
17096
17097 /*
17098 * Interrupts and polling as the first thing to avoid creating havoc.
17099 * Too much stuff here (turning of connectors, ...) would
17100 * experience fancy races otherwise.
17101 */
17102 intel_irq_uninstall(dev_priv);
17103
17104 /*
17105 * Due to the hpd irq storm handling the hotplug work can re-arm the
17106 * poll handlers. Hence disable polling after hpd handling is shut down.
17107 */
17108 drm_kms_helper_poll_fini(dev);
17109
17110 intel_unregister_dsm_handler();
17111
17112 intel_fbc_global_disable(dev_priv);
17113
17114 /* flush any delayed tasks or pending work */
17115 flush_scheduled_work();
17116
17117 drm_mode_config_cleanup(dev);
17118
17119 intel_cleanup_overlay(dev_priv);
17120
17121 intel_cleanup_gt_powersave(dev_priv);
17122
17123 intel_teardown_gmbus(dev);
17124 }
17125
17126 void intel_connector_attach_encoder(struct intel_connector *connector,
17127 struct intel_encoder *encoder)
17128 {
17129 connector->encoder = encoder;
17130 drm_mode_connector_attach_encoder(&connector->base,
17131 &encoder->base);
17132 }
17133
17134 /*
17135 * set vga decode state - true == enable VGA decode
17136 */
17137 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17138 {
17139 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17140 u16 gmch_ctrl;
17141
17142 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17143 DRM_ERROR("failed to read control word\n");
17144 return -EIO;
17145 }
17146
17147 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17148 return 0;
17149
17150 if (state)
17151 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17152 else
17153 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17154
17155 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17156 DRM_ERROR("failed to write control word\n");
17157 return -EIO;
17158 }
17159
17160 return 0;
17161 }
17162
17163 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17164
17165 struct intel_display_error_state {
17166
17167 u32 power_well_driver;
17168
17169 int num_transcoders;
17170
17171 struct intel_cursor_error_state {
17172 u32 control;
17173 u32 position;
17174 u32 base;
17175 u32 size;
17176 } cursor[I915_MAX_PIPES];
17177
17178 struct intel_pipe_error_state {
17179 bool power_domain_on;
17180 u32 source;
17181 u32 stat;
17182 } pipe[I915_MAX_PIPES];
17183
17184 struct intel_plane_error_state {
17185 u32 control;
17186 u32 stride;
17187 u32 size;
17188 u32 pos;
17189 u32 addr;
17190 u32 surface;
17191 u32 tile_offset;
17192 } plane[I915_MAX_PIPES];
17193
17194 struct intel_transcoder_error_state {
17195 bool power_domain_on;
17196 enum transcoder cpu_transcoder;
17197
17198 u32 conf;
17199
17200 u32 htotal;
17201 u32 hblank;
17202 u32 hsync;
17203 u32 vtotal;
17204 u32 vblank;
17205 u32 vsync;
17206 } transcoder[4];
17207 };
17208
17209 struct intel_display_error_state *
17210 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17211 {
17212 struct intel_display_error_state *error;
17213 int transcoders[] = {
17214 TRANSCODER_A,
17215 TRANSCODER_B,
17216 TRANSCODER_C,
17217 TRANSCODER_EDP,
17218 };
17219 int i;
17220
17221 if (INTEL_INFO(dev_priv)->num_pipes == 0)
17222 return NULL;
17223
17224 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17225 if (error == NULL)
17226 return NULL;
17227
17228 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17229 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17230
17231 for_each_pipe(dev_priv, i) {
17232 error->pipe[i].power_domain_on =
17233 __intel_display_power_is_enabled(dev_priv,
17234 POWER_DOMAIN_PIPE(i));
17235 if (!error->pipe[i].power_domain_on)
17236 continue;
17237
17238 error->cursor[i].control = I915_READ(CURCNTR(i));
17239 error->cursor[i].position = I915_READ(CURPOS(i));
17240 error->cursor[i].base = I915_READ(CURBASE(i));
17241
17242 error->plane[i].control = I915_READ(DSPCNTR(i));
17243 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17244 if (INTEL_GEN(dev_priv) <= 3) {
17245 error->plane[i].size = I915_READ(DSPSIZE(i));
17246 error->plane[i].pos = I915_READ(DSPPOS(i));
17247 }
17248 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17249 error->plane[i].addr = I915_READ(DSPADDR(i));
17250 if (INTEL_GEN(dev_priv) >= 4) {
17251 error->plane[i].surface = I915_READ(DSPSURF(i));
17252 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17253 }
17254
17255 error->pipe[i].source = I915_READ(PIPESRC(i));
17256
17257 if (HAS_GMCH_DISPLAY(dev_priv))
17258 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17259 }
17260
17261 /* Note: this does not include DSI transcoders. */
17262 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17263 if (HAS_DDI(dev_priv))
17264 error->num_transcoders++; /* Account for eDP. */
17265
17266 for (i = 0; i < error->num_transcoders; i++) {
17267 enum transcoder cpu_transcoder = transcoders[i];
17268
17269 error->transcoder[i].power_domain_on =
17270 __intel_display_power_is_enabled(dev_priv,
17271 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17272 if (!error->transcoder[i].power_domain_on)
17273 continue;
17274
17275 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17276
17277 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17278 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17279 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17280 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17281 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17282 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17283 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17284 }
17285
17286 return error;
17287 }
17288
17289 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17290
17291 void
17292 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17293 struct drm_i915_private *dev_priv,
17294 struct intel_display_error_state *error)
17295 {
17296 int i;
17297
17298 if (!error)
17299 return;
17300
17301 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17302 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17303 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17304 error->power_well_driver);
17305 for_each_pipe(dev_priv, i) {
17306 err_printf(m, "Pipe [%d]:\n", i);
17307 err_printf(m, " Power: %s\n",
17308 onoff(error->pipe[i].power_domain_on));
17309 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17310 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17311
17312 err_printf(m, "Plane [%d]:\n", i);
17313 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17314 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17315 if (INTEL_GEN(dev_priv) <= 3) {
17316 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17317 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17318 }
17319 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17320 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17321 if (INTEL_GEN(dev_priv) >= 4) {
17322 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17323 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17324 }
17325
17326 err_printf(m, "Cursor [%d]:\n", i);
17327 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17328 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17329 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17330 }
17331
17332 for (i = 0; i < error->num_transcoders; i++) {
17333 err_printf(m, "CPU transcoder: %s\n",
17334 transcoder_name(error->transcoder[i].cpu_transcoder));
17335 err_printf(m, " Power: %s\n",
17336 onoff(error->transcoder[i].power_domain_on));
17337 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17338 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17339 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17340 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17341 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17342 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17343 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17344 }
17345 }
17346
17347 #endif
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