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drm/i915: Remove intel_clock_t typedef
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg, int ref_freq)
152 {
153 u32 val;
154 int divider;
155
156 mutex_lock(&dev_priv->sb_lock);
157 val = vlv_cck_read(dev_priv, reg);
158 mutex_unlock(&dev_priv->sb_lock);
159
160 divider = val & CCK_FREQUENCY_VALUES;
161
162 WARN((val & CCK_FREQUENCY_STATUS) !=
163 (divider << CCK_FREQUENCY_STATUS_SHIFT),
164 "%s change in progress\n", name);
165
166 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
167 }
168
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170 const char *name, u32 reg)
171 {
172 if (dev_priv->hpll_freq == 0)
173 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
174
175 return vlv_get_cck_clock(dev_priv, name, reg,
176 dev_priv->hpll_freq);
177 }
178
179 static int
180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
181 {
182 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
183 }
184
185 static int
186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
187 {
188 /* RAWCLK_FREQ_VLV register updated from power well code */
189 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
190 CCK_DISPLAY_REF_CLOCK_CONTROL);
191 }
192
193 static int
194 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
195 {
196 uint32_t clkcfg;
197
198 /* hrawclock is 1/4 the FSB frequency */
199 clkcfg = I915_READ(CLKCFG);
200 switch (clkcfg & CLKCFG_FSB_MASK) {
201 case CLKCFG_FSB_400:
202 return 100000;
203 case CLKCFG_FSB_533:
204 return 133333;
205 case CLKCFG_FSB_667:
206 return 166667;
207 case CLKCFG_FSB_800:
208 return 200000;
209 case CLKCFG_FSB_1067:
210 return 266667;
211 case CLKCFG_FSB_1333:
212 return 333333;
213 /* these two are just a guess; one of them might be right */
214 case CLKCFG_FSB_1600:
215 case CLKCFG_FSB_1600_ALT:
216 return 400000;
217 default:
218 return 133333;
219 }
220 }
221
222 void intel_update_rawclk(struct drm_i915_private *dev_priv)
223 {
224 if (HAS_PCH_SPLIT(dev_priv))
225 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
226 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
227 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
228 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
229 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
230 else
231 return; /* no rawclk on other platforms, or no need to know it */
232
233 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
234 }
235
236 static void intel_update_czclk(struct drm_i915_private *dev_priv)
237 {
238 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
239 return;
240
241 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
242 CCK_CZ_CLOCK_CONTROL);
243
244 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
245 }
246
247 static inline u32 /* units of 100MHz */
248 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
249 const struct intel_crtc_state *pipe_config)
250 {
251 if (HAS_DDI(dev_priv))
252 return pipe_config->port_clock; /* SPLL */
253 else if (IS_GEN5(dev_priv))
254 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
255 else
256 return 270000;
257 }
258
259 static const intel_limit_t intel_limits_i8xx_dac = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 908000, .max = 1512000 },
262 .n = { .min = 2, .max = 16 },
263 .m = { .min = 96, .max = 140 },
264 .m1 = { .min = 18, .max = 26 },
265 .m2 = { .min = 6, .max = 16 },
266 .p = { .min = 4, .max = 128 },
267 .p1 = { .min = 2, .max = 33 },
268 .p2 = { .dot_limit = 165000,
269 .p2_slow = 4, .p2_fast = 2 },
270 };
271
272 static const intel_limit_t intel_limits_i8xx_dvo = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 908000, .max = 1512000 },
275 .n = { .min = 2, .max = 16 },
276 .m = { .min = 96, .max = 140 },
277 .m1 = { .min = 18, .max = 26 },
278 .m2 = { .min = 6, .max = 16 },
279 .p = { .min = 4, .max = 128 },
280 .p1 = { .min = 2, .max = 33 },
281 .p2 = { .dot_limit = 165000,
282 .p2_slow = 4, .p2_fast = 4 },
283 };
284
285 static const intel_limit_t intel_limits_i8xx_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 908000, .max = 1512000 },
288 .n = { .min = 2, .max = 16 },
289 .m = { .min = 96, .max = 140 },
290 .m1 = { .min = 18, .max = 26 },
291 .m2 = { .min = 6, .max = 16 },
292 .p = { .min = 4, .max = 128 },
293 .p1 = { .min = 1, .max = 6 },
294 .p2 = { .dot_limit = 165000,
295 .p2_slow = 14, .p2_fast = 7 },
296 };
297
298 static const intel_limit_t intel_limits_i9xx_sdvo = {
299 .dot = { .min = 20000, .max = 400000 },
300 .vco = { .min = 1400000, .max = 2800000 },
301 .n = { .min = 1, .max = 6 },
302 .m = { .min = 70, .max = 120 },
303 .m1 = { .min = 8, .max = 18 },
304 .m2 = { .min = 3, .max = 7 },
305 .p = { .min = 5, .max = 80 },
306 .p1 = { .min = 1, .max = 8 },
307 .p2 = { .dot_limit = 200000,
308 .p2_slow = 10, .p2_fast = 5 },
309 };
310
311 static const intel_limit_t intel_limits_i9xx_lvds = {
312 .dot = { .min = 20000, .max = 400000 },
313 .vco = { .min = 1400000, .max = 2800000 },
314 .n = { .min = 1, .max = 6 },
315 .m = { .min = 70, .max = 120 },
316 .m1 = { .min = 8, .max = 18 },
317 .m2 = { .min = 3, .max = 7 },
318 .p = { .min = 7, .max = 98 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 112000,
321 .p2_slow = 14, .p2_fast = 7 },
322 };
323
324
325 static const intel_limit_t intel_limits_g4x_sdvo = {
326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 1750000, .max = 3500000},
328 .n = { .min = 1, .max = 4 },
329 .m = { .min = 104, .max = 138 },
330 .m1 = { .min = 17, .max = 23 },
331 .m2 = { .min = 5, .max = 11 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 1, .max = 3},
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 10,
336 .p2_fast = 10
337 },
338 };
339
340 static const intel_limit_t intel_limits_g4x_hdmi = {
341 .dot = { .min = 22000, .max = 400000 },
342 .vco = { .min = 1750000, .max = 3500000},
343 .n = { .min = 1, .max = 4 },
344 .m = { .min = 104, .max = 138 },
345 .m1 = { .min = 16, .max = 23 },
346 .m2 = { .min = 5, .max = 11 },
347 .p = { .min = 5, .max = 80 },
348 .p1 = { .min = 1, .max = 8},
349 .p2 = { .dot_limit = 165000,
350 .p2_slow = 10, .p2_fast = 5 },
351 };
352
353 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
354 .dot = { .min = 20000, .max = 115000 },
355 .vco = { .min = 1750000, .max = 3500000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 104, .max = 138 },
358 .m1 = { .min = 17, .max = 23 },
359 .m2 = { .min = 5, .max = 11 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 14, .p2_fast = 14
364 },
365 };
366
367 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
368 .dot = { .min = 80000, .max = 224000 },
369 .vco = { .min = 1750000, .max = 3500000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 104, .max = 138 },
372 .m1 = { .min = 17, .max = 23 },
373 .m2 = { .min = 5, .max = 11 },
374 .p = { .min = 14, .max = 42 },
375 .p1 = { .min = 2, .max = 6 },
376 .p2 = { .dot_limit = 0,
377 .p2_slow = 7, .p2_fast = 7
378 },
379 };
380
381 static const intel_limit_t intel_limits_pineview_sdvo = {
382 .dot = { .min = 20000, .max = 400000},
383 .vco = { .min = 1700000, .max = 3500000 },
384 /* Pineview's Ncounter is a ring counter */
385 .n = { .min = 3, .max = 6 },
386 .m = { .min = 2, .max = 256 },
387 /* Pineview only has one combined m divider, which we treat as m2. */
388 .m1 = { .min = 0, .max = 0 },
389 .m2 = { .min = 0, .max = 254 },
390 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = 200000,
393 .p2_slow = 10, .p2_fast = 5 },
394 };
395
396 static const intel_limit_t intel_limits_pineview_lvds = {
397 .dot = { .min = 20000, .max = 400000 },
398 .vco = { .min = 1700000, .max = 3500000 },
399 .n = { .min = 3, .max = 6 },
400 .m = { .min = 2, .max = 256 },
401 .m1 = { .min = 0, .max = 0 },
402 .m2 = { .min = 0, .max = 254 },
403 .p = { .min = 7, .max = 112 },
404 .p1 = { .min = 1, .max = 8 },
405 .p2 = { .dot_limit = 112000,
406 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 /* Ironlake / Sandybridge
410 *
411 * We calculate clock using (register_value + 2) for N/M1/M2, so here
412 * the range value for them is (actual_value - 2).
413 */
414 static const intel_limit_t intel_limits_ironlake_dac = {
415 .dot = { .min = 25000, .max = 350000 },
416 .vco = { .min = 1760000, .max = 3510000 },
417 .n = { .min = 1, .max = 5 },
418 .m = { .min = 79, .max = 127 },
419 .m1 = { .min = 12, .max = 22 },
420 .m2 = { .min = 5, .max = 9 },
421 .p = { .min = 5, .max = 80 },
422 .p1 = { .min = 1, .max = 8 },
423 .p2 = { .dot_limit = 225000,
424 .p2_slow = 10, .p2_fast = 5 },
425 };
426
427 static const intel_limit_t intel_limits_ironlake_single_lvds = {
428 .dot = { .min = 25000, .max = 350000 },
429 .vco = { .min = 1760000, .max = 3510000 },
430 .n = { .min = 1, .max = 3 },
431 .m = { .min = 79, .max = 118 },
432 .m1 = { .min = 12, .max = 22 },
433 .m2 = { .min = 5, .max = 9 },
434 .p = { .min = 28, .max = 112 },
435 .p1 = { .min = 2, .max = 8 },
436 .p2 = { .dot_limit = 225000,
437 .p2_slow = 14, .p2_fast = 14 },
438 };
439
440 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
441 .dot = { .min = 25000, .max = 350000 },
442 .vco = { .min = 1760000, .max = 3510000 },
443 .n = { .min = 1, .max = 3 },
444 .m = { .min = 79, .max = 127 },
445 .m1 = { .min = 12, .max = 22 },
446 .m2 = { .min = 5, .max = 9 },
447 .p = { .min = 14, .max = 56 },
448 .p1 = { .min = 2, .max = 8 },
449 .p2 = { .dot_limit = 225000,
450 .p2_slow = 7, .p2_fast = 7 },
451 };
452
453 /* LVDS 100mhz refclk limits. */
454 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
455 .dot = { .min = 25000, .max = 350000 },
456 .vco = { .min = 1760000, .max = 3510000 },
457 .n = { .min = 1, .max = 2 },
458 .m = { .min = 79, .max = 126 },
459 .m1 = { .min = 12, .max = 22 },
460 .m2 = { .min = 5, .max = 9 },
461 .p = { .min = 28, .max = 112 },
462 .p1 = { .min = 2, .max = 8 },
463 .p2 = { .dot_limit = 225000,
464 .p2_slow = 14, .p2_fast = 14 },
465 };
466
467 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
468 .dot = { .min = 25000, .max = 350000 },
469 .vco = { .min = 1760000, .max = 3510000 },
470 .n = { .min = 1, .max = 3 },
471 .m = { .min = 79, .max = 126 },
472 .m1 = { .min = 12, .max = 22 },
473 .m2 = { .min = 5, .max = 9 },
474 .p = { .min = 14, .max = 42 },
475 .p1 = { .min = 2, .max = 6 },
476 .p2 = { .dot_limit = 225000,
477 .p2_slow = 7, .p2_fast = 7 },
478 };
479
480 static const intel_limit_t intel_limits_vlv = {
481 /*
482 * These are the data rate limits (measured in fast clocks)
483 * since those are the strictest limits we have. The fast
484 * clock and actual rate limits are more relaxed, so checking
485 * them would make no difference.
486 */
487 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
488 .vco = { .min = 4000000, .max = 6000000 },
489 .n = { .min = 1, .max = 7 },
490 .m1 = { .min = 2, .max = 3 },
491 .m2 = { .min = 11, .max = 156 },
492 .p1 = { .min = 2, .max = 3 },
493 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
494 };
495
496 static const intel_limit_t intel_limits_chv = {
497 /*
498 * These are the data rate limits (measured in fast clocks)
499 * since those are the strictest limits we have. The fast
500 * clock and actual rate limits are more relaxed, so checking
501 * them would make no difference.
502 */
503 .dot = { .min = 25000 * 5, .max = 540000 * 5},
504 .vco = { .min = 4800000, .max = 6480000 },
505 .n = { .min = 1, .max = 1 },
506 .m1 = { .min = 2, .max = 2 },
507 .m2 = { .min = 24 << 22, .max = 175 << 22 },
508 .p1 = { .min = 2, .max = 4 },
509 .p2 = { .p2_slow = 1, .p2_fast = 14 },
510 };
511
512 static const intel_limit_t intel_limits_bxt = {
513 /* FIXME: find real dot limits */
514 .dot = { .min = 0, .max = INT_MAX },
515 .vco = { .min = 4800000, .max = 6700000 },
516 .n = { .min = 1, .max = 1 },
517 .m1 = { .min = 2, .max = 2 },
518 /* FIXME: find real m2 limits */
519 .m2 = { .min = 2 << 22, .max = 255 << 22 },
520 .p1 = { .min = 2, .max = 4 },
521 .p2 = { .p2_slow = 1, .p2_fast = 20 },
522 };
523
524 static bool
525 needs_modeset(struct drm_crtc_state *state)
526 {
527 return drm_atomic_crtc_needs_modeset(state);
528 }
529
530 /**
531 * Returns whether any output on the specified pipe is of the specified type
532 */
533 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
534 {
535 struct drm_device *dev = crtc->base.dev;
536 struct intel_encoder *encoder;
537
538 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
539 if (encoder->type == type)
540 return true;
541
542 return false;
543 }
544
545 /**
546 * Returns whether any output on the specified pipe will have the specified
547 * type after a staged modeset is complete, i.e., the same as
548 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
549 * encoder->crtc.
550 */
551 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
552 int type)
553 {
554 struct drm_atomic_state *state = crtc_state->base.state;
555 struct drm_connector *connector;
556 struct drm_connector_state *connector_state;
557 struct intel_encoder *encoder;
558 int i, num_connectors = 0;
559
560 for_each_connector_in_state(state, connector, connector_state, i) {
561 if (connector_state->crtc != crtc_state->base.crtc)
562 continue;
563
564 num_connectors++;
565
566 encoder = to_intel_encoder(connector_state->best_encoder);
567 if (encoder->type == type)
568 return true;
569 }
570
571 WARN_ON(num_connectors == 0);
572
573 return false;
574 }
575
576 /*
577 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
578 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
579 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
580 * The helpers' return value is the rate of the clock that is fed to the
581 * display engine's pipe which can be the above fast dot clock rate or a
582 * divided-down version of it.
583 */
584 /* m1 is reserved as 0 in Pineview, n is a ring counter */
585 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
586 {
587 clock->m = clock->m2 + 2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return 0;
591 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot;
595 }
596
597 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
598 {
599 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
600 }
601
602 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
603 {
604 clock->m = i9xx_dpll_compute_m(clock);
605 clock->p = clock->p1 * clock->p2;
606 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
607 return 0;
608 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
609 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
610
611 return clock->dot;
612 }
613
614 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
615 {
616 clock->m = clock->m1 * clock->m2;
617 clock->p = clock->p1 * clock->p2;
618 if (WARN_ON(clock->n == 0 || clock->p == 0))
619 return 0;
620 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
621 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
622
623 return clock->dot / 5;
624 }
625
626 int chv_calc_dpll_params(int refclk, struct dpll *clock)
627 {
628 clock->m = clock->m1 * clock->m2;
629 clock->p = clock->p1 * clock->p2;
630 if (WARN_ON(clock->n == 0 || clock->p == 0))
631 return 0;
632 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
633 clock->n << 22);
634 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
635
636 return clock->dot / 5;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const struct dpll *clock)
648 {
649 if (clock->n < limit->n.min || limit->n.max < clock->n)
650 INTELPllInvalid("n out of range\n");
651 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
652 INTELPllInvalid("p1 out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657
658 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
659 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
660 if (clock->m1 <= clock->m2)
661 INTELPllInvalid("m1 <= m2\n");
662
663 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
664 if (clock->p < limit->p.min || limit->p.max < clock->p)
665 INTELPllInvalid("p out of range\n");
666 if (clock->m < limit->m.min || limit->m.max < clock->m)
667 INTELPllInvalid("m out of range\n");
668 }
669
670 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
671 INTELPllInvalid("vco out of range\n");
672 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
673 * connector, etc., rather than just a single range.
674 */
675 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
676 INTELPllInvalid("dot out of range\n");
677
678 return true;
679 }
680
681 static int
682 i9xx_select_p2_div(const intel_limit_t *limit,
683 const struct intel_crtc_state *crtc_state,
684 int target)
685 {
686 struct drm_device *dev = crtc_state->base.crtc->dev;
687
688 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
689 /*
690 * For LVDS just rely on its current settings for dual-channel.
691 * We haven't figured out how to reliably set up different
692 * single/dual channel state, if we even can.
693 */
694 if (intel_is_dual_link_lvds(dev))
695 return limit->p2.p2_fast;
696 else
697 return limit->p2.p2_slow;
698 } else {
699 if (target < limit->p2.dot_limit)
700 return limit->p2.p2_slow;
701 else
702 return limit->p2.p2_fast;
703 }
704 }
705
706 /*
707 * Returns a set of divisors for the desired target clock with the given
708 * refclk, or FALSE. The returned values represent the clock equation:
709 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
710 *
711 * Target and reference clocks are specified in kHz.
712 *
713 * If match_clock is provided, then best_clock P divider must match the P
714 * divider from @match_clock used for LVDS downclocking.
715 */
716 static bool
717 i9xx_find_best_dpll(const intel_limit_t *limit,
718 struct intel_crtc_state *crtc_state,
719 int target, int refclk, struct dpll *match_clock,
720 struct dpll *best_clock)
721 {
722 struct drm_device *dev = crtc_state->base.crtc->dev;
723 struct dpll clock;
724 int err = target;
725
726 memset(best_clock, 0, sizeof(*best_clock));
727
728 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 if (clock.m2 >= clock.m1)
735 break;
736 for (clock.n = limit->n.min;
737 clock.n <= limit->n.max; clock.n++) {
738 for (clock.p1 = limit->p1.min;
739 clock.p1 <= limit->p1.max; clock.p1++) {
740 int this_err;
741
742 i9xx_calc_dpll_params(refclk, &clock);
743 if (!intel_PLL_is_valid(dev, limit,
744 &clock))
745 continue;
746 if (match_clock &&
747 clock.p != match_clock->p)
748 continue;
749
750 this_err = abs(clock.dot - target);
751 if (this_err < err) {
752 *best_clock = clock;
753 err = this_err;
754 }
755 }
756 }
757 }
758 }
759
760 return (err != target);
761 }
762
763 /*
764 * Returns a set of divisors for the desired target clock with the given
765 * refclk, or FALSE. The returned values represent the clock equation:
766 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
767 *
768 * Target and reference clocks are specified in kHz.
769 *
770 * If match_clock is provided, then best_clock P divider must match the P
771 * divider from @match_clock used for LVDS downclocking.
772 */
773 static bool
774 pnv_find_best_dpll(const intel_limit_t *limit,
775 struct intel_crtc_state *crtc_state,
776 int target, int refclk, struct dpll *match_clock,
777 struct dpll *best_clock)
778 {
779 struct drm_device *dev = crtc_state->base.crtc->dev;
780 struct dpll clock;
781 int err = target;
782
783 memset(best_clock, 0, sizeof(*best_clock));
784
785 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
786
787 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
788 clock.m1++) {
789 for (clock.m2 = limit->m2.min;
790 clock.m2 <= limit->m2.max; clock.m2++) {
791 for (clock.n = limit->n.min;
792 clock.n <= limit->n.max; clock.n++) {
793 for (clock.p1 = limit->p1.min;
794 clock.p1 <= limit->p1.max; clock.p1++) {
795 int this_err;
796
797 pnv_calc_dpll_params(refclk, &clock);
798 if (!intel_PLL_is_valid(dev, limit,
799 &clock))
800 continue;
801 if (match_clock &&
802 clock.p != match_clock->p)
803 continue;
804
805 this_err = abs(clock.dot - target);
806 if (this_err < err) {
807 *best_clock = clock;
808 err = this_err;
809 }
810 }
811 }
812 }
813 }
814
815 return (err != target);
816 }
817
818 /*
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822 *
823 * Target and reference clocks are specified in kHz.
824 *
825 * If match_clock is provided, then best_clock P divider must match the P
826 * divider from @match_clock used for LVDS downclocking.
827 */
828 static bool
829 g4x_find_best_dpll(const intel_limit_t *limit,
830 struct intel_crtc_state *crtc_state,
831 int target, int refclk, struct dpll *match_clock,
832 struct dpll *best_clock)
833 {
834 struct drm_device *dev = crtc_state->base.crtc->dev;
835 struct dpll clock;
836 int max_n;
837 bool found = false;
838 /* approximately equals target * 0.00585 */
839 int err_most = (target >> 8) + (target >> 9);
840
841 memset(best_clock, 0, sizeof(*best_clock));
842
843 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
844
845 max_n = limit->n.max;
846 /* based on hardware requirement, prefer smaller n to precision */
847 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
848 /* based on hardware requirement, prefere larger m1,m2 */
849 for (clock.m1 = limit->m1.max;
850 clock.m1 >= limit->m1.min; clock.m1--) {
851 for (clock.m2 = limit->m2.max;
852 clock.m2 >= limit->m2.min; clock.m2--) {
853 for (clock.p1 = limit->p1.max;
854 clock.p1 >= limit->p1.min; clock.p1--) {
855 int this_err;
856
857 i9xx_calc_dpll_params(refclk, &clock);
858 if (!intel_PLL_is_valid(dev, limit,
859 &clock))
860 continue;
861
862 this_err = abs(clock.dot - target);
863 if (this_err < err_most) {
864 *best_clock = clock;
865 err_most = this_err;
866 max_n = clock.n;
867 found = true;
868 }
869 }
870 }
871 }
872 }
873 return found;
874 }
875
876 /*
877 * Check if the calculated PLL configuration is more optimal compared to the
878 * best configuration and error found so far. Return the calculated error.
879 */
880 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
881 const struct dpll *calculated_clock,
882 const struct dpll *best_clock,
883 unsigned int best_error_ppm,
884 unsigned int *error_ppm)
885 {
886 /*
887 * For CHV ignore the error and consider only the P value.
888 * Prefer a bigger P value based on HW requirements.
889 */
890 if (IS_CHERRYVIEW(dev)) {
891 *error_ppm = 0;
892
893 return calculated_clock->p > best_clock->p;
894 }
895
896 if (WARN_ON_ONCE(!target_freq))
897 return false;
898
899 *error_ppm = div_u64(1000000ULL *
900 abs(target_freq - calculated_clock->dot),
901 target_freq);
902 /*
903 * Prefer a better P value over a better (smaller) error if the error
904 * is small. Ensure this preference for future configurations too by
905 * setting the error to 0.
906 */
907 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
908 *error_ppm = 0;
909
910 return true;
911 }
912
913 return *error_ppm + 10 < best_error_ppm;
914 }
915
916 /*
917 * Returns a set of divisors for the desired target clock with the given
918 * refclk, or FALSE. The returned values represent the clock equation:
919 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
920 */
921 static bool
922 vlv_find_best_dpll(const intel_limit_t *limit,
923 struct intel_crtc_state *crtc_state,
924 int target, int refclk, struct dpll *match_clock,
925 struct dpll *best_clock)
926 {
927 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
928 struct drm_device *dev = crtc->base.dev;
929 struct dpll clock;
930 unsigned int bestppm = 1000000;
931 /* min update 19.2 MHz */
932 int max_n = min(limit->n.max, refclk / 19200);
933 bool found = false;
934
935 target *= 5; /* fast clock */
936
937 memset(best_clock, 0, sizeof(*best_clock));
938
939 /* based on hardware requirement, prefer smaller n to precision */
940 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
941 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
942 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
943 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
944 clock.p = clock.p1 * clock.p2;
945 /* based on hardware requirement, prefer bigger m1,m2 values */
946 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
947 unsigned int ppm;
948
949 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
950 refclk * clock.m1);
951
952 vlv_calc_dpll_params(refclk, &clock);
953
954 if (!intel_PLL_is_valid(dev, limit,
955 &clock))
956 continue;
957
958 if (!vlv_PLL_is_optimal(dev, target,
959 &clock,
960 best_clock,
961 bestppm, &ppm))
962 continue;
963
964 *best_clock = clock;
965 bestppm = ppm;
966 found = true;
967 }
968 }
969 }
970 }
971
972 return found;
973 }
974
975 /*
976 * Returns a set of divisors for the desired target clock with the given
977 * refclk, or FALSE. The returned values represent the clock equation:
978 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
979 */
980 static bool
981 chv_find_best_dpll(const intel_limit_t *limit,
982 struct intel_crtc_state *crtc_state,
983 int target, int refclk, struct dpll *match_clock,
984 struct dpll *best_clock)
985 {
986 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
987 struct drm_device *dev = crtc->base.dev;
988 unsigned int best_error_ppm;
989 struct dpll clock;
990 uint64_t m2;
991 int found = false;
992
993 memset(best_clock, 0, sizeof(*best_clock));
994 best_error_ppm = 1000000;
995
996 /*
997 * Based on hardware doc, the n always set to 1, and m1 always
998 * set to 2. If requires to support 200Mhz refclk, we need to
999 * revisit this because n may not 1 anymore.
1000 */
1001 clock.n = 1, clock.m1 = 2;
1002 target *= 5; /* fast clock */
1003
1004 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1005 for (clock.p2 = limit->p2.p2_fast;
1006 clock.p2 >= limit->p2.p2_slow;
1007 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1008 unsigned int error_ppm;
1009
1010 clock.p = clock.p1 * clock.p2;
1011
1012 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1013 clock.n) << 22, refclk * clock.m1);
1014
1015 if (m2 > INT_MAX/clock.m1)
1016 continue;
1017
1018 clock.m2 = m2;
1019
1020 chv_calc_dpll_params(refclk, &clock);
1021
1022 if (!intel_PLL_is_valid(dev, limit, &clock))
1023 continue;
1024
1025 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1026 best_error_ppm, &error_ppm))
1027 continue;
1028
1029 *best_clock = clock;
1030 best_error_ppm = error_ppm;
1031 found = true;
1032 }
1033 }
1034
1035 return found;
1036 }
1037
1038 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1039 struct dpll *best_clock)
1040 {
1041 int refclk = 100000;
1042 const intel_limit_t *limit = &intel_limits_bxt;
1043
1044 return chv_find_best_dpll(limit, crtc_state,
1045 target_clock, refclk, NULL, best_clock);
1046 }
1047
1048 bool intel_crtc_active(struct drm_crtc *crtc)
1049 {
1050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1051
1052 /* Be paranoid as we can arrive here with only partial
1053 * state retrieved from the hardware during setup.
1054 *
1055 * We can ditch the adjusted_mode.crtc_clock check as soon
1056 * as Haswell has gained clock readout/fastboot support.
1057 *
1058 * We can ditch the crtc->primary->fb check as soon as we can
1059 * properly reconstruct framebuffers.
1060 *
1061 * FIXME: The intel_crtc->active here should be switched to
1062 * crtc->state->active once we have proper CRTC states wired up
1063 * for atomic.
1064 */
1065 return intel_crtc->active && crtc->primary->state->fb &&
1066 intel_crtc->config->base.adjusted_mode.crtc_clock;
1067 }
1068
1069 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1070 enum pipe pipe)
1071 {
1072 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1074
1075 return intel_crtc->config->cpu_transcoder;
1076 }
1077
1078 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1079 {
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 i915_reg_t reg = PIPEDSL(pipe);
1082 u32 line1, line2;
1083 u32 line_mask;
1084
1085 if (IS_GEN2(dev))
1086 line_mask = DSL_LINEMASK_GEN2;
1087 else
1088 line_mask = DSL_LINEMASK_GEN3;
1089
1090 line1 = I915_READ(reg) & line_mask;
1091 msleep(5);
1092 line2 = I915_READ(reg) & line_mask;
1093
1094 return line1 == line2;
1095 }
1096
1097 /*
1098 * intel_wait_for_pipe_off - wait for pipe to turn off
1099 * @crtc: crtc whose pipe to wait for
1100 *
1101 * After disabling a pipe, we can't wait for vblank in the usual way,
1102 * spinning on the vblank interrupt status bit, since we won't actually
1103 * see an interrupt when the pipe is disabled.
1104 *
1105 * On Gen4 and above:
1106 * wait for the pipe register state bit to turn off
1107 *
1108 * Otherwise:
1109 * wait for the display line value to settle (it usually
1110 * ends up stopping at the start of the next frame).
1111 *
1112 */
1113 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1114 {
1115 struct drm_device *dev = crtc->base.dev;
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1117 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1118 enum pipe pipe = crtc->pipe;
1119
1120 if (INTEL_INFO(dev)->gen >= 4) {
1121 i915_reg_t reg = PIPECONF(cpu_transcoder);
1122
1123 /* Wait for the Pipe State to go off */
1124 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1125 100))
1126 WARN(1, "pipe_off wait timed out\n");
1127 } else {
1128 /* Wait for the display line to settle */
1129 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1130 WARN(1, "pipe_off wait timed out\n");
1131 }
1132 }
1133
1134 /* Only for pre-ILK configs */
1135 void assert_pll(struct drm_i915_private *dev_priv,
1136 enum pipe pipe, bool state)
1137 {
1138 u32 val;
1139 bool cur_state;
1140
1141 val = I915_READ(DPLL(pipe));
1142 cur_state = !!(val & DPLL_VCO_ENABLE);
1143 I915_STATE_WARN(cur_state != state,
1144 "PLL state assertion failure (expected %s, current %s)\n",
1145 onoff(state), onoff(cur_state));
1146 }
1147
1148 /* XXX: the dsi pll is shared between MIPI DSI ports */
1149 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1150 {
1151 u32 val;
1152 bool cur_state;
1153
1154 mutex_lock(&dev_priv->sb_lock);
1155 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1156 mutex_unlock(&dev_priv->sb_lock);
1157
1158 cur_state = val & DSI_PLL_VCO_EN;
1159 I915_STATE_WARN(cur_state != state,
1160 "DSI PLL state assertion failure (expected %s, current %s)\n",
1161 onoff(state), onoff(cur_state));
1162 }
1163
1164 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1165 enum pipe pipe, bool state)
1166 {
1167 bool cur_state;
1168 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1169 pipe);
1170
1171 if (HAS_DDI(dev_priv)) {
1172 /* DDI does not have a specific FDI_TX register */
1173 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1174 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1175 } else {
1176 u32 val = I915_READ(FDI_TX_CTL(pipe));
1177 cur_state = !!(val & FDI_TX_ENABLE);
1178 }
1179 I915_STATE_WARN(cur_state != state,
1180 "FDI TX state assertion failure (expected %s, current %s)\n",
1181 onoff(state), onoff(cur_state));
1182 }
1183 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1184 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1185
1186 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, bool state)
1188 {
1189 u32 val;
1190 bool cur_state;
1191
1192 val = I915_READ(FDI_RX_CTL(pipe));
1193 cur_state = !!(val & FDI_RX_ENABLE);
1194 I915_STATE_WARN(cur_state != state,
1195 "FDI RX state assertion failure (expected %s, current %s)\n",
1196 onoff(state), onoff(cur_state));
1197 }
1198 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1199 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1200
1201 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1202 enum pipe pipe)
1203 {
1204 u32 val;
1205
1206 /* ILK FDI PLL is always enabled */
1207 if (IS_GEN5(dev_priv))
1208 return;
1209
1210 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1211 if (HAS_DDI(dev_priv))
1212 return;
1213
1214 val = I915_READ(FDI_TX_CTL(pipe));
1215 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1216 }
1217
1218 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 u32 val;
1222 bool cur_state;
1223
1224 val = I915_READ(FDI_RX_CTL(pipe));
1225 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1226 I915_STATE_WARN(cur_state != state,
1227 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1228 onoff(state), onoff(cur_state));
1229 }
1230
1231 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 struct drm_device *dev = dev_priv->dev;
1235 i915_reg_t pp_reg;
1236 u32 val;
1237 enum pipe panel_pipe = PIPE_A;
1238 bool locked = true;
1239
1240 if (WARN_ON(HAS_DDI(dev)))
1241 return;
1242
1243 if (HAS_PCH_SPLIT(dev)) {
1244 u32 port_sel;
1245
1246 pp_reg = PCH_PP_CONTROL;
1247 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1248
1249 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1250 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1251 panel_pipe = PIPE_B;
1252 /* XXX: else fix for eDP */
1253 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1254 /* presumably write lock depends on pipe, not port select */
1255 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1256 panel_pipe = pipe;
1257 } else {
1258 pp_reg = PP_CONTROL;
1259 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1260 panel_pipe = PIPE_B;
1261 }
1262
1263 val = I915_READ(pp_reg);
1264 if (!(val & PANEL_POWER_ON) ||
1265 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1266 locked = false;
1267
1268 I915_STATE_WARN(panel_pipe == pipe && locked,
1269 "panel assertion failure, pipe %c regs locked\n",
1270 pipe_name(pipe));
1271 }
1272
1273 static void assert_cursor(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, bool state)
1275 {
1276 struct drm_device *dev = dev_priv->dev;
1277 bool cur_state;
1278
1279 if (IS_845G(dev) || IS_I865G(dev))
1280 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1281 else
1282 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1283
1284 I915_STATE_WARN(cur_state != state,
1285 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1286 pipe_name(pipe), onoff(state), onoff(cur_state));
1287 }
1288 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1289 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1290
1291 void assert_pipe(struct drm_i915_private *dev_priv,
1292 enum pipe pipe, bool state)
1293 {
1294 bool cur_state;
1295 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1296 pipe);
1297 enum intel_display_power_domain power_domain;
1298
1299 /* if we need the pipe quirk it must be always on */
1300 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1301 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1302 state = true;
1303
1304 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1305 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1306 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1307 cur_state = !!(val & PIPECONF_ENABLE);
1308
1309 intel_display_power_put(dev_priv, power_domain);
1310 } else {
1311 cur_state = false;
1312 }
1313
1314 I915_STATE_WARN(cur_state != state,
1315 "pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), onoff(state), onoff(cur_state));
1317 }
1318
1319 static void assert_plane(struct drm_i915_private *dev_priv,
1320 enum plane plane, bool state)
1321 {
1322 u32 val;
1323 bool cur_state;
1324
1325 val = I915_READ(DSPCNTR(plane));
1326 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1327 I915_STATE_WARN(cur_state != state,
1328 "plane %c assertion failure (expected %s, current %s)\n",
1329 plane_name(plane), onoff(state), onoff(cur_state));
1330 }
1331
1332 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1333 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1334
1335 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1336 enum pipe pipe)
1337 {
1338 struct drm_device *dev = dev_priv->dev;
1339 int i;
1340
1341 /* Primary planes are fixed to pipes on gen4+ */
1342 if (INTEL_INFO(dev)->gen >= 4) {
1343 u32 val = I915_READ(DSPCNTR(pipe));
1344 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1345 "plane %c assertion failure, should be disabled but not\n",
1346 plane_name(pipe));
1347 return;
1348 }
1349
1350 /* Need to check both planes against the pipe */
1351 for_each_pipe(dev_priv, i) {
1352 u32 val = I915_READ(DSPCNTR(i));
1353 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1354 DISPPLANE_SEL_PIPE_SHIFT;
1355 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1356 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(i), pipe_name(pipe));
1358 }
1359 }
1360
1361 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1362 enum pipe pipe)
1363 {
1364 struct drm_device *dev = dev_priv->dev;
1365 int sprite;
1366
1367 if (INTEL_INFO(dev)->gen >= 9) {
1368 for_each_sprite(dev_priv, pipe, sprite) {
1369 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1370 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1371 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1372 sprite, pipe_name(pipe));
1373 }
1374 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1375 for_each_sprite(dev_priv, pipe, sprite) {
1376 u32 val = I915_READ(SPCNTR(pipe, sprite));
1377 I915_STATE_WARN(val & SP_ENABLE,
1378 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1379 sprite_name(pipe, sprite), pipe_name(pipe));
1380 }
1381 } else if (INTEL_INFO(dev)->gen >= 7) {
1382 u32 val = I915_READ(SPRCTL(pipe));
1383 I915_STATE_WARN(val & SPRITE_ENABLE,
1384 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1385 plane_name(pipe), pipe_name(pipe));
1386 } else if (INTEL_INFO(dev)->gen >= 5) {
1387 u32 val = I915_READ(DVSCNTR(pipe));
1388 I915_STATE_WARN(val & DVS_ENABLE,
1389 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1390 plane_name(pipe), pipe_name(pipe));
1391 }
1392 }
1393
1394 static void assert_vblank_disabled(struct drm_crtc *crtc)
1395 {
1396 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1397 drm_crtc_vblank_put(crtc);
1398 }
1399
1400 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402 {
1403 u32 val;
1404 bool enabled;
1405
1406 val = I915_READ(PCH_TRANSCONF(pipe));
1407 enabled = !!(val & TRANS_ENABLE);
1408 I915_STATE_WARN(enabled,
1409 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1410 pipe_name(pipe));
1411 }
1412
1413 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, u32 port_sel, u32 val)
1415 {
1416 if ((val & DP_PORT_EN) == 0)
1417 return false;
1418
1419 if (HAS_PCH_CPT(dev_priv)) {
1420 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1421 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1422 return false;
1423 } else if (IS_CHERRYVIEW(dev_priv)) {
1424 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1425 return false;
1426 } else {
1427 if ((val & DP_PIPE_MASK) != (pipe << 30))
1428 return false;
1429 }
1430 return true;
1431 }
1432
1433 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe, u32 val)
1435 {
1436 if ((val & SDVO_ENABLE) == 0)
1437 return false;
1438
1439 if (HAS_PCH_CPT(dev_priv)) {
1440 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1441 return false;
1442 } else if (IS_CHERRYVIEW(dev_priv)) {
1443 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1444 return false;
1445 } else {
1446 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1447 return false;
1448 }
1449 return true;
1450 }
1451
1452 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1453 enum pipe pipe, u32 val)
1454 {
1455 if ((val & LVDS_PORT_EN) == 0)
1456 return false;
1457
1458 if (HAS_PCH_CPT(dev_priv)) {
1459 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1460 return false;
1461 } else {
1462 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1463 return false;
1464 }
1465 return true;
1466 }
1467
1468 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 val)
1470 {
1471 if ((val & ADPA_DAC_ENABLE) == 0)
1472 return false;
1473 if (HAS_PCH_CPT(dev_priv)) {
1474 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1475 return false;
1476 } else {
1477 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1478 return false;
1479 }
1480 return true;
1481 }
1482
1483 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1484 enum pipe pipe, i915_reg_t reg,
1485 u32 port_sel)
1486 {
1487 u32 val = I915_READ(reg);
1488 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1489 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1490 i915_mmio_reg_offset(reg), pipe_name(pipe));
1491
1492 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1493 && (val & DP_PIPEB_SELECT),
1494 "IBX PCH dp port still using transcoder B\n");
1495 }
1496
1497 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, i915_reg_t reg)
1499 {
1500 u32 val = I915_READ(reg);
1501 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1502 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1503 i915_mmio_reg_offset(reg), pipe_name(pipe));
1504
1505 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1506 && (val & SDVO_PIPE_B_SELECT),
1507 "IBX PCH hdmi port still using transcoder B\n");
1508 }
1509
1510 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1511 enum pipe pipe)
1512 {
1513 u32 val;
1514
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1516 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1517 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1518
1519 val = I915_READ(PCH_ADPA);
1520 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1521 "PCH VGA enabled on transcoder %c, should be disabled\n",
1522 pipe_name(pipe));
1523
1524 val = I915_READ(PCH_LVDS);
1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1527 pipe_name(pipe));
1528
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1532 }
1533
1534 static void _vlv_enable_pll(struct intel_crtc *crtc,
1535 const struct intel_crtc_state *pipe_config)
1536 {
1537 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1538 enum pipe pipe = crtc->pipe;
1539
1540 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1541 POSTING_READ(DPLL(pipe));
1542 udelay(150);
1543
1544 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1545 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1546 }
1547
1548 static void vlv_enable_pll(struct intel_crtc *crtc,
1549 const struct intel_crtc_state *pipe_config)
1550 {
1551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1552 enum pipe pipe = crtc->pipe;
1553
1554 assert_pipe_disabled(dev_priv, pipe);
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 assert_panel_unlocked(dev_priv, pipe);
1558
1559 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1560 _vlv_enable_pll(crtc, pipe_config);
1561
1562 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1563 POSTING_READ(DPLL_MD(pipe));
1564 }
1565
1566
1567 static void _chv_enable_pll(struct intel_crtc *crtc,
1568 const struct intel_crtc_state *pipe_config)
1569 {
1570 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1571 enum pipe pipe = crtc->pipe;
1572 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1573 u32 tmp;
1574
1575 mutex_lock(&dev_priv->sb_lock);
1576
1577 /* Enable back the 10bit clock to display controller */
1578 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1579 tmp |= DPIO_DCLKP_EN;
1580 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1581
1582 mutex_unlock(&dev_priv->sb_lock);
1583
1584 /*
1585 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1586 */
1587 udelay(1);
1588
1589 /* Enable PLL */
1590 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1591
1592 /* Check PLL is locked */
1593 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1594 DRM_ERROR("PLL %d failed to lock\n", pipe);
1595 }
1596
1597 static void chv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1601 enum pipe pipe = crtc->pipe;
1602
1603 assert_pipe_disabled(dev_priv, pipe);
1604
1605 /* PLL is protected by panel, make sure we can write it */
1606 assert_panel_unlocked(dev_priv, pipe);
1607
1608 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1609 _chv_enable_pll(crtc, pipe_config);
1610
1611 if (pipe != PIPE_A) {
1612 /*
1613 * WaPixelRepeatModeFixForC0:chv
1614 *
1615 * DPLLCMD is AWOL. Use chicken bits to propagate
1616 * the value from DPLLBMD to either pipe B or C.
1617 */
1618 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1619 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1620 I915_WRITE(CBR4_VLV, 0);
1621 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1622
1623 /*
1624 * DPLLB VGA mode also seems to cause problems.
1625 * We should always have it disabled.
1626 */
1627 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1628 } else {
1629 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1630 POSTING_READ(DPLL_MD(pipe));
1631 }
1632 }
1633
1634 static int intel_num_dvo_pipes(struct drm_device *dev)
1635 {
1636 struct intel_crtc *crtc;
1637 int count = 0;
1638
1639 for_each_intel_crtc(dev, crtc)
1640 count += crtc->base.state->active &&
1641 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1642
1643 return count;
1644 }
1645
1646 static void i9xx_enable_pll(struct intel_crtc *crtc)
1647 {
1648 struct drm_device *dev = crtc->base.dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 i915_reg_t reg = DPLL(crtc->pipe);
1651 u32 dpll = crtc->config->dpll_hw_state.dpll;
1652
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655 /* PLL is protected by panel, make sure we can write it */
1656 if (IS_MOBILE(dev) && !IS_I830(dev))
1657 assert_panel_unlocked(dev_priv, crtc->pipe);
1658
1659 /* Enable DVO 2x clock on both PLLs if necessary */
1660 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1661 /*
1662 * It appears to be important that we don't enable this
1663 * for the current pipe before otherwise configuring the
1664 * PLL. No idea how this should be handled if multiple
1665 * DVO outputs are enabled simultaneosly.
1666 */
1667 dpll |= DPLL_DVO_2X_MODE;
1668 I915_WRITE(DPLL(!crtc->pipe),
1669 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1670 }
1671
1672 /*
1673 * Apparently we need to have VGA mode enabled prior to changing
1674 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1675 * dividers, even though the register value does change.
1676 */
1677 I915_WRITE(reg, 0);
1678
1679 I915_WRITE(reg, dpll);
1680
1681 /* Wait for the clocks to stabilize. */
1682 POSTING_READ(reg);
1683 udelay(150);
1684
1685 if (INTEL_INFO(dev)->gen >= 4) {
1686 I915_WRITE(DPLL_MD(crtc->pipe),
1687 crtc->config->dpll_hw_state.dpll_md);
1688 } else {
1689 /* The pixel multiplier can only be updated once the
1690 * DPLL is enabled and the clocks are stable.
1691 *
1692 * So write it again.
1693 */
1694 I915_WRITE(reg, dpll);
1695 }
1696
1697 /* We do this three times for luck */
1698 I915_WRITE(reg, dpll);
1699 POSTING_READ(reg);
1700 udelay(150); /* wait for warmup */
1701 I915_WRITE(reg, dpll);
1702 POSTING_READ(reg);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg, dpll);
1705 POSTING_READ(reg);
1706 udelay(150); /* wait for warmup */
1707 }
1708
1709 /**
1710 * i9xx_disable_pll - disable a PLL
1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe PLL to disable
1713 *
1714 * Disable the PLL for @pipe, making sure the pipe is off first.
1715 *
1716 * Note! This is for pre-ILK only.
1717 */
1718 static void i9xx_disable_pll(struct intel_crtc *crtc)
1719 {
1720 struct drm_device *dev = crtc->base.dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 enum pipe pipe = crtc->pipe;
1723
1724 /* Disable DVO 2x clock on both PLLs if necessary */
1725 if (IS_I830(dev) &&
1726 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1727 !intel_num_dvo_pipes(dev)) {
1728 I915_WRITE(DPLL(PIPE_B),
1729 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1730 I915_WRITE(DPLL(PIPE_A),
1731 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1732 }
1733
1734 /* Don't disable pipe or pipe PLLs if needed */
1735 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1736 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1737 return;
1738
1739 /* Make sure the pipe isn't still relying on us */
1740 assert_pipe_disabled(dev_priv, pipe);
1741
1742 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1743 POSTING_READ(DPLL(pipe));
1744 }
1745
1746 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1747 {
1748 u32 val;
1749
1750 /* Make sure the pipe isn't still relying on us */
1751 assert_pipe_disabled(dev_priv, pipe);
1752
1753 val = DPLL_INTEGRATED_REF_CLK_VLV |
1754 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1755 if (pipe != PIPE_A)
1756 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1757
1758 I915_WRITE(DPLL(pipe), val);
1759 POSTING_READ(DPLL(pipe));
1760 }
1761
1762 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1763 {
1764 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1765 u32 val;
1766
1767 /* Make sure the pipe isn't still relying on us */
1768 assert_pipe_disabled(dev_priv, pipe);
1769
1770 val = DPLL_SSC_REF_CLK_CHV |
1771 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1772 if (pipe != PIPE_A)
1773 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1774
1775 I915_WRITE(DPLL(pipe), val);
1776 POSTING_READ(DPLL(pipe));
1777
1778 mutex_lock(&dev_priv->sb_lock);
1779
1780 /* Disable 10bit clock to display controller */
1781 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1782 val &= ~DPIO_DCLKP_EN;
1783 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1784
1785 mutex_unlock(&dev_priv->sb_lock);
1786 }
1787
1788 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1789 struct intel_digital_port *dport,
1790 unsigned int expected_mask)
1791 {
1792 u32 port_mask;
1793 i915_reg_t dpll_reg;
1794
1795 switch (dport->port) {
1796 case PORT_B:
1797 port_mask = DPLL_PORTB_READY_MASK;
1798 dpll_reg = DPLL(0);
1799 break;
1800 case PORT_C:
1801 port_mask = DPLL_PORTC_READY_MASK;
1802 dpll_reg = DPLL(0);
1803 expected_mask <<= 4;
1804 break;
1805 case PORT_D:
1806 port_mask = DPLL_PORTD_READY_MASK;
1807 dpll_reg = DPIO_PHY_STATUS;
1808 break;
1809 default:
1810 BUG();
1811 }
1812
1813 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1814 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1815 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1816 }
1817
1818 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1819 enum pipe pipe)
1820 {
1821 struct drm_device *dev = dev_priv->dev;
1822 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1824 i915_reg_t reg;
1825 uint32_t val, pipeconf_val;
1826
1827 /* Make sure PCH DPLL is enabled */
1828 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1829
1830 /* FDI must be feeding us bits for PCH ports */
1831 assert_fdi_tx_enabled(dev_priv, pipe);
1832 assert_fdi_rx_enabled(dev_priv, pipe);
1833
1834 if (HAS_PCH_CPT(dev)) {
1835 /* Workaround: Set the timing override bit before enabling the
1836 * pch transcoder. */
1837 reg = TRANS_CHICKEN2(pipe);
1838 val = I915_READ(reg);
1839 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1840 I915_WRITE(reg, val);
1841 }
1842
1843 reg = PCH_TRANSCONF(pipe);
1844 val = I915_READ(reg);
1845 pipeconf_val = I915_READ(PIPECONF(pipe));
1846
1847 if (HAS_PCH_IBX(dev_priv)) {
1848 /*
1849 * Make the BPC in transcoder be consistent with
1850 * that in pipeconf reg. For HDMI we must use 8bpc
1851 * here for both 8bpc and 12bpc.
1852 */
1853 val &= ~PIPECONF_BPC_MASK;
1854 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1855 val |= PIPECONF_8BPC;
1856 else
1857 val |= pipeconf_val & PIPECONF_BPC_MASK;
1858 }
1859
1860 val &= ~TRANS_INTERLACE_MASK;
1861 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1862 if (HAS_PCH_IBX(dev_priv) &&
1863 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1864 val |= TRANS_LEGACY_INTERLACED_ILK;
1865 else
1866 val |= TRANS_INTERLACED;
1867 else
1868 val |= TRANS_PROGRESSIVE;
1869
1870 I915_WRITE(reg, val | TRANS_ENABLE);
1871 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1872 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1873 }
1874
1875 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1876 enum transcoder cpu_transcoder)
1877 {
1878 u32 val, pipeconf_val;
1879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1882 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1883
1884 /* Workaround: set timing override bit. */
1885 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1886 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1887 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1888
1889 val = TRANS_ENABLE;
1890 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1891
1892 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1893 PIPECONF_INTERLACED_ILK)
1894 val |= TRANS_INTERLACED;
1895 else
1896 val |= TRANS_PROGRESSIVE;
1897
1898 I915_WRITE(LPT_TRANSCONF, val);
1899 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1900 DRM_ERROR("Failed to enable PCH transcoder\n");
1901 }
1902
1903 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1904 enum pipe pipe)
1905 {
1906 struct drm_device *dev = dev_priv->dev;
1907 i915_reg_t reg;
1908 uint32_t val;
1909
1910 /* FDI relies on the transcoder */
1911 assert_fdi_tx_disabled(dev_priv, pipe);
1912 assert_fdi_rx_disabled(dev_priv, pipe);
1913
1914 /* Ports must be off as well */
1915 assert_pch_ports_disabled(dev_priv, pipe);
1916
1917 reg = PCH_TRANSCONF(pipe);
1918 val = I915_READ(reg);
1919 val &= ~TRANS_ENABLE;
1920 I915_WRITE(reg, val);
1921 /* wait for PCH transcoder off, transcoder state */
1922 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1923 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1924
1925 if (HAS_PCH_CPT(dev)) {
1926 /* Workaround: Clear the timing override chicken bit again. */
1927 reg = TRANS_CHICKEN2(pipe);
1928 val = I915_READ(reg);
1929 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1930 I915_WRITE(reg, val);
1931 }
1932 }
1933
1934 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1935 {
1936 u32 val;
1937
1938 val = I915_READ(LPT_TRANSCONF);
1939 val &= ~TRANS_ENABLE;
1940 I915_WRITE(LPT_TRANSCONF, val);
1941 /* wait for PCH transcoder off, transcoder state */
1942 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1943 DRM_ERROR("Failed to disable PCH transcoder\n");
1944
1945 /* Workaround: clear timing override bit. */
1946 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1947 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1948 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1949 }
1950
1951 /**
1952 * intel_enable_pipe - enable a pipe, asserting requirements
1953 * @crtc: crtc responsible for the pipe
1954 *
1955 * Enable @crtc's pipe, making sure that various hardware specific requirements
1956 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1957 */
1958 static void intel_enable_pipe(struct intel_crtc *crtc)
1959 {
1960 struct drm_device *dev = crtc->base.dev;
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962 enum pipe pipe = crtc->pipe;
1963 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1964 enum pipe pch_transcoder;
1965 i915_reg_t reg;
1966 u32 val;
1967
1968 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1969
1970 assert_planes_disabled(dev_priv, pipe);
1971 assert_cursor_disabled(dev_priv, pipe);
1972 assert_sprites_disabled(dev_priv, pipe);
1973
1974 if (HAS_PCH_LPT(dev_priv))
1975 pch_transcoder = TRANSCODER_A;
1976 else
1977 pch_transcoder = pipe;
1978
1979 /*
1980 * A pipe without a PLL won't actually be able to drive bits from
1981 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1982 * need the check.
1983 */
1984 if (HAS_GMCH_DISPLAY(dev_priv))
1985 if (crtc->config->has_dsi_encoder)
1986 assert_dsi_pll_enabled(dev_priv);
1987 else
1988 assert_pll_enabled(dev_priv, pipe);
1989 else {
1990 if (crtc->config->has_pch_encoder) {
1991 /* if driving the PCH, we need FDI enabled */
1992 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1993 assert_fdi_tx_pll_enabled(dev_priv,
1994 (enum pipe) cpu_transcoder);
1995 }
1996 /* FIXME: assert CPU port conditions for SNB+ */
1997 }
1998
1999 reg = PIPECONF(cpu_transcoder);
2000 val = I915_READ(reg);
2001 if (val & PIPECONF_ENABLE) {
2002 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2003 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2004 return;
2005 }
2006
2007 I915_WRITE(reg, val | PIPECONF_ENABLE);
2008 POSTING_READ(reg);
2009
2010 /*
2011 * Until the pipe starts DSL will read as 0, which would cause
2012 * an apparent vblank timestamp jump, which messes up also the
2013 * frame count when it's derived from the timestamps. So let's
2014 * wait for the pipe to start properly before we call
2015 * drm_crtc_vblank_on()
2016 */
2017 if (dev->max_vblank_count == 0 &&
2018 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2019 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2020 }
2021
2022 /**
2023 * intel_disable_pipe - disable a pipe, asserting requirements
2024 * @crtc: crtc whose pipes is to be disabled
2025 *
2026 * Disable the pipe of @crtc, making sure that various hardware
2027 * specific requirements are met, if applicable, e.g. plane
2028 * disabled, panel fitter off, etc.
2029 *
2030 * Will wait until the pipe has shut down before returning.
2031 */
2032 static void intel_disable_pipe(struct intel_crtc *crtc)
2033 {
2034 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2035 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2036 enum pipe pipe = crtc->pipe;
2037 i915_reg_t reg;
2038 u32 val;
2039
2040 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2041
2042 /*
2043 * Make sure planes won't keep trying to pump pixels to us,
2044 * or we might hang the display.
2045 */
2046 assert_planes_disabled(dev_priv, pipe);
2047 assert_cursor_disabled(dev_priv, pipe);
2048 assert_sprites_disabled(dev_priv, pipe);
2049
2050 reg = PIPECONF(cpu_transcoder);
2051 val = I915_READ(reg);
2052 if ((val & PIPECONF_ENABLE) == 0)
2053 return;
2054
2055 /*
2056 * Double wide has implications for planes
2057 * so best keep it disabled when not needed.
2058 */
2059 if (crtc->config->double_wide)
2060 val &= ~PIPECONF_DOUBLE_WIDE;
2061
2062 /* Don't disable pipe or pipe PLLs if needed */
2063 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2064 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2065 val &= ~PIPECONF_ENABLE;
2066
2067 I915_WRITE(reg, val);
2068 if ((val & PIPECONF_ENABLE) == 0)
2069 intel_wait_for_pipe_off(crtc);
2070 }
2071
2072 static bool need_vtd_wa(struct drm_device *dev)
2073 {
2074 #ifdef CONFIG_INTEL_IOMMU
2075 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2076 return true;
2077 #endif
2078 return false;
2079 }
2080
2081 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2082 {
2083 return IS_GEN2(dev_priv) ? 2048 : 4096;
2084 }
2085
2086 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2087 uint64_t fb_modifier, unsigned int cpp)
2088 {
2089 switch (fb_modifier) {
2090 case DRM_FORMAT_MOD_NONE:
2091 return cpp;
2092 case I915_FORMAT_MOD_X_TILED:
2093 if (IS_GEN2(dev_priv))
2094 return 128;
2095 else
2096 return 512;
2097 case I915_FORMAT_MOD_Y_TILED:
2098 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2099 return 128;
2100 else
2101 return 512;
2102 case I915_FORMAT_MOD_Yf_TILED:
2103 switch (cpp) {
2104 case 1:
2105 return 64;
2106 case 2:
2107 case 4:
2108 return 128;
2109 case 8:
2110 case 16:
2111 return 256;
2112 default:
2113 MISSING_CASE(cpp);
2114 return cpp;
2115 }
2116 break;
2117 default:
2118 MISSING_CASE(fb_modifier);
2119 return cpp;
2120 }
2121 }
2122
2123 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2124 uint64_t fb_modifier, unsigned int cpp)
2125 {
2126 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2127 return 1;
2128 else
2129 return intel_tile_size(dev_priv) /
2130 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2131 }
2132
2133 /* Return the tile dimensions in pixel units */
2134 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2135 unsigned int *tile_width,
2136 unsigned int *tile_height,
2137 uint64_t fb_modifier,
2138 unsigned int cpp)
2139 {
2140 unsigned int tile_width_bytes =
2141 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2142
2143 *tile_width = tile_width_bytes / cpp;
2144 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2145 }
2146
2147 unsigned int
2148 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2149 uint32_t pixel_format, uint64_t fb_modifier)
2150 {
2151 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2152 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2153
2154 return ALIGN(height, tile_height);
2155 }
2156
2157 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2158 {
2159 unsigned int size = 0;
2160 int i;
2161
2162 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2163 size += rot_info->plane[i].width * rot_info->plane[i].height;
2164
2165 return size;
2166 }
2167
2168 static void
2169 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2170 const struct drm_framebuffer *fb,
2171 unsigned int rotation)
2172 {
2173 if (intel_rotation_90_or_270(rotation)) {
2174 *view = i915_ggtt_view_rotated;
2175 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2176 } else {
2177 *view = i915_ggtt_view_normal;
2178 }
2179 }
2180
2181 static void
2182 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2183 struct drm_framebuffer *fb)
2184 {
2185 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2186 unsigned int tile_size, tile_width, tile_height, cpp;
2187
2188 tile_size = intel_tile_size(dev_priv);
2189
2190 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2191 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2192 fb->modifier[0], cpp);
2193
2194 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2195 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2196
2197 if (info->pixel_format == DRM_FORMAT_NV12) {
2198 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2199 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2200 fb->modifier[1], cpp);
2201
2202 info->uv_offset = fb->offsets[1];
2203 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2204 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2205 }
2206 }
2207
2208 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2209 {
2210 if (INTEL_INFO(dev_priv)->gen >= 9)
2211 return 256 * 1024;
2212 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2213 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2214 return 128 * 1024;
2215 else if (INTEL_INFO(dev_priv)->gen >= 4)
2216 return 4 * 1024;
2217 else
2218 return 0;
2219 }
2220
2221 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2222 uint64_t fb_modifier)
2223 {
2224 switch (fb_modifier) {
2225 case DRM_FORMAT_MOD_NONE:
2226 return intel_linear_alignment(dev_priv);
2227 case I915_FORMAT_MOD_X_TILED:
2228 if (INTEL_INFO(dev_priv)->gen >= 9)
2229 return 256 * 1024;
2230 return 0;
2231 case I915_FORMAT_MOD_Y_TILED:
2232 case I915_FORMAT_MOD_Yf_TILED:
2233 return 1 * 1024 * 1024;
2234 default:
2235 MISSING_CASE(fb_modifier);
2236 return 0;
2237 }
2238 }
2239
2240 int
2241 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2242 unsigned int rotation)
2243 {
2244 struct drm_device *dev = fb->dev;
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2247 struct i915_ggtt_view view;
2248 u32 alignment;
2249 int ret;
2250
2251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2252
2253 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2254
2255 intel_fill_fb_ggtt_view(&view, fb, rotation);
2256
2257 /* Note that the w/a also requires 64 PTE of padding following the
2258 * bo. We currently fill all unused PTE with the shadow page and so
2259 * we should always have valid PTE following the scanout preventing
2260 * the VT-d warning.
2261 */
2262 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2263 alignment = 256 * 1024;
2264
2265 /*
2266 * Global gtt pte registers are special registers which actually forward
2267 * writes to a chunk of system memory. Which means that there is no risk
2268 * that the register values disappear as soon as we call
2269 * intel_runtime_pm_put(), so it is correct to wrap only the
2270 * pin/unpin/fence and not more.
2271 */
2272 intel_runtime_pm_get(dev_priv);
2273
2274 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2275 &view);
2276 if (ret)
2277 goto err_pm;
2278
2279 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always install
2282 * a fence as the cost is not that onerous.
2283 */
2284 if (view.type == I915_GGTT_VIEW_NORMAL) {
2285 ret = i915_gem_object_get_fence(obj);
2286 if (ret == -EDEADLK) {
2287 /*
2288 * -EDEADLK means there are no free fences
2289 * no pending flips.
2290 *
2291 * This is propagated to atomic, but it uses
2292 * -EDEADLK to force a locking recovery, so
2293 * change the returned error to -EBUSY.
2294 */
2295 ret = -EBUSY;
2296 goto err_unpin;
2297 } else if (ret)
2298 goto err_unpin;
2299
2300 i915_gem_object_pin_fence(obj);
2301 }
2302
2303 intel_runtime_pm_put(dev_priv);
2304 return 0;
2305
2306 err_unpin:
2307 i915_gem_object_unpin_from_display_plane(obj, &view);
2308 err_pm:
2309 intel_runtime_pm_put(dev_priv);
2310 return ret;
2311 }
2312
2313 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2314 {
2315 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2316 struct i915_ggtt_view view;
2317
2318 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2319
2320 intel_fill_fb_ggtt_view(&view, fb, rotation);
2321
2322 if (view.type == I915_GGTT_VIEW_NORMAL)
2323 i915_gem_object_unpin_fence(obj);
2324
2325 i915_gem_object_unpin_from_display_plane(obj, &view);
2326 }
2327
2328 /*
2329 * Adjust the tile offset by moving the difference into
2330 * the x/y offsets.
2331 *
2332 * Input tile dimensions and pitch must already be
2333 * rotated to match x and y, and in pixel units.
2334 */
2335 static u32 intel_adjust_tile_offset(int *x, int *y,
2336 unsigned int tile_width,
2337 unsigned int tile_height,
2338 unsigned int tile_size,
2339 unsigned int pitch_tiles,
2340 u32 old_offset,
2341 u32 new_offset)
2342 {
2343 unsigned int tiles;
2344
2345 WARN_ON(old_offset & (tile_size - 1));
2346 WARN_ON(new_offset & (tile_size - 1));
2347 WARN_ON(new_offset > old_offset);
2348
2349 tiles = (old_offset - new_offset) / tile_size;
2350
2351 *y += tiles / pitch_tiles * tile_height;
2352 *x += tiles % pitch_tiles * tile_width;
2353
2354 return new_offset;
2355 }
2356
2357 /*
2358 * Computes the linear offset to the base tile and adjusts
2359 * x, y. bytes per pixel is assumed to be a power-of-two.
2360 *
2361 * In the 90/270 rotated case, x and y are assumed
2362 * to be already rotated to match the rotated GTT view, and
2363 * pitch is the tile_height aligned framebuffer height.
2364 */
2365 u32 intel_compute_tile_offset(int *x, int *y,
2366 const struct drm_framebuffer *fb, int plane,
2367 unsigned int pitch,
2368 unsigned int rotation)
2369 {
2370 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2371 uint64_t fb_modifier = fb->modifier[plane];
2372 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2373 u32 offset, offset_aligned, alignment;
2374
2375 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2376 if (alignment)
2377 alignment--;
2378
2379 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2380 unsigned int tile_size, tile_width, tile_height;
2381 unsigned int tile_rows, tiles, pitch_tiles;
2382
2383 tile_size = intel_tile_size(dev_priv);
2384 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2385 fb_modifier, cpp);
2386
2387 if (intel_rotation_90_or_270(rotation)) {
2388 pitch_tiles = pitch / tile_height;
2389 swap(tile_width, tile_height);
2390 } else {
2391 pitch_tiles = pitch / (tile_width * cpp);
2392 }
2393
2394 tile_rows = *y / tile_height;
2395 *y %= tile_height;
2396
2397 tiles = *x / tile_width;
2398 *x %= tile_width;
2399
2400 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2401 offset_aligned = offset & ~alignment;
2402
2403 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2404 tile_size, pitch_tiles,
2405 offset, offset_aligned);
2406 } else {
2407 offset = *y * pitch + *x * cpp;
2408 offset_aligned = offset & ~alignment;
2409
2410 *y = (offset & alignment) / pitch;
2411 *x = ((offset & alignment) - *y * pitch) / cpp;
2412 }
2413
2414 return offset_aligned;
2415 }
2416
2417 static int i9xx_format_to_fourcc(int format)
2418 {
2419 switch (format) {
2420 case DISPPLANE_8BPP:
2421 return DRM_FORMAT_C8;
2422 case DISPPLANE_BGRX555:
2423 return DRM_FORMAT_XRGB1555;
2424 case DISPPLANE_BGRX565:
2425 return DRM_FORMAT_RGB565;
2426 default:
2427 case DISPPLANE_BGRX888:
2428 return DRM_FORMAT_XRGB8888;
2429 case DISPPLANE_RGBX888:
2430 return DRM_FORMAT_XBGR8888;
2431 case DISPPLANE_BGRX101010:
2432 return DRM_FORMAT_XRGB2101010;
2433 case DISPPLANE_RGBX101010:
2434 return DRM_FORMAT_XBGR2101010;
2435 }
2436 }
2437
2438 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2439 {
2440 switch (format) {
2441 case PLANE_CTL_FORMAT_RGB_565:
2442 return DRM_FORMAT_RGB565;
2443 default:
2444 case PLANE_CTL_FORMAT_XRGB_8888:
2445 if (rgb_order) {
2446 if (alpha)
2447 return DRM_FORMAT_ABGR8888;
2448 else
2449 return DRM_FORMAT_XBGR8888;
2450 } else {
2451 if (alpha)
2452 return DRM_FORMAT_ARGB8888;
2453 else
2454 return DRM_FORMAT_XRGB8888;
2455 }
2456 case PLANE_CTL_FORMAT_XRGB_2101010:
2457 if (rgb_order)
2458 return DRM_FORMAT_XBGR2101010;
2459 else
2460 return DRM_FORMAT_XRGB2101010;
2461 }
2462 }
2463
2464 static bool
2465 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2466 struct intel_initial_plane_config *plane_config)
2467 {
2468 struct drm_device *dev = crtc->base.dev;
2469 struct drm_i915_private *dev_priv = to_i915(dev);
2470 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2471 struct drm_i915_gem_object *obj = NULL;
2472 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2473 struct drm_framebuffer *fb = &plane_config->fb->base;
2474 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2475 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2476 PAGE_SIZE);
2477
2478 size_aligned -= base_aligned;
2479
2480 if (plane_config->size == 0)
2481 return false;
2482
2483 /* If the FB is too big, just don't use it since fbdev is not very
2484 * important and we should probably use that space with FBC or other
2485 * features. */
2486 if (size_aligned * 2 > ggtt->stolen_usable_size)
2487 return false;
2488
2489 mutex_lock(&dev->struct_mutex);
2490
2491 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2492 base_aligned,
2493 base_aligned,
2494 size_aligned);
2495 if (!obj) {
2496 mutex_unlock(&dev->struct_mutex);
2497 return false;
2498 }
2499
2500 obj->tiling_mode = plane_config->tiling;
2501 if (obj->tiling_mode == I915_TILING_X)
2502 obj->stride = fb->pitches[0];
2503
2504 mode_cmd.pixel_format = fb->pixel_format;
2505 mode_cmd.width = fb->width;
2506 mode_cmd.height = fb->height;
2507 mode_cmd.pitches[0] = fb->pitches[0];
2508 mode_cmd.modifier[0] = fb->modifier[0];
2509 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2510
2511 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2512 &mode_cmd, obj)) {
2513 DRM_DEBUG_KMS("intel fb init failed\n");
2514 goto out_unref_obj;
2515 }
2516
2517 mutex_unlock(&dev->struct_mutex);
2518
2519 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2520 return true;
2521
2522 out_unref_obj:
2523 drm_gem_object_unreference(&obj->base);
2524 mutex_unlock(&dev->struct_mutex);
2525 return false;
2526 }
2527
2528 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2529 static void
2530 update_state_fb(struct drm_plane *plane)
2531 {
2532 if (plane->fb == plane->state->fb)
2533 return;
2534
2535 if (plane->state->fb)
2536 drm_framebuffer_unreference(plane->state->fb);
2537 plane->state->fb = plane->fb;
2538 if (plane->state->fb)
2539 drm_framebuffer_reference(plane->state->fb);
2540 }
2541
2542 static void
2543 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2544 struct intel_initial_plane_config *plane_config)
2545 {
2546 struct drm_device *dev = intel_crtc->base.dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct drm_crtc *c;
2549 struct intel_crtc *i;
2550 struct drm_i915_gem_object *obj;
2551 struct drm_plane *primary = intel_crtc->base.primary;
2552 struct drm_plane_state *plane_state = primary->state;
2553 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2554 struct intel_plane *intel_plane = to_intel_plane(primary);
2555 struct intel_plane_state *intel_state =
2556 to_intel_plane_state(plane_state);
2557 struct drm_framebuffer *fb;
2558
2559 if (!plane_config->fb)
2560 return;
2561
2562 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2563 fb = &plane_config->fb->base;
2564 goto valid_fb;
2565 }
2566
2567 kfree(plane_config->fb);
2568
2569 /*
2570 * Failed to alloc the obj, check to see if we should share
2571 * an fb with another CRTC instead
2572 */
2573 for_each_crtc(dev, c) {
2574 i = to_intel_crtc(c);
2575
2576 if (c == &intel_crtc->base)
2577 continue;
2578
2579 if (!i->active)
2580 continue;
2581
2582 fb = c->primary->fb;
2583 if (!fb)
2584 continue;
2585
2586 obj = intel_fb_obj(fb);
2587 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2588 drm_framebuffer_reference(fb);
2589 goto valid_fb;
2590 }
2591 }
2592
2593 /*
2594 * We've failed to reconstruct the BIOS FB. Current display state
2595 * indicates that the primary plane is visible, but has a NULL FB,
2596 * which will lead to problems later if we don't fix it up. The
2597 * simplest solution is to just disable the primary plane now and
2598 * pretend the BIOS never had it enabled.
2599 */
2600 to_intel_plane_state(plane_state)->visible = false;
2601 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2602 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2603 intel_plane->disable_plane(primary, &intel_crtc->base);
2604
2605 return;
2606
2607 valid_fb:
2608 plane_state->src_x = 0;
2609 plane_state->src_y = 0;
2610 plane_state->src_w = fb->width << 16;
2611 plane_state->src_h = fb->height << 16;
2612
2613 plane_state->crtc_x = 0;
2614 plane_state->crtc_y = 0;
2615 plane_state->crtc_w = fb->width;
2616 plane_state->crtc_h = fb->height;
2617
2618 intel_state->src.x1 = plane_state->src_x;
2619 intel_state->src.y1 = plane_state->src_y;
2620 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2621 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2622 intel_state->dst.x1 = plane_state->crtc_x;
2623 intel_state->dst.y1 = plane_state->crtc_y;
2624 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2625 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2626
2627 obj = intel_fb_obj(fb);
2628 if (obj->tiling_mode != I915_TILING_NONE)
2629 dev_priv->preserve_bios_swizzle = true;
2630
2631 drm_framebuffer_reference(fb);
2632 primary->fb = primary->state->fb = fb;
2633 primary->crtc = primary->state->crtc = &intel_crtc->base;
2634 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2635 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2636 }
2637
2638 static void i9xx_update_primary_plane(struct drm_plane *primary,
2639 const struct intel_crtc_state *crtc_state,
2640 const struct intel_plane_state *plane_state)
2641 {
2642 struct drm_device *dev = primary->dev;
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2645 struct drm_framebuffer *fb = plane_state->base.fb;
2646 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2647 int plane = intel_crtc->plane;
2648 u32 linear_offset;
2649 u32 dspcntr;
2650 i915_reg_t reg = DSPCNTR(plane);
2651 unsigned int rotation = plane_state->base.rotation;
2652 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2653 int x = plane_state->src.x1 >> 16;
2654 int y = plane_state->src.y1 >> 16;
2655
2656 dspcntr = DISPPLANE_GAMMA_ENABLE;
2657
2658 dspcntr |= DISPLAY_PLANE_ENABLE;
2659
2660 if (INTEL_INFO(dev)->gen < 4) {
2661 if (intel_crtc->pipe == PIPE_B)
2662 dspcntr |= DISPPLANE_SEL_PIPE_B;
2663
2664 /* pipesrc and dspsize control the size that is scaled from,
2665 * which should always be the user's requested size.
2666 */
2667 I915_WRITE(DSPSIZE(plane),
2668 ((crtc_state->pipe_src_h - 1) << 16) |
2669 (crtc_state->pipe_src_w - 1));
2670 I915_WRITE(DSPPOS(plane), 0);
2671 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2672 I915_WRITE(PRIMSIZE(plane),
2673 ((crtc_state->pipe_src_h - 1) << 16) |
2674 (crtc_state->pipe_src_w - 1));
2675 I915_WRITE(PRIMPOS(plane), 0);
2676 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2677 }
2678
2679 switch (fb->pixel_format) {
2680 case DRM_FORMAT_C8:
2681 dspcntr |= DISPPLANE_8BPP;
2682 break;
2683 case DRM_FORMAT_XRGB1555:
2684 dspcntr |= DISPPLANE_BGRX555;
2685 break;
2686 case DRM_FORMAT_RGB565:
2687 dspcntr |= DISPPLANE_BGRX565;
2688 break;
2689 case DRM_FORMAT_XRGB8888:
2690 dspcntr |= DISPPLANE_BGRX888;
2691 break;
2692 case DRM_FORMAT_XBGR8888:
2693 dspcntr |= DISPPLANE_RGBX888;
2694 break;
2695 case DRM_FORMAT_XRGB2101010:
2696 dspcntr |= DISPPLANE_BGRX101010;
2697 break;
2698 case DRM_FORMAT_XBGR2101010:
2699 dspcntr |= DISPPLANE_RGBX101010;
2700 break;
2701 default:
2702 BUG();
2703 }
2704
2705 if (INTEL_INFO(dev)->gen >= 4 &&
2706 obj->tiling_mode != I915_TILING_NONE)
2707 dspcntr |= DISPPLANE_TILED;
2708
2709 if (IS_G4X(dev))
2710 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2711
2712 linear_offset = y * fb->pitches[0] + x * cpp;
2713
2714 if (INTEL_INFO(dev)->gen >= 4) {
2715 intel_crtc->dspaddr_offset =
2716 intel_compute_tile_offset(&x, &y, fb, 0,
2717 fb->pitches[0], rotation);
2718 linear_offset -= intel_crtc->dspaddr_offset;
2719 } else {
2720 intel_crtc->dspaddr_offset = linear_offset;
2721 }
2722
2723 if (rotation == BIT(DRM_ROTATE_180)) {
2724 dspcntr |= DISPPLANE_ROTATE_180;
2725
2726 x += (crtc_state->pipe_src_w - 1);
2727 y += (crtc_state->pipe_src_h - 1);
2728
2729 /* Finding the last pixel of the last line of the display
2730 data and adding to linear_offset*/
2731 linear_offset +=
2732 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2733 (crtc_state->pipe_src_w - 1) * cpp;
2734 }
2735
2736 intel_crtc->adjusted_x = x;
2737 intel_crtc->adjusted_y = y;
2738
2739 I915_WRITE(reg, dspcntr);
2740
2741 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 I915_WRITE(DSPSURF(plane),
2744 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2745 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2746 I915_WRITE(DSPLINOFF(plane), linear_offset);
2747 } else
2748 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2749 POSTING_READ(reg);
2750 }
2751
2752 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2753 struct drm_crtc *crtc)
2754 {
2755 struct drm_device *dev = crtc->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2758 int plane = intel_crtc->plane;
2759
2760 I915_WRITE(DSPCNTR(plane), 0);
2761 if (INTEL_INFO(dev_priv)->gen >= 4)
2762 I915_WRITE(DSPSURF(plane), 0);
2763 else
2764 I915_WRITE(DSPADDR(plane), 0);
2765 POSTING_READ(DSPCNTR(plane));
2766 }
2767
2768 static void ironlake_update_primary_plane(struct drm_plane *primary,
2769 const struct intel_crtc_state *crtc_state,
2770 const struct intel_plane_state *plane_state)
2771 {
2772 struct drm_device *dev = primary->dev;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2775 struct drm_framebuffer *fb = plane_state->base.fb;
2776 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2777 int plane = intel_crtc->plane;
2778 u32 linear_offset;
2779 u32 dspcntr;
2780 i915_reg_t reg = DSPCNTR(plane);
2781 unsigned int rotation = plane_state->base.rotation;
2782 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2783 int x = plane_state->src.x1 >> 16;
2784 int y = plane_state->src.y1 >> 16;
2785
2786 dspcntr = DISPPLANE_GAMMA_ENABLE;
2787 dspcntr |= DISPLAY_PLANE_ENABLE;
2788
2789 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2790 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2791
2792 switch (fb->pixel_format) {
2793 case DRM_FORMAT_C8:
2794 dspcntr |= DISPPLANE_8BPP;
2795 break;
2796 case DRM_FORMAT_RGB565:
2797 dspcntr |= DISPPLANE_BGRX565;
2798 break;
2799 case DRM_FORMAT_XRGB8888:
2800 dspcntr |= DISPPLANE_BGRX888;
2801 break;
2802 case DRM_FORMAT_XBGR8888:
2803 dspcntr |= DISPPLANE_RGBX888;
2804 break;
2805 case DRM_FORMAT_XRGB2101010:
2806 dspcntr |= DISPPLANE_BGRX101010;
2807 break;
2808 case DRM_FORMAT_XBGR2101010:
2809 dspcntr |= DISPPLANE_RGBX101010;
2810 break;
2811 default:
2812 BUG();
2813 }
2814
2815 if (obj->tiling_mode != I915_TILING_NONE)
2816 dspcntr |= DISPPLANE_TILED;
2817
2818 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2820
2821 linear_offset = y * fb->pitches[0] + x * cpp;
2822 intel_crtc->dspaddr_offset =
2823 intel_compute_tile_offset(&x, &y, fb, 0,
2824 fb->pitches[0], rotation);
2825 linear_offset -= intel_crtc->dspaddr_offset;
2826 if (rotation == BIT(DRM_ROTATE_180)) {
2827 dspcntr |= DISPPLANE_ROTATE_180;
2828
2829 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2830 x += (crtc_state->pipe_src_w - 1);
2831 y += (crtc_state->pipe_src_h - 1);
2832
2833 /* Finding the last pixel of the last line of the display
2834 data and adding to linear_offset*/
2835 linear_offset +=
2836 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2837 (crtc_state->pipe_src_w - 1) * cpp;
2838 }
2839 }
2840
2841 intel_crtc->adjusted_x = x;
2842 intel_crtc->adjusted_y = y;
2843
2844 I915_WRITE(reg, dspcntr);
2845
2846 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2847 I915_WRITE(DSPSURF(plane),
2848 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2849 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2850 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2851 } else {
2852 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2853 I915_WRITE(DSPLINOFF(plane), linear_offset);
2854 }
2855 POSTING_READ(reg);
2856 }
2857
2858 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2859 uint64_t fb_modifier, uint32_t pixel_format)
2860 {
2861 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2862 return 64;
2863 } else {
2864 int cpp = drm_format_plane_cpp(pixel_format, 0);
2865
2866 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2867 }
2868 }
2869
2870 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2871 struct drm_i915_gem_object *obj,
2872 unsigned int plane)
2873 {
2874 struct i915_ggtt_view view;
2875 struct i915_vma *vma;
2876 u64 offset;
2877
2878 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2879 intel_plane->base.state->rotation);
2880
2881 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2882 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2883 view.type))
2884 return -1;
2885
2886 offset = vma->node.start;
2887
2888 if (plane == 1) {
2889 offset += vma->ggtt_view.params.rotated.uv_start_page *
2890 PAGE_SIZE;
2891 }
2892
2893 WARN_ON(upper_32_bits(offset));
2894
2895 return lower_32_bits(offset);
2896 }
2897
2898 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2899 {
2900 struct drm_device *dev = intel_crtc->base.dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902
2903 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2904 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2905 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2906 }
2907
2908 /*
2909 * This function detaches (aka. unbinds) unused scalers in hardware
2910 */
2911 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2912 {
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 scaler_state = &intel_crtc->config->scaler_state;
2917
2918 /* loop through and disable scalers that aren't in use */
2919 for (i = 0; i < intel_crtc->num_scalers; i++) {
2920 if (!scaler_state->scalers[i].in_use)
2921 skl_detach_scaler(intel_crtc, i);
2922 }
2923 }
2924
2925 u32 skl_plane_ctl_format(uint32_t pixel_format)
2926 {
2927 switch (pixel_format) {
2928 case DRM_FORMAT_C8:
2929 return PLANE_CTL_FORMAT_INDEXED;
2930 case DRM_FORMAT_RGB565:
2931 return PLANE_CTL_FORMAT_RGB_565;
2932 case DRM_FORMAT_XBGR8888:
2933 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2934 case DRM_FORMAT_XRGB8888:
2935 return PLANE_CTL_FORMAT_XRGB_8888;
2936 /*
2937 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2938 * to be already pre-multiplied. We need to add a knob (or a different
2939 * DRM_FORMAT) for user-space to configure that.
2940 */
2941 case DRM_FORMAT_ABGR8888:
2942 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2943 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2944 case DRM_FORMAT_ARGB8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888 |
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2947 case DRM_FORMAT_XRGB2101010:
2948 return PLANE_CTL_FORMAT_XRGB_2101010;
2949 case DRM_FORMAT_XBGR2101010:
2950 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2951 case DRM_FORMAT_YUYV:
2952 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2953 case DRM_FORMAT_YVYU:
2954 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2955 case DRM_FORMAT_UYVY:
2956 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2957 case DRM_FORMAT_VYUY:
2958 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2959 default:
2960 MISSING_CASE(pixel_format);
2961 }
2962
2963 return 0;
2964 }
2965
2966 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2967 {
2968 switch (fb_modifier) {
2969 case DRM_FORMAT_MOD_NONE:
2970 break;
2971 case I915_FORMAT_MOD_X_TILED:
2972 return PLANE_CTL_TILED_X;
2973 case I915_FORMAT_MOD_Y_TILED:
2974 return PLANE_CTL_TILED_Y;
2975 case I915_FORMAT_MOD_Yf_TILED:
2976 return PLANE_CTL_TILED_YF;
2977 default:
2978 MISSING_CASE(fb_modifier);
2979 }
2980
2981 return 0;
2982 }
2983
2984 u32 skl_plane_ctl_rotation(unsigned int rotation)
2985 {
2986 switch (rotation) {
2987 case BIT(DRM_ROTATE_0):
2988 break;
2989 /*
2990 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2991 * while i915 HW rotation is clockwise, thats why this swapping.
2992 */
2993 case BIT(DRM_ROTATE_90):
2994 return PLANE_CTL_ROTATE_270;
2995 case BIT(DRM_ROTATE_180):
2996 return PLANE_CTL_ROTATE_180;
2997 case BIT(DRM_ROTATE_270):
2998 return PLANE_CTL_ROTATE_90;
2999 default:
3000 MISSING_CASE(rotation);
3001 }
3002
3003 return 0;
3004 }
3005
3006 static void skylake_update_primary_plane(struct drm_plane *plane,
3007 const struct intel_crtc_state *crtc_state,
3008 const struct intel_plane_state *plane_state)
3009 {
3010 struct drm_device *dev = plane->dev;
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3013 struct drm_framebuffer *fb = plane_state->base.fb;
3014 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3015 int pipe = intel_crtc->pipe;
3016 u32 plane_ctl, stride_div, stride;
3017 u32 tile_height, plane_offset, plane_size;
3018 unsigned int rotation = plane_state->base.rotation;
3019 int x_offset, y_offset;
3020 u32 surf_addr;
3021 int scaler_id = plane_state->scaler_id;
3022 int src_x = plane_state->src.x1 >> 16;
3023 int src_y = plane_state->src.y1 >> 16;
3024 int src_w = drm_rect_width(&plane_state->src) >> 16;
3025 int src_h = drm_rect_height(&plane_state->src) >> 16;
3026 int dst_x = plane_state->dst.x1;
3027 int dst_y = plane_state->dst.y1;
3028 int dst_w = drm_rect_width(&plane_state->dst);
3029 int dst_h = drm_rect_height(&plane_state->dst);
3030
3031 plane_ctl = PLANE_CTL_ENABLE |
3032 PLANE_CTL_PIPE_GAMMA_ENABLE |
3033 PLANE_CTL_PIPE_CSC_ENABLE;
3034
3035 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3036 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3037 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3038 plane_ctl |= skl_plane_ctl_rotation(rotation);
3039
3040 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3041 fb->pixel_format);
3042 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3043
3044 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3045
3046 if (intel_rotation_90_or_270(rotation)) {
3047 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3048
3049 /* stride = Surface height in tiles */
3050 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3051 stride = DIV_ROUND_UP(fb->height, tile_height);
3052 x_offset = stride * tile_height - src_y - src_h;
3053 y_offset = src_x;
3054 plane_size = (src_w - 1) << 16 | (src_h - 1);
3055 } else {
3056 stride = fb->pitches[0] / stride_div;
3057 x_offset = src_x;
3058 y_offset = src_y;
3059 plane_size = (src_h - 1) << 16 | (src_w - 1);
3060 }
3061 plane_offset = y_offset << 16 | x_offset;
3062
3063 intel_crtc->adjusted_x = x_offset;
3064 intel_crtc->adjusted_y = y_offset;
3065
3066 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3067 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3068 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3069 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3070
3071 if (scaler_id >= 0) {
3072 uint32_t ps_ctrl = 0;
3073
3074 WARN_ON(!dst_w || !dst_h);
3075 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3076 crtc_state->scaler_state.scalers[scaler_id].mode;
3077 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3078 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3079 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3080 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3081 I915_WRITE(PLANE_POS(pipe, 0), 0);
3082 } else {
3083 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3084 }
3085
3086 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3087
3088 POSTING_READ(PLANE_SURF(pipe, 0));
3089 }
3090
3091 static void skylake_disable_primary_plane(struct drm_plane *primary,
3092 struct drm_crtc *crtc)
3093 {
3094 struct drm_device *dev = crtc->dev;
3095 struct drm_i915_private *dev_priv = dev->dev_private;
3096 int pipe = to_intel_crtc(crtc)->pipe;
3097
3098 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3099 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3100 POSTING_READ(PLANE_SURF(pipe, 0));
3101 }
3102
3103 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3104 static int
3105 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3106 int x, int y, enum mode_set_atomic state)
3107 {
3108 /* Support for kgdboc is disabled, this needs a major rework. */
3109 DRM_ERROR("legacy panic handler not supported any more.\n");
3110
3111 return -ENODEV;
3112 }
3113
3114 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3115 {
3116 struct drm_crtc *crtc;
3117
3118 for_each_crtc(dev_priv->dev, crtc) {
3119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3120 enum plane plane = intel_crtc->plane;
3121
3122 intel_prepare_page_flip(dev_priv, plane);
3123 intel_finish_page_flip_plane(dev_priv, plane);
3124 }
3125 }
3126
3127 static void intel_update_primary_planes(struct drm_device *dev)
3128 {
3129 struct drm_crtc *crtc;
3130
3131 for_each_crtc(dev, crtc) {
3132 struct intel_plane *plane = to_intel_plane(crtc->primary);
3133 struct intel_plane_state *plane_state;
3134
3135 drm_modeset_lock_crtc(crtc, &plane->base);
3136 plane_state = to_intel_plane_state(plane->base.state);
3137
3138 if (plane_state->visible)
3139 plane->update_plane(&plane->base,
3140 to_intel_crtc_state(crtc->state),
3141 plane_state);
3142
3143 drm_modeset_unlock_crtc(crtc);
3144 }
3145 }
3146
3147 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3148 {
3149 /* no reset support for gen2 */
3150 if (IS_GEN2(dev_priv))
3151 return;
3152
3153 /* reset doesn't touch the display */
3154 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3155 return;
3156
3157 drm_modeset_lock_all(dev_priv->dev);
3158 /*
3159 * Disabling the crtcs gracefully seems nicer. Also the
3160 * g33 docs say we should at least disable all the planes.
3161 */
3162 intel_display_suspend(dev_priv->dev);
3163 }
3164
3165 void intel_finish_reset(struct drm_i915_private *dev_priv)
3166 {
3167 /*
3168 * Flips in the rings will be nuked by the reset,
3169 * so complete all pending flips so that user space
3170 * will get its events and not get stuck.
3171 */
3172 intel_complete_page_flips(dev_priv);
3173
3174 /* no reset support for gen2 */
3175 if (IS_GEN2(dev_priv))
3176 return;
3177
3178 /* reset doesn't touch the display */
3179 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3180 /*
3181 * Flips in the rings have been nuked by the reset,
3182 * so update the base address of all primary
3183 * planes to the the last fb to make sure we're
3184 * showing the correct fb after a reset.
3185 *
3186 * FIXME: Atomic will make this obsolete since we won't schedule
3187 * CS-based flips (which might get lost in gpu resets) any more.
3188 */
3189 intel_update_primary_planes(dev_priv->dev);
3190 return;
3191 }
3192
3193 /*
3194 * The display has been reset as well,
3195 * so need a full re-initialization.
3196 */
3197 intel_runtime_pm_disable_interrupts(dev_priv);
3198 intel_runtime_pm_enable_interrupts(dev_priv);
3199
3200 intel_modeset_init_hw(dev_priv->dev);
3201
3202 spin_lock_irq(&dev_priv->irq_lock);
3203 if (dev_priv->display.hpd_irq_setup)
3204 dev_priv->display.hpd_irq_setup(dev_priv);
3205 spin_unlock_irq(&dev_priv->irq_lock);
3206
3207 intel_display_resume(dev_priv->dev);
3208
3209 intel_hpd_init(dev_priv);
3210
3211 drm_modeset_unlock_all(dev_priv->dev);
3212 }
3213
3214 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3215 {
3216 struct drm_device *dev = crtc->dev;
3217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218 unsigned reset_counter;
3219 bool pending;
3220
3221 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3222 if (intel_crtc->reset_counter != reset_counter)
3223 return false;
3224
3225 spin_lock_irq(&dev->event_lock);
3226 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3227 spin_unlock_irq(&dev->event_lock);
3228
3229 return pending;
3230 }
3231
3232 static void intel_update_pipe_config(struct intel_crtc *crtc,
3233 struct intel_crtc_state *old_crtc_state)
3234 {
3235 struct drm_device *dev = crtc->base.dev;
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 struct intel_crtc_state *pipe_config =
3238 to_intel_crtc_state(crtc->base.state);
3239
3240 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3241 crtc->base.mode = crtc->base.state->mode;
3242
3243 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3244 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3245 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3246
3247 /*
3248 * Update pipe size and adjust fitter if needed: the reason for this is
3249 * that in compute_mode_changes we check the native mode (not the pfit
3250 * mode) to see if we can flip rather than do a full mode set. In the
3251 * fastboot case, we'll flip, but if we don't update the pipesrc and
3252 * pfit state, we'll end up with a big fb scanned out into the wrong
3253 * sized surface.
3254 */
3255
3256 I915_WRITE(PIPESRC(crtc->pipe),
3257 ((pipe_config->pipe_src_w - 1) << 16) |
3258 (pipe_config->pipe_src_h - 1));
3259
3260 /* on skylake this is done by detaching scalers */
3261 if (INTEL_INFO(dev)->gen >= 9) {
3262 skl_detach_scalers(crtc);
3263
3264 if (pipe_config->pch_pfit.enabled)
3265 skylake_pfit_enable(crtc);
3266 } else if (HAS_PCH_SPLIT(dev)) {
3267 if (pipe_config->pch_pfit.enabled)
3268 ironlake_pfit_enable(crtc);
3269 else if (old_crtc_state->pch_pfit.enabled)
3270 ironlake_pfit_disable(crtc, true);
3271 }
3272 }
3273
3274 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3275 {
3276 struct drm_device *dev = crtc->dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279 int pipe = intel_crtc->pipe;
3280 i915_reg_t reg;
3281 u32 temp;
3282
3283 /* enable normal train */
3284 reg = FDI_TX_CTL(pipe);
3285 temp = I915_READ(reg);
3286 if (IS_IVYBRIDGE(dev)) {
3287 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3288 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3289 } else {
3290 temp &= ~FDI_LINK_TRAIN_NONE;
3291 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3292 }
3293 I915_WRITE(reg, temp);
3294
3295 reg = FDI_RX_CTL(pipe);
3296 temp = I915_READ(reg);
3297 if (HAS_PCH_CPT(dev)) {
3298 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3299 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3300 } else {
3301 temp &= ~FDI_LINK_TRAIN_NONE;
3302 temp |= FDI_LINK_TRAIN_NONE;
3303 }
3304 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3305
3306 /* wait one idle pattern time */
3307 POSTING_READ(reg);
3308 udelay(1000);
3309
3310 /* IVB wants error correction enabled */
3311 if (IS_IVYBRIDGE(dev))
3312 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3313 FDI_FE_ERRC_ENABLE);
3314 }
3315
3316 /* The FDI link training functions for ILK/Ibexpeak. */
3317 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3318 {
3319 struct drm_device *dev = crtc->dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3322 int pipe = intel_crtc->pipe;
3323 i915_reg_t reg;
3324 u32 temp, tries;
3325
3326 /* FDI needs bits from pipe first */
3327 assert_pipe_enabled(dev_priv, pipe);
3328
3329 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3330 for train result */
3331 reg = FDI_RX_IMR(pipe);
3332 temp = I915_READ(reg);
3333 temp &= ~FDI_RX_SYMBOL_LOCK;
3334 temp &= ~FDI_RX_BIT_LOCK;
3335 I915_WRITE(reg, temp);
3336 I915_READ(reg);
3337 udelay(150);
3338
3339 /* enable CPU FDI TX and PCH FDI RX */
3340 reg = FDI_TX_CTL(pipe);
3341 temp = I915_READ(reg);
3342 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3343 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_PATTERN_1;
3346 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3347
3348 reg = FDI_RX_CTL(pipe);
3349 temp = I915_READ(reg);
3350 temp &= ~FDI_LINK_TRAIN_NONE;
3351 temp |= FDI_LINK_TRAIN_PATTERN_1;
3352 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3353
3354 POSTING_READ(reg);
3355 udelay(150);
3356
3357 /* Ironlake workaround, enable clock pointer after FDI enable*/
3358 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3359 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3360 FDI_RX_PHASE_SYNC_POINTER_EN);
3361
3362 reg = FDI_RX_IIR(pipe);
3363 for (tries = 0; tries < 5; tries++) {
3364 temp = I915_READ(reg);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366
3367 if ((temp & FDI_RX_BIT_LOCK)) {
3368 DRM_DEBUG_KMS("FDI train 1 done.\n");
3369 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3370 break;
3371 }
3372 }
3373 if (tries == 5)
3374 DRM_ERROR("FDI train 1 fail!\n");
3375
3376 /* Train 2 */
3377 reg = FDI_TX_CTL(pipe);
3378 temp = I915_READ(reg);
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_PATTERN_2;
3381 I915_WRITE(reg, temp);
3382
3383 reg = FDI_RX_CTL(pipe);
3384 temp = I915_READ(reg);
3385 temp &= ~FDI_LINK_TRAIN_NONE;
3386 temp |= FDI_LINK_TRAIN_PATTERN_2;
3387 I915_WRITE(reg, temp);
3388
3389 POSTING_READ(reg);
3390 udelay(150);
3391
3392 reg = FDI_RX_IIR(pipe);
3393 for (tries = 0; tries < 5; tries++) {
3394 temp = I915_READ(reg);
3395 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3396
3397 if (temp & FDI_RX_SYMBOL_LOCK) {
3398 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3399 DRM_DEBUG_KMS("FDI train 2 done.\n");
3400 break;
3401 }
3402 }
3403 if (tries == 5)
3404 DRM_ERROR("FDI train 2 fail!\n");
3405
3406 DRM_DEBUG_KMS("FDI train done\n");
3407
3408 }
3409
3410 static const int snb_b_fdi_train_param[] = {
3411 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3412 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3413 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3414 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3415 };
3416
3417 /* The FDI link training functions for SNB/Cougarpoint. */
3418 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3419 {
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 int pipe = intel_crtc->pipe;
3424 i915_reg_t reg;
3425 u32 temp, i, retry;
3426
3427 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3428 for train result */
3429 reg = FDI_RX_IMR(pipe);
3430 temp = I915_READ(reg);
3431 temp &= ~FDI_RX_SYMBOL_LOCK;
3432 temp &= ~FDI_RX_BIT_LOCK;
3433 I915_WRITE(reg, temp);
3434
3435 POSTING_READ(reg);
3436 udelay(150);
3437
3438 /* enable CPU FDI TX and PCH FDI RX */
3439 reg = FDI_TX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3442 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3443 temp &= ~FDI_LINK_TRAIN_NONE;
3444 temp |= FDI_LINK_TRAIN_PATTERN_1;
3445 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3446 /* SNB-B */
3447 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3448 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3449
3450 I915_WRITE(FDI_RX_MISC(pipe),
3451 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3452
3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 if (HAS_PCH_CPT(dev)) {
3456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3458 } else {
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_1;
3461 }
3462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3463
3464 POSTING_READ(reg);
3465 udelay(150);
3466
3467 for (i = 0; i < 4; i++) {
3468 reg = FDI_TX_CTL(pipe);
3469 temp = I915_READ(reg);
3470 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3471 temp |= snb_b_fdi_train_param[i];
3472 I915_WRITE(reg, temp);
3473
3474 POSTING_READ(reg);
3475 udelay(500);
3476
3477 for (retry = 0; retry < 5; retry++) {
3478 reg = FDI_RX_IIR(pipe);
3479 temp = I915_READ(reg);
3480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3481 if (temp & FDI_RX_BIT_LOCK) {
3482 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3483 DRM_DEBUG_KMS("FDI train 1 done.\n");
3484 break;
3485 }
3486 udelay(50);
3487 }
3488 if (retry < 5)
3489 break;
3490 }
3491 if (i == 4)
3492 DRM_ERROR("FDI train 1 fail!\n");
3493
3494 /* Train 2 */
3495 reg = FDI_TX_CTL(pipe);
3496 temp = I915_READ(reg);
3497 temp &= ~FDI_LINK_TRAIN_NONE;
3498 temp |= FDI_LINK_TRAIN_PATTERN_2;
3499 if (IS_GEN6(dev)) {
3500 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3501 /* SNB-B */
3502 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3503 }
3504 I915_WRITE(reg, temp);
3505
3506 reg = FDI_RX_CTL(pipe);
3507 temp = I915_READ(reg);
3508 if (HAS_PCH_CPT(dev)) {
3509 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3511 } else {
3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_2;
3514 }
3515 I915_WRITE(reg, temp);
3516
3517 POSTING_READ(reg);
3518 udelay(150);
3519
3520 for (i = 0; i < 4; i++) {
3521 reg = FDI_TX_CTL(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3524 temp |= snb_b_fdi_train_param[i];
3525 I915_WRITE(reg, temp);
3526
3527 POSTING_READ(reg);
3528 udelay(500);
3529
3530 for (retry = 0; retry < 5; retry++) {
3531 reg = FDI_RX_IIR(pipe);
3532 temp = I915_READ(reg);
3533 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3534 if (temp & FDI_RX_SYMBOL_LOCK) {
3535 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3536 DRM_DEBUG_KMS("FDI train 2 done.\n");
3537 break;
3538 }
3539 udelay(50);
3540 }
3541 if (retry < 5)
3542 break;
3543 }
3544 if (i == 4)
3545 DRM_ERROR("FDI train 2 fail!\n");
3546
3547 DRM_DEBUG_KMS("FDI train done.\n");
3548 }
3549
3550 /* Manual link training for Ivy Bridge A0 parts */
3551 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3552 {
3553 struct drm_device *dev = crtc->dev;
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3556 int pipe = intel_crtc->pipe;
3557 i915_reg_t reg;
3558 u32 temp, i, j;
3559
3560 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3561 for train result */
3562 reg = FDI_RX_IMR(pipe);
3563 temp = I915_READ(reg);
3564 temp &= ~FDI_RX_SYMBOL_LOCK;
3565 temp &= ~FDI_RX_BIT_LOCK;
3566 I915_WRITE(reg, temp);
3567
3568 POSTING_READ(reg);
3569 udelay(150);
3570
3571 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3572 I915_READ(FDI_RX_IIR(pipe)));
3573
3574 /* Try each vswing and preemphasis setting twice before moving on */
3575 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3576 /* disable first in case we need to retry */
3577 reg = FDI_TX_CTL(pipe);
3578 temp = I915_READ(reg);
3579 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3580 temp &= ~FDI_TX_ENABLE;
3581 I915_WRITE(reg, temp);
3582
3583 reg = FDI_RX_CTL(pipe);
3584 temp = I915_READ(reg);
3585 temp &= ~FDI_LINK_TRAIN_AUTO;
3586 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3587 temp &= ~FDI_RX_ENABLE;
3588 I915_WRITE(reg, temp);
3589
3590 /* enable CPU FDI TX and PCH FDI RX */
3591 reg = FDI_TX_CTL(pipe);
3592 temp = I915_READ(reg);
3593 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3594 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3595 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[j/2];
3598 temp |= FDI_COMPOSITE_SYNC;
3599 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3600
3601 I915_WRITE(FDI_RX_MISC(pipe),
3602 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3603
3604 reg = FDI_RX_CTL(pipe);
3605 temp = I915_READ(reg);
3606 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3607 temp |= FDI_COMPOSITE_SYNC;
3608 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3609
3610 POSTING_READ(reg);
3611 udelay(1); /* should be 0.5us */
3612
3613 for (i = 0; i < 4; i++) {
3614 reg = FDI_RX_IIR(pipe);
3615 temp = I915_READ(reg);
3616 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3617
3618 if (temp & FDI_RX_BIT_LOCK ||
3619 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3620 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3621 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3622 i);
3623 break;
3624 }
3625 udelay(1); /* should be 0.5us */
3626 }
3627 if (i == 4) {
3628 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3629 continue;
3630 }
3631
3632 /* Train 2 */
3633 reg = FDI_TX_CTL(pipe);
3634 temp = I915_READ(reg);
3635 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3636 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3637 I915_WRITE(reg, temp);
3638
3639 reg = FDI_RX_CTL(pipe);
3640 temp = I915_READ(reg);
3641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3642 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3643 I915_WRITE(reg, temp);
3644
3645 POSTING_READ(reg);
3646 udelay(2); /* should be 1.5us */
3647
3648 for (i = 0; i < 4; i++) {
3649 reg = FDI_RX_IIR(pipe);
3650 temp = I915_READ(reg);
3651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3652
3653 if (temp & FDI_RX_SYMBOL_LOCK ||
3654 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3655 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3656 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3657 i);
3658 goto train_done;
3659 }
3660 udelay(2); /* should be 1.5us */
3661 }
3662 if (i == 4)
3663 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3664 }
3665
3666 train_done:
3667 DRM_DEBUG_KMS("FDI train done.\n");
3668 }
3669
3670 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3671 {
3672 struct drm_device *dev = intel_crtc->base.dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 int pipe = intel_crtc->pipe;
3675 i915_reg_t reg;
3676 u32 temp;
3677
3678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3679 reg = FDI_RX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3682 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3683 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3685
3686 POSTING_READ(reg);
3687 udelay(200);
3688
3689 /* Switch from Rawclk to PCDclk */
3690 temp = I915_READ(reg);
3691 I915_WRITE(reg, temp | FDI_PCDCLK);
3692
3693 POSTING_READ(reg);
3694 udelay(200);
3695
3696 /* Enable CPU FDI TX PLL, always on for Ironlake */
3697 reg = FDI_TX_CTL(pipe);
3698 temp = I915_READ(reg);
3699 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3700 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3701
3702 POSTING_READ(reg);
3703 udelay(100);
3704 }
3705 }
3706
3707 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3708 {
3709 struct drm_device *dev = intel_crtc->base.dev;
3710 struct drm_i915_private *dev_priv = dev->dev_private;
3711 int pipe = intel_crtc->pipe;
3712 i915_reg_t reg;
3713 u32 temp;
3714
3715 /* Switch from PCDclk to Rawclk */
3716 reg = FDI_RX_CTL(pipe);
3717 temp = I915_READ(reg);
3718 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3719
3720 /* Disable CPU FDI TX PLL */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3724
3725 POSTING_READ(reg);
3726 udelay(100);
3727
3728 reg = FDI_RX_CTL(pipe);
3729 temp = I915_READ(reg);
3730 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3731
3732 /* Wait for the clocks to turn off. */
3733 POSTING_READ(reg);
3734 udelay(100);
3735 }
3736
3737 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3738 {
3739 struct drm_device *dev = crtc->dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742 int pipe = intel_crtc->pipe;
3743 i915_reg_t reg;
3744 u32 temp;
3745
3746 /* disable CPU FDI tx and PCH FDI rx */
3747 reg = FDI_TX_CTL(pipe);
3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3750 POSTING_READ(reg);
3751
3752 reg = FDI_RX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 temp &= ~(0x7 << 16);
3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3756 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3757
3758 POSTING_READ(reg);
3759 udelay(100);
3760
3761 /* Ironlake workaround, disable clock pointer after downing FDI */
3762 if (HAS_PCH_IBX(dev))
3763 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3764
3765 /* still set train pattern 1 */
3766 reg = FDI_TX_CTL(pipe);
3767 temp = I915_READ(reg);
3768 temp &= ~FDI_LINK_TRAIN_NONE;
3769 temp |= FDI_LINK_TRAIN_PATTERN_1;
3770 I915_WRITE(reg, temp);
3771
3772 reg = FDI_RX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 if (HAS_PCH_CPT(dev)) {
3775 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3776 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3777 } else {
3778 temp &= ~FDI_LINK_TRAIN_NONE;
3779 temp |= FDI_LINK_TRAIN_PATTERN_1;
3780 }
3781 /* BPC in FDI rx is consistent with that in PIPECONF */
3782 temp &= ~(0x07 << 16);
3783 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3784 I915_WRITE(reg, temp);
3785
3786 POSTING_READ(reg);
3787 udelay(100);
3788 }
3789
3790 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3791 {
3792 struct intel_crtc *crtc;
3793
3794 /* Note that we don't need to be called with mode_config.lock here
3795 * as our list of CRTC objects is static for the lifetime of the
3796 * device and so cannot disappear as we iterate. Similarly, we can
3797 * happily treat the predicates as racy, atomic checks as userspace
3798 * cannot claim and pin a new fb without at least acquring the
3799 * struct_mutex and so serialising with us.
3800 */
3801 for_each_intel_crtc(dev, crtc) {
3802 if (atomic_read(&crtc->unpin_work_count) == 0)
3803 continue;
3804
3805 if (crtc->unpin_work)
3806 intel_wait_for_vblank(dev, crtc->pipe);
3807
3808 return true;
3809 }
3810
3811 return false;
3812 }
3813
3814 static void page_flip_completed(struct intel_crtc *intel_crtc)
3815 {
3816 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3817 struct intel_unpin_work *work = intel_crtc->unpin_work;
3818
3819 /* ensure that the unpin work is consistent wrt ->pending. */
3820 smp_rmb();
3821 intel_crtc->unpin_work = NULL;
3822
3823 if (work->event)
3824 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3825
3826 drm_crtc_vblank_put(&intel_crtc->base);
3827
3828 wake_up_all(&dev_priv->pending_flip_queue);
3829 queue_work(dev_priv->wq, &work->work);
3830
3831 trace_i915_flip_complete(intel_crtc->plane,
3832 work->pending_flip_obj);
3833 }
3834
3835 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3836 {
3837 struct drm_device *dev = crtc->dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 long ret;
3840
3841 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3842
3843 ret = wait_event_interruptible_timeout(
3844 dev_priv->pending_flip_queue,
3845 !intel_crtc_has_pending_flip(crtc),
3846 60*HZ);
3847
3848 if (ret < 0)
3849 return ret;
3850
3851 if (ret == 0) {
3852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3853
3854 spin_lock_irq(&dev->event_lock);
3855 if (intel_crtc->unpin_work) {
3856 WARN_ONCE(1, "Removing stuck page flip\n");
3857 page_flip_completed(intel_crtc);
3858 }
3859 spin_unlock_irq(&dev->event_lock);
3860 }
3861
3862 return 0;
3863 }
3864
3865 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3866 {
3867 u32 temp;
3868
3869 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3870
3871 mutex_lock(&dev_priv->sb_lock);
3872
3873 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3874 temp |= SBI_SSCCTL_DISABLE;
3875 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3876
3877 mutex_unlock(&dev_priv->sb_lock);
3878 }
3879
3880 /* Program iCLKIP clock to the desired frequency */
3881 static void lpt_program_iclkip(struct drm_crtc *crtc)
3882 {
3883 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3884 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3885 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3886 u32 temp;
3887
3888 lpt_disable_iclkip(dev_priv);
3889
3890 /* The iCLK virtual clock root frequency is in MHz,
3891 * but the adjusted_mode->crtc_clock in in KHz. To get the
3892 * divisors, it is necessary to divide one by another, so we
3893 * convert the virtual clock precision to KHz here for higher
3894 * precision.
3895 */
3896 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3897 u32 iclk_virtual_root_freq = 172800 * 1000;
3898 u32 iclk_pi_range = 64;
3899 u32 desired_divisor;
3900
3901 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3902 clock << auxdiv);
3903 divsel = (desired_divisor / iclk_pi_range) - 2;
3904 phaseinc = desired_divisor % iclk_pi_range;
3905
3906 /*
3907 * Near 20MHz is a corner case which is
3908 * out of range for the 7-bit divisor
3909 */
3910 if (divsel <= 0x7f)
3911 break;
3912 }
3913
3914 /* This should not happen with any sane values */
3915 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3916 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3917 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3918 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3919
3920 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3921 clock,
3922 auxdiv,
3923 divsel,
3924 phasedir,
3925 phaseinc);
3926
3927 mutex_lock(&dev_priv->sb_lock);
3928
3929 /* Program SSCDIVINTPHASE6 */
3930 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3931 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3932 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3933 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3934 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3935 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3936 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3937 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3938
3939 /* Program SSCAUXDIV */
3940 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3941 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3942 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3943 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3944
3945 /* Enable modulator and associated divider */
3946 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3947 temp &= ~SBI_SSCCTL_DISABLE;
3948 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3949
3950 mutex_unlock(&dev_priv->sb_lock);
3951
3952 /* Wait for initialization time */
3953 udelay(24);
3954
3955 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3956 }
3957
3958 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3959 {
3960 u32 divsel, phaseinc, auxdiv;
3961 u32 iclk_virtual_root_freq = 172800 * 1000;
3962 u32 iclk_pi_range = 64;
3963 u32 desired_divisor;
3964 u32 temp;
3965
3966 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3967 return 0;
3968
3969 mutex_lock(&dev_priv->sb_lock);
3970
3971 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3972 if (temp & SBI_SSCCTL_DISABLE) {
3973 mutex_unlock(&dev_priv->sb_lock);
3974 return 0;
3975 }
3976
3977 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3978 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3979 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3980 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3981 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3982
3983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3984 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3985 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3986
3987 mutex_unlock(&dev_priv->sb_lock);
3988
3989 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3990
3991 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3992 desired_divisor << auxdiv);
3993 }
3994
3995 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3996 enum pipe pch_transcoder)
3997 {
3998 struct drm_device *dev = crtc->base.dev;
3999 struct drm_i915_private *dev_priv = dev->dev_private;
4000 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4001
4002 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4003 I915_READ(HTOTAL(cpu_transcoder)));
4004 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4005 I915_READ(HBLANK(cpu_transcoder)));
4006 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4007 I915_READ(HSYNC(cpu_transcoder)));
4008
4009 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4010 I915_READ(VTOTAL(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4012 I915_READ(VBLANK(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4014 I915_READ(VSYNC(cpu_transcoder)));
4015 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4016 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4017 }
4018
4019 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4020 {
4021 struct drm_i915_private *dev_priv = dev->dev_private;
4022 uint32_t temp;
4023
4024 temp = I915_READ(SOUTH_CHICKEN1);
4025 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4026 return;
4027
4028 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4029 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4030
4031 temp &= ~FDI_BC_BIFURCATION_SELECT;
4032 if (enable)
4033 temp |= FDI_BC_BIFURCATION_SELECT;
4034
4035 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4036 I915_WRITE(SOUTH_CHICKEN1, temp);
4037 POSTING_READ(SOUTH_CHICKEN1);
4038 }
4039
4040 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4041 {
4042 struct drm_device *dev = intel_crtc->base.dev;
4043
4044 switch (intel_crtc->pipe) {
4045 case PIPE_A:
4046 break;
4047 case PIPE_B:
4048 if (intel_crtc->config->fdi_lanes > 2)
4049 cpt_set_fdi_bc_bifurcation(dev, false);
4050 else
4051 cpt_set_fdi_bc_bifurcation(dev, true);
4052
4053 break;
4054 case PIPE_C:
4055 cpt_set_fdi_bc_bifurcation(dev, true);
4056
4057 break;
4058 default:
4059 BUG();
4060 }
4061 }
4062
4063 /* Return which DP Port should be selected for Transcoder DP control */
4064 static enum port
4065 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4066 {
4067 struct drm_device *dev = crtc->dev;
4068 struct intel_encoder *encoder;
4069
4070 for_each_encoder_on_crtc(dev, crtc, encoder) {
4071 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4072 encoder->type == INTEL_OUTPUT_EDP)
4073 return enc_to_dig_port(&encoder->base)->port;
4074 }
4075
4076 return -1;
4077 }
4078
4079 /*
4080 * Enable PCH resources required for PCH ports:
4081 * - PCH PLLs
4082 * - FDI training & RX/TX
4083 * - update transcoder timings
4084 * - DP transcoding bits
4085 * - transcoder
4086 */
4087 static void ironlake_pch_enable(struct drm_crtc *crtc)
4088 {
4089 struct drm_device *dev = crtc->dev;
4090 struct drm_i915_private *dev_priv = dev->dev_private;
4091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4092 int pipe = intel_crtc->pipe;
4093 u32 temp;
4094
4095 assert_pch_transcoder_disabled(dev_priv, pipe);
4096
4097 if (IS_IVYBRIDGE(dev))
4098 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4099
4100 /* Write the TU size bits before fdi link training, so that error
4101 * detection works. */
4102 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4103 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4104
4105 /* For PCH output, training FDI link */
4106 dev_priv->display.fdi_link_train(crtc);
4107
4108 /* We need to program the right clock selection before writing the pixel
4109 * mutliplier into the DPLL. */
4110 if (HAS_PCH_CPT(dev)) {
4111 u32 sel;
4112
4113 temp = I915_READ(PCH_DPLL_SEL);
4114 temp |= TRANS_DPLL_ENABLE(pipe);
4115 sel = TRANS_DPLLB_SEL(pipe);
4116 if (intel_crtc->config->shared_dpll ==
4117 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4118 temp |= sel;
4119 else
4120 temp &= ~sel;
4121 I915_WRITE(PCH_DPLL_SEL, temp);
4122 }
4123
4124 /* XXX: pch pll's can be enabled any time before we enable the PCH
4125 * transcoder, and we actually should do this to not upset any PCH
4126 * transcoder that already use the clock when we share it.
4127 *
4128 * Note that enable_shared_dpll tries to do the right thing, but
4129 * get_shared_dpll unconditionally resets the pll - we need that to have
4130 * the right LVDS enable sequence. */
4131 intel_enable_shared_dpll(intel_crtc);
4132
4133 /* set transcoder timing, panel must allow it */
4134 assert_panel_unlocked(dev_priv, pipe);
4135 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4136
4137 intel_fdi_normal_train(crtc);
4138
4139 /* For PCH DP, enable TRANS_DP_CTL */
4140 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4141 const struct drm_display_mode *adjusted_mode =
4142 &intel_crtc->config->base.adjusted_mode;
4143 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4144 i915_reg_t reg = TRANS_DP_CTL(pipe);
4145 temp = I915_READ(reg);
4146 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4147 TRANS_DP_SYNC_MASK |
4148 TRANS_DP_BPC_MASK);
4149 temp |= TRANS_DP_OUTPUT_ENABLE;
4150 temp |= bpc << 9; /* same format but at 11:9 */
4151
4152 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4153 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4154 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4155 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4156
4157 switch (intel_trans_dp_port_sel(crtc)) {
4158 case PORT_B:
4159 temp |= TRANS_DP_PORT_SEL_B;
4160 break;
4161 case PORT_C:
4162 temp |= TRANS_DP_PORT_SEL_C;
4163 break;
4164 case PORT_D:
4165 temp |= TRANS_DP_PORT_SEL_D;
4166 break;
4167 default:
4168 BUG();
4169 }
4170
4171 I915_WRITE(reg, temp);
4172 }
4173
4174 ironlake_enable_pch_transcoder(dev_priv, pipe);
4175 }
4176
4177 static void lpt_pch_enable(struct drm_crtc *crtc)
4178 {
4179 struct drm_device *dev = crtc->dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4183
4184 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4185
4186 lpt_program_iclkip(crtc);
4187
4188 /* Set transcoder timing. */
4189 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4190
4191 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4192 }
4193
4194 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4195 {
4196 struct drm_i915_private *dev_priv = dev->dev_private;
4197 i915_reg_t dslreg = PIPEDSL(pipe);
4198 u32 temp;
4199
4200 temp = I915_READ(dslreg);
4201 udelay(500);
4202 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4203 if (wait_for(I915_READ(dslreg) != temp, 5))
4204 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4205 }
4206 }
4207
4208 static int
4209 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4210 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4211 int src_w, int src_h, int dst_w, int dst_h)
4212 {
4213 struct intel_crtc_scaler_state *scaler_state =
4214 &crtc_state->scaler_state;
4215 struct intel_crtc *intel_crtc =
4216 to_intel_crtc(crtc_state->base.crtc);
4217 int need_scaling;
4218
4219 need_scaling = intel_rotation_90_or_270(rotation) ?
4220 (src_h != dst_w || src_w != dst_h):
4221 (src_w != dst_w || src_h != dst_h);
4222
4223 /*
4224 * if plane is being disabled or scaler is no more required or force detach
4225 * - free scaler binded to this plane/crtc
4226 * - in order to do this, update crtc->scaler_usage
4227 *
4228 * Here scaler state in crtc_state is set free so that
4229 * scaler can be assigned to other user. Actual register
4230 * update to free the scaler is done in plane/panel-fit programming.
4231 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4232 */
4233 if (force_detach || !need_scaling) {
4234 if (*scaler_id >= 0) {
4235 scaler_state->scaler_users &= ~(1 << scaler_user);
4236 scaler_state->scalers[*scaler_id].in_use = 0;
4237
4238 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4239 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4240 intel_crtc->pipe, scaler_user, *scaler_id,
4241 scaler_state->scaler_users);
4242 *scaler_id = -1;
4243 }
4244 return 0;
4245 }
4246
4247 /* range checks */
4248 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4249 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4250
4251 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4252 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4253 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4254 "size is out of scaler range\n",
4255 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4256 return -EINVAL;
4257 }
4258
4259 /* mark this plane as a scaler user in crtc_state */
4260 scaler_state->scaler_users |= (1 << scaler_user);
4261 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4262 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4263 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4264 scaler_state->scaler_users);
4265
4266 return 0;
4267 }
4268
4269 /**
4270 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4271 *
4272 * @state: crtc's scaler state
4273 *
4274 * Return
4275 * 0 - scaler_usage updated successfully
4276 * error - requested scaling cannot be supported or other error condition
4277 */
4278 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4279 {
4280 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4281 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4282
4283 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4284 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4285
4286 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4287 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4288 state->pipe_src_w, state->pipe_src_h,
4289 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4290 }
4291
4292 /**
4293 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4294 *
4295 * @state: crtc's scaler state
4296 * @plane_state: atomic plane state to update
4297 *
4298 * Return
4299 * 0 - scaler_usage updated successfully
4300 * error - requested scaling cannot be supported or other error condition
4301 */
4302 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4303 struct intel_plane_state *plane_state)
4304 {
4305
4306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4307 struct intel_plane *intel_plane =
4308 to_intel_plane(plane_state->base.plane);
4309 struct drm_framebuffer *fb = plane_state->base.fb;
4310 int ret;
4311
4312 bool force_detach = !fb || !plane_state->visible;
4313
4314 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4315 intel_plane->base.base.id, intel_crtc->pipe,
4316 drm_plane_index(&intel_plane->base));
4317
4318 ret = skl_update_scaler(crtc_state, force_detach,
4319 drm_plane_index(&intel_plane->base),
4320 &plane_state->scaler_id,
4321 plane_state->base.rotation,
4322 drm_rect_width(&plane_state->src) >> 16,
4323 drm_rect_height(&plane_state->src) >> 16,
4324 drm_rect_width(&plane_state->dst),
4325 drm_rect_height(&plane_state->dst));
4326
4327 if (ret || plane_state->scaler_id < 0)
4328 return ret;
4329
4330 /* check colorkey */
4331 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4332 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4333 intel_plane->base.base.id);
4334 return -EINVAL;
4335 }
4336
4337 /* Check src format */
4338 switch (fb->pixel_format) {
4339 case DRM_FORMAT_RGB565:
4340 case DRM_FORMAT_XBGR8888:
4341 case DRM_FORMAT_XRGB8888:
4342 case DRM_FORMAT_ABGR8888:
4343 case DRM_FORMAT_ARGB8888:
4344 case DRM_FORMAT_XRGB2101010:
4345 case DRM_FORMAT_XBGR2101010:
4346 case DRM_FORMAT_YUYV:
4347 case DRM_FORMAT_YVYU:
4348 case DRM_FORMAT_UYVY:
4349 case DRM_FORMAT_VYUY:
4350 break;
4351 default:
4352 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4353 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4354 return -EINVAL;
4355 }
4356
4357 return 0;
4358 }
4359
4360 static void skylake_scaler_disable(struct intel_crtc *crtc)
4361 {
4362 int i;
4363
4364 for (i = 0; i < crtc->num_scalers; i++)
4365 skl_detach_scaler(crtc, i);
4366 }
4367
4368 static void skylake_pfit_enable(struct intel_crtc *crtc)
4369 {
4370 struct drm_device *dev = crtc->base.dev;
4371 struct drm_i915_private *dev_priv = dev->dev_private;
4372 int pipe = crtc->pipe;
4373 struct intel_crtc_scaler_state *scaler_state =
4374 &crtc->config->scaler_state;
4375
4376 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4377
4378 if (crtc->config->pch_pfit.enabled) {
4379 int id;
4380
4381 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4382 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4383 return;
4384 }
4385
4386 id = scaler_state->scaler_id;
4387 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4388 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4389 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4390 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4391
4392 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4393 }
4394 }
4395
4396 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4397 {
4398 struct drm_device *dev = crtc->base.dev;
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 int pipe = crtc->pipe;
4401
4402 if (crtc->config->pch_pfit.enabled) {
4403 /* Force use of hard-coded filter coefficients
4404 * as some pre-programmed values are broken,
4405 * e.g. x201.
4406 */
4407 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4408 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4409 PF_PIPE_SEL_IVB(pipe));
4410 else
4411 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4412 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4413 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4414 }
4415 }
4416
4417 void hsw_enable_ips(struct intel_crtc *crtc)
4418 {
4419 struct drm_device *dev = crtc->base.dev;
4420 struct drm_i915_private *dev_priv = dev->dev_private;
4421
4422 if (!crtc->config->ips_enabled)
4423 return;
4424
4425 /*
4426 * We can only enable IPS after we enable a plane and wait for a vblank
4427 * This function is called from post_plane_update, which is run after
4428 * a vblank wait.
4429 */
4430
4431 assert_plane_enabled(dev_priv, crtc->plane);
4432 if (IS_BROADWELL(dev)) {
4433 mutex_lock(&dev_priv->rps.hw_lock);
4434 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4435 mutex_unlock(&dev_priv->rps.hw_lock);
4436 /* Quoting Art Runyan: "its not safe to expect any particular
4437 * value in IPS_CTL bit 31 after enabling IPS through the
4438 * mailbox." Moreover, the mailbox may return a bogus state,
4439 * so we need to just enable it and continue on.
4440 */
4441 } else {
4442 I915_WRITE(IPS_CTL, IPS_ENABLE);
4443 /* The bit only becomes 1 in the next vblank, so this wait here
4444 * is essentially intel_wait_for_vblank. If we don't have this
4445 * and don't wait for vblanks until the end of crtc_enable, then
4446 * the HW state readout code will complain that the expected
4447 * IPS_CTL value is not the one we read. */
4448 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4449 DRM_ERROR("Timed out waiting for IPS enable\n");
4450 }
4451 }
4452
4453 void hsw_disable_ips(struct intel_crtc *crtc)
4454 {
4455 struct drm_device *dev = crtc->base.dev;
4456 struct drm_i915_private *dev_priv = dev->dev_private;
4457
4458 if (!crtc->config->ips_enabled)
4459 return;
4460
4461 assert_plane_enabled(dev_priv, crtc->plane);
4462 if (IS_BROADWELL(dev)) {
4463 mutex_lock(&dev_priv->rps.hw_lock);
4464 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4465 mutex_unlock(&dev_priv->rps.hw_lock);
4466 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4467 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4468 DRM_ERROR("Timed out waiting for IPS disable\n");
4469 } else {
4470 I915_WRITE(IPS_CTL, 0);
4471 POSTING_READ(IPS_CTL);
4472 }
4473
4474 /* We need to wait for a vblank before we can disable the plane. */
4475 intel_wait_for_vblank(dev, crtc->pipe);
4476 }
4477
4478 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4479 {
4480 if (intel_crtc->overlay) {
4481 struct drm_device *dev = intel_crtc->base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483
4484 mutex_lock(&dev->struct_mutex);
4485 dev_priv->mm.interruptible = false;
4486 (void) intel_overlay_switch_off(intel_crtc->overlay);
4487 dev_priv->mm.interruptible = true;
4488 mutex_unlock(&dev->struct_mutex);
4489 }
4490
4491 /* Let userspace switch the overlay on again. In most cases userspace
4492 * has to recompute where to put it anyway.
4493 */
4494 }
4495
4496 /**
4497 * intel_post_enable_primary - Perform operations after enabling primary plane
4498 * @crtc: the CRTC whose primary plane was just enabled
4499 *
4500 * Performs potentially sleeping operations that must be done after the primary
4501 * plane is enabled, such as updating FBC and IPS. Note that this may be
4502 * called due to an explicit primary plane update, or due to an implicit
4503 * re-enable that is caused when a sprite plane is updated to no longer
4504 * completely hide the primary plane.
4505 */
4506 static void
4507 intel_post_enable_primary(struct drm_crtc *crtc)
4508 {
4509 struct drm_device *dev = crtc->dev;
4510 struct drm_i915_private *dev_priv = dev->dev_private;
4511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4512 int pipe = intel_crtc->pipe;
4513
4514 /*
4515 * FIXME IPS should be fine as long as one plane is
4516 * enabled, but in practice it seems to have problems
4517 * when going from primary only to sprite only and vice
4518 * versa.
4519 */
4520 hsw_enable_ips(intel_crtc);
4521
4522 /*
4523 * Gen2 reports pipe underruns whenever all planes are disabled.
4524 * So don't enable underrun reporting before at least some planes
4525 * are enabled.
4526 * FIXME: Need to fix the logic to work when we turn off all planes
4527 * but leave the pipe running.
4528 */
4529 if (IS_GEN2(dev))
4530 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4531
4532 /* Underruns don't always raise interrupts, so check manually. */
4533 intel_check_cpu_fifo_underruns(dev_priv);
4534 intel_check_pch_fifo_underruns(dev_priv);
4535 }
4536
4537 /* FIXME move all this to pre_plane_update() with proper state tracking */
4538 static void
4539 intel_pre_disable_primary(struct drm_crtc *crtc)
4540 {
4541 struct drm_device *dev = crtc->dev;
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4544 int pipe = intel_crtc->pipe;
4545
4546 /*
4547 * Gen2 reports pipe underruns whenever all planes are disabled.
4548 * So diasble underrun reporting before all the planes get disabled.
4549 * FIXME: Need to fix the logic to work when we turn off all planes
4550 * but leave the pipe running.
4551 */
4552 if (IS_GEN2(dev))
4553 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4554
4555 /*
4556 * FIXME IPS should be fine as long as one plane is
4557 * enabled, but in practice it seems to have problems
4558 * when going from primary only to sprite only and vice
4559 * versa.
4560 */
4561 hsw_disable_ips(intel_crtc);
4562 }
4563
4564 /* FIXME get rid of this and use pre_plane_update */
4565 static void
4566 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4567 {
4568 struct drm_device *dev = crtc->dev;
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4571 int pipe = intel_crtc->pipe;
4572
4573 intel_pre_disable_primary(crtc);
4574
4575 /*
4576 * Vblank time updates from the shadow to live plane control register
4577 * are blocked if the memory self-refresh mode is active at that
4578 * moment. So to make sure the plane gets truly disabled, disable
4579 * first the self-refresh mode. The self-refresh enable bit in turn
4580 * will be checked/applied by the HW only at the next frame start
4581 * event which is after the vblank start event, so we need to have a
4582 * wait-for-vblank between disabling the plane and the pipe.
4583 */
4584 if (HAS_GMCH_DISPLAY(dev)) {
4585 intel_set_memory_cxsr(dev_priv, false);
4586 dev_priv->wm.vlv.cxsr = false;
4587 intel_wait_for_vblank(dev, pipe);
4588 }
4589 }
4590
4591 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4592 {
4593 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4594 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4595 struct intel_crtc_state *pipe_config =
4596 to_intel_crtc_state(crtc->base.state);
4597 struct drm_device *dev = crtc->base.dev;
4598 struct drm_plane *primary = crtc->base.primary;
4599 struct drm_plane_state *old_pri_state =
4600 drm_atomic_get_existing_plane_state(old_state, primary);
4601
4602 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4603
4604 crtc->wm.cxsr_allowed = true;
4605
4606 if (pipe_config->update_wm_post && pipe_config->base.active)
4607 intel_update_watermarks(&crtc->base);
4608
4609 if (old_pri_state) {
4610 struct intel_plane_state *primary_state =
4611 to_intel_plane_state(primary->state);
4612 struct intel_plane_state *old_primary_state =
4613 to_intel_plane_state(old_pri_state);
4614
4615 intel_fbc_post_update(crtc);
4616
4617 if (primary_state->visible &&
4618 (needs_modeset(&pipe_config->base) ||
4619 !old_primary_state->visible))
4620 intel_post_enable_primary(&crtc->base);
4621 }
4622 }
4623
4624 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4625 {
4626 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4627 struct drm_device *dev = crtc->base.dev;
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 struct intel_crtc_state *pipe_config =
4630 to_intel_crtc_state(crtc->base.state);
4631 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4632 struct drm_plane *primary = crtc->base.primary;
4633 struct drm_plane_state *old_pri_state =
4634 drm_atomic_get_existing_plane_state(old_state, primary);
4635 bool modeset = needs_modeset(&pipe_config->base);
4636
4637 if (old_pri_state) {
4638 struct intel_plane_state *primary_state =
4639 to_intel_plane_state(primary->state);
4640 struct intel_plane_state *old_primary_state =
4641 to_intel_plane_state(old_pri_state);
4642
4643 intel_fbc_pre_update(crtc);
4644
4645 if (old_primary_state->visible &&
4646 (modeset || !primary_state->visible))
4647 intel_pre_disable_primary(&crtc->base);
4648 }
4649
4650 if (pipe_config->disable_cxsr) {
4651 crtc->wm.cxsr_allowed = false;
4652
4653 /*
4654 * Vblank time updates from the shadow to live plane control register
4655 * are blocked if the memory self-refresh mode is active at that
4656 * moment. So to make sure the plane gets truly disabled, disable
4657 * first the self-refresh mode. The self-refresh enable bit in turn
4658 * will be checked/applied by the HW only at the next frame start
4659 * event which is after the vblank start event, so we need to have a
4660 * wait-for-vblank between disabling the plane and the pipe.
4661 */
4662 if (old_crtc_state->base.active) {
4663 intel_set_memory_cxsr(dev_priv, false);
4664 dev_priv->wm.vlv.cxsr = false;
4665 intel_wait_for_vblank(dev, crtc->pipe);
4666 }
4667 }
4668
4669 /*
4670 * IVB workaround: must disable low power watermarks for at least
4671 * one frame before enabling scaling. LP watermarks can be re-enabled
4672 * when scaling is disabled.
4673 *
4674 * WaCxSRDisabledForSpriteScaling:ivb
4675 */
4676 if (pipe_config->disable_lp_wm) {
4677 ilk_disable_lp_wm(dev);
4678 intel_wait_for_vblank(dev, crtc->pipe);
4679 }
4680
4681 /*
4682 * If we're doing a modeset, we're done. No need to do any pre-vblank
4683 * watermark programming here.
4684 */
4685 if (needs_modeset(&pipe_config->base))
4686 return;
4687
4688 /*
4689 * For platforms that support atomic watermarks, program the
4690 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4691 * will be the intermediate values that are safe for both pre- and
4692 * post- vblank; when vblank happens, the 'active' values will be set
4693 * to the final 'target' values and we'll do this again to get the
4694 * optimal watermarks. For gen9+ platforms, the values we program here
4695 * will be the final target values which will get automatically latched
4696 * at vblank time; no further programming will be necessary.
4697 *
4698 * If a platform hasn't been transitioned to atomic watermarks yet,
4699 * we'll continue to update watermarks the old way, if flags tell
4700 * us to.
4701 */
4702 if (dev_priv->display.initial_watermarks != NULL)
4703 dev_priv->display.initial_watermarks(pipe_config);
4704 else if (pipe_config->update_wm_pre)
4705 intel_update_watermarks(&crtc->base);
4706 }
4707
4708 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4709 {
4710 struct drm_device *dev = crtc->dev;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 struct drm_plane *p;
4713 int pipe = intel_crtc->pipe;
4714
4715 intel_crtc_dpms_overlay_disable(intel_crtc);
4716
4717 drm_for_each_plane_mask(p, dev, plane_mask)
4718 to_intel_plane(p)->disable_plane(p, crtc);
4719
4720 /*
4721 * FIXME: Once we grow proper nuclear flip support out of this we need
4722 * to compute the mask of flip planes precisely. For the time being
4723 * consider this a flip to a NULL plane.
4724 */
4725 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4726 }
4727
4728 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4729 {
4730 struct drm_device *dev = crtc->dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733 struct intel_encoder *encoder;
4734 int pipe = intel_crtc->pipe;
4735 struct intel_crtc_state *pipe_config =
4736 to_intel_crtc_state(crtc->state);
4737
4738 if (WARN_ON(intel_crtc->active))
4739 return;
4740
4741 /*
4742 * Sometimes spurious CPU pipe underruns happen during FDI
4743 * training, at least with VGA+HDMI cloning. Suppress them.
4744 *
4745 * On ILK we get an occasional spurious CPU pipe underruns
4746 * between eDP port A enable and vdd enable. Also PCH port
4747 * enable seems to result in the occasional CPU pipe underrun.
4748 *
4749 * Spurious PCH underruns also occur during PCH enabling.
4750 */
4751 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4752 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4753 if (intel_crtc->config->has_pch_encoder)
4754 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4755
4756 if (intel_crtc->config->has_pch_encoder)
4757 intel_prepare_shared_dpll(intel_crtc);
4758
4759 if (intel_crtc->config->has_dp_encoder)
4760 intel_dp_set_m_n(intel_crtc, M1_N1);
4761
4762 intel_set_pipe_timings(intel_crtc);
4763 intel_set_pipe_src_size(intel_crtc);
4764
4765 if (intel_crtc->config->has_pch_encoder) {
4766 intel_cpu_transcoder_set_m_n(intel_crtc,
4767 &intel_crtc->config->fdi_m_n, NULL);
4768 }
4769
4770 ironlake_set_pipeconf(crtc);
4771
4772 intel_crtc->active = true;
4773
4774 for_each_encoder_on_crtc(dev, crtc, encoder)
4775 if (encoder->pre_enable)
4776 encoder->pre_enable(encoder);
4777
4778 if (intel_crtc->config->has_pch_encoder) {
4779 /* Note: FDI PLL enabling _must_ be done before we enable the
4780 * cpu pipes, hence this is separate from all the other fdi/pch
4781 * enabling. */
4782 ironlake_fdi_pll_enable(intel_crtc);
4783 } else {
4784 assert_fdi_tx_disabled(dev_priv, pipe);
4785 assert_fdi_rx_disabled(dev_priv, pipe);
4786 }
4787
4788 ironlake_pfit_enable(intel_crtc);
4789
4790 /*
4791 * On ILK+ LUT must be loaded before the pipe is running but with
4792 * clocks enabled
4793 */
4794 intel_color_load_luts(&pipe_config->base);
4795
4796 if (dev_priv->display.initial_watermarks != NULL)
4797 dev_priv->display.initial_watermarks(intel_crtc->config);
4798 intel_enable_pipe(intel_crtc);
4799
4800 if (intel_crtc->config->has_pch_encoder)
4801 ironlake_pch_enable(crtc);
4802
4803 assert_vblank_disabled(crtc);
4804 drm_crtc_vblank_on(crtc);
4805
4806 for_each_encoder_on_crtc(dev, crtc, encoder)
4807 encoder->enable(encoder);
4808
4809 if (HAS_PCH_CPT(dev))
4810 cpt_verify_modeset(dev, intel_crtc->pipe);
4811
4812 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4813 if (intel_crtc->config->has_pch_encoder)
4814 intel_wait_for_vblank(dev, pipe);
4815 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4816 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4817 }
4818
4819 /* IPS only exists on ULT machines and is tied to pipe A. */
4820 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4821 {
4822 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4823 }
4824
4825 static void haswell_crtc_enable(struct drm_crtc *crtc)
4826 {
4827 struct drm_device *dev = crtc->dev;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4830 struct intel_encoder *encoder;
4831 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4832 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4833 struct intel_crtc_state *pipe_config =
4834 to_intel_crtc_state(crtc->state);
4835
4836 if (WARN_ON(intel_crtc->active))
4837 return;
4838
4839 if (intel_crtc->config->has_pch_encoder)
4840 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4841 false);
4842
4843 if (intel_crtc->config->shared_dpll)
4844 intel_enable_shared_dpll(intel_crtc);
4845
4846 if (intel_crtc->config->has_dp_encoder)
4847 intel_dp_set_m_n(intel_crtc, M1_N1);
4848
4849 if (!intel_crtc->config->has_dsi_encoder)
4850 intel_set_pipe_timings(intel_crtc);
4851
4852 intel_set_pipe_src_size(intel_crtc);
4853
4854 if (cpu_transcoder != TRANSCODER_EDP &&
4855 !transcoder_is_dsi(cpu_transcoder)) {
4856 I915_WRITE(PIPE_MULT(cpu_transcoder),
4857 intel_crtc->config->pixel_multiplier - 1);
4858 }
4859
4860 if (intel_crtc->config->has_pch_encoder) {
4861 intel_cpu_transcoder_set_m_n(intel_crtc,
4862 &intel_crtc->config->fdi_m_n, NULL);
4863 }
4864
4865 if (!intel_crtc->config->has_dsi_encoder)
4866 haswell_set_pipeconf(crtc);
4867
4868 haswell_set_pipemisc(crtc);
4869
4870 intel_color_set_csc(&pipe_config->base);
4871
4872 intel_crtc->active = true;
4873
4874 if (intel_crtc->config->has_pch_encoder)
4875 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4876 else
4877 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4878
4879 for_each_encoder_on_crtc(dev, crtc, encoder) {
4880 if (encoder->pre_enable)
4881 encoder->pre_enable(encoder);
4882 }
4883
4884 if (intel_crtc->config->has_pch_encoder)
4885 dev_priv->display.fdi_link_train(crtc);
4886
4887 if (!intel_crtc->config->has_dsi_encoder)
4888 intel_ddi_enable_pipe_clock(intel_crtc);
4889
4890 if (INTEL_INFO(dev)->gen >= 9)
4891 skylake_pfit_enable(intel_crtc);
4892 else
4893 ironlake_pfit_enable(intel_crtc);
4894
4895 /*
4896 * On ILK+ LUT must be loaded before the pipe is running but with
4897 * clocks enabled
4898 */
4899 intel_color_load_luts(&pipe_config->base);
4900
4901 intel_ddi_set_pipe_settings(crtc);
4902 if (!intel_crtc->config->has_dsi_encoder)
4903 intel_ddi_enable_transcoder_func(crtc);
4904
4905 if (dev_priv->display.initial_watermarks != NULL)
4906 dev_priv->display.initial_watermarks(pipe_config);
4907 else
4908 intel_update_watermarks(crtc);
4909
4910 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4911 if (!intel_crtc->config->has_dsi_encoder)
4912 intel_enable_pipe(intel_crtc);
4913
4914 if (intel_crtc->config->has_pch_encoder)
4915 lpt_pch_enable(crtc);
4916
4917 if (intel_crtc->config->dp_encoder_is_mst)
4918 intel_ddi_set_vc_payload_alloc(crtc, true);
4919
4920 assert_vblank_disabled(crtc);
4921 drm_crtc_vblank_on(crtc);
4922
4923 for_each_encoder_on_crtc(dev, crtc, encoder) {
4924 encoder->enable(encoder);
4925 intel_opregion_notify_encoder(encoder, true);
4926 }
4927
4928 if (intel_crtc->config->has_pch_encoder) {
4929 intel_wait_for_vblank(dev, pipe);
4930 intel_wait_for_vblank(dev, pipe);
4931 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4932 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4933 true);
4934 }
4935
4936 /* If we change the relative order between pipe/planes enabling, we need
4937 * to change the workaround. */
4938 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4939 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4940 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4941 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4942 }
4943 }
4944
4945 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4946 {
4947 struct drm_device *dev = crtc->base.dev;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 int pipe = crtc->pipe;
4950
4951 /* To avoid upsetting the power well on haswell only disable the pfit if
4952 * it's in use. The hw state code will make sure we get this right. */
4953 if (force || crtc->config->pch_pfit.enabled) {
4954 I915_WRITE(PF_CTL(pipe), 0);
4955 I915_WRITE(PF_WIN_POS(pipe), 0);
4956 I915_WRITE(PF_WIN_SZ(pipe), 0);
4957 }
4958 }
4959
4960 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4961 {
4962 struct drm_device *dev = crtc->dev;
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4965 struct intel_encoder *encoder;
4966 int pipe = intel_crtc->pipe;
4967
4968 /*
4969 * Sometimes spurious CPU pipe underruns happen when the
4970 * pipe is already disabled, but FDI RX/TX is still enabled.
4971 * Happens at least with VGA+HDMI cloning. Suppress them.
4972 */
4973 if (intel_crtc->config->has_pch_encoder) {
4974 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4975 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4976 }
4977
4978 for_each_encoder_on_crtc(dev, crtc, encoder)
4979 encoder->disable(encoder);
4980
4981 drm_crtc_vblank_off(crtc);
4982 assert_vblank_disabled(crtc);
4983
4984 intel_disable_pipe(intel_crtc);
4985
4986 ironlake_pfit_disable(intel_crtc, false);
4987
4988 if (intel_crtc->config->has_pch_encoder)
4989 ironlake_fdi_disable(crtc);
4990
4991 for_each_encoder_on_crtc(dev, crtc, encoder)
4992 if (encoder->post_disable)
4993 encoder->post_disable(encoder);
4994
4995 if (intel_crtc->config->has_pch_encoder) {
4996 ironlake_disable_pch_transcoder(dev_priv, pipe);
4997
4998 if (HAS_PCH_CPT(dev)) {
4999 i915_reg_t reg;
5000 u32 temp;
5001
5002 /* disable TRANS_DP_CTL */
5003 reg = TRANS_DP_CTL(pipe);
5004 temp = I915_READ(reg);
5005 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5006 TRANS_DP_PORT_SEL_MASK);
5007 temp |= TRANS_DP_PORT_SEL_NONE;
5008 I915_WRITE(reg, temp);
5009
5010 /* disable DPLL_SEL */
5011 temp = I915_READ(PCH_DPLL_SEL);
5012 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5013 I915_WRITE(PCH_DPLL_SEL, temp);
5014 }
5015
5016 ironlake_fdi_pll_disable(intel_crtc);
5017 }
5018
5019 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5020 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5021 }
5022
5023 static void haswell_crtc_disable(struct drm_crtc *crtc)
5024 {
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 struct intel_encoder *encoder;
5029 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5030
5031 if (intel_crtc->config->has_pch_encoder)
5032 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5033 false);
5034
5035 for_each_encoder_on_crtc(dev, crtc, encoder) {
5036 intel_opregion_notify_encoder(encoder, false);
5037 encoder->disable(encoder);
5038 }
5039
5040 drm_crtc_vblank_off(crtc);
5041 assert_vblank_disabled(crtc);
5042
5043 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5044 if (!intel_crtc->config->has_dsi_encoder)
5045 intel_disable_pipe(intel_crtc);
5046
5047 if (intel_crtc->config->dp_encoder_is_mst)
5048 intel_ddi_set_vc_payload_alloc(crtc, false);
5049
5050 if (!intel_crtc->config->has_dsi_encoder)
5051 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5052
5053 if (INTEL_INFO(dev)->gen >= 9)
5054 skylake_scaler_disable(intel_crtc);
5055 else
5056 ironlake_pfit_disable(intel_crtc, false);
5057
5058 if (!intel_crtc->config->has_dsi_encoder)
5059 intel_ddi_disable_pipe_clock(intel_crtc);
5060
5061 for_each_encoder_on_crtc(dev, crtc, encoder)
5062 if (encoder->post_disable)
5063 encoder->post_disable(encoder);
5064
5065 if (intel_crtc->config->has_pch_encoder) {
5066 lpt_disable_pch_transcoder(dev_priv);
5067 lpt_disable_iclkip(dev_priv);
5068 intel_ddi_fdi_disable(crtc);
5069
5070 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5071 true);
5072 }
5073 }
5074
5075 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5076 {
5077 struct drm_device *dev = crtc->base.dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 struct intel_crtc_state *pipe_config = crtc->config;
5080
5081 if (!pipe_config->gmch_pfit.control)
5082 return;
5083
5084 /*
5085 * The panel fitter should only be adjusted whilst the pipe is disabled,
5086 * according to register description and PRM.
5087 */
5088 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5089 assert_pipe_disabled(dev_priv, crtc->pipe);
5090
5091 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5092 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5093
5094 /* Border color in case we don't scale up to the full screen. Black by
5095 * default, change to something else for debugging. */
5096 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5097 }
5098
5099 static enum intel_display_power_domain port_to_power_domain(enum port port)
5100 {
5101 switch (port) {
5102 case PORT_A:
5103 return POWER_DOMAIN_PORT_DDI_A_LANES;
5104 case PORT_B:
5105 return POWER_DOMAIN_PORT_DDI_B_LANES;
5106 case PORT_C:
5107 return POWER_DOMAIN_PORT_DDI_C_LANES;
5108 case PORT_D:
5109 return POWER_DOMAIN_PORT_DDI_D_LANES;
5110 case PORT_E:
5111 return POWER_DOMAIN_PORT_DDI_E_LANES;
5112 default:
5113 MISSING_CASE(port);
5114 return POWER_DOMAIN_PORT_OTHER;
5115 }
5116 }
5117
5118 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5119 {
5120 switch (port) {
5121 case PORT_A:
5122 return POWER_DOMAIN_AUX_A;
5123 case PORT_B:
5124 return POWER_DOMAIN_AUX_B;
5125 case PORT_C:
5126 return POWER_DOMAIN_AUX_C;
5127 case PORT_D:
5128 return POWER_DOMAIN_AUX_D;
5129 case PORT_E:
5130 /* FIXME: Check VBT for actual wiring of PORT E */
5131 return POWER_DOMAIN_AUX_D;
5132 default:
5133 MISSING_CASE(port);
5134 return POWER_DOMAIN_AUX_A;
5135 }
5136 }
5137
5138 enum intel_display_power_domain
5139 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5140 {
5141 struct drm_device *dev = intel_encoder->base.dev;
5142 struct intel_digital_port *intel_dig_port;
5143
5144 switch (intel_encoder->type) {
5145 case INTEL_OUTPUT_UNKNOWN:
5146 /* Only DDI platforms should ever use this output type */
5147 WARN_ON_ONCE(!HAS_DDI(dev));
5148 case INTEL_OUTPUT_DISPLAYPORT:
5149 case INTEL_OUTPUT_HDMI:
5150 case INTEL_OUTPUT_EDP:
5151 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5152 return port_to_power_domain(intel_dig_port->port);
5153 case INTEL_OUTPUT_DP_MST:
5154 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5155 return port_to_power_domain(intel_dig_port->port);
5156 case INTEL_OUTPUT_ANALOG:
5157 return POWER_DOMAIN_PORT_CRT;
5158 case INTEL_OUTPUT_DSI:
5159 return POWER_DOMAIN_PORT_DSI;
5160 default:
5161 return POWER_DOMAIN_PORT_OTHER;
5162 }
5163 }
5164
5165 enum intel_display_power_domain
5166 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5167 {
5168 struct drm_device *dev = intel_encoder->base.dev;
5169 struct intel_digital_port *intel_dig_port;
5170
5171 switch (intel_encoder->type) {
5172 case INTEL_OUTPUT_UNKNOWN:
5173 case INTEL_OUTPUT_HDMI:
5174 /*
5175 * Only DDI platforms should ever use these output types.
5176 * We can get here after the HDMI detect code has already set
5177 * the type of the shared encoder. Since we can't be sure
5178 * what's the status of the given connectors, play safe and
5179 * run the DP detection too.
5180 */
5181 WARN_ON_ONCE(!HAS_DDI(dev));
5182 case INTEL_OUTPUT_DISPLAYPORT:
5183 case INTEL_OUTPUT_EDP:
5184 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5185 return port_to_aux_power_domain(intel_dig_port->port);
5186 case INTEL_OUTPUT_DP_MST:
5187 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5188 return port_to_aux_power_domain(intel_dig_port->port);
5189 default:
5190 MISSING_CASE(intel_encoder->type);
5191 return POWER_DOMAIN_AUX_A;
5192 }
5193 }
5194
5195 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5196 struct intel_crtc_state *crtc_state)
5197 {
5198 struct drm_device *dev = crtc->dev;
5199 struct drm_encoder *encoder;
5200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5201 enum pipe pipe = intel_crtc->pipe;
5202 unsigned long mask;
5203 enum transcoder transcoder = crtc_state->cpu_transcoder;
5204
5205 if (!crtc_state->base.active)
5206 return 0;
5207
5208 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5209 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5210 if (crtc_state->pch_pfit.enabled ||
5211 crtc_state->pch_pfit.force_thru)
5212 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5213
5214 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5215 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5216
5217 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5218 }
5219
5220 if (crtc_state->shared_dpll)
5221 mask |= BIT(POWER_DOMAIN_PLLS);
5222
5223 return mask;
5224 }
5225
5226 static unsigned long
5227 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5228 struct intel_crtc_state *crtc_state)
5229 {
5230 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5232 enum intel_display_power_domain domain;
5233 unsigned long domains, new_domains, old_domains;
5234
5235 old_domains = intel_crtc->enabled_power_domains;
5236 intel_crtc->enabled_power_domains = new_domains =
5237 get_crtc_power_domains(crtc, crtc_state);
5238
5239 domains = new_domains & ~old_domains;
5240
5241 for_each_power_domain(domain, domains)
5242 intel_display_power_get(dev_priv, domain);
5243
5244 return old_domains & ~new_domains;
5245 }
5246
5247 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5248 unsigned long domains)
5249 {
5250 enum intel_display_power_domain domain;
5251
5252 for_each_power_domain(domain, domains)
5253 intel_display_power_put(dev_priv, domain);
5254 }
5255
5256 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5257 {
5258 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5259
5260 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5261 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5262 return max_cdclk_freq;
5263 else if (IS_CHERRYVIEW(dev_priv))
5264 return max_cdclk_freq*95/100;
5265 else if (INTEL_INFO(dev_priv)->gen < 4)
5266 return 2*max_cdclk_freq*90/100;
5267 else
5268 return max_cdclk_freq*90/100;
5269 }
5270
5271 static void intel_update_max_cdclk(struct drm_device *dev)
5272 {
5273 struct drm_i915_private *dev_priv = dev->dev_private;
5274
5275 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5276 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5277
5278 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5279 dev_priv->max_cdclk_freq = 675000;
5280 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5281 dev_priv->max_cdclk_freq = 540000;
5282 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5283 dev_priv->max_cdclk_freq = 450000;
5284 else
5285 dev_priv->max_cdclk_freq = 337500;
5286 } else if (IS_BROXTON(dev)) {
5287 dev_priv->max_cdclk_freq = 624000;
5288 } else if (IS_BROADWELL(dev)) {
5289 /*
5290 * FIXME with extra cooling we can allow
5291 * 540 MHz for ULX and 675 Mhz for ULT.
5292 * How can we know if extra cooling is
5293 * available? PCI ID, VTB, something else?
5294 */
5295 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5296 dev_priv->max_cdclk_freq = 450000;
5297 else if (IS_BDW_ULX(dev))
5298 dev_priv->max_cdclk_freq = 450000;
5299 else if (IS_BDW_ULT(dev))
5300 dev_priv->max_cdclk_freq = 540000;
5301 else
5302 dev_priv->max_cdclk_freq = 675000;
5303 } else if (IS_CHERRYVIEW(dev)) {
5304 dev_priv->max_cdclk_freq = 320000;
5305 } else if (IS_VALLEYVIEW(dev)) {
5306 dev_priv->max_cdclk_freq = 400000;
5307 } else {
5308 /* otherwise assume cdclk is fixed */
5309 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5310 }
5311
5312 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5313
5314 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5315 dev_priv->max_cdclk_freq);
5316
5317 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5318 dev_priv->max_dotclk_freq);
5319 }
5320
5321 static void intel_update_cdclk(struct drm_device *dev)
5322 {
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324
5325 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5326 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5327 dev_priv->cdclk_freq);
5328
5329 /*
5330 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5331 * Programmng [sic] note: bit[9:2] should be programmed to the number
5332 * of cdclk that generates 4MHz reference clock freq which is used to
5333 * generate GMBus clock. This will vary with the cdclk freq.
5334 */
5335 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5336 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5337
5338 if (dev_priv->max_cdclk_freq == 0)
5339 intel_update_max_cdclk(dev);
5340 }
5341
5342 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
5343 {
5344 uint32_t divider;
5345 uint32_t ratio;
5346 uint32_t current_freq;
5347 int ret;
5348
5349 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5350 switch (frequency) {
5351 case 144000:
5352 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5353 ratio = BXT_DE_PLL_RATIO(60);
5354 break;
5355 case 288000:
5356 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5357 ratio = BXT_DE_PLL_RATIO(60);
5358 break;
5359 case 384000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 576000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 624000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5369 ratio = BXT_DE_PLL_RATIO(65);
5370 break;
5371 case 19200:
5372 /*
5373 * Bypass frequency with DE PLL disabled. Init ratio, divider
5374 * to suppress GCC warning.
5375 */
5376 ratio = 0;
5377 divider = 0;
5378 break;
5379 default:
5380 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5381
5382 return;
5383 }
5384
5385 mutex_lock(&dev_priv->rps.hw_lock);
5386 /* Inform power controller of upcoming frequency change */
5387 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5388 0x80000000);
5389 mutex_unlock(&dev_priv->rps.hw_lock);
5390
5391 if (ret) {
5392 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5393 ret, frequency);
5394 return;
5395 }
5396
5397 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5398 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5399 current_freq = current_freq * 500 + 1000;
5400
5401 /*
5402 * DE PLL has to be disabled when
5403 * - setting to 19.2MHz (bypass, PLL isn't used)
5404 * - before setting to 624MHz (PLL needs toggling)
5405 * - before setting to any frequency from 624MHz (PLL needs toggling)
5406 */
5407 if (frequency == 19200 || frequency == 624000 ||
5408 current_freq == 624000) {
5409 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5410 /* Timeout 200us */
5411 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5412 1))
5413 DRM_ERROR("timout waiting for DE PLL unlock\n");
5414 }
5415
5416 if (frequency != 19200) {
5417 uint32_t val;
5418
5419 val = I915_READ(BXT_DE_PLL_CTL);
5420 val &= ~BXT_DE_PLL_RATIO_MASK;
5421 val |= ratio;
5422 I915_WRITE(BXT_DE_PLL_CTL, val);
5423
5424 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5425 /* Timeout 200us */
5426 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5427 DRM_ERROR("timeout waiting for DE PLL lock\n");
5428
5429 val = I915_READ(CDCLK_CTL);
5430 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5431 val |= divider;
5432 /*
5433 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5434 * enable otherwise.
5435 */
5436 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5437 if (frequency >= 500000)
5438 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5439
5440 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5441 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5442 val |= (frequency - 1000) / 500;
5443 I915_WRITE(CDCLK_CTL, val);
5444 }
5445
5446 mutex_lock(&dev_priv->rps.hw_lock);
5447 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5448 DIV_ROUND_UP(frequency, 25000));
5449 mutex_unlock(&dev_priv->rps.hw_lock);
5450
5451 if (ret) {
5452 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5453 ret, frequency);
5454 return;
5455 }
5456
5457 intel_update_cdclk(dev_priv->dev);
5458 }
5459
5460 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5461 {
5462 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5463 return false;
5464
5465 /* TODO: Check for a valid CDCLK rate */
5466
5467 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5468 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5469
5470 return false;
5471 }
5472
5473 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5474 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5475
5476 return false;
5477 }
5478
5479 return true;
5480 }
5481
5482 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5483 {
5484 return broxton_cdclk_is_enabled(dev_priv);
5485 }
5486
5487 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5488 {
5489 /* check if cd clock is enabled */
5490 if (broxton_cdclk_is_enabled(dev_priv)) {
5491 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5492 return;
5493 }
5494
5495 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5496
5497 /*
5498 * FIXME:
5499 * - The initial CDCLK needs to be read from VBT.
5500 * Need to make this change after VBT has changes for BXT.
5501 * - check if setting the max (or any) cdclk freq is really necessary
5502 * here, it belongs to modeset time
5503 */
5504 broxton_set_cdclk(dev_priv, 624000);
5505
5506 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5507 POSTING_READ(DBUF_CTL);
5508
5509 udelay(10);
5510
5511 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5512 DRM_ERROR("DBuf power enable timeout!\n");
5513 }
5514
5515 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5516 {
5517 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5518 POSTING_READ(DBUF_CTL);
5519
5520 udelay(10);
5521
5522 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5523 DRM_ERROR("DBuf power disable timeout!\n");
5524
5525 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5526 broxton_set_cdclk(dev_priv, 19200);
5527 }
5528
5529 static const struct skl_cdclk_entry {
5530 unsigned int freq;
5531 unsigned int vco;
5532 } skl_cdclk_frequencies[] = {
5533 { .freq = 308570, .vco = 8640 },
5534 { .freq = 337500, .vco = 8100 },
5535 { .freq = 432000, .vco = 8640 },
5536 { .freq = 450000, .vco = 8100 },
5537 { .freq = 540000, .vco = 8100 },
5538 { .freq = 617140, .vco = 8640 },
5539 { .freq = 675000, .vco = 8100 },
5540 };
5541
5542 static unsigned int skl_cdclk_decimal(unsigned int freq)
5543 {
5544 return (freq - 1000) / 500;
5545 }
5546
5547 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5548 {
5549 unsigned int i;
5550
5551 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5552 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5553
5554 if (e->freq == freq)
5555 return e->vco;
5556 }
5557
5558 return 8100;
5559 }
5560
5561 static void
5562 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5563 {
5564 unsigned int min_freq;
5565 u32 val;
5566
5567 /* select the minimum CDCLK before enabling DPLL 0 */
5568 val = I915_READ(CDCLK_CTL);
5569 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5570 val |= CDCLK_FREQ_337_308;
5571
5572 if (required_vco == 8640)
5573 min_freq = 308570;
5574 else
5575 min_freq = 337500;
5576
5577 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5578
5579 I915_WRITE(CDCLK_CTL, val);
5580 POSTING_READ(CDCLK_CTL);
5581
5582 /*
5583 * We always enable DPLL0 with the lowest link rate possible, but still
5584 * taking into account the VCO required to operate the eDP panel at the
5585 * desired frequency. The usual DP link rates operate with a VCO of
5586 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5587 * The modeset code is responsible for the selection of the exact link
5588 * rate later on, with the constraint of choosing a frequency that
5589 * works with required_vco.
5590 */
5591 val = I915_READ(DPLL_CTRL1);
5592
5593 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5594 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5595 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5596 if (required_vco == 8640)
5597 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5598 SKL_DPLL0);
5599 else
5600 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5601 SKL_DPLL0);
5602
5603 I915_WRITE(DPLL_CTRL1, val);
5604 POSTING_READ(DPLL_CTRL1);
5605
5606 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5607
5608 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5609 DRM_ERROR("DPLL0 not locked\n");
5610 }
5611
5612 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5613 {
5614 int ret;
5615 u32 val;
5616
5617 /* inform PCU we want to change CDCLK */
5618 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5619 mutex_lock(&dev_priv->rps.hw_lock);
5620 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5621 mutex_unlock(&dev_priv->rps.hw_lock);
5622
5623 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5624 }
5625
5626 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5627 {
5628 unsigned int i;
5629
5630 for (i = 0; i < 15; i++) {
5631 if (skl_cdclk_pcu_ready(dev_priv))
5632 return true;
5633 udelay(10);
5634 }
5635
5636 return false;
5637 }
5638
5639 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5640 {
5641 struct drm_device *dev = dev_priv->dev;
5642 u32 freq_select, pcu_ack;
5643
5644 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5645
5646 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5647 DRM_ERROR("failed to inform PCU about cdclk change\n");
5648 return;
5649 }
5650
5651 /* set CDCLK_CTL */
5652 switch(freq) {
5653 case 450000:
5654 case 432000:
5655 freq_select = CDCLK_FREQ_450_432;
5656 pcu_ack = 1;
5657 break;
5658 case 540000:
5659 freq_select = CDCLK_FREQ_540;
5660 pcu_ack = 2;
5661 break;
5662 case 308570:
5663 case 337500:
5664 default:
5665 freq_select = CDCLK_FREQ_337_308;
5666 pcu_ack = 0;
5667 break;
5668 case 617140:
5669 case 675000:
5670 freq_select = CDCLK_FREQ_675_617;
5671 pcu_ack = 3;
5672 break;
5673 }
5674
5675 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5676 POSTING_READ(CDCLK_CTL);
5677
5678 /* inform PCU of the change */
5679 mutex_lock(&dev_priv->rps.hw_lock);
5680 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5681 mutex_unlock(&dev_priv->rps.hw_lock);
5682
5683 intel_update_cdclk(dev);
5684 }
5685
5686 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5687 {
5688 /* disable DBUF power */
5689 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5690 POSTING_READ(DBUF_CTL);
5691
5692 udelay(10);
5693
5694 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5695 DRM_ERROR("DBuf power disable timeout\n");
5696
5697 /* disable DPLL0 */
5698 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5699 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5700 DRM_ERROR("Couldn't disable DPLL0\n");
5701 }
5702
5703 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5704 {
5705 unsigned int required_vco;
5706
5707 /* DPLL0 not enabled (happens on early BIOS versions) */
5708 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5709 /* enable DPLL0 */
5710 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5711 skl_dpll0_enable(dev_priv, required_vco);
5712 }
5713
5714 /* set CDCLK to the frequency the BIOS chose */
5715 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5716
5717 /* enable DBUF power */
5718 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5719 POSTING_READ(DBUF_CTL);
5720
5721 udelay(10);
5722
5723 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5724 DRM_ERROR("DBuf power enable timeout\n");
5725 }
5726
5727 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5728 {
5729 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5730 uint32_t cdctl = I915_READ(CDCLK_CTL);
5731 int freq = dev_priv->skl_boot_cdclk;
5732
5733 /*
5734 * check if the pre-os intialized the display
5735 * There is SWF18 scratchpad register defined which is set by the
5736 * pre-os which can be used by the OS drivers to check the status
5737 */
5738 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5739 goto sanitize;
5740
5741 /* Is PLL enabled and locked ? */
5742 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5743 goto sanitize;
5744
5745 /* DPLL okay; verify the cdclock
5746 *
5747 * Noticed in some instances that the freq selection is correct but
5748 * decimal part is programmed wrong from BIOS where pre-os does not
5749 * enable display. Verify the same as well.
5750 */
5751 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5752 /* All well; nothing to sanitize */
5753 return false;
5754 sanitize:
5755 /*
5756 * As of now initialize with max cdclk till
5757 * we get dynamic cdclk support
5758 * */
5759 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5760 skl_init_cdclk(dev_priv);
5761
5762 /* we did have to sanitize */
5763 return true;
5764 }
5765
5766 /* Adjust CDclk dividers to allow high res or save power if possible */
5767 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5768 {
5769 struct drm_i915_private *dev_priv = dev->dev_private;
5770 u32 val, cmd;
5771
5772 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5773 != dev_priv->cdclk_freq);
5774
5775 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5776 cmd = 2;
5777 else if (cdclk == 266667)
5778 cmd = 1;
5779 else
5780 cmd = 0;
5781
5782 mutex_lock(&dev_priv->rps.hw_lock);
5783 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5784 val &= ~DSPFREQGUAR_MASK;
5785 val |= (cmd << DSPFREQGUAR_SHIFT);
5786 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5787 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5788 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5789 50)) {
5790 DRM_ERROR("timed out waiting for CDclk change\n");
5791 }
5792 mutex_unlock(&dev_priv->rps.hw_lock);
5793
5794 mutex_lock(&dev_priv->sb_lock);
5795
5796 if (cdclk == 400000) {
5797 u32 divider;
5798
5799 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5800
5801 /* adjust cdclk divider */
5802 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5803 val &= ~CCK_FREQUENCY_VALUES;
5804 val |= divider;
5805 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5806
5807 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5808 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5809 50))
5810 DRM_ERROR("timed out waiting for CDclk change\n");
5811 }
5812
5813 /* adjust self-refresh exit latency value */
5814 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5815 val &= ~0x7f;
5816
5817 /*
5818 * For high bandwidth configs, we set a higher latency in the bunit
5819 * so that the core display fetch happens in time to avoid underruns.
5820 */
5821 if (cdclk == 400000)
5822 val |= 4500 / 250; /* 4.5 usec */
5823 else
5824 val |= 3000 / 250; /* 3.0 usec */
5825 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5826
5827 mutex_unlock(&dev_priv->sb_lock);
5828
5829 intel_update_cdclk(dev);
5830 }
5831
5832 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5833 {
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835 u32 val, cmd;
5836
5837 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5838 != dev_priv->cdclk_freq);
5839
5840 switch (cdclk) {
5841 case 333333:
5842 case 320000:
5843 case 266667:
5844 case 200000:
5845 break;
5846 default:
5847 MISSING_CASE(cdclk);
5848 return;
5849 }
5850
5851 /*
5852 * Specs are full of misinformation, but testing on actual
5853 * hardware has shown that we just need to write the desired
5854 * CCK divider into the Punit register.
5855 */
5856 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5857
5858 mutex_lock(&dev_priv->rps.hw_lock);
5859 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5860 val &= ~DSPFREQGUAR_MASK_CHV;
5861 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5862 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5863 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5864 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5865 50)) {
5866 DRM_ERROR("timed out waiting for CDclk change\n");
5867 }
5868 mutex_unlock(&dev_priv->rps.hw_lock);
5869
5870 intel_update_cdclk(dev);
5871 }
5872
5873 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5874 int max_pixclk)
5875 {
5876 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5877 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5878
5879 /*
5880 * Really only a few cases to deal with, as only 4 CDclks are supported:
5881 * 200MHz
5882 * 267MHz
5883 * 320/333MHz (depends on HPLL freq)
5884 * 400MHz (VLV only)
5885 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5886 * of the lower bin and adjust if needed.
5887 *
5888 * We seem to get an unstable or solid color picture at 200MHz.
5889 * Not sure what's wrong. For now use 200MHz only when all pipes
5890 * are off.
5891 */
5892 if (!IS_CHERRYVIEW(dev_priv) &&
5893 max_pixclk > freq_320*limit/100)
5894 return 400000;
5895 else if (max_pixclk > 266667*limit/100)
5896 return freq_320;
5897 else if (max_pixclk > 0)
5898 return 266667;
5899 else
5900 return 200000;
5901 }
5902
5903 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5904 int max_pixclk)
5905 {
5906 /*
5907 * FIXME:
5908 * - remove the guardband, it's not needed on BXT
5909 * - set 19.2MHz bypass frequency if there are no active pipes
5910 */
5911 if (max_pixclk > 576000*9/10)
5912 return 624000;
5913 else if (max_pixclk > 384000*9/10)
5914 return 576000;
5915 else if (max_pixclk > 288000*9/10)
5916 return 384000;
5917 else if (max_pixclk > 144000*9/10)
5918 return 288000;
5919 else
5920 return 144000;
5921 }
5922
5923 /* Compute the max pixel clock for new configuration. */
5924 static int intel_mode_max_pixclk(struct drm_device *dev,
5925 struct drm_atomic_state *state)
5926 {
5927 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929 struct drm_crtc *crtc;
5930 struct drm_crtc_state *crtc_state;
5931 unsigned max_pixclk = 0, i;
5932 enum pipe pipe;
5933
5934 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5935 sizeof(intel_state->min_pixclk));
5936
5937 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5938 int pixclk = 0;
5939
5940 if (crtc_state->enable)
5941 pixclk = crtc_state->adjusted_mode.crtc_clock;
5942
5943 intel_state->min_pixclk[i] = pixclk;
5944 }
5945
5946 for_each_pipe(dev_priv, pipe)
5947 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5948
5949 return max_pixclk;
5950 }
5951
5952 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5953 {
5954 struct drm_device *dev = state->dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 int max_pixclk = intel_mode_max_pixclk(dev, state);
5957 struct intel_atomic_state *intel_state =
5958 to_intel_atomic_state(state);
5959
5960 if (max_pixclk < 0)
5961 return max_pixclk;
5962
5963 intel_state->cdclk = intel_state->dev_cdclk =
5964 valleyview_calc_cdclk(dev_priv, max_pixclk);
5965
5966 if (!intel_state->active_crtcs)
5967 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5968
5969 return 0;
5970 }
5971
5972 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5973 {
5974 struct drm_device *dev = state->dev;
5975 struct drm_i915_private *dev_priv = dev->dev_private;
5976 int max_pixclk = intel_mode_max_pixclk(dev, state);
5977 struct intel_atomic_state *intel_state =
5978 to_intel_atomic_state(state);
5979
5980 if (max_pixclk < 0)
5981 return max_pixclk;
5982
5983 intel_state->cdclk = intel_state->dev_cdclk =
5984 broxton_calc_cdclk(dev_priv, max_pixclk);
5985
5986 if (!intel_state->active_crtcs)
5987 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5988
5989 return 0;
5990 }
5991
5992 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5993 {
5994 unsigned int credits, default_credits;
5995
5996 if (IS_CHERRYVIEW(dev_priv))
5997 default_credits = PFI_CREDIT(12);
5998 else
5999 default_credits = PFI_CREDIT(8);
6000
6001 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6002 /* CHV suggested value is 31 or 63 */
6003 if (IS_CHERRYVIEW(dev_priv))
6004 credits = PFI_CREDIT_63;
6005 else
6006 credits = PFI_CREDIT(15);
6007 } else {
6008 credits = default_credits;
6009 }
6010
6011 /*
6012 * WA - write default credits before re-programming
6013 * FIXME: should we also set the resend bit here?
6014 */
6015 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6016 default_credits);
6017
6018 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6019 credits | PFI_CREDIT_RESEND);
6020
6021 /*
6022 * FIXME is this guaranteed to clear
6023 * immediately or should we poll for it?
6024 */
6025 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6026 }
6027
6028 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6029 {
6030 struct drm_device *dev = old_state->dev;
6031 struct drm_i915_private *dev_priv = dev->dev_private;
6032 struct intel_atomic_state *old_intel_state =
6033 to_intel_atomic_state(old_state);
6034 unsigned req_cdclk = old_intel_state->dev_cdclk;
6035
6036 /*
6037 * FIXME: We can end up here with all power domains off, yet
6038 * with a CDCLK frequency other than the minimum. To account
6039 * for this take the PIPE-A power domain, which covers the HW
6040 * blocks needed for the following programming. This can be
6041 * removed once it's guaranteed that we get here either with
6042 * the minimum CDCLK set, or the required power domains
6043 * enabled.
6044 */
6045 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6046
6047 if (IS_CHERRYVIEW(dev))
6048 cherryview_set_cdclk(dev, req_cdclk);
6049 else
6050 valleyview_set_cdclk(dev, req_cdclk);
6051
6052 vlv_program_pfi_credits(dev_priv);
6053
6054 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6055 }
6056
6057 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6058 {
6059 struct drm_device *dev = crtc->dev;
6060 struct drm_i915_private *dev_priv = to_i915(dev);
6061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6062 struct intel_encoder *encoder;
6063 struct intel_crtc_state *pipe_config =
6064 to_intel_crtc_state(crtc->state);
6065 int pipe = intel_crtc->pipe;
6066
6067 if (WARN_ON(intel_crtc->active))
6068 return;
6069
6070 if (intel_crtc->config->has_dp_encoder)
6071 intel_dp_set_m_n(intel_crtc, M1_N1);
6072
6073 intel_set_pipe_timings(intel_crtc);
6074 intel_set_pipe_src_size(intel_crtc);
6075
6076 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6077 struct drm_i915_private *dev_priv = dev->dev_private;
6078
6079 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6080 I915_WRITE(CHV_CANVAS(pipe), 0);
6081 }
6082
6083 i9xx_set_pipeconf(intel_crtc);
6084
6085 intel_crtc->active = true;
6086
6087 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6088
6089 for_each_encoder_on_crtc(dev, crtc, encoder)
6090 if (encoder->pre_pll_enable)
6091 encoder->pre_pll_enable(encoder);
6092
6093 if (IS_CHERRYVIEW(dev)) {
6094 chv_prepare_pll(intel_crtc, intel_crtc->config);
6095 chv_enable_pll(intel_crtc, intel_crtc->config);
6096 } else {
6097 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6098 vlv_enable_pll(intel_crtc, intel_crtc->config);
6099 }
6100
6101 for_each_encoder_on_crtc(dev, crtc, encoder)
6102 if (encoder->pre_enable)
6103 encoder->pre_enable(encoder);
6104
6105 i9xx_pfit_enable(intel_crtc);
6106
6107 intel_color_load_luts(&pipe_config->base);
6108
6109 intel_update_watermarks(crtc);
6110 intel_enable_pipe(intel_crtc);
6111
6112 assert_vblank_disabled(crtc);
6113 drm_crtc_vblank_on(crtc);
6114
6115 for_each_encoder_on_crtc(dev, crtc, encoder)
6116 encoder->enable(encoder);
6117 }
6118
6119 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6120 {
6121 struct drm_device *dev = crtc->base.dev;
6122 struct drm_i915_private *dev_priv = dev->dev_private;
6123
6124 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6125 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6126 }
6127
6128 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6129 {
6130 struct drm_device *dev = crtc->dev;
6131 struct drm_i915_private *dev_priv = to_i915(dev);
6132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133 struct intel_encoder *encoder;
6134 struct intel_crtc_state *pipe_config =
6135 to_intel_crtc_state(crtc->state);
6136 enum pipe pipe = intel_crtc->pipe;
6137
6138 if (WARN_ON(intel_crtc->active))
6139 return;
6140
6141 i9xx_set_pll_dividers(intel_crtc);
6142
6143 if (intel_crtc->config->has_dp_encoder)
6144 intel_dp_set_m_n(intel_crtc, M1_N1);
6145
6146 intel_set_pipe_timings(intel_crtc);
6147 intel_set_pipe_src_size(intel_crtc);
6148
6149 i9xx_set_pipeconf(intel_crtc);
6150
6151 intel_crtc->active = true;
6152
6153 if (!IS_GEN2(dev))
6154 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6155
6156 for_each_encoder_on_crtc(dev, crtc, encoder)
6157 if (encoder->pre_enable)
6158 encoder->pre_enable(encoder);
6159
6160 i9xx_enable_pll(intel_crtc);
6161
6162 i9xx_pfit_enable(intel_crtc);
6163
6164 intel_color_load_luts(&pipe_config->base);
6165
6166 intel_update_watermarks(crtc);
6167 intel_enable_pipe(intel_crtc);
6168
6169 assert_vblank_disabled(crtc);
6170 drm_crtc_vblank_on(crtc);
6171
6172 for_each_encoder_on_crtc(dev, crtc, encoder)
6173 encoder->enable(encoder);
6174 }
6175
6176 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6177 {
6178 struct drm_device *dev = crtc->base.dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6180
6181 if (!crtc->config->gmch_pfit.control)
6182 return;
6183
6184 assert_pipe_disabled(dev_priv, crtc->pipe);
6185
6186 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6187 I915_READ(PFIT_CONTROL));
6188 I915_WRITE(PFIT_CONTROL, 0);
6189 }
6190
6191 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6192 {
6193 struct drm_device *dev = crtc->dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 struct intel_encoder *encoder;
6197 int pipe = intel_crtc->pipe;
6198
6199 /*
6200 * On gen2 planes are double buffered but the pipe isn't, so we must
6201 * wait for planes to fully turn off before disabling the pipe.
6202 */
6203 if (IS_GEN2(dev))
6204 intel_wait_for_vblank(dev, pipe);
6205
6206 for_each_encoder_on_crtc(dev, crtc, encoder)
6207 encoder->disable(encoder);
6208
6209 drm_crtc_vblank_off(crtc);
6210 assert_vblank_disabled(crtc);
6211
6212 intel_disable_pipe(intel_crtc);
6213
6214 i9xx_pfit_disable(intel_crtc);
6215
6216 for_each_encoder_on_crtc(dev, crtc, encoder)
6217 if (encoder->post_disable)
6218 encoder->post_disable(encoder);
6219
6220 if (!intel_crtc->config->has_dsi_encoder) {
6221 if (IS_CHERRYVIEW(dev))
6222 chv_disable_pll(dev_priv, pipe);
6223 else if (IS_VALLEYVIEW(dev))
6224 vlv_disable_pll(dev_priv, pipe);
6225 else
6226 i9xx_disable_pll(intel_crtc);
6227 }
6228
6229 for_each_encoder_on_crtc(dev, crtc, encoder)
6230 if (encoder->post_pll_disable)
6231 encoder->post_pll_disable(encoder);
6232
6233 if (!IS_GEN2(dev))
6234 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6235 }
6236
6237 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6238 {
6239 struct intel_encoder *encoder;
6240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6241 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6242 enum intel_display_power_domain domain;
6243 unsigned long domains;
6244
6245 if (!intel_crtc->active)
6246 return;
6247
6248 if (to_intel_plane_state(crtc->primary->state)->visible) {
6249 WARN_ON(intel_crtc->unpin_work);
6250
6251 intel_pre_disable_primary_noatomic(crtc);
6252
6253 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6254 to_intel_plane_state(crtc->primary->state)->visible = false;
6255 }
6256
6257 dev_priv->display.crtc_disable(crtc);
6258
6259 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6260 crtc->base.id);
6261
6262 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6263 crtc->state->active = false;
6264 intel_crtc->active = false;
6265 crtc->enabled = false;
6266 crtc->state->connector_mask = 0;
6267 crtc->state->encoder_mask = 0;
6268
6269 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6270 encoder->base.crtc = NULL;
6271
6272 intel_fbc_disable(intel_crtc);
6273 intel_update_watermarks(crtc);
6274 intel_disable_shared_dpll(intel_crtc);
6275
6276 domains = intel_crtc->enabled_power_domains;
6277 for_each_power_domain(domain, domains)
6278 intel_display_power_put(dev_priv, domain);
6279 intel_crtc->enabled_power_domains = 0;
6280
6281 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6282 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6283 }
6284
6285 /*
6286 * turn all crtc's off, but do not adjust state
6287 * This has to be paired with a call to intel_modeset_setup_hw_state.
6288 */
6289 int intel_display_suspend(struct drm_device *dev)
6290 {
6291 struct drm_i915_private *dev_priv = to_i915(dev);
6292 struct drm_atomic_state *state;
6293 int ret;
6294
6295 state = drm_atomic_helper_suspend(dev);
6296 ret = PTR_ERR_OR_ZERO(state);
6297 if (ret)
6298 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6299 else
6300 dev_priv->modeset_restore_state = state;
6301 return ret;
6302 }
6303
6304 void intel_encoder_destroy(struct drm_encoder *encoder)
6305 {
6306 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6307
6308 drm_encoder_cleanup(encoder);
6309 kfree(intel_encoder);
6310 }
6311
6312 /* Cross check the actual hw state with our own modeset state tracking (and it's
6313 * internal consistency). */
6314 static void intel_connector_verify_state(struct intel_connector *connector)
6315 {
6316 struct drm_crtc *crtc = connector->base.state->crtc;
6317
6318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6319 connector->base.base.id,
6320 connector->base.name);
6321
6322 if (connector->get_hw_state(connector)) {
6323 struct intel_encoder *encoder = connector->encoder;
6324 struct drm_connector_state *conn_state = connector->base.state;
6325
6326 I915_STATE_WARN(!crtc,
6327 "connector enabled without attached crtc\n");
6328
6329 if (!crtc)
6330 return;
6331
6332 I915_STATE_WARN(!crtc->state->active,
6333 "connector is active, but attached crtc isn't\n");
6334
6335 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6336 return;
6337
6338 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6339 "atomic encoder doesn't match attached encoder\n");
6340
6341 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6342 "attached encoder crtc differs from connector crtc\n");
6343 } else {
6344 I915_STATE_WARN(crtc && crtc->state->active,
6345 "attached crtc is active, but connector isn't\n");
6346 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6347 "best encoder set without crtc!\n");
6348 }
6349 }
6350
6351 int intel_connector_init(struct intel_connector *connector)
6352 {
6353 drm_atomic_helper_connector_reset(&connector->base);
6354
6355 if (!connector->base.state)
6356 return -ENOMEM;
6357
6358 return 0;
6359 }
6360
6361 struct intel_connector *intel_connector_alloc(void)
6362 {
6363 struct intel_connector *connector;
6364
6365 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6366 if (!connector)
6367 return NULL;
6368
6369 if (intel_connector_init(connector) < 0) {
6370 kfree(connector);
6371 return NULL;
6372 }
6373
6374 return connector;
6375 }
6376
6377 /* Simple connector->get_hw_state implementation for encoders that support only
6378 * one connector and no cloning and hence the encoder state determines the state
6379 * of the connector. */
6380 bool intel_connector_get_hw_state(struct intel_connector *connector)
6381 {
6382 enum pipe pipe = 0;
6383 struct intel_encoder *encoder = connector->encoder;
6384
6385 return encoder->get_hw_state(encoder, &pipe);
6386 }
6387
6388 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6389 {
6390 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6391 return crtc_state->fdi_lanes;
6392
6393 return 0;
6394 }
6395
6396 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6397 struct intel_crtc_state *pipe_config)
6398 {
6399 struct drm_atomic_state *state = pipe_config->base.state;
6400 struct intel_crtc *other_crtc;
6401 struct intel_crtc_state *other_crtc_state;
6402
6403 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6404 pipe_name(pipe), pipe_config->fdi_lanes);
6405 if (pipe_config->fdi_lanes > 4) {
6406 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6407 pipe_name(pipe), pipe_config->fdi_lanes);
6408 return -EINVAL;
6409 }
6410
6411 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6412 if (pipe_config->fdi_lanes > 2) {
6413 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6414 pipe_config->fdi_lanes);
6415 return -EINVAL;
6416 } else {
6417 return 0;
6418 }
6419 }
6420
6421 if (INTEL_INFO(dev)->num_pipes == 2)
6422 return 0;
6423
6424 /* Ivybridge 3 pipe is really complicated */
6425 switch (pipe) {
6426 case PIPE_A:
6427 return 0;
6428 case PIPE_B:
6429 if (pipe_config->fdi_lanes <= 2)
6430 return 0;
6431
6432 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6433 other_crtc_state =
6434 intel_atomic_get_crtc_state(state, other_crtc);
6435 if (IS_ERR(other_crtc_state))
6436 return PTR_ERR(other_crtc_state);
6437
6438 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6439 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6440 pipe_name(pipe), pipe_config->fdi_lanes);
6441 return -EINVAL;
6442 }
6443 return 0;
6444 case PIPE_C:
6445 if (pipe_config->fdi_lanes > 2) {
6446 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6447 pipe_name(pipe), pipe_config->fdi_lanes);
6448 return -EINVAL;
6449 }
6450
6451 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6452 other_crtc_state =
6453 intel_atomic_get_crtc_state(state, other_crtc);
6454 if (IS_ERR(other_crtc_state))
6455 return PTR_ERR(other_crtc_state);
6456
6457 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6458 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6459 return -EINVAL;
6460 }
6461 return 0;
6462 default:
6463 BUG();
6464 }
6465 }
6466
6467 #define RETRY 1
6468 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6469 struct intel_crtc_state *pipe_config)
6470 {
6471 struct drm_device *dev = intel_crtc->base.dev;
6472 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6473 int lane, link_bw, fdi_dotclock, ret;
6474 bool needs_recompute = false;
6475
6476 retry:
6477 /* FDI is a binary signal running at ~2.7GHz, encoding
6478 * each output octet as 10 bits. The actual frequency
6479 * is stored as a divider into a 100MHz clock, and the
6480 * mode pixel clock is stored in units of 1KHz.
6481 * Hence the bw of each lane in terms of the mode signal
6482 * is:
6483 */
6484 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6485
6486 fdi_dotclock = adjusted_mode->crtc_clock;
6487
6488 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6489 pipe_config->pipe_bpp);
6490
6491 pipe_config->fdi_lanes = lane;
6492
6493 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6494 link_bw, &pipe_config->fdi_m_n);
6495
6496 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6497 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6498 pipe_config->pipe_bpp -= 2*3;
6499 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6500 pipe_config->pipe_bpp);
6501 needs_recompute = true;
6502 pipe_config->bw_constrained = true;
6503
6504 goto retry;
6505 }
6506
6507 if (needs_recompute)
6508 return RETRY;
6509
6510 return ret;
6511 }
6512
6513 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6514 struct intel_crtc_state *pipe_config)
6515 {
6516 if (pipe_config->pipe_bpp > 24)
6517 return false;
6518
6519 /* HSW can handle pixel rate up to cdclk? */
6520 if (IS_HASWELL(dev_priv))
6521 return true;
6522
6523 /*
6524 * We compare against max which means we must take
6525 * the increased cdclk requirement into account when
6526 * calculating the new cdclk.
6527 *
6528 * Should measure whether using a lower cdclk w/o IPS
6529 */
6530 return ilk_pipe_pixel_rate(pipe_config) <=
6531 dev_priv->max_cdclk_freq * 95 / 100;
6532 }
6533
6534 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6535 struct intel_crtc_state *pipe_config)
6536 {
6537 struct drm_device *dev = crtc->base.dev;
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539
6540 pipe_config->ips_enabled = i915.enable_ips &&
6541 hsw_crtc_supports_ips(crtc) &&
6542 pipe_config_supports_ips(dev_priv, pipe_config);
6543 }
6544
6545 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6546 {
6547 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6548
6549 /* GDG double wide on either pipe, otherwise pipe A only */
6550 return INTEL_INFO(dev_priv)->gen < 4 &&
6551 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6552 }
6553
6554 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6555 struct intel_crtc_state *pipe_config)
6556 {
6557 struct drm_device *dev = crtc->base.dev;
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6560
6561 /* FIXME should check pixel clock limits on all platforms */
6562 if (INTEL_INFO(dev)->gen < 4) {
6563 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6564
6565 /*
6566 * Enable double wide mode when the dot clock
6567 * is > 90% of the (display) core speed.
6568 */
6569 if (intel_crtc_supports_double_wide(crtc) &&
6570 adjusted_mode->crtc_clock > clock_limit) {
6571 clock_limit *= 2;
6572 pipe_config->double_wide = true;
6573 }
6574
6575 if (adjusted_mode->crtc_clock > clock_limit) {
6576 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6577 adjusted_mode->crtc_clock, clock_limit,
6578 yesno(pipe_config->double_wide));
6579 return -EINVAL;
6580 }
6581 }
6582
6583 /*
6584 * Pipe horizontal size must be even in:
6585 * - DVO ganged mode
6586 * - LVDS dual channel mode
6587 * - Double wide pipe
6588 */
6589 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6590 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6591 pipe_config->pipe_src_w &= ~1;
6592
6593 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6594 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6595 */
6596 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6597 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6598 return -EINVAL;
6599
6600 if (HAS_IPS(dev))
6601 hsw_compute_ips_config(crtc, pipe_config);
6602
6603 if (pipe_config->has_pch_encoder)
6604 return ironlake_fdi_compute_config(crtc, pipe_config);
6605
6606 return 0;
6607 }
6608
6609 static int skylake_get_display_clock_speed(struct drm_device *dev)
6610 {
6611 struct drm_i915_private *dev_priv = to_i915(dev);
6612 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6613 uint32_t cdctl = I915_READ(CDCLK_CTL);
6614 uint32_t linkrate;
6615
6616 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6617 return 24000; /* 24MHz is the cd freq with NSSC ref */
6618
6619 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6620 return 540000;
6621
6622 linkrate = (I915_READ(DPLL_CTRL1) &
6623 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6624
6625 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6626 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6627 /* vco 8640 */
6628 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6629 case CDCLK_FREQ_450_432:
6630 return 432000;
6631 case CDCLK_FREQ_337_308:
6632 return 308570;
6633 case CDCLK_FREQ_675_617:
6634 return 617140;
6635 default:
6636 WARN(1, "Unknown cd freq selection\n");
6637 }
6638 } else {
6639 /* vco 8100 */
6640 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6641 case CDCLK_FREQ_450_432:
6642 return 450000;
6643 case CDCLK_FREQ_337_308:
6644 return 337500;
6645 case CDCLK_FREQ_675_617:
6646 return 675000;
6647 default:
6648 WARN(1, "Unknown cd freq selection\n");
6649 }
6650 }
6651
6652 /* error case, do as if DPLL0 isn't enabled */
6653 return 24000;
6654 }
6655
6656 static int broxton_get_display_clock_speed(struct drm_device *dev)
6657 {
6658 struct drm_i915_private *dev_priv = to_i915(dev);
6659 uint32_t cdctl = I915_READ(CDCLK_CTL);
6660 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6661 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6662 int cdclk;
6663
6664 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6665 return 19200;
6666
6667 cdclk = 19200 * pll_ratio / 2;
6668
6669 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6670 case BXT_CDCLK_CD2X_DIV_SEL_1:
6671 return cdclk; /* 576MHz or 624MHz */
6672 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6673 return cdclk * 2 / 3; /* 384MHz */
6674 case BXT_CDCLK_CD2X_DIV_SEL_2:
6675 return cdclk / 2; /* 288MHz */
6676 case BXT_CDCLK_CD2X_DIV_SEL_4:
6677 return cdclk / 4; /* 144MHz */
6678 }
6679
6680 /* error case, do as if DE PLL isn't enabled */
6681 return 19200;
6682 }
6683
6684 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6685 {
6686 struct drm_i915_private *dev_priv = dev->dev_private;
6687 uint32_t lcpll = I915_READ(LCPLL_CTL);
6688 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6689
6690 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6691 return 800000;
6692 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6693 return 450000;
6694 else if (freq == LCPLL_CLK_FREQ_450)
6695 return 450000;
6696 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6697 return 540000;
6698 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6699 return 337500;
6700 else
6701 return 675000;
6702 }
6703
6704 static int haswell_get_display_clock_speed(struct drm_device *dev)
6705 {
6706 struct drm_i915_private *dev_priv = dev->dev_private;
6707 uint32_t lcpll = I915_READ(LCPLL_CTL);
6708 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6709
6710 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6711 return 800000;
6712 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6713 return 450000;
6714 else if (freq == LCPLL_CLK_FREQ_450)
6715 return 450000;
6716 else if (IS_HSW_ULT(dev))
6717 return 337500;
6718 else
6719 return 540000;
6720 }
6721
6722 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6723 {
6724 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6725 CCK_DISPLAY_CLOCK_CONTROL);
6726 }
6727
6728 static int ilk_get_display_clock_speed(struct drm_device *dev)
6729 {
6730 return 450000;
6731 }
6732
6733 static int i945_get_display_clock_speed(struct drm_device *dev)
6734 {
6735 return 400000;
6736 }
6737
6738 static int i915_get_display_clock_speed(struct drm_device *dev)
6739 {
6740 return 333333;
6741 }
6742
6743 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6744 {
6745 return 200000;
6746 }
6747
6748 static int pnv_get_display_clock_speed(struct drm_device *dev)
6749 {
6750 u16 gcfgc = 0;
6751
6752 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6753
6754 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6755 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6756 return 266667;
6757 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6758 return 333333;
6759 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6760 return 444444;
6761 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6762 return 200000;
6763 default:
6764 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6765 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6766 return 133333;
6767 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6768 return 166667;
6769 }
6770 }
6771
6772 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6773 {
6774 u16 gcfgc = 0;
6775
6776 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6777
6778 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6779 return 133333;
6780 else {
6781 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6782 case GC_DISPLAY_CLOCK_333_MHZ:
6783 return 333333;
6784 default:
6785 case GC_DISPLAY_CLOCK_190_200_MHZ:
6786 return 190000;
6787 }
6788 }
6789 }
6790
6791 static int i865_get_display_clock_speed(struct drm_device *dev)
6792 {
6793 return 266667;
6794 }
6795
6796 static int i85x_get_display_clock_speed(struct drm_device *dev)
6797 {
6798 u16 hpllcc = 0;
6799
6800 /*
6801 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6802 * encoding is different :(
6803 * FIXME is this the right way to detect 852GM/852GMV?
6804 */
6805 if (dev->pdev->revision == 0x1)
6806 return 133333;
6807
6808 pci_bus_read_config_word(dev->pdev->bus,
6809 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6810
6811 /* Assume that the hardware is in the high speed state. This
6812 * should be the default.
6813 */
6814 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6815 case GC_CLOCK_133_200:
6816 case GC_CLOCK_133_200_2:
6817 case GC_CLOCK_100_200:
6818 return 200000;
6819 case GC_CLOCK_166_250:
6820 return 250000;
6821 case GC_CLOCK_100_133:
6822 return 133333;
6823 case GC_CLOCK_133_266:
6824 case GC_CLOCK_133_266_2:
6825 case GC_CLOCK_166_266:
6826 return 266667;
6827 }
6828
6829 /* Shouldn't happen */
6830 return 0;
6831 }
6832
6833 static int i830_get_display_clock_speed(struct drm_device *dev)
6834 {
6835 return 133333;
6836 }
6837
6838 static unsigned int intel_hpll_vco(struct drm_device *dev)
6839 {
6840 struct drm_i915_private *dev_priv = dev->dev_private;
6841 static const unsigned int blb_vco[8] = {
6842 [0] = 3200000,
6843 [1] = 4000000,
6844 [2] = 5333333,
6845 [3] = 4800000,
6846 [4] = 6400000,
6847 };
6848 static const unsigned int pnv_vco[8] = {
6849 [0] = 3200000,
6850 [1] = 4000000,
6851 [2] = 5333333,
6852 [3] = 4800000,
6853 [4] = 2666667,
6854 };
6855 static const unsigned int cl_vco[8] = {
6856 [0] = 3200000,
6857 [1] = 4000000,
6858 [2] = 5333333,
6859 [3] = 6400000,
6860 [4] = 3333333,
6861 [5] = 3566667,
6862 [6] = 4266667,
6863 };
6864 static const unsigned int elk_vco[8] = {
6865 [0] = 3200000,
6866 [1] = 4000000,
6867 [2] = 5333333,
6868 [3] = 4800000,
6869 };
6870 static const unsigned int ctg_vco[8] = {
6871 [0] = 3200000,
6872 [1] = 4000000,
6873 [2] = 5333333,
6874 [3] = 6400000,
6875 [4] = 2666667,
6876 [5] = 4266667,
6877 };
6878 const unsigned int *vco_table;
6879 unsigned int vco;
6880 uint8_t tmp = 0;
6881
6882 /* FIXME other chipsets? */
6883 if (IS_GM45(dev))
6884 vco_table = ctg_vco;
6885 else if (IS_G4X(dev))
6886 vco_table = elk_vco;
6887 else if (IS_CRESTLINE(dev))
6888 vco_table = cl_vco;
6889 else if (IS_PINEVIEW(dev))
6890 vco_table = pnv_vco;
6891 else if (IS_G33(dev))
6892 vco_table = blb_vco;
6893 else
6894 return 0;
6895
6896 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6897
6898 vco = vco_table[tmp & 0x7];
6899 if (vco == 0)
6900 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6901 else
6902 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6903
6904 return vco;
6905 }
6906
6907 static int gm45_get_display_clock_speed(struct drm_device *dev)
6908 {
6909 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6910 uint16_t tmp = 0;
6911
6912 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6913
6914 cdclk_sel = (tmp >> 12) & 0x1;
6915
6916 switch (vco) {
6917 case 2666667:
6918 case 4000000:
6919 case 5333333:
6920 return cdclk_sel ? 333333 : 222222;
6921 case 3200000:
6922 return cdclk_sel ? 320000 : 228571;
6923 default:
6924 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6925 return 222222;
6926 }
6927 }
6928
6929 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6930 {
6931 static const uint8_t div_3200[] = { 16, 10, 8 };
6932 static const uint8_t div_4000[] = { 20, 12, 10 };
6933 static const uint8_t div_5333[] = { 24, 16, 14 };
6934 const uint8_t *div_table;
6935 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6936 uint16_t tmp = 0;
6937
6938 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6939
6940 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6941
6942 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6943 goto fail;
6944
6945 switch (vco) {
6946 case 3200000:
6947 div_table = div_3200;
6948 break;
6949 case 4000000:
6950 div_table = div_4000;
6951 break;
6952 case 5333333:
6953 div_table = div_5333;
6954 break;
6955 default:
6956 goto fail;
6957 }
6958
6959 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6960
6961 fail:
6962 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6963 return 200000;
6964 }
6965
6966 static int g33_get_display_clock_speed(struct drm_device *dev)
6967 {
6968 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6969 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6970 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6971 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6972 const uint8_t *div_table;
6973 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6974 uint16_t tmp = 0;
6975
6976 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6977
6978 cdclk_sel = (tmp >> 4) & 0x7;
6979
6980 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6981 goto fail;
6982
6983 switch (vco) {
6984 case 3200000:
6985 div_table = div_3200;
6986 break;
6987 case 4000000:
6988 div_table = div_4000;
6989 break;
6990 case 4800000:
6991 div_table = div_4800;
6992 break;
6993 case 5333333:
6994 div_table = div_5333;
6995 break;
6996 default:
6997 goto fail;
6998 }
6999
7000 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7001
7002 fail:
7003 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7004 return 190476;
7005 }
7006
7007 static void
7008 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7009 {
7010 while (*num > DATA_LINK_M_N_MASK ||
7011 *den > DATA_LINK_M_N_MASK) {
7012 *num >>= 1;
7013 *den >>= 1;
7014 }
7015 }
7016
7017 static void compute_m_n(unsigned int m, unsigned int n,
7018 uint32_t *ret_m, uint32_t *ret_n)
7019 {
7020 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7021 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7022 intel_reduce_m_n_ratio(ret_m, ret_n);
7023 }
7024
7025 void
7026 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7027 int pixel_clock, int link_clock,
7028 struct intel_link_m_n *m_n)
7029 {
7030 m_n->tu = 64;
7031
7032 compute_m_n(bits_per_pixel * pixel_clock,
7033 link_clock * nlanes * 8,
7034 &m_n->gmch_m, &m_n->gmch_n);
7035
7036 compute_m_n(pixel_clock, link_clock,
7037 &m_n->link_m, &m_n->link_n);
7038 }
7039
7040 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7041 {
7042 if (i915.panel_use_ssc >= 0)
7043 return i915.panel_use_ssc != 0;
7044 return dev_priv->vbt.lvds_use_ssc
7045 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7046 }
7047
7048 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7049 {
7050 return (1 << dpll->n) << 16 | dpll->m2;
7051 }
7052
7053 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7054 {
7055 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7056 }
7057
7058 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7059 struct intel_crtc_state *crtc_state,
7060 struct dpll *reduced_clock)
7061 {
7062 struct drm_device *dev = crtc->base.dev;
7063 u32 fp, fp2 = 0;
7064
7065 if (IS_PINEVIEW(dev)) {
7066 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7067 if (reduced_clock)
7068 fp2 = pnv_dpll_compute_fp(reduced_clock);
7069 } else {
7070 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7071 if (reduced_clock)
7072 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7073 }
7074
7075 crtc_state->dpll_hw_state.fp0 = fp;
7076
7077 crtc->lowfreq_avail = false;
7078 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7079 reduced_clock) {
7080 crtc_state->dpll_hw_state.fp1 = fp2;
7081 crtc->lowfreq_avail = true;
7082 } else {
7083 crtc_state->dpll_hw_state.fp1 = fp;
7084 }
7085 }
7086
7087 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7088 pipe)
7089 {
7090 u32 reg_val;
7091
7092 /*
7093 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7094 * and set it to a reasonable value instead.
7095 */
7096 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7097 reg_val &= 0xffffff00;
7098 reg_val |= 0x00000030;
7099 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7100
7101 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7102 reg_val &= 0x8cffffff;
7103 reg_val = 0x8c000000;
7104 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7105
7106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7107 reg_val &= 0xffffff00;
7108 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7109
7110 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7111 reg_val &= 0x00ffffff;
7112 reg_val |= 0xb0000000;
7113 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7114 }
7115
7116 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7117 struct intel_link_m_n *m_n)
7118 {
7119 struct drm_device *dev = crtc->base.dev;
7120 struct drm_i915_private *dev_priv = dev->dev_private;
7121 int pipe = crtc->pipe;
7122
7123 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7124 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7125 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7126 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7127 }
7128
7129 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7130 struct intel_link_m_n *m_n,
7131 struct intel_link_m_n *m2_n2)
7132 {
7133 struct drm_device *dev = crtc->base.dev;
7134 struct drm_i915_private *dev_priv = dev->dev_private;
7135 int pipe = crtc->pipe;
7136 enum transcoder transcoder = crtc->config->cpu_transcoder;
7137
7138 if (INTEL_INFO(dev)->gen >= 5) {
7139 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7140 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7141 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7142 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7143 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7144 * for gen < 8) and if DRRS is supported (to make sure the
7145 * registers are not unnecessarily accessed).
7146 */
7147 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7148 crtc->config->has_drrs) {
7149 I915_WRITE(PIPE_DATA_M2(transcoder),
7150 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7151 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7152 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7153 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7154 }
7155 } else {
7156 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7157 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7158 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7159 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7160 }
7161 }
7162
7163 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7164 {
7165 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7166
7167 if (m_n == M1_N1) {
7168 dp_m_n = &crtc->config->dp_m_n;
7169 dp_m2_n2 = &crtc->config->dp_m2_n2;
7170 } else if (m_n == M2_N2) {
7171
7172 /*
7173 * M2_N2 registers are not supported. Hence m2_n2 divider value
7174 * needs to be programmed into M1_N1.
7175 */
7176 dp_m_n = &crtc->config->dp_m2_n2;
7177 } else {
7178 DRM_ERROR("Unsupported divider value\n");
7179 return;
7180 }
7181
7182 if (crtc->config->has_pch_encoder)
7183 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7184 else
7185 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7186 }
7187
7188 static void vlv_compute_dpll(struct intel_crtc *crtc,
7189 struct intel_crtc_state *pipe_config)
7190 {
7191 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7192 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7193 if (crtc->pipe != PIPE_A)
7194 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7195
7196 /* DPLL not used with DSI, but still need the rest set up */
7197 if (!pipe_config->has_dsi_encoder)
7198 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7199 DPLL_EXT_BUFFER_ENABLE_VLV;
7200
7201 pipe_config->dpll_hw_state.dpll_md =
7202 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7203 }
7204
7205 static void chv_compute_dpll(struct intel_crtc *crtc,
7206 struct intel_crtc_state *pipe_config)
7207 {
7208 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7209 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7210 if (crtc->pipe != PIPE_A)
7211 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7212
7213 /* DPLL not used with DSI, but still need the rest set up */
7214 if (!pipe_config->has_dsi_encoder)
7215 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7216
7217 pipe_config->dpll_hw_state.dpll_md =
7218 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7219 }
7220
7221 static void vlv_prepare_pll(struct intel_crtc *crtc,
7222 const struct intel_crtc_state *pipe_config)
7223 {
7224 struct drm_device *dev = crtc->base.dev;
7225 struct drm_i915_private *dev_priv = dev->dev_private;
7226 enum pipe pipe = crtc->pipe;
7227 u32 mdiv;
7228 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7229 u32 coreclk, reg_val;
7230
7231 /* Enable Refclk */
7232 I915_WRITE(DPLL(pipe),
7233 pipe_config->dpll_hw_state.dpll &
7234 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7235
7236 /* No need to actually set up the DPLL with DSI */
7237 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7238 return;
7239
7240 mutex_lock(&dev_priv->sb_lock);
7241
7242 bestn = pipe_config->dpll.n;
7243 bestm1 = pipe_config->dpll.m1;
7244 bestm2 = pipe_config->dpll.m2;
7245 bestp1 = pipe_config->dpll.p1;
7246 bestp2 = pipe_config->dpll.p2;
7247
7248 /* See eDP HDMI DPIO driver vbios notes doc */
7249
7250 /* PLL B needs special handling */
7251 if (pipe == PIPE_B)
7252 vlv_pllb_recal_opamp(dev_priv, pipe);
7253
7254 /* Set up Tx target for periodic Rcomp update */
7255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7256
7257 /* Disable target IRef on PLL */
7258 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7259 reg_val &= 0x00ffffff;
7260 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7261
7262 /* Disable fast lock */
7263 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7264
7265 /* Set idtafcrecal before PLL is enabled */
7266 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7267 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7268 mdiv |= ((bestn << DPIO_N_SHIFT));
7269 mdiv |= (1 << DPIO_K_SHIFT);
7270
7271 /*
7272 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7273 * but we don't support that).
7274 * Note: don't use the DAC post divider as it seems unstable.
7275 */
7276 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7278
7279 mdiv |= DPIO_ENABLE_CALIBRATION;
7280 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7281
7282 /* Set HBR and RBR LPF coefficients */
7283 if (pipe_config->port_clock == 162000 ||
7284 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7285 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7287 0x009f0003);
7288 else
7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7290 0x00d0000f);
7291
7292 if (pipe_config->has_dp_encoder) {
7293 /* Use SSC source */
7294 if (pipe == PIPE_A)
7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7296 0x0df40000);
7297 else
7298 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7299 0x0df70000);
7300 } else { /* HDMI or VGA */
7301 /* Use bend source */
7302 if (pipe == PIPE_A)
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7304 0x0df70000);
7305 else
7306 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7307 0x0df40000);
7308 }
7309
7310 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7311 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7312 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7313 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7314 coreclk |= 0x01000000;
7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7316
7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7318 mutex_unlock(&dev_priv->sb_lock);
7319 }
7320
7321 static void chv_prepare_pll(struct intel_crtc *crtc,
7322 const struct intel_crtc_state *pipe_config)
7323 {
7324 struct drm_device *dev = crtc->base.dev;
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326 enum pipe pipe = crtc->pipe;
7327 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7328 u32 loopfilter, tribuf_calcntr;
7329 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7330 u32 dpio_val;
7331 int vco;
7332
7333 /* Enable Refclk and SSC */
7334 I915_WRITE(DPLL(pipe),
7335 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7336
7337 /* No need to actually set up the DPLL with DSI */
7338 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7339 return;
7340
7341 bestn = pipe_config->dpll.n;
7342 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7343 bestm1 = pipe_config->dpll.m1;
7344 bestm2 = pipe_config->dpll.m2 >> 22;
7345 bestp1 = pipe_config->dpll.p1;
7346 bestp2 = pipe_config->dpll.p2;
7347 vco = pipe_config->dpll.vco;
7348 dpio_val = 0;
7349 loopfilter = 0;
7350
7351 mutex_lock(&dev_priv->sb_lock);
7352
7353 /* p1 and p2 divider */
7354 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7355 5 << DPIO_CHV_S1_DIV_SHIFT |
7356 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7357 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7358 1 << DPIO_CHV_K_DIV_SHIFT);
7359
7360 /* Feedback post-divider - m2 */
7361 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7362
7363 /* Feedback refclk divider - n and m1 */
7364 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7365 DPIO_CHV_M1_DIV_BY_2 |
7366 1 << DPIO_CHV_N_DIV_SHIFT);
7367
7368 /* M2 fraction division */
7369 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7370
7371 /* M2 fraction division enable */
7372 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7373 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7374 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7375 if (bestm2_frac)
7376 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7377 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7378
7379 /* Program digital lock detect threshold */
7380 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7381 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7382 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7383 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7384 if (!bestm2_frac)
7385 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7387
7388 /* Loop filter */
7389 if (vco == 5400000) {
7390 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7391 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7392 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7393 tribuf_calcntr = 0x9;
7394 } else if (vco <= 6200000) {
7395 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7396 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7397 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7398 tribuf_calcntr = 0x9;
7399 } else if (vco <= 6480000) {
7400 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7401 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7402 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7403 tribuf_calcntr = 0x8;
7404 } else {
7405 /* Not supported. Apply the same limits as in the max case */
7406 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7407 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7408 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7409 tribuf_calcntr = 0;
7410 }
7411 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7412
7413 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7414 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7415 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7416 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7417
7418 /* AFC Recal */
7419 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7420 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7421 DPIO_AFC_RECAL);
7422
7423 mutex_unlock(&dev_priv->sb_lock);
7424 }
7425
7426 /**
7427 * vlv_force_pll_on - forcibly enable just the PLL
7428 * @dev_priv: i915 private structure
7429 * @pipe: pipe PLL to enable
7430 * @dpll: PLL configuration
7431 *
7432 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7433 * in cases where we need the PLL enabled even when @pipe is not going to
7434 * be enabled.
7435 */
7436 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7437 const struct dpll *dpll)
7438 {
7439 struct intel_crtc *crtc =
7440 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7441 struct intel_crtc_state *pipe_config;
7442
7443 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7444 if (!pipe_config)
7445 return -ENOMEM;
7446
7447 pipe_config->base.crtc = &crtc->base;
7448 pipe_config->pixel_multiplier = 1;
7449 pipe_config->dpll = *dpll;
7450
7451 if (IS_CHERRYVIEW(dev)) {
7452 chv_compute_dpll(crtc, pipe_config);
7453 chv_prepare_pll(crtc, pipe_config);
7454 chv_enable_pll(crtc, pipe_config);
7455 } else {
7456 vlv_compute_dpll(crtc, pipe_config);
7457 vlv_prepare_pll(crtc, pipe_config);
7458 vlv_enable_pll(crtc, pipe_config);
7459 }
7460
7461 kfree(pipe_config);
7462
7463 return 0;
7464 }
7465
7466 /**
7467 * vlv_force_pll_off - forcibly disable just the PLL
7468 * @dev_priv: i915 private structure
7469 * @pipe: pipe PLL to disable
7470 *
7471 * Disable the PLL for @pipe. To be used in cases where we need
7472 * the PLL enabled even when @pipe is not going to be enabled.
7473 */
7474 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7475 {
7476 if (IS_CHERRYVIEW(dev))
7477 chv_disable_pll(to_i915(dev), pipe);
7478 else
7479 vlv_disable_pll(to_i915(dev), pipe);
7480 }
7481
7482 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7483 struct intel_crtc_state *crtc_state,
7484 struct dpll *reduced_clock)
7485 {
7486 struct drm_device *dev = crtc->base.dev;
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 u32 dpll;
7489 bool is_sdvo;
7490 struct dpll *clock = &crtc_state->dpll;
7491
7492 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7493
7494 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7495 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7496
7497 dpll = DPLL_VGA_MODE_DIS;
7498
7499 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7500 dpll |= DPLLB_MODE_LVDS;
7501 else
7502 dpll |= DPLLB_MODE_DAC_SERIAL;
7503
7504 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7505 dpll |= (crtc_state->pixel_multiplier - 1)
7506 << SDVO_MULTIPLIER_SHIFT_HIRES;
7507 }
7508
7509 if (is_sdvo)
7510 dpll |= DPLL_SDVO_HIGH_SPEED;
7511
7512 if (crtc_state->has_dp_encoder)
7513 dpll |= DPLL_SDVO_HIGH_SPEED;
7514
7515 /* compute bitmask from p1 value */
7516 if (IS_PINEVIEW(dev))
7517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7518 else {
7519 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7520 if (IS_G4X(dev) && reduced_clock)
7521 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7522 }
7523 switch (clock->p2) {
7524 case 5:
7525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7526 break;
7527 case 7:
7528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7529 break;
7530 case 10:
7531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7532 break;
7533 case 14:
7534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7535 break;
7536 }
7537 if (INTEL_INFO(dev)->gen >= 4)
7538 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7539
7540 if (crtc_state->sdvo_tv_clock)
7541 dpll |= PLL_REF_INPUT_TVCLKINBC;
7542 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7543 intel_panel_use_ssc(dev_priv))
7544 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7545 else
7546 dpll |= PLL_REF_INPUT_DREFCLK;
7547
7548 dpll |= DPLL_VCO_ENABLE;
7549 crtc_state->dpll_hw_state.dpll = dpll;
7550
7551 if (INTEL_INFO(dev)->gen >= 4) {
7552 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7553 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7554 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7555 }
7556 }
7557
7558 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7559 struct intel_crtc_state *crtc_state,
7560 struct dpll *reduced_clock)
7561 {
7562 struct drm_device *dev = crtc->base.dev;
7563 struct drm_i915_private *dev_priv = dev->dev_private;
7564 u32 dpll;
7565 struct dpll *clock = &crtc_state->dpll;
7566
7567 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7568
7569 dpll = DPLL_VGA_MODE_DIS;
7570
7571 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7572 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7573 } else {
7574 if (clock->p1 == 2)
7575 dpll |= PLL_P1_DIVIDE_BY_TWO;
7576 else
7577 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7578 if (clock->p2 == 4)
7579 dpll |= PLL_P2_DIVIDE_BY_4;
7580 }
7581
7582 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7583 dpll |= DPLL_DVO_2X_MODE;
7584
7585 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7586 intel_panel_use_ssc(dev_priv))
7587 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7588 else
7589 dpll |= PLL_REF_INPUT_DREFCLK;
7590
7591 dpll |= DPLL_VCO_ENABLE;
7592 crtc_state->dpll_hw_state.dpll = dpll;
7593 }
7594
7595 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7596 {
7597 struct drm_device *dev = intel_crtc->base.dev;
7598 struct drm_i915_private *dev_priv = dev->dev_private;
7599 enum pipe pipe = intel_crtc->pipe;
7600 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7601 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7602 uint32_t crtc_vtotal, crtc_vblank_end;
7603 int vsyncshift = 0;
7604
7605 /* We need to be careful not to changed the adjusted mode, for otherwise
7606 * the hw state checker will get angry at the mismatch. */
7607 crtc_vtotal = adjusted_mode->crtc_vtotal;
7608 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7609
7610 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7611 /* the chip adds 2 halflines automatically */
7612 crtc_vtotal -= 1;
7613 crtc_vblank_end -= 1;
7614
7615 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7616 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7617 else
7618 vsyncshift = adjusted_mode->crtc_hsync_start -
7619 adjusted_mode->crtc_htotal / 2;
7620 if (vsyncshift < 0)
7621 vsyncshift += adjusted_mode->crtc_htotal;
7622 }
7623
7624 if (INTEL_INFO(dev)->gen > 3)
7625 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7626
7627 I915_WRITE(HTOTAL(cpu_transcoder),
7628 (adjusted_mode->crtc_hdisplay - 1) |
7629 ((adjusted_mode->crtc_htotal - 1) << 16));
7630 I915_WRITE(HBLANK(cpu_transcoder),
7631 (adjusted_mode->crtc_hblank_start - 1) |
7632 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7633 I915_WRITE(HSYNC(cpu_transcoder),
7634 (adjusted_mode->crtc_hsync_start - 1) |
7635 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7636
7637 I915_WRITE(VTOTAL(cpu_transcoder),
7638 (adjusted_mode->crtc_vdisplay - 1) |
7639 ((crtc_vtotal - 1) << 16));
7640 I915_WRITE(VBLANK(cpu_transcoder),
7641 (adjusted_mode->crtc_vblank_start - 1) |
7642 ((crtc_vblank_end - 1) << 16));
7643 I915_WRITE(VSYNC(cpu_transcoder),
7644 (adjusted_mode->crtc_vsync_start - 1) |
7645 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7646
7647 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7648 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7649 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7650 * bits. */
7651 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7652 (pipe == PIPE_B || pipe == PIPE_C))
7653 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7654
7655 }
7656
7657 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7658 {
7659 struct drm_device *dev = intel_crtc->base.dev;
7660 struct drm_i915_private *dev_priv = dev->dev_private;
7661 enum pipe pipe = intel_crtc->pipe;
7662
7663 /* pipesrc controls the size that is scaled from, which should
7664 * always be the user's requested size.
7665 */
7666 I915_WRITE(PIPESRC(pipe),
7667 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7668 (intel_crtc->config->pipe_src_h - 1));
7669 }
7670
7671 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7672 struct intel_crtc_state *pipe_config)
7673 {
7674 struct drm_device *dev = crtc->base.dev;
7675 struct drm_i915_private *dev_priv = dev->dev_private;
7676 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7677 uint32_t tmp;
7678
7679 tmp = I915_READ(HTOTAL(cpu_transcoder));
7680 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7681 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7682 tmp = I915_READ(HBLANK(cpu_transcoder));
7683 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7684 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7685 tmp = I915_READ(HSYNC(cpu_transcoder));
7686 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7687 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7688
7689 tmp = I915_READ(VTOTAL(cpu_transcoder));
7690 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7691 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7692 tmp = I915_READ(VBLANK(cpu_transcoder));
7693 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7694 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7695 tmp = I915_READ(VSYNC(cpu_transcoder));
7696 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7697 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7698
7699 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7700 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7701 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7702 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7703 }
7704 }
7705
7706 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7707 struct intel_crtc_state *pipe_config)
7708 {
7709 struct drm_device *dev = crtc->base.dev;
7710 struct drm_i915_private *dev_priv = dev->dev_private;
7711 u32 tmp;
7712
7713 tmp = I915_READ(PIPESRC(crtc->pipe));
7714 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7715 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7716
7717 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7718 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7719 }
7720
7721 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7722 struct intel_crtc_state *pipe_config)
7723 {
7724 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7725 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7726 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7727 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7728
7729 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7730 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7731 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7732 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7733
7734 mode->flags = pipe_config->base.adjusted_mode.flags;
7735 mode->type = DRM_MODE_TYPE_DRIVER;
7736
7737 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7738 mode->flags |= pipe_config->base.adjusted_mode.flags;
7739
7740 mode->hsync = drm_mode_hsync(mode);
7741 mode->vrefresh = drm_mode_vrefresh(mode);
7742 drm_mode_set_name(mode);
7743 }
7744
7745 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7746 {
7747 struct drm_device *dev = intel_crtc->base.dev;
7748 struct drm_i915_private *dev_priv = dev->dev_private;
7749 uint32_t pipeconf;
7750
7751 pipeconf = 0;
7752
7753 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7754 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7755 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7756
7757 if (intel_crtc->config->double_wide)
7758 pipeconf |= PIPECONF_DOUBLE_WIDE;
7759
7760 /* only g4x and later have fancy bpc/dither controls */
7761 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7762 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7763 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7764 pipeconf |= PIPECONF_DITHER_EN |
7765 PIPECONF_DITHER_TYPE_SP;
7766
7767 switch (intel_crtc->config->pipe_bpp) {
7768 case 18:
7769 pipeconf |= PIPECONF_6BPC;
7770 break;
7771 case 24:
7772 pipeconf |= PIPECONF_8BPC;
7773 break;
7774 case 30:
7775 pipeconf |= PIPECONF_10BPC;
7776 break;
7777 default:
7778 /* Case prevented by intel_choose_pipe_bpp_dither. */
7779 BUG();
7780 }
7781 }
7782
7783 if (HAS_PIPE_CXSR(dev)) {
7784 if (intel_crtc->lowfreq_avail) {
7785 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7786 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7787 } else {
7788 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7789 }
7790 }
7791
7792 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7793 if (INTEL_INFO(dev)->gen < 4 ||
7794 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7795 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7796 else
7797 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7798 } else
7799 pipeconf |= PIPECONF_PROGRESSIVE;
7800
7801 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7802 intel_crtc->config->limited_color_range)
7803 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7804
7805 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7806 POSTING_READ(PIPECONF(intel_crtc->pipe));
7807 }
7808
7809 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7810 struct intel_crtc_state *crtc_state)
7811 {
7812 struct drm_device *dev = crtc->base.dev;
7813 struct drm_i915_private *dev_priv = dev->dev_private;
7814 const intel_limit_t *limit;
7815 int refclk = 48000;
7816
7817 memset(&crtc_state->dpll_hw_state, 0,
7818 sizeof(crtc_state->dpll_hw_state));
7819
7820 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7821 if (intel_panel_use_ssc(dev_priv)) {
7822 refclk = dev_priv->vbt.lvds_ssc_freq;
7823 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7824 }
7825
7826 limit = &intel_limits_i8xx_lvds;
7827 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7828 limit = &intel_limits_i8xx_dvo;
7829 } else {
7830 limit = &intel_limits_i8xx_dac;
7831 }
7832
7833 if (!crtc_state->clock_set &&
7834 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7835 refclk, NULL, &crtc_state->dpll)) {
7836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7837 return -EINVAL;
7838 }
7839
7840 i8xx_compute_dpll(crtc, crtc_state, NULL);
7841
7842 return 0;
7843 }
7844
7845 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7846 struct intel_crtc_state *crtc_state)
7847 {
7848 struct drm_device *dev = crtc->base.dev;
7849 struct drm_i915_private *dev_priv = dev->dev_private;
7850 const intel_limit_t *limit;
7851 int refclk = 96000;
7852
7853 memset(&crtc_state->dpll_hw_state, 0,
7854 sizeof(crtc_state->dpll_hw_state));
7855
7856 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7857 if (intel_panel_use_ssc(dev_priv)) {
7858 refclk = dev_priv->vbt.lvds_ssc_freq;
7859 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7860 }
7861
7862 if (intel_is_dual_link_lvds(dev))
7863 limit = &intel_limits_g4x_dual_channel_lvds;
7864 else
7865 limit = &intel_limits_g4x_single_channel_lvds;
7866 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7867 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7868 limit = &intel_limits_g4x_hdmi;
7869 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7870 limit = &intel_limits_g4x_sdvo;
7871 } else {
7872 /* The option is for other outputs */
7873 limit = &intel_limits_i9xx_sdvo;
7874 }
7875
7876 if (!crtc_state->clock_set &&
7877 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7878 refclk, NULL, &crtc_state->dpll)) {
7879 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7880 return -EINVAL;
7881 }
7882
7883 i9xx_compute_dpll(crtc, crtc_state, NULL);
7884
7885 return 0;
7886 }
7887
7888 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7889 struct intel_crtc_state *crtc_state)
7890 {
7891 struct drm_device *dev = crtc->base.dev;
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7893 const intel_limit_t *limit;
7894 int refclk = 96000;
7895
7896 memset(&crtc_state->dpll_hw_state, 0,
7897 sizeof(crtc_state->dpll_hw_state));
7898
7899 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7900 if (intel_panel_use_ssc(dev_priv)) {
7901 refclk = dev_priv->vbt.lvds_ssc_freq;
7902 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7903 }
7904
7905 limit = &intel_limits_pineview_lvds;
7906 } else {
7907 limit = &intel_limits_pineview_sdvo;
7908 }
7909
7910 if (!crtc_state->clock_set &&
7911 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7912 refclk, NULL, &crtc_state->dpll)) {
7913 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7914 return -EINVAL;
7915 }
7916
7917 i9xx_compute_dpll(crtc, crtc_state, NULL);
7918
7919 return 0;
7920 }
7921
7922 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7923 struct intel_crtc_state *crtc_state)
7924 {
7925 struct drm_device *dev = crtc->base.dev;
7926 struct drm_i915_private *dev_priv = dev->dev_private;
7927 const intel_limit_t *limit;
7928 int refclk = 96000;
7929
7930 memset(&crtc_state->dpll_hw_state, 0,
7931 sizeof(crtc_state->dpll_hw_state));
7932
7933 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7934 if (intel_panel_use_ssc(dev_priv)) {
7935 refclk = dev_priv->vbt.lvds_ssc_freq;
7936 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7937 }
7938
7939 limit = &intel_limits_i9xx_lvds;
7940 } else {
7941 limit = &intel_limits_i9xx_sdvo;
7942 }
7943
7944 if (!crtc_state->clock_set &&
7945 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7946 refclk, NULL, &crtc_state->dpll)) {
7947 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7948 return -EINVAL;
7949 }
7950
7951 i9xx_compute_dpll(crtc, crtc_state, NULL);
7952
7953 return 0;
7954 }
7955
7956 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7957 struct intel_crtc_state *crtc_state)
7958 {
7959 int refclk = 100000;
7960 const intel_limit_t *limit = &intel_limits_chv;
7961
7962 memset(&crtc_state->dpll_hw_state, 0,
7963 sizeof(crtc_state->dpll_hw_state));
7964
7965 if (!crtc_state->clock_set &&
7966 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7967 refclk, NULL, &crtc_state->dpll)) {
7968 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7969 return -EINVAL;
7970 }
7971
7972 chv_compute_dpll(crtc, crtc_state);
7973
7974 return 0;
7975 }
7976
7977 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7978 struct intel_crtc_state *crtc_state)
7979 {
7980 int refclk = 100000;
7981 const intel_limit_t *limit = &intel_limits_vlv;
7982
7983 memset(&crtc_state->dpll_hw_state, 0,
7984 sizeof(crtc_state->dpll_hw_state));
7985
7986 if (!crtc_state->clock_set &&
7987 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7988 refclk, NULL, &crtc_state->dpll)) {
7989 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7990 return -EINVAL;
7991 }
7992
7993 vlv_compute_dpll(crtc, crtc_state);
7994
7995 return 0;
7996 }
7997
7998 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7999 struct intel_crtc_state *pipe_config)
8000 {
8001 struct drm_device *dev = crtc->base.dev;
8002 struct drm_i915_private *dev_priv = dev->dev_private;
8003 uint32_t tmp;
8004
8005 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8006 return;
8007
8008 tmp = I915_READ(PFIT_CONTROL);
8009 if (!(tmp & PFIT_ENABLE))
8010 return;
8011
8012 /* Check whether the pfit is attached to our pipe. */
8013 if (INTEL_INFO(dev)->gen < 4) {
8014 if (crtc->pipe != PIPE_B)
8015 return;
8016 } else {
8017 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8018 return;
8019 }
8020
8021 pipe_config->gmch_pfit.control = tmp;
8022 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8023 }
8024
8025 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8026 struct intel_crtc_state *pipe_config)
8027 {
8028 struct drm_device *dev = crtc->base.dev;
8029 struct drm_i915_private *dev_priv = dev->dev_private;
8030 int pipe = pipe_config->cpu_transcoder;
8031 struct dpll clock;
8032 u32 mdiv;
8033 int refclk = 100000;
8034
8035 /* In case of DSI, DPLL will not be used */
8036 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8037 return;
8038
8039 mutex_lock(&dev_priv->sb_lock);
8040 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8041 mutex_unlock(&dev_priv->sb_lock);
8042
8043 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8044 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8045 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8046 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8047 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8048
8049 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8050 }
8051
8052 static void
8053 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8054 struct intel_initial_plane_config *plane_config)
8055 {
8056 struct drm_device *dev = crtc->base.dev;
8057 struct drm_i915_private *dev_priv = dev->dev_private;
8058 u32 val, base, offset;
8059 int pipe = crtc->pipe, plane = crtc->plane;
8060 int fourcc, pixel_format;
8061 unsigned int aligned_height;
8062 struct drm_framebuffer *fb;
8063 struct intel_framebuffer *intel_fb;
8064
8065 val = I915_READ(DSPCNTR(plane));
8066 if (!(val & DISPLAY_PLANE_ENABLE))
8067 return;
8068
8069 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8070 if (!intel_fb) {
8071 DRM_DEBUG_KMS("failed to alloc fb\n");
8072 return;
8073 }
8074
8075 fb = &intel_fb->base;
8076
8077 if (INTEL_INFO(dev)->gen >= 4) {
8078 if (val & DISPPLANE_TILED) {
8079 plane_config->tiling = I915_TILING_X;
8080 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8081 }
8082 }
8083
8084 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8085 fourcc = i9xx_format_to_fourcc(pixel_format);
8086 fb->pixel_format = fourcc;
8087 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8088
8089 if (INTEL_INFO(dev)->gen >= 4) {
8090 if (plane_config->tiling)
8091 offset = I915_READ(DSPTILEOFF(plane));
8092 else
8093 offset = I915_READ(DSPLINOFF(plane));
8094 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8095 } else {
8096 base = I915_READ(DSPADDR(plane));
8097 }
8098 plane_config->base = base;
8099
8100 val = I915_READ(PIPESRC(pipe));
8101 fb->width = ((val >> 16) & 0xfff) + 1;
8102 fb->height = ((val >> 0) & 0xfff) + 1;
8103
8104 val = I915_READ(DSPSTRIDE(pipe));
8105 fb->pitches[0] = val & 0xffffffc0;
8106
8107 aligned_height = intel_fb_align_height(dev, fb->height,
8108 fb->pixel_format,
8109 fb->modifier[0]);
8110
8111 plane_config->size = fb->pitches[0] * aligned_height;
8112
8113 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8114 pipe_name(pipe), plane, fb->width, fb->height,
8115 fb->bits_per_pixel, base, fb->pitches[0],
8116 plane_config->size);
8117
8118 plane_config->fb = intel_fb;
8119 }
8120
8121 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8122 struct intel_crtc_state *pipe_config)
8123 {
8124 struct drm_device *dev = crtc->base.dev;
8125 struct drm_i915_private *dev_priv = dev->dev_private;
8126 int pipe = pipe_config->cpu_transcoder;
8127 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8128 struct dpll clock;
8129 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8130 int refclk = 100000;
8131
8132 /* In case of DSI, DPLL will not be used */
8133 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8134 return;
8135
8136 mutex_lock(&dev_priv->sb_lock);
8137 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8138 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8139 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8140 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8141 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8142 mutex_unlock(&dev_priv->sb_lock);
8143
8144 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8145 clock.m2 = (pll_dw0 & 0xff) << 22;
8146 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8147 clock.m2 |= pll_dw2 & 0x3fffff;
8148 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8149 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8150 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8151
8152 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8153 }
8154
8155 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8156 struct intel_crtc_state *pipe_config)
8157 {
8158 struct drm_device *dev = crtc->base.dev;
8159 struct drm_i915_private *dev_priv = dev->dev_private;
8160 enum intel_display_power_domain power_domain;
8161 uint32_t tmp;
8162 bool ret;
8163
8164 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8165 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8166 return false;
8167
8168 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8169 pipe_config->shared_dpll = NULL;
8170
8171 ret = false;
8172
8173 tmp = I915_READ(PIPECONF(crtc->pipe));
8174 if (!(tmp & PIPECONF_ENABLE))
8175 goto out;
8176
8177 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8178 switch (tmp & PIPECONF_BPC_MASK) {
8179 case PIPECONF_6BPC:
8180 pipe_config->pipe_bpp = 18;
8181 break;
8182 case PIPECONF_8BPC:
8183 pipe_config->pipe_bpp = 24;
8184 break;
8185 case PIPECONF_10BPC:
8186 pipe_config->pipe_bpp = 30;
8187 break;
8188 default:
8189 break;
8190 }
8191 }
8192
8193 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8194 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8195 pipe_config->limited_color_range = true;
8196
8197 if (INTEL_INFO(dev)->gen < 4)
8198 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8199
8200 intel_get_pipe_timings(crtc, pipe_config);
8201 intel_get_pipe_src_size(crtc, pipe_config);
8202
8203 i9xx_get_pfit_config(crtc, pipe_config);
8204
8205 if (INTEL_INFO(dev)->gen >= 4) {
8206 /* No way to read it out on pipes B and C */
8207 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8208 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8209 else
8210 tmp = I915_READ(DPLL_MD(crtc->pipe));
8211 pipe_config->pixel_multiplier =
8212 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8213 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8214 pipe_config->dpll_hw_state.dpll_md = tmp;
8215 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8216 tmp = I915_READ(DPLL(crtc->pipe));
8217 pipe_config->pixel_multiplier =
8218 ((tmp & SDVO_MULTIPLIER_MASK)
8219 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8220 } else {
8221 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8222 * port and will be fixed up in the encoder->get_config
8223 * function. */
8224 pipe_config->pixel_multiplier = 1;
8225 }
8226 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8227 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8228 /*
8229 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8230 * on 830. Filter it out here so that we don't
8231 * report errors due to that.
8232 */
8233 if (IS_I830(dev))
8234 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8235
8236 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8237 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8238 } else {
8239 /* Mask out read-only status bits. */
8240 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8241 DPLL_PORTC_READY_MASK |
8242 DPLL_PORTB_READY_MASK);
8243 }
8244
8245 if (IS_CHERRYVIEW(dev))
8246 chv_crtc_clock_get(crtc, pipe_config);
8247 else if (IS_VALLEYVIEW(dev))
8248 vlv_crtc_clock_get(crtc, pipe_config);
8249 else
8250 i9xx_crtc_clock_get(crtc, pipe_config);
8251
8252 /*
8253 * Normally the dotclock is filled in by the encoder .get_config()
8254 * but in case the pipe is enabled w/o any ports we need a sane
8255 * default.
8256 */
8257 pipe_config->base.adjusted_mode.crtc_clock =
8258 pipe_config->port_clock / pipe_config->pixel_multiplier;
8259
8260 ret = true;
8261
8262 out:
8263 intel_display_power_put(dev_priv, power_domain);
8264
8265 return ret;
8266 }
8267
8268 static void ironlake_init_pch_refclk(struct drm_device *dev)
8269 {
8270 struct drm_i915_private *dev_priv = dev->dev_private;
8271 struct intel_encoder *encoder;
8272 u32 val, final;
8273 bool has_lvds = false;
8274 bool has_cpu_edp = false;
8275 bool has_panel = false;
8276 bool has_ck505 = false;
8277 bool can_ssc = false;
8278
8279 /* We need to take the global config into account */
8280 for_each_intel_encoder(dev, encoder) {
8281 switch (encoder->type) {
8282 case INTEL_OUTPUT_LVDS:
8283 has_panel = true;
8284 has_lvds = true;
8285 break;
8286 case INTEL_OUTPUT_EDP:
8287 has_panel = true;
8288 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8289 has_cpu_edp = true;
8290 break;
8291 default:
8292 break;
8293 }
8294 }
8295
8296 if (HAS_PCH_IBX(dev)) {
8297 has_ck505 = dev_priv->vbt.display_clock_mode;
8298 can_ssc = has_ck505;
8299 } else {
8300 has_ck505 = false;
8301 can_ssc = true;
8302 }
8303
8304 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8305 has_panel, has_lvds, has_ck505);
8306
8307 /* Ironlake: try to setup display ref clock before DPLL
8308 * enabling. This is only under driver's control after
8309 * PCH B stepping, previous chipset stepping should be
8310 * ignoring this setting.
8311 */
8312 val = I915_READ(PCH_DREF_CONTROL);
8313
8314 /* As we must carefully and slowly disable/enable each source in turn,
8315 * compute the final state we want first and check if we need to
8316 * make any changes at all.
8317 */
8318 final = val;
8319 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8320 if (has_ck505)
8321 final |= DREF_NONSPREAD_CK505_ENABLE;
8322 else
8323 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8324
8325 final &= ~DREF_SSC_SOURCE_MASK;
8326 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8327 final &= ~DREF_SSC1_ENABLE;
8328
8329 if (has_panel) {
8330 final |= DREF_SSC_SOURCE_ENABLE;
8331
8332 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8333 final |= DREF_SSC1_ENABLE;
8334
8335 if (has_cpu_edp) {
8336 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8337 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8338 else
8339 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8340 } else
8341 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8342 } else {
8343 final |= DREF_SSC_SOURCE_DISABLE;
8344 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8345 }
8346
8347 if (final == val)
8348 return;
8349
8350 /* Always enable nonspread source */
8351 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8352
8353 if (has_ck505)
8354 val |= DREF_NONSPREAD_CK505_ENABLE;
8355 else
8356 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8357
8358 if (has_panel) {
8359 val &= ~DREF_SSC_SOURCE_MASK;
8360 val |= DREF_SSC_SOURCE_ENABLE;
8361
8362 /* SSC must be turned on before enabling the CPU output */
8363 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8364 DRM_DEBUG_KMS("Using SSC on panel\n");
8365 val |= DREF_SSC1_ENABLE;
8366 } else
8367 val &= ~DREF_SSC1_ENABLE;
8368
8369 /* Get SSC going before enabling the outputs */
8370 I915_WRITE(PCH_DREF_CONTROL, val);
8371 POSTING_READ(PCH_DREF_CONTROL);
8372 udelay(200);
8373
8374 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8375
8376 /* Enable CPU source on CPU attached eDP */
8377 if (has_cpu_edp) {
8378 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8379 DRM_DEBUG_KMS("Using SSC on eDP\n");
8380 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8381 } else
8382 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8383 } else
8384 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8385
8386 I915_WRITE(PCH_DREF_CONTROL, val);
8387 POSTING_READ(PCH_DREF_CONTROL);
8388 udelay(200);
8389 } else {
8390 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8391
8392 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8393
8394 /* Turn off CPU output */
8395 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8396
8397 I915_WRITE(PCH_DREF_CONTROL, val);
8398 POSTING_READ(PCH_DREF_CONTROL);
8399 udelay(200);
8400
8401 /* Turn off the SSC source */
8402 val &= ~DREF_SSC_SOURCE_MASK;
8403 val |= DREF_SSC_SOURCE_DISABLE;
8404
8405 /* Turn off SSC1 */
8406 val &= ~DREF_SSC1_ENABLE;
8407
8408 I915_WRITE(PCH_DREF_CONTROL, val);
8409 POSTING_READ(PCH_DREF_CONTROL);
8410 udelay(200);
8411 }
8412
8413 BUG_ON(val != final);
8414 }
8415
8416 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8417 {
8418 uint32_t tmp;
8419
8420 tmp = I915_READ(SOUTH_CHICKEN2);
8421 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8422 I915_WRITE(SOUTH_CHICKEN2, tmp);
8423
8424 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8425 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8426 DRM_ERROR("FDI mPHY reset assert timeout\n");
8427
8428 tmp = I915_READ(SOUTH_CHICKEN2);
8429 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8430 I915_WRITE(SOUTH_CHICKEN2, tmp);
8431
8432 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8433 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8434 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8435 }
8436
8437 /* WaMPhyProgramming:hsw */
8438 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8439 {
8440 uint32_t tmp;
8441
8442 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8443 tmp &= ~(0xFF << 24);
8444 tmp |= (0x12 << 24);
8445 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8446
8447 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8448 tmp |= (1 << 11);
8449 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8450
8451 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8452 tmp |= (1 << 11);
8453 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8454
8455 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8456 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8457 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8458
8459 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8460 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8461 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8462
8463 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8464 tmp &= ~(7 << 13);
8465 tmp |= (5 << 13);
8466 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8467
8468 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8469 tmp &= ~(7 << 13);
8470 tmp |= (5 << 13);
8471 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8472
8473 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8474 tmp &= ~0xFF;
8475 tmp |= 0x1C;
8476 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8477
8478 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8479 tmp &= ~0xFF;
8480 tmp |= 0x1C;
8481 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8482
8483 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8484 tmp &= ~(0xFF << 16);
8485 tmp |= (0x1C << 16);
8486 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8487
8488 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8489 tmp &= ~(0xFF << 16);
8490 tmp |= (0x1C << 16);
8491 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8492
8493 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8494 tmp |= (1 << 27);
8495 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8496
8497 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8498 tmp |= (1 << 27);
8499 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8500
8501 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8502 tmp &= ~(0xF << 28);
8503 tmp |= (4 << 28);
8504 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8505
8506 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8507 tmp &= ~(0xF << 28);
8508 tmp |= (4 << 28);
8509 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8510 }
8511
8512 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8513 * Programming" based on the parameters passed:
8514 * - Sequence to enable CLKOUT_DP
8515 * - Sequence to enable CLKOUT_DP without spread
8516 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8517 */
8518 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8519 bool with_fdi)
8520 {
8521 struct drm_i915_private *dev_priv = dev->dev_private;
8522 uint32_t reg, tmp;
8523
8524 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8525 with_spread = true;
8526 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8527 with_fdi = false;
8528
8529 mutex_lock(&dev_priv->sb_lock);
8530
8531 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8532 tmp &= ~SBI_SSCCTL_DISABLE;
8533 tmp |= SBI_SSCCTL_PATHALT;
8534 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8535
8536 udelay(24);
8537
8538 if (with_spread) {
8539 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8540 tmp &= ~SBI_SSCCTL_PATHALT;
8541 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8542
8543 if (with_fdi) {
8544 lpt_reset_fdi_mphy(dev_priv);
8545 lpt_program_fdi_mphy(dev_priv);
8546 }
8547 }
8548
8549 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8550 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8551 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8552 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8553
8554 mutex_unlock(&dev_priv->sb_lock);
8555 }
8556
8557 /* Sequence to disable CLKOUT_DP */
8558 static void lpt_disable_clkout_dp(struct drm_device *dev)
8559 {
8560 struct drm_i915_private *dev_priv = dev->dev_private;
8561 uint32_t reg, tmp;
8562
8563 mutex_lock(&dev_priv->sb_lock);
8564
8565 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8566 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8567 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8568 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8569
8570 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8571 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8572 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8573 tmp |= SBI_SSCCTL_PATHALT;
8574 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8575 udelay(32);
8576 }
8577 tmp |= SBI_SSCCTL_DISABLE;
8578 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8579 }
8580
8581 mutex_unlock(&dev_priv->sb_lock);
8582 }
8583
8584 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8585
8586 static const uint16_t sscdivintphase[] = {
8587 [BEND_IDX( 50)] = 0x3B23,
8588 [BEND_IDX( 45)] = 0x3B23,
8589 [BEND_IDX( 40)] = 0x3C23,
8590 [BEND_IDX( 35)] = 0x3C23,
8591 [BEND_IDX( 30)] = 0x3D23,
8592 [BEND_IDX( 25)] = 0x3D23,
8593 [BEND_IDX( 20)] = 0x3E23,
8594 [BEND_IDX( 15)] = 0x3E23,
8595 [BEND_IDX( 10)] = 0x3F23,
8596 [BEND_IDX( 5)] = 0x3F23,
8597 [BEND_IDX( 0)] = 0x0025,
8598 [BEND_IDX( -5)] = 0x0025,
8599 [BEND_IDX(-10)] = 0x0125,
8600 [BEND_IDX(-15)] = 0x0125,
8601 [BEND_IDX(-20)] = 0x0225,
8602 [BEND_IDX(-25)] = 0x0225,
8603 [BEND_IDX(-30)] = 0x0325,
8604 [BEND_IDX(-35)] = 0x0325,
8605 [BEND_IDX(-40)] = 0x0425,
8606 [BEND_IDX(-45)] = 0x0425,
8607 [BEND_IDX(-50)] = 0x0525,
8608 };
8609
8610 /*
8611 * Bend CLKOUT_DP
8612 * steps -50 to 50 inclusive, in steps of 5
8613 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8614 * change in clock period = -(steps / 10) * 5.787 ps
8615 */
8616 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8617 {
8618 uint32_t tmp;
8619 int idx = BEND_IDX(steps);
8620
8621 if (WARN_ON(steps % 5 != 0))
8622 return;
8623
8624 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8625 return;
8626
8627 mutex_lock(&dev_priv->sb_lock);
8628
8629 if (steps % 10 != 0)
8630 tmp = 0xAAAAAAAB;
8631 else
8632 tmp = 0x00000000;
8633 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8634
8635 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8636 tmp &= 0xffff0000;
8637 tmp |= sscdivintphase[idx];
8638 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8639
8640 mutex_unlock(&dev_priv->sb_lock);
8641 }
8642
8643 #undef BEND_IDX
8644
8645 static void lpt_init_pch_refclk(struct drm_device *dev)
8646 {
8647 struct intel_encoder *encoder;
8648 bool has_vga = false;
8649
8650 for_each_intel_encoder(dev, encoder) {
8651 switch (encoder->type) {
8652 case INTEL_OUTPUT_ANALOG:
8653 has_vga = true;
8654 break;
8655 default:
8656 break;
8657 }
8658 }
8659
8660 if (has_vga) {
8661 lpt_bend_clkout_dp(to_i915(dev), 0);
8662 lpt_enable_clkout_dp(dev, true, true);
8663 } else {
8664 lpt_disable_clkout_dp(dev);
8665 }
8666 }
8667
8668 /*
8669 * Initialize reference clocks when the driver loads
8670 */
8671 void intel_init_pch_refclk(struct drm_device *dev)
8672 {
8673 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8674 ironlake_init_pch_refclk(dev);
8675 else if (HAS_PCH_LPT(dev))
8676 lpt_init_pch_refclk(dev);
8677 }
8678
8679 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8680 {
8681 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8683 int pipe = intel_crtc->pipe;
8684 uint32_t val;
8685
8686 val = 0;
8687
8688 switch (intel_crtc->config->pipe_bpp) {
8689 case 18:
8690 val |= PIPECONF_6BPC;
8691 break;
8692 case 24:
8693 val |= PIPECONF_8BPC;
8694 break;
8695 case 30:
8696 val |= PIPECONF_10BPC;
8697 break;
8698 case 36:
8699 val |= PIPECONF_12BPC;
8700 break;
8701 default:
8702 /* Case prevented by intel_choose_pipe_bpp_dither. */
8703 BUG();
8704 }
8705
8706 if (intel_crtc->config->dither)
8707 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8708
8709 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8710 val |= PIPECONF_INTERLACED_ILK;
8711 else
8712 val |= PIPECONF_PROGRESSIVE;
8713
8714 if (intel_crtc->config->limited_color_range)
8715 val |= PIPECONF_COLOR_RANGE_SELECT;
8716
8717 I915_WRITE(PIPECONF(pipe), val);
8718 POSTING_READ(PIPECONF(pipe));
8719 }
8720
8721 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8722 {
8723 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8725 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8726 u32 val = 0;
8727
8728 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8729 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8730
8731 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8732 val |= PIPECONF_INTERLACED_ILK;
8733 else
8734 val |= PIPECONF_PROGRESSIVE;
8735
8736 I915_WRITE(PIPECONF(cpu_transcoder), val);
8737 POSTING_READ(PIPECONF(cpu_transcoder));
8738 }
8739
8740 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8741 {
8742 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8744
8745 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8746 u32 val = 0;
8747
8748 switch (intel_crtc->config->pipe_bpp) {
8749 case 18:
8750 val |= PIPEMISC_DITHER_6_BPC;
8751 break;
8752 case 24:
8753 val |= PIPEMISC_DITHER_8_BPC;
8754 break;
8755 case 30:
8756 val |= PIPEMISC_DITHER_10_BPC;
8757 break;
8758 case 36:
8759 val |= PIPEMISC_DITHER_12_BPC;
8760 break;
8761 default:
8762 /* Case prevented by pipe_config_set_bpp. */
8763 BUG();
8764 }
8765
8766 if (intel_crtc->config->dither)
8767 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8768
8769 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8770 }
8771 }
8772
8773 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8774 {
8775 /*
8776 * Account for spread spectrum to avoid
8777 * oversubscribing the link. Max center spread
8778 * is 2.5%; use 5% for safety's sake.
8779 */
8780 u32 bps = target_clock * bpp * 21 / 20;
8781 return DIV_ROUND_UP(bps, link_bw * 8);
8782 }
8783
8784 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8785 {
8786 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8787 }
8788
8789 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8790 struct intel_crtc_state *crtc_state,
8791 struct dpll *reduced_clock)
8792 {
8793 struct drm_crtc *crtc = &intel_crtc->base;
8794 struct drm_device *dev = crtc->dev;
8795 struct drm_i915_private *dev_priv = dev->dev_private;
8796 struct drm_atomic_state *state = crtc_state->base.state;
8797 struct drm_connector *connector;
8798 struct drm_connector_state *connector_state;
8799 struct intel_encoder *encoder;
8800 u32 dpll, fp, fp2;
8801 int factor, i;
8802 bool is_lvds = false, is_sdvo = false;
8803
8804 for_each_connector_in_state(state, connector, connector_state, i) {
8805 if (connector_state->crtc != crtc_state->base.crtc)
8806 continue;
8807
8808 encoder = to_intel_encoder(connector_state->best_encoder);
8809
8810 switch (encoder->type) {
8811 case INTEL_OUTPUT_LVDS:
8812 is_lvds = true;
8813 break;
8814 case INTEL_OUTPUT_SDVO:
8815 case INTEL_OUTPUT_HDMI:
8816 is_sdvo = true;
8817 break;
8818 default:
8819 break;
8820 }
8821 }
8822
8823 /* Enable autotuning of the PLL clock (if permissible) */
8824 factor = 21;
8825 if (is_lvds) {
8826 if ((intel_panel_use_ssc(dev_priv) &&
8827 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8828 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8829 factor = 25;
8830 } else if (crtc_state->sdvo_tv_clock)
8831 factor = 20;
8832
8833 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8834
8835 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8836 fp |= FP_CB_TUNE;
8837
8838 if (reduced_clock) {
8839 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8840
8841 if (reduced_clock->m < factor * reduced_clock->n)
8842 fp2 |= FP_CB_TUNE;
8843 } else {
8844 fp2 = fp;
8845 }
8846
8847 dpll = 0;
8848
8849 if (is_lvds)
8850 dpll |= DPLLB_MODE_LVDS;
8851 else
8852 dpll |= DPLLB_MODE_DAC_SERIAL;
8853
8854 dpll |= (crtc_state->pixel_multiplier - 1)
8855 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8856
8857 if (is_sdvo)
8858 dpll |= DPLL_SDVO_HIGH_SPEED;
8859 if (crtc_state->has_dp_encoder)
8860 dpll |= DPLL_SDVO_HIGH_SPEED;
8861
8862 /* compute bitmask from p1 value */
8863 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8864 /* also FPA1 */
8865 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8866
8867 switch (crtc_state->dpll.p2) {
8868 case 5:
8869 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8870 break;
8871 case 7:
8872 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8873 break;
8874 case 10:
8875 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8876 break;
8877 case 14:
8878 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8879 break;
8880 }
8881
8882 if (is_lvds && intel_panel_use_ssc(dev_priv))
8883 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8884 else
8885 dpll |= PLL_REF_INPUT_DREFCLK;
8886
8887 dpll |= DPLL_VCO_ENABLE;
8888
8889 crtc_state->dpll_hw_state.dpll = dpll;
8890 crtc_state->dpll_hw_state.fp0 = fp;
8891 crtc_state->dpll_hw_state.fp1 = fp2;
8892 }
8893
8894 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8895 struct intel_crtc_state *crtc_state)
8896 {
8897 struct drm_device *dev = crtc->base.dev;
8898 struct drm_i915_private *dev_priv = dev->dev_private;
8899 struct dpll reduced_clock;
8900 bool has_reduced_clock = false;
8901 struct intel_shared_dpll *pll;
8902 const intel_limit_t *limit;
8903 int refclk = 120000;
8904
8905 memset(&crtc_state->dpll_hw_state, 0,
8906 sizeof(crtc_state->dpll_hw_state));
8907
8908 crtc->lowfreq_avail = false;
8909
8910 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8911 if (!crtc_state->has_pch_encoder)
8912 return 0;
8913
8914 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8915 if (intel_panel_use_ssc(dev_priv)) {
8916 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8917 dev_priv->vbt.lvds_ssc_freq);
8918 refclk = dev_priv->vbt.lvds_ssc_freq;
8919 }
8920
8921 if (intel_is_dual_link_lvds(dev)) {
8922 if (refclk == 100000)
8923 limit = &intel_limits_ironlake_dual_lvds_100m;
8924 else
8925 limit = &intel_limits_ironlake_dual_lvds;
8926 } else {
8927 if (refclk == 100000)
8928 limit = &intel_limits_ironlake_single_lvds_100m;
8929 else
8930 limit = &intel_limits_ironlake_single_lvds;
8931 }
8932 } else {
8933 limit = &intel_limits_ironlake_dac;
8934 }
8935
8936 if (!crtc_state->clock_set &&
8937 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8938 refclk, NULL, &crtc_state->dpll)) {
8939 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8940 return -EINVAL;
8941 }
8942
8943 ironlake_compute_dpll(crtc, crtc_state,
8944 has_reduced_clock ? &reduced_clock : NULL);
8945
8946 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8947 if (pll == NULL) {
8948 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8949 pipe_name(crtc->pipe));
8950 return -EINVAL;
8951 }
8952
8953 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8954 has_reduced_clock)
8955 crtc->lowfreq_avail = true;
8956
8957 return 0;
8958 }
8959
8960 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8961 struct intel_link_m_n *m_n)
8962 {
8963 struct drm_device *dev = crtc->base.dev;
8964 struct drm_i915_private *dev_priv = dev->dev_private;
8965 enum pipe pipe = crtc->pipe;
8966
8967 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8968 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8969 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8970 & ~TU_SIZE_MASK;
8971 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8972 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8973 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8974 }
8975
8976 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8977 enum transcoder transcoder,
8978 struct intel_link_m_n *m_n,
8979 struct intel_link_m_n *m2_n2)
8980 {
8981 struct drm_device *dev = crtc->base.dev;
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8983 enum pipe pipe = crtc->pipe;
8984
8985 if (INTEL_INFO(dev)->gen >= 5) {
8986 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8987 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8988 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8989 & ~TU_SIZE_MASK;
8990 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8991 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8992 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8993 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8994 * gen < 8) and if DRRS is supported (to make sure the
8995 * registers are not unnecessarily read).
8996 */
8997 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8998 crtc->config->has_drrs) {
8999 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9000 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9001 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9002 & ~TU_SIZE_MASK;
9003 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9004 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9005 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9006 }
9007 } else {
9008 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9009 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9010 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9011 & ~TU_SIZE_MASK;
9012 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9013 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9014 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9015 }
9016 }
9017
9018 void intel_dp_get_m_n(struct intel_crtc *crtc,
9019 struct intel_crtc_state *pipe_config)
9020 {
9021 if (pipe_config->has_pch_encoder)
9022 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9023 else
9024 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9025 &pipe_config->dp_m_n,
9026 &pipe_config->dp_m2_n2);
9027 }
9028
9029 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9030 struct intel_crtc_state *pipe_config)
9031 {
9032 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9033 &pipe_config->fdi_m_n, NULL);
9034 }
9035
9036 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9037 struct intel_crtc_state *pipe_config)
9038 {
9039 struct drm_device *dev = crtc->base.dev;
9040 struct drm_i915_private *dev_priv = dev->dev_private;
9041 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9042 uint32_t ps_ctrl = 0;
9043 int id = -1;
9044 int i;
9045
9046 /* find scaler attached to this pipe */
9047 for (i = 0; i < crtc->num_scalers; i++) {
9048 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9049 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9050 id = i;
9051 pipe_config->pch_pfit.enabled = true;
9052 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9053 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9054 break;
9055 }
9056 }
9057
9058 scaler_state->scaler_id = id;
9059 if (id >= 0) {
9060 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9061 } else {
9062 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9063 }
9064 }
9065
9066 static void
9067 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9068 struct intel_initial_plane_config *plane_config)
9069 {
9070 struct drm_device *dev = crtc->base.dev;
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 u32 val, base, offset, stride_mult, tiling;
9073 int pipe = crtc->pipe;
9074 int fourcc, pixel_format;
9075 unsigned int aligned_height;
9076 struct drm_framebuffer *fb;
9077 struct intel_framebuffer *intel_fb;
9078
9079 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9080 if (!intel_fb) {
9081 DRM_DEBUG_KMS("failed to alloc fb\n");
9082 return;
9083 }
9084
9085 fb = &intel_fb->base;
9086
9087 val = I915_READ(PLANE_CTL(pipe, 0));
9088 if (!(val & PLANE_CTL_ENABLE))
9089 goto error;
9090
9091 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9092 fourcc = skl_format_to_fourcc(pixel_format,
9093 val & PLANE_CTL_ORDER_RGBX,
9094 val & PLANE_CTL_ALPHA_MASK);
9095 fb->pixel_format = fourcc;
9096 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9097
9098 tiling = val & PLANE_CTL_TILED_MASK;
9099 switch (tiling) {
9100 case PLANE_CTL_TILED_LINEAR:
9101 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9102 break;
9103 case PLANE_CTL_TILED_X:
9104 plane_config->tiling = I915_TILING_X;
9105 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9106 break;
9107 case PLANE_CTL_TILED_Y:
9108 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9109 break;
9110 case PLANE_CTL_TILED_YF:
9111 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9112 break;
9113 default:
9114 MISSING_CASE(tiling);
9115 goto error;
9116 }
9117
9118 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9119 plane_config->base = base;
9120
9121 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9122
9123 val = I915_READ(PLANE_SIZE(pipe, 0));
9124 fb->height = ((val >> 16) & 0xfff) + 1;
9125 fb->width = ((val >> 0) & 0x1fff) + 1;
9126
9127 val = I915_READ(PLANE_STRIDE(pipe, 0));
9128 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9129 fb->pixel_format);
9130 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9131
9132 aligned_height = intel_fb_align_height(dev, fb->height,
9133 fb->pixel_format,
9134 fb->modifier[0]);
9135
9136 plane_config->size = fb->pitches[0] * aligned_height;
9137
9138 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9139 pipe_name(pipe), fb->width, fb->height,
9140 fb->bits_per_pixel, base, fb->pitches[0],
9141 plane_config->size);
9142
9143 plane_config->fb = intel_fb;
9144 return;
9145
9146 error:
9147 kfree(fb);
9148 }
9149
9150 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9151 struct intel_crtc_state *pipe_config)
9152 {
9153 struct drm_device *dev = crtc->base.dev;
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9155 uint32_t tmp;
9156
9157 tmp = I915_READ(PF_CTL(crtc->pipe));
9158
9159 if (tmp & PF_ENABLE) {
9160 pipe_config->pch_pfit.enabled = true;
9161 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9162 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9163
9164 /* We currently do not free assignements of panel fitters on
9165 * ivb/hsw (since we don't use the higher upscaling modes which
9166 * differentiates them) so just WARN about this case for now. */
9167 if (IS_GEN7(dev)) {
9168 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9169 PF_PIPE_SEL_IVB(crtc->pipe));
9170 }
9171 }
9172 }
9173
9174 static void
9175 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9176 struct intel_initial_plane_config *plane_config)
9177 {
9178 struct drm_device *dev = crtc->base.dev;
9179 struct drm_i915_private *dev_priv = dev->dev_private;
9180 u32 val, base, offset;
9181 int pipe = crtc->pipe;
9182 int fourcc, pixel_format;
9183 unsigned int aligned_height;
9184 struct drm_framebuffer *fb;
9185 struct intel_framebuffer *intel_fb;
9186
9187 val = I915_READ(DSPCNTR(pipe));
9188 if (!(val & DISPLAY_PLANE_ENABLE))
9189 return;
9190
9191 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9192 if (!intel_fb) {
9193 DRM_DEBUG_KMS("failed to alloc fb\n");
9194 return;
9195 }
9196
9197 fb = &intel_fb->base;
9198
9199 if (INTEL_INFO(dev)->gen >= 4) {
9200 if (val & DISPPLANE_TILED) {
9201 plane_config->tiling = I915_TILING_X;
9202 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9203 }
9204 }
9205
9206 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9207 fourcc = i9xx_format_to_fourcc(pixel_format);
9208 fb->pixel_format = fourcc;
9209 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9210
9211 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9212 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9213 offset = I915_READ(DSPOFFSET(pipe));
9214 } else {
9215 if (plane_config->tiling)
9216 offset = I915_READ(DSPTILEOFF(pipe));
9217 else
9218 offset = I915_READ(DSPLINOFF(pipe));
9219 }
9220 plane_config->base = base;
9221
9222 val = I915_READ(PIPESRC(pipe));
9223 fb->width = ((val >> 16) & 0xfff) + 1;
9224 fb->height = ((val >> 0) & 0xfff) + 1;
9225
9226 val = I915_READ(DSPSTRIDE(pipe));
9227 fb->pitches[0] = val & 0xffffffc0;
9228
9229 aligned_height = intel_fb_align_height(dev, fb->height,
9230 fb->pixel_format,
9231 fb->modifier[0]);
9232
9233 plane_config->size = fb->pitches[0] * aligned_height;
9234
9235 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9236 pipe_name(pipe), fb->width, fb->height,
9237 fb->bits_per_pixel, base, fb->pitches[0],
9238 plane_config->size);
9239
9240 plane_config->fb = intel_fb;
9241 }
9242
9243 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9244 struct intel_crtc_state *pipe_config)
9245 {
9246 struct drm_device *dev = crtc->base.dev;
9247 struct drm_i915_private *dev_priv = dev->dev_private;
9248 enum intel_display_power_domain power_domain;
9249 uint32_t tmp;
9250 bool ret;
9251
9252 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9253 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9254 return false;
9255
9256 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9257 pipe_config->shared_dpll = NULL;
9258
9259 ret = false;
9260 tmp = I915_READ(PIPECONF(crtc->pipe));
9261 if (!(tmp & PIPECONF_ENABLE))
9262 goto out;
9263
9264 switch (tmp & PIPECONF_BPC_MASK) {
9265 case PIPECONF_6BPC:
9266 pipe_config->pipe_bpp = 18;
9267 break;
9268 case PIPECONF_8BPC:
9269 pipe_config->pipe_bpp = 24;
9270 break;
9271 case PIPECONF_10BPC:
9272 pipe_config->pipe_bpp = 30;
9273 break;
9274 case PIPECONF_12BPC:
9275 pipe_config->pipe_bpp = 36;
9276 break;
9277 default:
9278 break;
9279 }
9280
9281 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9282 pipe_config->limited_color_range = true;
9283
9284 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9285 struct intel_shared_dpll *pll;
9286 enum intel_dpll_id pll_id;
9287
9288 pipe_config->has_pch_encoder = true;
9289
9290 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9291 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9292 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9293
9294 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9295
9296 if (HAS_PCH_IBX(dev_priv)) {
9297 pll_id = (enum intel_dpll_id) crtc->pipe;
9298 } else {
9299 tmp = I915_READ(PCH_DPLL_SEL);
9300 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9301 pll_id = DPLL_ID_PCH_PLL_B;
9302 else
9303 pll_id= DPLL_ID_PCH_PLL_A;
9304 }
9305
9306 pipe_config->shared_dpll =
9307 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9308 pll = pipe_config->shared_dpll;
9309
9310 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9311 &pipe_config->dpll_hw_state));
9312
9313 tmp = pipe_config->dpll_hw_state.dpll;
9314 pipe_config->pixel_multiplier =
9315 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9316 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9317
9318 ironlake_pch_clock_get(crtc, pipe_config);
9319 } else {
9320 pipe_config->pixel_multiplier = 1;
9321 }
9322
9323 intel_get_pipe_timings(crtc, pipe_config);
9324 intel_get_pipe_src_size(crtc, pipe_config);
9325
9326 ironlake_get_pfit_config(crtc, pipe_config);
9327
9328 ret = true;
9329
9330 out:
9331 intel_display_power_put(dev_priv, power_domain);
9332
9333 return ret;
9334 }
9335
9336 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9337 {
9338 struct drm_device *dev = dev_priv->dev;
9339 struct intel_crtc *crtc;
9340
9341 for_each_intel_crtc(dev, crtc)
9342 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9343 pipe_name(crtc->pipe));
9344
9345 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9346 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9347 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9348 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9349 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9350 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9351 "CPU PWM1 enabled\n");
9352 if (IS_HASWELL(dev))
9353 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9354 "CPU PWM2 enabled\n");
9355 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9356 "PCH PWM1 enabled\n");
9357 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9358 "Utility pin enabled\n");
9359 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9360
9361 /*
9362 * In theory we can still leave IRQs enabled, as long as only the HPD
9363 * interrupts remain enabled. We used to check for that, but since it's
9364 * gen-specific and since we only disable LCPLL after we fully disable
9365 * the interrupts, the check below should be enough.
9366 */
9367 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9368 }
9369
9370 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9371 {
9372 struct drm_device *dev = dev_priv->dev;
9373
9374 if (IS_HASWELL(dev))
9375 return I915_READ(D_COMP_HSW);
9376 else
9377 return I915_READ(D_COMP_BDW);
9378 }
9379
9380 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9381 {
9382 struct drm_device *dev = dev_priv->dev;
9383
9384 if (IS_HASWELL(dev)) {
9385 mutex_lock(&dev_priv->rps.hw_lock);
9386 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9387 val))
9388 DRM_ERROR("Failed to write to D_COMP\n");
9389 mutex_unlock(&dev_priv->rps.hw_lock);
9390 } else {
9391 I915_WRITE(D_COMP_BDW, val);
9392 POSTING_READ(D_COMP_BDW);
9393 }
9394 }
9395
9396 /*
9397 * This function implements pieces of two sequences from BSpec:
9398 * - Sequence for display software to disable LCPLL
9399 * - Sequence for display software to allow package C8+
9400 * The steps implemented here are just the steps that actually touch the LCPLL
9401 * register. Callers should take care of disabling all the display engine
9402 * functions, doing the mode unset, fixing interrupts, etc.
9403 */
9404 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9405 bool switch_to_fclk, bool allow_power_down)
9406 {
9407 uint32_t val;
9408
9409 assert_can_disable_lcpll(dev_priv);
9410
9411 val = I915_READ(LCPLL_CTL);
9412
9413 if (switch_to_fclk) {
9414 val |= LCPLL_CD_SOURCE_FCLK;
9415 I915_WRITE(LCPLL_CTL, val);
9416
9417 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9418 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9419 DRM_ERROR("Switching to FCLK failed\n");
9420
9421 val = I915_READ(LCPLL_CTL);
9422 }
9423
9424 val |= LCPLL_PLL_DISABLE;
9425 I915_WRITE(LCPLL_CTL, val);
9426 POSTING_READ(LCPLL_CTL);
9427
9428 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9429 DRM_ERROR("LCPLL still locked\n");
9430
9431 val = hsw_read_dcomp(dev_priv);
9432 val |= D_COMP_COMP_DISABLE;
9433 hsw_write_dcomp(dev_priv, val);
9434 ndelay(100);
9435
9436 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9437 1))
9438 DRM_ERROR("D_COMP RCOMP still in progress\n");
9439
9440 if (allow_power_down) {
9441 val = I915_READ(LCPLL_CTL);
9442 val |= LCPLL_POWER_DOWN_ALLOW;
9443 I915_WRITE(LCPLL_CTL, val);
9444 POSTING_READ(LCPLL_CTL);
9445 }
9446 }
9447
9448 /*
9449 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9450 * source.
9451 */
9452 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9453 {
9454 uint32_t val;
9455
9456 val = I915_READ(LCPLL_CTL);
9457
9458 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9459 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9460 return;
9461
9462 /*
9463 * Make sure we're not on PC8 state before disabling PC8, otherwise
9464 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9465 */
9466 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9467
9468 if (val & LCPLL_POWER_DOWN_ALLOW) {
9469 val &= ~LCPLL_POWER_DOWN_ALLOW;
9470 I915_WRITE(LCPLL_CTL, val);
9471 POSTING_READ(LCPLL_CTL);
9472 }
9473
9474 val = hsw_read_dcomp(dev_priv);
9475 val |= D_COMP_COMP_FORCE;
9476 val &= ~D_COMP_COMP_DISABLE;
9477 hsw_write_dcomp(dev_priv, val);
9478
9479 val = I915_READ(LCPLL_CTL);
9480 val &= ~LCPLL_PLL_DISABLE;
9481 I915_WRITE(LCPLL_CTL, val);
9482
9483 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9484 DRM_ERROR("LCPLL not locked yet\n");
9485
9486 if (val & LCPLL_CD_SOURCE_FCLK) {
9487 val = I915_READ(LCPLL_CTL);
9488 val &= ~LCPLL_CD_SOURCE_FCLK;
9489 I915_WRITE(LCPLL_CTL, val);
9490
9491 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9492 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9493 DRM_ERROR("Switching back to LCPLL failed\n");
9494 }
9495
9496 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9497 intel_update_cdclk(dev_priv->dev);
9498 }
9499
9500 /*
9501 * Package states C8 and deeper are really deep PC states that can only be
9502 * reached when all the devices on the system allow it, so even if the graphics
9503 * device allows PC8+, it doesn't mean the system will actually get to these
9504 * states. Our driver only allows PC8+ when going into runtime PM.
9505 *
9506 * The requirements for PC8+ are that all the outputs are disabled, the power
9507 * well is disabled and most interrupts are disabled, and these are also
9508 * requirements for runtime PM. When these conditions are met, we manually do
9509 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9510 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9511 * hang the machine.
9512 *
9513 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9514 * the state of some registers, so when we come back from PC8+ we need to
9515 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9516 * need to take care of the registers kept by RC6. Notice that this happens even
9517 * if we don't put the device in PCI D3 state (which is what currently happens
9518 * because of the runtime PM support).
9519 *
9520 * For more, read "Display Sequences for Package C8" on the hardware
9521 * documentation.
9522 */
9523 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9524 {
9525 struct drm_device *dev = dev_priv->dev;
9526 uint32_t val;
9527
9528 DRM_DEBUG_KMS("Enabling package C8+\n");
9529
9530 if (HAS_PCH_LPT_LP(dev)) {
9531 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9532 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9533 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9534 }
9535
9536 lpt_disable_clkout_dp(dev);
9537 hsw_disable_lcpll(dev_priv, true, true);
9538 }
9539
9540 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9541 {
9542 struct drm_device *dev = dev_priv->dev;
9543 uint32_t val;
9544
9545 DRM_DEBUG_KMS("Disabling package C8+\n");
9546
9547 hsw_restore_lcpll(dev_priv);
9548 lpt_init_pch_refclk(dev);
9549
9550 if (HAS_PCH_LPT_LP(dev)) {
9551 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9552 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9553 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9554 }
9555 }
9556
9557 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9558 {
9559 struct drm_device *dev = old_state->dev;
9560 struct intel_atomic_state *old_intel_state =
9561 to_intel_atomic_state(old_state);
9562 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9563
9564 broxton_set_cdclk(to_i915(dev), req_cdclk);
9565 }
9566
9567 /* compute the max rate for new configuration */
9568 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9569 {
9570 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9571 struct drm_i915_private *dev_priv = state->dev->dev_private;
9572 struct drm_crtc *crtc;
9573 struct drm_crtc_state *cstate;
9574 struct intel_crtc_state *crtc_state;
9575 unsigned max_pixel_rate = 0, i;
9576 enum pipe pipe;
9577
9578 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9579 sizeof(intel_state->min_pixclk));
9580
9581 for_each_crtc_in_state(state, crtc, cstate, i) {
9582 int pixel_rate;
9583
9584 crtc_state = to_intel_crtc_state(cstate);
9585 if (!crtc_state->base.enable) {
9586 intel_state->min_pixclk[i] = 0;
9587 continue;
9588 }
9589
9590 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9591
9592 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9593 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9594 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9595
9596 intel_state->min_pixclk[i] = pixel_rate;
9597 }
9598
9599 for_each_pipe(dev_priv, pipe)
9600 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9601
9602 return max_pixel_rate;
9603 }
9604
9605 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9606 {
9607 struct drm_i915_private *dev_priv = dev->dev_private;
9608 uint32_t val, data;
9609 int ret;
9610
9611 if (WARN((I915_READ(LCPLL_CTL) &
9612 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9613 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9614 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9615 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9616 "trying to change cdclk frequency with cdclk not enabled\n"))
9617 return;
9618
9619 mutex_lock(&dev_priv->rps.hw_lock);
9620 ret = sandybridge_pcode_write(dev_priv,
9621 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9622 mutex_unlock(&dev_priv->rps.hw_lock);
9623 if (ret) {
9624 DRM_ERROR("failed to inform pcode about cdclk change\n");
9625 return;
9626 }
9627
9628 val = I915_READ(LCPLL_CTL);
9629 val |= LCPLL_CD_SOURCE_FCLK;
9630 I915_WRITE(LCPLL_CTL, val);
9631
9632 if (wait_for_us(I915_READ(LCPLL_CTL) &
9633 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9634 DRM_ERROR("Switching to FCLK failed\n");
9635
9636 val = I915_READ(LCPLL_CTL);
9637 val &= ~LCPLL_CLK_FREQ_MASK;
9638
9639 switch (cdclk) {
9640 case 450000:
9641 val |= LCPLL_CLK_FREQ_450;
9642 data = 0;
9643 break;
9644 case 540000:
9645 val |= LCPLL_CLK_FREQ_54O_BDW;
9646 data = 1;
9647 break;
9648 case 337500:
9649 val |= LCPLL_CLK_FREQ_337_5_BDW;
9650 data = 2;
9651 break;
9652 case 675000:
9653 val |= LCPLL_CLK_FREQ_675_BDW;
9654 data = 3;
9655 break;
9656 default:
9657 WARN(1, "invalid cdclk frequency\n");
9658 return;
9659 }
9660
9661 I915_WRITE(LCPLL_CTL, val);
9662
9663 val = I915_READ(LCPLL_CTL);
9664 val &= ~LCPLL_CD_SOURCE_FCLK;
9665 I915_WRITE(LCPLL_CTL, val);
9666
9667 if (wait_for_us((I915_READ(LCPLL_CTL) &
9668 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9669 DRM_ERROR("Switching back to LCPLL failed\n");
9670
9671 mutex_lock(&dev_priv->rps.hw_lock);
9672 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9673 mutex_unlock(&dev_priv->rps.hw_lock);
9674
9675 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9676
9677 intel_update_cdclk(dev);
9678
9679 WARN(cdclk != dev_priv->cdclk_freq,
9680 "cdclk requested %d kHz but got %d kHz\n",
9681 cdclk, dev_priv->cdclk_freq);
9682 }
9683
9684 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9685 {
9686 struct drm_i915_private *dev_priv = to_i915(state->dev);
9687 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9688 int max_pixclk = ilk_max_pixel_rate(state);
9689 int cdclk;
9690
9691 /*
9692 * FIXME should also account for plane ratio
9693 * once 64bpp pixel formats are supported.
9694 */
9695 if (max_pixclk > 540000)
9696 cdclk = 675000;
9697 else if (max_pixclk > 450000)
9698 cdclk = 540000;
9699 else if (max_pixclk > 337500)
9700 cdclk = 450000;
9701 else
9702 cdclk = 337500;
9703
9704 if (cdclk > dev_priv->max_cdclk_freq) {
9705 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9706 cdclk, dev_priv->max_cdclk_freq);
9707 return -EINVAL;
9708 }
9709
9710 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9711 if (!intel_state->active_crtcs)
9712 intel_state->dev_cdclk = 337500;
9713
9714 return 0;
9715 }
9716
9717 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9718 {
9719 struct drm_device *dev = old_state->dev;
9720 struct intel_atomic_state *old_intel_state =
9721 to_intel_atomic_state(old_state);
9722 unsigned req_cdclk = old_intel_state->dev_cdclk;
9723
9724 broadwell_set_cdclk(dev, req_cdclk);
9725 }
9726
9727 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9728 struct intel_crtc_state *crtc_state)
9729 {
9730 struct intel_encoder *intel_encoder =
9731 intel_ddi_get_crtc_new_encoder(crtc_state);
9732
9733 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9734 if (!intel_ddi_pll_select(crtc, crtc_state))
9735 return -EINVAL;
9736 }
9737
9738 crtc->lowfreq_avail = false;
9739
9740 return 0;
9741 }
9742
9743 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9744 enum port port,
9745 struct intel_crtc_state *pipe_config)
9746 {
9747 enum intel_dpll_id id;
9748
9749 switch (port) {
9750 case PORT_A:
9751 pipe_config->ddi_pll_sel = SKL_DPLL0;
9752 id = DPLL_ID_SKL_DPLL0;
9753 break;
9754 case PORT_B:
9755 pipe_config->ddi_pll_sel = SKL_DPLL1;
9756 id = DPLL_ID_SKL_DPLL1;
9757 break;
9758 case PORT_C:
9759 pipe_config->ddi_pll_sel = SKL_DPLL2;
9760 id = DPLL_ID_SKL_DPLL2;
9761 break;
9762 default:
9763 DRM_ERROR("Incorrect port type\n");
9764 return;
9765 }
9766
9767 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9768 }
9769
9770 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9771 enum port port,
9772 struct intel_crtc_state *pipe_config)
9773 {
9774 enum intel_dpll_id id;
9775 u32 temp;
9776
9777 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9778 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9779
9780 switch (pipe_config->ddi_pll_sel) {
9781 case SKL_DPLL0:
9782 id = DPLL_ID_SKL_DPLL0;
9783 break;
9784 case SKL_DPLL1:
9785 id = DPLL_ID_SKL_DPLL1;
9786 break;
9787 case SKL_DPLL2:
9788 id = DPLL_ID_SKL_DPLL2;
9789 break;
9790 case SKL_DPLL3:
9791 id = DPLL_ID_SKL_DPLL3;
9792 break;
9793 default:
9794 MISSING_CASE(pipe_config->ddi_pll_sel);
9795 return;
9796 }
9797
9798 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9799 }
9800
9801 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9802 enum port port,
9803 struct intel_crtc_state *pipe_config)
9804 {
9805 enum intel_dpll_id id;
9806
9807 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9808
9809 switch (pipe_config->ddi_pll_sel) {
9810 case PORT_CLK_SEL_WRPLL1:
9811 id = DPLL_ID_WRPLL1;
9812 break;
9813 case PORT_CLK_SEL_WRPLL2:
9814 id = DPLL_ID_WRPLL2;
9815 break;
9816 case PORT_CLK_SEL_SPLL:
9817 id = DPLL_ID_SPLL;
9818 break;
9819 case PORT_CLK_SEL_LCPLL_810:
9820 id = DPLL_ID_LCPLL_810;
9821 break;
9822 case PORT_CLK_SEL_LCPLL_1350:
9823 id = DPLL_ID_LCPLL_1350;
9824 break;
9825 case PORT_CLK_SEL_LCPLL_2700:
9826 id = DPLL_ID_LCPLL_2700;
9827 break;
9828 default:
9829 MISSING_CASE(pipe_config->ddi_pll_sel);
9830 /* fall through */
9831 case PORT_CLK_SEL_NONE:
9832 return;
9833 }
9834
9835 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9836 }
9837
9838 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9839 struct intel_crtc_state *pipe_config,
9840 unsigned long *power_domain_mask)
9841 {
9842 struct drm_device *dev = crtc->base.dev;
9843 struct drm_i915_private *dev_priv = dev->dev_private;
9844 enum intel_display_power_domain power_domain;
9845 u32 tmp;
9846
9847 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9848
9849 /*
9850 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9851 * consistency and less surprising code; it's in always on power).
9852 */
9853 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9854 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9855 enum pipe trans_edp_pipe;
9856 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9857 default:
9858 WARN(1, "unknown pipe linked to edp transcoder\n");
9859 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9860 case TRANS_DDI_EDP_INPUT_A_ON:
9861 trans_edp_pipe = PIPE_A;
9862 break;
9863 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9864 trans_edp_pipe = PIPE_B;
9865 break;
9866 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9867 trans_edp_pipe = PIPE_C;
9868 break;
9869 }
9870
9871 if (trans_edp_pipe == crtc->pipe)
9872 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9873 }
9874
9875 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9876 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9877 return false;
9878 *power_domain_mask |= BIT(power_domain);
9879
9880 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9881
9882 return tmp & PIPECONF_ENABLE;
9883 }
9884
9885 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9886 struct intel_crtc_state *pipe_config,
9887 unsigned long *power_domain_mask)
9888 {
9889 struct drm_device *dev = crtc->base.dev;
9890 struct drm_i915_private *dev_priv = dev->dev_private;
9891 enum intel_display_power_domain power_domain;
9892 enum port port;
9893 enum transcoder cpu_transcoder;
9894 u32 tmp;
9895
9896 pipe_config->has_dsi_encoder = false;
9897
9898 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9899 if (port == PORT_A)
9900 cpu_transcoder = TRANSCODER_DSI_A;
9901 else
9902 cpu_transcoder = TRANSCODER_DSI_C;
9903
9904 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9905 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9906 continue;
9907 *power_domain_mask |= BIT(power_domain);
9908
9909 /*
9910 * The PLL needs to be enabled with a valid divider
9911 * configuration, otherwise accessing DSI registers will hang
9912 * the machine. See BSpec North Display Engine
9913 * registers/MIPI[BXT]. We can break out here early, since we
9914 * need the same DSI PLL to be enabled for both DSI ports.
9915 */
9916 if (!intel_dsi_pll_is_enabled(dev_priv))
9917 break;
9918
9919 /* XXX: this works for video mode only */
9920 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9921 if (!(tmp & DPI_ENABLE))
9922 continue;
9923
9924 tmp = I915_READ(MIPI_CTRL(port));
9925 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9926 continue;
9927
9928 pipe_config->cpu_transcoder = cpu_transcoder;
9929 pipe_config->has_dsi_encoder = true;
9930 break;
9931 }
9932
9933 return pipe_config->has_dsi_encoder;
9934 }
9935
9936 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9937 struct intel_crtc_state *pipe_config)
9938 {
9939 struct drm_device *dev = crtc->base.dev;
9940 struct drm_i915_private *dev_priv = dev->dev_private;
9941 struct intel_shared_dpll *pll;
9942 enum port port;
9943 uint32_t tmp;
9944
9945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9946
9947 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9948
9949 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9950 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9951 else if (IS_BROXTON(dev))
9952 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9953 else
9954 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9955
9956 pll = pipe_config->shared_dpll;
9957 if (pll) {
9958 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9959 &pipe_config->dpll_hw_state));
9960 }
9961
9962 /*
9963 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9964 * DDI E. So just check whether this pipe is wired to DDI E and whether
9965 * the PCH transcoder is on.
9966 */
9967 if (INTEL_INFO(dev)->gen < 9 &&
9968 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9969 pipe_config->has_pch_encoder = true;
9970
9971 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9972 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9973 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9974
9975 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9976 }
9977 }
9978
9979 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9980 struct intel_crtc_state *pipe_config)
9981 {
9982 struct drm_device *dev = crtc->base.dev;
9983 struct drm_i915_private *dev_priv = dev->dev_private;
9984 enum intel_display_power_domain power_domain;
9985 unsigned long power_domain_mask;
9986 bool active;
9987
9988 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9989 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9990 return false;
9991 power_domain_mask = BIT(power_domain);
9992
9993 pipe_config->shared_dpll = NULL;
9994
9995 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9996
9997 if (IS_BROXTON(dev_priv)) {
9998 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9999 &power_domain_mask);
10000 WARN_ON(active && pipe_config->has_dsi_encoder);
10001 if (pipe_config->has_dsi_encoder)
10002 active = true;
10003 }
10004
10005 if (!active)
10006 goto out;
10007
10008 if (!pipe_config->has_dsi_encoder) {
10009 haswell_get_ddi_port_state(crtc, pipe_config);
10010 intel_get_pipe_timings(crtc, pipe_config);
10011 }
10012
10013 intel_get_pipe_src_size(crtc, pipe_config);
10014
10015 pipe_config->gamma_mode =
10016 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10017
10018 if (INTEL_INFO(dev)->gen >= 9) {
10019 skl_init_scalers(dev, crtc, pipe_config);
10020 }
10021
10022 if (INTEL_INFO(dev)->gen >= 9) {
10023 pipe_config->scaler_state.scaler_id = -1;
10024 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10025 }
10026
10027 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10028 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10029 power_domain_mask |= BIT(power_domain);
10030 if (INTEL_INFO(dev)->gen >= 9)
10031 skylake_get_pfit_config(crtc, pipe_config);
10032 else
10033 ironlake_get_pfit_config(crtc, pipe_config);
10034 }
10035
10036 if (IS_HASWELL(dev))
10037 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10038 (I915_READ(IPS_CTL) & IPS_ENABLE);
10039
10040 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10041 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10042 pipe_config->pixel_multiplier =
10043 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10044 } else {
10045 pipe_config->pixel_multiplier = 1;
10046 }
10047
10048 out:
10049 for_each_power_domain(power_domain, power_domain_mask)
10050 intel_display_power_put(dev_priv, power_domain);
10051
10052 return active;
10053 }
10054
10055 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10056 const struct intel_plane_state *plane_state)
10057 {
10058 struct drm_device *dev = crtc->dev;
10059 struct drm_i915_private *dev_priv = dev->dev_private;
10060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10061 uint32_t cntl = 0, size = 0;
10062
10063 if (plane_state && plane_state->visible) {
10064 unsigned int width = plane_state->base.crtc_w;
10065 unsigned int height = plane_state->base.crtc_h;
10066 unsigned int stride = roundup_pow_of_two(width) * 4;
10067
10068 switch (stride) {
10069 default:
10070 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10071 width, stride);
10072 stride = 256;
10073 /* fallthrough */
10074 case 256:
10075 case 512:
10076 case 1024:
10077 case 2048:
10078 break;
10079 }
10080
10081 cntl |= CURSOR_ENABLE |
10082 CURSOR_GAMMA_ENABLE |
10083 CURSOR_FORMAT_ARGB |
10084 CURSOR_STRIDE(stride);
10085
10086 size = (height << 12) | width;
10087 }
10088
10089 if (intel_crtc->cursor_cntl != 0 &&
10090 (intel_crtc->cursor_base != base ||
10091 intel_crtc->cursor_size != size ||
10092 intel_crtc->cursor_cntl != cntl)) {
10093 /* On these chipsets we can only modify the base/size/stride
10094 * whilst the cursor is disabled.
10095 */
10096 I915_WRITE(CURCNTR(PIPE_A), 0);
10097 POSTING_READ(CURCNTR(PIPE_A));
10098 intel_crtc->cursor_cntl = 0;
10099 }
10100
10101 if (intel_crtc->cursor_base != base) {
10102 I915_WRITE(CURBASE(PIPE_A), base);
10103 intel_crtc->cursor_base = base;
10104 }
10105
10106 if (intel_crtc->cursor_size != size) {
10107 I915_WRITE(CURSIZE, size);
10108 intel_crtc->cursor_size = size;
10109 }
10110
10111 if (intel_crtc->cursor_cntl != cntl) {
10112 I915_WRITE(CURCNTR(PIPE_A), cntl);
10113 POSTING_READ(CURCNTR(PIPE_A));
10114 intel_crtc->cursor_cntl = cntl;
10115 }
10116 }
10117
10118 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10119 const struct intel_plane_state *plane_state)
10120 {
10121 struct drm_device *dev = crtc->dev;
10122 struct drm_i915_private *dev_priv = dev->dev_private;
10123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10124 int pipe = intel_crtc->pipe;
10125 uint32_t cntl = 0;
10126
10127 if (plane_state && plane_state->visible) {
10128 cntl = MCURSOR_GAMMA_ENABLE;
10129 switch (plane_state->base.crtc_w) {
10130 case 64:
10131 cntl |= CURSOR_MODE_64_ARGB_AX;
10132 break;
10133 case 128:
10134 cntl |= CURSOR_MODE_128_ARGB_AX;
10135 break;
10136 case 256:
10137 cntl |= CURSOR_MODE_256_ARGB_AX;
10138 break;
10139 default:
10140 MISSING_CASE(plane_state->base.crtc_w);
10141 return;
10142 }
10143 cntl |= pipe << 28; /* Connect to correct pipe */
10144
10145 if (HAS_DDI(dev))
10146 cntl |= CURSOR_PIPE_CSC_ENABLE;
10147
10148 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10149 cntl |= CURSOR_ROTATE_180;
10150 }
10151
10152 if (intel_crtc->cursor_cntl != cntl) {
10153 I915_WRITE(CURCNTR(pipe), cntl);
10154 POSTING_READ(CURCNTR(pipe));
10155 intel_crtc->cursor_cntl = cntl;
10156 }
10157
10158 /* and commit changes on next vblank */
10159 I915_WRITE(CURBASE(pipe), base);
10160 POSTING_READ(CURBASE(pipe));
10161
10162 intel_crtc->cursor_base = base;
10163 }
10164
10165 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10166 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10167 const struct intel_plane_state *plane_state)
10168 {
10169 struct drm_device *dev = crtc->dev;
10170 struct drm_i915_private *dev_priv = dev->dev_private;
10171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10172 int pipe = intel_crtc->pipe;
10173 u32 base = intel_crtc->cursor_addr;
10174 u32 pos = 0;
10175
10176 if (plane_state) {
10177 int x = plane_state->base.crtc_x;
10178 int y = plane_state->base.crtc_y;
10179
10180 if (x < 0) {
10181 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10182 x = -x;
10183 }
10184 pos |= x << CURSOR_X_SHIFT;
10185
10186 if (y < 0) {
10187 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10188 y = -y;
10189 }
10190 pos |= y << CURSOR_Y_SHIFT;
10191
10192 /* ILK+ do this automagically */
10193 if (HAS_GMCH_DISPLAY(dev) &&
10194 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10195 base += (plane_state->base.crtc_h *
10196 plane_state->base.crtc_w - 1) * 4;
10197 }
10198 }
10199
10200 I915_WRITE(CURPOS(pipe), pos);
10201
10202 if (IS_845G(dev) || IS_I865G(dev))
10203 i845_update_cursor(crtc, base, plane_state);
10204 else
10205 i9xx_update_cursor(crtc, base, plane_state);
10206 }
10207
10208 static bool cursor_size_ok(struct drm_device *dev,
10209 uint32_t width, uint32_t height)
10210 {
10211 if (width == 0 || height == 0)
10212 return false;
10213
10214 /*
10215 * 845g/865g are special in that they are only limited by
10216 * the width of their cursors, the height is arbitrary up to
10217 * the precision of the register. Everything else requires
10218 * square cursors, limited to a few power-of-two sizes.
10219 */
10220 if (IS_845G(dev) || IS_I865G(dev)) {
10221 if ((width & 63) != 0)
10222 return false;
10223
10224 if (width > (IS_845G(dev) ? 64 : 512))
10225 return false;
10226
10227 if (height > 1023)
10228 return false;
10229 } else {
10230 switch (width | height) {
10231 case 256:
10232 case 128:
10233 if (IS_GEN2(dev))
10234 return false;
10235 case 64:
10236 break;
10237 default:
10238 return false;
10239 }
10240 }
10241
10242 return true;
10243 }
10244
10245 /* VESA 640x480x72Hz mode to set on the pipe */
10246 static struct drm_display_mode load_detect_mode = {
10247 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10248 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10249 };
10250
10251 struct drm_framebuffer *
10252 __intel_framebuffer_create(struct drm_device *dev,
10253 struct drm_mode_fb_cmd2 *mode_cmd,
10254 struct drm_i915_gem_object *obj)
10255 {
10256 struct intel_framebuffer *intel_fb;
10257 int ret;
10258
10259 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10260 if (!intel_fb)
10261 return ERR_PTR(-ENOMEM);
10262
10263 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10264 if (ret)
10265 goto err;
10266
10267 return &intel_fb->base;
10268
10269 err:
10270 kfree(intel_fb);
10271 return ERR_PTR(ret);
10272 }
10273
10274 static struct drm_framebuffer *
10275 intel_framebuffer_create(struct drm_device *dev,
10276 struct drm_mode_fb_cmd2 *mode_cmd,
10277 struct drm_i915_gem_object *obj)
10278 {
10279 struct drm_framebuffer *fb;
10280 int ret;
10281
10282 ret = i915_mutex_lock_interruptible(dev);
10283 if (ret)
10284 return ERR_PTR(ret);
10285 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10286 mutex_unlock(&dev->struct_mutex);
10287
10288 return fb;
10289 }
10290
10291 static u32
10292 intel_framebuffer_pitch_for_width(int width, int bpp)
10293 {
10294 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10295 return ALIGN(pitch, 64);
10296 }
10297
10298 static u32
10299 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10300 {
10301 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10302 return PAGE_ALIGN(pitch * mode->vdisplay);
10303 }
10304
10305 static struct drm_framebuffer *
10306 intel_framebuffer_create_for_mode(struct drm_device *dev,
10307 struct drm_display_mode *mode,
10308 int depth, int bpp)
10309 {
10310 struct drm_framebuffer *fb;
10311 struct drm_i915_gem_object *obj;
10312 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10313
10314 obj = i915_gem_object_create(dev,
10315 intel_framebuffer_size_for_mode(mode, bpp));
10316 if (IS_ERR(obj))
10317 return ERR_CAST(obj);
10318
10319 mode_cmd.width = mode->hdisplay;
10320 mode_cmd.height = mode->vdisplay;
10321 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10322 bpp);
10323 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10324
10325 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10326 if (IS_ERR(fb))
10327 drm_gem_object_unreference_unlocked(&obj->base);
10328
10329 return fb;
10330 }
10331
10332 static struct drm_framebuffer *
10333 mode_fits_in_fbdev(struct drm_device *dev,
10334 struct drm_display_mode *mode)
10335 {
10336 #ifdef CONFIG_DRM_FBDEV_EMULATION
10337 struct drm_i915_private *dev_priv = dev->dev_private;
10338 struct drm_i915_gem_object *obj;
10339 struct drm_framebuffer *fb;
10340
10341 if (!dev_priv->fbdev)
10342 return NULL;
10343
10344 if (!dev_priv->fbdev->fb)
10345 return NULL;
10346
10347 obj = dev_priv->fbdev->fb->obj;
10348 BUG_ON(!obj);
10349
10350 fb = &dev_priv->fbdev->fb->base;
10351 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10352 fb->bits_per_pixel))
10353 return NULL;
10354
10355 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10356 return NULL;
10357
10358 drm_framebuffer_reference(fb);
10359 return fb;
10360 #else
10361 return NULL;
10362 #endif
10363 }
10364
10365 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10366 struct drm_crtc *crtc,
10367 struct drm_display_mode *mode,
10368 struct drm_framebuffer *fb,
10369 int x, int y)
10370 {
10371 struct drm_plane_state *plane_state;
10372 int hdisplay, vdisplay;
10373 int ret;
10374
10375 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10376 if (IS_ERR(plane_state))
10377 return PTR_ERR(plane_state);
10378
10379 if (mode)
10380 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10381 else
10382 hdisplay = vdisplay = 0;
10383
10384 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10385 if (ret)
10386 return ret;
10387 drm_atomic_set_fb_for_plane(plane_state, fb);
10388 plane_state->crtc_x = 0;
10389 plane_state->crtc_y = 0;
10390 plane_state->crtc_w = hdisplay;
10391 plane_state->crtc_h = vdisplay;
10392 plane_state->src_x = x << 16;
10393 plane_state->src_y = y << 16;
10394 plane_state->src_w = hdisplay << 16;
10395 plane_state->src_h = vdisplay << 16;
10396
10397 return 0;
10398 }
10399
10400 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10401 struct drm_display_mode *mode,
10402 struct intel_load_detect_pipe *old,
10403 struct drm_modeset_acquire_ctx *ctx)
10404 {
10405 struct intel_crtc *intel_crtc;
10406 struct intel_encoder *intel_encoder =
10407 intel_attached_encoder(connector);
10408 struct drm_crtc *possible_crtc;
10409 struct drm_encoder *encoder = &intel_encoder->base;
10410 struct drm_crtc *crtc = NULL;
10411 struct drm_device *dev = encoder->dev;
10412 struct drm_framebuffer *fb;
10413 struct drm_mode_config *config = &dev->mode_config;
10414 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10415 struct drm_connector_state *connector_state;
10416 struct intel_crtc_state *crtc_state;
10417 int ret, i = -1;
10418
10419 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10420 connector->base.id, connector->name,
10421 encoder->base.id, encoder->name);
10422
10423 old->restore_state = NULL;
10424
10425 retry:
10426 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10427 if (ret)
10428 goto fail;
10429
10430 /*
10431 * Algorithm gets a little messy:
10432 *
10433 * - if the connector already has an assigned crtc, use it (but make
10434 * sure it's on first)
10435 *
10436 * - try to find the first unused crtc that can drive this connector,
10437 * and use that if we find one
10438 */
10439
10440 /* See if we already have a CRTC for this connector */
10441 if (connector->state->crtc) {
10442 crtc = connector->state->crtc;
10443
10444 ret = drm_modeset_lock(&crtc->mutex, ctx);
10445 if (ret)
10446 goto fail;
10447
10448 /* Make sure the crtc and connector are running */
10449 goto found;
10450 }
10451
10452 /* Find an unused one (if possible) */
10453 for_each_crtc(dev, possible_crtc) {
10454 i++;
10455 if (!(encoder->possible_crtcs & (1 << i)))
10456 continue;
10457
10458 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10459 if (ret)
10460 goto fail;
10461
10462 if (possible_crtc->state->enable) {
10463 drm_modeset_unlock(&possible_crtc->mutex);
10464 continue;
10465 }
10466
10467 crtc = possible_crtc;
10468 break;
10469 }
10470
10471 /*
10472 * If we didn't find an unused CRTC, don't use any.
10473 */
10474 if (!crtc) {
10475 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10476 goto fail;
10477 }
10478
10479 found:
10480 intel_crtc = to_intel_crtc(crtc);
10481
10482 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10483 if (ret)
10484 goto fail;
10485
10486 state = drm_atomic_state_alloc(dev);
10487 restore_state = drm_atomic_state_alloc(dev);
10488 if (!state || !restore_state) {
10489 ret = -ENOMEM;
10490 goto fail;
10491 }
10492
10493 state->acquire_ctx = ctx;
10494 restore_state->acquire_ctx = ctx;
10495
10496 connector_state = drm_atomic_get_connector_state(state, connector);
10497 if (IS_ERR(connector_state)) {
10498 ret = PTR_ERR(connector_state);
10499 goto fail;
10500 }
10501
10502 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10503 if (ret)
10504 goto fail;
10505
10506 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10507 if (IS_ERR(crtc_state)) {
10508 ret = PTR_ERR(crtc_state);
10509 goto fail;
10510 }
10511
10512 crtc_state->base.active = crtc_state->base.enable = true;
10513
10514 if (!mode)
10515 mode = &load_detect_mode;
10516
10517 /* We need a framebuffer large enough to accommodate all accesses
10518 * that the plane may generate whilst we perform load detection.
10519 * We can not rely on the fbcon either being present (we get called
10520 * during its initialisation to detect all boot displays, or it may
10521 * not even exist) or that it is large enough to satisfy the
10522 * requested mode.
10523 */
10524 fb = mode_fits_in_fbdev(dev, mode);
10525 if (fb == NULL) {
10526 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10527 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10528 } else
10529 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10530 if (IS_ERR(fb)) {
10531 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10532 goto fail;
10533 }
10534
10535 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10536 if (ret)
10537 goto fail;
10538
10539 drm_framebuffer_unreference(fb);
10540
10541 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10542 if (ret)
10543 goto fail;
10544
10545 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10546 if (!ret)
10547 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10548 if (!ret)
10549 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10550 if (ret) {
10551 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10552 goto fail;
10553 }
10554
10555 ret = drm_atomic_commit(state);
10556 if (ret) {
10557 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10558 goto fail;
10559 }
10560
10561 old->restore_state = restore_state;
10562
10563 /* let the connector get through one full cycle before testing */
10564 intel_wait_for_vblank(dev, intel_crtc->pipe);
10565 return true;
10566
10567 fail:
10568 drm_atomic_state_free(state);
10569 drm_atomic_state_free(restore_state);
10570 restore_state = state = NULL;
10571
10572 if (ret == -EDEADLK) {
10573 drm_modeset_backoff(ctx);
10574 goto retry;
10575 }
10576
10577 return false;
10578 }
10579
10580 void intel_release_load_detect_pipe(struct drm_connector *connector,
10581 struct intel_load_detect_pipe *old,
10582 struct drm_modeset_acquire_ctx *ctx)
10583 {
10584 struct intel_encoder *intel_encoder =
10585 intel_attached_encoder(connector);
10586 struct drm_encoder *encoder = &intel_encoder->base;
10587 struct drm_atomic_state *state = old->restore_state;
10588 int ret;
10589
10590 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10591 connector->base.id, connector->name,
10592 encoder->base.id, encoder->name);
10593
10594 if (!state)
10595 return;
10596
10597 ret = drm_atomic_commit(state);
10598 if (ret) {
10599 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10600 drm_atomic_state_free(state);
10601 }
10602 }
10603
10604 static int i9xx_pll_refclk(struct drm_device *dev,
10605 const struct intel_crtc_state *pipe_config)
10606 {
10607 struct drm_i915_private *dev_priv = dev->dev_private;
10608 u32 dpll = pipe_config->dpll_hw_state.dpll;
10609
10610 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10611 return dev_priv->vbt.lvds_ssc_freq;
10612 else if (HAS_PCH_SPLIT(dev))
10613 return 120000;
10614 else if (!IS_GEN2(dev))
10615 return 96000;
10616 else
10617 return 48000;
10618 }
10619
10620 /* Returns the clock of the currently programmed mode of the given pipe. */
10621 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10622 struct intel_crtc_state *pipe_config)
10623 {
10624 struct drm_device *dev = crtc->base.dev;
10625 struct drm_i915_private *dev_priv = dev->dev_private;
10626 int pipe = pipe_config->cpu_transcoder;
10627 u32 dpll = pipe_config->dpll_hw_state.dpll;
10628 u32 fp;
10629 struct dpll clock;
10630 int port_clock;
10631 int refclk = i9xx_pll_refclk(dev, pipe_config);
10632
10633 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10634 fp = pipe_config->dpll_hw_state.fp0;
10635 else
10636 fp = pipe_config->dpll_hw_state.fp1;
10637
10638 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10639 if (IS_PINEVIEW(dev)) {
10640 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10641 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10642 } else {
10643 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10644 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10645 }
10646
10647 if (!IS_GEN2(dev)) {
10648 if (IS_PINEVIEW(dev))
10649 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10650 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10651 else
10652 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10653 DPLL_FPA01_P1_POST_DIV_SHIFT);
10654
10655 switch (dpll & DPLL_MODE_MASK) {
10656 case DPLLB_MODE_DAC_SERIAL:
10657 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10658 5 : 10;
10659 break;
10660 case DPLLB_MODE_LVDS:
10661 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10662 7 : 14;
10663 break;
10664 default:
10665 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10666 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10667 return;
10668 }
10669
10670 if (IS_PINEVIEW(dev))
10671 port_clock = pnv_calc_dpll_params(refclk, &clock);
10672 else
10673 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10674 } else {
10675 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10676 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10677
10678 if (is_lvds) {
10679 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10680 DPLL_FPA01_P1_POST_DIV_SHIFT);
10681
10682 if (lvds & LVDS_CLKB_POWER_UP)
10683 clock.p2 = 7;
10684 else
10685 clock.p2 = 14;
10686 } else {
10687 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10688 clock.p1 = 2;
10689 else {
10690 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10691 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10692 }
10693 if (dpll & PLL_P2_DIVIDE_BY_4)
10694 clock.p2 = 4;
10695 else
10696 clock.p2 = 2;
10697 }
10698
10699 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10700 }
10701
10702 /*
10703 * This value includes pixel_multiplier. We will use
10704 * port_clock to compute adjusted_mode.crtc_clock in the
10705 * encoder's get_config() function.
10706 */
10707 pipe_config->port_clock = port_clock;
10708 }
10709
10710 int intel_dotclock_calculate(int link_freq,
10711 const struct intel_link_m_n *m_n)
10712 {
10713 /*
10714 * The calculation for the data clock is:
10715 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10716 * But we want to avoid losing precison if possible, so:
10717 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10718 *
10719 * and the link clock is simpler:
10720 * link_clock = (m * link_clock) / n
10721 */
10722
10723 if (!m_n->link_n)
10724 return 0;
10725
10726 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10727 }
10728
10729 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10730 struct intel_crtc_state *pipe_config)
10731 {
10732 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10733
10734 /* read out port_clock from the DPLL */
10735 i9xx_crtc_clock_get(crtc, pipe_config);
10736
10737 /*
10738 * In case there is an active pipe without active ports,
10739 * we may need some idea for the dotclock anyway.
10740 * Calculate one based on the FDI configuration.
10741 */
10742 pipe_config->base.adjusted_mode.crtc_clock =
10743 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10744 &pipe_config->fdi_m_n);
10745 }
10746
10747 /** Returns the currently programmed mode of the given pipe. */
10748 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10749 struct drm_crtc *crtc)
10750 {
10751 struct drm_i915_private *dev_priv = dev->dev_private;
10752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10753 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10754 struct drm_display_mode *mode;
10755 struct intel_crtc_state *pipe_config;
10756 int htot = I915_READ(HTOTAL(cpu_transcoder));
10757 int hsync = I915_READ(HSYNC(cpu_transcoder));
10758 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10759 int vsync = I915_READ(VSYNC(cpu_transcoder));
10760 enum pipe pipe = intel_crtc->pipe;
10761
10762 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10763 if (!mode)
10764 return NULL;
10765
10766 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10767 if (!pipe_config) {
10768 kfree(mode);
10769 return NULL;
10770 }
10771
10772 /*
10773 * Construct a pipe_config sufficient for getting the clock info
10774 * back out of crtc_clock_get.
10775 *
10776 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10777 * to use a real value here instead.
10778 */
10779 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10780 pipe_config->pixel_multiplier = 1;
10781 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10782 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10783 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10784 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10785
10786 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10787 mode->hdisplay = (htot & 0xffff) + 1;
10788 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10789 mode->hsync_start = (hsync & 0xffff) + 1;
10790 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10791 mode->vdisplay = (vtot & 0xffff) + 1;
10792 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10793 mode->vsync_start = (vsync & 0xffff) + 1;
10794 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10795
10796 drm_mode_set_name(mode);
10797
10798 kfree(pipe_config);
10799
10800 return mode;
10801 }
10802
10803 void intel_mark_busy(struct drm_i915_private *dev_priv)
10804 {
10805 if (dev_priv->mm.busy)
10806 return;
10807
10808 intel_runtime_pm_get(dev_priv);
10809 i915_update_gfx_val(dev_priv);
10810 if (INTEL_GEN(dev_priv) >= 6)
10811 gen6_rps_busy(dev_priv);
10812 dev_priv->mm.busy = true;
10813 }
10814
10815 void intel_mark_idle(struct drm_i915_private *dev_priv)
10816 {
10817 if (!dev_priv->mm.busy)
10818 return;
10819
10820 dev_priv->mm.busy = false;
10821
10822 if (INTEL_GEN(dev_priv) >= 6)
10823 gen6_rps_idle(dev_priv);
10824
10825 intel_runtime_pm_put(dev_priv);
10826 }
10827
10828 static void intel_crtc_destroy(struct drm_crtc *crtc)
10829 {
10830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10831 struct drm_device *dev = crtc->dev;
10832 struct intel_unpin_work *work;
10833
10834 spin_lock_irq(&dev->event_lock);
10835 work = intel_crtc->unpin_work;
10836 intel_crtc->unpin_work = NULL;
10837 spin_unlock_irq(&dev->event_lock);
10838
10839 if (work) {
10840 cancel_work_sync(&work->work);
10841 kfree(work);
10842 }
10843
10844 drm_crtc_cleanup(crtc);
10845
10846 kfree(intel_crtc);
10847 }
10848
10849 static void intel_unpin_work_fn(struct work_struct *__work)
10850 {
10851 struct intel_unpin_work *work =
10852 container_of(__work, struct intel_unpin_work, work);
10853 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10854 struct drm_device *dev = crtc->base.dev;
10855 struct drm_plane *primary = crtc->base.primary;
10856
10857 mutex_lock(&dev->struct_mutex);
10858 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10859 drm_gem_object_unreference(&work->pending_flip_obj->base);
10860
10861 if (work->flip_queued_req)
10862 i915_gem_request_assign(&work->flip_queued_req, NULL);
10863 mutex_unlock(&dev->struct_mutex);
10864
10865 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10866 intel_fbc_post_update(crtc);
10867 drm_framebuffer_unreference(work->old_fb);
10868
10869 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10870 atomic_dec(&crtc->unpin_work_count);
10871
10872 kfree(work);
10873 }
10874
10875 static void do_intel_finish_page_flip(struct drm_i915_private *dev_priv,
10876 struct drm_crtc *crtc)
10877 {
10878 struct drm_device *dev = dev_priv->dev;
10879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10880 struct intel_unpin_work *work;
10881 unsigned long flags;
10882
10883 /* Ignore early vblank irqs */
10884 if (intel_crtc == NULL)
10885 return;
10886
10887 /*
10888 * This is called both by irq handlers and the reset code (to complete
10889 * lost pageflips) so needs the full irqsave spinlocks.
10890 */
10891 spin_lock_irqsave(&dev->event_lock, flags);
10892 work = intel_crtc->unpin_work;
10893
10894 /* Ensure we don't miss a work->pending update ... */
10895 smp_rmb();
10896
10897 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10898 spin_unlock_irqrestore(&dev->event_lock, flags);
10899 return;
10900 }
10901
10902 page_flip_completed(intel_crtc);
10903
10904 spin_unlock_irqrestore(&dev->event_lock, flags);
10905 }
10906
10907 void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe)
10908 {
10909 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10910
10911 do_intel_finish_page_flip(dev_priv, crtc);
10912 }
10913
10914 void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane)
10915 {
10916 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10917
10918 do_intel_finish_page_flip(dev_priv, crtc);
10919 }
10920
10921 /* Is 'a' after or equal to 'b'? */
10922 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10923 {
10924 return !((a - b) & 0x80000000);
10925 }
10926
10927 static bool page_flip_finished(struct intel_crtc *crtc)
10928 {
10929 struct drm_device *dev = crtc->base.dev;
10930 struct drm_i915_private *dev_priv = dev->dev_private;
10931 unsigned reset_counter;
10932
10933 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10934 if (crtc->reset_counter != reset_counter)
10935 return true;
10936
10937 /*
10938 * The relevant registers doen't exist on pre-ctg.
10939 * As the flip done interrupt doesn't trigger for mmio
10940 * flips on gmch platforms, a flip count check isn't
10941 * really needed there. But since ctg has the registers,
10942 * include it in the check anyway.
10943 */
10944 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10945 return true;
10946
10947 /*
10948 * BDW signals flip done immediately if the plane
10949 * is disabled, even if the plane enable is already
10950 * armed to occur at the next vblank :(
10951 */
10952
10953 /*
10954 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10955 * used the same base address. In that case the mmio flip might
10956 * have completed, but the CS hasn't even executed the flip yet.
10957 *
10958 * A flip count check isn't enough as the CS might have updated
10959 * the base address just after start of vblank, but before we
10960 * managed to process the interrupt. This means we'd complete the
10961 * CS flip too soon.
10962 *
10963 * Combining both checks should get us a good enough result. It may
10964 * still happen that the CS flip has been executed, but has not
10965 * yet actually completed. But in case the base address is the same
10966 * anyway, we don't really care.
10967 */
10968 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10969 crtc->unpin_work->gtt_offset &&
10970 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10971 crtc->unpin_work->flip_count);
10972 }
10973
10974 void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane)
10975 {
10976 struct drm_device *dev = dev_priv->dev;
10977 struct intel_crtc *intel_crtc =
10978 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10979 unsigned long flags;
10980
10981
10982 /*
10983 * This is called both by irq handlers and the reset code (to complete
10984 * lost pageflips) so needs the full irqsave spinlocks.
10985 *
10986 * NB: An MMIO update of the plane base pointer will also
10987 * generate a page-flip completion irq, i.e. every modeset
10988 * is also accompanied by a spurious intel_prepare_page_flip().
10989 */
10990 spin_lock_irqsave(&dev->event_lock, flags);
10991 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10992 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10993 spin_unlock_irqrestore(&dev->event_lock, flags);
10994 }
10995
10996 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10997 {
10998 /* Ensure that the work item is consistent when activating it ... */
10999 smp_wmb();
11000 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11001 /* and that it is marked active as soon as the irq could fire. */
11002 smp_wmb();
11003 }
11004
11005 static int intel_gen2_queue_flip(struct drm_device *dev,
11006 struct drm_crtc *crtc,
11007 struct drm_framebuffer *fb,
11008 struct drm_i915_gem_object *obj,
11009 struct drm_i915_gem_request *req,
11010 uint32_t flags)
11011 {
11012 struct intel_engine_cs *engine = req->engine;
11013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11014 u32 flip_mask;
11015 int ret;
11016
11017 ret = intel_ring_begin(req, 6);
11018 if (ret)
11019 return ret;
11020
11021 /* Can't queue multiple flips, so wait for the previous
11022 * one to finish before executing the next.
11023 */
11024 if (intel_crtc->plane)
11025 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11026 else
11027 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11028 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11029 intel_ring_emit(engine, MI_NOOP);
11030 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11031 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11032 intel_ring_emit(engine, fb->pitches[0]);
11033 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11034 intel_ring_emit(engine, 0); /* aux display base address, unused */
11035
11036 intel_mark_page_flip_active(intel_crtc->unpin_work);
11037 return 0;
11038 }
11039
11040 static int intel_gen3_queue_flip(struct drm_device *dev,
11041 struct drm_crtc *crtc,
11042 struct drm_framebuffer *fb,
11043 struct drm_i915_gem_object *obj,
11044 struct drm_i915_gem_request *req,
11045 uint32_t flags)
11046 {
11047 struct intel_engine_cs *engine = req->engine;
11048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11049 u32 flip_mask;
11050 int ret;
11051
11052 ret = intel_ring_begin(req, 6);
11053 if (ret)
11054 return ret;
11055
11056 if (intel_crtc->plane)
11057 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11058 else
11059 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11060 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11061 intel_ring_emit(engine, MI_NOOP);
11062 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11063 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11064 intel_ring_emit(engine, fb->pitches[0]);
11065 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11066 intel_ring_emit(engine, MI_NOOP);
11067
11068 intel_mark_page_flip_active(intel_crtc->unpin_work);
11069 return 0;
11070 }
11071
11072 static int intel_gen4_queue_flip(struct drm_device *dev,
11073 struct drm_crtc *crtc,
11074 struct drm_framebuffer *fb,
11075 struct drm_i915_gem_object *obj,
11076 struct drm_i915_gem_request *req,
11077 uint32_t flags)
11078 {
11079 struct intel_engine_cs *engine = req->engine;
11080 struct drm_i915_private *dev_priv = dev->dev_private;
11081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11082 uint32_t pf, pipesrc;
11083 int ret;
11084
11085 ret = intel_ring_begin(req, 4);
11086 if (ret)
11087 return ret;
11088
11089 /* i965+ uses the linear or tiled offsets from the
11090 * Display Registers (which do not change across a page-flip)
11091 * so we need only reprogram the base address.
11092 */
11093 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11094 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11095 intel_ring_emit(engine, fb->pitches[0]);
11096 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11097 obj->tiling_mode);
11098
11099 /* XXX Enabling the panel-fitter across page-flip is so far
11100 * untested on non-native modes, so ignore it for now.
11101 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11102 */
11103 pf = 0;
11104 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11105 intel_ring_emit(engine, pf | pipesrc);
11106
11107 intel_mark_page_flip_active(intel_crtc->unpin_work);
11108 return 0;
11109 }
11110
11111 static int intel_gen6_queue_flip(struct drm_device *dev,
11112 struct drm_crtc *crtc,
11113 struct drm_framebuffer *fb,
11114 struct drm_i915_gem_object *obj,
11115 struct drm_i915_gem_request *req,
11116 uint32_t flags)
11117 {
11118 struct intel_engine_cs *engine = req->engine;
11119 struct drm_i915_private *dev_priv = dev->dev_private;
11120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11121 uint32_t pf, pipesrc;
11122 int ret;
11123
11124 ret = intel_ring_begin(req, 4);
11125 if (ret)
11126 return ret;
11127
11128 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11129 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11130 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11131 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11132
11133 /* Contrary to the suggestions in the documentation,
11134 * "Enable Panel Fitter" does not seem to be required when page
11135 * flipping with a non-native mode, and worse causes a normal
11136 * modeset to fail.
11137 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11138 */
11139 pf = 0;
11140 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11141 intel_ring_emit(engine, pf | pipesrc);
11142
11143 intel_mark_page_flip_active(intel_crtc->unpin_work);
11144 return 0;
11145 }
11146
11147 static int intel_gen7_queue_flip(struct drm_device *dev,
11148 struct drm_crtc *crtc,
11149 struct drm_framebuffer *fb,
11150 struct drm_i915_gem_object *obj,
11151 struct drm_i915_gem_request *req,
11152 uint32_t flags)
11153 {
11154 struct intel_engine_cs *engine = req->engine;
11155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11156 uint32_t plane_bit = 0;
11157 int len, ret;
11158
11159 switch (intel_crtc->plane) {
11160 case PLANE_A:
11161 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11162 break;
11163 case PLANE_B:
11164 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11165 break;
11166 case PLANE_C:
11167 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11168 break;
11169 default:
11170 WARN_ONCE(1, "unknown plane in flip command\n");
11171 return -ENODEV;
11172 }
11173
11174 len = 4;
11175 if (engine->id == RCS) {
11176 len += 6;
11177 /*
11178 * On Gen 8, SRM is now taking an extra dword to accommodate
11179 * 48bits addresses, and we need a NOOP for the batch size to
11180 * stay even.
11181 */
11182 if (IS_GEN8(dev))
11183 len += 2;
11184 }
11185
11186 /*
11187 * BSpec MI_DISPLAY_FLIP for IVB:
11188 * "The full packet must be contained within the same cache line."
11189 *
11190 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11191 * cacheline, if we ever start emitting more commands before
11192 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11193 * then do the cacheline alignment, and finally emit the
11194 * MI_DISPLAY_FLIP.
11195 */
11196 ret = intel_ring_cacheline_align(req);
11197 if (ret)
11198 return ret;
11199
11200 ret = intel_ring_begin(req, len);
11201 if (ret)
11202 return ret;
11203
11204 /* Unmask the flip-done completion message. Note that the bspec says that
11205 * we should do this for both the BCS and RCS, and that we must not unmask
11206 * more than one flip event at any time (or ensure that one flip message
11207 * can be sent by waiting for flip-done prior to queueing new flips).
11208 * Experimentation says that BCS works despite DERRMR masking all
11209 * flip-done completion events and that unmasking all planes at once
11210 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11211 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11212 */
11213 if (engine->id == RCS) {
11214 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11215 intel_ring_emit_reg(engine, DERRMR);
11216 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11217 DERRMR_PIPEB_PRI_FLIP_DONE |
11218 DERRMR_PIPEC_PRI_FLIP_DONE));
11219 if (IS_GEN8(dev))
11220 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11221 MI_SRM_LRM_GLOBAL_GTT);
11222 else
11223 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11224 MI_SRM_LRM_GLOBAL_GTT);
11225 intel_ring_emit_reg(engine, DERRMR);
11226 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11227 if (IS_GEN8(dev)) {
11228 intel_ring_emit(engine, 0);
11229 intel_ring_emit(engine, MI_NOOP);
11230 }
11231 }
11232
11233 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11234 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11235 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11236 intel_ring_emit(engine, (MI_NOOP));
11237
11238 intel_mark_page_flip_active(intel_crtc->unpin_work);
11239 return 0;
11240 }
11241
11242 static bool use_mmio_flip(struct intel_engine_cs *engine,
11243 struct drm_i915_gem_object *obj)
11244 {
11245 /*
11246 * This is not being used for older platforms, because
11247 * non-availability of flip done interrupt forces us to use
11248 * CS flips. Older platforms derive flip done using some clever
11249 * tricks involving the flip_pending status bits and vblank irqs.
11250 * So using MMIO flips there would disrupt this mechanism.
11251 */
11252
11253 if (engine == NULL)
11254 return true;
11255
11256 if (INTEL_GEN(engine->i915) < 5)
11257 return false;
11258
11259 if (i915.use_mmio_flip < 0)
11260 return false;
11261 else if (i915.use_mmio_flip > 0)
11262 return true;
11263 else if (i915.enable_execlists)
11264 return true;
11265 else if (obj->base.dma_buf &&
11266 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11267 false))
11268 return true;
11269 else
11270 return engine != i915_gem_request_get_engine(obj->last_write_req);
11271 }
11272
11273 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11274 unsigned int rotation,
11275 struct intel_unpin_work *work)
11276 {
11277 struct drm_device *dev = intel_crtc->base.dev;
11278 struct drm_i915_private *dev_priv = dev->dev_private;
11279 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11280 const enum pipe pipe = intel_crtc->pipe;
11281 u32 ctl, stride, tile_height;
11282
11283 ctl = I915_READ(PLANE_CTL(pipe, 0));
11284 ctl &= ~PLANE_CTL_TILED_MASK;
11285 switch (fb->modifier[0]) {
11286 case DRM_FORMAT_MOD_NONE:
11287 break;
11288 case I915_FORMAT_MOD_X_TILED:
11289 ctl |= PLANE_CTL_TILED_X;
11290 break;
11291 case I915_FORMAT_MOD_Y_TILED:
11292 ctl |= PLANE_CTL_TILED_Y;
11293 break;
11294 case I915_FORMAT_MOD_Yf_TILED:
11295 ctl |= PLANE_CTL_TILED_YF;
11296 break;
11297 default:
11298 MISSING_CASE(fb->modifier[0]);
11299 }
11300
11301 /*
11302 * The stride is either expressed as a multiple of 64 bytes chunks for
11303 * linear buffers or in number of tiles for tiled buffers.
11304 */
11305 if (intel_rotation_90_or_270(rotation)) {
11306 /* stride = Surface height in tiles */
11307 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11308 stride = DIV_ROUND_UP(fb->height, tile_height);
11309 } else {
11310 stride = fb->pitches[0] /
11311 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11312 fb->pixel_format);
11313 }
11314
11315 /*
11316 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11317 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11318 */
11319 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11320 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11321
11322 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11323 POSTING_READ(PLANE_SURF(pipe, 0));
11324 }
11325
11326 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11327 struct intel_unpin_work *work)
11328 {
11329 struct drm_device *dev = intel_crtc->base.dev;
11330 struct drm_i915_private *dev_priv = dev->dev_private;
11331 struct intel_framebuffer *intel_fb =
11332 to_intel_framebuffer(intel_crtc->base.primary->fb);
11333 struct drm_i915_gem_object *obj = intel_fb->obj;
11334 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11335 u32 dspcntr;
11336
11337 dspcntr = I915_READ(reg);
11338
11339 if (obj->tiling_mode != I915_TILING_NONE)
11340 dspcntr |= DISPPLANE_TILED;
11341 else
11342 dspcntr &= ~DISPPLANE_TILED;
11343
11344 I915_WRITE(reg, dspcntr);
11345
11346 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11347 POSTING_READ(DSPSURF(intel_crtc->plane));
11348 }
11349
11350 /*
11351 * XXX: This is the temporary way to update the plane registers until we get
11352 * around to using the usual plane update functions for MMIO flips
11353 */
11354 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11355 {
11356 struct intel_crtc *crtc = mmio_flip->crtc;
11357 struct intel_unpin_work *work;
11358
11359 spin_lock_irq(&crtc->base.dev->event_lock);
11360 work = crtc->unpin_work;
11361 spin_unlock_irq(&crtc->base.dev->event_lock);
11362 if (work == NULL)
11363 return;
11364
11365 intel_mark_page_flip_active(work);
11366
11367 intel_pipe_update_start(crtc);
11368
11369 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11370 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11371 else
11372 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11373 ilk_do_mmio_flip(crtc, work);
11374
11375 intel_pipe_update_end(crtc);
11376 }
11377
11378 static void intel_mmio_flip_work_func(struct work_struct *work)
11379 {
11380 struct intel_mmio_flip *mmio_flip =
11381 container_of(work, struct intel_mmio_flip, work);
11382 struct intel_framebuffer *intel_fb =
11383 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11384 struct drm_i915_gem_object *obj = intel_fb->obj;
11385
11386 if (mmio_flip->req) {
11387 WARN_ON(__i915_wait_request(mmio_flip->req,
11388 false, NULL,
11389 &mmio_flip->i915->rps.mmioflips));
11390 i915_gem_request_unreference(mmio_flip->req);
11391 }
11392
11393 /* For framebuffer backed by dmabuf, wait for fence */
11394 if (obj->base.dma_buf)
11395 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11396 false, false,
11397 MAX_SCHEDULE_TIMEOUT) < 0);
11398
11399 intel_do_mmio_flip(mmio_flip);
11400 kfree(mmio_flip);
11401 }
11402
11403 static int intel_queue_mmio_flip(struct drm_device *dev,
11404 struct drm_crtc *crtc,
11405 struct drm_i915_gem_object *obj)
11406 {
11407 struct intel_mmio_flip *mmio_flip;
11408
11409 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11410 if (mmio_flip == NULL)
11411 return -ENOMEM;
11412
11413 mmio_flip->i915 = to_i915(dev);
11414 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11415 mmio_flip->crtc = to_intel_crtc(crtc);
11416 mmio_flip->rotation = crtc->primary->state->rotation;
11417
11418 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11419 schedule_work(&mmio_flip->work);
11420
11421 return 0;
11422 }
11423
11424 static int intel_default_queue_flip(struct drm_device *dev,
11425 struct drm_crtc *crtc,
11426 struct drm_framebuffer *fb,
11427 struct drm_i915_gem_object *obj,
11428 struct drm_i915_gem_request *req,
11429 uint32_t flags)
11430 {
11431 return -ENODEV;
11432 }
11433
11434 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11435 struct drm_crtc *crtc)
11436 {
11437 struct drm_i915_private *dev_priv = dev->dev_private;
11438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11439 struct intel_unpin_work *work = intel_crtc->unpin_work;
11440 u32 addr;
11441
11442 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11443 return true;
11444
11445 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11446 return false;
11447
11448 if (!work->enable_stall_check)
11449 return false;
11450
11451 if (work->flip_ready_vblank == 0) {
11452 if (work->flip_queued_req &&
11453 !i915_gem_request_completed(work->flip_queued_req, true))
11454 return false;
11455
11456 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11457 }
11458
11459 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11460 return false;
11461
11462 /* Potential stall - if we see that the flip has happened,
11463 * assume a missed interrupt. */
11464 if (INTEL_INFO(dev)->gen >= 4)
11465 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11466 else
11467 addr = I915_READ(DSPADDR(intel_crtc->plane));
11468
11469 /* There is a potential issue here with a false positive after a flip
11470 * to the same address. We could address this by checking for a
11471 * non-incrementing frame counter.
11472 */
11473 return addr == work->gtt_offset;
11474 }
11475
11476 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11477 {
11478 struct drm_device *dev = dev_priv->dev;
11479 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11481 struct intel_unpin_work *work;
11482
11483 WARN_ON(!in_interrupt());
11484
11485 if (crtc == NULL)
11486 return;
11487
11488 spin_lock(&dev->event_lock);
11489 work = intel_crtc->unpin_work;
11490 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11491 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11492 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11493 page_flip_completed(intel_crtc);
11494 work = NULL;
11495 }
11496 if (work != NULL &&
11497 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11498 intel_queue_rps_boost_for_request(work->flip_queued_req);
11499 spin_unlock(&dev->event_lock);
11500 }
11501
11502 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11503 struct drm_framebuffer *fb,
11504 struct drm_pending_vblank_event *event,
11505 uint32_t page_flip_flags)
11506 {
11507 struct drm_device *dev = crtc->dev;
11508 struct drm_i915_private *dev_priv = dev->dev_private;
11509 struct drm_framebuffer *old_fb = crtc->primary->fb;
11510 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11512 struct drm_plane *primary = crtc->primary;
11513 enum pipe pipe = intel_crtc->pipe;
11514 struct intel_unpin_work *work;
11515 struct intel_engine_cs *engine;
11516 bool mmio_flip;
11517 struct drm_i915_gem_request *request = NULL;
11518 int ret;
11519
11520 /*
11521 * drm_mode_page_flip_ioctl() should already catch this, but double
11522 * check to be safe. In the future we may enable pageflipping from
11523 * a disabled primary plane.
11524 */
11525 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11526 return -EBUSY;
11527
11528 /* Can't change pixel format via MI display flips. */
11529 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11530 return -EINVAL;
11531
11532 /*
11533 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11534 * Note that pitch changes could also affect these register.
11535 */
11536 if (INTEL_INFO(dev)->gen > 3 &&
11537 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11538 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11539 return -EINVAL;
11540
11541 if (i915_terminally_wedged(&dev_priv->gpu_error))
11542 goto out_hang;
11543
11544 work = kzalloc(sizeof(*work), GFP_KERNEL);
11545 if (work == NULL)
11546 return -ENOMEM;
11547
11548 work->event = event;
11549 work->crtc = crtc;
11550 work->old_fb = old_fb;
11551 INIT_WORK(&work->work, intel_unpin_work_fn);
11552
11553 ret = drm_crtc_vblank_get(crtc);
11554 if (ret)
11555 goto free_work;
11556
11557 /* We borrow the event spin lock for protecting unpin_work */
11558 spin_lock_irq(&dev->event_lock);
11559 if (intel_crtc->unpin_work) {
11560 /* Before declaring the flip queue wedged, check if
11561 * the hardware completed the operation behind our backs.
11562 */
11563 if (__intel_pageflip_stall_check(dev, crtc)) {
11564 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11565 page_flip_completed(intel_crtc);
11566 } else {
11567 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11568 spin_unlock_irq(&dev->event_lock);
11569
11570 drm_crtc_vblank_put(crtc);
11571 kfree(work);
11572 return -EBUSY;
11573 }
11574 }
11575 intel_crtc->unpin_work = work;
11576 spin_unlock_irq(&dev->event_lock);
11577
11578 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11579 flush_workqueue(dev_priv->wq);
11580
11581 /* Reference the objects for the scheduled work. */
11582 drm_framebuffer_reference(work->old_fb);
11583 drm_gem_object_reference(&obj->base);
11584
11585 crtc->primary->fb = fb;
11586 update_state_fb(crtc->primary);
11587 intel_fbc_pre_update(intel_crtc);
11588
11589 work->pending_flip_obj = obj;
11590
11591 ret = i915_mutex_lock_interruptible(dev);
11592 if (ret)
11593 goto cleanup;
11594
11595 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11596 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11597 ret = -EIO;
11598 goto cleanup;
11599 }
11600
11601 atomic_inc(&intel_crtc->unpin_work_count);
11602
11603 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11604 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11605
11606 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11607 engine = &dev_priv->engine[BCS];
11608 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11609 /* vlv: DISPLAY_FLIP fails to change tiling */
11610 engine = NULL;
11611 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11612 engine = &dev_priv->engine[BCS];
11613 } else if (INTEL_INFO(dev)->gen >= 7) {
11614 engine = i915_gem_request_get_engine(obj->last_write_req);
11615 if (engine == NULL || engine->id != RCS)
11616 engine = &dev_priv->engine[BCS];
11617 } else {
11618 engine = &dev_priv->engine[RCS];
11619 }
11620
11621 mmio_flip = use_mmio_flip(engine, obj);
11622
11623 /* When using CS flips, we want to emit semaphores between rings.
11624 * However, when using mmio flips we will create a task to do the
11625 * synchronisation, so all we want here is to pin the framebuffer
11626 * into the display plane and skip any waits.
11627 */
11628 if (!mmio_flip) {
11629 ret = i915_gem_object_sync(obj, engine, &request);
11630 if (ret)
11631 goto cleanup_pending;
11632 }
11633
11634 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11635 if (ret)
11636 goto cleanup_pending;
11637
11638 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11639 obj, 0);
11640 work->gtt_offset += intel_crtc->dspaddr_offset;
11641
11642 if (mmio_flip) {
11643 ret = intel_queue_mmio_flip(dev, crtc, obj);
11644 if (ret)
11645 goto cleanup_unpin;
11646
11647 i915_gem_request_assign(&work->flip_queued_req,
11648 obj->last_write_req);
11649 } else {
11650 if (!request) {
11651 request = i915_gem_request_alloc(engine, NULL);
11652 if (IS_ERR(request)) {
11653 ret = PTR_ERR(request);
11654 goto cleanup_unpin;
11655 }
11656 }
11657
11658 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11659 page_flip_flags);
11660 if (ret)
11661 goto cleanup_unpin;
11662
11663 i915_gem_request_assign(&work->flip_queued_req, request);
11664 }
11665
11666 if (request)
11667 i915_add_request_no_flush(request);
11668
11669 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11670 work->enable_stall_check = true;
11671
11672 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11673 to_intel_plane(primary)->frontbuffer_bit);
11674 mutex_unlock(&dev->struct_mutex);
11675
11676 intel_frontbuffer_flip_prepare(dev,
11677 to_intel_plane(primary)->frontbuffer_bit);
11678
11679 trace_i915_flip_request(intel_crtc->plane, obj);
11680
11681 return 0;
11682
11683 cleanup_unpin:
11684 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11685 cleanup_pending:
11686 if (!IS_ERR_OR_NULL(request))
11687 i915_add_request_no_flush(request);
11688 atomic_dec(&intel_crtc->unpin_work_count);
11689 mutex_unlock(&dev->struct_mutex);
11690 cleanup:
11691 crtc->primary->fb = old_fb;
11692 update_state_fb(crtc->primary);
11693
11694 drm_gem_object_unreference_unlocked(&obj->base);
11695 drm_framebuffer_unreference(work->old_fb);
11696
11697 spin_lock_irq(&dev->event_lock);
11698 intel_crtc->unpin_work = NULL;
11699 spin_unlock_irq(&dev->event_lock);
11700
11701 drm_crtc_vblank_put(crtc);
11702 free_work:
11703 kfree(work);
11704
11705 if (ret == -EIO) {
11706 struct drm_atomic_state *state;
11707 struct drm_plane_state *plane_state;
11708
11709 out_hang:
11710 state = drm_atomic_state_alloc(dev);
11711 if (!state)
11712 return -ENOMEM;
11713 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11714
11715 retry:
11716 plane_state = drm_atomic_get_plane_state(state, primary);
11717 ret = PTR_ERR_OR_ZERO(plane_state);
11718 if (!ret) {
11719 drm_atomic_set_fb_for_plane(plane_state, fb);
11720
11721 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11722 if (!ret)
11723 ret = drm_atomic_commit(state);
11724 }
11725
11726 if (ret == -EDEADLK) {
11727 drm_modeset_backoff(state->acquire_ctx);
11728 drm_atomic_state_clear(state);
11729 goto retry;
11730 }
11731
11732 if (ret)
11733 drm_atomic_state_free(state);
11734
11735 if (ret == 0 && event) {
11736 spin_lock_irq(&dev->event_lock);
11737 drm_crtc_send_vblank_event(crtc, event);
11738 spin_unlock_irq(&dev->event_lock);
11739 }
11740 }
11741 return ret;
11742 }
11743
11744
11745 /**
11746 * intel_wm_need_update - Check whether watermarks need updating
11747 * @plane: drm plane
11748 * @state: new plane state
11749 *
11750 * Check current plane state versus the new one to determine whether
11751 * watermarks need to be recalculated.
11752 *
11753 * Returns true or false.
11754 */
11755 static bool intel_wm_need_update(struct drm_plane *plane,
11756 struct drm_plane_state *state)
11757 {
11758 struct intel_plane_state *new = to_intel_plane_state(state);
11759 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11760
11761 /* Update watermarks on tiling or size changes. */
11762 if (new->visible != cur->visible)
11763 return true;
11764
11765 if (!cur->base.fb || !new->base.fb)
11766 return false;
11767
11768 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11769 cur->base.rotation != new->base.rotation ||
11770 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11771 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11772 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11773 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11774 return true;
11775
11776 return false;
11777 }
11778
11779 static bool needs_scaling(struct intel_plane_state *state)
11780 {
11781 int src_w = drm_rect_width(&state->src) >> 16;
11782 int src_h = drm_rect_height(&state->src) >> 16;
11783 int dst_w = drm_rect_width(&state->dst);
11784 int dst_h = drm_rect_height(&state->dst);
11785
11786 return (src_w != dst_w || src_h != dst_h);
11787 }
11788
11789 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11790 struct drm_plane_state *plane_state)
11791 {
11792 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11793 struct drm_crtc *crtc = crtc_state->crtc;
11794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11795 struct drm_plane *plane = plane_state->plane;
11796 struct drm_device *dev = crtc->dev;
11797 struct drm_i915_private *dev_priv = to_i915(dev);
11798 struct intel_plane_state *old_plane_state =
11799 to_intel_plane_state(plane->state);
11800 int idx = intel_crtc->base.base.id, ret;
11801 bool mode_changed = needs_modeset(crtc_state);
11802 bool was_crtc_enabled = crtc->state->active;
11803 bool is_crtc_enabled = crtc_state->active;
11804 bool turn_off, turn_on, visible, was_visible;
11805 struct drm_framebuffer *fb = plane_state->fb;
11806
11807 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11808 plane->type != DRM_PLANE_TYPE_CURSOR) {
11809 ret = skl_update_scaler_plane(
11810 to_intel_crtc_state(crtc_state),
11811 to_intel_plane_state(plane_state));
11812 if (ret)
11813 return ret;
11814 }
11815
11816 was_visible = old_plane_state->visible;
11817 visible = to_intel_plane_state(plane_state)->visible;
11818
11819 if (!was_crtc_enabled && WARN_ON(was_visible))
11820 was_visible = false;
11821
11822 /*
11823 * Visibility is calculated as if the crtc was on, but
11824 * after scaler setup everything depends on it being off
11825 * when the crtc isn't active.
11826 *
11827 * FIXME this is wrong for watermarks. Watermarks should also
11828 * be computed as if the pipe would be active. Perhaps move
11829 * per-plane wm computation to the .check_plane() hook, and
11830 * only combine the results from all planes in the current place?
11831 */
11832 if (!is_crtc_enabled)
11833 to_intel_plane_state(plane_state)->visible = visible = false;
11834
11835 if (!was_visible && !visible)
11836 return 0;
11837
11838 if (fb != old_plane_state->base.fb)
11839 pipe_config->fb_changed = true;
11840
11841 turn_off = was_visible && (!visible || mode_changed);
11842 turn_on = visible && (!was_visible || mode_changed);
11843
11844 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11845 plane->base.id, fb ? fb->base.id : -1);
11846
11847 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11848 plane->base.id, was_visible, visible,
11849 turn_off, turn_on, mode_changed);
11850
11851 if (turn_on) {
11852 pipe_config->update_wm_pre = true;
11853
11854 /* must disable cxsr around plane enable/disable */
11855 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11856 pipe_config->disable_cxsr = true;
11857 } else if (turn_off) {
11858 pipe_config->update_wm_post = true;
11859
11860 /* must disable cxsr around plane enable/disable */
11861 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11862 pipe_config->disable_cxsr = true;
11863 } else if (intel_wm_need_update(plane, plane_state)) {
11864 /* FIXME bollocks */
11865 pipe_config->update_wm_pre = true;
11866 pipe_config->update_wm_post = true;
11867 }
11868
11869 /* Pre-gen9 platforms need two-step watermark updates */
11870 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11871 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11872 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11873
11874 if (visible || was_visible)
11875 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11876
11877 /*
11878 * WaCxSRDisabledForSpriteScaling:ivb
11879 *
11880 * cstate->update_wm was already set above, so this flag will
11881 * take effect when we commit and program watermarks.
11882 */
11883 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11884 needs_scaling(to_intel_plane_state(plane_state)) &&
11885 !needs_scaling(old_plane_state))
11886 pipe_config->disable_lp_wm = true;
11887
11888 return 0;
11889 }
11890
11891 static bool encoders_cloneable(const struct intel_encoder *a,
11892 const struct intel_encoder *b)
11893 {
11894 /* masks could be asymmetric, so check both ways */
11895 return a == b || (a->cloneable & (1 << b->type) &&
11896 b->cloneable & (1 << a->type));
11897 }
11898
11899 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11900 struct intel_crtc *crtc,
11901 struct intel_encoder *encoder)
11902 {
11903 struct intel_encoder *source_encoder;
11904 struct drm_connector *connector;
11905 struct drm_connector_state *connector_state;
11906 int i;
11907
11908 for_each_connector_in_state(state, connector, connector_state, i) {
11909 if (connector_state->crtc != &crtc->base)
11910 continue;
11911
11912 source_encoder =
11913 to_intel_encoder(connector_state->best_encoder);
11914 if (!encoders_cloneable(encoder, source_encoder))
11915 return false;
11916 }
11917
11918 return true;
11919 }
11920
11921 static bool check_encoder_cloning(struct drm_atomic_state *state,
11922 struct intel_crtc *crtc)
11923 {
11924 struct intel_encoder *encoder;
11925 struct drm_connector *connector;
11926 struct drm_connector_state *connector_state;
11927 int i;
11928
11929 for_each_connector_in_state(state, connector, connector_state, i) {
11930 if (connector_state->crtc != &crtc->base)
11931 continue;
11932
11933 encoder = to_intel_encoder(connector_state->best_encoder);
11934 if (!check_single_encoder_cloning(state, crtc, encoder))
11935 return false;
11936 }
11937
11938 return true;
11939 }
11940
11941 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11942 struct drm_crtc_state *crtc_state)
11943 {
11944 struct drm_device *dev = crtc->dev;
11945 struct drm_i915_private *dev_priv = dev->dev_private;
11946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11947 struct intel_crtc_state *pipe_config =
11948 to_intel_crtc_state(crtc_state);
11949 struct drm_atomic_state *state = crtc_state->state;
11950 int ret;
11951 bool mode_changed = needs_modeset(crtc_state);
11952
11953 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11954 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11955 return -EINVAL;
11956 }
11957
11958 if (mode_changed && !crtc_state->active)
11959 pipe_config->update_wm_post = true;
11960
11961 if (mode_changed && crtc_state->enable &&
11962 dev_priv->display.crtc_compute_clock &&
11963 !WARN_ON(pipe_config->shared_dpll)) {
11964 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11965 pipe_config);
11966 if (ret)
11967 return ret;
11968 }
11969
11970 if (crtc_state->color_mgmt_changed) {
11971 ret = intel_color_check(crtc, crtc_state);
11972 if (ret)
11973 return ret;
11974 }
11975
11976 ret = 0;
11977 if (dev_priv->display.compute_pipe_wm) {
11978 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11979 if (ret) {
11980 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11981 return ret;
11982 }
11983 }
11984
11985 if (dev_priv->display.compute_intermediate_wm &&
11986 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11987 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11988 return 0;
11989
11990 /*
11991 * Calculate 'intermediate' watermarks that satisfy both the
11992 * old state and the new state. We can program these
11993 * immediately.
11994 */
11995 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11996 intel_crtc,
11997 pipe_config);
11998 if (ret) {
11999 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12000 return ret;
12001 }
12002 }
12003
12004 if (INTEL_INFO(dev)->gen >= 9) {
12005 if (mode_changed)
12006 ret = skl_update_scaler_crtc(pipe_config);
12007
12008 if (!ret)
12009 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12010 pipe_config);
12011 }
12012
12013 return ret;
12014 }
12015
12016 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12017 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12018 .atomic_begin = intel_begin_crtc_commit,
12019 .atomic_flush = intel_finish_crtc_commit,
12020 .atomic_check = intel_crtc_atomic_check,
12021 };
12022
12023 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12024 {
12025 struct intel_connector *connector;
12026
12027 for_each_intel_connector(dev, connector) {
12028 if (connector->base.encoder) {
12029 connector->base.state->best_encoder =
12030 connector->base.encoder;
12031 connector->base.state->crtc =
12032 connector->base.encoder->crtc;
12033 } else {
12034 connector->base.state->best_encoder = NULL;
12035 connector->base.state->crtc = NULL;
12036 }
12037 }
12038 }
12039
12040 static void
12041 connected_sink_compute_bpp(struct intel_connector *connector,
12042 struct intel_crtc_state *pipe_config)
12043 {
12044 int bpp = pipe_config->pipe_bpp;
12045
12046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12047 connector->base.base.id,
12048 connector->base.name);
12049
12050 /* Don't use an invalid EDID bpc value */
12051 if (connector->base.display_info.bpc &&
12052 connector->base.display_info.bpc * 3 < bpp) {
12053 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12054 bpp, connector->base.display_info.bpc*3);
12055 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12056 }
12057
12058 /* Clamp bpp to default limit on screens without EDID 1.4 */
12059 if (connector->base.display_info.bpc == 0) {
12060 int type = connector->base.connector_type;
12061 int clamp_bpp = 24;
12062
12063 /* Fall back to 18 bpp when DP sink capability is unknown. */
12064 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12065 type == DRM_MODE_CONNECTOR_eDP)
12066 clamp_bpp = 18;
12067
12068 if (bpp > clamp_bpp) {
12069 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12070 bpp, clamp_bpp);
12071 pipe_config->pipe_bpp = clamp_bpp;
12072 }
12073 }
12074 }
12075
12076 static int
12077 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12078 struct intel_crtc_state *pipe_config)
12079 {
12080 struct drm_device *dev = crtc->base.dev;
12081 struct drm_atomic_state *state;
12082 struct drm_connector *connector;
12083 struct drm_connector_state *connector_state;
12084 int bpp, i;
12085
12086 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12087 bpp = 10*3;
12088 else if (INTEL_INFO(dev)->gen >= 5)
12089 bpp = 12*3;
12090 else
12091 bpp = 8*3;
12092
12093
12094 pipe_config->pipe_bpp = bpp;
12095
12096 state = pipe_config->base.state;
12097
12098 /* Clamp display bpp to EDID value */
12099 for_each_connector_in_state(state, connector, connector_state, i) {
12100 if (connector_state->crtc != &crtc->base)
12101 continue;
12102
12103 connected_sink_compute_bpp(to_intel_connector(connector),
12104 pipe_config);
12105 }
12106
12107 return bpp;
12108 }
12109
12110 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12111 {
12112 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12113 "type: 0x%x flags: 0x%x\n",
12114 mode->crtc_clock,
12115 mode->crtc_hdisplay, mode->crtc_hsync_start,
12116 mode->crtc_hsync_end, mode->crtc_htotal,
12117 mode->crtc_vdisplay, mode->crtc_vsync_start,
12118 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12119 }
12120
12121 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12122 struct intel_crtc_state *pipe_config,
12123 const char *context)
12124 {
12125 struct drm_device *dev = crtc->base.dev;
12126 struct drm_plane *plane;
12127 struct intel_plane *intel_plane;
12128 struct intel_plane_state *state;
12129 struct drm_framebuffer *fb;
12130
12131 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12132 context, pipe_config, pipe_name(crtc->pipe));
12133
12134 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12135 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12136 pipe_config->pipe_bpp, pipe_config->dither);
12137 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12138 pipe_config->has_pch_encoder,
12139 pipe_config->fdi_lanes,
12140 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12141 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12142 pipe_config->fdi_m_n.tu);
12143 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12144 pipe_config->has_dp_encoder,
12145 pipe_config->lane_count,
12146 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12147 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12148 pipe_config->dp_m_n.tu);
12149
12150 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12151 pipe_config->has_dp_encoder,
12152 pipe_config->lane_count,
12153 pipe_config->dp_m2_n2.gmch_m,
12154 pipe_config->dp_m2_n2.gmch_n,
12155 pipe_config->dp_m2_n2.link_m,
12156 pipe_config->dp_m2_n2.link_n,
12157 pipe_config->dp_m2_n2.tu);
12158
12159 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12160 pipe_config->has_audio,
12161 pipe_config->has_infoframe);
12162
12163 DRM_DEBUG_KMS("requested mode:\n");
12164 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12165 DRM_DEBUG_KMS("adjusted mode:\n");
12166 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12167 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12168 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12169 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12170 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12171 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12172 crtc->num_scalers,
12173 pipe_config->scaler_state.scaler_users,
12174 pipe_config->scaler_state.scaler_id);
12175 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12176 pipe_config->gmch_pfit.control,
12177 pipe_config->gmch_pfit.pgm_ratios,
12178 pipe_config->gmch_pfit.lvds_border_bits);
12179 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12180 pipe_config->pch_pfit.pos,
12181 pipe_config->pch_pfit.size,
12182 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12183 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12184 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12185
12186 if (IS_BROXTON(dev)) {
12187 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12188 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12189 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12190 pipe_config->ddi_pll_sel,
12191 pipe_config->dpll_hw_state.ebb0,
12192 pipe_config->dpll_hw_state.ebb4,
12193 pipe_config->dpll_hw_state.pll0,
12194 pipe_config->dpll_hw_state.pll1,
12195 pipe_config->dpll_hw_state.pll2,
12196 pipe_config->dpll_hw_state.pll3,
12197 pipe_config->dpll_hw_state.pll6,
12198 pipe_config->dpll_hw_state.pll8,
12199 pipe_config->dpll_hw_state.pll9,
12200 pipe_config->dpll_hw_state.pll10,
12201 pipe_config->dpll_hw_state.pcsdw12);
12202 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12203 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12204 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12205 pipe_config->ddi_pll_sel,
12206 pipe_config->dpll_hw_state.ctrl1,
12207 pipe_config->dpll_hw_state.cfgcr1,
12208 pipe_config->dpll_hw_state.cfgcr2);
12209 } else if (HAS_DDI(dev)) {
12210 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12211 pipe_config->ddi_pll_sel,
12212 pipe_config->dpll_hw_state.wrpll,
12213 pipe_config->dpll_hw_state.spll);
12214 } else {
12215 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12216 "fp0: 0x%x, fp1: 0x%x\n",
12217 pipe_config->dpll_hw_state.dpll,
12218 pipe_config->dpll_hw_state.dpll_md,
12219 pipe_config->dpll_hw_state.fp0,
12220 pipe_config->dpll_hw_state.fp1);
12221 }
12222
12223 DRM_DEBUG_KMS("planes on this crtc\n");
12224 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12225 intel_plane = to_intel_plane(plane);
12226 if (intel_plane->pipe != crtc->pipe)
12227 continue;
12228
12229 state = to_intel_plane_state(plane->state);
12230 fb = state->base.fb;
12231 if (!fb) {
12232 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12233 "disabled, scaler_id = %d\n",
12234 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12235 plane->base.id, intel_plane->pipe,
12236 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12237 drm_plane_index(plane), state->scaler_id);
12238 continue;
12239 }
12240
12241 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12242 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12243 plane->base.id, intel_plane->pipe,
12244 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12245 drm_plane_index(plane));
12246 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12247 fb->base.id, fb->width, fb->height, fb->pixel_format);
12248 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12249 state->scaler_id,
12250 state->src.x1 >> 16, state->src.y1 >> 16,
12251 drm_rect_width(&state->src) >> 16,
12252 drm_rect_height(&state->src) >> 16,
12253 state->dst.x1, state->dst.y1,
12254 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12255 }
12256 }
12257
12258 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12259 {
12260 struct drm_device *dev = state->dev;
12261 struct drm_connector *connector;
12262 unsigned int used_ports = 0;
12263
12264 /*
12265 * Walk the connector list instead of the encoder
12266 * list to detect the problem on ddi platforms
12267 * where there's just one encoder per digital port.
12268 */
12269 drm_for_each_connector(connector, dev) {
12270 struct drm_connector_state *connector_state;
12271 struct intel_encoder *encoder;
12272
12273 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12274 if (!connector_state)
12275 connector_state = connector->state;
12276
12277 if (!connector_state->best_encoder)
12278 continue;
12279
12280 encoder = to_intel_encoder(connector_state->best_encoder);
12281
12282 WARN_ON(!connector_state->crtc);
12283
12284 switch (encoder->type) {
12285 unsigned int port_mask;
12286 case INTEL_OUTPUT_UNKNOWN:
12287 if (WARN_ON(!HAS_DDI(dev)))
12288 break;
12289 case INTEL_OUTPUT_DISPLAYPORT:
12290 case INTEL_OUTPUT_HDMI:
12291 case INTEL_OUTPUT_EDP:
12292 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12293
12294 /* the same port mustn't appear more than once */
12295 if (used_ports & port_mask)
12296 return false;
12297
12298 used_ports |= port_mask;
12299 default:
12300 break;
12301 }
12302 }
12303
12304 return true;
12305 }
12306
12307 static void
12308 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12309 {
12310 struct drm_crtc_state tmp_state;
12311 struct intel_crtc_scaler_state scaler_state;
12312 struct intel_dpll_hw_state dpll_hw_state;
12313 struct intel_shared_dpll *shared_dpll;
12314 uint32_t ddi_pll_sel;
12315 bool force_thru;
12316
12317 /* FIXME: before the switch to atomic started, a new pipe_config was
12318 * kzalloc'd. Code that depends on any field being zero should be
12319 * fixed, so that the crtc_state can be safely duplicated. For now,
12320 * only fields that are know to not cause problems are preserved. */
12321
12322 tmp_state = crtc_state->base;
12323 scaler_state = crtc_state->scaler_state;
12324 shared_dpll = crtc_state->shared_dpll;
12325 dpll_hw_state = crtc_state->dpll_hw_state;
12326 ddi_pll_sel = crtc_state->ddi_pll_sel;
12327 force_thru = crtc_state->pch_pfit.force_thru;
12328
12329 memset(crtc_state, 0, sizeof *crtc_state);
12330
12331 crtc_state->base = tmp_state;
12332 crtc_state->scaler_state = scaler_state;
12333 crtc_state->shared_dpll = shared_dpll;
12334 crtc_state->dpll_hw_state = dpll_hw_state;
12335 crtc_state->ddi_pll_sel = ddi_pll_sel;
12336 crtc_state->pch_pfit.force_thru = force_thru;
12337 }
12338
12339 static int
12340 intel_modeset_pipe_config(struct drm_crtc *crtc,
12341 struct intel_crtc_state *pipe_config)
12342 {
12343 struct drm_atomic_state *state = pipe_config->base.state;
12344 struct intel_encoder *encoder;
12345 struct drm_connector *connector;
12346 struct drm_connector_state *connector_state;
12347 int base_bpp, ret = -EINVAL;
12348 int i;
12349 bool retry = true;
12350
12351 clear_intel_crtc_state(pipe_config);
12352
12353 pipe_config->cpu_transcoder =
12354 (enum transcoder) to_intel_crtc(crtc)->pipe;
12355
12356 /*
12357 * Sanitize sync polarity flags based on requested ones. If neither
12358 * positive or negative polarity is requested, treat this as meaning
12359 * negative polarity.
12360 */
12361 if (!(pipe_config->base.adjusted_mode.flags &
12362 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12363 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12364
12365 if (!(pipe_config->base.adjusted_mode.flags &
12366 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12367 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12368
12369 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12370 pipe_config);
12371 if (base_bpp < 0)
12372 goto fail;
12373
12374 /*
12375 * Determine the real pipe dimensions. Note that stereo modes can
12376 * increase the actual pipe size due to the frame doubling and
12377 * insertion of additional space for blanks between the frame. This
12378 * is stored in the crtc timings. We use the requested mode to do this
12379 * computation to clearly distinguish it from the adjusted mode, which
12380 * can be changed by the connectors in the below retry loop.
12381 */
12382 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12383 &pipe_config->pipe_src_w,
12384 &pipe_config->pipe_src_h);
12385
12386 encoder_retry:
12387 /* Ensure the port clock defaults are reset when retrying. */
12388 pipe_config->port_clock = 0;
12389 pipe_config->pixel_multiplier = 1;
12390
12391 /* Fill in default crtc timings, allow encoders to overwrite them. */
12392 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12393 CRTC_STEREO_DOUBLE);
12394
12395 /* Pass our mode to the connectors and the CRTC to give them a chance to
12396 * adjust it according to limitations or connector properties, and also
12397 * a chance to reject the mode entirely.
12398 */
12399 for_each_connector_in_state(state, connector, connector_state, i) {
12400 if (connector_state->crtc != crtc)
12401 continue;
12402
12403 encoder = to_intel_encoder(connector_state->best_encoder);
12404
12405 if (!(encoder->compute_config(encoder, pipe_config))) {
12406 DRM_DEBUG_KMS("Encoder config failure\n");
12407 goto fail;
12408 }
12409 }
12410
12411 /* Set default port clock if not overwritten by the encoder. Needs to be
12412 * done afterwards in case the encoder adjusts the mode. */
12413 if (!pipe_config->port_clock)
12414 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12415 * pipe_config->pixel_multiplier;
12416
12417 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12418 if (ret < 0) {
12419 DRM_DEBUG_KMS("CRTC fixup failed\n");
12420 goto fail;
12421 }
12422
12423 if (ret == RETRY) {
12424 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12425 ret = -EINVAL;
12426 goto fail;
12427 }
12428
12429 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12430 retry = false;
12431 goto encoder_retry;
12432 }
12433
12434 /* Dithering seems to not pass-through bits correctly when it should, so
12435 * only enable it on 6bpc panels. */
12436 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12437 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12438 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12439
12440 fail:
12441 return ret;
12442 }
12443
12444 static void
12445 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12446 {
12447 struct drm_crtc *crtc;
12448 struct drm_crtc_state *crtc_state;
12449 int i;
12450
12451 /* Double check state. */
12452 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12453 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12454
12455 /* Update hwmode for vblank functions */
12456 if (crtc->state->active)
12457 crtc->hwmode = crtc->state->adjusted_mode;
12458 else
12459 crtc->hwmode.crtc_clock = 0;
12460
12461 /*
12462 * Update legacy state to satisfy fbc code. This can
12463 * be removed when fbc uses the atomic state.
12464 */
12465 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12466 struct drm_plane_state *plane_state = crtc->primary->state;
12467
12468 crtc->primary->fb = plane_state->fb;
12469 crtc->x = plane_state->src_x >> 16;
12470 crtc->y = plane_state->src_y >> 16;
12471 }
12472 }
12473 }
12474
12475 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12476 {
12477 int diff;
12478
12479 if (clock1 == clock2)
12480 return true;
12481
12482 if (!clock1 || !clock2)
12483 return false;
12484
12485 diff = abs(clock1 - clock2);
12486
12487 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12488 return true;
12489
12490 return false;
12491 }
12492
12493 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12494 list_for_each_entry((intel_crtc), \
12495 &(dev)->mode_config.crtc_list, \
12496 base.head) \
12497 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12498
12499 static bool
12500 intel_compare_m_n(unsigned int m, unsigned int n,
12501 unsigned int m2, unsigned int n2,
12502 bool exact)
12503 {
12504 if (m == m2 && n == n2)
12505 return true;
12506
12507 if (exact || !m || !n || !m2 || !n2)
12508 return false;
12509
12510 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12511
12512 if (n > n2) {
12513 while (n > n2) {
12514 m2 <<= 1;
12515 n2 <<= 1;
12516 }
12517 } else if (n < n2) {
12518 while (n < n2) {
12519 m <<= 1;
12520 n <<= 1;
12521 }
12522 }
12523
12524 if (n != n2)
12525 return false;
12526
12527 return intel_fuzzy_clock_check(m, m2);
12528 }
12529
12530 static bool
12531 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12532 struct intel_link_m_n *m2_n2,
12533 bool adjust)
12534 {
12535 if (m_n->tu == m2_n2->tu &&
12536 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12537 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12538 intel_compare_m_n(m_n->link_m, m_n->link_n,
12539 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12540 if (adjust)
12541 *m2_n2 = *m_n;
12542
12543 return true;
12544 }
12545
12546 return false;
12547 }
12548
12549 static bool
12550 intel_pipe_config_compare(struct drm_device *dev,
12551 struct intel_crtc_state *current_config,
12552 struct intel_crtc_state *pipe_config,
12553 bool adjust)
12554 {
12555 bool ret = true;
12556
12557 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12558 do { \
12559 if (!adjust) \
12560 DRM_ERROR(fmt, ##__VA_ARGS__); \
12561 else \
12562 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12563 } while (0)
12564
12565 #define PIPE_CONF_CHECK_X(name) \
12566 if (current_config->name != pipe_config->name) { \
12567 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12568 "(expected 0x%08x, found 0x%08x)\n", \
12569 current_config->name, \
12570 pipe_config->name); \
12571 ret = false; \
12572 }
12573
12574 #define PIPE_CONF_CHECK_I(name) \
12575 if (current_config->name != pipe_config->name) { \
12576 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12577 "(expected %i, found %i)\n", \
12578 current_config->name, \
12579 pipe_config->name); \
12580 ret = false; \
12581 }
12582
12583 #define PIPE_CONF_CHECK_P(name) \
12584 if (current_config->name != pipe_config->name) { \
12585 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12586 "(expected %p, found %p)\n", \
12587 current_config->name, \
12588 pipe_config->name); \
12589 ret = false; \
12590 }
12591
12592 #define PIPE_CONF_CHECK_M_N(name) \
12593 if (!intel_compare_link_m_n(&current_config->name, \
12594 &pipe_config->name,\
12595 adjust)) { \
12596 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12597 "(expected tu %i gmch %i/%i link %i/%i, " \
12598 "found tu %i, gmch %i/%i link %i/%i)\n", \
12599 current_config->name.tu, \
12600 current_config->name.gmch_m, \
12601 current_config->name.gmch_n, \
12602 current_config->name.link_m, \
12603 current_config->name.link_n, \
12604 pipe_config->name.tu, \
12605 pipe_config->name.gmch_m, \
12606 pipe_config->name.gmch_n, \
12607 pipe_config->name.link_m, \
12608 pipe_config->name.link_n); \
12609 ret = false; \
12610 }
12611
12612 /* This is required for BDW+ where there is only one set of registers for
12613 * switching between high and low RR.
12614 * This macro can be used whenever a comparison has to be made between one
12615 * hw state and multiple sw state variables.
12616 */
12617 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12618 if (!intel_compare_link_m_n(&current_config->name, \
12619 &pipe_config->name, adjust) && \
12620 !intel_compare_link_m_n(&current_config->alt_name, \
12621 &pipe_config->name, adjust)) { \
12622 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12623 "(expected tu %i gmch %i/%i link %i/%i, " \
12624 "or tu %i gmch %i/%i link %i/%i, " \
12625 "found tu %i, gmch %i/%i link %i/%i)\n", \
12626 current_config->name.tu, \
12627 current_config->name.gmch_m, \
12628 current_config->name.gmch_n, \
12629 current_config->name.link_m, \
12630 current_config->name.link_n, \
12631 current_config->alt_name.tu, \
12632 current_config->alt_name.gmch_m, \
12633 current_config->alt_name.gmch_n, \
12634 current_config->alt_name.link_m, \
12635 current_config->alt_name.link_n, \
12636 pipe_config->name.tu, \
12637 pipe_config->name.gmch_m, \
12638 pipe_config->name.gmch_n, \
12639 pipe_config->name.link_m, \
12640 pipe_config->name.link_n); \
12641 ret = false; \
12642 }
12643
12644 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12645 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12646 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12647 "(expected %i, found %i)\n", \
12648 current_config->name & (mask), \
12649 pipe_config->name & (mask)); \
12650 ret = false; \
12651 }
12652
12653 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12654 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12655 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12656 "(expected %i, found %i)\n", \
12657 current_config->name, \
12658 pipe_config->name); \
12659 ret = false; \
12660 }
12661
12662 #define PIPE_CONF_QUIRK(quirk) \
12663 ((current_config->quirks | pipe_config->quirks) & (quirk))
12664
12665 PIPE_CONF_CHECK_I(cpu_transcoder);
12666
12667 PIPE_CONF_CHECK_I(has_pch_encoder);
12668 PIPE_CONF_CHECK_I(fdi_lanes);
12669 PIPE_CONF_CHECK_M_N(fdi_m_n);
12670
12671 PIPE_CONF_CHECK_I(has_dp_encoder);
12672 PIPE_CONF_CHECK_I(lane_count);
12673
12674 if (INTEL_INFO(dev)->gen < 8) {
12675 PIPE_CONF_CHECK_M_N(dp_m_n);
12676
12677 if (current_config->has_drrs)
12678 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12679 } else
12680 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12681
12682 PIPE_CONF_CHECK_I(has_dsi_encoder);
12683
12684 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12685 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12686 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12687 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12690
12691 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12694 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12697
12698 PIPE_CONF_CHECK_I(pixel_multiplier);
12699 PIPE_CONF_CHECK_I(has_hdmi_sink);
12700 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12701 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12702 PIPE_CONF_CHECK_I(limited_color_range);
12703 PIPE_CONF_CHECK_I(has_infoframe);
12704
12705 PIPE_CONF_CHECK_I(has_audio);
12706
12707 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12708 DRM_MODE_FLAG_INTERLACE);
12709
12710 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12711 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12712 DRM_MODE_FLAG_PHSYNC);
12713 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12714 DRM_MODE_FLAG_NHSYNC);
12715 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12716 DRM_MODE_FLAG_PVSYNC);
12717 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12718 DRM_MODE_FLAG_NVSYNC);
12719 }
12720
12721 PIPE_CONF_CHECK_X(gmch_pfit.control);
12722 /* pfit ratios are autocomputed by the hw on gen4+ */
12723 if (INTEL_INFO(dev)->gen < 4)
12724 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12725 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12726
12727 if (!adjust) {
12728 PIPE_CONF_CHECK_I(pipe_src_w);
12729 PIPE_CONF_CHECK_I(pipe_src_h);
12730
12731 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12732 if (current_config->pch_pfit.enabled) {
12733 PIPE_CONF_CHECK_X(pch_pfit.pos);
12734 PIPE_CONF_CHECK_X(pch_pfit.size);
12735 }
12736
12737 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12738 }
12739
12740 /* BDW+ don't expose a synchronous way to read the state */
12741 if (IS_HASWELL(dev))
12742 PIPE_CONF_CHECK_I(ips_enabled);
12743
12744 PIPE_CONF_CHECK_I(double_wide);
12745
12746 PIPE_CONF_CHECK_X(ddi_pll_sel);
12747
12748 PIPE_CONF_CHECK_P(shared_dpll);
12749 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12750 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12751 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12752 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12753 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12754 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12755 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12756 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12757 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12758
12759 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12760 PIPE_CONF_CHECK_X(dsi_pll.div);
12761
12762 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12763 PIPE_CONF_CHECK_I(pipe_bpp);
12764
12765 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12766 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12767
12768 #undef PIPE_CONF_CHECK_X
12769 #undef PIPE_CONF_CHECK_I
12770 #undef PIPE_CONF_CHECK_P
12771 #undef PIPE_CONF_CHECK_FLAGS
12772 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12773 #undef PIPE_CONF_QUIRK
12774 #undef INTEL_ERR_OR_DBG_KMS
12775
12776 return ret;
12777 }
12778
12779 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12780 const struct intel_crtc_state *pipe_config)
12781 {
12782 if (pipe_config->has_pch_encoder) {
12783 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12784 &pipe_config->fdi_m_n);
12785 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12786
12787 /*
12788 * FDI already provided one idea for the dotclock.
12789 * Yell if the encoder disagrees.
12790 */
12791 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12792 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12793 fdi_dotclock, dotclock);
12794 }
12795 }
12796
12797 static void verify_wm_state(struct drm_crtc *crtc,
12798 struct drm_crtc_state *new_state)
12799 {
12800 struct drm_device *dev = crtc->dev;
12801 struct drm_i915_private *dev_priv = dev->dev_private;
12802 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12803 struct skl_ddb_entry *hw_entry, *sw_entry;
12804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12805 const enum pipe pipe = intel_crtc->pipe;
12806 int plane;
12807
12808 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12809 return;
12810
12811 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12812 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12813
12814 /* planes */
12815 for_each_plane(dev_priv, pipe, plane) {
12816 hw_entry = &hw_ddb.plane[pipe][plane];
12817 sw_entry = &sw_ddb->plane[pipe][plane];
12818
12819 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12820 continue;
12821
12822 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12823 "(expected (%u,%u), found (%u,%u))\n",
12824 pipe_name(pipe), plane + 1,
12825 sw_entry->start, sw_entry->end,
12826 hw_entry->start, hw_entry->end);
12827 }
12828
12829 /* cursor */
12830 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12831 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12832
12833 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12834 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12835 "(expected (%u,%u), found (%u,%u))\n",
12836 pipe_name(pipe),
12837 sw_entry->start, sw_entry->end,
12838 hw_entry->start, hw_entry->end);
12839 }
12840 }
12841
12842 static void
12843 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12844 {
12845 struct drm_connector *connector;
12846
12847 drm_for_each_connector(connector, dev) {
12848 struct drm_encoder *encoder = connector->encoder;
12849 struct drm_connector_state *state = connector->state;
12850
12851 if (state->crtc != crtc)
12852 continue;
12853
12854 intel_connector_verify_state(to_intel_connector(connector));
12855
12856 I915_STATE_WARN(state->best_encoder != encoder,
12857 "connector's atomic encoder doesn't match legacy encoder\n");
12858 }
12859 }
12860
12861 static void
12862 verify_encoder_state(struct drm_device *dev)
12863 {
12864 struct intel_encoder *encoder;
12865 struct intel_connector *connector;
12866
12867 for_each_intel_encoder(dev, encoder) {
12868 bool enabled = false;
12869 enum pipe pipe;
12870
12871 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12872 encoder->base.base.id,
12873 encoder->base.name);
12874
12875 for_each_intel_connector(dev, connector) {
12876 if (connector->base.state->best_encoder != &encoder->base)
12877 continue;
12878 enabled = true;
12879
12880 I915_STATE_WARN(connector->base.state->crtc !=
12881 encoder->base.crtc,
12882 "connector's crtc doesn't match encoder crtc\n");
12883 }
12884
12885 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12886 "encoder's enabled state mismatch "
12887 "(expected %i, found %i)\n",
12888 !!encoder->base.crtc, enabled);
12889
12890 if (!encoder->base.crtc) {
12891 bool active;
12892
12893 active = encoder->get_hw_state(encoder, &pipe);
12894 I915_STATE_WARN(active,
12895 "encoder detached but still enabled on pipe %c.\n",
12896 pipe_name(pipe));
12897 }
12898 }
12899 }
12900
12901 static void
12902 verify_crtc_state(struct drm_crtc *crtc,
12903 struct drm_crtc_state *old_crtc_state,
12904 struct drm_crtc_state *new_crtc_state)
12905 {
12906 struct drm_device *dev = crtc->dev;
12907 struct drm_i915_private *dev_priv = dev->dev_private;
12908 struct intel_encoder *encoder;
12909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12910 struct intel_crtc_state *pipe_config, *sw_config;
12911 struct drm_atomic_state *old_state;
12912 bool active;
12913
12914 old_state = old_crtc_state->state;
12915 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12916 pipe_config = to_intel_crtc_state(old_crtc_state);
12917 memset(pipe_config, 0, sizeof(*pipe_config));
12918 pipe_config->base.crtc = crtc;
12919 pipe_config->base.state = old_state;
12920
12921 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12922
12923 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12924
12925 /* hw state is inconsistent with the pipe quirk */
12926 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12927 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12928 active = new_crtc_state->active;
12929
12930 I915_STATE_WARN(new_crtc_state->active != active,
12931 "crtc active state doesn't match with hw state "
12932 "(expected %i, found %i)\n", new_crtc_state->active, active);
12933
12934 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12935 "transitional active state does not match atomic hw state "
12936 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12937
12938 for_each_encoder_on_crtc(dev, crtc, encoder) {
12939 enum pipe pipe;
12940
12941 active = encoder->get_hw_state(encoder, &pipe);
12942 I915_STATE_WARN(active != new_crtc_state->active,
12943 "[ENCODER:%i] active %i with crtc active %i\n",
12944 encoder->base.base.id, active, new_crtc_state->active);
12945
12946 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12947 "Encoder connected to wrong pipe %c\n",
12948 pipe_name(pipe));
12949
12950 if (active)
12951 encoder->get_config(encoder, pipe_config);
12952 }
12953
12954 if (!new_crtc_state->active)
12955 return;
12956
12957 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12958
12959 sw_config = to_intel_crtc_state(crtc->state);
12960 if (!intel_pipe_config_compare(dev, sw_config,
12961 pipe_config, false)) {
12962 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12963 intel_dump_pipe_config(intel_crtc, pipe_config,
12964 "[hw state]");
12965 intel_dump_pipe_config(intel_crtc, sw_config,
12966 "[sw state]");
12967 }
12968 }
12969
12970 static void
12971 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12972 struct intel_shared_dpll *pll,
12973 struct drm_crtc *crtc,
12974 struct drm_crtc_state *new_state)
12975 {
12976 struct intel_dpll_hw_state dpll_hw_state;
12977 unsigned crtc_mask;
12978 bool active;
12979
12980 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12981
12982 DRM_DEBUG_KMS("%s\n", pll->name);
12983
12984 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12985
12986 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12987 I915_STATE_WARN(!pll->on && pll->active_mask,
12988 "pll in active use but not on in sw tracking\n");
12989 I915_STATE_WARN(pll->on && !pll->active_mask,
12990 "pll is on but not used by any active crtc\n");
12991 I915_STATE_WARN(pll->on != active,
12992 "pll on state mismatch (expected %i, found %i)\n",
12993 pll->on, active);
12994 }
12995
12996 if (!crtc) {
12997 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12998 "more active pll users than references: %x vs %x\n",
12999 pll->active_mask, pll->config.crtc_mask);
13000
13001 return;
13002 }
13003
13004 crtc_mask = 1 << drm_crtc_index(crtc);
13005
13006 if (new_state->active)
13007 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13008 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13009 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13010 else
13011 I915_STATE_WARN(pll->active_mask & crtc_mask,
13012 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13013 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13014
13015 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13016 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13017 crtc_mask, pll->config.crtc_mask);
13018
13019 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13020 &dpll_hw_state,
13021 sizeof(dpll_hw_state)),
13022 "pll hw state mismatch\n");
13023 }
13024
13025 static void
13026 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13027 struct drm_crtc_state *old_crtc_state,
13028 struct drm_crtc_state *new_crtc_state)
13029 {
13030 struct drm_i915_private *dev_priv = dev->dev_private;
13031 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13032 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13033
13034 if (new_state->shared_dpll)
13035 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13036
13037 if (old_state->shared_dpll &&
13038 old_state->shared_dpll != new_state->shared_dpll) {
13039 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13040 struct intel_shared_dpll *pll = old_state->shared_dpll;
13041
13042 I915_STATE_WARN(pll->active_mask & crtc_mask,
13043 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13044 pipe_name(drm_crtc_index(crtc)));
13045 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13046 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13047 pipe_name(drm_crtc_index(crtc)));
13048 }
13049 }
13050
13051 static void
13052 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13053 struct drm_crtc_state *old_state,
13054 struct drm_crtc_state *new_state)
13055 {
13056 if (!needs_modeset(new_state) &&
13057 !to_intel_crtc_state(new_state)->update_pipe)
13058 return;
13059
13060 verify_wm_state(crtc, new_state);
13061 verify_connector_state(crtc->dev, crtc);
13062 verify_crtc_state(crtc, old_state, new_state);
13063 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13064 }
13065
13066 static void
13067 verify_disabled_dpll_state(struct drm_device *dev)
13068 {
13069 struct drm_i915_private *dev_priv = dev->dev_private;
13070 int i;
13071
13072 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13073 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13074 }
13075
13076 static void
13077 intel_modeset_verify_disabled(struct drm_device *dev)
13078 {
13079 verify_encoder_state(dev);
13080 verify_connector_state(dev, NULL);
13081 verify_disabled_dpll_state(dev);
13082 }
13083
13084 static void update_scanline_offset(struct intel_crtc *crtc)
13085 {
13086 struct drm_device *dev = crtc->base.dev;
13087
13088 /*
13089 * The scanline counter increments at the leading edge of hsync.
13090 *
13091 * On most platforms it starts counting from vtotal-1 on the
13092 * first active line. That means the scanline counter value is
13093 * always one less than what we would expect. Ie. just after
13094 * start of vblank, which also occurs at start of hsync (on the
13095 * last active line), the scanline counter will read vblank_start-1.
13096 *
13097 * On gen2 the scanline counter starts counting from 1 instead
13098 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13099 * to keep the value positive), instead of adding one.
13100 *
13101 * On HSW+ the behaviour of the scanline counter depends on the output
13102 * type. For DP ports it behaves like most other platforms, but on HDMI
13103 * there's an extra 1 line difference. So we need to add two instead of
13104 * one to the value.
13105 */
13106 if (IS_GEN2(dev)) {
13107 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13108 int vtotal;
13109
13110 vtotal = adjusted_mode->crtc_vtotal;
13111 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13112 vtotal /= 2;
13113
13114 crtc->scanline_offset = vtotal - 1;
13115 } else if (HAS_DDI(dev) &&
13116 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13117 crtc->scanline_offset = 2;
13118 } else
13119 crtc->scanline_offset = 1;
13120 }
13121
13122 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13123 {
13124 struct drm_device *dev = state->dev;
13125 struct drm_i915_private *dev_priv = to_i915(dev);
13126 struct intel_shared_dpll_config *shared_dpll = NULL;
13127 struct drm_crtc *crtc;
13128 struct drm_crtc_state *crtc_state;
13129 int i;
13130
13131 if (!dev_priv->display.crtc_compute_clock)
13132 return;
13133
13134 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13136 struct intel_shared_dpll *old_dpll =
13137 to_intel_crtc_state(crtc->state)->shared_dpll;
13138
13139 if (!needs_modeset(crtc_state))
13140 continue;
13141
13142 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13143
13144 if (!old_dpll)
13145 continue;
13146
13147 if (!shared_dpll)
13148 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13149
13150 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13151 }
13152 }
13153
13154 /*
13155 * This implements the workaround described in the "notes" section of the mode
13156 * set sequence documentation. When going from no pipes or single pipe to
13157 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13158 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13159 */
13160 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13161 {
13162 struct drm_crtc_state *crtc_state;
13163 struct intel_crtc *intel_crtc;
13164 struct drm_crtc *crtc;
13165 struct intel_crtc_state *first_crtc_state = NULL;
13166 struct intel_crtc_state *other_crtc_state = NULL;
13167 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13168 int i;
13169
13170 /* look at all crtc's that are going to be enabled in during modeset */
13171 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13172 intel_crtc = to_intel_crtc(crtc);
13173
13174 if (!crtc_state->active || !needs_modeset(crtc_state))
13175 continue;
13176
13177 if (first_crtc_state) {
13178 other_crtc_state = to_intel_crtc_state(crtc_state);
13179 break;
13180 } else {
13181 first_crtc_state = to_intel_crtc_state(crtc_state);
13182 first_pipe = intel_crtc->pipe;
13183 }
13184 }
13185
13186 /* No workaround needed? */
13187 if (!first_crtc_state)
13188 return 0;
13189
13190 /* w/a possibly needed, check how many crtc's are already enabled. */
13191 for_each_intel_crtc(state->dev, intel_crtc) {
13192 struct intel_crtc_state *pipe_config;
13193
13194 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13195 if (IS_ERR(pipe_config))
13196 return PTR_ERR(pipe_config);
13197
13198 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13199
13200 if (!pipe_config->base.active ||
13201 needs_modeset(&pipe_config->base))
13202 continue;
13203
13204 /* 2 or more enabled crtcs means no need for w/a */
13205 if (enabled_pipe != INVALID_PIPE)
13206 return 0;
13207
13208 enabled_pipe = intel_crtc->pipe;
13209 }
13210
13211 if (enabled_pipe != INVALID_PIPE)
13212 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13213 else if (other_crtc_state)
13214 other_crtc_state->hsw_workaround_pipe = first_pipe;
13215
13216 return 0;
13217 }
13218
13219 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13220 {
13221 struct drm_crtc *crtc;
13222 struct drm_crtc_state *crtc_state;
13223 int ret = 0;
13224
13225 /* add all active pipes to the state */
13226 for_each_crtc(state->dev, crtc) {
13227 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13228 if (IS_ERR(crtc_state))
13229 return PTR_ERR(crtc_state);
13230
13231 if (!crtc_state->active || needs_modeset(crtc_state))
13232 continue;
13233
13234 crtc_state->mode_changed = true;
13235
13236 ret = drm_atomic_add_affected_connectors(state, crtc);
13237 if (ret)
13238 break;
13239
13240 ret = drm_atomic_add_affected_planes(state, crtc);
13241 if (ret)
13242 break;
13243 }
13244
13245 return ret;
13246 }
13247
13248 static int intel_modeset_checks(struct drm_atomic_state *state)
13249 {
13250 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13251 struct drm_i915_private *dev_priv = state->dev->dev_private;
13252 struct drm_crtc *crtc;
13253 struct drm_crtc_state *crtc_state;
13254 int ret = 0, i;
13255
13256 if (!check_digital_port_conflicts(state)) {
13257 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13258 return -EINVAL;
13259 }
13260
13261 intel_state->modeset = true;
13262 intel_state->active_crtcs = dev_priv->active_crtcs;
13263
13264 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13265 if (crtc_state->active)
13266 intel_state->active_crtcs |= 1 << i;
13267 else
13268 intel_state->active_crtcs &= ~(1 << i);
13269 }
13270
13271 /*
13272 * See if the config requires any additional preparation, e.g.
13273 * to adjust global state with pipes off. We need to do this
13274 * here so we can get the modeset_pipe updated config for the new
13275 * mode set on this crtc. For other crtcs we need to use the
13276 * adjusted_mode bits in the crtc directly.
13277 */
13278 if (dev_priv->display.modeset_calc_cdclk) {
13279 ret = dev_priv->display.modeset_calc_cdclk(state);
13280
13281 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13282 ret = intel_modeset_all_pipes(state);
13283
13284 if (ret < 0)
13285 return ret;
13286
13287 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13288 intel_state->cdclk, intel_state->dev_cdclk);
13289 } else
13290 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13291
13292 intel_modeset_clear_plls(state);
13293
13294 if (IS_HASWELL(dev_priv))
13295 return haswell_mode_set_planes_workaround(state);
13296
13297 return 0;
13298 }
13299
13300 /*
13301 * Handle calculation of various watermark data at the end of the atomic check
13302 * phase. The code here should be run after the per-crtc and per-plane 'check'
13303 * handlers to ensure that all derived state has been updated.
13304 */
13305 static void calc_watermark_data(struct drm_atomic_state *state)
13306 {
13307 struct drm_device *dev = state->dev;
13308 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13309 struct drm_crtc *crtc;
13310 struct drm_crtc_state *cstate;
13311 struct drm_plane *plane;
13312 struct drm_plane_state *pstate;
13313
13314 /*
13315 * Calculate watermark configuration details now that derived
13316 * plane/crtc state is all properly updated.
13317 */
13318 drm_for_each_crtc(crtc, dev) {
13319 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13320 crtc->state;
13321
13322 if (cstate->active)
13323 intel_state->wm_config.num_pipes_active++;
13324 }
13325 drm_for_each_legacy_plane(plane, dev) {
13326 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13327 plane->state;
13328
13329 if (!to_intel_plane_state(pstate)->visible)
13330 continue;
13331
13332 intel_state->wm_config.sprites_enabled = true;
13333 if (pstate->crtc_w != pstate->src_w >> 16 ||
13334 pstate->crtc_h != pstate->src_h >> 16)
13335 intel_state->wm_config.sprites_scaled = true;
13336 }
13337 }
13338
13339 /**
13340 * intel_atomic_check - validate state object
13341 * @dev: drm device
13342 * @state: state to validate
13343 */
13344 static int intel_atomic_check(struct drm_device *dev,
13345 struct drm_atomic_state *state)
13346 {
13347 struct drm_i915_private *dev_priv = to_i915(dev);
13348 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13349 struct drm_crtc *crtc;
13350 struct drm_crtc_state *crtc_state;
13351 int ret, i;
13352 bool any_ms = false;
13353
13354 ret = drm_atomic_helper_check_modeset(dev, state);
13355 if (ret)
13356 return ret;
13357
13358 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13359 struct intel_crtc_state *pipe_config =
13360 to_intel_crtc_state(crtc_state);
13361
13362 /* Catch I915_MODE_FLAG_INHERITED */
13363 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13364 crtc_state->mode_changed = true;
13365
13366 if (!crtc_state->enable) {
13367 if (needs_modeset(crtc_state))
13368 any_ms = true;
13369 continue;
13370 }
13371
13372 if (!needs_modeset(crtc_state))
13373 continue;
13374
13375 /* FIXME: For only active_changed we shouldn't need to do any
13376 * state recomputation at all. */
13377
13378 ret = drm_atomic_add_affected_connectors(state, crtc);
13379 if (ret)
13380 return ret;
13381
13382 ret = intel_modeset_pipe_config(crtc, pipe_config);
13383 if (ret) {
13384 intel_dump_pipe_config(to_intel_crtc(crtc),
13385 pipe_config, "[failed]");
13386 return ret;
13387 }
13388
13389 if (i915.fastboot &&
13390 intel_pipe_config_compare(dev,
13391 to_intel_crtc_state(crtc->state),
13392 pipe_config, true)) {
13393 crtc_state->mode_changed = false;
13394 to_intel_crtc_state(crtc_state)->update_pipe = true;
13395 }
13396
13397 if (needs_modeset(crtc_state)) {
13398 any_ms = true;
13399
13400 ret = drm_atomic_add_affected_planes(state, crtc);
13401 if (ret)
13402 return ret;
13403 }
13404
13405 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13406 needs_modeset(crtc_state) ?
13407 "[modeset]" : "[fastset]");
13408 }
13409
13410 if (any_ms) {
13411 ret = intel_modeset_checks(state);
13412
13413 if (ret)
13414 return ret;
13415 } else
13416 intel_state->cdclk = dev_priv->cdclk_freq;
13417
13418 ret = drm_atomic_helper_check_planes(dev, state);
13419 if (ret)
13420 return ret;
13421
13422 intel_fbc_choose_crtc(dev_priv, state);
13423 calc_watermark_data(state);
13424
13425 return 0;
13426 }
13427
13428 static int intel_atomic_prepare_commit(struct drm_device *dev,
13429 struct drm_atomic_state *state,
13430 bool async)
13431 {
13432 struct drm_i915_private *dev_priv = dev->dev_private;
13433 struct drm_plane_state *plane_state;
13434 struct drm_crtc_state *crtc_state;
13435 struct drm_plane *plane;
13436 struct drm_crtc *crtc;
13437 int i, ret;
13438
13439 if (async) {
13440 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13441 return -EINVAL;
13442 }
13443
13444 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13445 if (state->legacy_cursor_update)
13446 continue;
13447
13448 ret = intel_crtc_wait_for_pending_flips(crtc);
13449 if (ret)
13450 return ret;
13451
13452 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13453 flush_workqueue(dev_priv->wq);
13454 }
13455
13456 ret = mutex_lock_interruptible(&dev->struct_mutex);
13457 if (ret)
13458 return ret;
13459
13460 ret = drm_atomic_helper_prepare_planes(dev, state);
13461 mutex_unlock(&dev->struct_mutex);
13462
13463 if (!ret && !async) {
13464 for_each_plane_in_state(state, plane, plane_state, i) {
13465 struct intel_plane_state *intel_plane_state =
13466 to_intel_plane_state(plane_state);
13467
13468 if (!intel_plane_state->wait_req)
13469 continue;
13470
13471 ret = __i915_wait_request(intel_plane_state->wait_req,
13472 true, NULL, NULL);
13473 if (ret) {
13474 /* Any hang should be swallowed by the wait */
13475 WARN_ON(ret == -EIO);
13476 mutex_lock(&dev->struct_mutex);
13477 drm_atomic_helper_cleanup_planes(dev, state);
13478 mutex_unlock(&dev->struct_mutex);
13479 break;
13480 }
13481 }
13482 }
13483
13484 return ret;
13485 }
13486
13487 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13488 struct drm_i915_private *dev_priv,
13489 unsigned crtc_mask)
13490 {
13491 unsigned last_vblank_count[I915_MAX_PIPES];
13492 enum pipe pipe;
13493 int ret;
13494
13495 if (!crtc_mask)
13496 return;
13497
13498 for_each_pipe(dev_priv, pipe) {
13499 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13500
13501 if (!((1 << pipe) & crtc_mask))
13502 continue;
13503
13504 ret = drm_crtc_vblank_get(crtc);
13505 if (WARN_ON(ret != 0)) {
13506 crtc_mask &= ~(1 << pipe);
13507 continue;
13508 }
13509
13510 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13511 }
13512
13513 for_each_pipe(dev_priv, pipe) {
13514 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13515 long lret;
13516
13517 if (!((1 << pipe) & crtc_mask))
13518 continue;
13519
13520 lret = wait_event_timeout(dev->vblank[pipe].queue,
13521 last_vblank_count[pipe] !=
13522 drm_crtc_vblank_count(crtc),
13523 msecs_to_jiffies(50));
13524
13525 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13526
13527 drm_crtc_vblank_put(crtc);
13528 }
13529 }
13530
13531 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13532 {
13533 /* fb updated, need to unpin old fb */
13534 if (crtc_state->fb_changed)
13535 return true;
13536
13537 /* wm changes, need vblank before final wm's */
13538 if (crtc_state->update_wm_post)
13539 return true;
13540
13541 /*
13542 * cxsr is re-enabled after vblank.
13543 * This is already handled by crtc_state->update_wm_post,
13544 * but added for clarity.
13545 */
13546 if (crtc_state->disable_cxsr)
13547 return true;
13548
13549 return false;
13550 }
13551
13552 /**
13553 * intel_atomic_commit - commit validated state object
13554 * @dev: DRM device
13555 * @state: the top-level driver state object
13556 * @async: asynchronous commit
13557 *
13558 * This function commits a top-level state object that has been validated
13559 * with drm_atomic_helper_check().
13560 *
13561 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13562 * we can only handle plane-related operations and do not yet support
13563 * asynchronous commit.
13564 *
13565 * RETURNS
13566 * Zero for success or -errno.
13567 */
13568 static int intel_atomic_commit(struct drm_device *dev,
13569 struct drm_atomic_state *state,
13570 bool async)
13571 {
13572 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13573 struct drm_i915_private *dev_priv = dev->dev_private;
13574 struct drm_crtc_state *old_crtc_state;
13575 struct drm_crtc *crtc;
13576 struct intel_crtc_state *intel_cstate;
13577 int ret = 0, i;
13578 bool hw_check = intel_state->modeset;
13579 unsigned long put_domains[I915_MAX_PIPES] = {};
13580 unsigned crtc_vblank_mask = 0;
13581
13582 ret = intel_atomic_prepare_commit(dev, state, async);
13583 if (ret) {
13584 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13585 return ret;
13586 }
13587
13588 drm_atomic_helper_swap_state(dev, state);
13589 dev_priv->wm.config = intel_state->wm_config;
13590 intel_shared_dpll_commit(state);
13591
13592 if (intel_state->modeset) {
13593 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13594 sizeof(intel_state->min_pixclk));
13595 dev_priv->active_crtcs = intel_state->active_crtcs;
13596 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13597
13598 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13599 }
13600
13601 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13603
13604 if (needs_modeset(crtc->state) ||
13605 to_intel_crtc_state(crtc->state)->update_pipe) {
13606 hw_check = true;
13607
13608 put_domains[to_intel_crtc(crtc)->pipe] =
13609 modeset_get_crtc_power_domains(crtc,
13610 to_intel_crtc_state(crtc->state));
13611 }
13612
13613 if (!needs_modeset(crtc->state))
13614 continue;
13615
13616 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13617
13618 if (old_crtc_state->active) {
13619 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13620 dev_priv->display.crtc_disable(crtc);
13621 intel_crtc->active = false;
13622 intel_fbc_disable(intel_crtc);
13623 intel_disable_shared_dpll(intel_crtc);
13624
13625 /*
13626 * Underruns don't always raise
13627 * interrupts, so check manually.
13628 */
13629 intel_check_cpu_fifo_underruns(dev_priv);
13630 intel_check_pch_fifo_underruns(dev_priv);
13631
13632 if (!crtc->state->active)
13633 intel_update_watermarks(crtc);
13634 }
13635 }
13636
13637 /* Only after disabling all output pipelines that will be changed can we
13638 * update the the output configuration. */
13639 intel_modeset_update_crtc_state(state);
13640
13641 if (intel_state->modeset) {
13642 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13643
13644 if (dev_priv->display.modeset_commit_cdclk &&
13645 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13646 dev_priv->display.modeset_commit_cdclk(state);
13647
13648 intel_modeset_verify_disabled(dev);
13649 }
13650
13651 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13652 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13654 bool modeset = needs_modeset(crtc->state);
13655 struct intel_crtc_state *pipe_config =
13656 to_intel_crtc_state(crtc->state);
13657 bool update_pipe = !modeset && pipe_config->update_pipe;
13658
13659 if (modeset && crtc->state->active) {
13660 update_scanline_offset(to_intel_crtc(crtc));
13661 dev_priv->display.crtc_enable(crtc);
13662 }
13663
13664 if (!modeset)
13665 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13666
13667 if (crtc->state->active &&
13668 drm_atomic_get_existing_plane_state(state, crtc->primary))
13669 intel_fbc_enable(intel_crtc);
13670
13671 if (crtc->state->active &&
13672 (crtc->state->planes_changed || update_pipe))
13673 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13674
13675 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13676 crtc_vblank_mask |= 1 << i;
13677 }
13678
13679 /* FIXME: add subpixel order */
13680
13681 if (!state->legacy_cursor_update)
13682 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13683
13684 /*
13685 * Now that the vblank has passed, we can go ahead and program the
13686 * optimal watermarks on platforms that need two-step watermark
13687 * programming.
13688 *
13689 * TODO: Move this (and other cleanup) to an async worker eventually.
13690 */
13691 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13692 intel_cstate = to_intel_crtc_state(crtc->state);
13693
13694 if (dev_priv->display.optimize_watermarks)
13695 dev_priv->display.optimize_watermarks(intel_cstate);
13696 }
13697
13698 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13699 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13700
13701 if (put_domains[i])
13702 modeset_put_power_domains(dev_priv, put_domains[i]);
13703
13704 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13705 }
13706
13707 if (intel_state->modeset)
13708 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13709
13710 mutex_lock(&dev->struct_mutex);
13711 drm_atomic_helper_cleanup_planes(dev, state);
13712 mutex_unlock(&dev->struct_mutex);
13713
13714 drm_atomic_state_free(state);
13715
13716 /* As one of the primary mmio accessors, KMS has a high likelihood
13717 * of triggering bugs in unclaimed access. After we finish
13718 * modesetting, see if an error has been flagged, and if so
13719 * enable debugging for the next modeset - and hope we catch
13720 * the culprit.
13721 *
13722 * XXX note that we assume display power is on at this point.
13723 * This might hold true now but we need to add pm helper to check
13724 * unclaimed only when the hardware is on, as atomic commits
13725 * can happen also when the device is completely off.
13726 */
13727 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13728
13729 return 0;
13730 }
13731
13732 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13733 {
13734 struct drm_device *dev = crtc->dev;
13735 struct drm_atomic_state *state;
13736 struct drm_crtc_state *crtc_state;
13737 int ret;
13738
13739 state = drm_atomic_state_alloc(dev);
13740 if (!state) {
13741 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13742 crtc->base.id);
13743 return;
13744 }
13745
13746 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13747
13748 retry:
13749 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13750 ret = PTR_ERR_OR_ZERO(crtc_state);
13751 if (!ret) {
13752 if (!crtc_state->active)
13753 goto out;
13754
13755 crtc_state->mode_changed = true;
13756 ret = drm_atomic_commit(state);
13757 }
13758
13759 if (ret == -EDEADLK) {
13760 drm_atomic_state_clear(state);
13761 drm_modeset_backoff(state->acquire_ctx);
13762 goto retry;
13763 }
13764
13765 if (ret)
13766 out:
13767 drm_atomic_state_free(state);
13768 }
13769
13770 #undef for_each_intel_crtc_masked
13771
13772 static const struct drm_crtc_funcs intel_crtc_funcs = {
13773 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13774 .set_config = drm_atomic_helper_set_config,
13775 .set_property = drm_atomic_helper_crtc_set_property,
13776 .destroy = intel_crtc_destroy,
13777 .page_flip = intel_crtc_page_flip,
13778 .atomic_duplicate_state = intel_crtc_duplicate_state,
13779 .atomic_destroy_state = intel_crtc_destroy_state,
13780 };
13781
13782 /**
13783 * intel_prepare_plane_fb - Prepare fb for usage on plane
13784 * @plane: drm plane to prepare for
13785 * @fb: framebuffer to prepare for presentation
13786 *
13787 * Prepares a framebuffer for usage on a display plane. Generally this
13788 * involves pinning the underlying object and updating the frontbuffer tracking
13789 * bits. Some older platforms need special physical address handling for
13790 * cursor planes.
13791 *
13792 * Must be called with struct_mutex held.
13793 *
13794 * Returns 0 on success, negative error code on failure.
13795 */
13796 int
13797 intel_prepare_plane_fb(struct drm_plane *plane,
13798 const struct drm_plane_state *new_state)
13799 {
13800 struct drm_device *dev = plane->dev;
13801 struct drm_framebuffer *fb = new_state->fb;
13802 struct intel_plane *intel_plane = to_intel_plane(plane);
13803 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13804 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13805 int ret = 0;
13806
13807 if (!obj && !old_obj)
13808 return 0;
13809
13810 if (old_obj) {
13811 struct drm_crtc_state *crtc_state =
13812 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13813
13814 /* Big Hammer, we also need to ensure that any pending
13815 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13816 * current scanout is retired before unpinning the old
13817 * framebuffer. Note that we rely on userspace rendering
13818 * into the buffer attached to the pipe they are waiting
13819 * on. If not, userspace generates a GPU hang with IPEHR
13820 * point to the MI_WAIT_FOR_EVENT.
13821 *
13822 * This should only fail upon a hung GPU, in which case we
13823 * can safely continue.
13824 */
13825 if (needs_modeset(crtc_state))
13826 ret = i915_gem_object_wait_rendering(old_obj, true);
13827 if (ret) {
13828 /* GPU hangs should have been swallowed by the wait */
13829 WARN_ON(ret == -EIO);
13830 return ret;
13831 }
13832 }
13833
13834 /* For framebuffer backed by dmabuf, wait for fence */
13835 if (obj && obj->base.dma_buf) {
13836 long lret;
13837
13838 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13839 false, true,
13840 MAX_SCHEDULE_TIMEOUT);
13841 if (lret == -ERESTARTSYS)
13842 return lret;
13843
13844 WARN(lret < 0, "waiting returns %li\n", lret);
13845 }
13846
13847 if (!obj) {
13848 ret = 0;
13849 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13850 INTEL_INFO(dev)->cursor_needs_physical) {
13851 int align = IS_I830(dev) ? 16 * 1024 : 256;
13852 ret = i915_gem_object_attach_phys(obj, align);
13853 if (ret)
13854 DRM_DEBUG_KMS("failed to attach phys object\n");
13855 } else {
13856 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13857 }
13858
13859 if (ret == 0) {
13860 if (obj) {
13861 struct intel_plane_state *plane_state =
13862 to_intel_plane_state(new_state);
13863
13864 i915_gem_request_assign(&plane_state->wait_req,
13865 obj->last_write_req);
13866 }
13867
13868 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13869 }
13870
13871 return ret;
13872 }
13873
13874 /**
13875 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13876 * @plane: drm plane to clean up for
13877 * @fb: old framebuffer that was on plane
13878 *
13879 * Cleans up a framebuffer that has just been removed from a plane.
13880 *
13881 * Must be called with struct_mutex held.
13882 */
13883 void
13884 intel_cleanup_plane_fb(struct drm_plane *plane,
13885 const struct drm_plane_state *old_state)
13886 {
13887 struct drm_device *dev = plane->dev;
13888 struct intel_plane *intel_plane = to_intel_plane(plane);
13889 struct intel_plane_state *old_intel_state;
13890 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13891 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13892
13893 old_intel_state = to_intel_plane_state(old_state);
13894
13895 if (!obj && !old_obj)
13896 return;
13897
13898 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13899 !INTEL_INFO(dev)->cursor_needs_physical))
13900 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13901
13902 /* prepare_fb aborted? */
13903 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13904 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13905 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13906
13907 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13908 }
13909
13910 int
13911 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13912 {
13913 int max_scale;
13914 struct drm_device *dev;
13915 struct drm_i915_private *dev_priv;
13916 int crtc_clock, cdclk;
13917
13918 if (!intel_crtc || !crtc_state->base.enable)
13919 return DRM_PLANE_HELPER_NO_SCALING;
13920
13921 dev = intel_crtc->base.dev;
13922 dev_priv = dev->dev_private;
13923 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13924 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13925
13926 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13927 return DRM_PLANE_HELPER_NO_SCALING;
13928
13929 /*
13930 * skl max scale is lower of:
13931 * close to 3 but not 3, -1 is for that purpose
13932 * or
13933 * cdclk/crtc_clock
13934 */
13935 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13936
13937 return max_scale;
13938 }
13939
13940 static int
13941 intel_check_primary_plane(struct drm_plane *plane,
13942 struct intel_crtc_state *crtc_state,
13943 struct intel_plane_state *state)
13944 {
13945 struct drm_crtc *crtc = state->base.crtc;
13946 struct drm_framebuffer *fb = state->base.fb;
13947 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13948 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13949 bool can_position = false;
13950
13951 if (INTEL_INFO(plane->dev)->gen >= 9) {
13952 /* use scaler when colorkey is not required */
13953 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13954 min_scale = 1;
13955 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13956 }
13957 can_position = true;
13958 }
13959
13960 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13961 &state->dst, &state->clip,
13962 min_scale, max_scale,
13963 can_position, true,
13964 &state->visible);
13965 }
13966
13967 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13968 struct drm_crtc_state *old_crtc_state)
13969 {
13970 struct drm_device *dev = crtc->dev;
13971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13972 struct intel_crtc_state *old_intel_state =
13973 to_intel_crtc_state(old_crtc_state);
13974 bool modeset = needs_modeset(crtc->state);
13975
13976 /* Perform vblank evasion around commit operation */
13977 intel_pipe_update_start(intel_crtc);
13978
13979 if (modeset)
13980 return;
13981
13982 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13983 intel_color_set_csc(crtc->state);
13984 intel_color_load_luts(crtc->state);
13985 }
13986
13987 if (to_intel_crtc_state(crtc->state)->update_pipe)
13988 intel_update_pipe_config(intel_crtc, old_intel_state);
13989 else if (INTEL_INFO(dev)->gen >= 9)
13990 skl_detach_scalers(intel_crtc);
13991 }
13992
13993 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13994 struct drm_crtc_state *old_crtc_state)
13995 {
13996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13997
13998 intel_pipe_update_end(intel_crtc);
13999 }
14000
14001 /**
14002 * intel_plane_destroy - destroy a plane
14003 * @plane: plane to destroy
14004 *
14005 * Common destruction function for all types of planes (primary, cursor,
14006 * sprite).
14007 */
14008 void intel_plane_destroy(struct drm_plane *plane)
14009 {
14010 struct intel_plane *intel_plane = to_intel_plane(plane);
14011 drm_plane_cleanup(plane);
14012 kfree(intel_plane);
14013 }
14014
14015 const struct drm_plane_funcs intel_plane_funcs = {
14016 .update_plane = drm_atomic_helper_update_plane,
14017 .disable_plane = drm_atomic_helper_disable_plane,
14018 .destroy = intel_plane_destroy,
14019 .set_property = drm_atomic_helper_plane_set_property,
14020 .atomic_get_property = intel_plane_atomic_get_property,
14021 .atomic_set_property = intel_plane_atomic_set_property,
14022 .atomic_duplicate_state = intel_plane_duplicate_state,
14023 .atomic_destroy_state = intel_plane_destroy_state,
14024
14025 };
14026
14027 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14028 int pipe)
14029 {
14030 struct intel_plane *primary = NULL;
14031 struct intel_plane_state *state = NULL;
14032 const uint32_t *intel_primary_formats;
14033 unsigned int num_formats;
14034 int ret;
14035
14036 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14037 if (!primary)
14038 goto fail;
14039
14040 state = intel_create_plane_state(&primary->base);
14041 if (!state)
14042 goto fail;
14043 primary->base.state = &state->base;
14044
14045 primary->can_scale = false;
14046 primary->max_downscale = 1;
14047 if (INTEL_INFO(dev)->gen >= 9) {
14048 primary->can_scale = true;
14049 state->scaler_id = -1;
14050 }
14051 primary->pipe = pipe;
14052 primary->plane = pipe;
14053 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14054 primary->check_plane = intel_check_primary_plane;
14055 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14056 primary->plane = !pipe;
14057
14058 if (INTEL_INFO(dev)->gen >= 9) {
14059 intel_primary_formats = skl_primary_formats;
14060 num_formats = ARRAY_SIZE(skl_primary_formats);
14061
14062 primary->update_plane = skylake_update_primary_plane;
14063 primary->disable_plane = skylake_disable_primary_plane;
14064 } else if (HAS_PCH_SPLIT(dev)) {
14065 intel_primary_formats = i965_primary_formats;
14066 num_formats = ARRAY_SIZE(i965_primary_formats);
14067
14068 primary->update_plane = ironlake_update_primary_plane;
14069 primary->disable_plane = i9xx_disable_primary_plane;
14070 } else if (INTEL_INFO(dev)->gen >= 4) {
14071 intel_primary_formats = i965_primary_formats;
14072 num_formats = ARRAY_SIZE(i965_primary_formats);
14073
14074 primary->update_plane = i9xx_update_primary_plane;
14075 primary->disable_plane = i9xx_disable_primary_plane;
14076 } else {
14077 intel_primary_formats = i8xx_primary_formats;
14078 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14079
14080 primary->update_plane = i9xx_update_primary_plane;
14081 primary->disable_plane = i9xx_disable_primary_plane;
14082 }
14083
14084 ret = drm_universal_plane_init(dev, &primary->base, 0,
14085 &intel_plane_funcs,
14086 intel_primary_formats, num_formats,
14087 DRM_PLANE_TYPE_PRIMARY, NULL);
14088 if (ret)
14089 goto fail;
14090
14091 if (INTEL_INFO(dev)->gen >= 4)
14092 intel_create_rotation_property(dev, primary);
14093
14094 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14095
14096 return &primary->base;
14097
14098 fail:
14099 kfree(state);
14100 kfree(primary);
14101
14102 return NULL;
14103 }
14104
14105 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14106 {
14107 if (!dev->mode_config.rotation_property) {
14108 unsigned long flags = BIT(DRM_ROTATE_0) |
14109 BIT(DRM_ROTATE_180);
14110
14111 if (INTEL_INFO(dev)->gen >= 9)
14112 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14113
14114 dev->mode_config.rotation_property =
14115 drm_mode_create_rotation_property(dev, flags);
14116 }
14117 if (dev->mode_config.rotation_property)
14118 drm_object_attach_property(&plane->base.base,
14119 dev->mode_config.rotation_property,
14120 plane->base.state->rotation);
14121 }
14122
14123 static int
14124 intel_check_cursor_plane(struct drm_plane *plane,
14125 struct intel_crtc_state *crtc_state,
14126 struct intel_plane_state *state)
14127 {
14128 struct drm_crtc *crtc = crtc_state->base.crtc;
14129 struct drm_framebuffer *fb = state->base.fb;
14130 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14131 enum pipe pipe = to_intel_plane(plane)->pipe;
14132 unsigned stride;
14133 int ret;
14134
14135 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14136 &state->dst, &state->clip,
14137 DRM_PLANE_HELPER_NO_SCALING,
14138 DRM_PLANE_HELPER_NO_SCALING,
14139 true, true, &state->visible);
14140 if (ret)
14141 return ret;
14142
14143 /* if we want to turn off the cursor ignore width and height */
14144 if (!obj)
14145 return 0;
14146
14147 /* Check for which cursor types we support */
14148 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14149 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14150 state->base.crtc_w, state->base.crtc_h);
14151 return -EINVAL;
14152 }
14153
14154 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14155 if (obj->base.size < stride * state->base.crtc_h) {
14156 DRM_DEBUG_KMS("buffer is too small\n");
14157 return -ENOMEM;
14158 }
14159
14160 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14161 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14162 return -EINVAL;
14163 }
14164
14165 /*
14166 * There's something wrong with the cursor on CHV pipe C.
14167 * If it straddles the left edge of the screen then
14168 * moving it away from the edge or disabling it often
14169 * results in a pipe underrun, and often that can lead to
14170 * dead pipe (constant underrun reported, and it scans
14171 * out just a solid color). To recover from that, the
14172 * display power well must be turned off and on again.
14173 * Refuse the put the cursor into that compromised position.
14174 */
14175 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14176 state->visible && state->base.crtc_x < 0) {
14177 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14178 return -EINVAL;
14179 }
14180
14181 return 0;
14182 }
14183
14184 static void
14185 intel_disable_cursor_plane(struct drm_plane *plane,
14186 struct drm_crtc *crtc)
14187 {
14188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14189
14190 intel_crtc->cursor_addr = 0;
14191 intel_crtc_update_cursor(crtc, NULL);
14192 }
14193
14194 static void
14195 intel_update_cursor_plane(struct drm_plane *plane,
14196 const struct intel_crtc_state *crtc_state,
14197 const struct intel_plane_state *state)
14198 {
14199 struct drm_crtc *crtc = crtc_state->base.crtc;
14200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14201 struct drm_device *dev = plane->dev;
14202 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14203 uint32_t addr;
14204
14205 if (!obj)
14206 addr = 0;
14207 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14208 addr = i915_gem_obj_ggtt_offset(obj);
14209 else
14210 addr = obj->phys_handle->busaddr;
14211
14212 intel_crtc->cursor_addr = addr;
14213 intel_crtc_update_cursor(crtc, state);
14214 }
14215
14216 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14217 int pipe)
14218 {
14219 struct intel_plane *cursor = NULL;
14220 struct intel_plane_state *state = NULL;
14221 int ret;
14222
14223 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14224 if (!cursor)
14225 goto fail;
14226
14227 state = intel_create_plane_state(&cursor->base);
14228 if (!state)
14229 goto fail;
14230 cursor->base.state = &state->base;
14231
14232 cursor->can_scale = false;
14233 cursor->max_downscale = 1;
14234 cursor->pipe = pipe;
14235 cursor->plane = pipe;
14236 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14237 cursor->check_plane = intel_check_cursor_plane;
14238 cursor->update_plane = intel_update_cursor_plane;
14239 cursor->disable_plane = intel_disable_cursor_plane;
14240
14241 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14242 &intel_plane_funcs,
14243 intel_cursor_formats,
14244 ARRAY_SIZE(intel_cursor_formats),
14245 DRM_PLANE_TYPE_CURSOR, NULL);
14246 if (ret)
14247 goto fail;
14248
14249 if (INTEL_INFO(dev)->gen >= 4) {
14250 if (!dev->mode_config.rotation_property)
14251 dev->mode_config.rotation_property =
14252 drm_mode_create_rotation_property(dev,
14253 BIT(DRM_ROTATE_0) |
14254 BIT(DRM_ROTATE_180));
14255 if (dev->mode_config.rotation_property)
14256 drm_object_attach_property(&cursor->base.base,
14257 dev->mode_config.rotation_property,
14258 state->base.rotation);
14259 }
14260
14261 if (INTEL_INFO(dev)->gen >=9)
14262 state->scaler_id = -1;
14263
14264 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14265
14266 return &cursor->base;
14267
14268 fail:
14269 kfree(state);
14270 kfree(cursor);
14271
14272 return NULL;
14273 }
14274
14275 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14276 struct intel_crtc_state *crtc_state)
14277 {
14278 int i;
14279 struct intel_scaler *intel_scaler;
14280 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14281
14282 for (i = 0; i < intel_crtc->num_scalers; i++) {
14283 intel_scaler = &scaler_state->scalers[i];
14284 intel_scaler->in_use = 0;
14285 intel_scaler->mode = PS_SCALER_MODE_DYN;
14286 }
14287
14288 scaler_state->scaler_id = -1;
14289 }
14290
14291 static void intel_crtc_init(struct drm_device *dev, int pipe)
14292 {
14293 struct drm_i915_private *dev_priv = dev->dev_private;
14294 struct intel_crtc *intel_crtc;
14295 struct intel_crtc_state *crtc_state = NULL;
14296 struct drm_plane *primary = NULL;
14297 struct drm_plane *cursor = NULL;
14298 int ret;
14299
14300 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14301 if (intel_crtc == NULL)
14302 return;
14303
14304 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14305 if (!crtc_state)
14306 goto fail;
14307 intel_crtc->config = crtc_state;
14308 intel_crtc->base.state = &crtc_state->base;
14309 crtc_state->base.crtc = &intel_crtc->base;
14310
14311 /* initialize shared scalers */
14312 if (INTEL_INFO(dev)->gen >= 9) {
14313 if (pipe == PIPE_C)
14314 intel_crtc->num_scalers = 1;
14315 else
14316 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14317
14318 skl_init_scalers(dev, intel_crtc, crtc_state);
14319 }
14320
14321 primary = intel_primary_plane_create(dev, pipe);
14322 if (!primary)
14323 goto fail;
14324
14325 cursor = intel_cursor_plane_create(dev, pipe);
14326 if (!cursor)
14327 goto fail;
14328
14329 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14330 cursor, &intel_crtc_funcs, NULL);
14331 if (ret)
14332 goto fail;
14333
14334 /*
14335 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14336 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14337 */
14338 intel_crtc->pipe = pipe;
14339 intel_crtc->plane = pipe;
14340 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14341 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14342 intel_crtc->plane = !pipe;
14343 }
14344
14345 intel_crtc->cursor_base = ~0;
14346 intel_crtc->cursor_cntl = ~0;
14347 intel_crtc->cursor_size = ~0;
14348
14349 intel_crtc->wm.cxsr_allowed = true;
14350
14351 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14352 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14353 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14354 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14355
14356 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14357
14358 intel_color_init(&intel_crtc->base);
14359
14360 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14361 return;
14362
14363 fail:
14364 if (primary)
14365 drm_plane_cleanup(primary);
14366 if (cursor)
14367 drm_plane_cleanup(cursor);
14368 kfree(crtc_state);
14369 kfree(intel_crtc);
14370 }
14371
14372 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14373 {
14374 struct drm_encoder *encoder = connector->base.encoder;
14375 struct drm_device *dev = connector->base.dev;
14376
14377 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14378
14379 if (!encoder || WARN_ON(!encoder->crtc))
14380 return INVALID_PIPE;
14381
14382 return to_intel_crtc(encoder->crtc)->pipe;
14383 }
14384
14385 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14386 struct drm_file *file)
14387 {
14388 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14389 struct drm_crtc *drmmode_crtc;
14390 struct intel_crtc *crtc;
14391
14392 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14393
14394 if (!drmmode_crtc) {
14395 DRM_ERROR("no such CRTC id\n");
14396 return -ENOENT;
14397 }
14398
14399 crtc = to_intel_crtc(drmmode_crtc);
14400 pipe_from_crtc_id->pipe = crtc->pipe;
14401
14402 return 0;
14403 }
14404
14405 static int intel_encoder_clones(struct intel_encoder *encoder)
14406 {
14407 struct drm_device *dev = encoder->base.dev;
14408 struct intel_encoder *source_encoder;
14409 int index_mask = 0;
14410 int entry = 0;
14411
14412 for_each_intel_encoder(dev, source_encoder) {
14413 if (encoders_cloneable(encoder, source_encoder))
14414 index_mask |= (1 << entry);
14415
14416 entry++;
14417 }
14418
14419 return index_mask;
14420 }
14421
14422 static bool has_edp_a(struct drm_device *dev)
14423 {
14424 struct drm_i915_private *dev_priv = dev->dev_private;
14425
14426 if (!IS_MOBILE(dev))
14427 return false;
14428
14429 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14430 return false;
14431
14432 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14433 return false;
14434
14435 return true;
14436 }
14437
14438 static bool intel_crt_present(struct drm_device *dev)
14439 {
14440 struct drm_i915_private *dev_priv = dev->dev_private;
14441
14442 if (INTEL_INFO(dev)->gen >= 9)
14443 return false;
14444
14445 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14446 return false;
14447
14448 if (IS_CHERRYVIEW(dev))
14449 return false;
14450
14451 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14452 return false;
14453
14454 /* DDI E can't be used if DDI A requires 4 lanes */
14455 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14456 return false;
14457
14458 if (!dev_priv->vbt.int_crt_support)
14459 return false;
14460
14461 return true;
14462 }
14463
14464 static void intel_setup_outputs(struct drm_device *dev)
14465 {
14466 struct drm_i915_private *dev_priv = dev->dev_private;
14467 struct intel_encoder *encoder;
14468 bool dpd_is_edp = false;
14469
14470 intel_lvds_init(dev);
14471
14472 if (intel_crt_present(dev))
14473 intel_crt_init(dev);
14474
14475 if (IS_BROXTON(dev)) {
14476 /*
14477 * FIXME: Broxton doesn't support port detection via the
14478 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14479 * detect the ports.
14480 */
14481 intel_ddi_init(dev, PORT_A);
14482 intel_ddi_init(dev, PORT_B);
14483 intel_ddi_init(dev, PORT_C);
14484
14485 intel_dsi_init(dev);
14486 } else if (HAS_DDI(dev)) {
14487 int found;
14488
14489 /*
14490 * Haswell uses DDI functions to detect digital outputs.
14491 * On SKL pre-D0 the strap isn't connected, so we assume
14492 * it's there.
14493 */
14494 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14495 /* WaIgnoreDDIAStrap: skl */
14496 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14497 intel_ddi_init(dev, PORT_A);
14498
14499 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14500 * register */
14501 found = I915_READ(SFUSE_STRAP);
14502
14503 if (found & SFUSE_STRAP_DDIB_DETECTED)
14504 intel_ddi_init(dev, PORT_B);
14505 if (found & SFUSE_STRAP_DDIC_DETECTED)
14506 intel_ddi_init(dev, PORT_C);
14507 if (found & SFUSE_STRAP_DDID_DETECTED)
14508 intel_ddi_init(dev, PORT_D);
14509 /*
14510 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14511 */
14512 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14513 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14514 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14515 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14516 intel_ddi_init(dev, PORT_E);
14517
14518 } else if (HAS_PCH_SPLIT(dev)) {
14519 int found;
14520 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14521
14522 if (has_edp_a(dev))
14523 intel_dp_init(dev, DP_A, PORT_A);
14524
14525 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14526 /* PCH SDVOB multiplex with HDMIB */
14527 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14528 if (!found)
14529 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14530 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14531 intel_dp_init(dev, PCH_DP_B, PORT_B);
14532 }
14533
14534 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14535 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14536
14537 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14538 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14539
14540 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14541 intel_dp_init(dev, PCH_DP_C, PORT_C);
14542
14543 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14544 intel_dp_init(dev, PCH_DP_D, PORT_D);
14545 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14546 /*
14547 * The DP_DETECTED bit is the latched state of the DDC
14548 * SDA pin at boot. However since eDP doesn't require DDC
14549 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14550 * eDP ports may have been muxed to an alternate function.
14551 * Thus we can't rely on the DP_DETECTED bit alone to detect
14552 * eDP ports. Consult the VBT as well as DP_DETECTED to
14553 * detect eDP ports.
14554 */
14555 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14556 !intel_dp_is_edp(dev, PORT_B))
14557 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14558 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14559 intel_dp_is_edp(dev, PORT_B))
14560 intel_dp_init(dev, VLV_DP_B, PORT_B);
14561
14562 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14563 !intel_dp_is_edp(dev, PORT_C))
14564 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14565 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14566 intel_dp_is_edp(dev, PORT_C))
14567 intel_dp_init(dev, VLV_DP_C, PORT_C);
14568
14569 if (IS_CHERRYVIEW(dev)) {
14570 /* eDP not supported on port D, so don't check VBT */
14571 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14572 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14573 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14574 intel_dp_init(dev, CHV_DP_D, PORT_D);
14575 }
14576
14577 intel_dsi_init(dev);
14578 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14579 bool found = false;
14580
14581 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14582 DRM_DEBUG_KMS("probing SDVOB\n");
14583 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14584 if (!found && IS_G4X(dev)) {
14585 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14586 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14587 }
14588
14589 if (!found && IS_G4X(dev))
14590 intel_dp_init(dev, DP_B, PORT_B);
14591 }
14592
14593 /* Before G4X SDVOC doesn't have its own detect register */
14594
14595 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14596 DRM_DEBUG_KMS("probing SDVOC\n");
14597 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14598 }
14599
14600 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14601
14602 if (IS_G4X(dev)) {
14603 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14604 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14605 }
14606 if (IS_G4X(dev))
14607 intel_dp_init(dev, DP_C, PORT_C);
14608 }
14609
14610 if (IS_G4X(dev) &&
14611 (I915_READ(DP_D) & DP_DETECTED))
14612 intel_dp_init(dev, DP_D, PORT_D);
14613 } else if (IS_GEN2(dev))
14614 intel_dvo_init(dev);
14615
14616 if (SUPPORTS_TV(dev))
14617 intel_tv_init(dev);
14618
14619 intel_psr_init(dev);
14620
14621 for_each_intel_encoder(dev, encoder) {
14622 encoder->base.possible_crtcs = encoder->crtc_mask;
14623 encoder->base.possible_clones =
14624 intel_encoder_clones(encoder);
14625 }
14626
14627 intel_init_pch_refclk(dev);
14628
14629 drm_helper_move_panel_connectors_to_head(dev);
14630 }
14631
14632 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14633 {
14634 struct drm_device *dev = fb->dev;
14635 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14636
14637 drm_framebuffer_cleanup(fb);
14638 mutex_lock(&dev->struct_mutex);
14639 WARN_ON(!intel_fb->obj->framebuffer_references--);
14640 drm_gem_object_unreference(&intel_fb->obj->base);
14641 mutex_unlock(&dev->struct_mutex);
14642 kfree(intel_fb);
14643 }
14644
14645 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14646 struct drm_file *file,
14647 unsigned int *handle)
14648 {
14649 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14650 struct drm_i915_gem_object *obj = intel_fb->obj;
14651
14652 if (obj->userptr.mm) {
14653 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14654 return -EINVAL;
14655 }
14656
14657 return drm_gem_handle_create(file, &obj->base, handle);
14658 }
14659
14660 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14661 struct drm_file *file,
14662 unsigned flags, unsigned color,
14663 struct drm_clip_rect *clips,
14664 unsigned num_clips)
14665 {
14666 struct drm_device *dev = fb->dev;
14667 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14668 struct drm_i915_gem_object *obj = intel_fb->obj;
14669
14670 mutex_lock(&dev->struct_mutex);
14671 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14672 mutex_unlock(&dev->struct_mutex);
14673
14674 return 0;
14675 }
14676
14677 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14678 .destroy = intel_user_framebuffer_destroy,
14679 .create_handle = intel_user_framebuffer_create_handle,
14680 .dirty = intel_user_framebuffer_dirty,
14681 };
14682
14683 static
14684 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14685 uint32_t pixel_format)
14686 {
14687 u32 gen = INTEL_INFO(dev)->gen;
14688
14689 if (gen >= 9) {
14690 int cpp = drm_format_plane_cpp(pixel_format, 0);
14691
14692 /* "The stride in bytes must not exceed the of the size of 8K
14693 * pixels and 32K bytes."
14694 */
14695 return min(8192 * cpp, 32768);
14696 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14697 return 32*1024;
14698 } else if (gen >= 4) {
14699 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14700 return 16*1024;
14701 else
14702 return 32*1024;
14703 } else if (gen >= 3) {
14704 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14705 return 8*1024;
14706 else
14707 return 16*1024;
14708 } else {
14709 /* XXX DSPC is limited to 4k tiled */
14710 return 8*1024;
14711 }
14712 }
14713
14714 static int intel_framebuffer_init(struct drm_device *dev,
14715 struct intel_framebuffer *intel_fb,
14716 struct drm_mode_fb_cmd2 *mode_cmd,
14717 struct drm_i915_gem_object *obj)
14718 {
14719 struct drm_i915_private *dev_priv = to_i915(dev);
14720 unsigned int aligned_height;
14721 int ret;
14722 u32 pitch_limit, stride_alignment;
14723
14724 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14725
14726 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14727 /* Enforce that fb modifier and tiling mode match, but only for
14728 * X-tiled. This is needed for FBC. */
14729 if (!!(obj->tiling_mode == I915_TILING_X) !=
14730 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14731 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14732 return -EINVAL;
14733 }
14734 } else {
14735 if (obj->tiling_mode == I915_TILING_X)
14736 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14737 else if (obj->tiling_mode == I915_TILING_Y) {
14738 DRM_DEBUG("No Y tiling for legacy addfb\n");
14739 return -EINVAL;
14740 }
14741 }
14742
14743 /* Passed in modifier sanity checking. */
14744 switch (mode_cmd->modifier[0]) {
14745 case I915_FORMAT_MOD_Y_TILED:
14746 case I915_FORMAT_MOD_Yf_TILED:
14747 if (INTEL_INFO(dev)->gen < 9) {
14748 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14749 mode_cmd->modifier[0]);
14750 return -EINVAL;
14751 }
14752 case DRM_FORMAT_MOD_NONE:
14753 case I915_FORMAT_MOD_X_TILED:
14754 break;
14755 default:
14756 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14757 mode_cmd->modifier[0]);
14758 return -EINVAL;
14759 }
14760
14761 stride_alignment = intel_fb_stride_alignment(dev_priv,
14762 mode_cmd->modifier[0],
14763 mode_cmd->pixel_format);
14764 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14765 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14766 mode_cmd->pitches[0], stride_alignment);
14767 return -EINVAL;
14768 }
14769
14770 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14771 mode_cmd->pixel_format);
14772 if (mode_cmd->pitches[0] > pitch_limit) {
14773 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14774 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14775 "tiled" : "linear",
14776 mode_cmd->pitches[0], pitch_limit);
14777 return -EINVAL;
14778 }
14779
14780 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14781 mode_cmd->pitches[0] != obj->stride) {
14782 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14783 mode_cmd->pitches[0], obj->stride);
14784 return -EINVAL;
14785 }
14786
14787 /* Reject formats not supported by any plane early. */
14788 switch (mode_cmd->pixel_format) {
14789 case DRM_FORMAT_C8:
14790 case DRM_FORMAT_RGB565:
14791 case DRM_FORMAT_XRGB8888:
14792 case DRM_FORMAT_ARGB8888:
14793 break;
14794 case DRM_FORMAT_XRGB1555:
14795 if (INTEL_INFO(dev)->gen > 3) {
14796 DRM_DEBUG("unsupported pixel format: %s\n",
14797 drm_get_format_name(mode_cmd->pixel_format));
14798 return -EINVAL;
14799 }
14800 break;
14801 case DRM_FORMAT_ABGR8888:
14802 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14803 INTEL_INFO(dev)->gen < 9) {
14804 DRM_DEBUG("unsupported pixel format: %s\n",
14805 drm_get_format_name(mode_cmd->pixel_format));
14806 return -EINVAL;
14807 }
14808 break;
14809 case DRM_FORMAT_XBGR8888:
14810 case DRM_FORMAT_XRGB2101010:
14811 case DRM_FORMAT_XBGR2101010:
14812 if (INTEL_INFO(dev)->gen < 4) {
14813 DRM_DEBUG("unsupported pixel format: %s\n",
14814 drm_get_format_name(mode_cmd->pixel_format));
14815 return -EINVAL;
14816 }
14817 break;
14818 case DRM_FORMAT_ABGR2101010:
14819 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14820 DRM_DEBUG("unsupported pixel format: %s\n",
14821 drm_get_format_name(mode_cmd->pixel_format));
14822 return -EINVAL;
14823 }
14824 break;
14825 case DRM_FORMAT_YUYV:
14826 case DRM_FORMAT_UYVY:
14827 case DRM_FORMAT_YVYU:
14828 case DRM_FORMAT_VYUY:
14829 if (INTEL_INFO(dev)->gen < 5) {
14830 DRM_DEBUG("unsupported pixel format: %s\n",
14831 drm_get_format_name(mode_cmd->pixel_format));
14832 return -EINVAL;
14833 }
14834 break;
14835 default:
14836 DRM_DEBUG("unsupported pixel format: %s\n",
14837 drm_get_format_name(mode_cmd->pixel_format));
14838 return -EINVAL;
14839 }
14840
14841 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14842 if (mode_cmd->offsets[0] != 0)
14843 return -EINVAL;
14844
14845 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14846 mode_cmd->pixel_format,
14847 mode_cmd->modifier[0]);
14848 /* FIXME drm helper for size checks (especially planar formats)? */
14849 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14850 return -EINVAL;
14851
14852 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14853 intel_fb->obj = obj;
14854
14855 intel_fill_fb_info(dev_priv, &intel_fb->base);
14856
14857 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14858 if (ret) {
14859 DRM_ERROR("framebuffer init failed %d\n", ret);
14860 return ret;
14861 }
14862
14863 intel_fb->obj->framebuffer_references++;
14864
14865 return 0;
14866 }
14867
14868 static struct drm_framebuffer *
14869 intel_user_framebuffer_create(struct drm_device *dev,
14870 struct drm_file *filp,
14871 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14872 {
14873 struct drm_framebuffer *fb;
14874 struct drm_i915_gem_object *obj;
14875 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14876
14877 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14878 mode_cmd.handles[0]));
14879 if (&obj->base == NULL)
14880 return ERR_PTR(-ENOENT);
14881
14882 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14883 if (IS_ERR(fb))
14884 drm_gem_object_unreference_unlocked(&obj->base);
14885
14886 return fb;
14887 }
14888
14889 #ifndef CONFIG_DRM_FBDEV_EMULATION
14890 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14891 {
14892 }
14893 #endif
14894
14895 static const struct drm_mode_config_funcs intel_mode_funcs = {
14896 .fb_create = intel_user_framebuffer_create,
14897 .output_poll_changed = intel_fbdev_output_poll_changed,
14898 .atomic_check = intel_atomic_check,
14899 .atomic_commit = intel_atomic_commit,
14900 .atomic_state_alloc = intel_atomic_state_alloc,
14901 .atomic_state_clear = intel_atomic_state_clear,
14902 };
14903
14904 /**
14905 * intel_init_display_hooks - initialize the display modesetting hooks
14906 * @dev_priv: device private
14907 */
14908 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14909 {
14910 if (INTEL_INFO(dev_priv)->gen >= 9) {
14911 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14912 dev_priv->display.get_initial_plane_config =
14913 skylake_get_initial_plane_config;
14914 dev_priv->display.crtc_compute_clock =
14915 haswell_crtc_compute_clock;
14916 dev_priv->display.crtc_enable = haswell_crtc_enable;
14917 dev_priv->display.crtc_disable = haswell_crtc_disable;
14918 } else if (HAS_DDI(dev_priv)) {
14919 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14920 dev_priv->display.get_initial_plane_config =
14921 ironlake_get_initial_plane_config;
14922 dev_priv->display.crtc_compute_clock =
14923 haswell_crtc_compute_clock;
14924 dev_priv->display.crtc_enable = haswell_crtc_enable;
14925 dev_priv->display.crtc_disable = haswell_crtc_disable;
14926 } else if (HAS_PCH_SPLIT(dev_priv)) {
14927 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14928 dev_priv->display.get_initial_plane_config =
14929 ironlake_get_initial_plane_config;
14930 dev_priv->display.crtc_compute_clock =
14931 ironlake_crtc_compute_clock;
14932 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14933 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14934 } else if (IS_CHERRYVIEW(dev_priv)) {
14935 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14936 dev_priv->display.get_initial_plane_config =
14937 i9xx_get_initial_plane_config;
14938 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14939 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14940 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14941 } else if (IS_VALLEYVIEW(dev_priv)) {
14942 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14943 dev_priv->display.get_initial_plane_config =
14944 i9xx_get_initial_plane_config;
14945 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14946 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14947 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14948 } else if (IS_G4X(dev_priv)) {
14949 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14950 dev_priv->display.get_initial_plane_config =
14951 i9xx_get_initial_plane_config;
14952 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14953 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14954 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14955 } else if (IS_PINEVIEW(dev_priv)) {
14956 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14957 dev_priv->display.get_initial_plane_config =
14958 i9xx_get_initial_plane_config;
14959 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14960 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14961 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14962 } else if (!IS_GEN2(dev_priv)) {
14963 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14964 dev_priv->display.get_initial_plane_config =
14965 i9xx_get_initial_plane_config;
14966 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14967 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14968 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14969 } else {
14970 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14971 dev_priv->display.get_initial_plane_config =
14972 i9xx_get_initial_plane_config;
14973 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14974 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14975 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14976 }
14977
14978 /* Returns the core display clock speed */
14979 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14980 dev_priv->display.get_display_clock_speed =
14981 skylake_get_display_clock_speed;
14982 else if (IS_BROXTON(dev_priv))
14983 dev_priv->display.get_display_clock_speed =
14984 broxton_get_display_clock_speed;
14985 else if (IS_BROADWELL(dev_priv))
14986 dev_priv->display.get_display_clock_speed =
14987 broadwell_get_display_clock_speed;
14988 else if (IS_HASWELL(dev_priv))
14989 dev_priv->display.get_display_clock_speed =
14990 haswell_get_display_clock_speed;
14991 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14992 dev_priv->display.get_display_clock_speed =
14993 valleyview_get_display_clock_speed;
14994 else if (IS_GEN5(dev_priv))
14995 dev_priv->display.get_display_clock_speed =
14996 ilk_get_display_clock_speed;
14997 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14998 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14999 dev_priv->display.get_display_clock_speed =
15000 i945_get_display_clock_speed;
15001 else if (IS_GM45(dev_priv))
15002 dev_priv->display.get_display_clock_speed =
15003 gm45_get_display_clock_speed;
15004 else if (IS_CRESTLINE(dev_priv))
15005 dev_priv->display.get_display_clock_speed =
15006 i965gm_get_display_clock_speed;
15007 else if (IS_PINEVIEW(dev_priv))
15008 dev_priv->display.get_display_clock_speed =
15009 pnv_get_display_clock_speed;
15010 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15011 dev_priv->display.get_display_clock_speed =
15012 g33_get_display_clock_speed;
15013 else if (IS_I915G(dev_priv))
15014 dev_priv->display.get_display_clock_speed =
15015 i915_get_display_clock_speed;
15016 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15017 dev_priv->display.get_display_clock_speed =
15018 i9xx_misc_get_display_clock_speed;
15019 else if (IS_I915GM(dev_priv))
15020 dev_priv->display.get_display_clock_speed =
15021 i915gm_get_display_clock_speed;
15022 else if (IS_I865G(dev_priv))
15023 dev_priv->display.get_display_clock_speed =
15024 i865_get_display_clock_speed;
15025 else if (IS_I85X(dev_priv))
15026 dev_priv->display.get_display_clock_speed =
15027 i85x_get_display_clock_speed;
15028 else { /* 830 */
15029 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15030 dev_priv->display.get_display_clock_speed =
15031 i830_get_display_clock_speed;
15032 }
15033
15034 if (IS_GEN5(dev_priv)) {
15035 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15036 } else if (IS_GEN6(dev_priv)) {
15037 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15038 } else if (IS_IVYBRIDGE(dev_priv)) {
15039 /* FIXME: detect B0+ stepping and use auto training */
15040 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15041 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15042 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15043 if (IS_BROADWELL(dev_priv)) {
15044 dev_priv->display.modeset_commit_cdclk =
15045 broadwell_modeset_commit_cdclk;
15046 dev_priv->display.modeset_calc_cdclk =
15047 broadwell_modeset_calc_cdclk;
15048 }
15049 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15050 dev_priv->display.modeset_commit_cdclk =
15051 valleyview_modeset_commit_cdclk;
15052 dev_priv->display.modeset_calc_cdclk =
15053 valleyview_modeset_calc_cdclk;
15054 } else if (IS_BROXTON(dev_priv)) {
15055 dev_priv->display.modeset_commit_cdclk =
15056 broxton_modeset_commit_cdclk;
15057 dev_priv->display.modeset_calc_cdclk =
15058 broxton_modeset_calc_cdclk;
15059 }
15060
15061 switch (INTEL_INFO(dev_priv)->gen) {
15062 case 2:
15063 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15064 break;
15065
15066 case 3:
15067 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15068 break;
15069
15070 case 4:
15071 case 5:
15072 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15073 break;
15074
15075 case 6:
15076 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15077 break;
15078 case 7:
15079 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15080 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15081 break;
15082 case 9:
15083 /* Drop through - unsupported since execlist only. */
15084 default:
15085 /* Default just returns -ENODEV to indicate unsupported */
15086 dev_priv->display.queue_flip = intel_default_queue_flip;
15087 }
15088 }
15089
15090 /*
15091 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15092 * resume, or other times. This quirk makes sure that's the case for
15093 * affected systems.
15094 */
15095 static void quirk_pipea_force(struct drm_device *dev)
15096 {
15097 struct drm_i915_private *dev_priv = dev->dev_private;
15098
15099 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15100 DRM_INFO("applying pipe a force quirk\n");
15101 }
15102
15103 static void quirk_pipeb_force(struct drm_device *dev)
15104 {
15105 struct drm_i915_private *dev_priv = dev->dev_private;
15106
15107 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15108 DRM_INFO("applying pipe b force quirk\n");
15109 }
15110
15111 /*
15112 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15113 */
15114 static void quirk_ssc_force_disable(struct drm_device *dev)
15115 {
15116 struct drm_i915_private *dev_priv = dev->dev_private;
15117 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15118 DRM_INFO("applying lvds SSC disable quirk\n");
15119 }
15120
15121 /*
15122 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15123 * brightness value
15124 */
15125 static void quirk_invert_brightness(struct drm_device *dev)
15126 {
15127 struct drm_i915_private *dev_priv = dev->dev_private;
15128 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15129 DRM_INFO("applying inverted panel brightness quirk\n");
15130 }
15131
15132 /* Some VBT's incorrectly indicate no backlight is present */
15133 static void quirk_backlight_present(struct drm_device *dev)
15134 {
15135 struct drm_i915_private *dev_priv = dev->dev_private;
15136 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15137 DRM_INFO("applying backlight present quirk\n");
15138 }
15139
15140 struct intel_quirk {
15141 int device;
15142 int subsystem_vendor;
15143 int subsystem_device;
15144 void (*hook)(struct drm_device *dev);
15145 };
15146
15147 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15148 struct intel_dmi_quirk {
15149 void (*hook)(struct drm_device *dev);
15150 const struct dmi_system_id (*dmi_id_list)[];
15151 };
15152
15153 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15154 {
15155 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15156 return 1;
15157 }
15158
15159 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15160 {
15161 .dmi_id_list = &(const struct dmi_system_id[]) {
15162 {
15163 .callback = intel_dmi_reverse_brightness,
15164 .ident = "NCR Corporation",
15165 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15166 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15167 },
15168 },
15169 { } /* terminating entry */
15170 },
15171 .hook = quirk_invert_brightness,
15172 },
15173 };
15174
15175 static struct intel_quirk intel_quirks[] = {
15176 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15177 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15178
15179 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15180 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15181
15182 /* 830 needs to leave pipe A & dpll A up */
15183 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15184
15185 /* 830 needs to leave pipe B & dpll B up */
15186 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15187
15188 /* Lenovo U160 cannot use SSC on LVDS */
15189 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15190
15191 /* Sony Vaio Y cannot use SSC on LVDS */
15192 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15193
15194 /* Acer Aspire 5734Z must invert backlight brightness */
15195 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15196
15197 /* Acer/eMachines G725 */
15198 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15199
15200 /* Acer/eMachines e725 */
15201 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15202
15203 /* Acer/Packard Bell NCL20 */
15204 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15205
15206 /* Acer Aspire 4736Z */
15207 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15208
15209 /* Acer Aspire 5336 */
15210 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15211
15212 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15213 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15214
15215 /* Acer C720 Chromebook (Core i3 4005U) */
15216 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15217
15218 /* Apple Macbook 2,1 (Core 2 T7400) */
15219 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15220
15221 /* Apple Macbook 4,1 */
15222 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15223
15224 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15225 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15226
15227 /* HP Chromebook 14 (Celeron 2955U) */
15228 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15229
15230 /* Dell Chromebook 11 */
15231 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15232
15233 /* Dell Chromebook 11 (2015 version) */
15234 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15235 };
15236
15237 static void intel_init_quirks(struct drm_device *dev)
15238 {
15239 struct pci_dev *d = dev->pdev;
15240 int i;
15241
15242 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15243 struct intel_quirk *q = &intel_quirks[i];
15244
15245 if (d->device == q->device &&
15246 (d->subsystem_vendor == q->subsystem_vendor ||
15247 q->subsystem_vendor == PCI_ANY_ID) &&
15248 (d->subsystem_device == q->subsystem_device ||
15249 q->subsystem_device == PCI_ANY_ID))
15250 q->hook(dev);
15251 }
15252 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15253 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15254 intel_dmi_quirks[i].hook(dev);
15255 }
15256 }
15257
15258 /* Disable the VGA plane that we never use */
15259 static void i915_disable_vga(struct drm_device *dev)
15260 {
15261 struct drm_i915_private *dev_priv = dev->dev_private;
15262 u8 sr1;
15263 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15264
15265 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15266 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15267 outb(SR01, VGA_SR_INDEX);
15268 sr1 = inb(VGA_SR_DATA);
15269 outb(sr1 | 1<<5, VGA_SR_DATA);
15270 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15271 udelay(300);
15272
15273 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15274 POSTING_READ(vga_reg);
15275 }
15276
15277 void intel_modeset_init_hw(struct drm_device *dev)
15278 {
15279 struct drm_i915_private *dev_priv = dev->dev_private;
15280
15281 intel_update_cdclk(dev);
15282
15283 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15284
15285 intel_init_clock_gating(dev);
15286 intel_enable_gt_powersave(dev_priv);
15287 }
15288
15289 /*
15290 * Calculate what we think the watermarks should be for the state we've read
15291 * out of the hardware and then immediately program those watermarks so that
15292 * we ensure the hardware settings match our internal state.
15293 *
15294 * We can calculate what we think WM's should be by creating a duplicate of the
15295 * current state (which was constructed during hardware readout) and running it
15296 * through the atomic check code to calculate new watermark values in the
15297 * state object.
15298 */
15299 static void sanitize_watermarks(struct drm_device *dev)
15300 {
15301 struct drm_i915_private *dev_priv = to_i915(dev);
15302 struct drm_atomic_state *state;
15303 struct drm_crtc *crtc;
15304 struct drm_crtc_state *cstate;
15305 struct drm_modeset_acquire_ctx ctx;
15306 int ret;
15307 int i;
15308
15309 /* Only supported on platforms that use atomic watermark design */
15310 if (!dev_priv->display.optimize_watermarks)
15311 return;
15312
15313 /*
15314 * We need to hold connection_mutex before calling duplicate_state so
15315 * that the connector loop is protected.
15316 */
15317 drm_modeset_acquire_init(&ctx, 0);
15318 retry:
15319 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15320 if (ret == -EDEADLK) {
15321 drm_modeset_backoff(&ctx);
15322 goto retry;
15323 } else if (WARN_ON(ret)) {
15324 goto fail;
15325 }
15326
15327 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15328 if (WARN_ON(IS_ERR(state)))
15329 goto fail;
15330
15331 /*
15332 * Hardware readout is the only time we don't want to calculate
15333 * intermediate watermarks (since we don't trust the current
15334 * watermarks).
15335 */
15336 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15337
15338 ret = intel_atomic_check(dev, state);
15339 if (ret) {
15340 /*
15341 * If we fail here, it means that the hardware appears to be
15342 * programmed in a way that shouldn't be possible, given our
15343 * understanding of watermark requirements. This might mean a
15344 * mistake in the hardware readout code or a mistake in the
15345 * watermark calculations for a given platform. Raise a WARN
15346 * so that this is noticeable.
15347 *
15348 * If this actually happens, we'll have to just leave the
15349 * BIOS-programmed watermarks untouched and hope for the best.
15350 */
15351 WARN(true, "Could not determine valid watermarks for inherited state\n");
15352 goto fail;
15353 }
15354
15355 /* Write calculated watermark values back */
15356 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15357 for_each_crtc_in_state(state, crtc, cstate, i) {
15358 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15359
15360 cs->wm.need_postvbl_update = true;
15361 dev_priv->display.optimize_watermarks(cs);
15362 }
15363
15364 drm_atomic_state_free(state);
15365 fail:
15366 drm_modeset_drop_locks(&ctx);
15367 drm_modeset_acquire_fini(&ctx);
15368 }
15369
15370 void intel_modeset_init(struct drm_device *dev)
15371 {
15372 struct drm_i915_private *dev_priv = to_i915(dev);
15373 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15374 int sprite, ret;
15375 enum pipe pipe;
15376 struct intel_crtc *crtc;
15377
15378 drm_mode_config_init(dev);
15379
15380 dev->mode_config.min_width = 0;
15381 dev->mode_config.min_height = 0;
15382
15383 dev->mode_config.preferred_depth = 24;
15384 dev->mode_config.prefer_shadow = 1;
15385
15386 dev->mode_config.allow_fb_modifiers = true;
15387
15388 dev->mode_config.funcs = &intel_mode_funcs;
15389
15390 intel_init_quirks(dev);
15391
15392 intel_init_pm(dev);
15393
15394 if (INTEL_INFO(dev)->num_pipes == 0)
15395 return;
15396
15397 /*
15398 * There may be no VBT; and if the BIOS enabled SSC we can
15399 * just keep using it to avoid unnecessary flicker. Whereas if the
15400 * BIOS isn't using it, don't assume it will work even if the VBT
15401 * indicates as much.
15402 */
15403 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15404 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15405 DREF_SSC1_ENABLE);
15406
15407 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15408 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15409 bios_lvds_use_ssc ? "en" : "dis",
15410 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15411 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15412 }
15413 }
15414
15415 if (IS_GEN2(dev)) {
15416 dev->mode_config.max_width = 2048;
15417 dev->mode_config.max_height = 2048;
15418 } else if (IS_GEN3(dev)) {
15419 dev->mode_config.max_width = 4096;
15420 dev->mode_config.max_height = 4096;
15421 } else {
15422 dev->mode_config.max_width = 8192;
15423 dev->mode_config.max_height = 8192;
15424 }
15425
15426 if (IS_845G(dev) || IS_I865G(dev)) {
15427 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15428 dev->mode_config.cursor_height = 1023;
15429 } else if (IS_GEN2(dev)) {
15430 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15431 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15432 } else {
15433 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15434 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15435 }
15436
15437 dev->mode_config.fb_base = ggtt->mappable_base;
15438
15439 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15440 INTEL_INFO(dev)->num_pipes,
15441 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15442
15443 for_each_pipe(dev_priv, pipe) {
15444 intel_crtc_init(dev, pipe);
15445 for_each_sprite(dev_priv, pipe, sprite) {
15446 ret = intel_plane_init(dev, pipe, sprite);
15447 if (ret)
15448 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15449 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15450 }
15451 }
15452
15453 intel_update_czclk(dev_priv);
15454 intel_update_cdclk(dev);
15455
15456 intel_shared_dpll_init(dev);
15457
15458 /* Just disable it once at startup */
15459 i915_disable_vga(dev);
15460 intel_setup_outputs(dev);
15461
15462 drm_modeset_lock_all(dev);
15463 intel_modeset_setup_hw_state(dev);
15464 drm_modeset_unlock_all(dev);
15465
15466 for_each_intel_crtc(dev, crtc) {
15467 struct intel_initial_plane_config plane_config = {};
15468
15469 if (!crtc->active)
15470 continue;
15471
15472 /*
15473 * Note that reserving the BIOS fb up front prevents us
15474 * from stuffing other stolen allocations like the ring
15475 * on top. This prevents some ugliness at boot time, and
15476 * can even allow for smooth boot transitions if the BIOS
15477 * fb is large enough for the active pipe configuration.
15478 */
15479 dev_priv->display.get_initial_plane_config(crtc,
15480 &plane_config);
15481
15482 /*
15483 * If the fb is shared between multiple heads, we'll
15484 * just get the first one.
15485 */
15486 intel_find_initial_plane_obj(crtc, &plane_config);
15487 }
15488
15489 /*
15490 * Make sure hardware watermarks really match the state we read out.
15491 * Note that we need to do this after reconstructing the BIOS fb's
15492 * since the watermark calculation done here will use pstate->fb.
15493 */
15494 sanitize_watermarks(dev);
15495 }
15496
15497 static void intel_enable_pipe_a(struct drm_device *dev)
15498 {
15499 struct intel_connector *connector;
15500 struct drm_connector *crt = NULL;
15501 struct intel_load_detect_pipe load_detect_temp;
15502 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15503
15504 /* We can't just switch on the pipe A, we need to set things up with a
15505 * proper mode and output configuration. As a gross hack, enable pipe A
15506 * by enabling the load detect pipe once. */
15507 for_each_intel_connector(dev, connector) {
15508 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15509 crt = &connector->base;
15510 break;
15511 }
15512 }
15513
15514 if (!crt)
15515 return;
15516
15517 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15518 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15519 }
15520
15521 static bool
15522 intel_check_plane_mapping(struct intel_crtc *crtc)
15523 {
15524 struct drm_device *dev = crtc->base.dev;
15525 struct drm_i915_private *dev_priv = dev->dev_private;
15526 u32 val;
15527
15528 if (INTEL_INFO(dev)->num_pipes == 1)
15529 return true;
15530
15531 val = I915_READ(DSPCNTR(!crtc->plane));
15532
15533 if ((val & DISPLAY_PLANE_ENABLE) &&
15534 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15535 return false;
15536
15537 return true;
15538 }
15539
15540 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15541 {
15542 struct drm_device *dev = crtc->base.dev;
15543 struct intel_encoder *encoder;
15544
15545 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15546 return true;
15547
15548 return false;
15549 }
15550
15551 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15552 {
15553 struct drm_device *dev = encoder->base.dev;
15554 struct intel_connector *connector;
15555
15556 for_each_connector_on_encoder(dev, &encoder->base, connector)
15557 return true;
15558
15559 return false;
15560 }
15561
15562 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15563 {
15564 struct drm_device *dev = crtc->base.dev;
15565 struct drm_i915_private *dev_priv = dev->dev_private;
15566 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15567
15568 /* Clear any frame start delays used for debugging left by the BIOS */
15569 if (!transcoder_is_dsi(cpu_transcoder)) {
15570 i915_reg_t reg = PIPECONF(cpu_transcoder);
15571
15572 I915_WRITE(reg,
15573 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15574 }
15575
15576 /* restore vblank interrupts to correct state */
15577 drm_crtc_vblank_reset(&crtc->base);
15578 if (crtc->active) {
15579 struct intel_plane *plane;
15580
15581 drm_crtc_vblank_on(&crtc->base);
15582
15583 /* Disable everything but the primary plane */
15584 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15585 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15586 continue;
15587
15588 plane->disable_plane(&plane->base, &crtc->base);
15589 }
15590 }
15591
15592 /* We need to sanitize the plane -> pipe mapping first because this will
15593 * disable the crtc (and hence change the state) if it is wrong. Note
15594 * that gen4+ has a fixed plane -> pipe mapping. */
15595 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15596 bool plane;
15597
15598 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15599 crtc->base.base.id);
15600
15601 /* Pipe has the wrong plane attached and the plane is active.
15602 * Temporarily change the plane mapping and disable everything
15603 * ... */
15604 plane = crtc->plane;
15605 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15606 crtc->plane = !plane;
15607 intel_crtc_disable_noatomic(&crtc->base);
15608 crtc->plane = plane;
15609 }
15610
15611 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15612 crtc->pipe == PIPE_A && !crtc->active) {
15613 /* BIOS forgot to enable pipe A, this mostly happens after
15614 * resume. Force-enable the pipe to fix this, the update_dpms
15615 * call below we restore the pipe to the right state, but leave
15616 * the required bits on. */
15617 intel_enable_pipe_a(dev);
15618 }
15619
15620 /* Adjust the state of the output pipe according to whether we
15621 * have active connectors/encoders. */
15622 if (crtc->active && !intel_crtc_has_encoders(crtc))
15623 intel_crtc_disable_noatomic(&crtc->base);
15624
15625 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15626 /*
15627 * We start out with underrun reporting disabled to avoid races.
15628 * For correct bookkeeping mark this on active crtcs.
15629 *
15630 * Also on gmch platforms we dont have any hardware bits to
15631 * disable the underrun reporting. Which means we need to start
15632 * out with underrun reporting disabled also on inactive pipes,
15633 * since otherwise we'll complain about the garbage we read when
15634 * e.g. coming up after runtime pm.
15635 *
15636 * No protection against concurrent access is required - at
15637 * worst a fifo underrun happens which also sets this to false.
15638 */
15639 crtc->cpu_fifo_underrun_disabled = true;
15640 crtc->pch_fifo_underrun_disabled = true;
15641 }
15642 }
15643
15644 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15645 {
15646 struct intel_connector *connector;
15647 struct drm_device *dev = encoder->base.dev;
15648
15649 /* We need to check both for a crtc link (meaning that the
15650 * encoder is active and trying to read from a pipe) and the
15651 * pipe itself being active. */
15652 bool has_active_crtc = encoder->base.crtc &&
15653 to_intel_crtc(encoder->base.crtc)->active;
15654
15655 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15656 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15657 encoder->base.base.id,
15658 encoder->base.name);
15659
15660 /* Connector is active, but has no active pipe. This is
15661 * fallout from our resume register restoring. Disable
15662 * the encoder manually again. */
15663 if (encoder->base.crtc) {
15664 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15665 encoder->base.base.id,
15666 encoder->base.name);
15667 encoder->disable(encoder);
15668 if (encoder->post_disable)
15669 encoder->post_disable(encoder);
15670 }
15671 encoder->base.crtc = NULL;
15672
15673 /* Inconsistent output/port/pipe state happens presumably due to
15674 * a bug in one of the get_hw_state functions. Or someplace else
15675 * in our code, like the register restore mess on resume. Clamp
15676 * things to off as a safer default. */
15677 for_each_intel_connector(dev, connector) {
15678 if (connector->encoder != encoder)
15679 continue;
15680 connector->base.dpms = DRM_MODE_DPMS_OFF;
15681 connector->base.encoder = NULL;
15682 }
15683 }
15684 /* Enabled encoders without active connectors will be fixed in
15685 * the crtc fixup. */
15686 }
15687
15688 void i915_redisable_vga_power_on(struct drm_device *dev)
15689 {
15690 struct drm_i915_private *dev_priv = dev->dev_private;
15691 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15692
15693 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15694 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15695 i915_disable_vga(dev);
15696 }
15697 }
15698
15699 void i915_redisable_vga(struct drm_device *dev)
15700 {
15701 struct drm_i915_private *dev_priv = dev->dev_private;
15702
15703 /* This function can be called both from intel_modeset_setup_hw_state or
15704 * at a very early point in our resume sequence, where the power well
15705 * structures are not yet restored. Since this function is at a very
15706 * paranoid "someone might have enabled VGA while we were not looking"
15707 * level, just check if the power well is enabled instead of trying to
15708 * follow the "don't touch the power well if we don't need it" policy
15709 * the rest of the driver uses. */
15710 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15711 return;
15712
15713 i915_redisable_vga_power_on(dev);
15714
15715 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15716 }
15717
15718 static bool primary_get_hw_state(struct intel_plane *plane)
15719 {
15720 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15721
15722 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15723 }
15724
15725 /* FIXME read out full plane state for all planes */
15726 static void readout_plane_state(struct intel_crtc *crtc)
15727 {
15728 struct drm_plane *primary = crtc->base.primary;
15729 struct intel_plane_state *plane_state =
15730 to_intel_plane_state(primary->state);
15731
15732 plane_state->visible = crtc->active &&
15733 primary_get_hw_state(to_intel_plane(primary));
15734
15735 if (plane_state->visible)
15736 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15737 }
15738
15739 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15740 {
15741 struct drm_i915_private *dev_priv = dev->dev_private;
15742 enum pipe pipe;
15743 struct intel_crtc *crtc;
15744 struct intel_encoder *encoder;
15745 struct intel_connector *connector;
15746 int i;
15747
15748 dev_priv->active_crtcs = 0;
15749
15750 for_each_intel_crtc(dev, crtc) {
15751 struct intel_crtc_state *crtc_state = crtc->config;
15752 int pixclk = 0;
15753
15754 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15755 memset(crtc_state, 0, sizeof(*crtc_state));
15756 crtc_state->base.crtc = &crtc->base;
15757
15758 crtc_state->base.active = crtc_state->base.enable =
15759 dev_priv->display.get_pipe_config(crtc, crtc_state);
15760
15761 crtc->base.enabled = crtc_state->base.enable;
15762 crtc->active = crtc_state->base.active;
15763
15764 if (crtc_state->base.active) {
15765 dev_priv->active_crtcs |= 1 << crtc->pipe;
15766
15767 if (IS_BROADWELL(dev_priv)) {
15768 pixclk = ilk_pipe_pixel_rate(crtc_state);
15769
15770 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15771 if (crtc_state->ips_enabled)
15772 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15773 } else if (IS_VALLEYVIEW(dev_priv) ||
15774 IS_CHERRYVIEW(dev_priv) ||
15775 IS_BROXTON(dev_priv))
15776 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15777 else
15778 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15779 }
15780
15781 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15782
15783 readout_plane_state(crtc);
15784
15785 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15786 crtc->base.base.id,
15787 crtc->active ? "enabled" : "disabled");
15788 }
15789
15790 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15791 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15792
15793 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15794 &pll->config.hw_state);
15795 pll->config.crtc_mask = 0;
15796 for_each_intel_crtc(dev, crtc) {
15797 if (crtc->active && crtc->config->shared_dpll == pll)
15798 pll->config.crtc_mask |= 1 << crtc->pipe;
15799 }
15800 pll->active_mask = pll->config.crtc_mask;
15801
15802 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15803 pll->name, pll->config.crtc_mask, pll->on);
15804 }
15805
15806 for_each_intel_encoder(dev, encoder) {
15807 pipe = 0;
15808
15809 if (encoder->get_hw_state(encoder, &pipe)) {
15810 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15811 encoder->base.crtc = &crtc->base;
15812 encoder->get_config(encoder, crtc->config);
15813 } else {
15814 encoder->base.crtc = NULL;
15815 }
15816
15817 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15818 encoder->base.base.id,
15819 encoder->base.name,
15820 encoder->base.crtc ? "enabled" : "disabled",
15821 pipe_name(pipe));
15822 }
15823
15824 for_each_intel_connector(dev, connector) {
15825 if (connector->get_hw_state(connector)) {
15826 connector->base.dpms = DRM_MODE_DPMS_ON;
15827
15828 encoder = connector->encoder;
15829 connector->base.encoder = &encoder->base;
15830
15831 if (encoder->base.crtc &&
15832 encoder->base.crtc->state->active) {
15833 /*
15834 * This has to be done during hardware readout
15835 * because anything calling .crtc_disable may
15836 * rely on the connector_mask being accurate.
15837 */
15838 encoder->base.crtc->state->connector_mask |=
15839 1 << drm_connector_index(&connector->base);
15840 encoder->base.crtc->state->encoder_mask |=
15841 1 << drm_encoder_index(&encoder->base);
15842 }
15843
15844 } else {
15845 connector->base.dpms = DRM_MODE_DPMS_OFF;
15846 connector->base.encoder = NULL;
15847 }
15848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15849 connector->base.base.id,
15850 connector->base.name,
15851 connector->base.encoder ? "enabled" : "disabled");
15852 }
15853
15854 for_each_intel_crtc(dev, crtc) {
15855 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15856
15857 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15858 if (crtc->base.state->active) {
15859 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15860 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15861 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15862
15863 /*
15864 * The initial mode needs to be set in order to keep
15865 * the atomic core happy. It wants a valid mode if the
15866 * crtc's enabled, so we do the above call.
15867 *
15868 * At this point some state updated by the connectors
15869 * in their ->detect() callback has not run yet, so
15870 * no recalculation can be done yet.
15871 *
15872 * Even if we could do a recalculation and modeset
15873 * right now it would cause a double modeset if
15874 * fbdev or userspace chooses a different initial mode.
15875 *
15876 * If that happens, someone indicated they wanted a
15877 * mode change, which means it's safe to do a full
15878 * recalculation.
15879 */
15880 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15881
15882 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15883 update_scanline_offset(crtc);
15884 }
15885
15886 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15887 }
15888 }
15889
15890 /* Scan out the current hw modeset state,
15891 * and sanitizes it to the current state
15892 */
15893 static void
15894 intel_modeset_setup_hw_state(struct drm_device *dev)
15895 {
15896 struct drm_i915_private *dev_priv = dev->dev_private;
15897 enum pipe pipe;
15898 struct intel_crtc *crtc;
15899 struct intel_encoder *encoder;
15900 int i;
15901
15902 intel_modeset_readout_hw_state(dev);
15903
15904 /* HW state is read out, now we need to sanitize this mess. */
15905 for_each_intel_encoder(dev, encoder) {
15906 intel_sanitize_encoder(encoder);
15907 }
15908
15909 for_each_pipe(dev_priv, pipe) {
15910 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15911 intel_sanitize_crtc(crtc);
15912 intel_dump_pipe_config(crtc, crtc->config,
15913 "[setup_hw_state]");
15914 }
15915
15916 intel_modeset_update_connector_atomic_state(dev);
15917
15918 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15919 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15920
15921 if (!pll->on || pll->active_mask)
15922 continue;
15923
15924 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15925
15926 pll->funcs.disable(dev_priv, pll);
15927 pll->on = false;
15928 }
15929
15930 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15931 vlv_wm_get_hw_state(dev);
15932 else if (IS_GEN9(dev))
15933 skl_wm_get_hw_state(dev);
15934 else if (HAS_PCH_SPLIT(dev))
15935 ilk_wm_get_hw_state(dev);
15936
15937 for_each_intel_crtc(dev, crtc) {
15938 unsigned long put_domains;
15939
15940 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15941 if (WARN_ON(put_domains))
15942 modeset_put_power_domains(dev_priv, put_domains);
15943 }
15944 intel_display_set_init_power(dev_priv, false);
15945
15946 intel_fbc_init_pipe_state(dev_priv);
15947 }
15948
15949 void intel_display_resume(struct drm_device *dev)
15950 {
15951 struct drm_i915_private *dev_priv = to_i915(dev);
15952 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15953 struct drm_modeset_acquire_ctx ctx;
15954 int ret;
15955 bool setup = false;
15956
15957 dev_priv->modeset_restore_state = NULL;
15958
15959 /*
15960 * This is a cludge because with real atomic modeset mode_config.mutex
15961 * won't be taken. Unfortunately some probed state like
15962 * audio_codec_enable is still protected by mode_config.mutex, so lock
15963 * it here for now.
15964 */
15965 mutex_lock(&dev->mode_config.mutex);
15966 drm_modeset_acquire_init(&ctx, 0);
15967
15968 retry:
15969 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15970
15971 if (ret == 0 && !setup) {
15972 setup = true;
15973
15974 intel_modeset_setup_hw_state(dev);
15975 i915_redisable_vga(dev);
15976 }
15977
15978 if (ret == 0 && state) {
15979 struct drm_crtc_state *crtc_state;
15980 struct drm_crtc *crtc;
15981 int i;
15982
15983 state->acquire_ctx = &ctx;
15984
15985 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15986 /*
15987 * Force recalculation even if we restore
15988 * current state. With fast modeset this may not result
15989 * in a modeset when the state is compatible.
15990 */
15991 crtc_state->mode_changed = true;
15992 }
15993
15994 ret = drm_atomic_commit(state);
15995 }
15996
15997 if (ret == -EDEADLK) {
15998 drm_modeset_backoff(&ctx);
15999 goto retry;
16000 }
16001
16002 drm_modeset_drop_locks(&ctx);
16003 drm_modeset_acquire_fini(&ctx);
16004 mutex_unlock(&dev->mode_config.mutex);
16005
16006 if (ret) {
16007 DRM_ERROR("Restoring old state failed with %i\n", ret);
16008 drm_atomic_state_free(state);
16009 }
16010 }
16011
16012 void intel_modeset_gem_init(struct drm_device *dev)
16013 {
16014 struct drm_i915_private *dev_priv = to_i915(dev);
16015 struct drm_crtc *c;
16016 struct drm_i915_gem_object *obj;
16017 int ret;
16018
16019 intel_init_gt_powersave(dev_priv);
16020
16021 intel_modeset_init_hw(dev);
16022
16023 intel_setup_overlay(dev_priv);
16024
16025 /*
16026 * Make sure any fbs we allocated at startup are properly
16027 * pinned & fenced. When we do the allocation it's too early
16028 * for this.
16029 */
16030 for_each_crtc(dev, c) {
16031 obj = intel_fb_obj(c->primary->fb);
16032 if (obj == NULL)
16033 continue;
16034
16035 mutex_lock(&dev->struct_mutex);
16036 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16037 c->primary->state->rotation);
16038 mutex_unlock(&dev->struct_mutex);
16039 if (ret) {
16040 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16041 to_intel_crtc(c)->pipe);
16042 drm_framebuffer_unreference(c->primary->fb);
16043 c->primary->fb = NULL;
16044 c->primary->crtc = c->primary->state->crtc = NULL;
16045 update_state_fb(c->primary);
16046 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16047 }
16048 }
16049
16050 intel_backlight_register(dev);
16051 }
16052
16053 void intel_connector_unregister(struct intel_connector *intel_connector)
16054 {
16055 struct drm_connector *connector = &intel_connector->base;
16056
16057 intel_panel_destroy_backlight(connector);
16058 drm_connector_unregister(connector);
16059 }
16060
16061 void intel_modeset_cleanup(struct drm_device *dev)
16062 {
16063 struct drm_i915_private *dev_priv = dev->dev_private;
16064 struct intel_connector *connector;
16065
16066 intel_disable_gt_powersave(dev_priv);
16067
16068 intel_backlight_unregister(dev);
16069
16070 /*
16071 * Interrupts and polling as the first thing to avoid creating havoc.
16072 * Too much stuff here (turning of connectors, ...) would
16073 * experience fancy races otherwise.
16074 */
16075 intel_irq_uninstall(dev_priv);
16076
16077 /*
16078 * Due to the hpd irq storm handling the hotplug work can re-arm the
16079 * poll handlers. Hence disable polling after hpd handling is shut down.
16080 */
16081 drm_kms_helper_poll_fini(dev);
16082
16083 intel_unregister_dsm_handler();
16084
16085 intel_fbc_global_disable(dev_priv);
16086
16087 /* flush any delayed tasks or pending work */
16088 flush_scheduled_work();
16089
16090 /* destroy the backlight and sysfs files before encoders/connectors */
16091 for_each_intel_connector(dev, connector)
16092 connector->unregister(connector);
16093
16094 drm_mode_config_cleanup(dev);
16095
16096 intel_cleanup_overlay(dev_priv);
16097
16098 intel_cleanup_gt_powersave(dev_priv);
16099
16100 intel_teardown_gmbus(dev);
16101 }
16102
16103 /*
16104 * Return which encoder is currently attached for connector.
16105 */
16106 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16107 {
16108 return &intel_attached_encoder(connector)->base;
16109 }
16110
16111 void intel_connector_attach_encoder(struct intel_connector *connector,
16112 struct intel_encoder *encoder)
16113 {
16114 connector->encoder = encoder;
16115 drm_mode_connector_attach_encoder(&connector->base,
16116 &encoder->base);
16117 }
16118
16119 /*
16120 * set vga decode state - true == enable VGA decode
16121 */
16122 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16123 {
16124 struct drm_i915_private *dev_priv = dev->dev_private;
16125 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16126 u16 gmch_ctrl;
16127
16128 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16129 DRM_ERROR("failed to read control word\n");
16130 return -EIO;
16131 }
16132
16133 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16134 return 0;
16135
16136 if (state)
16137 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16138 else
16139 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16140
16141 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16142 DRM_ERROR("failed to write control word\n");
16143 return -EIO;
16144 }
16145
16146 return 0;
16147 }
16148
16149 struct intel_display_error_state {
16150
16151 u32 power_well_driver;
16152
16153 int num_transcoders;
16154
16155 struct intel_cursor_error_state {
16156 u32 control;
16157 u32 position;
16158 u32 base;
16159 u32 size;
16160 } cursor[I915_MAX_PIPES];
16161
16162 struct intel_pipe_error_state {
16163 bool power_domain_on;
16164 u32 source;
16165 u32 stat;
16166 } pipe[I915_MAX_PIPES];
16167
16168 struct intel_plane_error_state {
16169 u32 control;
16170 u32 stride;
16171 u32 size;
16172 u32 pos;
16173 u32 addr;
16174 u32 surface;
16175 u32 tile_offset;
16176 } plane[I915_MAX_PIPES];
16177
16178 struct intel_transcoder_error_state {
16179 bool power_domain_on;
16180 enum transcoder cpu_transcoder;
16181
16182 u32 conf;
16183
16184 u32 htotal;
16185 u32 hblank;
16186 u32 hsync;
16187 u32 vtotal;
16188 u32 vblank;
16189 u32 vsync;
16190 } transcoder[4];
16191 };
16192
16193 struct intel_display_error_state *
16194 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16195 {
16196 struct intel_display_error_state *error;
16197 int transcoders[] = {
16198 TRANSCODER_A,
16199 TRANSCODER_B,
16200 TRANSCODER_C,
16201 TRANSCODER_EDP,
16202 };
16203 int i;
16204
16205 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16206 return NULL;
16207
16208 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16209 if (error == NULL)
16210 return NULL;
16211
16212 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16213 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16214
16215 for_each_pipe(dev_priv, i) {
16216 error->pipe[i].power_domain_on =
16217 __intel_display_power_is_enabled(dev_priv,
16218 POWER_DOMAIN_PIPE(i));
16219 if (!error->pipe[i].power_domain_on)
16220 continue;
16221
16222 error->cursor[i].control = I915_READ(CURCNTR(i));
16223 error->cursor[i].position = I915_READ(CURPOS(i));
16224 error->cursor[i].base = I915_READ(CURBASE(i));
16225
16226 error->plane[i].control = I915_READ(DSPCNTR(i));
16227 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16228 if (INTEL_GEN(dev_priv) <= 3) {
16229 error->plane[i].size = I915_READ(DSPSIZE(i));
16230 error->plane[i].pos = I915_READ(DSPPOS(i));
16231 }
16232 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16233 error->plane[i].addr = I915_READ(DSPADDR(i));
16234 if (INTEL_GEN(dev_priv) >= 4) {
16235 error->plane[i].surface = I915_READ(DSPSURF(i));
16236 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16237 }
16238
16239 error->pipe[i].source = I915_READ(PIPESRC(i));
16240
16241 if (HAS_GMCH_DISPLAY(dev_priv))
16242 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16243 }
16244
16245 /* Note: this does not include DSI transcoders. */
16246 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16247 if (HAS_DDI(dev_priv))
16248 error->num_transcoders++; /* Account for eDP. */
16249
16250 for (i = 0; i < error->num_transcoders; i++) {
16251 enum transcoder cpu_transcoder = transcoders[i];
16252
16253 error->transcoder[i].power_domain_on =
16254 __intel_display_power_is_enabled(dev_priv,
16255 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16256 if (!error->transcoder[i].power_domain_on)
16257 continue;
16258
16259 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16260
16261 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16262 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16263 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16264 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16265 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16266 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16267 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16268 }
16269
16270 return error;
16271 }
16272
16273 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16274
16275 void
16276 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16277 struct drm_device *dev,
16278 struct intel_display_error_state *error)
16279 {
16280 struct drm_i915_private *dev_priv = dev->dev_private;
16281 int i;
16282
16283 if (!error)
16284 return;
16285
16286 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16287 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16288 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16289 error->power_well_driver);
16290 for_each_pipe(dev_priv, i) {
16291 err_printf(m, "Pipe [%d]:\n", i);
16292 err_printf(m, " Power: %s\n",
16293 onoff(error->pipe[i].power_domain_on));
16294 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16295 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16296
16297 err_printf(m, "Plane [%d]:\n", i);
16298 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16299 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16300 if (INTEL_INFO(dev)->gen <= 3) {
16301 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16302 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16303 }
16304 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16305 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16306 if (INTEL_INFO(dev)->gen >= 4) {
16307 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16308 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16309 }
16310
16311 err_printf(m, "Cursor [%d]:\n", i);
16312 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16313 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16314 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16315 }
16316
16317 for (i = 0; i < error->num_transcoders; i++) {
16318 err_printf(m, "CPU transcoder: %s\n",
16319 transcoder_name(error->transcoder[i].cpu_transcoder));
16320 err_printf(m, " Power: %s\n",
16321 onoff(error->transcoder[i].power_domain_on));
16322 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16323 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16324 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16325 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16326 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16327 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16328 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16329 }
16330 }
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