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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_device *dev,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
629 INTELPllInvalid("vco out of range\n");
630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
634 INTELPllInvalid("dot out of range\n");
635
636 return true;
637 }
638
639 static int
640 i9xx_select_p2_div(const struct intel_limit *limit,
641 const struct intel_crtc_state *crtc_state,
642 int target)
643 {
644 struct drm_device *dev = crtc_state->base.crtc->dev;
645
646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
647 /*
648 * For LVDS just rely on its current settings for dual-channel.
649 * We haven't figured out how to reliably set up different
650 * single/dual channel state, if we even can.
651 */
652 if (intel_is_dual_link_lvds(dev))
653 return limit->p2.p2_fast;
654 else
655 return limit->p2.p2_slow;
656 } else {
657 if (target < limit->p2.dot_limit)
658 return limit->p2.p2_slow;
659 else
660 return limit->p2.p2_fast;
661 }
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 i9xx_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 if (clock.m2 >= clock.m1)
693 break;
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 i9xx_calc_dpll_params(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 /*
722 * Returns a set of divisors for the desired target clock with the given
723 * refclk, or FALSE. The returned values represent the clock equation:
724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725 *
726 * Target and reference clocks are specified in kHz.
727 *
728 * If match_clock is provided, then best_clock P divider must match the P
729 * divider from @match_clock used for LVDS downclocking.
730 */
731 static bool
732 pnv_find_best_dpll(const struct intel_limit *limit,
733 struct intel_crtc_state *crtc_state,
734 int target, int refclk, struct dpll *match_clock,
735 struct dpll *best_clock)
736 {
737 struct drm_device *dev = crtc_state->base.crtc->dev;
738 struct dpll clock;
739 int err = target;
740
741 memset(best_clock, 0, sizeof(*best_clock));
742
743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
744
745 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
746 clock.m1++) {
747 for (clock.m2 = limit->m2.min;
748 clock.m2 <= limit->m2.max; clock.m2++) {
749 for (clock.n = limit->n.min;
750 clock.n <= limit->n.max; clock.n++) {
751 for (clock.p1 = limit->p1.min;
752 clock.p1 <= limit->p1.max; clock.p1++) {
753 int this_err;
754
755 pnv_calc_dpll_params(refclk, &clock);
756 if (!intel_PLL_is_valid(dev, limit,
757 &clock))
758 continue;
759 if (match_clock &&
760 clock.p != match_clock->p)
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err) {
765 *best_clock = clock;
766 err = this_err;
767 }
768 }
769 }
770 }
771 }
772
773 return (err != target);
774 }
775
776 /*
777 * Returns a set of divisors for the desired target clock with the given
778 * refclk, or FALSE. The returned values represent the clock equation:
779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
780 *
781 * Target and reference clocks are specified in kHz.
782 *
783 * If match_clock is provided, then best_clock P divider must match the P
784 * divider from @match_clock used for LVDS downclocking.
785 */
786 static bool
787 g4x_find_best_dpll(const struct intel_limit *limit,
788 struct intel_crtc_state *crtc_state,
789 int target, int refclk, struct dpll *match_clock,
790 struct dpll *best_clock)
791 {
792 struct drm_device *dev = crtc_state->base.crtc->dev;
793 struct dpll clock;
794 int max_n;
795 bool found = false;
796 /* approximately equals target * 0.00585 */
797 int err_most = (target >> 8) + (target >> 9);
798
799 memset(best_clock, 0, sizeof(*best_clock));
800
801 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
802
803 max_n = limit->n.max;
804 /* based on hardware requirement, prefer smaller n to precision */
805 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
806 /* based on hardware requirement, prefere larger m1,m2 */
807 for (clock.m1 = limit->m1.max;
808 clock.m1 >= limit->m1.min; clock.m1--) {
809 for (clock.m2 = limit->m2.max;
810 clock.m2 >= limit->m2.min; clock.m2--) {
811 for (clock.p1 = limit->p1.max;
812 clock.p1 >= limit->p1.min; clock.p1--) {
813 int this_err;
814
815 i9xx_calc_dpll_params(refclk, &clock);
816 if (!intel_PLL_is_valid(dev, limit,
817 &clock))
818 continue;
819
820 this_err = abs(clock.dot - target);
821 if (this_err < err_most) {
822 *best_clock = clock;
823 err_most = this_err;
824 max_n = clock.n;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831 return found;
832 }
833
834 /*
835 * Check if the calculated PLL configuration is more optimal compared to the
836 * best configuration and error found so far. Return the calculated error.
837 */
838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
839 const struct dpll *calculated_clock,
840 const struct dpll *best_clock,
841 unsigned int best_error_ppm,
842 unsigned int *error_ppm)
843 {
844 /*
845 * For CHV ignore the error and consider only the P value.
846 * Prefer a bigger P value based on HW requirements.
847 */
848 if (IS_CHERRYVIEW(dev)) {
849 *error_ppm = 0;
850
851 return calculated_clock->p > best_clock->p;
852 }
853
854 if (WARN_ON_ONCE(!target_freq))
855 return false;
856
857 *error_ppm = div_u64(1000000ULL *
858 abs(target_freq - calculated_clock->dot),
859 target_freq);
860 /*
861 * Prefer a better P value over a better (smaller) error if the error
862 * is small. Ensure this preference for future configurations too by
863 * setting the error to 0.
864 */
865 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
866 *error_ppm = 0;
867
868 return true;
869 }
870
871 return *error_ppm + 10 < best_error_ppm;
872 }
873
874 /*
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878 */
879 static bool
880 vlv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
884 {
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
887 struct dpll clock;
888 unsigned int bestppm = 1000000;
889 /* min update 19.2 MHz */
890 int max_n = min(limit->n.max, refclk / 19200);
891 bool found = false;
892
893 target *= 5; /* fast clock */
894
895 memset(best_clock, 0, sizeof(*best_clock));
896
897 /* based on hardware requirement, prefer smaller n to precision */
898 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
899 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
900 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
901 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
902 clock.p = clock.p1 * clock.p2;
903 /* based on hardware requirement, prefer bigger m1,m2 values */
904 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
905 unsigned int ppm;
906
907 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
908 refclk * clock.m1);
909
910 vlv_calc_dpll_params(refclk, &clock);
911
912 if (!intel_PLL_is_valid(dev, limit,
913 &clock))
914 continue;
915
916 if (!vlv_PLL_is_optimal(dev, target,
917 &clock,
918 best_clock,
919 bestppm, &ppm))
920 continue;
921
922 *best_clock = clock;
923 bestppm = ppm;
924 found = true;
925 }
926 }
927 }
928 }
929
930 return found;
931 }
932
933 /*
934 * Returns a set of divisors for the desired target clock with the given
935 * refclk, or FALSE. The returned values represent the clock equation:
936 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
937 */
938 static bool
939 chv_find_best_dpll(const struct intel_limit *limit,
940 struct intel_crtc_state *crtc_state,
941 int target, int refclk, struct dpll *match_clock,
942 struct dpll *best_clock)
943 {
944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
945 struct drm_device *dev = crtc->base.dev;
946 unsigned int best_error_ppm;
947 struct dpll clock;
948 uint64_t m2;
949 int found = false;
950
951 memset(best_clock, 0, sizeof(*best_clock));
952 best_error_ppm = 1000000;
953
954 /*
955 * Based on hardware doc, the n always set to 1, and m1 always
956 * set to 2. If requires to support 200Mhz refclk, we need to
957 * revisit this because n may not 1 anymore.
958 */
959 clock.n = 1, clock.m1 = 2;
960 target *= 5; /* fast clock */
961
962 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963 for (clock.p2 = limit->p2.p2_fast;
964 clock.p2 >= limit->p2.p2_slow;
965 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
966 unsigned int error_ppm;
967
968 clock.p = clock.p1 * clock.p2;
969
970 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971 clock.n) << 22, refclk * clock.m1);
972
973 if (m2 > INT_MAX/clock.m1)
974 continue;
975
976 clock.m2 = m2;
977
978 chv_calc_dpll_params(refclk, &clock);
979
980 if (!intel_PLL_is_valid(dev, limit, &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984 best_error_ppm, &error_ppm))
985 continue;
986
987 *best_clock = clock;
988 best_error_ppm = error_ppm;
989 found = true;
990 }
991 }
992
993 return found;
994 }
995
996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
997 struct dpll *best_clock)
998 {
999 int refclk = 100000;
1000 const struct intel_limit *limit = &intel_limits_bxt;
1001
1002 return chv_find_best_dpll(limit, crtc_state,
1003 target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010 /* Be paranoid as we can arrive here with only partial
1011 * state retrieved from the hardware during setup.
1012 *
1013 * We can ditch the adjusted_mode.crtc_clock check as soon
1014 * as Haswell has gained clock readout/fastboot support.
1015 *
1016 * We can ditch the crtc->primary->fb check as soon as we can
1017 * properly reconstruct framebuffers.
1018 *
1019 * FIXME: The intel_crtc->active here should be switched to
1020 * crtc->state->active once we have proper CRTC states wired up
1021 * for atomic.
1022 */
1023 return intel_crtc->active && crtc->primary->state->fb &&
1024 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029 {
1030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033 return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038 struct drm_i915_private *dev_priv = to_i915(dev);
1039 i915_reg_t reg = PIPEDSL(pipe);
1040 u32 line1, line2;
1041 u32 line_mask;
1042
1043 if (IS_GEN2(dev))
1044 line_mask = DSL_LINEMASK_GEN2;
1045 else
1046 line_mask = DSL_LINEMASK_GEN3;
1047
1048 line1 = I915_READ(reg) & line_mask;
1049 msleep(5);
1050 line2 = I915_READ(reg) & line_mask;
1051
1052 return line1 == line2;
1053 }
1054
1055 /*
1056 * intel_wait_for_pipe_off - wait for pipe to turn off
1057 * @crtc: crtc whose pipe to wait for
1058 *
1059 * After disabling a pipe, we can't wait for vblank in the usual way,
1060 * spinning on the vblank interrupt status bit, since we won't actually
1061 * see an interrupt when the pipe is disabled.
1062 *
1063 * On Gen4 and above:
1064 * wait for the pipe register state bit to turn off
1065 *
1066 * Otherwise:
1067 * wait for the display line value to settle (it usually
1068 * ends up stopping at the start of the next frame).
1069 *
1070 */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073 struct drm_device *dev = crtc->base.dev;
1074 struct drm_i915_private *dev_priv = to_i915(dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1077
1078 if (INTEL_INFO(dev)->gen >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
1085 WARN(1, "pipe_off wait timed out\n");
1086 } else {
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1090 }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 u32 val;
1098 bool cur_state;
1099
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110 u32 val;
1111 bool cur_state;
1112
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1116
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 } else {
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1171 return;
1172
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 u32 val;
1181 bool cur_state;
1182
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191 enum pipe pipe)
1192 {
1193 struct drm_device *dev = &dev_priv->drm;
1194 i915_reg_t pp_reg;
1195 u32 val;
1196 enum pipe panel_pipe = PIPE_A;
1197 bool locked = true;
1198
1199 if (WARN_ON(HAS_DDI(dev)))
1200 return;
1201
1202 if (HAS_PCH_SPLIT(dev)) {
1203 u32 port_sel;
1204
1205 pp_reg = PP_CONTROL(0);
1206 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211 /* XXX: else fix for eDP */
1212 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213 /* presumably write lock depends on pipe, not port select */
1214 pp_reg = PP_CONTROL(pipe);
1215 panel_pipe = pipe;
1216 } else {
1217 pp_reg = PP_CONTROL(0);
1218 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219 panel_pipe = PIPE_B;
1220 }
1221
1222 val = I915_READ(pp_reg);
1223 if (!(val & PANEL_POWER_ON) ||
1224 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225 locked = false;
1226
1227 I915_STATE_WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1229 pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1234 {
1235 struct drm_device *dev = &dev_priv->drm;
1236 bool cur_state;
1237
1238 if (IS_845G(dev) || IS_I865G(dev))
1239 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240 else
1241 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243 I915_STATE_WARN(cur_state != state,
1244 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe, bool state)
1252 {
1253 bool cur_state;
1254 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255 pipe);
1256 enum intel_display_power_domain power_domain;
1257
1258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261 state = true;
1262
1263 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268 intel_display_power_put(dev_priv, power_domain);
1269 } else {
1270 cur_state = false;
1271 }
1272
1273 I915_STATE_WARN(cur_state != state,
1274 "pipe %c assertion failure (expected %s, current %s)\n",
1275 pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279 enum plane plane, bool state)
1280 {
1281 u32 val;
1282 bool cur_state;
1283
1284 val = I915_READ(DSPCNTR(plane));
1285 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286 I915_STATE_WARN(cur_state != state,
1287 "plane %c assertion failure (expected %s, current %s)\n",
1288 plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 struct drm_device *dev = &dev_priv->drm;
1298 int i;
1299
1300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
1302 u32 val = I915_READ(DSPCNTR(pipe));
1303 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304 "plane %c assertion failure, should be disabled but not\n",
1305 plane_name(pipe));
1306 return;
1307 }
1308
1309 /* Need to check both planes against the pipe */
1310 for_each_pipe(dev_priv, i) {
1311 u32 val = I915_READ(DSPCNTR(i));
1312 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313 DISPPLANE_SEL_PIPE_SHIFT;
1314 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316 plane_name(i), pipe_name(pipe));
1317 }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe)
1322 {
1323 struct drm_device *dev = &dev_priv->drm;
1324 int sprite;
1325
1326 if (INTEL_INFO(dev)->gen >= 9) {
1327 for_each_sprite(dev_priv, pipe, sprite) {
1328 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331 sprite, pipe_name(pipe));
1332 }
1333 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334 for_each_sprite(dev_priv, pipe, sprite) {
1335 u32 val = I915_READ(SPCNTR(pipe, sprite));
1336 I915_STATE_WARN(val & SP_ENABLE,
1337 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338 sprite_name(pipe, sprite), pipe_name(pipe));
1339 }
1340 } else if (INTEL_INFO(dev)->gen >= 7) {
1341 u32 val = I915_READ(SPRCTL(pipe));
1342 I915_STATE_WARN(val & SPRITE_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 } else if (INTEL_INFO(dev)->gen >= 5) {
1346 u32 val = I915_READ(DVSCNTR(pipe));
1347 I915_STATE_WARN(val & DVS_ENABLE,
1348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
1350 }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 u32 val;
1363 bool enabled;
1364
1365 val = I915_READ(PCH_TRANSCONF(pipe));
1366 enabled = !!(val & TRANS_ENABLE);
1367 I915_STATE_WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375 if ((val & DP_PORT_EN) == 0)
1376 return false;
1377
1378 if (HAS_PCH_CPT(dev_priv)) {
1379 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381 return false;
1382 } else if (IS_CHERRYVIEW(dev_priv)) {
1383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384 return false;
1385 } else {
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & SDVO_ENABLE) == 0)
1396 return false;
1397
1398 if (HAS_PCH_CPT(dev_priv)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400 return false;
1401 } else if (IS_CHERRYVIEW(dev_priv)) {
1402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403 return false;
1404 } else {
1405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1413 {
1414 if ((val & LVDS_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419 return false;
1420 } else {
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 return false;
1423 }
1424 return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1429 {
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1431 return false;
1432 if (HAS_PCH_CPT(dev_priv)) {
1433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434 return false;
1435 } else {
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 return false;
1438 }
1439 return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, i915_reg_t reg,
1444 u32 port_sel)
1445 {
1446 u32 val = I915_READ(reg);
1447 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, i915_reg_t reg)
1458 {
1459 u32 val = I915_READ(reg);
1460 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471 {
1472 u32 val;
1473
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478 val = I915_READ(PCH_ADPA);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 val = I915_READ(PCH_LVDS);
1484 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *pipe_config)
1495 {
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1498
1499 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500 POSTING_READ(DPLL(pipe));
1501 udelay(150);
1502
1503 if (intel_wait_for_register(dev_priv,
1504 DPLL(pipe),
1505 DPLL_LOCK_VLV,
1506 DPLL_LOCK_VLV,
1507 1))
1508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *pipe_config)
1513 {
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 enum pipe pipe = crtc->pipe;
1516
1517 assert_pipe_disabled(dev_priv, pipe);
1518
1519 /* PLL is protected by panel, make sure we can write it */
1520 assert_panel_unlocked(dev_priv, pipe);
1521
1522 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523 _vlv_enable_pll(crtc, pipe_config);
1524
1525 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526 POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
1532 {
1533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534 enum pipe pipe = crtc->pipe;
1535 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536 u32 tmp;
1537
1538 mutex_lock(&dev_priv->sb_lock);
1539
1540 /* Enable back the 10bit clock to display controller */
1541 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542 tmp |= DPIO_DCLKP_EN;
1543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545 mutex_unlock(&dev_priv->sb_lock);
1546
1547 /*
1548 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549 */
1550 udelay(1);
1551
1552 /* Enable PLL */
1553 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555 /* Check PLL is locked */
1556 if (intel_wait_for_register(dev_priv,
1557 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558 1))
1559 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563 const struct intel_crtc_state *pipe_config)
1564 {
1565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566 enum pipe pipe = crtc->pipe;
1567
1568 assert_pipe_disabled(dev_priv, pipe);
1569
1570 /* PLL is protected by panel, make sure we can write it */
1571 assert_panel_unlocked(dev_priv, pipe);
1572
1573 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574 _chv_enable_pll(crtc, pipe_config);
1575
1576 if (pipe != PIPE_A) {
1577 /*
1578 * WaPixelRepeatModeFixForC0:chv
1579 *
1580 * DPLLCMD is AWOL. Use chicken bits to propagate
1581 * the value from DPLLBMD to either pipe B or C.
1582 */
1583 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585 I915_WRITE(CBR4_VLV, 0);
1586 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588 /*
1589 * DPLLB VGA mode also seems to cause problems.
1590 * We should always have it disabled.
1591 */
1592 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593 } else {
1594 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595 POSTING_READ(DPLL_MD(pipe));
1596 }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601 struct intel_crtc *crtc;
1602 int count = 0;
1603
1604 for_each_intel_crtc(dev, crtc) {
1605 count += crtc->base.state->active &&
1606 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607 }
1608
1609 return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = to_i915(dev);
1616 i915_reg_t reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 /* Enable DVO 2x clock on both PLLs if necessary */
1626 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627 /*
1628 * It appears to be important that we don't enable this
1629 * for the current pipe before otherwise configuring the
1630 * PLL. No idea how this should be handled if multiple
1631 * DVO outputs are enabled simultaneosly.
1632 */
1633 dpll |= DPLL_DVO_2X_MODE;
1634 I915_WRITE(DPLL(!crtc->pipe),
1635 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636 }
1637
1638 /*
1639 * Apparently we need to have VGA mode enabled prior to changing
1640 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641 * dividers, even though the register value does change.
1642 */
1643 I915_WRITE(reg, 0);
1644
1645 I915_WRITE(reg, dpll);
1646
1647 /* Wait for the clocks to stabilize. */
1648 POSTING_READ(reg);
1649 udelay(150);
1650
1651 if (INTEL_INFO(dev)->gen >= 4) {
1652 I915_WRITE(DPLL_MD(crtc->pipe),
1653 crtc->config->dpll_hw_state.dpll_md);
1654 } else {
1655 /* The pixel multiplier can only be updated once the
1656 * DPLL is enabled and the clocks are stable.
1657 *
1658 * So write it again.
1659 */
1660 I915_WRITE(reg, dpll);
1661 }
1662
1663 /* We do this three times for luck */
1664 I915_WRITE(reg, dpll);
1665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
1667 I915_WRITE(reg, dpll);
1668 POSTING_READ(reg);
1669 udelay(150); /* wait for warmup */
1670 I915_WRITE(reg, dpll);
1671 POSTING_READ(reg);
1672 udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676 * i9xx_disable_pll - disable a PLL
1677 * @dev_priv: i915 private structure
1678 * @pipe: pipe PLL to disable
1679 *
1680 * Disable the PLL for @pipe, making sure the pipe is off first.
1681 *
1682 * Note! This is for pre-ILK only.
1683 */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686 struct drm_device *dev = crtc->base.dev;
1687 struct drm_i915_private *dev_priv = to_i915(dev);
1688 enum pipe pipe = crtc->pipe;
1689
1690 /* Disable DVO 2x clock on both PLLs if necessary */
1691 if (IS_I830(dev) &&
1692 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693 !intel_num_dvo_pipes(dev)) {
1694 I915_WRITE(DPLL(PIPE_B),
1695 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696 I915_WRITE(DPLL(PIPE_A),
1697 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698 }
1699
1700 /* Don't disable pipe or pipe PLLs if needed */
1701 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703 return;
1704
1705 /* Make sure the pipe isn't still relying on us */
1706 assert_pipe_disabled(dev_priv, pipe);
1707
1708 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709 POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 u32 val;
1715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
1719 val = DPLL_INTEGRATED_REF_CLK_VLV |
1720 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731 u32 val;
1732
1733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
1735
1736 val = DPLL_SSC_REF_CLK_CHV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738 if (pipe != PIPE_A)
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
1743
1744 mutex_lock(&dev_priv->sb_lock);
1745
1746 /* Disable 10bit clock to display controller */
1747 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748 val &= ~DPIO_DCLKP_EN;
1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751 mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755 struct intel_digital_port *dport,
1756 unsigned int expected_mask)
1757 {
1758 u32 port_mask;
1759 i915_reg_t dpll_reg;
1760
1761 switch (dport->port) {
1762 case PORT_B:
1763 port_mask = DPLL_PORTB_READY_MASK;
1764 dpll_reg = DPLL(0);
1765 break;
1766 case PORT_C:
1767 port_mask = DPLL_PORTC_READY_MASK;
1768 dpll_reg = DPLL(0);
1769 expected_mask <<= 4;
1770 break;
1771 case PORT_D:
1772 port_mask = DPLL_PORTD_READY_MASK;
1773 dpll_reg = DPIO_PHY_STATUS;
1774 break;
1775 default:
1776 BUG();
1777 }
1778
1779 if (intel_wait_for_register(dev_priv,
1780 dpll_reg, port_mask, expected_mask,
1781 1000))
1782 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787 enum pipe pipe)
1788 {
1789 struct drm_device *dev = &dev_priv->drm;
1790 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792 i915_reg_t reg;
1793 uint32_t val, pipeconf_val;
1794
1795 /* Make sure PCH DPLL is enabled */
1796 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798 /* FDI must be feeding us bits for PCH ports */
1799 assert_fdi_tx_enabled(dev_priv, pipe);
1800 assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802 if (HAS_PCH_CPT(dev)) {
1803 /* Workaround: Set the timing override bit before enabling the
1804 * pch transcoder. */
1805 reg = TRANS_CHICKEN2(pipe);
1806 val = I915_READ(reg);
1807 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808 I915_WRITE(reg, val);
1809 }
1810
1811 reg = PCH_TRANSCONF(pipe);
1812 val = I915_READ(reg);
1813 pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815 if (HAS_PCH_IBX(dev_priv)) {
1816 /*
1817 * Make the BPC in transcoder be consistent with
1818 * that in pipeconf reg. For HDMI we must use 8bpc
1819 * here for both 8bpc and 12bpc.
1820 */
1821 val &= ~PIPECONF_BPC_MASK;
1822 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823 val |= PIPECONF_8BPC;
1824 else
1825 val |= pipeconf_val & PIPECONF_BPC_MASK;
1826 }
1827
1828 val &= ~TRANS_INTERLACE_MASK;
1829 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830 if (HAS_PCH_IBX(dev_priv) &&
1831 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832 val |= TRANS_LEGACY_INTERLACED_ILK;
1833 else
1834 val |= TRANS_INTERLACED;
1835 else
1836 val |= TRANS_PROGRESSIVE;
1837
1838 I915_WRITE(reg, val | TRANS_ENABLE);
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841 100))
1842 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846 enum transcoder cpu_transcoder)
1847 {
1848 u32 val, pipeconf_val;
1849
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854 /* Workaround: set timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859 val = TRANS_ENABLE;
1860 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863 PIPECONF_INTERLACED_ILK)
1864 val |= TRANS_INTERLACED;
1865 else
1866 val |= TRANS_PROGRESSIVE;
1867
1868 I915_WRITE(LPT_TRANSCONF, val);
1869 if (intel_wait_for_register(dev_priv,
1870 LPT_TRANSCONF,
1871 TRANS_STATE_ENABLE,
1872 TRANS_STATE_ENABLE,
1873 100))
1874 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum pipe pipe)
1879 {
1880 struct drm_device *dev = &dev_priv->drm;
1881 i915_reg_t reg;
1882 uint32_t val;
1883
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1890
1891 reg = PCH_TRANSCONF(pipe);
1892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
1896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1898 50))
1899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901 if (HAS_PCH_CPT(dev)) {
1902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1907 }
1908 }
1909
1910 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912 u32 val;
1913
1914 val = I915_READ(LPT_TRANSCONF);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(LPT_TRANSCONF, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920 50))
1921 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923 /* Workaround: clear timing override bit. */
1924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930 * intel_enable_pipe - enable a pipe, asserting requirements
1931 * @crtc: crtc responsible for the pipe
1932 *
1933 * Enable @crtc's pipe, making sure that various hardware specific requirements
1934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935 */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938 struct drm_device *dev = crtc->base.dev;
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 enum pipe pipe = crtc->pipe;
1941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942 enum pipe pch_transcoder;
1943 i915_reg_t reg;
1944 u32 val;
1945
1946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948 assert_planes_disabled(dev_priv, pipe);
1949 assert_cursor_disabled(dev_priv, pipe);
1950 assert_sprites_disabled(dev_priv, pipe);
1951
1952 if (HAS_PCH_LPT(dev_priv))
1953 pch_transcoder = TRANSCODER_A;
1954 else
1955 pch_transcoder = pipe;
1956
1957 /*
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1960 * need the check.
1961 */
1962 if (HAS_GMCH_DISPLAY(dev_priv)) {
1963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964 assert_dsi_pll_enabled(dev_priv);
1965 else
1966 assert_pll_enabled(dev_priv, pipe);
1967 } else {
1968 if (crtc->config->has_pch_encoder) {
1969 /* if driving the PCH, we need FDI enabled */
1970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
1973 }
1974 /* FIXME: assert CPU port conditions for SNB+ */
1975 }
1976
1977 reg = PIPECONF(cpu_transcoder);
1978 val = I915_READ(reg);
1979 if (val & PIPECONF_ENABLE) {
1980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982 return;
1983 }
1984
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
1986 POSTING_READ(reg);
1987
1988 /*
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1994 */
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001 * intel_disable_pipe - disable a pipe, asserting requirements
2002 * @crtc: crtc whose pipes is to be disabled
2003 *
2004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
2007 *
2008 * Will wait until the pipe has shut down before returning.
2009 */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014 enum pipe pipe = crtc->pipe;
2015 i915_reg_t reg;
2016 u32 val;
2017
2018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020 /*
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2023 */
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if ((val & PIPECONF_ENABLE) == 0)
2031 return;
2032
2033 /*
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2036 */
2037 if (crtc->config->double_wide)
2038 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040 /* Don't disable pipe or pipe PLLs if needed */
2041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043 val &= ~PIPECONF_ENABLE;
2044
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
2057 {
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2060 return cpp;
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2063 return 128;
2064 else
2065 return 512;
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068 return 128;
2069 else
2070 return 512;
2071 case I915_FORMAT_MOD_Yf_TILED:
2072 switch (cpp) {
2073 case 1:
2074 return 64;
2075 case 2:
2076 case 4:
2077 return 128;
2078 case 8:
2079 case 16:
2080 return 256;
2081 default:
2082 MISSING_CASE(cpp);
2083 return cpp;
2084 }
2085 break;
2086 default:
2087 MISSING_CASE(fb_modifier);
2088 return cpp;
2089 }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
2094 {
2095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096 return 1;
2097 else
2098 return intel_tile_size(dev_priv) /
2099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2107 unsigned int cpp)
2108 {
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118 uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123 return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128 unsigned int size = 0;
2129 int i;
2130
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134 return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
2141 {
2142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145 } else {
2146 *view = i915_ggtt_view_normal;
2147 }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152 if (INTEL_INFO(dev_priv)->gen >= 9)
2153 return 256 * 1024;
2154 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156 return 128 * 1024;
2157 else if (INTEL_INFO(dev_priv)->gen >= 4)
2158 return 4 * 1024;
2159 else
2160 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164 uint64_t fb_modifier)
2165 {
2166 switch (fb_modifier) {
2167 case DRM_FORMAT_MOD_NONE:
2168 return intel_linear_alignment(dev_priv);
2169 case I915_FORMAT_MOD_X_TILED:
2170 if (INTEL_INFO(dev_priv)->gen >= 9)
2171 return 256 * 1024;
2172 return 0;
2173 case I915_FORMAT_MOD_Y_TILED:
2174 case I915_FORMAT_MOD_Yf_TILED:
2175 return 1 * 1024 * 1024;
2176 default:
2177 MISSING_CASE(fb_modifier);
2178 return 0;
2179 }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185 struct drm_device *dev = fb->dev;
2186 struct drm_i915_private *dev_priv = to_i915(dev);
2187 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188 struct i915_ggtt_view view;
2189 struct i915_vma *vma;
2190 u32 alignment;
2191 int ret;
2192
2193 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2194
2195 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2196
2197 intel_fill_fb_ggtt_view(&view, fb, rotation);
2198
2199 /* Note that the w/a also requires 64 PTE of padding following the
2200 * bo. We currently fill all unused PTE with the shadow page and so
2201 * we should always have valid PTE following the scanout preventing
2202 * the VT-d warning.
2203 */
2204 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2205 alignment = 256 * 1024;
2206
2207 /*
2208 * Global gtt pte registers are special registers which actually forward
2209 * writes to a chunk of system memory. Which means that there is no risk
2210 * that the register values disappear as soon as we call
2211 * intel_runtime_pm_put(), so it is correct to wrap only the
2212 * pin/unpin/fence and not more.
2213 */
2214 intel_runtime_pm_get(dev_priv);
2215
2216 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2217 if (IS_ERR(vma)) {
2218 ret = PTR_ERR(vma);
2219 goto err_pm;
2220 }
2221
2222 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2223 * fence, whereas 965+ only requires a fence if using
2224 * framebuffer compression. For simplicity, we always install
2225 * a fence as the cost is not that onerous.
2226 */
2227 if (view.type == I915_GGTT_VIEW_NORMAL) {
2228 ret = i915_gem_object_get_fence(obj);
2229 if (ret == -EDEADLK) {
2230 /*
2231 * -EDEADLK means there are no free fences
2232 * no pending flips.
2233 *
2234 * This is propagated to atomic, but it uses
2235 * -EDEADLK to force a locking recovery, so
2236 * change the returned error to -EBUSY.
2237 */
2238 ret = -EBUSY;
2239 goto err_unpin;
2240 } else if (ret)
2241 goto err_unpin;
2242
2243 i915_gem_object_pin_fence(obj);
2244 }
2245
2246 intel_runtime_pm_put(dev_priv);
2247 return vma;
2248
2249 err_unpin:
2250 i915_gem_object_unpin_from_display_plane(vma);
2251 err_pm:
2252 intel_runtime_pm_put(dev_priv);
2253 return ERR_PTR(ret);
2254 }
2255
2256 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2257 {
2258 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2259 struct i915_ggtt_view view;
2260 struct i915_vma *vma;
2261
2262 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2263
2264 intel_fill_fb_ggtt_view(&view, fb, rotation);
2265
2266 if (view.type == I915_GGTT_VIEW_NORMAL)
2267 i915_gem_object_unpin_fence(obj);
2268
2269 vma = i915_gem_object_to_ggtt(obj, &view);
2270 i915_gem_object_unpin_from_display_plane(vma);
2271 }
2272
2273 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2274 unsigned int rotation)
2275 {
2276 if (intel_rotation_90_or_270(rotation))
2277 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2278 else
2279 return fb->pitches[plane];
2280 }
2281
2282 /*
2283 * Convert the x/y offsets into a linear offset.
2284 * Only valid with 0/180 degree rotation, which is fine since linear
2285 * offset is only used with linear buffers on pre-hsw and tiled buffers
2286 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2287 */
2288 u32 intel_fb_xy_to_linear(int x, int y,
2289 const struct intel_plane_state *state,
2290 int plane)
2291 {
2292 const struct drm_framebuffer *fb = state->base.fb;
2293 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2294 unsigned int pitch = fb->pitches[plane];
2295
2296 return y * pitch + x * cpp;
2297 }
2298
2299 /*
2300 * Add the x/y offsets derived from fb->offsets[] to the user
2301 * specified plane src x/y offsets. The resulting x/y offsets
2302 * specify the start of scanout from the beginning of the gtt mapping.
2303 */
2304 void intel_add_fb_offsets(int *x, int *y,
2305 const struct intel_plane_state *state,
2306 int plane)
2307
2308 {
2309 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2310 unsigned int rotation = state->base.rotation;
2311
2312 if (intel_rotation_90_or_270(rotation)) {
2313 *x += intel_fb->rotated[plane].x;
2314 *y += intel_fb->rotated[plane].y;
2315 } else {
2316 *x += intel_fb->normal[plane].x;
2317 *y += intel_fb->normal[plane].y;
2318 }
2319 }
2320
2321 /*
2322 * Input tile dimensions and pitch must already be
2323 * rotated to match x and y, and in pixel units.
2324 */
2325 static u32 _intel_adjust_tile_offset(int *x, int *y,
2326 unsigned int tile_width,
2327 unsigned int tile_height,
2328 unsigned int tile_size,
2329 unsigned int pitch_tiles,
2330 u32 old_offset,
2331 u32 new_offset)
2332 {
2333 unsigned int pitch_pixels = pitch_tiles * tile_width;
2334 unsigned int tiles;
2335
2336 WARN_ON(old_offset & (tile_size - 1));
2337 WARN_ON(new_offset & (tile_size - 1));
2338 WARN_ON(new_offset > old_offset);
2339
2340 tiles = (old_offset - new_offset) / tile_size;
2341
2342 *y += tiles / pitch_tiles * tile_height;
2343 *x += tiles % pitch_tiles * tile_width;
2344
2345 /* minimize x in case it got needlessly big */
2346 *y += *x / pitch_pixels * tile_height;
2347 *x %= pitch_pixels;
2348
2349 return new_offset;
2350 }
2351
2352 /*
2353 * Adjust the tile offset by moving the difference into
2354 * the x/y offsets.
2355 */
2356 static u32 intel_adjust_tile_offset(int *x, int *y,
2357 const struct intel_plane_state *state, int plane,
2358 u32 old_offset, u32 new_offset)
2359 {
2360 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2361 const struct drm_framebuffer *fb = state->base.fb;
2362 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2363 unsigned int rotation = state->base.rotation;
2364 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2365
2366 WARN_ON(new_offset > old_offset);
2367
2368 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2369 unsigned int tile_size, tile_width, tile_height;
2370 unsigned int pitch_tiles;
2371
2372 tile_size = intel_tile_size(dev_priv);
2373 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2374 fb->modifier[plane], cpp);
2375
2376 if (intel_rotation_90_or_270(rotation)) {
2377 pitch_tiles = pitch / tile_height;
2378 swap(tile_width, tile_height);
2379 } else {
2380 pitch_tiles = pitch / (tile_width * cpp);
2381 }
2382
2383 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2384 tile_size, pitch_tiles,
2385 old_offset, new_offset);
2386 } else {
2387 old_offset += *y * pitch + *x * cpp;
2388
2389 *y = (old_offset - new_offset) / pitch;
2390 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2391 }
2392
2393 return new_offset;
2394 }
2395
2396 /*
2397 * Computes the linear offset to the base tile and adjusts
2398 * x, y. bytes per pixel is assumed to be a power-of-two.
2399 *
2400 * In the 90/270 rotated case, x and y are assumed
2401 * to be already rotated to match the rotated GTT view, and
2402 * pitch is the tile_height aligned framebuffer height.
2403 *
2404 * This function is used when computing the derived information
2405 * under intel_framebuffer, so using any of that information
2406 * here is not allowed. Anything under drm_framebuffer can be
2407 * used. This is why the user has to pass in the pitch since it
2408 * is specified in the rotated orientation.
2409 */
2410 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2411 int *x, int *y,
2412 const struct drm_framebuffer *fb, int plane,
2413 unsigned int pitch,
2414 unsigned int rotation,
2415 u32 alignment)
2416 {
2417 uint64_t fb_modifier = fb->modifier[plane];
2418 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2419 u32 offset, offset_aligned;
2420
2421 if (alignment)
2422 alignment--;
2423
2424 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2425 unsigned int tile_size, tile_width, tile_height;
2426 unsigned int tile_rows, tiles, pitch_tiles;
2427
2428 tile_size = intel_tile_size(dev_priv);
2429 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2430 fb_modifier, cpp);
2431
2432 if (intel_rotation_90_or_270(rotation)) {
2433 pitch_tiles = pitch / tile_height;
2434 swap(tile_width, tile_height);
2435 } else {
2436 pitch_tiles = pitch / (tile_width * cpp);
2437 }
2438
2439 tile_rows = *y / tile_height;
2440 *y %= tile_height;
2441
2442 tiles = *x / tile_width;
2443 *x %= tile_width;
2444
2445 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2446 offset_aligned = offset & ~alignment;
2447
2448 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2449 tile_size, pitch_tiles,
2450 offset, offset_aligned);
2451 } else {
2452 offset = *y * pitch + *x * cpp;
2453 offset_aligned = offset & ~alignment;
2454
2455 *y = (offset & alignment) / pitch;
2456 *x = ((offset & alignment) - *y * pitch) / cpp;
2457 }
2458
2459 return offset_aligned;
2460 }
2461
2462 u32 intel_compute_tile_offset(int *x, int *y,
2463 const struct intel_plane_state *state,
2464 int plane)
2465 {
2466 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2467 const struct drm_framebuffer *fb = state->base.fb;
2468 unsigned int rotation = state->base.rotation;
2469 int pitch = intel_fb_pitch(fb, plane, rotation);
2470 u32 alignment;
2471
2472 /* AUX_DIST needs only 4K alignment */
2473 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2474 alignment = 4096;
2475 else
2476 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2477
2478 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2479 rotation, alignment);
2480 }
2481
2482 /* Convert the fb->offset[] linear offset into x/y offsets */
2483 static void intel_fb_offset_to_xy(int *x, int *y,
2484 const struct drm_framebuffer *fb, int plane)
2485 {
2486 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2487 unsigned int pitch = fb->pitches[plane];
2488 u32 linear_offset = fb->offsets[plane];
2489
2490 *y = linear_offset / pitch;
2491 *x = linear_offset % pitch / cpp;
2492 }
2493
2494 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2495 {
2496 switch (fb_modifier) {
2497 case I915_FORMAT_MOD_X_TILED:
2498 return I915_TILING_X;
2499 case I915_FORMAT_MOD_Y_TILED:
2500 return I915_TILING_Y;
2501 default:
2502 return I915_TILING_NONE;
2503 }
2504 }
2505
2506 static int
2507 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2508 struct drm_framebuffer *fb)
2509 {
2510 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2511 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2512 u32 gtt_offset_rotated = 0;
2513 unsigned int max_size = 0;
2514 uint32_t format = fb->pixel_format;
2515 int i, num_planes = drm_format_num_planes(format);
2516 unsigned int tile_size = intel_tile_size(dev_priv);
2517
2518 for (i = 0; i < num_planes; i++) {
2519 unsigned int width, height;
2520 unsigned int cpp, size;
2521 u32 offset;
2522 int x, y;
2523
2524 cpp = drm_format_plane_cpp(format, i);
2525 width = drm_format_plane_width(fb->width, format, i);
2526 height = drm_format_plane_height(fb->height, format, i);
2527
2528 intel_fb_offset_to_xy(&x, &y, fb, i);
2529
2530 /*
2531 * The fence (if used) is aligned to the start of the object
2532 * so having the framebuffer wrap around across the edge of the
2533 * fenced region doesn't really work. We have no API to configure
2534 * the fence start offset within the object (nor could we probably
2535 * on gen2/3). So it's just easier if we just require that the
2536 * fb layout agrees with the fence layout. We already check that the
2537 * fb stride matches the fence stride elsewhere.
2538 */
2539 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2540 (x + width) * cpp > fb->pitches[i]) {
2541 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2542 i, fb->offsets[i]);
2543 return -EINVAL;
2544 }
2545
2546 /*
2547 * First pixel of the framebuffer from
2548 * the start of the normal gtt mapping.
2549 */
2550 intel_fb->normal[i].x = x;
2551 intel_fb->normal[i].y = y;
2552
2553 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2554 fb, 0, fb->pitches[i],
2555 DRM_ROTATE_0, tile_size);
2556 offset /= tile_size;
2557
2558 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2559 unsigned int tile_width, tile_height;
2560 unsigned int pitch_tiles;
2561 struct drm_rect r;
2562
2563 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2564 fb->modifier[i], cpp);
2565
2566 rot_info->plane[i].offset = offset;
2567 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2568 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2569 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2570
2571 intel_fb->rotated[i].pitch =
2572 rot_info->plane[i].height * tile_height;
2573
2574 /* how many tiles does this plane need */
2575 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2576 /*
2577 * If the plane isn't horizontally tile aligned,
2578 * we need one more tile.
2579 */
2580 if (x != 0)
2581 size++;
2582
2583 /* rotate the x/y offsets to match the GTT view */
2584 r.x1 = x;
2585 r.y1 = y;
2586 r.x2 = x + width;
2587 r.y2 = y + height;
2588 drm_rect_rotate(&r,
2589 rot_info->plane[i].width * tile_width,
2590 rot_info->plane[i].height * tile_height,
2591 DRM_ROTATE_270);
2592 x = r.x1;
2593 y = r.y1;
2594
2595 /* rotate the tile dimensions to match the GTT view */
2596 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2597 swap(tile_width, tile_height);
2598
2599 /*
2600 * We only keep the x/y offsets, so push all of the
2601 * gtt offset into the x/y offsets.
2602 */
2603 _intel_adjust_tile_offset(&x, &y, tile_size,
2604 tile_width, tile_height, pitch_tiles,
2605 gtt_offset_rotated * tile_size, 0);
2606
2607 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2608
2609 /*
2610 * First pixel of the framebuffer from
2611 * the start of the rotated gtt mapping.
2612 */
2613 intel_fb->rotated[i].x = x;
2614 intel_fb->rotated[i].y = y;
2615 } else {
2616 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2617 x * cpp, tile_size);
2618 }
2619
2620 /* how many tiles in total needed in the bo */
2621 max_size = max(max_size, offset + size);
2622 }
2623
2624 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2625 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2626 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2627 return -EINVAL;
2628 }
2629
2630 return 0;
2631 }
2632
2633 static int i9xx_format_to_fourcc(int format)
2634 {
2635 switch (format) {
2636 case DISPPLANE_8BPP:
2637 return DRM_FORMAT_C8;
2638 case DISPPLANE_BGRX555:
2639 return DRM_FORMAT_XRGB1555;
2640 case DISPPLANE_BGRX565:
2641 return DRM_FORMAT_RGB565;
2642 default:
2643 case DISPPLANE_BGRX888:
2644 return DRM_FORMAT_XRGB8888;
2645 case DISPPLANE_RGBX888:
2646 return DRM_FORMAT_XBGR8888;
2647 case DISPPLANE_BGRX101010:
2648 return DRM_FORMAT_XRGB2101010;
2649 case DISPPLANE_RGBX101010:
2650 return DRM_FORMAT_XBGR2101010;
2651 }
2652 }
2653
2654 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2655 {
2656 switch (format) {
2657 case PLANE_CTL_FORMAT_RGB_565:
2658 return DRM_FORMAT_RGB565;
2659 default:
2660 case PLANE_CTL_FORMAT_XRGB_8888:
2661 if (rgb_order) {
2662 if (alpha)
2663 return DRM_FORMAT_ABGR8888;
2664 else
2665 return DRM_FORMAT_XBGR8888;
2666 } else {
2667 if (alpha)
2668 return DRM_FORMAT_ARGB8888;
2669 else
2670 return DRM_FORMAT_XRGB8888;
2671 }
2672 case PLANE_CTL_FORMAT_XRGB_2101010:
2673 if (rgb_order)
2674 return DRM_FORMAT_XBGR2101010;
2675 else
2676 return DRM_FORMAT_XRGB2101010;
2677 }
2678 }
2679
2680 static bool
2681 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2682 struct intel_initial_plane_config *plane_config)
2683 {
2684 struct drm_device *dev = crtc->base.dev;
2685 struct drm_i915_private *dev_priv = to_i915(dev);
2686 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2687 struct drm_i915_gem_object *obj = NULL;
2688 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2689 struct drm_framebuffer *fb = &plane_config->fb->base;
2690 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2691 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2692 PAGE_SIZE);
2693
2694 size_aligned -= base_aligned;
2695
2696 if (plane_config->size == 0)
2697 return false;
2698
2699 /* If the FB is too big, just don't use it since fbdev is not very
2700 * important and we should probably use that space with FBC or other
2701 * features. */
2702 if (size_aligned * 2 > ggtt->stolen_usable_size)
2703 return false;
2704
2705 mutex_lock(&dev->struct_mutex);
2706
2707 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2708 base_aligned,
2709 base_aligned,
2710 size_aligned);
2711 if (!obj) {
2712 mutex_unlock(&dev->struct_mutex);
2713 return false;
2714 }
2715
2716 if (plane_config->tiling == I915_TILING_X)
2717 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2718
2719 mode_cmd.pixel_format = fb->pixel_format;
2720 mode_cmd.width = fb->width;
2721 mode_cmd.height = fb->height;
2722 mode_cmd.pitches[0] = fb->pitches[0];
2723 mode_cmd.modifier[0] = fb->modifier[0];
2724 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2725
2726 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2727 &mode_cmd, obj)) {
2728 DRM_DEBUG_KMS("intel fb init failed\n");
2729 goto out_unref_obj;
2730 }
2731
2732 mutex_unlock(&dev->struct_mutex);
2733
2734 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2735 return true;
2736
2737 out_unref_obj:
2738 i915_gem_object_put(obj);
2739 mutex_unlock(&dev->struct_mutex);
2740 return false;
2741 }
2742
2743 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2744 static void
2745 update_state_fb(struct drm_plane *plane)
2746 {
2747 if (plane->fb == plane->state->fb)
2748 return;
2749
2750 if (plane->state->fb)
2751 drm_framebuffer_unreference(plane->state->fb);
2752 plane->state->fb = plane->fb;
2753 if (plane->state->fb)
2754 drm_framebuffer_reference(plane->state->fb);
2755 }
2756
2757 static void
2758 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2759 struct intel_initial_plane_config *plane_config)
2760 {
2761 struct drm_device *dev = intel_crtc->base.dev;
2762 struct drm_i915_private *dev_priv = to_i915(dev);
2763 struct drm_crtc *c;
2764 struct intel_crtc *i;
2765 struct drm_i915_gem_object *obj;
2766 struct drm_plane *primary = intel_crtc->base.primary;
2767 struct drm_plane_state *plane_state = primary->state;
2768 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2769 struct intel_plane *intel_plane = to_intel_plane(primary);
2770 struct intel_plane_state *intel_state =
2771 to_intel_plane_state(plane_state);
2772 struct drm_framebuffer *fb;
2773
2774 if (!plane_config->fb)
2775 return;
2776
2777 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2778 fb = &plane_config->fb->base;
2779 goto valid_fb;
2780 }
2781
2782 kfree(plane_config->fb);
2783
2784 /*
2785 * Failed to alloc the obj, check to see if we should share
2786 * an fb with another CRTC instead
2787 */
2788 for_each_crtc(dev, c) {
2789 i = to_intel_crtc(c);
2790
2791 if (c == &intel_crtc->base)
2792 continue;
2793
2794 if (!i->active)
2795 continue;
2796
2797 fb = c->primary->fb;
2798 if (!fb)
2799 continue;
2800
2801 obj = intel_fb_obj(fb);
2802 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2803 drm_framebuffer_reference(fb);
2804 goto valid_fb;
2805 }
2806 }
2807
2808 /*
2809 * We've failed to reconstruct the BIOS FB. Current display state
2810 * indicates that the primary plane is visible, but has a NULL FB,
2811 * which will lead to problems later if we don't fix it up. The
2812 * simplest solution is to just disable the primary plane now and
2813 * pretend the BIOS never had it enabled.
2814 */
2815 to_intel_plane_state(plane_state)->base.visible = false;
2816 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2817 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2818 intel_plane->disable_plane(primary, &intel_crtc->base);
2819
2820 return;
2821
2822 valid_fb:
2823 plane_state->src_x = 0;
2824 plane_state->src_y = 0;
2825 plane_state->src_w = fb->width << 16;
2826 plane_state->src_h = fb->height << 16;
2827
2828 plane_state->crtc_x = 0;
2829 plane_state->crtc_y = 0;
2830 plane_state->crtc_w = fb->width;
2831 plane_state->crtc_h = fb->height;
2832
2833 intel_state->base.src.x1 = plane_state->src_x;
2834 intel_state->base.src.y1 = plane_state->src_y;
2835 intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2836 intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2837 intel_state->base.dst.x1 = plane_state->crtc_x;
2838 intel_state->base.dst.y1 = plane_state->crtc_y;
2839 intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2840 intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2841
2842 obj = intel_fb_obj(fb);
2843 if (i915_gem_object_is_tiled(obj))
2844 dev_priv->preserve_bios_swizzle = true;
2845
2846 drm_framebuffer_reference(fb);
2847 primary->fb = primary->state->fb = fb;
2848 primary->crtc = primary->state->crtc = &intel_crtc->base;
2849 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2850 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2851 &obj->frontbuffer_bits);
2852 }
2853
2854 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2855 unsigned int rotation)
2856 {
2857 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2858
2859 switch (fb->modifier[plane]) {
2860 case DRM_FORMAT_MOD_NONE:
2861 case I915_FORMAT_MOD_X_TILED:
2862 switch (cpp) {
2863 case 8:
2864 return 4096;
2865 case 4:
2866 case 2:
2867 case 1:
2868 return 8192;
2869 default:
2870 MISSING_CASE(cpp);
2871 break;
2872 }
2873 break;
2874 case I915_FORMAT_MOD_Y_TILED:
2875 case I915_FORMAT_MOD_Yf_TILED:
2876 switch (cpp) {
2877 case 8:
2878 return 2048;
2879 case 4:
2880 return 4096;
2881 case 2:
2882 case 1:
2883 return 8192;
2884 default:
2885 MISSING_CASE(cpp);
2886 break;
2887 }
2888 break;
2889 default:
2890 MISSING_CASE(fb->modifier[plane]);
2891 }
2892
2893 return 2048;
2894 }
2895
2896 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2897 {
2898 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2899 const struct drm_framebuffer *fb = plane_state->base.fb;
2900 unsigned int rotation = plane_state->base.rotation;
2901 int x = plane_state->base.src.x1 >> 16;
2902 int y = plane_state->base.src.y1 >> 16;
2903 int w = drm_rect_width(&plane_state->base.src) >> 16;
2904 int h = drm_rect_height(&plane_state->base.src) >> 16;
2905 int max_width = skl_max_plane_width(fb, 0, rotation);
2906 int max_height = 4096;
2907 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2908
2909 if (w > max_width || h > max_height) {
2910 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2911 w, h, max_width, max_height);
2912 return -EINVAL;
2913 }
2914
2915 intel_add_fb_offsets(&x, &y, plane_state, 0);
2916 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2917
2918 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2919
2920 /*
2921 * AUX surface offset is specified as the distance from the
2922 * main surface offset, and it must be non-negative. Make
2923 * sure that is what we will get.
2924 */
2925 if (offset > aux_offset)
2926 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2927 offset, aux_offset & ~(alignment - 1));
2928
2929 /*
2930 * When using an X-tiled surface, the plane blows up
2931 * if the x offset + width exceed the stride.
2932 *
2933 * TODO: linear and Y-tiled seem fine, Yf untested,
2934 */
2935 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2936 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2937
2938 while ((x + w) * cpp > fb->pitches[0]) {
2939 if (offset == 0) {
2940 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2941 return -EINVAL;
2942 }
2943
2944 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2945 offset, offset - alignment);
2946 }
2947 }
2948
2949 plane_state->main.offset = offset;
2950 plane_state->main.x = x;
2951 plane_state->main.y = y;
2952
2953 return 0;
2954 }
2955
2956 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2957 {
2958 const struct drm_framebuffer *fb = plane_state->base.fb;
2959 unsigned int rotation = plane_state->base.rotation;
2960 int max_width = skl_max_plane_width(fb, 1, rotation);
2961 int max_height = 4096;
2962 int x = plane_state->base.src.x1 >> 17;
2963 int y = plane_state->base.src.y1 >> 17;
2964 int w = drm_rect_width(&plane_state->base.src) >> 17;
2965 int h = drm_rect_height(&plane_state->base.src) >> 17;
2966 u32 offset;
2967
2968 intel_add_fb_offsets(&x, &y, plane_state, 1);
2969 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2970
2971 /* FIXME not quite sure how/if these apply to the chroma plane */
2972 if (w > max_width || h > max_height) {
2973 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2974 w, h, max_width, max_height);
2975 return -EINVAL;
2976 }
2977
2978 plane_state->aux.offset = offset;
2979 plane_state->aux.x = x;
2980 plane_state->aux.y = y;
2981
2982 return 0;
2983 }
2984
2985 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2986 {
2987 const struct drm_framebuffer *fb = plane_state->base.fb;
2988 unsigned int rotation = plane_state->base.rotation;
2989 int ret;
2990
2991 /* Rotate src coordinates to match rotated GTT view */
2992 if (intel_rotation_90_or_270(rotation))
2993 drm_rect_rotate(&plane_state->base.src,
2994 fb->width, fb->height, DRM_ROTATE_270);
2995
2996 /*
2997 * Handle the AUX surface first since
2998 * the main surface setup depends on it.
2999 */
3000 if (fb->pixel_format == DRM_FORMAT_NV12) {
3001 ret = skl_check_nv12_aux_surface(plane_state);
3002 if (ret)
3003 return ret;
3004 } else {
3005 plane_state->aux.offset = ~0xfff;
3006 plane_state->aux.x = 0;
3007 plane_state->aux.y = 0;
3008 }
3009
3010 ret = skl_check_main_surface(plane_state);
3011 if (ret)
3012 return ret;
3013
3014 return 0;
3015 }
3016
3017 static void i9xx_update_primary_plane(struct drm_plane *primary,
3018 const struct intel_crtc_state *crtc_state,
3019 const struct intel_plane_state *plane_state)
3020 {
3021 struct drm_device *dev = primary->dev;
3022 struct drm_i915_private *dev_priv = to_i915(dev);
3023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3024 struct drm_framebuffer *fb = plane_state->base.fb;
3025 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3026 int plane = intel_crtc->plane;
3027 u32 linear_offset;
3028 u32 dspcntr;
3029 i915_reg_t reg = DSPCNTR(plane);
3030 unsigned int rotation = plane_state->base.rotation;
3031 int x = plane_state->base.src.x1 >> 16;
3032 int y = plane_state->base.src.y1 >> 16;
3033
3034 dspcntr = DISPPLANE_GAMMA_ENABLE;
3035
3036 dspcntr |= DISPLAY_PLANE_ENABLE;
3037
3038 if (INTEL_INFO(dev)->gen < 4) {
3039 if (intel_crtc->pipe == PIPE_B)
3040 dspcntr |= DISPPLANE_SEL_PIPE_B;
3041
3042 /* pipesrc and dspsize control the size that is scaled from,
3043 * which should always be the user's requested size.
3044 */
3045 I915_WRITE(DSPSIZE(plane),
3046 ((crtc_state->pipe_src_h - 1) << 16) |
3047 (crtc_state->pipe_src_w - 1));
3048 I915_WRITE(DSPPOS(plane), 0);
3049 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3050 I915_WRITE(PRIMSIZE(plane),
3051 ((crtc_state->pipe_src_h - 1) << 16) |
3052 (crtc_state->pipe_src_w - 1));
3053 I915_WRITE(PRIMPOS(plane), 0);
3054 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3055 }
3056
3057 switch (fb->pixel_format) {
3058 case DRM_FORMAT_C8:
3059 dspcntr |= DISPPLANE_8BPP;
3060 break;
3061 case DRM_FORMAT_XRGB1555:
3062 dspcntr |= DISPPLANE_BGRX555;
3063 break;
3064 case DRM_FORMAT_RGB565:
3065 dspcntr |= DISPPLANE_BGRX565;
3066 break;
3067 case DRM_FORMAT_XRGB8888:
3068 dspcntr |= DISPPLANE_BGRX888;
3069 break;
3070 case DRM_FORMAT_XBGR8888:
3071 dspcntr |= DISPPLANE_RGBX888;
3072 break;
3073 case DRM_FORMAT_XRGB2101010:
3074 dspcntr |= DISPPLANE_BGRX101010;
3075 break;
3076 case DRM_FORMAT_XBGR2101010:
3077 dspcntr |= DISPPLANE_RGBX101010;
3078 break;
3079 default:
3080 BUG();
3081 }
3082
3083 if (INTEL_GEN(dev_priv) >= 4 &&
3084 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3085 dspcntr |= DISPPLANE_TILED;
3086
3087 if (IS_G4X(dev))
3088 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3089
3090 intel_add_fb_offsets(&x, &y, plane_state, 0);
3091
3092 if (INTEL_INFO(dev)->gen >= 4)
3093 intel_crtc->dspaddr_offset =
3094 intel_compute_tile_offset(&x, &y, plane_state, 0);
3095
3096 if (rotation == DRM_ROTATE_180) {
3097 dspcntr |= DISPPLANE_ROTATE_180;
3098
3099 x += (crtc_state->pipe_src_w - 1);
3100 y += (crtc_state->pipe_src_h - 1);
3101 }
3102
3103 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3104
3105 if (INTEL_INFO(dev)->gen < 4)
3106 intel_crtc->dspaddr_offset = linear_offset;
3107
3108 intel_crtc->adjusted_x = x;
3109 intel_crtc->adjusted_y = y;
3110
3111 I915_WRITE(reg, dspcntr);
3112
3113 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3114 if (INTEL_INFO(dev)->gen >= 4) {
3115 I915_WRITE(DSPSURF(plane),
3116 intel_fb_gtt_offset(fb, rotation) +
3117 intel_crtc->dspaddr_offset);
3118 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3119 I915_WRITE(DSPLINOFF(plane), linear_offset);
3120 } else
3121 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3122 POSTING_READ(reg);
3123 }
3124
3125 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3126 struct drm_crtc *crtc)
3127 {
3128 struct drm_device *dev = crtc->dev;
3129 struct drm_i915_private *dev_priv = to_i915(dev);
3130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3131 int plane = intel_crtc->plane;
3132
3133 I915_WRITE(DSPCNTR(plane), 0);
3134 if (INTEL_INFO(dev_priv)->gen >= 4)
3135 I915_WRITE(DSPSURF(plane), 0);
3136 else
3137 I915_WRITE(DSPADDR(plane), 0);
3138 POSTING_READ(DSPCNTR(plane));
3139 }
3140
3141 static void ironlake_update_primary_plane(struct drm_plane *primary,
3142 const struct intel_crtc_state *crtc_state,
3143 const struct intel_plane_state *plane_state)
3144 {
3145 struct drm_device *dev = primary->dev;
3146 struct drm_i915_private *dev_priv = to_i915(dev);
3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3148 struct drm_framebuffer *fb = plane_state->base.fb;
3149 int plane = intel_crtc->plane;
3150 u32 linear_offset;
3151 u32 dspcntr;
3152 i915_reg_t reg = DSPCNTR(plane);
3153 unsigned int rotation = plane_state->base.rotation;
3154 int x = plane_state->base.src.x1 >> 16;
3155 int y = plane_state->base.src.y1 >> 16;
3156
3157 dspcntr = DISPPLANE_GAMMA_ENABLE;
3158 dspcntr |= DISPLAY_PLANE_ENABLE;
3159
3160 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3161 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3162
3163 switch (fb->pixel_format) {
3164 case DRM_FORMAT_C8:
3165 dspcntr |= DISPPLANE_8BPP;
3166 break;
3167 case DRM_FORMAT_RGB565:
3168 dspcntr |= DISPPLANE_BGRX565;
3169 break;
3170 case DRM_FORMAT_XRGB8888:
3171 dspcntr |= DISPPLANE_BGRX888;
3172 break;
3173 case DRM_FORMAT_XBGR8888:
3174 dspcntr |= DISPPLANE_RGBX888;
3175 break;
3176 case DRM_FORMAT_XRGB2101010:
3177 dspcntr |= DISPPLANE_BGRX101010;
3178 break;
3179 case DRM_FORMAT_XBGR2101010:
3180 dspcntr |= DISPPLANE_RGBX101010;
3181 break;
3182 default:
3183 BUG();
3184 }
3185
3186 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3187 dspcntr |= DISPPLANE_TILED;
3188
3189 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3190 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3191
3192 intel_add_fb_offsets(&x, &y, plane_state, 0);
3193
3194 intel_crtc->dspaddr_offset =
3195 intel_compute_tile_offset(&x, &y, plane_state, 0);
3196
3197 if (rotation == DRM_ROTATE_180) {
3198 dspcntr |= DISPPLANE_ROTATE_180;
3199
3200 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3201 x += (crtc_state->pipe_src_w - 1);
3202 y += (crtc_state->pipe_src_h - 1);
3203 }
3204 }
3205
3206 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3207
3208 intel_crtc->adjusted_x = x;
3209 intel_crtc->adjusted_y = y;
3210
3211 I915_WRITE(reg, dspcntr);
3212
3213 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3214 I915_WRITE(DSPSURF(plane),
3215 intel_fb_gtt_offset(fb, rotation) +
3216 intel_crtc->dspaddr_offset);
3217 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3218 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3219 } else {
3220 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3221 I915_WRITE(DSPLINOFF(plane), linear_offset);
3222 }
3223 POSTING_READ(reg);
3224 }
3225
3226 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3227 uint64_t fb_modifier, uint32_t pixel_format)
3228 {
3229 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3230 return 64;
3231 } else {
3232 int cpp = drm_format_plane_cpp(pixel_format, 0);
3233
3234 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3235 }
3236 }
3237
3238 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3239 unsigned int rotation)
3240 {
3241 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3242 struct i915_ggtt_view view;
3243 struct i915_vma *vma;
3244
3245 intel_fill_fb_ggtt_view(&view, fb, rotation);
3246
3247 vma = i915_gem_object_to_ggtt(obj, &view);
3248 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3249 view.type))
3250 return -1;
3251
3252 return i915_ggtt_offset(vma);
3253 }
3254
3255 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3256 {
3257 struct drm_device *dev = intel_crtc->base.dev;
3258 struct drm_i915_private *dev_priv = to_i915(dev);
3259
3260 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3261 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3262 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3263 }
3264
3265 /*
3266 * This function detaches (aka. unbinds) unused scalers in hardware
3267 */
3268 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3269 {
3270 struct intel_crtc_scaler_state *scaler_state;
3271 int i;
3272
3273 scaler_state = &intel_crtc->config->scaler_state;
3274
3275 /* loop through and disable scalers that aren't in use */
3276 for (i = 0; i < intel_crtc->num_scalers; i++) {
3277 if (!scaler_state->scalers[i].in_use)
3278 skl_detach_scaler(intel_crtc, i);
3279 }
3280 }
3281
3282 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3283 unsigned int rotation)
3284 {
3285 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3286 u32 stride = intel_fb_pitch(fb, plane, rotation);
3287
3288 /*
3289 * The stride is either expressed as a multiple of 64 bytes chunks for
3290 * linear buffers or in number of tiles for tiled buffers.
3291 */
3292 if (intel_rotation_90_or_270(rotation)) {
3293 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3294
3295 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3296 } else {
3297 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3298 fb->pixel_format);
3299 }
3300
3301 return stride;
3302 }
3303
3304 u32 skl_plane_ctl_format(uint32_t pixel_format)
3305 {
3306 switch (pixel_format) {
3307 case DRM_FORMAT_C8:
3308 return PLANE_CTL_FORMAT_INDEXED;
3309 case DRM_FORMAT_RGB565:
3310 return PLANE_CTL_FORMAT_RGB_565;
3311 case DRM_FORMAT_XBGR8888:
3312 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3313 case DRM_FORMAT_XRGB8888:
3314 return PLANE_CTL_FORMAT_XRGB_8888;
3315 /*
3316 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3317 * to be already pre-multiplied. We need to add a knob (or a different
3318 * DRM_FORMAT) for user-space to configure that.
3319 */
3320 case DRM_FORMAT_ABGR8888:
3321 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3322 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3323 case DRM_FORMAT_ARGB8888:
3324 return PLANE_CTL_FORMAT_XRGB_8888 |
3325 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3326 case DRM_FORMAT_XRGB2101010:
3327 return PLANE_CTL_FORMAT_XRGB_2101010;
3328 case DRM_FORMAT_XBGR2101010:
3329 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3330 case DRM_FORMAT_YUYV:
3331 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3332 case DRM_FORMAT_YVYU:
3333 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3334 case DRM_FORMAT_UYVY:
3335 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3336 case DRM_FORMAT_VYUY:
3337 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3338 default:
3339 MISSING_CASE(pixel_format);
3340 }
3341
3342 return 0;
3343 }
3344
3345 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3346 {
3347 switch (fb_modifier) {
3348 case DRM_FORMAT_MOD_NONE:
3349 break;
3350 case I915_FORMAT_MOD_X_TILED:
3351 return PLANE_CTL_TILED_X;
3352 case I915_FORMAT_MOD_Y_TILED:
3353 return PLANE_CTL_TILED_Y;
3354 case I915_FORMAT_MOD_Yf_TILED:
3355 return PLANE_CTL_TILED_YF;
3356 default:
3357 MISSING_CASE(fb_modifier);
3358 }
3359
3360 return 0;
3361 }
3362
3363 u32 skl_plane_ctl_rotation(unsigned int rotation)
3364 {
3365 switch (rotation) {
3366 case DRM_ROTATE_0:
3367 break;
3368 /*
3369 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3370 * while i915 HW rotation is clockwise, thats why this swapping.
3371 */
3372 case DRM_ROTATE_90:
3373 return PLANE_CTL_ROTATE_270;
3374 case DRM_ROTATE_180:
3375 return PLANE_CTL_ROTATE_180;
3376 case DRM_ROTATE_270:
3377 return PLANE_CTL_ROTATE_90;
3378 default:
3379 MISSING_CASE(rotation);
3380 }
3381
3382 return 0;
3383 }
3384
3385 static void skylake_update_primary_plane(struct drm_plane *plane,
3386 const struct intel_crtc_state *crtc_state,
3387 const struct intel_plane_state *plane_state)
3388 {
3389 struct drm_device *dev = plane->dev;
3390 struct drm_i915_private *dev_priv = to_i915(dev);
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3392 struct drm_framebuffer *fb = plane_state->base.fb;
3393 int pipe = intel_crtc->pipe;
3394 u32 plane_ctl;
3395 unsigned int rotation = plane_state->base.rotation;
3396 u32 stride = skl_plane_stride(fb, 0, rotation);
3397 u32 surf_addr = plane_state->main.offset;
3398 int scaler_id = plane_state->scaler_id;
3399 int src_x = plane_state->main.x;
3400 int src_y = plane_state->main.y;
3401 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3402 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3403 int dst_x = plane_state->base.dst.x1;
3404 int dst_y = plane_state->base.dst.y1;
3405 int dst_w = drm_rect_width(&plane_state->base.dst);
3406 int dst_h = drm_rect_height(&plane_state->base.dst);
3407
3408 plane_ctl = PLANE_CTL_ENABLE |
3409 PLANE_CTL_PIPE_GAMMA_ENABLE |
3410 PLANE_CTL_PIPE_CSC_ENABLE;
3411
3412 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3413 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3414 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3415 plane_ctl |= skl_plane_ctl_rotation(rotation);
3416
3417 /* Sizes are 0 based */
3418 src_w--;
3419 src_h--;
3420 dst_w--;
3421 dst_h--;
3422
3423 intel_crtc->adjusted_x = src_x;
3424 intel_crtc->adjusted_y = src_y;
3425
3426 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3427 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3428 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3429 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3430
3431 if (scaler_id >= 0) {
3432 uint32_t ps_ctrl = 0;
3433
3434 WARN_ON(!dst_w || !dst_h);
3435 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3436 crtc_state->scaler_state.scalers[scaler_id].mode;
3437 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3438 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3439 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3440 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3441 I915_WRITE(PLANE_POS(pipe, 0), 0);
3442 } else {
3443 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3444 }
3445
3446 I915_WRITE(PLANE_SURF(pipe, 0),
3447 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3448
3449 POSTING_READ(PLANE_SURF(pipe, 0));
3450 }
3451
3452 static void skylake_disable_primary_plane(struct drm_plane *primary,
3453 struct drm_crtc *crtc)
3454 {
3455 struct drm_device *dev = crtc->dev;
3456 struct drm_i915_private *dev_priv = to_i915(dev);
3457 int pipe = to_intel_crtc(crtc)->pipe;
3458
3459 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3460 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3461 POSTING_READ(PLANE_SURF(pipe, 0));
3462 }
3463
3464 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3465 static int
3466 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3467 int x, int y, enum mode_set_atomic state)
3468 {
3469 /* Support for kgdboc is disabled, this needs a major rework. */
3470 DRM_ERROR("legacy panic handler not supported any more.\n");
3471
3472 return -ENODEV;
3473 }
3474
3475 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3476 {
3477 struct intel_crtc *crtc;
3478
3479 for_each_intel_crtc(&dev_priv->drm, crtc)
3480 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3481 }
3482
3483 static void intel_update_primary_planes(struct drm_device *dev)
3484 {
3485 struct drm_crtc *crtc;
3486
3487 for_each_crtc(dev, crtc) {
3488 struct intel_plane *plane = to_intel_plane(crtc->primary);
3489 struct intel_plane_state *plane_state =
3490 to_intel_plane_state(plane->base.state);
3491
3492 if (plane_state->base.visible)
3493 plane->update_plane(&plane->base,
3494 to_intel_crtc_state(crtc->state),
3495 plane_state);
3496 }
3497 }
3498
3499 static int
3500 __intel_display_resume(struct drm_device *dev,
3501 struct drm_atomic_state *state)
3502 {
3503 struct drm_crtc_state *crtc_state;
3504 struct drm_crtc *crtc;
3505 int i, ret;
3506
3507 intel_modeset_setup_hw_state(dev);
3508 i915_redisable_vga(dev);
3509
3510 if (!state)
3511 return 0;
3512
3513 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3514 /*
3515 * Force recalculation even if we restore
3516 * current state. With fast modeset this may not result
3517 * in a modeset when the state is compatible.
3518 */
3519 crtc_state->mode_changed = true;
3520 }
3521
3522 /* ignore any reset values/BIOS leftovers in the WM registers */
3523 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3524
3525 ret = drm_atomic_commit(state);
3526
3527 WARN_ON(ret == -EDEADLK);
3528 return ret;
3529 }
3530
3531 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3532 {
3533 return intel_has_gpu_reset(dev_priv) &&
3534 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3535 }
3536
3537 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3538 {
3539 struct drm_device *dev = &dev_priv->drm;
3540 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3541 struct drm_atomic_state *state;
3542 int ret;
3543
3544 /*
3545 * Need mode_config.mutex so that we don't
3546 * trample ongoing ->detect() and whatnot.
3547 */
3548 mutex_lock(&dev->mode_config.mutex);
3549 drm_modeset_acquire_init(ctx, 0);
3550 while (1) {
3551 ret = drm_modeset_lock_all_ctx(dev, ctx);
3552 if (ret != -EDEADLK)
3553 break;
3554
3555 drm_modeset_backoff(ctx);
3556 }
3557
3558 /* reset doesn't touch the display, but flips might get nuked anyway, */
3559 if (!i915.force_reset_modeset_test &&
3560 !gpu_reset_clobbers_display(dev_priv))
3561 return;
3562
3563 /*
3564 * Disabling the crtcs gracefully seems nicer. Also the
3565 * g33 docs say we should at least disable all the planes.
3566 */
3567 state = drm_atomic_helper_duplicate_state(dev, ctx);
3568 if (IS_ERR(state)) {
3569 ret = PTR_ERR(state);
3570 state = NULL;
3571 DRM_ERROR("Duplicating state failed with %i\n", ret);
3572 goto err;
3573 }
3574
3575 ret = drm_atomic_helper_disable_all(dev, ctx);
3576 if (ret) {
3577 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3578 goto err;
3579 }
3580
3581 dev_priv->modeset_restore_state = state;
3582 state->acquire_ctx = ctx;
3583 return;
3584
3585 err:
3586 drm_atomic_state_free(state);
3587 }
3588
3589 void intel_finish_reset(struct drm_i915_private *dev_priv)
3590 {
3591 struct drm_device *dev = &dev_priv->drm;
3592 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3593 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3594 int ret;
3595
3596 /*
3597 * Flips in the rings will be nuked by the reset,
3598 * so complete all pending flips so that user space
3599 * will get its events and not get stuck.
3600 */
3601 intel_complete_page_flips(dev_priv);
3602
3603 dev_priv->modeset_restore_state = NULL;
3604
3605 /* reset doesn't touch the display */
3606 if (!gpu_reset_clobbers_display(dev_priv)) {
3607 if (!state) {
3608 /*
3609 * Flips in the rings have been nuked by the reset,
3610 * so update the base address of all primary
3611 * planes to the the last fb to make sure we're
3612 * showing the correct fb after a reset.
3613 *
3614 * FIXME: Atomic will make this obsolete since we won't schedule
3615 * CS-based flips (which might get lost in gpu resets) any more.
3616 */
3617 intel_update_primary_planes(dev);
3618 } else {
3619 ret = __intel_display_resume(dev, state);
3620 if (ret)
3621 DRM_ERROR("Restoring old state failed with %i\n", ret);
3622 }
3623 } else {
3624 /*
3625 * The display has been reset as well,
3626 * so need a full re-initialization.
3627 */
3628 intel_runtime_pm_disable_interrupts(dev_priv);
3629 intel_runtime_pm_enable_interrupts(dev_priv);
3630
3631 intel_modeset_init_hw(dev);
3632
3633 spin_lock_irq(&dev_priv->irq_lock);
3634 if (dev_priv->display.hpd_irq_setup)
3635 dev_priv->display.hpd_irq_setup(dev_priv);
3636 spin_unlock_irq(&dev_priv->irq_lock);
3637
3638 ret = __intel_display_resume(dev, state);
3639 if (ret)
3640 DRM_ERROR("Restoring old state failed with %i\n", ret);
3641
3642 intel_hpd_init(dev_priv);
3643 }
3644
3645 drm_modeset_drop_locks(ctx);
3646 drm_modeset_acquire_fini(ctx);
3647 mutex_unlock(&dev->mode_config.mutex);
3648 }
3649
3650 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3651 {
3652 struct drm_device *dev = crtc->dev;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654 unsigned reset_counter;
3655 bool pending;
3656
3657 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3658 if (intel_crtc->reset_counter != reset_counter)
3659 return false;
3660
3661 spin_lock_irq(&dev->event_lock);
3662 pending = to_intel_crtc(crtc)->flip_work != NULL;
3663 spin_unlock_irq(&dev->event_lock);
3664
3665 return pending;
3666 }
3667
3668 static void intel_update_pipe_config(struct intel_crtc *crtc,
3669 struct intel_crtc_state *old_crtc_state)
3670 {
3671 struct drm_device *dev = crtc->base.dev;
3672 struct drm_i915_private *dev_priv = to_i915(dev);
3673 struct intel_crtc_state *pipe_config =
3674 to_intel_crtc_state(crtc->base.state);
3675
3676 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3677 crtc->base.mode = crtc->base.state->mode;
3678
3679 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3680 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3681 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3682
3683 /*
3684 * Update pipe size and adjust fitter if needed: the reason for this is
3685 * that in compute_mode_changes we check the native mode (not the pfit
3686 * mode) to see if we can flip rather than do a full mode set. In the
3687 * fastboot case, we'll flip, but if we don't update the pipesrc and
3688 * pfit state, we'll end up with a big fb scanned out into the wrong
3689 * sized surface.
3690 */
3691
3692 I915_WRITE(PIPESRC(crtc->pipe),
3693 ((pipe_config->pipe_src_w - 1) << 16) |
3694 (pipe_config->pipe_src_h - 1));
3695
3696 /* on skylake this is done by detaching scalers */
3697 if (INTEL_INFO(dev)->gen >= 9) {
3698 skl_detach_scalers(crtc);
3699
3700 if (pipe_config->pch_pfit.enabled)
3701 skylake_pfit_enable(crtc);
3702 } else if (HAS_PCH_SPLIT(dev)) {
3703 if (pipe_config->pch_pfit.enabled)
3704 ironlake_pfit_enable(crtc);
3705 else if (old_crtc_state->pch_pfit.enabled)
3706 ironlake_pfit_disable(crtc, true);
3707 }
3708 }
3709
3710 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3711 {
3712 struct drm_device *dev = crtc->dev;
3713 struct drm_i915_private *dev_priv = to_i915(dev);
3714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3715 int pipe = intel_crtc->pipe;
3716 i915_reg_t reg;
3717 u32 temp;
3718
3719 /* enable normal train */
3720 reg = FDI_TX_CTL(pipe);
3721 temp = I915_READ(reg);
3722 if (IS_IVYBRIDGE(dev)) {
3723 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3724 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3725 } else {
3726 temp &= ~FDI_LINK_TRAIN_NONE;
3727 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3728 }
3729 I915_WRITE(reg, temp);
3730
3731 reg = FDI_RX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 if (HAS_PCH_CPT(dev)) {
3734 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3735 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3736 } else {
3737 temp &= ~FDI_LINK_TRAIN_NONE;
3738 temp |= FDI_LINK_TRAIN_NONE;
3739 }
3740 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3741
3742 /* wait one idle pattern time */
3743 POSTING_READ(reg);
3744 udelay(1000);
3745
3746 /* IVB wants error correction enabled */
3747 if (IS_IVYBRIDGE(dev))
3748 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3749 FDI_FE_ERRC_ENABLE);
3750 }
3751
3752 /* The FDI link training functions for ILK/Ibexpeak. */
3753 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3754 {
3755 struct drm_device *dev = crtc->dev;
3756 struct drm_i915_private *dev_priv = to_i915(dev);
3757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3758 int pipe = intel_crtc->pipe;
3759 i915_reg_t reg;
3760 u32 temp, tries;
3761
3762 /* FDI needs bits from pipe first */
3763 assert_pipe_enabled(dev_priv, pipe);
3764
3765 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3766 for train result */
3767 reg = FDI_RX_IMR(pipe);
3768 temp = I915_READ(reg);
3769 temp &= ~FDI_RX_SYMBOL_LOCK;
3770 temp &= ~FDI_RX_BIT_LOCK;
3771 I915_WRITE(reg, temp);
3772 I915_READ(reg);
3773 udelay(150);
3774
3775 /* enable CPU FDI TX and PCH FDI RX */
3776 reg = FDI_TX_CTL(pipe);
3777 temp = I915_READ(reg);
3778 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3779 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3780 temp &= ~FDI_LINK_TRAIN_NONE;
3781 temp |= FDI_LINK_TRAIN_PATTERN_1;
3782 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3783
3784 reg = FDI_RX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 temp &= ~FDI_LINK_TRAIN_NONE;
3787 temp |= FDI_LINK_TRAIN_PATTERN_1;
3788 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3789
3790 POSTING_READ(reg);
3791 udelay(150);
3792
3793 /* Ironlake workaround, enable clock pointer after FDI enable*/
3794 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3795 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3796 FDI_RX_PHASE_SYNC_POINTER_EN);
3797
3798 reg = FDI_RX_IIR(pipe);
3799 for (tries = 0; tries < 5; tries++) {
3800 temp = I915_READ(reg);
3801 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3802
3803 if ((temp & FDI_RX_BIT_LOCK)) {
3804 DRM_DEBUG_KMS("FDI train 1 done.\n");
3805 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3806 break;
3807 }
3808 }
3809 if (tries == 5)
3810 DRM_ERROR("FDI train 1 fail!\n");
3811
3812 /* Train 2 */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 temp &= ~FDI_LINK_TRAIN_NONE;
3816 temp |= FDI_LINK_TRAIN_PATTERN_2;
3817 I915_WRITE(reg, temp);
3818
3819 reg = FDI_RX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 temp &= ~FDI_LINK_TRAIN_NONE;
3822 temp |= FDI_LINK_TRAIN_PATTERN_2;
3823 I915_WRITE(reg, temp);
3824
3825 POSTING_READ(reg);
3826 udelay(150);
3827
3828 reg = FDI_RX_IIR(pipe);
3829 for (tries = 0; tries < 5; tries++) {
3830 temp = I915_READ(reg);
3831 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3832
3833 if (temp & FDI_RX_SYMBOL_LOCK) {
3834 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3835 DRM_DEBUG_KMS("FDI train 2 done.\n");
3836 break;
3837 }
3838 }
3839 if (tries == 5)
3840 DRM_ERROR("FDI train 2 fail!\n");
3841
3842 DRM_DEBUG_KMS("FDI train done\n");
3843
3844 }
3845
3846 static const int snb_b_fdi_train_param[] = {
3847 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3848 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3849 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3850 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3851 };
3852
3853 /* The FDI link training functions for SNB/Cougarpoint. */
3854 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3855 {
3856 struct drm_device *dev = crtc->dev;
3857 struct drm_i915_private *dev_priv = to_i915(dev);
3858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3859 int pipe = intel_crtc->pipe;
3860 i915_reg_t reg;
3861 u32 temp, i, retry;
3862
3863 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3864 for train result */
3865 reg = FDI_RX_IMR(pipe);
3866 temp = I915_READ(reg);
3867 temp &= ~FDI_RX_SYMBOL_LOCK;
3868 temp &= ~FDI_RX_BIT_LOCK;
3869 I915_WRITE(reg, temp);
3870
3871 POSTING_READ(reg);
3872 udelay(150);
3873
3874 /* enable CPU FDI TX and PCH FDI RX */
3875 reg = FDI_TX_CTL(pipe);
3876 temp = I915_READ(reg);
3877 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3878 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3879 temp &= ~FDI_LINK_TRAIN_NONE;
3880 temp |= FDI_LINK_TRAIN_PATTERN_1;
3881 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3882 /* SNB-B */
3883 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3884 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3885
3886 I915_WRITE(FDI_RX_MISC(pipe),
3887 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3888
3889 reg = FDI_RX_CTL(pipe);
3890 temp = I915_READ(reg);
3891 if (HAS_PCH_CPT(dev)) {
3892 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3893 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3894 } else {
3895 temp &= ~FDI_LINK_TRAIN_NONE;
3896 temp |= FDI_LINK_TRAIN_PATTERN_1;
3897 }
3898 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3899
3900 POSTING_READ(reg);
3901 udelay(150);
3902
3903 for (i = 0; i < 4; i++) {
3904 reg = FDI_TX_CTL(pipe);
3905 temp = I915_READ(reg);
3906 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3907 temp |= snb_b_fdi_train_param[i];
3908 I915_WRITE(reg, temp);
3909
3910 POSTING_READ(reg);
3911 udelay(500);
3912
3913 for (retry = 0; retry < 5; retry++) {
3914 reg = FDI_RX_IIR(pipe);
3915 temp = I915_READ(reg);
3916 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3917 if (temp & FDI_RX_BIT_LOCK) {
3918 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3919 DRM_DEBUG_KMS("FDI train 1 done.\n");
3920 break;
3921 }
3922 udelay(50);
3923 }
3924 if (retry < 5)
3925 break;
3926 }
3927 if (i == 4)
3928 DRM_ERROR("FDI train 1 fail!\n");
3929
3930 /* Train 2 */
3931 reg = FDI_TX_CTL(pipe);
3932 temp = I915_READ(reg);
3933 temp &= ~FDI_LINK_TRAIN_NONE;
3934 temp |= FDI_LINK_TRAIN_PATTERN_2;
3935 if (IS_GEN6(dev)) {
3936 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3937 /* SNB-B */
3938 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3939 }
3940 I915_WRITE(reg, temp);
3941
3942 reg = FDI_RX_CTL(pipe);
3943 temp = I915_READ(reg);
3944 if (HAS_PCH_CPT(dev)) {
3945 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3946 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3947 } else {
3948 temp &= ~FDI_LINK_TRAIN_NONE;
3949 temp |= FDI_LINK_TRAIN_PATTERN_2;
3950 }
3951 I915_WRITE(reg, temp);
3952
3953 POSTING_READ(reg);
3954 udelay(150);
3955
3956 for (i = 0; i < 4; i++) {
3957 reg = FDI_TX_CTL(pipe);
3958 temp = I915_READ(reg);
3959 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3960 temp |= snb_b_fdi_train_param[i];
3961 I915_WRITE(reg, temp);
3962
3963 POSTING_READ(reg);
3964 udelay(500);
3965
3966 for (retry = 0; retry < 5; retry++) {
3967 reg = FDI_RX_IIR(pipe);
3968 temp = I915_READ(reg);
3969 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3970 if (temp & FDI_RX_SYMBOL_LOCK) {
3971 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3972 DRM_DEBUG_KMS("FDI train 2 done.\n");
3973 break;
3974 }
3975 udelay(50);
3976 }
3977 if (retry < 5)
3978 break;
3979 }
3980 if (i == 4)
3981 DRM_ERROR("FDI train 2 fail!\n");
3982
3983 DRM_DEBUG_KMS("FDI train done.\n");
3984 }
3985
3986 /* Manual link training for Ivy Bridge A0 parts */
3987 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3988 {
3989 struct drm_device *dev = crtc->dev;
3990 struct drm_i915_private *dev_priv = to_i915(dev);
3991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3992 int pipe = intel_crtc->pipe;
3993 i915_reg_t reg;
3994 u32 temp, i, j;
3995
3996 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3997 for train result */
3998 reg = FDI_RX_IMR(pipe);
3999 temp = I915_READ(reg);
4000 temp &= ~FDI_RX_SYMBOL_LOCK;
4001 temp &= ~FDI_RX_BIT_LOCK;
4002 I915_WRITE(reg, temp);
4003
4004 POSTING_READ(reg);
4005 udelay(150);
4006
4007 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4008 I915_READ(FDI_RX_IIR(pipe)));
4009
4010 /* Try each vswing and preemphasis setting twice before moving on */
4011 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4012 /* disable first in case we need to retry */
4013 reg = FDI_TX_CTL(pipe);
4014 temp = I915_READ(reg);
4015 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4016 temp &= ~FDI_TX_ENABLE;
4017 I915_WRITE(reg, temp);
4018
4019 reg = FDI_RX_CTL(pipe);
4020 temp = I915_READ(reg);
4021 temp &= ~FDI_LINK_TRAIN_AUTO;
4022 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4023 temp &= ~FDI_RX_ENABLE;
4024 I915_WRITE(reg, temp);
4025
4026 /* enable CPU FDI TX and PCH FDI RX */
4027 reg = FDI_TX_CTL(pipe);
4028 temp = I915_READ(reg);
4029 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4030 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4031 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4032 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4033 temp |= snb_b_fdi_train_param[j/2];
4034 temp |= FDI_COMPOSITE_SYNC;
4035 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4036
4037 I915_WRITE(FDI_RX_MISC(pipe),
4038 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4039
4040 reg = FDI_RX_CTL(pipe);
4041 temp = I915_READ(reg);
4042 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4043 temp |= FDI_COMPOSITE_SYNC;
4044 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4045
4046 POSTING_READ(reg);
4047 udelay(1); /* should be 0.5us */
4048
4049 for (i = 0; i < 4; i++) {
4050 reg = FDI_RX_IIR(pipe);
4051 temp = I915_READ(reg);
4052 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4053
4054 if (temp & FDI_RX_BIT_LOCK ||
4055 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4056 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4057 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4058 i);
4059 break;
4060 }
4061 udelay(1); /* should be 0.5us */
4062 }
4063 if (i == 4) {
4064 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4065 continue;
4066 }
4067
4068 /* Train 2 */
4069 reg = FDI_TX_CTL(pipe);
4070 temp = I915_READ(reg);
4071 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4072 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4073 I915_WRITE(reg, temp);
4074
4075 reg = FDI_RX_CTL(pipe);
4076 temp = I915_READ(reg);
4077 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4078 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4079 I915_WRITE(reg, temp);
4080
4081 POSTING_READ(reg);
4082 udelay(2); /* should be 1.5us */
4083
4084 for (i = 0; i < 4; i++) {
4085 reg = FDI_RX_IIR(pipe);
4086 temp = I915_READ(reg);
4087 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4088
4089 if (temp & FDI_RX_SYMBOL_LOCK ||
4090 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4091 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4092 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4093 i);
4094 goto train_done;
4095 }
4096 udelay(2); /* should be 1.5us */
4097 }
4098 if (i == 4)
4099 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4100 }
4101
4102 train_done:
4103 DRM_DEBUG_KMS("FDI train done.\n");
4104 }
4105
4106 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4107 {
4108 struct drm_device *dev = intel_crtc->base.dev;
4109 struct drm_i915_private *dev_priv = to_i915(dev);
4110 int pipe = intel_crtc->pipe;
4111 i915_reg_t reg;
4112 u32 temp;
4113
4114 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4115 reg = FDI_RX_CTL(pipe);
4116 temp = I915_READ(reg);
4117 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4118 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4119 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4120 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4121
4122 POSTING_READ(reg);
4123 udelay(200);
4124
4125 /* Switch from Rawclk to PCDclk */
4126 temp = I915_READ(reg);
4127 I915_WRITE(reg, temp | FDI_PCDCLK);
4128
4129 POSTING_READ(reg);
4130 udelay(200);
4131
4132 /* Enable CPU FDI TX PLL, always on for Ironlake */
4133 reg = FDI_TX_CTL(pipe);
4134 temp = I915_READ(reg);
4135 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4136 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4137
4138 POSTING_READ(reg);
4139 udelay(100);
4140 }
4141 }
4142
4143 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4144 {
4145 struct drm_device *dev = intel_crtc->base.dev;
4146 struct drm_i915_private *dev_priv = to_i915(dev);
4147 int pipe = intel_crtc->pipe;
4148 i915_reg_t reg;
4149 u32 temp;
4150
4151 /* Switch from PCDclk to Rawclk */
4152 reg = FDI_RX_CTL(pipe);
4153 temp = I915_READ(reg);
4154 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4155
4156 /* Disable CPU FDI TX PLL */
4157 reg = FDI_TX_CTL(pipe);
4158 temp = I915_READ(reg);
4159 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4160
4161 POSTING_READ(reg);
4162 udelay(100);
4163
4164 reg = FDI_RX_CTL(pipe);
4165 temp = I915_READ(reg);
4166 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4167
4168 /* Wait for the clocks to turn off. */
4169 POSTING_READ(reg);
4170 udelay(100);
4171 }
4172
4173 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4174 {
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = to_i915(dev);
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 int pipe = intel_crtc->pipe;
4179 i915_reg_t reg;
4180 u32 temp;
4181
4182 /* disable CPU FDI tx and PCH FDI rx */
4183 reg = FDI_TX_CTL(pipe);
4184 temp = I915_READ(reg);
4185 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4186 POSTING_READ(reg);
4187
4188 reg = FDI_RX_CTL(pipe);
4189 temp = I915_READ(reg);
4190 temp &= ~(0x7 << 16);
4191 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4192 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4193
4194 POSTING_READ(reg);
4195 udelay(100);
4196
4197 /* Ironlake workaround, disable clock pointer after downing FDI */
4198 if (HAS_PCH_IBX(dev))
4199 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4200
4201 /* still set train pattern 1 */
4202 reg = FDI_TX_CTL(pipe);
4203 temp = I915_READ(reg);
4204 temp &= ~FDI_LINK_TRAIN_NONE;
4205 temp |= FDI_LINK_TRAIN_PATTERN_1;
4206 I915_WRITE(reg, temp);
4207
4208 reg = FDI_RX_CTL(pipe);
4209 temp = I915_READ(reg);
4210 if (HAS_PCH_CPT(dev)) {
4211 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4212 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4213 } else {
4214 temp &= ~FDI_LINK_TRAIN_NONE;
4215 temp |= FDI_LINK_TRAIN_PATTERN_1;
4216 }
4217 /* BPC in FDI rx is consistent with that in PIPECONF */
4218 temp &= ~(0x07 << 16);
4219 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4220 I915_WRITE(reg, temp);
4221
4222 POSTING_READ(reg);
4223 udelay(100);
4224 }
4225
4226 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4227 {
4228 struct intel_crtc *crtc;
4229
4230 /* Note that we don't need to be called with mode_config.lock here
4231 * as our list of CRTC objects is static for the lifetime of the
4232 * device and so cannot disappear as we iterate. Similarly, we can
4233 * happily treat the predicates as racy, atomic checks as userspace
4234 * cannot claim and pin a new fb without at least acquring the
4235 * struct_mutex and so serialising with us.
4236 */
4237 for_each_intel_crtc(dev, crtc) {
4238 if (atomic_read(&crtc->unpin_work_count) == 0)
4239 continue;
4240
4241 if (crtc->flip_work)
4242 intel_wait_for_vblank(dev, crtc->pipe);
4243
4244 return true;
4245 }
4246
4247 return false;
4248 }
4249
4250 static void page_flip_completed(struct intel_crtc *intel_crtc)
4251 {
4252 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4253 struct intel_flip_work *work = intel_crtc->flip_work;
4254
4255 intel_crtc->flip_work = NULL;
4256
4257 if (work->event)
4258 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4259
4260 drm_crtc_vblank_put(&intel_crtc->base);
4261
4262 wake_up_all(&dev_priv->pending_flip_queue);
4263 queue_work(dev_priv->wq, &work->unpin_work);
4264
4265 trace_i915_flip_complete(intel_crtc->plane,
4266 work->pending_flip_obj);
4267 }
4268
4269 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4270 {
4271 struct drm_device *dev = crtc->dev;
4272 struct drm_i915_private *dev_priv = to_i915(dev);
4273 long ret;
4274
4275 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4276
4277 ret = wait_event_interruptible_timeout(
4278 dev_priv->pending_flip_queue,
4279 !intel_crtc_has_pending_flip(crtc),
4280 60*HZ);
4281
4282 if (ret < 0)
4283 return ret;
4284
4285 if (ret == 0) {
4286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4287 struct intel_flip_work *work;
4288
4289 spin_lock_irq(&dev->event_lock);
4290 work = intel_crtc->flip_work;
4291 if (work && !is_mmio_work(work)) {
4292 WARN_ONCE(1, "Removing stuck page flip\n");
4293 page_flip_completed(intel_crtc);
4294 }
4295 spin_unlock_irq(&dev->event_lock);
4296 }
4297
4298 return 0;
4299 }
4300
4301 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4302 {
4303 u32 temp;
4304
4305 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4306
4307 mutex_lock(&dev_priv->sb_lock);
4308
4309 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4310 temp |= SBI_SSCCTL_DISABLE;
4311 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4312
4313 mutex_unlock(&dev_priv->sb_lock);
4314 }
4315
4316 /* Program iCLKIP clock to the desired frequency */
4317 static void lpt_program_iclkip(struct drm_crtc *crtc)
4318 {
4319 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4320 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4321 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4322 u32 temp;
4323
4324 lpt_disable_iclkip(dev_priv);
4325
4326 /* The iCLK virtual clock root frequency is in MHz,
4327 * but the adjusted_mode->crtc_clock in in KHz. To get the
4328 * divisors, it is necessary to divide one by another, so we
4329 * convert the virtual clock precision to KHz here for higher
4330 * precision.
4331 */
4332 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4333 u32 iclk_virtual_root_freq = 172800 * 1000;
4334 u32 iclk_pi_range = 64;
4335 u32 desired_divisor;
4336
4337 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4338 clock << auxdiv);
4339 divsel = (desired_divisor / iclk_pi_range) - 2;
4340 phaseinc = desired_divisor % iclk_pi_range;
4341
4342 /*
4343 * Near 20MHz is a corner case which is
4344 * out of range for the 7-bit divisor
4345 */
4346 if (divsel <= 0x7f)
4347 break;
4348 }
4349
4350 /* This should not happen with any sane values */
4351 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4352 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4353 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4354 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4355
4356 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4357 clock,
4358 auxdiv,
4359 divsel,
4360 phasedir,
4361 phaseinc);
4362
4363 mutex_lock(&dev_priv->sb_lock);
4364
4365 /* Program SSCDIVINTPHASE6 */
4366 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4367 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4368 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4369 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4370 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4371 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4372 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4373 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4374
4375 /* Program SSCAUXDIV */
4376 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4377 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4378 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4379 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4380
4381 /* Enable modulator and associated divider */
4382 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4383 temp &= ~SBI_SSCCTL_DISABLE;
4384 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4385
4386 mutex_unlock(&dev_priv->sb_lock);
4387
4388 /* Wait for initialization time */
4389 udelay(24);
4390
4391 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4392 }
4393
4394 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4395 {
4396 u32 divsel, phaseinc, auxdiv;
4397 u32 iclk_virtual_root_freq = 172800 * 1000;
4398 u32 iclk_pi_range = 64;
4399 u32 desired_divisor;
4400 u32 temp;
4401
4402 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4403 return 0;
4404
4405 mutex_lock(&dev_priv->sb_lock);
4406
4407 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4408 if (temp & SBI_SSCCTL_DISABLE) {
4409 mutex_unlock(&dev_priv->sb_lock);
4410 return 0;
4411 }
4412
4413 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4414 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4415 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4416 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4417 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4418
4419 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4420 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4421 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4422
4423 mutex_unlock(&dev_priv->sb_lock);
4424
4425 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4426
4427 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4428 desired_divisor << auxdiv);
4429 }
4430
4431 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4432 enum pipe pch_transcoder)
4433 {
4434 struct drm_device *dev = crtc->base.dev;
4435 struct drm_i915_private *dev_priv = to_i915(dev);
4436 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4437
4438 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4439 I915_READ(HTOTAL(cpu_transcoder)));
4440 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4441 I915_READ(HBLANK(cpu_transcoder)));
4442 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4443 I915_READ(HSYNC(cpu_transcoder)));
4444
4445 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4446 I915_READ(VTOTAL(cpu_transcoder)));
4447 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4448 I915_READ(VBLANK(cpu_transcoder)));
4449 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4450 I915_READ(VSYNC(cpu_transcoder)));
4451 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4452 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4453 }
4454
4455 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4456 {
4457 struct drm_i915_private *dev_priv = to_i915(dev);
4458 uint32_t temp;
4459
4460 temp = I915_READ(SOUTH_CHICKEN1);
4461 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4462 return;
4463
4464 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4465 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4466
4467 temp &= ~FDI_BC_BIFURCATION_SELECT;
4468 if (enable)
4469 temp |= FDI_BC_BIFURCATION_SELECT;
4470
4471 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4472 I915_WRITE(SOUTH_CHICKEN1, temp);
4473 POSTING_READ(SOUTH_CHICKEN1);
4474 }
4475
4476 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4477 {
4478 struct drm_device *dev = intel_crtc->base.dev;
4479
4480 switch (intel_crtc->pipe) {
4481 case PIPE_A:
4482 break;
4483 case PIPE_B:
4484 if (intel_crtc->config->fdi_lanes > 2)
4485 cpt_set_fdi_bc_bifurcation(dev, false);
4486 else
4487 cpt_set_fdi_bc_bifurcation(dev, true);
4488
4489 break;
4490 case PIPE_C:
4491 cpt_set_fdi_bc_bifurcation(dev, true);
4492
4493 break;
4494 default:
4495 BUG();
4496 }
4497 }
4498
4499 /* Return which DP Port should be selected for Transcoder DP control */
4500 static enum port
4501 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4502 {
4503 struct drm_device *dev = crtc->dev;
4504 struct intel_encoder *encoder;
4505
4506 for_each_encoder_on_crtc(dev, crtc, encoder) {
4507 if (encoder->type == INTEL_OUTPUT_DP ||
4508 encoder->type == INTEL_OUTPUT_EDP)
4509 return enc_to_dig_port(&encoder->base)->port;
4510 }
4511
4512 return -1;
4513 }
4514
4515 /*
4516 * Enable PCH resources required for PCH ports:
4517 * - PCH PLLs
4518 * - FDI training & RX/TX
4519 * - update transcoder timings
4520 * - DP transcoding bits
4521 * - transcoder
4522 */
4523 static void ironlake_pch_enable(struct drm_crtc *crtc)
4524 {
4525 struct drm_device *dev = crtc->dev;
4526 struct drm_i915_private *dev_priv = to_i915(dev);
4527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4528 int pipe = intel_crtc->pipe;
4529 u32 temp;
4530
4531 assert_pch_transcoder_disabled(dev_priv, pipe);
4532
4533 if (IS_IVYBRIDGE(dev))
4534 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4535
4536 /* Write the TU size bits before fdi link training, so that error
4537 * detection works. */
4538 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4539 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4540
4541 /* For PCH output, training FDI link */
4542 dev_priv->display.fdi_link_train(crtc);
4543
4544 /* We need to program the right clock selection before writing the pixel
4545 * mutliplier into the DPLL. */
4546 if (HAS_PCH_CPT(dev)) {
4547 u32 sel;
4548
4549 temp = I915_READ(PCH_DPLL_SEL);
4550 temp |= TRANS_DPLL_ENABLE(pipe);
4551 sel = TRANS_DPLLB_SEL(pipe);
4552 if (intel_crtc->config->shared_dpll ==
4553 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4554 temp |= sel;
4555 else
4556 temp &= ~sel;
4557 I915_WRITE(PCH_DPLL_SEL, temp);
4558 }
4559
4560 /* XXX: pch pll's can be enabled any time before we enable the PCH
4561 * transcoder, and we actually should do this to not upset any PCH
4562 * transcoder that already use the clock when we share it.
4563 *
4564 * Note that enable_shared_dpll tries to do the right thing, but
4565 * get_shared_dpll unconditionally resets the pll - we need that to have
4566 * the right LVDS enable sequence. */
4567 intel_enable_shared_dpll(intel_crtc);
4568
4569 /* set transcoder timing, panel must allow it */
4570 assert_panel_unlocked(dev_priv, pipe);
4571 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4572
4573 intel_fdi_normal_train(crtc);
4574
4575 /* For PCH DP, enable TRANS_DP_CTL */
4576 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4577 const struct drm_display_mode *adjusted_mode =
4578 &intel_crtc->config->base.adjusted_mode;
4579 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4580 i915_reg_t reg = TRANS_DP_CTL(pipe);
4581 temp = I915_READ(reg);
4582 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4583 TRANS_DP_SYNC_MASK |
4584 TRANS_DP_BPC_MASK);
4585 temp |= TRANS_DP_OUTPUT_ENABLE;
4586 temp |= bpc << 9; /* same format but at 11:9 */
4587
4588 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4589 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4590 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4591 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4592
4593 switch (intel_trans_dp_port_sel(crtc)) {
4594 case PORT_B:
4595 temp |= TRANS_DP_PORT_SEL_B;
4596 break;
4597 case PORT_C:
4598 temp |= TRANS_DP_PORT_SEL_C;
4599 break;
4600 case PORT_D:
4601 temp |= TRANS_DP_PORT_SEL_D;
4602 break;
4603 default:
4604 BUG();
4605 }
4606
4607 I915_WRITE(reg, temp);
4608 }
4609
4610 ironlake_enable_pch_transcoder(dev_priv, pipe);
4611 }
4612
4613 static void lpt_pch_enable(struct drm_crtc *crtc)
4614 {
4615 struct drm_device *dev = crtc->dev;
4616 struct drm_i915_private *dev_priv = to_i915(dev);
4617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4618 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4619
4620 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4621
4622 lpt_program_iclkip(crtc);
4623
4624 /* Set transcoder timing. */
4625 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4626
4627 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4628 }
4629
4630 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4631 {
4632 struct drm_i915_private *dev_priv = to_i915(dev);
4633 i915_reg_t dslreg = PIPEDSL(pipe);
4634 u32 temp;
4635
4636 temp = I915_READ(dslreg);
4637 udelay(500);
4638 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4639 if (wait_for(I915_READ(dslreg) != temp, 5))
4640 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4641 }
4642 }
4643
4644 static int
4645 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4646 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4647 int src_w, int src_h, int dst_w, int dst_h)
4648 {
4649 struct intel_crtc_scaler_state *scaler_state =
4650 &crtc_state->scaler_state;
4651 struct intel_crtc *intel_crtc =
4652 to_intel_crtc(crtc_state->base.crtc);
4653 int need_scaling;
4654
4655 need_scaling = intel_rotation_90_or_270(rotation) ?
4656 (src_h != dst_w || src_w != dst_h):
4657 (src_w != dst_w || src_h != dst_h);
4658
4659 /*
4660 * if plane is being disabled or scaler is no more required or force detach
4661 * - free scaler binded to this plane/crtc
4662 * - in order to do this, update crtc->scaler_usage
4663 *
4664 * Here scaler state in crtc_state is set free so that
4665 * scaler can be assigned to other user. Actual register
4666 * update to free the scaler is done in plane/panel-fit programming.
4667 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4668 */
4669 if (force_detach || !need_scaling) {
4670 if (*scaler_id >= 0) {
4671 scaler_state->scaler_users &= ~(1 << scaler_user);
4672 scaler_state->scalers[*scaler_id].in_use = 0;
4673
4674 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4675 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4676 intel_crtc->pipe, scaler_user, *scaler_id,
4677 scaler_state->scaler_users);
4678 *scaler_id = -1;
4679 }
4680 return 0;
4681 }
4682
4683 /* range checks */
4684 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4685 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4686
4687 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4688 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4689 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4690 "size is out of scaler range\n",
4691 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4692 return -EINVAL;
4693 }
4694
4695 /* mark this plane as a scaler user in crtc_state */
4696 scaler_state->scaler_users |= (1 << scaler_user);
4697 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4698 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4699 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4700 scaler_state->scaler_users);
4701
4702 return 0;
4703 }
4704
4705 /**
4706 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4707 *
4708 * @state: crtc's scaler state
4709 *
4710 * Return
4711 * 0 - scaler_usage updated successfully
4712 * error - requested scaling cannot be supported or other error condition
4713 */
4714 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4715 {
4716 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4717 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4718
4719 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4720 intel_crtc->base.base.id, intel_crtc->base.name,
4721 intel_crtc->pipe, SKL_CRTC_INDEX);
4722
4723 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4724 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4725 state->pipe_src_w, state->pipe_src_h,
4726 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4727 }
4728
4729 /**
4730 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4731 *
4732 * @state: crtc's scaler state
4733 * @plane_state: atomic plane state to update
4734 *
4735 * Return
4736 * 0 - scaler_usage updated successfully
4737 * error - requested scaling cannot be supported or other error condition
4738 */
4739 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4740 struct intel_plane_state *plane_state)
4741 {
4742
4743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4744 struct intel_plane *intel_plane =
4745 to_intel_plane(plane_state->base.plane);
4746 struct drm_framebuffer *fb = plane_state->base.fb;
4747 int ret;
4748
4749 bool force_detach = !fb || !plane_state->base.visible;
4750
4751 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4752 intel_plane->base.base.id, intel_plane->base.name,
4753 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4754
4755 ret = skl_update_scaler(crtc_state, force_detach,
4756 drm_plane_index(&intel_plane->base),
4757 &plane_state->scaler_id,
4758 plane_state->base.rotation,
4759 drm_rect_width(&plane_state->base.src) >> 16,
4760 drm_rect_height(&plane_state->base.src) >> 16,
4761 drm_rect_width(&plane_state->base.dst),
4762 drm_rect_height(&plane_state->base.dst));
4763
4764 if (ret || plane_state->scaler_id < 0)
4765 return ret;
4766
4767 /* check colorkey */
4768 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4769 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4770 intel_plane->base.base.id,
4771 intel_plane->base.name);
4772 return -EINVAL;
4773 }
4774
4775 /* Check src format */
4776 switch (fb->pixel_format) {
4777 case DRM_FORMAT_RGB565:
4778 case DRM_FORMAT_XBGR8888:
4779 case DRM_FORMAT_XRGB8888:
4780 case DRM_FORMAT_ABGR8888:
4781 case DRM_FORMAT_ARGB8888:
4782 case DRM_FORMAT_XRGB2101010:
4783 case DRM_FORMAT_XBGR2101010:
4784 case DRM_FORMAT_YUYV:
4785 case DRM_FORMAT_YVYU:
4786 case DRM_FORMAT_UYVY:
4787 case DRM_FORMAT_VYUY:
4788 break;
4789 default:
4790 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4791 intel_plane->base.base.id, intel_plane->base.name,
4792 fb->base.id, fb->pixel_format);
4793 return -EINVAL;
4794 }
4795
4796 return 0;
4797 }
4798
4799 static void skylake_scaler_disable(struct intel_crtc *crtc)
4800 {
4801 int i;
4802
4803 for (i = 0; i < crtc->num_scalers; i++)
4804 skl_detach_scaler(crtc, i);
4805 }
4806
4807 static void skylake_pfit_enable(struct intel_crtc *crtc)
4808 {
4809 struct drm_device *dev = crtc->base.dev;
4810 struct drm_i915_private *dev_priv = to_i915(dev);
4811 int pipe = crtc->pipe;
4812 struct intel_crtc_scaler_state *scaler_state =
4813 &crtc->config->scaler_state;
4814
4815 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4816
4817 if (crtc->config->pch_pfit.enabled) {
4818 int id;
4819
4820 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4821 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4822 return;
4823 }
4824
4825 id = scaler_state->scaler_id;
4826 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4827 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4828 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4829 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4830
4831 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4832 }
4833 }
4834
4835 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4836 {
4837 struct drm_device *dev = crtc->base.dev;
4838 struct drm_i915_private *dev_priv = to_i915(dev);
4839 int pipe = crtc->pipe;
4840
4841 if (crtc->config->pch_pfit.enabled) {
4842 /* Force use of hard-coded filter coefficients
4843 * as some pre-programmed values are broken,
4844 * e.g. x201.
4845 */
4846 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4847 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4848 PF_PIPE_SEL_IVB(pipe));
4849 else
4850 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4851 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4852 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4853 }
4854 }
4855
4856 void hsw_enable_ips(struct intel_crtc *crtc)
4857 {
4858 struct drm_device *dev = crtc->base.dev;
4859 struct drm_i915_private *dev_priv = to_i915(dev);
4860
4861 if (!crtc->config->ips_enabled)
4862 return;
4863
4864 /*
4865 * We can only enable IPS after we enable a plane and wait for a vblank
4866 * This function is called from post_plane_update, which is run after
4867 * a vblank wait.
4868 */
4869
4870 assert_plane_enabled(dev_priv, crtc->plane);
4871 if (IS_BROADWELL(dev)) {
4872 mutex_lock(&dev_priv->rps.hw_lock);
4873 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4874 mutex_unlock(&dev_priv->rps.hw_lock);
4875 /* Quoting Art Runyan: "its not safe to expect any particular
4876 * value in IPS_CTL bit 31 after enabling IPS through the
4877 * mailbox." Moreover, the mailbox may return a bogus state,
4878 * so we need to just enable it and continue on.
4879 */
4880 } else {
4881 I915_WRITE(IPS_CTL, IPS_ENABLE);
4882 /* The bit only becomes 1 in the next vblank, so this wait here
4883 * is essentially intel_wait_for_vblank. If we don't have this
4884 * and don't wait for vblanks until the end of crtc_enable, then
4885 * the HW state readout code will complain that the expected
4886 * IPS_CTL value is not the one we read. */
4887 if (intel_wait_for_register(dev_priv,
4888 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4889 50))
4890 DRM_ERROR("Timed out waiting for IPS enable\n");
4891 }
4892 }
4893
4894 void hsw_disable_ips(struct intel_crtc *crtc)
4895 {
4896 struct drm_device *dev = crtc->base.dev;
4897 struct drm_i915_private *dev_priv = to_i915(dev);
4898
4899 if (!crtc->config->ips_enabled)
4900 return;
4901
4902 assert_plane_enabled(dev_priv, crtc->plane);
4903 if (IS_BROADWELL(dev)) {
4904 mutex_lock(&dev_priv->rps.hw_lock);
4905 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4906 mutex_unlock(&dev_priv->rps.hw_lock);
4907 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4908 if (intel_wait_for_register(dev_priv,
4909 IPS_CTL, IPS_ENABLE, 0,
4910 42))
4911 DRM_ERROR("Timed out waiting for IPS disable\n");
4912 } else {
4913 I915_WRITE(IPS_CTL, 0);
4914 POSTING_READ(IPS_CTL);
4915 }
4916
4917 /* We need to wait for a vblank before we can disable the plane. */
4918 intel_wait_for_vblank(dev, crtc->pipe);
4919 }
4920
4921 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4922 {
4923 if (intel_crtc->overlay) {
4924 struct drm_device *dev = intel_crtc->base.dev;
4925 struct drm_i915_private *dev_priv = to_i915(dev);
4926
4927 mutex_lock(&dev->struct_mutex);
4928 dev_priv->mm.interruptible = false;
4929 (void) intel_overlay_switch_off(intel_crtc->overlay);
4930 dev_priv->mm.interruptible = true;
4931 mutex_unlock(&dev->struct_mutex);
4932 }
4933
4934 /* Let userspace switch the overlay on again. In most cases userspace
4935 * has to recompute where to put it anyway.
4936 */
4937 }
4938
4939 /**
4940 * intel_post_enable_primary - Perform operations after enabling primary plane
4941 * @crtc: the CRTC whose primary plane was just enabled
4942 *
4943 * Performs potentially sleeping operations that must be done after the primary
4944 * plane is enabled, such as updating FBC and IPS. Note that this may be
4945 * called due to an explicit primary plane update, or due to an implicit
4946 * re-enable that is caused when a sprite plane is updated to no longer
4947 * completely hide the primary plane.
4948 */
4949 static void
4950 intel_post_enable_primary(struct drm_crtc *crtc)
4951 {
4952 struct drm_device *dev = crtc->dev;
4953 struct drm_i915_private *dev_priv = to_i915(dev);
4954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4955 int pipe = intel_crtc->pipe;
4956
4957 /*
4958 * FIXME IPS should be fine as long as one plane is
4959 * enabled, but in practice it seems to have problems
4960 * when going from primary only to sprite only and vice
4961 * versa.
4962 */
4963 hsw_enable_ips(intel_crtc);
4964
4965 /*
4966 * Gen2 reports pipe underruns whenever all planes are disabled.
4967 * So don't enable underrun reporting before at least some planes
4968 * are enabled.
4969 * FIXME: Need to fix the logic to work when we turn off all planes
4970 * but leave the pipe running.
4971 */
4972 if (IS_GEN2(dev))
4973 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4974
4975 /* Underruns don't always raise interrupts, so check manually. */
4976 intel_check_cpu_fifo_underruns(dev_priv);
4977 intel_check_pch_fifo_underruns(dev_priv);
4978 }
4979
4980 /* FIXME move all this to pre_plane_update() with proper state tracking */
4981 static void
4982 intel_pre_disable_primary(struct drm_crtc *crtc)
4983 {
4984 struct drm_device *dev = crtc->dev;
4985 struct drm_i915_private *dev_priv = to_i915(dev);
4986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4987 int pipe = intel_crtc->pipe;
4988
4989 /*
4990 * Gen2 reports pipe underruns whenever all planes are disabled.
4991 * So diasble underrun reporting before all the planes get disabled.
4992 * FIXME: Need to fix the logic to work when we turn off all planes
4993 * but leave the pipe running.
4994 */
4995 if (IS_GEN2(dev))
4996 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4997
4998 /*
4999 * FIXME IPS should be fine as long as one plane is
5000 * enabled, but in practice it seems to have problems
5001 * when going from primary only to sprite only and vice
5002 * versa.
5003 */
5004 hsw_disable_ips(intel_crtc);
5005 }
5006
5007 /* FIXME get rid of this and use pre_plane_update */
5008 static void
5009 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5010 {
5011 struct drm_device *dev = crtc->dev;
5012 struct drm_i915_private *dev_priv = to_i915(dev);
5013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014 int pipe = intel_crtc->pipe;
5015
5016 intel_pre_disable_primary(crtc);
5017
5018 /*
5019 * Vblank time updates from the shadow to live plane control register
5020 * are blocked if the memory self-refresh mode is active at that
5021 * moment. So to make sure the plane gets truly disabled, disable
5022 * first the self-refresh mode. The self-refresh enable bit in turn
5023 * will be checked/applied by the HW only at the next frame start
5024 * event which is after the vblank start event, so we need to have a
5025 * wait-for-vblank between disabling the plane and the pipe.
5026 */
5027 if (HAS_GMCH_DISPLAY(dev)) {
5028 intel_set_memory_cxsr(dev_priv, false);
5029 dev_priv->wm.vlv.cxsr = false;
5030 intel_wait_for_vblank(dev, pipe);
5031 }
5032 }
5033
5034 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5035 {
5036 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5037 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5038 struct intel_crtc_state *pipe_config =
5039 to_intel_crtc_state(crtc->base.state);
5040 struct drm_plane *primary = crtc->base.primary;
5041 struct drm_plane_state *old_pri_state =
5042 drm_atomic_get_existing_plane_state(old_state, primary);
5043
5044 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5045
5046 crtc->wm.cxsr_allowed = true;
5047
5048 if (pipe_config->update_wm_post && pipe_config->base.active)
5049 intel_update_watermarks(&crtc->base);
5050
5051 if (old_pri_state) {
5052 struct intel_plane_state *primary_state =
5053 to_intel_plane_state(primary->state);
5054 struct intel_plane_state *old_primary_state =
5055 to_intel_plane_state(old_pri_state);
5056
5057 intel_fbc_post_update(crtc);
5058
5059 if (primary_state->base.visible &&
5060 (needs_modeset(&pipe_config->base) ||
5061 !old_primary_state->base.visible))
5062 intel_post_enable_primary(&crtc->base);
5063 }
5064 }
5065
5066 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5067 {
5068 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5069 struct drm_device *dev = crtc->base.dev;
5070 struct drm_i915_private *dev_priv = to_i915(dev);
5071 struct intel_crtc_state *pipe_config =
5072 to_intel_crtc_state(crtc->base.state);
5073 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5074 struct drm_plane *primary = crtc->base.primary;
5075 struct drm_plane_state *old_pri_state =
5076 drm_atomic_get_existing_plane_state(old_state, primary);
5077 bool modeset = needs_modeset(&pipe_config->base);
5078
5079 if (old_pri_state) {
5080 struct intel_plane_state *primary_state =
5081 to_intel_plane_state(primary->state);
5082 struct intel_plane_state *old_primary_state =
5083 to_intel_plane_state(old_pri_state);
5084
5085 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5086
5087 if (old_primary_state->base.visible &&
5088 (modeset || !primary_state->base.visible))
5089 intel_pre_disable_primary(&crtc->base);
5090 }
5091
5092 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5093 crtc->wm.cxsr_allowed = false;
5094
5095 /*
5096 * Vblank time updates from the shadow to live plane control register
5097 * are blocked if the memory self-refresh mode is active at that
5098 * moment. So to make sure the plane gets truly disabled, disable
5099 * first the self-refresh mode. The self-refresh enable bit in turn
5100 * will be checked/applied by the HW only at the next frame start
5101 * event which is after the vblank start event, so we need to have a
5102 * wait-for-vblank between disabling the plane and the pipe.
5103 */
5104 if (old_crtc_state->base.active) {
5105 intel_set_memory_cxsr(dev_priv, false);
5106 dev_priv->wm.vlv.cxsr = false;
5107 intel_wait_for_vblank(dev, crtc->pipe);
5108 }
5109 }
5110
5111 /*
5112 * IVB workaround: must disable low power watermarks for at least
5113 * one frame before enabling scaling. LP watermarks can be re-enabled
5114 * when scaling is disabled.
5115 *
5116 * WaCxSRDisabledForSpriteScaling:ivb
5117 */
5118 if (pipe_config->disable_lp_wm) {
5119 ilk_disable_lp_wm(dev);
5120 intel_wait_for_vblank(dev, crtc->pipe);
5121 }
5122
5123 /*
5124 * If we're doing a modeset, we're done. No need to do any pre-vblank
5125 * watermark programming here.
5126 */
5127 if (needs_modeset(&pipe_config->base))
5128 return;
5129
5130 /*
5131 * For platforms that support atomic watermarks, program the
5132 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5133 * will be the intermediate values that are safe for both pre- and
5134 * post- vblank; when vblank happens, the 'active' values will be set
5135 * to the final 'target' values and we'll do this again to get the
5136 * optimal watermarks. For gen9+ platforms, the values we program here
5137 * will be the final target values which will get automatically latched
5138 * at vblank time; no further programming will be necessary.
5139 *
5140 * If a platform hasn't been transitioned to atomic watermarks yet,
5141 * we'll continue to update watermarks the old way, if flags tell
5142 * us to.
5143 */
5144 if (dev_priv->display.initial_watermarks != NULL)
5145 dev_priv->display.initial_watermarks(pipe_config);
5146 else if (pipe_config->update_wm_pre)
5147 intel_update_watermarks(&crtc->base);
5148 }
5149
5150 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5151 {
5152 struct drm_device *dev = crtc->dev;
5153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5154 struct drm_plane *p;
5155 int pipe = intel_crtc->pipe;
5156
5157 intel_crtc_dpms_overlay_disable(intel_crtc);
5158
5159 drm_for_each_plane_mask(p, dev, plane_mask)
5160 to_intel_plane(p)->disable_plane(p, crtc);
5161
5162 /*
5163 * FIXME: Once we grow proper nuclear flip support out of this we need
5164 * to compute the mask of flip planes precisely. For the time being
5165 * consider this a flip to a NULL plane.
5166 */
5167 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5168 }
5169
5170 static void ironlake_crtc_enable(struct drm_crtc *crtc)
5171 {
5172 struct drm_device *dev = crtc->dev;
5173 struct drm_i915_private *dev_priv = to_i915(dev);
5174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175 struct intel_encoder *encoder;
5176 int pipe = intel_crtc->pipe;
5177 struct intel_crtc_state *pipe_config =
5178 to_intel_crtc_state(crtc->state);
5179
5180 if (WARN_ON(intel_crtc->active))
5181 return;
5182
5183 /*
5184 * Sometimes spurious CPU pipe underruns happen during FDI
5185 * training, at least with VGA+HDMI cloning. Suppress them.
5186 *
5187 * On ILK we get an occasional spurious CPU pipe underruns
5188 * between eDP port A enable and vdd enable. Also PCH port
5189 * enable seems to result in the occasional CPU pipe underrun.
5190 *
5191 * Spurious PCH underruns also occur during PCH enabling.
5192 */
5193 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5194 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5195 if (intel_crtc->config->has_pch_encoder)
5196 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5197
5198 if (intel_crtc->config->has_pch_encoder)
5199 intel_prepare_shared_dpll(intel_crtc);
5200
5201 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5202 intel_dp_set_m_n(intel_crtc, M1_N1);
5203
5204 intel_set_pipe_timings(intel_crtc);
5205 intel_set_pipe_src_size(intel_crtc);
5206
5207 if (intel_crtc->config->has_pch_encoder) {
5208 intel_cpu_transcoder_set_m_n(intel_crtc,
5209 &intel_crtc->config->fdi_m_n, NULL);
5210 }
5211
5212 ironlake_set_pipeconf(crtc);
5213
5214 intel_crtc->active = true;
5215
5216 for_each_encoder_on_crtc(dev, crtc, encoder)
5217 if (encoder->pre_enable)
5218 encoder->pre_enable(encoder);
5219
5220 if (intel_crtc->config->has_pch_encoder) {
5221 /* Note: FDI PLL enabling _must_ be done before we enable the
5222 * cpu pipes, hence this is separate from all the other fdi/pch
5223 * enabling. */
5224 ironlake_fdi_pll_enable(intel_crtc);
5225 } else {
5226 assert_fdi_tx_disabled(dev_priv, pipe);
5227 assert_fdi_rx_disabled(dev_priv, pipe);
5228 }
5229
5230 ironlake_pfit_enable(intel_crtc);
5231
5232 /*
5233 * On ILK+ LUT must be loaded before the pipe is running but with
5234 * clocks enabled
5235 */
5236 intel_color_load_luts(&pipe_config->base);
5237
5238 if (dev_priv->display.initial_watermarks != NULL)
5239 dev_priv->display.initial_watermarks(intel_crtc->config);
5240 intel_enable_pipe(intel_crtc);
5241
5242 if (intel_crtc->config->has_pch_encoder)
5243 ironlake_pch_enable(crtc);
5244
5245 assert_vblank_disabled(crtc);
5246 drm_crtc_vblank_on(crtc);
5247
5248 for_each_encoder_on_crtc(dev, crtc, encoder)
5249 encoder->enable(encoder);
5250
5251 if (HAS_PCH_CPT(dev))
5252 cpt_verify_modeset(dev, intel_crtc->pipe);
5253
5254 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5255 if (intel_crtc->config->has_pch_encoder)
5256 intel_wait_for_vblank(dev, pipe);
5257 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5258 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5259 }
5260
5261 /* IPS only exists on ULT machines and is tied to pipe A. */
5262 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5263 {
5264 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5265 }
5266
5267 static void haswell_crtc_enable(struct drm_crtc *crtc)
5268 {
5269 struct drm_device *dev = crtc->dev;
5270 struct drm_i915_private *dev_priv = to_i915(dev);
5271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5272 struct intel_encoder *encoder;
5273 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5274 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5275 struct intel_crtc_state *pipe_config =
5276 to_intel_crtc_state(crtc->state);
5277
5278 if (WARN_ON(intel_crtc->active))
5279 return;
5280
5281 if (intel_crtc->config->has_pch_encoder)
5282 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5283 false);
5284
5285 for_each_encoder_on_crtc(dev, crtc, encoder)
5286 if (encoder->pre_pll_enable)
5287 encoder->pre_pll_enable(encoder);
5288
5289 if (intel_crtc->config->shared_dpll)
5290 intel_enable_shared_dpll(intel_crtc);
5291
5292 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5293 intel_dp_set_m_n(intel_crtc, M1_N1);
5294
5295 if (!transcoder_is_dsi(cpu_transcoder))
5296 intel_set_pipe_timings(intel_crtc);
5297
5298 intel_set_pipe_src_size(intel_crtc);
5299
5300 if (cpu_transcoder != TRANSCODER_EDP &&
5301 !transcoder_is_dsi(cpu_transcoder)) {
5302 I915_WRITE(PIPE_MULT(cpu_transcoder),
5303 intel_crtc->config->pixel_multiplier - 1);
5304 }
5305
5306 if (intel_crtc->config->has_pch_encoder) {
5307 intel_cpu_transcoder_set_m_n(intel_crtc,
5308 &intel_crtc->config->fdi_m_n, NULL);
5309 }
5310
5311 if (!transcoder_is_dsi(cpu_transcoder))
5312 haswell_set_pipeconf(crtc);
5313
5314 haswell_set_pipemisc(crtc);
5315
5316 intel_color_set_csc(&pipe_config->base);
5317
5318 intel_crtc->active = true;
5319
5320 if (intel_crtc->config->has_pch_encoder)
5321 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5322 else
5323 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5324
5325 for_each_encoder_on_crtc(dev, crtc, encoder) {
5326 if (encoder->pre_enable)
5327 encoder->pre_enable(encoder);
5328 }
5329
5330 if (intel_crtc->config->has_pch_encoder)
5331 dev_priv->display.fdi_link_train(crtc);
5332
5333 if (!transcoder_is_dsi(cpu_transcoder))
5334 intel_ddi_enable_pipe_clock(intel_crtc);
5335
5336 if (INTEL_INFO(dev)->gen >= 9)
5337 skylake_pfit_enable(intel_crtc);
5338 else
5339 ironlake_pfit_enable(intel_crtc);
5340
5341 /*
5342 * On ILK+ LUT must be loaded before the pipe is running but with
5343 * clocks enabled
5344 */
5345 intel_color_load_luts(&pipe_config->base);
5346
5347 intel_ddi_set_pipe_settings(crtc);
5348 if (!transcoder_is_dsi(cpu_transcoder))
5349 intel_ddi_enable_transcoder_func(crtc);
5350
5351 if (dev_priv->display.initial_watermarks != NULL)
5352 dev_priv->display.initial_watermarks(pipe_config);
5353 else
5354 intel_update_watermarks(crtc);
5355
5356 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5357 if (!transcoder_is_dsi(cpu_transcoder))
5358 intel_enable_pipe(intel_crtc);
5359
5360 if (intel_crtc->config->has_pch_encoder)
5361 lpt_pch_enable(crtc);
5362
5363 if (intel_crtc->config->dp_encoder_is_mst)
5364 intel_ddi_set_vc_payload_alloc(crtc, true);
5365
5366 assert_vblank_disabled(crtc);
5367 drm_crtc_vblank_on(crtc);
5368
5369 for_each_encoder_on_crtc(dev, crtc, encoder) {
5370 encoder->enable(encoder);
5371 intel_opregion_notify_encoder(encoder, true);
5372 }
5373
5374 if (intel_crtc->config->has_pch_encoder) {
5375 intel_wait_for_vblank(dev, pipe);
5376 intel_wait_for_vblank(dev, pipe);
5377 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5378 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5379 true);
5380 }
5381
5382 /* If we change the relative order between pipe/planes enabling, we need
5383 * to change the workaround. */
5384 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5385 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5386 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5387 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5388 }
5389 }
5390
5391 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5392 {
5393 struct drm_device *dev = crtc->base.dev;
5394 struct drm_i915_private *dev_priv = to_i915(dev);
5395 int pipe = crtc->pipe;
5396
5397 /* To avoid upsetting the power well on haswell only disable the pfit if
5398 * it's in use. The hw state code will make sure we get this right. */
5399 if (force || crtc->config->pch_pfit.enabled) {
5400 I915_WRITE(PF_CTL(pipe), 0);
5401 I915_WRITE(PF_WIN_POS(pipe), 0);
5402 I915_WRITE(PF_WIN_SZ(pipe), 0);
5403 }
5404 }
5405
5406 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5407 {
5408 struct drm_device *dev = crtc->dev;
5409 struct drm_i915_private *dev_priv = to_i915(dev);
5410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411 struct intel_encoder *encoder;
5412 int pipe = intel_crtc->pipe;
5413
5414 /*
5415 * Sometimes spurious CPU pipe underruns happen when the
5416 * pipe is already disabled, but FDI RX/TX is still enabled.
5417 * Happens at least with VGA+HDMI cloning. Suppress them.
5418 */
5419 if (intel_crtc->config->has_pch_encoder) {
5420 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5421 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5422 }
5423
5424 for_each_encoder_on_crtc(dev, crtc, encoder)
5425 encoder->disable(encoder);
5426
5427 drm_crtc_vblank_off(crtc);
5428 assert_vblank_disabled(crtc);
5429
5430 intel_disable_pipe(intel_crtc);
5431
5432 ironlake_pfit_disable(intel_crtc, false);
5433
5434 if (intel_crtc->config->has_pch_encoder)
5435 ironlake_fdi_disable(crtc);
5436
5437 for_each_encoder_on_crtc(dev, crtc, encoder)
5438 if (encoder->post_disable)
5439 encoder->post_disable(encoder);
5440
5441 if (intel_crtc->config->has_pch_encoder) {
5442 ironlake_disable_pch_transcoder(dev_priv, pipe);
5443
5444 if (HAS_PCH_CPT(dev)) {
5445 i915_reg_t reg;
5446 u32 temp;
5447
5448 /* disable TRANS_DP_CTL */
5449 reg = TRANS_DP_CTL(pipe);
5450 temp = I915_READ(reg);
5451 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5452 TRANS_DP_PORT_SEL_MASK);
5453 temp |= TRANS_DP_PORT_SEL_NONE;
5454 I915_WRITE(reg, temp);
5455
5456 /* disable DPLL_SEL */
5457 temp = I915_READ(PCH_DPLL_SEL);
5458 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5459 I915_WRITE(PCH_DPLL_SEL, temp);
5460 }
5461
5462 ironlake_fdi_pll_disable(intel_crtc);
5463 }
5464
5465 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5466 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5467 }
5468
5469 static void haswell_crtc_disable(struct drm_crtc *crtc)
5470 {
5471 struct drm_device *dev = crtc->dev;
5472 struct drm_i915_private *dev_priv = to_i915(dev);
5473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5474 struct intel_encoder *encoder;
5475 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5476
5477 if (intel_crtc->config->has_pch_encoder)
5478 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5479 false);
5480
5481 for_each_encoder_on_crtc(dev, crtc, encoder) {
5482 intel_opregion_notify_encoder(encoder, false);
5483 encoder->disable(encoder);
5484 }
5485
5486 drm_crtc_vblank_off(crtc);
5487 assert_vblank_disabled(crtc);
5488
5489 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5490 if (!transcoder_is_dsi(cpu_transcoder))
5491 intel_disable_pipe(intel_crtc);
5492
5493 if (intel_crtc->config->dp_encoder_is_mst)
5494 intel_ddi_set_vc_payload_alloc(crtc, false);
5495
5496 if (!transcoder_is_dsi(cpu_transcoder))
5497 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5498
5499 if (INTEL_INFO(dev)->gen >= 9)
5500 skylake_scaler_disable(intel_crtc);
5501 else
5502 ironlake_pfit_disable(intel_crtc, false);
5503
5504 if (!transcoder_is_dsi(cpu_transcoder))
5505 intel_ddi_disable_pipe_clock(intel_crtc);
5506
5507 for_each_encoder_on_crtc(dev, crtc, encoder)
5508 if (encoder->post_disable)
5509 encoder->post_disable(encoder);
5510
5511 if (intel_crtc->config->has_pch_encoder) {
5512 lpt_disable_pch_transcoder(dev_priv);
5513 lpt_disable_iclkip(dev_priv);
5514 intel_ddi_fdi_disable(crtc);
5515
5516 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5517 true);
5518 }
5519 }
5520
5521 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5522 {
5523 struct drm_device *dev = crtc->base.dev;
5524 struct drm_i915_private *dev_priv = to_i915(dev);
5525 struct intel_crtc_state *pipe_config = crtc->config;
5526
5527 if (!pipe_config->gmch_pfit.control)
5528 return;
5529
5530 /*
5531 * The panel fitter should only be adjusted whilst the pipe is disabled,
5532 * according to register description and PRM.
5533 */
5534 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5535 assert_pipe_disabled(dev_priv, crtc->pipe);
5536
5537 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5538 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5539
5540 /* Border color in case we don't scale up to the full screen. Black by
5541 * default, change to something else for debugging. */
5542 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5543 }
5544
5545 static enum intel_display_power_domain port_to_power_domain(enum port port)
5546 {
5547 switch (port) {
5548 case PORT_A:
5549 return POWER_DOMAIN_PORT_DDI_A_LANES;
5550 case PORT_B:
5551 return POWER_DOMAIN_PORT_DDI_B_LANES;
5552 case PORT_C:
5553 return POWER_DOMAIN_PORT_DDI_C_LANES;
5554 case PORT_D:
5555 return POWER_DOMAIN_PORT_DDI_D_LANES;
5556 case PORT_E:
5557 return POWER_DOMAIN_PORT_DDI_E_LANES;
5558 default:
5559 MISSING_CASE(port);
5560 return POWER_DOMAIN_PORT_OTHER;
5561 }
5562 }
5563
5564 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5565 {
5566 switch (port) {
5567 case PORT_A:
5568 return POWER_DOMAIN_AUX_A;
5569 case PORT_B:
5570 return POWER_DOMAIN_AUX_B;
5571 case PORT_C:
5572 return POWER_DOMAIN_AUX_C;
5573 case PORT_D:
5574 return POWER_DOMAIN_AUX_D;
5575 case PORT_E:
5576 /* FIXME: Check VBT for actual wiring of PORT E */
5577 return POWER_DOMAIN_AUX_D;
5578 default:
5579 MISSING_CASE(port);
5580 return POWER_DOMAIN_AUX_A;
5581 }
5582 }
5583
5584 enum intel_display_power_domain
5585 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5586 {
5587 struct drm_device *dev = intel_encoder->base.dev;
5588 struct intel_digital_port *intel_dig_port;
5589
5590 switch (intel_encoder->type) {
5591 case INTEL_OUTPUT_UNKNOWN:
5592 /* Only DDI platforms should ever use this output type */
5593 WARN_ON_ONCE(!HAS_DDI(dev));
5594 case INTEL_OUTPUT_DP:
5595 case INTEL_OUTPUT_HDMI:
5596 case INTEL_OUTPUT_EDP:
5597 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5598 return port_to_power_domain(intel_dig_port->port);
5599 case INTEL_OUTPUT_DP_MST:
5600 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5601 return port_to_power_domain(intel_dig_port->port);
5602 case INTEL_OUTPUT_ANALOG:
5603 return POWER_DOMAIN_PORT_CRT;
5604 case INTEL_OUTPUT_DSI:
5605 return POWER_DOMAIN_PORT_DSI;
5606 default:
5607 return POWER_DOMAIN_PORT_OTHER;
5608 }
5609 }
5610
5611 enum intel_display_power_domain
5612 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5613 {
5614 struct drm_device *dev = intel_encoder->base.dev;
5615 struct intel_digital_port *intel_dig_port;
5616
5617 switch (intel_encoder->type) {
5618 case INTEL_OUTPUT_UNKNOWN:
5619 case INTEL_OUTPUT_HDMI:
5620 /*
5621 * Only DDI platforms should ever use these output types.
5622 * We can get here after the HDMI detect code has already set
5623 * the type of the shared encoder. Since we can't be sure
5624 * what's the status of the given connectors, play safe and
5625 * run the DP detection too.
5626 */
5627 WARN_ON_ONCE(!HAS_DDI(dev));
5628 case INTEL_OUTPUT_DP:
5629 case INTEL_OUTPUT_EDP:
5630 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5631 return port_to_aux_power_domain(intel_dig_port->port);
5632 case INTEL_OUTPUT_DP_MST:
5633 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5634 return port_to_aux_power_domain(intel_dig_port->port);
5635 default:
5636 MISSING_CASE(intel_encoder->type);
5637 return POWER_DOMAIN_AUX_A;
5638 }
5639 }
5640
5641 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5642 struct intel_crtc_state *crtc_state)
5643 {
5644 struct drm_device *dev = crtc->dev;
5645 struct drm_encoder *encoder;
5646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5647 enum pipe pipe = intel_crtc->pipe;
5648 unsigned long mask;
5649 enum transcoder transcoder = crtc_state->cpu_transcoder;
5650
5651 if (!crtc_state->base.active)
5652 return 0;
5653
5654 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5655 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5656 if (crtc_state->pch_pfit.enabled ||
5657 crtc_state->pch_pfit.force_thru)
5658 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5659
5660 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5661 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5662
5663 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5664 }
5665
5666 if (crtc_state->shared_dpll)
5667 mask |= BIT(POWER_DOMAIN_PLLS);
5668
5669 return mask;
5670 }
5671
5672 static unsigned long
5673 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5674 struct intel_crtc_state *crtc_state)
5675 {
5676 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5678 enum intel_display_power_domain domain;
5679 unsigned long domains, new_domains, old_domains;
5680
5681 old_domains = intel_crtc->enabled_power_domains;
5682 intel_crtc->enabled_power_domains = new_domains =
5683 get_crtc_power_domains(crtc, crtc_state);
5684
5685 domains = new_domains & ~old_domains;
5686
5687 for_each_power_domain(domain, domains)
5688 intel_display_power_get(dev_priv, domain);
5689
5690 return old_domains & ~new_domains;
5691 }
5692
5693 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5694 unsigned long domains)
5695 {
5696 enum intel_display_power_domain domain;
5697
5698 for_each_power_domain(domain, domains)
5699 intel_display_power_put(dev_priv, domain);
5700 }
5701
5702 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5703 {
5704 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5705
5706 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5707 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5708 return max_cdclk_freq;
5709 else if (IS_CHERRYVIEW(dev_priv))
5710 return max_cdclk_freq*95/100;
5711 else if (INTEL_INFO(dev_priv)->gen < 4)
5712 return 2*max_cdclk_freq*90/100;
5713 else
5714 return max_cdclk_freq*90/100;
5715 }
5716
5717 static int skl_calc_cdclk(int max_pixclk, int vco);
5718
5719 static void intel_update_max_cdclk(struct drm_device *dev)
5720 {
5721 struct drm_i915_private *dev_priv = to_i915(dev);
5722
5723 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5724 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5725 int max_cdclk, vco;
5726
5727 vco = dev_priv->skl_preferred_vco_freq;
5728 WARN_ON(vco != 8100000 && vco != 8640000);
5729
5730 /*
5731 * Use the lower (vco 8640) cdclk values as a
5732 * first guess. skl_calc_cdclk() will correct it
5733 * if the preferred vco is 8100 instead.
5734 */
5735 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5736 max_cdclk = 617143;
5737 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5738 max_cdclk = 540000;
5739 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5740 max_cdclk = 432000;
5741 else
5742 max_cdclk = 308571;
5743
5744 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5745 } else if (IS_BROXTON(dev)) {
5746 dev_priv->max_cdclk_freq = 624000;
5747 } else if (IS_BROADWELL(dev)) {
5748 /*
5749 * FIXME with extra cooling we can allow
5750 * 540 MHz for ULX and 675 Mhz for ULT.
5751 * How can we know if extra cooling is
5752 * available? PCI ID, VTB, something else?
5753 */
5754 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5755 dev_priv->max_cdclk_freq = 450000;
5756 else if (IS_BDW_ULX(dev))
5757 dev_priv->max_cdclk_freq = 450000;
5758 else if (IS_BDW_ULT(dev))
5759 dev_priv->max_cdclk_freq = 540000;
5760 else
5761 dev_priv->max_cdclk_freq = 675000;
5762 } else if (IS_CHERRYVIEW(dev)) {
5763 dev_priv->max_cdclk_freq = 320000;
5764 } else if (IS_VALLEYVIEW(dev)) {
5765 dev_priv->max_cdclk_freq = 400000;
5766 } else {
5767 /* otherwise assume cdclk is fixed */
5768 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5769 }
5770
5771 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5772
5773 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5774 dev_priv->max_cdclk_freq);
5775
5776 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5777 dev_priv->max_dotclk_freq);
5778 }
5779
5780 static void intel_update_cdclk(struct drm_device *dev)
5781 {
5782 struct drm_i915_private *dev_priv = to_i915(dev);
5783
5784 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5785
5786 if (INTEL_GEN(dev_priv) >= 9)
5787 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5788 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5789 dev_priv->cdclk_pll.ref);
5790 else
5791 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5792 dev_priv->cdclk_freq);
5793
5794 /*
5795 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5796 * Programmng [sic] note: bit[9:2] should be programmed to the number
5797 * of cdclk that generates 4MHz reference clock freq which is used to
5798 * generate GMBus clock. This will vary with the cdclk freq.
5799 */
5800 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5801 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5802 }
5803
5804 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5805 static int skl_cdclk_decimal(int cdclk)
5806 {
5807 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5808 }
5809
5810 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5811 {
5812 int ratio;
5813
5814 if (cdclk == dev_priv->cdclk_pll.ref)
5815 return 0;
5816
5817 switch (cdclk) {
5818 default:
5819 MISSING_CASE(cdclk);
5820 case 144000:
5821 case 288000:
5822 case 384000:
5823 case 576000:
5824 ratio = 60;
5825 break;
5826 case 624000:
5827 ratio = 65;
5828 break;
5829 }
5830
5831 return dev_priv->cdclk_pll.ref * ratio;
5832 }
5833
5834 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5835 {
5836 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5837
5838 /* Timeout 200us */
5839 if (intel_wait_for_register(dev_priv,
5840 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5841 1))
5842 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5843
5844 dev_priv->cdclk_pll.vco = 0;
5845 }
5846
5847 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5848 {
5849 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5850 u32 val;
5851
5852 val = I915_READ(BXT_DE_PLL_CTL);
5853 val &= ~BXT_DE_PLL_RATIO_MASK;
5854 val |= BXT_DE_PLL_RATIO(ratio);
5855 I915_WRITE(BXT_DE_PLL_CTL, val);
5856
5857 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5858
5859 /* Timeout 200us */
5860 if (intel_wait_for_register(dev_priv,
5861 BXT_DE_PLL_ENABLE,
5862 BXT_DE_PLL_LOCK,
5863 BXT_DE_PLL_LOCK,
5864 1))
5865 DRM_ERROR("timeout waiting for DE PLL lock\n");
5866
5867 dev_priv->cdclk_pll.vco = vco;
5868 }
5869
5870 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5871 {
5872 u32 val, divider;
5873 int vco, ret;
5874
5875 vco = bxt_de_pll_vco(dev_priv, cdclk);
5876
5877 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5878
5879 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5880 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5881 case 8:
5882 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5883 break;
5884 case 4:
5885 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5886 break;
5887 case 3:
5888 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5889 break;
5890 case 2:
5891 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5892 break;
5893 default:
5894 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5895 WARN_ON(vco != 0);
5896
5897 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5898 break;
5899 }
5900
5901 /* Inform power controller of upcoming frequency change */
5902 mutex_lock(&dev_priv->rps.hw_lock);
5903 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5904 0x80000000);
5905 mutex_unlock(&dev_priv->rps.hw_lock);
5906
5907 if (ret) {
5908 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5909 ret, cdclk);
5910 return;
5911 }
5912
5913 if (dev_priv->cdclk_pll.vco != 0 &&
5914 dev_priv->cdclk_pll.vco != vco)
5915 bxt_de_pll_disable(dev_priv);
5916
5917 if (dev_priv->cdclk_pll.vco != vco)
5918 bxt_de_pll_enable(dev_priv, vco);
5919
5920 val = divider | skl_cdclk_decimal(cdclk);
5921 /*
5922 * FIXME if only the cd2x divider needs changing, it could be done
5923 * without shutting off the pipe (if only one pipe is active).
5924 */
5925 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5926 /*
5927 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5928 * enable otherwise.
5929 */
5930 if (cdclk >= 500000)
5931 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5932 I915_WRITE(CDCLK_CTL, val);
5933
5934 mutex_lock(&dev_priv->rps.hw_lock);
5935 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5936 DIV_ROUND_UP(cdclk, 25000));
5937 mutex_unlock(&dev_priv->rps.hw_lock);
5938
5939 if (ret) {
5940 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5941 ret, cdclk);
5942 return;
5943 }
5944
5945 intel_update_cdclk(&dev_priv->drm);
5946 }
5947
5948 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5949 {
5950 u32 cdctl, expected;
5951
5952 intel_update_cdclk(&dev_priv->drm);
5953
5954 if (dev_priv->cdclk_pll.vco == 0 ||
5955 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5956 goto sanitize;
5957
5958 /* DPLL okay; verify the cdclock
5959 *
5960 * Some BIOS versions leave an incorrect decimal frequency value and
5961 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5962 * so sanitize this register.
5963 */
5964 cdctl = I915_READ(CDCLK_CTL);
5965 /*
5966 * Let's ignore the pipe field, since BIOS could have configured the
5967 * dividers both synching to an active pipe, or asynchronously
5968 * (PIPE_NONE).
5969 */
5970 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5971
5972 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5973 skl_cdclk_decimal(dev_priv->cdclk_freq);
5974 /*
5975 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5976 * enable otherwise.
5977 */
5978 if (dev_priv->cdclk_freq >= 500000)
5979 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5980
5981 if (cdctl == expected)
5982 /* All well; nothing to sanitize */
5983 return;
5984
5985 sanitize:
5986 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5987
5988 /* force cdclk programming */
5989 dev_priv->cdclk_freq = 0;
5990
5991 /* force full PLL disable + enable */
5992 dev_priv->cdclk_pll.vco = -1;
5993 }
5994
5995 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5996 {
5997 bxt_sanitize_cdclk(dev_priv);
5998
5999 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6000 return;
6001
6002 /*
6003 * FIXME:
6004 * - The initial CDCLK needs to be read from VBT.
6005 * Need to make this change after VBT has changes for BXT.
6006 */
6007 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6008 }
6009
6010 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6011 {
6012 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6013 }
6014
6015 static int skl_calc_cdclk(int max_pixclk, int vco)
6016 {
6017 if (vco == 8640000) {
6018 if (max_pixclk > 540000)
6019 return 617143;
6020 else if (max_pixclk > 432000)
6021 return 540000;
6022 else if (max_pixclk > 308571)
6023 return 432000;
6024 else
6025 return 308571;
6026 } else {
6027 if (max_pixclk > 540000)
6028 return 675000;
6029 else if (max_pixclk > 450000)
6030 return 540000;
6031 else if (max_pixclk > 337500)
6032 return 450000;
6033 else
6034 return 337500;
6035 }
6036 }
6037
6038 static void
6039 skl_dpll0_update(struct drm_i915_private *dev_priv)
6040 {
6041 u32 val;
6042
6043 dev_priv->cdclk_pll.ref = 24000;
6044 dev_priv->cdclk_pll.vco = 0;
6045
6046 val = I915_READ(LCPLL1_CTL);
6047 if ((val & LCPLL_PLL_ENABLE) == 0)
6048 return;
6049
6050 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6051 return;
6052
6053 val = I915_READ(DPLL_CTRL1);
6054
6055 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6056 DPLL_CTRL1_SSC(SKL_DPLL0) |
6057 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6058 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6059 return;
6060
6061 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6062 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6063 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6064 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6065 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6066 dev_priv->cdclk_pll.vco = 8100000;
6067 break;
6068 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6069 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6070 dev_priv->cdclk_pll.vco = 8640000;
6071 break;
6072 default:
6073 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6074 break;
6075 }
6076 }
6077
6078 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6079 {
6080 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6081
6082 dev_priv->skl_preferred_vco_freq = vco;
6083
6084 if (changed)
6085 intel_update_max_cdclk(&dev_priv->drm);
6086 }
6087
6088 static void
6089 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6090 {
6091 int min_cdclk = skl_calc_cdclk(0, vco);
6092 u32 val;
6093
6094 WARN_ON(vco != 8100000 && vco != 8640000);
6095
6096 /* select the minimum CDCLK before enabling DPLL 0 */
6097 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6098 I915_WRITE(CDCLK_CTL, val);
6099 POSTING_READ(CDCLK_CTL);
6100
6101 /*
6102 * We always enable DPLL0 with the lowest link rate possible, but still
6103 * taking into account the VCO required to operate the eDP panel at the
6104 * desired frequency. The usual DP link rates operate with a VCO of
6105 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6106 * The modeset code is responsible for the selection of the exact link
6107 * rate later on, with the constraint of choosing a frequency that
6108 * works with vco.
6109 */
6110 val = I915_READ(DPLL_CTRL1);
6111
6112 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6113 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6114 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6115 if (vco == 8640000)
6116 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6117 SKL_DPLL0);
6118 else
6119 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6120 SKL_DPLL0);
6121
6122 I915_WRITE(DPLL_CTRL1, val);
6123 POSTING_READ(DPLL_CTRL1);
6124
6125 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6126
6127 if (intel_wait_for_register(dev_priv,
6128 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6129 5))
6130 DRM_ERROR("DPLL0 not locked\n");
6131
6132 dev_priv->cdclk_pll.vco = vco;
6133
6134 /* We'll want to keep using the current vco from now on. */
6135 skl_set_preferred_cdclk_vco(dev_priv, vco);
6136 }
6137
6138 static void
6139 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6140 {
6141 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6142 if (intel_wait_for_register(dev_priv,
6143 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6144 1))
6145 DRM_ERROR("Couldn't disable DPLL0\n");
6146
6147 dev_priv->cdclk_pll.vco = 0;
6148 }
6149
6150 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6151 {
6152 int ret;
6153 u32 val;
6154
6155 /* inform PCU we want to change CDCLK */
6156 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6157 mutex_lock(&dev_priv->rps.hw_lock);
6158 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6159 mutex_unlock(&dev_priv->rps.hw_lock);
6160
6161 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6162 }
6163
6164 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6165 {
6166 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6167 }
6168
6169 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6170 {
6171 struct drm_device *dev = &dev_priv->drm;
6172 u32 freq_select, pcu_ack;
6173
6174 WARN_ON((cdclk == 24000) != (vco == 0));
6175
6176 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6177
6178 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6179 DRM_ERROR("failed to inform PCU about cdclk change\n");
6180 return;
6181 }
6182
6183 /* set CDCLK_CTL */
6184 switch (cdclk) {
6185 case 450000:
6186 case 432000:
6187 freq_select = CDCLK_FREQ_450_432;
6188 pcu_ack = 1;
6189 break;
6190 case 540000:
6191 freq_select = CDCLK_FREQ_540;
6192 pcu_ack = 2;
6193 break;
6194 case 308571:
6195 case 337500:
6196 default:
6197 freq_select = CDCLK_FREQ_337_308;
6198 pcu_ack = 0;
6199 break;
6200 case 617143:
6201 case 675000:
6202 freq_select = CDCLK_FREQ_675_617;
6203 pcu_ack = 3;
6204 break;
6205 }
6206
6207 if (dev_priv->cdclk_pll.vco != 0 &&
6208 dev_priv->cdclk_pll.vco != vco)
6209 skl_dpll0_disable(dev_priv);
6210
6211 if (dev_priv->cdclk_pll.vco != vco)
6212 skl_dpll0_enable(dev_priv, vco);
6213
6214 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6215 POSTING_READ(CDCLK_CTL);
6216
6217 /* inform PCU of the change */
6218 mutex_lock(&dev_priv->rps.hw_lock);
6219 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6220 mutex_unlock(&dev_priv->rps.hw_lock);
6221
6222 intel_update_cdclk(dev);
6223 }
6224
6225 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6226
6227 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6228 {
6229 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6230 }
6231
6232 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6233 {
6234 int cdclk, vco;
6235
6236 skl_sanitize_cdclk(dev_priv);
6237
6238 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6239 /*
6240 * Use the current vco as our initial
6241 * guess as to what the preferred vco is.
6242 */
6243 if (dev_priv->skl_preferred_vco_freq == 0)
6244 skl_set_preferred_cdclk_vco(dev_priv,
6245 dev_priv->cdclk_pll.vco);
6246 return;
6247 }
6248
6249 vco = dev_priv->skl_preferred_vco_freq;
6250 if (vco == 0)
6251 vco = 8100000;
6252 cdclk = skl_calc_cdclk(0, vco);
6253
6254 skl_set_cdclk(dev_priv, cdclk, vco);
6255 }
6256
6257 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6258 {
6259 uint32_t cdctl, expected;
6260
6261 /*
6262 * check if the pre-os intialized the display
6263 * There is SWF18 scratchpad register defined which is set by the
6264 * pre-os which can be used by the OS drivers to check the status
6265 */
6266 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6267 goto sanitize;
6268
6269 intel_update_cdclk(&dev_priv->drm);
6270 /* Is PLL enabled and locked ? */
6271 if (dev_priv->cdclk_pll.vco == 0 ||
6272 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6273 goto sanitize;
6274
6275 /* DPLL okay; verify the cdclock
6276 *
6277 * Noticed in some instances that the freq selection is correct but
6278 * decimal part is programmed wrong from BIOS where pre-os does not
6279 * enable display. Verify the same as well.
6280 */
6281 cdctl = I915_READ(CDCLK_CTL);
6282 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6283 skl_cdclk_decimal(dev_priv->cdclk_freq);
6284 if (cdctl == expected)
6285 /* All well; nothing to sanitize */
6286 return;
6287
6288 sanitize:
6289 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6290
6291 /* force cdclk programming */
6292 dev_priv->cdclk_freq = 0;
6293 /* force full PLL disable + enable */
6294 dev_priv->cdclk_pll.vco = -1;
6295 }
6296
6297 /* Adjust CDclk dividers to allow high res or save power if possible */
6298 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6299 {
6300 struct drm_i915_private *dev_priv = to_i915(dev);
6301 u32 val, cmd;
6302
6303 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6304 != dev_priv->cdclk_freq);
6305
6306 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6307 cmd = 2;
6308 else if (cdclk == 266667)
6309 cmd = 1;
6310 else
6311 cmd = 0;
6312
6313 mutex_lock(&dev_priv->rps.hw_lock);
6314 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6315 val &= ~DSPFREQGUAR_MASK;
6316 val |= (cmd << DSPFREQGUAR_SHIFT);
6317 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6318 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6319 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6320 50)) {
6321 DRM_ERROR("timed out waiting for CDclk change\n");
6322 }
6323 mutex_unlock(&dev_priv->rps.hw_lock);
6324
6325 mutex_lock(&dev_priv->sb_lock);
6326
6327 if (cdclk == 400000) {
6328 u32 divider;
6329
6330 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6331
6332 /* adjust cdclk divider */
6333 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6334 val &= ~CCK_FREQUENCY_VALUES;
6335 val |= divider;
6336 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6337
6338 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6339 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6340 50))
6341 DRM_ERROR("timed out waiting for CDclk change\n");
6342 }
6343
6344 /* adjust self-refresh exit latency value */
6345 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6346 val &= ~0x7f;
6347
6348 /*
6349 * For high bandwidth configs, we set a higher latency in the bunit
6350 * so that the core display fetch happens in time to avoid underruns.
6351 */
6352 if (cdclk == 400000)
6353 val |= 4500 / 250; /* 4.5 usec */
6354 else
6355 val |= 3000 / 250; /* 3.0 usec */
6356 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6357
6358 mutex_unlock(&dev_priv->sb_lock);
6359
6360 intel_update_cdclk(dev);
6361 }
6362
6363 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6364 {
6365 struct drm_i915_private *dev_priv = to_i915(dev);
6366 u32 val, cmd;
6367
6368 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6369 != dev_priv->cdclk_freq);
6370
6371 switch (cdclk) {
6372 case 333333:
6373 case 320000:
6374 case 266667:
6375 case 200000:
6376 break;
6377 default:
6378 MISSING_CASE(cdclk);
6379 return;
6380 }
6381
6382 /*
6383 * Specs are full of misinformation, but testing on actual
6384 * hardware has shown that we just need to write the desired
6385 * CCK divider into the Punit register.
6386 */
6387 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6388
6389 mutex_lock(&dev_priv->rps.hw_lock);
6390 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6391 val &= ~DSPFREQGUAR_MASK_CHV;
6392 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6393 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6394 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6395 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6396 50)) {
6397 DRM_ERROR("timed out waiting for CDclk change\n");
6398 }
6399 mutex_unlock(&dev_priv->rps.hw_lock);
6400
6401 intel_update_cdclk(dev);
6402 }
6403
6404 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6405 int max_pixclk)
6406 {
6407 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6408 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6409
6410 /*
6411 * Really only a few cases to deal with, as only 4 CDclks are supported:
6412 * 200MHz
6413 * 267MHz
6414 * 320/333MHz (depends on HPLL freq)
6415 * 400MHz (VLV only)
6416 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6417 * of the lower bin and adjust if needed.
6418 *
6419 * We seem to get an unstable or solid color picture at 200MHz.
6420 * Not sure what's wrong. For now use 200MHz only when all pipes
6421 * are off.
6422 */
6423 if (!IS_CHERRYVIEW(dev_priv) &&
6424 max_pixclk > freq_320*limit/100)
6425 return 400000;
6426 else if (max_pixclk > 266667*limit/100)
6427 return freq_320;
6428 else if (max_pixclk > 0)
6429 return 266667;
6430 else
6431 return 200000;
6432 }
6433
6434 static int bxt_calc_cdclk(int max_pixclk)
6435 {
6436 if (max_pixclk > 576000)
6437 return 624000;
6438 else if (max_pixclk > 384000)
6439 return 576000;
6440 else if (max_pixclk > 288000)
6441 return 384000;
6442 else if (max_pixclk > 144000)
6443 return 288000;
6444 else
6445 return 144000;
6446 }
6447
6448 /* Compute the max pixel clock for new configuration. */
6449 static int intel_mode_max_pixclk(struct drm_device *dev,
6450 struct drm_atomic_state *state)
6451 {
6452 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6453 struct drm_i915_private *dev_priv = to_i915(dev);
6454 struct drm_crtc *crtc;
6455 struct drm_crtc_state *crtc_state;
6456 unsigned max_pixclk = 0, i;
6457 enum pipe pipe;
6458
6459 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6460 sizeof(intel_state->min_pixclk));
6461
6462 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6463 int pixclk = 0;
6464
6465 if (crtc_state->enable)
6466 pixclk = crtc_state->adjusted_mode.crtc_clock;
6467
6468 intel_state->min_pixclk[i] = pixclk;
6469 }
6470
6471 for_each_pipe(dev_priv, pipe)
6472 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6473
6474 return max_pixclk;
6475 }
6476
6477 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6478 {
6479 struct drm_device *dev = state->dev;
6480 struct drm_i915_private *dev_priv = to_i915(dev);
6481 int max_pixclk = intel_mode_max_pixclk(dev, state);
6482 struct intel_atomic_state *intel_state =
6483 to_intel_atomic_state(state);
6484
6485 intel_state->cdclk = intel_state->dev_cdclk =
6486 valleyview_calc_cdclk(dev_priv, max_pixclk);
6487
6488 if (!intel_state->active_crtcs)
6489 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6490
6491 return 0;
6492 }
6493
6494 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6495 {
6496 int max_pixclk = ilk_max_pixel_rate(state);
6497 struct intel_atomic_state *intel_state =
6498 to_intel_atomic_state(state);
6499
6500 intel_state->cdclk = intel_state->dev_cdclk =
6501 bxt_calc_cdclk(max_pixclk);
6502
6503 if (!intel_state->active_crtcs)
6504 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6505
6506 return 0;
6507 }
6508
6509 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6510 {
6511 unsigned int credits, default_credits;
6512
6513 if (IS_CHERRYVIEW(dev_priv))
6514 default_credits = PFI_CREDIT(12);
6515 else
6516 default_credits = PFI_CREDIT(8);
6517
6518 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6519 /* CHV suggested value is 31 or 63 */
6520 if (IS_CHERRYVIEW(dev_priv))
6521 credits = PFI_CREDIT_63;
6522 else
6523 credits = PFI_CREDIT(15);
6524 } else {
6525 credits = default_credits;
6526 }
6527
6528 /*
6529 * WA - write default credits before re-programming
6530 * FIXME: should we also set the resend bit here?
6531 */
6532 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6533 default_credits);
6534
6535 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6536 credits | PFI_CREDIT_RESEND);
6537
6538 /*
6539 * FIXME is this guaranteed to clear
6540 * immediately or should we poll for it?
6541 */
6542 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6543 }
6544
6545 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6546 {
6547 struct drm_device *dev = old_state->dev;
6548 struct drm_i915_private *dev_priv = to_i915(dev);
6549 struct intel_atomic_state *old_intel_state =
6550 to_intel_atomic_state(old_state);
6551 unsigned req_cdclk = old_intel_state->dev_cdclk;
6552
6553 /*
6554 * FIXME: We can end up here with all power domains off, yet
6555 * with a CDCLK frequency other than the minimum. To account
6556 * for this take the PIPE-A power domain, which covers the HW
6557 * blocks needed for the following programming. This can be
6558 * removed once it's guaranteed that we get here either with
6559 * the minimum CDCLK set, or the required power domains
6560 * enabled.
6561 */
6562 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6563
6564 if (IS_CHERRYVIEW(dev))
6565 cherryview_set_cdclk(dev, req_cdclk);
6566 else
6567 valleyview_set_cdclk(dev, req_cdclk);
6568
6569 vlv_program_pfi_credits(dev_priv);
6570
6571 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6572 }
6573
6574 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6575 {
6576 struct drm_device *dev = crtc->dev;
6577 struct drm_i915_private *dev_priv = to_i915(dev);
6578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6579 struct intel_encoder *encoder;
6580 struct intel_crtc_state *pipe_config =
6581 to_intel_crtc_state(crtc->state);
6582 int pipe = intel_crtc->pipe;
6583
6584 if (WARN_ON(intel_crtc->active))
6585 return;
6586
6587 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6588 intel_dp_set_m_n(intel_crtc, M1_N1);
6589
6590 intel_set_pipe_timings(intel_crtc);
6591 intel_set_pipe_src_size(intel_crtc);
6592
6593 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6594 struct drm_i915_private *dev_priv = to_i915(dev);
6595
6596 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6597 I915_WRITE(CHV_CANVAS(pipe), 0);
6598 }
6599
6600 i9xx_set_pipeconf(intel_crtc);
6601
6602 intel_crtc->active = true;
6603
6604 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6605
6606 for_each_encoder_on_crtc(dev, crtc, encoder)
6607 if (encoder->pre_pll_enable)
6608 encoder->pre_pll_enable(encoder);
6609
6610 if (IS_CHERRYVIEW(dev)) {
6611 chv_prepare_pll(intel_crtc, intel_crtc->config);
6612 chv_enable_pll(intel_crtc, intel_crtc->config);
6613 } else {
6614 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6615 vlv_enable_pll(intel_crtc, intel_crtc->config);
6616 }
6617
6618 for_each_encoder_on_crtc(dev, crtc, encoder)
6619 if (encoder->pre_enable)
6620 encoder->pre_enable(encoder);
6621
6622 i9xx_pfit_enable(intel_crtc);
6623
6624 intel_color_load_luts(&pipe_config->base);
6625
6626 intel_update_watermarks(crtc);
6627 intel_enable_pipe(intel_crtc);
6628
6629 assert_vblank_disabled(crtc);
6630 drm_crtc_vblank_on(crtc);
6631
6632 for_each_encoder_on_crtc(dev, crtc, encoder)
6633 encoder->enable(encoder);
6634 }
6635
6636 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6637 {
6638 struct drm_device *dev = crtc->base.dev;
6639 struct drm_i915_private *dev_priv = to_i915(dev);
6640
6641 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6642 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6643 }
6644
6645 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6646 {
6647 struct drm_device *dev = crtc->dev;
6648 struct drm_i915_private *dev_priv = to_i915(dev);
6649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650 struct intel_encoder *encoder;
6651 struct intel_crtc_state *pipe_config =
6652 to_intel_crtc_state(crtc->state);
6653 enum pipe pipe = intel_crtc->pipe;
6654
6655 if (WARN_ON(intel_crtc->active))
6656 return;
6657
6658 i9xx_set_pll_dividers(intel_crtc);
6659
6660 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6661 intel_dp_set_m_n(intel_crtc, M1_N1);
6662
6663 intel_set_pipe_timings(intel_crtc);
6664 intel_set_pipe_src_size(intel_crtc);
6665
6666 i9xx_set_pipeconf(intel_crtc);
6667
6668 intel_crtc->active = true;
6669
6670 if (!IS_GEN2(dev))
6671 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6672
6673 for_each_encoder_on_crtc(dev, crtc, encoder)
6674 if (encoder->pre_enable)
6675 encoder->pre_enable(encoder);
6676
6677 i9xx_enable_pll(intel_crtc);
6678
6679 i9xx_pfit_enable(intel_crtc);
6680
6681 intel_color_load_luts(&pipe_config->base);
6682
6683 intel_update_watermarks(crtc);
6684 intel_enable_pipe(intel_crtc);
6685
6686 assert_vblank_disabled(crtc);
6687 drm_crtc_vblank_on(crtc);
6688
6689 for_each_encoder_on_crtc(dev, crtc, encoder)
6690 encoder->enable(encoder);
6691 }
6692
6693 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6694 {
6695 struct drm_device *dev = crtc->base.dev;
6696 struct drm_i915_private *dev_priv = to_i915(dev);
6697
6698 if (!crtc->config->gmch_pfit.control)
6699 return;
6700
6701 assert_pipe_disabled(dev_priv, crtc->pipe);
6702
6703 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6704 I915_READ(PFIT_CONTROL));
6705 I915_WRITE(PFIT_CONTROL, 0);
6706 }
6707
6708 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6709 {
6710 struct drm_device *dev = crtc->dev;
6711 struct drm_i915_private *dev_priv = to_i915(dev);
6712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6713 struct intel_encoder *encoder;
6714 int pipe = intel_crtc->pipe;
6715
6716 /*
6717 * On gen2 planes are double buffered but the pipe isn't, so we must
6718 * wait for planes to fully turn off before disabling the pipe.
6719 */
6720 if (IS_GEN2(dev))
6721 intel_wait_for_vblank(dev, pipe);
6722
6723 for_each_encoder_on_crtc(dev, crtc, encoder)
6724 encoder->disable(encoder);
6725
6726 drm_crtc_vblank_off(crtc);
6727 assert_vblank_disabled(crtc);
6728
6729 intel_disable_pipe(intel_crtc);
6730
6731 i9xx_pfit_disable(intel_crtc);
6732
6733 for_each_encoder_on_crtc(dev, crtc, encoder)
6734 if (encoder->post_disable)
6735 encoder->post_disable(encoder);
6736
6737 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6738 if (IS_CHERRYVIEW(dev))
6739 chv_disable_pll(dev_priv, pipe);
6740 else if (IS_VALLEYVIEW(dev))
6741 vlv_disable_pll(dev_priv, pipe);
6742 else
6743 i9xx_disable_pll(intel_crtc);
6744 }
6745
6746 for_each_encoder_on_crtc(dev, crtc, encoder)
6747 if (encoder->post_pll_disable)
6748 encoder->post_pll_disable(encoder);
6749
6750 if (!IS_GEN2(dev))
6751 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6752 }
6753
6754 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6755 {
6756 struct intel_encoder *encoder;
6757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6758 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6759 enum intel_display_power_domain domain;
6760 unsigned long domains;
6761
6762 if (!intel_crtc->active)
6763 return;
6764
6765 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6766 WARN_ON(intel_crtc->flip_work);
6767
6768 intel_pre_disable_primary_noatomic(crtc);
6769
6770 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6771 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6772 }
6773
6774 dev_priv->display.crtc_disable(crtc);
6775
6776 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6777 crtc->base.id, crtc->name);
6778
6779 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6780 crtc->state->active = false;
6781 intel_crtc->active = false;
6782 crtc->enabled = false;
6783 crtc->state->connector_mask = 0;
6784 crtc->state->encoder_mask = 0;
6785
6786 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6787 encoder->base.crtc = NULL;
6788
6789 intel_fbc_disable(intel_crtc);
6790 intel_update_watermarks(crtc);
6791 intel_disable_shared_dpll(intel_crtc);
6792
6793 domains = intel_crtc->enabled_power_domains;
6794 for_each_power_domain(domain, domains)
6795 intel_display_power_put(dev_priv, domain);
6796 intel_crtc->enabled_power_domains = 0;
6797
6798 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6799 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6800 }
6801
6802 /*
6803 * turn all crtc's off, but do not adjust state
6804 * This has to be paired with a call to intel_modeset_setup_hw_state.
6805 */
6806 int intel_display_suspend(struct drm_device *dev)
6807 {
6808 struct drm_i915_private *dev_priv = to_i915(dev);
6809 struct drm_atomic_state *state;
6810 int ret;
6811
6812 state = drm_atomic_helper_suspend(dev);
6813 ret = PTR_ERR_OR_ZERO(state);
6814 if (ret)
6815 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6816 else
6817 dev_priv->modeset_restore_state = state;
6818 return ret;
6819 }
6820
6821 void intel_encoder_destroy(struct drm_encoder *encoder)
6822 {
6823 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6824
6825 drm_encoder_cleanup(encoder);
6826 kfree(intel_encoder);
6827 }
6828
6829 /* Cross check the actual hw state with our own modeset state tracking (and it's
6830 * internal consistency). */
6831 static void intel_connector_verify_state(struct intel_connector *connector)
6832 {
6833 struct drm_crtc *crtc = connector->base.state->crtc;
6834
6835 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6836 connector->base.base.id,
6837 connector->base.name);
6838
6839 if (connector->get_hw_state(connector)) {
6840 struct intel_encoder *encoder = connector->encoder;
6841 struct drm_connector_state *conn_state = connector->base.state;
6842
6843 I915_STATE_WARN(!crtc,
6844 "connector enabled without attached crtc\n");
6845
6846 if (!crtc)
6847 return;
6848
6849 I915_STATE_WARN(!crtc->state->active,
6850 "connector is active, but attached crtc isn't\n");
6851
6852 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6853 return;
6854
6855 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6856 "atomic encoder doesn't match attached encoder\n");
6857
6858 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6859 "attached encoder crtc differs from connector crtc\n");
6860 } else {
6861 I915_STATE_WARN(crtc && crtc->state->active,
6862 "attached crtc is active, but connector isn't\n");
6863 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6864 "best encoder set without crtc!\n");
6865 }
6866 }
6867
6868 int intel_connector_init(struct intel_connector *connector)
6869 {
6870 drm_atomic_helper_connector_reset(&connector->base);
6871
6872 if (!connector->base.state)
6873 return -ENOMEM;
6874
6875 return 0;
6876 }
6877
6878 struct intel_connector *intel_connector_alloc(void)
6879 {
6880 struct intel_connector *connector;
6881
6882 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6883 if (!connector)
6884 return NULL;
6885
6886 if (intel_connector_init(connector) < 0) {
6887 kfree(connector);
6888 return NULL;
6889 }
6890
6891 return connector;
6892 }
6893
6894 /* Simple connector->get_hw_state implementation for encoders that support only
6895 * one connector and no cloning and hence the encoder state determines the state
6896 * of the connector. */
6897 bool intel_connector_get_hw_state(struct intel_connector *connector)
6898 {
6899 enum pipe pipe = 0;
6900 struct intel_encoder *encoder = connector->encoder;
6901
6902 return encoder->get_hw_state(encoder, &pipe);
6903 }
6904
6905 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6906 {
6907 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6908 return crtc_state->fdi_lanes;
6909
6910 return 0;
6911 }
6912
6913 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6914 struct intel_crtc_state *pipe_config)
6915 {
6916 struct drm_atomic_state *state = pipe_config->base.state;
6917 struct intel_crtc *other_crtc;
6918 struct intel_crtc_state *other_crtc_state;
6919
6920 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6921 pipe_name(pipe), pipe_config->fdi_lanes);
6922 if (pipe_config->fdi_lanes > 4) {
6923 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6924 pipe_name(pipe), pipe_config->fdi_lanes);
6925 return -EINVAL;
6926 }
6927
6928 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6929 if (pipe_config->fdi_lanes > 2) {
6930 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6931 pipe_config->fdi_lanes);
6932 return -EINVAL;
6933 } else {
6934 return 0;
6935 }
6936 }
6937
6938 if (INTEL_INFO(dev)->num_pipes == 2)
6939 return 0;
6940
6941 /* Ivybridge 3 pipe is really complicated */
6942 switch (pipe) {
6943 case PIPE_A:
6944 return 0;
6945 case PIPE_B:
6946 if (pipe_config->fdi_lanes <= 2)
6947 return 0;
6948
6949 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6950 other_crtc_state =
6951 intel_atomic_get_crtc_state(state, other_crtc);
6952 if (IS_ERR(other_crtc_state))
6953 return PTR_ERR(other_crtc_state);
6954
6955 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6956 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6957 pipe_name(pipe), pipe_config->fdi_lanes);
6958 return -EINVAL;
6959 }
6960 return 0;
6961 case PIPE_C:
6962 if (pipe_config->fdi_lanes > 2) {
6963 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6964 pipe_name(pipe), pipe_config->fdi_lanes);
6965 return -EINVAL;
6966 }
6967
6968 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6969 other_crtc_state =
6970 intel_atomic_get_crtc_state(state, other_crtc);
6971 if (IS_ERR(other_crtc_state))
6972 return PTR_ERR(other_crtc_state);
6973
6974 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6975 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6976 return -EINVAL;
6977 }
6978 return 0;
6979 default:
6980 BUG();
6981 }
6982 }
6983
6984 #define RETRY 1
6985 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6986 struct intel_crtc_state *pipe_config)
6987 {
6988 struct drm_device *dev = intel_crtc->base.dev;
6989 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6990 int lane, link_bw, fdi_dotclock, ret;
6991 bool needs_recompute = false;
6992
6993 retry:
6994 /* FDI is a binary signal running at ~2.7GHz, encoding
6995 * each output octet as 10 bits. The actual frequency
6996 * is stored as a divider into a 100MHz clock, and the
6997 * mode pixel clock is stored in units of 1KHz.
6998 * Hence the bw of each lane in terms of the mode signal
6999 * is:
7000 */
7001 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7002
7003 fdi_dotclock = adjusted_mode->crtc_clock;
7004
7005 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7006 pipe_config->pipe_bpp);
7007
7008 pipe_config->fdi_lanes = lane;
7009
7010 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7011 link_bw, &pipe_config->fdi_m_n);
7012
7013 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7014 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7015 pipe_config->pipe_bpp -= 2*3;
7016 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7017 pipe_config->pipe_bpp);
7018 needs_recompute = true;
7019 pipe_config->bw_constrained = true;
7020
7021 goto retry;
7022 }
7023
7024 if (needs_recompute)
7025 return RETRY;
7026
7027 return ret;
7028 }
7029
7030 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7031 struct intel_crtc_state *pipe_config)
7032 {
7033 if (pipe_config->pipe_bpp > 24)
7034 return false;
7035
7036 /* HSW can handle pixel rate up to cdclk? */
7037 if (IS_HASWELL(dev_priv))
7038 return true;
7039
7040 /*
7041 * We compare against max which means we must take
7042 * the increased cdclk requirement into account when
7043 * calculating the new cdclk.
7044 *
7045 * Should measure whether using a lower cdclk w/o IPS
7046 */
7047 return ilk_pipe_pixel_rate(pipe_config) <=
7048 dev_priv->max_cdclk_freq * 95 / 100;
7049 }
7050
7051 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7052 struct intel_crtc_state *pipe_config)
7053 {
7054 struct drm_device *dev = crtc->base.dev;
7055 struct drm_i915_private *dev_priv = to_i915(dev);
7056
7057 pipe_config->ips_enabled = i915.enable_ips &&
7058 hsw_crtc_supports_ips(crtc) &&
7059 pipe_config_supports_ips(dev_priv, pipe_config);
7060 }
7061
7062 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7063 {
7064 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7065
7066 /* GDG double wide on either pipe, otherwise pipe A only */
7067 return INTEL_INFO(dev_priv)->gen < 4 &&
7068 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7069 }
7070
7071 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7072 struct intel_crtc_state *pipe_config)
7073 {
7074 struct drm_device *dev = crtc->base.dev;
7075 struct drm_i915_private *dev_priv = to_i915(dev);
7076 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7077 int clock_limit = dev_priv->max_dotclk_freq;
7078
7079 if (INTEL_INFO(dev)->gen < 4) {
7080 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7081
7082 /*
7083 * Enable double wide mode when the dot clock
7084 * is > 90% of the (display) core speed.
7085 */
7086 if (intel_crtc_supports_double_wide(crtc) &&
7087 adjusted_mode->crtc_clock > clock_limit) {
7088 clock_limit = dev_priv->max_dotclk_freq;
7089 pipe_config->double_wide = true;
7090 }
7091 }
7092
7093 if (adjusted_mode->crtc_clock > clock_limit) {
7094 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7095 adjusted_mode->crtc_clock, clock_limit,
7096 yesno(pipe_config->double_wide));
7097 return -EINVAL;
7098 }
7099
7100 /*
7101 * Pipe horizontal size must be even in:
7102 * - DVO ganged mode
7103 * - LVDS dual channel mode
7104 * - Double wide pipe
7105 */
7106 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7107 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7108 pipe_config->pipe_src_w &= ~1;
7109
7110 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7111 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7112 */
7113 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7114 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7115 return -EINVAL;
7116
7117 if (HAS_IPS(dev))
7118 hsw_compute_ips_config(crtc, pipe_config);
7119
7120 if (pipe_config->has_pch_encoder)
7121 return ironlake_fdi_compute_config(crtc, pipe_config);
7122
7123 return 0;
7124 }
7125
7126 static int skylake_get_display_clock_speed(struct drm_device *dev)
7127 {
7128 struct drm_i915_private *dev_priv = to_i915(dev);
7129 uint32_t cdctl;
7130
7131 skl_dpll0_update(dev_priv);
7132
7133 if (dev_priv->cdclk_pll.vco == 0)
7134 return dev_priv->cdclk_pll.ref;
7135
7136 cdctl = I915_READ(CDCLK_CTL);
7137
7138 if (dev_priv->cdclk_pll.vco == 8640000) {
7139 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7140 case CDCLK_FREQ_450_432:
7141 return 432000;
7142 case CDCLK_FREQ_337_308:
7143 return 308571;
7144 case CDCLK_FREQ_540:
7145 return 540000;
7146 case CDCLK_FREQ_675_617:
7147 return 617143;
7148 default:
7149 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7150 }
7151 } else {
7152 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7153 case CDCLK_FREQ_450_432:
7154 return 450000;
7155 case CDCLK_FREQ_337_308:
7156 return 337500;
7157 case CDCLK_FREQ_540:
7158 return 540000;
7159 case CDCLK_FREQ_675_617:
7160 return 675000;
7161 default:
7162 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7163 }
7164 }
7165
7166 return dev_priv->cdclk_pll.ref;
7167 }
7168
7169 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7170 {
7171 u32 val;
7172
7173 dev_priv->cdclk_pll.ref = 19200;
7174 dev_priv->cdclk_pll.vco = 0;
7175
7176 val = I915_READ(BXT_DE_PLL_ENABLE);
7177 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7178 return;
7179
7180 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7181 return;
7182
7183 val = I915_READ(BXT_DE_PLL_CTL);
7184 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7185 dev_priv->cdclk_pll.ref;
7186 }
7187
7188 static int broxton_get_display_clock_speed(struct drm_device *dev)
7189 {
7190 struct drm_i915_private *dev_priv = to_i915(dev);
7191 u32 divider;
7192 int div, vco;
7193
7194 bxt_de_pll_update(dev_priv);
7195
7196 vco = dev_priv->cdclk_pll.vco;
7197 if (vco == 0)
7198 return dev_priv->cdclk_pll.ref;
7199
7200 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7201
7202 switch (divider) {
7203 case BXT_CDCLK_CD2X_DIV_SEL_1:
7204 div = 2;
7205 break;
7206 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7207 div = 3;
7208 break;
7209 case BXT_CDCLK_CD2X_DIV_SEL_2:
7210 div = 4;
7211 break;
7212 case BXT_CDCLK_CD2X_DIV_SEL_4:
7213 div = 8;
7214 break;
7215 default:
7216 MISSING_CASE(divider);
7217 return dev_priv->cdclk_pll.ref;
7218 }
7219
7220 return DIV_ROUND_CLOSEST(vco, div);
7221 }
7222
7223 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7224 {
7225 struct drm_i915_private *dev_priv = to_i915(dev);
7226 uint32_t lcpll = I915_READ(LCPLL_CTL);
7227 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7228
7229 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7230 return 800000;
7231 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7232 return 450000;
7233 else if (freq == LCPLL_CLK_FREQ_450)
7234 return 450000;
7235 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7236 return 540000;
7237 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7238 return 337500;
7239 else
7240 return 675000;
7241 }
7242
7243 static int haswell_get_display_clock_speed(struct drm_device *dev)
7244 {
7245 struct drm_i915_private *dev_priv = to_i915(dev);
7246 uint32_t lcpll = I915_READ(LCPLL_CTL);
7247 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7248
7249 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7250 return 800000;
7251 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7252 return 450000;
7253 else if (freq == LCPLL_CLK_FREQ_450)
7254 return 450000;
7255 else if (IS_HSW_ULT(dev))
7256 return 337500;
7257 else
7258 return 540000;
7259 }
7260
7261 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7262 {
7263 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7264 CCK_DISPLAY_CLOCK_CONTROL);
7265 }
7266
7267 static int ilk_get_display_clock_speed(struct drm_device *dev)
7268 {
7269 return 450000;
7270 }
7271
7272 static int i945_get_display_clock_speed(struct drm_device *dev)
7273 {
7274 return 400000;
7275 }
7276
7277 static int i915_get_display_clock_speed(struct drm_device *dev)
7278 {
7279 return 333333;
7280 }
7281
7282 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7283 {
7284 return 200000;
7285 }
7286
7287 static int pnv_get_display_clock_speed(struct drm_device *dev)
7288 {
7289 u16 gcfgc = 0;
7290
7291 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7292
7293 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7294 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7295 return 266667;
7296 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7297 return 333333;
7298 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7299 return 444444;
7300 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7301 return 200000;
7302 default:
7303 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7304 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7305 return 133333;
7306 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7307 return 166667;
7308 }
7309 }
7310
7311 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7312 {
7313 u16 gcfgc = 0;
7314
7315 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7316
7317 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7318 return 133333;
7319 else {
7320 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7321 case GC_DISPLAY_CLOCK_333_MHZ:
7322 return 333333;
7323 default:
7324 case GC_DISPLAY_CLOCK_190_200_MHZ:
7325 return 190000;
7326 }
7327 }
7328 }
7329
7330 static int i865_get_display_clock_speed(struct drm_device *dev)
7331 {
7332 return 266667;
7333 }
7334
7335 static int i85x_get_display_clock_speed(struct drm_device *dev)
7336 {
7337 u16 hpllcc = 0;
7338
7339 /*
7340 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7341 * encoding is different :(
7342 * FIXME is this the right way to detect 852GM/852GMV?
7343 */
7344 if (dev->pdev->revision == 0x1)
7345 return 133333;
7346
7347 pci_bus_read_config_word(dev->pdev->bus,
7348 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7349
7350 /* Assume that the hardware is in the high speed state. This
7351 * should be the default.
7352 */
7353 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7354 case GC_CLOCK_133_200:
7355 case GC_CLOCK_133_200_2:
7356 case GC_CLOCK_100_200:
7357 return 200000;
7358 case GC_CLOCK_166_250:
7359 return 250000;
7360 case GC_CLOCK_100_133:
7361 return 133333;
7362 case GC_CLOCK_133_266:
7363 case GC_CLOCK_133_266_2:
7364 case GC_CLOCK_166_266:
7365 return 266667;
7366 }
7367
7368 /* Shouldn't happen */
7369 return 0;
7370 }
7371
7372 static int i830_get_display_clock_speed(struct drm_device *dev)
7373 {
7374 return 133333;
7375 }
7376
7377 static unsigned int intel_hpll_vco(struct drm_device *dev)
7378 {
7379 struct drm_i915_private *dev_priv = to_i915(dev);
7380 static const unsigned int blb_vco[8] = {
7381 [0] = 3200000,
7382 [1] = 4000000,
7383 [2] = 5333333,
7384 [3] = 4800000,
7385 [4] = 6400000,
7386 };
7387 static const unsigned int pnv_vco[8] = {
7388 [0] = 3200000,
7389 [1] = 4000000,
7390 [2] = 5333333,
7391 [3] = 4800000,
7392 [4] = 2666667,
7393 };
7394 static const unsigned int cl_vco[8] = {
7395 [0] = 3200000,
7396 [1] = 4000000,
7397 [2] = 5333333,
7398 [3] = 6400000,
7399 [4] = 3333333,
7400 [5] = 3566667,
7401 [6] = 4266667,
7402 };
7403 static const unsigned int elk_vco[8] = {
7404 [0] = 3200000,
7405 [1] = 4000000,
7406 [2] = 5333333,
7407 [3] = 4800000,
7408 };
7409 static const unsigned int ctg_vco[8] = {
7410 [0] = 3200000,
7411 [1] = 4000000,
7412 [2] = 5333333,
7413 [3] = 6400000,
7414 [4] = 2666667,
7415 [5] = 4266667,
7416 };
7417 const unsigned int *vco_table;
7418 unsigned int vco;
7419 uint8_t tmp = 0;
7420
7421 /* FIXME other chipsets? */
7422 if (IS_GM45(dev))
7423 vco_table = ctg_vco;
7424 else if (IS_G4X(dev))
7425 vco_table = elk_vco;
7426 else if (IS_CRESTLINE(dev))
7427 vco_table = cl_vco;
7428 else if (IS_PINEVIEW(dev))
7429 vco_table = pnv_vco;
7430 else if (IS_G33(dev))
7431 vco_table = blb_vco;
7432 else
7433 return 0;
7434
7435 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7436
7437 vco = vco_table[tmp & 0x7];
7438 if (vco == 0)
7439 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7440 else
7441 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7442
7443 return vco;
7444 }
7445
7446 static int gm45_get_display_clock_speed(struct drm_device *dev)
7447 {
7448 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7449 uint16_t tmp = 0;
7450
7451 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7452
7453 cdclk_sel = (tmp >> 12) & 0x1;
7454
7455 switch (vco) {
7456 case 2666667:
7457 case 4000000:
7458 case 5333333:
7459 return cdclk_sel ? 333333 : 222222;
7460 case 3200000:
7461 return cdclk_sel ? 320000 : 228571;
7462 default:
7463 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7464 return 222222;
7465 }
7466 }
7467
7468 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7469 {
7470 static const uint8_t div_3200[] = { 16, 10, 8 };
7471 static const uint8_t div_4000[] = { 20, 12, 10 };
7472 static const uint8_t div_5333[] = { 24, 16, 14 };
7473 const uint8_t *div_table;
7474 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7475 uint16_t tmp = 0;
7476
7477 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7478
7479 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7480
7481 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7482 goto fail;
7483
7484 switch (vco) {
7485 case 3200000:
7486 div_table = div_3200;
7487 break;
7488 case 4000000:
7489 div_table = div_4000;
7490 break;
7491 case 5333333:
7492 div_table = div_5333;
7493 break;
7494 default:
7495 goto fail;
7496 }
7497
7498 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7499
7500 fail:
7501 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7502 return 200000;
7503 }
7504
7505 static int g33_get_display_clock_speed(struct drm_device *dev)
7506 {
7507 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7508 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7509 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7510 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7511 const uint8_t *div_table;
7512 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7513 uint16_t tmp = 0;
7514
7515 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7516
7517 cdclk_sel = (tmp >> 4) & 0x7;
7518
7519 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7520 goto fail;
7521
7522 switch (vco) {
7523 case 3200000:
7524 div_table = div_3200;
7525 break;
7526 case 4000000:
7527 div_table = div_4000;
7528 break;
7529 case 4800000:
7530 div_table = div_4800;
7531 break;
7532 case 5333333:
7533 div_table = div_5333;
7534 break;
7535 default:
7536 goto fail;
7537 }
7538
7539 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7540
7541 fail:
7542 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7543 return 190476;
7544 }
7545
7546 static void
7547 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7548 {
7549 while (*num > DATA_LINK_M_N_MASK ||
7550 *den > DATA_LINK_M_N_MASK) {
7551 *num >>= 1;
7552 *den >>= 1;
7553 }
7554 }
7555
7556 static void compute_m_n(unsigned int m, unsigned int n,
7557 uint32_t *ret_m, uint32_t *ret_n)
7558 {
7559 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7560 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7561 intel_reduce_m_n_ratio(ret_m, ret_n);
7562 }
7563
7564 void
7565 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7566 int pixel_clock, int link_clock,
7567 struct intel_link_m_n *m_n)
7568 {
7569 m_n->tu = 64;
7570
7571 compute_m_n(bits_per_pixel * pixel_clock,
7572 link_clock * nlanes * 8,
7573 &m_n->gmch_m, &m_n->gmch_n);
7574
7575 compute_m_n(pixel_clock, link_clock,
7576 &m_n->link_m, &m_n->link_n);
7577 }
7578
7579 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7580 {
7581 if (i915.panel_use_ssc >= 0)
7582 return i915.panel_use_ssc != 0;
7583 return dev_priv->vbt.lvds_use_ssc
7584 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7585 }
7586
7587 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7588 {
7589 return (1 << dpll->n) << 16 | dpll->m2;
7590 }
7591
7592 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7593 {
7594 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7595 }
7596
7597 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7598 struct intel_crtc_state *crtc_state,
7599 struct dpll *reduced_clock)
7600 {
7601 struct drm_device *dev = crtc->base.dev;
7602 u32 fp, fp2 = 0;
7603
7604 if (IS_PINEVIEW(dev)) {
7605 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7606 if (reduced_clock)
7607 fp2 = pnv_dpll_compute_fp(reduced_clock);
7608 } else {
7609 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7610 if (reduced_clock)
7611 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7612 }
7613
7614 crtc_state->dpll_hw_state.fp0 = fp;
7615
7616 crtc->lowfreq_avail = false;
7617 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7618 reduced_clock) {
7619 crtc_state->dpll_hw_state.fp1 = fp2;
7620 crtc->lowfreq_avail = true;
7621 } else {
7622 crtc_state->dpll_hw_state.fp1 = fp;
7623 }
7624 }
7625
7626 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7627 pipe)
7628 {
7629 u32 reg_val;
7630
7631 /*
7632 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7633 * and set it to a reasonable value instead.
7634 */
7635 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7636 reg_val &= 0xffffff00;
7637 reg_val |= 0x00000030;
7638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7639
7640 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7641 reg_val &= 0x8cffffff;
7642 reg_val = 0x8c000000;
7643 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7644
7645 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7646 reg_val &= 0xffffff00;
7647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7648
7649 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7650 reg_val &= 0x00ffffff;
7651 reg_val |= 0xb0000000;
7652 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7653 }
7654
7655 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7656 struct intel_link_m_n *m_n)
7657 {
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = to_i915(dev);
7660 int pipe = crtc->pipe;
7661
7662 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7663 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7664 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7665 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7666 }
7667
7668 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7669 struct intel_link_m_n *m_n,
7670 struct intel_link_m_n *m2_n2)
7671 {
7672 struct drm_device *dev = crtc->base.dev;
7673 struct drm_i915_private *dev_priv = to_i915(dev);
7674 int pipe = crtc->pipe;
7675 enum transcoder transcoder = crtc->config->cpu_transcoder;
7676
7677 if (INTEL_INFO(dev)->gen >= 5) {
7678 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7679 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7680 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7681 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7682 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7683 * for gen < 8) and if DRRS is supported (to make sure the
7684 * registers are not unnecessarily accessed).
7685 */
7686 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7687 crtc->config->has_drrs) {
7688 I915_WRITE(PIPE_DATA_M2(transcoder),
7689 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7690 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7691 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7692 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7693 }
7694 } else {
7695 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7696 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7697 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7698 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7699 }
7700 }
7701
7702 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7703 {
7704 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7705
7706 if (m_n == M1_N1) {
7707 dp_m_n = &crtc->config->dp_m_n;
7708 dp_m2_n2 = &crtc->config->dp_m2_n2;
7709 } else if (m_n == M2_N2) {
7710
7711 /*
7712 * M2_N2 registers are not supported. Hence m2_n2 divider value
7713 * needs to be programmed into M1_N1.
7714 */
7715 dp_m_n = &crtc->config->dp_m2_n2;
7716 } else {
7717 DRM_ERROR("Unsupported divider value\n");
7718 return;
7719 }
7720
7721 if (crtc->config->has_pch_encoder)
7722 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7723 else
7724 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7725 }
7726
7727 static void vlv_compute_dpll(struct intel_crtc *crtc,
7728 struct intel_crtc_state *pipe_config)
7729 {
7730 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7731 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7732 if (crtc->pipe != PIPE_A)
7733 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7734
7735 /* DPLL not used with DSI, but still need the rest set up */
7736 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7737 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7738 DPLL_EXT_BUFFER_ENABLE_VLV;
7739
7740 pipe_config->dpll_hw_state.dpll_md =
7741 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7742 }
7743
7744 static void chv_compute_dpll(struct intel_crtc *crtc,
7745 struct intel_crtc_state *pipe_config)
7746 {
7747 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7748 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7749 if (crtc->pipe != PIPE_A)
7750 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7751
7752 /* DPLL not used with DSI, but still need the rest set up */
7753 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7754 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7755
7756 pipe_config->dpll_hw_state.dpll_md =
7757 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7758 }
7759
7760 static void vlv_prepare_pll(struct intel_crtc *crtc,
7761 const struct intel_crtc_state *pipe_config)
7762 {
7763 struct drm_device *dev = crtc->base.dev;
7764 struct drm_i915_private *dev_priv = to_i915(dev);
7765 enum pipe pipe = crtc->pipe;
7766 u32 mdiv;
7767 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7768 u32 coreclk, reg_val;
7769
7770 /* Enable Refclk */
7771 I915_WRITE(DPLL(pipe),
7772 pipe_config->dpll_hw_state.dpll &
7773 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7774
7775 /* No need to actually set up the DPLL with DSI */
7776 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7777 return;
7778
7779 mutex_lock(&dev_priv->sb_lock);
7780
7781 bestn = pipe_config->dpll.n;
7782 bestm1 = pipe_config->dpll.m1;
7783 bestm2 = pipe_config->dpll.m2;
7784 bestp1 = pipe_config->dpll.p1;
7785 bestp2 = pipe_config->dpll.p2;
7786
7787 /* See eDP HDMI DPIO driver vbios notes doc */
7788
7789 /* PLL B needs special handling */
7790 if (pipe == PIPE_B)
7791 vlv_pllb_recal_opamp(dev_priv, pipe);
7792
7793 /* Set up Tx target for periodic Rcomp update */
7794 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7795
7796 /* Disable target IRef on PLL */
7797 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7798 reg_val &= 0x00ffffff;
7799 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7800
7801 /* Disable fast lock */
7802 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7803
7804 /* Set idtafcrecal before PLL is enabled */
7805 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7806 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7807 mdiv |= ((bestn << DPIO_N_SHIFT));
7808 mdiv |= (1 << DPIO_K_SHIFT);
7809
7810 /*
7811 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7812 * but we don't support that).
7813 * Note: don't use the DAC post divider as it seems unstable.
7814 */
7815 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7816 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7817
7818 mdiv |= DPIO_ENABLE_CALIBRATION;
7819 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7820
7821 /* Set HBR and RBR LPF coefficients */
7822 if (pipe_config->port_clock == 162000 ||
7823 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7824 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7825 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7826 0x009f0003);
7827 else
7828 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7829 0x00d0000f);
7830
7831 if (intel_crtc_has_dp_encoder(pipe_config)) {
7832 /* Use SSC source */
7833 if (pipe == PIPE_A)
7834 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7835 0x0df40000);
7836 else
7837 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7838 0x0df70000);
7839 } else { /* HDMI or VGA */
7840 /* Use bend source */
7841 if (pipe == PIPE_A)
7842 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7843 0x0df70000);
7844 else
7845 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7846 0x0df40000);
7847 }
7848
7849 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7850 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7851 if (intel_crtc_has_dp_encoder(crtc->config))
7852 coreclk |= 0x01000000;
7853 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7854
7855 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7856 mutex_unlock(&dev_priv->sb_lock);
7857 }
7858
7859 static void chv_prepare_pll(struct intel_crtc *crtc,
7860 const struct intel_crtc_state *pipe_config)
7861 {
7862 struct drm_device *dev = crtc->base.dev;
7863 struct drm_i915_private *dev_priv = to_i915(dev);
7864 enum pipe pipe = crtc->pipe;
7865 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7866 u32 loopfilter, tribuf_calcntr;
7867 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7868 u32 dpio_val;
7869 int vco;
7870
7871 /* Enable Refclk and SSC */
7872 I915_WRITE(DPLL(pipe),
7873 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7874
7875 /* No need to actually set up the DPLL with DSI */
7876 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7877 return;
7878
7879 bestn = pipe_config->dpll.n;
7880 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7881 bestm1 = pipe_config->dpll.m1;
7882 bestm2 = pipe_config->dpll.m2 >> 22;
7883 bestp1 = pipe_config->dpll.p1;
7884 bestp2 = pipe_config->dpll.p2;
7885 vco = pipe_config->dpll.vco;
7886 dpio_val = 0;
7887 loopfilter = 0;
7888
7889 mutex_lock(&dev_priv->sb_lock);
7890
7891 /* p1 and p2 divider */
7892 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7893 5 << DPIO_CHV_S1_DIV_SHIFT |
7894 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7895 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7896 1 << DPIO_CHV_K_DIV_SHIFT);
7897
7898 /* Feedback post-divider - m2 */
7899 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7900
7901 /* Feedback refclk divider - n and m1 */
7902 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7903 DPIO_CHV_M1_DIV_BY_2 |
7904 1 << DPIO_CHV_N_DIV_SHIFT);
7905
7906 /* M2 fraction division */
7907 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7908
7909 /* M2 fraction division enable */
7910 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7911 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7912 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7913 if (bestm2_frac)
7914 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7915 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7916
7917 /* Program digital lock detect threshold */
7918 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7919 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7920 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7921 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7922 if (!bestm2_frac)
7923 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7924 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7925
7926 /* Loop filter */
7927 if (vco == 5400000) {
7928 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7929 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7930 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7931 tribuf_calcntr = 0x9;
7932 } else if (vco <= 6200000) {
7933 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7934 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7935 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7936 tribuf_calcntr = 0x9;
7937 } else if (vco <= 6480000) {
7938 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7939 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7940 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7941 tribuf_calcntr = 0x8;
7942 } else {
7943 /* Not supported. Apply the same limits as in the max case */
7944 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7945 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7946 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7947 tribuf_calcntr = 0;
7948 }
7949 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7950
7951 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7952 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7953 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7954 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7955
7956 /* AFC Recal */
7957 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7958 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7959 DPIO_AFC_RECAL);
7960
7961 mutex_unlock(&dev_priv->sb_lock);
7962 }
7963
7964 /**
7965 * vlv_force_pll_on - forcibly enable just the PLL
7966 * @dev_priv: i915 private structure
7967 * @pipe: pipe PLL to enable
7968 * @dpll: PLL configuration
7969 *
7970 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7971 * in cases where we need the PLL enabled even when @pipe is not going to
7972 * be enabled.
7973 */
7974 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7975 const struct dpll *dpll)
7976 {
7977 struct intel_crtc *crtc =
7978 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7979 struct intel_crtc_state *pipe_config;
7980
7981 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7982 if (!pipe_config)
7983 return -ENOMEM;
7984
7985 pipe_config->base.crtc = &crtc->base;
7986 pipe_config->pixel_multiplier = 1;
7987 pipe_config->dpll = *dpll;
7988
7989 if (IS_CHERRYVIEW(dev)) {
7990 chv_compute_dpll(crtc, pipe_config);
7991 chv_prepare_pll(crtc, pipe_config);
7992 chv_enable_pll(crtc, pipe_config);
7993 } else {
7994 vlv_compute_dpll(crtc, pipe_config);
7995 vlv_prepare_pll(crtc, pipe_config);
7996 vlv_enable_pll(crtc, pipe_config);
7997 }
7998
7999 kfree(pipe_config);
8000
8001 return 0;
8002 }
8003
8004 /**
8005 * vlv_force_pll_off - forcibly disable just the PLL
8006 * @dev_priv: i915 private structure
8007 * @pipe: pipe PLL to disable
8008 *
8009 * Disable the PLL for @pipe. To be used in cases where we need
8010 * the PLL enabled even when @pipe is not going to be enabled.
8011 */
8012 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8013 {
8014 if (IS_CHERRYVIEW(dev))
8015 chv_disable_pll(to_i915(dev), pipe);
8016 else
8017 vlv_disable_pll(to_i915(dev), pipe);
8018 }
8019
8020 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8021 struct intel_crtc_state *crtc_state,
8022 struct dpll *reduced_clock)
8023 {
8024 struct drm_device *dev = crtc->base.dev;
8025 struct drm_i915_private *dev_priv = to_i915(dev);
8026 u32 dpll;
8027 struct dpll *clock = &crtc_state->dpll;
8028
8029 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8030
8031 dpll = DPLL_VGA_MODE_DIS;
8032
8033 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8034 dpll |= DPLLB_MODE_LVDS;
8035 else
8036 dpll |= DPLLB_MODE_DAC_SERIAL;
8037
8038 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8039 dpll |= (crtc_state->pixel_multiplier - 1)
8040 << SDVO_MULTIPLIER_SHIFT_HIRES;
8041 }
8042
8043 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8044 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8045 dpll |= DPLL_SDVO_HIGH_SPEED;
8046
8047 if (intel_crtc_has_dp_encoder(crtc_state))
8048 dpll |= DPLL_SDVO_HIGH_SPEED;
8049
8050 /* compute bitmask from p1 value */
8051 if (IS_PINEVIEW(dev))
8052 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8053 else {
8054 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8055 if (IS_G4X(dev) && reduced_clock)
8056 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8057 }
8058 switch (clock->p2) {
8059 case 5:
8060 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8061 break;
8062 case 7:
8063 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8064 break;
8065 case 10:
8066 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8067 break;
8068 case 14:
8069 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8070 break;
8071 }
8072 if (INTEL_INFO(dev)->gen >= 4)
8073 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8074
8075 if (crtc_state->sdvo_tv_clock)
8076 dpll |= PLL_REF_INPUT_TVCLKINBC;
8077 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8078 intel_panel_use_ssc(dev_priv))
8079 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8080 else
8081 dpll |= PLL_REF_INPUT_DREFCLK;
8082
8083 dpll |= DPLL_VCO_ENABLE;
8084 crtc_state->dpll_hw_state.dpll = dpll;
8085
8086 if (INTEL_INFO(dev)->gen >= 4) {
8087 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8088 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8089 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8090 }
8091 }
8092
8093 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8094 struct intel_crtc_state *crtc_state,
8095 struct dpll *reduced_clock)
8096 {
8097 struct drm_device *dev = crtc->base.dev;
8098 struct drm_i915_private *dev_priv = to_i915(dev);
8099 u32 dpll;
8100 struct dpll *clock = &crtc_state->dpll;
8101
8102 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8103
8104 dpll = DPLL_VGA_MODE_DIS;
8105
8106 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8107 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8108 } else {
8109 if (clock->p1 == 2)
8110 dpll |= PLL_P1_DIVIDE_BY_TWO;
8111 else
8112 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8113 if (clock->p2 == 4)
8114 dpll |= PLL_P2_DIVIDE_BY_4;
8115 }
8116
8117 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8118 dpll |= DPLL_DVO_2X_MODE;
8119
8120 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8121 intel_panel_use_ssc(dev_priv))
8122 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8123 else
8124 dpll |= PLL_REF_INPUT_DREFCLK;
8125
8126 dpll |= DPLL_VCO_ENABLE;
8127 crtc_state->dpll_hw_state.dpll = dpll;
8128 }
8129
8130 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8131 {
8132 struct drm_device *dev = intel_crtc->base.dev;
8133 struct drm_i915_private *dev_priv = to_i915(dev);
8134 enum pipe pipe = intel_crtc->pipe;
8135 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8136 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8137 uint32_t crtc_vtotal, crtc_vblank_end;
8138 int vsyncshift = 0;
8139
8140 /* We need to be careful not to changed the adjusted mode, for otherwise
8141 * the hw state checker will get angry at the mismatch. */
8142 crtc_vtotal = adjusted_mode->crtc_vtotal;
8143 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8144
8145 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8146 /* the chip adds 2 halflines automatically */
8147 crtc_vtotal -= 1;
8148 crtc_vblank_end -= 1;
8149
8150 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8151 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8152 else
8153 vsyncshift = adjusted_mode->crtc_hsync_start -
8154 adjusted_mode->crtc_htotal / 2;
8155 if (vsyncshift < 0)
8156 vsyncshift += adjusted_mode->crtc_htotal;
8157 }
8158
8159 if (INTEL_INFO(dev)->gen > 3)
8160 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8161
8162 I915_WRITE(HTOTAL(cpu_transcoder),
8163 (adjusted_mode->crtc_hdisplay - 1) |
8164 ((adjusted_mode->crtc_htotal - 1) << 16));
8165 I915_WRITE(HBLANK(cpu_transcoder),
8166 (adjusted_mode->crtc_hblank_start - 1) |
8167 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8168 I915_WRITE(HSYNC(cpu_transcoder),
8169 (adjusted_mode->crtc_hsync_start - 1) |
8170 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8171
8172 I915_WRITE(VTOTAL(cpu_transcoder),
8173 (adjusted_mode->crtc_vdisplay - 1) |
8174 ((crtc_vtotal - 1) << 16));
8175 I915_WRITE(VBLANK(cpu_transcoder),
8176 (adjusted_mode->crtc_vblank_start - 1) |
8177 ((crtc_vblank_end - 1) << 16));
8178 I915_WRITE(VSYNC(cpu_transcoder),
8179 (adjusted_mode->crtc_vsync_start - 1) |
8180 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8181
8182 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8183 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8184 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8185 * bits. */
8186 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8187 (pipe == PIPE_B || pipe == PIPE_C))
8188 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8189
8190 }
8191
8192 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8193 {
8194 struct drm_device *dev = intel_crtc->base.dev;
8195 struct drm_i915_private *dev_priv = to_i915(dev);
8196 enum pipe pipe = intel_crtc->pipe;
8197
8198 /* pipesrc controls the size that is scaled from, which should
8199 * always be the user's requested size.
8200 */
8201 I915_WRITE(PIPESRC(pipe),
8202 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8203 (intel_crtc->config->pipe_src_h - 1));
8204 }
8205
8206 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8207 struct intel_crtc_state *pipe_config)
8208 {
8209 struct drm_device *dev = crtc->base.dev;
8210 struct drm_i915_private *dev_priv = to_i915(dev);
8211 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8212 uint32_t tmp;
8213
8214 tmp = I915_READ(HTOTAL(cpu_transcoder));
8215 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8216 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8217 tmp = I915_READ(HBLANK(cpu_transcoder));
8218 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8219 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8220 tmp = I915_READ(HSYNC(cpu_transcoder));
8221 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8222 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8223
8224 tmp = I915_READ(VTOTAL(cpu_transcoder));
8225 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8226 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8227 tmp = I915_READ(VBLANK(cpu_transcoder));
8228 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8229 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8230 tmp = I915_READ(VSYNC(cpu_transcoder));
8231 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8232 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8233
8234 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8235 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8236 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8237 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8238 }
8239 }
8240
8241 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8242 struct intel_crtc_state *pipe_config)
8243 {
8244 struct drm_device *dev = crtc->base.dev;
8245 struct drm_i915_private *dev_priv = to_i915(dev);
8246 u32 tmp;
8247
8248 tmp = I915_READ(PIPESRC(crtc->pipe));
8249 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8250 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8251
8252 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8253 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8254 }
8255
8256 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8257 struct intel_crtc_state *pipe_config)
8258 {
8259 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8260 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8261 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8262 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8263
8264 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8265 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8266 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8267 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8268
8269 mode->flags = pipe_config->base.adjusted_mode.flags;
8270 mode->type = DRM_MODE_TYPE_DRIVER;
8271
8272 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8273 mode->flags |= pipe_config->base.adjusted_mode.flags;
8274
8275 mode->hsync = drm_mode_hsync(mode);
8276 mode->vrefresh = drm_mode_vrefresh(mode);
8277 drm_mode_set_name(mode);
8278 }
8279
8280 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8281 {
8282 struct drm_device *dev = intel_crtc->base.dev;
8283 struct drm_i915_private *dev_priv = to_i915(dev);
8284 uint32_t pipeconf;
8285
8286 pipeconf = 0;
8287
8288 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8289 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8290 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8291
8292 if (intel_crtc->config->double_wide)
8293 pipeconf |= PIPECONF_DOUBLE_WIDE;
8294
8295 /* only g4x and later have fancy bpc/dither controls */
8296 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8297 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8298 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8299 pipeconf |= PIPECONF_DITHER_EN |
8300 PIPECONF_DITHER_TYPE_SP;
8301
8302 switch (intel_crtc->config->pipe_bpp) {
8303 case 18:
8304 pipeconf |= PIPECONF_6BPC;
8305 break;
8306 case 24:
8307 pipeconf |= PIPECONF_8BPC;
8308 break;
8309 case 30:
8310 pipeconf |= PIPECONF_10BPC;
8311 break;
8312 default:
8313 /* Case prevented by intel_choose_pipe_bpp_dither. */
8314 BUG();
8315 }
8316 }
8317
8318 if (HAS_PIPE_CXSR(dev)) {
8319 if (intel_crtc->lowfreq_avail) {
8320 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8321 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8322 } else {
8323 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8324 }
8325 }
8326
8327 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8328 if (INTEL_INFO(dev)->gen < 4 ||
8329 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8330 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8331 else
8332 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8333 } else
8334 pipeconf |= PIPECONF_PROGRESSIVE;
8335
8336 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8337 intel_crtc->config->limited_color_range)
8338 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8339
8340 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8341 POSTING_READ(PIPECONF(intel_crtc->pipe));
8342 }
8343
8344 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8345 struct intel_crtc_state *crtc_state)
8346 {
8347 struct drm_device *dev = crtc->base.dev;
8348 struct drm_i915_private *dev_priv = to_i915(dev);
8349 const struct intel_limit *limit;
8350 int refclk = 48000;
8351
8352 memset(&crtc_state->dpll_hw_state, 0,
8353 sizeof(crtc_state->dpll_hw_state));
8354
8355 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8356 if (intel_panel_use_ssc(dev_priv)) {
8357 refclk = dev_priv->vbt.lvds_ssc_freq;
8358 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8359 }
8360
8361 limit = &intel_limits_i8xx_lvds;
8362 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8363 limit = &intel_limits_i8xx_dvo;
8364 } else {
8365 limit = &intel_limits_i8xx_dac;
8366 }
8367
8368 if (!crtc_state->clock_set &&
8369 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8370 refclk, NULL, &crtc_state->dpll)) {
8371 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8372 return -EINVAL;
8373 }
8374
8375 i8xx_compute_dpll(crtc, crtc_state, NULL);
8376
8377 return 0;
8378 }
8379
8380 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8381 struct intel_crtc_state *crtc_state)
8382 {
8383 struct drm_device *dev = crtc->base.dev;
8384 struct drm_i915_private *dev_priv = to_i915(dev);
8385 const struct intel_limit *limit;
8386 int refclk = 96000;
8387
8388 memset(&crtc_state->dpll_hw_state, 0,
8389 sizeof(crtc_state->dpll_hw_state));
8390
8391 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8392 if (intel_panel_use_ssc(dev_priv)) {
8393 refclk = dev_priv->vbt.lvds_ssc_freq;
8394 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8395 }
8396
8397 if (intel_is_dual_link_lvds(dev))
8398 limit = &intel_limits_g4x_dual_channel_lvds;
8399 else
8400 limit = &intel_limits_g4x_single_channel_lvds;
8401 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8402 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8403 limit = &intel_limits_g4x_hdmi;
8404 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8405 limit = &intel_limits_g4x_sdvo;
8406 } else {
8407 /* The option is for other outputs */
8408 limit = &intel_limits_i9xx_sdvo;
8409 }
8410
8411 if (!crtc_state->clock_set &&
8412 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8413 refclk, NULL, &crtc_state->dpll)) {
8414 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8415 return -EINVAL;
8416 }
8417
8418 i9xx_compute_dpll(crtc, crtc_state, NULL);
8419
8420 return 0;
8421 }
8422
8423 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8424 struct intel_crtc_state *crtc_state)
8425 {
8426 struct drm_device *dev = crtc->base.dev;
8427 struct drm_i915_private *dev_priv = to_i915(dev);
8428 const struct intel_limit *limit;
8429 int refclk = 96000;
8430
8431 memset(&crtc_state->dpll_hw_state, 0,
8432 sizeof(crtc_state->dpll_hw_state));
8433
8434 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8435 if (intel_panel_use_ssc(dev_priv)) {
8436 refclk = dev_priv->vbt.lvds_ssc_freq;
8437 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8438 }
8439
8440 limit = &intel_limits_pineview_lvds;
8441 } else {
8442 limit = &intel_limits_pineview_sdvo;
8443 }
8444
8445 if (!crtc_state->clock_set &&
8446 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8447 refclk, NULL, &crtc_state->dpll)) {
8448 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8449 return -EINVAL;
8450 }
8451
8452 i9xx_compute_dpll(crtc, crtc_state, NULL);
8453
8454 return 0;
8455 }
8456
8457 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8458 struct intel_crtc_state *crtc_state)
8459 {
8460 struct drm_device *dev = crtc->base.dev;
8461 struct drm_i915_private *dev_priv = to_i915(dev);
8462 const struct intel_limit *limit;
8463 int refclk = 96000;
8464
8465 memset(&crtc_state->dpll_hw_state, 0,
8466 sizeof(crtc_state->dpll_hw_state));
8467
8468 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8469 if (intel_panel_use_ssc(dev_priv)) {
8470 refclk = dev_priv->vbt.lvds_ssc_freq;
8471 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8472 }
8473
8474 limit = &intel_limits_i9xx_lvds;
8475 } else {
8476 limit = &intel_limits_i9xx_sdvo;
8477 }
8478
8479 if (!crtc_state->clock_set &&
8480 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8481 refclk, NULL, &crtc_state->dpll)) {
8482 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8483 return -EINVAL;
8484 }
8485
8486 i9xx_compute_dpll(crtc, crtc_state, NULL);
8487
8488 return 0;
8489 }
8490
8491 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8492 struct intel_crtc_state *crtc_state)
8493 {
8494 int refclk = 100000;
8495 const struct intel_limit *limit = &intel_limits_chv;
8496
8497 memset(&crtc_state->dpll_hw_state, 0,
8498 sizeof(crtc_state->dpll_hw_state));
8499
8500 if (!crtc_state->clock_set &&
8501 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8502 refclk, NULL, &crtc_state->dpll)) {
8503 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8504 return -EINVAL;
8505 }
8506
8507 chv_compute_dpll(crtc, crtc_state);
8508
8509 return 0;
8510 }
8511
8512 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8513 struct intel_crtc_state *crtc_state)
8514 {
8515 int refclk = 100000;
8516 const struct intel_limit *limit = &intel_limits_vlv;
8517
8518 memset(&crtc_state->dpll_hw_state, 0,
8519 sizeof(crtc_state->dpll_hw_state));
8520
8521 if (!crtc_state->clock_set &&
8522 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8523 refclk, NULL, &crtc_state->dpll)) {
8524 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8525 return -EINVAL;
8526 }
8527
8528 vlv_compute_dpll(crtc, crtc_state);
8529
8530 return 0;
8531 }
8532
8533 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8534 struct intel_crtc_state *pipe_config)
8535 {
8536 struct drm_device *dev = crtc->base.dev;
8537 struct drm_i915_private *dev_priv = to_i915(dev);
8538 uint32_t tmp;
8539
8540 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8541 return;
8542
8543 tmp = I915_READ(PFIT_CONTROL);
8544 if (!(tmp & PFIT_ENABLE))
8545 return;
8546
8547 /* Check whether the pfit is attached to our pipe. */
8548 if (INTEL_INFO(dev)->gen < 4) {
8549 if (crtc->pipe != PIPE_B)
8550 return;
8551 } else {
8552 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8553 return;
8554 }
8555
8556 pipe_config->gmch_pfit.control = tmp;
8557 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8558 }
8559
8560 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8561 struct intel_crtc_state *pipe_config)
8562 {
8563 struct drm_device *dev = crtc->base.dev;
8564 struct drm_i915_private *dev_priv = to_i915(dev);
8565 int pipe = pipe_config->cpu_transcoder;
8566 struct dpll clock;
8567 u32 mdiv;
8568 int refclk = 100000;
8569
8570 /* In case of DSI, DPLL will not be used */
8571 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8572 return;
8573
8574 mutex_lock(&dev_priv->sb_lock);
8575 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8576 mutex_unlock(&dev_priv->sb_lock);
8577
8578 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8579 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8580 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8581 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8582 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8583
8584 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8585 }
8586
8587 static void
8588 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8589 struct intel_initial_plane_config *plane_config)
8590 {
8591 struct drm_device *dev = crtc->base.dev;
8592 struct drm_i915_private *dev_priv = to_i915(dev);
8593 u32 val, base, offset;
8594 int pipe = crtc->pipe, plane = crtc->plane;
8595 int fourcc, pixel_format;
8596 unsigned int aligned_height;
8597 struct drm_framebuffer *fb;
8598 struct intel_framebuffer *intel_fb;
8599
8600 val = I915_READ(DSPCNTR(plane));
8601 if (!(val & DISPLAY_PLANE_ENABLE))
8602 return;
8603
8604 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8605 if (!intel_fb) {
8606 DRM_DEBUG_KMS("failed to alloc fb\n");
8607 return;
8608 }
8609
8610 fb = &intel_fb->base;
8611
8612 if (INTEL_INFO(dev)->gen >= 4) {
8613 if (val & DISPPLANE_TILED) {
8614 plane_config->tiling = I915_TILING_X;
8615 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8616 }
8617 }
8618
8619 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8620 fourcc = i9xx_format_to_fourcc(pixel_format);
8621 fb->pixel_format = fourcc;
8622 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8623
8624 if (INTEL_INFO(dev)->gen >= 4) {
8625 if (plane_config->tiling)
8626 offset = I915_READ(DSPTILEOFF(plane));
8627 else
8628 offset = I915_READ(DSPLINOFF(plane));
8629 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8630 } else {
8631 base = I915_READ(DSPADDR(plane));
8632 }
8633 plane_config->base = base;
8634
8635 val = I915_READ(PIPESRC(pipe));
8636 fb->width = ((val >> 16) & 0xfff) + 1;
8637 fb->height = ((val >> 0) & 0xfff) + 1;
8638
8639 val = I915_READ(DSPSTRIDE(pipe));
8640 fb->pitches[0] = val & 0xffffffc0;
8641
8642 aligned_height = intel_fb_align_height(dev, fb->height,
8643 fb->pixel_format,
8644 fb->modifier[0]);
8645
8646 plane_config->size = fb->pitches[0] * aligned_height;
8647
8648 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8649 pipe_name(pipe), plane, fb->width, fb->height,
8650 fb->bits_per_pixel, base, fb->pitches[0],
8651 plane_config->size);
8652
8653 plane_config->fb = intel_fb;
8654 }
8655
8656 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8657 struct intel_crtc_state *pipe_config)
8658 {
8659 struct drm_device *dev = crtc->base.dev;
8660 struct drm_i915_private *dev_priv = to_i915(dev);
8661 int pipe = pipe_config->cpu_transcoder;
8662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8663 struct dpll clock;
8664 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8665 int refclk = 100000;
8666
8667 /* In case of DSI, DPLL will not be used */
8668 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8669 return;
8670
8671 mutex_lock(&dev_priv->sb_lock);
8672 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8673 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8674 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8675 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8676 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8677 mutex_unlock(&dev_priv->sb_lock);
8678
8679 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8680 clock.m2 = (pll_dw0 & 0xff) << 22;
8681 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8682 clock.m2 |= pll_dw2 & 0x3fffff;
8683 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8684 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8685 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8686
8687 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8688 }
8689
8690 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8691 struct intel_crtc_state *pipe_config)
8692 {
8693 struct drm_device *dev = crtc->base.dev;
8694 struct drm_i915_private *dev_priv = to_i915(dev);
8695 enum intel_display_power_domain power_domain;
8696 uint32_t tmp;
8697 bool ret;
8698
8699 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8700 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8701 return false;
8702
8703 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8704 pipe_config->shared_dpll = NULL;
8705
8706 ret = false;
8707
8708 tmp = I915_READ(PIPECONF(crtc->pipe));
8709 if (!(tmp & PIPECONF_ENABLE))
8710 goto out;
8711
8712 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8713 switch (tmp & PIPECONF_BPC_MASK) {
8714 case PIPECONF_6BPC:
8715 pipe_config->pipe_bpp = 18;
8716 break;
8717 case PIPECONF_8BPC:
8718 pipe_config->pipe_bpp = 24;
8719 break;
8720 case PIPECONF_10BPC:
8721 pipe_config->pipe_bpp = 30;
8722 break;
8723 default:
8724 break;
8725 }
8726 }
8727
8728 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8729 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8730 pipe_config->limited_color_range = true;
8731
8732 if (INTEL_INFO(dev)->gen < 4)
8733 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8734
8735 intel_get_pipe_timings(crtc, pipe_config);
8736 intel_get_pipe_src_size(crtc, pipe_config);
8737
8738 i9xx_get_pfit_config(crtc, pipe_config);
8739
8740 if (INTEL_INFO(dev)->gen >= 4) {
8741 /* No way to read it out on pipes B and C */
8742 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8743 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8744 else
8745 tmp = I915_READ(DPLL_MD(crtc->pipe));
8746 pipe_config->pixel_multiplier =
8747 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8748 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8749 pipe_config->dpll_hw_state.dpll_md = tmp;
8750 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8751 tmp = I915_READ(DPLL(crtc->pipe));
8752 pipe_config->pixel_multiplier =
8753 ((tmp & SDVO_MULTIPLIER_MASK)
8754 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8755 } else {
8756 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8757 * port and will be fixed up in the encoder->get_config
8758 * function. */
8759 pipe_config->pixel_multiplier = 1;
8760 }
8761 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8762 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8763 /*
8764 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8765 * on 830. Filter it out here so that we don't
8766 * report errors due to that.
8767 */
8768 if (IS_I830(dev))
8769 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8770
8771 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8772 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8773 } else {
8774 /* Mask out read-only status bits. */
8775 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8776 DPLL_PORTC_READY_MASK |
8777 DPLL_PORTB_READY_MASK);
8778 }
8779
8780 if (IS_CHERRYVIEW(dev))
8781 chv_crtc_clock_get(crtc, pipe_config);
8782 else if (IS_VALLEYVIEW(dev))
8783 vlv_crtc_clock_get(crtc, pipe_config);
8784 else
8785 i9xx_crtc_clock_get(crtc, pipe_config);
8786
8787 /*
8788 * Normally the dotclock is filled in by the encoder .get_config()
8789 * but in case the pipe is enabled w/o any ports we need a sane
8790 * default.
8791 */
8792 pipe_config->base.adjusted_mode.crtc_clock =
8793 pipe_config->port_clock / pipe_config->pixel_multiplier;
8794
8795 ret = true;
8796
8797 out:
8798 intel_display_power_put(dev_priv, power_domain);
8799
8800 return ret;
8801 }
8802
8803 static void ironlake_init_pch_refclk(struct drm_device *dev)
8804 {
8805 struct drm_i915_private *dev_priv = to_i915(dev);
8806 struct intel_encoder *encoder;
8807 int i;
8808 u32 val, final;
8809 bool has_lvds = false;
8810 bool has_cpu_edp = false;
8811 bool has_panel = false;
8812 bool has_ck505 = false;
8813 bool can_ssc = false;
8814 bool using_ssc_source = false;
8815
8816 /* We need to take the global config into account */
8817 for_each_intel_encoder(dev, encoder) {
8818 switch (encoder->type) {
8819 case INTEL_OUTPUT_LVDS:
8820 has_panel = true;
8821 has_lvds = true;
8822 break;
8823 case INTEL_OUTPUT_EDP:
8824 has_panel = true;
8825 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8826 has_cpu_edp = true;
8827 break;
8828 default:
8829 break;
8830 }
8831 }
8832
8833 if (HAS_PCH_IBX(dev)) {
8834 has_ck505 = dev_priv->vbt.display_clock_mode;
8835 can_ssc = has_ck505;
8836 } else {
8837 has_ck505 = false;
8838 can_ssc = true;
8839 }
8840
8841 /* Check if any DPLLs are using the SSC source */
8842 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8843 u32 temp = I915_READ(PCH_DPLL(i));
8844
8845 if (!(temp & DPLL_VCO_ENABLE))
8846 continue;
8847
8848 if ((temp & PLL_REF_INPUT_MASK) ==
8849 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8850 using_ssc_source = true;
8851 break;
8852 }
8853 }
8854
8855 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8856 has_panel, has_lvds, has_ck505, using_ssc_source);
8857
8858 /* Ironlake: try to setup display ref clock before DPLL
8859 * enabling. This is only under driver's control after
8860 * PCH B stepping, previous chipset stepping should be
8861 * ignoring this setting.
8862 */
8863 val = I915_READ(PCH_DREF_CONTROL);
8864
8865 /* As we must carefully and slowly disable/enable each source in turn,
8866 * compute the final state we want first and check if we need to
8867 * make any changes at all.
8868 */
8869 final = val;
8870 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8871 if (has_ck505)
8872 final |= DREF_NONSPREAD_CK505_ENABLE;
8873 else
8874 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8875
8876 final &= ~DREF_SSC_SOURCE_MASK;
8877 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8878 final &= ~DREF_SSC1_ENABLE;
8879
8880 if (has_panel) {
8881 final |= DREF_SSC_SOURCE_ENABLE;
8882
8883 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8884 final |= DREF_SSC1_ENABLE;
8885
8886 if (has_cpu_edp) {
8887 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8888 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8889 else
8890 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8891 } else
8892 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8893 } else if (using_ssc_source) {
8894 final |= DREF_SSC_SOURCE_ENABLE;
8895 final |= DREF_SSC1_ENABLE;
8896 }
8897
8898 if (final == val)
8899 return;
8900
8901 /* Always enable nonspread source */
8902 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8903
8904 if (has_ck505)
8905 val |= DREF_NONSPREAD_CK505_ENABLE;
8906 else
8907 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8908
8909 if (has_panel) {
8910 val &= ~DREF_SSC_SOURCE_MASK;
8911 val |= DREF_SSC_SOURCE_ENABLE;
8912
8913 /* SSC must be turned on before enabling the CPU output */
8914 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8915 DRM_DEBUG_KMS("Using SSC on panel\n");
8916 val |= DREF_SSC1_ENABLE;
8917 } else
8918 val &= ~DREF_SSC1_ENABLE;
8919
8920 /* Get SSC going before enabling the outputs */
8921 I915_WRITE(PCH_DREF_CONTROL, val);
8922 POSTING_READ(PCH_DREF_CONTROL);
8923 udelay(200);
8924
8925 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8926
8927 /* Enable CPU source on CPU attached eDP */
8928 if (has_cpu_edp) {
8929 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8930 DRM_DEBUG_KMS("Using SSC on eDP\n");
8931 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8932 } else
8933 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8934 } else
8935 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8936
8937 I915_WRITE(PCH_DREF_CONTROL, val);
8938 POSTING_READ(PCH_DREF_CONTROL);
8939 udelay(200);
8940 } else {
8941 DRM_DEBUG_KMS("Disabling CPU source output\n");
8942
8943 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8944
8945 /* Turn off CPU output */
8946 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8947
8948 I915_WRITE(PCH_DREF_CONTROL, val);
8949 POSTING_READ(PCH_DREF_CONTROL);
8950 udelay(200);
8951
8952 if (!using_ssc_source) {
8953 DRM_DEBUG_KMS("Disabling SSC source\n");
8954
8955 /* Turn off the SSC source */
8956 val &= ~DREF_SSC_SOURCE_MASK;
8957 val |= DREF_SSC_SOURCE_DISABLE;
8958
8959 /* Turn off SSC1 */
8960 val &= ~DREF_SSC1_ENABLE;
8961
8962 I915_WRITE(PCH_DREF_CONTROL, val);
8963 POSTING_READ(PCH_DREF_CONTROL);
8964 udelay(200);
8965 }
8966 }
8967
8968 BUG_ON(val != final);
8969 }
8970
8971 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8972 {
8973 uint32_t tmp;
8974
8975 tmp = I915_READ(SOUTH_CHICKEN2);
8976 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8977 I915_WRITE(SOUTH_CHICKEN2, tmp);
8978
8979 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8980 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8981 DRM_ERROR("FDI mPHY reset assert timeout\n");
8982
8983 tmp = I915_READ(SOUTH_CHICKEN2);
8984 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8985 I915_WRITE(SOUTH_CHICKEN2, tmp);
8986
8987 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8988 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8989 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8990 }
8991
8992 /* WaMPhyProgramming:hsw */
8993 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8994 {
8995 uint32_t tmp;
8996
8997 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8998 tmp &= ~(0xFF << 24);
8999 tmp |= (0x12 << 24);
9000 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9001
9002 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9003 tmp |= (1 << 11);
9004 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9005
9006 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9007 tmp |= (1 << 11);
9008 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9009
9010 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9011 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9012 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9013
9014 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9015 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9016 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9017
9018 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9019 tmp &= ~(7 << 13);
9020 tmp |= (5 << 13);
9021 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9022
9023 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9024 tmp &= ~(7 << 13);
9025 tmp |= (5 << 13);
9026 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9027
9028 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9029 tmp &= ~0xFF;
9030 tmp |= 0x1C;
9031 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9032
9033 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9034 tmp &= ~0xFF;
9035 tmp |= 0x1C;
9036 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9037
9038 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9039 tmp &= ~(0xFF << 16);
9040 tmp |= (0x1C << 16);
9041 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9042
9043 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9044 tmp &= ~(0xFF << 16);
9045 tmp |= (0x1C << 16);
9046 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9047
9048 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9049 tmp |= (1 << 27);
9050 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9051
9052 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9053 tmp |= (1 << 27);
9054 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9055
9056 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9057 tmp &= ~(0xF << 28);
9058 tmp |= (4 << 28);
9059 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9060
9061 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9062 tmp &= ~(0xF << 28);
9063 tmp |= (4 << 28);
9064 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9065 }
9066
9067 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9068 * Programming" based on the parameters passed:
9069 * - Sequence to enable CLKOUT_DP
9070 * - Sequence to enable CLKOUT_DP without spread
9071 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9072 */
9073 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9074 bool with_fdi)
9075 {
9076 struct drm_i915_private *dev_priv = to_i915(dev);
9077 uint32_t reg, tmp;
9078
9079 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9080 with_spread = true;
9081 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9082 with_fdi = false;
9083
9084 mutex_lock(&dev_priv->sb_lock);
9085
9086 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9087 tmp &= ~SBI_SSCCTL_DISABLE;
9088 tmp |= SBI_SSCCTL_PATHALT;
9089 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9090
9091 udelay(24);
9092
9093 if (with_spread) {
9094 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9095 tmp &= ~SBI_SSCCTL_PATHALT;
9096 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9097
9098 if (with_fdi) {
9099 lpt_reset_fdi_mphy(dev_priv);
9100 lpt_program_fdi_mphy(dev_priv);
9101 }
9102 }
9103
9104 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9105 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9106 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9107 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9108
9109 mutex_unlock(&dev_priv->sb_lock);
9110 }
9111
9112 /* Sequence to disable CLKOUT_DP */
9113 static void lpt_disable_clkout_dp(struct drm_device *dev)
9114 {
9115 struct drm_i915_private *dev_priv = to_i915(dev);
9116 uint32_t reg, tmp;
9117
9118 mutex_lock(&dev_priv->sb_lock);
9119
9120 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9121 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9122 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9123 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9124
9125 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9126 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9127 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9128 tmp |= SBI_SSCCTL_PATHALT;
9129 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9130 udelay(32);
9131 }
9132 tmp |= SBI_SSCCTL_DISABLE;
9133 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9134 }
9135
9136 mutex_unlock(&dev_priv->sb_lock);
9137 }
9138
9139 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9140
9141 static const uint16_t sscdivintphase[] = {
9142 [BEND_IDX( 50)] = 0x3B23,
9143 [BEND_IDX( 45)] = 0x3B23,
9144 [BEND_IDX( 40)] = 0x3C23,
9145 [BEND_IDX( 35)] = 0x3C23,
9146 [BEND_IDX( 30)] = 0x3D23,
9147 [BEND_IDX( 25)] = 0x3D23,
9148 [BEND_IDX( 20)] = 0x3E23,
9149 [BEND_IDX( 15)] = 0x3E23,
9150 [BEND_IDX( 10)] = 0x3F23,
9151 [BEND_IDX( 5)] = 0x3F23,
9152 [BEND_IDX( 0)] = 0x0025,
9153 [BEND_IDX( -5)] = 0x0025,
9154 [BEND_IDX(-10)] = 0x0125,
9155 [BEND_IDX(-15)] = 0x0125,
9156 [BEND_IDX(-20)] = 0x0225,
9157 [BEND_IDX(-25)] = 0x0225,
9158 [BEND_IDX(-30)] = 0x0325,
9159 [BEND_IDX(-35)] = 0x0325,
9160 [BEND_IDX(-40)] = 0x0425,
9161 [BEND_IDX(-45)] = 0x0425,
9162 [BEND_IDX(-50)] = 0x0525,
9163 };
9164
9165 /*
9166 * Bend CLKOUT_DP
9167 * steps -50 to 50 inclusive, in steps of 5
9168 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9169 * change in clock period = -(steps / 10) * 5.787 ps
9170 */
9171 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9172 {
9173 uint32_t tmp;
9174 int idx = BEND_IDX(steps);
9175
9176 if (WARN_ON(steps % 5 != 0))
9177 return;
9178
9179 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9180 return;
9181
9182 mutex_lock(&dev_priv->sb_lock);
9183
9184 if (steps % 10 != 0)
9185 tmp = 0xAAAAAAAB;
9186 else
9187 tmp = 0x00000000;
9188 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9189
9190 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9191 tmp &= 0xffff0000;
9192 tmp |= sscdivintphase[idx];
9193 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9194
9195 mutex_unlock(&dev_priv->sb_lock);
9196 }
9197
9198 #undef BEND_IDX
9199
9200 static void lpt_init_pch_refclk(struct drm_device *dev)
9201 {
9202 struct intel_encoder *encoder;
9203 bool has_vga = false;
9204
9205 for_each_intel_encoder(dev, encoder) {
9206 switch (encoder->type) {
9207 case INTEL_OUTPUT_ANALOG:
9208 has_vga = true;
9209 break;
9210 default:
9211 break;
9212 }
9213 }
9214
9215 if (has_vga) {
9216 lpt_bend_clkout_dp(to_i915(dev), 0);
9217 lpt_enable_clkout_dp(dev, true, true);
9218 } else {
9219 lpt_disable_clkout_dp(dev);
9220 }
9221 }
9222
9223 /*
9224 * Initialize reference clocks when the driver loads
9225 */
9226 void intel_init_pch_refclk(struct drm_device *dev)
9227 {
9228 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9229 ironlake_init_pch_refclk(dev);
9230 else if (HAS_PCH_LPT(dev))
9231 lpt_init_pch_refclk(dev);
9232 }
9233
9234 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9235 {
9236 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9238 int pipe = intel_crtc->pipe;
9239 uint32_t val;
9240
9241 val = 0;
9242
9243 switch (intel_crtc->config->pipe_bpp) {
9244 case 18:
9245 val |= PIPECONF_6BPC;
9246 break;
9247 case 24:
9248 val |= PIPECONF_8BPC;
9249 break;
9250 case 30:
9251 val |= PIPECONF_10BPC;
9252 break;
9253 case 36:
9254 val |= PIPECONF_12BPC;
9255 break;
9256 default:
9257 /* Case prevented by intel_choose_pipe_bpp_dither. */
9258 BUG();
9259 }
9260
9261 if (intel_crtc->config->dither)
9262 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9263
9264 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9265 val |= PIPECONF_INTERLACED_ILK;
9266 else
9267 val |= PIPECONF_PROGRESSIVE;
9268
9269 if (intel_crtc->config->limited_color_range)
9270 val |= PIPECONF_COLOR_RANGE_SELECT;
9271
9272 I915_WRITE(PIPECONF(pipe), val);
9273 POSTING_READ(PIPECONF(pipe));
9274 }
9275
9276 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9277 {
9278 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9280 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9281 u32 val = 0;
9282
9283 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9284 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9285
9286 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9287 val |= PIPECONF_INTERLACED_ILK;
9288 else
9289 val |= PIPECONF_PROGRESSIVE;
9290
9291 I915_WRITE(PIPECONF(cpu_transcoder), val);
9292 POSTING_READ(PIPECONF(cpu_transcoder));
9293 }
9294
9295 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9296 {
9297 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9299
9300 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9301 u32 val = 0;
9302
9303 switch (intel_crtc->config->pipe_bpp) {
9304 case 18:
9305 val |= PIPEMISC_DITHER_6_BPC;
9306 break;
9307 case 24:
9308 val |= PIPEMISC_DITHER_8_BPC;
9309 break;
9310 case 30:
9311 val |= PIPEMISC_DITHER_10_BPC;
9312 break;
9313 case 36:
9314 val |= PIPEMISC_DITHER_12_BPC;
9315 break;
9316 default:
9317 /* Case prevented by pipe_config_set_bpp. */
9318 BUG();
9319 }
9320
9321 if (intel_crtc->config->dither)
9322 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9323
9324 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9325 }
9326 }
9327
9328 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9329 {
9330 /*
9331 * Account for spread spectrum to avoid
9332 * oversubscribing the link. Max center spread
9333 * is 2.5%; use 5% for safety's sake.
9334 */
9335 u32 bps = target_clock * bpp * 21 / 20;
9336 return DIV_ROUND_UP(bps, link_bw * 8);
9337 }
9338
9339 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9340 {
9341 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9342 }
9343
9344 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9345 struct intel_crtc_state *crtc_state,
9346 struct dpll *reduced_clock)
9347 {
9348 struct drm_crtc *crtc = &intel_crtc->base;
9349 struct drm_device *dev = crtc->dev;
9350 struct drm_i915_private *dev_priv = to_i915(dev);
9351 u32 dpll, fp, fp2;
9352 int factor;
9353
9354 /* Enable autotuning of the PLL clock (if permissible) */
9355 factor = 21;
9356 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9357 if ((intel_panel_use_ssc(dev_priv) &&
9358 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9359 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9360 factor = 25;
9361 } else if (crtc_state->sdvo_tv_clock)
9362 factor = 20;
9363
9364 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9365
9366 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9367 fp |= FP_CB_TUNE;
9368
9369 if (reduced_clock) {
9370 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9371
9372 if (reduced_clock->m < factor * reduced_clock->n)
9373 fp2 |= FP_CB_TUNE;
9374 } else {
9375 fp2 = fp;
9376 }
9377
9378 dpll = 0;
9379
9380 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9381 dpll |= DPLLB_MODE_LVDS;
9382 else
9383 dpll |= DPLLB_MODE_DAC_SERIAL;
9384
9385 dpll |= (crtc_state->pixel_multiplier - 1)
9386 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9387
9388 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9389 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9390 dpll |= DPLL_SDVO_HIGH_SPEED;
9391
9392 if (intel_crtc_has_dp_encoder(crtc_state))
9393 dpll |= DPLL_SDVO_HIGH_SPEED;
9394
9395 /* compute bitmask from p1 value */
9396 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9397 /* also FPA1 */
9398 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9399
9400 switch (crtc_state->dpll.p2) {
9401 case 5:
9402 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9403 break;
9404 case 7:
9405 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9406 break;
9407 case 10:
9408 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9409 break;
9410 case 14:
9411 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9412 break;
9413 }
9414
9415 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9416 intel_panel_use_ssc(dev_priv))
9417 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9418 else
9419 dpll |= PLL_REF_INPUT_DREFCLK;
9420
9421 dpll |= DPLL_VCO_ENABLE;
9422
9423 crtc_state->dpll_hw_state.dpll = dpll;
9424 crtc_state->dpll_hw_state.fp0 = fp;
9425 crtc_state->dpll_hw_state.fp1 = fp2;
9426 }
9427
9428 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9429 struct intel_crtc_state *crtc_state)
9430 {
9431 struct drm_device *dev = crtc->base.dev;
9432 struct drm_i915_private *dev_priv = to_i915(dev);
9433 struct dpll reduced_clock;
9434 bool has_reduced_clock = false;
9435 struct intel_shared_dpll *pll;
9436 const struct intel_limit *limit;
9437 int refclk = 120000;
9438
9439 memset(&crtc_state->dpll_hw_state, 0,
9440 sizeof(crtc_state->dpll_hw_state));
9441
9442 crtc->lowfreq_avail = false;
9443
9444 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9445 if (!crtc_state->has_pch_encoder)
9446 return 0;
9447
9448 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9449 if (intel_panel_use_ssc(dev_priv)) {
9450 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9451 dev_priv->vbt.lvds_ssc_freq);
9452 refclk = dev_priv->vbt.lvds_ssc_freq;
9453 }
9454
9455 if (intel_is_dual_link_lvds(dev)) {
9456 if (refclk == 100000)
9457 limit = &intel_limits_ironlake_dual_lvds_100m;
9458 else
9459 limit = &intel_limits_ironlake_dual_lvds;
9460 } else {
9461 if (refclk == 100000)
9462 limit = &intel_limits_ironlake_single_lvds_100m;
9463 else
9464 limit = &intel_limits_ironlake_single_lvds;
9465 }
9466 } else {
9467 limit = &intel_limits_ironlake_dac;
9468 }
9469
9470 if (!crtc_state->clock_set &&
9471 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9472 refclk, NULL, &crtc_state->dpll)) {
9473 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9474 return -EINVAL;
9475 }
9476
9477 ironlake_compute_dpll(crtc, crtc_state,
9478 has_reduced_clock ? &reduced_clock : NULL);
9479
9480 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9481 if (pll == NULL) {
9482 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9483 pipe_name(crtc->pipe));
9484 return -EINVAL;
9485 }
9486
9487 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9488 has_reduced_clock)
9489 crtc->lowfreq_avail = true;
9490
9491 return 0;
9492 }
9493
9494 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9495 struct intel_link_m_n *m_n)
9496 {
9497 struct drm_device *dev = crtc->base.dev;
9498 struct drm_i915_private *dev_priv = to_i915(dev);
9499 enum pipe pipe = crtc->pipe;
9500
9501 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9502 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9503 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9504 & ~TU_SIZE_MASK;
9505 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9506 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9507 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9508 }
9509
9510 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9511 enum transcoder transcoder,
9512 struct intel_link_m_n *m_n,
9513 struct intel_link_m_n *m2_n2)
9514 {
9515 struct drm_device *dev = crtc->base.dev;
9516 struct drm_i915_private *dev_priv = to_i915(dev);
9517 enum pipe pipe = crtc->pipe;
9518
9519 if (INTEL_INFO(dev)->gen >= 5) {
9520 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9521 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9522 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9523 & ~TU_SIZE_MASK;
9524 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9525 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9526 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9527 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9528 * gen < 8) and if DRRS is supported (to make sure the
9529 * registers are not unnecessarily read).
9530 */
9531 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9532 crtc->config->has_drrs) {
9533 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9534 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9535 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9536 & ~TU_SIZE_MASK;
9537 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9538 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9539 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9540 }
9541 } else {
9542 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9543 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9544 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9545 & ~TU_SIZE_MASK;
9546 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9547 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9548 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9549 }
9550 }
9551
9552 void intel_dp_get_m_n(struct intel_crtc *crtc,
9553 struct intel_crtc_state *pipe_config)
9554 {
9555 if (pipe_config->has_pch_encoder)
9556 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9557 else
9558 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9559 &pipe_config->dp_m_n,
9560 &pipe_config->dp_m2_n2);
9561 }
9562
9563 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9564 struct intel_crtc_state *pipe_config)
9565 {
9566 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9567 &pipe_config->fdi_m_n, NULL);
9568 }
9569
9570 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9571 struct intel_crtc_state *pipe_config)
9572 {
9573 struct drm_device *dev = crtc->base.dev;
9574 struct drm_i915_private *dev_priv = to_i915(dev);
9575 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9576 uint32_t ps_ctrl = 0;
9577 int id = -1;
9578 int i;
9579
9580 /* find scaler attached to this pipe */
9581 for (i = 0; i < crtc->num_scalers; i++) {
9582 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9583 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9584 id = i;
9585 pipe_config->pch_pfit.enabled = true;
9586 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9587 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9588 break;
9589 }
9590 }
9591
9592 scaler_state->scaler_id = id;
9593 if (id >= 0) {
9594 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9595 } else {
9596 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9597 }
9598 }
9599
9600 static void
9601 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9602 struct intel_initial_plane_config *plane_config)
9603 {
9604 struct drm_device *dev = crtc->base.dev;
9605 struct drm_i915_private *dev_priv = to_i915(dev);
9606 u32 val, base, offset, stride_mult, tiling;
9607 int pipe = crtc->pipe;
9608 int fourcc, pixel_format;
9609 unsigned int aligned_height;
9610 struct drm_framebuffer *fb;
9611 struct intel_framebuffer *intel_fb;
9612
9613 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9614 if (!intel_fb) {
9615 DRM_DEBUG_KMS("failed to alloc fb\n");
9616 return;
9617 }
9618
9619 fb = &intel_fb->base;
9620
9621 val = I915_READ(PLANE_CTL(pipe, 0));
9622 if (!(val & PLANE_CTL_ENABLE))
9623 goto error;
9624
9625 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9626 fourcc = skl_format_to_fourcc(pixel_format,
9627 val & PLANE_CTL_ORDER_RGBX,
9628 val & PLANE_CTL_ALPHA_MASK);
9629 fb->pixel_format = fourcc;
9630 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9631
9632 tiling = val & PLANE_CTL_TILED_MASK;
9633 switch (tiling) {
9634 case PLANE_CTL_TILED_LINEAR:
9635 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9636 break;
9637 case PLANE_CTL_TILED_X:
9638 plane_config->tiling = I915_TILING_X;
9639 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9640 break;
9641 case PLANE_CTL_TILED_Y:
9642 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9643 break;
9644 case PLANE_CTL_TILED_YF:
9645 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9646 break;
9647 default:
9648 MISSING_CASE(tiling);
9649 goto error;
9650 }
9651
9652 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9653 plane_config->base = base;
9654
9655 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9656
9657 val = I915_READ(PLANE_SIZE(pipe, 0));
9658 fb->height = ((val >> 16) & 0xfff) + 1;
9659 fb->width = ((val >> 0) & 0x1fff) + 1;
9660
9661 val = I915_READ(PLANE_STRIDE(pipe, 0));
9662 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9663 fb->pixel_format);
9664 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9665
9666 aligned_height = intel_fb_align_height(dev, fb->height,
9667 fb->pixel_format,
9668 fb->modifier[0]);
9669
9670 plane_config->size = fb->pitches[0] * aligned_height;
9671
9672 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9673 pipe_name(pipe), fb->width, fb->height,
9674 fb->bits_per_pixel, base, fb->pitches[0],
9675 plane_config->size);
9676
9677 plane_config->fb = intel_fb;
9678 return;
9679
9680 error:
9681 kfree(fb);
9682 }
9683
9684 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9685 struct intel_crtc_state *pipe_config)
9686 {
9687 struct drm_device *dev = crtc->base.dev;
9688 struct drm_i915_private *dev_priv = to_i915(dev);
9689 uint32_t tmp;
9690
9691 tmp = I915_READ(PF_CTL(crtc->pipe));
9692
9693 if (tmp & PF_ENABLE) {
9694 pipe_config->pch_pfit.enabled = true;
9695 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9696 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9697
9698 /* We currently do not free assignements of panel fitters on
9699 * ivb/hsw (since we don't use the higher upscaling modes which
9700 * differentiates them) so just WARN about this case for now. */
9701 if (IS_GEN7(dev)) {
9702 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9703 PF_PIPE_SEL_IVB(crtc->pipe));
9704 }
9705 }
9706 }
9707
9708 static void
9709 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9710 struct intel_initial_plane_config *plane_config)
9711 {
9712 struct drm_device *dev = crtc->base.dev;
9713 struct drm_i915_private *dev_priv = to_i915(dev);
9714 u32 val, base, offset;
9715 int pipe = crtc->pipe;
9716 int fourcc, pixel_format;
9717 unsigned int aligned_height;
9718 struct drm_framebuffer *fb;
9719 struct intel_framebuffer *intel_fb;
9720
9721 val = I915_READ(DSPCNTR(pipe));
9722 if (!(val & DISPLAY_PLANE_ENABLE))
9723 return;
9724
9725 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9726 if (!intel_fb) {
9727 DRM_DEBUG_KMS("failed to alloc fb\n");
9728 return;
9729 }
9730
9731 fb = &intel_fb->base;
9732
9733 if (INTEL_INFO(dev)->gen >= 4) {
9734 if (val & DISPPLANE_TILED) {
9735 plane_config->tiling = I915_TILING_X;
9736 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9737 }
9738 }
9739
9740 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9741 fourcc = i9xx_format_to_fourcc(pixel_format);
9742 fb->pixel_format = fourcc;
9743 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9744
9745 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9746 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9747 offset = I915_READ(DSPOFFSET(pipe));
9748 } else {
9749 if (plane_config->tiling)
9750 offset = I915_READ(DSPTILEOFF(pipe));
9751 else
9752 offset = I915_READ(DSPLINOFF(pipe));
9753 }
9754 plane_config->base = base;
9755
9756 val = I915_READ(PIPESRC(pipe));
9757 fb->width = ((val >> 16) & 0xfff) + 1;
9758 fb->height = ((val >> 0) & 0xfff) + 1;
9759
9760 val = I915_READ(DSPSTRIDE(pipe));
9761 fb->pitches[0] = val & 0xffffffc0;
9762
9763 aligned_height = intel_fb_align_height(dev, fb->height,
9764 fb->pixel_format,
9765 fb->modifier[0]);
9766
9767 plane_config->size = fb->pitches[0] * aligned_height;
9768
9769 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9770 pipe_name(pipe), fb->width, fb->height,
9771 fb->bits_per_pixel, base, fb->pitches[0],
9772 plane_config->size);
9773
9774 plane_config->fb = intel_fb;
9775 }
9776
9777 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9778 struct intel_crtc_state *pipe_config)
9779 {
9780 struct drm_device *dev = crtc->base.dev;
9781 struct drm_i915_private *dev_priv = to_i915(dev);
9782 enum intel_display_power_domain power_domain;
9783 uint32_t tmp;
9784 bool ret;
9785
9786 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9787 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9788 return false;
9789
9790 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9791 pipe_config->shared_dpll = NULL;
9792
9793 ret = false;
9794 tmp = I915_READ(PIPECONF(crtc->pipe));
9795 if (!(tmp & PIPECONF_ENABLE))
9796 goto out;
9797
9798 switch (tmp & PIPECONF_BPC_MASK) {
9799 case PIPECONF_6BPC:
9800 pipe_config->pipe_bpp = 18;
9801 break;
9802 case PIPECONF_8BPC:
9803 pipe_config->pipe_bpp = 24;
9804 break;
9805 case PIPECONF_10BPC:
9806 pipe_config->pipe_bpp = 30;
9807 break;
9808 case PIPECONF_12BPC:
9809 pipe_config->pipe_bpp = 36;
9810 break;
9811 default:
9812 break;
9813 }
9814
9815 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9816 pipe_config->limited_color_range = true;
9817
9818 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9819 struct intel_shared_dpll *pll;
9820 enum intel_dpll_id pll_id;
9821
9822 pipe_config->has_pch_encoder = true;
9823
9824 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9825 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9826 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9827
9828 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9829
9830 if (HAS_PCH_IBX(dev_priv)) {
9831 /*
9832 * The pipe->pch transcoder and pch transcoder->pll
9833 * mapping is fixed.
9834 */
9835 pll_id = (enum intel_dpll_id) crtc->pipe;
9836 } else {
9837 tmp = I915_READ(PCH_DPLL_SEL);
9838 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9839 pll_id = DPLL_ID_PCH_PLL_B;
9840 else
9841 pll_id= DPLL_ID_PCH_PLL_A;
9842 }
9843
9844 pipe_config->shared_dpll =
9845 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9846 pll = pipe_config->shared_dpll;
9847
9848 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9849 &pipe_config->dpll_hw_state));
9850
9851 tmp = pipe_config->dpll_hw_state.dpll;
9852 pipe_config->pixel_multiplier =
9853 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9854 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9855
9856 ironlake_pch_clock_get(crtc, pipe_config);
9857 } else {
9858 pipe_config->pixel_multiplier = 1;
9859 }
9860
9861 intel_get_pipe_timings(crtc, pipe_config);
9862 intel_get_pipe_src_size(crtc, pipe_config);
9863
9864 ironlake_get_pfit_config(crtc, pipe_config);
9865
9866 ret = true;
9867
9868 out:
9869 intel_display_power_put(dev_priv, power_domain);
9870
9871 return ret;
9872 }
9873
9874 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9875 {
9876 struct drm_device *dev = &dev_priv->drm;
9877 struct intel_crtc *crtc;
9878
9879 for_each_intel_crtc(dev, crtc)
9880 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9881 pipe_name(crtc->pipe));
9882
9883 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9884 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9885 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9886 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9887 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9888 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9889 "CPU PWM1 enabled\n");
9890 if (IS_HASWELL(dev))
9891 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9892 "CPU PWM2 enabled\n");
9893 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9894 "PCH PWM1 enabled\n");
9895 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9896 "Utility pin enabled\n");
9897 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9898
9899 /*
9900 * In theory we can still leave IRQs enabled, as long as only the HPD
9901 * interrupts remain enabled. We used to check for that, but since it's
9902 * gen-specific and since we only disable LCPLL after we fully disable
9903 * the interrupts, the check below should be enough.
9904 */
9905 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9906 }
9907
9908 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9909 {
9910 struct drm_device *dev = &dev_priv->drm;
9911
9912 if (IS_HASWELL(dev))
9913 return I915_READ(D_COMP_HSW);
9914 else
9915 return I915_READ(D_COMP_BDW);
9916 }
9917
9918 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9919 {
9920 struct drm_device *dev = &dev_priv->drm;
9921
9922 if (IS_HASWELL(dev)) {
9923 mutex_lock(&dev_priv->rps.hw_lock);
9924 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9925 val))
9926 DRM_ERROR("Failed to write to D_COMP\n");
9927 mutex_unlock(&dev_priv->rps.hw_lock);
9928 } else {
9929 I915_WRITE(D_COMP_BDW, val);
9930 POSTING_READ(D_COMP_BDW);
9931 }
9932 }
9933
9934 /*
9935 * This function implements pieces of two sequences from BSpec:
9936 * - Sequence for display software to disable LCPLL
9937 * - Sequence for display software to allow package C8+
9938 * The steps implemented here are just the steps that actually touch the LCPLL
9939 * register. Callers should take care of disabling all the display engine
9940 * functions, doing the mode unset, fixing interrupts, etc.
9941 */
9942 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9943 bool switch_to_fclk, bool allow_power_down)
9944 {
9945 uint32_t val;
9946
9947 assert_can_disable_lcpll(dev_priv);
9948
9949 val = I915_READ(LCPLL_CTL);
9950
9951 if (switch_to_fclk) {
9952 val |= LCPLL_CD_SOURCE_FCLK;
9953 I915_WRITE(LCPLL_CTL, val);
9954
9955 if (wait_for_us(I915_READ(LCPLL_CTL) &
9956 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9957 DRM_ERROR("Switching to FCLK failed\n");
9958
9959 val = I915_READ(LCPLL_CTL);
9960 }
9961
9962 val |= LCPLL_PLL_DISABLE;
9963 I915_WRITE(LCPLL_CTL, val);
9964 POSTING_READ(LCPLL_CTL);
9965
9966 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9967 DRM_ERROR("LCPLL still locked\n");
9968
9969 val = hsw_read_dcomp(dev_priv);
9970 val |= D_COMP_COMP_DISABLE;
9971 hsw_write_dcomp(dev_priv, val);
9972 ndelay(100);
9973
9974 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9975 1))
9976 DRM_ERROR("D_COMP RCOMP still in progress\n");
9977
9978 if (allow_power_down) {
9979 val = I915_READ(LCPLL_CTL);
9980 val |= LCPLL_POWER_DOWN_ALLOW;
9981 I915_WRITE(LCPLL_CTL, val);
9982 POSTING_READ(LCPLL_CTL);
9983 }
9984 }
9985
9986 /*
9987 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9988 * source.
9989 */
9990 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9991 {
9992 uint32_t val;
9993
9994 val = I915_READ(LCPLL_CTL);
9995
9996 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9997 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9998 return;
9999
10000 /*
10001 * Make sure we're not on PC8 state before disabling PC8, otherwise
10002 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10003 */
10004 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10005
10006 if (val & LCPLL_POWER_DOWN_ALLOW) {
10007 val &= ~LCPLL_POWER_DOWN_ALLOW;
10008 I915_WRITE(LCPLL_CTL, val);
10009 POSTING_READ(LCPLL_CTL);
10010 }
10011
10012 val = hsw_read_dcomp(dev_priv);
10013 val |= D_COMP_COMP_FORCE;
10014 val &= ~D_COMP_COMP_DISABLE;
10015 hsw_write_dcomp(dev_priv, val);
10016
10017 val = I915_READ(LCPLL_CTL);
10018 val &= ~LCPLL_PLL_DISABLE;
10019 I915_WRITE(LCPLL_CTL, val);
10020
10021 if (intel_wait_for_register(dev_priv,
10022 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10023 5))
10024 DRM_ERROR("LCPLL not locked yet\n");
10025
10026 if (val & LCPLL_CD_SOURCE_FCLK) {
10027 val = I915_READ(LCPLL_CTL);
10028 val &= ~LCPLL_CD_SOURCE_FCLK;
10029 I915_WRITE(LCPLL_CTL, val);
10030
10031 if (wait_for_us((I915_READ(LCPLL_CTL) &
10032 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10033 DRM_ERROR("Switching back to LCPLL failed\n");
10034 }
10035
10036 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10037 intel_update_cdclk(&dev_priv->drm);
10038 }
10039
10040 /*
10041 * Package states C8 and deeper are really deep PC states that can only be
10042 * reached when all the devices on the system allow it, so even if the graphics
10043 * device allows PC8+, it doesn't mean the system will actually get to these
10044 * states. Our driver only allows PC8+ when going into runtime PM.
10045 *
10046 * The requirements for PC8+ are that all the outputs are disabled, the power
10047 * well is disabled and most interrupts are disabled, and these are also
10048 * requirements for runtime PM. When these conditions are met, we manually do
10049 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10050 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10051 * hang the machine.
10052 *
10053 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10054 * the state of some registers, so when we come back from PC8+ we need to
10055 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10056 * need to take care of the registers kept by RC6. Notice that this happens even
10057 * if we don't put the device in PCI D3 state (which is what currently happens
10058 * because of the runtime PM support).
10059 *
10060 * For more, read "Display Sequences for Package C8" on the hardware
10061 * documentation.
10062 */
10063 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10064 {
10065 struct drm_device *dev = &dev_priv->drm;
10066 uint32_t val;
10067
10068 DRM_DEBUG_KMS("Enabling package C8+\n");
10069
10070 if (HAS_PCH_LPT_LP(dev)) {
10071 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10072 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10073 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10074 }
10075
10076 lpt_disable_clkout_dp(dev);
10077 hsw_disable_lcpll(dev_priv, true, true);
10078 }
10079
10080 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10081 {
10082 struct drm_device *dev = &dev_priv->drm;
10083 uint32_t val;
10084
10085 DRM_DEBUG_KMS("Disabling package C8+\n");
10086
10087 hsw_restore_lcpll(dev_priv);
10088 lpt_init_pch_refclk(dev);
10089
10090 if (HAS_PCH_LPT_LP(dev)) {
10091 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10092 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10093 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10094 }
10095 }
10096
10097 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10098 {
10099 struct drm_device *dev = old_state->dev;
10100 struct intel_atomic_state *old_intel_state =
10101 to_intel_atomic_state(old_state);
10102 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10103
10104 bxt_set_cdclk(to_i915(dev), req_cdclk);
10105 }
10106
10107 /* compute the max rate for new configuration */
10108 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10109 {
10110 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10111 struct drm_i915_private *dev_priv = to_i915(state->dev);
10112 struct drm_crtc *crtc;
10113 struct drm_crtc_state *cstate;
10114 struct intel_crtc_state *crtc_state;
10115 unsigned max_pixel_rate = 0, i;
10116 enum pipe pipe;
10117
10118 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10119 sizeof(intel_state->min_pixclk));
10120
10121 for_each_crtc_in_state(state, crtc, cstate, i) {
10122 int pixel_rate;
10123
10124 crtc_state = to_intel_crtc_state(cstate);
10125 if (!crtc_state->base.enable) {
10126 intel_state->min_pixclk[i] = 0;
10127 continue;
10128 }
10129
10130 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10131
10132 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10133 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10134 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10135
10136 intel_state->min_pixclk[i] = pixel_rate;
10137 }
10138
10139 for_each_pipe(dev_priv, pipe)
10140 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10141
10142 return max_pixel_rate;
10143 }
10144
10145 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10146 {
10147 struct drm_i915_private *dev_priv = to_i915(dev);
10148 uint32_t val, data;
10149 int ret;
10150
10151 if (WARN((I915_READ(LCPLL_CTL) &
10152 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10153 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10154 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10155 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10156 "trying to change cdclk frequency with cdclk not enabled\n"))
10157 return;
10158
10159 mutex_lock(&dev_priv->rps.hw_lock);
10160 ret = sandybridge_pcode_write(dev_priv,
10161 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10162 mutex_unlock(&dev_priv->rps.hw_lock);
10163 if (ret) {
10164 DRM_ERROR("failed to inform pcode about cdclk change\n");
10165 return;
10166 }
10167
10168 val = I915_READ(LCPLL_CTL);
10169 val |= LCPLL_CD_SOURCE_FCLK;
10170 I915_WRITE(LCPLL_CTL, val);
10171
10172 if (wait_for_us(I915_READ(LCPLL_CTL) &
10173 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10174 DRM_ERROR("Switching to FCLK failed\n");
10175
10176 val = I915_READ(LCPLL_CTL);
10177 val &= ~LCPLL_CLK_FREQ_MASK;
10178
10179 switch (cdclk) {
10180 case 450000:
10181 val |= LCPLL_CLK_FREQ_450;
10182 data = 0;
10183 break;
10184 case 540000:
10185 val |= LCPLL_CLK_FREQ_54O_BDW;
10186 data = 1;
10187 break;
10188 case 337500:
10189 val |= LCPLL_CLK_FREQ_337_5_BDW;
10190 data = 2;
10191 break;
10192 case 675000:
10193 val |= LCPLL_CLK_FREQ_675_BDW;
10194 data = 3;
10195 break;
10196 default:
10197 WARN(1, "invalid cdclk frequency\n");
10198 return;
10199 }
10200
10201 I915_WRITE(LCPLL_CTL, val);
10202
10203 val = I915_READ(LCPLL_CTL);
10204 val &= ~LCPLL_CD_SOURCE_FCLK;
10205 I915_WRITE(LCPLL_CTL, val);
10206
10207 if (wait_for_us((I915_READ(LCPLL_CTL) &
10208 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10209 DRM_ERROR("Switching back to LCPLL failed\n");
10210
10211 mutex_lock(&dev_priv->rps.hw_lock);
10212 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10213 mutex_unlock(&dev_priv->rps.hw_lock);
10214
10215 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10216
10217 intel_update_cdclk(dev);
10218
10219 WARN(cdclk != dev_priv->cdclk_freq,
10220 "cdclk requested %d kHz but got %d kHz\n",
10221 cdclk, dev_priv->cdclk_freq);
10222 }
10223
10224 static int broadwell_calc_cdclk(int max_pixclk)
10225 {
10226 if (max_pixclk > 540000)
10227 return 675000;
10228 else if (max_pixclk > 450000)
10229 return 540000;
10230 else if (max_pixclk > 337500)
10231 return 450000;
10232 else
10233 return 337500;
10234 }
10235
10236 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10237 {
10238 struct drm_i915_private *dev_priv = to_i915(state->dev);
10239 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10240 int max_pixclk = ilk_max_pixel_rate(state);
10241 int cdclk;
10242
10243 /*
10244 * FIXME should also account for plane ratio
10245 * once 64bpp pixel formats are supported.
10246 */
10247 cdclk = broadwell_calc_cdclk(max_pixclk);
10248
10249 if (cdclk > dev_priv->max_cdclk_freq) {
10250 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10251 cdclk, dev_priv->max_cdclk_freq);
10252 return -EINVAL;
10253 }
10254
10255 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10256 if (!intel_state->active_crtcs)
10257 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10258
10259 return 0;
10260 }
10261
10262 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10263 {
10264 struct drm_device *dev = old_state->dev;
10265 struct intel_atomic_state *old_intel_state =
10266 to_intel_atomic_state(old_state);
10267 unsigned req_cdclk = old_intel_state->dev_cdclk;
10268
10269 broadwell_set_cdclk(dev, req_cdclk);
10270 }
10271
10272 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10273 {
10274 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10275 struct drm_i915_private *dev_priv = to_i915(state->dev);
10276 const int max_pixclk = ilk_max_pixel_rate(state);
10277 int vco = intel_state->cdclk_pll_vco;
10278 int cdclk;
10279
10280 /*
10281 * FIXME should also account for plane ratio
10282 * once 64bpp pixel formats are supported.
10283 */
10284 cdclk = skl_calc_cdclk(max_pixclk, vco);
10285
10286 /*
10287 * FIXME move the cdclk caclulation to
10288 * compute_config() so we can fail gracegully.
10289 */
10290 if (cdclk > dev_priv->max_cdclk_freq) {
10291 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10292 cdclk, dev_priv->max_cdclk_freq);
10293 cdclk = dev_priv->max_cdclk_freq;
10294 }
10295
10296 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10297 if (!intel_state->active_crtcs)
10298 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10299
10300 return 0;
10301 }
10302
10303 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10304 {
10305 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10306 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10307 unsigned int req_cdclk = intel_state->dev_cdclk;
10308 unsigned int req_vco = intel_state->cdclk_pll_vco;
10309
10310 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10311 }
10312
10313 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10314 struct intel_crtc_state *crtc_state)
10315 {
10316 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10317 if (!intel_ddi_pll_select(crtc, crtc_state))
10318 return -EINVAL;
10319 }
10320
10321 crtc->lowfreq_avail = false;
10322
10323 return 0;
10324 }
10325
10326 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10327 enum port port,
10328 struct intel_crtc_state *pipe_config)
10329 {
10330 enum intel_dpll_id id;
10331
10332 switch (port) {
10333 case PORT_A:
10334 pipe_config->ddi_pll_sel = SKL_DPLL0;
10335 id = DPLL_ID_SKL_DPLL0;
10336 break;
10337 case PORT_B:
10338 pipe_config->ddi_pll_sel = SKL_DPLL1;
10339 id = DPLL_ID_SKL_DPLL1;
10340 break;
10341 case PORT_C:
10342 pipe_config->ddi_pll_sel = SKL_DPLL2;
10343 id = DPLL_ID_SKL_DPLL2;
10344 break;
10345 default:
10346 DRM_ERROR("Incorrect port type\n");
10347 return;
10348 }
10349
10350 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10351 }
10352
10353 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10354 enum port port,
10355 struct intel_crtc_state *pipe_config)
10356 {
10357 enum intel_dpll_id id;
10358 u32 temp;
10359
10360 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10361 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
10362
10363 switch (pipe_config->ddi_pll_sel) {
10364 case SKL_DPLL0:
10365 id = DPLL_ID_SKL_DPLL0;
10366 break;
10367 case SKL_DPLL1:
10368 id = DPLL_ID_SKL_DPLL1;
10369 break;
10370 case SKL_DPLL2:
10371 id = DPLL_ID_SKL_DPLL2;
10372 break;
10373 case SKL_DPLL3:
10374 id = DPLL_ID_SKL_DPLL3;
10375 break;
10376 default:
10377 MISSING_CASE(pipe_config->ddi_pll_sel);
10378 return;
10379 }
10380
10381 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10382 }
10383
10384 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10385 enum port port,
10386 struct intel_crtc_state *pipe_config)
10387 {
10388 enum intel_dpll_id id;
10389
10390 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10391
10392 switch (pipe_config->ddi_pll_sel) {
10393 case PORT_CLK_SEL_WRPLL1:
10394 id = DPLL_ID_WRPLL1;
10395 break;
10396 case PORT_CLK_SEL_WRPLL2:
10397 id = DPLL_ID_WRPLL2;
10398 break;
10399 case PORT_CLK_SEL_SPLL:
10400 id = DPLL_ID_SPLL;
10401 break;
10402 case PORT_CLK_SEL_LCPLL_810:
10403 id = DPLL_ID_LCPLL_810;
10404 break;
10405 case PORT_CLK_SEL_LCPLL_1350:
10406 id = DPLL_ID_LCPLL_1350;
10407 break;
10408 case PORT_CLK_SEL_LCPLL_2700:
10409 id = DPLL_ID_LCPLL_2700;
10410 break;
10411 default:
10412 MISSING_CASE(pipe_config->ddi_pll_sel);
10413 /* fall through */
10414 case PORT_CLK_SEL_NONE:
10415 return;
10416 }
10417
10418 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10419 }
10420
10421 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10422 struct intel_crtc_state *pipe_config,
10423 unsigned long *power_domain_mask)
10424 {
10425 struct drm_device *dev = crtc->base.dev;
10426 struct drm_i915_private *dev_priv = to_i915(dev);
10427 enum intel_display_power_domain power_domain;
10428 u32 tmp;
10429
10430 /*
10431 * The pipe->transcoder mapping is fixed with the exception of the eDP
10432 * transcoder handled below.
10433 */
10434 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10435
10436 /*
10437 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10438 * consistency and less surprising code; it's in always on power).
10439 */
10440 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10441 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10442 enum pipe trans_edp_pipe;
10443 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10444 default:
10445 WARN(1, "unknown pipe linked to edp transcoder\n");
10446 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10447 case TRANS_DDI_EDP_INPUT_A_ON:
10448 trans_edp_pipe = PIPE_A;
10449 break;
10450 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10451 trans_edp_pipe = PIPE_B;
10452 break;
10453 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10454 trans_edp_pipe = PIPE_C;
10455 break;
10456 }
10457
10458 if (trans_edp_pipe == crtc->pipe)
10459 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10460 }
10461
10462 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10463 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10464 return false;
10465 *power_domain_mask |= BIT(power_domain);
10466
10467 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10468
10469 return tmp & PIPECONF_ENABLE;
10470 }
10471
10472 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10473 struct intel_crtc_state *pipe_config,
10474 unsigned long *power_domain_mask)
10475 {
10476 struct drm_device *dev = crtc->base.dev;
10477 struct drm_i915_private *dev_priv = to_i915(dev);
10478 enum intel_display_power_domain power_domain;
10479 enum port port;
10480 enum transcoder cpu_transcoder;
10481 u32 tmp;
10482
10483 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10484 if (port == PORT_A)
10485 cpu_transcoder = TRANSCODER_DSI_A;
10486 else
10487 cpu_transcoder = TRANSCODER_DSI_C;
10488
10489 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10490 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10491 continue;
10492 *power_domain_mask |= BIT(power_domain);
10493
10494 /*
10495 * The PLL needs to be enabled with a valid divider
10496 * configuration, otherwise accessing DSI registers will hang
10497 * the machine. See BSpec North Display Engine
10498 * registers/MIPI[BXT]. We can break out here early, since we
10499 * need the same DSI PLL to be enabled for both DSI ports.
10500 */
10501 if (!intel_dsi_pll_is_enabled(dev_priv))
10502 break;
10503
10504 /* XXX: this works for video mode only */
10505 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10506 if (!(tmp & DPI_ENABLE))
10507 continue;
10508
10509 tmp = I915_READ(MIPI_CTRL(port));
10510 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10511 continue;
10512
10513 pipe_config->cpu_transcoder = cpu_transcoder;
10514 break;
10515 }
10516
10517 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10518 }
10519
10520 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10521 struct intel_crtc_state *pipe_config)
10522 {
10523 struct drm_device *dev = crtc->base.dev;
10524 struct drm_i915_private *dev_priv = to_i915(dev);
10525 struct intel_shared_dpll *pll;
10526 enum port port;
10527 uint32_t tmp;
10528
10529 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10530
10531 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10532
10533 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10534 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10535 else if (IS_BROXTON(dev))
10536 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10537 else
10538 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10539
10540 pll = pipe_config->shared_dpll;
10541 if (pll) {
10542 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10543 &pipe_config->dpll_hw_state));
10544 }
10545
10546 /*
10547 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10548 * DDI E. So just check whether this pipe is wired to DDI E and whether
10549 * the PCH transcoder is on.
10550 */
10551 if (INTEL_INFO(dev)->gen < 9 &&
10552 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10553 pipe_config->has_pch_encoder = true;
10554
10555 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10556 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10557 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10558
10559 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10560 }
10561 }
10562
10563 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10564 struct intel_crtc_state *pipe_config)
10565 {
10566 struct drm_device *dev = crtc->base.dev;
10567 struct drm_i915_private *dev_priv = to_i915(dev);
10568 enum intel_display_power_domain power_domain;
10569 unsigned long power_domain_mask;
10570 bool active;
10571
10572 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10573 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10574 return false;
10575 power_domain_mask = BIT(power_domain);
10576
10577 pipe_config->shared_dpll = NULL;
10578
10579 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10580
10581 if (IS_BROXTON(dev_priv) &&
10582 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10583 WARN_ON(active);
10584 active = true;
10585 }
10586
10587 if (!active)
10588 goto out;
10589
10590 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10591 haswell_get_ddi_port_state(crtc, pipe_config);
10592 intel_get_pipe_timings(crtc, pipe_config);
10593 }
10594
10595 intel_get_pipe_src_size(crtc, pipe_config);
10596
10597 pipe_config->gamma_mode =
10598 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10599
10600 if (INTEL_INFO(dev)->gen >= 9) {
10601 skl_init_scalers(dev, crtc, pipe_config);
10602 }
10603
10604 if (INTEL_INFO(dev)->gen >= 9) {
10605 pipe_config->scaler_state.scaler_id = -1;
10606 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10607 }
10608
10609 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10610 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10611 power_domain_mask |= BIT(power_domain);
10612 if (INTEL_INFO(dev)->gen >= 9)
10613 skylake_get_pfit_config(crtc, pipe_config);
10614 else
10615 ironlake_get_pfit_config(crtc, pipe_config);
10616 }
10617
10618 if (IS_HASWELL(dev))
10619 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10620 (I915_READ(IPS_CTL) & IPS_ENABLE);
10621
10622 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10623 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10624 pipe_config->pixel_multiplier =
10625 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10626 } else {
10627 pipe_config->pixel_multiplier = 1;
10628 }
10629
10630 out:
10631 for_each_power_domain(power_domain, power_domain_mask)
10632 intel_display_power_put(dev_priv, power_domain);
10633
10634 return active;
10635 }
10636
10637 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10638 const struct intel_plane_state *plane_state)
10639 {
10640 struct drm_device *dev = crtc->dev;
10641 struct drm_i915_private *dev_priv = to_i915(dev);
10642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10643 uint32_t cntl = 0, size = 0;
10644
10645 if (plane_state && plane_state->base.visible) {
10646 unsigned int width = plane_state->base.crtc_w;
10647 unsigned int height = plane_state->base.crtc_h;
10648 unsigned int stride = roundup_pow_of_two(width) * 4;
10649
10650 switch (stride) {
10651 default:
10652 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10653 width, stride);
10654 stride = 256;
10655 /* fallthrough */
10656 case 256:
10657 case 512:
10658 case 1024:
10659 case 2048:
10660 break;
10661 }
10662
10663 cntl |= CURSOR_ENABLE |
10664 CURSOR_GAMMA_ENABLE |
10665 CURSOR_FORMAT_ARGB |
10666 CURSOR_STRIDE(stride);
10667
10668 size = (height << 12) | width;
10669 }
10670
10671 if (intel_crtc->cursor_cntl != 0 &&
10672 (intel_crtc->cursor_base != base ||
10673 intel_crtc->cursor_size != size ||
10674 intel_crtc->cursor_cntl != cntl)) {
10675 /* On these chipsets we can only modify the base/size/stride
10676 * whilst the cursor is disabled.
10677 */
10678 I915_WRITE(CURCNTR(PIPE_A), 0);
10679 POSTING_READ(CURCNTR(PIPE_A));
10680 intel_crtc->cursor_cntl = 0;
10681 }
10682
10683 if (intel_crtc->cursor_base != base) {
10684 I915_WRITE(CURBASE(PIPE_A), base);
10685 intel_crtc->cursor_base = base;
10686 }
10687
10688 if (intel_crtc->cursor_size != size) {
10689 I915_WRITE(CURSIZE, size);
10690 intel_crtc->cursor_size = size;
10691 }
10692
10693 if (intel_crtc->cursor_cntl != cntl) {
10694 I915_WRITE(CURCNTR(PIPE_A), cntl);
10695 POSTING_READ(CURCNTR(PIPE_A));
10696 intel_crtc->cursor_cntl = cntl;
10697 }
10698 }
10699
10700 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10701 const struct intel_plane_state *plane_state)
10702 {
10703 struct drm_device *dev = crtc->dev;
10704 struct drm_i915_private *dev_priv = to_i915(dev);
10705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10706 int pipe = intel_crtc->pipe;
10707 uint32_t cntl = 0;
10708
10709 if (plane_state && plane_state->base.visible) {
10710 cntl = MCURSOR_GAMMA_ENABLE;
10711 switch (plane_state->base.crtc_w) {
10712 case 64:
10713 cntl |= CURSOR_MODE_64_ARGB_AX;
10714 break;
10715 case 128:
10716 cntl |= CURSOR_MODE_128_ARGB_AX;
10717 break;
10718 case 256:
10719 cntl |= CURSOR_MODE_256_ARGB_AX;
10720 break;
10721 default:
10722 MISSING_CASE(plane_state->base.crtc_w);
10723 return;
10724 }
10725 cntl |= pipe << 28; /* Connect to correct pipe */
10726
10727 if (HAS_DDI(dev))
10728 cntl |= CURSOR_PIPE_CSC_ENABLE;
10729
10730 if (plane_state->base.rotation == DRM_ROTATE_180)
10731 cntl |= CURSOR_ROTATE_180;
10732 }
10733
10734 if (intel_crtc->cursor_cntl != cntl) {
10735 I915_WRITE(CURCNTR(pipe), cntl);
10736 POSTING_READ(CURCNTR(pipe));
10737 intel_crtc->cursor_cntl = cntl;
10738 }
10739
10740 /* and commit changes on next vblank */
10741 I915_WRITE(CURBASE(pipe), base);
10742 POSTING_READ(CURBASE(pipe));
10743
10744 intel_crtc->cursor_base = base;
10745 }
10746
10747 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10748 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10749 const struct intel_plane_state *plane_state)
10750 {
10751 struct drm_device *dev = crtc->dev;
10752 struct drm_i915_private *dev_priv = to_i915(dev);
10753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10754 int pipe = intel_crtc->pipe;
10755 u32 base = intel_crtc->cursor_addr;
10756 u32 pos = 0;
10757
10758 if (plane_state) {
10759 int x = plane_state->base.crtc_x;
10760 int y = plane_state->base.crtc_y;
10761
10762 if (x < 0) {
10763 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10764 x = -x;
10765 }
10766 pos |= x << CURSOR_X_SHIFT;
10767
10768 if (y < 0) {
10769 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10770 y = -y;
10771 }
10772 pos |= y << CURSOR_Y_SHIFT;
10773
10774 /* ILK+ do this automagically */
10775 if (HAS_GMCH_DISPLAY(dev) &&
10776 plane_state->base.rotation == DRM_ROTATE_180) {
10777 base += (plane_state->base.crtc_h *
10778 plane_state->base.crtc_w - 1) * 4;
10779 }
10780 }
10781
10782 I915_WRITE(CURPOS(pipe), pos);
10783
10784 if (IS_845G(dev) || IS_I865G(dev))
10785 i845_update_cursor(crtc, base, plane_state);
10786 else
10787 i9xx_update_cursor(crtc, base, plane_state);
10788 }
10789
10790 static bool cursor_size_ok(struct drm_device *dev,
10791 uint32_t width, uint32_t height)
10792 {
10793 if (width == 0 || height == 0)
10794 return false;
10795
10796 /*
10797 * 845g/865g are special in that they are only limited by
10798 * the width of their cursors, the height is arbitrary up to
10799 * the precision of the register. Everything else requires
10800 * square cursors, limited to a few power-of-two sizes.
10801 */
10802 if (IS_845G(dev) || IS_I865G(dev)) {
10803 if ((width & 63) != 0)
10804 return false;
10805
10806 if (width > (IS_845G(dev) ? 64 : 512))
10807 return false;
10808
10809 if (height > 1023)
10810 return false;
10811 } else {
10812 switch (width | height) {
10813 case 256:
10814 case 128:
10815 if (IS_GEN2(dev))
10816 return false;
10817 case 64:
10818 break;
10819 default:
10820 return false;
10821 }
10822 }
10823
10824 return true;
10825 }
10826
10827 /* VESA 640x480x72Hz mode to set on the pipe */
10828 static struct drm_display_mode load_detect_mode = {
10829 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10830 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10831 };
10832
10833 struct drm_framebuffer *
10834 __intel_framebuffer_create(struct drm_device *dev,
10835 struct drm_mode_fb_cmd2 *mode_cmd,
10836 struct drm_i915_gem_object *obj)
10837 {
10838 struct intel_framebuffer *intel_fb;
10839 int ret;
10840
10841 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10842 if (!intel_fb)
10843 return ERR_PTR(-ENOMEM);
10844
10845 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10846 if (ret)
10847 goto err;
10848
10849 return &intel_fb->base;
10850
10851 err:
10852 kfree(intel_fb);
10853 return ERR_PTR(ret);
10854 }
10855
10856 static struct drm_framebuffer *
10857 intel_framebuffer_create(struct drm_device *dev,
10858 struct drm_mode_fb_cmd2 *mode_cmd,
10859 struct drm_i915_gem_object *obj)
10860 {
10861 struct drm_framebuffer *fb;
10862 int ret;
10863
10864 ret = i915_mutex_lock_interruptible(dev);
10865 if (ret)
10866 return ERR_PTR(ret);
10867 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10868 mutex_unlock(&dev->struct_mutex);
10869
10870 return fb;
10871 }
10872
10873 static u32
10874 intel_framebuffer_pitch_for_width(int width, int bpp)
10875 {
10876 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10877 return ALIGN(pitch, 64);
10878 }
10879
10880 static u32
10881 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10882 {
10883 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10884 return PAGE_ALIGN(pitch * mode->vdisplay);
10885 }
10886
10887 static struct drm_framebuffer *
10888 intel_framebuffer_create_for_mode(struct drm_device *dev,
10889 struct drm_display_mode *mode,
10890 int depth, int bpp)
10891 {
10892 struct drm_framebuffer *fb;
10893 struct drm_i915_gem_object *obj;
10894 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10895
10896 obj = i915_gem_object_create(dev,
10897 intel_framebuffer_size_for_mode(mode, bpp));
10898 if (IS_ERR(obj))
10899 return ERR_CAST(obj);
10900
10901 mode_cmd.width = mode->hdisplay;
10902 mode_cmd.height = mode->vdisplay;
10903 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10904 bpp);
10905 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10906
10907 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10908 if (IS_ERR(fb))
10909 i915_gem_object_put_unlocked(obj);
10910
10911 return fb;
10912 }
10913
10914 static struct drm_framebuffer *
10915 mode_fits_in_fbdev(struct drm_device *dev,
10916 struct drm_display_mode *mode)
10917 {
10918 #ifdef CONFIG_DRM_FBDEV_EMULATION
10919 struct drm_i915_private *dev_priv = to_i915(dev);
10920 struct drm_i915_gem_object *obj;
10921 struct drm_framebuffer *fb;
10922
10923 if (!dev_priv->fbdev)
10924 return NULL;
10925
10926 if (!dev_priv->fbdev->fb)
10927 return NULL;
10928
10929 obj = dev_priv->fbdev->fb->obj;
10930 BUG_ON(!obj);
10931
10932 fb = &dev_priv->fbdev->fb->base;
10933 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10934 fb->bits_per_pixel))
10935 return NULL;
10936
10937 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10938 return NULL;
10939
10940 drm_framebuffer_reference(fb);
10941 return fb;
10942 #else
10943 return NULL;
10944 #endif
10945 }
10946
10947 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10948 struct drm_crtc *crtc,
10949 struct drm_display_mode *mode,
10950 struct drm_framebuffer *fb,
10951 int x, int y)
10952 {
10953 struct drm_plane_state *plane_state;
10954 int hdisplay, vdisplay;
10955 int ret;
10956
10957 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10958 if (IS_ERR(plane_state))
10959 return PTR_ERR(plane_state);
10960
10961 if (mode)
10962 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10963 else
10964 hdisplay = vdisplay = 0;
10965
10966 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10967 if (ret)
10968 return ret;
10969 drm_atomic_set_fb_for_plane(plane_state, fb);
10970 plane_state->crtc_x = 0;
10971 plane_state->crtc_y = 0;
10972 plane_state->crtc_w = hdisplay;
10973 plane_state->crtc_h = vdisplay;
10974 plane_state->src_x = x << 16;
10975 plane_state->src_y = y << 16;
10976 plane_state->src_w = hdisplay << 16;
10977 plane_state->src_h = vdisplay << 16;
10978
10979 return 0;
10980 }
10981
10982 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10983 struct drm_display_mode *mode,
10984 struct intel_load_detect_pipe *old,
10985 struct drm_modeset_acquire_ctx *ctx)
10986 {
10987 struct intel_crtc *intel_crtc;
10988 struct intel_encoder *intel_encoder =
10989 intel_attached_encoder(connector);
10990 struct drm_crtc *possible_crtc;
10991 struct drm_encoder *encoder = &intel_encoder->base;
10992 struct drm_crtc *crtc = NULL;
10993 struct drm_device *dev = encoder->dev;
10994 struct drm_framebuffer *fb;
10995 struct drm_mode_config *config = &dev->mode_config;
10996 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10997 struct drm_connector_state *connector_state;
10998 struct intel_crtc_state *crtc_state;
10999 int ret, i = -1;
11000
11001 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11002 connector->base.id, connector->name,
11003 encoder->base.id, encoder->name);
11004
11005 old->restore_state = NULL;
11006
11007 retry:
11008 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11009 if (ret)
11010 goto fail;
11011
11012 /*
11013 * Algorithm gets a little messy:
11014 *
11015 * - if the connector already has an assigned crtc, use it (but make
11016 * sure it's on first)
11017 *
11018 * - try to find the first unused crtc that can drive this connector,
11019 * and use that if we find one
11020 */
11021
11022 /* See if we already have a CRTC for this connector */
11023 if (connector->state->crtc) {
11024 crtc = connector->state->crtc;
11025
11026 ret = drm_modeset_lock(&crtc->mutex, ctx);
11027 if (ret)
11028 goto fail;
11029
11030 /* Make sure the crtc and connector are running */
11031 goto found;
11032 }
11033
11034 /* Find an unused one (if possible) */
11035 for_each_crtc(dev, possible_crtc) {
11036 i++;
11037 if (!(encoder->possible_crtcs & (1 << i)))
11038 continue;
11039
11040 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11041 if (ret)
11042 goto fail;
11043
11044 if (possible_crtc->state->enable) {
11045 drm_modeset_unlock(&possible_crtc->mutex);
11046 continue;
11047 }
11048
11049 crtc = possible_crtc;
11050 break;
11051 }
11052
11053 /*
11054 * If we didn't find an unused CRTC, don't use any.
11055 */
11056 if (!crtc) {
11057 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11058 goto fail;
11059 }
11060
11061 found:
11062 intel_crtc = to_intel_crtc(crtc);
11063
11064 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11065 if (ret)
11066 goto fail;
11067
11068 state = drm_atomic_state_alloc(dev);
11069 restore_state = drm_atomic_state_alloc(dev);
11070 if (!state || !restore_state) {
11071 ret = -ENOMEM;
11072 goto fail;
11073 }
11074
11075 state->acquire_ctx = ctx;
11076 restore_state->acquire_ctx = ctx;
11077
11078 connector_state = drm_atomic_get_connector_state(state, connector);
11079 if (IS_ERR(connector_state)) {
11080 ret = PTR_ERR(connector_state);
11081 goto fail;
11082 }
11083
11084 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11085 if (ret)
11086 goto fail;
11087
11088 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11089 if (IS_ERR(crtc_state)) {
11090 ret = PTR_ERR(crtc_state);
11091 goto fail;
11092 }
11093
11094 crtc_state->base.active = crtc_state->base.enable = true;
11095
11096 if (!mode)
11097 mode = &load_detect_mode;
11098
11099 /* We need a framebuffer large enough to accommodate all accesses
11100 * that the plane may generate whilst we perform load detection.
11101 * We can not rely on the fbcon either being present (we get called
11102 * during its initialisation to detect all boot displays, or it may
11103 * not even exist) or that it is large enough to satisfy the
11104 * requested mode.
11105 */
11106 fb = mode_fits_in_fbdev(dev, mode);
11107 if (fb == NULL) {
11108 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11109 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11110 } else
11111 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11112 if (IS_ERR(fb)) {
11113 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11114 goto fail;
11115 }
11116
11117 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11118 if (ret)
11119 goto fail;
11120
11121 drm_framebuffer_unreference(fb);
11122
11123 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11124 if (ret)
11125 goto fail;
11126
11127 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11128 if (!ret)
11129 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11130 if (!ret)
11131 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11132 if (ret) {
11133 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11134 goto fail;
11135 }
11136
11137 ret = drm_atomic_commit(state);
11138 if (ret) {
11139 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11140 goto fail;
11141 }
11142
11143 old->restore_state = restore_state;
11144
11145 /* let the connector get through one full cycle before testing */
11146 intel_wait_for_vblank(dev, intel_crtc->pipe);
11147 return true;
11148
11149 fail:
11150 drm_atomic_state_free(state);
11151 drm_atomic_state_free(restore_state);
11152 restore_state = state = NULL;
11153
11154 if (ret == -EDEADLK) {
11155 drm_modeset_backoff(ctx);
11156 goto retry;
11157 }
11158
11159 return false;
11160 }
11161
11162 void intel_release_load_detect_pipe(struct drm_connector *connector,
11163 struct intel_load_detect_pipe *old,
11164 struct drm_modeset_acquire_ctx *ctx)
11165 {
11166 struct intel_encoder *intel_encoder =
11167 intel_attached_encoder(connector);
11168 struct drm_encoder *encoder = &intel_encoder->base;
11169 struct drm_atomic_state *state = old->restore_state;
11170 int ret;
11171
11172 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11173 connector->base.id, connector->name,
11174 encoder->base.id, encoder->name);
11175
11176 if (!state)
11177 return;
11178
11179 ret = drm_atomic_commit(state);
11180 if (ret) {
11181 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11182 drm_atomic_state_free(state);
11183 }
11184 }
11185
11186 static int i9xx_pll_refclk(struct drm_device *dev,
11187 const struct intel_crtc_state *pipe_config)
11188 {
11189 struct drm_i915_private *dev_priv = to_i915(dev);
11190 u32 dpll = pipe_config->dpll_hw_state.dpll;
11191
11192 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11193 return dev_priv->vbt.lvds_ssc_freq;
11194 else if (HAS_PCH_SPLIT(dev))
11195 return 120000;
11196 else if (!IS_GEN2(dev))
11197 return 96000;
11198 else
11199 return 48000;
11200 }
11201
11202 /* Returns the clock of the currently programmed mode of the given pipe. */
11203 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11204 struct intel_crtc_state *pipe_config)
11205 {
11206 struct drm_device *dev = crtc->base.dev;
11207 struct drm_i915_private *dev_priv = to_i915(dev);
11208 int pipe = pipe_config->cpu_transcoder;
11209 u32 dpll = pipe_config->dpll_hw_state.dpll;
11210 u32 fp;
11211 struct dpll clock;
11212 int port_clock;
11213 int refclk = i9xx_pll_refclk(dev, pipe_config);
11214
11215 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11216 fp = pipe_config->dpll_hw_state.fp0;
11217 else
11218 fp = pipe_config->dpll_hw_state.fp1;
11219
11220 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11221 if (IS_PINEVIEW(dev)) {
11222 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11223 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11224 } else {
11225 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11226 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11227 }
11228
11229 if (!IS_GEN2(dev)) {
11230 if (IS_PINEVIEW(dev))
11231 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11232 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11233 else
11234 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11235 DPLL_FPA01_P1_POST_DIV_SHIFT);
11236
11237 switch (dpll & DPLL_MODE_MASK) {
11238 case DPLLB_MODE_DAC_SERIAL:
11239 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11240 5 : 10;
11241 break;
11242 case DPLLB_MODE_LVDS:
11243 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11244 7 : 14;
11245 break;
11246 default:
11247 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11248 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11249 return;
11250 }
11251
11252 if (IS_PINEVIEW(dev))
11253 port_clock = pnv_calc_dpll_params(refclk, &clock);
11254 else
11255 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11256 } else {
11257 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11258 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11259
11260 if (is_lvds) {
11261 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11262 DPLL_FPA01_P1_POST_DIV_SHIFT);
11263
11264 if (lvds & LVDS_CLKB_POWER_UP)
11265 clock.p2 = 7;
11266 else
11267 clock.p2 = 14;
11268 } else {
11269 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11270 clock.p1 = 2;
11271 else {
11272 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11273 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11274 }
11275 if (dpll & PLL_P2_DIVIDE_BY_4)
11276 clock.p2 = 4;
11277 else
11278 clock.p2 = 2;
11279 }
11280
11281 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11282 }
11283
11284 /*
11285 * This value includes pixel_multiplier. We will use
11286 * port_clock to compute adjusted_mode.crtc_clock in the
11287 * encoder's get_config() function.
11288 */
11289 pipe_config->port_clock = port_clock;
11290 }
11291
11292 int intel_dotclock_calculate(int link_freq,
11293 const struct intel_link_m_n *m_n)
11294 {
11295 /*
11296 * The calculation for the data clock is:
11297 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11298 * But we want to avoid losing precison if possible, so:
11299 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11300 *
11301 * and the link clock is simpler:
11302 * link_clock = (m * link_clock) / n
11303 */
11304
11305 if (!m_n->link_n)
11306 return 0;
11307
11308 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11309 }
11310
11311 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11312 struct intel_crtc_state *pipe_config)
11313 {
11314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11315
11316 /* read out port_clock from the DPLL */
11317 i9xx_crtc_clock_get(crtc, pipe_config);
11318
11319 /*
11320 * In case there is an active pipe without active ports,
11321 * we may need some idea for the dotclock anyway.
11322 * Calculate one based on the FDI configuration.
11323 */
11324 pipe_config->base.adjusted_mode.crtc_clock =
11325 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11326 &pipe_config->fdi_m_n);
11327 }
11328
11329 /** Returns the currently programmed mode of the given pipe. */
11330 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11331 struct drm_crtc *crtc)
11332 {
11333 struct drm_i915_private *dev_priv = to_i915(dev);
11334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11335 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11336 struct drm_display_mode *mode;
11337 struct intel_crtc_state *pipe_config;
11338 int htot = I915_READ(HTOTAL(cpu_transcoder));
11339 int hsync = I915_READ(HSYNC(cpu_transcoder));
11340 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11341 int vsync = I915_READ(VSYNC(cpu_transcoder));
11342 enum pipe pipe = intel_crtc->pipe;
11343
11344 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11345 if (!mode)
11346 return NULL;
11347
11348 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11349 if (!pipe_config) {
11350 kfree(mode);
11351 return NULL;
11352 }
11353
11354 /*
11355 * Construct a pipe_config sufficient for getting the clock info
11356 * back out of crtc_clock_get.
11357 *
11358 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11359 * to use a real value here instead.
11360 */
11361 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11362 pipe_config->pixel_multiplier = 1;
11363 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11364 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11365 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11366 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11367
11368 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11369 mode->hdisplay = (htot & 0xffff) + 1;
11370 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11371 mode->hsync_start = (hsync & 0xffff) + 1;
11372 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11373 mode->vdisplay = (vtot & 0xffff) + 1;
11374 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11375 mode->vsync_start = (vsync & 0xffff) + 1;
11376 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11377
11378 drm_mode_set_name(mode);
11379
11380 kfree(pipe_config);
11381
11382 return mode;
11383 }
11384
11385 static void intel_crtc_destroy(struct drm_crtc *crtc)
11386 {
11387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11388 struct drm_device *dev = crtc->dev;
11389 struct intel_flip_work *work;
11390
11391 spin_lock_irq(&dev->event_lock);
11392 work = intel_crtc->flip_work;
11393 intel_crtc->flip_work = NULL;
11394 spin_unlock_irq(&dev->event_lock);
11395
11396 if (work) {
11397 cancel_work_sync(&work->mmio_work);
11398 cancel_work_sync(&work->unpin_work);
11399 kfree(work);
11400 }
11401
11402 drm_crtc_cleanup(crtc);
11403
11404 kfree(intel_crtc);
11405 }
11406
11407 static void intel_unpin_work_fn(struct work_struct *__work)
11408 {
11409 struct intel_flip_work *work =
11410 container_of(__work, struct intel_flip_work, unpin_work);
11411 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11412 struct drm_device *dev = crtc->base.dev;
11413 struct drm_plane *primary = crtc->base.primary;
11414
11415 if (is_mmio_work(work))
11416 flush_work(&work->mmio_work);
11417
11418 mutex_lock(&dev->struct_mutex);
11419 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11420 i915_gem_object_put(work->pending_flip_obj);
11421 mutex_unlock(&dev->struct_mutex);
11422
11423 i915_gem_request_put(work->flip_queued_req);
11424
11425 intel_frontbuffer_flip_complete(to_i915(dev),
11426 to_intel_plane(primary)->frontbuffer_bit);
11427 intel_fbc_post_update(crtc);
11428 drm_framebuffer_unreference(work->old_fb);
11429
11430 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11431 atomic_dec(&crtc->unpin_work_count);
11432
11433 kfree(work);
11434 }
11435
11436 /* Is 'a' after or equal to 'b'? */
11437 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11438 {
11439 return !((a - b) & 0x80000000);
11440 }
11441
11442 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11443 struct intel_flip_work *work)
11444 {
11445 struct drm_device *dev = crtc->base.dev;
11446 struct drm_i915_private *dev_priv = to_i915(dev);
11447 unsigned reset_counter;
11448
11449 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11450 if (crtc->reset_counter != reset_counter)
11451 return true;
11452
11453 /*
11454 * The relevant registers doen't exist on pre-ctg.
11455 * As the flip done interrupt doesn't trigger for mmio
11456 * flips on gmch platforms, a flip count check isn't
11457 * really needed there. But since ctg has the registers,
11458 * include it in the check anyway.
11459 */
11460 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11461 return true;
11462
11463 /*
11464 * BDW signals flip done immediately if the plane
11465 * is disabled, even if the plane enable is already
11466 * armed to occur at the next vblank :(
11467 */
11468
11469 /*
11470 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11471 * used the same base address. In that case the mmio flip might
11472 * have completed, but the CS hasn't even executed the flip yet.
11473 *
11474 * A flip count check isn't enough as the CS might have updated
11475 * the base address just after start of vblank, but before we
11476 * managed to process the interrupt. This means we'd complete the
11477 * CS flip too soon.
11478 *
11479 * Combining both checks should get us a good enough result. It may
11480 * still happen that the CS flip has been executed, but has not
11481 * yet actually completed. But in case the base address is the same
11482 * anyway, we don't really care.
11483 */
11484 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11485 crtc->flip_work->gtt_offset &&
11486 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11487 crtc->flip_work->flip_count);
11488 }
11489
11490 static bool
11491 __pageflip_finished_mmio(struct intel_crtc *crtc,
11492 struct intel_flip_work *work)
11493 {
11494 /*
11495 * MMIO work completes when vblank is different from
11496 * flip_queued_vblank.
11497 *
11498 * Reset counter value doesn't matter, this is handled by
11499 * i915_wait_request finishing early, so no need to handle
11500 * reset here.
11501 */
11502 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11503 }
11504
11505
11506 static bool pageflip_finished(struct intel_crtc *crtc,
11507 struct intel_flip_work *work)
11508 {
11509 if (!atomic_read(&work->pending))
11510 return false;
11511
11512 smp_rmb();
11513
11514 if (is_mmio_work(work))
11515 return __pageflip_finished_mmio(crtc, work);
11516 else
11517 return __pageflip_finished_cs(crtc, work);
11518 }
11519
11520 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11521 {
11522 struct drm_device *dev = &dev_priv->drm;
11523 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11525 struct intel_flip_work *work;
11526 unsigned long flags;
11527
11528 /* Ignore early vblank irqs */
11529 if (!crtc)
11530 return;
11531
11532 /*
11533 * This is called both by irq handlers and the reset code (to complete
11534 * lost pageflips) so needs the full irqsave spinlocks.
11535 */
11536 spin_lock_irqsave(&dev->event_lock, flags);
11537 work = intel_crtc->flip_work;
11538
11539 if (work != NULL &&
11540 !is_mmio_work(work) &&
11541 pageflip_finished(intel_crtc, work))
11542 page_flip_completed(intel_crtc);
11543
11544 spin_unlock_irqrestore(&dev->event_lock, flags);
11545 }
11546
11547 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11548 {
11549 struct drm_device *dev = &dev_priv->drm;
11550 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11552 struct intel_flip_work *work;
11553 unsigned long flags;
11554
11555 /* Ignore early vblank irqs */
11556 if (!crtc)
11557 return;
11558
11559 /*
11560 * This is called both by irq handlers and the reset code (to complete
11561 * lost pageflips) so needs the full irqsave spinlocks.
11562 */
11563 spin_lock_irqsave(&dev->event_lock, flags);
11564 work = intel_crtc->flip_work;
11565
11566 if (work != NULL &&
11567 is_mmio_work(work) &&
11568 pageflip_finished(intel_crtc, work))
11569 page_flip_completed(intel_crtc);
11570
11571 spin_unlock_irqrestore(&dev->event_lock, flags);
11572 }
11573
11574 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11575 struct intel_flip_work *work)
11576 {
11577 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11578
11579 /* Ensure that the work item is consistent when activating it ... */
11580 smp_mb__before_atomic();
11581 atomic_set(&work->pending, 1);
11582 }
11583
11584 static int intel_gen2_queue_flip(struct drm_device *dev,
11585 struct drm_crtc *crtc,
11586 struct drm_framebuffer *fb,
11587 struct drm_i915_gem_object *obj,
11588 struct drm_i915_gem_request *req,
11589 uint32_t flags)
11590 {
11591 struct intel_ring *ring = req->ring;
11592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11593 u32 flip_mask;
11594 int ret;
11595
11596 ret = intel_ring_begin(req, 6);
11597 if (ret)
11598 return ret;
11599
11600 /* Can't queue multiple flips, so wait for the previous
11601 * one to finish before executing the next.
11602 */
11603 if (intel_crtc->plane)
11604 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11605 else
11606 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11607 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11608 intel_ring_emit(ring, MI_NOOP);
11609 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11610 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11611 intel_ring_emit(ring, fb->pitches[0]);
11612 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11613 intel_ring_emit(ring, 0); /* aux display base address, unused */
11614
11615 return 0;
11616 }
11617
11618 static int intel_gen3_queue_flip(struct drm_device *dev,
11619 struct drm_crtc *crtc,
11620 struct drm_framebuffer *fb,
11621 struct drm_i915_gem_object *obj,
11622 struct drm_i915_gem_request *req,
11623 uint32_t flags)
11624 {
11625 struct intel_ring *ring = req->ring;
11626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11627 u32 flip_mask;
11628 int ret;
11629
11630 ret = intel_ring_begin(req, 6);
11631 if (ret)
11632 return ret;
11633
11634 if (intel_crtc->plane)
11635 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11636 else
11637 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11638 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11639 intel_ring_emit(ring, MI_NOOP);
11640 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11641 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11642 intel_ring_emit(ring, fb->pitches[0]);
11643 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11644 intel_ring_emit(ring, MI_NOOP);
11645
11646 return 0;
11647 }
11648
11649 static int intel_gen4_queue_flip(struct drm_device *dev,
11650 struct drm_crtc *crtc,
11651 struct drm_framebuffer *fb,
11652 struct drm_i915_gem_object *obj,
11653 struct drm_i915_gem_request *req,
11654 uint32_t flags)
11655 {
11656 struct intel_ring *ring = req->ring;
11657 struct drm_i915_private *dev_priv = to_i915(dev);
11658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11659 uint32_t pf, pipesrc;
11660 int ret;
11661
11662 ret = intel_ring_begin(req, 4);
11663 if (ret)
11664 return ret;
11665
11666 /* i965+ uses the linear or tiled offsets from the
11667 * Display Registers (which do not change across a page-flip)
11668 * so we need only reprogram the base address.
11669 */
11670 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11671 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11672 intel_ring_emit(ring, fb->pitches[0]);
11673 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11674 intel_fb_modifier_to_tiling(fb->modifier[0]));
11675
11676 /* XXX Enabling the panel-fitter across page-flip is so far
11677 * untested on non-native modes, so ignore it for now.
11678 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11679 */
11680 pf = 0;
11681 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11682 intel_ring_emit(ring, pf | pipesrc);
11683
11684 return 0;
11685 }
11686
11687 static int intel_gen6_queue_flip(struct drm_device *dev,
11688 struct drm_crtc *crtc,
11689 struct drm_framebuffer *fb,
11690 struct drm_i915_gem_object *obj,
11691 struct drm_i915_gem_request *req,
11692 uint32_t flags)
11693 {
11694 struct intel_ring *ring = req->ring;
11695 struct drm_i915_private *dev_priv = to_i915(dev);
11696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11697 uint32_t pf, pipesrc;
11698 int ret;
11699
11700 ret = intel_ring_begin(req, 4);
11701 if (ret)
11702 return ret;
11703
11704 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11705 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11706 intel_ring_emit(ring, fb->pitches[0] |
11707 intel_fb_modifier_to_tiling(fb->modifier[0]));
11708 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11709
11710 /* Contrary to the suggestions in the documentation,
11711 * "Enable Panel Fitter" does not seem to be required when page
11712 * flipping with a non-native mode, and worse causes a normal
11713 * modeset to fail.
11714 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11715 */
11716 pf = 0;
11717 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11718 intel_ring_emit(ring, pf | pipesrc);
11719
11720 return 0;
11721 }
11722
11723 static int intel_gen7_queue_flip(struct drm_device *dev,
11724 struct drm_crtc *crtc,
11725 struct drm_framebuffer *fb,
11726 struct drm_i915_gem_object *obj,
11727 struct drm_i915_gem_request *req,
11728 uint32_t flags)
11729 {
11730 struct intel_ring *ring = req->ring;
11731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11732 uint32_t plane_bit = 0;
11733 int len, ret;
11734
11735 switch (intel_crtc->plane) {
11736 case PLANE_A:
11737 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11738 break;
11739 case PLANE_B:
11740 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11741 break;
11742 case PLANE_C:
11743 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11744 break;
11745 default:
11746 WARN_ONCE(1, "unknown plane in flip command\n");
11747 return -ENODEV;
11748 }
11749
11750 len = 4;
11751 if (req->engine->id == RCS) {
11752 len += 6;
11753 /*
11754 * On Gen 8, SRM is now taking an extra dword to accommodate
11755 * 48bits addresses, and we need a NOOP for the batch size to
11756 * stay even.
11757 */
11758 if (IS_GEN8(dev))
11759 len += 2;
11760 }
11761
11762 /*
11763 * BSpec MI_DISPLAY_FLIP for IVB:
11764 * "The full packet must be contained within the same cache line."
11765 *
11766 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11767 * cacheline, if we ever start emitting more commands before
11768 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11769 * then do the cacheline alignment, and finally emit the
11770 * MI_DISPLAY_FLIP.
11771 */
11772 ret = intel_ring_cacheline_align(req);
11773 if (ret)
11774 return ret;
11775
11776 ret = intel_ring_begin(req, len);
11777 if (ret)
11778 return ret;
11779
11780 /* Unmask the flip-done completion message. Note that the bspec says that
11781 * we should do this for both the BCS and RCS, and that we must not unmask
11782 * more than one flip event at any time (or ensure that one flip message
11783 * can be sent by waiting for flip-done prior to queueing new flips).
11784 * Experimentation says that BCS works despite DERRMR masking all
11785 * flip-done completion events and that unmasking all planes at once
11786 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11787 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11788 */
11789 if (req->engine->id == RCS) {
11790 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11791 intel_ring_emit_reg(ring, DERRMR);
11792 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11793 DERRMR_PIPEB_PRI_FLIP_DONE |
11794 DERRMR_PIPEC_PRI_FLIP_DONE));
11795 if (IS_GEN8(dev))
11796 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11797 MI_SRM_LRM_GLOBAL_GTT);
11798 else
11799 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11800 MI_SRM_LRM_GLOBAL_GTT);
11801 intel_ring_emit_reg(ring, DERRMR);
11802 intel_ring_emit(ring,
11803 i915_ggtt_offset(req->engine->scratch) + 256);
11804 if (IS_GEN8(dev)) {
11805 intel_ring_emit(ring, 0);
11806 intel_ring_emit(ring, MI_NOOP);
11807 }
11808 }
11809
11810 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11811 intel_ring_emit(ring, fb->pitches[0] |
11812 intel_fb_modifier_to_tiling(fb->modifier[0]));
11813 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11814 intel_ring_emit(ring, (MI_NOOP));
11815
11816 return 0;
11817 }
11818
11819 static bool use_mmio_flip(struct intel_engine_cs *engine,
11820 struct drm_i915_gem_object *obj)
11821 {
11822 struct reservation_object *resv;
11823
11824 /*
11825 * This is not being used for older platforms, because
11826 * non-availability of flip done interrupt forces us to use
11827 * CS flips. Older platforms derive flip done using some clever
11828 * tricks involving the flip_pending status bits and vblank irqs.
11829 * So using MMIO flips there would disrupt this mechanism.
11830 */
11831
11832 if (engine == NULL)
11833 return true;
11834
11835 if (INTEL_GEN(engine->i915) < 5)
11836 return false;
11837
11838 if (i915.use_mmio_flip < 0)
11839 return false;
11840 else if (i915.use_mmio_flip > 0)
11841 return true;
11842 else if (i915.enable_execlists)
11843 return true;
11844
11845 resv = i915_gem_object_get_dmabuf_resv(obj);
11846 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11847 return true;
11848
11849 return engine != i915_gem_active_get_engine(&obj->last_write,
11850 &obj->base.dev->struct_mutex);
11851 }
11852
11853 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11854 unsigned int rotation,
11855 struct intel_flip_work *work)
11856 {
11857 struct drm_device *dev = intel_crtc->base.dev;
11858 struct drm_i915_private *dev_priv = to_i915(dev);
11859 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11860 const enum pipe pipe = intel_crtc->pipe;
11861 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11862
11863 ctl = I915_READ(PLANE_CTL(pipe, 0));
11864 ctl &= ~PLANE_CTL_TILED_MASK;
11865 switch (fb->modifier[0]) {
11866 case DRM_FORMAT_MOD_NONE:
11867 break;
11868 case I915_FORMAT_MOD_X_TILED:
11869 ctl |= PLANE_CTL_TILED_X;
11870 break;
11871 case I915_FORMAT_MOD_Y_TILED:
11872 ctl |= PLANE_CTL_TILED_Y;
11873 break;
11874 case I915_FORMAT_MOD_Yf_TILED:
11875 ctl |= PLANE_CTL_TILED_YF;
11876 break;
11877 default:
11878 MISSING_CASE(fb->modifier[0]);
11879 }
11880
11881 /*
11882 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11883 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11884 */
11885 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11886 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11887
11888 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11889 POSTING_READ(PLANE_SURF(pipe, 0));
11890 }
11891
11892 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11893 struct intel_flip_work *work)
11894 {
11895 struct drm_device *dev = intel_crtc->base.dev;
11896 struct drm_i915_private *dev_priv = to_i915(dev);
11897 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11898 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11899 u32 dspcntr;
11900
11901 dspcntr = I915_READ(reg);
11902
11903 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
11904 dspcntr |= DISPPLANE_TILED;
11905 else
11906 dspcntr &= ~DISPPLANE_TILED;
11907
11908 I915_WRITE(reg, dspcntr);
11909
11910 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11911 POSTING_READ(DSPSURF(intel_crtc->plane));
11912 }
11913
11914 static void intel_mmio_flip_work_func(struct work_struct *w)
11915 {
11916 struct intel_flip_work *work =
11917 container_of(w, struct intel_flip_work, mmio_work);
11918 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11919 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11920 struct intel_framebuffer *intel_fb =
11921 to_intel_framebuffer(crtc->base.primary->fb);
11922 struct drm_i915_gem_object *obj = intel_fb->obj;
11923 struct reservation_object *resv;
11924
11925 if (work->flip_queued_req)
11926 WARN_ON(i915_wait_request(work->flip_queued_req,
11927 false, NULL,
11928 NO_WAITBOOST));
11929
11930 /* For framebuffer backed by dmabuf, wait for fence */
11931 resv = i915_gem_object_get_dmabuf_resv(obj);
11932 if (resv)
11933 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11934 MAX_SCHEDULE_TIMEOUT) < 0);
11935
11936 intel_pipe_update_start(crtc);
11937
11938 if (INTEL_GEN(dev_priv) >= 9)
11939 skl_do_mmio_flip(crtc, work->rotation, work);
11940 else
11941 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11942 ilk_do_mmio_flip(crtc, work);
11943
11944 intel_pipe_update_end(crtc, work);
11945 }
11946
11947 static int intel_default_queue_flip(struct drm_device *dev,
11948 struct drm_crtc *crtc,
11949 struct drm_framebuffer *fb,
11950 struct drm_i915_gem_object *obj,
11951 struct drm_i915_gem_request *req,
11952 uint32_t flags)
11953 {
11954 return -ENODEV;
11955 }
11956
11957 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11958 struct intel_crtc *intel_crtc,
11959 struct intel_flip_work *work)
11960 {
11961 u32 addr, vblank;
11962
11963 if (!atomic_read(&work->pending))
11964 return false;
11965
11966 smp_rmb();
11967
11968 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11969 if (work->flip_ready_vblank == 0) {
11970 if (work->flip_queued_req &&
11971 !i915_gem_request_completed(work->flip_queued_req))
11972 return false;
11973
11974 work->flip_ready_vblank = vblank;
11975 }
11976
11977 if (vblank - work->flip_ready_vblank < 3)
11978 return false;
11979
11980 /* Potential stall - if we see that the flip has happened,
11981 * assume a missed interrupt. */
11982 if (INTEL_GEN(dev_priv) >= 4)
11983 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11984 else
11985 addr = I915_READ(DSPADDR(intel_crtc->plane));
11986
11987 /* There is a potential issue here with a false positive after a flip
11988 * to the same address. We could address this by checking for a
11989 * non-incrementing frame counter.
11990 */
11991 return addr == work->gtt_offset;
11992 }
11993
11994 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11995 {
11996 struct drm_device *dev = &dev_priv->drm;
11997 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11999 struct intel_flip_work *work;
12000
12001 WARN_ON(!in_interrupt());
12002
12003 if (crtc == NULL)
12004 return;
12005
12006 spin_lock(&dev->event_lock);
12007 work = intel_crtc->flip_work;
12008
12009 if (work != NULL && !is_mmio_work(work) &&
12010 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12011 WARN_ONCE(1,
12012 "Kicking stuck page flip: queued at %d, now %d\n",
12013 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12014 page_flip_completed(intel_crtc);
12015 work = NULL;
12016 }
12017
12018 if (work != NULL && !is_mmio_work(work) &&
12019 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12020 intel_queue_rps_boost_for_request(work->flip_queued_req);
12021 spin_unlock(&dev->event_lock);
12022 }
12023
12024 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12025 struct drm_framebuffer *fb,
12026 struct drm_pending_vblank_event *event,
12027 uint32_t page_flip_flags)
12028 {
12029 struct drm_device *dev = crtc->dev;
12030 struct drm_i915_private *dev_priv = to_i915(dev);
12031 struct drm_framebuffer *old_fb = crtc->primary->fb;
12032 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12034 struct drm_plane *primary = crtc->primary;
12035 enum pipe pipe = intel_crtc->pipe;
12036 struct intel_flip_work *work;
12037 struct intel_engine_cs *engine;
12038 bool mmio_flip;
12039 struct drm_i915_gem_request *request;
12040 struct i915_vma *vma;
12041 int ret;
12042
12043 /*
12044 * drm_mode_page_flip_ioctl() should already catch this, but double
12045 * check to be safe. In the future we may enable pageflipping from
12046 * a disabled primary plane.
12047 */
12048 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12049 return -EBUSY;
12050
12051 /* Can't change pixel format via MI display flips. */
12052 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12053 return -EINVAL;
12054
12055 /*
12056 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12057 * Note that pitch changes could also affect these register.
12058 */
12059 if (INTEL_INFO(dev)->gen > 3 &&
12060 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12061 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12062 return -EINVAL;
12063
12064 if (i915_terminally_wedged(&dev_priv->gpu_error))
12065 goto out_hang;
12066
12067 work = kzalloc(sizeof(*work), GFP_KERNEL);
12068 if (work == NULL)
12069 return -ENOMEM;
12070
12071 work->event = event;
12072 work->crtc = crtc;
12073 work->old_fb = old_fb;
12074 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12075
12076 ret = drm_crtc_vblank_get(crtc);
12077 if (ret)
12078 goto free_work;
12079
12080 /* We borrow the event spin lock for protecting flip_work */
12081 spin_lock_irq(&dev->event_lock);
12082 if (intel_crtc->flip_work) {
12083 /* Before declaring the flip queue wedged, check if
12084 * the hardware completed the operation behind our backs.
12085 */
12086 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12087 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12088 page_flip_completed(intel_crtc);
12089 } else {
12090 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12091 spin_unlock_irq(&dev->event_lock);
12092
12093 drm_crtc_vblank_put(crtc);
12094 kfree(work);
12095 return -EBUSY;
12096 }
12097 }
12098 intel_crtc->flip_work = work;
12099 spin_unlock_irq(&dev->event_lock);
12100
12101 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12102 flush_workqueue(dev_priv->wq);
12103
12104 /* Reference the objects for the scheduled work. */
12105 drm_framebuffer_reference(work->old_fb);
12106
12107 crtc->primary->fb = fb;
12108 update_state_fb(crtc->primary);
12109
12110 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12111 to_intel_plane_state(primary->state));
12112
12113 work->pending_flip_obj = i915_gem_object_get(obj);
12114
12115 ret = i915_mutex_lock_interruptible(dev);
12116 if (ret)
12117 goto cleanup;
12118
12119 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
12120 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
12121 ret = -EIO;
12122 goto cleanup;
12123 }
12124
12125 atomic_inc(&intel_crtc->unpin_work_count);
12126
12127 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12128 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12129
12130 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12131 engine = &dev_priv->engine[BCS];
12132 if (fb->modifier[0] != old_fb->modifier[0])
12133 /* vlv: DISPLAY_FLIP fails to change tiling */
12134 engine = NULL;
12135 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12136 engine = &dev_priv->engine[BCS];
12137 } else if (INTEL_INFO(dev)->gen >= 7) {
12138 engine = i915_gem_active_get_engine(&obj->last_write,
12139 &obj->base.dev->struct_mutex);
12140 if (engine == NULL || engine->id != RCS)
12141 engine = &dev_priv->engine[BCS];
12142 } else {
12143 engine = &dev_priv->engine[RCS];
12144 }
12145
12146 mmio_flip = use_mmio_flip(engine, obj);
12147
12148 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12149 if (IS_ERR(vma)) {
12150 ret = PTR_ERR(vma);
12151 goto cleanup_pending;
12152 }
12153
12154 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12155 work->gtt_offset += intel_crtc->dspaddr_offset;
12156 work->rotation = crtc->primary->state->rotation;
12157
12158 if (mmio_flip) {
12159 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12160
12161 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12162 &obj->base.dev->struct_mutex);
12163 schedule_work(&work->mmio_work);
12164 } else {
12165 request = i915_gem_request_alloc(engine, engine->last_context);
12166 if (IS_ERR(request)) {
12167 ret = PTR_ERR(request);
12168 goto cleanup_unpin;
12169 }
12170
12171 ret = i915_gem_object_sync(obj, request);
12172 if (ret)
12173 goto cleanup_request;
12174
12175 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12176 page_flip_flags);
12177 if (ret)
12178 goto cleanup_request;
12179
12180 intel_mark_page_flip_active(intel_crtc, work);
12181
12182 work->flip_queued_req = i915_gem_request_get(request);
12183 i915_add_request_no_flush(request);
12184 }
12185
12186 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12187 to_intel_plane(primary)->frontbuffer_bit);
12188 mutex_unlock(&dev->struct_mutex);
12189
12190 intel_frontbuffer_flip_prepare(to_i915(dev),
12191 to_intel_plane(primary)->frontbuffer_bit);
12192
12193 trace_i915_flip_request(intel_crtc->plane, obj);
12194
12195 return 0;
12196
12197 cleanup_request:
12198 i915_add_request_no_flush(request);
12199 cleanup_unpin:
12200 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12201 cleanup_pending:
12202 atomic_dec(&intel_crtc->unpin_work_count);
12203 mutex_unlock(&dev->struct_mutex);
12204 cleanup:
12205 crtc->primary->fb = old_fb;
12206 update_state_fb(crtc->primary);
12207
12208 i915_gem_object_put_unlocked(obj);
12209 drm_framebuffer_unreference(work->old_fb);
12210
12211 spin_lock_irq(&dev->event_lock);
12212 intel_crtc->flip_work = NULL;
12213 spin_unlock_irq(&dev->event_lock);
12214
12215 drm_crtc_vblank_put(crtc);
12216 free_work:
12217 kfree(work);
12218
12219 if (ret == -EIO) {
12220 struct drm_atomic_state *state;
12221 struct drm_plane_state *plane_state;
12222
12223 out_hang:
12224 state = drm_atomic_state_alloc(dev);
12225 if (!state)
12226 return -ENOMEM;
12227 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12228
12229 retry:
12230 plane_state = drm_atomic_get_plane_state(state, primary);
12231 ret = PTR_ERR_OR_ZERO(plane_state);
12232 if (!ret) {
12233 drm_atomic_set_fb_for_plane(plane_state, fb);
12234
12235 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12236 if (!ret)
12237 ret = drm_atomic_commit(state);
12238 }
12239
12240 if (ret == -EDEADLK) {
12241 drm_modeset_backoff(state->acquire_ctx);
12242 drm_atomic_state_clear(state);
12243 goto retry;
12244 }
12245
12246 if (ret)
12247 drm_atomic_state_free(state);
12248
12249 if (ret == 0 && event) {
12250 spin_lock_irq(&dev->event_lock);
12251 drm_crtc_send_vblank_event(crtc, event);
12252 spin_unlock_irq(&dev->event_lock);
12253 }
12254 }
12255 return ret;
12256 }
12257
12258
12259 /**
12260 * intel_wm_need_update - Check whether watermarks need updating
12261 * @plane: drm plane
12262 * @state: new plane state
12263 *
12264 * Check current plane state versus the new one to determine whether
12265 * watermarks need to be recalculated.
12266 *
12267 * Returns true or false.
12268 */
12269 static bool intel_wm_need_update(struct drm_plane *plane,
12270 struct drm_plane_state *state)
12271 {
12272 struct intel_plane_state *new = to_intel_plane_state(state);
12273 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12274
12275 /* Update watermarks on tiling or size changes. */
12276 if (new->base.visible != cur->base.visible)
12277 return true;
12278
12279 if (!cur->base.fb || !new->base.fb)
12280 return false;
12281
12282 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12283 cur->base.rotation != new->base.rotation ||
12284 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12285 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12286 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12287 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12288 return true;
12289
12290 return false;
12291 }
12292
12293 static bool needs_scaling(struct intel_plane_state *state)
12294 {
12295 int src_w = drm_rect_width(&state->base.src) >> 16;
12296 int src_h = drm_rect_height(&state->base.src) >> 16;
12297 int dst_w = drm_rect_width(&state->base.dst);
12298 int dst_h = drm_rect_height(&state->base.dst);
12299
12300 return (src_w != dst_w || src_h != dst_h);
12301 }
12302
12303 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12304 struct drm_plane_state *plane_state)
12305 {
12306 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12307 struct drm_crtc *crtc = crtc_state->crtc;
12308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12309 struct drm_plane *plane = plane_state->plane;
12310 struct drm_device *dev = crtc->dev;
12311 struct drm_i915_private *dev_priv = to_i915(dev);
12312 struct intel_plane_state *old_plane_state =
12313 to_intel_plane_state(plane->state);
12314 bool mode_changed = needs_modeset(crtc_state);
12315 bool was_crtc_enabled = crtc->state->active;
12316 bool is_crtc_enabled = crtc_state->active;
12317 bool turn_off, turn_on, visible, was_visible;
12318 struct drm_framebuffer *fb = plane_state->fb;
12319 int ret;
12320
12321 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12322 ret = skl_update_scaler_plane(
12323 to_intel_crtc_state(crtc_state),
12324 to_intel_plane_state(plane_state));
12325 if (ret)
12326 return ret;
12327 }
12328
12329 was_visible = old_plane_state->base.visible;
12330 visible = to_intel_plane_state(plane_state)->base.visible;
12331
12332 if (!was_crtc_enabled && WARN_ON(was_visible))
12333 was_visible = false;
12334
12335 /*
12336 * Visibility is calculated as if the crtc was on, but
12337 * after scaler setup everything depends on it being off
12338 * when the crtc isn't active.
12339 *
12340 * FIXME this is wrong for watermarks. Watermarks should also
12341 * be computed as if the pipe would be active. Perhaps move
12342 * per-plane wm computation to the .check_plane() hook, and
12343 * only combine the results from all planes in the current place?
12344 */
12345 if (!is_crtc_enabled)
12346 to_intel_plane_state(plane_state)->base.visible = visible = false;
12347
12348 if (!was_visible && !visible)
12349 return 0;
12350
12351 if (fb != old_plane_state->base.fb)
12352 pipe_config->fb_changed = true;
12353
12354 turn_off = was_visible && (!visible || mode_changed);
12355 turn_on = visible && (!was_visible || mode_changed);
12356
12357 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12358 intel_crtc->base.base.id,
12359 intel_crtc->base.name,
12360 plane->base.id, plane->name,
12361 fb ? fb->base.id : -1);
12362
12363 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12364 plane->base.id, plane->name,
12365 was_visible, visible,
12366 turn_off, turn_on, mode_changed);
12367
12368 if (turn_on) {
12369 pipe_config->update_wm_pre = true;
12370
12371 /* must disable cxsr around plane enable/disable */
12372 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12373 pipe_config->disable_cxsr = true;
12374 } else if (turn_off) {
12375 pipe_config->update_wm_post = true;
12376
12377 /* must disable cxsr around plane enable/disable */
12378 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12379 pipe_config->disable_cxsr = true;
12380 } else if (intel_wm_need_update(plane, plane_state)) {
12381 /* FIXME bollocks */
12382 pipe_config->update_wm_pre = true;
12383 pipe_config->update_wm_post = true;
12384 }
12385
12386 /* Pre-gen9 platforms need two-step watermark updates */
12387 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12388 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12389 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12390
12391 if (visible || was_visible)
12392 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12393
12394 /*
12395 * WaCxSRDisabledForSpriteScaling:ivb
12396 *
12397 * cstate->update_wm was already set above, so this flag will
12398 * take effect when we commit and program watermarks.
12399 */
12400 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12401 needs_scaling(to_intel_plane_state(plane_state)) &&
12402 !needs_scaling(old_plane_state))
12403 pipe_config->disable_lp_wm = true;
12404
12405 return 0;
12406 }
12407
12408 static bool encoders_cloneable(const struct intel_encoder *a,
12409 const struct intel_encoder *b)
12410 {
12411 /* masks could be asymmetric, so check both ways */
12412 return a == b || (a->cloneable & (1 << b->type) &&
12413 b->cloneable & (1 << a->type));
12414 }
12415
12416 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12417 struct intel_crtc *crtc,
12418 struct intel_encoder *encoder)
12419 {
12420 struct intel_encoder *source_encoder;
12421 struct drm_connector *connector;
12422 struct drm_connector_state *connector_state;
12423 int i;
12424
12425 for_each_connector_in_state(state, connector, connector_state, i) {
12426 if (connector_state->crtc != &crtc->base)
12427 continue;
12428
12429 source_encoder =
12430 to_intel_encoder(connector_state->best_encoder);
12431 if (!encoders_cloneable(encoder, source_encoder))
12432 return false;
12433 }
12434
12435 return true;
12436 }
12437
12438 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12439 struct drm_crtc_state *crtc_state)
12440 {
12441 struct drm_device *dev = crtc->dev;
12442 struct drm_i915_private *dev_priv = to_i915(dev);
12443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12444 struct intel_crtc_state *pipe_config =
12445 to_intel_crtc_state(crtc_state);
12446 struct drm_atomic_state *state = crtc_state->state;
12447 int ret;
12448 bool mode_changed = needs_modeset(crtc_state);
12449
12450 if (mode_changed && !crtc_state->active)
12451 pipe_config->update_wm_post = true;
12452
12453 if (mode_changed && crtc_state->enable &&
12454 dev_priv->display.crtc_compute_clock &&
12455 !WARN_ON(pipe_config->shared_dpll)) {
12456 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12457 pipe_config);
12458 if (ret)
12459 return ret;
12460 }
12461
12462 if (crtc_state->color_mgmt_changed) {
12463 ret = intel_color_check(crtc, crtc_state);
12464 if (ret)
12465 return ret;
12466
12467 /*
12468 * Changing color management on Intel hardware is
12469 * handled as part of planes update.
12470 */
12471 crtc_state->planes_changed = true;
12472 }
12473
12474 ret = 0;
12475 if (dev_priv->display.compute_pipe_wm) {
12476 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12477 if (ret) {
12478 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12479 return ret;
12480 }
12481 }
12482
12483 if (dev_priv->display.compute_intermediate_wm &&
12484 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12485 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12486 return 0;
12487
12488 /*
12489 * Calculate 'intermediate' watermarks that satisfy both the
12490 * old state and the new state. We can program these
12491 * immediately.
12492 */
12493 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12494 intel_crtc,
12495 pipe_config);
12496 if (ret) {
12497 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12498 return ret;
12499 }
12500 } else if (dev_priv->display.compute_intermediate_wm) {
12501 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12502 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12503 }
12504
12505 if (INTEL_INFO(dev)->gen >= 9) {
12506 if (mode_changed)
12507 ret = skl_update_scaler_crtc(pipe_config);
12508
12509 if (!ret)
12510 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12511 pipe_config);
12512 }
12513
12514 return ret;
12515 }
12516
12517 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12518 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12519 .atomic_begin = intel_begin_crtc_commit,
12520 .atomic_flush = intel_finish_crtc_commit,
12521 .atomic_check = intel_crtc_atomic_check,
12522 };
12523
12524 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12525 {
12526 struct intel_connector *connector;
12527
12528 for_each_intel_connector(dev, connector) {
12529 if (connector->base.state->crtc)
12530 drm_connector_unreference(&connector->base);
12531
12532 if (connector->base.encoder) {
12533 connector->base.state->best_encoder =
12534 connector->base.encoder;
12535 connector->base.state->crtc =
12536 connector->base.encoder->crtc;
12537
12538 drm_connector_reference(&connector->base);
12539 } else {
12540 connector->base.state->best_encoder = NULL;
12541 connector->base.state->crtc = NULL;
12542 }
12543 }
12544 }
12545
12546 static void
12547 connected_sink_compute_bpp(struct intel_connector *connector,
12548 struct intel_crtc_state *pipe_config)
12549 {
12550 int bpp = pipe_config->pipe_bpp;
12551
12552 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12553 connector->base.base.id,
12554 connector->base.name);
12555
12556 /* Don't use an invalid EDID bpc value */
12557 if (connector->base.display_info.bpc &&
12558 connector->base.display_info.bpc * 3 < bpp) {
12559 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12560 bpp, connector->base.display_info.bpc*3);
12561 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12562 }
12563
12564 /* Clamp bpp to 8 on screens without EDID 1.4 */
12565 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12566 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12567 bpp);
12568 pipe_config->pipe_bpp = 24;
12569 }
12570 }
12571
12572 static int
12573 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12574 struct intel_crtc_state *pipe_config)
12575 {
12576 struct drm_device *dev = crtc->base.dev;
12577 struct drm_atomic_state *state;
12578 struct drm_connector *connector;
12579 struct drm_connector_state *connector_state;
12580 int bpp, i;
12581
12582 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12583 bpp = 10*3;
12584 else if (INTEL_INFO(dev)->gen >= 5)
12585 bpp = 12*3;
12586 else
12587 bpp = 8*3;
12588
12589
12590 pipe_config->pipe_bpp = bpp;
12591
12592 state = pipe_config->base.state;
12593
12594 /* Clamp display bpp to EDID value */
12595 for_each_connector_in_state(state, connector, connector_state, i) {
12596 if (connector_state->crtc != &crtc->base)
12597 continue;
12598
12599 connected_sink_compute_bpp(to_intel_connector(connector),
12600 pipe_config);
12601 }
12602
12603 return bpp;
12604 }
12605
12606 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12607 {
12608 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12609 "type: 0x%x flags: 0x%x\n",
12610 mode->crtc_clock,
12611 mode->crtc_hdisplay, mode->crtc_hsync_start,
12612 mode->crtc_hsync_end, mode->crtc_htotal,
12613 mode->crtc_vdisplay, mode->crtc_vsync_start,
12614 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12615 }
12616
12617 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12618 struct intel_crtc_state *pipe_config,
12619 const char *context)
12620 {
12621 struct drm_device *dev = crtc->base.dev;
12622 struct drm_plane *plane;
12623 struct intel_plane *intel_plane;
12624 struct intel_plane_state *state;
12625 struct drm_framebuffer *fb;
12626
12627 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12628 crtc->base.base.id, crtc->base.name,
12629 context, pipe_config, pipe_name(crtc->pipe));
12630
12631 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12632 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12633 pipe_config->pipe_bpp, pipe_config->dither);
12634 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12635 pipe_config->has_pch_encoder,
12636 pipe_config->fdi_lanes,
12637 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12638 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12639 pipe_config->fdi_m_n.tu);
12640 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12641 intel_crtc_has_dp_encoder(pipe_config),
12642 pipe_config->lane_count,
12643 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12644 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12645 pipe_config->dp_m_n.tu);
12646
12647 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12648 intel_crtc_has_dp_encoder(pipe_config),
12649 pipe_config->lane_count,
12650 pipe_config->dp_m2_n2.gmch_m,
12651 pipe_config->dp_m2_n2.gmch_n,
12652 pipe_config->dp_m2_n2.link_m,
12653 pipe_config->dp_m2_n2.link_n,
12654 pipe_config->dp_m2_n2.tu);
12655
12656 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12657 pipe_config->has_audio,
12658 pipe_config->has_infoframe);
12659
12660 DRM_DEBUG_KMS("requested mode:\n");
12661 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12662 DRM_DEBUG_KMS("adjusted mode:\n");
12663 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12664 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12665 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12666 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12667 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12668 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12669 crtc->num_scalers,
12670 pipe_config->scaler_state.scaler_users,
12671 pipe_config->scaler_state.scaler_id);
12672 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12673 pipe_config->gmch_pfit.control,
12674 pipe_config->gmch_pfit.pgm_ratios,
12675 pipe_config->gmch_pfit.lvds_border_bits);
12676 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12677 pipe_config->pch_pfit.pos,
12678 pipe_config->pch_pfit.size,
12679 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12680 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12681 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12682
12683 if (IS_BROXTON(dev)) {
12684 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12685 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12686 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12687 pipe_config->ddi_pll_sel,
12688 pipe_config->dpll_hw_state.ebb0,
12689 pipe_config->dpll_hw_state.ebb4,
12690 pipe_config->dpll_hw_state.pll0,
12691 pipe_config->dpll_hw_state.pll1,
12692 pipe_config->dpll_hw_state.pll2,
12693 pipe_config->dpll_hw_state.pll3,
12694 pipe_config->dpll_hw_state.pll6,
12695 pipe_config->dpll_hw_state.pll8,
12696 pipe_config->dpll_hw_state.pll9,
12697 pipe_config->dpll_hw_state.pll10,
12698 pipe_config->dpll_hw_state.pcsdw12);
12699 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12700 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12701 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12702 pipe_config->ddi_pll_sel,
12703 pipe_config->dpll_hw_state.ctrl1,
12704 pipe_config->dpll_hw_state.cfgcr1,
12705 pipe_config->dpll_hw_state.cfgcr2);
12706 } else if (HAS_DDI(dev)) {
12707 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12708 pipe_config->ddi_pll_sel,
12709 pipe_config->dpll_hw_state.wrpll,
12710 pipe_config->dpll_hw_state.spll);
12711 } else {
12712 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12713 "fp0: 0x%x, fp1: 0x%x\n",
12714 pipe_config->dpll_hw_state.dpll,
12715 pipe_config->dpll_hw_state.dpll_md,
12716 pipe_config->dpll_hw_state.fp0,
12717 pipe_config->dpll_hw_state.fp1);
12718 }
12719
12720 DRM_DEBUG_KMS("planes on this crtc\n");
12721 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12722 intel_plane = to_intel_plane(plane);
12723 if (intel_plane->pipe != crtc->pipe)
12724 continue;
12725
12726 state = to_intel_plane_state(plane->state);
12727 fb = state->base.fb;
12728 if (!fb) {
12729 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12730 plane->base.id, plane->name, state->scaler_id);
12731 continue;
12732 }
12733
12734 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12735 plane->base.id, plane->name);
12736 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12737 fb->base.id, fb->width, fb->height,
12738 drm_get_format_name(fb->pixel_format));
12739 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12740 state->scaler_id,
12741 state->base.src.x1 >> 16,
12742 state->base.src.y1 >> 16,
12743 drm_rect_width(&state->base.src) >> 16,
12744 drm_rect_height(&state->base.src) >> 16,
12745 state->base.dst.x1, state->base.dst.y1,
12746 drm_rect_width(&state->base.dst),
12747 drm_rect_height(&state->base.dst));
12748 }
12749 }
12750
12751 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12752 {
12753 struct drm_device *dev = state->dev;
12754 struct drm_connector *connector;
12755 unsigned int used_ports = 0;
12756 unsigned int used_mst_ports = 0;
12757
12758 /*
12759 * Walk the connector list instead of the encoder
12760 * list to detect the problem on ddi platforms
12761 * where there's just one encoder per digital port.
12762 */
12763 drm_for_each_connector(connector, dev) {
12764 struct drm_connector_state *connector_state;
12765 struct intel_encoder *encoder;
12766
12767 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12768 if (!connector_state)
12769 connector_state = connector->state;
12770
12771 if (!connector_state->best_encoder)
12772 continue;
12773
12774 encoder = to_intel_encoder(connector_state->best_encoder);
12775
12776 WARN_ON(!connector_state->crtc);
12777
12778 switch (encoder->type) {
12779 unsigned int port_mask;
12780 case INTEL_OUTPUT_UNKNOWN:
12781 if (WARN_ON(!HAS_DDI(dev)))
12782 break;
12783 case INTEL_OUTPUT_DP:
12784 case INTEL_OUTPUT_HDMI:
12785 case INTEL_OUTPUT_EDP:
12786 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12787
12788 /* the same port mustn't appear more than once */
12789 if (used_ports & port_mask)
12790 return false;
12791
12792 used_ports |= port_mask;
12793 break;
12794 case INTEL_OUTPUT_DP_MST:
12795 used_mst_ports |=
12796 1 << enc_to_mst(&encoder->base)->primary->port;
12797 break;
12798 default:
12799 break;
12800 }
12801 }
12802
12803 /* can't mix MST and SST/HDMI on the same port */
12804 if (used_ports & used_mst_ports)
12805 return false;
12806
12807 return true;
12808 }
12809
12810 static void
12811 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12812 {
12813 struct drm_crtc_state tmp_state;
12814 struct intel_crtc_scaler_state scaler_state;
12815 struct intel_dpll_hw_state dpll_hw_state;
12816 struct intel_shared_dpll *shared_dpll;
12817 uint32_t ddi_pll_sel;
12818 bool force_thru;
12819
12820 /* FIXME: before the switch to atomic started, a new pipe_config was
12821 * kzalloc'd. Code that depends on any field being zero should be
12822 * fixed, so that the crtc_state can be safely duplicated. For now,
12823 * only fields that are know to not cause problems are preserved. */
12824
12825 tmp_state = crtc_state->base;
12826 scaler_state = crtc_state->scaler_state;
12827 shared_dpll = crtc_state->shared_dpll;
12828 dpll_hw_state = crtc_state->dpll_hw_state;
12829 ddi_pll_sel = crtc_state->ddi_pll_sel;
12830 force_thru = crtc_state->pch_pfit.force_thru;
12831
12832 memset(crtc_state, 0, sizeof *crtc_state);
12833
12834 crtc_state->base = tmp_state;
12835 crtc_state->scaler_state = scaler_state;
12836 crtc_state->shared_dpll = shared_dpll;
12837 crtc_state->dpll_hw_state = dpll_hw_state;
12838 crtc_state->ddi_pll_sel = ddi_pll_sel;
12839 crtc_state->pch_pfit.force_thru = force_thru;
12840 }
12841
12842 static int
12843 intel_modeset_pipe_config(struct drm_crtc *crtc,
12844 struct intel_crtc_state *pipe_config)
12845 {
12846 struct drm_atomic_state *state = pipe_config->base.state;
12847 struct intel_encoder *encoder;
12848 struct drm_connector *connector;
12849 struct drm_connector_state *connector_state;
12850 int base_bpp, ret = -EINVAL;
12851 int i;
12852 bool retry = true;
12853
12854 clear_intel_crtc_state(pipe_config);
12855
12856 pipe_config->cpu_transcoder =
12857 (enum transcoder) to_intel_crtc(crtc)->pipe;
12858
12859 /*
12860 * Sanitize sync polarity flags based on requested ones. If neither
12861 * positive or negative polarity is requested, treat this as meaning
12862 * negative polarity.
12863 */
12864 if (!(pipe_config->base.adjusted_mode.flags &
12865 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12866 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12867
12868 if (!(pipe_config->base.adjusted_mode.flags &
12869 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12870 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12871
12872 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12873 pipe_config);
12874 if (base_bpp < 0)
12875 goto fail;
12876
12877 /*
12878 * Determine the real pipe dimensions. Note that stereo modes can
12879 * increase the actual pipe size due to the frame doubling and
12880 * insertion of additional space for blanks between the frame. This
12881 * is stored in the crtc timings. We use the requested mode to do this
12882 * computation to clearly distinguish it from the adjusted mode, which
12883 * can be changed by the connectors in the below retry loop.
12884 */
12885 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12886 &pipe_config->pipe_src_w,
12887 &pipe_config->pipe_src_h);
12888
12889 for_each_connector_in_state(state, connector, connector_state, i) {
12890 if (connector_state->crtc != crtc)
12891 continue;
12892
12893 encoder = to_intel_encoder(connector_state->best_encoder);
12894
12895 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12896 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12897 goto fail;
12898 }
12899
12900 /*
12901 * Determine output_types before calling the .compute_config()
12902 * hooks so that the hooks can use this information safely.
12903 */
12904 pipe_config->output_types |= 1 << encoder->type;
12905 }
12906
12907 encoder_retry:
12908 /* Ensure the port clock defaults are reset when retrying. */
12909 pipe_config->port_clock = 0;
12910 pipe_config->pixel_multiplier = 1;
12911
12912 /* Fill in default crtc timings, allow encoders to overwrite them. */
12913 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12914 CRTC_STEREO_DOUBLE);
12915
12916 /* Pass our mode to the connectors and the CRTC to give them a chance to
12917 * adjust it according to limitations or connector properties, and also
12918 * a chance to reject the mode entirely.
12919 */
12920 for_each_connector_in_state(state, connector, connector_state, i) {
12921 if (connector_state->crtc != crtc)
12922 continue;
12923
12924 encoder = to_intel_encoder(connector_state->best_encoder);
12925
12926 if (!(encoder->compute_config(encoder, pipe_config))) {
12927 DRM_DEBUG_KMS("Encoder config failure\n");
12928 goto fail;
12929 }
12930 }
12931
12932 /* Set default port clock if not overwritten by the encoder. Needs to be
12933 * done afterwards in case the encoder adjusts the mode. */
12934 if (!pipe_config->port_clock)
12935 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12936 * pipe_config->pixel_multiplier;
12937
12938 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12939 if (ret < 0) {
12940 DRM_DEBUG_KMS("CRTC fixup failed\n");
12941 goto fail;
12942 }
12943
12944 if (ret == RETRY) {
12945 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12946 ret = -EINVAL;
12947 goto fail;
12948 }
12949
12950 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12951 retry = false;
12952 goto encoder_retry;
12953 }
12954
12955 /* Dithering seems to not pass-through bits correctly when it should, so
12956 * only enable it on 6bpc panels. */
12957 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12958 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12959 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12960
12961 fail:
12962 return ret;
12963 }
12964
12965 static void
12966 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12967 {
12968 struct drm_crtc *crtc;
12969 struct drm_crtc_state *crtc_state;
12970 int i;
12971
12972 /* Double check state. */
12973 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12974 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12975
12976 /* Update hwmode for vblank functions */
12977 if (crtc->state->active)
12978 crtc->hwmode = crtc->state->adjusted_mode;
12979 else
12980 crtc->hwmode.crtc_clock = 0;
12981
12982 /*
12983 * Update legacy state to satisfy fbc code. This can
12984 * be removed when fbc uses the atomic state.
12985 */
12986 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12987 struct drm_plane_state *plane_state = crtc->primary->state;
12988
12989 crtc->primary->fb = plane_state->fb;
12990 crtc->x = plane_state->src_x >> 16;
12991 crtc->y = plane_state->src_y >> 16;
12992 }
12993 }
12994 }
12995
12996 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12997 {
12998 int diff;
12999
13000 if (clock1 == clock2)
13001 return true;
13002
13003 if (!clock1 || !clock2)
13004 return false;
13005
13006 diff = abs(clock1 - clock2);
13007
13008 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13009 return true;
13010
13011 return false;
13012 }
13013
13014 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
13015 list_for_each_entry((intel_crtc), \
13016 &(dev)->mode_config.crtc_list, \
13017 base.head) \
13018 for_each_if (mask & (1 <<(intel_crtc)->pipe))
13019
13020 static bool
13021 intel_compare_m_n(unsigned int m, unsigned int n,
13022 unsigned int m2, unsigned int n2,
13023 bool exact)
13024 {
13025 if (m == m2 && n == n2)
13026 return true;
13027
13028 if (exact || !m || !n || !m2 || !n2)
13029 return false;
13030
13031 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13032
13033 if (n > n2) {
13034 while (n > n2) {
13035 m2 <<= 1;
13036 n2 <<= 1;
13037 }
13038 } else if (n < n2) {
13039 while (n < n2) {
13040 m <<= 1;
13041 n <<= 1;
13042 }
13043 }
13044
13045 if (n != n2)
13046 return false;
13047
13048 return intel_fuzzy_clock_check(m, m2);
13049 }
13050
13051 static bool
13052 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13053 struct intel_link_m_n *m2_n2,
13054 bool adjust)
13055 {
13056 if (m_n->tu == m2_n2->tu &&
13057 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13058 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13059 intel_compare_m_n(m_n->link_m, m_n->link_n,
13060 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13061 if (adjust)
13062 *m2_n2 = *m_n;
13063
13064 return true;
13065 }
13066
13067 return false;
13068 }
13069
13070 static bool
13071 intel_pipe_config_compare(struct drm_device *dev,
13072 struct intel_crtc_state *current_config,
13073 struct intel_crtc_state *pipe_config,
13074 bool adjust)
13075 {
13076 bool ret = true;
13077
13078 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13079 do { \
13080 if (!adjust) \
13081 DRM_ERROR(fmt, ##__VA_ARGS__); \
13082 else \
13083 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13084 } while (0)
13085
13086 #define PIPE_CONF_CHECK_X(name) \
13087 if (current_config->name != pipe_config->name) { \
13088 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13089 "(expected 0x%08x, found 0x%08x)\n", \
13090 current_config->name, \
13091 pipe_config->name); \
13092 ret = false; \
13093 }
13094
13095 #define PIPE_CONF_CHECK_I(name) \
13096 if (current_config->name != pipe_config->name) { \
13097 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13098 "(expected %i, found %i)\n", \
13099 current_config->name, \
13100 pipe_config->name); \
13101 ret = false; \
13102 }
13103
13104 #define PIPE_CONF_CHECK_P(name) \
13105 if (current_config->name != pipe_config->name) { \
13106 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13107 "(expected %p, found %p)\n", \
13108 current_config->name, \
13109 pipe_config->name); \
13110 ret = false; \
13111 }
13112
13113 #define PIPE_CONF_CHECK_M_N(name) \
13114 if (!intel_compare_link_m_n(&current_config->name, \
13115 &pipe_config->name,\
13116 adjust)) { \
13117 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13118 "(expected tu %i gmch %i/%i link %i/%i, " \
13119 "found tu %i, gmch %i/%i link %i/%i)\n", \
13120 current_config->name.tu, \
13121 current_config->name.gmch_m, \
13122 current_config->name.gmch_n, \
13123 current_config->name.link_m, \
13124 current_config->name.link_n, \
13125 pipe_config->name.tu, \
13126 pipe_config->name.gmch_m, \
13127 pipe_config->name.gmch_n, \
13128 pipe_config->name.link_m, \
13129 pipe_config->name.link_n); \
13130 ret = false; \
13131 }
13132
13133 /* This is required for BDW+ where there is only one set of registers for
13134 * switching between high and low RR.
13135 * This macro can be used whenever a comparison has to be made between one
13136 * hw state and multiple sw state variables.
13137 */
13138 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13139 if (!intel_compare_link_m_n(&current_config->name, \
13140 &pipe_config->name, adjust) && \
13141 !intel_compare_link_m_n(&current_config->alt_name, \
13142 &pipe_config->name, adjust)) { \
13143 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13144 "(expected tu %i gmch %i/%i link %i/%i, " \
13145 "or tu %i gmch %i/%i link %i/%i, " \
13146 "found tu %i, gmch %i/%i link %i/%i)\n", \
13147 current_config->name.tu, \
13148 current_config->name.gmch_m, \
13149 current_config->name.gmch_n, \
13150 current_config->name.link_m, \
13151 current_config->name.link_n, \
13152 current_config->alt_name.tu, \
13153 current_config->alt_name.gmch_m, \
13154 current_config->alt_name.gmch_n, \
13155 current_config->alt_name.link_m, \
13156 current_config->alt_name.link_n, \
13157 pipe_config->name.tu, \
13158 pipe_config->name.gmch_m, \
13159 pipe_config->name.gmch_n, \
13160 pipe_config->name.link_m, \
13161 pipe_config->name.link_n); \
13162 ret = false; \
13163 }
13164
13165 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13166 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13167 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13168 "(expected %i, found %i)\n", \
13169 current_config->name & (mask), \
13170 pipe_config->name & (mask)); \
13171 ret = false; \
13172 }
13173
13174 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13175 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13176 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13177 "(expected %i, found %i)\n", \
13178 current_config->name, \
13179 pipe_config->name); \
13180 ret = false; \
13181 }
13182
13183 #define PIPE_CONF_QUIRK(quirk) \
13184 ((current_config->quirks | pipe_config->quirks) & (quirk))
13185
13186 PIPE_CONF_CHECK_I(cpu_transcoder);
13187
13188 PIPE_CONF_CHECK_I(has_pch_encoder);
13189 PIPE_CONF_CHECK_I(fdi_lanes);
13190 PIPE_CONF_CHECK_M_N(fdi_m_n);
13191
13192 PIPE_CONF_CHECK_I(lane_count);
13193 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13194
13195 if (INTEL_INFO(dev)->gen < 8) {
13196 PIPE_CONF_CHECK_M_N(dp_m_n);
13197
13198 if (current_config->has_drrs)
13199 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13200 } else
13201 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13202
13203 PIPE_CONF_CHECK_X(output_types);
13204
13205 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13206 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13207 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13208 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13209 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13210 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13211
13212 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13213 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13214 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13215 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13216 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13217 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13218
13219 PIPE_CONF_CHECK_I(pixel_multiplier);
13220 PIPE_CONF_CHECK_I(has_hdmi_sink);
13221 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13222 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13223 PIPE_CONF_CHECK_I(limited_color_range);
13224 PIPE_CONF_CHECK_I(has_infoframe);
13225
13226 PIPE_CONF_CHECK_I(has_audio);
13227
13228 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13229 DRM_MODE_FLAG_INTERLACE);
13230
13231 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13232 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13233 DRM_MODE_FLAG_PHSYNC);
13234 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13235 DRM_MODE_FLAG_NHSYNC);
13236 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13237 DRM_MODE_FLAG_PVSYNC);
13238 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13239 DRM_MODE_FLAG_NVSYNC);
13240 }
13241
13242 PIPE_CONF_CHECK_X(gmch_pfit.control);
13243 /* pfit ratios are autocomputed by the hw on gen4+ */
13244 if (INTEL_INFO(dev)->gen < 4)
13245 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13246 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13247
13248 if (!adjust) {
13249 PIPE_CONF_CHECK_I(pipe_src_w);
13250 PIPE_CONF_CHECK_I(pipe_src_h);
13251
13252 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13253 if (current_config->pch_pfit.enabled) {
13254 PIPE_CONF_CHECK_X(pch_pfit.pos);
13255 PIPE_CONF_CHECK_X(pch_pfit.size);
13256 }
13257
13258 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13259 }
13260
13261 /* BDW+ don't expose a synchronous way to read the state */
13262 if (IS_HASWELL(dev))
13263 PIPE_CONF_CHECK_I(ips_enabled);
13264
13265 PIPE_CONF_CHECK_I(double_wide);
13266
13267 PIPE_CONF_CHECK_X(ddi_pll_sel);
13268
13269 PIPE_CONF_CHECK_P(shared_dpll);
13270 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13271 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13272 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13273 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13274 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13275 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13276 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13277 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13278 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13279
13280 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13281 PIPE_CONF_CHECK_X(dsi_pll.div);
13282
13283 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13284 PIPE_CONF_CHECK_I(pipe_bpp);
13285
13286 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13287 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13288
13289 #undef PIPE_CONF_CHECK_X
13290 #undef PIPE_CONF_CHECK_I
13291 #undef PIPE_CONF_CHECK_P
13292 #undef PIPE_CONF_CHECK_FLAGS
13293 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13294 #undef PIPE_CONF_QUIRK
13295 #undef INTEL_ERR_OR_DBG_KMS
13296
13297 return ret;
13298 }
13299
13300 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13301 const struct intel_crtc_state *pipe_config)
13302 {
13303 if (pipe_config->has_pch_encoder) {
13304 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13305 &pipe_config->fdi_m_n);
13306 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13307
13308 /*
13309 * FDI already provided one idea for the dotclock.
13310 * Yell if the encoder disagrees.
13311 */
13312 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13313 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13314 fdi_dotclock, dotclock);
13315 }
13316 }
13317
13318 static void verify_wm_state(struct drm_crtc *crtc,
13319 struct drm_crtc_state *new_state)
13320 {
13321 struct drm_device *dev = crtc->dev;
13322 struct drm_i915_private *dev_priv = to_i915(dev);
13323 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13324 struct skl_ddb_entry *hw_entry, *sw_entry;
13325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13326 const enum pipe pipe = intel_crtc->pipe;
13327 int plane;
13328
13329 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13330 return;
13331
13332 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13333 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13334
13335 /* planes */
13336 for_each_plane(dev_priv, pipe, plane) {
13337 hw_entry = &hw_ddb.plane[pipe][plane];
13338 sw_entry = &sw_ddb->plane[pipe][plane];
13339
13340 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13341 continue;
13342
13343 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13344 "(expected (%u,%u), found (%u,%u))\n",
13345 pipe_name(pipe), plane + 1,
13346 sw_entry->start, sw_entry->end,
13347 hw_entry->start, hw_entry->end);
13348 }
13349
13350 /* cursor */
13351 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13352 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13353
13354 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13355 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13356 "(expected (%u,%u), found (%u,%u))\n",
13357 pipe_name(pipe),
13358 sw_entry->start, sw_entry->end,
13359 hw_entry->start, hw_entry->end);
13360 }
13361 }
13362
13363 static void
13364 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13365 {
13366 struct drm_connector *connector;
13367
13368 drm_for_each_connector(connector, dev) {
13369 struct drm_encoder *encoder = connector->encoder;
13370 struct drm_connector_state *state = connector->state;
13371
13372 if (state->crtc != crtc)
13373 continue;
13374
13375 intel_connector_verify_state(to_intel_connector(connector));
13376
13377 I915_STATE_WARN(state->best_encoder != encoder,
13378 "connector's atomic encoder doesn't match legacy encoder\n");
13379 }
13380 }
13381
13382 static void
13383 verify_encoder_state(struct drm_device *dev)
13384 {
13385 struct intel_encoder *encoder;
13386 struct intel_connector *connector;
13387
13388 for_each_intel_encoder(dev, encoder) {
13389 bool enabled = false;
13390 enum pipe pipe;
13391
13392 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13393 encoder->base.base.id,
13394 encoder->base.name);
13395
13396 for_each_intel_connector(dev, connector) {
13397 if (connector->base.state->best_encoder != &encoder->base)
13398 continue;
13399 enabled = true;
13400
13401 I915_STATE_WARN(connector->base.state->crtc !=
13402 encoder->base.crtc,
13403 "connector's crtc doesn't match encoder crtc\n");
13404 }
13405
13406 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13407 "encoder's enabled state mismatch "
13408 "(expected %i, found %i)\n",
13409 !!encoder->base.crtc, enabled);
13410
13411 if (!encoder->base.crtc) {
13412 bool active;
13413
13414 active = encoder->get_hw_state(encoder, &pipe);
13415 I915_STATE_WARN(active,
13416 "encoder detached but still enabled on pipe %c.\n",
13417 pipe_name(pipe));
13418 }
13419 }
13420 }
13421
13422 static void
13423 verify_crtc_state(struct drm_crtc *crtc,
13424 struct drm_crtc_state *old_crtc_state,
13425 struct drm_crtc_state *new_crtc_state)
13426 {
13427 struct drm_device *dev = crtc->dev;
13428 struct drm_i915_private *dev_priv = to_i915(dev);
13429 struct intel_encoder *encoder;
13430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13431 struct intel_crtc_state *pipe_config, *sw_config;
13432 struct drm_atomic_state *old_state;
13433 bool active;
13434
13435 old_state = old_crtc_state->state;
13436 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13437 pipe_config = to_intel_crtc_state(old_crtc_state);
13438 memset(pipe_config, 0, sizeof(*pipe_config));
13439 pipe_config->base.crtc = crtc;
13440 pipe_config->base.state = old_state;
13441
13442 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13443
13444 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13445
13446 /* hw state is inconsistent with the pipe quirk */
13447 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13448 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13449 active = new_crtc_state->active;
13450
13451 I915_STATE_WARN(new_crtc_state->active != active,
13452 "crtc active state doesn't match with hw state "
13453 "(expected %i, found %i)\n", new_crtc_state->active, active);
13454
13455 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13456 "transitional active state does not match atomic hw state "
13457 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13458
13459 for_each_encoder_on_crtc(dev, crtc, encoder) {
13460 enum pipe pipe;
13461
13462 active = encoder->get_hw_state(encoder, &pipe);
13463 I915_STATE_WARN(active != new_crtc_state->active,
13464 "[ENCODER:%i] active %i with crtc active %i\n",
13465 encoder->base.base.id, active, new_crtc_state->active);
13466
13467 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13468 "Encoder connected to wrong pipe %c\n",
13469 pipe_name(pipe));
13470
13471 if (active) {
13472 pipe_config->output_types |= 1 << encoder->type;
13473 encoder->get_config(encoder, pipe_config);
13474 }
13475 }
13476
13477 if (!new_crtc_state->active)
13478 return;
13479
13480 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13481
13482 sw_config = to_intel_crtc_state(crtc->state);
13483 if (!intel_pipe_config_compare(dev, sw_config,
13484 pipe_config, false)) {
13485 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13486 intel_dump_pipe_config(intel_crtc, pipe_config,
13487 "[hw state]");
13488 intel_dump_pipe_config(intel_crtc, sw_config,
13489 "[sw state]");
13490 }
13491 }
13492
13493 static void
13494 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13495 struct intel_shared_dpll *pll,
13496 struct drm_crtc *crtc,
13497 struct drm_crtc_state *new_state)
13498 {
13499 struct intel_dpll_hw_state dpll_hw_state;
13500 unsigned crtc_mask;
13501 bool active;
13502
13503 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13504
13505 DRM_DEBUG_KMS("%s\n", pll->name);
13506
13507 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13508
13509 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13510 I915_STATE_WARN(!pll->on && pll->active_mask,
13511 "pll in active use but not on in sw tracking\n");
13512 I915_STATE_WARN(pll->on && !pll->active_mask,
13513 "pll is on but not used by any active crtc\n");
13514 I915_STATE_WARN(pll->on != active,
13515 "pll on state mismatch (expected %i, found %i)\n",
13516 pll->on, active);
13517 }
13518
13519 if (!crtc) {
13520 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13521 "more active pll users than references: %x vs %x\n",
13522 pll->active_mask, pll->config.crtc_mask);
13523
13524 return;
13525 }
13526
13527 crtc_mask = 1 << drm_crtc_index(crtc);
13528
13529 if (new_state->active)
13530 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13531 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13532 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13533 else
13534 I915_STATE_WARN(pll->active_mask & crtc_mask,
13535 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13536 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13537
13538 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13539 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13540 crtc_mask, pll->config.crtc_mask);
13541
13542 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13543 &dpll_hw_state,
13544 sizeof(dpll_hw_state)),
13545 "pll hw state mismatch\n");
13546 }
13547
13548 static void
13549 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13550 struct drm_crtc_state *old_crtc_state,
13551 struct drm_crtc_state *new_crtc_state)
13552 {
13553 struct drm_i915_private *dev_priv = to_i915(dev);
13554 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13555 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13556
13557 if (new_state->shared_dpll)
13558 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13559
13560 if (old_state->shared_dpll &&
13561 old_state->shared_dpll != new_state->shared_dpll) {
13562 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13563 struct intel_shared_dpll *pll = old_state->shared_dpll;
13564
13565 I915_STATE_WARN(pll->active_mask & crtc_mask,
13566 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13567 pipe_name(drm_crtc_index(crtc)));
13568 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13569 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13570 pipe_name(drm_crtc_index(crtc)));
13571 }
13572 }
13573
13574 static void
13575 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13576 struct drm_crtc_state *old_state,
13577 struct drm_crtc_state *new_state)
13578 {
13579 if (!needs_modeset(new_state) &&
13580 !to_intel_crtc_state(new_state)->update_pipe)
13581 return;
13582
13583 verify_wm_state(crtc, new_state);
13584 verify_connector_state(crtc->dev, crtc);
13585 verify_crtc_state(crtc, old_state, new_state);
13586 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13587 }
13588
13589 static void
13590 verify_disabled_dpll_state(struct drm_device *dev)
13591 {
13592 struct drm_i915_private *dev_priv = to_i915(dev);
13593 int i;
13594
13595 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13596 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13597 }
13598
13599 static void
13600 intel_modeset_verify_disabled(struct drm_device *dev)
13601 {
13602 verify_encoder_state(dev);
13603 verify_connector_state(dev, NULL);
13604 verify_disabled_dpll_state(dev);
13605 }
13606
13607 static void update_scanline_offset(struct intel_crtc *crtc)
13608 {
13609 struct drm_device *dev = crtc->base.dev;
13610
13611 /*
13612 * The scanline counter increments at the leading edge of hsync.
13613 *
13614 * On most platforms it starts counting from vtotal-1 on the
13615 * first active line. That means the scanline counter value is
13616 * always one less than what we would expect. Ie. just after
13617 * start of vblank, which also occurs at start of hsync (on the
13618 * last active line), the scanline counter will read vblank_start-1.
13619 *
13620 * On gen2 the scanline counter starts counting from 1 instead
13621 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13622 * to keep the value positive), instead of adding one.
13623 *
13624 * On HSW+ the behaviour of the scanline counter depends on the output
13625 * type. For DP ports it behaves like most other platforms, but on HDMI
13626 * there's an extra 1 line difference. So we need to add two instead of
13627 * one to the value.
13628 */
13629 if (IS_GEN2(dev)) {
13630 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13631 int vtotal;
13632
13633 vtotal = adjusted_mode->crtc_vtotal;
13634 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13635 vtotal /= 2;
13636
13637 crtc->scanline_offset = vtotal - 1;
13638 } else if (HAS_DDI(dev) &&
13639 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13640 crtc->scanline_offset = 2;
13641 } else
13642 crtc->scanline_offset = 1;
13643 }
13644
13645 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13646 {
13647 struct drm_device *dev = state->dev;
13648 struct drm_i915_private *dev_priv = to_i915(dev);
13649 struct intel_shared_dpll_config *shared_dpll = NULL;
13650 struct drm_crtc *crtc;
13651 struct drm_crtc_state *crtc_state;
13652 int i;
13653
13654 if (!dev_priv->display.crtc_compute_clock)
13655 return;
13656
13657 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13659 struct intel_shared_dpll *old_dpll =
13660 to_intel_crtc_state(crtc->state)->shared_dpll;
13661
13662 if (!needs_modeset(crtc_state))
13663 continue;
13664
13665 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13666
13667 if (!old_dpll)
13668 continue;
13669
13670 if (!shared_dpll)
13671 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13672
13673 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13674 }
13675 }
13676
13677 /*
13678 * This implements the workaround described in the "notes" section of the mode
13679 * set sequence documentation. When going from no pipes or single pipe to
13680 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13681 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13682 */
13683 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13684 {
13685 struct drm_crtc_state *crtc_state;
13686 struct intel_crtc *intel_crtc;
13687 struct drm_crtc *crtc;
13688 struct intel_crtc_state *first_crtc_state = NULL;
13689 struct intel_crtc_state *other_crtc_state = NULL;
13690 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13691 int i;
13692
13693 /* look at all crtc's that are going to be enabled in during modeset */
13694 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13695 intel_crtc = to_intel_crtc(crtc);
13696
13697 if (!crtc_state->active || !needs_modeset(crtc_state))
13698 continue;
13699
13700 if (first_crtc_state) {
13701 other_crtc_state = to_intel_crtc_state(crtc_state);
13702 break;
13703 } else {
13704 first_crtc_state = to_intel_crtc_state(crtc_state);
13705 first_pipe = intel_crtc->pipe;
13706 }
13707 }
13708
13709 /* No workaround needed? */
13710 if (!first_crtc_state)
13711 return 0;
13712
13713 /* w/a possibly needed, check how many crtc's are already enabled. */
13714 for_each_intel_crtc(state->dev, intel_crtc) {
13715 struct intel_crtc_state *pipe_config;
13716
13717 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13718 if (IS_ERR(pipe_config))
13719 return PTR_ERR(pipe_config);
13720
13721 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13722
13723 if (!pipe_config->base.active ||
13724 needs_modeset(&pipe_config->base))
13725 continue;
13726
13727 /* 2 or more enabled crtcs means no need for w/a */
13728 if (enabled_pipe != INVALID_PIPE)
13729 return 0;
13730
13731 enabled_pipe = intel_crtc->pipe;
13732 }
13733
13734 if (enabled_pipe != INVALID_PIPE)
13735 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13736 else if (other_crtc_state)
13737 other_crtc_state->hsw_workaround_pipe = first_pipe;
13738
13739 return 0;
13740 }
13741
13742 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13743 {
13744 struct drm_crtc *crtc;
13745 struct drm_crtc_state *crtc_state;
13746 int ret = 0;
13747
13748 /* add all active pipes to the state */
13749 for_each_crtc(state->dev, crtc) {
13750 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13751 if (IS_ERR(crtc_state))
13752 return PTR_ERR(crtc_state);
13753
13754 if (!crtc_state->active || needs_modeset(crtc_state))
13755 continue;
13756
13757 crtc_state->mode_changed = true;
13758
13759 ret = drm_atomic_add_affected_connectors(state, crtc);
13760 if (ret)
13761 break;
13762
13763 ret = drm_atomic_add_affected_planes(state, crtc);
13764 if (ret)
13765 break;
13766 }
13767
13768 return ret;
13769 }
13770
13771 static int intel_modeset_checks(struct drm_atomic_state *state)
13772 {
13773 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13774 struct drm_i915_private *dev_priv = to_i915(state->dev);
13775 struct drm_crtc *crtc;
13776 struct drm_crtc_state *crtc_state;
13777 int ret = 0, i;
13778
13779 if (!check_digital_port_conflicts(state)) {
13780 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13781 return -EINVAL;
13782 }
13783
13784 intel_state->modeset = true;
13785 intel_state->active_crtcs = dev_priv->active_crtcs;
13786
13787 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13788 if (crtc_state->active)
13789 intel_state->active_crtcs |= 1 << i;
13790 else
13791 intel_state->active_crtcs &= ~(1 << i);
13792
13793 if (crtc_state->active != crtc->state->active)
13794 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13795 }
13796
13797 /*
13798 * See if the config requires any additional preparation, e.g.
13799 * to adjust global state with pipes off. We need to do this
13800 * here so we can get the modeset_pipe updated config for the new
13801 * mode set on this crtc. For other crtcs we need to use the
13802 * adjusted_mode bits in the crtc directly.
13803 */
13804 if (dev_priv->display.modeset_calc_cdclk) {
13805 if (!intel_state->cdclk_pll_vco)
13806 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13807 if (!intel_state->cdclk_pll_vco)
13808 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13809
13810 ret = dev_priv->display.modeset_calc_cdclk(state);
13811 if (ret < 0)
13812 return ret;
13813
13814 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13815 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13816 ret = intel_modeset_all_pipes(state);
13817
13818 if (ret < 0)
13819 return ret;
13820
13821 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13822 intel_state->cdclk, intel_state->dev_cdclk);
13823 } else
13824 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13825
13826 intel_modeset_clear_plls(state);
13827
13828 if (IS_HASWELL(dev_priv))
13829 return haswell_mode_set_planes_workaround(state);
13830
13831 return 0;
13832 }
13833
13834 /*
13835 * Handle calculation of various watermark data at the end of the atomic check
13836 * phase. The code here should be run after the per-crtc and per-plane 'check'
13837 * handlers to ensure that all derived state has been updated.
13838 */
13839 static int calc_watermark_data(struct drm_atomic_state *state)
13840 {
13841 struct drm_device *dev = state->dev;
13842 struct drm_i915_private *dev_priv = to_i915(dev);
13843
13844 /* Is there platform-specific watermark information to calculate? */
13845 if (dev_priv->display.compute_global_watermarks)
13846 return dev_priv->display.compute_global_watermarks(state);
13847
13848 return 0;
13849 }
13850
13851 /**
13852 * intel_atomic_check - validate state object
13853 * @dev: drm device
13854 * @state: state to validate
13855 */
13856 static int intel_atomic_check(struct drm_device *dev,
13857 struct drm_atomic_state *state)
13858 {
13859 struct drm_i915_private *dev_priv = to_i915(dev);
13860 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13861 struct drm_crtc *crtc;
13862 struct drm_crtc_state *crtc_state;
13863 int ret, i;
13864 bool any_ms = false;
13865
13866 ret = drm_atomic_helper_check_modeset(dev, state);
13867 if (ret)
13868 return ret;
13869
13870 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13871 struct intel_crtc_state *pipe_config =
13872 to_intel_crtc_state(crtc_state);
13873
13874 /* Catch I915_MODE_FLAG_INHERITED */
13875 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13876 crtc_state->mode_changed = true;
13877
13878 if (!needs_modeset(crtc_state))
13879 continue;
13880
13881 if (!crtc_state->enable) {
13882 any_ms = true;
13883 continue;
13884 }
13885
13886 /* FIXME: For only active_changed we shouldn't need to do any
13887 * state recomputation at all. */
13888
13889 ret = drm_atomic_add_affected_connectors(state, crtc);
13890 if (ret)
13891 return ret;
13892
13893 ret = intel_modeset_pipe_config(crtc, pipe_config);
13894 if (ret) {
13895 intel_dump_pipe_config(to_intel_crtc(crtc),
13896 pipe_config, "[failed]");
13897 return ret;
13898 }
13899
13900 if (i915.fastboot &&
13901 intel_pipe_config_compare(dev,
13902 to_intel_crtc_state(crtc->state),
13903 pipe_config, true)) {
13904 crtc_state->mode_changed = false;
13905 to_intel_crtc_state(crtc_state)->update_pipe = true;
13906 }
13907
13908 if (needs_modeset(crtc_state))
13909 any_ms = true;
13910
13911 ret = drm_atomic_add_affected_planes(state, crtc);
13912 if (ret)
13913 return ret;
13914
13915 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13916 needs_modeset(crtc_state) ?
13917 "[modeset]" : "[fastset]");
13918 }
13919
13920 if (any_ms) {
13921 ret = intel_modeset_checks(state);
13922
13923 if (ret)
13924 return ret;
13925 } else
13926 intel_state->cdclk = dev_priv->cdclk_freq;
13927
13928 ret = drm_atomic_helper_check_planes(dev, state);
13929 if (ret)
13930 return ret;
13931
13932 intel_fbc_choose_crtc(dev_priv, state);
13933 return calc_watermark_data(state);
13934 }
13935
13936 static int intel_atomic_prepare_commit(struct drm_device *dev,
13937 struct drm_atomic_state *state,
13938 bool nonblock)
13939 {
13940 struct drm_i915_private *dev_priv = to_i915(dev);
13941 struct drm_plane_state *plane_state;
13942 struct drm_crtc_state *crtc_state;
13943 struct drm_plane *plane;
13944 struct drm_crtc *crtc;
13945 int i, ret;
13946
13947 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13948 if (state->legacy_cursor_update)
13949 continue;
13950
13951 ret = intel_crtc_wait_for_pending_flips(crtc);
13952 if (ret)
13953 return ret;
13954
13955 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13956 flush_workqueue(dev_priv->wq);
13957 }
13958
13959 ret = mutex_lock_interruptible(&dev->struct_mutex);
13960 if (ret)
13961 return ret;
13962
13963 ret = drm_atomic_helper_prepare_planes(dev, state);
13964 mutex_unlock(&dev->struct_mutex);
13965
13966 if (!ret && !nonblock) {
13967 for_each_plane_in_state(state, plane, plane_state, i) {
13968 struct intel_plane_state *intel_plane_state =
13969 to_intel_plane_state(plane_state);
13970
13971 if (!intel_plane_state->wait_req)
13972 continue;
13973
13974 ret = i915_wait_request(intel_plane_state->wait_req,
13975 true, NULL, NULL);
13976 if (ret) {
13977 /* Any hang should be swallowed by the wait */
13978 WARN_ON(ret == -EIO);
13979 mutex_lock(&dev->struct_mutex);
13980 drm_atomic_helper_cleanup_planes(dev, state);
13981 mutex_unlock(&dev->struct_mutex);
13982 break;
13983 }
13984 }
13985 }
13986
13987 return ret;
13988 }
13989
13990 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13991 {
13992 struct drm_device *dev = crtc->base.dev;
13993
13994 if (!dev->max_vblank_count)
13995 return drm_accurate_vblank_count(&crtc->base);
13996
13997 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13998 }
13999
14000 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14001 struct drm_i915_private *dev_priv,
14002 unsigned crtc_mask)
14003 {
14004 unsigned last_vblank_count[I915_MAX_PIPES];
14005 enum pipe pipe;
14006 int ret;
14007
14008 if (!crtc_mask)
14009 return;
14010
14011 for_each_pipe(dev_priv, pipe) {
14012 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14013
14014 if (!((1 << pipe) & crtc_mask))
14015 continue;
14016
14017 ret = drm_crtc_vblank_get(crtc);
14018 if (WARN_ON(ret != 0)) {
14019 crtc_mask &= ~(1 << pipe);
14020 continue;
14021 }
14022
14023 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14024 }
14025
14026 for_each_pipe(dev_priv, pipe) {
14027 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14028 long lret;
14029
14030 if (!((1 << pipe) & crtc_mask))
14031 continue;
14032
14033 lret = wait_event_timeout(dev->vblank[pipe].queue,
14034 last_vblank_count[pipe] !=
14035 drm_crtc_vblank_count(crtc),
14036 msecs_to_jiffies(50));
14037
14038 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14039
14040 drm_crtc_vblank_put(crtc);
14041 }
14042 }
14043
14044 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14045 {
14046 /* fb updated, need to unpin old fb */
14047 if (crtc_state->fb_changed)
14048 return true;
14049
14050 /* wm changes, need vblank before final wm's */
14051 if (crtc_state->update_wm_post)
14052 return true;
14053
14054 /*
14055 * cxsr is re-enabled after vblank.
14056 * This is already handled by crtc_state->update_wm_post,
14057 * but added for clarity.
14058 */
14059 if (crtc_state->disable_cxsr)
14060 return true;
14061
14062 return false;
14063 }
14064
14065 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14066 {
14067 struct drm_device *dev = state->dev;
14068 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14069 struct drm_i915_private *dev_priv = to_i915(dev);
14070 struct drm_crtc_state *old_crtc_state;
14071 struct drm_crtc *crtc;
14072 struct intel_crtc_state *intel_cstate;
14073 struct drm_plane *plane;
14074 struct drm_plane_state *plane_state;
14075 bool hw_check = intel_state->modeset;
14076 unsigned long put_domains[I915_MAX_PIPES] = {};
14077 unsigned crtc_vblank_mask = 0;
14078 int i, ret;
14079
14080 for_each_plane_in_state(state, plane, plane_state, i) {
14081 struct intel_plane_state *intel_plane_state =
14082 to_intel_plane_state(plane_state);
14083
14084 if (!intel_plane_state->wait_req)
14085 continue;
14086
14087 ret = i915_wait_request(intel_plane_state->wait_req,
14088 true, NULL, NULL);
14089 /* EIO should be eaten, and we can't get interrupted in the
14090 * worker, and blocking commits have waited already. */
14091 WARN_ON(ret);
14092 }
14093
14094 drm_atomic_helper_wait_for_dependencies(state);
14095
14096 if (intel_state->modeset) {
14097 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14098 sizeof(intel_state->min_pixclk));
14099 dev_priv->active_crtcs = intel_state->active_crtcs;
14100 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14101
14102 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14103 }
14104
14105 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14107
14108 if (needs_modeset(crtc->state) ||
14109 to_intel_crtc_state(crtc->state)->update_pipe) {
14110 hw_check = true;
14111
14112 put_domains[to_intel_crtc(crtc)->pipe] =
14113 modeset_get_crtc_power_domains(crtc,
14114 to_intel_crtc_state(crtc->state));
14115 }
14116
14117 if (!needs_modeset(crtc->state))
14118 continue;
14119
14120 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14121
14122 if (old_crtc_state->active) {
14123 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14124 dev_priv->display.crtc_disable(crtc);
14125 intel_crtc->active = false;
14126 intel_fbc_disable(intel_crtc);
14127 intel_disable_shared_dpll(intel_crtc);
14128
14129 /*
14130 * Underruns don't always raise
14131 * interrupts, so check manually.
14132 */
14133 intel_check_cpu_fifo_underruns(dev_priv);
14134 intel_check_pch_fifo_underruns(dev_priv);
14135
14136 if (!crtc->state->active)
14137 intel_update_watermarks(crtc);
14138 }
14139 }
14140
14141 /* Only after disabling all output pipelines that will be changed can we
14142 * update the the output configuration. */
14143 intel_modeset_update_crtc_state(state);
14144
14145 if (intel_state->modeset) {
14146 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14147
14148 if (dev_priv->display.modeset_commit_cdclk &&
14149 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14150 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14151 dev_priv->display.modeset_commit_cdclk(state);
14152
14153 intel_modeset_verify_disabled(dev);
14154 }
14155
14156 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14157 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14159 bool modeset = needs_modeset(crtc->state);
14160 struct intel_crtc_state *pipe_config =
14161 to_intel_crtc_state(crtc->state);
14162
14163 if (modeset && crtc->state->active) {
14164 update_scanline_offset(to_intel_crtc(crtc));
14165 dev_priv->display.crtc_enable(crtc);
14166 }
14167
14168 /* Complete events for now disable pipes here. */
14169 if (modeset && !crtc->state->active && crtc->state->event) {
14170 spin_lock_irq(&dev->event_lock);
14171 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14172 spin_unlock_irq(&dev->event_lock);
14173
14174 crtc->state->event = NULL;
14175 }
14176
14177 if (!modeset)
14178 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14179
14180 if (crtc->state->active &&
14181 drm_atomic_get_existing_plane_state(state, crtc->primary))
14182 intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
14183
14184 if (crtc->state->active)
14185 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14186
14187 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
14188 crtc_vblank_mask |= 1 << i;
14189 }
14190
14191 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14192 * already, but still need the state for the delayed optimization. To
14193 * fix this:
14194 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14195 * - schedule that vblank worker _before_ calling hw_done
14196 * - at the start of commit_tail, cancel it _synchrously
14197 * - switch over to the vblank wait helper in the core after that since
14198 * we don't need out special handling any more.
14199 */
14200 if (!state->legacy_cursor_update)
14201 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14202
14203 /*
14204 * Now that the vblank has passed, we can go ahead and program the
14205 * optimal watermarks on platforms that need two-step watermark
14206 * programming.
14207 *
14208 * TODO: Move this (and other cleanup) to an async worker eventually.
14209 */
14210 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14211 intel_cstate = to_intel_crtc_state(crtc->state);
14212
14213 if (dev_priv->display.optimize_watermarks)
14214 dev_priv->display.optimize_watermarks(intel_cstate);
14215 }
14216
14217 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14218 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14219
14220 if (put_domains[i])
14221 modeset_put_power_domains(dev_priv, put_domains[i]);
14222
14223 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14224 }
14225
14226 drm_atomic_helper_commit_hw_done(state);
14227
14228 if (intel_state->modeset)
14229 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14230
14231 mutex_lock(&dev->struct_mutex);
14232 drm_atomic_helper_cleanup_planes(dev, state);
14233 mutex_unlock(&dev->struct_mutex);
14234
14235 drm_atomic_helper_commit_cleanup_done(state);
14236
14237 drm_atomic_state_free(state);
14238
14239 /* As one of the primary mmio accessors, KMS has a high likelihood
14240 * of triggering bugs in unclaimed access. After we finish
14241 * modesetting, see if an error has been flagged, and if so
14242 * enable debugging for the next modeset - and hope we catch
14243 * the culprit.
14244 *
14245 * XXX note that we assume display power is on at this point.
14246 * This might hold true now but we need to add pm helper to check
14247 * unclaimed only when the hardware is on, as atomic commits
14248 * can happen also when the device is completely off.
14249 */
14250 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14251 }
14252
14253 static void intel_atomic_commit_work(struct work_struct *work)
14254 {
14255 struct drm_atomic_state *state = container_of(work,
14256 struct drm_atomic_state,
14257 commit_work);
14258 intel_atomic_commit_tail(state);
14259 }
14260
14261 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14262 {
14263 struct drm_plane_state *old_plane_state;
14264 struct drm_plane *plane;
14265 int i;
14266
14267 for_each_plane_in_state(state, plane, old_plane_state, i)
14268 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14269 intel_fb_obj(plane->state->fb),
14270 to_intel_plane(plane)->frontbuffer_bit);
14271 }
14272
14273 /**
14274 * intel_atomic_commit - commit validated state object
14275 * @dev: DRM device
14276 * @state: the top-level driver state object
14277 * @nonblock: nonblocking commit
14278 *
14279 * This function commits a top-level state object that has been validated
14280 * with drm_atomic_helper_check().
14281 *
14282 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14283 * nonblocking commits are only safe for pure plane updates. Everything else
14284 * should work though.
14285 *
14286 * RETURNS
14287 * Zero for success or -errno.
14288 */
14289 static int intel_atomic_commit(struct drm_device *dev,
14290 struct drm_atomic_state *state,
14291 bool nonblock)
14292 {
14293 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14294 struct drm_i915_private *dev_priv = to_i915(dev);
14295 int ret = 0;
14296
14297 if (intel_state->modeset && nonblock) {
14298 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14299 return -EINVAL;
14300 }
14301
14302 ret = drm_atomic_helper_setup_commit(state, nonblock);
14303 if (ret)
14304 return ret;
14305
14306 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14307
14308 ret = intel_atomic_prepare_commit(dev, state, nonblock);
14309 if (ret) {
14310 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14311 return ret;
14312 }
14313
14314 drm_atomic_helper_swap_state(state, true);
14315 dev_priv->wm.distrust_bios_wm = false;
14316 dev_priv->wm.skl_results = intel_state->wm_results;
14317 intel_shared_dpll_commit(state);
14318 intel_atomic_track_fbs(state);
14319
14320 if (nonblock)
14321 queue_work(system_unbound_wq, &state->commit_work);
14322 else
14323 intel_atomic_commit_tail(state);
14324
14325 return 0;
14326 }
14327
14328 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14329 {
14330 struct drm_device *dev = crtc->dev;
14331 struct drm_atomic_state *state;
14332 struct drm_crtc_state *crtc_state;
14333 int ret;
14334
14335 state = drm_atomic_state_alloc(dev);
14336 if (!state) {
14337 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14338 crtc->base.id, crtc->name);
14339 return;
14340 }
14341
14342 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14343
14344 retry:
14345 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14346 ret = PTR_ERR_OR_ZERO(crtc_state);
14347 if (!ret) {
14348 if (!crtc_state->active)
14349 goto out;
14350
14351 crtc_state->mode_changed = true;
14352 ret = drm_atomic_commit(state);
14353 }
14354
14355 if (ret == -EDEADLK) {
14356 drm_atomic_state_clear(state);
14357 drm_modeset_backoff(state->acquire_ctx);
14358 goto retry;
14359 }
14360
14361 if (ret)
14362 out:
14363 drm_atomic_state_free(state);
14364 }
14365
14366 #undef for_each_intel_crtc_masked
14367
14368 /*
14369 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14370 * drm_atomic_helper_legacy_gamma_set() directly.
14371 */
14372 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14373 u16 *red, u16 *green, u16 *blue,
14374 uint32_t size)
14375 {
14376 struct drm_device *dev = crtc->dev;
14377 struct drm_mode_config *config = &dev->mode_config;
14378 struct drm_crtc_state *state;
14379 int ret;
14380
14381 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14382 if (ret)
14383 return ret;
14384
14385 /*
14386 * Make sure we update the legacy properties so this works when
14387 * atomic is not enabled.
14388 */
14389
14390 state = crtc->state;
14391
14392 drm_object_property_set_value(&crtc->base,
14393 config->degamma_lut_property,
14394 (state->degamma_lut) ?
14395 state->degamma_lut->base.id : 0);
14396
14397 drm_object_property_set_value(&crtc->base,
14398 config->ctm_property,
14399 (state->ctm) ?
14400 state->ctm->base.id : 0);
14401
14402 drm_object_property_set_value(&crtc->base,
14403 config->gamma_lut_property,
14404 (state->gamma_lut) ?
14405 state->gamma_lut->base.id : 0);
14406
14407 return 0;
14408 }
14409
14410 static const struct drm_crtc_funcs intel_crtc_funcs = {
14411 .gamma_set = intel_atomic_legacy_gamma_set,
14412 .set_config = drm_atomic_helper_set_config,
14413 .set_property = drm_atomic_helper_crtc_set_property,
14414 .destroy = intel_crtc_destroy,
14415 .page_flip = intel_crtc_page_flip,
14416 .atomic_duplicate_state = intel_crtc_duplicate_state,
14417 .atomic_destroy_state = intel_crtc_destroy_state,
14418 };
14419
14420 /**
14421 * intel_prepare_plane_fb - Prepare fb for usage on plane
14422 * @plane: drm plane to prepare for
14423 * @fb: framebuffer to prepare for presentation
14424 *
14425 * Prepares a framebuffer for usage on a display plane. Generally this
14426 * involves pinning the underlying object and updating the frontbuffer tracking
14427 * bits. Some older platforms need special physical address handling for
14428 * cursor planes.
14429 *
14430 * Must be called with struct_mutex held.
14431 *
14432 * Returns 0 on success, negative error code on failure.
14433 */
14434 int
14435 intel_prepare_plane_fb(struct drm_plane *plane,
14436 const struct drm_plane_state *new_state)
14437 {
14438 struct drm_device *dev = plane->dev;
14439 struct drm_framebuffer *fb = new_state->fb;
14440 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14441 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14442 struct reservation_object *resv;
14443 int ret = 0;
14444
14445 if (!obj && !old_obj)
14446 return 0;
14447
14448 if (old_obj) {
14449 struct drm_crtc_state *crtc_state =
14450 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14451
14452 /* Big Hammer, we also need to ensure that any pending
14453 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14454 * current scanout is retired before unpinning the old
14455 * framebuffer. Note that we rely on userspace rendering
14456 * into the buffer attached to the pipe they are waiting
14457 * on. If not, userspace generates a GPU hang with IPEHR
14458 * point to the MI_WAIT_FOR_EVENT.
14459 *
14460 * This should only fail upon a hung GPU, in which case we
14461 * can safely continue.
14462 */
14463 if (needs_modeset(crtc_state))
14464 ret = i915_gem_object_wait_rendering(old_obj, true);
14465 if (ret) {
14466 /* GPU hangs should have been swallowed by the wait */
14467 WARN_ON(ret == -EIO);
14468 return ret;
14469 }
14470 }
14471
14472 if (!obj)
14473 return 0;
14474
14475 /* For framebuffer backed by dmabuf, wait for fence */
14476 resv = i915_gem_object_get_dmabuf_resv(obj);
14477 if (resv) {
14478 long lret;
14479
14480 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14481 MAX_SCHEDULE_TIMEOUT);
14482 if (lret == -ERESTARTSYS)
14483 return lret;
14484
14485 WARN(lret < 0, "waiting returns %li\n", lret);
14486 }
14487
14488 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14489 INTEL_INFO(dev)->cursor_needs_physical) {
14490 int align = IS_I830(dev) ? 16 * 1024 : 256;
14491 ret = i915_gem_object_attach_phys(obj, align);
14492 if (ret)
14493 DRM_DEBUG_KMS("failed to attach phys object\n");
14494 } else {
14495 struct i915_vma *vma;
14496
14497 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14498 if (IS_ERR(vma))
14499 ret = PTR_ERR(vma);
14500 }
14501
14502 if (ret == 0) {
14503 to_intel_plane_state(new_state)->wait_req =
14504 i915_gem_active_get(&obj->last_write,
14505 &obj->base.dev->struct_mutex);
14506 }
14507
14508 return ret;
14509 }
14510
14511 /**
14512 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14513 * @plane: drm plane to clean up for
14514 * @fb: old framebuffer that was on plane
14515 *
14516 * Cleans up a framebuffer that has just been removed from a plane.
14517 *
14518 * Must be called with struct_mutex held.
14519 */
14520 void
14521 intel_cleanup_plane_fb(struct drm_plane *plane,
14522 const struct drm_plane_state *old_state)
14523 {
14524 struct drm_device *dev = plane->dev;
14525 struct intel_plane_state *old_intel_state;
14526 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14527 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14528 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14529
14530 old_intel_state = to_intel_plane_state(old_state);
14531
14532 if (!obj && !old_obj)
14533 return;
14534
14535 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14536 !INTEL_INFO(dev)->cursor_needs_physical))
14537 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14538
14539 i915_gem_request_assign(&intel_state->wait_req, NULL);
14540 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14541 }
14542
14543 int
14544 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14545 {
14546 int max_scale;
14547 int crtc_clock, cdclk;
14548
14549 if (!intel_crtc || !crtc_state->base.enable)
14550 return DRM_PLANE_HELPER_NO_SCALING;
14551
14552 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14553 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14554
14555 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14556 return DRM_PLANE_HELPER_NO_SCALING;
14557
14558 /*
14559 * skl max scale is lower of:
14560 * close to 3 but not 3, -1 is for that purpose
14561 * or
14562 * cdclk/crtc_clock
14563 */
14564 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14565
14566 return max_scale;
14567 }
14568
14569 static int
14570 intel_check_primary_plane(struct drm_plane *plane,
14571 struct intel_crtc_state *crtc_state,
14572 struct intel_plane_state *state)
14573 {
14574 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14575 struct drm_crtc *crtc = state->base.crtc;
14576 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14577 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14578 bool can_position = false;
14579 int ret;
14580
14581 if (INTEL_GEN(dev_priv) >= 9) {
14582 /* use scaler when colorkey is not required */
14583 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14584 min_scale = 1;
14585 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14586 }
14587 can_position = true;
14588 }
14589
14590 ret = drm_plane_helper_check_state(&state->base,
14591 &state->clip,
14592 min_scale, max_scale,
14593 can_position, true);
14594 if (ret)
14595 return ret;
14596
14597 if (!state->base.fb)
14598 return 0;
14599
14600 if (INTEL_GEN(dev_priv) >= 9) {
14601 ret = skl_check_plane_surface(state);
14602 if (ret)
14603 return ret;
14604 }
14605
14606 return 0;
14607 }
14608
14609 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14610 struct drm_crtc_state *old_crtc_state)
14611 {
14612 struct drm_device *dev = crtc->dev;
14613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14614 struct intel_crtc_state *old_intel_state =
14615 to_intel_crtc_state(old_crtc_state);
14616 bool modeset = needs_modeset(crtc->state);
14617
14618 /* Perform vblank evasion around commit operation */
14619 intel_pipe_update_start(intel_crtc);
14620
14621 if (modeset)
14622 return;
14623
14624 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14625 intel_color_set_csc(crtc->state);
14626 intel_color_load_luts(crtc->state);
14627 }
14628
14629 if (to_intel_crtc_state(crtc->state)->update_pipe)
14630 intel_update_pipe_config(intel_crtc, old_intel_state);
14631 else if (INTEL_INFO(dev)->gen >= 9)
14632 skl_detach_scalers(intel_crtc);
14633 }
14634
14635 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14636 struct drm_crtc_state *old_crtc_state)
14637 {
14638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14639
14640 intel_pipe_update_end(intel_crtc, NULL);
14641 }
14642
14643 /**
14644 * intel_plane_destroy - destroy a plane
14645 * @plane: plane to destroy
14646 *
14647 * Common destruction function for all types of planes (primary, cursor,
14648 * sprite).
14649 */
14650 void intel_plane_destroy(struct drm_plane *plane)
14651 {
14652 if (!plane)
14653 return;
14654
14655 drm_plane_cleanup(plane);
14656 kfree(to_intel_plane(plane));
14657 }
14658
14659 const struct drm_plane_funcs intel_plane_funcs = {
14660 .update_plane = drm_atomic_helper_update_plane,
14661 .disable_plane = drm_atomic_helper_disable_plane,
14662 .destroy = intel_plane_destroy,
14663 .set_property = drm_atomic_helper_plane_set_property,
14664 .atomic_get_property = intel_plane_atomic_get_property,
14665 .atomic_set_property = intel_plane_atomic_set_property,
14666 .atomic_duplicate_state = intel_plane_duplicate_state,
14667 .atomic_destroy_state = intel_plane_destroy_state,
14668
14669 };
14670
14671 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14672 int pipe)
14673 {
14674 struct intel_plane *primary = NULL;
14675 struct intel_plane_state *state = NULL;
14676 const uint32_t *intel_primary_formats;
14677 unsigned int num_formats;
14678 int ret;
14679
14680 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14681 if (!primary)
14682 goto fail;
14683
14684 state = intel_create_plane_state(&primary->base);
14685 if (!state)
14686 goto fail;
14687 primary->base.state = &state->base;
14688
14689 primary->can_scale = false;
14690 primary->max_downscale = 1;
14691 if (INTEL_INFO(dev)->gen >= 9) {
14692 primary->can_scale = true;
14693 state->scaler_id = -1;
14694 }
14695 primary->pipe = pipe;
14696 primary->plane = pipe;
14697 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14698 primary->check_plane = intel_check_primary_plane;
14699 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14700 primary->plane = !pipe;
14701
14702 if (INTEL_INFO(dev)->gen >= 9) {
14703 intel_primary_formats = skl_primary_formats;
14704 num_formats = ARRAY_SIZE(skl_primary_formats);
14705
14706 primary->update_plane = skylake_update_primary_plane;
14707 primary->disable_plane = skylake_disable_primary_plane;
14708 } else if (HAS_PCH_SPLIT(dev)) {
14709 intel_primary_formats = i965_primary_formats;
14710 num_formats = ARRAY_SIZE(i965_primary_formats);
14711
14712 primary->update_plane = ironlake_update_primary_plane;
14713 primary->disable_plane = i9xx_disable_primary_plane;
14714 } else if (INTEL_INFO(dev)->gen >= 4) {
14715 intel_primary_formats = i965_primary_formats;
14716 num_formats = ARRAY_SIZE(i965_primary_formats);
14717
14718 primary->update_plane = i9xx_update_primary_plane;
14719 primary->disable_plane = i9xx_disable_primary_plane;
14720 } else {
14721 intel_primary_formats = i8xx_primary_formats;
14722 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14723
14724 primary->update_plane = i9xx_update_primary_plane;
14725 primary->disable_plane = i9xx_disable_primary_plane;
14726 }
14727
14728 if (INTEL_INFO(dev)->gen >= 9)
14729 ret = drm_universal_plane_init(dev, &primary->base, 0,
14730 &intel_plane_funcs,
14731 intel_primary_formats, num_formats,
14732 DRM_PLANE_TYPE_PRIMARY,
14733 "plane 1%c", pipe_name(pipe));
14734 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14735 ret = drm_universal_plane_init(dev, &primary->base, 0,
14736 &intel_plane_funcs,
14737 intel_primary_formats, num_formats,
14738 DRM_PLANE_TYPE_PRIMARY,
14739 "primary %c", pipe_name(pipe));
14740 else
14741 ret = drm_universal_plane_init(dev, &primary->base, 0,
14742 &intel_plane_funcs,
14743 intel_primary_formats, num_formats,
14744 DRM_PLANE_TYPE_PRIMARY,
14745 "plane %c", plane_name(primary->plane));
14746 if (ret)
14747 goto fail;
14748
14749 if (INTEL_INFO(dev)->gen >= 4)
14750 intel_create_rotation_property(dev, primary);
14751
14752 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14753
14754 return &primary->base;
14755
14756 fail:
14757 kfree(state);
14758 kfree(primary);
14759
14760 return NULL;
14761 }
14762
14763 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14764 {
14765 if (!dev->mode_config.rotation_property) {
14766 unsigned long flags = DRM_ROTATE_0 |
14767 DRM_ROTATE_180;
14768
14769 if (INTEL_INFO(dev)->gen >= 9)
14770 flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
14771
14772 dev->mode_config.rotation_property =
14773 drm_mode_create_rotation_property(dev, flags);
14774 }
14775 if (dev->mode_config.rotation_property)
14776 drm_object_attach_property(&plane->base.base,
14777 dev->mode_config.rotation_property,
14778 plane->base.state->rotation);
14779 }
14780
14781 static int
14782 intel_check_cursor_plane(struct drm_plane *plane,
14783 struct intel_crtc_state *crtc_state,
14784 struct intel_plane_state *state)
14785 {
14786 struct drm_framebuffer *fb = state->base.fb;
14787 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14788 enum pipe pipe = to_intel_plane(plane)->pipe;
14789 unsigned stride;
14790 int ret;
14791
14792 ret = drm_plane_helper_check_state(&state->base,
14793 &state->clip,
14794 DRM_PLANE_HELPER_NO_SCALING,
14795 DRM_PLANE_HELPER_NO_SCALING,
14796 true, true);
14797 if (ret)
14798 return ret;
14799
14800 /* if we want to turn off the cursor ignore width and height */
14801 if (!obj)
14802 return 0;
14803
14804 /* Check for which cursor types we support */
14805 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14806 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14807 state->base.crtc_w, state->base.crtc_h);
14808 return -EINVAL;
14809 }
14810
14811 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14812 if (obj->base.size < stride * state->base.crtc_h) {
14813 DRM_DEBUG_KMS("buffer is too small\n");
14814 return -ENOMEM;
14815 }
14816
14817 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14818 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14819 return -EINVAL;
14820 }
14821
14822 /*
14823 * There's something wrong with the cursor on CHV pipe C.
14824 * If it straddles the left edge of the screen then
14825 * moving it away from the edge or disabling it often
14826 * results in a pipe underrun, and often that can lead to
14827 * dead pipe (constant underrun reported, and it scans
14828 * out just a solid color). To recover from that, the
14829 * display power well must be turned off and on again.
14830 * Refuse the put the cursor into that compromised position.
14831 */
14832 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14833 state->base.visible && state->base.crtc_x < 0) {
14834 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14835 return -EINVAL;
14836 }
14837
14838 return 0;
14839 }
14840
14841 static void
14842 intel_disable_cursor_plane(struct drm_plane *plane,
14843 struct drm_crtc *crtc)
14844 {
14845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14846
14847 intel_crtc->cursor_addr = 0;
14848 intel_crtc_update_cursor(crtc, NULL);
14849 }
14850
14851 static void
14852 intel_update_cursor_plane(struct drm_plane *plane,
14853 const struct intel_crtc_state *crtc_state,
14854 const struct intel_plane_state *state)
14855 {
14856 struct drm_crtc *crtc = crtc_state->base.crtc;
14857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14858 struct drm_device *dev = plane->dev;
14859 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14860 uint32_t addr;
14861
14862 if (!obj)
14863 addr = 0;
14864 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14865 addr = i915_gem_object_ggtt_offset(obj, NULL);
14866 else
14867 addr = obj->phys_handle->busaddr;
14868
14869 intel_crtc->cursor_addr = addr;
14870 intel_crtc_update_cursor(crtc, state);
14871 }
14872
14873 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14874 int pipe)
14875 {
14876 struct intel_plane *cursor = NULL;
14877 struct intel_plane_state *state = NULL;
14878 int ret;
14879
14880 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14881 if (!cursor)
14882 goto fail;
14883
14884 state = intel_create_plane_state(&cursor->base);
14885 if (!state)
14886 goto fail;
14887 cursor->base.state = &state->base;
14888
14889 cursor->can_scale = false;
14890 cursor->max_downscale = 1;
14891 cursor->pipe = pipe;
14892 cursor->plane = pipe;
14893 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14894 cursor->check_plane = intel_check_cursor_plane;
14895 cursor->update_plane = intel_update_cursor_plane;
14896 cursor->disable_plane = intel_disable_cursor_plane;
14897
14898 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14899 &intel_plane_funcs,
14900 intel_cursor_formats,
14901 ARRAY_SIZE(intel_cursor_formats),
14902 DRM_PLANE_TYPE_CURSOR,
14903 "cursor %c", pipe_name(pipe));
14904 if (ret)
14905 goto fail;
14906
14907 if (INTEL_INFO(dev)->gen >= 4) {
14908 if (!dev->mode_config.rotation_property)
14909 dev->mode_config.rotation_property =
14910 drm_mode_create_rotation_property(dev,
14911 DRM_ROTATE_0 |
14912 DRM_ROTATE_180);
14913 if (dev->mode_config.rotation_property)
14914 drm_object_attach_property(&cursor->base.base,
14915 dev->mode_config.rotation_property,
14916 state->base.rotation);
14917 }
14918
14919 if (INTEL_INFO(dev)->gen >=9)
14920 state->scaler_id = -1;
14921
14922 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14923
14924 return &cursor->base;
14925
14926 fail:
14927 kfree(state);
14928 kfree(cursor);
14929
14930 return NULL;
14931 }
14932
14933 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14934 struct intel_crtc_state *crtc_state)
14935 {
14936 int i;
14937 struct intel_scaler *intel_scaler;
14938 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14939
14940 for (i = 0; i < intel_crtc->num_scalers; i++) {
14941 intel_scaler = &scaler_state->scalers[i];
14942 intel_scaler->in_use = 0;
14943 intel_scaler->mode = PS_SCALER_MODE_DYN;
14944 }
14945
14946 scaler_state->scaler_id = -1;
14947 }
14948
14949 static void intel_crtc_init(struct drm_device *dev, int pipe)
14950 {
14951 struct drm_i915_private *dev_priv = to_i915(dev);
14952 struct intel_crtc *intel_crtc;
14953 struct intel_crtc_state *crtc_state = NULL;
14954 struct drm_plane *primary = NULL;
14955 struct drm_plane *cursor = NULL;
14956 int ret;
14957
14958 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14959 if (intel_crtc == NULL)
14960 return;
14961
14962 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14963 if (!crtc_state)
14964 goto fail;
14965 intel_crtc->config = crtc_state;
14966 intel_crtc->base.state = &crtc_state->base;
14967 crtc_state->base.crtc = &intel_crtc->base;
14968
14969 /* initialize shared scalers */
14970 if (INTEL_INFO(dev)->gen >= 9) {
14971 if (pipe == PIPE_C)
14972 intel_crtc->num_scalers = 1;
14973 else
14974 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14975
14976 skl_init_scalers(dev, intel_crtc, crtc_state);
14977 }
14978
14979 primary = intel_primary_plane_create(dev, pipe);
14980 if (!primary)
14981 goto fail;
14982
14983 cursor = intel_cursor_plane_create(dev, pipe);
14984 if (!cursor)
14985 goto fail;
14986
14987 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14988 cursor, &intel_crtc_funcs,
14989 "pipe %c", pipe_name(pipe));
14990 if (ret)
14991 goto fail;
14992
14993 /*
14994 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14995 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14996 */
14997 intel_crtc->pipe = pipe;
14998 intel_crtc->plane = pipe;
14999 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15000 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15001 intel_crtc->plane = !pipe;
15002 }
15003
15004 intel_crtc->cursor_base = ~0;
15005 intel_crtc->cursor_cntl = ~0;
15006 intel_crtc->cursor_size = ~0;
15007
15008 intel_crtc->wm.cxsr_allowed = true;
15009
15010 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15011 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15012 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15013 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15014
15015 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15016
15017 intel_color_init(&intel_crtc->base);
15018
15019 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15020 return;
15021
15022 fail:
15023 intel_plane_destroy(primary);
15024 intel_plane_destroy(cursor);
15025 kfree(crtc_state);
15026 kfree(intel_crtc);
15027 }
15028
15029 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15030 {
15031 struct drm_encoder *encoder = connector->base.encoder;
15032 struct drm_device *dev = connector->base.dev;
15033
15034 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15035
15036 if (!encoder || WARN_ON(!encoder->crtc))
15037 return INVALID_PIPE;
15038
15039 return to_intel_crtc(encoder->crtc)->pipe;
15040 }
15041
15042 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15043 struct drm_file *file)
15044 {
15045 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15046 struct drm_crtc *drmmode_crtc;
15047 struct intel_crtc *crtc;
15048
15049 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15050 if (!drmmode_crtc)
15051 return -ENOENT;
15052
15053 crtc = to_intel_crtc(drmmode_crtc);
15054 pipe_from_crtc_id->pipe = crtc->pipe;
15055
15056 return 0;
15057 }
15058
15059 static int intel_encoder_clones(struct intel_encoder *encoder)
15060 {
15061 struct drm_device *dev = encoder->base.dev;
15062 struct intel_encoder *source_encoder;
15063 int index_mask = 0;
15064 int entry = 0;
15065
15066 for_each_intel_encoder(dev, source_encoder) {
15067 if (encoders_cloneable(encoder, source_encoder))
15068 index_mask |= (1 << entry);
15069
15070 entry++;
15071 }
15072
15073 return index_mask;
15074 }
15075
15076 static bool has_edp_a(struct drm_device *dev)
15077 {
15078 struct drm_i915_private *dev_priv = to_i915(dev);
15079
15080 if (!IS_MOBILE(dev))
15081 return false;
15082
15083 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15084 return false;
15085
15086 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15087 return false;
15088
15089 return true;
15090 }
15091
15092 static bool intel_crt_present(struct drm_device *dev)
15093 {
15094 struct drm_i915_private *dev_priv = to_i915(dev);
15095
15096 if (INTEL_INFO(dev)->gen >= 9)
15097 return false;
15098
15099 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15100 return false;
15101
15102 if (IS_CHERRYVIEW(dev))
15103 return false;
15104
15105 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15106 return false;
15107
15108 /* DDI E can't be used if DDI A requires 4 lanes */
15109 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15110 return false;
15111
15112 if (!dev_priv->vbt.int_crt_support)
15113 return false;
15114
15115 return true;
15116 }
15117
15118 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15119 {
15120 int pps_num;
15121 int pps_idx;
15122
15123 if (HAS_DDI(dev_priv))
15124 return;
15125 /*
15126 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15127 * everywhere where registers can be write protected.
15128 */
15129 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15130 pps_num = 2;
15131 else
15132 pps_num = 1;
15133
15134 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15135 u32 val = I915_READ(PP_CONTROL(pps_idx));
15136
15137 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15138 I915_WRITE(PP_CONTROL(pps_idx), val);
15139 }
15140 }
15141
15142 static void intel_pps_init(struct drm_i915_private *dev_priv)
15143 {
15144 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15145 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15146 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15147 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15148 else
15149 dev_priv->pps_mmio_base = PPS_BASE;
15150
15151 intel_pps_unlock_regs_wa(dev_priv);
15152 }
15153
15154 static void intel_setup_outputs(struct drm_device *dev)
15155 {
15156 struct drm_i915_private *dev_priv = to_i915(dev);
15157 struct intel_encoder *encoder;
15158 bool dpd_is_edp = false;
15159
15160 intel_pps_init(dev_priv);
15161
15162 /*
15163 * intel_edp_init_connector() depends on this completing first, to
15164 * prevent the registeration of both eDP and LVDS and the incorrect
15165 * sharing of the PPS.
15166 */
15167 intel_lvds_init(dev);
15168
15169 if (intel_crt_present(dev))
15170 intel_crt_init(dev);
15171
15172 if (IS_BROXTON(dev)) {
15173 /*
15174 * FIXME: Broxton doesn't support port detection via the
15175 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15176 * detect the ports.
15177 */
15178 intel_ddi_init(dev, PORT_A);
15179 intel_ddi_init(dev, PORT_B);
15180 intel_ddi_init(dev, PORT_C);
15181
15182 intel_dsi_init(dev);
15183 } else if (HAS_DDI(dev)) {
15184 int found;
15185
15186 /*
15187 * Haswell uses DDI functions to detect digital outputs.
15188 * On SKL pre-D0 the strap isn't connected, so we assume
15189 * it's there.
15190 */
15191 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15192 /* WaIgnoreDDIAStrap: skl */
15193 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15194 intel_ddi_init(dev, PORT_A);
15195
15196 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15197 * register */
15198 found = I915_READ(SFUSE_STRAP);
15199
15200 if (found & SFUSE_STRAP_DDIB_DETECTED)
15201 intel_ddi_init(dev, PORT_B);
15202 if (found & SFUSE_STRAP_DDIC_DETECTED)
15203 intel_ddi_init(dev, PORT_C);
15204 if (found & SFUSE_STRAP_DDID_DETECTED)
15205 intel_ddi_init(dev, PORT_D);
15206 /*
15207 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15208 */
15209 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15210 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15211 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15212 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15213 intel_ddi_init(dev, PORT_E);
15214
15215 } else if (HAS_PCH_SPLIT(dev)) {
15216 int found;
15217 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15218
15219 if (has_edp_a(dev))
15220 intel_dp_init(dev, DP_A, PORT_A);
15221
15222 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15223 /* PCH SDVOB multiplex with HDMIB */
15224 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15225 if (!found)
15226 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15227 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15228 intel_dp_init(dev, PCH_DP_B, PORT_B);
15229 }
15230
15231 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15232 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15233
15234 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15235 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15236
15237 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15238 intel_dp_init(dev, PCH_DP_C, PORT_C);
15239
15240 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15241 intel_dp_init(dev, PCH_DP_D, PORT_D);
15242 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15243 bool has_edp, has_port;
15244
15245 /*
15246 * The DP_DETECTED bit is the latched state of the DDC
15247 * SDA pin at boot. However since eDP doesn't require DDC
15248 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15249 * eDP ports may have been muxed to an alternate function.
15250 * Thus we can't rely on the DP_DETECTED bit alone to detect
15251 * eDP ports. Consult the VBT as well as DP_DETECTED to
15252 * detect eDP ports.
15253 *
15254 * Sadly the straps seem to be missing sometimes even for HDMI
15255 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15256 * and VBT for the presence of the port. Additionally we can't
15257 * trust the port type the VBT declares as we've seen at least
15258 * HDMI ports that the VBT claim are DP or eDP.
15259 */
15260 has_edp = intel_dp_is_edp(dev, PORT_B);
15261 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15262 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15263 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15264 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15265 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15266
15267 has_edp = intel_dp_is_edp(dev, PORT_C);
15268 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15269 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15270 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15271 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15272 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15273
15274 if (IS_CHERRYVIEW(dev)) {
15275 /*
15276 * eDP not supported on port D,
15277 * so no need to worry about it
15278 */
15279 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15280 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15281 intel_dp_init(dev, CHV_DP_D, PORT_D);
15282 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15283 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15284 }
15285
15286 intel_dsi_init(dev);
15287 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15288 bool found = false;
15289
15290 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15291 DRM_DEBUG_KMS("probing SDVOB\n");
15292 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15293 if (!found && IS_G4X(dev)) {
15294 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15295 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15296 }
15297
15298 if (!found && IS_G4X(dev))
15299 intel_dp_init(dev, DP_B, PORT_B);
15300 }
15301
15302 /* Before G4X SDVOC doesn't have its own detect register */
15303
15304 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15305 DRM_DEBUG_KMS("probing SDVOC\n");
15306 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15307 }
15308
15309 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15310
15311 if (IS_G4X(dev)) {
15312 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15313 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15314 }
15315 if (IS_G4X(dev))
15316 intel_dp_init(dev, DP_C, PORT_C);
15317 }
15318
15319 if (IS_G4X(dev) &&
15320 (I915_READ(DP_D) & DP_DETECTED))
15321 intel_dp_init(dev, DP_D, PORT_D);
15322 } else if (IS_GEN2(dev))
15323 intel_dvo_init(dev);
15324
15325 if (SUPPORTS_TV(dev))
15326 intel_tv_init(dev);
15327
15328 intel_psr_init(dev);
15329
15330 for_each_intel_encoder(dev, encoder) {
15331 encoder->base.possible_crtcs = encoder->crtc_mask;
15332 encoder->base.possible_clones =
15333 intel_encoder_clones(encoder);
15334 }
15335
15336 intel_init_pch_refclk(dev);
15337
15338 drm_helper_move_panel_connectors_to_head(dev);
15339 }
15340
15341 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15342 {
15343 struct drm_device *dev = fb->dev;
15344 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15345
15346 drm_framebuffer_cleanup(fb);
15347 mutex_lock(&dev->struct_mutex);
15348 WARN_ON(!intel_fb->obj->framebuffer_references--);
15349 i915_gem_object_put(intel_fb->obj);
15350 mutex_unlock(&dev->struct_mutex);
15351 kfree(intel_fb);
15352 }
15353
15354 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15355 struct drm_file *file,
15356 unsigned int *handle)
15357 {
15358 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15359 struct drm_i915_gem_object *obj = intel_fb->obj;
15360
15361 if (obj->userptr.mm) {
15362 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15363 return -EINVAL;
15364 }
15365
15366 return drm_gem_handle_create(file, &obj->base, handle);
15367 }
15368
15369 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15370 struct drm_file *file,
15371 unsigned flags, unsigned color,
15372 struct drm_clip_rect *clips,
15373 unsigned num_clips)
15374 {
15375 struct drm_device *dev = fb->dev;
15376 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15377 struct drm_i915_gem_object *obj = intel_fb->obj;
15378
15379 mutex_lock(&dev->struct_mutex);
15380 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15381 mutex_unlock(&dev->struct_mutex);
15382
15383 return 0;
15384 }
15385
15386 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15387 .destroy = intel_user_framebuffer_destroy,
15388 .create_handle = intel_user_framebuffer_create_handle,
15389 .dirty = intel_user_framebuffer_dirty,
15390 };
15391
15392 static
15393 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15394 uint32_t pixel_format)
15395 {
15396 u32 gen = INTEL_INFO(dev)->gen;
15397
15398 if (gen >= 9) {
15399 int cpp = drm_format_plane_cpp(pixel_format, 0);
15400
15401 /* "The stride in bytes must not exceed the of the size of 8K
15402 * pixels and 32K bytes."
15403 */
15404 return min(8192 * cpp, 32768);
15405 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15406 return 32*1024;
15407 } else if (gen >= 4) {
15408 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15409 return 16*1024;
15410 else
15411 return 32*1024;
15412 } else if (gen >= 3) {
15413 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15414 return 8*1024;
15415 else
15416 return 16*1024;
15417 } else {
15418 /* XXX DSPC is limited to 4k tiled */
15419 return 8*1024;
15420 }
15421 }
15422
15423 static int intel_framebuffer_init(struct drm_device *dev,
15424 struct intel_framebuffer *intel_fb,
15425 struct drm_mode_fb_cmd2 *mode_cmd,
15426 struct drm_i915_gem_object *obj)
15427 {
15428 struct drm_i915_private *dev_priv = to_i915(dev);
15429 unsigned int tiling = i915_gem_object_get_tiling(obj);
15430 int ret;
15431 u32 pitch_limit, stride_alignment;
15432
15433 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15434
15435 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15436 /*
15437 * If there's a fence, enforce that
15438 * the fb modifier and tiling mode match.
15439 */
15440 if (tiling != I915_TILING_NONE &&
15441 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15442 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15443 return -EINVAL;
15444 }
15445 } else {
15446 if (tiling == I915_TILING_X) {
15447 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15448 } else if (tiling == I915_TILING_Y) {
15449 DRM_DEBUG("No Y tiling for legacy addfb\n");
15450 return -EINVAL;
15451 }
15452 }
15453
15454 /* Passed in modifier sanity checking. */
15455 switch (mode_cmd->modifier[0]) {
15456 case I915_FORMAT_MOD_Y_TILED:
15457 case I915_FORMAT_MOD_Yf_TILED:
15458 if (INTEL_INFO(dev)->gen < 9) {
15459 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15460 mode_cmd->modifier[0]);
15461 return -EINVAL;
15462 }
15463 case DRM_FORMAT_MOD_NONE:
15464 case I915_FORMAT_MOD_X_TILED:
15465 break;
15466 default:
15467 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15468 mode_cmd->modifier[0]);
15469 return -EINVAL;
15470 }
15471
15472 /*
15473 * gen2/3 display engine uses the fence if present,
15474 * so the tiling mode must match the fb modifier exactly.
15475 */
15476 if (INTEL_INFO(dev_priv)->gen < 4 &&
15477 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15478 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15479 return -EINVAL;
15480 }
15481
15482 stride_alignment = intel_fb_stride_alignment(dev_priv,
15483 mode_cmd->modifier[0],
15484 mode_cmd->pixel_format);
15485 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15486 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15487 mode_cmd->pitches[0], stride_alignment);
15488 return -EINVAL;
15489 }
15490
15491 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15492 mode_cmd->pixel_format);
15493 if (mode_cmd->pitches[0] > pitch_limit) {
15494 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15495 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15496 "tiled" : "linear",
15497 mode_cmd->pitches[0], pitch_limit);
15498 return -EINVAL;
15499 }
15500
15501 /*
15502 * If there's a fence, enforce that
15503 * the fb pitch and fence stride match.
15504 */
15505 if (tiling != I915_TILING_NONE &&
15506 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15507 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15508 mode_cmd->pitches[0],
15509 i915_gem_object_get_stride(obj));
15510 return -EINVAL;
15511 }
15512
15513 /* Reject formats not supported by any plane early. */
15514 switch (mode_cmd->pixel_format) {
15515 case DRM_FORMAT_C8:
15516 case DRM_FORMAT_RGB565:
15517 case DRM_FORMAT_XRGB8888:
15518 case DRM_FORMAT_ARGB8888:
15519 break;
15520 case DRM_FORMAT_XRGB1555:
15521 if (INTEL_INFO(dev)->gen > 3) {
15522 DRM_DEBUG("unsupported pixel format: %s\n",
15523 drm_get_format_name(mode_cmd->pixel_format));
15524 return -EINVAL;
15525 }
15526 break;
15527 case DRM_FORMAT_ABGR8888:
15528 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15529 INTEL_INFO(dev)->gen < 9) {
15530 DRM_DEBUG("unsupported pixel format: %s\n",
15531 drm_get_format_name(mode_cmd->pixel_format));
15532 return -EINVAL;
15533 }
15534 break;
15535 case DRM_FORMAT_XBGR8888:
15536 case DRM_FORMAT_XRGB2101010:
15537 case DRM_FORMAT_XBGR2101010:
15538 if (INTEL_INFO(dev)->gen < 4) {
15539 DRM_DEBUG("unsupported pixel format: %s\n",
15540 drm_get_format_name(mode_cmd->pixel_format));
15541 return -EINVAL;
15542 }
15543 break;
15544 case DRM_FORMAT_ABGR2101010:
15545 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15546 DRM_DEBUG("unsupported pixel format: %s\n",
15547 drm_get_format_name(mode_cmd->pixel_format));
15548 return -EINVAL;
15549 }
15550 break;
15551 case DRM_FORMAT_YUYV:
15552 case DRM_FORMAT_UYVY:
15553 case DRM_FORMAT_YVYU:
15554 case DRM_FORMAT_VYUY:
15555 if (INTEL_INFO(dev)->gen < 5) {
15556 DRM_DEBUG("unsupported pixel format: %s\n",
15557 drm_get_format_name(mode_cmd->pixel_format));
15558 return -EINVAL;
15559 }
15560 break;
15561 default:
15562 DRM_DEBUG("unsupported pixel format: %s\n",
15563 drm_get_format_name(mode_cmd->pixel_format));
15564 return -EINVAL;
15565 }
15566
15567 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15568 if (mode_cmd->offsets[0] != 0)
15569 return -EINVAL;
15570
15571 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15572 intel_fb->obj = obj;
15573
15574 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15575 if (ret)
15576 return ret;
15577
15578 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15579 if (ret) {
15580 DRM_ERROR("framebuffer init failed %d\n", ret);
15581 return ret;
15582 }
15583
15584 intel_fb->obj->framebuffer_references++;
15585
15586 return 0;
15587 }
15588
15589 static struct drm_framebuffer *
15590 intel_user_framebuffer_create(struct drm_device *dev,
15591 struct drm_file *filp,
15592 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15593 {
15594 struct drm_framebuffer *fb;
15595 struct drm_i915_gem_object *obj;
15596 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15597
15598 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15599 if (!obj)
15600 return ERR_PTR(-ENOENT);
15601
15602 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15603 if (IS_ERR(fb))
15604 i915_gem_object_put_unlocked(obj);
15605
15606 return fb;
15607 }
15608
15609 #ifndef CONFIG_DRM_FBDEV_EMULATION
15610 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15611 {
15612 }
15613 #endif
15614
15615 static const struct drm_mode_config_funcs intel_mode_funcs = {
15616 .fb_create = intel_user_framebuffer_create,
15617 .output_poll_changed = intel_fbdev_output_poll_changed,
15618 .atomic_check = intel_atomic_check,
15619 .atomic_commit = intel_atomic_commit,
15620 .atomic_state_alloc = intel_atomic_state_alloc,
15621 .atomic_state_clear = intel_atomic_state_clear,
15622 };
15623
15624 /**
15625 * intel_init_display_hooks - initialize the display modesetting hooks
15626 * @dev_priv: device private
15627 */
15628 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15629 {
15630 if (INTEL_INFO(dev_priv)->gen >= 9) {
15631 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15632 dev_priv->display.get_initial_plane_config =
15633 skylake_get_initial_plane_config;
15634 dev_priv->display.crtc_compute_clock =
15635 haswell_crtc_compute_clock;
15636 dev_priv->display.crtc_enable = haswell_crtc_enable;
15637 dev_priv->display.crtc_disable = haswell_crtc_disable;
15638 } else if (HAS_DDI(dev_priv)) {
15639 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15640 dev_priv->display.get_initial_plane_config =
15641 ironlake_get_initial_plane_config;
15642 dev_priv->display.crtc_compute_clock =
15643 haswell_crtc_compute_clock;
15644 dev_priv->display.crtc_enable = haswell_crtc_enable;
15645 dev_priv->display.crtc_disable = haswell_crtc_disable;
15646 } else if (HAS_PCH_SPLIT(dev_priv)) {
15647 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15648 dev_priv->display.get_initial_plane_config =
15649 ironlake_get_initial_plane_config;
15650 dev_priv->display.crtc_compute_clock =
15651 ironlake_crtc_compute_clock;
15652 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15653 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15654 } else if (IS_CHERRYVIEW(dev_priv)) {
15655 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15656 dev_priv->display.get_initial_plane_config =
15657 i9xx_get_initial_plane_config;
15658 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15659 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15660 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15661 } else if (IS_VALLEYVIEW(dev_priv)) {
15662 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15663 dev_priv->display.get_initial_plane_config =
15664 i9xx_get_initial_plane_config;
15665 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15666 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15667 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15668 } else if (IS_G4X(dev_priv)) {
15669 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15670 dev_priv->display.get_initial_plane_config =
15671 i9xx_get_initial_plane_config;
15672 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15673 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15674 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15675 } else if (IS_PINEVIEW(dev_priv)) {
15676 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15677 dev_priv->display.get_initial_plane_config =
15678 i9xx_get_initial_plane_config;
15679 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15680 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15681 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15682 } else if (!IS_GEN2(dev_priv)) {
15683 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15684 dev_priv->display.get_initial_plane_config =
15685 i9xx_get_initial_plane_config;
15686 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15687 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15688 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15689 } else {
15690 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15691 dev_priv->display.get_initial_plane_config =
15692 i9xx_get_initial_plane_config;
15693 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15694 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15695 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15696 }
15697
15698 /* Returns the core display clock speed */
15699 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15700 dev_priv->display.get_display_clock_speed =
15701 skylake_get_display_clock_speed;
15702 else if (IS_BROXTON(dev_priv))
15703 dev_priv->display.get_display_clock_speed =
15704 broxton_get_display_clock_speed;
15705 else if (IS_BROADWELL(dev_priv))
15706 dev_priv->display.get_display_clock_speed =
15707 broadwell_get_display_clock_speed;
15708 else if (IS_HASWELL(dev_priv))
15709 dev_priv->display.get_display_clock_speed =
15710 haswell_get_display_clock_speed;
15711 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15712 dev_priv->display.get_display_clock_speed =
15713 valleyview_get_display_clock_speed;
15714 else if (IS_GEN5(dev_priv))
15715 dev_priv->display.get_display_clock_speed =
15716 ilk_get_display_clock_speed;
15717 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15718 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15719 dev_priv->display.get_display_clock_speed =
15720 i945_get_display_clock_speed;
15721 else if (IS_GM45(dev_priv))
15722 dev_priv->display.get_display_clock_speed =
15723 gm45_get_display_clock_speed;
15724 else if (IS_CRESTLINE(dev_priv))
15725 dev_priv->display.get_display_clock_speed =
15726 i965gm_get_display_clock_speed;
15727 else if (IS_PINEVIEW(dev_priv))
15728 dev_priv->display.get_display_clock_speed =
15729 pnv_get_display_clock_speed;
15730 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15731 dev_priv->display.get_display_clock_speed =
15732 g33_get_display_clock_speed;
15733 else if (IS_I915G(dev_priv))
15734 dev_priv->display.get_display_clock_speed =
15735 i915_get_display_clock_speed;
15736 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15737 dev_priv->display.get_display_clock_speed =
15738 i9xx_misc_get_display_clock_speed;
15739 else if (IS_I915GM(dev_priv))
15740 dev_priv->display.get_display_clock_speed =
15741 i915gm_get_display_clock_speed;
15742 else if (IS_I865G(dev_priv))
15743 dev_priv->display.get_display_clock_speed =
15744 i865_get_display_clock_speed;
15745 else if (IS_I85X(dev_priv))
15746 dev_priv->display.get_display_clock_speed =
15747 i85x_get_display_clock_speed;
15748 else { /* 830 */
15749 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15750 dev_priv->display.get_display_clock_speed =
15751 i830_get_display_clock_speed;
15752 }
15753
15754 if (IS_GEN5(dev_priv)) {
15755 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15756 } else if (IS_GEN6(dev_priv)) {
15757 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15758 } else if (IS_IVYBRIDGE(dev_priv)) {
15759 /* FIXME: detect B0+ stepping and use auto training */
15760 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15761 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15762 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15763 }
15764
15765 if (IS_BROADWELL(dev_priv)) {
15766 dev_priv->display.modeset_commit_cdclk =
15767 broadwell_modeset_commit_cdclk;
15768 dev_priv->display.modeset_calc_cdclk =
15769 broadwell_modeset_calc_cdclk;
15770 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15771 dev_priv->display.modeset_commit_cdclk =
15772 valleyview_modeset_commit_cdclk;
15773 dev_priv->display.modeset_calc_cdclk =
15774 valleyview_modeset_calc_cdclk;
15775 } else if (IS_BROXTON(dev_priv)) {
15776 dev_priv->display.modeset_commit_cdclk =
15777 bxt_modeset_commit_cdclk;
15778 dev_priv->display.modeset_calc_cdclk =
15779 bxt_modeset_calc_cdclk;
15780 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15781 dev_priv->display.modeset_commit_cdclk =
15782 skl_modeset_commit_cdclk;
15783 dev_priv->display.modeset_calc_cdclk =
15784 skl_modeset_calc_cdclk;
15785 }
15786
15787 switch (INTEL_INFO(dev_priv)->gen) {
15788 case 2:
15789 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15790 break;
15791
15792 case 3:
15793 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15794 break;
15795
15796 case 4:
15797 case 5:
15798 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15799 break;
15800
15801 case 6:
15802 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15803 break;
15804 case 7:
15805 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15806 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15807 break;
15808 case 9:
15809 /* Drop through - unsupported since execlist only. */
15810 default:
15811 /* Default just returns -ENODEV to indicate unsupported */
15812 dev_priv->display.queue_flip = intel_default_queue_flip;
15813 }
15814 }
15815
15816 /*
15817 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15818 * resume, or other times. This quirk makes sure that's the case for
15819 * affected systems.
15820 */
15821 static void quirk_pipea_force(struct drm_device *dev)
15822 {
15823 struct drm_i915_private *dev_priv = to_i915(dev);
15824
15825 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15826 DRM_INFO("applying pipe a force quirk\n");
15827 }
15828
15829 static void quirk_pipeb_force(struct drm_device *dev)
15830 {
15831 struct drm_i915_private *dev_priv = to_i915(dev);
15832
15833 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15834 DRM_INFO("applying pipe b force quirk\n");
15835 }
15836
15837 /*
15838 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15839 */
15840 static void quirk_ssc_force_disable(struct drm_device *dev)
15841 {
15842 struct drm_i915_private *dev_priv = to_i915(dev);
15843 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15844 DRM_INFO("applying lvds SSC disable quirk\n");
15845 }
15846
15847 /*
15848 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15849 * brightness value
15850 */
15851 static void quirk_invert_brightness(struct drm_device *dev)
15852 {
15853 struct drm_i915_private *dev_priv = to_i915(dev);
15854 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15855 DRM_INFO("applying inverted panel brightness quirk\n");
15856 }
15857
15858 /* Some VBT's incorrectly indicate no backlight is present */
15859 static void quirk_backlight_present(struct drm_device *dev)
15860 {
15861 struct drm_i915_private *dev_priv = to_i915(dev);
15862 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15863 DRM_INFO("applying backlight present quirk\n");
15864 }
15865
15866 struct intel_quirk {
15867 int device;
15868 int subsystem_vendor;
15869 int subsystem_device;
15870 void (*hook)(struct drm_device *dev);
15871 };
15872
15873 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15874 struct intel_dmi_quirk {
15875 void (*hook)(struct drm_device *dev);
15876 const struct dmi_system_id (*dmi_id_list)[];
15877 };
15878
15879 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15880 {
15881 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15882 return 1;
15883 }
15884
15885 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15886 {
15887 .dmi_id_list = &(const struct dmi_system_id[]) {
15888 {
15889 .callback = intel_dmi_reverse_brightness,
15890 .ident = "NCR Corporation",
15891 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15892 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15893 },
15894 },
15895 { } /* terminating entry */
15896 },
15897 .hook = quirk_invert_brightness,
15898 },
15899 };
15900
15901 static struct intel_quirk intel_quirks[] = {
15902 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15903 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15904
15905 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15906 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15907
15908 /* 830 needs to leave pipe A & dpll A up */
15909 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15910
15911 /* 830 needs to leave pipe B & dpll B up */
15912 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15913
15914 /* Lenovo U160 cannot use SSC on LVDS */
15915 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15916
15917 /* Sony Vaio Y cannot use SSC on LVDS */
15918 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15919
15920 /* Acer Aspire 5734Z must invert backlight brightness */
15921 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15922
15923 /* Acer/eMachines G725 */
15924 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15925
15926 /* Acer/eMachines e725 */
15927 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15928
15929 /* Acer/Packard Bell NCL20 */
15930 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15931
15932 /* Acer Aspire 4736Z */
15933 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15934
15935 /* Acer Aspire 5336 */
15936 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15937
15938 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15939 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15940
15941 /* Acer C720 Chromebook (Core i3 4005U) */
15942 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15943
15944 /* Apple Macbook 2,1 (Core 2 T7400) */
15945 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15946
15947 /* Apple Macbook 4,1 */
15948 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15949
15950 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15951 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15952
15953 /* HP Chromebook 14 (Celeron 2955U) */
15954 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15955
15956 /* Dell Chromebook 11 */
15957 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15958
15959 /* Dell Chromebook 11 (2015 version) */
15960 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15961 };
15962
15963 static void intel_init_quirks(struct drm_device *dev)
15964 {
15965 struct pci_dev *d = dev->pdev;
15966 int i;
15967
15968 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15969 struct intel_quirk *q = &intel_quirks[i];
15970
15971 if (d->device == q->device &&
15972 (d->subsystem_vendor == q->subsystem_vendor ||
15973 q->subsystem_vendor == PCI_ANY_ID) &&
15974 (d->subsystem_device == q->subsystem_device ||
15975 q->subsystem_device == PCI_ANY_ID))
15976 q->hook(dev);
15977 }
15978 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15979 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15980 intel_dmi_quirks[i].hook(dev);
15981 }
15982 }
15983
15984 /* Disable the VGA plane that we never use */
15985 static void i915_disable_vga(struct drm_device *dev)
15986 {
15987 struct drm_i915_private *dev_priv = to_i915(dev);
15988 u8 sr1;
15989 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15990
15991 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15992 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15993 outb(SR01, VGA_SR_INDEX);
15994 sr1 = inb(VGA_SR_DATA);
15995 outb(sr1 | 1<<5, VGA_SR_DATA);
15996 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15997 udelay(300);
15998
15999 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16000 POSTING_READ(vga_reg);
16001 }
16002
16003 void intel_modeset_init_hw(struct drm_device *dev)
16004 {
16005 struct drm_i915_private *dev_priv = to_i915(dev);
16006
16007 intel_update_cdclk(dev);
16008
16009 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16010
16011 intel_init_clock_gating(dev);
16012 }
16013
16014 /*
16015 * Calculate what we think the watermarks should be for the state we've read
16016 * out of the hardware and then immediately program those watermarks so that
16017 * we ensure the hardware settings match our internal state.
16018 *
16019 * We can calculate what we think WM's should be by creating a duplicate of the
16020 * current state (which was constructed during hardware readout) and running it
16021 * through the atomic check code to calculate new watermark values in the
16022 * state object.
16023 */
16024 static void sanitize_watermarks(struct drm_device *dev)
16025 {
16026 struct drm_i915_private *dev_priv = to_i915(dev);
16027 struct drm_atomic_state *state;
16028 struct drm_crtc *crtc;
16029 struct drm_crtc_state *cstate;
16030 struct drm_modeset_acquire_ctx ctx;
16031 int ret;
16032 int i;
16033
16034 /* Only supported on platforms that use atomic watermark design */
16035 if (!dev_priv->display.optimize_watermarks)
16036 return;
16037
16038 /*
16039 * We need to hold connection_mutex before calling duplicate_state so
16040 * that the connector loop is protected.
16041 */
16042 drm_modeset_acquire_init(&ctx, 0);
16043 retry:
16044 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16045 if (ret == -EDEADLK) {
16046 drm_modeset_backoff(&ctx);
16047 goto retry;
16048 } else if (WARN_ON(ret)) {
16049 goto fail;
16050 }
16051
16052 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16053 if (WARN_ON(IS_ERR(state)))
16054 goto fail;
16055
16056 /*
16057 * Hardware readout is the only time we don't want to calculate
16058 * intermediate watermarks (since we don't trust the current
16059 * watermarks).
16060 */
16061 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16062
16063 ret = intel_atomic_check(dev, state);
16064 if (ret) {
16065 /*
16066 * If we fail here, it means that the hardware appears to be
16067 * programmed in a way that shouldn't be possible, given our
16068 * understanding of watermark requirements. This might mean a
16069 * mistake in the hardware readout code or a mistake in the
16070 * watermark calculations for a given platform. Raise a WARN
16071 * so that this is noticeable.
16072 *
16073 * If this actually happens, we'll have to just leave the
16074 * BIOS-programmed watermarks untouched and hope for the best.
16075 */
16076 WARN(true, "Could not determine valid watermarks for inherited state\n");
16077 goto fail;
16078 }
16079
16080 /* Write calculated watermark values back */
16081 for_each_crtc_in_state(state, crtc, cstate, i) {
16082 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16083
16084 cs->wm.need_postvbl_update = true;
16085 dev_priv->display.optimize_watermarks(cs);
16086 }
16087
16088 drm_atomic_state_free(state);
16089 fail:
16090 drm_modeset_drop_locks(&ctx);
16091 drm_modeset_acquire_fini(&ctx);
16092 }
16093
16094 void intel_modeset_init(struct drm_device *dev)
16095 {
16096 struct drm_i915_private *dev_priv = to_i915(dev);
16097 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16098 int sprite, ret;
16099 enum pipe pipe;
16100 struct intel_crtc *crtc;
16101
16102 drm_mode_config_init(dev);
16103
16104 dev->mode_config.min_width = 0;
16105 dev->mode_config.min_height = 0;
16106
16107 dev->mode_config.preferred_depth = 24;
16108 dev->mode_config.prefer_shadow = 1;
16109
16110 dev->mode_config.allow_fb_modifiers = true;
16111
16112 dev->mode_config.funcs = &intel_mode_funcs;
16113
16114 intel_init_quirks(dev);
16115
16116 intel_init_pm(dev);
16117
16118 if (INTEL_INFO(dev)->num_pipes == 0)
16119 return;
16120
16121 /*
16122 * There may be no VBT; and if the BIOS enabled SSC we can
16123 * just keep using it to avoid unnecessary flicker. Whereas if the
16124 * BIOS isn't using it, don't assume it will work even if the VBT
16125 * indicates as much.
16126 */
16127 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16128 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16129 DREF_SSC1_ENABLE);
16130
16131 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16132 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16133 bios_lvds_use_ssc ? "en" : "dis",
16134 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16135 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16136 }
16137 }
16138
16139 if (IS_GEN2(dev)) {
16140 dev->mode_config.max_width = 2048;
16141 dev->mode_config.max_height = 2048;
16142 } else if (IS_GEN3(dev)) {
16143 dev->mode_config.max_width = 4096;
16144 dev->mode_config.max_height = 4096;
16145 } else {
16146 dev->mode_config.max_width = 8192;
16147 dev->mode_config.max_height = 8192;
16148 }
16149
16150 if (IS_845G(dev) || IS_I865G(dev)) {
16151 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16152 dev->mode_config.cursor_height = 1023;
16153 } else if (IS_GEN2(dev)) {
16154 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16155 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16156 } else {
16157 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16158 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16159 }
16160
16161 dev->mode_config.fb_base = ggtt->mappable_base;
16162
16163 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16164 INTEL_INFO(dev)->num_pipes,
16165 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16166
16167 for_each_pipe(dev_priv, pipe) {
16168 intel_crtc_init(dev, pipe);
16169 for_each_sprite(dev_priv, pipe, sprite) {
16170 ret = intel_plane_init(dev, pipe, sprite);
16171 if (ret)
16172 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16173 pipe_name(pipe), sprite_name(pipe, sprite), ret);
16174 }
16175 }
16176
16177 intel_update_czclk(dev_priv);
16178 intel_update_cdclk(dev);
16179
16180 intel_shared_dpll_init(dev);
16181
16182 if (dev_priv->max_cdclk_freq == 0)
16183 intel_update_max_cdclk(dev);
16184
16185 /* Just disable it once at startup */
16186 i915_disable_vga(dev);
16187 intel_setup_outputs(dev);
16188
16189 drm_modeset_lock_all(dev);
16190 intel_modeset_setup_hw_state(dev);
16191 drm_modeset_unlock_all(dev);
16192
16193 for_each_intel_crtc(dev, crtc) {
16194 struct intel_initial_plane_config plane_config = {};
16195
16196 if (!crtc->active)
16197 continue;
16198
16199 /*
16200 * Note that reserving the BIOS fb up front prevents us
16201 * from stuffing other stolen allocations like the ring
16202 * on top. This prevents some ugliness at boot time, and
16203 * can even allow for smooth boot transitions if the BIOS
16204 * fb is large enough for the active pipe configuration.
16205 */
16206 dev_priv->display.get_initial_plane_config(crtc,
16207 &plane_config);
16208
16209 /*
16210 * If the fb is shared between multiple heads, we'll
16211 * just get the first one.
16212 */
16213 intel_find_initial_plane_obj(crtc, &plane_config);
16214 }
16215
16216 /*
16217 * Make sure hardware watermarks really match the state we read out.
16218 * Note that we need to do this after reconstructing the BIOS fb's
16219 * since the watermark calculation done here will use pstate->fb.
16220 */
16221 sanitize_watermarks(dev);
16222 }
16223
16224 static void intel_enable_pipe_a(struct drm_device *dev)
16225 {
16226 struct intel_connector *connector;
16227 struct drm_connector *crt = NULL;
16228 struct intel_load_detect_pipe load_detect_temp;
16229 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16230
16231 /* We can't just switch on the pipe A, we need to set things up with a
16232 * proper mode and output configuration. As a gross hack, enable pipe A
16233 * by enabling the load detect pipe once. */
16234 for_each_intel_connector(dev, connector) {
16235 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16236 crt = &connector->base;
16237 break;
16238 }
16239 }
16240
16241 if (!crt)
16242 return;
16243
16244 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16245 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16246 }
16247
16248 static bool
16249 intel_check_plane_mapping(struct intel_crtc *crtc)
16250 {
16251 struct drm_device *dev = crtc->base.dev;
16252 struct drm_i915_private *dev_priv = to_i915(dev);
16253 u32 val;
16254
16255 if (INTEL_INFO(dev)->num_pipes == 1)
16256 return true;
16257
16258 val = I915_READ(DSPCNTR(!crtc->plane));
16259
16260 if ((val & DISPLAY_PLANE_ENABLE) &&
16261 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16262 return false;
16263
16264 return true;
16265 }
16266
16267 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16268 {
16269 struct drm_device *dev = crtc->base.dev;
16270 struct intel_encoder *encoder;
16271
16272 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16273 return true;
16274
16275 return false;
16276 }
16277
16278 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
16279 {
16280 struct drm_device *dev = encoder->base.dev;
16281 struct intel_connector *connector;
16282
16283 for_each_connector_on_encoder(dev, &encoder->base, connector)
16284 return true;
16285
16286 return false;
16287 }
16288
16289 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16290 enum transcoder pch_transcoder)
16291 {
16292 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16293 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16294 }
16295
16296 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16297 {
16298 struct drm_device *dev = crtc->base.dev;
16299 struct drm_i915_private *dev_priv = to_i915(dev);
16300 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16301
16302 /* Clear any frame start delays used for debugging left by the BIOS */
16303 if (!transcoder_is_dsi(cpu_transcoder)) {
16304 i915_reg_t reg = PIPECONF(cpu_transcoder);
16305
16306 I915_WRITE(reg,
16307 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16308 }
16309
16310 /* restore vblank interrupts to correct state */
16311 drm_crtc_vblank_reset(&crtc->base);
16312 if (crtc->active) {
16313 struct intel_plane *plane;
16314
16315 drm_crtc_vblank_on(&crtc->base);
16316
16317 /* Disable everything but the primary plane */
16318 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16319 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16320 continue;
16321
16322 plane->disable_plane(&plane->base, &crtc->base);
16323 }
16324 }
16325
16326 /* We need to sanitize the plane -> pipe mapping first because this will
16327 * disable the crtc (and hence change the state) if it is wrong. Note
16328 * that gen4+ has a fixed plane -> pipe mapping. */
16329 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16330 bool plane;
16331
16332 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16333 crtc->base.base.id, crtc->base.name);
16334
16335 /* Pipe has the wrong plane attached and the plane is active.
16336 * Temporarily change the plane mapping and disable everything
16337 * ... */
16338 plane = crtc->plane;
16339 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16340 crtc->plane = !plane;
16341 intel_crtc_disable_noatomic(&crtc->base);
16342 crtc->plane = plane;
16343 }
16344
16345 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16346 crtc->pipe == PIPE_A && !crtc->active) {
16347 /* BIOS forgot to enable pipe A, this mostly happens after
16348 * resume. Force-enable the pipe to fix this, the update_dpms
16349 * call below we restore the pipe to the right state, but leave
16350 * the required bits on. */
16351 intel_enable_pipe_a(dev);
16352 }
16353
16354 /* Adjust the state of the output pipe according to whether we
16355 * have active connectors/encoders. */
16356 if (crtc->active && !intel_crtc_has_encoders(crtc))
16357 intel_crtc_disable_noatomic(&crtc->base);
16358
16359 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16360 /*
16361 * We start out with underrun reporting disabled to avoid races.
16362 * For correct bookkeeping mark this on active crtcs.
16363 *
16364 * Also on gmch platforms we dont have any hardware bits to
16365 * disable the underrun reporting. Which means we need to start
16366 * out with underrun reporting disabled also on inactive pipes,
16367 * since otherwise we'll complain about the garbage we read when
16368 * e.g. coming up after runtime pm.
16369 *
16370 * No protection against concurrent access is required - at
16371 * worst a fifo underrun happens which also sets this to false.
16372 */
16373 crtc->cpu_fifo_underrun_disabled = true;
16374 /*
16375 * We track the PCH trancoder underrun reporting state
16376 * within the crtc. With crtc for pipe A housing the underrun
16377 * reporting state for PCH transcoder A, crtc for pipe B housing
16378 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16379 * and marking underrun reporting as disabled for the non-existing
16380 * PCH transcoders B and C would prevent enabling the south
16381 * error interrupt (see cpt_can_enable_serr_int()).
16382 */
16383 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16384 crtc->pch_fifo_underrun_disabled = true;
16385 }
16386 }
16387
16388 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16389 {
16390 struct intel_connector *connector;
16391 struct drm_device *dev = encoder->base.dev;
16392
16393 /* We need to check both for a crtc link (meaning that the
16394 * encoder is active and trying to read from a pipe) and the
16395 * pipe itself being active. */
16396 bool has_active_crtc = encoder->base.crtc &&
16397 to_intel_crtc(encoder->base.crtc)->active;
16398
16399 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
16400 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16401 encoder->base.base.id,
16402 encoder->base.name);
16403
16404 /* Connector is active, but has no active pipe. This is
16405 * fallout from our resume register restoring. Disable
16406 * the encoder manually again. */
16407 if (encoder->base.crtc) {
16408 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16409 encoder->base.base.id,
16410 encoder->base.name);
16411 encoder->disable(encoder);
16412 if (encoder->post_disable)
16413 encoder->post_disable(encoder);
16414 }
16415 encoder->base.crtc = NULL;
16416
16417 /* Inconsistent output/port/pipe state happens presumably due to
16418 * a bug in one of the get_hw_state functions. Or someplace else
16419 * in our code, like the register restore mess on resume. Clamp
16420 * things to off as a safer default. */
16421 for_each_intel_connector(dev, connector) {
16422 if (connector->encoder != encoder)
16423 continue;
16424 connector->base.dpms = DRM_MODE_DPMS_OFF;
16425 connector->base.encoder = NULL;
16426 }
16427 }
16428 /* Enabled encoders without active connectors will be fixed in
16429 * the crtc fixup. */
16430 }
16431
16432 void i915_redisable_vga_power_on(struct drm_device *dev)
16433 {
16434 struct drm_i915_private *dev_priv = to_i915(dev);
16435 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16436
16437 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16438 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16439 i915_disable_vga(dev);
16440 }
16441 }
16442
16443 void i915_redisable_vga(struct drm_device *dev)
16444 {
16445 struct drm_i915_private *dev_priv = to_i915(dev);
16446
16447 /* This function can be called both from intel_modeset_setup_hw_state or
16448 * at a very early point in our resume sequence, where the power well
16449 * structures are not yet restored. Since this function is at a very
16450 * paranoid "someone might have enabled VGA while we were not looking"
16451 * level, just check if the power well is enabled instead of trying to
16452 * follow the "don't touch the power well if we don't need it" policy
16453 * the rest of the driver uses. */
16454 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16455 return;
16456
16457 i915_redisable_vga_power_on(dev);
16458
16459 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16460 }
16461
16462 static bool primary_get_hw_state(struct intel_plane *plane)
16463 {
16464 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16465
16466 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16467 }
16468
16469 /* FIXME read out full plane state for all planes */
16470 static void readout_plane_state(struct intel_crtc *crtc)
16471 {
16472 struct drm_plane *primary = crtc->base.primary;
16473 struct intel_plane_state *plane_state =
16474 to_intel_plane_state(primary->state);
16475
16476 plane_state->base.visible = crtc->active &&
16477 primary_get_hw_state(to_intel_plane(primary));
16478
16479 if (plane_state->base.visible)
16480 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16481 }
16482
16483 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16484 {
16485 struct drm_i915_private *dev_priv = to_i915(dev);
16486 enum pipe pipe;
16487 struct intel_crtc *crtc;
16488 struct intel_encoder *encoder;
16489 struct intel_connector *connector;
16490 int i;
16491
16492 dev_priv->active_crtcs = 0;
16493
16494 for_each_intel_crtc(dev, crtc) {
16495 struct intel_crtc_state *crtc_state = crtc->config;
16496 int pixclk = 0;
16497
16498 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16499 memset(crtc_state, 0, sizeof(*crtc_state));
16500 crtc_state->base.crtc = &crtc->base;
16501
16502 crtc_state->base.active = crtc_state->base.enable =
16503 dev_priv->display.get_pipe_config(crtc, crtc_state);
16504
16505 crtc->base.enabled = crtc_state->base.enable;
16506 crtc->active = crtc_state->base.active;
16507
16508 if (crtc_state->base.active) {
16509 dev_priv->active_crtcs |= 1 << crtc->pipe;
16510
16511 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16512 pixclk = ilk_pipe_pixel_rate(crtc_state);
16513 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16514 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16515 else
16516 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16517
16518 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16519 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16520 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16521 }
16522
16523 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16524
16525 readout_plane_state(crtc);
16526
16527 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16528 crtc->base.base.id, crtc->base.name,
16529 crtc->active ? "enabled" : "disabled");
16530 }
16531
16532 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16533 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16534
16535 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16536 &pll->config.hw_state);
16537 pll->config.crtc_mask = 0;
16538 for_each_intel_crtc(dev, crtc) {
16539 if (crtc->active && crtc->config->shared_dpll == pll)
16540 pll->config.crtc_mask |= 1 << crtc->pipe;
16541 }
16542 pll->active_mask = pll->config.crtc_mask;
16543
16544 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16545 pll->name, pll->config.crtc_mask, pll->on);
16546 }
16547
16548 for_each_intel_encoder(dev, encoder) {
16549 pipe = 0;
16550
16551 if (encoder->get_hw_state(encoder, &pipe)) {
16552 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16553 encoder->base.crtc = &crtc->base;
16554 crtc->config->output_types |= 1 << encoder->type;
16555 encoder->get_config(encoder, crtc->config);
16556 } else {
16557 encoder->base.crtc = NULL;
16558 }
16559
16560 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16561 encoder->base.base.id,
16562 encoder->base.name,
16563 encoder->base.crtc ? "enabled" : "disabled",
16564 pipe_name(pipe));
16565 }
16566
16567 for_each_intel_connector(dev, connector) {
16568 if (connector->get_hw_state(connector)) {
16569 connector->base.dpms = DRM_MODE_DPMS_ON;
16570
16571 encoder = connector->encoder;
16572 connector->base.encoder = &encoder->base;
16573
16574 if (encoder->base.crtc &&
16575 encoder->base.crtc->state->active) {
16576 /*
16577 * This has to be done during hardware readout
16578 * because anything calling .crtc_disable may
16579 * rely on the connector_mask being accurate.
16580 */
16581 encoder->base.crtc->state->connector_mask |=
16582 1 << drm_connector_index(&connector->base);
16583 encoder->base.crtc->state->encoder_mask |=
16584 1 << drm_encoder_index(&encoder->base);
16585 }
16586
16587 } else {
16588 connector->base.dpms = DRM_MODE_DPMS_OFF;
16589 connector->base.encoder = NULL;
16590 }
16591 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16592 connector->base.base.id,
16593 connector->base.name,
16594 connector->base.encoder ? "enabled" : "disabled");
16595 }
16596
16597 for_each_intel_crtc(dev, crtc) {
16598 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16599
16600 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16601 if (crtc->base.state->active) {
16602 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16603 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16604 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16605
16606 /*
16607 * The initial mode needs to be set in order to keep
16608 * the atomic core happy. It wants a valid mode if the
16609 * crtc's enabled, so we do the above call.
16610 *
16611 * At this point some state updated by the connectors
16612 * in their ->detect() callback has not run yet, so
16613 * no recalculation can be done yet.
16614 *
16615 * Even if we could do a recalculation and modeset
16616 * right now it would cause a double modeset if
16617 * fbdev or userspace chooses a different initial mode.
16618 *
16619 * If that happens, someone indicated they wanted a
16620 * mode change, which means it's safe to do a full
16621 * recalculation.
16622 */
16623 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16624
16625 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16626 update_scanline_offset(crtc);
16627 }
16628
16629 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16630 }
16631 }
16632
16633 /* Scan out the current hw modeset state,
16634 * and sanitizes it to the current state
16635 */
16636 static void
16637 intel_modeset_setup_hw_state(struct drm_device *dev)
16638 {
16639 struct drm_i915_private *dev_priv = to_i915(dev);
16640 enum pipe pipe;
16641 struct intel_crtc *crtc;
16642 struct intel_encoder *encoder;
16643 int i;
16644
16645 intel_modeset_readout_hw_state(dev);
16646
16647 /* HW state is read out, now we need to sanitize this mess. */
16648 for_each_intel_encoder(dev, encoder) {
16649 intel_sanitize_encoder(encoder);
16650 }
16651
16652 for_each_pipe(dev_priv, pipe) {
16653 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16654 intel_sanitize_crtc(crtc);
16655 intel_dump_pipe_config(crtc, crtc->config,
16656 "[setup_hw_state]");
16657 }
16658
16659 intel_modeset_update_connector_atomic_state(dev);
16660
16661 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16662 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16663
16664 if (!pll->on || pll->active_mask)
16665 continue;
16666
16667 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16668
16669 pll->funcs.disable(dev_priv, pll);
16670 pll->on = false;
16671 }
16672
16673 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16674 vlv_wm_get_hw_state(dev);
16675 else if (IS_GEN9(dev))
16676 skl_wm_get_hw_state(dev);
16677 else if (HAS_PCH_SPLIT(dev))
16678 ilk_wm_get_hw_state(dev);
16679
16680 for_each_intel_crtc(dev, crtc) {
16681 unsigned long put_domains;
16682
16683 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16684 if (WARN_ON(put_domains))
16685 modeset_put_power_domains(dev_priv, put_domains);
16686 }
16687 intel_display_set_init_power(dev_priv, false);
16688
16689 intel_fbc_init_pipe_state(dev_priv);
16690 }
16691
16692 void intel_display_resume(struct drm_device *dev)
16693 {
16694 struct drm_i915_private *dev_priv = to_i915(dev);
16695 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16696 struct drm_modeset_acquire_ctx ctx;
16697 int ret;
16698
16699 dev_priv->modeset_restore_state = NULL;
16700 if (state)
16701 state->acquire_ctx = &ctx;
16702
16703 /*
16704 * This is a cludge because with real atomic modeset mode_config.mutex
16705 * won't be taken. Unfortunately some probed state like
16706 * audio_codec_enable is still protected by mode_config.mutex, so lock
16707 * it here for now.
16708 */
16709 mutex_lock(&dev->mode_config.mutex);
16710 drm_modeset_acquire_init(&ctx, 0);
16711
16712 while (1) {
16713 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16714 if (ret != -EDEADLK)
16715 break;
16716
16717 drm_modeset_backoff(&ctx);
16718 }
16719
16720 if (!ret)
16721 ret = __intel_display_resume(dev, state);
16722
16723 drm_modeset_drop_locks(&ctx);
16724 drm_modeset_acquire_fini(&ctx);
16725 mutex_unlock(&dev->mode_config.mutex);
16726
16727 if (ret) {
16728 DRM_ERROR("Restoring old state failed with %i\n", ret);
16729 drm_atomic_state_free(state);
16730 }
16731 }
16732
16733 void intel_modeset_gem_init(struct drm_device *dev)
16734 {
16735 struct drm_i915_private *dev_priv = to_i915(dev);
16736 struct drm_crtc *c;
16737 struct drm_i915_gem_object *obj;
16738
16739 intel_init_gt_powersave(dev_priv);
16740
16741 intel_modeset_init_hw(dev);
16742
16743 intel_setup_overlay(dev_priv);
16744
16745 /*
16746 * Make sure any fbs we allocated at startup are properly
16747 * pinned & fenced. When we do the allocation it's too early
16748 * for this.
16749 */
16750 for_each_crtc(dev, c) {
16751 struct i915_vma *vma;
16752
16753 obj = intel_fb_obj(c->primary->fb);
16754 if (obj == NULL)
16755 continue;
16756
16757 mutex_lock(&dev->struct_mutex);
16758 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
16759 c->primary->state->rotation);
16760 mutex_unlock(&dev->struct_mutex);
16761 if (IS_ERR(vma)) {
16762 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16763 to_intel_crtc(c)->pipe);
16764 drm_framebuffer_unreference(c->primary->fb);
16765 c->primary->fb = NULL;
16766 c->primary->crtc = c->primary->state->crtc = NULL;
16767 update_state_fb(c->primary);
16768 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16769 }
16770 }
16771 }
16772
16773 int intel_connector_register(struct drm_connector *connector)
16774 {
16775 struct intel_connector *intel_connector = to_intel_connector(connector);
16776 int ret;
16777
16778 ret = intel_backlight_device_register(intel_connector);
16779 if (ret)
16780 goto err;
16781
16782 return 0;
16783
16784 err:
16785 return ret;
16786 }
16787
16788 void intel_connector_unregister(struct drm_connector *connector)
16789 {
16790 struct intel_connector *intel_connector = to_intel_connector(connector);
16791
16792 intel_backlight_device_unregister(intel_connector);
16793 intel_panel_destroy_backlight(connector);
16794 }
16795
16796 void intel_modeset_cleanup(struct drm_device *dev)
16797 {
16798 struct drm_i915_private *dev_priv = to_i915(dev);
16799
16800 intel_disable_gt_powersave(dev_priv);
16801
16802 /*
16803 * Interrupts and polling as the first thing to avoid creating havoc.
16804 * Too much stuff here (turning of connectors, ...) would
16805 * experience fancy races otherwise.
16806 */
16807 intel_irq_uninstall(dev_priv);
16808
16809 /*
16810 * Due to the hpd irq storm handling the hotplug work can re-arm the
16811 * poll handlers. Hence disable polling after hpd handling is shut down.
16812 */
16813 drm_kms_helper_poll_fini(dev);
16814
16815 intel_unregister_dsm_handler();
16816
16817 intel_fbc_global_disable(dev_priv);
16818
16819 /* flush any delayed tasks or pending work */
16820 flush_scheduled_work();
16821
16822 drm_mode_config_cleanup(dev);
16823
16824 intel_cleanup_overlay(dev_priv);
16825
16826 intel_cleanup_gt_powersave(dev_priv);
16827
16828 intel_teardown_gmbus(dev);
16829 }
16830
16831 void intel_connector_attach_encoder(struct intel_connector *connector,
16832 struct intel_encoder *encoder)
16833 {
16834 connector->encoder = encoder;
16835 drm_mode_connector_attach_encoder(&connector->base,
16836 &encoder->base);
16837 }
16838
16839 /*
16840 * set vga decode state - true == enable VGA decode
16841 */
16842 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16843 {
16844 struct drm_i915_private *dev_priv = to_i915(dev);
16845 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16846 u16 gmch_ctrl;
16847
16848 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16849 DRM_ERROR("failed to read control word\n");
16850 return -EIO;
16851 }
16852
16853 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16854 return 0;
16855
16856 if (state)
16857 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16858 else
16859 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16860
16861 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16862 DRM_ERROR("failed to write control word\n");
16863 return -EIO;
16864 }
16865
16866 return 0;
16867 }
16868
16869 struct intel_display_error_state {
16870
16871 u32 power_well_driver;
16872
16873 int num_transcoders;
16874
16875 struct intel_cursor_error_state {
16876 u32 control;
16877 u32 position;
16878 u32 base;
16879 u32 size;
16880 } cursor[I915_MAX_PIPES];
16881
16882 struct intel_pipe_error_state {
16883 bool power_domain_on;
16884 u32 source;
16885 u32 stat;
16886 } pipe[I915_MAX_PIPES];
16887
16888 struct intel_plane_error_state {
16889 u32 control;
16890 u32 stride;
16891 u32 size;
16892 u32 pos;
16893 u32 addr;
16894 u32 surface;
16895 u32 tile_offset;
16896 } plane[I915_MAX_PIPES];
16897
16898 struct intel_transcoder_error_state {
16899 bool power_domain_on;
16900 enum transcoder cpu_transcoder;
16901
16902 u32 conf;
16903
16904 u32 htotal;
16905 u32 hblank;
16906 u32 hsync;
16907 u32 vtotal;
16908 u32 vblank;
16909 u32 vsync;
16910 } transcoder[4];
16911 };
16912
16913 struct intel_display_error_state *
16914 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16915 {
16916 struct intel_display_error_state *error;
16917 int transcoders[] = {
16918 TRANSCODER_A,
16919 TRANSCODER_B,
16920 TRANSCODER_C,
16921 TRANSCODER_EDP,
16922 };
16923 int i;
16924
16925 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16926 return NULL;
16927
16928 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16929 if (error == NULL)
16930 return NULL;
16931
16932 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16933 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16934
16935 for_each_pipe(dev_priv, i) {
16936 error->pipe[i].power_domain_on =
16937 __intel_display_power_is_enabled(dev_priv,
16938 POWER_DOMAIN_PIPE(i));
16939 if (!error->pipe[i].power_domain_on)
16940 continue;
16941
16942 error->cursor[i].control = I915_READ(CURCNTR(i));
16943 error->cursor[i].position = I915_READ(CURPOS(i));
16944 error->cursor[i].base = I915_READ(CURBASE(i));
16945
16946 error->plane[i].control = I915_READ(DSPCNTR(i));
16947 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16948 if (INTEL_GEN(dev_priv) <= 3) {
16949 error->plane[i].size = I915_READ(DSPSIZE(i));
16950 error->plane[i].pos = I915_READ(DSPPOS(i));
16951 }
16952 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16953 error->plane[i].addr = I915_READ(DSPADDR(i));
16954 if (INTEL_GEN(dev_priv) >= 4) {
16955 error->plane[i].surface = I915_READ(DSPSURF(i));
16956 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16957 }
16958
16959 error->pipe[i].source = I915_READ(PIPESRC(i));
16960
16961 if (HAS_GMCH_DISPLAY(dev_priv))
16962 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16963 }
16964
16965 /* Note: this does not include DSI transcoders. */
16966 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16967 if (HAS_DDI(dev_priv))
16968 error->num_transcoders++; /* Account for eDP. */
16969
16970 for (i = 0; i < error->num_transcoders; i++) {
16971 enum transcoder cpu_transcoder = transcoders[i];
16972
16973 error->transcoder[i].power_domain_on =
16974 __intel_display_power_is_enabled(dev_priv,
16975 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16976 if (!error->transcoder[i].power_domain_on)
16977 continue;
16978
16979 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16980
16981 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16982 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16983 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16984 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16985 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16986 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16987 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16988 }
16989
16990 return error;
16991 }
16992
16993 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16994
16995 void
16996 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16997 struct drm_device *dev,
16998 struct intel_display_error_state *error)
16999 {
17000 struct drm_i915_private *dev_priv = to_i915(dev);
17001 int i;
17002
17003 if (!error)
17004 return;
17005
17006 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17007 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17008 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17009 error->power_well_driver);
17010 for_each_pipe(dev_priv, i) {
17011 err_printf(m, "Pipe [%d]:\n", i);
17012 err_printf(m, " Power: %s\n",
17013 onoff(error->pipe[i].power_domain_on));
17014 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17015 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17016
17017 err_printf(m, "Plane [%d]:\n", i);
17018 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17019 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17020 if (INTEL_INFO(dev)->gen <= 3) {
17021 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17022 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17023 }
17024 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17025 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17026 if (INTEL_INFO(dev)->gen >= 4) {
17027 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17028 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17029 }
17030
17031 err_printf(m, "Cursor [%d]:\n", i);
17032 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17033 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17034 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17035 }
17036
17037 for (i = 0; i < error->num_transcoders; i++) {
17038 err_printf(m, "CPU transcoder: %s\n",
17039 transcoder_name(error->transcoder[i].cpu_transcoder));
17040 err_printf(m, " Power: %s\n",
17041 onoff(error->transcoder[i].power_domain_on));
17042 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17043 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17044 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17045 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17046 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17047 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17048 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17049 }
17050 }
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