]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
90
91 static const uint64_t skl_format_modifiers_noccs[] = {
92 I915_FORMAT_MOD_Yf_TILED,
93 I915_FORMAT_MOD_Y_TILED,
94 I915_FORMAT_MOD_X_TILED,
95 DRM_FORMAT_MOD_LINEAR,
96 DRM_FORMAT_MOD_INVALID
97 };
98
99 static const uint64_t skl_format_modifiers_ccs[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS,
101 I915_FORMAT_MOD_Y_TILED_CCS,
102 I915_FORMAT_MOD_Yf_TILED,
103 I915_FORMAT_MOD_Y_TILED,
104 I915_FORMAT_MOD_X_TILED,
105 DRM_FORMAT_MOD_LINEAR,
106 DRM_FORMAT_MOD_INVALID
107 };
108
109 /* Cursor formats */
110 static const uint32_t intel_cursor_formats[] = {
111 DRM_FORMAT_ARGB8888,
112 };
113
114 static const uint64_t cursor_format_modifiers[] = {
115 DRM_FORMAT_MOD_LINEAR,
116 DRM_FORMAT_MOD_INVALID
117 };
118
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122 struct intel_crtc_state *pipe_config);
123
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125 struct drm_i915_gem_object *obj,
126 struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131 struct intel_link_m_n *m_n,
132 struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139 const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143 struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148 struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150
151 struct intel_limit {
152 struct {
153 int min, max;
154 } dot, vco, n, m, m1, m2, p, p1;
155
156 struct {
157 int dot_limit;
158 int p2_slow, p2_fast;
159 } p2;
160 };
161
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
164 {
165 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
166
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv->sb_lock);
169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170 CCK_FUSE_HPLL_FREQ_MASK;
171 mutex_unlock(&dev_priv->sb_lock);
172
173 return vco_freq[hpll_freq] * 1000;
174 }
175
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177 const char *name, u32 reg, int ref_freq)
178 {
179 u32 val;
180 int divider;
181
182 mutex_lock(&dev_priv->sb_lock);
183 val = vlv_cck_read(dev_priv, reg);
184 mutex_unlock(&dev_priv->sb_lock);
185
186 divider = val & CCK_FREQUENCY_VALUES;
187
188 WARN((val & CCK_FREQUENCY_STATUS) !=
189 (divider << CCK_FREQUENCY_STATUS_SHIFT),
190 "%s change in progress\n", name);
191
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
193 }
194
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196 const char *name, u32 reg)
197 {
198 if (dev_priv->hpll_freq == 0)
199 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
200
201 return vlv_get_cck_clock(dev_priv, name, reg,
202 dev_priv->hpll_freq);
203 }
204
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
206 {
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208 return;
209
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
212
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 }
215
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
219 {
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
222 else if (IS_GEN5(dev_priv))
223 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
224 else
225 return 270000;
226 }
227
228 static const struct intel_limit intel_limits_i8xx_dac = {
229 .dot = { .min = 25000, .max = 350000 },
230 .vco = { .min = 908000, .max = 1512000 },
231 .n = { .min = 2, .max = 16 },
232 .m = { .min = 96, .max = 140 },
233 .m1 = { .min = 18, .max = 26 },
234 .m2 = { .min = 6, .max = 16 },
235 .p = { .min = 4, .max = 128 },
236 .p1 = { .min = 2, .max = 33 },
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 4, .p2_fast = 2 },
239 };
240
241 static const struct intel_limit intel_limits_i8xx_dvo = {
242 .dot = { .min = 25000, .max = 350000 },
243 .vco = { .min = 908000, .max = 1512000 },
244 .n = { .min = 2, .max = 16 },
245 .m = { .min = 96, .max = 140 },
246 .m1 = { .min = 18, .max = 26 },
247 .m2 = { .min = 6, .max = 16 },
248 .p = { .min = 4, .max = 128 },
249 .p1 = { .min = 2, .max = 33 },
250 .p2 = { .dot_limit = 165000,
251 .p2_slow = 4, .p2_fast = 4 },
252 };
253
254 static const struct intel_limit intel_limits_i8xx_lvds = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 1, .max = 6 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 14, .p2_fast = 7 },
265 };
266
267 static const struct intel_limit intel_limits_i9xx_sdvo = {
268 .dot = { .min = 20000, .max = 400000 },
269 .vco = { .min = 1400000, .max = 2800000 },
270 .n = { .min = 1, .max = 6 },
271 .m = { .min = 70, .max = 120 },
272 .m1 = { .min = 8, .max = 18 },
273 .m2 = { .min = 3, .max = 7 },
274 .p = { .min = 5, .max = 80 },
275 .p1 = { .min = 1, .max = 8 },
276 .p2 = { .dot_limit = 200000,
277 .p2_slow = 10, .p2_fast = 5 },
278 };
279
280 static const struct intel_limit intel_limits_i9xx_lvds = {
281 .dot = { .min = 20000, .max = 400000 },
282 .vco = { .min = 1400000, .max = 2800000 },
283 .n = { .min = 1, .max = 6 },
284 .m = { .min = 70, .max = 120 },
285 .m1 = { .min = 8, .max = 18 },
286 .m2 = { .min = 3, .max = 7 },
287 .p = { .min = 7, .max = 98 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 112000,
290 .p2_slow = 14, .p2_fast = 7 },
291 };
292
293
294 static const struct intel_limit intel_limits_g4x_sdvo = {
295 .dot = { .min = 25000, .max = 270000 },
296 .vco = { .min = 1750000, .max = 3500000},
297 .n = { .min = 1, .max = 4 },
298 .m = { .min = 104, .max = 138 },
299 .m1 = { .min = 17, .max = 23 },
300 .m2 = { .min = 5, .max = 11 },
301 .p = { .min = 10, .max = 30 },
302 .p1 = { .min = 1, .max = 3},
303 .p2 = { .dot_limit = 270000,
304 .p2_slow = 10,
305 .p2_fast = 10
306 },
307 };
308
309 static const struct intel_limit intel_limits_g4x_hdmi = {
310 .dot = { .min = 22000, .max = 400000 },
311 .vco = { .min = 1750000, .max = 3500000},
312 .n = { .min = 1, .max = 4 },
313 .m = { .min = 104, .max = 138 },
314 .m1 = { .min = 16, .max = 23 },
315 .m2 = { .min = 5, .max = 11 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8},
318 .p2 = { .dot_limit = 165000,
319 .p2_slow = 10, .p2_fast = 5 },
320 };
321
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
323 .dot = { .min = 20000, .max = 115000 },
324 .vco = { .min = 1750000, .max = 3500000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 104, .max = 138 },
327 .m1 = { .min = 17, .max = 23 },
328 .m2 = { .min = 5, .max = 11 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 0,
332 .p2_slow = 14, .p2_fast = 14
333 },
334 };
335
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
337 .dot = { .min = 80000, .max = 224000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 14, .max = 42 },
344 .p1 = { .min = 2, .max = 6 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 7, .p2_fast = 7
347 },
348 };
349
350 static const struct intel_limit intel_limits_pineview_sdvo = {
351 .dot = { .min = 20000, .max = 400000},
352 .vco = { .min = 1700000, .max = 3500000 },
353 /* Pineview's Ncounter is a ring counter */
354 .n = { .min = 3, .max = 6 },
355 .m = { .min = 2, .max = 256 },
356 /* Pineview only has one combined m divider, which we treat as m2. */
357 .m1 = { .min = 0, .max = 0 },
358 .m2 = { .min = 0, .max = 254 },
359 .p = { .min = 5, .max = 80 },
360 .p1 = { .min = 1, .max = 8 },
361 .p2 = { .dot_limit = 200000,
362 .p2_slow = 10, .p2_fast = 5 },
363 };
364
365 static const struct intel_limit intel_limits_pineview_lvds = {
366 .dot = { .min = 20000, .max = 400000 },
367 .vco = { .min = 1700000, .max = 3500000 },
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 .m1 = { .min = 0, .max = 0 },
371 .m2 = { .min = 0, .max = 254 },
372 .p = { .min = 7, .max = 112 },
373 .p1 = { .min = 1, .max = 8 },
374 .p2 = { .dot_limit = 112000,
375 .p2_slow = 14, .p2_fast = 14 },
376 };
377
378 /* Ironlake / Sandybridge
379 *
380 * We calculate clock using (register_value + 2) for N/M1/M2, so here
381 * the range value for them is (actual_value - 2).
382 */
383 static const struct intel_limit intel_limits_ironlake_dac = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 5 },
387 .m = { .min = 79, .max = 127 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 10, .p2_fast = 5 },
394 };
395
396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 118 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 28, .max = 112 },
404 .p1 = { .min = 2, .max = 8 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 3 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 14, .max = 56 },
417 .p1 = { .min = 2, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 7, .p2_fast = 7 },
420 };
421
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 2 },
427 .m = { .min = 79, .max = 126 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 28, .max = 112 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 14, .p2_fast = 14 },
434 };
435
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
437 .dot = { .min = 25000, .max = 350000 },
438 .vco = { .min = 1760000, .max = 3510000 },
439 .n = { .min = 1, .max = 3 },
440 .m = { .min = 79, .max = 126 },
441 .m1 = { .min = 12, .max = 22 },
442 .m2 = { .min = 5, .max = 9 },
443 .p = { .min = 14, .max = 42 },
444 .p1 = { .min = 2, .max = 6 },
445 .p2 = { .dot_limit = 225000,
446 .p2_slow = 7, .p2_fast = 7 },
447 };
448
449 static const struct intel_limit intel_limits_vlv = {
450 /*
451 * These are the data rate limits (measured in fast clocks)
452 * since those are the strictest limits we have. The fast
453 * clock and actual rate limits are more relaxed, so checking
454 * them would make no difference.
455 */
456 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
457 .vco = { .min = 4000000, .max = 6000000 },
458 .n = { .min = 1, .max = 7 },
459 .m1 = { .min = 2, .max = 3 },
460 .m2 = { .min = 11, .max = 156 },
461 .p1 = { .min = 2, .max = 3 },
462 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 };
464
465 static const struct intel_limit intel_limits_chv = {
466 /*
467 * These are the data rate limits (measured in fast clocks)
468 * since those are the strictest limits we have. The fast
469 * clock and actual rate limits are more relaxed, so checking
470 * them would make no difference.
471 */
472 .dot = { .min = 25000 * 5, .max = 540000 * 5},
473 .vco = { .min = 4800000, .max = 6480000 },
474 .n = { .min = 1, .max = 1 },
475 .m1 = { .min = 2, .max = 2 },
476 .m2 = { .min = 24 << 22, .max = 175 << 22 },
477 .p1 = { .min = 2, .max = 4 },
478 .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 };
480
481 static const struct intel_limit intel_limits_bxt = {
482 /* FIXME: find real dot limits */
483 .dot = { .min = 0, .max = INT_MAX },
484 .vco = { .min = 4800000, .max = 6700000 },
485 .n = { .min = 1, .max = 1 },
486 .m1 = { .min = 2, .max = 2 },
487 /* FIXME: find real m2 limits */
488 .m2 = { .min = 2 << 22, .max = 255 << 22 },
489 .p1 = { .min = 2, .max = 4 },
490 .p2 = { .p2_slow = 1, .p2_fast = 20 },
491 };
492
493 static bool
494 needs_modeset(struct drm_crtc_state *state)
495 {
496 return drm_atomic_crtc_needs_modeset(state);
497 }
498
499 /*
500 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503 * The helpers' return value is the rate of the clock that is fed to the
504 * display engine's pipe which can be the above fast dot clock rate or a
505 * divided-down version of it.
506 */
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510 clock->m = clock->m2 + 2;
511 clock->p = clock->p1 * clock->p2;
512 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 return 0;
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517 return clock->dot;
518 }
519
520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
521 {
522 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
523 }
524
525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = i9xx_dpll_compute_m(clock);
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot;
535 }
536
537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
538 {
539 clock->m = clock->m1 * clock->m2;
540 clock->p = clock->p1 * clock->p2;
541 if (WARN_ON(clock->n == 0 || clock->p == 0))
542 return 0;
543 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
544 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545
546 return clock->dot / 5;
547 }
548
549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return 0;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558
559 return clock->dot / 5;
560 }
561
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 /**
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
566 */
567
568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
569 const struct intel_limit *limit,
570 const struct dpll *clock)
571 {
572 if (clock->n < limit->n.min || limit->n.max < clock->n)
573 INTELPllInvalid("n out of range\n");
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
579 INTELPllInvalid("m1 out of range\n");
580
581 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
582 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
583 if (clock->m1 <= clock->m2)
584 INTELPllInvalid("m1 <= m2\n");
585
586 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
587 !IS_GEN9_LP(dev_priv)) {
588 if (clock->p < limit->p.min || limit->p.max < clock->p)
589 INTELPllInvalid("p out of range\n");
590 if (clock->m < limit->m.min || limit->m.max < clock->m)
591 INTELPllInvalid("m out of range\n");
592 }
593
594 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
595 INTELPllInvalid("vco out of range\n");
596 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597 * connector, etc., rather than just a single range.
598 */
599 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
600 INTELPllInvalid("dot out of range\n");
601
602 return true;
603 }
604
605 static int
606 i9xx_select_p2_div(const struct intel_limit *limit,
607 const struct intel_crtc_state *crtc_state,
608 int target)
609 {
610 struct drm_device *dev = crtc_state->base.crtc->dev;
611
612 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
613 /*
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
617 */
618 if (intel_is_dual_link_lvds(dev))
619 return limit->p2.p2_fast;
620 else
621 return limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 return limit->p2.p2_slow;
625 else
626 return limit->p2.p2_fast;
627 }
628 }
629
630 /*
631 * Returns a set of divisors for the desired target clock with the given
632 * refclk, or FALSE. The returned values represent the clock equation:
633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634 *
635 * Target and reference clocks are specified in kHz.
636 *
637 * If match_clock is provided, then best_clock P divider must match the P
638 * divider from @match_clock used for LVDS downclocking.
639 */
640 static bool
641 i9xx_find_best_dpll(const struct intel_limit *limit,
642 struct intel_crtc_state *crtc_state,
643 int target, int refclk, struct dpll *match_clock,
644 struct dpll *best_clock)
645 {
646 struct drm_device *dev = crtc_state->base.crtc->dev;
647 struct dpll clock;
648 int err = target;
649
650 memset(best_clock, 0, sizeof(*best_clock));
651
652 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
653
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 if (clock.m2 >= clock.m1)
659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
664 int this_err;
665
666 i9xx_calc_dpll_params(refclk, &clock);
667 if (!intel_PLL_is_valid(to_i915(dev),
668 limit,
669 &clock))
670 continue;
671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686 }
687
688 /*
689 * Returns a set of divisors for the desired target clock with the given
690 * refclk, or FALSE. The returned values represent the clock equation:
691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692 *
693 * Target and reference clocks are specified in kHz.
694 *
695 * If match_clock is provided, then best_clock P divider must match the P
696 * divider from @match_clock used for LVDS downclocking.
697 */
698 static bool
699 pnv_find_best_dpll(const struct intel_limit *limit,
700 struct intel_crtc_state *crtc_state,
701 int target, int refclk, struct dpll *match_clock,
702 struct dpll *best_clock)
703 {
704 struct drm_device *dev = crtc_state->base.crtc->dev;
705 struct dpll clock;
706 int err = target;
707
708 memset(best_clock, 0, sizeof(*best_clock));
709
710 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
711
712 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713 clock.m1++) {
714 for (clock.m2 = limit->m2.min;
715 clock.m2 <= limit->m2.max; clock.m2++) {
716 for (clock.n = limit->n.min;
717 clock.n <= limit->n.max; clock.n++) {
718 for (clock.p1 = limit->p1.min;
719 clock.p1 <= limit->p1.max; clock.p1++) {
720 int this_err;
721
722 pnv_calc_dpll_params(refclk, &clock);
723 if (!intel_PLL_is_valid(to_i915(dev),
724 limit,
725 &clock))
726 continue;
727 if (match_clock &&
728 clock.p != match_clock->p)
729 continue;
730
731 this_err = abs(clock.dot - target);
732 if (this_err < err) {
733 *best_clock = clock;
734 err = this_err;
735 }
736 }
737 }
738 }
739 }
740
741 return (err != target);
742 }
743
744 /*
745 * Returns a set of divisors for the desired target clock with the given
746 * refclk, or FALSE. The returned values represent the clock equation:
747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748 *
749 * Target and reference clocks are specified in kHz.
750 *
751 * If match_clock is provided, then best_clock P divider must match the P
752 * divider from @match_clock used for LVDS downclocking.
753 */
754 static bool
755 g4x_find_best_dpll(const struct intel_limit *limit,
756 struct intel_crtc_state *crtc_state,
757 int target, int refclk, struct dpll *match_clock,
758 struct dpll *best_clock)
759 {
760 struct drm_device *dev = crtc_state->base.crtc->dev;
761 struct dpll clock;
762 int max_n;
763 bool found = false;
764 /* approximately equals target * 0.00585 */
765 int err_most = (target >> 8) + (target >> 9);
766
767 memset(best_clock, 0, sizeof(*best_clock));
768
769 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770
771 max_n = limit->n.max;
772 /* based on hardware requirement, prefer smaller n to precision */
773 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
774 /* based on hardware requirement, prefere larger m1,m2 */
775 for (clock.m1 = limit->m1.max;
776 clock.m1 >= limit->m1.min; clock.m1--) {
777 for (clock.m2 = limit->m2.max;
778 clock.m2 >= limit->m2.min; clock.m2--) {
779 for (clock.p1 = limit->p1.max;
780 clock.p1 >= limit->p1.min; clock.p1--) {
781 int this_err;
782
783 i9xx_calc_dpll_params(refclk, &clock);
784 if (!intel_PLL_is_valid(to_i915(dev),
785 limit,
786 &clock))
787 continue;
788
789 this_err = abs(clock.dot - target);
790 if (this_err < err_most) {
791 *best_clock = clock;
792 err_most = this_err;
793 max_n = clock.n;
794 found = true;
795 }
796 }
797 }
798 }
799 }
800 return found;
801 }
802
803 /*
804 * Check if the calculated PLL configuration is more optimal compared to the
805 * best configuration and error found so far. Return the calculated error.
806 */
807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
808 const struct dpll *calculated_clock,
809 const struct dpll *best_clock,
810 unsigned int best_error_ppm,
811 unsigned int *error_ppm)
812 {
813 /*
814 * For CHV ignore the error and consider only the P value.
815 * Prefer a bigger P value based on HW requirements.
816 */
817 if (IS_CHERRYVIEW(to_i915(dev))) {
818 *error_ppm = 0;
819
820 return calculated_clock->p > best_clock->p;
821 }
822
823 if (WARN_ON_ONCE(!target_freq))
824 return false;
825
826 *error_ppm = div_u64(1000000ULL *
827 abs(target_freq - calculated_clock->dot),
828 target_freq);
829 /*
830 * Prefer a better P value over a better (smaller) error if the error
831 * is small. Ensure this preference for future configurations too by
832 * setting the error to 0.
833 */
834 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
835 *error_ppm = 0;
836
837 return true;
838 }
839
840 return *error_ppm + 10 < best_error_ppm;
841 }
842
843 /*
844 * Returns a set of divisors for the desired target clock with the given
845 * refclk, or FALSE. The returned values represent the clock equation:
846 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
847 */
848 static bool
849 vlv_find_best_dpll(const struct intel_limit *limit,
850 struct intel_crtc_state *crtc_state,
851 int target, int refclk, struct dpll *match_clock,
852 struct dpll *best_clock)
853 {
854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
855 struct drm_device *dev = crtc->base.dev;
856 struct dpll clock;
857 unsigned int bestppm = 1000000;
858 /* min update 19.2 MHz */
859 int max_n = min(limit->n.max, refclk / 19200);
860 bool found = false;
861
862 target *= 5; /* fast clock */
863
864 memset(best_clock, 0, sizeof(*best_clock));
865
866 /* based on hardware requirement, prefer smaller n to precision */
867 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
868 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
869 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
870 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
871 clock.p = clock.p1 * clock.p2;
872 /* based on hardware requirement, prefer bigger m1,m2 values */
873 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
874 unsigned int ppm;
875
876 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
877 refclk * clock.m1);
878
879 vlv_calc_dpll_params(refclk, &clock);
880
881 if (!intel_PLL_is_valid(to_i915(dev),
882 limit,
883 &clock))
884 continue;
885
886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
891
892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
895 }
896 }
897 }
898 }
899
900 return found;
901 }
902
903 /*
904 * Returns a set of divisors for the desired target clock with the given
905 * refclk, or FALSE. The returned values represent the clock equation:
906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
907 */
908 static bool
909 chv_find_best_dpll(const struct intel_limit *limit,
910 struct intel_crtc_state *crtc_state,
911 int target, int refclk, struct dpll *match_clock,
912 struct dpll *best_clock)
913 {
914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
915 struct drm_device *dev = crtc->base.dev;
916 unsigned int best_error_ppm;
917 struct dpll clock;
918 uint64_t m2;
919 int found = false;
920
921 memset(best_clock, 0, sizeof(*best_clock));
922 best_error_ppm = 1000000;
923
924 /*
925 * Based on hardware doc, the n always set to 1, and m1 always
926 * set to 2. If requires to support 200Mhz refclk, we need to
927 * revisit this because n may not 1 anymore.
928 */
929 clock.n = 1, clock.m1 = 2;
930 target *= 5; /* fast clock */
931
932 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
933 for (clock.p2 = limit->p2.p2_fast;
934 clock.p2 >= limit->p2.p2_slow;
935 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
936 unsigned int error_ppm;
937
938 clock.p = clock.p1 * clock.p2;
939
940 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
941 clock.n) << 22, refclk * clock.m1);
942
943 if (m2 > INT_MAX/clock.m1)
944 continue;
945
946 clock.m2 = m2;
947
948 chv_calc_dpll_params(refclk, &clock);
949
950 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
951 continue;
952
953 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
954 best_error_ppm, &error_ppm))
955 continue;
956
957 *best_clock = clock;
958 best_error_ppm = error_ppm;
959 found = true;
960 }
961 }
962
963 return found;
964 }
965
966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
967 struct dpll *best_clock)
968 {
969 int refclk = 100000;
970 const struct intel_limit *limit = &intel_limits_bxt;
971
972 return chv_find_best_dpll(limit, crtc_state,
973 target_clock, refclk, NULL, best_clock);
974 }
975
976 bool intel_crtc_active(struct intel_crtc *crtc)
977 {
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
980 *
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
983 *
984 * We can ditch the crtc->primary->fb check as soon as we can
985 * properly reconstruct framebuffers.
986 *
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
989 * for atomic.
990 */
991 return crtc->active && crtc->base.primary->state->fb &&
992 crtc->config->base.adjusted_mode.crtc_clock;
993 }
994
995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
996 enum pipe pipe)
997 {
998 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
999
1000 return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1004 enum pipe pipe)
1005 {
1006 i915_reg_t reg = PIPEDSL(pipe);
1007 u32 line1, line2;
1008 u32 line_mask;
1009
1010 if (IS_GEN2(dev_priv))
1011 line_mask = DSL_LINEMASK_GEN2;
1012 else
1013 line_mask = DSL_LINEMASK_GEN3;
1014
1015 line1 = I915_READ(reg) & line_mask;
1016 msleep(5);
1017 line2 = I915_READ(reg) & line_mask;
1018
1019 return line1 != line2;
1020 }
1021
1022 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1023 {
1024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1025 enum pipe pipe = crtc->pipe;
1026
1027 /* Wait for the display line to settle/start moving */
1028 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1029 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1030 pipe_name(pipe), onoff(state));
1031 }
1032
1033 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1034 {
1035 wait_for_pipe_scanline_moving(crtc, false);
1036 }
1037
1038 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1039 {
1040 wait_for_pipe_scanline_moving(crtc, true);
1041 }
1042
1043 /*
1044 * intel_wait_for_pipe_off - wait for pipe to turn off
1045 * @crtc: crtc whose pipe to wait for
1046 *
1047 * After disabling a pipe, we can't wait for vblank in the usual way,
1048 * spinning on the vblank interrupt status bit, since we won't actually
1049 * see an interrupt when the pipe is disabled.
1050 *
1051 * On Gen4 and above:
1052 * wait for the pipe register state bit to turn off
1053 *
1054 * Otherwise:
1055 * wait for the display line value to settle (it usually
1056 * ends up stopping at the start of the next frame).
1057 *
1058 */
1059 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1060 {
1061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1062 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1063
1064 if (INTEL_GEN(dev_priv) >= 4) {
1065 i915_reg_t reg = PIPECONF(cpu_transcoder);
1066
1067 /* Wait for the Pipe State to go off */
1068 if (intel_wait_for_register(dev_priv,
1069 reg, I965_PIPECONF_ACTIVE, 0,
1070 100))
1071 WARN(1, "pipe_off wait timed out\n");
1072 } else {
1073 intel_wait_for_pipe_scanline_stopped(crtc);
1074 }
1075 }
1076
1077 /* Only for pre-ILK configs */
1078 void assert_pll(struct drm_i915_private *dev_priv,
1079 enum pipe pipe, bool state)
1080 {
1081 u32 val;
1082 bool cur_state;
1083
1084 val = I915_READ(DPLL(pipe));
1085 cur_state = !!(val & DPLL_VCO_ENABLE);
1086 I915_STATE_WARN(cur_state != state,
1087 "PLL state assertion failure (expected %s, current %s)\n",
1088 onoff(state), onoff(cur_state));
1089 }
1090
1091 /* XXX: the dsi pll is shared between MIPI DSI ports */
1092 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1093 {
1094 u32 val;
1095 bool cur_state;
1096
1097 mutex_lock(&dev_priv->sb_lock);
1098 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1099 mutex_unlock(&dev_priv->sb_lock);
1100
1101 cur_state = val & DSI_PLL_VCO_EN;
1102 I915_STATE_WARN(cur_state != state,
1103 "DSI PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 bool cur_state;
1111 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1112 pipe);
1113
1114 if (HAS_DDI(dev_priv)) {
1115 /* DDI does not have a specific FDI_TX register */
1116 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1117 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1118 } else {
1119 u32 val = I915_READ(FDI_TX_CTL(pipe));
1120 cur_state = !!(val & FDI_TX_ENABLE);
1121 }
1122 I915_STATE_WARN(cur_state != state,
1123 "FDI TX state assertion failure (expected %s, current %s)\n",
1124 onoff(state), onoff(cur_state));
1125 }
1126 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1127 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1128
1129 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1130 enum pipe pipe, bool state)
1131 {
1132 u32 val;
1133 bool cur_state;
1134
1135 val = I915_READ(FDI_RX_CTL(pipe));
1136 cur_state = !!(val & FDI_RX_ENABLE);
1137 I915_STATE_WARN(cur_state != state,
1138 "FDI RX state assertion failure (expected %s, current %s)\n",
1139 onoff(state), onoff(cur_state));
1140 }
1141 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1142 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1143
1144 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1145 enum pipe pipe)
1146 {
1147 u32 val;
1148
1149 /* ILK FDI PLL is always enabled */
1150 if (IS_GEN5(dev_priv))
1151 return;
1152
1153 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1154 if (HAS_DDI(dev_priv))
1155 return;
1156
1157 val = I915_READ(FDI_TX_CTL(pipe));
1158 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1159 }
1160
1161 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1162 enum pipe pipe, bool state)
1163 {
1164 u32 val;
1165 bool cur_state;
1166
1167 val = I915_READ(FDI_RX_CTL(pipe));
1168 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1169 I915_STATE_WARN(cur_state != state,
1170 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1171 onoff(state), onoff(cur_state));
1172 }
1173
1174 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1175 {
1176 i915_reg_t pp_reg;
1177 u32 val;
1178 enum pipe panel_pipe = PIPE_A;
1179 bool locked = true;
1180
1181 if (WARN_ON(HAS_DDI(dev_priv)))
1182 return;
1183
1184 if (HAS_PCH_SPLIT(dev_priv)) {
1185 u32 port_sel;
1186
1187 pp_reg = PP_CONTROL(0);
1188 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1189
1190 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1191 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1192 panel_pipe = PIPE_B;
1193 /* XXX: else fix for eDP */
1194 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1195 /* presumably write lock depends on pipe, not port select */
1196 pp_reg = PP_CONTROL(pipe);
1197 panel_pipe = pipe;
1198 } else {
1199 pp_reg = PP_CONTROL(0);
1200 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1201 panel_pipe = PIPE_B;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 I915_STATE_WARN(panel_pipe == pipe && locked,
1210 "panel assertion failure, pipe %c regs locked\n",
1211 pipe_name(pipe));
1212 }
1213
1214 void assert_pipe(struct drm_i915_private *dev_priv,
1215 enum pipe pipe, bool state)
1216 {
1217 bool cur_state;
1218 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1219 pipe);
1220 enum intel_display_power_domain power_domain;
1221
1222 /* we keep both pipes enabled on 830 */
1223 if (IS_I830(dev_priv))
1224 state = true;
1225
1226 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1227 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1228 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1229 cur_state = !!(val & PIPECONF_ENABLE);
1230
1231 intel_display_power_put(dev_priv, power_domain);
1232 } else {
1233 cur_state = false;
1234 }
1235
1236 I915_STATE_WARN(cur_state != state,
1237 "pipe %c assertion failure (expected %s, current %s)\n",
1238 pipe_name(pipe), onoff(state), onoff(cur_state));
1239 }
1240
1241 static void assert_plane(struct intel_plane *plane, bool state)
1242 {
1243 bool cur_state = plane->get_hw_state(plane);
1244
1245 I915_STATE_WARN(cur_state != state,
1246 "%s assertion failure (expected %s, current %s)\n",
1247 plane->base.name, onoff(state), onoff(cur_state));
1248 }
1249
1250 #define assert_plane_enabled(p) assert_plane(p, true)
1251 #define assert_plane_disabled(p) assert_plane(p, false)
1252
1253 static void assert_planes_disabled(struct intel_crtc *crtc)
1254 {
1255 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1256 struct intel_plane *plane;
1257
1258 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1259 assert_plane_disabled(plane);
1260 }
1261
1262 static void assert_vblank_disabled(struct drm_crtc *crtc)
1263 {
1264 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1265 drm_crtc_vblank_put(crtc);
1266 }
1267
1268 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe)
1270 {
1271 u32 val;
1272 bool enabled;
1273
1274 val = I915_READ(PCH_TRANSCONF(pipe));
1275 enabled = !!(val & TRANS_ENABLE);
1276 I915_STATE_WARN(enabled,
1277 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1278 pipe_name(pipe));
1279 }
1280
1281 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1282 enum pipe pipe, u32 port_sel, u32 val)
1283 {
1284 if ((val & DP_PORT_EN) == 0)
1285 return false;
1286
1287 if (HAS_PCH_CPT(dev_priv)) {
1288 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1289 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1290 return false;
1291 } else if (IS_CHERRYVIEW(dev_priv)) {
1292 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1293 return false;
1294 } else {
1295 if ((val & DP_PIPE_MASK) != (pipe << 30))
1296 return false;
1297 }
1298 return true;
1299 }
1300
1301 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe, u32 val)
1303 {
1304 if ((val & SDVO_ENABLE) == 0)
1305 return false;
1306
1307 if (HAS_PCH_CPT(dev_priv)) {
1308 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1309 return false;
1310 } else if (IS_CHERRYVIEW(dev_priv)) {
1311 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1312 return false;
1313 } else {
1314 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1315 return false;
1316 }
1317 return true;
1318 }
1319
1320 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 val)
1322 {
1323 if ((val & LVDS_PORT_EN) == 0)
1324 return false;
1325
1326 if (HAS_PCH_CPT(dev_priv)) {
1327 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1328 return false;
1329 } else {
1330 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1331 return false;
1332 }
1333 return true;
1334 }
1335
1336 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, u32 val)
1338 {
1339 if ((val & ADPA_DAC_ENABLE) == 0)
1340 return false;
1341 if (HAS_PCH_CPT(dev_priv)) {
1342 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1343 return false;
1344 } else {
1345 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1346 return false;
1347 }
1348 return true;
1349 }
1350
1351 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe, i915_reg_t reg,
1353 u32 port_sel)
1354 {
1355 u32 val = I915_READ(reg);
1356 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1357 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1358 i915_mmio_reg_offset(reg), pipe_name(pipe));
1359
1360 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1361 && (val & DP_PIPEB_SELECT),
1362 "IBX PCH dp port still using transcoder B\n");
1363 }
1364
1365 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, i915_reg_t reg)
1367 {
1368 u32 val = I915_READ(reg);
1369 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1370 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1371 i915_mmio_reg_offset(reg), pipe_name(pipe));
1372
1373 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1374 && (val & SDVO_PIPE_B_SELECT),
1375 "IBX PCH hdmi port still using transcoder B\n");
1376 }
1377
1378 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1379 enum pipe pipe)
1380 {
1381 u32 val;
1382
1383 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1384 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1385 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1386
1387 val = I915_READ(PCH_ADPA);
1388 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1389 "PCH VGA enabled on transcoder %c, should be disabled\n",
1390 pipe_name(pipe));
1391
1392 val = I915_READ(PCH_LVDS);
1393 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1394 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1395 pipe_name(pipe));
1396
1397 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1398 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1399 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1400 }
1401
1402 static void _vlv_enable_pll(struct intel_crtc *crtc,
1403 const struct intel_crtc_state *pipe_config)
1404 {
1405 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1406 enum pipe pipe = crtc->pipe;
1407
1408 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1409 POSTING_READ(DPLL(pipe));
1410 udelay(150);
1411
1412 if (intel_wait_for_register(dev_priv,
1413 DPLL(pipe),
1414 DPLL_LOCK_VLV,
1415 DPLL_LOCK_VLV,
1416 1))
1417 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1418 }
1419
1420 static void vlv_enable_pll(struct intel_crtc *crtc,
1421 const struct intel_crtc_state *pipe_config)
1422 {
1423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1424 enum pipe pipe = crtc->pipe;
1425
1426 assert_pipe_disabled(dev_priv, pipe);
1427
1428 /* PLL is protected by panel, make sure we can write it */
1429 assert_panel_unlocked(dev_priv, pipe);
1430
1431 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1432 _vlv_enable_pll(crtc, pipe_config);
1433
1434 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1435 POSTING_READ(DPLL_MD(pipe));
1436 }
1437
1438
1439 static void _chv_enable_pll(struct intel_crtc *crtc,
1440 const struct intel_crtc_state *pipe_config)
1441 {
1442 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1443 enum pipe pipe = crtc->pipe;
1444 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1445 u32 tmp;
1446
1447 mutex_lock(&dev_priv->sb_lock);
1448
1449 /* Enable back the 10bit clock to display controller */
1450 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1451 tmp |= DPIO_DCLKP_EN;
1452 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1453
1454 mutex_unlock(&dev_priv->sb_lock);
1455
1456 /*
1457 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1458 */
1459 udelay(1);
1460
1461 /* Enable PLL */
1462 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1463
1464 /* Check PLL is locked */
1465 if (intel_wait_for_register(dev_priv,
1466 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1467 1))
1468 DRM_ERROR("PLL %d failed to lock\n", pipe);
1469 }
1470
1471 static void chv_enable_pll(struct intel_crtc *crtc,
1472 const struct intel_crtc_state *pipe_config)
1473 {
1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1475 enum pipe pipe = crtc->pipe;
1476
1477 assert_pipe_disabled(dev_priv, pipe);
1478
1479 /* PLL is protected by panel, make sure we can write it */
1480 assert_panel_unlocked(dev_priv, pipe);
1481
1482 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1483 _chv_enable_pll(crtc, pipe_config);
1484
1485 if (pipe != PIPE_A) {
1486 /*
1487 * WaPixelRepeatModeFixForC0:chv
1488 *
1489 * DPLLCMD is AWOL. Use chicken bits to propagate
1490 * the value from DPLLBMD to either pipe B or C.
1491 */
1492 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1493 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1494 I915_WRITE(CBR4_VLV, 0);
1495 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1496
1497 /*
1498 * DPLLB VGA mode also seems to cause problems.
1499 * We should always have it disabled.
1500 */
1501 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1502 } else {
1503 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1504 POSTING_READ(DPLL_MD(pipe));
1505 }
1506 }
1507
1508 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1509 {
1510 struct intel_crtc *crtc;
1511 int count = 0;
1512
1513 for_each_intel_crtc(&dev_priv->drm, crtc) {
1514 count += crtc->base.state->active &&
1515 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1516 }
1517
1518 return count;
1519 }
1520
1521 static void i9xx_enable_pll(struct intel_crtc *crtc,
1522 const struct intel_crtc_state *crtc_state)
1523 {
1524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525 i915_reg_t reg = DPLL(crtc->pipe);
1526 u32 dpll = crtc_state->dpll_hw_state.dpll;
1527 int i;
1528
1529 assert_pipe_disabled(dev_priv, crtc->pipe);
1530
1531 /* PLL is protected by panel, make sure we can write it */
1532 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1533 assert_panel_unlocked(dev_priv, crtc->pipe);
1534
1535 /* Enable DVO 2x clock on both PLLs if necessary */
1536 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1537 /*
1538 * It appears to be important that we don't enable this
1539 * for the current pipe before otherwise configuring the
1540 * PLL. No idea how this should be handled if multiple
1541 * DVO outputs are enabled simultaneosly.
1542 */
1543 dpll |= DPLL_DVO_2X_MODE;
1544 I915_WRITE(DPLL(!crtc->pipe),
1545 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1546 }
1547
1548 /*
1549 * Apparently we need to have VGA mode enabled prior to changing
1550 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1551 * dividers, even though the register value does change.
1552 */
1553 I915_WRITE(reg, 0);
1554
1555 I915_WRITE(reg, dpll);
1556
1557 /* Wait for the clocks to stabilize. */
1558 POSTING_READ(reg);
1559 udelay(150);
1560
1561 if (INTEL_GEN(dev_priv) >= 4) {
1562 I915_WRITE(DPLL_MD(crtc->pipe),
1563 crtc_state->dpll_hw_state.dpll_md);
1564 } else {
1565 /* The pixel multiplier can only be updated once the
1566 * DPLL is enabled and the clocks are stable.
1567 *
1568 * So write it again.
1569 */
1570 I915_WRITE(reg, dpll);
1571 }
1572
1573 /* We do this three times for luck */
1574 for (i = 0; i < 3; i++) {
1575 I915_WRITE(reg, dpll);
1576 POSTING_READ(reg);
1577 udelay(150); /* wait for warmup */
1578 }
1579 }
1580
1581 static void i9xx_disable_pll(struct intel_crtc *crtc)
1582 {
1583 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1584 enum pipe pipe = crtc->pipe;
1585
1586 /* Disable DVO 2x clock on both PLLs if necessary */
1587 if (IS_I830(dev_priv) &&
1588 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1589 !intel_num_dvo_pipes(dev_priv)) {
1590 I915_WRITE(DPLL(PIPE_B),
1591 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1592 I915_WRITE(DPLL(PIPE_A),
1593 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1594 }
1595
1596 /* Don't disable pipe or pipe PLLs if needed */
1597 if (IS_I830(dev_priv))
1598 return;
1599
1600 /* Make sure the pipe isn't still relying on us */
1601 assert_pipe_disabled(dev_priv, pipe);
1602
1603 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1604 POSTING_READ(DPLL(pipe));
1605 }
1606
1607 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1608 {
1609 u32 val;
1610
1611 /* Make sure the pipe isn't still relying on us */
1612 assert_pipe_disabled(dev_priv, pipe);
1613
1614 val = DPLL_INTEGRATED_REF_CLK_VLV |
1615 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1616 if (pipe != PIPE_A)
1617 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1618
1619 I915_WRITE(DPLL(pipe), val);
1620 POSTING_READ(DPLL(pipe));
1621 }
1622
1623 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1624 {
1625 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1626 u32 val;
1627
1628 /* Make sure the pipe isn't still relying on us */
1629 assert_pipe_disabled(dev_priv, pipe);
1630
1631 val = DPLL_SSC_REF_CLK_CHV |
1632 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1633 if (pipe != PIPE_A)
1634 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1635
1636 I915_WRITE(DPLL(pipe), val);
1637 POSTING_READ(DPLL(pipe));
1638
1639 mutex_lock(&dev_priv->sb_lock);
1640
1641 /* Disable 10bit clock to display controller */
1642 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1643 val &= ~DPIO_DCLKP_EN;
1644 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1645
1646 mutex_unlock(&dev_priv->sb_lock);
1647 }
1648
1649 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1650 struct intel_digital_port *dport,
1651 unsigned int expected_mask)
1652 {
1653 u32 port_mask;
1654 i915_reg_t dpll_reg;
1655
1656 switch (dport->port) {
1657 case PORT_B:
1658 port_mask = DPLL_PORTB_READY_MASK;
1659 dpll_reg = DPLL(0);
1660 break;
1661 case PORT_C:
1662 port_mask = DPLL_PORTC_READY_MASK;
1663 dpll_reg = DPLL(0);
1664 expected_mask <<= 4;
1665 break;
1666 case PORT_D:
1667 port_mask = DPLL_PORTD_READY_MASK;
1668 dpll_reg = DPIO_PHY_STATUS;
1669 break;
1670 default:
1671 BUG();
1672 }
1673
1674 if (intel_wait_for_register(dev_priv,
1675 dpll_reg, port_mask, expected_mask,
1676 1000))
1677 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1678 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1679 }
1680
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
1683 {
1684 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1685 pipe);
1686 i915_reg_t reg;
1687 uint32_t val, pipeconf_val;
1688
1689 /* Make sure PCH DPLL is enabled */
1690 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1691
1692 /* FDI must be feeding us bits for PCH ports */
1693 assert_fdi_tx_enabled(dev_priv, pipe);
1694 assert_fdi_rx_enabled(dev_priv, pipe);
1695
1696 if (HAS_PCH_CPT(dev_priv)) {
1697 /* Workaround: Set the timing override bit before enabling the
1698 * pch transcoder. */
1699 reg = TRANS_CHICKEN2(pipe);
1700 val = I915_READ(reg);
1701 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1702 I915_WRITE(reg, val);
1703 }
1704
1705 reg = PCH_TRANSCONF(pipe);
1706 val = I915_READ(reg);
1707 pipeconf_val = I915_READ(PIPECONF(pipe));
1708
1709 if (HAS_PCH_IBX(dev_priv)) {
1710 /*
1711 * Make the BPC in transcoder be consistent with
1712 * that in pipeconf reg. For HDMI we must use 8bpc
1713 * here for both 8bpc and 12bpc.
1714 */
1715 val &= ~PIPECONF_BPC_MASK;
1716 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1717 val |= PIPECONF_8BPC;
1718 else
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
1720 }
1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724 if (HAS_PCH_IBX(dev_priv) &&
1725 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (intel_wait_for_register(dev_priv,
1734 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1735 100))
1736 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1737 }
1738
1739 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1740 enum transcoder cpu_transcoder)
1741 {
1742 u32 val, pipeconf_val;
1743
1744 /* FDI must be feeding us bits for PCH ports */
1745 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1746 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1747
1748 /* Workaround: set timing override bit. */
1749 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1750 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1751 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1752
1753 val = TRANS_ENABLE;
1754 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1755
1756 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1757 PIPECONF_INTERLACED_ILK)
1758 val |= TRANS_INTERLACED;
1759 else
1760 val |= TRANS_PROGRESSIVE;
1761
1762 I915_WRITE(LPT_TRANSCONF, val);
1763 if (intel_wait_for_register(dev_priv,
1764 LPT_TRANSCONF,
1765 TRANS_STATE_ENABLE,
1766 TRANS_STATE_ENABLE,
1767 100))
1768 DRM_ERROR("Failed to enable PCH transcoder\n");
1769 }
1770
1771 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1772 enum pipe pipe)
1773 {
1774 i915_reg_t reg;
1775 uint32_t val;
1776
1777 /* FDI relies on the transcoder */
1778 assert_fdi_tx_disabled(dev_priv, pipe);
1779 assert_fdi_rx_disabled(dev_priv, pipe);
1780
1781 /* Ports must be off as well */
1782 assert_pch_ports_disabled(dev_priv, pipe);
1783
1784 reg = PCH_TRANSCONF(pipe);
1785 val = I915_READ(reg);
1786 val &= ~TRANS_ENABLE;
1787 I915_WRITE(reg, val);
1788 /* wait for PCH transcoder off, transcoder state */
1789 if (intel_wait_for_register(dev_priv,
1790 reg, TRANS_STATE_ENABLE, 0,
1791 50))
1792 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1793
1794 if (HAS_PCH_CPT(dev_priv)) {
1795 /* Workaround: Clear the timing override chicken bit again. */
1796 reg = TRANS_CHICKEN2(pipe);
1797 val = I915_READ(reg);
1798 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1799 I915_WRITE(reg, val);
1800 }
1801 }
1802
1803 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1804 {
1805 u32 val;
1806
1807 val = I915_READ(LPT_TRANSCONF);
1808 val &= ~TRANS_ENABLE;
1809 I915_WRITE(LPT_TRANSCONF, val);
1810 /* wait for PCH transcoder off, transcoder state */
1811 if (intel_wait_for_register(dev_priv,
1812 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1813 50))
1814 DRM_ERROR("Failed to disable PCH transcoder\n");
1815
1816 /* Workaround: clear timing override bit. */
1817 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1818 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1819 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1820 }
1821
1822 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1823 {
1824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1825
1826 WARN_ON(!crtc->config->has_pch_encoder);
1827
1828 if (HAS_PCH_LPT(dev_priv))
1829 return PIPE_A;
1830 else
1831 return crtc->pipe;
1832 }
1833
1834 /**
1835 * intel_enable_pipe - enable a pipe, asserting requirements
1836 * @crtc: crtc responsible for the pipe
1837 *
1838 * Enable @crtc's pipe, making sure that various hardware specific requirements
1839 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1840 */
1841 static void intel_enable_pipe(struct intel_crtc *crtc)
1842 {
1843 struct drm_device *dev = crtc->base.dev;
1844 struct drm_i915_private *dev_priv = to_i915(dev);
1845 enum pipe pipe = crtc->pipe;
1846 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1847 i915_reg_t reg;
1848 u32 val;
1849
1850 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1851
1852 assert_planes_disabled(crtc);
1853
1854 /*
1855 * A pipe without a PLL won't actually be able to drive bits from
1856 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1857 * need the check.
1858 */
1859 if (HAS_GMCH_DISPLAY(dev_priv)) {
1860 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1861 assert_dsi_pll_enabled(dev_priv);
1862 else
1863 assert_pll_enabled(dev_priv, pipe);
1864 } else {
1865 if (crtc->config->has_pch_encoder) {
1866 /* if driving the PCH, we need FDI enabled */
1867 assert_fdi_rx_pll_enabled(dev_priv,
1868 intel_crtc_pch_transcoder(crtc));
1869 assert_fdi_tx_pll_enabled(dev_priv,
1870 (enum pipe) cpu_transcoder);
1871 }
1872 /* FIXME: assert CPU port conditions for SNB+ */
1873 }
1874
1875 reg = PIPECONF(cpu_transcoder);
1876 val = I915_READ(reg);
1877 if (val & PIPECONF_ENABLE) {
1878 /* we keep both pipes enabled on 830 */
1879 WARN_ON(!IS_I830(dev_priv));
1880 return;
1881 }
1882
1883 I915_WRITE(reg, val | PIPECONF_ENABLE);
1884 POSTING_READ(reg);
1885
1886 /*
1887 * Until the pipe starts PIPEDSL reads will return a stale value,
1888 * which causes an apparent vblank timestamp jump when PIPEDSL
1889 * resets to its proper value. That also messes up the frame count
1890 * when it's derived from the timestamps. So let's wait for the
1891 * pipe to start properly before we call drm_crtc_vblank_on()
1892 */
1893 if (dev->max_vblank_count == 0)
1894 intel_wait_for_pipe_scanline_moving(crtc);
1895 }
1896
1897 /**
1898 * intel_disable_pipe - disable a pipe, asserting requirements
1899 * @crtc: crtc whose pipes is to be disabled
1900 *
1901 * Disable the pipe of @crtc, making sure that various hardware
1902 * specific requirements are met, if applicable, e.g. plane
1903 * disabled, panel fitter off, etc.
1904 *
1905 * Will wait until the pipe has shut down before returning.
1906 */
1907 static void intel_disable_pipe(struct intel_crtc *crtc)
1908 {
1909 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1910 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1911 enum pipe pipe = crtc->pipe;
1912 i915_reg_t reg;
1913 u32 val;
1914
1915 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1916
1917 /*
1918 * Make sure planes won't keep trying to pump pixels to us,
1919 * or we might hang the display.
1920 */
1921 assert_planes_disabled(crtc);
1922
1923 reg = PIPECONF(cpu_transcoder);
1924 val = I915_READ(reg);
1925 if ((val & PIPECONF_ENABLE) == 0)
1926 return;
1927
1928 /*
1929 * Double wide has implications for planes
1930 * so best keep it disabled when not needed.
1931 */
1932 if (crtc->config->double_wide)
1933 val &= ~PIPECONF_DOUBLE_WIDE;
1934
1935 /* Don't disable pipe or pipe PLLs if needed */
1936 if (!IS_I830(dev_priv))
1937 val &= ~PIPECONF_ENABLE;
1938
1939 I915_WRITE(reg, val);
1940 if ((val & PIPECONF_ENABLE) == 0)
1941 intel_wait_for_pipe_off(crtc);
1942 }
1943
1944 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1945 {
1946 return IS_GEN2(dev_priv) ? 2048 : 4096;
1947 }
1948
1949 static unsigned int
1950 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1951 {
1952 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1953 unsigned int cpp = fb->format->cpp[plane];
1954
1955 switch (fb->modifier) {
1956 case DRM_FORMAT_MOD_LINEAR:
1957 return cpp;
1958 case I915_FORMAT_MOD_X_TILED:
1959 if (IS_GEN2(dev_priv))
1960 return 128;
1961 else
1962 return 512;
1963 case I915_FORMAT_MOD_Y_TILED_CCS:
1964 if (plane == 1)
1965 return 128;
1966 /* fall through */
1967 case I915_FORMAT_MOD_Y_TILED:
1968 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1969 return 128;
1970 else
1971 return 512;
1972 case I915_FORMAT_MOD_Yf_TILED_CCS:
1973 if (plane == 1)
1974 return 128;
1975 /* fall through */
1976 case I915_FORMAT_MOD_Yf_TILED:
1977 switch (cpp) {
1978 case 1:
1979 return 64;
1980 case 2:
1981 case 4:
1982 return 128;
1983 case 8:
1984 case 16:
1985 return 256;
1986 default:
1987 MISSING_CASE(cpp);
1988 return cpp;
1989 }
1990 break;
1991 default:
1992 MISSING_CASE(fb->modifier);
1993 return cpp;
1994 }
1995 }
1996
1997 static unsigned int
1998 intel_tile_height(const struct drm_framebuffer *fb, int plane)
1999 {
2000 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2001 return 1;
2002 else
2003 return intel_tile_size(to_i915(fb->dev)) /
2004 intel_tile_width_bytes(fb, plane);
2005 }
2006
2007 /* Return the tile dimensions in pixel units */
2008 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2009 unsigned int *tile_width,
2010 unsigned int *tile_height)
2011 {
2012 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2013 unsigned int cpp = fb->format->cpp[plane];
2014
2015 *tile_width = tile_width_bytes / cpp;
2016 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2017 }
2018
2019 unsigned int
2020 intel_fb_align_height(const struct drm_framebuffer *fb,
2021 int plane, unsigned int height)
2022 {
2023 unsigned int tile_height = intel_tile_height(fb, plane);
2024
2025 return ALIGN(height, tile_height);
2026 }
2027
2028 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2029 {
2030 unsigned int size = 0;
2031 int i;
2032
2033 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2034 size += rot_info->plane[i].width * rot_info->plane[i].height;
2035
2036 return size;
2037 }
2038
2039 static void
2040 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2041 const struct drm_framebuffer *fb,
2042 unsigned int rotation)
2043 {
2044 view->type = I915_GGTT_VIEW_NORMAL;
2045 if (drm_rotation_90_or_270(rotation)) {
2046 view->type = I915_GGTT_VIEW_ROTATED;
2047 view->rotated = to_intel_framebuffer(fb)->rot_info;
2048 }
2049 }
2050
2051 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2052 {
2053 if (IS_I830(dev_priv))
2054 return 16 * 1024;
2055 else if (IS_I85X(dev_priv))
2056 return 256;
2057 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2058 return 32;
2059 else
2060 return 4 * 1024;
2061 }
2062
2063 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2064 {
2065 if (INTEL_INFO(dev_priv)->gen >= 9)
2066 return 256 * 1024;
2067 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2068 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2069 return 128 * 1024;
2070 else if (INTEL_INFO(dev_priv)->gen >= 4)
2071 return 4 * 1024;
2072 else
2073 return 0;
2074 }
2075
2076 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2077 int plane)
2078 {
2079 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2080
2081 /* AUX_DIST needs only 4K alignment */
2082 if (plane == 1)
2083 return 4096;
2084
2085 switch (fb->modifier) {
2086 case DRM_FORMAT_MOD_LINEAR:
2087 return intel_linear_alignment(dev_priv);
2088 case I915_FORMAT_MOD_X_TILED:
2089 if (INTEL_GEN(dev_priv) >= 9)
2090 return 256 * 1024;
2091 return 0;
2092 case I915_FORMAT_MOD_Y_TILED_CCS:
2093 case I915_FORMAT_MOD_Yf_TILED_CCS:
2094 case I915_FORMAT_MOD_Y_TILED:
2095 case I915_FORMAT_MOD_Yf_TILED:
2096 return 1 * 1024 * 1024;
2097 default:
2098 MISSING_CASE(fb->modifier);
2099 return 0;
2100 }
2101 }
2102
2103 struct i915_vma *
2104 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2105 {
2106 struct drm_device *dev = fb->dev;
2107 struct drm_i915_private *dev_priv = to_i915(dev);
2108 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2109 struct i915_ggtt_view view;
2110 struct i915_vma *vma;
2111 u32 alignment;
2112
2113 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2114
2115 alignment = intel_surf_alignment(fb, 0);
2116
2117 intel_fill_fb_ggtt_view(&view, fb, rotation);
2118
2119 /* Note that the w/a also requires 64 PTE of padding following the
2120 * bo. We currently fill all unused PTE with the shadow page and so
2121 * we should always have valid PTE following the scanout preventing
2122 * the VT-d warning.
2123 */
2124 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2125 alignment = 256 * 1024;
2126
2127 /*
2128 * Global gtt pte registers are special registers which actually forward
2129 * writes to a chunk of system memory. Which means that there is no risk
2130 * that the register values disappear as soon as we call
2131 * intel_runtime_pm_put(), so it is correct to wrap only the
2132 * pin/unpin/fence and not more.
2133 */
2134 intel_runtime_pm_get(dev_priv);
2135
2136 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2137
2138 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2139 if (IS_ERR(vma))
2140 goto err;
2141
2142 if (i915_vma_is_map_and_fenceable(vma)) {
2143 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2144 * fence, whereas 965+ only requires a fence if using
2145 * framebuffer compression. For simplicity, we always, when
2146 * possible, install a fence as the cost is not that onerous.
2147 *
2148 * If we fail to fence the tiled scanout, then either the
2149 * modeset will reject the change (which is highly unlikely as
2150 * the affected systems, all but one, do not have unmappable
2151 * space) or we will not be able to enable full powersaving
2152 * techniques (also likely not to apply due to various limits
2153 * FBC and the like impose on the size of the buffer, which
2154 * presumably we violated anyway with this unmappable buffer).
2155 * Anyway, it is presumably better to stumble onwards with
2156 * something and try to run the system in a "less than optimal"
2157 * mode that matches the user configuration.
2158 */
2159 i915_vma_pin_fence(vma);
2160 }
2161
2162 i915_vma_get(vma);
2163 err:
2164 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2165
2166 intel_runtime_pm_put(dev_priv);
2167 return vma;
2168 }
2169
2170 void intel_unpin_fb_vma(struct i915_vma *vma)
2171 {
2172 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2173
2174 i915_vma_unpin_fence(vma);
2175 i915_gem_object_unpin_from_display_plane(vma);
2176 i915_vma_put(vma);
2177 }
2178
2179 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2180 unsigned int rotation)
2181 {
2182 if (drm_rotation_90_or_270(rotation))
2183 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2184 else
2185 return fb->pitches[plane];
2186 }
2187
2188 /*
2189 * Convert the x/y offsets into a linear offset.
2190 * Only valid with 0/180 degree rotation, which is fine since linear
2191 * offset is only used with linear buffers on pre-hsw and tiled buffers
2192 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2193 */
2194 u32 intel_fb_xy_to_linear(int x, int y,
2195 const struct intel_plane_state *state,
2196 int plane)
2197 {
2198 const struct drm_framebuffer *fb = state->base.fb;
2199 unsigned int cpp = fb->format->cpp[plane];
2200 unsigned int pitch = fb->pitches[plane];
2201
2202 return y * pitch + x * cpp;
2203 }
2204
2205 /*
2206 * Add the x/y offsets derived from fb->offsets[] to the user
2207 * specified plane src x/y offsets. The resulting x/y offsets
2208 * specify the start of scanout from the beginning of the gtt mapping.
2209 */
2210 void intel_add_fb_offsets(int *x, int *y,
2211 const struct intel_plane_state *state,
2212 int plane)
2213
2214 {
2215 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2216 unsigned int rotation = state->base.rotation;
2217
2218 if (drm_rotation_90_or_270(rotation)) {
2219 *x += intel_fb->rotated[plane].x;
2220 *y += intel_fb->rotated[plane].y;
2221 } else {
2222 *x += intel_fb->normal[plane].x;
2223 *y += intel_fb->normal[plane].y;
2224 }
2225 }
2226
2227 static u32 __intel_adjust_tile_offset(int *x, int *y,
2228 unsigned int tile_width,
2229 unsigned int tile_height,
2230 unsigned int tile_size,
2231 unsigned int pitch_tiles,
2232 u32 old_offset,
2233 u32 new_offset)
2234 {
2235 unsigned int pitch_pixels = pitch_tiles * tile_width;
2236 unsigned int tiles;
2237
2238 WARN_ON(old_offset & (tile_size - 1));
2239 WARN_ON(new_offset & (tile_size - 1));
2240 WARN_ON(new_offset > old_offset);
2241
2242 tiles = (old_offset - new_offset) / tile_size;
2243
2244 *y += tiles / pitch_tiles * tile_height;
2245 *x += tiles % pitch_tiles * tile_width;
2246
2247 /* minimize x in case it got needlessly big */
2248 *y += *x / pitch_pixels * tile_height;
2249 *x %= pitch_pixels;
2250
2251 return new_offset;
2252 }
2253
2254 static u32 _intel_adjust_tile_offset(int *x, int *y,
2255 const struct drm_framebuffer *fb, int plane,
2256 unsigned int rotation,
2257 u32 old_offset, u32 new_offset)
2258 {
2259 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2260 unsigned int cpp = fb->format->cpp[plane];
2261 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2262
2263 WARN_ON(new_offset > old_offset);
2264
2265 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2266 unsigned int tile_size, tile_width, tile_height;
2267 unsigned int pitch_tiles;
2268
2269 tile_size = intel_tile_size(dev_priv);
2270 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2271
2272 if (drm_rotation_90_or_270(rotation)) {
2273 pitch_tiles = pitch / tile_height;
2274 swap(tile_width, tile_height);
2275 } else {
2276 pitch_tiles = pitch / (tile_width * cpp);
2277 }
2278
2279 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2280 tile_size, pitch_tiles,
2281 old_offset, new_offset);
2282 } else {
2283 old_offset += *y * pitch + *x * cpp;
2284
2285 *y = (old_offset - new_offset) / pitch;
2286 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2287 }
2288
2289 return new_offset;
2290 }
2291
2292 /*
2293 * Adjust the tile offset by moving the difference into
2294 * the x/y offsets.
2295 */
2296 static u32 intel_adjust_tile_offset(int *x, int *y,
2297 const struct intel_plane_state *state, int plane,
2298 u32 old_offset, u32 new_offset)
2299 {
2300 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2301 state->base.rotation,
2302 old_offset, new_offset);
2303 }
2304
2305 /*
2306 * Computes the linear offset to the base tile and adjusts
2307 * x, y. bytes per pixel is assumed to be a power-of-two.
2308 *
2309 * In the 90/270 rotated case, x and y are assumed
2310 * to be already rotated to match the rotated GTT view, and
2311 * pitch is the tile_height aligned framebuffer height.
2312 *
2313 * This function is used when computing the derived information
2314 * under intel_framebuffer, so using any of that information
2315 * here is not allowed. Anything under drm_framebuffer can be
2316 * used. This is why the user has to pass in the pitch since it
2317 * is specified in the rotated orientation.
2318 */
2319 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2320 int *x, int *y,
2321 const struct drm_framebuffer *fb, int plane,
2322 unsigned int pitch,
2323 unsigned int rotation,
2324 u32 alignment)
2325 {
2326 uint64_t fb_modifier = fb->modifier;
2327 unsigned int cpp = fb->format->cpp[plane];
2328 u32 offset, offset_aligned;
2329
2330 if (alignment)
2331 alignment--;
2332
2333 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2334 unsigned int tile_size, tile_width, tile_height;
2335 unsigned int tile_rows, tiles, pitch_tiles;
2336
2337 tile_size = intel_tile_size(dev_priv);
2338 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2339
2340 if (drm_rotation_90_or_270(rotation)) {
2341 pitch_tiles = pitch / tile_height;
2342 swap(tile_width, tile_height);
2343 } else {
2344 pitch_tiles = pitch / (tile_width * cpp);
2345 }
2346
2347 tile_rows = *y / tile_height;
2348 *y %= tile_height;
2349
2350 tiles = *x / tile_width;
2351 *x %= tile_width;
2352
2353 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2354 offset_aligned = offset & ~alignment;
2355
2356 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2357 tile_size, pitch_tiles,
2358 offset, offset_aligned);
2359 } else {
2360 offset = *y * pitch + *x * cpp;
2361 offset_aligned = offset & ~alignment;
2362
2363 *y = (offset & alignment) / pitch;
2364 *x = ((offset & alignment) - *y * pitch) / cpp;
2365 }
2366
2367 return offset_aligned;
2368 }
2369
2370 u32 intel_compute_tile_offset(int *x, int *y,
2371 const struct intel_plane_state *state,
2372 int plane)
2373 {
2374 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2375 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2376 const struct drm_framebuffer *fb = state->base.fb;
2377 unsigned int rotation = state->base.rotation;
2378 int pitch = intel_fb_pitch(fb, plane, rotation);
2379 u32 alignment;
2380
2381 if (intel_plane->id == PLANE_CURSOR)
2382 alignment = intel_cursor_alignment(dev_priv);
2383 else
2384 alignment = intel_surf_alignment(fb, plane);
2385
2386 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2387 rotation, alignment);
2388 }
2389
2390 /* Convert the fb->offset[] into x/y offsets */
2391 static int intel_fb_offset_to_xy(int *x, int *y,
2392 const struct drm_framebuffer *fb, int plane)
2393 {
2394 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2395
2396 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2397 fb->offsets[plane] % intel_tile_size(dev_priv))
2398 return -EINVAL;
2399
2400 *x = 0;
2401 *y = 0;
2402
2403 _intel_adjust_tile_offset(x, y,
2404 fb, plane, DRM_MODE_ROTATE_0,
2405 fb->offsets[plane], 0);
2406
2407 return 0;
2408 }
2409
2410 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2411 {
2412 switch (fb_modifier) {
2413 case I915_FORMAT_MOD_X_TILED:
2414 return I915_TILING_X;
2415 case I915_FORMAT_MOD_Y_TILED:
2416 case I915_FORMAT_MOD_Y_TILED_CCS:
2417 return I915_TILING_Y;
2418 default:
2419 return I915_TILING_NONE;
2420 }
2421 }
2422
2423 static const struct drm_format_info ccs_formats[] = {
2424 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2425 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2426 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2427 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2428 };
2429
2430 static const struct drm_format_info *
2431 lookup_format_info(const struct drm_format_info formats[],
2432 int num_formats, u32 format)
2433 {
2434 int i;
2435
2436 for (i = 0; i < num_formats; i++) {
2437 if (formats[i].format == format)
2438 return &formats[i];
2439 }
2440
2441 return NULL;
2442 }
2443
2444 static const struct drm_format_info *
2445 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2446 {
2447 switch (cmd->modifier[0]) {
2448 case I915_FORMAT_MOD_Y_TILED_CCS:
2449 case I915_FORMAT_MOD_Yf_TILED_CCS:
2450 return lookup_format_info(ccs_formats,
2451 ARRAY_SIZE(ccs_formats),
2452 cmd->pixel_format);
2453 default:
2454 return NULL;
2455 }
2456 }
2457
2458 static int
2459 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2460 struct drm_framebuffer *fb)
2461 {
2462 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2463 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2464 u32 gtt_offset_rotated = 0;
2465 unsigned int max_size = 0;
2466 int i, num_planes = fb->format->num_planes;
2467 unsigned int tile_size = intel_tile_size(dev_priv);
2468
2469 for (i = 0; i < num_planes; i++) {
2470 unsigned int width, height;
2471 unsigned int cpp, size;
2472 u32 offset;
2473 int x, y;
2474 int ret;
2475
2476 cpp = fb->format->cpp[i];
2477 width = drm_framebuffer_plane_width(fb->width, fb, i);
2478 height = drm_framebuffer_plane_height(fb->height, fb, i);
2479
2480 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2481 if (ret) {
2482 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2483 i, fb->offsets[i]);
2484 return ret;
2485 }
2486
2487 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2488 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2489 int hsub = fb->format->hsub;
2490 int vsub = fb->format->vsub;
2491 int tile_width, tile_height;
2492 int main_x, main_y;
2493 int ccs_x, ccs_y;
2494
2495 intel_tile_dims(fb, i, &tile_width, &tile_height);
2496 tile_width *= hsub;
2497 tile_height *= vsub;
2498
2499 ccs_x = (x * hsub) % tile_width;
2500 ccs_y = (y * vsub) % tile_height;
2501 main_x = intel_fb->normal[0].x % tile_width;
2502 main_y = intel_fb->normal[0].y % tile_height;
2503
2504 /*
2505 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2506 * x/y offsets must match between CCS and the main surface.
2507 */
2508 if (main_x != ccs_x || main_y != ccs_y) {
2509 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2510 main_x, main_y,
2511 ccs_x, ccs_y,
2512 intel_fb->normal[0].x,
2513 intel_fb->normal[0].y,
2514 x, y);
2515 return -EINVAL;
2516 }
2517 }
2518
2519 /*
2520 * The fence (if used) is aligned to the start of the object
2521 * so having the framebuffer wrap around across the edge of the
2522 * fenced region doesn't really work. We have no API to configure
2523 * the fence start offset within the object (nor could we probably
2524 * on gen2/3). So it's just easier if we just require that the
2525 * fb layout agrees with the fence layout. We already check that the
2526 * fb stride matches the fence stride elsewhere.
2527 */
2528 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2529 (x + width) * cpp > fb->pitches[i]) {
2530 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2531 i, fb->offsets[i]);
2532 return -EINVAL;
2533 }
2534
2535 /*
2536 * First pixel of the framebuffer from
2537 * the start of the normal gtt mapping.
2538 */
2539 intel_fb->normal[i].x = x;
2540 intel_fb->normal[i].y = y;
2541
2542 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2543 fb, i, fb->pitches[i],
2544 DRM_MODE_ROTATE_0, tile_size);
2545 offset /= tile_size;
2546
2547 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2548 unsigned int tile_width, tile_height;
2549 unsigned int pitch_tiles;
2550 struct drm_rect r;
2551
2552 intel_tile_dims(fb, i, &tile_width, &tile_height);
2553
2554 rot_info->plane[i].offset = offset;
2555 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2556 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2557 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2558
2559 intel_fb->rotated[i].pitch =
2560 rot_info->plane[i].height * tile_height;
2561
2562 /* how many tiles does this plane need */
2563 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2564 /*
2565 * If the plane isn't horizontally tile aligned,
2566 * we need one more tile.
2567 */
2568 if (x != 0)
2569 size++;
2570
2571 /* rotate the x/y offsets to match the GTT view */
2572 r.x1 = x;
2573 r.y1 = y;
2574 r.x2 = x + width;
2575 r.y2 = y + height;
2576 drm_rect_rotate(&r,
2577 rot_info->plane[i].width * tile_width,
2578 rot_info->plane[i].height * tile_height,
2579 DRM_MODE_ROTATE_270);
2580 x = r.x1;
2581 y = r.y1;
2582
2583 /* rotate the tile dimensions to match the GTT view */
2584 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2585 swap(tile_width, tile_height);
2586
2587 /*
2588 * We only keep the x/y offsets, so push all of the
2589 * gtt offset into the x/y offsets.
2590 */
2591 __intel_adjust_tile_offset(&x, &y,
2592 tile_width, tile_height,
2593 tile_size, pitch_tiles,
2594 gtt_offset_rotated * tile_size, 0);
2595
2596 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2597
2598 /*
2599 * First pixel of the framebuffer from
2600 * the start of the rotated gtt mapping.
2601 */
2602 intel_fb->rotated[i].x = x;
2603 intel_fb->rotated[i].y = y;
2604 } else {
2605 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2606 x * cpp, tile_size);
2607 }
2608
2609 /* how many tiles in total needed in the bo */
2610 max_size = max(max_size, offset + size);
2611 }
2612
2613 if (max_size * tile_size > intel_fb->obj->base.size) {
2614 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2615 max_size * tile_size, intel_fb->obj->base.size);
2616 return -EINVAL;
2617 }
2618
2619 return 0;
2620 }
2621
2622 static int i9xx_format_to_fourcc(int format)
2623 {
2624 switch (format) {
2625 case DISPPLANE_8BPP:
2626 return DRM_FORMAT_C8;
2627 case DISPPLANE_BGRX555:
2628 return DRM_FORMAT_XRGB1555;
2629 case DISPPLANE_BGRX565:
2630 return DRM_FORMAT_RGB565;
2631 default:
2632 case DISPPLANE_BGRX888:
2633 return DRM_FORMAT_XRGB8888;
2634 case DISPPLANE_RGBX888:
2635 return DRM_FORMAT_XBGR8888;
2636 case DISPPLANE_BGRX101010:
2637 return DRM_FORMAT_XRGB2101010;
2638 case DISPPLANE_RGBX101010:
2639 return DRM_FORMAT_XBGR2101010;
2640 }
2641 }
2642
2643 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2644 {
2645 switch (format) {
2646 case PLANE_CTL_FORMAT_RGB_565:
2647 return DRM_FORMAT_RGB565;
2648 default:
2649 case PLANE_CTL_FORMAT_XRGB_8888:
2650 if (rgb_order) {
2651 if (alpha)
2652 return DRM_FORMAT_ABGR8888;
2653 else
2654 return DRM_FORMAT_XBGR8888;
2655 } else {
2656 if (alpha)
2657 return DRM_FORMAT_ARGB8888;
2658 else
2659 return DRM_FORMAT_XRGB8888;
2660 }
2661 case PLANE_CTL_FORMAT_XRGB_2101010:
2662 if (rgb_order)
2663 return DRM_FORMAT_XBGR2101010;
2664 else
2665 return DRM_FORMAT_XRGB2101010;
2666 }
2667 }
2668
2669 static bool
2670 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2671 struct intel_initial_plane_config *plane_config)
2672 {
2673 struct drm_device *dev = crtc->base.dev;
2674 struct drm_i915_private *dev_priv = to_i915(dev);
2675 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2676 struct drm_i915_gem_object *obj = NULL;
2677 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2678 struct drm_framebuffer *fb = &plane_config->fb->base;
2679 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2680 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2681 PAGE_SIZE);
2682
2683 size_aligned -= base_aligned;
2684
2685 if (plane_config->size == 0)
2686 return false;
2687
2688 /* If the FB is too big, just don't use it since fbdev is not very
2689 * important and we should probably use that space with FBC or other
2690 * features. */
2691 if (size_aligned * 2 > ggtt->stolen_usable_size)
2692 return false;
2693
2694 switch (fb->modifier) {
2695 case DRM_FORMAT_MOD_LINEAR:
2696 case I915_FORMAT_MOD_X_TILED:
2697 case I915_FORMAT_MOD_Y_TILED:
2698 break;
2699 default:
2700 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2701 fb->modifier);
2702 return false;
2703 }
2704
2705 mutex_lock(&dev->struct_mutex);
2706 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2707 base_aligned,
2708 base_aligned,
2709 size_aligned);
2710 mutex_unlock(&dev->struct_mutex);
2711 if (!obj)
2712 return false;
2713
2714 switch (plane_config->tiling) {
2715 case I915_TILING_NONE:
2716 break;
2717 case I915_TILING_X:
2718 case I915_TILING_Y:
2719 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2720 break;
2721 default:
2722 MISSING_CASE(plane_config->tiling);
2723 return false;
2724 }
2725
2726 mode_cmd.pixel_format = fb->format->format;
2727 mode_cmd.width = fb->width;
2728 mode_cmd.height = fb->height;
2729 mode_cmd.pitches[0] = fb->pitches[0];
2730 mode_cmd.modifier[0] = fb->modifier;
2731 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2732
2733 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2734 DRM_DEBUG_KMS("intel fb init failed\n");
2735 goto out_unref_obj;
2736 }
2737
2738
2739 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2740 return true;
2741
2742 out_unref_obj:
2743 i915_gem_object_put(obj);
2744 return false;
2745 }
2746
2747 static void
2748 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2749 struct intel_plane_state *plane_state,
2750 bool visible)
2751 {
2752 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2753
2754 plane_state->base.visible = visible;
2755
2756 /* FIXME pre-g4x don't work like this */
2757 if (visible) {
2758 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2759 crtc_state->active_planes |= BIT(plane->id);
2760 } else {
2761 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2762 crtc_state->active_planes &= ~BIT(plane->id);
2763 }
2764
2765 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2766 crtc_state->base.crtc->name,
2767 crtc_state->active_planes);
2768 }
2769
2770 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2771 struct intel_plane *plane)
2772 {
2773 struct intel_crtc_state *crtc_state =
2774 to_intel_crtc_state(crtc->base.state);
2775 struct intel_plane_state *plane_state =
2776 to_intel_plane_state(plane->base.state);
2777
2778 intel_set_plane_visible(crtc_state, plane_state, false);
2779
2780 if (plane->id == PLANE_PRIMARY)
2781 intel_pre_disable_primary_noatomic(&crtc->base);
2782
2783 trace_intel_disable_plane(&plane->base, crtc);
2784 plane->disable_plane(plane, crtc);
2785 }
2786
2787 static void
2788 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2789 struct intel_initial_plane_config *plane_config)
2790 {
2791 struct drm_device *dev = intel_crtc->base.dev;
2792 struct drm_i915_private *dev_priv = to_i915(dev);
2793 struct drm_crtc *c;
2794 struct drm_i915_gem_object *obj;
2795 struct drm_plane *primary = intel_crtc->base.primary;
2796 struct drm_plane_state *plane_state = primary->state;
2797 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2798 struct intel_plane *intel_plane = to_intel_plane(primary);
2799 struct intel_plane_state *intel_state =
2800 to_intel_plane_state(plane_state);
2801 struct drm_framebuffer *fb;
2802
2803 if (!plane_config->fb)
2804 return;
2805
2806 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2807 fb = &plane_config->fb->base;
2808 goto valid_fb;
2809 }
2810
2811 kfree(plane_config->fb);
2812
2813 /*
2814 * Failed to alloc the obj, check to see if we should share
2815 * an fb with another CRTC instead
2816 */
2817 for_each_crtc(dev, c) {
2818 struct intel_plane_state *state;
2819
2820 if (c == &intel_crtc->base)
2821 continue;
2822
2823 if (!to_intel_crtc(c)->active)
2824 continue;
2825
2826 state = to_intel_plane_state(c->primary->state);
2827 if (!state->vma)
2828 continue;
2829
2830 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2831 fb = c->primary->fb;
2832 drm_framebuffer_get(fb);
2833 goto valid_fb;
2834 }
2835 }
2836
2837 /*
2838 * We've failed to reconstruct the BIOS FB. Current display state
2839 * indicates that the primary plane is visible, but has a NULL FB,
2840 * which will lead to problems later if we don't fix it up. The
2841 * simplest solution is to just disable the primary plane now and
2842 * pretend the BIOS never had it enabled.
2843 */
2844 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2845
2846 return;
2847
2848 valid_fb:
2849 mutex_lock(&dev->struct_mutex);
2850 intel_state->vma =
2851 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2852 mutex_unlock(&dev->struct_mutex);
2853 if (IS_ERR(intel_state->vma)) {
2854 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2855 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2856
2857 intel_state->vma = NULL;
2858 drm_framebuffer_put(fb);
2859 return;
2860 }
2861
2862 plane_state->src_x = 0;
2863 plane_state->src_y = 0;
2864 plane_state->src_w = fb->width << 16;
2865 plane_state->src_h = fb->height << 16;
2866
2867 plane_state->crtc_x = 0;
2868 plane_state->crtc_y = 0;
2869 plane_state->crtc_w = fb->width;
2870 plane_state->crtc_h = fb->height;
2871
2872 intel_state->base.src = drm_plane_state_src(plane_state);
2873 intel_state->base.dst = drm_plane_state_dest(plane_state);
2874
2875 obj = intel_fb_obj(fb);
2876 if (i915_gem_object_is_tiled(obj))
2877 dev_priv->preserve_bios_swizzle = true;
2878
2879 drm_framebuffer_get(fb);
2880 primary->fb = primary->state->fb = fb;
2881 primary->crtc = primary->state->crtc = &intel_crtc->base;
2882
2883 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2884 to_intel_plane_state(plane_state),
2885 true);
2886
2887 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2888 &obj->frontbuffer_bits);
2889 }
2890
2891 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2892 unsigned int rotation)
2893 {
2894 int cpp = fb->format->cpp[plane];
2895
2896 switch (fb->modifier) {
2897 case DRM_FORMAT_MOD_LINEAR:
2898 case I915_FORMAT_MOD_X_TILED:
2899 switch (cpp) {
2900 case 8:
2901 return 4096;
2902 case 4:
2903 case 2:
2904 case 1:
2905 return 8192;
2906 default:
2907 MISSING_CASE(cpp);
2908 break;
2909 }
2910 break;
2911 case I915_FORMAT_MOD_Y_TILED_CCS:
2912 case I915_FORMAT_MOD_Yf_TILED_CCS:
2913 /* FIXME AUX plane? */
2914 case I915_FORMAT_MOD_Y_TILED:
2915 case I915_FORMAT_MOD_Yf_TILED:
2916 switch (cpp) {
2917 case 8:
2918 return 2048;
2919 case 4:
2920 return 4096;
2921 case 2:
2922 case 1:
2923 return 8192;
2924 default:
2925 MISSING_CASE(cpp);
2926 break;
2927 }
2928 break;
2929 default:
2930 MISSING_CASE(fb->modifier);
2931 }
2932
2933 return 2048;
2934 }
2935
2936 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2937 int main_x, int main_y, u32 main_offset)
2938 {
2939 const struct drm_framebuffer *fb = plane_state->base.fb;
2940 int hsub = fb->format->hsub;
2941 int vsub = fb->format->vsub;
2942 int aux_x = plane_state->aux.x;
2943 int aux_y = plane_state->aux.y;
2944 u32 aux_offset = plane_state->aux.offset;
2945 u32 alignment = intel_surf_alignment(fb, 1);
2946
2947 while (aux_offset >= main_offset && aux_y <= main_y) {
2948 int x, y;
2949
2950 if (aux_x == main_x && aux_y == main_y)
2951 break;
2952
2953 if (aux_offset == 0)
2954 break;
2955
2956 x = aux_x / hsub;
2957 y = aux_y / vsub;
2958 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2959 aux_offset, aux_offset - alignment);
2960 aux_x = x * hsub + aux_x % hsub;
2961 aux_y = y * vsub + aux_y % vsub;
2962 }
2963
2964 if (aux_x != main_x || aux_y != main_y)
2965 return false;
2966
2967 plane_state->aux.offset = aux_offset;
2968 plane_state->aux.x = aux_x;
2969 plane_state->aux.y = aux_y;
2970
2971 return true;
2972 }
2973
2974 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2975 {
2976 const struct drm_framebuffer *fb = plane_state->base.fb;
2977 unsigned int rotation = plane_state->base.rotation;
2978 int x = plane_state->base.src.x1 >> 16;
2979 int y = plane_state->base.src.y1 >> 16;
2980 int w = drm_rect_width(&plane_state->base.src) >> 16;
2981 int h = drm_rect_height(&plane_state->base.src) >> 16;
2982 int max_width = skl_max_plane_width(fb, 0, rotation);
2983 int max_height = 4096;
2984 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2985
2986 if (w > max_width || h > max_height) {
2987 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2988 w, h, max_width, max_height);
2989 return -EINVAL;
2990 }
2991
2992 intel_add_fb_offsets(&x, &y, plane_state, 0);
2993 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2994 alignment = intel_surf_alignment(fb, 0);
2995
2996 /*
2997 * AUX surface offset is specified as the distance from the
2998 * main surface offset, and it must be non-negative. Make
2999 * sure that is what we will get.
3000 */
3001 if (offset > aux_offset)
3002 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3003 offset, aux_offset & ~(alignment - 1));
3004
3005 /*
3006 * When using an X-tiled surface, the plane blows up
3007 * if the x offset + width exceed the stride.
3008 *
3009 * TODO: linear and Y-tiled seem fine, Yf untested,
3010 */
3011 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3012 int cpp = fb->format->cpp[0];
3013
3014 while ((x + w) * cpp > fb->pitches[0]) {
3015 if (offset == 0) {
3016 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3017 return -EINVAL;
3018 }
3019
3020 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3021 offset, offset - alignment);
3022 }
3023 }
3024
3025 /*
3026 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3027 * they match with the main surface x/y offsets.
3028 */
3029 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3030 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3031 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3032 if (offset == 0)
3033 break;
3034
3035 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3036 offset, offset - alignment);
3037 }
3038
3039 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3040 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3041 return -EINVAL;
3042 }
3043 }
3044
3045 plane_state->main.offset = offset;
3046 plane_state->main.x = x;
3047 plane_state->main.y = y;
3048
3049 return 0;
3050 }
3051
3052 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3053 {
3054 const struct drm_framebuffer *fb = plane_state->base.fb;
3055 unsigned int rotation = plane_state->base.rotation;
3056 int max_width = skl_max_plane_width(fb, 1, rotation);
3057 int max_height = 4096;
3058 int x = plane_state->base.src.x1 >> 17;
3059 int y = plane_state->base.src.y1 >> 17;
3060 int w = drm_rect_width(&plane_state->base.src) >> 17;
3061 int h = drm_rect_height(&plane_state->base.src) >> 17;
3062 u32 offset;
3063
3064 intel_add_fb_offsets(&x, &y, plane_state, 1);
3065 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3066
3067 /* FIXME not quite sure how/if these apply to the chroma plane */
3068 if (w > max_width || h > max_height) {
3069 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3070 w, h, max_width, max_height);
3071 return -EINVAL;
3072 }
3073
3074 plane_state->aux.offset = offset;
3075 plane_state->aux.x = x;
3076 plane_state->aux.y = y;
3077
3078 return 0;
3079 }
3080
3081 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3082 {
3083 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3084 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3085 const struct drm_framebuffer *fb = plane_state->base.fb;
3086 int src_x = plane_state->base.src.x1 >> 16;
3087 int src_y = plane_state->base.src.y1 >> 16;
3088 int hsub = fb->format->hsub;
3089 int vsub = fb->format->vsub;
3090 int x = src_x / hsub;
3091 int y = src_y / vsub;
3092 u32 offset;
3093
3094 switch (plane->id) {
3095 case PLANE_PRIMARY:
3096 case PLANE_SPRITE0:
3097 break;
3098 default:
3099 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3100 return -EINVAL;
3101 }
3102
3103 if (crtc->pipe == PIPE_C) {
3104 DRM_DEBUG_KMS("No RC support on pipe C\n");
3105 return -EINVAL;
3106 }
3107
3108 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3109 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3110 plane_state->base.rotation);
3111 return -EINVAL;
3112 }
3113
3114 intel_add_fb_offsets(&x, &y, plane_state, 1);
3115 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3116
3117 plane_state->aux.offset = offset;
3118 plane_state->aux.x = x * hsub + src_x % hsub;
3119 plane_state->aux.y = y * vsub + src_y % vsub;
3120
3121 return 0;
3122 }
3123
3124 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3125 {
3126 const struct drm_framebuffer *fb = plane_state->base.fb;
3127 unsigned int rotation = plane_state->base.rotation;
3128 int ret;
3129
3130 if (!plane_state->base.visible)
3131 return 0;
3132
3133 /* Rotate src coordinates to match rotated GTT view */
3134 if (drm_rotation_90_or_270(rotation))
3135 drm_rect_rotate(&plane_state->base.src,
3136 fb->width << 16, fb->height << 16,
3137 DRM_MODE_ROTATE_270);
3138
3139 /*
3140 * Handle the AUX surface first since
3141 * the main surface setup depends on it.
3142 */
3143 if (fb->format->format == DRM_FORMAT_NV12) {
3144 ret = skl_check_nv12_aux_surface(plane_state);
3145 if (ret)
3146 return ret;
3147 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3148 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3149 ret = skl_check_ccs_aux_surface(plane_state);
3150 if (ret)
3151 return ret;
3152 } else {
3153 plane_state->aux.offset = ~0xfff;
3154 plane_state->aux.x = 0;
3155 plane_state->aux.y = 0;
3156 }
3157
3158 ret = skl_check_main_surface(plane_state);
3159 if (ret)
3160 return ret;
3161
3162 return 0;
3163 }
3164
3165 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3166 const struct intel_plane_state *plane_state)
3167 {
3168 struct drm_i915_private *dev_priv =
3169 to_i915(plane_state->base.plane->dev);
3170 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3171 const struct drm_framebuffer *fb = plane_state->base.fb;
3172 unsigned int rotation = plane_state->base.rotation;
3173 u32 dspcntr;
3174
3175 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3176
3177 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3178 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3180
3181 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3182 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3183
3184 if (INTEL_GEN(dev_priv) < 4)
3185 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3186
3187 switch (fb->format->format) {
3188 case DRM_FORMAT_C8:
3189 dspcntr |= DISPPLANE_8BPP;
3190 break;
3191 case DRM_FORMAT_XRGB1555:
3192 dspcntr |= DISPPLANE_BGRX555;
3193 break;
3194 case DRM_FORMAT_RGB565:
3195 dspcntr |= DISPPLANE_BGRX565;
3196 break;
3197 case DRM_FORMAT_XRGB8888:
3198 dspcntr |= DISPPLANE_BGRX888;
3199 break;
3200 case DRM_FORMAT_XBGR8888:
3201 dspcntr |= DISPPLANE_RGBX888;
3202 break;
3203 case DRM_FORMAT_XRGB2101010:
3204 dspcntr |= DISPPLANE_BGRX101010;
3205 break;
3206 case DRM_FORMAT_XBGR2101010:
3207 dspcntr |= DISPPLANE_RGBX101010;
3208 break;
3209 default:
3210 MISSING_CASE(fb->format->format);
3211 return 0;
3212 }
3213
3214 if (INTEL_GEN(dev_priv) >= 4 &&
3215 fb->modifier == I915_FORMAT_MOD_X_TILED)
3216 dspcntr |= DISPPLANE_TILED;
3217
3218 if (rotation & DRM_MODE_ROTATE_180)
3219 dspcntr |= DISPPLANE_ROTATE_180;
3220
3221 if (rotation & DRM_MODE_REFLECT_X)
3222 dspcntr |= DISPPLANE_MIRROR;
3223
3224 return dspcntr;
3225 }
3226
3227 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3228 {
3229 struct drm_i915_private *dev_priv =
3230 to_i915(plane_state->base.plane->dev);
3231 int src_x = plane_state->base.src.x1 >> 16;
3232 int src_y = plane_state->base.src.y1 >> 16;
3233 u32 offset;
3234
3235 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3236
3237 if (INTEL_GEN(dev_priv) >= 4)
3238 offset = intel_compute_tile_offset(&src_x, &src_y,
3239 plane_state, 0);
3240 else
3241 offset = 0;
3242
3243 /* HSW/BDW do this automagically in hardware */
3244 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3245 unsigned int rotation = plane_state->base.rotation;
3246 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3247 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3248
3249 if (rotation & DRM_MODE_ROTATE_180) {
3250 src_x += src_w - 1;
3251 src_y += src_h - 1;
3252 } else if (rotation & DRM_MODE_REFLECT_X) {
3253 src_x += src_w - 1;
3254 }
3255 }
3256
3257 plane_state->main.offset = offset;
3258 plane_state->main.x = src_x;
3259 plane_state->main.y = src_y;
3260
3261 return 0;
3262 }
3263
3264 static void i9xx_update_primary_plane(struct intel_plane *primary,
3265 const struct intel_crtc_state *crtc_state,
3266 const struct intel_plane_state *plane_state)
3267 {
3268 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3269 const struct drm_framebuffer *fb = plane_state->base.fb;
3270 enum plane plane = primary->plane;
3271 u32 linear_offset;
3272 u32 dspcntr = plane_state->ctl;
3273 i915_reg_t reg = DSPCNTR(plane);
3274 int x = plane_state->main.x;
3275 int y = plane_state->main.y;
3276 unsigned long irqflags;
3277 u32 dspaddr_offset;
3278
3279 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3280
3281 if (INTEL_GEN(dev_priv) >= 4)
3282 dspaddr_offset = plane_state->main.offset;
3283 else
3284 dspaddr_offset = linear_offset;
3285
3286 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3287
3288 if (INTEL_GEN(dev_priv) < 4) {
3289 /* pipesrc and dspsize control the size that is scaled from,
3290 * which should always be the user's requested size.
3291 */
3292 I915_WRITE_FW(DSPSIZE(plane),
3293 ((crtc_state->pipe_src_h - 1) << 16) |
3294 (crtc_state->pipe_src_w - 1));
3295 I915_WRITE_FW(DSPPOS(plane), 0);
3296 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3297 I915_WRITE_FW(PRIMSIZE(plane),
3298 ((crtc_state->pipe_src_h - 1) << 16) |
3299 (crtc_state->pipe_src_w - 1));
3300 I915_WRITE_FW(PRIMPOS(plane), 0);
3301 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3302 }
3303
3304 I915_WRITE_FW(reg, dspcntr);
3305
3306 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3307 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3308 I915_WRITE_FW(DSPSURF(plane),
3309 intel_plane_ggtt_offset(plane_state) +
3310 dspaddr_offset);
3311 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3312 } else if (INTEL_GEN(dev_priv) >= 4) {
3313 I915_WRITE_FW(DSPSURF(plane),
3314 intel_plane_ggtt_offset(plane_state) +
3315 dspaddr_offset);
3316 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3317 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3318 } else {
3319 I915_WRITE_FW(DSPADDR(plane),
3320 intel_plane_ggtt_offset(plane_state) +
3321 dspaddr_offset);
3322 }
3323 POSTING_READ_FW(reg);
3324
3325 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3326 }
3327
3328 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3329 struct intel_crtc *crtc)
3330 {
3331 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3332 enum plane plane = primary->plane;
3333 unsigned long irqflags;
3334
3335 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3336
3337 I915_WRITE_FW(DSPCNTR(plane), 0);
3338 if (INTEL_INFO(dev_priv)->gen >= 4)
3339 I915_WRITE_FW(DSPSURF(plane), 0);
3340 else
3341 I915_WRITE_FW(DSPADDR(plane), 0);
3342 POSTING_READ_FW(DSPCNTR(plane));
3343
3344 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3345 }
3346
3347 static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
3348 {
3349
3350 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3351 enum intel_display_power_domain power_domain;
3352 enum plane plane = primary->plane;
3353 enum pipe pipe = primary->pipe;
3354 bool ret;
3355
3356 /*
3357 * Not 100% correct for planes that can move between pipes,
3358 * but that's only the case for gen2-4 which don't have any
3359 * display power wells.
3360 */
3361 power_domain = POWER_DOMAIN_PIPE(pipe);
3362 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3363 return false;
3364
3365 ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
3366
3367 intel_display_power_put(dev_priv, power_domain);
3368
3369 return ret;
3370 }
3371
3372 static u32
3373 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3374 {
3375 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3376 return 64;
3377 else
3378 return intel_tile_width_bytes(fb, plane);
3379 }
3380
3381 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3382 {
3383 struct drm_device *dev = intel_crtc->base.dev;
3384 struct drm_i915_private *dev_priv = to_i915(dev);
3385
3386 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3387 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3388 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3389 }
3390
3391 /*
3392 * This function detaches (aka. unbinds) unused scalers in hardware
3393 */
3394 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3395 {
3396 struct intel_crtc_scaler_state *scaler_state;
3397 int i;
3398
3399 scaler_state = &intel_crtc->config->scaler_state;
3400
3401 /* loop through and disable scalers that aren't in use */
3402 for (i = 0; i < intel_crtc->num_scalers; i++) {
3403 if (!scaler_state->scalers[i].in_use)
3404 skl_detach_scaler(intel_crtc, i);
3405 }
3406 }
3407
3408 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3409 unsigned int rotation)
3410 {
3411 u32 stride;
3412
3413 if (plane >= fb->format->num_planes)
3414 return 0;
3415
3416 stride = intel_fb_pitch(fb, plane, rotation);
3417
3418 /*
3419 * The stride is either expressed as a multiple of 64 bytes chunks for
3420 * linear buffers or in number of tiles for tiled buffers.
3421 */
3422 if (drm_rotation_90_or_270(rotation))
3423 stride /= intel_tile_height(fb, plane);
3424 else
3425 stride /= intel_fb_stride_alignment(fb, plane);
3426
3427 return stride;
3428 }
3429
3430 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3431 {
3432 switch (pixel_format) {
3433 case DRM_FORMAT_C8:
3434 return PLANE_CTL_FORMAT_INDEXED;
3435 case DRM_FORMAT_RGB565:
3436 return PLANE_CTL_FORMAT_RGB_565;
3437 case DRM_FORMAT_XBGR8888:
3438 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3439 case DRM_FORMAT_XRGB8888:
3440 return PLANE_CTL_FORMAT_XRGB_8888;
3441 /*
3442 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3443 * to be already pre-multiplied. We need to add a knob (or a different
3444 * DRM_FORMAT) for user-space to configure that.
3445 */
3446 case DRM_FORMAT_ABGR8888:
3447 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3448 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3449 case DRM_FORMAT_ARGB8888:
3450 return PLANE_CTL_FORMAT_XRGB_8888 |
3451 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3452 case DRM_FORMAT_XRGB2101010:
3453 return PLANE_CTL_FORMAT_XRGB_2101010;
3454 case DRM_FORMAT_XBGR2101010:
3455 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3456 case DRM_FORMAT_YUYV:
3457 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3458 case DRM_FORMAT_YVYU:
3459 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3460 case DRM_FORMAT_UYVY:
3461 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3462 case DRM_FORMAT_VYUY:
3463 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3464 default:
3465 MISSING_CASE(pixel_format);
3466 }
3467
3468 return 0;
3469 }
3470
3471 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3472 {
3473 switch (fb_modifier) {
3474 case DRM_FORMAT_MOD_LINEAR:
3475 break;
3476 case I915_FORMAT_MOD_X_TILED:
3477 return PLANE_CTL_TILED_X;
3478 case I915_FORMAT_MOD_Y_TILED:
3479 return PLANE_CTL_TILED_Y;
3480 case I915_FORMAT_MOD_Y_TILED_CCS:
3481 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3482 case I915_FORMAT_MOD_Yf_TILED:
3483 return PLANE_CTL_TILED_YF;
3484 case I915_FORMAT_MOD_Yf_TILED_CCS:
3485 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3486 default:
3487 MISSING_CASE(fb_modifier);
3488 }
3489
3490 return 0;
3491 }
3492
3493 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3494 {
3495 switch (rotation) {
3496 case DRM_MODE_ROTATE_0:
3497 break;
3498 /*
3499 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3500 * while i915 HW rotation is clockwise, thats why this swapping.
3501 */
3502 case DRM_MODE_ROTATE_90:
3503 return PLANE_CTL_ROTATE_270;
3504 case DRM_MODE_ROTATE_180:
3505 return PLANE_CTL_ROTATE_180;
3506 case DRM_MODE_ROTATE_270:
3507 return PLANE_CTL_ROTATE_90;
3508 default:
3509 MISSING_CASE(rotation);
3510 }
3511
3512 return 0;
3513 }
3514
3515 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3516 const struct intel_plane_state *plane_state)
3517 {
3518 struct drm_i915_private *dev_priv =
3519 to_i915(plane_state->base.plane->dev);
3520 const struct drm_framebuffer *fb = plane_state->base.fb;
3521 unsigned int rotation = plane_state->base.rotation;
3522 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3523 u32 plane_ctl;
3524
3525 plane_ctl = PLANE_CTL_ENABLE;
3526
3527 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3528 plane_ctl |=
3529 PLANE_CTL_PIPE_GAMMA_ENABLE |
3530 PLANE_CTL_PIPE_CSC_ENABLE |
3531 PLANE_CTL_PLANE_GAMMA_DISABLE;
3532 }
3533
3534 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3535 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3536 plane_ctl |= skl_plane_ctl_rotation(rotation);
3537
3538 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3539 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3540 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3541 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3542
3543 return plane_ctl;
3544 }
3545
3546 static int
3547 __intel_display_resume(struct drm_device *dev,
3548 struct drm_atomic_state *state,
3549 struct drm_modeset_acquire_ctx *ctx)
3550 {
3551 struct drm_crtc_state *crtc_state;
3552 struct drm_crtc *crtc;
3553 int i, ret;
3554
3555 intel_modeset_setup_hw_state(dev, ctx);
3556 i915_redisable_vga(to_i915(dev));
3557
3558 if (!state)
3559 return 0;
3560
3561 /*
3562 * We've duplicated the state, pointers to the old state are invalid.
3563 *
3564 * Don't attempt to use the old state until we commit the duplicated state.
3565 */
3566 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3567 /*
3568 * Force recalculation even if we restore
3569 * current state. With fast modeset this may not result
3570 * in a modeset when the state is compatible.
3571 */
3572 crtc_state->mode_changed = true;
3573 }
3574
3575 /* ignore any reset values/BIOS leftovers in the WM registers */
3576 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3577 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3578
3579 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3580
3581 WARN_ON(ret == -EDEADLK);
3582 return ret;
3583 }
3584
3585 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3586 {
3587 return intel_has_gpu_reset(dev_priv) &&
3588 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3589 }
3590
3591 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3592 {
3593 struct drm_device *dev = &dev_priv->drm;
3594 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3595 struct drm_atomic_state *state;
3596 int ret;
3597
3598
3599 /* reset doesn't touch the display */
3600 if (!i915_modparams.force_reset_modeset_test &&
3601 !gpu_reset_clobbers_display(dev_priv))
3602 return;
3603
3604 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3605 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3606 wake_up_all(&dev_priv->gpu_error.wait_queue);
3607
3608 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3609 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3610 i915_gem_set_wedged(dev_priv);
3611 }
3612
3613 /*
3614 * Need mode_config.mutex so that we don't
3615 * trample ongoing ->detect() and whatnot.
3616 */
3617 mutex_lock(&dev->mode_config.mutex);
3618 drm_modeset_acquire_init(ctx, 0);
3619 while (1) {
3620 ret = drm_modeset_lock_all_ctx(dev, ctx);
3621 if (ret != -EDEADLK)
3622 break;
3623
3624 drm_modeset_backoff(ctx);
3625 }
3626 /*
3627 * Disabling the crtcs gracefully seems nicer. Also the
3628 * g33 docs say we should at least disable all the planes.
3629 */
3630 state = drm_atomic_helper_duplicate_state(dev, ctx);
3631 if (IS_ERR(state)) {
3632 ret = PTR_ERR(state);
3633 DRM_ERROR("Duplicating state failed with %i\n", ret);
3634 return;
3635 }
3636
3637 ret = drm_atomic_helper_disable_all(dev, ctx);
3638 if (ret) {
3639 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3640 drm_atomic_state_put(state);
3641 return;
3642 }
3643
3644 dev_priv->modeset_restore_state = state;
3645 state->acquire_ctx = ctx;
3646 }
3647
3648 void intel_finish_reset(struct drm_i915_private *dev_priv)
3649 {
3650 struct drm_device *dev = &dev_priv->drm;
3651 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3652 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3653 int ret;
3654
3655 /* reset doesn't touch the display */
3656 if (!i915_modparams.force_reset_modeset_test &&
3657 !gpu_reset_clobbers_display(dev_priv))
3658 return;
3659
3660 if (!state)
3661 goto unlock;
3662
3663 dev_priv->modeset_restore_state = NULL;
3664
3665 /* reset doesn't touch the display */
3666 if (!gpu_reset_clobbers_display(dev_priv)) {
3667 /* for testing only restore the display */
3668 ret = __intel_display_resume(dev, state, ctx);
3669 if (ret)
3670 DRM_ERROR("Restoring old state failed with %i\n", ret);
3671 } else {
3672 /*
3673 * The display has been reset as well,
3674 * so need a full re-initialization.
3675 */
3676 intel_runtime_pm_disable_interrupts(dev_priv);
3677 intel_runtime_pm_enable_interrupts(dev_priv);
3678
3679 intel_pps_unlock_regs_wa(dev_priv);
3680 intel_modeset_init_hw(dev);
3681 intel_init_clock_gating(dev_priv);
3682
3683 spin_lock_irq(&dev_priv->irq_lock);
3684 if (dev_priv->display.hpd_irq_setup)
3685 dev_priv->display.hpd_irq_setup(dev_priv);
3686 spin_unlock_irq(&dev_priv->irq_lock);
3687
3688 ret = __intel_display_resume(dev, state, ctx);
3689 if (ret)
3690 DRM_ERROR("Restoring old state failed with %i\n", ret);
3691
3692 intel_hpd_init(dev_priv);
3693 }
3694
3695 drm_atomic_state_put(state);
3696 unlock:
3697 drm_modeset_drop_locks(ctx);
3698 drm_modeset_acquire_fini(ctx);
3699 mutex_unlock(&dev->mode_config.mutex);
3700
3701 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3702 }
3703
3704 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3705 const struct intel_crtc_state *new_crtc_state)
3706 {
3707 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3708 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3709
3710 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3711 crtc->base.mode = new_crtc_state->base.mode;
3712
3713 /*
3714 * Update pipe size and adjust fitter if needed: the reason for this is
3715 * that in compute_mode_changes we check the native mode (not the pfit
3716 * mode) to see if we can flip rather than do a full mode set. In the
3717 * fastboot case, we'll flip, but if we don't update the pipesrc and
3718 * pfit state, we'll end up with a big fb scanned out into the wrong
3719 * sized surface.
3720 */
3721
3722 I915_WRITE(PIPESRC(crtc->pipe),
3723 ((new_crtc_state->pipe_src_w - 1) << 16) |
3724 (new_crtc_state->pipe_src_h - 1));
3725
3726 /* on skylake this is done by detaching scalers */
3727 if (INTEL_GEN(dev_priv) >= 9) {
3728 skl_detach_scalers(crtc);
3729
3730 if (new_crtc_state->pch_pfit.enabled)
3731 skylake_pfit_enable(crtc);
3732 } else if (HAS_PCH_SPLIT(dev_priv)) {
3733 if (new_crtc_state->pch_pfit.enabled)
3734 ironlake_pfit_enable(crtc);
3735 else if (old_crtc_state->pch_pfit.enabled)
3736 ironlake_pfit_disable(crtc, true);
3737 }
3738 }
3739
3740 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3741 {
3742 struct drm_device *dev = crtc->base.dev;
3743 struct drm_i915_private *dev_priv = to_i915(dev);
3744 int pipe = crtc->pipe;
3745 i915_reg_t reg;
3746 u32 temp;
3747
3748 /* enable normal train */
3749 reg = FDI_TX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 if (IS_IVYBRIDGE(dev_priv)) {
3752 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3753 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3754 } else {
3755 temp &= ~FDI_LINK_TRAIN_NONE;
3756 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3757 }
3758 I915_WRITE(reg, temp);
3759
3760 reg = FDI_RX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 if (HAS_PCH_CPT(dev_priv)) {
3763 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3764 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3765 } else {
3766 temp &= ~FDI_LINK_TRAIN_NONE;
3767 temp |= FDI_LINK_TRAIN_NONE;
3768 }
3769 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3770
3771 /* wait one idle pattern time */
3772 POSTING_READ(reg);
3773 udelay(1000);
3774
3775 /* IVB wants error correction enabled */
3776 if (IS_IVYBRIDGE(dev_priv))
3777 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3778 FDI_FE_ERRC_ENABLE);
3779 }
3780
3781 /* The FDI link training functions for ILK/Ibexpeak. */
3782 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3783 const struct intel_crtc_state *crtc_state)
3784 {
3785 struct drm_device *dev = crtc->base.dev;
3786 struct drm_i915_private *dev_priv = to_i915(dev);
3787 int pipe = crtc->pipe;
3788 i915_reg_t reg;
3789 u32 temp, tries;
3790
3791 /* FDI needs bits from pipe first */
3792 assert_pipe_enabled(dev_priv, pipe);
3793
3794 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3795 for train result */
3796 reg = FDI_RX_IMR(pipe);
3797 temp = I915_READ(reg);
3798 temp &= ~FDI_RX_SYMBOL_LOCK;
3799 temp &= ~FDI_RX_BIT_LOCK;
3800 I915_WRITE(reg, temp);
3801 I915_READ(reg);
3802 udelay(150);
3803
3804 /* enable CPU FDI TX and PCH FDI RX */
3805 reg = FDI_TX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3808 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3809 temp &= ~FDI_LINK_TRAIN_NONE;
3810 temp |= FDI_LINK_TRAIN_PATTERN_1;
3811 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 temp &= ~FDI_LINK_TRAIN_NONE;
3816 temp |= FDI_LINK_TRAIN_PATTERN_1;
3817 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3818
3819 POSTING_READ(reg);
3820 udelay(150);
3821
3822 /* Ironlake workaround, enable clock pointer after FDI enable*/
3823 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3824 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3825 FDI_RX_PHASE_SYNC_POINTER_EN);
3826
3827 reg = FDI_RX_IIR(pipe);
3828 for (tries = 0; tries < 5; tries++) {
3829 temp = I915_READ(reg);
3830 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3831
3832 if ((temp & FDI_RX_BIT_LOCK)) {
3833 DRM_DEBUG_KMS("FDI train 1 done.\n");
3834 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3835 break;
3836 }
3837 }
3838 if (tries == 5)
3839 DRM_ERROR("FDI train 1 fail!\n");
3840
3841 /* Train 2 */
3842 reg = FDI_TX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 temp &= ~FDI_LINK_TRAIN_NONE;
3845 temp |= FDI_LINK_TRAIN_PATTERN_2;
3846 I915_WRITE(reg, temp);
3847
3848 reg = FDI_RX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_2;
3852 I915_WRITE(reg, temp);
3853
3854 POSTING_READ(reg);
3855 udelay(150);
3856
3857 reg = FDI_RX_IIR(pipe);
3858 for (tries = 0; tries < 5; tries++) {
3859 temp = I915_READ(reg);
3860 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3861
3862 if (temp & FDI_RX_SYMBOL_LOCK) {
3863 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3864 DRM_DEBUG_KMS("FDI train 2 done.\n");
3865 break;
3866 }
3867 }
3868 if (tries == 5)
3869 DRM_ERROR("FDI train 2 fail!\n");
3870
3871 DRM_DEBUG_KMS("FDI train done\n");
3872
3873 }
3874
3875 static const int snb_b_fdi_train_param[] = {
3876 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3877 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3878 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3879 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3880 };
3881
3882 /* The FDI link training functions for SNB/Cougarpoint. */
3883 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3884 const struct intel_crtc_state *crtc_state)
3885 {
3886 struct drm_device *dev = crtc->base.dev;
3887 struct drm_i915_private *dev_priv = to_i915(dev);
3888 int pipe = crtc->pipe;
3889 i915_reg_t reg;
3890 u32 temp, i, retry;
3891
3892 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3893 for train result */
3894 reg = FDI_RX_IMR(pipe);
3895 temp = I915_READ(reg);
3896 temp &= ~FDI_RX_SYMBOL_LOCK;
3897 temp &= ~FDI_RX_BIT_LOCK;
3898 I915_WRITE(reg, temp);
3899
3900 POSTING_READ(reg);
3901 udelay(150);
3902
3903 /* enable CPU FDI TX and PCH FDI RX */
3904 reg = FDI_TX_CTL(pipe);
3905 temp = I915_READ(reg);
3906 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3907 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3908 temp &= ~FDI_LINK_TRAIN_NONE;
3909 temp |= FDI_LINK_TRAIN_PATTERN_1;
3910 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3911 /* SNB-B */
3912 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3913 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3914
3915 I915_WRITE(FDI_RX_MISC(pipe),
3916 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3917
3918 reg = FDI_RX_CTL(pipe);
3919 temp = I915_READ(reg);
3920 if (HAS_PCH_CPT(dev_priv)) {
3921 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3922 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3923 } else {
3924 temp &= ~FDI_LINK_TRAIN_NONE;
3925 temp |= FDI_LINK_TRAIN_PATTERN_1;
3926 }
3927 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3928
3929 POSTING_READ(reg);
3930 udelay(150);
3931
3932 for (i = 0; i < 4; i++) {
3933 reg = FDI_TX_CTL(pipe);
3934 temp = I915_READ(reg);
3935 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3936 temp |= snb_b_fdi_train_param[i];
3937 I915_WRITE(reg, temp);
3938
3939 POSTING_READ(reg);
3940 udelay(500);
3941
3942 for (retry = 0; retry < 5; retry++) {
3943 reg = FDI_RX_IIR(pipe);
3944 temp = I915_READ(reg);
3945 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3946 if (temp & FDI_RX_BIT_LOCK) {
3947 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3948 DRM_DEBUG_KMS("FDI train 1 done.\n");
3949 break;
3950 }
3951 udelay(50);
3952 }
3953 if (retry < 5)
3954 break;
3955 }
3956 if (i == 4)
3957 DRM_ERROR("FDI train 1 fail!\n");
3958
3959 /* Train 2 */
3960 reg = FDI_TX_CTL(pipe);
3961 temp = I915_READ(reg);
3962 temp &= ~FDI_LINK_TRAIN_NONE;
3963 temp |= FDI_LINK_TRAIN_PATTERN_2;
3964 if (IS_GEN6(dev_priv)) {
3965 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3966 /* SNB-B */
3967 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3968 }
3969 I915_WRITE(reg, temp);
3970
3971 reg = FDI_RX_CTL(pipe);
3972 temp = I915_READ(reg);
3973 if (HAS_PCH_CPT(dev_priv)) {
3974 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3975 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3976 } else {
3977 temp &= ~FDI_LINK_TRAIN_NONE;
3978 temp |= FDI_LINK_TRAIN_PATTERN_2;
3979 }
3980 I915_WRITE(reg, temp);
3981
3982 POSTING_READ(reg);
3983 udelay(150);
3984
3985 for (i = 0; i < 4; i++) {
3986 reg = FDI_TX_CTL(pipe);
3987 temp = I915_READ(reg);
3988 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3989 temp |= snb_b_fdi_train_param[i];
3990 I915_WRITE(reg, temp);
3991
3992 POSTING_READ(reg);
3993 udelay(500);
3994
3995 for (retry = 0; retry < 5; retry++) {
3996 reg = FDI_RX_IIR(pipe);
3997 temp = I915_READ(reg);
3998 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3999 if (temp & FDI_RX_SYMBOL_LOCK) {
4000 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4001 DRM_DEBUG_KMS("FDI train 2 done.\n");
4002 break;
4003 }
4004 udelay(50);
4005 }
4006 if (retry < 5)
4007 break;
4008 }
4009 if (i == 4)
4010 DRM_ERROR("FDI train 2 fail!\n");
4011
4012 DRM_DEBUG_KMS("FDI train done.\n");
4013 }
4014
4015 /* Manual link training for Ivy Bridge A0 parts */
4016 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4017 const struct intel_crtc_state *crtc_state)
4018 {
4019 struct drm_device *dev = crtc->base.dev;
4020 struct drm_i915_private *dev_priv = to_i915(dev);
4021 int pipe = crtc->pipe;
4022 i915_reg_t reg;
4023 u32 temp, i, j;
4024
4025 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4026 for train result */
4027 reg = FDI_RX_IMR(pipe);
4028 temp = I915_READ(reg);
4029 temp &= ~FDI_RX_SYMBOL_LOCK;
4030 temp &= ~FDI_RX_BIT_LOCK;
4031 I915_WRITE(reg, temp);
4032
4033 POSTING_READ(reg);
4034 udelay(150);
4035
4036 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4037 I915_READ(FDI_RX_IIR(pipe)));
4038
4039 /* Try each vswing and preemphasis setting twice before moving on */
4040 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4041 /* disable first in case we need to retry */
4042 reg = FDI_TX_CTL(pipe);
4043 temp = I915_READ(reg);
4044 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4045 temp &= ~FDI_TX_ENABLE;
4046 I915_WRITE(reg, temp);
4047
4048 reg = FDI_RX_CTL(pipe);
4049 temp = I915_READ(reg);
4050 temp &= ~FDI_LINK_TRAIN_AUTO;
4051 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4052 temp &= ~FDI_RX_ENABLE;
4053 I915_WRITE(reg, temp);
4054
4055 /* enable CPU FDI TX and PCH FDI RX */
4056 reg = FDI_TX_CTL(pipe);
4057 temp = I915_READ(reg);
4058 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4059 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4060 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4061 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4062 temp |= snb_b_fdi_train_param[j/2];
4063 temp |= FDI_COMPOSITE_SYNC;
4064 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4065
4066 I915_WRITE(FDI_RX_MISC(pipe),
4067 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4068
4069 reg = FDI_RX_CTL(pipe);
4070 temp = I915_READ(reg);
4071 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4072 temp |= FDI_COMPOSITE_SYNC;
4073 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4074
4075 POSTING_READ(reg);
4076 udelay(1); /* should be 0.5us */
4077
4078 for (i = 0; i < 4; i++) {
4079 reg = FDI_RX_IIR(pipe);
4080 temp = I915_READ(reg);
4081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4082
4083 if (temp & FDI_RX_BIT_LOCK ||
4084 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4085 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4086 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4087 i);
4088 break;
4089 }
4090 udelay(1); /* should be 0.5us */
4091 }
4092 if (i == 4) {
4093 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4094 continue;
4095 }
4096
4097 /* Train 2 */
4098 reg = FDI_TX_CTL(pipe);
4099 temp = I915_READ(reg);
4100 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4101 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4102 I915_WRITE(reg, temp);
4103
4104 reg = FDI_RX_CTL(pipe);
4105 temp = I915_READ(reg);
4106 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4107 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4108 I915_WRITE(reg, temp);
4109
4110 POSTING_READ(reg);
4111 udelay(2); /* should be 1.5us */
4112
4113 for (i = 0; i < 4; i++) {
4114 reg = FDI_RX_IIR(pipe);
4115 temp = I915_READ(reg);
4116 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4117
4118 if (temp & FDI_RX_SYMBOL_LOCK ||
4119 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4120 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4121 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4122 i);
4123 goto train_done;
4124 }
4125 udelay(2); /* should be 1.5us */
4126 }
4127 if (i == 4)
4128 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4129 }
4130
4131 train_done:
4132 DRM_DEBUG_KMS("FDI train done.\n");
4133 }
4134
4135 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4136 {
4137 struct drm_device *dev = intel_crtc->base.dev;
4138 struct drm_i915_private *dev_priv = to_i915(dev);
4139 int pipe = intel_crtc->pipe;
4140 i915_reg_t reg;
4141 u32 temp;
4142
4143 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4144 reg = FDI_RX_CTL(pipe);
4145 temp = I915_READ(reg);
4146 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4147 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4148 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4149 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4150
4151 POSTING_READ(reg);
4152 udelay(200);
4153
4154 /* Switch from Rawclk to PCDclk */
4155 temp = I915_READ(reg);
4156 I915_WRITE(reg, temp | FDI_PCDCLK);
4157
4158 POSTING_READ(reg);
4159 udelay(200);
4160
4161 /* Enable CPU FDI TX PLL, always on for Ironlake */
4162 reg = FDI_TX_CTL(pipe);
4163 temp = I915_READ(reg);
4164 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4165 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4166
4167 POSTING_READ(reg);
4168 udelay(100);
4169 }
4170 }
4171
4172 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4173 {
4174 struct drm_device *dev = intel_crtc->base.dev;
4175 struct drm_i915_private *dev_priv = to_i915(dev);
4176 int pipe = intel_crtc->pipe;
4177 i915_reg_t reg;
4178 u32 temp;
4179
4180 /* Switch from PCDclk to Rawclk */
4181 reg = FDI_RX_CTL(pipe);
4182 temp = I915_READ(reg);
4183 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4184
4185 /* Disable CPU FDI TX PLL */
4186 reg = FDI_TX_CTL(pipe);
4187 temp = I915_READ(reg);
4188 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4189
4190 POSTING_READ(reg);
4191 udelay(100);
4192
4193 reg = FDI_RX_CTL(pipe);
4194 temp = I915_READ(reg);
4195 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4196
4197 /* Wait for the clocks to turn off. */
4198 POSTING_READ(reg);
4199 udelay(100);
4200 }
4201
4202 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4203 {
4204 struct drm_device *dev = crtc->dev;
4205 struct drm_i915_private *dev_priv = to_i915(dev);
4206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207 int pipe = intel_crtc->pipe;
4208 i915_reg_t reg;
4209 u32 temp;
4210
4211 /* disable CPU FDI tx and PCH FDI rx */
4212 reg = FDI_TX_CTL(pipe);
4213 temp = I915_READ(reg);
4214 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4215 POSTING_READ(reg);
4216
4217 reg = FDI_RX_CTL(pipe);
4218 temp = I915_READ(reg);
4219 temp &= ~(0x7 << 16);
4220 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4221 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4222
4223 POSTING_READ(reg);
4224 udelay(100);
4225
4226 /* Ironlake workaround, disable clock pointer after downing FDI */
4227 if (HAS_PCH_IBX(dev_priv))
4228 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4229
4230 /* still set train pattern 1 */
4231 reg = FDI_TX_CTL(pipe);
4232 temp = I915_READ(reg);
4233 temp &= ~FDI_LINK_TRAIN_NONE;
4234 temp |= FDI_LINK_TRAIN_PATTERN_1;
4235 I915_WRITE(reg, temp);
4236
4237 reg = FDI_RX_CTL(pipe);
4238 temp = I915_READ(reg);
4239 if (HAS_PCH_CPT(dev_priv)) {
4240 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4241 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4242 } else {
4243 temp &= ~FDI_LINK_TRAIN_NONE;
4244 temp |= FDI_LINK_TRAIN_PATTERN_1;
4245 }
4246 /* BPC in FDI rx is consistent with that in PIPECONF */
4247 temp &= ~(0x07 << 16);
4248 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4249 I915_WRITE(reg, temp);
4250
4251 POSTING_READ(reg);
4252 udelay(100);
4253 }
4254
4255 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4256 {
4257 struct drm_crtc *crtc;
4258 bool cleanup_done;
4259
4260 drm_for_each_crtc(crtc, &dev_priv->drm) {
4261 struct drm_crtc_commit *commit;
4262 spin_lock(&crtc->commit_lock);
4263 commit = list_first_entry_or_null(&crtc->commit_list,
4264 struct drm_crtc_commit, commit_entry);
4265 cleanup_done = commit ?
4266 try_wait_for_completion(&commit->cleanup_done) : true;
4267 spin_unlock(&crtc->commit_lock);
4268
4269 if (cleanup_done)
4270 continue;
4271
4272 drm_crtc_wait_one_vblank(crtc);
4273
4274 return true;
4275 }
4276
4277 return false;
4278 }
4279
4280 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4281 {
4282 u32 temp;
4283
4284 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4285
4286 mutex_lock(&dev_priv->sb_lock);
4287
4288 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4289 temp |= SBI_SSCCTL_DISABLE;
4290 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4291
4292 mutex_unlock(&dev_priv->sb_lock);
4293 }
4294
4295 /* Program iCLKIP clock to the desired frequency */
4296 static void lpt_program_iclkip(struct intel_crtc *crtc)
4297 {
4298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4299 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4300 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4301 u32 temp;
4302
4303 lpt_disable_iclkip(dev_priv);
4304
4305 /* The iCLK virtual clock root frequency is in MHz,
4306 * but the adjusted_mode->crtc_clock in in KHz. To get the
4307 * divisors, it is necessary to divide one by another, so we
4308 * convert the virtual clock precision to KHz here for higher
4309 * precision.
4310 */
4311 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4312 u32 iclk_virtual_root_freq = 172800 * 1000;
4313 u32 iclk_pi_range = 64;
4314 u32 desired_divisor;
4315
4316 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4317 clock << auxdiv);
4318 divsel = (desired_divisor / iclk_pi_range) - 2;
4319 phaseinc = desired_divisor % iclk_pi_range;
4320
4321 /*
4322 * Near 20MHz is a corner case which is
4323 * out of range for the 7-bit divisor
4324 */
4325 if (divsel <= 0x7f)
4326 break;
4327 }
4328
4329 /* This should not happen with any sane values */
4330 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4331 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4332 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4333 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4334
4335 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4336 clock,
4337 auxdiv,
4338 divsel,
4339 phasedir,
4340 phaseinc);
4341
4342 mutex_lock(&dev_priv->sb_lock);
4343
4344 /* Program SSCDIVINTPHASE6 */
4345 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4346 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4347 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4348 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4349 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4350 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4351 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4352 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4353
4354 /* Program SSCAUXDIV */
4355 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4356 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4357 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4358 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4359
4360 /* Enable modulator and associated divider */
4361 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4362 temp &= ~SBI_SSCCTL_DISABLE;
4363 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4364
4365 mutex_unlock(&dev_priv->sb_lock);
4366
4367 /* Wait for initialization time */
4368 udelay(24);
4369
4370 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4371 }
4372
4373 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4374 {
4375 u32 divsel, phaseinc, auxdiv;
4376 u32 iclk_virtual_root_freq = 172800 * 1000;
4377 u32 iclk_pi_range = 64;
4378 u32 desired_divisor;
4379 u32 temp;
4380
4381 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4382 return 0;
4383
4384 mutex_lock(&dev_priv->sb_lock);
4385
4386 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4387 if (temp & SBI_SSCCTL_DISABLE) {
4388 mutex_unlock(&dev_priv->sb_lock);
4389 return 0;
4390 }
4391
4392 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4393 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4394 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4395 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4396 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4397
4398 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4399 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4400 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4401
4402 mutex_unlock(&dev_priv->sb_lock);
4403
4404 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4405
4406 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4407 desired_divisor << auxdiv);
4408 }
4409
4410 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4411 enum pipe pch_transcoder)
4412 {
4413 struct drm_device *dev = crtc->base.dev;
4414 struct drm_i915_private *dev_priv = to_i915(dev);
4415 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4416
4417 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4418 I915_READ(HTOTAL(cpu_transcoder)));
4419 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4420 I915_READ(HBLANK(cpu_transcoder)));
4421 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4422 I915_READ(HSYNC(cpu_transcoder)));
4423
4424 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4425 I915_READ(VTOTAL(cpu_transcoder)));
4426 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4427 I915_READ(VBLANK(cpu_transcoder)));
4428 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4429 I915_READ(VSYNC(cpu_transcoder)));
4430 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4431 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4432 }
4433
4434 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4435 {
4436 struct drm_i915_private *dev_priv = to_i915(dev);
4437 uint32_t temp;
4438
4439 temp = I915_READ(SOUTH_CHICKEN1);
4440 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4441 return;
4442
4443 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4444 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4445
4446 temp &= ~FDI_BC_BIFURCATION_SELECT;
4447 if (enable)
4448 temp |= FDI_BC_BIFURCATION_SELECT;
4449
4450 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4451 I915_WRITE(SOUTH_CHICKEN1, temp);
4452 POSTING_READ(SOUTH_CHICKEN1);
4453 }
4454
4455 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4456 {
4457 struct drm_device *dev = intel_crtc->base.dev;
4458
4459 switch (intel_crtc->pipe) {
4460 case PIPE_A:
4461 break;
4462 case PIPE_B:
4463 if (intel_crtc->config->fdi_lanes > 2)
4464 cpt_set_fdi_bc_bifurcation(dev, false);
4465 else
4466 cpt_set_fdi_bc_bifurcation(dev, true);
4467
4468 break;
4469 case PIPE_C:
4470 cpt_set_fdi_bc_bifurcation(dev, true);
4471
4472 break;
4473 default:
4474 BUG();
4475 }
4476 }
4477
4478 /* Return which DP Port should be selected for Transcoder DP control */
4479 static enum port
4480 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4481 {
4482 struct drm_device *dev = crtc->base.dev;
4483 struct intel_encoder *encoder;
4484
4485 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4486 if (encoder->type == INTEL_OUTPUT_DP ||
4487 encoder->type == INTEL_OUTPUT_EDP)
4488 return enc_to_dig_port(&encoder->base)->port;
4489 }
4490
4491 return -1;
4492 }
4493
4494 /*
4495 * Enable PCH resources required for PCH ports:
4496 * - PCH PLLs
4497 * - FDI training & RX/TX
4498 * - update transcoder timings
4499 * - DP transcoding bits
4500 * - transcoder
4501 */
4502 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4503 {
4504 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4505 struct drm_device *dev = crtc->base.dev;
4506 struct drm_i915_private *dev_priv = to_i915(dev);
4507 int pipe = crtc->pipe;
4508 u32 temp;
4509
4510 assert_pch_transcoder_disabled(dev_priv, pipe);
4511
4512 if (IS_IVYBRIDGE(dev_priv))
4513 ivybridge_update_fdi_bc_bifurcation(crtc);
4514
4515 /* Write the TU size bits before fdi link training, so that error
4516 * detection works. */
4517 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4518 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4519
4520 /* For PCH output, training FDI link */
4521 dev_priv->display.fdi_link_train(crtc, crtc_state);
4522
4523 /* We need to program the right clock selection before writing the pixel
4524 * mutliplier into the DPLL. */
4525 if (HAS_PCH_CPT(dev_priv)) {
4526 u32 sel;
4527
4528 temp = I915_READ(PCH_DPLL_SEL);
4529 temp |= TRANS_DPLL_ENABLE(pipe);
4530 sel = TRANS_DPLLB_SEL(pipe);
4531 if (crtc_state->shared_dpll ==
4532 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4533 temp |= sel;
4534 else
4535 temp &= ~sel;
4536 I915_WRITE(PCH_DPLL_SEL, temp);
4537 }
4538
4539 /* XXX: pch pll's can be enabled any time before we enable the PCH
4540 * transcoder, and we actually should do this to not upset any PCH
4541 * transcoder that already use the clock when we share it.
4542 *
4543 * Note that enable_shared_dpll tries to do the right thing, but
4544 * get_shared_dpll unconditionally resets the pll - we need that to have
4545 * the right LVDS enable sequence. */
4546 intel_enable_shared_dpll(crtc);
4547
4548 /* set transcoder timing, panel must allow it */
4549 assert_panel_unlocked(dev_priv, pipe);
4550 ironlake_pch_transcoder_set_timings(crtc, pipe);
4551
4552 intel_fdi_normal_train(crtc);
4553
4554 /* For PCH DP, enable TRANS_DP_CTL */
4555 if (HAS_PCH_CPT(dev_priv) &&
4556 intel_crtc_has_dp_encoder(crtc_state)) {
4557 const struct drm_display_mode *adjusted_mode =
4558 &crtc_state->base.adjusted_mode;
4559 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4560 i915_reg_t reg = TRANS_DP_CTL(pipe);
4561 temp = I915_READ(reg);
4562 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4563 TRANS_DP_SYNC_MASK |
4564 TRANS_DP_BPC_MASK);
4565 temp |= TRANS_DP_OUTPUT_ENABLE;
4566 temp |= bpc << 9; /* same format but at 11:9 */
4567
4568 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4569 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4570 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4571 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4572
4573 switch (intel_trans_dp_port_sel(crtc)) {
4574 case PORT_B:
4575 temp |= TRANS_DP_PORT_SEL_B;
4576 break;
4577 case PORT_C:
4578 temp |= TRANS_DP_PORT_SEL_C;
4579 break;
4580 case PORT_D:
4581 temp |= TRANS_DP_PORT_SEL_D;
4582 break;
4583 default:
4584 BUG();
4585 }
4586
4587 I915_WRITE(reg, temp);
4588 }
4589
4590 ironlake_enable_pch_transcoder(dev_priv, pipe);
4591 }
4592
4593 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4594 {
4595 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4597 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4598
4599 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4600
4601 lpt_program_iclkip(crtc);
4602
4603 /* Set transcoder timing. */
4604 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4605
4606 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4607 }
4608
4609 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4610 {
4611 struct drm_i915_private *dev_priv = to_i915(dev);
4612 i915_reg_t dslreg = PIPEDSL(pipe);
4613 u32 temp;
4614
4615 temp = I915_READ(dslreg);
4616 udelay(500);
4617 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4618 if (wait_for(I915_READ(dslreg) != temp, 5))
4619 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4620 }
4621 }
4622
4623 static int
4624 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4625 unsigned int scaler_user, int *scaler_id,
4626 int src_w, int src_h, int dst_w, int dst_h)
4627 {
4628 struct intel_crtc_scaler_state *scaler_state =
4629 &crtc_state->scaler_state;
4630 struct intel_crtc *intel_crtc =
4631 to_intel_crtc(crtc_state->base.crtc);
4632 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4633 const struct drm_display_mode *adjusted_mode =
4634 &crtc_state->base.adjusted_mode;
4635 int need_scaling;
4636
4637 /*
4638 * Src coordinates are already rotated by 270 degrees for
4639 * the 90/270 degree plane rotation cases (to match the
4640 * GTT mapping), hence no need to account for rotation here.
4641 */
4642 need_scaling = src_w != dst_w || src_h != dst_h;
4643
4644 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4645 need_scaling = true;
4646
4647 /*
4648 * Scaling/fitting not supported in IF-ID mode in GEN9+
4649 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4650 * Once NV12 is enabled, handle it here while allocating scaler
4651 * for NV12.
4652 */
4653 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4654 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4655 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4656 return -EINVAL;
4657 }
4658
4659 /*
4660 * if plane is being disabled or scaler is no more required or force detach
4661 * - free scaler binded to this plane/crtc
4662 * - in order to do this, update crtc->scaler_usage
4663 *
4664 * Here scaler state in crtc_state is set free so that
4665 * scaler can be assigned to other user. Actual register
4666 * update to free the scaler is done in plane/panel-fit programming.
4667 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4668 */
4669 if (force_detach || !need_scaling) {
4670 if (*scaler_id >= 0) {
4671 scaler_state->scaler_users &= ~(1 << scaler_user);
4672 scaler_state->scalers[*scaler_id].in_use = 0;
4673
4674 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4675 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4676 intel_crtc->pipe, scaler_user, *scaler_id,
4677 scaler_state->scaler_users);
4678 *scaler_id = -1;
4679 }
4680 return 0;
4681 }
4682
4683 /* range checks */
4684 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4685 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4686
4687 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4688 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4689 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4690 "size is out of scaler range\n",
4691 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4692 return -EINVAL;
4693 }
4694
4695 /* mark this plane as a scaler user in crtc_state */
4696 scaler_state->scaler_users |= (1 << scaler_user);
4697 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4698 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4699 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4700 scaler_state->scaler_users);
4701
4702 return 0;
4703 }
4704
4705 /**
4706 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4707 *
4708 * @state: crtc's scaler state
4709 *
4710 * Return
4711 * 0 - scaler_usage updated successfully
4712 * error - requested scaling cannot be supported or other error condition
4713 */
4714 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4715 {
4716 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4717
4718 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4719 &state->scaler_state.scaler_id,
4720 state->pipe_src_w, state->pipe_src_h,
4721 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4722 }
4723
4724 /**
4725 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4726 *
4727 * @state: crtc's scaler state
4728 * @plane_state: atomic plane state to update
4729 *
4730 * Return
4731 * 0 - scaler_usage updated successfully
4732 * error - requested scaling cannot be supported or other error condition
4733 */
4734 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4735 struct intel_plane_state *plane_state)
4736 {
4737
4738 struct intel_plane *intel_plane =
4739 to_intel_plane(plane_state->base.plane);
4740 struct drm_framebuffer *fb = plane_state->base.fb;
4741 int ret;
4742
4743 bool force_detach = !fb || !plane_state->base.visible;
4744
4745 ret = skl_update_scaler(crtc_state, force_detach,
4746 drm_plane_index(&intel_plane->base),
4747 &plane_state->scaler_id,
4748 drm_rect_width(&plane_state->base.src) >> 16,
4749 drm_rect_height(&plane_state->base.src) >> 16,
4750 drm_rect_width(&plane_state->base.dst),
4751 drm_rect_height(&plane_state->base.dst));
4752
4753 if (ret || plane_state->scaler_id < 0)
4754 return ret;
4755
4756 /* check colorkey */
4757 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4758 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4759 intel_plane->base.base.id,
4760 intel_plane->base.name);
4761 return -EINVAL;
4762 }
4763
4764 /* Check src format */
4765 switch (fb->format->format) {
4766 case DRM_FORMAT_RGB565:
4767 case DRM_FORMAT_XBGR8888:
4768 case DRM_FORMAT_XRGB8888:
4769 case DRM_FORMAT_ABGR8888:
4770 case DRM_FORMAT_ARGB8888:
4771 case DRM_FORMAT_XRGB2101010:
4772 case DRM_FORMAT_XBGR2101010:
4773 case DRM_FORMAT_YUYV:
4774 case DRM_FORMAT_YVYU:
4775 case DRM_FORMAT_UYVY:
4776 case DRM_FORMAT_VYUY:
4777 break;
4778 default:
4779 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4780 intel_plane->base.base.id, intel_plane->base.name,
4781 fb->base.id, fb->format->format);
4782 return -EINVAL;
4783 }
4784
4785 return 0;
4786 }
4787
4788 static void skylake_scaler_disable(struct intel_crtc *crtc)
4789 {
4790 int i;
4791
4792 for (i = 0; i < crtc->num_scalers; i++)
4793 skl_detach_scaler(crtc, i);
4794 }
4795
4796 static void skylake_pfit_enable(struct intel_crtc *crtc)
4797 {
4798 struct drm_device *dev = crtc->base.dev;
4799 struct drm_i915_private *dev_priv = to_i915(dev);
4800 int pipe = crtc->pipe;
4801 struct intel_crtc_scaler_state *scaler_state =
4802 &crtc->config->scaler_state;
4803
4804 if (crtc->config->pch_pfit.enabled) {
4805 int id;
4806
4807 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4808 return;
4809
4810 id = scaler_state->scaler_id;
4811 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4812 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4813 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4814 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4815 }
4816 }
4817
4818 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4819 {
4820 struct drm_device *dev = crtc->base.dev;
4821 struct drm_i915_private *dev_priv = to_i915(dev);
4822 int pipe = crtc->pipe;
4823
4824 if (crtc->config->pch_pfit.enabled) {
4825 /* Force use of hard-coded filter coefficients
4826 * as some pre-programmed values are broken,
4827 * e.g. x201.
4828 */
4829 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4830 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4831 PF_PIPE_SEL_IVB(pipe));
4832 else
4833 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4834 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4835 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4836 }
4837 }
4838
4839 void hsw_enable_ips(struct intel_crtc *crtc)
4840 {
4841 struct drm_device *dev = crtc->base.dev;
4842 struct drm_i915_private *dev_priv = to_i915(dev);
4843
4844 if (!crtc->config->ips_enabled)
4845 return;
4846
4847 /*
4848 * We can only enable IPS after we enable a plane and wait for a vblank
4849 * This function is called from post_plane_update, which is run after
4850 * a vblank wait.
4851 */
4852
4853 assert_plane_enabled(to_intel_plane(crtc->base.primary));
4854
4855 if (IS_BROADWELL(dev_priv)) {
4856 mutex_lock(&dev_priv->pcu_lock);
4857 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4858 IPS_ENABLE | IPS_PCODE_CONTROL));
4859 mutex_unlock(&dev_priv->pcu_lock);
4860 /* Quoting Art Runyan: "its not safe to expect any particular
4861 * value in IPS_CTL bit 31 after enabling IPS through the
4862 * mailbox." Moreover, the mailbox may return a bogus state,
4863 * so we need to just enable it and continue on.
4864 */
4865 } else {
4866 I915_WRITE(IPS_CTL, IPS_ENABLE);
4867 /* The bit only becomes 1 in the next vblank, so this wait here
4868 * is essentially intel_wait_for_vblank. If we don't have this
4869 * and don't wait for vblanks until the end of crtc_enable, then
4870 * the HW state readout code will complain that the expected
4871 * IPS_CTL value is not the one we read. */
4872 if (intel_wait_for_register(dev_priv,
4873 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4874 50))
4875 DRM_ERROR("Timed out waiting for IPS enable\n");
4876 }
4877 }
4878
4879 void hsw_disable_ips(struct intel_crtc *crtc)
4880 {
4881 struct drm_device *dev = crtc->base.dev;
4882 struct drm_i915_private *dev_priv = to_i915(dev);
4883
4884 if (!crtc->config->ips_enabled)
4885 return;
4886
4887 assert_plane_enabled(to_intel_plane(crtc->base.primary));
4888
4889 if (IS_BROADWELL(dev_priv)) {
4890 mutex_lock(&dev_priv->pcu_lock);
4891 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4892 mutex_unlock(&dev_priv->pcu_lock);
4893 /*
4894 * Wait for PCODE to finish disabling IPS. The BSpec specified
4895 * 42ms timeout value leads to occasional timeouts so use 100ms
4896 * instead.
4897 */
4898 if (intel_wait_for_register(dev_priv,
4899 IPS_CTL, IPS_ENABLE, 0,
4900 100))
4901 DRM_ERROR("Timed out waiting for IPS disable\n");
4902 } else {
4903 I915_WRITE(IPS_CTL, 0);
4904 POSTING_READ(IPS_CTL);
4905 }
4906
4907 /* We need to wait for a vblank before we can disable the plane. */
4908 intel_wait_for_vblank(dev_priv, crtc->pipe);
4909 }
4910
4911 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4912 {
4913 if (intel_crtc->overlay) {
4914 struct drm_device *dev = intel_crtc->base.dev;
4915
4916 mutex_lock(&dev->struct_mutex);
4917 (void) intel_overlay_switch_off(intel_crtc->overlay);
4918 mutex_unlock(&dev->struct_mutex);
4919 }
4920
4921 /* Let userspace switch the overlay on again. In most cases userspace
4922 * has to recompute where to put it anyway.
4923 */
4924 }
4925
4926 /**
4927 * intel_post_enable_primary - Perform operations after enabling primary plane
4928 * @crtc: the CRTC whose primary plane was just enabled
4929 *
4930 * Performs potentially sleeping operations that must be done after the primary
4931 * plane is enabled, such as updating FBC and IPS. Note that this may be
4932 * called due to an explicit primary plane update, or due to an implicit
4933 * re-enable that is caused when a sprite plane is updated to no longer
4934 * completely hide the primary plane.
4935 */
4936 static void
4937 intel_post_enable_primary(struct drm_crtc *crtc)
4938 {
4939 struct drm_device *dev = crtc->dev;
4940 struct drm_i915_private *dev_priv = to_i915(dev);
4941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942 int pipe = intel_crtc->pipe;
4943
4944 /*
4945 * FIXME IPS should be fine as long as one plane is
4946 * enabled, but in practice it seems to have problems
4947 * when going from primary only to sprite only and vice
4948 * versa.
4949 */
4950 hsw_enable_ips(intel_crtc);
4951
4952 /*
4953 * Gen2 reports pipe underruns whenever all planes are disabled.
4954 * So don't enable underrun reporting before at least some planes
4955 * are enabled.
4956 * FIXME: Need to fix the logic to work when we turn off all planes
4957 * but leave the pipe running.
4958 */
4959 if (IS_GEN2(dev_priv))
4960 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4961
4962 /* Underruns don't always raise interrupts, so check manually. */
4963 intel_check_cpu_fifo_underruns(dev_priv);
4964 intel_check_pch_fifo_underruns(dev_priv);
4965 }
4966
4967 /* FIXME move all this to pre_plane_update() with proper state tracking */
4968 static void
4969 intel_pre_disable_primary(struct drm_crtc *crtc)
4970 {
4971 struct drm_device *dev = crtc->dev;
4972 struct drm_i915_private *dev_priv = to_i915(dev);
4973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974 int pipe = intel_crtc->pipe;
4975
4976 /*
4977 * Gen2 reports pipe underruns whenever all planes are disabled.
4978 * So diasble underrun reporting before all the planes get disabled.
4979 * FIXME: Need to fix the logic to work when we turn off all planes
4980 * but leave the pipe running.
4981 */
4982 if (IS_GEN2(dev_priv))
4983 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4984
4985 /*
4986 * FIXME IPS should be fine as long as one plane is
4987 * enabled, but in practice it seems to have problems
4988 * when going from primary only to sprite only and vice
4989 * versa.
4990 */
4991 hsw_disable_ips(intel_crtc);
4992 }
4993
4994 /* FIXME get rid of this and use pre_plane_update */
4995 static void
4996 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4997 {
4998 struct drm_device *dev = crtc->dev;
4999 struct drm_i915_private *dev_priv = to_i915(dev);
5000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5001 int pipe = intel_crtc->pipe;
5002
5003 intel_pre_disable_primary(crtc);
5004
5005 /*
5006 * Vblank time updates from the shadow to live plane control register
5007 * are blocked if the memory self-refresh mode is active at that
5008 * moment. So to make sure the plane gets truly disabled, disable
5009 * first the self-refresh mode. The self-refresh enable bit in turn
5010 * will be checked/applied by the HW only at the next frame start
5011 * event which is after the vblank start event, so we need to have a
5012 * wait-for-vblank between disabling the plane and the pipe.
5013 */
5014 if (HAS_GMCH_DISPLAY(dev_priv) &&
5015 intel_set_memory_cxsr(dev_priv, false))
5016 intel_wait_for_vblank(dev_priv, pipe);
5017 }
5018
5019 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5020 {
5021 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5022 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5023 struct intel_crtc_state *pipe_config =
5024 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5025 crtc);
5026 struct drm_plane *primary = crtc->base.primary;
5027 struct drm_plane_state *old_pri_state =
5028 drm_atomic_get_existing_plane_state(old_state, primary);
5029
5030 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5031
5032 if (pipe_config->update_wm_post && pipe_config->base.active)
5033 intel_update_watermarks(crtc);
5034
5035 if (old_pri_state) {
5036 struct intel_plane_state *primary_state =
5037 intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5038 to_intel_plane(primary));
5039 struct intel_plane_state *old_primary_state =
5040 to_intel_plane_state(old_pri_state);
5041
5042 intel_fbc_post_update(crtc);
5043
5044 if (primary_state->base.visible &&
5045 (needs_modeset(&pipe_config->base) ||
5046 !old_primary_state->base.visible))
5047 intel_post_enable_primary(&crtc->base);
5048 }
5049 }
5050
5051 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5052 struct intel_crtc_state *pipe_config)
5053 {
5054 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5055 struct drm_device *dev = crtc->base.dev;
5056 struct drm_i915_private *dev_priv = to_i915(dev);
5057 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5058 struct drm_plane *primary = crtc->base.primary;
5059 struct drm_plane_state *old_pri_state =
5060 drm_atomic_get_existing_plane_state(old_state, primary);
5061 bool modeset = needs_modeset(&pipe_config->base);
5062 struct intel_atomic_state *old_intel_state =
5063 to_intel_atomic_state(old_state);
5064
5065 if (old_pri_state) {
5066 struct intel_plane_state *primary_state =
5067 intel_atomic_get_new_plane_state(old_intel_state,
5068 to_intel_plane(primary));
5069 struct intel_plane_state *old_primary_state =
5070 to_intel_plane_state(old_pri_state);
5071
5072 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5073
5074 if (old_primary_state->base.visible &&
5075 (modeset || !primary_state->base.visible))
5076 intel_pre_disable_primary(&crtc->base);
5077 }
5078
5079 /*
5080 * Vblank time updates from the shadow to live plane control register
5081 * are blocked if the memory self-refresh mode is active at that
5082 * moment. So to make sure the plane gets truly disabled, disable
5083 * first the self-refresh mode. The self-refresh enable bit in turn
5084 * will be checked/applied by the HW only at the next frame start
5085 * event which is after the vblank start event, so we need to have a
5086 * wait-for-vblank between disabling the plane and the pipe.
5087 */
5088 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5089 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5090 intel_wait_for_vblank(dev_priv, crtc->pipe);
5091
5092 /*
5093 * IVB workaround: must disable low power watermarks for at least
5094 * one frame before enabling scaling. LP watermarks can be re-enabled
5095 * when scaling is disabled.
5096 *
5097 * WaCxSRDisabledForSpriteScaling:ivb
5098 */
5099 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5100 intel_wait_for_vblank(dev_priv, crtc->pipe);
5101
5102 /*
5103 * If we're doing a modeset, we're done. No need to do any pre-vblank
5104 * watermark programming here.
5105 */
5106 if (needs_modeset(&pipe_config->base))
5107 return;
5108
5109 /*
5110 * For platforms that support atomic watermarks, program the
5111 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5112 * will be the intermediate values that are safe for both pre- and
5113 * post- vblank; when vblank happens, the 'active' values will be set
5114 * to the final 'target' values and we'll do this again to get the
5115 * optimal watermarks. For gen9+ platforms, the values we program here
5116 * will be the final target values which will get automatically latched
5117 * at vblank time; no further programming will be necessary.
5118 *
5119 * If a platform hasn't been transitioned to atomic watermarks yet,
5120 * we'll continue to update watermarks the old way, if flags tell
5121 * us to.
5122 */
5123 if (dev_priv->display.initial_watermarks != NULL)
5124 dev_priv->display.initial_watermarks(old_intel_state,
5125 pipe_config);
5126 else if (pipe_config->update_wm_pre)
5127 intel_update_watermarks(crtc);
5128 }
5129
5130 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5131 {
5132 struct drm_device *dev = crtc->dev;
5133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5134 struct drm_plane *p;
5135 int pipe = intel_crtc->pipe;
5136
5137 intel_crtc_dpms_overlay_disable(intel_crtc);
5138
5139 drm_for_each_plane_mask(p, dev, plane_mask)
5140 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5141
5142 /*
5143 * FIXME: Once we grow proper nuclear flip support out of this we need
5144 * to compute the mask of flip planes precisely. For the time being
5145 * consider this a flip to a NULL plane.
5146 */
5147 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5148 }
5149
5150 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5151 struct intel_crtc_state *crtc_state,
5152 struct drm_atomic_state *old_state)
5153 {
5154 struct drm_connector_state *conn_state;
5155 struct drm_connector *conn;
5156 int i;
5157
5158 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5159 struct intel_encoder *encoder =
5160 to_intel_encoder(conn_state->best_encoder);
5161
5162 if (conn_state->crtc != crtc)
5163 continue;
5164
5165 if (encoder->pre_pll_enable)
5166 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5167 }
5168 }
5169
5170 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5171 struct intel_crtc_state *crtc_state,
5172 struct drm_atomic_state *old_state)
5173 {
5174 struct drm_connector_state *conn_state;
5175 struct drm_connector *conn;
5176 int i;
5177
5178 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5179 struct intel_encoder *encoder =
5180 to_intel_encoder(conn_state->best_encoder);
5181
5182 if (conn_state->crtc != crtc)
5183 continue;
5184
5185 if (encoder->pre_enable)
5186 encoder->pre_enable(encoder, crtc_state, conn_state);
5187 }
5188 }
5189
5190 static void intel_encoders_enable(struct drm_crtc *crtc,
5191 struct intel_crtc_state *crtc_state,
5192 struct drm_atomic_state *old_state)
5193 {
5194 struct drm_connector_state *conn_state;
5195 struct drm_connector *conn;
5196 int i;
5197
5198 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5199 struct intel_encoder *encoder =
5200 to_intel_encoder(conn_state->best_encoder);
5201
5202 if (conn_state->crtc != crtc)
5203 continue;
5204
5205 encoder->enable(encoder, crtc_state, conn_state);
5206 intel_opregion_notify_encoder(encoder, true);
5207 }
5208 }
5209
5210 static void intel_encoders_disable(struct drm_crtc *crtc,
5211 struct intel_crtc_state *old_crtc_state,
5212 struct drm_atomic_state *old_state)
5213 {
5214 struct drm_connector_state *old_conn_state;
5215 struct drm_connector *conn;
5216 int i;
5217
5218 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5219 struct intel_encoder *encoder =
5220 to_intel_encoder(old_conn_state->best_encoder);
5221
5222 if (old_conn_state->crtc != crtc)
5223 continue;
5224
5225 intel_opregion_notify_encoder(encoder, false);
5226 encoder->disable(encoder, old_crtc_state, old_conn_state);
5227 }
5228 }
5229
5230 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5231 struct intel_crtc_state *old_crtc_state,
5232 struct drm_atomic_state *old_state)
5233 {
5234 struct drm_connector_state *old_conn_state;
5235 struct drm_connector *conn;
5236 int i;
5237
5238 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5239 struct intel_encoder *encoder =
5240 to_intel_encoder(old_conn_state->best_encoder);
5241
5242 if (old_conn_state->crtc != crtc)
5243 continue;
5244
5245 if (encoder->post_disable)
5246 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5247 }
5248 }
5249
5250 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5251 struct intel_crtc_state *old_crtc_state,
5252 struct drm_atomic_state *old_state)
5253 {
5254 struct drm_connector_state *old_conn_state;
5255 struct drm_connector *conn;
5256 int i;
5257
5258 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5259 struct intel_encoder *encoder =
5260 to_intel_encoder(old_conn_state->best_encoder);
5261
5262 if (old_conn_state->crtc != crtc)
5263 continue;
5264
5265 if (encoder->post_pll_disable)
5266 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5267 }
5268 }
5269
5270 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5271 struct drm_atomic_state *old_state)
5272 {
5273 struct drm_crtc *crtc = pipe_config->base.crtc;
5274 struct drm_device *dev = crtc->dev;
5275 struct drm_i915_private *dev_priv = to_i915(dev);
5276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5277 int pipe = intel_crtc->pipe;
5278 struct intel_atomic_state *old_intel_state =
5279 to_intel_atomic_state(old_state);
5280
5281 if (WARN_ON(intel_crtc->active))
5282 return;
5283
5284 /*
5285 * Sometimes spurious CPU pipe underruns happen during FDI
5286 * training, at least with VGA+HDMI cloning. Suppress them.
5287 *
5288 * On ILK we get an occasional spurious CPU pipe underruns
5289 * between eDP port A enable and vdd enable. Also PCH port
5290 * enable seems to result in the occasional CPU pipe underrun.
5291 *
5292 * Spurious PCH underruns also occur during PCH enabling.
5293 */
5294 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5295 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5296 if (intel_crtc->config->has_pch_encoder)
5297 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5298
5299 if (intel_crtc->config->has_pch_encoder)
5300 intel_prepare_shared_dpll(intel_crtc);
5301
5302 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5303 intel_dp_set_m_n(intel_crtc, M1_N1);
5304
5305 intel_set_pipe_timings(intel_crtc);
5306 intel_set_pipe_src_size(intel_crtc);
5307
5308 if (intel_crtc->config->has_pch_encoder) {
5309 intel_cpu_transcoder_set_m_n(intel_crtc,
5310 &intel_crtc->config->fdi_m_n, NULL);
5311 }
5312
5313 ironlake_set_pipeconf(crtc);
5314
5315 intel_crtc->active = true;
5316
5317 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5318
5319 if (intel_crtc->config->has_pch_encoder) {
5320 /* Note: FDI PLL enabling _must_ be done before we enable the
5321 * cpu pipes, hence this is separate from all the other fdi/pch
5322 * enabling. */
5323 ironlake_fdi_pll_enable(intel_crtc);
5324 } else {
5325 assert_fdi_tx_disabled(dev_priv, pipe);
5326 assert_fdi_rx_disabled(dev_priv, pipe);
5327 }
5328
5329 ironlake_pfit_enable(intel_crtc);
5330
5331 /*
5332 * On ILK+ LUT must be loaded before the pipe is running but with
5333 * clocks enabled
5334 */
5335 intel_color_load_luts(&pipe_config->base);
5336
5337 if (dev_priv->display.initial_watermarks != NULL)
5338 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5339 intel_enable_pipe(intel_crtc);
5340
5341 if (intel_crtc->config->has_pch_encoder)
5342 ironlake_pch_enable(pipe_config);
5343
5344 assert_vblank_disabled(crtc);
5345 drm_crtc_vblank_on(crtc);
5346
5347 intel_encoders_enable(crtc, pipe_config, old_state);
5348
5349 if (HAS_PCH_CPT(dev_priv))
5350 cpt_verify_modeset(dev, intel_crtc->pipe);
5351
5352 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5353 if (intel_crtc->config->has_pch_encoder)
5354 intel_wait_for_vblank(dev_priv, pipe);
5355 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5356 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5357 }
5358
5359 /* IPS only exists on ULT machines and is tied to pipe A. */
5360 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5361 {
5362 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5363 }
5364
5365 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5366 enum pipe pipe, bool apply)
5367 {
5368 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5369 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5370
5371 if (apply)
5372 val |= mask;
5373 else
5374 val &= ~mask;
5375
5376 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5377 }
5378
5379 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5380 struct drm_atomic_state *old_state)
5381 {
5382 struct drm_crtc *crtc = pipe_config->base.crtc;
5383 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5385 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5386 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5387 struct intel_atomic_state *old_intel_state =
5388 to_intel_atomic_state(old_state);
5389 bool psl_clkgate_wa;
5390
5391 if (WARN_ON(intel_crtc->active))
5392 return;
5393
5394 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5395
5396 if (intel_crtc->config->shared_dpll)
5397 intel_enable_shared_dpll(intel_crtc);
5398
5399 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5400 intel_dp_set_m_n(intel_crtc, M1_N1);
5401
5402 if (!transcoder_is_dsi(cpu_transcoder))
5403 intel_set_pipe_timings(intel_crtc);
5404
5405 intel_set_pipe_src_size(intel_crtc);
5406
5407 if (cpu_transcoder != TRANSCODER_EDP &&
5408 !transcoder_is_dsi(cpu_transcoder)) {
5409 I915_WRITE(PIPE_MULT(cpu_transcoder),
5410 intel_crtc->config->pixel_multiplier - 1);
5411 }
5412
5413 if (intel_crtc->config->has_pch_encoder) {
5414 intel_cpu_transcoder_set_m_n(intel_crtc,
5415 &intel_crtc->config->fdi_m_n, NULL);
5416 }
5417
5418 if (!transcoder_is_dsi(cpu_transcoder))
5419 haswell_set_pipeconf(crtc);
5420
5421 haswell_set_pipemisc(crtc);
5422
5423 intel_color_set_csc(&pipe_config->base);
5424
5425 intel_crtc->active = true;
5426
5427 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5428
5429 if (!transcoder_is_dsi(cpu_transcoder))
5430 intel_ddi_enable_pipe_clock(pipe_config);
5431
5432 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5433 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5434 intel_crtc->config->pch_pfit.enabled;
5435 if (psl_clkgate_wa)
5436 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5437
5438 if (INTEL_GEN(dev_priv) >= 9)
5439 skylake_pfit_enable(intel_crtc);
5440 else
5441 ironlake_pfit_enable(intel_crtc);
5442
5443 /*
5444 * On ILK+ LUT must be loaded before the pipe is running but with
5445 * clocks enabled
5446 */
5447 intel_color_load_luts(&pipe_config->base);
5448
5449 intel_ddi_set_pipe_settings(pipe_config);
5450 if (!transcoder_is_dsi(cpu_transcoder))
5451 intel_ddi_enable_transcoder_func(pipe_config);
5452
5453 if (dev_priv->display.initial_watermarks != NULL)
5454 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5455
5456 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5457 if (!transcoder_is_dsi(cpu_transcoder))
5458 intel_enable_pipe(intel_crtc);
5459
5460 if (intel_crtc->config->has_pch_encoder)
5461 lpt_pch_enable(pipe_config);
5462
5463 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5464 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5465
5466 assert_vblank_disabled(crtc);
5467 drm_crtc_vblank_on(crtc);
5468
5469 intel_encoders_enable(crtc, pipe_config, old_state);
5470
5471 if (psl_clkgate_wa) {
5472 intel_wait_for_vblank(dev_priv, pipe);
5473 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5474 }
5475
5476 /* If we change the relative order between pipe/planes enabling, we need
5477 * to change the workaround. */
5478 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5479 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5480 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5481 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5482 }
5483 }
5484
5485 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5486 {
5487 struct drm_device *dev = crtc->base.dev;
5488 struct drm_i915_private *dev_priv = to_i915(dev);
5489 int pipe = crtc->pipe;
5490
5491 /* To avoid upsetting the power well on haswell only disable the pfit if
5492 * it's in use. The hw state code will make sure we get this right. */
5493 if (force || crtc->config->pch_pfit.enabled) {
5494 I915_WRITE(PF_CTL(pipe), 0);
5495 I915_WRITE(PF_WIN_POS(pipe), 0);
5496 I915_WRITE(PF_WIN_SZ(pipe), 0);
5497 }
5498 }
5499
5500 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5501 struct drm_atomic_state *old_state)
5502 {
5503 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5504 struct drm_device *dev = crtc->dev;
5505 struct drm_i915_private *dev_priv = to_i915(dev);
5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507 int pipe = intel_crtc->pipe;
5508
5509 /*
5510 * Sometimes spurious CPU pipe underruns happen when the
5511 * pipe is already disabled, but FDI RX/TX is still enabled.
5512 * Happens at least with VGA+HDMI cloning. Suppress them.
5513 */
5514 if (intel_crtc->config->has_pch_encoder) {
5515 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5516 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5517 }
5518
5519 intel_encoders_disable(crtc, old_crtc_state, old_state);
5520
5521 drm_crtc_vblank_off(crtc);
5522 assert_vblank_disabled(crtc);
5523
5524 intel_disable_pipe(intel_crtc);
5525
5526 ironlake_pfit_disable(intel_crtc, false);
5527
5528 if (intel_crtc->config->has_pch_encoder)
5529 ironlake_fdi_disable(crtc);
5530
5531 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5532
5533 if (intel_crtc->config->has_pch_encoder) {
5534 ironlake_disable_pch_transcoder(dev_priv, pipe);
5535
5536 if (HAS_PCH_CPT(dev_priv)) {
5537 i915_reg_t reg;
5538 u32 temp;
5539
5540 /* disable TRANS_DP_CTL */
5541 reg = TRANS_DP_CTL(pipe);
5542 temp = I915_READ(reg);
5543 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5544 TRANS_DP_PORT_SEL_MASK);
5545 temp |= TRANS_DP_PORT_SEL_NONE;
5546 I915_WRITE(reg, temp);
5547
5548 /* disable DPLL_SEL */
5549 temp = I915_READ(PCH_DPLL_SEL);
5550 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5551 I915_WRITE(PCH_DPLL_SEL, temp);
5552 }
5553
5554 ironlake_fdi_pll_disable(intel_crtc);
5555 }
5556
5557 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5558 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5559 }
5560
5561 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5562 struct drm_atomic_state *old_state)
5563 {
5564 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5565 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5567 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5568
5569 intel_encoders_disable(crtc, old_crtc_state, old_state);
5570
5571 drm_crtc_vblank_off(crtc);
5572 assert_vblank_disabled(crtc);
5573
5574 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5575 if (!transcoder_is_dsi(cpu_transcoder))
5576 intel_disable_pipe(intel_crtc);
5577
5578 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5579 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5580
5581 if (!transcoder_is_dsi(cpu_transcoder))
5582 intel_ddi_disable_transcoder_func(old_crtc_state);
5583
5584 if (INTEL_GEN(dev_priv) >= 9)
5585 skylake_scaler_disable(intel_crtc);
5586 else
5587 ironlake_pfit_disable(intel_crtc, false);
5588
5589 if (!transcoder_is_dsi(cpu_transcoder))
5590 intel_ddi_disable_pipe_clock(intel_crtc->config);
5591
5592 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5593 }
5594
5595 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5596 {
5597 struct drm_device *dev = crtc->base.dev;
5598 struct drm_i915_private *dev_priv = to_i915(dev);
5599 struct intel_crtc_state *pipe_config = crtc->config;
5600
5601 if (!pipe_config->gmch_pfit.control)
5602 return;
5603
5604 /*
5605 * The panel fitter should only be adjusted whilst the pipe is disabled,
5606 * according to register description and PRM.
5607 */
5608 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5609 assert_pipe_disabled(dev_priv, crtc->pipe);
5610
5611 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5612 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5613
5614 /* Border color in case we don't scale up to the full screen. Black by
5615 * default, change to something else for debugging. */
5616 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5617 }
5618
5619 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5620 {
5621 switch (port) {
5622 case PORT_A:
5623 return POWER_DOMAIN_PORT_DDI_A_LANES;
5624 case PORT_B:
5625 return POWER_DOMAIN_PORT_DDI_B_LANES;
5626 case PORT_C:
5627 return POWER_DOMAIN_PORT_DDI_C_LANES;
5628 case PORT_D:
5629 return POWER_DOMAIN_PORT_DDI_D_LANES;
5630 case PORT_E:
5631 return POWER_DOMAIN_PORT_DDI_E_LANES;
5632 default:
5633 MISSING_CASE(port);
5634 return POWER_DOMAIN_PORT_OTHER;
5635 }
5636 }
5637
5638 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5639 struct intel_crtc_state *crtc_state)
5640 {
5641 struct drm_device *dev = crtc->dev;
5642 struct drm_i915_private *dev_priv = to_i915(dev);
5643 struct drm_encoder *encoder;
5644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5645 enum pipe pipe = intel_crtc->pipe;
5646 u64 mask;
5647 enum transcoder transcoder = crtc_state->cpu_transcoder;
5648
5649 if (!crtc_state->base.active)
5650 return 0;
5651
5652 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5653 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5654 if (crtc_state->pch_pfit.enabled ||
5655 crtc_state->pch_pfit.force_thru)
5656 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5657
5658 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5659 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5660
5661 mask |= BIT_ULL(intel_encoder->power_domain);
5662 }
5663
5664 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5665 mask |= BIT(POWER_DOMAIN_AUDIO);
5666
5667 if (crtc_state->shared_dpll)
5668 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5669
5670 return mask;
5671 }
5672
5673 static u64
5674 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5675 struct intel_crtc_state *crtc_state)
5676 {
5677 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5679 enum intel_display_power_domain domain;
5680 u64 domains, new_domains, old_domains;
5681
5682 old_domains = intel_crtc->enabled_power_domains;
5683 intel_crtc->enabled_power_domains = new_domains =
5684 get_crtc_power_domains(crtc, crtc_state);
5685
5686 domains = new_domains & ~old_domains;
5687
5688 for_each_power_domain(domain, domains)
5689 intel_display_power_get(dev_priv, domain);
5690
5691 return old_domains & ~new_domains;
5692 }
5693
5694 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5695 u64 domains)
5696 {
5697 enum intel_display_power_domain domain;
5698
5699 for_each_power_domain(domain, domains)
5700 intel_display_power_put(dev_priv, domain);
5701 }
5702
5703 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5704 struct drm_atomic_state *old_state)
5705 {
5706 struct intel_atomic_state *old_intel_state =
5707 to_intel_atomic_state(old_state);
5708 struct drm_crtc *crtc = pipe_config->base.crtc;
5709 struct drm_device *dev = crtc->dev;
5710 struct drm_i915_private *dev_priv = to_i915(dev);
5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712 int pipe = intel_crtc->pipe;
5713
5714 if (WARN_ON(intel_crtc->active))
5715 return;
5716
5717 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5718 intel_dp_set_m_n(intel_crtc, M1_N1);
5719
5720 intel_set_pipe_timings(intel_crtc);
5721 intel_set_pipe_src_size(intel_crtc);
5722
5723 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5724 struct drm_i915_private *dev_priv = to_i915(dev);
5725
5726 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5727 I915_WRITE(CHV_CANVAS(pipe), 0);
5728 }
5729
5730 i9xx_set_pipeconf(intel_crtc);
5731
5732 intel_crtc->active = true;
5733
5734 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5735
5736 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5737
5738 if (IS_CHERRYVIEW(dev_priv)) {
5739 chv_prepare_pll(intel_crtc, intel_crtc->config);
5740 chv_enable_pll(intel_crtc, intel_crtc->config);
5741 } else {
5742 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5743 vlv_enable_pll(intel_crtc, intel_crtc->config);
5744 }
5745
5746 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5747
5748 i9xx_pfit_enable(intel_crtc);
5749
5750 intel_color_load_luts(&pipe_config->base);
5751
5752 dev_priv->display.initial_watermarks(old_intel_state,
5753 pipe_config);
5754 intel_enable_pipe(intel_crtc);
5755
5756 assert_vblank_disabled(crtc);
5757 drm_crtc_vblank_on(crtc);
5758
5759 intel_encoders_enable(crtc, pipe_config, old_state);
5760 }
5761
5762 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5763 {
5764 struct drm_device *dev = crtc->base.dev;
5765 struct drm_i915_private *dev_priv = to_i915(dev);
5766
5767 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5768 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5769 }
5770
5771 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5772 struct drm_atomic_state *old_state)
5773 {
5774 struct intel_atomic_state *old_intel_state =
5775 to_intel_atomic_state(old_state);
5776 struct drm_crtc *crtc = pipe_config->base.crtc;
5777 struct drm_device *dev = crtc->dev;
5778 struct drm_i915_private *dev_priv = to_i915(dev);
5779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5780 enum pipe pipe = intel_crtc->pipe;
5781
5782 if (WARN_ON(intel_crtc->active))
5783 return;
5784
5785 i9xx_set_pll_dividers(intel_crtc);
5786
5787 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5788 intel_dp_set_m_n(intel_crtc, M1_N1);
5789
5790 intel_set_pipe_timings(intel_crtc);
5791 intel_set_pipe_src_size(intel_crtc);
5792
5793 i9xx_set_pipeconf(intel_crtc);
5794
5795 intel_crtc->active = true;
5796
5797 if (!IS_GEN2(dev_priv))
5798 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5799
5800 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5801
5802 i9xx_enable_pll(intel_crtc, pipe_config);
5803
5804 i9xx_pfit_enable(intel_crtc);
5805
5806 intel_color_load_luts(&pipe_config->base);
5807
5808 if (dev_priv->display.initial_watermarks != NULL)
5809 dev_priv->display.initial_watermarks(old_intel_state,
5810 intel_crtc->config);
5811 else
5812 intel_update_watermarks(intel_crtc);
5813 intel_enable_pipe(intel_crtc);
5814
5815 assert_vblank_disabled(crtc);
5816 drm_crtc_vblank_on(crtc);
5817
5818 intel_encoders_enable(crtc, pipe_config, old_state);
5819 }
5820
5821 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5822 {
5823 struct drm_device *dev = crtc->base.dev;
5824 struct drm_i915_private *dev_priv = to_i915(dev);
5825
5826 if (!crtc->config->gmch_pfit.control)
5827 return;
5828
5829 assert_pipe_disabled(dev_priv, crtc->pipe);
5830
5831 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5832 I915_READ(PFIT_CONTROL));
5833 I915_WRITE(PFIT_CONTROL, 0);
5834 }
5835
5836 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5837 struct drm_atomic_state *old_state)
5838 {
5839 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5840 struct drm_device *dev = crtc->dev;
5841 struct drm_i915_private *dev_priv = to_i915(dev);
5842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5843 int pipe = intel_crtc->pipe;
5844
5845 /*
5846 * On gen2 planes are double buffered but the pipe isn't, so we must
5847 * wait for planes to fully turn off before disabling the pipe.
5848 */
5849 if (IS_GEN2(dev_priv))
5850 intel_wait_for_vblank(dev_priv, pipe);
5851
5852 intel_encoders_disable(crtc, old_crtc_state, old_state);
5853
5854 drm_crtc_vblank_off(crtc);
5855 assert_vblank_disabled(crtc);
5856
5857 intel_disable_pipe(intel_crtc);
5858
5859 i9xx_pfit_disable(intel_crtc);
5860
5861 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5862
5863 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5864 if (IS_CHERRYVIEW(dev_priv))
5865 chv_disable_pll(dev_priv, pipe);
5866 else if (IS_VALLEYVIEW(dev_priv))
5867 vlv_disable_pll(dev_priv, pipe);
5868 else
5869 i9xx_disable_pll(intel_crtc);
5870 }
5871
5872 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5873
5874 if (!IS_GEN2(dev_priv))
5875 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5876
5877 if (!dev_priv->display.initial_watermarks)
5878 intel_update_watermarks(intel_crtc);
5879
5880 /* clock the pipe down to 640x480@60 to potentially save power */
5881 if (IS_I830(dev_priv))
5882 i830_enable_pipe(dev_priv, pipe);
5883 }
5884
5885 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5886 struct drm_modeset_acquire_ctx *ctx)
5887 {
5888 struct intel_encoder *encoder;
5889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5890 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5891 enum intel_display_power_domain domain;
5892 struct intel_plane *plane;
5893 u64 domains;
5894 struct drm_atomic_state *state;
5895 struct intel_crtc_state *crtc_state;
5896 int ret;
5897
5898 if (!intel_crtc->active)
5899 return;
5900
5901 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
5902 const struct intel_plane_state *plane_state =
5903 to_intel_plane_state(plane->base.state);
5904
5905 if (plane_state->base.visible)
5906 intel_plane_disable_noatomic(intel_crtc, plane);
5907 }
5908
5909 state = drm_atomic_state_alloc(crtc->dev);
5910 if (!state) {
5911 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5912 crtc->base.id, crtc->name);
5913 return;
5914 }
5915
5916 state->acquire_ctx = ctx;
5917
5918 /* Everything's already locked, -EDEADLK can't happen. */
5919 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5920 ret = drm_atomic_add_affected_connectors(state, crtc);
5921
5922 WARN_ON(IS_ERR(crtc_state) || ret);
5923
5924 dev_priv->display.crtc_disable(crtc_state, state);
5925
5926 drm_atomic_state_put(state);
5927
5928 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5929 crtc->base.id, crtc->name);
5930
5931 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5932 crtc->state->active = false;
5933 intel_crtc->active = false;
5934 crtc->enabled = false;
5935 crtc->state->connector_mask = 0;
5936 crtc->state->encoder_mask = 0;
5937
5938 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5939 encoder->base.crtc = NULL;
5940
5941 intel_fbc_disable(intel_crtc);
5942 intel_update_watermarks(intel_crtc);
5943 intel_disable_shared_dpll(intel_crtc);
5944
5945 domains = intel_crtc->enabled_power_domains;
5946 for_each_power_domain(domain, domains)
5947 intel_display_power_put(dev_priv, domain);
5948 intel_crtc->enabled_power_domains = 0;
5949
5950 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5951 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5952 }
5953
5954 /*
5955 * turn all crtc's off, but do not adjust state
5956 * This has to be paired with a call to intel_modeset_setup_hw_state.
5957 */
5958 int intel_display_suspend(struct drm_device *dev)
5959 {
5960 struct drm_i915_private *dev_priv = to_i915(dev);
5961 struct drm_atomic_state *state;
5962 int ret;
5963
5964 state = drm_atomic_helper_suspend(dev);
5965 ret = PTR_ERR_OR_ZERO(state);
5966 if (ret)
5967 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5968 else
5969 dev_priv->modeset_restore_state = state;
5970 return ret;
5971 }
5972
5973 void intel_encoder_destroy(struct drm_encoder *encoder)
5974 {
5975 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5976
5977 drm_encoder_cleanup(encoder);
5978 kfree(intel_encoder);
5979 }
5980
5981 /* Cross check the actual hw state with our own modeset state tracking (and it's
5982 * internal consistency). */
5983 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5984 struct drm_connector_state *conn_state)
5985 {
5986 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5987
5988 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5989 connector->base.base.id,
5990 connector->base.name);
5991
5992 if (connector->get_hw_state(connector)) {
5993 struct intel_encoder *encoder = connector->encoder;
5994
5995 I915_STATE_WARN(!crtc_state,
5996 "connector enabled without attached crtc\n");
5997
5998 if (!crtc_state)
5999 return;
6000
6001 I915_STATE_WARN(!crtc_state->active,
6002 "connector is active, but attached crtc isn't\n");
6003
6004 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6005 return;
6006
6007 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6008 "atomic encoder doesn't match attached encoder\n");
6009
6010 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6011 "attached encoder crtc differs from connector crtc\n");
6012 } else {
6013 I915_STATE_WARN(crtc_state && crtc_state->active,
6014 "attached crtc is active, but connector isn't\n");
6015 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6016 "best encoder set without crtc!\n");
6017 }
6018 }
6019
6020 int intel_connector_init(struct intel_connector *connector)
6021 {
6022 struct intel_digital_connector_state *conn_state;
6023
6024 /*
6025 * Allocate enough memory to hold intel_digital_connector_state,
6026 * This might be a few bytes too many, but for connectors that don't
6027 * need it we'll free the state and allocate a smaller one on the first
6028 * succesful commit anyway.
6029 */
6030 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6031 if (!conn_state)
6032 return -ENOMEM;
6033
6034 __drm_atomic_helper_connector_reset(&connector->base,
6035 &conn_state->base);
6036
6037 return 0;
6038 }
6039
6040 struct intel_connector *intel_connector_alloc(void)
6041 {
6042 struct intel_connector *connector;
6043
6044 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6045 if (!connector)
6046 return NULL;
6047
6048 if (intel_connector_init(connector) < 0) {
6049 kfree(connector);
6050 return NULL;
6051 }
6052
6053 return connector;
6054 }
6055
6056 /*
6057 * Free the bits allocated by intel_connector_alloc.
6058 * This should only be used after intel_connector_alloc has returned
6059 * successfully, and before drm_connector_init returns successfully.
6060 * Otherwise the destroy callbacks for the connector and the state should
6061 * take care of proper cleanup/free
6062 */
6063 void intel_connector_free(struct intel_connector *connector)
6064 {
6065 kfree(to_intel_digital_connector_state(connector->base.state));
6066 kfree(connector);
6067 }
6068
6069 /* Simple connector->get_hw_state implementation for encoders that support only
6070 * one connector and no cloning and hence the encoder state determines the state
6071 * of the connector. */
6072 bool intel_connector_get_hw_state(struct intel_connector *connector)
6073 {
6074 enum pipe pipe = 0;
6075 struct intel_encoder *encoder = connector->encoder;
6076
6077 return encoder->get_hw_state(encoder, &pipe);
6078 }
6079
6080 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6081 {
6082 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6083 return crtc_state->fdi_lanes;
6084
6085 return 0;
6086 }
6087
6088 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6089 struct intel_crtc_state *pipe_config)
6090 {
6091 struct drm_i915_private *dev_priv = to_i915(dev);
6092 struct drm_atomic_state *state = pipe_config->base.state;
6093 struct intel_crtc *other_crtc;
6094 struct intel_crtc_state *other_crtc_state;
6095
6096 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6097 pipe_name(pipe), pipe_config->fdi_lanes);
6098 if (pipe_config->fdi_lanes > 4) {
6099 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6100 pipe_name(pipe), pipe_config->fdi_lanes);
6101 return -EINVAL;
6102 }
6103
6104 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6105 if (pipe_config->fdi_lanes > 2) {
6106 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6107 pipe_config->fdi_lanes);
6108 return -EINVAL;
6109 } else {
6110 return 0;
6111 }
6112 }
6113
6114 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6115 return 0;
6116
6117 /* Ivybridge 3 pipe is really complicated */
6118 switch (pipe) {
6119 case PIPE_A:
6120 return 0;
6121 case PIPE_B:
6122 if (pipe_config->fdi_lanes <= 2)
6123 return 0;
6124
6125 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6126 other_crtc_state =
6127 intel_atomic_get_crtc_state(state, other_crtc);
6128 if (IS_ERR(other_crtc_state))
6129 return PTR_ERR(other_crtc_state);
6130
6131 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6132 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6133 pipe_name(pipe), pipe_config->fdi_lanes);
6134 return -EINVAL;
6135 }
6136 return 0;
6137 case PIPE_C:
6138 if (pipe_config->fdi_lanes > 2) {
6139 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6140 pipe_name(pipe), pipe_config->fdi_lanes);
6141 return -EINVAL;
6142 }
6143
6144 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6145 other_crtc_state =
6146 intel_atomic_get_crtc_state(state, other_crtc);
6147 if (IS_ERR(other_crtc_state))
6148 return PTR_ERR(other_crtc_state);
6149
6150 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6151 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6152 return -EINVAL;
6153 }
6154 return 0;
6155 default:
6156 BUG();
6157 }
6158 }
6159
6160 #define RETRY 1
6161 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6162 struct intel_crtc_state *pipe_config)
6163 {
6164 struct drm_device *dev = intel_crtc->base.dev;
6165 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6166 int lane, link_bw, fdi_dotclock, ret;
6167 bool needs_recompute = false;
6168
6169 retry:
6170 /* FDI is a binary signal running at ~2.7GHz, encoding
6171 * each output octet as 10 bits. The actual frequency
6172 * is stored as a divider into a 100MHz clock, and the
6173 * mode pixel clock is stored in units of 1KHz.
6174 * Hence the bw of each lane in terms of the mode signal
6175 * is:
6176 */
6177 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6178
6179 fdi_dotclock = adjusted_mode->crtc_clock;
6180
6181 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6182 pipe_config->pipe_bpp);
6183
6184 pipe_config->fdi_lanes = lane;
6185
6186 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6187 link_bw, &pipe_config->fdi_m_n, false);
6188
6189 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6190 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6191 pipe_config->pipe_bpp -= 2*3;
6192 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6193 pipe_config->pipe_bpp);
6194 needs_recompute = true;
6195 pipe_config->bw_constrained = true;
6196
6197 goto retry;
6198 }
6199
6200 if (needs_recompute)
6201 return RETRY;
6202
6203 return ret;
6204 }
6205
6206 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6207 struct intel_crtc_state *pipe_config)
6208 {
6209 if (pipe_config->ips_force_disable)
6210 return false;
6211
6212 if (pipe_config->pipe_bpp > 24)
6213 return false;
6214
6215 /* HSW can handle pixel rate up to cdclk? */
6216 if (IS_HASWELL(dev_priv))
6217 return true;
6218
6219 /*
6220 * We compare against max which means we must take
6221 * the increased cdclk requirement into account when
6222 * calculating the new cdclk.
6223 *
6224 * Should measure whether using a lower cdclk w/o IPS
6225 */
6226 return pipe_config->pixel_rate <=
6227 dev_priv->max_cdclk_freq * 95 / 100;
6228 }
6229
6230 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6231 struct intel_crtc_state *pipe_config)
6232 {
6233 struct drm_device *dev = crtc->base.dev;
6234 struct drm_i915_private *dev_priv = to_i915(dev);
6235
6236 pipe_config->ips_enabled = i915_modparams.enable_ips &&
6237 hsw_crtc_supports_ips(crtc) &&
6238 pipe_config_supports_ips(dev_priv, pipe_config);
6239 }
6240
6241 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6242 {
6243 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6244
6245 /* GDG double wide on either pipe, otherwise pipe A only */
6246 return INTEL_INFO(dev_priv)->gen < 4 &&
6247 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6248 }
6249
6250 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6251 {
6252 uint32_t pixel_rate;
6253
6254 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6255
6256 /*
6257 * We only use IF-ID interlacing. If we ever use
6258 * PF-ID we'll need to adjust the pixel_rate here.
6259 */
6260
6261 if (pipe_config->pch_pfit.enabled) {
6262 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6263 uint32_t pfit_size = pipe_config->pch_pfit.size;
6264
6265 pipe_w = pipe_config->pipe_src_w;
6266 pipe_h = pipe_config->pipe_src_h;
6267
6268 pfit_w = (pfit_size >> 16) & 0xFFFF;
6269 pfit_h = pfit_size & 0xFFFF;
6270 if (pipe_w < pfit_w)
6271 pipe_w = pfit_w;
6272 if (pipe_h < pfit_h)
6273 pipe_h = pfit_h;
6274
6275 if (WARN_ON(!pfit_w || !pfit_h))
6276 return pixel_rate;
6277
6278 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6279 pfit_w * pfit_h);
6280 }
6281
6282 return pixel_rate;
6283 }
6284
6285 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6286 {
6287 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6288
6289 if (HAS_GMCH_DISPLAY(dev_priv))
6290 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6291 crtc_state->pixel_rate =
6292 crtc_state->base.adjusted_mode.crtc_clock;
6293 else
6294 crtc_state->pixel_rate =
6295 ilk_pipe_pixel_rate(crtc_state);
6296 }
6297
6298 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6299 struct intel_crtc_state *pipe_config)
6300 {
6301 struct drm_device *dev = crtc->base.dev;
6302 struct drm_i915_private *dev_priv = to_i915(dev);
6303 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6304 int clock_limit = dev_priv->max_dotclk_freq;
6305
6306 if (INTEL_GEN(dev_priv) < 4) {
6307 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6308
6309 /*
6310 * Enable double wide mode when the dot clock
6311 * is > 90% of the (display) core speed.
6312 */
6313 if (intel_crtc_supports_double_wide(crtc) &&
6314 adjusted_mode->crtc_clock > clock_limit) {
6315 clock_limit = dev_priv->max_dotclk_freq;
6316 pipe_config->double_wide = true;
6317 }
6318 }
6319
6320 if (adjusted_mode->crtc_clock > clock_limit) {
6321 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6322 adjusted_mode->crtc_clock, clock_limit,
6323 yesno(pipe_config->double_wide));
6324 return -EINVAL;
6325 }
6326
6327 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6328 /*
6329 * There is only one pipe CSC unit per pipe, and we need that
6330 * for output conversion from RGB->YCBCR. So if CTM is already
6331 * applied we can't support YCBCR420 output.
6332 */
6333 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6334 return -EINVAL;
6335 }
6336
6337 /*
6338 * Pipe horizontal size must be even in:
6339 * - DVO ganged mode
6340 * - LVDS dual channel mode
6341 * - Double wide pipe
6342 */
6343 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6344 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6345 pipe_config->pipe_src_w &= ~1;
6346
6347 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6348 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6349 */
6350 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6351 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6352 return -EINVAL;
6353
6354 intel_crtc_compute_pixel_rate(pipe_config);
6355
6356 if (HAS_IPS(dev_priv))
6357 hsw_compute_ips_config(crtc, pipe_config);
6358
6359 if (pipe_config->has_pch_encoder)
6360 return ironlake_fdi_compute_config(crtc, pipe_config);
6361
6362 return 0;
6363 }
6364
6365 static void
6366 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6367 {
6368 while (*num > DATA_LINK_M_N_MASK ||
6369 *den > DATA_LINK_M_N_MASK) {
6370 *num >>= 1;
6371 *den >>= 1;
6372 }
6373 }
6374
6375 static void compute_m_n(unsigned int m, unsigned int n,
6376 uint32_t *ret_m, uint32_t *ret_n,
6377 bool reduce_m_n)
6378 {
6379 /*
6380 * Reduce M/N as much as possible without loss in precision. Several DP
6381 * dongles in particular seem to be fussy about too large *link* M/N
6382 * values. The passed in values are more likely to have the least
6383 * significant bits zero than M after rounding below, so do this first.
6384 */
6385 if (reduce_m_n) {
6386 while ((m & 1) == 0 && (n & 1) == 0) {
6387 m >>= 1;
6388 n >>= 1;
6389 }
6390 }
6391
6392 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6393 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6394 intel_reduce_m_n_ratio(ret_m, ret_n);
6395 }
6396
6397 void
6398 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6399 int pixel_clock, int link_clock,
6400 struct intel_link_m_n *m_n,
6401 bool reduce_m_n)
6402 {
6403 m_n->tu = 64;
6404
6405 compute_m_n(bits_per_pixel * pixel_clock,
6406 link_clock * nlanes * 8,
6407 &m_n->gmch_m, &m_n->gmch_n,
6408 reduce_m_n);
6409
6410 compute_m_n(pixel_clock, link_clock,
6411 &m_n->link_m, &m_n->link_n,
6412 reduce_m_n);
6413 }
6414
6415 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6416 {
6417 if (i915_modparams.panel_use_ssc >= 0)
6418 return i915_modparams.panel_use_ssc != 0;
6419 return dev_priv->vbt.lvds_use_ssc
6420 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6421 }
6422
6423 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6424 {
6425 return (1 << dpll->n) << 16 | dpll->m2;
6426 }
6427
6428 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6429 {
6430 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6431 }
6432
6433 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6434 struct intel_crtc_state *crtc_state,
6435 struct dpll *reduced_clock)
6436 {
6437 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6438 u32 fp, fp2 = 0;
6439
6440 if (IS_PINEVIEW(dev_priv)) {
6441 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6442 if (reduced_clock)
6443 fp2 = pnv_dpll_compute_fp(reduced_clock);
6444 } else {
6445 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6446 if (reduced_clock)
6447 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6448 }
6449
6450 crtc_state->dpll_hw_state.fp0 = fp;
6451
6452 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6453 reduced_clock) {
6454 crtc_state->dpll_hw_state.fp1 = fp2;
6455 } else {
6456 crtc_state->dpll_hw_state.fp1 = fp;
6457 }
6458 }
6459
6460 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6461 pipe)
6462 {
6463 u32 reg_val;
6464
6465 /*
6466 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6467 * and set it to a reasonable value instead.
6468 */
6469 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6470 reg_val &= 0xffffff00;
6471 reg_val |= 0x00000030;
6472 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6473
6474 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6475 reg_val &= 0x00ffffff;
6476 reg_val |= 0x8c000000;
6477 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6478
6479 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6480 reg_val &= 0xffffff00;
6481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6482
6483 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6484 reg_val &= 0x00ffffff;
6485 reg_val |= 0xb0000000;
6486 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6487 }
6488
6489 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6490 struct intel_link_m_n *m_n)
6491 {
6492 struct drm_device *dev = crtc->base.dev;
6493 struct drm_i915_private *dev_priv = to_i915(dev);
6494 int pipe = crtc->pipe;
6495
6496 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6497 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6498 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6499 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6500 }
6501
6502 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6503 struct intel_link_m_n *m_n,
6504 struct intel_link_m_n *m2_n2)
6505 {
6506 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6507 int pipe = crtc->pipe;
6508 enum transcoder transcoder = crtc->config->cpu_transcoder;
6509
6510 if (INTEL_GEN(dev_priv) >= 5) {
6511 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6512 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6513 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6514 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6515 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6516 * for gen < 8) and if DRRS is supported (to make sure the
6517 * registers are not unnecessarily accessed).
6518 */
6519 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6520 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6521 I915_WRITE(PIPE_DATA_M2(transcoder),
6522 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6523 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6524 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6525 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6526 }
6527 } else {
6528 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6529 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6530 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6531 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6532 }
6533 }
6534
6535 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6536 {
6537 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6538
6539 if (m_n == M1_N1) {
6540 dp_m_n = &crtc->config->dp_m_n;
6541 dp_m2_n2 = &crtc->config->dp_m2_n2;
6542 } else if (m_n == M2_N2) {
6543
6544 /*
6545 * M2_N2 registers are not supported. Hence m2_n2 divider value
6546 * needs to be programmed into M1_N1.
6547 */
6548 dp_m_n = &crtc->config->dp_m2_n2;
6549 } else {
6550 DRM_ERROR("Unsupported divider value\n");
6551 return;
6552 }
6553
6554 if (crtc->config->has_pch_encoder)
6555 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6556 else
6557 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6558 }
6559
6560 static void vlv_compute_dpll(struct intel_crtc *crtc,
6561 struct intel_crtc_state *pipe_config)
6562 {
6563 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6564 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6565 if (crtc->pipe != PIPE_A)
6566 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6567
6568 /* DPLL not used with DSI, but still need the rest set up */
6569 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6570 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6571 DPLL_EXT_BUFFER_ENABLE_VLV;
6572
6573 pipe_config->dpll_hw_state.dpll_md =
6574 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6575 }
6576
6577 static void chv_compute_dpll(struct intel_crtc *crtc,
6578 struct intel_crtc_state *pipe_config)
6579 {
6580 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6581 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6582 if (crtc->pipe != PIPE_A)
6583 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6584
6585 /* DPLL not used with DSI, but still need the rest set up */
6586 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6587 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6588
6589 pipe_config->dpll_hw_state.dpll_md =
6590 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6591 }
6592
6593 static void vlv_prepare_pll(struct intel_crtc *crtc,
6594 const struct intel_crtc_state *pipe_config)
6595 {
6596 struct drm_device *dev = crtc->base.dev;
6597 struct drm_i915_private *dev_priv = to_i915(dev);
6598 enum pipe pipe = crtc->pipe;
6599 u32 mdiv;
6600 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6601 u32 coreclk, reg_val;
6602
6603 /* Enable Refclk */
6604 I915_WRITE(DPLL(pipe),
6605 pipe_config->dpll_hw_state.dpll &
6606 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6607
6608 /* No need to actually set up the DPLL with DSI */
6609 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6610 return;
6611
6612 mutex_lock(&dev_priv->sb_lock);
6613
6614 bestn = pipe_config->dpll.n;
6615 bestm1 = pipe_config->dpll.m1;
6616 bestm2 = pipe_config->dpll.m2;
6617 bestp1 = pipe_config->dpll.p1;
6618 bestp2 = pipe_config->dpll.p2;
6619
6620 /* See eDP HDMI DPIO driver vbios notes doc */
6621
6622 /* PLL B needs special handling */
6623 if (pipe == PIPE_B)
6624 vlv_pllb_recal_opamp(dev_priv, pipe);
6625
6626 /* Set up Tx target for periodic Rcomp update */
6627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6628
6629 /* Disable target IRef on PLL */
6630 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6631 reg_val &= 0x00ffffff;
6632 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6633
6634 /* Disable fast lock */
6635 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6636
6637 /* Set idtafcrecal before PLL is enabled */
6638 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6639 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6640 mdiv |= ((bestn << DPIO_N_SHIFT));
6641 mdiv |= (1 << DPIO_K_SHIFT);
6642
6643 /*
6644 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6645 * but we don't support that).
6646 * Note: don't use the DAC post divider as it seems unstable.
6647 */
6648 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6649 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6650
6651 mdiv |= DPIO_ENABLE_CALIBRATION;
6652 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6653
6654 /* Set HBR and RBR LPF coefficients */
6655 if (pipe_config->port_clock == 162000 ||
6656 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6657 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6658 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6659 0x009f0003);
6660 else
6661 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6662 0x00d0000f);
6663
6664 if (intel_crtc_has_dp_encoder(pipe_config)) {
6665 /* Use SSC source */
6666 if (pipe == PIPE_A)
6667 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6668 0x0df40000);
6669 else
6670 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6671 0x0df70000);
6672 } else { /* HDMI or VGA */
6673 /* Use bend source */
6674 if (pipe == PIPE_A)
6675 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6676 0x0df70000);
6677 else
6678 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6679 0x0df40000);
6680 }
6681
6682 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6683 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6684 if (intel_crtc_has_dp_encoder(crtc->config))
6685 coreclk |= 0x01000000;
6686 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6687
6688 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6689 mutex_unlock(&dev_priv->sb_lock);
6690 }
6691
6692 static void chv_prepare_pll(struct intel_crtc *crtc,
6693 const struct intel_crtc_state *pipe_config)
6694 {
6695 struct drm_device *dev = crtc->base.dev;
6696 struct drm_i915_private *dev_priv = to_i915(dev);
6697 enum pipe pipe = crtc->pipe;
6698 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6699 u32 loopfilter, tribuf_calcntr;
6700 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6701 u32 dpio_val;
6702 int vco;
6703
6704 /* Enable Refclk and SSC */
6705 I915_WRITE(DPLL(pipe),
6706 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6707
6708 /* No need to actually set up the DPLL with DSI */
6709 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6710 return;
6711
6712 bestn = pipe_config->dpll.n;
6713 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6714 bestm1 = pipe_config->dpll.m1;
6715 bestm2 = pipe_config->dpll.m2 >> 22;
6716 bestp1 = pipe_config->dpll.p1;
6717 bestp2 = pipe_config->dpll.p2;
6718 vco = pipe_config->dpll.vco;
6719 dpio_val = 0;
6720 loopfilter = 0;
6721
6722 mutex_lock(&dev_priv->sb_lock);
6723
6724 /* p1 and p2 divider */
6725 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6726 5 << DPIO_CHV_S1_DIV_SHIFT |
6727 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6728 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6729 1 << DPIO_CHV_K_DIV_SHIFT);
6730
6731 /* Feedback post-divider - m2 */
6732 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6733
6734 /* Feedback refclk divider - n and m1 */
6735 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6736 DPIO_CHV_M1_DIV_BY_2 |
6737 1 << DPIO_CHV_N_DIV_SHIFT);
6738
6739 /* M2 fraction division */
6740 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6741
6742 /* M2 fraction division enable */
6743 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6744 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6745 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6746 if (bestm2_frac)
6747 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6748 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6749
6750 /* Program digital lock detect threshold */
6751 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6752 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6753 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6754 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6755 if (!bestm2_frac)
6756 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6757 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6758
6759 /* Loop filter */
6760 if (vco == 5400000) {
6761 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6762 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6763 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6764 tribuf_calcntr = 0x9;
6765 } else if (vco <= 6200000) {
6766 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6767 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6768 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6769 tribuf_calcntr = 0x9;
6770 } else if (vco <= 6480000) {
6771 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6772 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6773 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6774 tribuf_calcntr = 0x8;
6775 } else {
6776 /* Not supported. Apply the same limits as in the max case */
6777 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6778 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6779 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6780 tribuf_calcntr = 0;
6781 }
6782 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6783
6784 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6785 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6786 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6787 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6788
6789 /* AFC Recal */
6790 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6791 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6792 DPIO_AFC_RECAL);
6793
6794 mutex_unlock(&dev_priv->sb_lock);
6795 }
6796
6797 /**
6798 * vlv_force_pll_on - forcibly enable just the PLL
6799 * @dev_priv: i915 private structure
6800 * @pipe: pipe PLL to enable
6801 * @dpll: PLL configuration
6802 *
6803 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6804 * in cases where we need the PLL enabled even when @pipe is not going to
6805 * be enabled.
6806 */
6807 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6808 const struct dpll *dpll)
6809 {
6810 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6811 struct intel_crtc_state *pipe_config;
6812
6813 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6814 if (!pipe_config)
6815 return -ENOMEM;
6816
6817 pipe_config->base.crtc = &crtc->base;
6818 pipe_config->pixel_multiplier = 1;
6819 pipe_config->dpll = *dpll;
6820
6821 if (IS_CHERRYVIEW(dev_priv)) {
6822 chv_compute_dpll(crtc, pipe_config);
6823 chv_prepare_pll(crtc, pipe_config);
6824 chv_enable_pll(crtc, pipe_config);
6825 } else {
6826 vlv_compute_dpll(crtc, pipe_config);
6827 vlv_prepare_pll(crtc, pipe_config);
6828 vlv_enable_pll(crtc, pipe_config);
6829 }
6830
6831 kfree(pipe_config);
6832
6833 return 0;
6834 }
6835
6836 /**
6837 * vlv_force_pll_off - forcibly disable just the PLL
6838 * @dev_priv: i915 private structure
6839 * @pipe: pipe PLL to disable
6840 *
6841 * Disable the PLL for @pipe. To be used in cases where we need
6842 * the PLL enabled even when @pipe is not going to be enabled.
6843 */
6844 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6845 {
6846 if (IS_CHERRYVIEW(dev_priv))
6847 chv_disable_pll(dev_priv, pipe);
6848 else
6849 vlv_disable_pll(dev_priv, pipe);
6850 }
6851
6852 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6853 struct intel_crtc_state *crtc_state,
6854 struct dpll *reduced_clock)
6855 {
6856 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6857 u32 dpll;
6858 struct dpll *clock = &crtc_state->dpll;
6859
6860 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6861
6862 dpll = DPLL_VGA_MODE_DIS;
6863
6864 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6865 dpll |= DPLLB_MODE_LVDS;
6866 else
6867 dpll |= DPLLB_MODE_DAC_SERIAL;
6868
6869 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6870 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6871 dpll |= (crtc_state->pixel_multiplier - 1)
6872 << SDVO_MULTIPLIER_SHIFT_HIRES;
6873 }
6874
6875 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6876 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6877 dpll |= DPLL_SDVO_HIGH_SPEED;
6878
6879 if (intel_crtc_has_dp_encoder(crtc_state))
6880 dpll |= DPLL_SDVO_HIGH_SPEED;
6881
6882 /* compute bitmask from p1 value */
6883 if (IS_PINEVIEW(dev_priv))
6884 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6885 else {
6886 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6887 if (IS_G4X(dev_priv) && reduced_clock)
6888 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6889 }
6890 switch (clock->p2) {
6891 case 5:
6892 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6893 break;
6894 case 7:
6895 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6896 break;
6897 case 10:
6898 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6899 break;
6900 case 14:
6901 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6902 break;
6903 }
6904 if (INTEL_GEN(dev_priv) >= 4)
6905 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6906
6907 if (crtc_state->sdvo_tv_clock)
6908 dpll |= PLL_REF_INPUT_TVCLKINBC;
6909 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6910 intel_panel_use_ssc(dev_priv))
6911 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6912 else
6913 dpll |= PLL_REF_INPUT_DREFCLK;
6914
6915 dpll |= DPLL_VCO_ENABLE;
6916 crtc_state->dpll_hw_state.dpll = dpll;
6917
6918 if (INTEL_GEN(dev_priv) >= 4) {
6919 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6920 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6921 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6922 }
6923 }
6924
6925 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6926 struct intel_crtc_state *crtc_state,
6927 struct dpll *reduced_clock)
6928 {
6929 struct drm_device *dev = crtc->base.dev;
6930 struct drm_i915_private *dev_priv = to_i915(dev);
6931 u32 dpll;
6932 struct dpll *clock = &crtc_state->dpll;
6933
6934 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6935
6936 dpll = DPLL_VGA_MODE_DIS;
6937
6938 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6939 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6940 } else {
6941 if (clock->p1 == 2)
6942 dpll |= PLL_P1_DIVIDE_BY_TWO;
6943 else
6944 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6945 if (clock->p2 == 4)
6946 dpll |= PLL_P2_DIVIDE_BY_4;
6947 }
6948
6949 if (!IS_I830(dev_priv) &&
6950 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6951 dpll |= DPLL_DVO_2X_MODE;
6952
6953 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6954 intel_panel_use_ssc(dev_priv))
6955 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6956 else
6957 dpll |= PLL_REF_INPUT_DREFCLK;
6958
6959 dpll |= DPLL_VCO_ENABLE;
6960 crtc_state->dpll_hw_state.dpll = dpll;
6961 }
6962
6963 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6964 {
6965 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6966 enum pipe pipe = intel_crtc->pipe;
6967 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6968 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6969 uint32_t crtc_vtotal, crtc_vblank_end;
6970 int vsyncshift = 0;
6971
6972 /* We need to be careful not to changed the adjusted mode, for otherwise
6973 * the hw state checker will get angry at the mismatch. */
6974 crtc_vtotal = adjusted_mode->crtc_vtotal;
6975 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6976
6977 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6978 /* the chip adds 2 halflines automatically */
6979 crtc_vtotal -= 1;
6980 crtc_vblank_end -= 1;
6981
6982 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6983 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6984 else
6985 vsyncshift = adjusted_mode->crtc_hsync_start -
6986 adjusted_mode->crtc_htotal / 2;
6987 if (vsyncshift < 0)
6988 vsyncshift += adjusted_mode->crtc_htotal;
6989 }
6990
6991 if (INTEL_GEN(dev_priv) > 3)
6992 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6993
6994 I915_WRITE(HTOTAL(cpu_transcoder),
6995 (adjusted_mode->crtc_hdisplay - 1) |
6996 ((adjusted_mode->crtc_htotal - 1) << 16));
6997 I915_WRITE(HBLANK(cpu_transcoder),
6998 (adjusted_mode->crtc_hblank_start - 1) |
6999 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7000 I915_WRITE(HSYNC(cpu_transcoder),
7001 (adjusted_mode->crtc_hsync_start - 1) |
7002 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7003
7004 I915_WRITE(VTOTAL(cpu_transcoder),
7005 (adjusted_mode->crtc_vdisplay - 1) |
7006 ((crtc_vtotal - 1) << 16));
7007 I915_WRITE(VBLANK(cpu_transcoder),
7008 (adjusted_mode->crtc_vblank_start - 1) |
7009 ((crtc_vblank_end - 1) << 16));
7010 I915_WRITE(VSYNC(cpu_transcoder),
7011 (adjusted_mode->crtc_vsync_start - 1) |
7012 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7013
7014 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7015 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7016 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7017 * bits. */
7018 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7019 (pipe == PIPE_B || pipe == PIPE_C))
7020 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7021
7022 }
7023
7024 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7025 {
7026 struct drm_device *dev = intel_crtc->base.dev;
7027 struct drm_i915_private *dev_priv = to_i915(dev);
7028 enum pipe pipe = intel_crtc->pipe;
7029
7030 /* pipesrc controls the size that is scaled from, which should
7031 * always be the user's requested size.
7032 */
7033 I915_WRITE(PIPESRC(pipe),
7034 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7035 (intel_crtc->config->pipe_src_h - 1));
7036 }
7037
7038 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7039 struct intel_crtc_state *pipe_config)
7040 {
7041 struct drm_device *dev = crtc->base.dev;
7042 struct drm_i915_private *dev_priv = to_i915(dev);
7043 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7044 uint32_t tmp;
7045
7046 tmp = I915_READ(HTOTAL(cpu_transcoder));
7047 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7048 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7049 tmp = I915_READ(HBLANK(cpu_transcoder));
7050 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7051 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7052 tmp = I915_READ(HSYNC(cpu_transcoder));
7053 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7054 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7055
7056 tmp = I915_READ(VTOTAL(cpu_transcoder));
7057 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7058 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7059 tmp = I915_READ(VBLANK(cpu_transcoder));
7060 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7061 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7062 tmp = I915_READ(VSYNC(cpu_transcoder));
7063 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7064 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7065
7066 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7067 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7068 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7069 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7070 }
7071 }
7072
7073 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7074 struct intel_crtc_state *pipe_config)
7075 {
7076 struct drm_device *dev = crtc->base.dev;
7077 struct drm_i915_private *dev_priv = to_i915(dev);
7078 u32 tmp;
7079
7080 tmp = I915_READ(PIPESRC(crtc->pipe));
7081 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7082 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7083
7084 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7085 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7086 }
7087
7088 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7089 struct intel_crtc_state *pipe_config)
7090 {
7091 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7092 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7093 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7094 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7095
7096 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7097 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7098 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7099 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7100
7101 mode->flags = pipe_config->base.adjusted_mode.flags;
7102 mode->type = DRM_MODE_TYPE_DRIVER;
7103
7104 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7105
7106 mode->hsync = drm_mode_hsync(mode);
7107 mode->vrefresh = drm_mode_vrefresh(mode);
7108 drm_mode_set_name(mode);
7109 }
7110
7111 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7112 {
7113 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7114 uint32_t pipeconf;
7115
7116 pipeconf = 0;
7117
7118 /* we keep both pipes enabled on 830 */
7119 if (IS_I830(dev_priv))
7120 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7121
7122 if (intel_crtc->config->double_wide)
7123 pipeconf |= PIPECONF_DOUBLE_WIDE;
7124
7125 /* only g4x and later have fancy bpc/dither controls */
7126 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7127 IS_CHERRYVIEW(dev_priv)) {
7128 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7129 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7130 pipeconf |= PIPECONF_DITHER_EN |
7131 PIPECONF_DITHER_TYPE_SP;
7132
7133 switch (intel_crtc->config->pipe_bpp) {
7134 case 18:
7135 pipeconf |= PIPECONF_6BPC;
7136 break;
7137 case 24:
7138 pipeconf |= PIPECONF_8BPC;
7139 break;
7140 case 30:
7141 pipeconf |= PIPECONF_10BPC;
7142 break;
7143 default:
7144 /* Case prevented by intel_choose_pipe_bpp_dither. */
7145 BUG();
7146 }
7147 }
7148
7149 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7150 if (INTEL_GEN(dev_priv) < 4 ||
7151 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7152 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7153 else
7154 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7155 } else
7156 pipeconf |= PIPECONF_PROGRESSIVE;
7157
7158 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7159 intel_crtc->config->limited_color_range)
7160 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7161
7162 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7163 POSTING_READ(PIPECONF(intel_crtc->pipe));
7164 }
7165
7166 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7167 struct intel_crtc_state *crtc_state)
7168 {
7169 struct drm_device *dev = crtc->base.dev;
7170 struct drm_i915_private *dev_priv = to_i915(dev);
7171 const struct intel_limit *limit;
7172 int refclk = 48000;
7173
7174 memset(&crtc_state->dpll_hw_state, 0,
7175 sizeof(crtc_state->dpll_hw_state));
7176
7177 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7178 if (intel_panel_use_ssc(dev_priv)) {
7179 refclk = dev_priv->vbt.lvds_ssc_freq;
7180 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7181 }
7182
7183 limit = &intel_limits_i8xx_lvds;
7184 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7185 limit = &intel_limits_i8xx_dvo;
7186 } else {
7187 limit = &intel_limits_i8xx_dac;
7188 }
7189
7190 if (!crtc_state->clock_set &&
7191 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7192 refclk, NULL, &crtc_state->dpll)) {
7193 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7194 return -EINVAL;
7195 }
7196
7197 i8xx_compute_dpll(crtc, crtc_state, NULL);
7198
7199 return 0;
7200 }
7201
7202 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7203 struct intel_crtc_state *crtc_state)
7204 {
7205 struct drm_device *dev = crtc->base.dev;
7206 struct drm_i915_private *dev_priv = to_i915(dev);
7207 const struct intel_limit *limit;
7208 int refclk = 96000;
7209
7210 memset(&crtc_state->dpll_hw_state, 0,
7211 sizeof(crtc_state->dpll_hw_state));
7212
7213 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7214 if (intel_panel_use_ssc(dev_priv)) {
7215 refclk = dev_priv->vbt.lvds_ssc_freq;
7216 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7217 }
7218
7219 if (intel_is_dual_link_lvds(dev))
7220 limit = &intel_limits_g4x_dual_channel_lvds;
7221 else
7222 limit = &intel_limits_g4x_single_channel_lvds;
7223 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7224 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7225 limit = &intel_limits_g4x_hdmi;
7226 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7227 limit = &intel_limits_g4x_sdvo;
7228 } else {
7229 /* The option is for other outputs */
7230 limit = &intel_limits_i9xx_sdvo;
7231 }
7232
7233 if (!crtc_state->clock_set &&
7234 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7235 refclk, NULL, &crtc_state->dpll)) {
7236 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7237 return -EINVAL;
7238 }
7239
7240 i9xx_compute_dpll(crtc, crtc_state, NULL);
7241
7242 return 0;
7243 }
7244
7245 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7246 struct intel_crtc_state *crtc_state)
7247 {
7248 struct drm_device *dev = crtc->base.dev;
7249 struct drm_i915_private *dev_priv = to_i915(dev);
7250 const struct intel_limit *limit;
7251 int refclk = 96000;
7252
7253 memset(&crtc_state->dpll_hw_state, 0,
7254 sizeof(crtc_state->dpll_hw_state));
7255
7256 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7257 if (intel_panel_use_ssc(dev_priv)) {
7258 refclk = dev_priv->vbt.lvds_ssc_freq;
7259 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7260 }
7261
7262 limit = &intel_limits_pineview_lvds;
7263 } else {
7264 limit = &intel_limits_pineview_sdvo;
7265 }
7266
7267 if (!crtc_state->clock_set &&
7268 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7269 refclk, NULL, &crtc_state->dpll)) {
7270 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7271 return -EINVAL;
7272 }
7273
7274 i9xx_compute_dpll(crtc, crtc_state, NULL);
7275
7276 return 0;
7277 }
7278
7279 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7280 struct intel_crtc_state *crtc_state)
7281 {
7282 struct drm_device *dev = crtc->base.dev;
7283 struct drm_i915_private *dev_priv = to_i915(dev);
7284 const struct intel_limit *limit;
7285 int refclk = 96000;
7286
7287 memset(&crtc_state->dpll_hw_state, 0,
7288 sizeof(crtc_state->dpll_hw_state));
7289
7290 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7291 if (intel_panel_use_ssc(dev_priv)) {
7292 refclk = dev_priv->vbt.lvds_ssc_freq;
7293 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7294 }
7295
7296 limit = &intel_limits_i9xx_lvds;
7297 } else {
7298 limit = &intel_limits_i9xx_sdvo;
7299 }
7300
7301 if (!crtc_state->clock_set &&
7302 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7303 refclk, NULL, &crtc_state->dpll)) {
7304 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7305 return -EINVAL;
7306 }
7307
7308 i9xx_compute_dpll(crtc, crtc_state, NULL);
7309
7310 return 0;
7311 }
7312
7313 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7314 struct intel_crtc_state *crtc_state)
7315 {
7316 int refclk = 100000;
7317 const struct intel_limit *limit = &intel_limits_chv;
7318
7319 memset(&crtc_state->dpll_hw_state, 0,
7320 sizeof(crtc_state->dpll_hw_state));
7321
7322 if (!crtc_state->clock_set &&
7323 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7324 refclk, NULL, &crtc_state->dpll)) {
7325 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7326 return -EINVAL;
7327 }
7328
7329 chv_compute_dpll(crtc, crtc_state);
7330
7331 return 0;
7332 }
7333
7334 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7335 struct intel_crtc_state *crtc_state)
7336 {
7337 int refclk = 100000;
7338 const struct intel_limit *limit = &intel_limits_vlv;
7339
7340 memset(&crtc_state->dpll_hw_state, 0,
7341 sizeof(crtc_state->dpll_hw_state));
7342
7343 if (!crtc_state->clock_set &&
7344 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7345 refclk, NULL, &crtc_state->dpll)) {
7346 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7347 return -EINVAL;
7348 }
7349
7350 vlv_compute_dpll(crtc, crtc_state);
7351
7352 return 0;
7353 }
7354
7355 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7356 struct intel_crtc_state *pipe_config)
7357 {
7358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7359 uint32_t tmp;
7360
7361 if (INTEL_GEN(dev_priv) <= 3 &&
7362 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7363 return;
7364
7365 tmp = I915_READ(PFIT_CONTROL);
7366 if (!(tmp & PFIT_ENABLE))
7367 return;
7368
7369 /* Check whether the pfit is attached to our pipe. */
7370 if (INTEL_GEN(dev_priv) < 4) {
7371 if (crtc->pipe != PIPE_B)
7372 return;
7373 } else {
7374 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7375 return;
7376 }
7377
7378 pipe_config->gmch_pfit.control = tmp;
7379 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7380 }
7381
7382 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7383 struct intel_crtc_state *pipe_config)
7384 {
7385 struct drm_device *dev = crtc->base.dev;
7386 struct drm_i915_private *dev_priv = to_i915(dev);
7387 int pipe = pipe_config->cpu_transcoder;
7388 struct dpll clock;
7389 u32 mdiv;
7390 int refclk = 100000;
7391
7392 /* In case of DSI, DPLL will not be used */
7393 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7394 return;
7395
7396 mutex_lock(&dev_priv->sb_lock);
7397 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7398 mutex_unlock(&dev_priv->sb_lock);
7399
7400 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7401 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7402 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7403 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7404 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7405
7406 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7407 }
7408
7409 static void
7410 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7411 struct intel_initial_plane_config *plane_config)
7412 {
7413 struct drm_device *dev = crtc->base.dev;
7414 struct drm_i915_private *dev_priv = to_i915(dev);
7415 u32 val, base, offset;
7416 int pipe = crtc->pipe, plane = crtc->plane;
7417 int fourcc, pixel_format;
7418 unsigned int aligned_height;
7419 struct drm_framebuffer *fb;
7420 struct intel_framebuffer *intel_fb;
7421
7422 val = I915_READ(DSPCNTR(plane));
7423 if (!(val & DISPLAY_PLANE_ENABLE))
7424 return;
7425
7426 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7427 if (!intel_fb) {
7428 DRM_DEBUG_KMS("failed to alloc fb\n");
7429 return;
7430 }
7431
7432 fb = &intel_fb->base;
7433
7434 fb->dev = dev;
7435
7436 if (INTEL_GEN(dev_priv) >= 4) {
7437 if (val & DISPPLANE_TILED) {
7438 plane_config->tiling = I915_TILING_X;
7439 fb->modifier = I915_FORMAT_MOD_X_TILED;
7440 }
7441 }
7442
7443 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7444 fourcc = i9xx_format_to_fourcc(pixel_format);
7445 fb->format = drm_format_info(fourcc);
7446
7447 if (INTEL_GEN(dev_priv) >= 4) {
7448 if (plane_config->tiling)
7449 offset = I915_READ(DSPTILEOFF(plane));
7450 else
7451 offset = I915_READ(DSPLINOFF(plane));
7452 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7453 } else {
7454 base = I915_READ(DSPADDR(plane));
7455 }
7456 plane_config->base = base;
7457
7458 val = I915_READ(PIPESRC(pipe));
7459 fb->width = ((val >> 16) & 0xfff) + 1;
7460 fb->height = ((val >> 0) & 0xfff) + 1;
7461
7462 val = I915_READ(DSPSTRIDE(pipe));
7463 fb->pitches[0] = val & 0xffffffc0;
7464
7465 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7466
7467 plane_config->size = fb->pitches[0] * aligned_height;
7468
7469 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7470 pipe_name(pipe), plane, fb->width, fb->height,
7471 fb->format->cpp[0] * 8, base, fb->pitches[0],
7472 plane_config->size);
7473
7474 plane_config->fb = intel_fb;
7475 }
7476
7477 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7478 struct intel_crtc_state *pipe_config)
7479 {
7480 struct drm_device *dev = crtc->base.dev;
7481 struct drm_i915_private *dev_priv = to_i915(dev);
7482 int pipe = pipe_config->cpu_transcoder;
7483 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7484 struct dpll clock;
7485 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7486 int refclk = 100000;
7487
7488 /* In case of DSI, DPLL will not be used */
7489 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7490 return;
7491
7492 mutex_lock(&dev_priv->sb_lock);
7493 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7494 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7495 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7496 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7497 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7498 mutex_unlock(&dev_priv->sb_lock);
7499
7500 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7501 clock.m2 = (pll_dw0 & 0xff) << 22;
7502 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7503 clock.m2 |= pll_dw2 & 0x3fffff;
7504 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7505 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7506 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7507
7508 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7509 }
7510
7511 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7512 struct intel_crtc_state *pipe_config)
7513 {
7514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7515 enum intel_display_power_domain power_domain;
7516 uint32_t tmp;
7517 bool ret;
7518
7519 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7520 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7521 return false;
7522
7523 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7524 pipe_config->shared_dpll = NULL;
7525
7526 ret = false;
7527
7528 tmp = I915_READ(PIPECONF(crtc->pipe));
7529 if (!(tmp & PIPECONF_ENABLE))
7530 goto out;
7531
7532 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7533 IS_CHERRYVIEW(dev_priv)) {
7534 switch (tmp & PIPECONF_BPC_MASK) {
7535 case PIPECONF_6BPC:
7536 pipe_config->pipe_bpp = 18;
7537 break;
7538 case PIPECONF_8BPC:
7539 pipe_config->pipe_bpp = 24;
7540 break;
7541 case PIPECONF_10BPC:
7542 pipe_config->pipe_bpp = 30;
7543 break;
7544 default:
7545 break;
7546 }
7547 }
7548
7549 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7550 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7551 pipe_config->limited_color_range = true;
7552
7553 if (INTEL_GEN(dev_priv) < 4)
7554 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7555
7556 intel_get_pipe_timings(crtc, pipe_config);
7557 intel_get_pipe_src_size(crtc, pipe_config);
7558
7559 i9xx_get_pfit_config(crtc, pipe_config);
7560
7561 if (INTEL_GEN(dev_priv) >= 4) {
7562 /* No way to read it out on pipes B and C */
7563 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7564 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7565 else
7566 tmp = I915_READ(DPLL_MD(crtc->pipe));
7567 pipe_config->pixel_multiplier =
7568 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7569 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7570 pipe_config->dpll_hw_state.dpll_md = tmp;
7571 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7572 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7573 tmp = I915_READ(DPLL(crtc->pipe));
7574 pipe_config->pixel_multiplier =
7575 ((tmp & SDVO_MULTIPLIER_MASK)
7576 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7577 } else {
7578 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7579 * port and will be fixed up in the encoder->get_config
7580 * function. */
7581 pipe_config->pixel_multiplier = 1;
7582 }
7583 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7584 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7585 /*
7586 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7587 * on 830. Filter it out here so that we don't
7588 * report errors due to that.
7589 */
7590 if (IS_I830(dev_priv))
7591 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7592
7593 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7594 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7595 } else {
7596 /* Mask out read-only status bits. */
7597 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7598 DPLL_PORTC_READY_MASK |
7599 DPLL_PORTB_READY_MASK);
7600 }
7601
7602 if (IS_CHERRYVIEW(dev_priv))
7603 chv_crtc_clock_get(crtc, pipe_config);
7604 else if (IS_VALLEYVIEW(dev_priv))
7605 vlv_crtc_clock_get(crtc, pipe_config);
7606 else
7607 i9xx_crtc_clock_get(crtc, pipe_config);
7608
7609 /*
7610 * Normally the dotclock is filled in by the encoder .get_config()
7611 * but in case the pipe is enabled w/o any ports we need a sane
7612 * default.
7613 */
7614 pipe_config->base.adjusted_mode.crtc_clock =
7615 pipe_config->port_clock / pipe_config->pixel_multiplier;
7616
7617 ret = true;
7618
7619 out:
7620 intel_display_power_put(dev_priv, power_domain);
7621
7622 return ret;
7623 }
7624
7625 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7626 {
7627 struct intel_encoder *encoder;
7628 int i;
7629 u32 val, final;
7630 bool has_lvds = false;
7631 bool has_cpu_edp = false;
7632 bool has_panel = false;
7633 bool has_ck505 = false;
7634 bool can_ssc = false;
7635 bool using_ssc_source = false;
7636
7637 /* We need to take the global config into account */
7638 for_each_intel_encoder(&dev_priv->drm, encoder) {
7639 switch (encoder->type) {
7640 case INTEL_OUTPUT_LVDS:
7641 has_panel = true;
7642 has_lvds = true;
7643 break;
7644 case INTEL_OUTPUT_EDP:
7645 has_panel = true;
7646 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7647 has_cpu_edp = true;
7648 break;
7649 default:
7650 break;
7651 }
7652 }
7653
7654 if (HAS_PCH_IBX(dev_priv)) {
7655 has_ck505 = dev_priv->vbt.display_clock_mode;
7656 can_ssc = has_ck505;
7657 } else {
7658 has_ck505 = false;
7659 can_ssc = true;
7660 }
7661
7662 /* Check if any DPLLs are using the SSC source */
7663 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7664 u32 temp = I915_READ(PCH_DPLL(i));
7665
7666 if (!(temp & DPLL_VCO_ENABLE))
7667 continue;
7668
7669 if ((temp & PLL_REF_INPUT_MASK) ==
7670 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7671 using_ssc_source = true;
7672 break;
7673 }
7674 }
7675
7676 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7677 has_panel, has_lvds, has_ck505, using_ssc_source);
7678
7679 /* Ironlake: try to setup display ref clock before DPLL
7680 * enabling. This is only under driver's control after
7681 * PCH B stepping, previous chipset stepping should be
7682 * ignoring this setting.
7683 */
7684 val = I915_READ(PCH_DREF_CONTROL);
7685
7686 /* As we must carefully and slowly disable/enable each source in turn,
7687 * compute the final state we want first and check if we need to
7688 * make any changes at all.
7689 */
7690 final = val;
7691 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7692 if (has_ck505)
7693 final |= DREF_NONSPREAD_CK505_ENABLE;
7694 else
7695 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7696
7697 final &= ~DREF_SSC_SOURCE_MASK;
7698 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7699 final &= ~DREF_SSC1_ENABLE;
7700
7701 if (has_panel) {
7702 final |= DREF_SSC_SOURCE_ENABLE;
7703
7704 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7705 final |= DREF_SSC1_ENABLE;
7706
7707 if (has_cpu_edp) {
7708 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7709 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7710 else
7711 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7712 } else
7713 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7714 } else if (using_ssc_source) {
7715 final |= DREF_SSC_SOURCE_ENABLE;
7716 final |= DREF_SSC1_ENABLE;
7717 }
7718
7719 if (final == val)
7720 return;
7721
7722 /* Always enable nonspread source */
7723 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7724
7725 if (has_ck505)
7726 val |= DREF_NONSPREAD_CK505_ENABLE;
7727 else
7728 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7729
7730 if (has_panel) {
7731 val &= ~DREF_SSC_SOURCE_MASK;
7732 val |= DREF_SSC_SOURCE_ENABLE;
7733
7734 /* SSC must be turned on before enabling the CPU output */
7735 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7736 DRM_DEBUG_KMS("Using SSC on panel\n");
7737 val |= DREF_SSC1_ENABLE;
7738 } else
7739 val &= ~DREF_SSC1_ENABLE;
7740
7741 /* Get SSC going before enabling the outputs */
7742 I915_WRITE(PCH_DREF_CONTROL, val);
7743 POSTING_READ(PCH_DREF_CONTROL);
7744 udelay(200);
7745
7746 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7747
7748 /* Enable CPU source on CPU attached eDP */
7749 if (has_cpu_edp) {
7750 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7751 DRM_DEBUG_KMS("Using SSC on eDP\n");
7752 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7753 } else
7754 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7755 } else
7756 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7757
7758 I915_WRITE(PCH_DREF_CONTROL, val);
7759 POSTING_READ(PCH_DREF_CONTROL);
7760 udelay(200);
7761 } else {
7762 DRM_DEBUG_KMS("Disabling CPU source output\n");
7763
7764 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7765
7766 /* Turn off CPU output */
7767 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7768
7769 I915_WRITE(PCH_DREF_CONTROL, val);
7770 POSTING_READ(PCH_DREF_CONTROL);
7771 udelay(200);
7772
7773 if (!using_ssc_source) {
7774 DRM_DEBUG_KMS("Disabling SSC source\n");
7775
7776 /* Turn off the SSC source */
7777 val &= ~DREF_SSC_SOURCE_MASK;
7778 val |= DREF_SSC_SOURCE_DISABLE;
7779
7780 /* Turn off SSC1 */
7781 val &= ~DREF_SSC1_ENABLE;
7782
7783 I915_WRITE(PCH_DREF_CONTROL, val);
7784 POSTING_READ(PCH_DREF_CONTROL);
7785 udelay(200);
7786 }
7787 }
7788
7789 BUG_ON(val != final);
7790 }
7791
7792 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7793 {
7794 uint32_t tmp;
7795
7796 tmp = I915_READ(SOUTH_CHICKEN2);
7797 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7798 I915_WRITE(SOUTH_CHICKEN2, tmp);
7799
7800 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7801 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7802 DRM_ERROR("FDI mPHY reset assert timeout\n");
7803
7804 tmp = I915_READ(SOUTH_CHICKEN2);
7805 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7806 I915_WRITE(SOUTH_CHICKEN2, tmp);
7807
7808 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7809 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7810 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7811 }
7812
7813 /* WaMPhyProgramming:hsw */
7814 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7815 {
7816 uint32_t tmp;
7817
7818 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7819 tmp &= ~(0xFF << 24);
7820 tmp |= (0x12 << 24);
7821 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7822
7823 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7824 tmp |= (1 << 11);
7825 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7826
7827 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7828 tmp |= (1 << 11);
7829 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7830
7831 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7832 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7833 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7834
7835 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7836 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7837 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7838
7839 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7840 tmp &= ~(7 << 13);
7841 tmp |= (5 << 13);
7842 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7843
7844 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7845 tmp &= ~(7 << 13);
7846 tmp |= (5 << 13);
7847 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7848
7849 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7850 tmp &= ~0xFF;
7851 tmp |= 0x1C;
7852 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7853
7854 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7855 tmp &= ~0xFF;
7856 tmp |= 0x1C;
7857 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7858
7859 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7860 tmp &= ~(0xFF << 16);
7861 tmp |= (0x1C << 16);
7862 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7863
7864 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7865 tmp &= ~(0xFF << 16);
7866 tmp |= (0x1C << 16);
7867 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7868
7869 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7870 tmp |= (1 << 27);
7871 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7872
7873 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7874 tmp |= (1 << 27);
7875 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7876
7877 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7878 tmp &= ~(0xF << 28);
7879 tmp |= (4 << 28);
7880 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7881
7882 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7883 tmp &= ~(0xF << 28);
7884 tmp |= (4 << 28);
7885 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7886 }
7887
7888 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7889 * Programming" based on the parameters passed:
7890 * - Sequence to enable CLKOUT_DP
7891 * - Sequence to enable CLKOUT_DP without spread
7892 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7893 */
7894 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7895 bool with_spread, bool with_fdi)
7896 {
7897 uint32_t reg, tmp;
7898
7899 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7900 with_spread = true;
7901 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7902 with_fdi, "LP PCH doesn't have FDI\n"))
7903 with_fdi = false;
7904
7905 mutex_lock(&dev_priv->sb_lock);
7906
7907 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7908 tmp &= ~SBI_SSCCTL_DISABLE;
7909 tmp |= SBI_SSCCTL_PATHALT;
7910 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7911
7912 udelay(24);
7913
7914 if (with_spread) {
7915 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7916 tmp &= ~SBI_SSCCTL_PATHALT;
7917 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7918
7919 if (with_fdi) {
7920 lpt_reset_fdi_mphy(dev_priv);
7921 lpt_program_fdi_mphy(dev_priv);
7922 }
7923 }
7924
7925 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7926 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7927 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7928 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7929
7930 mutex_unlock(&dev_priv->sb_lock);
7931 }
7932
7933 /* Sequence to disable CLKOUT_DP */
7934 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7935 {
7936 uint32_t reg, tmp;
7937
7938 mutex_lock(&dev_priv->sb_lock);
7939
7940 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7941 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7942 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7943 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7944
7945 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7946 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7947 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7948 tmp |= SBI_SSCCTL_PATHALT;
7949 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7950 udelay(32);
7951 }
7952 tmp |= SBI_SSCCTL_DISABLE;
7953 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7954 }
7955
7956 mutex_unlock(&dev_priv->sb_lock);
7957 }
7958
7959 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7960
7961 static const uint16_t sscdivintphase[] = {
7962 [BEND_IDX( 50)] = 0x3B23,
7963 [BEND_IDX( 45)] = 0x3B23,
7964 [BEND_IDX( 40)] = 0x3C23,
7965 [BEND_IDX( 35)] = 0x3C23,
7966 [BEND_IDX( 30)] = 0x3D23,
7967 [BEND_IDX( 25)] = 0x3D23,
7968 [BEND_IDX( 20)] = 0x3E23,
7969 [BEND_IDX( 15)] = 0x3E23,
7970 [BEND_IDX( 10)] = 0x3F23,
7971 [BEND_IDX( 5)] = 0x3F23,
7972 [BEND_IDX( 0)] = 0x0025,
7973 [BEND_IDX( -5)] = 0x0025,
7974 [BEND_IDX(-10)] = 0x0125,
7975 [BEND_IDX(-15)] = 0x0125,
7976 [BEND_IDX(-20)] = 0x0225,
7977 [BEND_IDX(-25)] = 0x0225,
7978 [BEND_IDX(-30)] = 0x0325,
7979 [BEND_IDX(-35)] = 0x0325,
7980 [BEND_IDX(-40)] = 0x0425,
7981 [BEND_IDX(-45)] = 0x0425,
7982 [BEND_IDX(-50)] = 0x0525,
7983 };
7984
7985 /*
7986 * Bend CLKOUT_DP
7987 * steps -50 to 50 inclusive, in steps of 5
7988 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7989 * change in clock period = -(steps / 10) * 5.787 ps
7990 */
7991 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7992 {
7993 uint32_t tmp;
7994 int idx = BEND_IDX(steps);
7995
7996 if (WARN_ON(steps % 5 != 0))
7997 return;
7998
7999 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8000 return;
8001
8002 mutex_lock(&dev_priv->sb_lock);
8003
8004 if (steps % 10 != 0)
8005 tmp = 0xAAAAAAAB;
8006 else
8007 tmp = 0x00000000;
8008 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8009
8010 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8011 tmp &= 0xffff0000;
8012 tmp |= sscdivintphase[idx];
8013 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8014
8015 mutex_unlock(&dev_priv->sb_lock);
8016 }
8017
8018 #undef BEND_IDX
8019
8020 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8021 {
8022 struct intel_encoder *encoder;
8023 bool has_vga = false;
8024
8025 for_each_intel_encoder(&dev_priv->drm, encoder) {
8026 switch (encoder->type) {
8027 case INTEL_OUTPUT_ANALOG:
8028 has_vga = true;
8029 break;
8030 default:
8031 break;
8032 }
8033 }
8034
8035 if (has_vga) {
8036 lpt_bend_clkout_dp(dev_priv, 0);
8037 lpt_enable_clkout_dp(dev_priv, true, true);
8038 } else {
8039 lpt_disable_clkout_dp(dev_priv);
8040 }
8041 }
8042
8043 /*
8044 * Initialize reference clocks when the driver loads
8045 */
8046 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8047 {
8048 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8049 ironlake_init_pch_refclk(dev_priv);
8050 else if (HAS_PCH_LPT(dev_priv))
8051 lpt_init_pch_refclk(dev_priv);
8052 }
8053
8054 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8055 {
8056 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8058 int pipe = intel_crtc->pipe;
8059 uint32_t val;
8060
8061 val = 0;
8062
8063 switch (intel_crtc->config->pipe_bpp) {
8064 case 18:
8065 val |= PIPECONF_6BPC;
8066 break;
8067 case 24:
8068 val |= PIPECONF_8BPC;
8069 break;
8070 case 30:
8071 val |= PIPECONF_10BPC;
8072 break;
8073 case 36:
8074 val |= PIPECONF_12BPC;
8075 break;
8076 default:
8077 /* Case prevented by intel_choose_pipe_bpp_dither. */
8078 BUG();
8079 }
8080
8081 if (intel_crtc->config->dither)
8082 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8083
8084 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8085 val |= PIPECONF_INTERLACED_ILK;
8086 else
8087 val |= PIPECONF_PROGRESSIVE;
8088
8089 if (intel_crtc->config->limited_color_range)
8090 val |= PIPECONF_COLOR_RANGE_SELECT;
8091
8092 I915_WRITE(PIPECONF(pipe), val);
8093 POSTING_READ(PIPECONF(pipe));
8094 }
8095
8096 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8097 {
8098 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8100 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8101 u32 val = 0;
8102
8103 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8104 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8105
8106 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8107 val |= PIPECONF_INTERLACED_ILK;
8108 else
8109 val |= PIPECONF_PROGRESSIVE;
8110
8111 I915_WRITE(PIPECONF(cpu_transcoder), val);
8112 POSTING_READ(PIPECONF(cpu_transcoder));
8113 }
8114
8115 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8116 {
8117 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8119 struct intel_crtc_state *config = intel_crtc->config;
8120
8121 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8122 u32 val = 0;
8123
8124 switch (intel_crtc->config->pipe_bpp) {
8125 case 18:
8126 val |= PIPEMISC_DITHER_6_BPC;
8127 break;
8128 case 24:
8129 val |= PIPEMISC_DITHER_8_BPC;
8130 break;
8131 case 30:
8132 val |= PIPEMISC_DITHER_10_BPC;
8133 break;
8134 case 36:
8135 val |= PIPEMISC_DITHER_12_BPC;
8136 break;
8137 default:
8138 /* Case prevented by pipe_config_set_bpp. */
8139 BUG();
8140 }
8141
8142 if (intel_crtc->config->dither)
8143 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8144
8145 if (config->ycbcr420) {
8146 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8147 PIPEMISC_YUV420_ENABLE |
8148 PIPEMISC_YUV420_MODE_FULL_BLEND;
8149 }
8150
8151 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8152 }
8153 }
8154
8155 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8156 {
8157 /*
8158 * Account for spread spectrum to avoid
8159 * oversubscribing the link. Max center spread
8160 * is 2.5%; use 5% for safety's sake.
8161 */
8162 u32 bps = target_clock * bpp * 21 / 20;
8163 return DIV_ROUND_UP(bps, link_bw * 8);
8164 }
8165
8166 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8167 {
8168 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8169 }
8170
8171 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8172 struct intel_crtc_state *crtc_state,
8173 struct dpll *reduced_clock)
8174 {
8175 struct drm_crtc *crtc = &intel_crtc->base;
8176 struct drm_device *dev = crtc->dev;
8177 struct drm_i915_private *dev_priv = to_i915(dev);
8178 u32 dpll, fp, fp2;
8179 int factor;
8180
8181 /* Enable autotuning of the PLL clock (if permissible) */
8182 factor = 21;
8183 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8184 if ((intel_panel_use_ssc(dev_priv) &&
8185 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8186 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8187 factor = 25;
8188 } else if (crtc_state->sdvo_tv_clock)
8189 factor = 20;
8190
8191 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8192
8193 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8194 fp |= FP_CB_TUNE;
8195
8196 if (reduced_clock) {
8197 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8198
8199 if (reduced_clock->m < factor * reduced_clock->n)
8200 fp2 |= FP_CB_TUNE;
8201 } else {
8202 fp2 = fp;
8203 }
8204
8205 dpll = 0;
8206
8207 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8208 dpll |= DPLLB_MODE_LVDS;
8209 else
8210 dpll |= DPLLB_MODE_DAC_SERIAL;
8211
8212 dpll |= (crtc_state->pixel_multiplier - 1)
8213 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8214
8215 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8216 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8217 dpll |= DPLL_SDVO_HIGH_SPEED;
8218
8219 if (intel_crtc_has_dp_encoder(crtc_state))
8220 dpll |= DPLL_SDVO_HIGH_SPEED;
8221
8222 /*
8223 * The high speed IO clock is only really required for
8224 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8225 * possible to share the DPLL between CRT and HDMI. Enabling
8226 * the clock needlessly does no real harm, except use up a
8227 * bit of power potentially.
8228 *
8229 * We'll limit this to IVB with 3 pipes, since it has only two
8230 * DPLLs and so DPLL sharing is the only way to get three pipes
8231 * driving PCH ports at the same time. On SNB we could do this,
8232 * and potentially avoid enabling the second DPLL, but it's not
8233 * clear if it''s a win or loss power wise. No point in doing
8234 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8235 */
8236 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8237 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8238 dpll |= DPLL_SDVO_HIGH_SPEED;
8239
8240 /* compute bitmask from p1 value */
8241 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8242 /* also FPA1 */
8243 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8244
8245 switch (crtc_state->dpll.p2) {
8246 case 5:
8247 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8248 break;
8249 case 7:
8250 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8251 break;
8252 case 10:
8253 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8254 break;
8255 case 14:
8256 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8257 break;
8258 }
8259
8260 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8261 intel_panel_use_ssc(dev_priv))
8262 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8263 else
8264 dpll |= PLL_REF_INPUT_DREFCLK;
8265
8266 dpll |= DPLL_VCO_ENABLE;
8267
8268 crtc_state->dpll_hw_state.dpll = dpll;
8269 crtc_state->dpll_hw_state.fp0 = fp;
8270 crtc_state->dpll_hw_state.fp1 = fp2;
8271 }
8272
8273 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8274 struct intel_crtc_state *crtc_state)
8275 {
8276 struct drm_device *dev = crtc->base.dev;
8277 struct drm_i915_private *dev_priv = to_i915(dev);
8278 const struct intel_limit *limit;
8279 int refclk = 120000;
8280
8281 memset(&crtc_state->dpll_hw_state, 0,
8282 sizeof(crtc_state->dpll_hw_state));
8283
8284 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8285 if (!crtc_state->has_pch_encoder)
8286 return 0;
8287
8288 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8289 if (intel_panel_use_ssc(dev_priv)) {
8290 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8291 dev_priv->vbt.lvds_ssc_freq);
8292 refclk = dev_priv->vbt.lvds_ssc_freq;
8293 }
8294
8295 if (intel_is_dual_link_lvds(dev)) {
8296 if (refclk == 100000)
8297 limit = &intel_limits_ironlake_dual_lvds_100m;
8298 else
8299 limit = &intel_limits_ironlake_dual_lvds;
8300 } else {
8301 if (refclk == 100000)
8302 limit = &intel_limits_ironlake_single_lvds_100m;
8303 else
8304 limit = &intel_limits_ironlake_single_lvds;
8305 }
8306 } else {
8307 limit = &intel_limits_ironlake_dac;
8308 }
8309
8310 if (!crtc_state->clock_set &&
8311 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8312 refclk, NULL, &crtc_state->dpll)) {
8313 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8314 return -EINVAL;
8315 }
8316
8317 ironlake_compute_dpll(crtc, crtc_state, NULL);
8318
8319 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8320 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8321 pipe_name(crtc->pipe));
8322 return -EINVAL;
8323 }
8324
8325 return 0;
8326 }
8327
8328 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8329 struct intel_link_m_n *m_n)
8330 {
8331 struct drm_device *dev = crtc->base.dev;
8332 struct drm_i915_private *dev_priv = to_i915(dev);
8333 enum pipe pipe = crtc->pipe;
8334
8335 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8336 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8337 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8338 & ~TU_SIZE_MASK;
8339 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8340 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8341 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8342 }
8343
8344 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8345 enum transcoder transcoder,
8346 struct intel_link_m_n *m_n,
8347 struct intel_link_m_n *m2_n2)
8348 {
8349 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8350 enum pipe pipe = crtc->pipe;
8351
8352 if (INTEL_GEN(dev_priv) >= 5) {
8353 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8354 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8355 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8356 & ~TU_SIZE_MASK;
8357 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8358 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8359 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8360 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8361 * gen < 8) and if DRRS is supported (to make sure the
8362 * registers are not unnecessarily read).
8363 */
8364 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8365 crtc->config->has_drrs) {
8366 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8367 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8368 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8369 & ~TU_SIZE_MASK;
8370 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8371 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8372 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8373 }
8374 } else {
8375 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8376 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8377 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8378 & ~TU_SIZE_MASK;
8379 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8380 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8381 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8382 }
8383 }
8384
8385 void intel_dp_get_m_n(struct intel_crtc *crtc,
8386 struct intel_crtc_state *pipe_config)
8387 {
8388 if (pipe_config->has_pch_encoder)
8389 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8390 else
8391 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8392 &pipe_config->dp_m_n,
8393 &pipe_config->dp_m2_n2);
8394 }
8395
8396 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8397 struct intel_crtc_state *pipe_config)
8398 {
8399 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8400 &pipe_config->fdi_m_n, NULL);
8401 }
8402
8403 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8404 struct intel_crtc_state *pipe_config)
8405 {
8406 struct drm_device *dev = crtc->base.dev;
8407 struct drm_i915_private *dev_priv = to_i915(dev);
8408 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8409 uint32_t ps_ctrl = 0;
8410 int id = -1;
8411 int i;
8412
8413 /* find scaler attached to this pipe */
8414 for (i = 0; i < crtc->num_scalers; i++) {
8415 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8416 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8417 id = i;
8418 pipe_config->pch_pfit.enabled = true;
8419 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8420 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8421 break;
8422 }
8423 }
8424
8425 scaler_state->scaler_id = id;
8426 if (id >= 0) {
8427 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8428 } else {
8429 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8430 }
8431 }
8432
8433 static void
8434 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8435 struct intel_initial_plane_config *plane_config)
8436 {
8437 struct drm_device *dev = crtc->base.dev;
8438 struct drm_i915_private *dev_priv = to_i915(dev);
8439 u32 val, base, offset, stride_mult, tiling;
8440 int pipe = crtc->pipe;
8441 int fourcc, pixel_format;
8442 unsigned int aligned_height;
8443 struct drm_framebuffer *fb;
8444 struct intel_framebuffer *intel_fb;
8445
8446 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8447 if (!intel_fb) {
8448 DRM_DEBUG_KMS("failed to alloc fb\n");
8449 return;
8450 }
8451
8452 fb = &intel_fb->base;
8453
8454 fb->dev = dev;
8455
8456 val = I915_READ(PLANE_CTL(pipe, 0));
8457 if (!(val & PLANE_CTL_ENABLE))
8458 goto error;
8459
8460 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8461 fourcc = skl_format_to_fourcc(pixel_format,
8462 val & PLANE_CTL_ORDER_RGBX,
8463 val & PLANE_CTL_ALPHA_MASK);
8464 fb->format = drm_format_info(fourcc);
8465
8466 tiling = val & PLANE_CTL_TILED_MASK;
8467 switch (tiling) {
8468 case PLANE_CTL_TILED_LINEAR:
8469 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8470 break;
8471 case PLANE_CTL_TILED_X:
8472 plane_config->tiling = I915_TILING_X;
8473 fb->modifier = I915_FORMAT_MOD_X_TILED;
8474 break;
8475 case PLANE_CTL_TILED_Y:
8476 plane_config->tiling = I915_TILING_Y;
8477 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8478 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8479 else
8480 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8481 break;
8482 case PLANE_CTL_TILED_YF:
8483 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8484 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8485 else
8486 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8487 break;
8488 default:
8489 MISSING_CASE(tiling);
8490 goto error;
8491 }
8492
8493 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8494 plane_config->base = base;
8495
8496 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8497
8498 val = I915_READ(PLANE_SIZE(pipe, 0));
8499 fb->height = ((val >> 16) & 0xfff) + 1;
8500 fb->width = ((val >> 0) & 0x1fff) + 1;
8501
8502 val = I915_READ(PLANE_STRIDE(pipe, 0));
8503 stride_mult = intel_fb_stride_alignment(fb, 0);
8504 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8505
8506 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8507
8508 plane_config->size = fb->pitches[0] * aligned_height;
8509
8510 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8511 pipe_name(pipe), fb->width, fb->height,
8512 fb->format->cpp[0] * 8, base, fb->pitches[0],
8513 plane_config->size);
8514
8515 plane_config->fb = intel_fb;
8516 return;
8517
8518 error:
8519 kfree(intel_fb);
8520 }
8521
8522 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8523 struct intel_crtc_state *pipe_config)
8524 {
8525 struct drm_device *dev = crtc->base.dev;
8526 struct drm_i915_private *dev_priv = to_i915(dev);
8527 uint32_t tmp;
8528
8529 tmp = I915_READ(PF_CTL(crtc->pipe));
8530
8531 if (tmp & PF_ENABLE) {
8532 pipe_config->pch_pfit.enabled = true;
8533 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8534 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8535
8536 /* We currently do not free assignements of panel fitters on
8537 * ivb/hsw (since we don't use the higher upscaling modes which
8538 * differentiates them) so just WARN about this case for now. */
8539 if (IS_GEN7(dev_priv)) {
8540 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8541 PF_PIPE_SEL_IVB(crtc->pipe));
8542 }
8543 }
8544 }
8545
8546 static void
8547 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8548 struct intel_initial_plane_config *plane_config)
8549 {
8550 struct drm_device *dev = crtc->base.dev;
8551 struct drm_i915_private *dev_priv = to_i915(dev);
8552 u32 val, base, offset;
8553 int pipe = crtc->pipe;
8554 int fourcc, pixel_format;
8555 unsigned int aligned_height;
8556 struct drm_framebuffer *fb;
8557 struct intel_framebuffer *intel_fb;
8558
8559 val = I915_READ(DSPCNTR(pipe));
8560 if (!(val & DISPLAY_PLANE_ENABLE))
8561 return;
8562
8563 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8564 if (!intel_fb) {
8565 DRM_DEBUG_KMS("failed to alloc fb\n");
8566 return;
8567 }
8568
8569 fb = &intel_fb->base;
8570
8571 fb->dev = dev;
8572
8573 if (INTEL_GEN(dev_priv) >= 4) {
8574 if (val & DISPPLANE_TILED) {
8575 plane_config->tiling = I915_TILING_X;
8576 fb->modifier = I915_FORMAT_MOD_X_TILED;
8577 }
8578 }
8579
8580 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8581 fourcc = i9xx_format_to_fourcc(pixel_format);
8582 fb->format = drm_format_info(fourcc);
8583
8584 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8585 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8586 offset = I915_READ(DSPOFFSET(pipe));
8587 } else {
8588 if (plane_config->tiling)
8589 offset = I915_READ(DSPTILEOFF(pipe));
8590 else
8591 offset = I915_READ(DSPLINOFF(pipe));
8592 }
8593 plane_config->base = base;
8594
8595 val = I915_READ(PIPESRC(pipe));
8596 fb->width = ((val >> 16) & 0xfff) + 1;
8597 fb->height = ((val >> 0) & 0xfff) + 1;
8598
8599 val = I915_READ(DSPSTRIDE(pipe));
8600 fb->pitches[0] = val & 0xffffffc0;
8601
8602 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8603
8604 plane_config->size = fb->pitches[0] * aligned_height;
8605
8606 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8607 pipe_name(pipe), fb->width, fb->height,
8608 fb->format->cpp[0] * 8, base, fb->pitches[0],
8609 plane_config->size);
8610
8611 plane_config->fb = intel_fb;
8612 }
8613
8614 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8615 struct intel_crtc_state *pipe_config)
8616 {
8617 struct drm_device *dev = crtc->base.dev;
8618 struct drm_i915_private *dev_priv = to_i915(dev);
8619 enum intel_display_power_domain power_domain;
8620 uint32_t tmp;
8621 bool ret;
8622
8623 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8624 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8625 return false;
8626
8627 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8628 pipe_config->shared_dpll = NULL;
8629
8630 ret = false;
8631 tmp = I915_READ(PIPECONF(crtc->pipe));
8632 if (!(tmp & PIPECONF_ENABLE))
8633 goto out;
8634
8635 switch (tmp & PIPECONF_BPC_MASK) {
8636 case PIPECONF_6BPC:
8637 pipe_config->pipe_bpp = 18;
8638 break;
8639 case PIPECONF_8BPC:
8640 pipe_config->pipe_bpp = 24;
8641 break;
8642 case PIPECONF_10BPC:
8643 pipe_config->pipe_bpp = 30;
8644 break;
8645 case PIPECONF_12BPC:
8646 pipe_config->pipe_bpp = 36;
8647 break;
8648 default:
8649 break;
8650 }
8651
8652 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8653 pipe_config->limited_color_range = true;
8654
8655 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8656 struct intel_shared_dpll *pll;
8657 enum intel_dpll_id pll_id;
8658
8659 pipe_config->has_pch_encoder = true;
8660
8661 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8662 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8663 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8664
8665 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8666
8667 if (HAS_PCH_IBX(dev_priv)) {
8668 /*
8669 * The pipe->pch transcoder and pch transcoder->pll
8670 * mapping is fixed.
8671 */
8672 pll_id = (enum intel_dpll_id) crtc->pipe;
8673 } else {
8674 tmp = I915_READ(PCH_DPLL_SEL);
8675 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8676 pll_id = DPLL_ID_PCH_PLL_B;
8677 else
8678 pll_id= DPLL_ID_PCH_PLL_A;
8679 }
8680
8681 pipe_config->shared_dpll =
8682 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8683 pll = pipe_config->shared_dpll;
8684
8685 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8686 &pipe_config->dpll_hw_state));
8687
8688 tmp = pipe_config->dpll_hw_state.dpll;
8689 pipe_config->pixel_multiplier =
8690 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8691 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8692
8693 ironlake_pch_clock_get(crtc, pipe_config);
8694 } else {
8695 pipe_config->pixel_multiplier = 1;
8696 }
8697
8698 intel_get_pipe_timings(crtc, pipe_config);
8699 intel_get_pipe_src_size(crtc, pipe_config);
8700
8701 ironlake_get_pfit_config(crtc, pipe_config);
8702
8703 ret = true;
8704
8705 out:
8706 intel_display_power_put(dev_priv, power_domain);
8707
8708 return ret;
8709 }
8710
8711 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8712 {
8713 struct drm_device *dev = &dev_priv->drm;
8714 struct intel_crtc *crtc;
8715
8716 for_each_intel_crtc(dev, crtc)
8717 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8718 pipe_name(crtc->pipe));
8719
8720 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8721 "Display power well on\n");
8722 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8723 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8724 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8725 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8726 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8727 "CPU PWM1 enabled\n");
8728 if (IS_HASWELL(dev_priv))
8729 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8730 "CPU PWM2 enabled\n");
8731 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8732 "PCH PWM1 enabled\n");
8733 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8734 "Utility pin enabled\n");
8735 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8736
8737 /*
8738 * In theory we can still leave IRQs enabled, as long as only the HPD
8739 * interrupts remain enabled. We used to check for that, but since it's
8740 * gen-specific and since we only disable LCPLL after we fully disable
8741 * the interrupts, the check below should be enough.
8742 */
8743 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8744 }
8745
8746 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8747 {
8748 if (IS_HASWELL(dev_priv))
8749 return I915_READ(D_COMP_HSW);
8750 else
8751 return I915_READ(D_COMP_BDW);
8752 }
8753
8754 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8755 {
8756 if (IS_HASWELL(dev_priv)) {
8757 mutex_lock(&dev_priv->pcu_lock);
8758 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8759 val))
8760 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8761 mutex_unlock(&dev_priv->pcu_lock);
8762 } else {
8763 I915_WRITE(D_COMP_BDW, val);
8764 POSTING_READ(D_COMP_BDW);
8765 }
8766 }
8767
8768 /*
8769 * This function implements pieces of two sequences from BSpec:
8770 * - Sequence for display software to disable LCPLL
8771 * - Sequence for display software to allow package C8+
8772 * The steps implemented here are just the steps that actually touch the LCPLL
8773 * register. Callers should take care of disabling all the display engine
8774 * functions, doing the mode unset, fixing interrupts, etc.
8775 */
8776 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8777 bool switch_to_fclk, bool allow_power_down)
8778 {
8779 uint32_t val;
8780
8781 assert_can_disable_lcpll(dev_priv);
8782
8783 val = I915_READ(LCPLL_CTL);
8784
8785 if (switch_to_fclk) {
8786 val |= LCPLL_CD_SOURCE_FCLK;
8787 I915_WRITE(LCPLL_CTL, val);
8788
8789 if (wait_for_us(I915_READ(LCPLL_CTL) &
8790 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8791 DRM_ERROR("Switching to FCLK failed\n");
8792
8793 val = I915_READ(LCPLL_CTL);
8794 }
8795
8796 val |= LCPLL_PLL_DISABLE;
8797 I915_WRITE(LCPLL_CTL, val);
8798 POSTING_READ(LCPLL_CTL);
8799
8800 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8801 DRM_ERROR("LCPLL still locked\n");
8802
8803 val = hsw_read_dcomp(dev_priv);
8804 val |= D_COMP_COMP_DISABLE;
8805 hsw_write_dcomp(dev_priv, val);
8806 ndelay(100);
8807
8808 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8809 1))
8810 DRM_ERROR("D_COMP RCOMP still in progress\n");
8811
8812 if (allow_power_down) {
8813 val = I915_READ(LCPLL_CTL);
8814 val |= LCPLL_POWER_DOWN_ALLOW;
8815 I915_WRITE(LCPLL_CTL, val);
8816 POSTING_READ(LCPLL_CTL);
8817 }
8818 }
8819
8820 /*
8821 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8822 * source.
8823 */
8824 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8825 {
8826 uint32_t val;
8827
8828 val = I915_READ(LCPLL_CTL);
8829
8830 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8831 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8832 return;
8833
8834 /*
8835 * Make sure we're not on PC8 state before disabling PC8, otherwise
8836 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8837 */
8838 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8839
8840 if (val & LCPLL_POWER_DOWN_ALLOW) {
8841 val &= ~LCPLL_POWER_DOWN_ALLOW;
8842 I915_WRITE(LCPLL_CTL, val);
8843 POSTING_READ(LCPLL_CTL);
8844 }
8845
8846 val = hsw_read_dcomp(dev_priv);
8847 val |= D_COMP_COMP_FORCE;
8848 val &= ~D_COMP_COMP_DISABLE;
8849 hsw_write_dcomp(dev_priv, val);
8850
8851 val = I915_READ(LCPLL_CTL);
8852 val &= ~LCPLL_PLL_DISABLE;
8853 I915_WRITE(LCPLL_CTL, val);
8854
8855 if (intel_wait_for_register(dev_priv,
8856 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8857 5))
8858 DRM_ERROR("LCPLL not locked yet\n");
8859
8860 if (val & LCPLL_CD_SOURCE_FCLK) {
8861 val = I915_READ(LCPLL_CTL);
8862 val &= ~LCPLL_CD_SOURCE_FCLK;
8863 I915_WRITE(LCPLL_CTL, val);
8864
8865 if (wait_for_us((I915_READ(LCPLL_CTL) &
8866 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8867 DRM_ERROR("Switching back to LCPLL failed\n");
8868 }
8869
8870 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8871 intel_update_cdclk(dev_priv);
8872 }
8873
8874 /*
8875 * Package states C8 and deeper are really deep PC states that can only be
8876 * reached when all the devices on the system allow it, so even if the graphics
8877 * device allows PC8+, it doesn't mean the system will actually get to these
8878 * states. Our driver only allows PC8+ when going into runtime PM.
8879 *
8880 * The requirements for PC8+ are that all the outputs are disabled, the power
8881 * well is disabled and most interrupts are disabled, and these are also
8882 * requirements for runtime PM. When these conditions are met, we manually do
8883 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8884 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8885 * hang the machine.
8886 *
8887 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8888 * the state of some registers, so when we come back from PC8+ we need to
8889 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8890 * need to take care of the registers kept by RC6. Notice that this happens even
8891 * if we don't put the device in PCI D3 state (which is what currently happens
8892 * because of the runtime PM support).
8893 *
8894 * For more, read "Display Sequences for Package C8" on the hardware
8895 * documentation.
8896 */
8897 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8898 {
8899 uint32_t val;
8900
8901 DRM_DEBUG_KMS("Enabling package C8+\n");
8902
8903 if (HAS_PCH_LPT_LP(dev_priv)) {
8904 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8905 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8906 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8907 }
8908
8909 lpt_disable_clkout_dp(dev_priv);
8910 hsw_disable_lcpll(dev_priv, true, true);
8911 }
8912
8913 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8914 {
8915 uint32_t val;
8916
8917 DRM_DEBUG_KMS("Disabling package C8+\n");
8918
8919 hsw_restore_lcpll(dev_priv);
8920 lpt_init_pch_refclk(dev_priv);
8921
8922 if (HAS_PCH_LPT_LP(dev_priv)) {
8923 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8924 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8925 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8926 }
8927 }
8928
8929 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8930 struct intel_crtc_state *crtc_state)
8931 {
8932 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8933 struct intel_encoder *encoder =
8934 intel_ddi_get_crtc_new_encoder(crtc_state);
8935
8936 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8937 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8938 pipe_name(crtc->pipe));
8939 return -EINVAL;
8940 }
8941 }
8942
8943 return 0;
8944 }
8945
8946 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8947 enum port port,
8948 struct intel_crtc_state *pipe_config)
8949 {
8950 enum intel_dpll_id id;
8951 u32 temp;
8952
8953 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8954 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8955
8956 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8957 return;
8958
8959 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8960 }
8961
8962 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8963 enum port port,
8964 struct intel_crtc_state *pipe_config)
8965 {
8966 enum intel_dpll_id id;
8967
8968 switch (port) {
8969 case PORT_A:
8970 id = DPLL_ID_SKL_DPLL0;
8971 break;
8972 case PORT_B:
8973 id = DPLL_ID_SKL_DPLL1;
8974 break;
8975 case PORT_C:
8976 id = DPLL_ID_SKL_DPLL2;
8977 break;
8978 default:
8979 DRM_ERROR("Incorrect port type\n");
8980 return;
8981 }
8982
8983 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8984 }
8985
8986 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8987 enum port port,
8988 struct intel_crtc_state *pipe_config)
8989 {
8990 enum intel_dpll_id id;
8991 u32 temp;
8992
8993 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8994 id = temp >> (port * 3 + 1);
8995
8996 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8997 return;
8998
8999 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9000 }
9001
9002 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9003 enum port port,
9004 struct intel_crtc_state *pipe_config)
9005 {
9006 enum intel_dpll_id id;
9007 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9008
9009 switch (ddi_pll_sel) {
9010 case PORT_CLK_SEL_WRPLL1:
9011 id = DPLL_ID_WRPLL1;
9012 break;
9013 case PORT_CLK_SEL_WRPLL2:
9014 id = DPLL_ID_WRPLL2;
9015 break;
9016 case PORT_CLK_SEL_SPLL:
9017 id = DPLL_ID_SPLL;
9018 break;
9019 case PORT_CLK_SEL_LCPLL_810:
9020 id = DPLL_ID_LCPLL_810;
9021 break;
9022 case PORT_CLK_SEL_LCPLL_1350:
9023 id = DPLL_ID_LCPLL_1350;
9024 break;
9025 case PORT_CLK_SEL_LCPLL_2700:
9026 id = DPLL_ID_LCPLL_2700;
9027 break;
9028 default:
9029 MISSING_CASE(ddi_pll_sel);
9030 /* fall through */
9031 case PORT_CLK_SEL_NONE:
9032 return;
9033 }
9034
9035 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9036 }
9037
9038 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9039 struct intel_crtc_state *pipe_config,
9040 u64 *power_domain_mask)
9041 {
9042 struct drm_device *dev = crtc->base.dev;
9043 struct drm_i915_private *dev_priv = to_i915(dev);
9044 enum intel_display_power_domain power_domain;
9045 u32 tmp;
9046
9047 /*
9048 * The pipe->transcoder mapping is fixed with the exception of the eDP
9049 * transcoder handled below.
9050 */
9051 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9052
9053 /*
9054 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9055 * consistency and less surprising code; it's in always on power).
9056 */
9057 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9058 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9059 enum pipe trans_edp_pipe;
9060 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9061 default:
9062 WARN(1, "unknown pipe linked to edp transcoder\n");
9063 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9064 case TRANS_DDI_EDP_INPUT_A_ON:
9065 trans_edp_pipe = PIPE_A;
9066 break;
9067 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9068 trans_edp_pipe = PIPE_B;
9069 break;
9070 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9071 trans_edp_pipe = PIPE_C;
9072 break;
9073 }
9074
9075 if (trans_edp_pipe == crtc->pipe)
9076 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9077 }
9078
9079 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9080 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9081 return false;
9082 *power_domain_mask |= BIT_ULL(power_domain);
9083
9084 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9085
9086 return tmp & PIPECONF_ENABLE;
9087 }
9088
9089 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9090 struct intel_crtc_state *pipe_config,
9091 u64 *power_domain_mask)
9092 {
9093 struct drm_device *dev = crtc->base.dev;
9094 struct drm_i915_private *dev_priv = to_i915(dev);
9095 enum intel_display_power_domain power_domain;
9096 enum port port;
9097 enum transcoder cpu_transcoder;
9098 u32 tmp;
9099
9100 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9101 if (port == PORT_A)
9102 cpu_transcoder = TRANSCODER_DSI_A;
9103 else
9104 cpu_transcoder = TRANSCODER_DSI_C;
9105
9106 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9107 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9108 continue;
9109 *power_domain_mask |= BIT_ULL(power_domain);
9110
9111 /*
9112 * The PLL needs to be enabled with a valid divider
9113 * configuration, otherwise accessing DSI registers will hang
9114 * the machine. See BSpec North Display Engine
9115 * registers/MIPI[BXT]. We can break out here early, since we
9116 * need the same DSI PLL to be enabled for both DSI ports.
9117 */
9118 if (!intel_dsi_pll_is_enabled(dev_priv))
9119 break;
9120
9121 /* XXX: this works for video mode only */
9122 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9123 if (!(tmp & DPI_ENABLE))
9124 continue;
9125
9126 tmp = I915_READ(MIPI_CTRL(port));
9127 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9128 continue;
9129
9130 pipe_config->cpu_transcoder = cpu_transcoder;
9131 break;
9132 }
9133
9134 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9135 }
9136
9137 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9138 struct intel_crtc_state *pipe_config)
9139 {
9140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9141 struct intel_shared_dpll *pll;
9142 enum port port;
9143 uint32_t tmp;
9144
9145 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9146
9147 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9148
9149 if (IS_CANNONLAKE(dev_priv))
9150 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9151 else if (IS_GEN9_BC(dev_priv))
9152 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9153 else if (IS_GEN9_LP(dev_priv))
9154 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9155 else
9156 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9157
9158 pll = pipe_config->shared_dpll;
9159 if (pll) {
9160 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9161 &pipe_config->dpll_hw_state));
9162 }
9163
9164 /*
9165 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9166 * DDI E. So just check whether this pipe is wired to DDI E and whether
9167 * the PCH transcoder is on.
9168 */
9169 if (INTEL_GEN(dev_priv) < 9 &&
9170 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9171 pipe_config->has_pch_encoder = true;
9172
9173 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9174 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9175 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9176
9177 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9178 }
9179 }
9180
9181 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9182 struct intel_crtc_state *pipe_config)
9183 {
9184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9185 enum intel_display_power_domain power_domain;
9186 u64 power_domain_mask;
9187 bool active;
9188
9189 intel_crtc_init_scalers(crtc, pipe_config);
9190
9191 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9192 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9193 return false;
9194 power_domain_mask = BIT_ULL(power_domain);
9195
9196 pipe_config->shared_dpll = NULL;
9197
9198 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9199
9200 if (IS_GEN9_LP(dev_priv) &&
9201 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9202 WARN_ON(active);
9203 active = true;
9204 }
9205
9206 if (!active)
9207 goto out;
9208
9209 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9210 haswell_get_ddi_port_state(crtc, pipe_config);
9211 intel_get_pipe_timings(crtc, pipe_config);
9212 }
9213
9214 intel_get_pipe_src_size(crtc, pipe_config);
9215
9216 pipe_config->gamma_mode =
9217 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9218
9219 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9220 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9221 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9222
9223 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9224 bool blend_mode_420 = tmp &
9225 PIPEMISC_YUV420_MODE_FULL_BLEND;
9226
9227 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9228 if (pipe_config->ycbcr420 != clrspace_yuv ||
9229 pipe_config->ycbcr420 != blend_mode_420)
9230 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9231 } else if (clrspace_yuv) {
9232 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9233 }
9234 }
9235
9236 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9237 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9238 power_domain_mask |= BIT_ULL(power_domain);
9239 if (INTEL_GEN(dev_priv) >= 9)
9240 skylake_get_pfit_config(crtc, pipe_config);
9241 else
9242 ironlake_get_pfit_config(crtc, pipe_config);
9243 }
9244
9245 if (IS_HASWELL(dev_priv))
9246 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9247 (I915_READ(IPS_CTL) & IPS_ENABLE);
9248
9249 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9250 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9251 pipe_config->pixel_multiplier =
9252 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9253 } else {
9254 pipe_config->pixel_multiplier = 1;
9255 }
9256
9257 out:
9258 for_each_power_domain(power_domain, power_domain_mask)
9259 intel_display_power_put(dev_priv, power_domain);
9260
9261 return active;
9262 }
9263
9264 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9265 {
9266 struct drm_i915_private *dev_priv =
9267 to_i915(plane_state->base.plane->dev);
9268 const struct drm_framebuffer *fb = plane_state->base.fb;
9269 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9270 u32 base;
9271
9272 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9273 base = obj->phys_handle->busaddr;
9274 else
9275 base = intel_plane_ggtt_offset(plane_state);
9276
9277 base += plane_state->main.offset;
9278
9279 /* ILK+ do this automagically */
9280 if (HAS_GMCH_DISPLAY(dev_priv) &&
9281 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9282 base += (plane_state->base.crtc_h *
9283 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9284
9285 return base;
9286 }
9287
9288 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9289 {
9290 int x = plane_state->base.crtc_x;
9291 int y = plane_state->base.crtc_y;
9292 u32 pos = 0;
9293
9294 if (x < 0) {
9295 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9296 x = -x;
9297 }
9298 pos |= x << CURSOR_X_SHIFT;
9299
9300 if (y < 0) {
9301 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9302 y = -y;
9303 }
9304 pos |= y << CURSOR_Y_SHIFT;
9305
9306 return pos;
9307 }
9308
9309 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9310 {
9311 const struct drm_mode_config *config =
9312 &plane_state->base.plane->dev->mode_config;
9313 int width = plane_state->base.crtc_w;
9314 int height = plane_state->base.crtc_h;
9315
9316 return width > 0 && width <= config->cursor_width &&
9317 height > 0 && height <= config->cursor_height;
9318 }
9319
9320 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9321 struct intel_plane_state *plane_state)
9322 {
9323 const struct drm_framebuffer *fb = plane_state->base.fb;
9324 int src_x, src_y;
9325 u32 offset;
9326 int ret;
9327
9328 ret = drm_plane_helper_check_state(&plane_state->base,
9329 &plane_state->clip,
9330 DRM_PLANE_HELPER_NO_SCALING,
9331 DRM_PLANE_HELPER_NO_SCALING,
9332 true, true);
9333 if (ret)
9334 return ret;
9335
9336 if (!fb)
9337 return 0;
9338
9339 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9340 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9341 return -EINVAL;
9342 }
9343
9344 src_x = plane_state->base.src_x >> 16;
9345 src_y = plane_state->base.src_y >> 16;
9346
9347 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9348 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9349
9350 if (src_x != 0 || src_y != 0) {
9351 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9352 return -EINVAL;
9353 }
9354
9355 plane_state->main.offset = offset;
9356
9357 return 0;
9358 }
9359
9360 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9361 const struct intel_plane_state *plane_state)
9362 {
9363 const struct drm_framebuffer *fb = plane_state->base.fb;
9364
9365 return CURSOR_ENABLE |
9366 CURSOR_GAMMA_ENABLE |
9367 CURSOR_FORMAT_ARGB |
9368 CURSOR_STRIDE(fb->pitches[0]);
9369 }
9370
9371 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9372 {
9373 int width = plane_state->base.crtc_w;
9374
9375 /*
9376 * 845g/865g are only limited by the width of their cursors,
9377 * the height is arbitrary up to the precision of the register.
9378 */
9379 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9380 }
9381
9382 static int i845_check_cursor(struct intel_plane *plane,
9383 struct intel_crtc_state *crtc_state,
9384 struct intel_plane_state *plane_state)
9385 {
9386 const struct drm_framebuffer *fb = plane_state->base.fb;
9387 int ret;
9388
9389 ret = intel_check_cursor(crtc_state, plane_state);
9390 if (ret)
9391 return ret;
9392
9393 /* if we want to turn off the cursor ignore width and height */
9394 if (!fb)
9395 return 0;
9396
9397 /* Check for which cursor types we support */
9398 if (!i845_cursor_size_ok(plane_state)) {
9399 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9400 plane_state->base.crtc_w,
9401 plane_state->base.crtc_h);
9402 return -EINVAL;
9403 }
9404
9405 switch (fb->pitches[0]) {
9406 case 256:
9407 case 512:
9408 case 1024:
9409 case 2048:
9410 break;
9411 default:
9412 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9413 fb->pitches[0]);
9414 return -EINVAL;
9415 }
9416
9417 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9418
9419 return 0;
9420 }
9421
9422 static void i845_update_cursor(struct intel_plane *plane,
9423 const struct intel_crtc_state *crtc_state,
9424 const struct intel_plane_state *plane_state)
9425 {
9426 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9427 u32 cntl = 0, base = 0, pos = 0, size = 0;
9428 unsigned long irqflags;
9429
9430 if (plane_state && plane_state->base.visible) {
9431 unsigned int width = plane_state->base.crtc_w;
9432 unsigned int height = plane_state->base.crtc_h;
9433
9434 cntl = plane_state->ctl;
9435 size = (height << 12) | width;
9436
9437 base = intel_cursor_base(plane_state);
9438 pos = intel_cursor_position(plane_state);
9439 }
9440
9441 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9442
9443 /* On these chipsets we can only modify the base/size/stride
9444 * whilst the cursor is disabled.
9445 */
9446 if (plane->cursor.base != base ||
9447 plane->cursor.size != size ||
9448 plane->cursor.cntl != cntl) {
9449 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9450 I915_WRITE_FW(CURBASE(PIPE_A), base);
9451 I915_WRITE_FW(CURSIZE, size);
9452 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9453 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9454
9455 plane->cursor.base = base;
9456 plane->cursor.size = size;
9457 plane->cursor.cntl = cntl;
9458 } else {
9459 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9460 }
9461
9462 POSTING_READ_FW(CURCNTR(PIPE_A));
9463
9464 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9465 }
9466
9467 static void i845_disable_cursor(struct intel_plane *plane,
9468 struct intel_crtc *crtc)
9469 {
9470 i845_update_cursor(plane, NULL, NULL);
9471 }
9472
9473 static bool i845_cursor_get_hw_state(struct intel_plane *plane)
9474 {
9475 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9476 enum intel_display_power_domain power_domain;
9477 bool ret;
9478
9479 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9480 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9481 return false;
9482
9483 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9484
9485 intel_display_power_put(dev_priv, power_domain);
9486
9487 return ret;
9488 }
9489
9490 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9491 const struct intel_plane_state *plane_state)
9492 {
9493 struct drm_i915_private *dev_priv =
9494 to_i915(plane_state->base.plane->dev);
9495 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9496 u32 cntl;
9497
9498 cntl = MCURSOR_GAMMA_ENABLE;
9499
9500 if (HAS_DDI(dev_priv))
9501 cntl |= CURSOR_PIPE_CSC_ENABLE;
9502
9503 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9504
9505 switch (plane_state->base.crtc_w) {
9506 case 64:
9507 cntl |= CURSOR_MODE_64_ARGB_AX;
9508 break;
9509 case 128:
9510 cntl |= CURSOR_MODE_128_ARGB_AX;
9511 break;
9512 case 256:
9513 cntl |= CURSOR_MODE_256_ARGB_AX;
9514 break;
9515 default:
9516 MISSING_CASE(plane_state->base.crtc_w);
9517 return 0;
9518 }
9519
9520 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9521 cntl |= CURSOR_ROTATE_180;
9522
9523 return cntl;
9524 }
9525
9526 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9527 {
9528 struct drm_i915_private *dev_priv =
9529 to_i915(plane_state->base.plane->dev);
9530 int width = plane_state->base.crtc_w;
9531 int height = plane_state->base.crtc_h;
9532
9533 if (!intel_cursor_size_ok(plane_state))
9534 return false;
9535
9536 /* Cursor width is limited to a few power-of-two sizes */
9537 switch (width) {
9538 case 256:
9539 case 128:
9540 case 64:
9541 break;
9542 default:
9543 return false;
9544 }
9545
9546 /*
9547 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9548 * height from 8 lines up to the cursor width, when the
9549 * cursor is not rotated. Everything else requires square
9550 * cursors.
9551 */
9552 if (HAS_CUR_FBC(dev_priv) &&
9553 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9554 if (height < 8 || height > width)
9555 return false;
9556 } else {
9557 if (height != width)
9558 return false;
9559 }
9560
9561 return true;
9562 }
9563
9564 static int i9xx_check_cursor(struct intel_plane *plane,
9565 struct intel_crtc_state *crtc_state,
9566 struct intel_plane_state *plane_state)
9567 {
9568 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9569 const struct drm_framebuffer *fb = plane_state->base.fb;
9570 enum pipe pipe = plane->pipe;
9571 int ret;
9572
9573 ret = intel_check_cursor(crtc_state, plane_state);
9574 if (ret)
9575 return ret;
9576
9577 /* if we want to turn off the cursor ignore width and height */
9578 if (!fb)
9579 return 0;
9580
9581 /* Check for which cursor types we support */
9582 if (!i9xx_cursor_size_ok(plane_state)) {
9583 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9584 plane_state->base.crtc_w,
9585 plane_state->base.crtc_h);
9586 return -EINVAL;
9587 }
9588
9589 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9590 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9591 fb->pitches[0], plane_state->base.crtc_w);
9592 return -EINVAL;
9593 }
9594
9595 /*
9596 * There's something wrong with the cursor on CHV pipe C.
9597 * If it straddles the left edge of the screen then
9598 * moving it away from the edge or disabling it often
9599 * results in a pipe underrun, and often that can lead to
9600 * dead pipe (constant underrun reported, and it scans
9601 * out just a solid color). To recover from that, the
9602 * display power well must be turned off and on again.
9603 * Refuse the put the cursor into that compromised position.
9604 */
9605 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9606 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9607 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9608 return -EINVAL;
9609 }
9610
9611 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9612
9613 return 0;
9614 }
9615
9616 static void i9xx_update_cursor(struct intel_plane *plane,
9617 const struct intel_crtc_state *crtc_state,
9618 const struct intel_plane_state *plane_state)
9619 {
9620 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9621 enum pipe pipe = plane->pipe;
9622 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9623 unsigned long irqflags;
9624
9625 if (plane_state && plane_state->base.visible) {
9626 cntl = plane_state->ctl;
9627
9628 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9629 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9630
9631 base = intel_cursor_base(plane_state);
9632 pos = intel_cursor_position(plane_state);
9633 }
9634
9635 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9636
9637 /*
9638 * On some platforms writing CURCNTR first will also
9639 * cause CURPOS to be armed by the CURBASE write.
9640 * Without the CURCNTR write the CURPOS write would
9641 * arm itself. Thus we always start the full update
9642 * with a CURCNTR write.
9643 *
9644 * On other platforms CURPOS always requires the
9645 * CURBASE write to arm the update. Additonally
9646 * a write to any of the cursor register will cancel
9647 * an already armed cursor update. Thus leaving out
9648 * the CURBASE write after CURPOS could lead to a
9649 * cursor that doesn't appear to move, or even change
9650 * shape. Thus we always write CURBASE.
9651 *
9652 * CURCNTR and CUR_FBC_CTL are always
9653 * armed by the CURBASE write only.
9654 */
9655 if (plane->cursor.base != base ||
9656 plane->cursor.size != fbc_ctl ||
9657 plane->cursor.cntl != cntl) {
9658 I915_WRITE_FW(CURCNTR(pipe), cntl);
9659 if (HAS_CUR_FBC(dev_priv))
9660 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9661 I915_WRITE_FW(CURPOS(pipe), pos);
9662 I915_WRITE_FW(CURBASE(pipe), base);
9663
9664 plane->cursor.base = base;
9665 plane->cursor.size = fbc_ctl;
9666 plane->cursor.cntl = cntl;
9667 } else {
9668 I915_WRITE_FW(CURPOS(pipe), pos);
9669 I915_WRITE_FW(CURBASE(pipe), base);
9670 }
9671
9672 POSTING_READ_FW(CURBASE(pipe));
9673
9674 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9675 }
9676
9677 static void i9xx_disable_cursor(struct intel_plane *plane,
9678 struct intel_crtc *crtc)
9679 {
9680 i9xx_update_cursor(plane, NULL, NULL);
9681 }
9682
9683 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
9684 {
9685 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9686 enum intel_display_power_domain power_domain;
9687 enum pipe pipe = plane->pipe;
9688 bool ret;
9689
9690 /*
9691 * Not 100% correct for planes that can move between pipes,
9692 * but that's only the case for gen2-3 which don't have any
9693 * display power wells.
9694 */
9695 power_domain = POWER_DOMAIN_PIPE(pipe);
9696 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9697 return false;
9698
9699 ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
9700
9701 intel_display_power_put(dev_priv, power_domain);
9702
9703 return ret;
9704 }
9705
9706 /* VESA 640x480x72Hz mode to set on the pipe */
9707 static const struct drm_display_mode load_detect_mode = {
9708 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9709 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9710 };
9711
9712 struct drm_framebuffer *
9713 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9714 struct drm_mode_fb_cmd2 *mode_cmd)
9715 {
9716 struct intel_framebuffer *intel_fb;
9717 int ret;
9718
9719 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9720 if (!intel_fb)
9721 return ERR_PTR(-ENOMEM);
9722
9723 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9724 if (ret)
9725 goto err;
9726
9727 return &intel_fb->base;
9728
9729 err:
9730 kfree(intel_fb);
9731 return ERR_PTR(ret);
9732 }
9733
9734 static u32
9735 intel_framebuffer_pitch_for_width(int width, int bpp)
9736 {
9737 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9738 return ALIGN(pitch, 64);
9739 }
9740
9741 static u32
9742 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9743 {
9744 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9745 return PAGE_ALIGN(pitch * mode->vdisplay);
9746 }
9747
9748 static struct drm_framebuffer *
9749 intel_framebuffer_create_for_mode(struct drm_device *dev,
9750 const struct drm_display_mode *mode,
9751 int depth, int bpp)
9752 {
9753 struct drm_framebuffer *fb;
9754 struct drm_i915_gem_object *obj;
9755 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9756
9757 obj = i915_gem_object_create(to_i915(dev),
9758 intel_framebuffer_size_for_mode(mode, bpp));
9759 if (IS_ERR(obj))
9760 return ERR_CAST(obj);
9761
9762 mode_cmd.width = mode->hdisplay;
9763 mode_cmd.height = mode->vdisplay;
9764 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9765 bpp);
9766 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9767
9768 fb = intel_framebuffer_create(obj, &mode_cmd);
9769 if (IS_ERR(fb))
9770 i915_gem_object_put(obj);
9771
9772 return fb;
9773 }
9774
9775 static struct drm_framebuffer *
9776 mode_fits_in_fbdev(struct drm_device *dev,
9777 const struct drm_display_mode *mode)
9778 {
9779 #ifdef CONFIG_DRM_FBDEV_EMULATION
9780 struct drm_i915_private *dev_priv = to_i915(dev);
9781 struct drm_i915_gem_object *obj;
9782 struct drm_framebuffer *fb;
9783
9784 if (!dev_priv->fbdev)
9785 return NULL;
9786
9787 if (!dev_priv->fbdev->fb)
9788 return NULL;
9789
9790 obj = dev_priv->fbdev->fb->obj;
9791 BUG_ON(!obj);
9792
9793 fb = &dev_priv->fbdev->fb->base;
9794 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9795 fb->format->cpp[0] * 8))
9796 return NULL;
9797
9798 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9799 return NULL;
9800
9801 drm_framebuffer_get(fb);
9802 return fb;
9803 #else
9804 return NULL;
9805 #endif
9806 }
9807
9808 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9809 struct drm_crtc *crtc,
9810 const struct drm_display_mode *mode,
9811 struct drm_framebuffer *fb,
9812 int x, int y)
9813 {
9814 struct drm_plane_state *plane_state;
9815 int hdisplay, vdisplay;
9816 int ret;
9817
9818 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9819 if (IS_ERR(plane_state))
9820 return PTR_ERR(plane_state);
9821
9822 if (mode)
9823 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9824 else
9825 hdisplay = vdisplay = 0;
9826
9827 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9828 if (ret)
9829 return ret;
9830 drm_atomic_set_fb_for_plane(plane_state, fb);
9831 plane_state->crtc_x = 0;
9832 plane_state->crtc_y = 0;
9833 plane_state->crtc_w = hdisplay;
9834 plane_state->crtc_h = vdisplay;
9835 plane_state->src_x = x << 16;
9836 plane_state->src_y = y << 16;
9837 plane_state->src_w = hdisplay << 16;
9838 plane_state->src_h = vdisplay << 16;
9839
9840 return 0;
9841 }
9842
9843 int intel_get_load_detect_pipe(struct drm_connector *connector,
9844 const struct drm_display_mode *mode,
9845 struct intel_load_detect_pipe *old,
9846 struct drm_modeset_acquire_ctx *ctx)
9847 {
9848 struct intel_crtc *intel_crtc;
9849 struct intel_encoder *intel_encoder =
9850 intel_attached_encoder(connector);
9851 struct drm_crtc *possible_crtc;
9852 struct drm_encoder *encoder = &intel_encoder->base;
9853 struct drm_crtc *crtc = NULL;
9854 struct drm_device *dev = encoder->dev;
9855 struct drm_i915_private *dev_priv = to_i915(dev);
9856 struct drm_framebuffer *fb;
9857 struct drm_mode_config *config = &dev->mode_config;
9858 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9859 struct drm_connector_state *connector_state;
9860 struct intel_crtc_state *crtc_state;
9861 int ret, i = -1;
9862
9863 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9864 connector->base.id, connector->name,
9865 encoder->base.id, encoder->name);
9866
9867 old->restore_state = NULL;
9868
9869 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9870
9871 /*
9872 * Algorithm gets a little messy:
9873 *
9874 * - if the connector already has an assigned crtc, use it (but make
9875 * sure it's on first)
9876 *
9877 * - try to find the first unused crtc that can drive this connector,
9878 * and use that if we find one
9879 */
9880
9881 /* See if we already have a CRTC for this connector */
9882 if (connector->state->crtc) {
9883 crtc = connector->state->crtc;
9884
9885 ret = drm_modeset_lock(&crtc->mutex, ctx);
9886 if (ret)
9887 goto fail;
9888
9889 /* Make sure the crtc and connector are running */
9890 goto found;
9891 }
9892
9893 /* Find an unused one (if possible) */
9894 for_each_crtc(dev, possible_crtc) {
9895 i++;
9896 if (!(encoder->possible_crtcs & (1 << i)))
9897 continue;
9898
9899 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9900 if (ret)
9901 goto fail;
9902
9903 if (possible_crtc->state->enable) {
9904 drm_modeset_unlock(&possible_crtc->mutex);
9905 continue;
9906 }
9907
9908 crtc = possible_crtc;
9909 break;
9910 }
9911
9912 /*
9913 * If we didn't find an unused CRTC, don't use any.
9914 */
9915 if (!crtc) {
9916 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9917 ret = -ENODEV;
9918 goto fail;
9919 }
9920
9921 found:
9922 intel_crtc = to_intel_crtc(crtc);
9923
9924 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9925 if (ret)
9926 goto fail;
9927
9928 state = drm_atomic_state_alloc(dev);
9929 restore_state = drm_atomic_state_alloc(dev);
9930 if (!state || !restore_state) {
9931 ret = -ENOMEM;
9932 goto fail;
9933 }
9934
9935 state->acquire_ctx = ctx;
9936 restore_state->acquire_ctx = ctx;
9937
9938 connector_state = drm_atomic_get_connector_state(state, connector);
9939 if (IS_ERR(connector_state)) {
9940 ret = PTR_ERR(connector_state);
9941 goto fail;
9942 }
9943
9944 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9945 if (ret)
9946 goto fail;
9947
9948 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9949 if (IS_ERR(crtc_state)) {
9950 ret = PTR_ERR(crtc_state);
9951 goto fail;
9952 }
9953
9954 crtc_state->base.active = crtc_state->base.enable = true;
9955
9956 if (!mode)
9957 mode = &load_detect_mode;
9958
9959 /* We need a framebuffer large enough to accommodate all accesses
9960 * that the plane may generate whilst we perform load detection.
9961 * We can not rely on the fbcon either being present (we get called
9962 * during its initialisation to detect all boot displays, or it may
9963 * not even exist) or that it is large enough to satisfy the
9964 * requested mode.
9965 */
9966 fb = mode_fits_in_fbdev(dev, mode);
9967 if (fb == NULL) {
9968 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9969 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9970 } else
9971 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9972 if (IS_ERR(fb)) {
9973 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9974 ret = PTR_ERR(fb);
9975 goto fail;
9976 }
9977
9978 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9979 drm_framebuffer_put(fb);
9980 if (ret)
9981 goto fail;
9982
9983 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9984 if (ret)
9985 goto fail;
9986
9987 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9988 if (!ret)
9989 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9990 if (!ret)
9991 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9992 if (ret) {
9993 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9994 goto fail;
9995 }
9996
9997 ret = drm_atomic_commit(state);
9998 if (ret) {
9999 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10000 goto fail;
10001 }
10002
10003 old->restore_state = restore_state;
10004 drm_atomic_state_put(state);
10005
10006 /* let the connector get through one full cycle before testing */
10007 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10008 return true;
10009
10010 fail:
10011 if (state) {
10012 drm_atomic_state_put(state);
10013 state = NULL;
10014 }
10015 if (restore_state) {
10016 drm_atomic_state_put(restore_state);
10017 restore_state = NULL;
10018 }
10019
10020 if (ret == -EDEADLK)
10021 return ret;
10022
10023 return false;
10024 }
10025
10026 void intel_release_load_detect_pipe(struct drm_connector *connector,
10027 struct intel_load_detect_pipe *old,
10028 struct drm_modeset_acquire_ctx *ctx)
10029 {
10030 struct intel_encoder *intel_encoder =
10031 intel_attached_encoder(connector);
10032 struct drm_encoder *encoder = &intel_encoder->base;
10033 struct drm_atomic_state *state = old->restore_state;
10034 int ret;
10035
10036 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10037 connector->base.id, connector->name,
10038 encoder->base.id, encoder->name);
10039
10040 if (!state)
10041 return;
10042
10043 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10044 if (ret)
10045 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10046 drm_atomic_state_put(state);
10047 }
10048
10049 static int i9xx_pll_refclk(struct drm_device *dev,
10050 const struct intel_crtc_state *pipe_config)
10051 {
10052 struct drm_i915_private *dev_priv = to_i915(dev);
10053 u32 dpll = pipe_config->dpll_hw_state.dpll;
10054
10055 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10056 return dev_priv->vbt.lvds_ssc_freq;
10057 else if (HAS_PCH_SPLIT(dev_priv))
10058 return 120000;
10059 else if (!IS_GEN2(dev_priv))
10060 return 96000;
10061 else
10062 return 48000;
10063 }
10064
10065 /* Returns the clock of the currently programmed mode of the given pipe. */
10066 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10067 struct intel_crtc_state *pipe_config)
10068 {
10069 struct drm_device *dev = crtc->base.dev;
10070 struct drm_i915_private *dev_priv = to_i915(dev);
10071 int pipe = pipe_config->cpu_transcoder;
10072 u32 dpll = pipe_config->dpll_hw_state.dpll;
10073 u32 fp;
10074 struct dpll clock;
10075 int port_clock;
10076 int refclk = i9xx_pll_refclk(dev, pipe_config);
10077
10078 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10079 fp = pipe_config->dpll_hw_state.fp0;
10080 else
10081 fp = pipe_config->dpll_hw_state.fp1;
10082
10083 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10084 if (IS_PINEVIEW(dev_priv)) {
10085 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10086 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10087 } else {
10088 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10089 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10090 }
10091
10092 if (!IS_GEN2(dev_priv)) {
10093 if (IS_PINEVIEW(dev_priv))
10094 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10095 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10096 else
10097 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10098 DPLL_FPA01_P1_POST_DIV_SHIFT);
10099
10100 switch (dpll & DPLL_MODE_MASK) {
10101 case DPLLB_MODE_DAC_SERIAL:
10102 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10103 5 : 10;
10104 break;
10105 case DPLLB_MODE_LVDS:
10106 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10107 7 : 14;
10108 break;
10109 default:
10110 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10111 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10112 return;
10113 }
10114
10115 if (IS_PINEVIEW(dev_priv))
10116 port_clock = pnv_calc_dpll_params(refclk, &clock);
10117 else
10118 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10119 } else {
10120 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10121 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10122
10123 if (is_lvds) {
10124 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10125 DPLL_FPA01_P1_POST_DIV_SHIFT);
10126
10127 if (lvds & LVDS_CLKB_POWER_UP)
10128 clock.p2 = 7;
10129 else
10130 clock.p2 = 14;
10131 } else {
10132 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10133 clock.p1 = 2;
10134 else {
10135 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10136 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10137 }
10138 if (dpll & PLL_P2_DIVIDE_BY_4)
10139 clock.p2 = 4;
10140 else
10141 clock.p2 = 2;
10142 }
10143
10144 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10145 }
10146
10147 /*
10148 * This value includes pixel_multiplier. We will use
10149 * port_clock to compute adjusted_mode.crtc_clock in the
10150 * encoder's get_config() function.
10151 */
10152 pipe_config->port_clock = port_clock;
10153 }
10154
10155 int intel_dotclock_calculate(int link_freq,
10156 const struct intel_link_m_n *m_n)
10157 {
10158 /*
10159 * The calculation for the data clock is:
10160 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10161 * But we want to avoid losing precison if possible, so:
10162 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10163 *
10164 * and the link clock is simpler:
10165 * link_clock = (m * link_clock) / n
10166 */
10167
10168 if (!m_n->link_n)
10169 return 0;
10170
10171 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10172 }
10173
10174 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10175 struct intel_crtc_state *pipe_config)
10176 {
10177 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10178
10179 /* read out port_clock from the DPLL */
10180 i9xx_crtc_clock_get(crtc, pipe_config);
10181
10182 /*
10183 * In case there is an active pipe without active ports,
10184 * we may need some idea for the dotclock anyway.
10185 * Calculate one based on the FDI configuration.
10186 */
10187 pipe_config->base.adjusted_mode.crtc_clock =
10188 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10189 &pipe_config->fdi_m_n);
10190 }
10191
10192 /* Returns the currently programmed mode of the given encoder. */
10193 struct drm_display_mode *
10194 intel_encoder_current_mode(struct intel_encoder *encoder)
10195 {
10196 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10197 struct intel_crtc_state *crtc_state;
10198 struct drm_display_mode *mode;
10199 struct intel_crtc *crtc;
10200 enum pipe pipe;
10201
10202 if (!encoder->get_hw_state(encoder, &pipe))
10203 return NULL;
10204
10205 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10206
10207 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10208 if (!mode)
10209 return NULL;
10210
10211 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10212 if (!crtc_state) {
10213 kfree(mode);
10214 return NULL;
10215 }
10216
10217 crtc_state->base.crtc = &crtc->base;
10218
10219 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10220 kfree(crtc_state);
10221 kfree(mode);
10222 return NULL;
10223 }
10224
10225 encoder->get_config(encoder, crtc_state);
10226
10227 intel_mode_from_pipe_config(mode, crtc_state);
10228
10229 kfree(crtc_state);
10230
10231 return mode;
10232 }
10233
10234 static void intel_crtc_destroy(struct drm_crtc *crtc)
10235 {
10236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10237
10238 drm_crtc_cleanup(crtc);
10239 kfree(intel_crtc);
10240 }
10241
10242 /**
10243 * intel_wm_need_update - Check whether watermarks need updating
10244 * @plane: drm plane
10245 * @state: new plane state
10246 *
10247 * Check current plane state versus the new one to determine whether
10248 * watermarks need to be recalculated.
10249 *
10250 * Returns true or false.
10251 */
10252 static bool intel_wm_need_update(struct drm_plane *plane,
10253 struct drm_plane_state *state)
10254 {
10255 struct intel_plane_state *new = to_intel_plane_state(state);
10256 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10257
10258 /* Update watermarks on tiling or size changes. */
10259 if (new->base.visible != cur->base.visible)
10260 return true;
10261
10262 if (!cur->base.fb || !new->base.fb)
10263 return false;
10264
10265 if (cur->base.fb->modifier != new->base.fb->modifier ||
10266 cur->base.rotation != new->base.rotation ||
10267 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10268 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10269 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10270 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10271 return true;
10272
10273 return false;
10274 }
10275
10276 static bool needs_scaling(const struct intel_plane_state *state)
10277 {
10278 int src_w = drm_rect_width(&state->base.src) >> 16;
10279 int src_h = drm_rect_height(&state->base.src) >> 16;
10280 int dst_w = drm_rect_width(&state->base.dst);
10281 int dst_h = drm_rect_height(&state->base.dst);
10282
10283 return (src_w != dst_w || src_h != dst_h);
10284 }
10285
10286 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10287 struct drm_crtc_state *crtc_state,
10288 const struct intel_plane_state *old_plane_state,
10289 struct drm_plane_state *plane_state)
10290 {
10291 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10292 struct drm_crtc *crtc = crtc_state->crtc;
10293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10294 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10295 struct drm_device *dev = crtc->dev;
10296 struct drm_i915_private *dev_priv = to_i915(dev);
10297 bool mode_changed = needs_modeset(crtc_state);
10298 bool was_crtc_enabled = old_crtc_state->base.active;
10299 bool is_crtc_enabled = crtc_state->active;
10300 bool turn_off, turn_on, visible, was_visible;
10301 struct drm_framebuffer *fb = plane_state->fb;
10302 int ret;
10303
10304 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10305 ret = skl_update_scaler_plane(
10306 to_intel_crtc_state(crtc_state),
10307 to_intel_plane_state(plane_state));
10308 if (ret)
10309 return ret;
10310 }
10311
10312 was_visible = old_plane_state->base.visible;
10313 visible = plane_state->visible;
10314
10315 if (!was_crtc_enabled && WARN_ON(was_visible))
10316 was_visible = false;
10317
10318 /*
10319 * Visibility is calculated as if the crtc was on, but
10320 * after scaler setup everything depends on it being off
10321 * when the crtc isn't active.
10322 *
10323 * FIXME this is wrong for watermarks. Watermarks should also
10324 * be computed as if the pipe would be active. Perhaps move
10325 * per-plane wm computation to the .check_plane() hook, and
10326 * only combine the results from all planes in the current place?
10327 */
10328 if (!is_crtc_enabled) {
10329 plane_state->visible = visible = false;
10330 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10331 }
10332
10333 if (!was_visible && !visible)
10334 return 0;
10335
10336 if (fb != old_plane_state->base.fb)
10337 pipe_config->fb_changed = true;
10338
10339 turn_off = was_visible && (!visible || mode_changed);
10340 turn_on = visible && (!was_visible || mode_changed);
10341
10342 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10343 intel_crtc->base.base.id, intel_crtc->base.name,
10344 plane->base.base.id, plane->base.name,
10345 fb ? fb->base.id : -1);
10346
10347 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10348 plane->base.base.id, plane->base.name,
10349 was_visible, visible,
10350 turn_off, turn_on, mode_changed);
10351
10352 if (turn_on) {
10353 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10354 pipe_config->update_wm_pre = true;
10355
10356 /* must disable cxsr around plane enable/disable */
10357 if (plane->id != PLANE_CURSOR)
10358 pipe_config->disable_cxsr = true;
10359 } else if (turn_off) {
10360 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10361 pipe_config->update_wm_post = true;
10362
10363 /* must disable cxsr around plane enable/disable */
10364 if (plane->id != PLANE_CURSOR)
10365 pipe_config->disable_cxsr = true;
10366 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10367 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10368 /* FIXME bollocks */
10369 pipe_config->update_wm_pre = true;
10370 pipe_config->update_wm_post = true;
10371 }
10372 }
10373
10374 if (visible || was_visible)
10375 pipe_config->fb_bits |= plane->frontbuffer_bit;
10376
10377 /*
10378 * WaCxSRDisabledForSpriteScaling:ivb
10379 *
10380 * cstate->update_wm was already set above, so this flag will
10381 * take effect when we commit and program watermarks.
10382 */
10383 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10384 needs_scaling(to_intel_plane_state(plane_state)) &&
10385 !needs_scaling(old_plane_state))
10386 pipe_config->disable_lp_wm = true;
10387
10388 return 0;
10389 }
10390
10391 static bool encoders_cloneable(const struct intel_encoder *a,
10392 const struct intel_encoder *b)
10393 {
10394 /* masks could be asymmetric, so check both ways */
10395 return a == b || (a->cloneable & (1 << b->type) &&
10396 b->cloneable & (1 << a->type));
10397 }
10398
10399 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10400 struct intel_crtc *crtc,
10401 struct intel_encoder *encoder)
10402 {
10403 struct intel_encoder *source_encoder;
10404 struct drm_connector *connector;
10405 struct drm_connector_state *connector_state;
10406 int i;
10407
10408 for_each_new_connector_in_state(state, connector, connector_state, i) {
10409 if (connector_state->crtc != &crtc->base)
10410 continue;
10411
10412 source_encoder =
10413 to_intel_encoder(connector_state->best_encoder);
10414 if (!encoders_cloneable(encoder, source_encoder))
10415 return false;
10416 }
10417
10418 return true;
10419 }
10420
10421 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10422 struct drm_crtc_state *crtc_state)
10423 {
10424 struct drm_device *dev = crtc->dev;
10425 struct drm_i915_private *dev_priv = to_i915(dev);
10426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10427 struct intel_crtc_state *pipe_config =
10428 to_intel_crtc_state(crtc_state);
10429 struct drm_atomic_state *state = crtc_state->state;
10430 int ret;
10431 bool mode_changed = needs_modeset(crtc_state);
10432
10433 if (mode_changed && !crtc_state->active)
10434 pipe_config->update_wm_post = true;
10435
10436 if (mode_changed && crtc_state->enable &&
10437 dev_priv->display.crtc_compute_clock &&
10438 !WARN_ON(pipe_config->shared_dpll)) {
10439 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10440 pipe_config);
10441 if (ret)
10442 return ret;
10443 }
10444
10445 if (crtc_state->color_mgmt_changed) {
10446 ret = intel_color_check(crtc, crtc_state);
10447 if (ret)
10448 return ret;
10449
10450 /*
10451 * Changing color management on Intel hardware is
10452 * handled as part of planes update.
10453 */
10454 crtc_state->planes_changed = true;
10455 }
10456
10457 ret = 0;
10458 if (dev_priv->display.compute_pipe_wm) {
10459 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10460 if (ret) {
10461 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10462 return ret;
10463 }
10464 }
10465
10466 if (dev_priv->display.compute_intermediate_wm &&
10467 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10468 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10469 return 0;
10470
10471 /*
10472 * Calculate 'intermediate' watermarks that satisfy both the
10473 * old state and the new state. We can program these
10474 * immediately.
10475 */
10476 ret = dev_priv->display.compute_intermediate_wm(dev,
10477 intel_crtc,
10478 pipe_config);
10479 if (ret) {
10480 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10481 return ret;
10482 }
10483 } else if (dev_priv->display.compute_intermediate_wm) {
10484 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10485 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10486 }
10487
10488 if (INTEL_GEN(dev_priv) >= 9) {
10489 if (mode_changed)
10490 ret = skl_update_scaler_crtc(pipe_config);
10491
10492 if (!ret)
10493 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10494 pipe_config);
10495 if (!ret)
10496 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10497 pipe_config);
10498 }
10499
10500 return ret;
10501 }
10502
10503 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10504 .atomic_begin = intel_begin_crtc_commit,
10505 .atomic_flush = intel_finish_crtc_commit,
10506 .atomic_check = intel_crtc_atomic_check,
10507 };
10508
10509 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10510 {
10511 struct intel_connector *connector;
10512 struct drm_connector_list_iter conn_iter;
10513
10514 drm_connector_list_iter_begin(dev, &conn_iter);
10515 for_each_intel_connector_iter(connector, &conn_iter) {
10516 if (connector->base.state->crtc)
10517 drm_connector_unreference(&connector->base);
10518
10519 if (connector->base.encoder) {
10520 connector->base.state->best_encoder =
10521 connector->base.encoder;
10522 connector->base.state->crtc =
10523 connector->base.encoder->crtc;
10524
10525 drm_connector_reference(&connector->base);
10526 } else {
10527 connector->base.state->best_encoder = NULL;
10528 connector->base.state->crtc = NULL;
10529 }
10530 }
10531 drm_connector_list_iter_end(&conn_iter);
10532 }
10533
10534 static void
10535 connected_sink_compute_bpp(struct intel_connector *connector,
10536 struct intel_crtc_state *pipe_config)
10537 {
10538 const struct drm_display_info *info = &connector->base.display_info;
10539 int bpp = pipe_config->pipe_bpp;
10540
10541 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10542 connector->base.base.id,
10543 connector->base.name);
10544
10545 /* Don't use an invalid EDID bpc value */
10546 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10547 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10548 bpp, info->bpc * 3);
10549 pipe_config->pipe_bpp = info->bpc * 3;
10550 }
10551
10552 /* Clamp bpp to 8 on screens without EDID 1.4 */
10553 if (info->bpc == 0 && bpp > 24) {
10554 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10555 bpp);
10556 pipe_config->pipe_bpp = 24;
10557 }
10558 }
10559
10560 static int
10561 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10562 struct intel_crtc_state *pipe_config)
10563 {
10564 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10565 struct drm_atomic_state *state;
10566 struct drm_connector *connector;
10567 struct drm_connector_state *connector_state;
10568 int bpp, i;
10569
10570 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10571 IS_CHERRYVIEW(dev_priv)))
10572 bpp = 10*3;
10573 else if (INTEL_GEN(dev_priv) >= 5)
10574 bpp = 12*3;
10575 else
10576 bpp = 8*3;
10577
10578
10579 pipe_config->pipe_bpp = bpp;
10580
10581 state = pipe_config->base.state;
10582
10583 /* Clamp display bpp to EDID value */
10584 for_each_new_connector_in_state(state, connector, connector_state, i) {
10585 if (connector_state->crtc != &crtc->base)
10586 continue;
10587
10588 connected_sink_compute_bpp(to_intel_connector(connector),
10589 pipe_config);
10590 }
10591
10592 return bpp;
10593 }
10594
10595 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10596 {
10597 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10598 "type: 0x%x flags: 0x%x\n",
10599 mode->crtc_clock,
10600 mode->crtc_hdisplay, mode->crtc_hsync_start,
10601 mode->crtc_hsync_end, mode->crtc_htotal,
10602 mode->crtc_vdisplay, mode->crtc_vsync_start,
10603 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10604 }
10605
10606 static inline void
10607 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10608 unsigned int lane_count, struct intel_link_m_n *m_n)
10609 {
10610 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10611 id, lane_count,
10612 m_n->gmch_m, m_n->gmch_n,
10613 m_n->link_m, m_n->link_n, m_n->tu);
10614 }
10615
10616 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10617
10618 static const char * const output_type_str[] = {
10619 OUTPUT_TYPE(UNUSED),
10620 OUTPUT_TYPE(ANALOG),
10621 OUTPUT_TYPE(DVO),
10622 OUTPUT_TYPE(SDVO),
10623 OUTPUT_TYPE(LVDS),
10624 OUTPUT_TYPE(TVOUT),
10625 OUTPUT_TYPE(HDMI),
10626 OUTPUT_TYPE(DP),
10627 OUTPUT_TYPE(EDP),
10628 OUTPUT_TYPE(DSI),
10629 OUTPUT_TYPE(UNKNOWN),
10630 OUTPUT_TYPE(DP_MST),
10631 };
10632
10633 #undef OUTPUT_TYPE
10634
10635 static void snprintf_output_types(char *buf, size_t len,
10636 unsigned int output_types)
10637 {
10638 char *str = buf;
10639 int i;
10640
10641 str[0] = '\0';
10642
10643 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10644 int r;
10645
10646 if ((output_types & BIT(i)) == 0)
10647 continue;
10648
10649 r = snprintf(str, len, "%s%s",
10650 str != buf ? "," : "", output_type_str[i]);
10651 if (r >= len)
10652 break;
10653 str += r;
10654 len -= r;
10655
10656 output_types &= ~BIT(i);
10657 }
10658
10659 WARN_ON_ONCE(output_types != 0);
10660 }
10661
10662 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10663 struct intel_crtc_state *pipe_config,
10664 const char *context)
10665 {
10666 struct drm_device *dev = crtc->base.dev;
10667 struct drm_i915_private *dev_priv = to_i915(dev);
10668 struct drm_plane *plane;
10669 struct intel_plane *intel_plane;
10670 struct intel_plane_state *state;
10671 struct drm_framebuffer *fb;
10672 char buf[64];
10673
10674 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10675 crtc->base.base.id, crtc->base.name, context);
10676
10677 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10678 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10679 buf, pipe_config->output_types);
10680
10681 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10682 transcoder_name(pipe_config->cpu_transcoder),
10683 pipe_config->pipe_bpp, pipe_config->dither);
10684
10685 if (pipe_config->has_pch_encoder)
10686 intel_dump_m_n_config(pipe_config, "fdi",
10687 pipe_config->fdi_lanes,
10688 &pipe_config->fdi_m_n);
10689
10690 if (pipe_config->ycbcr420)
10691 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10692
10693 if (intel_crtc_has_dp_encoder(pipe_config)) {
10694 intel_dump_m_n_config(pipe_config, "dp m_n",
10695 pipe_config->lane_count, &pipe_config->dp_m_n);
10696 if (pipe_config->has_drrs)
10697 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10698 pipe_config->lane_count,
10699 &pipe_config->dp_m2_n2);
10700 }
10701
10702 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10703 pipe_config->has_audio, pipe_config->has_infoframe);
10704
10705 DRM_DEBUG_KMS("requested mode:\n");
10706 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10707 DRM_DEBUG_KMS("adjusted mode:\n");
10708 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10709 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10710 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10711 pipe_config->port_clock,
10712 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10713 pipe_config->pixel_rate);
10714
10715 if (INTEL_GEN(dev_priv) >= 9)
10716 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10717 crtc->num_scalers,
10718 pipe_config->scaler_state.scaler_users,
10719 pipe_config->scaler_state.scaler_id);
10720
10721 if (HAS_GMCH_DISPLAY(dev_priv))
10722 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10723 pipe_config->gmch_pfit.control,
10724 pipe_config->gmch_pfit.pgm_ratios,
10725 pipe_config->gmch_pfit.lvds_border_bits);
10726 else
10727 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10728 pipe_config->pch_pfit.pos,
10729 pipe_config->pch_pfit.size,
10730 enableddisabled(pipe_config->pch_pfit.enabled));
10731
10732 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10733 pipe_config->ips_enabled, pipe_config->double_wide);
10734
10735 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10736
10737 DRM_DEBUG_KMS("planes on this crtc\n");
10738 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10739 struct drm_format_name_buf format_name;
10740 intel_plane = to_intel_plane(plane);
10741 if (intel_plane->pipe != crtc->pipe)
10742 continue;
10743
10744 state = to_intel_plane_state(plane->state);
10745 fb = state->base.fb;
10746 if (!fb) {
10747 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10748 plane->base.id, plane->name, state->scaler_id);
10749 continue;
10750 }
10751
10752 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10753 plane->base.id, plane->name,
10754 fb->base.id, fb->width, fb->height,
10755 drm_get_format_name(fb->format->format, &format_name));
10756 if (INTEL_GEN(dev_priv) >= 9)
10757 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10758 state->scaler_id,
10759 state->base.src.x1 >> 16,
10760 state->base.src.y1 >> 16,
10761 drm_rect_width(&state->base.src) >> 16,
10762 drm_rect_height(&state->base.src) >> 16,
10763 state->base.dst.x1, state->base.dst.y1,
10764 drm_rect_width(&state->base.dst),
10765 drm_rect_height(&state->base.dst));
10766 }
10767 }
10768
10769 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10770 {
10771 struct drm_device *dev = state->dev;
10772 struct drm_connector *connector;
10773 struct drm_connector_list_iter conn_iter;
10774 unsigned int used_ports = 0;
10775 unsigned int used_mst_ports = 0;
10776
10777 /*
10778 * Walk the connector list instead of the encoder
10779 * list to detect the problem on ddi platforms
10780 * where there's just one encoder per digital port.
10781 */
10782 drm_connector_list_iter_begin(dev, &conn_iter);
10783 drm_for_each_connector_iter(connector, &conn_iter) {
10784 struct drm_connector_state *connector_state;
10785 struct intel_encoder *encoder;
10786
10787 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10788 if (!connector_state)
10789 connector_state = connector->state;
10790
10791 if (!connector_state->best_encoder)
10792 continue;
10793
10794 encoder = to_intel_encoder(connector_state->best_encoder);
10795
10796 WARN_ON(!connector_state->crtc);
10797
10798 switch (encoder->type) {
10799 unsigned int port_mask;
10800 case INTEL_OUTPUT_UNKNOWN:
10801 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10802 break;
10803 case INTEL_OUTPUT_DP:
10804 case INTEL_OUTPUT_HDMI:
10805 case INTEL_OUTPUT_EDP:
10806 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10807
10808 /* the same port mustn't appear more than once */
10809 if (used_ports & port_mask)
10810 return false;
10811
10812 used_ports |= port_mask;
10813 break;
10814 case INTEL_OUTPUT_DP_MST:
10815 used_mst_ports |=
10816 1 << enc_to_mst(&encoder->base)->primary->port;
10817 break;
10818 default:
10819 break;
10820 }
10821 }
10822 drm_connector_list_iter_end(&conn_iter);
10823
10824 /* can't mix MST and SST/HDMI on the same port */
10825 if (used_ports & used_mst_ports)
10826 return false;
10827
10828 return true;
10829 }
10830
10831 static void
10832 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10833 {
10834 struct drm_i915_private *dev_priv =
10835 to_i915(crtc_state->base.crtc->dev);
10836 struct intel_crtc_scaler_state scaler_state;
10837 struct intel_dpll_hw_state dpll_hw_state;
10838 struct intel_shared_dpll *shared_dpll;
10839 struct intel_crtc_wm_state wm_state;
10840 bool force_thru, ips_force_disable;
10841
10842 /* FIXME: before the switch to atomic started, a new pipe_config was
10843 * kzalloc'd. Code that depends on any field being zero should be
10844 * fixed, so that the crtc_state can be safely duplicated. For now,
10845 * only fields that are know to not cause problems are preserved. */
10846
10847 scaler_state = crtc_state->scaler_state;
10848 shared_dpll = crtc_state->shared_dpll;
10849 dpll_hw_state = crtc_state->dpll_hw_state;
10850 force_thru = crtc_state->pch_pfit.force_thru;
10851 ips_force_disable = crtc_state->ips_force_disable;
10852 if (IS_G4X(dev_priv) ||
10853 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10854 wm_state = crtc_state->wm;
10855
10856 /* Keep base drm_crtc_state intact, only clear our extended struct */
10857 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10858 memset(&crtc_state->base + 1, 0,
10859 sizeof(*crtc_state) - sizeof(crtc_state->base));
10860
10861 crtc_state->scaler_state = scaler_state;
10862 crtc_state->shared_dpll = shared_dpll;
10863 crtc_state->dpll_hw_state = dpll_hw_state;
10864 crtc_state->pch_pfit.force_thru = force_thru;
10865 crtc_state->ips_force_disable = ips_force_disable;
10866 if (IS_G4X(dev_priv) ||
10867 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10868 crtc_state->wm = wm_state;
10869 }
10870
10871 static int
10872 intel_modeset_pipe_config(struct drm_crtc *crtc,
10873 struct intel_crtc_state *pipe_config)
10874 {
10875 struct drm_atomic_state *state = pipe_config->base.state;
10876 struct intel_encoder *encoder;
10877 struct drm_connector *connector;
10878 struct drm_connector_state *connector_state;
10879 int base_bpp, ret = -EINVAL;
10880 int i;
10881 bool retry = true;
10882
10883 clear_intel_crtc_state(pipe_config);
10884
10885 pipe_config->cpu_transcoder =
10886 (enum transcoder) to_intel_crtc(crtc)->pipe;
10887
10888 /*
10889 * Sanitize sync polarity flags based on requested ones. If neither
10890 * positive or negative polarity is requested, treat this as meaning
10891 * negative polarity.
10892 */
10893 if (!(pipe_config->base.adjusted_mode.flags &
10894 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10895 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10896
10897 if (!(pipe_config->base.adjusted_mode.flags &
10898 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10899 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10900
10901 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10902 pipe_config);
10903 if (base_bpp < 0)
10904 goto fail;
10905
10906 /*
10907 * Determine the real pipe dimensions. Note that stereo modes can
10908 * increase the actual pipe size due to the frame doubling and
10909 * insertion of additional space for blanks between the frame. This
10910 * is stored in the crtc timings. We use the requested mode to do this
10911 * computation to clearly distinguish it from the adjusted mode, which
10912 * can be changed by the connectors in the below retry loop.
10913 */
10914 drm_mode_get_hv_timing(&pipe_config->base.mode,
10915 &pipe_config->pipe_src_w,
10916 &pipe_config->pipe_src_h);
10917
10918 for_each_new_connector_in_state(state, connector, connector_state, i) {
10919 if (connector_state->crtc != crtc)
10920 continue;
10921
10922 encoder = to_intel_encoder(connector_state->best_encoder);
10923
10924 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10925 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10926 goto fail;
10927 }
10928
10929 /*
10930 * Determine output_types before calling the .compute_config()
10931 * hooks so that the hooks can use this information safely.
10932 */
10933 pipe_config->output_types |= 1 << encoder->type;
10934 }
10935
10936 encoder_retry:
10937 /* Ensure the port clock defaults are reset when retrying. */
10938 pipe_config->port_clock = 0;
10939 pipe_config->pixel_multiplier = 1;
10940
10941 /* Fill in default crtc timings, allow encoders to overwrite them. */
10942 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10943 CRTC_STEREO_DOUBLE);
10944
10945 /* Pass our mode to the connectors and the CRTC to give them a chance to
10946 * adjust it according to limitations or connector properties, and also
10947 * a chance to reject the mode entirely.
10948 */
10949 for_each_new_connector_in_state(state, connector, connector_state, i) {
10950 if (connector_state->crtc != crtc)
10951 continue;
10952
10953 encoder = to_intel_encoder(connector_state->best_encoder);
10954
10955 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10956 DRM_DEBUG_KMS("Encoder config failure\n");
10957 goto fail;
10958 }
10959 }
10960
10961 /* Set default port clock if not overwritten by the encoder. Needs to be
10962 * done afterwards in case the encoder adjusts the mode. */
10963 if (!pipe_config->port_clock)
10964 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10965 * pipe_config->pixel_multiplier;
10966
10967 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10968 if (ret < 0) {
10969 DRM_DEBUG_KMS("CRTC fixup failed\n");
10970 goto fail;
10971 }
10972
10973 if (ret == RETRY) {
10974 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10975 ret = -EINVAL;
10976 goto fail;
10977 }
10978
10979 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10980 retry = false;
10981 goto encoder_retry;
10982 }
10983
10984 /* Dithering seems to not pass-through bits correctly when it should, so
10985 * only enable it on 6bpc panels and when its not a compliance
10986 * test requesting 6bpc video pattern.
10987 */
10988 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10989 !pipe_config->dither_force_disable;
10990 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10991 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10992
10993 fail:
10994 return ret;
10995 }
10996
10997 static void
10998 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10999 {
11000 struct drm_crtc *crtc;
11001 struct drm_crtc_state *new_crtc_state;
11002 int i;
11003
11004 /* Double check state. */
11005 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11006 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11007
11008 /*
11009 * Update legacy state to satisfy fbc code. This can
11010 * be removed when fbc uses the atomic state.
11011 */
11012 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11013 struct drm_plane_state *plane_state = crtc->primary->state;
11014
11015 crtc->primary->fb = plane_state->fb;
11016 crtc->x = plane_state->src_x >> 16;
11017 crtc->y = plane_state->src_y >> 16;
11018 }
11019 }
11020 }
11021
11022 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11023 {
11024 int diff;
11025
11026 if (clock1 == clock2)
11027 return true;
11028
11029 if (!clock1 || !clock2)
11030 return false;
11031
11032 diff = abs(clock1 - clock2);
11033
11034 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11035 return true;
11036
11037 return false;
11038 }
11039
11040 static bool
11041 intel_compare_m_n(unsigned int m, unsigned int n,
11042 unsigned int m2, unsigned int n2,
11043 bool exact)
11044 {
11045 if (m == m2 && n == n2)
11046 return true;
11047
11048 if (exact || !m || !n || !m2 || !n2)
11049 return false;
11050
11051 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11052
11053 if (n > n2) {
11054 while (n > n2) {
11055 m2 <<= 1;
11056 n2 <<= 1;
11057 }
11058 } else if (n < n2) {
11059 while (n < n2) {
11060 m <<= 1;
11061 n <<= 1;
11062 }
11063 }
11064
11065 if (n != n2)
11066 return false;
11067
11068 return intel_fuzzy_clock_check(m, m2);
11069 }
11070
11071 static bool
11072 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11073 struct intel_link_m_n *m2_n2,
11074 bool adjust)
11075 {
11076 if (m_n->tu == m2_n2->tu &&
11077 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11078 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11079 intel_compare_m_n(m_n->link_m, m_n->link_n,
11080 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11081 if (adjust)
11082 *m2_n2 = *m_n;
11083
11084 return true;
11085 }
11086
11087 return false;
11088 }
11089
11090 static void __printf(3, 4)
11091 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11092 {
11093 char *level;
11094 unsigned int category;
11095 struct va_format vaf;
11096 va_list args;
11097
11098 if (adjust) {
11099 level = KERN_DEBUG;
11100 category = DRM_UT_KMS;
11101 } else {
11102 level = KERN_ERR;
11103 category = DRM_UT_NONE;
11104 }
11105
11106 va_start(args, format);
11107 vaf.fmt = format;
11108 vaf.va = &args;
11109
11110 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11111
11112 va_end(args);
11113 }
11114
11115 static bool
11116 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11117 struct intel_crtc_state *current_config,
11118 struct intel_crtc_state *pipe_config,
11119 bool adjust)
11120 {
11121 bool ret = true;
11122
11123 #define PIPE_CONF_CHECK_X(name) \
11124 if (current_config->name != pipe_config->name) { \
11125 pipe_config_err(adjust, __stringify(name), \
11126 "(expected 0x%08x, found 0x%08x)\n", \
11127 current_config->name, \
11128 pipe_config->name); \
11129 ret = false; \
11130 }
11131
11132 #define PIPE_CONF_CHECK_I(name) \
11133 if (current_config->name != pipe_config->name) { \
11134 pipe_config_err(adjust, __stringify(name), \
11135 "(expected %i, found %i)\n", \
11136 current_config->name, \
11137 pipe_config->name); \
11138 ret = false; \
11139 }
11140
11141 #define PIPE_CONF_CHECK_P(name) \
11142 if (current_config->name != pipe_config->name) { \
11143 pipe_config_err(adjust, __stringify(name), \
11144 "(expected %p, found %p)\n", \
11145 current_config->name, \
11146 pipe_config->name); \
11147 ret = false; \
11148 }
11149
11150 #define PIPE_CONF_CHECK_M_N(name) \
11151 if (!intel_compare_link_m_n(&current_config->name, \
11152 &pipe_config->name,\
11153 adjust)) { \
11154 pipe_config_err(adjust, __stringify(name), \
11155 "(expected tu %i gmch %i/%i link %i/%i, " \
11156 "found tu %i, gmch %i/%i link %i/%i)\n", \
11157 current_config->name.tu, \
11158 current_config->name.gmch_m, \
11159 current_config->name.gmch_n, \
11160 current_config->name.link_m, \
11161 current_config->name.link_n, \
11162 pipe_config->name.tu, \
11163 pipe_config->name.gmch_m, \
11164 pipe_config->name.gmch_n, \
11165 pipe_config->name.link_m, \
11166 pipe_config->name.link_n); \
11167 ret = false; \
11168 }
11169
11170 /* This is required for BDW+ where there is only one set of registers for
11171 * switching between high and low RR.
11172 * This macro can be used whenever a comparison has to be made between one
11173 * hw state and multiple sw state variables.
11174 */
11175 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11176 if (!intel_compare_link_m_n(&current_config->name, \
11177 &pipe_config->name, adjust) && \
11178 !intel_compare_link_m_n(&current_config->alt_name, \
11179 &pipe_config->name, adjust)) { \
11180 pipe_config_err(adjust, __stringify(name), \
11181 "(expected tu %i gmch %i/%i link %i/%i, " \
11182 "or tu %i gmch %i/%i link %i/%i, " \
11183 "found tu %i, gmch %i/%i link %i/%i)\n", \
11184 current_config->name.tu, \
11185 current_config->name.gmch_m, \
11186 current_config->name.gmch_n, \
11187 current_config->name.link_m, \
11188 current_config->name.link_n, \
11189 current_config->alt_name.tu, \
11190 current_config->alt_name.gmch_m, \
11191 current_config->alt_name.gmch_n, \
11192 current_config->alt_name.link_m, \
11193 current_config->alt_name.link_n, \
11194 pipe_config->name.tu, \
11195 pipe_config->name.gmch_m, \
11196 pipe_config->name.gmch_n, \
11197 pipe_config->name.link_m, \
11198 pipe_config->name.link_n); \
11199 ret = false; \
11200 }
11201
11202 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11203 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11204 pipe_config_err(adjust, __stringify(name), \
11205 "(%x) (expected %i, found %i)\n", \
11206 (mask), \
11207 current_config->name & (mask), \
11208 pipe_config->name & (mask)); \
11209 ret = false; \
11210 }
11211
11212 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11213 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11214 pipe_config_err(adjust, __stringify(name), \
11215 "(expected %i, found %i)\n", \
11216 current_config->name, \
11217 pipe_config->name); \
11218 ret = false; \
11219 }
11220
11221 #define PIPE_CONF_QUIRK(quirk) \
11222 ((current_config->quirks | pipe_config->quirks) & (quirk))
11223
11224 PIPE_CONF_CHECK_I(cpu_transcoder);
11225
11226 PIPE_CONF_CHECK_I(has_pch_encoder);
11227 PIPE_CONF_CHECK_I(fdi_lanes);
11228 PIPE_CONF_CHECK_M_N(fdi_m_n);
11229
11230 PIPE_CONF_CHECK_I(lane_count);
11231 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11232
11233 if (INTEL_GEN(dev_priv) < 8) {
11234 PIPE_CONF_CHECK_M_N(dp_m_n);
11235
11236 if (current_config->has_drrs)
11237 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11238 } else
11239 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11240
11241 PIPE_CONF_CHECK_X(output_types);
11242
11243 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11244 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11245 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11246 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11247 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11248 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11249
11250 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11251 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11252 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11253 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11254 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11255 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11256
11257 PIPE_CONF_CHECK_I(pixel_multiplier);
11258 PIPE_CONF_CHECK_I(has_hdmi_sink);
11259 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11260 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11261 PIPE_CONF_CHECK_I(limited_color_range);
11262
11263 PIPE_CONF_CHECK_I(hdmi_scrambling);
11264 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11265 PIPE_CONF_CHECK_I(has_infoframe);
11266 PIPE_CONF_CHECK_I(ycbcr420);
11267
11268 PIPE_CONF_CHECK_I(has_audio);
11269
11270 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11271 DRM_MODE_FLAG_INTERLACE);
11272
11273 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11274 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11275 DRM_MODE_FLAG_PHSYNC);
11276 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11277 DRM_MODE_FLAG_NHSYNC);
11278 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11279 DRM_MODE_FLAG_PVSYNC);
11280 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11281 DRM_MODE_FLAG_NVSYNC);
11282 }
11283
11284 PIPE_CONF_CHECK_X(gmch_pfit.control);
11285 /* pfit ratios are autocomputed by the hw on gen4+ */
11286 if (INTEL_GEN(dev_priv) < 4)
11287 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11288 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11289
11290 if (!adjust) {
11291 PIPE_CONF_CHECK_I(pipe_src_w);
11292 PIPE_CONF_CHECK_I(pipe_src_h);
11293
11294 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11295 if (current_config->pch_pfit.enabled) {
11296 PIPE_CONF_CHECK_X(pch_pfit.pos);
11297 PIPE_CONF_CHECK_X(pch_pfit.size);
11298 }
11299
11300 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11301 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11302 }
11303
11304 /* BDW+ don't expose a synchronous way to read the state */
11305 if (IS_HASWELL(dev_priv))
11306 PIPE_CONF_CHECK_I(ips_enabled);
11307
11308 PIPE_CONF_CHECK_I(double_wide);
11309
11310 PIPE_CONF_CHECK_P(shared_dpll);
11311 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11312 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11313 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11314 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11315 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11316 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11317 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11318 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11319 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11320 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11321 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11322 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11323 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11324 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11325 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11326 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11327 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11328 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11329 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11330 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11331 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11332
11333 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11334 PIPE_CONF_CHECK_X(dsi_pll.div);
11335
11336 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11337 PIPE_CONF_CHECK_I(pipe_bpp);
11338
11339 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11340 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11341
11342 #undef PIPE_CONF_CHECK_X
11343 #undef PIPE_CONF_CHECK_I
11344 #undef PIPE_CONF_CHECK_P
11345 #undef PIPE_CONF_CHECK_FLAGS
11346 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11347 #undef PIPE_CONF_QUIRK
11348
11349 return ret;
11350 }
11351
11352 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11353 const struct intel_crtc_state *pipe_config)
11354 {
11355 if (pipe_config->has_pch_encoder) {
11356 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11357 &pipe_config->fdi_m_n);
11358 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11359
11360 /*
11361 * FDI already provided one idea for the dotclock.
11362 * Yell if the encoder disagrees.
11363 */
11364 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11365 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11366 fdi_dotclock, dotclock);
11367 }
11368 }
11369
11370 static void verify_wm_state(struct drm_crtc *crtc,
11371 struct drm_crtc_state *new_state)
11372 {
11373 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11374 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11375 struct skl_pipe_wm hw_wm, *sw_wm;
11376 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11377 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11379 const enum pipe pipe = intel_crtc->pipe;
11380 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11381
11382 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11383 return;
11384
11385 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11386 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11387
11388 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11389 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11390
11391 /* planes */
11392 for_each_universal_plane(dev_priv, pipe, plane) {
11393 hw_plane_wm = &hw_wm.planes[plane];
11394 sw_plane_wm = &sw_wm->planes[plane];
11395
11396 /* Watermarks */
11397 for (level = 0; level <= max_level; level++) {
11398 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11399 &sw_plane_wm->wm[level]))
11400 continue;
11401
11402 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11403 pipe_name(pipe), plane + 1, level,
11404 sw_plane_wm->wm[level].plane_en,
11405 sw_plane_wm->wm[level].plane_res_b,
11406 sw_plane_wm->wm[level].plane_res_l,
11407 hw_plane_wm->wm[level].plane_en,
11408 hw_plane_wm->wm[level].plane_res_b,
11409 hw_plane_wm->wm[level].plane_res_l);
11410 }
11411
11412 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11413 &sw_plane_wm->trans_wm)) {
11414 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11415 pipe_name(pipe), plane + 1,
11416 sw_plane_wm->trans_wm.plane_en,
11417 sw_plane_wm->trans_wm.plane_res_b,
11418 sw_plane_wm->trans_wm.plane_res_l,
11419 hw_plane_wm->trans_wm.plane_en,
11420 hw_plane_wm->trans_wm.plane_res_b,
11421 hw_plane_wm->trans_wm.plane_res_l);
11422 }
11423
11424 /* DDB */
11425 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11426 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11427
11428 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11429 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11430 pipe_name(pipe), plane + 1,
11431 sw_ddb_entry->start, sw_ddb_entry->end,
11432 hw_ddb_entry->start, hw_ddb_entry->end);
11433 }
11434 }
11435
11436 /*
11437 * cursor
11438 * If the cursor plane isn't active, we may not have updated it's ddb
11439 * allocation. In that case since the ddb allocation will be updated
11440 * once the plane becomes visible, we can skip this check
11441 */
11442 if (1) {
11443 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11444 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11445
11446 /* Watermarks */
11447 for (level = 0; level <= max_level; level++) {
11448 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11449 &sw_plane_wm->wm[level]))
11450 continue;
11451
11452 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11453 pipe_name(pipe), level,
11454 sw_plane_wm->wm[level].plane_en,
11455 sw_plane_wm->wm[level].plane_res_b,
11456 sw_plane_wm->wm[level].plane_res_l,
11457 hw_plane_wm->wm[level].plane_en,
11458 hw_plane_wm->wm[level].plane_res_b,
11459 hw_plane_wm->wm[level].plane_res_l);
11460 }
11461
11462 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11463 &sw_plane_wm->trans_wm)) {
11464 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11465 pipe_name(pipe),
11466 sw_plane_wm->trans_wm.plane_en,
11467 sw_plane_wm->trans_wm.plane_res_b,
11468 sw_plane_wm->trans_wm.plane_res_l,
11469 hw_plane_wm->trans_wm.plane_en,
11470 hw_plane_wm->trans_wm.plane_res_b,
11471 hw_plane_wm->trans_wm.plane_res_l);
11472 }
11473
11474 /* DDB */
11475 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11476 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11477
11478 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11479 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11480 pipe_name(pipe),
11481 sw_ddb_entry->start, sw_ddb_entry->end,
11482 hw_ddb_entry->start, hw_ddb_entry->end);
11483 }
11484 }
11485 }
11486
11487 static void
11488 verify_connector_state(struct drm_device *dev,
11489 struct drm_atomic_state *state,
11490 struct drm_crtc *crtc)
11491 {
11492 struct drm_connector *connector;
11493 struct drm_connector_state *new_conn_state;
11494 int i;
11495
11496 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11497 struct drm_encoder *encoder = connector->encoder;
11498 struct drm_crtc_state *crtc_state = NULL;
11499
11500 if (new_conn_state->crtc != crtc)
11501 continue;
11502
11503 if (crtc)
11504 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11505
11506 intel_connector_verify_state(crtc_state, new_conn_state);
11507
11508 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11509 "connector's atomic encoder doesn't match legacy encoder\n");
11510 }
11511 }
11512
11513 static void
11514 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11515 {
11516 struct intel_encoder *encoder;
11517 struct drm_connector *connector;
11518 struct drm_connector_state *old_conn_state, *new_conn_state;
11519 int i;
11520
11521 for_each_intel_encoder(dev, encoder) {
11522 bool enabled = false, found = false;
11523 enum pipe pipe;
11524
11525 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11526 encoder->base.base.id,
11527 encoder->base.name);
11528
11529 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11530 new_conn_state, i) {
11531 if (old_conn_state->best_encoder == &encoder->base)
11532 found = true;
11533
11534 if (new_conn_state->best_encoder != &encoder->base)
11535 continue;
11536 found = enabled = true;
11537
11538 I915_STATE_WARN(new_conn_state->crtc !=
11539 encoder->base.crtc,
11540 "connector's crtc doesn't match encoder crtc\n");
11541 }
11542
11543 if (!found)
11544 continue;
11545
11546 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11547 "encoder's enabled state mismatch "
11548 "(expected %i, found %i)\n",
11549 !!encoder->base.crtc, enabled);
11550
11551 if (!encoder->base.crtc) {
11552 bool active;
11553
11554 active = encoder->get_hw_state(encoder, &pipe);
11555 I915_STATE_WARN(active,
11556 "encoder detached but still enabled on pipe %c.\n",
11557 pipe_name(pipe));
11558 }
11559 }
11560 }
11561
11562 static void
11563 verify_crtc_state(struct drm_crtc *crtc,
11564 struct drm_crtc_state *old_crtc_state,
11565 struct drm_crtc_state *new_crtc_state)
11566 {
11567 struct drm_device *dev = crtc->dev;
11568 struct drm_i915_private *dev_priv = to_i915(dev);
11569 struct intel_encoder *encoder;
11570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11571 struct intel_crtc_state *pipe_config, *sw_config;
11572 struct drm_atomic_state *old_state;
11573 bool active;
11574
11575 old_state = old_crtc_state->state;
11576 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11577 pipe_config = to_intel_crtc_state(old_crtc_state);
11578 memset(pipe_config, 0, sizeof(*pipe_config));
11579 pipe_config->base.crtc = crtc;
11580 pipe_config->base.state = old_state;
11581
11582 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11583
11584 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11585
11586 /* we keep both pipes enabled on 830 */
11587 if (IS_I830(dev_priv))
11588 active = new_crtc_state->active;
11589
11590 I915_STATE_WARN(new_crtc_state->active != active,
11591 "crtc active state doesn't match with hw state "
11592 "(expected %i, found %i)\n", new_crtc_state->active, active);
11593
11594 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11595 "transitional active state does not match atomic hw state "
11596 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11597
11598 for_each_encoder_on_crtc(dev, crtc, encoder) {
11599 enum pipe pipe;
11600
11601 active = encoder->get_hw_state(encoder, &pipe);
11602 I915_STATE_WARN(active != new_crtc_state->active,
11603 "[ENCODER:%i] active %i with crtc active %i\n",
11604 encoder->base.base.id, active, new_crtc_state->active);
11605
11606 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11607 "Encoder connected to wrong pipe %c\n",
11608 pipe_name(pipe));
11609
11610 if (active) {
11611 pipe_config->output_types |= 1 << encoder->type;
11612 encoder->get_config(encoder, pipe_config);
11613 }
11614 }
11615
11616 intel_crtc_compute_pixel_rate(pipe_config);
11617
11618 if (!new_crtc_state->active)
11619 return;
11620
11621 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11622
11623 sw_config = to_intel_crtc_state(new_crtc_state);
11624 if (!intel_pipe_config_compare(dev_priv, sw_config,
11625 pipe_config, false)) {
11626 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11627 intel_dump_pipe_config(intel_crtc, pipe_config,
11628 "[hw state]");
11629 intel_dump_pipe_config(intel_crtc, sw_config,
11630 "[sw state]");
11631 }
11632 }
11633
11634 static void
11635 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11636 struct intel_shared_dpll *pll,
11637 struct drm_crtc *crtc,
11638 struct drm_crtc_state *new_state)
11639 {
11640 struct intel_dpll_hw_state dpll_hw_state;
11641 unsigned crtc_mask;
11642 bool active;
11643
11644 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11645
11646 DRM_DEBUG_KMS("%s\n", pll->name);
11647
11648 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11649
11650 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11651 I915_STATE_WARN(!pll->on && pll->active_mask,
11652 "pll in active use but not on in sw tracking\n");
11653 I915_STATE_WARN(pll->on && !pll->active_mask,
11654 "pll is on but not used by any active crtc\n");
11655 I915_STATE_WARN(pll->on != active,
11656 "pll on state mismatch (expected %i, found %i)\n",
11657 pll->on, active);
11658 }
11659
11660 if (!crtc) {
11661 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11662 "more active pll users than references: %x vs %x\n",
11663 pll->active_mask, pll->state.crtc_mask);
11664
11665 return;
11666 }
11667
11668 crtc_mask = 1 << drm_crtc_index(crtc);
11669
11670 if (new_state->active)
11671 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11672 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11673 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11674 else
11675 I915_STATE_WARN(pll->active_mask & crtc_mask,
11676 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11677 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11678
11679 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11680 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11681 crtc_mask, pll->state.crtc_mask);
11682
11683 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11684 &dpll_hw_state,
11685 sizeof(dpll_hw_state)),
11686 "pll hw state mismatch\n");
11687 }
11688
11689 static void
11690 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11691 struct drm_crtc_state *old_crtc_state,
11692 struct drm_crtc_state *new_crtc_state)
11693 {
11694 struct drm_i915_private *dev_priv = to_i915(dev);
11695 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11696 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11697
11698 if (new_state->shared_dpll)
11699 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11700
11701 if (old_state->shared_dpll &&
11702 old_state->shared_dpll != new_state->shared_dpll) {
11703 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11704 struct intel_shared_dpll *pll = old_state->shared_dpll;
11705
11706 I915_STATE_WARN(pll->active_mask & crtc_mask,
11707 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11708 pipe_name(drm_crtc_index(crtc)));
11709 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11710 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11711 pipe_name(drm_crtc_index(crtc)));
11712 }
11713 }
11714
11715 static void
11716 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11717 struct drm_atomic_state *state,
11718 struct drm_crtc_state *old_state,
11719 struct drm_crtc_state *new_state)
11720 {
11721 if (!needs_modeset(new_state) &&
11722 !to_intel_crtc_state(new_state)->update_pipe)
11723 return;
11724
11725 verify_wm_state(crtc, new_state);
11726 verify_connector_state(crtc->dev, state, crtc);
11727 verify_crtc_state(crtc, old_state, new_state);
11728 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11729 }
11730
11731 static void
11732 verify_disabled_dpll_state(struct drm_device *dev)
11733 {
11734 struct drm_i915_private *dev_priv = to_i915(dev);
11735 int i;
11736
11737 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11738 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11739 }
11740
11741 static void
11742 intel_modeset_verify_disabled(struct drm_device *dev,
11743 struct drm_atomic_state *state)
11744 {
11745 verify_encoder_state(dev, state);
11746 verify_connector_state(dev, state, NULL);
11747 verify_disabled_dpll_state(dev);
11748 }
11749
11750 static void update_scanline_offset(struct intel_crtc *crtc)
11751 {
11752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11753
11754 /*
11755 * The scanline counter increments at the leading edge of hsync.
11756 *
11757 * On most platforms it starts counting from vtotal-1 on the
11758 * first active line. That means the scanline counter value is
11759 * always one less than what we would expect. Ie. just after
11760 * start of vblank, which also occurs at start of hsync (on the
11761 * last active line), the scanline counter will read vblank_start-1.
11762 *
11763 * On gen2 the scanline counter starts counting from 1 instead
11764 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11765 * to keep the value positive), instead of adding one.
11766 *
11767 * On HSW+ the behaviour of the scanline counter depends on the output
11768 * type. For DP ports it behaves like most other platforms, but on HDMI
11769 * there's an extra 1 line difference. So we need to add two instead of
11770 * one to the value.
11771 *
11772 * On VLV/CHV DSI the scanline counter would appear to increment
11773 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11774 * that means we can't tell whether we're in vblank or not while
11775 * we're on that particular line. We must still set scanline_offset
11776 * to 1 so that the vblank timestamps come out correct when we query
11777 * the scanline counter from within the vblank interrupt handler.
11778 * However if queried just before the start of vblank we'll get an
11779 * answer that's slightly in the future.
11780 */
11781 if (IS_GEN2(dev_priv)) {
11782 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11783 int vtotal;
11784
11785 vtotal = adjusted_mode->crtc_vtotal;
11786 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11787 vtotal /= 2;
11788
11789 crtc->scanline_offset = vtotal - 1;
11790 } else if (HAS_DDI(dev_priv) &&
11791 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11792 crtc->scanline_offset = 2;
11793 } else
11794 crtc->scanline_offset = 1;
11795 }
11796
11797 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11798 {
11799 struct drm_device *dev = state->dev;
11800 struct drm_i915_private *dev_priv = to_i915(dev);
11801 struct drm_crtc *crtc;
11802 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11803 int i;
11804
11805 if (!dev_priv->display.crtc_compute_clock)
11806 return;
11807
11808 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11810 struct intel_shared_dpll *old_dpll =
11811 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11812
11813 if (!needs_modeset(new_crtc_state))
11814 continue;
11815
11816 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11817
11818 if (!old_dpll)
11819 continue;
11820
11821 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11822 }
11823 }
11824
11825 /*
11826 * This implements the workaround described in the "notes" section of the mode
11827 * set sequence documentation. When going from no pipes or single pipe to
11828 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11829 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11830 */
11831 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11832 {
11833 struct drm_crtc_state *crtc_state;
11834 struct intel_crtc *intel_crtc;
11835 struct drm_crtc *crtc;
11836 struct intel_crtc_state *first_crtc_state = NULL;
11837 struct intel_crtc_state *other_crtc_state = NULL;
11838 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11839 int i;
11840
11841 /* look at all crtc's that are going to be enabled in during modeset */
11842 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11843 intel_crtc = to_intel_crtc(crtc);
11844
11845 if (!crtc_state->active || !needs_modeset(crtc_state))
11846 continue;
11847
11848 if (first_crtc_state) {
11849 other_crtc_state = to_intel_crtc_state(crtc_state);
11850 break;
11851 } else {
11852 first_crtc_state = to_intel_crtc_state(crtc_state);
11853 first_pipe = intel_crtc->pipe;
11854 }
11855 }
11856
11857 /* No workaround needed? */
11858 if (!first_crtc_state)
11859 return 0;
11860
11861 /* w/a possibly needed, check how many crtc's are already enabled. */
11862 for_each_intel_crtc(state->dev, intel_crtc) {
11863 struct intel_crtc_state *pipe_config;
11864
11865 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11866 if (IS_ERR(pipe_config))
11867 return PTR_ERR(pipe_config);
11868
11869 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11870
11871 if (!pipe_config->base.active ||
11872 needs_modeset(&pipe_config->base))
11873 continue;
11874
11875 /* 2 or more enabled crtcs means no need for w/a */
11876 if (enabled_pipe != INVALID_PIPE)
11877 return 0;
11878
11879 enabled_pipe = intel_crtc->pipe;
11880 }
11881
11882 if (enabled_pipe != INVALID_PIPE)
11883 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11884 else if (other_crtc_state)
11885 other_crtc_state->hsw_workaround_pipe = first_pipe;
11886
11887 return 0;
11888 }
11889
11890 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11891 {
11892 struct drm_crtc *crtc;
11893
11894 /* Add all pipes to the state */
11895 for_each_crtc(state->dev, crtc) {
11896 struct drm_crtc_state *crtc_state;
11897
11898 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11899 if (IS_ERR(crtc_state))
11900 return PTR_ERR(crtc_state);
11901 }
11902
11903 return 0;
11904 }
11905
11906 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11907 {
11908 struct drm_crtc *crtc;
11909
11910 /*
11911 * Add all pipes to the state, and force
11912 * a modeset on all the active ones.
11913 */
11914 for_each_crtc(state->dev, crtc) {
11915 struct drm_crtc_state *crtc_state;
11916 int ret;
11917
11918 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11919 if (IS_ERR(crtc_state))
11920 return PTR_ERR(crtc_state);
11921
11922 if (!crtc_state->active || needs_modeset(crtc_state))
11923 continue;
11924
11925 crtc_state->mode_changed = true;
11926
11927 ret = drm_atomic_add_affected_connectors(state, crtc);
11928 if (ret)
11929 return ret;
11930
11931 ret = drm_atomic_add_affected_planes(state, crtc);
11932 if (ret)
11933 return ret;
11934 }
11935
11936 return 0;
11937 }
11938
11939 static int intel_modeset_checks(struct drm_atomic_state *state)
11940 {
11941 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11942 struct drm_i915_private *dev_priv = to_i915(state->dev);
11943 struct drm_crtc *crtc;
11944 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11945 int ret = 0, i;
11946
11947 if (!check_digital_port_conflicts(state)) {
11948 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11949 return -EINVAL;
11950 }
11951
11952 /* keep the current setting */
11953 if (!intel_state->cdclk.force_min_cdclk_changed)
11954 intel_state->cdclk.force_min_cdclk =
11955 dev_priv->cdclk.force_min_cdclk;
11956
11957
11958 intel_state->modeset = true;
11959 intel_state->active_crtcs = dev_priv->active_crtcs;
11960 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11961 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11962 intel_state->cdclk.pipe = INVALID_PIPE;
11963
11964 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11965 if (new_crtc_state->active)
11966 intel_state->active_crtcs |= 1 << i;
11967 else
11968 intel_state->active_crtcs &= ~(1 << i);
11969
11970 if (old_crtc_state->active != new_crtc_state->active)
11971 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11972 }
11973
11974 /*
11975 * See if the config requires any additional preparation, e.g.
11976 * to adjust global state with pipes off. We need to do this
11977 * here so we can get the modeset_pipe updated config for the new
11978 * mode set on this crtc. For other crtcs we need to use the
11979 * adjusted_mode bits in the crtc directly.
11980 */
11981 if (dev_priv->display.modeset_calc_cdclk) {
11982 enum pipe pipe;
11983
11984 ret = dev_priv->display.modeset_calc_cdclk(state);
11985 if (ret < 0)
11986 return ret;
11987
11988 /*
11989 * Writes to dev_priv->cdclk.logical must protected by
11990 * holding all the crtc locks, even if we don't end up
11991 * touching the hardware
11992 */
11993 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11994 &intel_state->cdclk.logical)) {
11995 ret = intel_lock_all_pipes(state);
11996 if (ret < 0)
11997 return ret;
11998 }
11999
12000 if (is_power_of_2(intel_state->active_crtcs)) {
12001 struct drm_crtc *crtc;
12002 struct drm_crtc_state *crtc_state;
12003
12004 pipe = ilog2(intel_state->active_crtcs);
12005 crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;
12006 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
12007 if (crtc_state && needs_modeset(crtc_state))
12008 pipe = INVALID_PIPE;
12009 } else {
12010 pipe = INVALID_PIPE;
12011 }
12012
12013 /* All pipes must be switched off while we change the cdclk. */
12014 if (pipe != INVALID_PIPE &&
12015 intel_cdclk_needs_cd2x_update(dev_priv,
12016 &dev_priv->cdclk.actual,
12017 &intel_state->cdclk.actual)) {
12018 ret = intel_lock_all_pipes(state);
12019 if (ret < 0)
12020 return ret;
12021
12022 intel_state->cdclk.pipe = pipe;
12023 } else if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12024 &intel_state->cdclk.actual)) {
12025 ret = intel_modeset_all_pipes(state);
12026 if (ret < 0)
12027 return ret;
12028
12029 intel_state->cdclk.pipe = INVALID_PIPE;
12030 }
12031
12032 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12033 intel_state->cdclk.logical.cdclk,
12034 intel_state->cdclk.actual.cdclk);
12035 }
12036
12037 intel_modeset_clear_plls(state);
12038
12039 if (IS_HASWELL(dev_priv))
12040 return haswell_mode_set_planes_workaround(state);
12041
12042 return 0;
12043 }
12044
12045 /*
12046 * Handle calculation of various watermark data at the end of the atomic check
12047 * phase. The code here should be run after the per-crtc and per-plane 'check'
12048 * handlers to ensure that all derived state has been updated.
12049 */
12050 static int calc_watermark_data(struct drm_atomic_state *state)
12051 {
12052 struct drm_device *dev = state->dev;
12053 struct drm_i915_private *dev_priv = to_i915(dev);
12054
12055 /* Is there platform-specific watermark information to calculate? */
12056 if (dev_priv->display.compute_global_watermarks)
12057 return dev_priv->display.compute_global_watermarks(state);
12058
12059 return 0;
12060 }
12061
12062 /**
12063 * intel_atomic_check - validate state object
12064 * @dev: drm device
12065 * @state: state to validate
12066 */
12067 static int intel_atomic_check(struct drm_device *dev,
12068 struct drm_atomic_state *state)
12069 {
12070 struct drm_i915_private *dev_priv = to_i915(dev);
12071 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12072 struct drm_crtc *crtc;
12073 struct drm_crtc_state *old_crtc_state, *crtc_state;
12074 int ret, i;
12075 bool any_ms = intel_state->cdclk.force_min_cdclk_changed;
12076
12077 ret = drm_atomic_helper_check_modeset(dev, state);
12078 if (ret)
12079 return ret;
12080
12081 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12082 struct intel_crtc_state *pipe_config =
12083 to_intel_crtc_state(crtc_state);
12084
12085 /* Catch I915_MODE_FLAG_INHERITED */
12086 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12087 crtc_state->mode_changed = true;
12088
12089 if (!needs_modeset(crtc_state))
12090 continue;
12091
12092 if (!crtc_state->enable) {
12093 any_ms = true;
12094 continue;
12095 }
12096
12097 /* FIXME: For only active_changed we shouldn't need to do any
12098 * state recomputation at all. */
12099
12100 ret = drm_atomic_add_affected_connectors(state, crtc);
12101 if (ret)
12102 return ret;
12103
12104 ret = intel_modeset_pipe_config(crtc, pipe_config);
12105 if (ret) {
12106 intel_dump_pipe_config(to_intel_crtc(crtc),
12107 pipe_config, "[failed]");
12108 return ret;
12109 }
12110
12111 if (i915_modparams.fastboot &&
12112 intel_pipe_config_compare(dev_priv,
12113 to_intel_crtc_state(old_crtc_state),
12114 pipe_config, true)) {
12115 crtc_state->mode_changed = false;
12116 pipe_config->update_pipe = true;
12117 }
12118
12119 if (needs_modeset(crtc_state))
12120 any_ms = true;
12121
12122 ret = drm_atomic_add_affected_planes(state, crtc);
12123 if (ret)
12124 return ret;
12125
12126 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12127 needs_modeset(crtc_state) ?
12128 "[modeset]" : "[fastset]");
12129 }
12130
12131 if (any_ms) {
12132 ret = intel_modeset_checks(state);
12133
12134 if (ret)
12135 return ret;
12136 } else {
12137 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12138 }
12139
12140 ret = drm_atomic_helper_check_planes(dev, state);
12141 if (ret)
12142 return ret;
12143
12144 intel_fbc_choose_crtc(dev_priv, state);
12145 return calc_watermark_data(state);
12146 }
12147
12148 static int intel_atomic_prepare_commit(struct drm_device *dev,
12149 struct drm_atomic_state *state)
12150 {
12151 return drm_atomic_helper_prepare_planes(dev, state);
12152 }
12153
12154 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12155 {
12156 struct drm_device *dev = crtc->base.dev;
12157
12158 if (!dev->max_vblank_count)
12159 return drm_crtc_accurate_vblank_count(&crtc->base);
12160
12161 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12162 }
12163
12164 static void intel_update_crtc(struct drm_crtc *crtc,
12165 struct drm_atomic_state *state,
12166 struct drm_crtc_state *old_crtc_state,
12167 struct drm_crtc_state *new_crtc_state)
12168 {
12169 struct drm_device *dev = crtc->dev;
12170 struct drm_i915_private *dev_priv = to_i915(dev);
12171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12172 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12173 bool modeset = needs_modeset(new_crtc_state);
12174
12175 if (modeset) {
12176 update_scanline_offset(intel_crtc);
12177 dev_priv->display.crtc_enable(pipe_config, state);
12178 } else {
12179 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12180 pipe_config);
12181 }
12182
12183 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12184 intel_fbc_enable(
12185 intel_crtc, pipe_config,
12186 to_intel_plane_state(crtc->primary->state));
12187 }
12188
12189 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12190 }
12191
12192 static void intel_update_crtcs(struct drm_atomic_state *state)
12193 {
12194 struct drm_crtc *crtc;
12195 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12196 int i;
12197
12198 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12199 if (!new_crtc_state->active)
12200 continue;
12201
12202 intel_update_crtc(crtc, state, old_crtc_state,
12203 new_crtc_state);
12204 }
12205 }
12206
12207 static void skl_update_crtcs(struct drm_atomic_state *state)
12208 {
12209 struct drm_i915_private *dev_priv = to_i915(state->dev);
12210 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12211 struct drm_crtc *crtc;
12212 struct intel_crtc *intel_crtc;
12213 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12214 struct intel_crtc_state *cstate;
12215 unsigned int updated = 0;
12216 bool progress;
12217 enum pipe pipe;
12218 int i;
12219
12220 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12221
12222 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12223 /* ignore allocations for crtc's that have been turned off. */
12224 if (new_crtc_state->active)
12225 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12226
12227 /*
12228 * Whenever the number of active pipes changes, we need to make sure we
12229 * update the pipes in the right order so that their ddb allocations
12230 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12231 * cause pipe underruns and other bad stuff.
12232 */
12233 do {
12234 progress = false;
12235
12236 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12237 bool vbl_wait = false;
12238 unsigned int cmask = drm_crtc_mask(crtc);
12239
12240 intel_crtc = to_intel_crtc(crtc);
12241 cstate = to_intel_crtc_state(new_crtc_state);
12242 pipe = intel_crtc->pipe;
12243
12244 if (updated & cmask || !cstate->base.active)
12245 continue;
12246
12247 if (skl_ddb_allocation_overlaps(dev_priv,
12248 entries,
12249 &cstate->wm.skl.ddb,
12250 i))
12251 continue;
12252
12253 updated |= cmask;
12254 entries[i] = &cstate->wm.skl.ddb;
12255
12256 /*
12257 * If this is an already active pipe, it's DDB changed,
12258 * and this isn't the last pipe that needs updating
12259 * then we need to wait for a vblank to pass for the
12260 * new ddb allocation to take effect.
12261 */
12262 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12263 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12264 !new_crtc_state->active_changed &&
12265 intel_state->wm_results.dirty_pipes != updated)
12266 vbl_wait = true;
12267
12268 intel_update_crtc(crtc, state, old_crtc_state,
12269 new_crtc_state);
12270
12271 if (vbl_wait)
12272 intel_wait_for_vblank(dev_priv, pipe);
12273
12274 progress = true;
12275 }
12276 } while (progress);
12277 }
12278
12279 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12280 {
12281 struct intel_atomic_state *state, *next;
12282 struct llist_node *freed;
12283
12284 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12285 llist_for_each_entry_safe(state, next, freed, freed)
12286 drm_atomic_state_put(&state->base);
12287 }
12288
12289 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12290 {
12291 struct drm_i915_private *dev_priv =
12292 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12293
12294 intel_atomic_helper_free_state(dev_priv);
12295 }
12296
12297 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12298 {
12299 struct wait_queue_entry wait_fence, wait_reset;
12300 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12301
12302 init_wait_entry(&wait_fence, 0);
12303 init_wait_entry(&wait_reset, 0);
12304 for (;;) {
12305 prepare_to_wait(&intel_state->commit_ready.wait,
12306 &wait_fence, TASK_UNINTERRUPTIBLE);
12307 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12308 &wait_reset, TASK_UNINTERRUPTIBLE);
12309
12310
12311 if (i915_sw_fence_done(&intel_state->commit_ready)
12312 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12313 break;
12314
12315 schedule();
12316 }
12317 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12318 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12319 }
12320
12321 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12322 {
12323 struct drm_device *dev = state->dev;
12324 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12325 struct drm_i915_private *dev_priv = to_i915(dev);
12326 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12327 struct drm_crtc *crtc;
12328 struct intel_crtc_state *intel_cstate;
12329 u64 put_domains[I915_MAX_PIPES] = {};
12330 int i;
12331
12332 intel_atomic_commit_fence_wait(intel_state);
12333
12334 drm_atomic_helper_wait_for_dependencies(state);
12335
12336 if (intel_state->modeset)
12337 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12338
12339 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12341
12342 if (needs_modeset(new_crtc_state) ||
12343 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12344
12345 put_domains[to_intel_crtc(crtc)->pipe] =
12346 modeset_get_crtc_power_domains(crtc,
12347 to_intel_crtc_state(new_crtc_state));
12348 }
12349
12350 if (!needs_modeset(new_crtc_state))
12351 continue;
12352
12353 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12354 to_intel_crtc_state(new_crtc_state));
12355
12356 if (old_crtc_state->active) {
12357 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12358 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12359 intel_crtc->active = false;
12360 intel_fbc_disable(intel_crtc);
12361 intel_disable_shared_dpll(intel_crtc);
12362
12363 /*
12364 * Underruns don't always raise
12365 * interrupts, so check manually.
12366 */
12367 intel_check_cpu_fifo_underruns(dev_priv);
12368 intel_check_pch_fifo_underruns(dev_priv);
12369
12370 /* FIXME unify this for all platforms */
12371 if (!new_crtc_state->active &&
12372 !HAS_GMCH_DISPLAY(dev_priv) &&
12373 dev_priv->display.initial_watermarks)
12374 dev_priv->display.initial_watermarks(intel_state,
12375 to_intel_crtc_state(new_crtc_state));
12376 }
12377 }
12378
12379 /* Only after disabling all output pipelines that will be changed can we
12380 * update the the output configuration. */
12381 intel_modeset_update_crtc_state(state);
12382
12383 if (intel_state->modeset) {
12384 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12385
12386 intel_set_cdclk_pre_plane_update(dev_priv,
12387 &intel_state->cdclk.actual,
12388 &dev_priv->cdclk.actual,
12389 intel_state->cdclk.pipe);
12390
12391 /*
12392 * SKL workaround: bspec recommends we disable the SAGV when we
12393 * have more then one pipe enabled
12394 */
12395 if (!intel_can_enable_sagv(state))
12396 intel_disable_sagv(dev_priv);
12397
12398 intel_modeset_verify_disabled(dev, state);
12399 }
12400
12401 /* Complete the events for pipes that have now been disabled */
12402 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12403 bool modeset = needs_modeset(new_crtc_state);
12404
12405 /* Complete events for now disable pipes here. */
12406 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12407 spin_lock_irq(&dev->event_lock);
12408 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12409 spin_unlock_irq(&dev->event_lock);
12410
12411 new_crtc_state->event = NULL;
12412 }
12413 }
12414
12415 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12416 dev_priv->display.update_crtcs(state);
12417
12418 if (intel_state->modeset)
12419 intel_set_cdclk_post_plane_update(dev_priv,
12420 &intel_state->cdclk.actual,
12421 &dev_priv->cdclk.actual,
12422 intel_state->cdclk.pipe);
12423
12424 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12425 * already, but still need the state for the delayed optimization. To
12426 * fix this:
12427 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12428 * - schedule that vblank worker _before_ calling hw_done
12429 * - at the start of commit_tail, cancel it _synchrously
12430 * - switch over to the vblank wait helper in the core after that since
12431 * we don't need out special handling any more.
12432 */
12433 drm_atomic_helper_wait_for_flip_done(dev, state);
12434
12435 /*
12436 * Now that the vblank has passed, we can go ahead and program the
12437 * optimal watermarks on platforms that need two-step watermark
12438 * programming.
12439 *
12440 * TODO: Move this (and other cleanup) to an async worker eventually.
12441 */
12442 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12443 intel_cstate = to_intel_crtc_state(new_crtc_state);
12444
12445 if (dev_priv->display.optimize_watermarks)
12446 dev_priv->display.optimize_watermarks(intel_state,
12447 intel_cstate);
12448 }
12449
12450 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12451 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12452
12453 if (put_domains[i])
12454 modeset_put_power_domains(dev_priv, put_domains[i]);
12455
12456 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12457 }
12458
12459 if (intel_state->modeset && intel_can_enable_sagv(state))
12460 intel_enable_sagv(dev_priv);
12461
12462 drm_atomic_helper_commit_hw_done(state);
12463
12464 if (intel_state->modeset) {
12465 /* As one of the primary mmio accessors, KMS has a high
12466 * likelihood of triggering bugs in unclaimed access. After we
12467 * finish modesetting, see if an error has been flagged, and if
12468 * so enable debugging for the next modeset - and hope we catch
12469 * the culprit.
12470 */
12471 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12472 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12473 }
12474
12475 drm_atomic_helper_cleanup_planes(dev, state);
12476
12477 drm_atomic_helper_commit_cleanup_done(state);
12478
12479 drm_atomic_state_put(state);
12480
12481 intel_atomic_helper_free_state(dev_priv);
12482 }
12483
12484 static void intel_atomic_commit_work(struct work_struct *work)
12485 {
12486 struct drm_atomic_state *state =
12487 container_of(work, struct drm_atomic_state, commit_work);
12488
12489 intel_atomic_commit_tail(state);
12490 }
12491
12492 static int __i915_sw_fence_call
12493 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12494 enum i915_sw_fence_notify notify)
12495 {
12496 struct intel_atomic_state *state =
12497 container_of(fence, struct intel_atomic_state, commit_ready);
12498
12499 switch (notify) {
12500 case FENCE_COMPLETE:
12501 /* we do blocking waits in the worker, nothing to do here */
12502 break;
12503 case FENCE_FREE:
12504 {
12505 struct intel_atomic_helper *helper =
12506 &to_i915(state->base.dev)->atomic_helper;
12507
12508 if (llist_add(&state->freed, &helper->free_list))
12509 schedule_work(&helper->free_work);
12510 break;
12511 }
12512 }
12513
12514 return NOTIFY_DONE;
12515 }
12516
12517 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12518 {
12519 struct drm_plane_state *old_plane_state, *new_plane_state;
12520 struct drm_plane *plane;
12521 int i;
12522
12523 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12524 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12525 intel_fb_obj(new_plane_state->fb),
12526 to_intel_plane(plane)->frontbuffer_bit);
12527 }
12528
12529 /**
12530 * intel_atomic_commit - commit validated state object
12531 * @dev: DRM device
12532 * @state: the top-level driver state object
12533 * @nonblock: nonblocking commit
12534 *
12535 * This function commits a top-level state object that has been validated
12536 * with drm_atomic_helper_check().
12537 *
12538 * RETURNS
12539 * Zero for success or -errno.
12540 */
12541 static int intel_atomic_commit(struct drm_device *dev,
12542 struct drm_atomic_state *state,
12543 bool nonblock)
12544 {
12545 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12546 struct drm_i915_private *dev_priv = to_i915(dev);
12547 int ret = 0;
12548
12549 drm_atomic_state_get(state);
12550 i915_sw_fence_init(&intel_state->commit_ready,
12551 intel_atomic_commit_ready);
12552
12553 /*
12554 * The intel_legacy_cursor_update() fast path takes care
12555 * of avoiding the vblank waits for simple cursor
12556 * movement and flips. For cursor on/off and size changes,
12557 * we want to perform the vblank waits so that watermark
12558 * updates happen during the correct frames. Gen9+ have
12559 * double buffered watermarks and so shouldn't need this.
12560 *
12561 * Unset state->legacy_cursor_update before the call to
12562 * drm_atomic_helper_setup_commit() because otherwise
12563 * drm_atomic_helper_wait_for_flip_done() is a noop and
12564 * we get FIFO underruns because we didn't wait
12565 * for vblank.
12566 *
12567 * FIXME doing watermarks and fb cleanup from a vblank worker
12568 * (assuming we had any) would solve these problems.
12569 */
12570 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12571 struct intel_crtc_state *new_crtc_state;
12572 struct intel_crtc *crtc;
12573 int i;
12574
12575 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12576 if (new_crtc_state->wm.need_postvbl_update ||
12577 new_crtc_state->update_wm_post)
12578 state->legacy_cursor_update = false;
12579 }
12580
12581 ret = intel_atomic_prepare_commit(dev, state);
12582 if (ret) {
12583 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12584 i915_sw_fence_commit(&intel_state->commit_ready);
12585 return ret;
12586 }
12587
12588 ret = drm_atomic_helper_setup_commit(state, nonblock);
12589 if (!ret)
12590 ret = drm_atomic_helper_swap_state(state, true);
12591
12592 if (ret) {
12593 i915_sw_fence_commit(&intel_state->commit_ready);
12594
12595 drm_atomic_helper_cleanup_planes(dev, state);
12596 return ret;
12597 }
12598 dev_priv->wm.distrust_bios_wm = false;
12599 intel_shared_dpll_swap_state(state);
12600 intel_atomic_track_fbs(state);
12601
12602 if (intel_state->modeset) {
12603 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12604 sizeof(intel_state->min_cdclk));
12605 dev_priv->active_crtcs = intel_state->active_crtcs;
12606 dev_priv->cdclk.force_min_cdclk =
12607 intel_state->cdclk.force_min_cdclk;
12608
12609 intel_cdclk_swap_state(intel_state);
12610 }
12611
12612 drm_atomic_state_get(state);
12613 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12614
12615 i915_sw_fence_commit(&intel_state->commit_ready);
12616 if (nonblock && intel_state->modeset) {
12617 queue_work(dev_priv->modeset_wq, &state->commit_work);
12618 } else if (nonblock) {
12619 queue_work(system_unbound_wq, &state->commit_work);
12620 } else {
12621 if (intel_state->modeset)
12622 flush_workqueue(dev_priv->modeset_wq);
12623 intel_atomic_commit_tail(state);
12624 }
12625
12626 return 0;
12627 }
12628
12629 static const struct drm_crtc_funcs intel_crtc_funcs = {
12630 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12631 .set_config = drm_atomic_helper_set_config,
12632 .destroy = intel_crtc_destroy,
12633 .page_flip = drm_atomic_helper_page_flip,
12634 .atomic_duplicate_state = intel_crtc_duplicate_state,
12635 .atomic_destroy_state = intel_crtc_destroy_state,
12636 .set_crc_source = intel_crtc_set_crc_source,
12637 };
12638
12639 struct wait_rps_boost {
12640 struct wait_queue_entry wait;
12641
12642 struct drm_crtc *crtc;
12643 struct drm_i915_gem_request *request;
12644 };
12645
12646 static int do_rps_boost(struct wait_queue_entry *_wait,
12647 unsigned mode, int sync, void *key)
12648 {
12649 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12650 struct drm_i915_gem_request *rq = wait->request;
12651
12652 gen6_rps_boost(rq, NULL);
12653 i915_gem_request_put(rq);
12654
12655 drm_crtc_vblank_put(wait->crtc);
12656
12657 list_del(&wait->wait.entry);
12658 kfree(wait);
12659 return 1;
12660 }
12661
12662 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12663 struct dma_fence *fence)
12664 {
12665 struct wait_rps_boost *wait;
12666
12667 if (!dma_fence_is_i915(fence))
12668 return;
12669
12670 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12671 return;
12672
12673 if (drm_crtc_vblank_get(crtc))
12674 return;
12675
12676 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12677 if (!wait) {
12678 drm_crtc_vblank_put(crtc);
12679 return;
12680 }
12681
12682 wait->request = to_request(dma_fence_get(fence));
12683 wait->crtc = crtc;
12684
12685 wait->wait.func = do_rps_boost;
12686 wait->wait.flags = 0;
12687
12688 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12689 }
12690
12691 /**
12692 * intel_prepare_plane_fb - Prepare fb for usage on plane
12693 * @plane: drm plane to prepare for
12694 * @fb: framebuffer to prepare for presentation
12695 *
12696 * Prepares a framebuffer for usage on a display plane. Generally this
12697 * involves pinning the underlying object and updating the frontbuffer tracking
12698 * bits. Some older platforms need special physical address handling for
12699 * cursor planes.
12700 *
12701 * Must be called with struct_mutex held.
12702 *
12703 * Returns 0 on success, negative error code on failure.
12704 */
12705 int
12706 intel_prepare_plane_fb(struct drm_plane *plane,
12707 struct drm_plane_state *new_state)
12708 {
12709 struct intel_atomic_state *intel_state =
12710 to_intel_atomic_state(new_state->state);
12711 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12712 struct drm_framebuffer *fb = new_state->fb;
12713 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12714 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12715 int ret;
12716
12717 if (old_obj) {
12718 struct drm_crtc_state *crtc_state =
12719 drm_atomic_get_existing_crtc_state(new_state->state,
12720 plane->state->crtc);
12721
12722 /* Big Hammer, we also need to ensure that any pending
12723 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12724 * current scanout is retired before unpinning the old
12725 * framebuffer. Note that we rely on userspace rendering
12726 * into the buffer attached to the pipe they are waiting
12727 * on. If not, userspace generates a GPU hang with IPEHR
12728 * point to the MI_WAIT_FOR_EVENT.
12729 *
12730 * This should only fail upon a hung GPU, in which case we
12731 * can safely continue.
12732 */
12733 if (needs_modeset(crtc_state)) {
12734 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12735 old_obj->resv, NULL,
12736 false, 0,
12737 GFP_KERNEL);
12738 if (ret < 0)
12739 return ret;
12740 }
12741 }
12742
12743 if (new_state->fence) { /* explicit fencing */
12744 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12745 new_state->fence,
12746 I915_FENCE_TIMEOUT,
12747 GFP_KERNEL);
12748 if (ret < 0)
12749 return ret;
12750 }
12751
12752 if (!obj)
12753 return 0;
12754
12755 ret = i915_gem_object_pin_pages(obj);
12756 if (ret)
12757 return ret;
12758
12759 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12760 if (ret) {
12761 i915_gem_object_unpin_pages(obj);
12762 return ret;
12763 }
12764
12765 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12766 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12767 const int align = intel_cursor_alignment(dev_priv);
12768
12769 ret = i915_gem_object_attach_phys(obj, align);
12770 } else {
12771 struct i915_vma *vma;
12772
12773 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12774 if (!IS_ERR(vma))
12775 to_intel_plane_state(new_state)->vma = vma;
12776 else
12777 ret = PTR_ERR(vma);
12778 }
12779
12780 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12781
12782 mutex_unlock(&dev_priv->drm.struct_mutex);
12783 i915_gem_object_unpin_pages(obj);
12784 if (ret)
12785 return ret;
12786
12787 if (!new_state->fence) { /* implicit fencing */
12788 struct dma_fence *fence;
12789
12790 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12791 obj->resv, NULL,
12792 false, I915_FENCE_TIMEOUT,
12793 GFP_KERNEL);
12794 if (ret < 0)
12795 return ret;
12796
12797 fence = reservation_object_get_excl_rcu(obj->resv);
12798 if (fence) {
12799 add_rps_boost_after_vblank(new_state->crtc, fence);
12800 dma_fence_put(fence);
12801 }
12802 } else {
12803 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12804 }
12805
12806 return 0;
12807 }
12808
12809 /**
12810 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12811 * @plane: drm plane to clean up for
12812 * @fb: old framebuffer that was on plane
12813 *
12814 * Cleans up a framebuffer that has just been removed from a plane.
12815 *
12816 * Must be called with struct_mutex held.
12817 */
12818 void
12819 intel_cleanup_plane_fb(struct drm_plane *plane,
12820 struct drm_plane_state *old_state)
12821 {
12822 struct i915_vma *vma;
12823
12824 /* Should only be called after a successful intel_prepare_plane_fb()! */
12825 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12826 if (vma) {
12827 mutex_lock(&plane->dev->struct_mutex);
12828 intel_unpin_fb_vma(vma);
12829 mutex_unlock(&plane->dev->struct_mutex);
12830 }
12831 }
12832
12833 int
12834 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12835 {
12836 struct drm_i915_private *dev_priv;
12837 int max_scale;
12838 int crtc_clock, max_dotclk;
12839
12840 if (!intel_crtc || !crtc_state->base.enable)
12841 return DRM_PLANE_HELPER_NO_SCALING;
12842
12843 dev_priv = to_i915(intel_crtc->base.dev);
12844
12845 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12846 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12847
12848 if (IS_GEMINILAKE(dev_priv))
12849 max_dotclk *= 2;
12850
12851 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12852 return DRM_PLANE_HELPER_NO_SCALING;
12853
12854 /*
12855 * skl max scale is lower of:
12856 * close to 3 but not 3, -1 is for that purpose
12857 * or
12858 * cdclk/crtc_clock
12859 */
12860 max_scale = min((1 << 16) * 3 - 1,
12861 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12862
12863 return max_scale;
12864 }
12865
12866 static int
12867 intel_check_primary_plane(struct intel_plane *plane,
12868 struct intel_crtc_state *crtc_state,
12869 struct intel_plane_state *state)
12870 {
12871 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12872 struct drm_crtc *crtc = state->base.crtc;
12873 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12874 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12875 bool can_position = false;
12876 int ret;
12877
12878 if (INTEL_GEN(dev_priv) >= 9) {
12879 /* use scaler when colorkey is not required */
12880 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12881 min_scale = 1;
12882 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12883 }
12884 can_position = true;
12885 }
12886
12887 ret = drm_plane_helper_check_state(&state->base,
12888 &state->clip,
12889 min_scale, max_scale,
12890 can_position, true);
12891 if (ret)
12892 return ret;
12893
12894 if (!state->base.fb)
12895 return 0;
12896
12897 if (INTEL_GEN(dev_priv) >= 9) {
12898 ret = skl_check_plane_surface(state);
12899 if (ret)
12900 return ret;
12901
12902 state->ctl = skl_plane_ctl(crtc_state, state);
12903 } else {
12904 ret = i9xx_check_plane_surface(state);
12905 if (ret)
12906 return ret;
12907
12908 state->ctl = i9xx_plane_ctl(crtc_state, state);
12909 }
12910
12911 return 0;
12912 }
12913
12914 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12915 struct drm_crtc_state *old_crtc_state)
12916 {
12917 struct drm_device *dev = crtc->dev;
12918 struct drm_i915_private *dev_priv = to_i915(dev);
12919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12920 struct intel_crtc_state *old_intel_cstate =
12921 to_intel_crtc_state(old_crtc_state);
12922 struct intel_atomic_state *old_intel_state =
12923 to_intel_atomic_state(old_crtc_state->state);
12924 struct intel_crtc_state *intel_cstate =
12925 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12926 bool modeset = needs_modeset(&intel_cstate->base);
12927
12928 if (!modeset &&
12929 (intel_cstate->base.color_mgmt_changed ||
12930 intel_cstate->update_pipe)) {
12931 intel_color_set_csc(&intel_cstate->base);
12932 intel_color_load_luts(&intel_cstate->base);
12933 }
12934
12935 /* Perform vblank evasion around commit operation */
12936 intel_pipe_update_start(intel_cstate);
12937
12938 if (modeset)
12939 goto out;
12940
12941 if (intel_cstate->update_pipe)
12942 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12943 else if (INTEL_GEN(dev_priv) >= 9)
12944 skl_detach_scalers(intel_crtc);
12945
12946 out:
12947 if (dev_priv->display.atomic_update_watermarks)
12948 dev_priv->display.atomic_update_watermarks(old_intel_state,
12949 intel_cstate);
12950 }
12951
12952 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12953 struct drm_crtc_state *old_crtc_state)
12954 {
12955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12956 struct intel_atomic_state *old_intel_state =
12957 to_intel_atomic_state(old_crtc_state->state);
12958 struct intel_crtc_state *new_crtc_state =
12959 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12960
12961 intel_pipe_update_end(new_crtc_state);
12962 }
12963
12964 /**
12965 * intel_plane_destroy - destroy a plane
12966 * @plane: plane to destroy
12967 *
12968 * Common destruction function for all types of planes (primary, cursor,
12969 * sprite).
12970 */
12971 void intel_plane_destroy(struct drm_plane *plane)
12972 {
12973 drm_plane_cleanup(plane);
12974 kfree(to_intel_plane(plane));
12975 }
12976
12977 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12978 {
12979 switch (format) {
12980 case DRM_FORMAT_C8:
12981 case DRM_FORMAT_RGB565:
12982 case DRM_FORMAT_XRGB1555:
12983 case DRM_FORMAT_XRGB8888:
12984 return modifier == DRM_FORMAT_MOD_LINEAR ||
12985 modifier == I915_FORMAT_MOD_X_TILED;
12986 default:
12987 return false;
12988 }
12989 }
12990
12991 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12992 {
12993 switch (format) {
12994 case DRM_FORMAT_C8:
12995 case DRM_FORMAT_RGB565:
12996 case DRM_FORMAT_XRGB8888:
12997 case DRM_FORMAT_XBGR8888:
12998 case DRM_FORMAT_XRGB2101010:
12999 case DRM_FORMAT_XBGR2101010:
13000 return modifier == DRM_FORMAT_MOD_LINEAR ||
13001 modifier == I915_FORMAT_MOD_X_TILED;
13002 default:
13003 return false;
13004 }
13005 }
13006
13007 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13008 {
13009 switch (format) {
13010 case DRM_FORMAT_XRGB8888:
13011 case DRM_FORMAT_XBGR8888:
13012 case DRM_FORMAT_ARGB8888:
13013 case DRM_FORMAT_ABGR8888:
13014 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13015 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13016 return true;
13017 /* fall through */
13018 case DRM_FORMAT_RGB565:
13019 case DRM_FORMAT_XRGB2101010:
13020 case DRM_FORMAT_XBGR2101010:
13021 case DRM_FORMAT_YUYV:
13022 case DRM_FORMAT_YVYU:
13023 case DRM_FORMAT_UYVY:
13024 case DRM_FORMAT_VYUY:
13025 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13026 return true;
13027 /* fall through */
13028 case DRM_FORMAT_C8:
13029 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13030 modifier == I915_FORMAT_MOD_X_TILED ||
13031 modifier == I915_FORMAT_MOD_Y_TILED)
13032 return true;
13033 /* fall through */
13034 default:
13035 return false;
13036 }
13037 }
13038
13039 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13040 uint32_t format,
13041 uint64_t modifier)
13042 {
13043 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13044
13045 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13046 return false;
13047
13048 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13049 modifier != DRM_FORMAT_MOD_LINEAR)
13050 return false;
13051
13052 if (INTEL_GEN(dev_priv) >= 9)
13053 return skl_mod_supported(format, modifier);
13054 else if (INTEL_GEN(dev_priv) >= 4)
13055 return i965_mod_supported(format, modifier);
13056 else
13057 return i8xx_mod_supported(format, modifier);
13058
13059 unreachable();
13060 }
13061
13062 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13063 uint32_t format,
13064 uint64_t modifier)
13065 {
13066 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13067 return false;
13068
13069 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13070 }
13071
13072 static struct drm_plane_funcs intel_plane_funcs = {
13073 .update_plane = drm_atomic_helper_update_plane,
13074 .disable_plane = drm_atomic_helper_disable_plane,
13075 .destroy = intel_plane_destroy,
13076 .atomic_get_property = intel_plane_atomic_get_property,
13077 .atomic_set_property = intel_plane_atomic_set_property,
13078 .atomic_duplicate_state = intel_plane_duplicate_state,
13079 .atomic_destroy_state = intel_plane_destroy_state,
13080 .format_mod_supported = intel_primary_plane_format_mod_supported,
13081 };
13082
13083 static int
13084 intel_legacy_cursor_update(struct drm_plane *plane,
13085 struct drm_crtc *crtc,
13086 struct drm_framebuffer *fb,
13087 int crtc_x, int crtc_y,
13088 unsigned int crtc_w, unsigned int crtc_h,
13089 uint32_t src_x, uint32_t src_y,
13090 uint32_t src_w, uint32_t src_h,
13091 struct drm_modeset_acquire_ctx *ctx)
13092 {
13093 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13094 int ret;
13095 struct drm_plane_state *old_plane_state, *new_plane_state;
13096 struct intel_plane *intel_plane = to_intel_plane(plane);
13097 struct drm_framebuffer *old_fb;
13098 struct drm_crtc_state *crtc_state = crtc->state;
13099 struct i915_vma *old_vma, *vma;
13100
13101 /*
13102 * When crtc is inactive or there is a modeset pending,
13103 * wait for it to complete in the slowpath
13104 */
13105 if (!crtc_state->active || needs_modeset(crtc_state) ||
13106 to_intel_crtc_state(crtc_state)->update_pipe)
13107 goto slow;
13108
13109 old_plane_state = plane->state;
13110 /*
13111 * Don't do an async update if there is an outstanding commit modifying
13112 * the plane. This prevents our async update's changes from getting
13113 * overridden by a previous synchronous update's state.
13114 */
13115 if (old_plane_state->commit &&
13116 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13117 goto slow;
13118
13119 /*
13120 * If any parameters change that may affect watermarks,
13121 * take the slowpath. Only changing fb or position should be
13122 * in the fastpath.
13123 */
13124 if (old_plane_state->crtc != crtc ||
13125 old_plane_state->src_w != src_w ||
13126 old_plane_state->src_h != src_h ||
13127 old_plane_state->crtc_w != crtc_w ||
13128 old_plane_state->crtc_h != crtc_h ||
13129 !old_plane_state->fb != !fb)
13130 goto slow;
13131
13132 new_plane_state = intel_plane_duplicate_state(plane);
13133 if (!new_plane_state)
13134 return -ENOMEM;
13135
13136 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13137
13138 new_plane_state->src_x = src_x;
13139 new_plane_state->src_y = src_y;
13140 new_plane_state->src_w = src_w;
13141 new_plane_state->src_h = src_h;
13142 new_plane_state->crtc_x = crtc_x;
13143 new_plane_state->crtc_y = crtc_y;
13144 new_plane_state->crtc_w = crtc_w;
13145 new_plane_state->crtc_h = crtc_h;
13146
13147 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13148 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13149 to_intel_plane_state(plane->state),
13150 to_intel_plane_state(new_plane_state));
13151 if (ret)
13152 goto out_free;
13153
13154 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13155 if (ret)
13156 goto out_free;
13157
13158 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13159 int align = intel_cursor_alignment(dev_priv);
13160
13161 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13162 if (ret) {
13163 DRM_DEBUG_KMS("failed to attach phys object\n");
13164 goto out_unlock;
13165 }
13166 } else {
13167 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13168 if (IS_ERR(vma)) {
13169 DRM_DEBUG_KMS("failed to pin object\n");
13170
13171 ret = PTR_ERR(vma);
13172 goto out_unlock;
13173 }
13174
13175 to_intel_plane_state(new_plane_state)->vma = vma;
13176 }
13177
13178 old_fb = old_plane_state->fb;
13179
13180 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13181 intel_plane->frontbuffer_bit);
13182
13183 /* Swap plane state */
13184 plane->state = new_plane_state;
13185
13186 if (plane->state->visible) {
13187 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13188 intel_plane->update_plane(intel_plane,
13189 to_intel_crtc_state(crtc->state),
13190 to_intel_plane_state(plane->state));
13191 } else {
13192 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13193 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13194 }
13195
13196 old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13197 if (old_vma)
13198 intel_unpin_fb_vma(old_vma);
13199
13200 out_unlock:
13201 mutex_unlock(&dev_priv->drm.struct_mutex);
13202 out_free:
13203 if (ret)
13204 intel_plane_destroy_state(plane, new_plane_state);
13205 else
13206 intel_plane_destroy_state(plane, old_plane_state);
13207 return ret;
13208
13209 slow:
13210 return drm_atomic_helper_update_plane(plane, crtc, fb,
13211 crtc_x, crtc_y, crtc_w, crtc_h,
13212 src_x, src_y, src_w, src_h, ctx);
13213 }
13214
13215 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13216 .update_plane = intel_legacy_cursor_update,
13217 .disable_plane = drm_atomic_helper_disable_plane,
13218 .destroy = intel_plane_destroy,
13219 .atomic_get_property = intel_plane_atomic_get_property,
13220 .atomic_set_property = intel_plane_atomic_set_property,
13221 .atomic_duplicate_state = intel_plane_duplicate_state,
13222 .atomic_destroy_state = intel_plane_destroy_state,
13223 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13224 };
13225
13226 static struct intel_plane *
13227 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13228 {
13229 struct intel_plane *primary = NULL;
13230 struct intel_plane_state *state = NULL;
13231 const uint32_t *intel_primary_formats;
13232 unsigned int supported_rotations;
13233 unsigned int num_formats;
13234 const uint64_t *modifiers;
13235 int ret;
13236
13237 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13238 if (!primary) {
13239 ret = -ENOMEM;
13240 goto fail;
13241 }
13242
13243 state = intel_create_plane_state(&primary->base);
13244 if (!state) {
13245 ret = -ENOMEM;
13246 goto fail;
13247 }
13248
13249 primary->base.state = &state->base;
13250
13251 primary->can_scale = false;
13252 primary->max_downscale = 1;
13253 if (INTEL_GEN(dev_priv) >= 9) {
13254 primary->can_scale = true;
13255 state->scaler_id = -1;
13256 }
13257 primary->pipe = pipe;
13258 /*
13259 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13260 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13261 */
13262 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13263 primary->plane = (enum plane) !pipe;
13264 else
13265 primary->plane = (enum plane) pipe;
13266 primary->id = PLANE_PRIMARY;
13267 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13268 primary->check_plane = intel_check_primary_plane;
13269
13270 if (INTEL_GEN(dev_priv) >= 10) {
13271 intel_primary_formats = skl_primary_formats;
13272 num_formats = ARRAY_SIZE(skl_primary_formats);
13273 modifiers = skl_format_modifiers_ccs;
13274
13275 primary->update_plane = skl_update_plane;
13276 primary->disable_plane = skl_disable_plane;
13277 primary->get_hw_state = skl_plane_get_hw_state;
13278 } else if (INTEL_GEN(dev_priv) >= 9) {
13279 intel_primary_formats = skl_primary_formats;
13280 num_formats = ARRAY_SIZE(skl_primary_formats);
13281 if (pipe < PIPE_C)
13282 modifiers = skl_format_modifiers_ccs;
13283 else
13284 modifiers = skl_format_modifiers_noccs;
13285
13286 primary->update_plane = skl_update_plane;
13287 primary->disable_plane = skl_disable_plane;
13288 primary->get_hw_state = skl_plane_get_hw_state;
13289 } else if (INTEL_GEN(dev_priv) >= 4) {
13290 intel_primary_formats = i965_primary_formats;
13291 num_formats = ARRAY_SIZE(i965_primary_formats);
13292 modifiers = i9xx_format_modifiers;
13293
13294 primary->update_plane = i9xx_update_primary_plane;
13295 primary->disable_plane = i9xx_disable_primary_plane;
13296 primary->get_hw_state = i9xx_plane_get_hw_state;
13297 } else {
13298 intel_primary_formats = i8xx_primary_formats;
13299 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13300 modifiers = i9xx_format_modifiers;
13301
13302 primary->update_plane = i9xx_update_primary_plane;
13303 primary->disable_plane = i9xx_disable_primary_plane;
13304 primary->get_hw_state = i9xx_plane_get_hw_state;
13305 }
13306
13307 if (INTEL_GEN(dev_priv) >= 9)
13308 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13309 0, &intel_plane_funcs,
13310 intel_primary_formats, num_formats,
13311 modifiers,
13312 DRM_PLANE_TYPE_PRIMARY,
13313 "plane 1%c", pipe_name(pipe));
13314 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13315 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13316 0, &intel_plane_funcs,
13317 intel_primary_formats, num_formats,
13318 modifiers,
13319 DRM_PLANE_TYPE_PRIMARY,
13320 "primary %c", pipe_name(pipe));
13321 else
13322 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13323 0, &intel_plane_funcs,
13324 intel_primary_formats, num_formats,
13325 modifiers,
13326 DRM_PLANE_TYPE_PRIMARY,
13327 "plane %c", plane_name(primary->plane));
13328 if (ret)
13329 goto fail;
13330
13331 if (INTEL_GEN(dev_priv) >= 9) {
13332 supported_rotations =
13333 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13334 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13335 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13336 supported_rotations =
13337 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13338 DRM_MODE_REFLECT_X;
13339 } else if (INTEL_GEN(dev_priv) >= 4) {
13340 supported_rotations =
13341 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13342 } else {
13343 supported_rotations = DRM_MODE_ROTATE_0;
13344 }
13345
13346 if (INTEL_GEN(dev_priv) >= 4)
13347 drm_plane_create_rotation_property(&primary->base,
13348 DRM_MODE_ROTATE_0,
13349 supported_rotations);
13350
13351 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13352
13353 return primary;
13354
13355 fail:
13356 kfree(state);
13357 kfree(primary);
13358
13359 return ERR_PTR(ret);
13360 }
13361
13362 static struct intel_plane *
13363 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13364 enum pipe pipe)
13365 {
13366 struct intel_plane *cursor = NULL;
13367 struct intel_plane_state *state = NULL;
13368 int ret;
13369
13370 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13371 if (!cursor) {
13372 ret = -ENOMEM;
13373 goto fail;
13374 }
13375
13376 state = intel_create_plane_state(&cursor->base);
13377 if (!state) {
13378 ret = -ENOMEM;
13379 goto fail;
13380 }
13381
13382 cursor->base.state = &state->base;
13383
13384 cursor->can_scale = false;
13385 cursor->max_downscale = 1;
13386 cursor->pipe = pipe;
13387 cursor->plane = pipe;
13388 cursor->id = PLANE_CURSOR;
13389 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13390
13391 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13392 cursor->update_plane = i845_update_cursor;
13393 cursor->disable_plane = i845_disable_cursor;
13394 cursor->get_hw_state = i845_cursor_get_hw_state;
13395 cursor->check_plane = i845_check_cursor;
13396 } else {
13397 cursor->update_plane = i9xx_update_cursor;
13398 cursor->disable_plane = i9xx_disable_cursor;
13399 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13400 cursor->check_plane = i9xx_check_cursor;
13401 }
13402
13403 cursor->cursor.base = ~0;
13404 cursor->cursor.cntl = ~0;
13405
13406 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13407 cursor->cursor.size = ~0;
13408
13409 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13410 0, &intel_cursor_plane_funcs,
13411 intel_cursor_formats,
13412 ARRAY_SIZE(intel_cursor_formats),
13413 cursor_format_modifiers,
13414 DRM_PLANE_TYPE_CURSOR,
13415 "cursor %c", pipe_name(pipe));
13416 if (ret)
13417 goto fail;
13418
13419 if (INTEL_GEN(dev_priv) >= 4)
13420 drm_plane_create_rotation_property(&cursor->base,
13421 DRM_MODE_ROTATE_0,
13422 DRM_MODE_ROTATE_0 |
13423 DRM_MODE_ROTATE_180);
13424
13425 if (INTEL_GEN(dev_priv) >= 9)
13426 state->scaler_id = -1;
13427
13428 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13429
13430 return cursor;
13431
13432 fail:
13433 kfree(state);
13434 kfree(cursor);
13435
13436 return ERR_PTR(ret);
13437 }
13438
13439 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13440 struct intel_crtc_state *crtc_state)
13441 {
13442 struct intel_crtc_scaler_state *scaler_state =
13443 &crtc_state->scaler_state;
13444 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13445 int i;
13446
13447 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13448 if (!crtc->num_scalers)
13449 return;
13450
13451 for (i = 0; i < crtc->num_scalers; i++) {
13452 struct intel_scaler *scaler = &scaler_state->scalers[i];
13453
13454 scaler->in_use = 0;
13455 scaler->mode = PS_SCALER_MODE_DYN;
13456 }
13457
13458 scaler_state->scaler_id = -1;
13459 }
13460
13461 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13462 {
13463 struct intel_crtc *intel_crtc;
13464 struct intel_crtc_state *crtc_state = NULL;
13465 struct intel_plane *primary = NULL;
13466 struct intel_plane *cursor = NULL;
13467 int sprite, ret;
13468
13469 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13470 if (!intel_crtc)
13471 return -ENOMEM;
13472
13473 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13474 if (!crtc_state) {
13475 ret = -ENOMEM;
13476 goto fail;
13477 }
13478 intel_crtc->config = crtc_state;
13479 intel_crtc->base.state = &crtc_state->base;
13480 crtc_state->base.crtc = &intel_crtc->base;
13481
13482 primary = intel_primary_plane_create(dev_priv, pipe);
13483 if (IS_ERR(primary)) {
13484 ret = PTR_ERR(primary);
13485 goto fail;
13486 }
13487 intel_crtc->plane_ids_mask |= BIT(primary->id);
13488
13489 for_each_sprite(dev_priv, pipe, sprite) {
13490 struct intel_plane *plane;
13491
13492 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13493 if (IS_ERR(plane)) {
13494 ret = PTR_ERR(plane);
13495 goto fail;
13496 }
13497 intel_crtc->plane_ids_mask |= BIT(plane->id);
13498 }
13499
13500 cursor = intel_cursor_plane_create(dev_priv, pipe);
13501 if (IS_ERR(cursor)) {
13502 ret = PTR_ERR(cursor);
13503 goto fail;
13504 }
13505 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13506
13507 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13508 &primary->base, &cursor->base,
13509 &intel_crtc_funcs,
13510 "pipe %c", pipe_name(pipe));
13511 if (ret)
13512 goto fail;
13513
13514 intel_crtc->pipe = pipe;
13515 intel_crtc->plane = primary->plane;
13516
13517 /* initialize shared scalers */
13518 intel_crtc_init_scalers(intel_crtc, crtc_state);
13519
13520 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13521 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13522 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13523 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13524
13525 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13526
13527 intel_color_init(&intel_crtc->base);
13528
13529 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13530
13531 return 0;
13532
13533 fail:
13534 /*
13535 * drm_mode_config_cleanup() will free up any
13536 * crtcs/planes already initialized.
13537 */
13538 kfree(crtc_state);
13539 kfree(intel_crtc);
13540
13541 return ret;
13542 }
13543
13544 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13545 {
13546 struct drm_device *dev = connector->base.dev;
13547
13548 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13549
13550 if (!connector->base.state->crtc)
13551 return INVALID_PIPE;
13552
13553 return to_intel_crtc(connector->base.state->crtc)->pipe;
13554 }
13555
13556 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13557 struct drm_file *file)
13558 {
13559 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13560 struct drm_crtc *drmmode_crtc;
13561 struct intel_crtc *crtc;
13562
13563 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13564 if (!drmmode_crtc)
13565 return -ENOENT;
13566
13567 crtc = to_intel_crtc(drmmode_crtc);
13568 pipe_from_crtc_id->pipe = crtc->pipe;
13569
13570 return 0;
13571 }
13572
13573 static int intel_encoder_clones(struct intel_encoder *encoder)
13574 {
13575 struct drm_device *dev = encoder->base.dev;
13576 struct intel_encoder *source_encoder;
13577 int index_mask = 0;
13578 int entry = 0;
13579
13580 for_each_intel_encoder(dev, source_encoder) {
13581 if (encoders_cloneable(encoder, source_encoder))
13582 index_mask |= (1 << entry);
13583
13584 entry++;
13585 }
13586
13587 return index_mask;
13588 }
13589
13590 static bool has_edp_a(struct drm_i915_private *dev_priv)
13591 {
13592 if (!IS_MOBILE(dev_priv))
13593 return false;
13594
13595 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13596 return false;
13597
13598 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13599 return false;
13600
13601 return true;
13602 }
13603
13604 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13605 {
13606 if (INTEL_GEN(dev_priv) >= 9)
13607 return false;
13608
13609 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13610 return false;
13611
13612 if (IS_CHERRYVIEW(dev_priv))
13613 return false;
13614
13615 if (HAS_PCH_LPT_H(dev_priv) &&
13616 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13617 return false;
13618
13619 /* DDI E can't be used if DDI A requires 4 lanes */
13620 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13621 return false;
13622
13623 if (!dev_priv->vbt.int_crt_support)
13624 return false;
13625
13626 return true;
13627 }
13628
13629 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13630 {
13631 int pps_num;
13632 int pps_idx;
13633
13634 if (HAS_DDI(dev_priv))
13635 return;
13636 /*
13637 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13638 * everywhere where registers can be write protected.
13639 */
13640 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13641 pps_num = 2;
13642 else
13643 pps_num = 1;
13644
13645 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13646 u32 val = I915_READ(PP_CONTROL(pps_idx));
13647
13648 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13649 I915_WRITE(PP_CONTROL(pps_idx), val);
13650 }
13651 }
13652
13653 static void intel_pps_init(struct drm_i915_private *dev_priv)
13654 {
13655 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13656 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13657 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13658 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13659 else
13660 dev_priv->pps_mmio_base = PPS_BASE;
13661
13662 intel_pps_unlock_regs_wa(dev_priv);
13663 }
13664
13665 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13666 {
13667 struct intel_encoder *encoder;
13668 bool dpd_is_edp = false;
13669
13670 intel_pps_init(dev_priv);
13671
13672 /*
13673 * intel_edp_init_connector() depends on this completing first, to
13674 * prevent the registeration of both eDP and LVDS and the incorrect
13675 * sharing of the PPS.
13676 */
13677 intel_lvds_init(dev_priv);
13678
13679 if (intel_crt_present(dev_priv))
13680 intel_crt_init(dev_priv);
13681
13682 if (IS_GEN9_LP(dev_priv)) {
13683 /*
13684 * FIXME: Broxton doesn't support port detection via the
13685 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13686 * detect the ports.
13687 */
13688 intel_ddi_init(dev_priv, PORT_A);
13689 intel_ddi_init(dev_priv, PORT_B);
13690 intel_ddi_init(dev_priv, PORT_C);
13691
13692 intel_dsi_init(dev_priv);
13693 } else if (HAS_DDI(dev_priv)) {
13694 int found;
13695
13696 /*
13697 * Haswell uses DDI functions to detect digital outputs.
13698 * On SKL pre-D0 the strap isn't connected, so we assume
13699 * it's there.
13700 */
13701 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13702 /* WaIgnoreDDIAStrap: skl */
13703 if (found || IS_GEN9_BC(dev_priv))
13704 intel_ddi_init(dev_priv, PORT_A);
13705
13706 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13707 * register */
13708 found = I915_READ(SFUSE_STRAP);
13709
13710 if (found & SFUSE_STRAP_DDIB_DETECTED)
13711 intel_ddi_init(dev_priv, PORT_B);
13712 if (found & SFUSE_STRAP_DDIC_DETECTED)
13713 intel_ddi_init(dev_priv, PORT_C);
13714 if (found & SFUSE_STRAP_DDID_DETECTED)
13715 intel_ddi_init(dev_priv, PORT_D);
13716 /*
13717 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13718 */
13719 if (IS_GEN9_BC(dev_priv) &&
13720 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13721 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13722 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13723 intel_ddi_init(dev_priv, PORT_E);
13724
13725 } else if (HAS_PCH_SPLIT(dev_priv)) {
13726 int found;
13727 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13728
13729 if (has_edp_a(dev_priv))
13730 intel_dp_init(dev_priv, DP_A, PORT_A);
13731
13732 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13733 /* PCH SDVOB multiplex with HDMIB */
13734 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13735 if (!found)
13736 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13737 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13738 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13739 }
13740
13741 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13742 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13743
13744 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13745 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13746
13747 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13748 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13749
13750 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13751 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13752 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13753 bool has_edp, has_port;
13754
13755 /*
13756 * The DP_DETECTED bit is the latched state of the DDC
13757 * SDA pin at boot. However since eDP doesn't require DDC
13758 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13759 * eDP ports may have been muxed to an alternate function.
13760 * Thus we can't rely on the DP_DETECTED bit alone to detect
13761 * eDP ports. Consult the VBT as well as DP_DETECTED to
13762 * detect eDP ports.
13763 *
13764 * Sadly the straps seem to be missing sometimes even for HDMI
13765 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13766 * and VBT for the presence of the port. Additionally we can't
13767 * trust the port type the VBT declares as we've seen at least
13768 * HDMI ports that the VBT claim are DP or eDP.
13769 */
13770 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13771 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13772 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13773 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13774 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13775 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13776
13777 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13778 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13779 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13780 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13781 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13782 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13783
13784 if (IS_CHERRYVIEW(dev_priv)) {
13785 /*
13786 * eDP not supported on port D,
13787 * so no need to worry about it
13788 */
13789 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13790 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13791 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13792 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13793 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13794 }
13795
13796 intel_dsi_init(dev_priv);
13797 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13798 bool found = false;
13799
13800 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13801 DRM_DEBUG_KMS("probing SDVOB\n");
13802 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13803 if (!found && IS_G4X(dev_priv)) {
13804 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13805 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13806 }
13807
13808 if (!found && IS_G4X(dev_priv))
13809 intel_dp_init(dev_priv, DP_B, PORT_B);
13810 }
13811
13812 /* Before G4X SDVOC doesn't have its own detect register */
13813
13814 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13815 DRM_DEBUG_KMS("probing SDVOC\n");
13816 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13817 }
13818
13819 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13820
13821 if (IS_G4X(dev_priv)) {
13822 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13823 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13824 }
13825 if (IS_G4X(dev_priv))
13826 intel_dp_init(dev_priv, DP_C, PORT_C);
13827 }
13828
13829 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13830 intel_dp_init(dev_priv, DP_D, PORT_D);
13831 } else if (IS_GEN2(dev_priv))
13832 intel_dvo_init(dev_priv);
13833
13834 if (SUPPORTS_TV(dev_priv))
13835 intel_tv_init(dev_priv);
13836
13837 intel_psr_init(dev_priv);
13838
13839 for_each_intel_encoder(&dev_priv->drm, encoder) {
13840 encoder->base.possible_crtcs = encoder->crtc_mask;
13841 encoder->base.possible_clones =
13842 intel_encoder_clones(encoder);
13843 }
13844
13845 intel_init_pch_refclk(dev_priv);
13846
13847 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13848 }
13849
13850 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13851 {
13852 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13853
13854 drm_framebuffer_cleanup(fb);
13855
13856 i915_gem_object_lock(intel_fb->obj);
13857 WARN_ON(!intel_fb->obj->framebuffer_references--);
13858 i915_gem_object_unlock(intel_fb->obj);
13859
13860 i915_gem_object_put(intel_fb->obj);
13861
13862 kfree(intel_fb);
13863 }
13864
13865 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13866 struct drm_file *file,
13867 unsigned int *handle)
13868 {
13869 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13870 struct drm_i915_gem_object *obj = intel_fb->obj;
13871
13872 if (obj->userptr.mm) {
13873 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13874 return -EINVAL;
13875 }
13876
13877 return drm_gem_handle_create(file, &obj->base, handle);
13878 }
13879
13880 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13881 struct drm_file *file,
13882 unsigned flags, unsigned color,
13883 struct drm_clip_rect *clips,
13884 unsigned num_clips)
13885 {
13886 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13887
13888 i915_gem_object_flush_if_display(obj);
13889 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13890
13891 return 0;
13892 }
13893
13894 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13895 .destroy = intel_user_framebuffer_destroy,
13896 .create_handle = intel_user_framebuffer_create_handle,
13897 .dirty = intel_user_framebuffer_dirty,
13898 };
13899
13900 static
13901 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13902 uint64_t fb_modifier, uint32_t pixel_format)
13903 {
13904 u32 gen = INTEL_GEN(dev_priv);
13905
13906 if (gen >= 9) {
13907 int cpp = drm_format_plane_cpp(pixel_format, 0);
13908
13909 /* "The stride in bytes must not exceed the of the size of 8K
13910 * pixels and 32K bytes."
13911 */
13912 return min(8192 * cpp, 32768);
13913 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13914 return 32*1024;
13915 } else if (gen >= 4) {
13916 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13917 return 16*1024;
13918 else
13919 return 32*1024;
13920 } else if (gen >= 3) {
13921 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13922 return 8*1024;
13923 else
13924 return 16*1024;
13925 } else {
13926 /* XXX DSPC is limited to 4k tiled */
13927 return 8*1024;
13928 }
13929 }
13930
13931 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13932 struct drm_i915_gem_object *obj,
13933 struct drm_mode_fb_cmd2 *mode_cmd)
13934 {
13935 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13936 struct drm_framebuffer *fb = &intel_fb->base;
13937 struct drm_format_name_buf format_name;
13938 u32 pitch_limit;
13939 unsigned int tiling, stride;
13940 int ret = -EINVAL;
13941 int i;
13942
13943 i915_gem_object_lock(obj);
13944 obj->framebuffer_references++;
13945 tiling = i915_gem_object_get_tiling(obj);
13946 stride = i915_gem_object_get_stride(obj);
13947 i915_gem_object_unlock(obj);
13948
13949 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13950 /*
13951 * If there's a fence, enforce that
13952 * the fb modifier and tiling mode match.
13953 */
13954 if (tiling != I915_TILING_NONE &&
13955 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13956 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13957 goto err;
13958 }
13959 } else {
13960 if (tiling == I915_TILING_X) {
13961 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13962 } else if (tiling == I915_TILING_Y) {
13963 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13964 goto err;
13965 }
13966 }
13967
13968 /* Passed in modifier sanity checking. */
13969 switch (mode_cmd->modifier[0]) {
13970 case I915_FORMAT_MOD_Y_TILED_CCS:
13971 case I915_FORMAT_MOD_Yf_TILED_CCS:
13972 switch (mode_cmd->pixel_format) {
13973 case DRM_FORMAT_XBGR8888:
13974 case DRM_FORMAT_ABGR8888:
13975 case DRM_FORMAT_XRGB8888:
13976 case DRM_FORMAT_ARGB8888:
13977 break;
13978 default:
13979 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13980 goto err;
13981 }
13982 /* fall through */
13983 case I915_FORMAT_MOD_Y_TILED:
13984 case I915_FORMAT_MOD_Yf_TILED:
13985 if (INTEL_GEN(dev_priv) < 9) {
13986 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13987 mode_cmd->modifier[0]);
13988 goto err;
13989 }
13990 case DRM_FORMAT_MOD_LINEAR:
13991 case I915_FORMAT_MOD_X_TILED:
13992 break;
13993 default:
13994 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13995 mode_cmd->modifier[0]);
13996 goto err;
13997 }
13998
13999 /*
14000 * gen2/3 display engine uses the fence if present,
14001 * so the tiling mode must match the fb modifier exactly.
14002 */
14003 if (INTEL_INFO(dev_priv)->gen < 4 &&
14004 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14005 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14006 goto err;
14007 }
14008
14009 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14010 mode_cmd->pixel_format);
14011 if (mode_cmd->pitches[0] > pitch_limit) {
14012 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14013 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14014 "tiled" : "linear",
14015 mode_cmd->pitches[0], pitch_limit);
14016 goto err;
14017 }
14018
14019 /*
14020 * If there's a fence, enforce that
14021 * the fb pitch and fence stride match.
14022 */
14023 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14024 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14025 mode_cmd->pitches[0], stride);
14026 goto err;
14027 }
14028
14029 /* Reject formats not supported by any plane early. */
14030 switch (mode_cmd->pixel_format) {
14031 case DRM_FORMAT_C8:
14032 case DRM_FORMAT_RGB565:
14033 case DRM_FORMAT_XRGB8888:
14034 case DRM_FORMAT_ARGB8888:
14035 break;
14036 case DRM_FORMAT_XRGB1555:
14037 if (INTEL_GEN(dev_priv) > 3) {
14038 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14039 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14040 goto err;
14041 }
14042 break;
14043 case DRM_FORMAT_ABGR8888:
14044 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14045 INTEL_GEN(dev_priv) < 9) {
14046 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14047 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14048 goto err;
14049 }
14050 break;
14051 case DRM_FORMAT_XBGR8888:
14052 case DRM_FORMAT_XRGB2101010:
14053 case DRM_FORMAT_XBGR2101010:
14054 if (INTEL_GEN(dev_priv) < 4) {
14055 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14056 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14057 goto err;
14058 }
14059 break;
14060 case DRM_FORMAT_ABGR2101010:
14061 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14062 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14063 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14064 goto err;
14065 }
14066 break;
14067 case DRM_FORMAT_YUYV:
14068 case DRM_FORMAT_UYVY:
14069 case DRM_FORMAT_YVYU:
14070 case DRM_FORMAT_VYUY:
14071 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14072 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14073 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14074 goto err;
14075 }
14076 break;
14077 default:
14078 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14079 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14080 goto err;
14081 }
14082
14083 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14084 if (mode_cmd->offsets[0] != 0)
14085 goto err;
14086
14087 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14088
14089 for (i = 0; i < fb->format->num_planes; i++) {
14090 u32 stride_alignment;
14091
14092 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14093 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14094 goto err;
14095 }
14096
14097 stride_alignment = intel_fb_stride_alignment(fb, i);
14098
14099 /*
14100 * Display WA #0531: skl,bxt,kbl,glk
14101 *
14102 * Render decompression and plane width > 3840
14103 * combined with horizontal panning requires the
14104 * plane stride to be a multiple of 4. We'll just
14105 * require the entire fb to accommodate that to avoid
14106 * potential runtime errors at plane configuration time.
14107 */
14108 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14109 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14110 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14111 stride_alignment *= 4;
14112
14113 if (fb->pitches[i] & (stride_alignment - 1)) {
14114 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14115 i, fb->pitches[i], stride_alignment);
14116 goto err;
14117 }
14118 }
14119
14120 intel_fb->obj = obj;
14121
14122 ret = intel_fill_fb_info(dev_priv, fb);
14123 if (ret)
14124 goto err;
14125
14126 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14127 if (ret) {
14128 DRM_ERROR("framebuffer init failed %d\n", ret);
14129 goto err;
14130 }
14131
14132 return 0;
14133
14134 err:
14135 i915_gem_object_lock(obj);
14136 obj->framebuffer_references--;
14137 i915_gem_object_unlock(obj);
14138 return ret;
14139 }
14140
14141 static struct drm_framebuffer *
14142 intel_user_framebuffer_create(struct drm_device *dev,
14143 struct drm_file *filp,
14144 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14145 {
14146 struct drm_framebuffer *fb;
14147 struct drm_i915_gem_object *obj;
14148 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14149
14150 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14151 if (!obj)
14152 return ERR_PTR(-ENOENT);
14153
14154 fb = intel_framebuffer_create(obj, &mode_cmd);
14155 if (IS_ERR(fb))
14156 i915_gem_object_put(obj);
14157
14158 return fb;
14159 }
14160
14161 static void intel_atomic_state_free(struct drm_atomic_state *state)
14162 {
14163 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14164
14165 drm_atomic_state_default_release(state);
14166
14167 i915_sw_fence_fini(&intel_state->commit_ready);
14168
14169 kfree(state);
14170 }
14171
14172 static const struct drm_mode_config_funcs intel_mode_funcs = {
14173 .fb_create = intel_user_framebuffer_create,
14174 .get_format_info = intel_get_format_info,
14175 .output_poll_changed = intel_fbdev_output_poll_changed,
14176 .atomic_check = intel_atomic_check,
14177 .atomic_commit = intel_atomic_commit,
14178 .atomic_state_alloc = intel_atomic_state_alloc,
14179 .atomic_state_clear = intel_atomic_state_clear,
14180 .atomic_state_free = intel_atomic_state_free,
14181 };
14182
14183 /**
14184 * intel_init_display_hooks - initialize the display modesetting hooks
14185 * @dev_priv: device private
14186 */
14187 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14188 {
14189 intel_init_cdclk_hooks(dev_priv);
14190
14191 if (INTEL_INFO(dev_priv)->gen >= 9) {
14192 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14193 dev_priv->display.get_initial_plane_config =
14194 skylake_get_initial_plane_config;
14195 dev_priv->display.crtc_compute_clock =
14196 haswell_crtc_compute_clock;
14197 dev_priv->display.crtc_enable = haswell_crtc_enable;
14198 dev_priv->display.crtc_disable = haswell_crtc_disable;
14199 } else if (HAS_DDI(dev_priv)) {
14200 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14201 dev_priv->display.get_initial_plane_config =
14202 ironlake_get_initial_plane_config;
14203 dev_priv->display.crtc_compute_clock =
14204 haswell_crtc_compute_clock;
14205 dev_priv->display.crtc_enable = haswell_crtc_enable;
14206 dev_priv->display.crtc_disable = haswell_crtc_disable;
14207 } else if (HAS_PCH_SPLIT(dev_priv)) {
14208 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14209 dev_priv->display.get_initial_plane_config =
14210 ironlake_get_initial_plane_config;
14211 dev_priv->display.crtc_compute_clock =
14212 ironlake_crtc_compute_clock;
14213 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14214 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14215 } else if (IS_CHERRYVIEW(dev_priv)) {
14216 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14217 dev_priv->display.get_initial_plane_config =
14218 i9xx_get_initial_plane_config;
14219 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14220 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14221 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14222 } else if (IS_VALLEYVIEW(dev_priv)) {
14223 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14224 dev_priv->display.get_initial_plane_config =
14225 i9xx_get_initial_plane_config;
14226 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14227 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14228 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14229 } else if (IS_G4X(dev_priv)) {
14230 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14231 dev_priv->display.get_initial_plane_config =
14232 i9xx_get_initial_plane_config;
14233 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14234 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14235 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14236 } else if (IS_PINEVIEW(dev_priv)) {
14237 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14238 dev_priv->display.get_initial_plane_config =
14239 i9xx_get_initial_plane_config;
14240 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14241 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14242 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14243 } else if (!IS_GEN2(dev_priv)) {
14244 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14245 dev_priv->display.get_initial_plane_config =
14246 i9xx_get_initial_plane_config;
14247 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14248 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14249 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14250 } else {
14251 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14252 dev_priv->display.get_initial_plane_config =
14253 i9xx_get_initial_plane_config;
14254 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14255 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14256 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14257 }
14258
14259 if (IS_GEN5(dev_priv)) {
14260 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14261 } else if (IS_GEN6(dev_priv)) {
14262 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14263 } else if (IS_IVYBRIDGE(dev_priv)) {
14264 /* FIXME: detect B0+ stepping and use auto training */
14265 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14266 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14267 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14268 }
14269
14270 if (INTEL_GEN(dev_priv) >= 9)
14271 dev_priv->display.update_crtcs = skl_update_crtcs;
14272 else
14273 dev_priv->display.update_crtcs = intel_update_crtcs;
14274 }
14275
14276 /*
14277 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14278 */
14279 static void quirk_ssc_force_disable(struct drm_device *dev)
14280 {
14281 struct drm_i915_private *dev_priv = to_i915(dev);
14282 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14283 DRM_INFO("applying lvds SSC disable quirk\n");
14284 }
14285
14286 /*
14287 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14288 * brightness value
14289 */
14290 static void quirk_invert_brightness(struct drm_device *dev)
14291 {
14292 struct drm_i915_private *dev_priv = to_i915(dev);
14293 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14294 DRM_INFO("applying inverted panel brightness quirk\n");
14295 }
14296
14297 /* Some VBT's incorrectly indicate no backlight is present */
14298 static void quirk_backlight_present(struct drm_device *dev)
14299 {
14300 struct drm_i915_private *dev_priv = to_i915(dev);
14301 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14302 DRM_INFO("applying backlight present quirk\n");
14303 }
14304
14305 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14306 * which is 300 ms greater than eDP spec T12 min.
14307 */
14308 static void quirk_increase_t12_delay(struct drm_device *dev)
14309 {
14310 struct drm_i915_private *dev_priv = to_i915(dev);
14311
14312 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14313 DRM_INFO("Applying T12 delay quirk\n");
14314 }
14315
14316 /*
14317 * GeminiLake NUC HDMI outputs require additional off time
14318 * this allows the onboard retimer to correctly sync to signal
14319 */
14320 static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
14321 {
14322 struct drm_i915_private *dev_priv = to_i915(dev);
14323
14324 dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
14325 DRM_INFO("Applying Increase DDI Disabled quirk\n");
14326 }
14327
14328 struct intel_quirk {
14329 int device;
14330 int subsystem_vendor;
14331 int subsystem_device;
14332 void (*hook)(struct drm_device *dev);
14333 };
14334
14335 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14336 struct intel_dmi_quirk {
14337 void (*hook)(struct drm_device *dev);
14338 const struct dmi_system_id (*dmi_id_list)[];
14339 };
14340
14341 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14342 {
14343 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14344 return 1;
14345 }
14346
14347 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14348 {
14349 .dmi_id_list = &(const struct dmi_system_id[]) {
14350 {
14351 .callback = intel_dmi_reverse_brightness,
14352 .ident = "NCR Corporation",
14353 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14354 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14355 },
14356 },
14357 { } /* terminating entry */
14358 },
14359 .hook = quirk_invert_brightness,
14360 },
14361 };
14362
14363 static struct intel_quirk intel_quirks[] = {
14364 /* Lenovo U160 cannot use SSC on LVDS */
14365 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14366
14367 /* Sony Vaio Y cannot use SSC on LVDS */
14368 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14369
14370 /* Acer Aspire 5734Z must invert backlight brightness */
14371 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14372
14373 /* Acer/eMachines G725 */
14374 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14375
14376 /* Acer/eMachines e725 */
14377 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14378
14379 /* Acer/Packard Bell NCL20 */
14380 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14381
14382 /* Acer Aspire 4736Z */
14383 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14384
14385 /* Acer Aspire 5336 */
14386 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14387
14388 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14389 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14390
14391 /* Acer C720 Chromebook (Core i3 4005U) */
14392 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14393
14394 /* Apple Macbook 2,1 (Core 2 T7400) */
14395 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14396
14397 /* Apple Macbook 4,1 */
14398 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14399
14400 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14401 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14402
14403 /* HP Chromebook 14 (Celeron 2955U) */
14404 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14405
14406 /* Dell Chromebook 11 */
14407 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14408
14409 /* Dell Chromebook 11 (2015 version) */
14410 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14411
14412 /* Toshiba Satellite P50-C-18C */
14413 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14414
14415 /* GeminiLake NUC */
14416 { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
14417 { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
14418 /* ASRock ITX*/
14419 { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
14420 { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
14421 };
14422
14423 static void intel_init_quirks(struct drm_device *dev)
14424 {
14425 struct pci_dev *d = dev->pdev;
14426 int i;
14427
14428 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14429 struct intel_quirk *q = &intel_quirks[i];
14430
14431 if (d->device == q->device &&
14432 (d->subsystem_vendor == q->subsystem_vendor ||
14433 q->subsystem_vendor == PCI_ANY_ID) &&
14434 (d->subsystem_device == q->subsystem_device ||
14435 q->subsystem_device == PCI_ANY_ID))
14436 q->hook(dev);
14437 }
14438 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14439 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14440 intel_dmi_quirks[i].hook(dev);
14441 }
14442 }
14443
14444 /* Disable the VGA plane that we never use */
14445 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14446 {
14447 struct pci_dev *pdev = dev_priv->drm.pdev;
14448 u8 sr1;
14449 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14450
14451 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14452 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14453 outb(SR01, VGA_SR_INDEX);
14454 sr1 = inb(VGA_SR_DATA);
14455 outb(sr1 | 1<<5, VGA_SR_DATA);
14456 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14457 udelay(300);
14458
14459 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14460 POSTING_READ(vga_reg);
14461 }
14462
14463 void intel_modeset_init_hw(struct drm_device *dev)
14464 {
14465 struct drm_i915_private *dev_priv = to_i915(dev);
14466
14467 intel_update_cdclk(dev_priv);
14468 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14469 }
14470
14471 /*
14472 * Calculate what we think the watermarks should be for the state we've read
14473 * out of the hardware and then immediately program those watermarks so that
14474 * we ensure the hardware settings match our internal state.
14475 *
14476 * We can calculate what we think WM's should be by creating a duplicate of the
14477 * current state (which was constructed during hardware readout) and running it
14478 * through the atomic check code to calculate new watermark values in the
14479 * state object.
14480 */
14481 static void sanitize_watermarks(struct drm_device *dev)
14482 {
14483 struct drm_i915_private *dev_priv = to_i915(dev);
14484 struct drm_atomic_state *state;
14485 struct intel_atomic_state *intel_state;
14486 struct drm_crtc *crtc;
14487 struct drm_crtc_state *cstate;
14488 struct drm_modeset_acquire_ctx ctx;
14489 int ret;
14490 int i;
14491
14492 /* Only supported on platforms that use atomic watermark design */
14493 if (!dev_priv->display.optimize_watermarks)
14494 return;
14495
14496 /*
14497 * We need to hold connection_mutex before calling duplicate_state so
14498 * that the connector loop is protected.
14499 */
14500 drm_modeset_acquire_init(&ctx, 0);
14501 retry:
14502 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14503 if (ret == -EDEADLK) {
14504 drm_modeset_backoff(&ctx);
14505 goto retry;
14506 } else if (WARN_ON(ret)) {
14507 goto fail;
14508 }
14509
14510 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14511 if (WARN_ON(IS_ERR(state)))
14512 goto fail;
14513
14514 intel_state = to_intel_atomic_state(state);
14515
14516 /*
14517 * Hardware readout is the only time we don't want to calculate
14518 * intermediate watermarks (since we don't trust the current
14519 * watermarks).
14520 */
14521 if (!HAS_GMCH_DISPLAY(dev_priv))
14522 intel_state->skip_intermediate_wm = true;
14523
14524 ret = intel_atomic_check(dev, state);
14525 if (ret) {
14526 /*
14527 * If we fail here, it means that the hardware appears to be
14528 * programmed in a way that shouldn't be possible, given our
14529 * understanding of watermark requirements. This might mean a
14530 * mistake in the hardware readout code or a mistake in the
14531 * watermark calculations for a given platform. Raise a WARN
14532 * so that this is noticeable.
14533 *
14534 * If this actually happens, we'll have to just leave the
14535 * BIOS-programmed watermarks untouched and hope for the best.
14536 */
14537 WARN(true, "Could not determine valid watermarks for inherited state\n");
14538 goto put_state;
14539 }
14540
14541 /* Write calculated watermark values back */
14542 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14543 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14544
14545 cs->wm.need_postvbl_update = true;
14546 dev_priv->display.optimize_watermarks(intel_state, cs);
14547
14548 to_intel_crtc_state(crtc->state)->wm = cs->wm;
14549 }
14550
14551 put_state:
14552 drm_atomic_state_put(state);
14553 fail:
14554 drm_modeset_drop_locks(&ctx);
14555 drm_modeset_acquire_fini(&ctx);
14556 }
14557
14558 int intel_modeset_init(struct drm_device *dev)
14559 {
14560 struct drm_i915_private *dev_priv = to_i915(dev);
14561 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14562 enum pipe pipe;
14563 struct intel_crtc *crtc;
14564
14565 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
14566
14567 drm_mode_config_init(dev);
14568
14569 dev->mode_config.min_width = 0;
14570 dev->mode_config.min_height = 0;
14571
14572 dev->mode_config.preferred_depth = 24;
14573 dev->mode_config.prefer_shadow = 1;
14574
14575 dev->mode_config.allow_fb_modifiers = true;
14576
14577 dev->mode_config.funcs = &intel_mode_funcs;
14578
14579 init_llist_head(&dev_priv->atomic_helper.free_list);
14580 INIT_WORK(&dev_priv->atomic_helper.free_work,
14581 intel_atomic_helper_free_state_worker);
14582
14583 intel_init_quirks(dev);
14584
14585 intel_init_pm(dev_priv);
14586
14587 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14588 return 0;
14589
14590 /*
14591 * There may be no VBT; and if the BIOS enabled SSC we can
14592 * just keep using it to avoid unnecessary flicker. Whereas if the
14593 * BIOS isn't using it, don't assume it will work even if the VBT
14594 * indicates as much.
14595 */
14596 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14597 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14598 DREF_SSC1_ENABLE);
14599
14600 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14601 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14602 bios_lvds_use_ssc ? "en" : "dis",
14603 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14604 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14605 }
14606 }
14607
14608 if (IS_GEN2(dev_priv)) {
14609 dev->mode_config.max_width = 2048;
14610 dev->mode_config.max_height = 2048;
14611 } else if (IS_GEN3(dev_priv)) {
14612 dev->mode_config.max_width = 4096;
14613 dev->mode_config.max_height = 4096;
14614 } else {
14615 dev->mode_config.max_width = 8192;
14616 dev->mode_config.max_height = 8192;
14617 }
14618
14619 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14620 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14621 dev->mode_config.cursor_height = 1023;
14622 } else if (IS_GEN2(dev_priv)) {
14623 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14624 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14625 } else {
14626 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14627 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14628 }
14629
14630 dev->mode_config.fb_base = ggtt->gmadr.start;
14631
14632 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14633 INTEL_INFO(dev_priv)->num_pipes,
14634 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14635
14636 for_each_pipe(dev_priv, pipe) {
14637 int ret;
14638
14639 ret = intel_crtc_init(dev_priv, pipe);
14640 if (ret) {
14641 drm_mode_config_cleanup(dev);
14642 return ret;
14643 }
14644 }
14645
14646 intel_shared_dpll_init(dev);
14647
14648 intel_update_czclk(dev_priv);
14649 intel_modeset_init_hw(dev);
14650
14651 if (dev_priv->max_cdclk_freq == 0)
14652 intel_update_max_cdclk(dev_priv);
14653
14654 /* Just disable it once at startup */
14655 i915_disable_vga(dev_priv);
14656 intel_setup_outputs(dev_priv);
14657
14658 drm_modeset_lock_all(dev);
14659 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14660 drm_modeset_unlock_all(dev);
14661
14662 for_each_intel_crtc(dev, crtc) {
14663 struct intel_initial_plane_config plane_config = {};
14664
14665 if (!crtc->active)
14666 continue;
14667
14668 /*
14669 * Note that reserving the BIOS fb up front prevents us
14670 * from stuffing other stolen allocations like the ring
14671 * on top. This prevents some ugliness at boot time, and
14672 * can even allow for smooth boot transitions if the BIOS
14673 * fb is large enough for the active pipe configuration.
14674 */
14675 dev_priv->display.get_initial_plane_config(crtc,
14676 &plane_config);
14677
14678 /*
14679 * If the fb is shared between multiple heads, we'll
14680 * just get the first one.
14681 */
14682 intel_find_initial_plane_obj(crtc, &plane_config);
14683 }
14684
14685 /*
14686 * Make sure hardware watermarks really match the state we read out.
14687 * Note that we need to do this after reconstructing the BIOS fb's
14688 * since the watermark calculation done here will use pstate->fb.
14689 */
14690 if (!HAS_GMCH_DISPLAY(dev_priv))
14691 sanitize_watermarks(dev);
14692
14693 return 0;
14694 }
14695
14696 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14697 {
14698 /* 640x480@60Hz, ~25175 kHz */
14699 struct dpll clock = {
14700 .m1 = 18,
14701 .m2 = 7,
14702 .p1 = 13,
14703 .p2 = 4,
14704 .n = 2,
14705 };
14706 u32 dpll, fp;
14707 int i;
14708
14709 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14710
14711 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14712 pipe_name(pipe), clock.vco, clock.dot);
14713
14714 fp = i9xx_dpll_compute_fp(&clock);
14715 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14716 DPLL_VGA_MODE_DIS |
14717 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14718 PLL_P2_DIVIDE_BY_4 |
14719 PLL_REF_INPUT_DREFCLK |
14720 DPLL_VCO_ENABLE;
14721
14722 I915_WRITE(FP0(pipe), fp);
14723 I915_WRITE(FP1(pipe), fp);
14724
14725 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14726 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14727 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14728 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14729 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14730 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14731 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14732
14733 /*
14734 * Apparently we need to have VGA mode enabled prior to changing
14735 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14736 * dividers, even though the register value does change.
14737 */
14738 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14739 I915_WRITE(DPLL(pipe), dpll);
14740
14741 /* Wait for the clocks to stabilize. */
14742 POSTING_READ(DPLL(pipe));
14743 udelay(150);
14744
14745 /* The pixel multiplier can only be updated once the
14746 * DPLL is enabled and the clocks are stable.
14747 *
14748 * So write it again.
14749 */
14750 I915_WRITE(DPLL(pipe), dpll);
14751
14752 /* We do this three times for luck */
14753 for (i = 0; i < 3 ; i++) {
14754 I915_WRITE(DPLL(pipe), dpll);
14755 POSTING_READ(DPLL(pipe));
14756 udelay(150); /* wait for warmup */
14757 }
14758
14759 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14760 POSTING_READ(PIPECONF(pipe));
14761 }
14762
14763 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14764 {
14765 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14766
14767 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14768 pipe_name(pipe));
14769
14770 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
14771 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
14772 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
14773 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
14774 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
14775
14776 I915_WRITE(PIPECONF(pipe), 0);
14777 POSTING_READ(PIPECONF(pipe));
14778
14779 intel_wait_for_pipe_scanline_stopped(crtc);
14780
14781 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14782 POSTING_READ(DPLL(pipe));
14783 }
14784
14785 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
14786 struct intel_plane *primary)
14787 {
14788 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14789 enum plane plane = primary->plane;
14790 u32 val = I915_READ(DSPCNTR(plane));
14791
14792 return (val & DISPLAY_PLANE_ENABLE) == 0 ||
14793 (val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
14794 }
14795
14796 static void
14797 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
14798 {
14799 struct intel_crtc *crtc;
14800
14801 if (INTEL_GEN(dev_priv) >= 4)
14802 return;
14803
14804 for_each_intel_crtc(&dev_priv->drm, crtc) {
14805 struct intel_plane *plane =
14806 to_intel_plane(crtc->base.primary);
14807
14808 if (intel_plane_mapping_ok(crtc, plane))
14809 continue;
14810
14811 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
14812 plane->base.name);
14813 intel_plane_disable_noatomic(crtc, plane);
14814 }
14815 }
14816
14817 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14818 {
14819 struct drm_device *dev = crtc->base.dev;
14820 struct intel_encoder *encoder;
14821
14822 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14823 return true;
14824
14825 return false;
14826 }
14827
14828 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14829 {
14830 struct drm_device *dev = encoder->base.dev;
14831 struct intel_connector *connector;
14832
14833 for_each_connector_on_encoder(dev, &encoder->base, connector)
14834 return connector;
14835
14836 return NULL;
14837 }
14838
14839 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14840 enum pipe pch_transcoder)
14841 {
14842 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14843 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14844 }
14845
14846 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14847 struct drm_modeset_acquire_ctx *ctx)
14848 {
14849 struct drm_device *dev = crtc->base.dev;
14850 struct drm_i915_private *dev_priv = to_i915(dev);
14851 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14852
14853 /* Clear any frame start delays used for debugging left by the BIOS */
14854 if (!transcoder_is_dsi(cpu_transcoder)) {
14855 i915_reg_t reg = PIPECONF(cpu_transcoder);
14856
14857 I915_WRITE(reg,
14858 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14859 }
14860
14861 if (crtc->active) {
14862 struct intel_plane *plane;
14863
14864 /* Disable everything but the primary plane */
14865 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14866 const struct intel_plane_state *plane_state =
14867 to_intel_plane_state(plane->base.state);
14868
14869 if (plane_state->base.visible &&
14870 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
14871 intel_plane_disable_noatomic(crtc, plane);
14872 }
14873 }
14874
14875 /* Adjust the state of the output pipe according to whether we
14876 * have active connectors/encoders. */
14877 if (crtc->active && !intel_crtc_has_encoders(crtc))
14878 intel_crtc_disable_noatomic(&crtc->base, ctx);
14879
14880 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14881 /*
14882 * We start out with underrun reporting disabled to avoid races.
14883 * For correct bookkeeping mark this on active crtcs.
14884 *
14885 * Also on gmch platforms we dont have any hardware bits to
14886 * disable the underrun reporting. Which means we need to start
14887 * out with underrun reporting disabled also on inactive pipes,
14888 * since otherwise we'll complain about the garbage we read when
14889 * e.g. coming up after runtime pm.
14890 *
14891 * No protection against concurrent access is required - at
14892 * worst a fifo underrun happens which also sets this to false.
14893 */
14894 crtc->cpu_fifo_underrun_disabled = true;
14895 /*
14896 * We track the PCH trancoder underrun reporting state
14897 * within the crtc. With crtc for pipe A housing the underrun
14898 * reporting state for PCH transcoder A, crtc for pipe B housing
14899 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14900 * and marking underrun reporting as disabled for the non-existing
14901 * PCH transcoders B and C would prevent enabling the south
14902 * error interrupt (see cpt_can_enable_serr_int()).
14903 */
14904 if (has_pch_trancoder(dev_priv, crtc->pipe))
14905 crtc->pch_fifo_underrun_disabled = true;
14906 }
14907 }
14908
14909 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14910 {
14911 struct intel_connector *connector;
14912
14913 /* We need to check both for a crtc link (meaning that the
14914 * encoder is active and trying to read from a pipe) and the
14915 * pipe itself being active. */
14916 bool has_active_crtc = encoder->base.crtc &&
14917 to_intel_crtc(encoder->base.crtc)->active;
14918
14919 connector = intel_encoder_find_connector(encoder);
14920 if (connector && !has_active_crtc) {
14921 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14922 encoder->base.base.id,
14923 encoder->base.name);
14924
14925 /* Connector is active, but has no active pipe. This is
14926 * fallout from our resume register restoring. Disable
14927 * the encoder manually again. */
14928 if (encoder->base.crtc) {
14929 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14930
14931 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14932 encoder->base.base.id,
14933 encoder->base.name);
14934 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14935 if (encoder->post_disable)
14936 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14937 }
14938 encoder->base.crtc = NULL;
14939
14940 /* Inconsistent output/port/pipe state happens presumably due to
14941 * a bug in one of the get_hw_state functions. Or someplace else
14942 * in our code, like the register restore mess on resume. Clamp
14943 * things to off as a safer default. */
14944
14945 connector->base.dpms = DRM_MODE_DPMS_OFF;
14946 connector->base.encoder = NULL;
14947 }
14948 /* Enabled encoders without active connectors will be fixed in
14949 * the crtc fixup. */
14950 }
14951
14952 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14953 {
14954 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14955
14956 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14957 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14958 i915_disable_vga(dev_priv);
14959 }
14960 }
14961
14962 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14963 {
14964 /* This function can be called both from intel_modeset_setup_hw_state or
14965 * at a very early point in our resume sequence, where the power well
14966 * structures are not yet restored. Since this function is at a very
14967 * paranoid "someone might have enabled VGA while we were not looking"
14968 * level, just check if the power well is enabled instead of trying to
14969 * follow the "don't touch the power well if we don't need it" policy
14970 * the rest of the driver uses. */
14971 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14972 return;
14973
14974 i915_redisable_vga_power_on(dev_priv);
14975
14976 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14977 }
14978
14979 /* FIXME read out full plane state for all planes */
14980 static void readout_plane_state(struct intel_crtc *crtc)
14981 {
14982 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14983 struct intel_crtc_state *crtc_state =
14984 to_intel_crtc_state(crtc->base.state);
14985 struct intel_plane *plane;
14986
14987 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14988 struct intel_plane_state *plane_state =
14989 to_intel_plane_state(plane->base.state);
14990 bool visible = plane->get_hw_state(plane);
14991
14992 intel_set_plane_visible(crtc_state, plane_state, visible);
14993 }
14994 }
14995
14996 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14997 {
14998 struct drm_i915_private *dev_priv = to_i915(dev);
14999 enum pipe pipe;
15000 struct intel_crtc *crtc;
15001 struct intel_encoder *encoder;
15002 struct intel_connector *connector;
15003 struct drm_connector_list_iter conn_iter;
15004 int i;
15005
15006 dev_priv->active_crtcs = 0;
15007
15008 for_each_intel_crtc(dev, crtc) {
15009 struct intel_crtc_state *crtc_state =
15010 to_intel_crtc_state(crtc->base.state);
15011
15012 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15013 memset(crtc_state, 0, sizeof(*crtc_state));
15014 crtc_state->base.crtc = &crtc->base;
15015
15016 crtc_state->base.active = crtc_state->base.enable =
15017 dev_priv->display.get_pipe_config(crtc, crtc_state);
15018
15019 crtc->base.enabled = crtc_state->base.enable;
15020 crtc->active = crtc_state->base.active;
15021
15022 if (crtc_state->base.active)
15023 dev_priv->active_crtcs |= 1 << crtc->pipe;
15024
15025 readout_plane_state(crtc);
15026
15027 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15028 crtc->base.base.id, crtc->base.name,
15029 enableddisabled(crtc_state->base.active));
15030 }
15031
15032 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15033 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15034
15035 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15036 &pll->state.hw_state);
15037 pll->state.crtc_mask = 0;
15038 for_each_intel_crtc(dev, crtc) {
15039 struct intel_crtc_state *crtc_state =
15040 to_intel_crtc_state(crtc->base.state);
15041
15042 if (crtc_state->base.active &&
15043 crtc_state->shared_dpll == pll)
15044 pll->state.crtc_mask |= 1 << crtc->pipe;
15045 }
15046 pll->active_mask = pll->state.crtc_mask;
15047
15048 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15049 pll->name, pll->state.crtc_mask, pll->on);
15050 }
15051
15052 for_each_intel_encoder(dev, encoder) {
15053 pipe = 0;
15054
15055 if (encoder->get_hw_state(encoder, &pipe)) {
15056 struct intel_crtc_state *crtc_state;
15057
15058 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15059 crtc_state = to_intel_crtc_state(crtc->base.state);
15060
15061 encoder->base.crtc = &crtc->base;
15062 crtc_state->output_types |= 1 << encoder->type;
15063 encoder->get_config(encoder, crtc_state);
15064 } else {
15065 encoder->base.crtc = NULL;
15066 }
15067
15068 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15069 encoder->base.base.id, encoder->base.name,
15070 enableddisabled(encoder->base.crtc),
15071 pipe_name(pipe));
15072 }
15073
15074 drm_connector_list_iter_begin(dev, &conn_iter);
15075 for_each_intel_connector_iter(connector, &conn_iter) {
15076 if (connector->get_hw_state(connector)) {
15077 connector->base.dpms = DRM_MODE_DPMS_ON;
15078
15079 encoder = connector->encoder;
15080 connector->base.encoder = &encoder->base;
15081
15082 if (encoder->base.crtc &&
15083 encoder->base.crtc->state->active) {
15084 /*
15085 * This has to be done during hardware readout
15086 * because anything calling .crtc_disable may
15087 * rely on the connector_mask being accurate.
15088 */
15089 encoder->base.crtc->state->connector_mask |=
15090 1 << drm_connector_index(&connector->base);
15091 encoder->base.crtc->state->encoder_mask |=
15092 1 << drm_encoder_index(&encoder->base);
15093 }
15094
15095 } else {
15096 connector->base.dpms = DRM_MODE_DPMS_OFF;
15097 connector->base.encoder = NULL;
15098 }
15099 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15100 connector->base.base.id, connector->base.name,
15101 enableddisabled(connector->base.encoder));
15102 }
15103 drm_connector_list_iter_end(&conn_iter);
15104
15105 for_each_intel_crtc(dev, crtc) {
15106 struct intel_crtc_state *crtc_state =
15107 to_intel_crtc_state(crtc->base.state);
15108 int min_cdclk = 0;
15109
15110 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15111 if (crtc_state->base.active) {
15112 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15113 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15114 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15115
15116 /*
15117 * The initial mode needs to be set in order to keep
15118 * the atomic core happy. It wants a valid mode if the
15119 * crtc's enabled, so we do the above call.
15120 *
15121 * But we don't set all the derived state fully, hence
15122 * set a flag to indicate that a full recalculation is
15123 * needed on the next commit.
15124 */
15125 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15126
15127 intel_crtc_compute_pixel_rate(crtc_state);
15128
15129 if (dev_priv->display.modeset_calc_cdclk) {
15130 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15131 if (WARN_ON(min_cdclk < 0))
15132 min_cdclk = 0;
15133 }
15134
15135 drm_calc_timestamping_constants(&crtc->base,
15136 &crtc_state->base.adjusted_mode);
15137 update_scanline_offset(crtc);
15138 }
15139
15140 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15141
15142 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15143 }
15144 }
15145
15146 static void
15147 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15148 {
15149 struct intel_encoder *encoder;
15150
15151 for_each_intel_encoder(&dev_priv->drm, encoder) {
15152 u64 get_domains;
15153 enum intel_display_power_domain domain;
15154
15155 if (!encoder->get_power_domains)
15156 continue;
15157
15158 get_domains = encoder->get_power_domains(encoder);
15159 for_each_power_domain(domain, get_domains)
15160 intel_display_power_get(dev_priv, domain);
15161 }
15162 }
15163
15164 /* Scan out the current hw modeset state,
15165 * and sanitizes it to the current state
15166 */
15167 static void
15168 intel_modeset_setup_hw_state(struct drm_device *dev,
15169 struct drm_modeset_acquire_ctx *ctx)
15170 {
15171 struct drm_i915_private *dev_priv = to_i915(dev);
15172 struct intel_crtc *crtc;
15173 struct intel_encoder *encoder;
15174 int i;
15175
15176 if (IS_HASWELL(dev_priv)) {
15177 /*
15178 * WaRsPkgCStateDisplayPMReq:hsw
15179 * System hang if this isn't done before disabling all planes!
15180 */
15181 I915_WRITE(CHICKEN_PAR1_1,
15182 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15183 }
15184
15185 intel_modeset_readout_hw_state(dev);
15186
15187 /* HW state is read out, now we need to sanitize this mess. */
15188 get_encoder_power_domains(dev_priv);
15189
15190 /*
15191 * intel_sanitize_plane_mapping() may need to do vblank
15192 * waits, so we need vblank interrupts restored beforehand.
15193 */
15194 for_each_intel_crtc(&dev_priv->drm, crtc) {
15195 drm_crtc_vblank_reset(&crtc->base);
15196
15197 if (crtc->active)
15198 drm_crtc_vblank_on(&crtc->base);
15199 }
15200
15201 intel_sanitize_plane_mapping(dev_priv);
15202
15203 for_each_intel_encoder(dev, encoder)
15204 intel_sanitize_encoder(encoder);
15205
15206 for_each_intel_crtc(&dev_priv->drm, crtc) {
15207 intel_sanitize_crtc(crtc, ctx);
15208 intel_dump_pipe_config(crtc, crtc->config,
15209 "[setup_hw_state]");
15210 }
15211
15212 intel_modeset_update_connector_atomic_state(dev);
15213
15214 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15215 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15216
15217 if (!pll->on || pll->active_mask)
15218 continue;
15219
15220 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15221
15222 pll->funcs.disable(dev_priv, pll);
15223 pll->on = false;
15224 }
15225
15226 if (IS_G4X(dev_priv)) {
15227 g4x_wm_get_hw_state(dev);
15228 g4x_wm_sanitize(dev_priv);
15229 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15230 vlv_wm_get_hw_state(dev);
15231 vlv_wm_sanitize(dev_priv);
15232 } else if (INTEL_GEN(dev_priv) >= 9) {
15233 skl_wm_get_hw_state(dev);
15234 } else if (HAS_PCH_SPLIT(dev_priv)) {
15235 ilk_wm_get_hw_state(dev);
15236 }
15237
15238 for_each_intel_crtc(dev, crtc) {
15239 u64 put_domains;
15240
15241 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15242 if (WARN_ON(put_domains))
15243 modeset_put_power_domains(dev_priv, put_domains);
15244 }
15245 intel_display_set_init_power(dev_priv, false);
15246
15247 intel_power_domains_verify_state(dev_priv);
15248
15249 intel_fbc_init_pipe_state(dev_priv);
15250 }
15251
15252 void intel_display_resume(struct drm_device *dev)
15253 {
15254 struct drm_i915_private *dev_priv = to_i915(dev);
15255 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15256 struct drm_modeset_acquire_ctx ctx;
15257 int ret;
15258
15259 dev_priv->modeset_restore_state = NULL;
15260 if (state)
15261 state->acquire_ctx = &ctx;
15262
15263 drm_modeset_acquire_init(&ctx, 0);
15264
15265 while (1) {
15266 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15267 if (ret != -EDEADLK)
15268 break;
15269
15270 drm_modeset_backoff(&ctx);
15271 }
15272
15273 if (!ret)
15274 ret = __intel_display_resume(dev, state, &ctx);
15275
15276 intel_enable_ipc(dev_priv);
15277 drm_modeset_drop_locks(&ctx);
15278 drm_modeset_acquire_fini(&ctx);
15279
15280 if (ret)
15281 DRM_ERROR("Restoring old state failed with %i\n", ret);
15282 if (state)
15283 drm_atomic_state_put(state);
15284 }
15285
15286 int intel_connector_register(struct drm_connector *connector)
15287 {
15288 struct intel_connector *intel_connector = to_intel_connector(connector);
15289 int ret;
15290
15291 ret = intel_backlight_device_register(intel_connector);
15292 if (ret)
15293 goto err;
15294
15295 return 0;
15296
15297 err:
15298 return ret;
15299 }
15300
15301 void intel_connector_unregister(struct drm_connector *connector)
15302 {
15303 struct intel_connector *intel_connector = to_intel_connector(connector);
15304
15305 intel_backlight_device_unregister(intel_connector);
15306 intel_panel_destroy_backlight(connector);
15307 }
15308
15309 static void intel_hpd_poll_fini(struct drm_device *dev)
15310 {
15311 struct intel_connector *connector;
15312 struct drm_connector_list_iter conn_iter;
15313
15314 /* First disable polling... */
15315 drm_kms_helper_poll_fini(dev);
15316
15317 /* Then kill the work that may have been queued by hpd. */
15318 drm_connector_list_iter_begin(dev, &conn_iter);
15319 for_each_intel_connector_iter(connector, &conn_iter) {
15320 if (connector->modeset_retry_work.func)
15321 cancel_work_sync(&connector->modeset_retry_work);
15322 }
15323 drm_connector_list_iter_end(&conn_iter);
15324 }
15325
15326 void intel_modeset_cleanup(struct drm_device *dev)
15327 {
15328 struct drm_i915_private *dev_priv = to_i915(dev);
15329
15330 flush_work(&dev_priv->atomic_helper.free_work);
15331 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15332
15333 intel_disable_gt_powersave(dev_priv);
15334
15335 /*
15336 * Interrupts and polling as the first thing to avoid creating havoc.
15337 * Too much stuff here (turning of connectors, ...) would
15338 * experience fancy races otherwise.
15339 */
15340 intel_irq_uninstall(dev_priv);
15341
15342 /*
15343 * Due to the hpd irq storm handling the hotplug work can re-arm the
15344 * poll handlers. Hence disable polling after hpd handling is shut down.
15345 */
15346 intel_hpd_poll_fini(dev);
15347
15348 /* poll work can call into fbdev, hence clean that up afterwards */
15349 intel_fbdev_fini(dev_priv);
15350
15351 intel_unregister_dsm_handler();
15352
15353 intel_fbc_global_disable(dev_priv);
15354
15355 /* flush any delayed tasks or pending work */
15356 flush_scheduled_work();
15357
15358 drm_mode_config_cleanup(dev);
15359
15360 intel_cleanup_overlay(dev_priv);
15361
15362 intel_cleanup_gt_powersave(dev_priv);
15363
15364 intel_teardown_gmbus(dev_priv);
15365
15366 destroy_workqueue(dev_priv->modeset_wq);
15367 }
15368
15369 void intel_connector_attach_encoder(struct intel_connector *connector,
15370 struct intel_encoder *encoder)
15371 {
15372 connector->encoder = encoder;
15373 drm_mode_connector_attach_encoder(&connector->base,
15374 &encoder->base);
15375 }
15376
15377 /*
15378 * set vga decode state - true == enable VGA decode
15379 */
15380 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15381 {
15382 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15383 u16 gmch_ctrl;
15384
15385 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15386 DRM_ERROR("failed to read control word\n");
15387 return -EIO;
15388 }
15389
15390 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15391 return 0;
15392
15393 if (state)
15394 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15395 else
15396 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15397
15398 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15399 DRM_ERROR("failed to write control word\n");
15400 return -EIO;
15401 }
15402
15403 return 0;
15404 }
15405
15406 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15407
15408 struct intel_display_error_state {
15409
15410 u32 power_well_driver;
15411
15412 int num_transcoders;
15413
15414 struct intel_cursor_error_state {
15415 u32 control;
15416 u32 position;
15417 u32 base;
15418 u32 size;
15419 } cursor[I915_MAX_PIPES];
15420
15421 struct intel_pipe_error_state {
15422 bool power_domain_on;
15423 u32 source;
15424 u32 stat;
15425 } pipe[I915_MAX_PIPES];
15426
15427 struct intel_plane_error_state {
15428 u32 control;
15429 u32 stride;
15430 u32 size;
15431 u32 pos;
15432 u32 addr;
15433 u32 surface;
15434 u32 tile_offset;
15435 } plane[I915_MAX_PIPES];
15436
15437 struct intel_transcoder_error_state {
15438 bool power_domain_on;
15439 enum transcoder cpu_transcoder;
15440
15441 u32 conf;
15442
15443 u32 htotal;
15444 u32 hblank;
15445 u32 hsync;
15446 u32 vtotal;
15447 u32 vblank;
15448 u32 vsync;
15449 } transcoder[4];
15450 };
15451
15452 struct intel_display_error_state *
15453 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15454 {
15455 struct intel_display_error_state *error;
15456 int transcoders[] = {
15457 TRANSCODER_A,
15458 TRANSCODER_B,
15459 TRANSCODER_C,
15460 TRANSCODER_EDP,
15461 };
15462 int i;
15463
15464 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15465 return NULL;
15466
15467 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15468 if (error == NULL)
15469 return NULL;
15470
15471 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15472 error->power_well_driver =
15473 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15474
15475 for_each_pipe(dev_priv, i) {
15476 error->pipe[i].power_domain_on =
15477 __intel_display_power_is_enabled(dev_priv,
15478 POWER_DOMAIN_PIPE(i));
15479 if (!error->pipe[i].power_domain_on)
15480 continue;
15481
15482 error->cursor[i].control = I915_READ(CURCNTR(i));
15483 error->cursor[i].position = I915_READ(CURPOS(i));
15484 error->cursor[i].base = I915_READ(CURBASE(i));
15485
15486 error->plane[i].control = I915_READ(DSPCNTR(i));
15487 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15488 if (INTEL_GEN(dev_priv) <= 3) {
15489 error->plane[i].size = I915_READ(DSPSIZE(i));
15490 error->plane[i].pos = I915_READ(DSPPOS(i));
15491 }
15492 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15493 error->plane[i].addr = I915_READ(DSPADDR(i));
15494 if (INTEL_GEN(dev_priv) >= 4) {
15495 error->plane[i].surface = I915_READ(DSPSURF(i));
15496 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15497 }
15498
15499 error->pipe[i].source = I915_READ(PIPESRC(i));
15500
15501 if (HAS_GMCH_DISPLAY(dev_priv))
15502 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15503 }
15504
15505 /* Note: this does not include DSI transcoders. */
15506 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15507 if (HAS_DDI(dev_priv))
15508 error->num_transcoders++; /* Account for eDP. */
15509
15510 for (i = 0; i < error->num_transcoders; i++) {
15511 enum transcoder cpu_transcoder = transcoders[i];
15512
15513 error->transcoder[i].power_domain_on =
15514 __intel_display_power_is_enabled(dev_priv,
15515 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15516 if (!error->transcoder[i].power_domain_on)
15517 continue;
15518
15519 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15520
15521 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15522 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15523 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15524 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15525 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15526 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15527 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15528 }
15529
15530 return error;
15531 }
15532
15533 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15534
15535 void
15536 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15537 struct intel_display_error_state *error)
15538 {
15539 struct drm_i915_private *dev_priv = m->i915;
15540 int i;
15541
15542 if (!error)
15543 return;
15544
15545 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15546 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15547 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15548 error->power_well_driver);
15549 for_each_pipe(dev_priv, i) {
15550 err_printf(m, "Pipe [%d]:\n", i);
15551 err_printf(m, " Power: %s\n",
15552 onoff(error->pipe[i].power_domain_on));
15553 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15554 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15555
15556 err_printf(m, "Plane [%d]:\n", i);
15557 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15558 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15559 if (INTEL_GEN(dev_priv) <= 3) {
15560 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15561 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15562 }
15563 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15564 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15565 if (INTEL_GEN(dev_priv) >= 4) {
15566 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15567 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15568 }
15569
15570 err_printf(m, "Cursor [%d]:\n", i);
15571 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15572 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15573 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15574 }
15575
15576 for (i = 0; i < error->num_transcoders; i++) {
15577 err_printf(m, "CPU transcoder: %s\n",
15578 transcoder_name(error->transcoder[i].cpu_transcoder));
15579 err_printf(m, " Power: %s\n",
15580 onoff(error->transcoder[i].power_domain_on));
15581 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15582 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15583 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15584 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15585 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15586 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15587 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15588 }
15589 }
15590
15591 #endif
ubuntu-bionic-kernel mirror