]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915/gen9: Drop re-allocation of DDB at atomic commit (v2)
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120
121 struct intel_limit {
122 struct {
123 int min, max;
124 } dot, vco, n, m, m1, m2, p, p1;
125
126 struct {
127 int dot_limit;
128 int p2_slow, p2_fast;
129 } p2;
130 };
131
132 /* returns HPLL frequency in kHz */
133 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
134 {
135 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
136
137 /* Obtain SKU information */
138 mutex_lock(&dev_priv->sb_lock);
139 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
140 CCK_FUSE_HPLL_FREQ_MASK;
141 mutex_unlock(&dev_priv->sb_lock);
142
143 return vco_freq[hpll_freq] * 1000;
144 }
145
146 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
147 const char *name, u32 reg, int ref_freq)
148 {
149 u32 val;
150 int divider;
151
152 mutex_lock(&dev_priv->sb_lock);
153 val = vlv_cck_read(dev_priv, reg);
154 mutex_unlock(&dev_priv->sb_lock);
155
156 divider = val & CCK_FREQUENCY_VALUES;
157
158 WARN((val & CCK_FREQUENCY_STATUS) !=
159 (divider << CCK_FREQUENCY_STATUS_SHIFT),
160 "%s change in progress\n", name);
161
162 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
163 }
164
165 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
166 const char *name, u32 reg)
167 {
168 if (dev_priv->hpll_freq == 0)
169 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
170
171 return vlv_get_cck_clock(dev_priv, name, reg,
172 dev_priv->hpll_freq);
173 }
174
175 static int
176 intel_pch_rawclk(struct drm_i915_private *dev_priv)
177 {
178 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
179 }
180
181 static int
182 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
183 {
184 /* RAWCLK_FREQ_VLV register updated from power well code */
185 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
186 CCK_DISPLAY_REF_CLOCK_CONTROL);
187 }
188
189 static int
190 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 uint32_t clkcfg;
193
194 /* hrawclock is 1/4 the FSB frequency */
195 clkcfg = I915_READ(CLKCFG);
196 switch (clkcfg & CLKCFG_FSB_MASK) {
197 case CLKCFG_FSB_400:
198 return 100000;
199 case CLKCFG_FSB_533:
200 return 133333;
201 case CLKCFG_FSB_667:
202 return 166667;
203 case CLKCFG_FSB_800:
204 return 200000;
205 case CLKCFG_FSB_1067:
206 return 266667;
207 case CLKCFG_FSB_1333:
208 return 333333;
209 /* these two are just a guess; one of them might be right */
210 case CLKCFG_FSB_1600:
211 case CLKCFG_FSB_1600_ALT:
212 return 400000;
213 default:
214 return 133333;
215 }
216 }
217
218 void intel_update_rawclk(struct drm_i915_private *dev_priv)
219 {
220 if (HAS_PCH_SPLIT(dev_priv))
221 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
222 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
223 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
224 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
225 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
226 else
227 return; /* no rawclk on other platforms, or no need to know it */
228
229 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
230 }
231
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
233 {
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
235 return;
236
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
239
240 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
241 }
242
243 static inline u32 /* units of 100MHz */
244 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
245 const struct intel_crtc_state *pipe_config)
246 {
247 if (HAS_DDI(dev_priv))
248 return pipe_config->port_clock; /* SPLL */
249 else if (IS_GEN5(dev_priv))
250 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
251 else
252 return 270000;
253 }
254
255 static const struct intel_limit intel_limits_i8xx_dac = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 908000, .max = 1512000 },
258 .n = { .min = 2, .max = 16 },
259 .m = { .min = 96, .max = 140 },
260 .m1 = { .min = 18, .max = 26 },
261 .m2 = { .min = 6, .max = 16 },
262 .p = { .min = 4, .max = 128 },
263 .p1 = { .min = 2, .max = 33 },
264 .p2 = { .dot_limit = 165000,
265 .p2_slow = 4, .p2_fast = 2 },
266 };
267
268 static const struct intel_limit intel_limits_i8xx_dvo = {
269 .dot = { .min = 25000, .max = 350000 },
270 .vco = { .min = 908000, .max = 1512000 },
271 .n = { .min = 2, .max = 16 },
272 .m = { .min = 96, .max = 140 },
273 .m1 = { .min = 18, .max = 26 },
274 .m2 = { .min = 6, .max = 16 },
275 .p = { .min = 4, .max = 128 },
276 .p1 = { .min = 2, .max = 33 },
277 .p2 = { .dot_limit = 165000,
278 .p2_slow = 4, .p2_fast = 4 },
279 };
280
281 static const struct intel_limit intel_limits_i8xx_lvds = {
282 .dot = { .min = 25000, .max = 350000 },
283 .vco = { .min = 908000, .max = 1512000 },
284 .n = { .min = 2, .max = 16 },
285 .m = { .min = 96, .max = 140 },
286 .m1 = { .min = 18, .max = 26 },
287 .m2 = { .min = 6, .max = 16 },
288 .p = { .min = 4, .max = 128 },
289 .p1 = { .min = 1, .max = 6 },
290 .p2 = { .dot_limit = 165000,
291 .p2_slow = 14, .p2_fast = 7 },
292 };
293
294 static const struct intel_limit intel_limits_i9xx_sdvo = {
295 .dot = { .min = 20000, .max = 400000 },
296 .vco = { .min = 1400000, .max = 2800000 },
297 .n = { .min = 1, .max = 6 },
298 .m = { .min = 70, .max = 120 },
299 .m1 = { .min = 8, .max = 18 },
300 .m2 = { .min = 3, .max = 7 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 200000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const struct intel_limit intel_limits_i9xx_lvds = {
308 .dot = { .min = 20000, .max = 400000 },
309 .vco = { .min = 1400000, .max = 2800000 },
310 .n = { .min = 1, .max = 6 },
311 .m = { .min = 70, .max = 120 },
312 .m1 = { .min = 8, .max = 18 },
313 .m2 = { .min = 3, .max = 7 },
314 .p = { .min = 7, .max = 98 },
315 .p1 = { .min = 1, .max = 8 },
316 .p2 = { .dot_limit = 112000,
317 .p2_slow = 14, .p2_fast = 7 },
318 };
319
320
321 static const struct intel_limit intel_limits_g4x_sdvo = {
322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 1750000, .max = 3500000},
324 .n = { .min = 1, .max = 4 },
325 .m = { .min = 104, .max = 138 },
326 .m1 = { .min = 17, .max = 23 },
327 .m2 = { .min = 5, .max = 11 },
328 .p = { .min = 10, .max = 30 },
329 .p1 = { .min = 1, .max = 3},
330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 10,
332 .p2_fast = 10
333 },
334 };
335
336 static const struct intel_limit intel_limits_g4x_hdmi = {
337 .dot = { .min = 22000, .max = 400000 },
338 .vco = { .min = 1750000, .max = 3500000},
339 .n = { .min = 1, .max = 4 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 16, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 5, .max = 80 },
344 .p1 = { .min = 1, .max = 8},
345 .p2 = { .dot_limit = 165000,
346 .p2_slow = 10, .p2_fast = 5 },
347 };
348
349 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
350 .dot = { .min = 20000, .max = 115000 },
351 .vco = { .min = 1750000, .max = 3500000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 104, .max = 138 },
354 .m1 = { .min = 17, .max = 23 },
355 .m2 = { .min = 5, .max = 11 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 0,
359 .p2_slow = 14, .p2_fast = 14
360 },
361 };
362
363 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
364 .dot = { .min = 80000, .max = 224000 },
365 .vco = { .min = 1750000, .max = 3500000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 104, .max = 138 },
368 .m1 = { .min = 17, .max = 23 },
369 .m2 = { .min = 5, .max = 11 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 0,
373 .p2_slow = 7, .p2_fast = 7
374 },
375 };
376
377 static const struct intel_limit intel_limits_pineview_sdvo = {
378 .dot = { .min = 20000, .max = 400000},
379 .vco = { .min = 1700000, .max = 3500000 },
380 /* Pineview's Ncounter is a ring counter */
381 .n = { .min = 3, .max = 6 },
382 .m = { .min = 2, .max = 256 },
383 /* Pineview only has one combined m divider, which we treat as m2. */
384 .m1 = { .min = 0, .max = 0 },
385 .m2 = { .min = 0, .max = 254 },
386 .p = { .min = 5, .max = 80 },
387 .p1 = { .min = 1, .max = 8 },
388 .p2 = { .dot_limit = 200000,
389 .p2_slow = 10, .p2_fast = 5 },
390 };
391
392 static const struct intel_limit intel_limits_pineview_lvds = {
393 .dot = { .min = 20000, .max = 400000 },
394 .vco = { .min = 1700000, .max = 3500000 },
395 .n = { .min = 3, .max = 6 },
396 .m = { .min = 2, .max = 256 },
397 .m1 = { .min = 0, .max = 0 },
398 .m2 = { .min = 0, .max = 254 },
399 .p = { .min = 7, .max = 112 },
400 .p1 = { .min = 1, .max = 8 },
401 .p2 = { .dot_limit = 112000,
402 .p2_slow = 14, .p2_fast = 14 },
403 };
404
405 /* Ironlake / Sandybridge
406 *
407 * We calculate clock using (register_value + 2) for N/M1/M2, so here
408 * the range value for them is (actual_value - 2).
409 */
410 static const struct intel_limit intel_limits_ironlake_dac = {
411 .dot = { .min = 25000, .max = 350000 },
412 .vco = { .min = 1760000, .max = 3510000 },
413 .n = { .min = 1, .max = 5 },
414 .m = { .min = 79, .max = 127 },
415 .m1 = { .min = 12, .max = 22 },
416 .m2 = { .min = 5, .max = 9 },
417 .p = { .min = 5, .max = 80 },
418 .p1 = { .min = 1, .max = 8 },
419 .p2 = { .dot_limit = 225000,
420 .p2_slow = 10, .p2_fast = 5 },
421 };
422
423 static const struct intel_limit intel_limits_ironlake_single_lvds = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 3 },
427 .m = { .min = 79, .max = 118 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 28, .max = 112 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 14, .p2_fast = 14 },
434 };
435
436 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
437 .dot = { .min = 25000, .max = 350000 },
438 .vco = { .min = 1760000, .max = 3510000 },
439 .n = { .min = 1, .max = 3 },
440 .m = { .min = 79, .max = 127 },
441 .m1 = { .min = 12, .max = 22 },
442 .m2 = { .min = 5, .max = 9 },
443 .p = { .min = 14, .max = 56 },
444 .p1 = { .min = 2, .max = 8 },
445 .p2 = { .dot_limit = 225000,
446 .p2_slow = 7, .p2_fast = 7 },
447 };
448
449 /* LVDS 100mhz refclk limits. */
450 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
451 .dot = { .min = 25000, .max = 350000 },
452 .vco = { .min = 1760000, .max = 3510000 },
453 .n = { .min = 1, .max = 2 },
454 .m = { .min = 79, .max = 126 },
455 .m1 = { .min = 12, .max = 22 },
456 .m2 = { .min = 5, .max = 9 },
457 .p = { .min = 28, .max = 112 },
458 .p1 = { .min = 2, .max = 8 },
459 .p2 = { .dot_limit = 225000,
460 .p2_slow = 14, .p2_fast = 14 },
461 };
462
463 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
464 .dot = { .min = 25000, .max = 350000 },
465 .vco = { .min = 1760000, .max = 3510000 },
466 .n = { .min = 1, .max = 3 },
467 .m = { .min = 79, .max = 126 },
468 .m1 = { .min = 12, .max = 22 },
469 .m2 = { .min = 5, .max = 9 },
470 .p = { .min = 14, .max = 42 },
471 .p1 = { .min = 2, .max = 6 },
472 .p2 = { .dot_limit = 225000,
473 .p2_slow = 7, .p2_fast = 7 },
474 };
475
476 static const struct intel_limit intel_limits_vlv = {
477 /*
478 * These are the data rate limits (measured in fast clocks)
479 * since those are the strictest limits we have. The fast
480 * clock and actual rate limits are more relaxed, so checking
481 * them would make no difference.
482 */
483 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
484 .vco = { .min = 4000000, .max = 6000000 },
485 .n = { .min = 1, .max = 7 },
486 .m1 = { .min = 2, .max = 3 },
487 .m2 = { .min = 11, .max = 156 },
488 .p1 = { .min = 2, .max = 3 },
489 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
490 };
491
492 static const struct intel_limit intel_limits_chv = {
493 /*
494 * These are the data rate limits (measured in fast clocks)
495 * since those are the strictest limits we have. The fast
496 * clock and actual rate limits are more relaxed, so checking
497 * them would make no difference.
498 */
499 .dot = { .min = 25000 * 5, .max = 540000 * 5},
500 .vco = { .min = 4800000, .max = 6480000 },
501 .n = { .min = 1, .max = 1 },
502 .m1 = { .min = 2, .max = 2 },
503 .m2 = { .min = 24 << 22, .max = 175 << 22 },
504 .p1 = { .min = 2, .max = 4 },
505 .p2 = { .p2_slow = 1, .p2_fast = 14 },
506 };
507
508 static const struct intel_limit intel_limits_bxt = {
509 /* FIXME: find real dot limits */
510 .dot = { .min = 0, .max = INT_MAX },
511 .vco = { .min = 4800000, .max = 6700000 },
512 .n = { .min = 1, .max = 1 },
513 .m1 = { .min = 2, .max = 2 },
514 /* FIXME: find real m2 limits */
515 .m2 = { .min = 2 << 22, .max = 255 << 22 },
516 .p1 = { .min = 2, .max = 4 },
517 .p2 = { .p2_slow = 1, .p2_fast = 20 },
518 };
519
520 static bool
521 needs_modeset(struct drm_crtc_state *state)
522 {
523 return drm_atomic_crtc_needs_modeset(state);
524 }
525
526 /**
527 * Returns whether any output on the specified pipe is of the specified type
528 */
529 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
530 {
531 struct drm_device *dev = crtc->base.dev;
532 struct intel_encoder *encoder;
533
534 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
535 if (encoder->type == type)
536 return true;
537
538 return false;
539 }
540
541 /**
542 * Returns whether any output on the specified pipe will have the specified
543 * type after a staged modeset is complete, i.e., the same as
544 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
545 * encoder->crtc.
546 */
547 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
548 int type)
549 {
550 struct drm_atomic_state *state = crtc_state->base.state;
551 struct drm_connector *connector;
552 struct drm_connector_state *connector_state;
553 struct intel_encoder *encoder;
554 int i, num_connectors = 0;
555
556 for_each_connector_in_state(state, connector, connector_state, i) {
557 if (connector_state->crtc != crtc_state->base.crtc)
558 continue;
559
560 num_connectors++;
561
562 encoder = to_intel_encoder(connector_state->best_encoder);
563 if (encoder->type == type)
564 return true;
565 }
566
567 WARN_ON(num_connectors == 0);
568
569 return false;
570 }
571
572 /*
573 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
574 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
575 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
576 * The helpers' return value is the rate of the clock that is fed to the
577 * display engine's pipe which can be the above fast dot clock rate or a
578 * divided-down version of it.
579 */
580 /* m1 is reserved as 0 in Pineview, n is a ring counter */
581 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
582 {
583 clock->m = clock->m2 + 2;
584 clock->p = clock->p1 * clock->p2;
585 if (WARN_ON(clock->n == 0 || clock->p == 0))
586 return 0;
587 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
588 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
589
590 return clock->dot;
591 }
592
593 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
594 {
595 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
596 }
597
598 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
599 {
600 clock->m = i9xx_dpll_compute_m(clock);
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
603 return 0;
604 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
605 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
606
607 return clock->dot;
608 }
609
610 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
611 {
612 clock->m = clock->m1 * clock->m2;
613 clock->p = clock->p1 * clock->p2;
614 if (WARN_ON(clock->n == 0 || clock->p == 0))
615 return 0;
616 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
617 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
618
619 return clock->dot / 5;
620 }
621
622 int chv_calc_dpll_params(int refclk, struct dpll *clock)
623 {
624 clock->m = clock->m1 * clock->m2;
625 clock->p = clock->p1 * clock->p2;
626 if (WARN_ON(clock->n == 0 || clock->p == 0))
627 return 0;
628 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
629 clock->n << 22);
630 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
631
632 return clock->dot / 5;
633 }
634
635 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
636 /**
637 * Returns whether the given set of divisors are valid for a given refclk with
638 * the given connectors.
639 */
640
641 static bool intel_PLL_is_valid(struct drm_device *dev,
642 const struct intel_limit *limit,
643 const struct dpll *clock)
644 {
645 if (clock->n < limit->n.min || limit->n.max < clock->n)
646 INTELPllInvalid("n out of range\n");
647 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
648 INTELPllInvalid("p1 out of range\n");
649 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
650 INTELPllInvalid("m2 out of range\n");
651 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
652 INTELPllInvalid("m1 out of range\n");
653
654 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
655 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
656 if (clock->m1 <= clock->m2)
657 INTELPllInvalid("m1 <= m2\n");
658
659 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
660 if (clock->p < limit->p.min || limit->p.max < clock->p)
661 INTELPllInvalid("p out of range\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid("m out of range\n");
664 }
665
666 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
667 INTELPllInvalid("vco out of range\n");
668 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
669 * connector, etc., rather than just a single range.
670 */
671 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
672 INTELPllInvalid("dot out of range\n");
673
674 return true;
675 }
676
677 static int
678 i9xx_select_p2_div(const struct intel_limit *limit,
679 const struct intel_crtc_state *crtc_state,
680 int target)
681 {
682 struct drm_device *dev = crtc_state->base.crtc->dev;
683
684 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
685 /*
686 * For LVDS just rely on its current settings for dual-channel.
687 * We haven't figured out how to reliably set up different
688 * single/dual channel state, if we even can.
689 */
690 if (intel_is_dual_link_lvds(dev))
691 return limit->p2.p2_fast;
692 else
693 return limit->p2.p2_slow;
694 } else {
695 if (target < limit->p2.dot_limit)
696 return limit->p2.p2_slow;
697 else
698 return limit->p2.p2_fast;
699 }
700 }
701
702 /*
703 * Returns a set of divisors for the desired target clock with the given
704 * refclk, or FALSE. The returned values represent the clock equation:
705 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
706 *
707 * Target and reference clocks are specified in kHz.
708 *
709 * If match_clock is provided, then best_clock P divider must match the P
710 * divider from @match_clock used for LVDS downclocking.
711 */
712 static bool
713 i9xx_find_best_dpll(const struct intel_limit *limit,
714 struct intel_crtc_state *crtc_state,
715 int target, int refclk, struct dpll *match_clock,
716 struct dpll *best_clock)
717 {
718 struct drm_device *dev = crtc_state->base.crtc->dev;
719 struct dpll clock;
720 int err = target;
721
722 memset(best_clock, 0, sizeof(*best_clock));
723
724 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
725
726 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
727 clock.m1++) {
728 for (clock.m2 = limit->m2.min;
729 clock.m2 <= limit->m2.max; clock.m2++) {
730 if (clock.m2 >= clock.m1)
731 break;
732 for (clock.n = limit->n.min;
733 clock.n <= limit->n.max; clock.n++) {
734 for (clock.p1 = limit->p1.min;
735 clock.p1 <= limit->p1.max; clock.p1++) {
736 int this_err;
737
738 i9xx_calc_dpll_params(refclk, &clock);
739 if (!intel_PLL_is_valid(dev, limit,
740 &clock))
741 continue;
742 if (match_clock &&
743 clock.p != match_clock->p)
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err) {
748 *best_clock = clock;
749 err = this_err;
750 }
751 }
752 }
753 }
754 }
755
756 return (err != target);
757 }
758
759 /*
760 * Returns a set of divisors for the desired target clock with the given
761 * refclk, or FALSE. The returned values represent the clock equation:
762 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
763 *
764 * Target and reference clocks are specified in kHz.
765 *
766 * If match_clock is provided, then best_clock P divider must match the P
767 * divider from @match_clock used for LVDS downclocking.
768 */
769 static bool
770 pnv_find_best_dpll(const struct intel_limit *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, struct dpll *match_clock,
773 struct dpll *best_clock)
774 {
775 struct drm_device *dev = crtc_state->base.crtc->dev;
776 struct dpll clock;
777 int err = target;
778
779 memset(best_clock, 0, sizeof(*best_clock));
780
781 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
782
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
784 clock.m1++) {
785 for (clock.m2 = limit->m2.min;
786 clock.m2 <= limit->m2.max; clock.m2++) {
787 for (clock.n = limit->n.min;
788 clock.n <= limit->n.max; clock.n++) {
789 for (clock.p1 = limit->p1.min;
790 clock.p1 <= limit->p1.max; clock.p1++) {
791 int this_err;
792
793 pnv_calc_dpll_params(refclk, &clock);
794 if (!intel_PLL_is_valid(dev, limit,
795 &clock))
796 continue;
797 if (match_clock &&
798 clock.p != match_clock->p)
799 continue;
800
801 this_err = abs(clock.dot - target);
802 if (this_err < err) {
803 *best_clock = clock;
804 err = this_err;
805 }
806 }
807 }
808 }
809 }
810
811 return (err != target);
812 }
813
814 /*
815 * Returns a set of divisors for the desired target clock with the given
816 * refclk, or FALSE. The returned values represent the clock equation:
817 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
818 *
819 * Target and reference clocks are specified in kHz.
820 *
821 * If match_clock is provided, then best_clock P divider must match the P
822 * divider from @match_clock used for LVDS downclocking.
823 */
824 static bool
825 g4x_find_best_dpll(const struct intel_limit *limit,
826 struct intel_crtc_state *crtc_state,
827 int target, int refclk, struct dpll *match_clock,
828 struct dpll *best_clock)
829 {
830 struct drm_device *dev = crtc_state->base.crtc->dev;
831 struct dpll clock;
832 int max_n;
833 bool found = false;
834 /* approximately equals target * 0.00585 */
835 int err_most = (target >> 8) + (target >> 9);
836
837 memset(best_clock, 0, sizeof(*best_clock));
838
839 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
840
841 max_n = limit->n.max;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
844 /* based on hardware requirement, prefere larger m1,m2 */
845 for (clock.m1 = limit->m1.max;
846 clock.m1 >= limit->m1.min; clock.m1--) {
847 for (clock.m2 = limit->m2.max;
848 clock.m2 >= limit->m2.min; clock.m2--) {
849 for (clock.p1 = limit->p1.max;
850 clock.p1 >= limit->p1.min; clock.p1--) {
851 int this_err;
852
853 i9xx_calc_dpll_params(refclk, &clock);
854 if (!intel_PLL_is_valid(dev, limit,
855 &clock))
856 continue;
857
858 this_err = abs(clock.dot - target);
859 if (this_err < err_most) {
860 *best_clock = clock;
861 err_most = this_err;
862 max_n = clock.n;
863 found = true;
864 }
865 }
866 }
867 }
868 }
869 return found;
870 }
871
872 /*
873 * Check if the calculated PLL configuration is more optimal compared to the
874 * best configuration and error found so far. Return the calculated error.
875 */
876 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
877 const struct dpll *calculated_clock,
878 const struct dpll *best_clock,
879 unsigned int best_error_ppm,
880 unsigned int *error_ppm)
881 {
882 /*
883 * For CHV ignore the error and consider only the P value.
884 * Prefer a bigger P value based on HW requirements.
885 */
886 if (IS_CHERRYVIEW(dev)) {
887 *error_ppm = 0;
888
889 return calculated_clock->p > best_clock->p;
890 }
891
892 if (WARN_ON_ONCE(!target_freq))
893 return false;
894
895 *error_ppm = div_u64(1000000ULL *
896 abs(target_freq - calculated_clock->dot),
897 target_freq);
898 /*
899 * Prefer a better P value over a better (smaller) error if the error
900 * is small. Ensure this preference for future configurations too by
901 * setting the error to 0.
902 */
903 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
904 *error_ppm = 0;
905
906 return true;
907 }
908
909 return *error_ppm + 10 < best_error_ppm;
910 }
911
912 /*
913 * Returns a set of divisors for the desired target clock with the given
914 * refclk, or FALSE. The returned values represent the clock equation:
915 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
916 */
917 static bool
918 vlv_find_best_dpll(const struct intel_limit *limit,
919 struct intel_crtc_state *crtc_state,
920 int target, int refclk, struct dpll *match_clock,
921 struct dpll *best_clock)
922 {
923 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
924 struct drm_device *dev = crtc->base.dev;
925 struct dpll clock;
926 unsigned int bestppm = 1000000;
927 /* min update 19.2 MHz */
928 int max_n = min(limit->n.max, refclk / 19200);
929 bool found = false;
930
931 target *= 5; /* fast clock */
932
933 memset(best_clock, 0, sizeof(*best_clock));
934
935 /* based on hardware requirement, prefer smaller n to precision */
936 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
937 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
938 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
939 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
940 clock.p = clock.p1 * clock.p2;
941 /* based on hardware requirement, prefer bigger m1,m2 values */
942 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
943 unsigned int ppm;
944
945 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
946 refclk * clock.m1);
947
948 vlv_calc_dpll_params(refclk, &clock);
949
950 if (!intel_PLL_is_valid(dev, limit,
951 &clock))
952 continue;
953
954 if (!vlv_PLL_is_optimal(dev, target,
955 &clock,
956 best_clock,
957 bestppm, &ppm))
958 continue;
959
960 *best_clock = clock;
961 bestppm = ppm;
962 found = true;
963 }
964 }
965 }
966 }
967
968 return found;
969 }
970
971 /*
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
975 */
976 static bool
977 chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
981 {
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
985 struct dpll clock;
986 uint64_t m2;
987 int found = false;
988
989 memset(best_clock, 0, sizeof(*best_clock));
990 best_error_ppm = 1000000;
991
992 /*
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
996 */
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
999
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1005
1006 clock.p = clock.p1 * clock.p2;
1007
1008 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1009 clock.n) << 22, refclk * clock.m1);
1010
1011 if (m2 > INT_MAX/clock.m1)
1012 continue;
1013
1014 clock.m2 = m2;
1015
1016 chv_calc_dpll_params(refclk, &clock);
1017
1018 if (!intel_PLL_is_valid(dev, limit, &clock))
1019 continue;
1020
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1023 continue;
1024
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1027 found = true;
1028 }
1029 }
1030
1031 return found;
1032 }
1033
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1035 struct dpll *best_clock)
1036 {
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1039
1040 return chv_find_best_dpll(limit, crtc_state,
1041 target_clock, refclk, NULL, best_clock);
1042 }
1043
1044 bool intel_crtc_active(struct drm_crtc *crtc)
1045 {
1046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1047
1048 /* Be paranoid as we can arrive here with only partial
1049 * state retrieved from the hardware during setup.
1050 *
1051 * We can ditch the adjusted_mode.crtc_clock check as soon
1052 * as Haswell has gained clock readout/fastboot support.
1053 *
1054 * We can ditch the crtc->primary->fb check as soon as we can
1055 * properly reconstruct framebuffers.
1056 *
1057 * FIXME: The intel_crtc->active here should be switched to
1058 * crtc->state->active once we have proper CRTC states wired up
1059 * for atomic.
1060 */
1061 return intel_crtc->active && crtc->primary->state->fb &&
1062 intel_crtc->config->base.adjusted_mode.crtc_clock;
1063 }
1064
1065 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1066 enum pipe pipe)
1067 {
1068 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071 return intel_crtc->config->cpu_transcoder;
1072 }
1073
1074 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1075 {
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 i915_reg_t reg = PIPEDSL(pipe);
1078 u32 line1, line2;
1079 u32 line_mask;
1080
1081 if (IS_GEN2(dev))
1082 line_mask = DSL_LINEMASK_GEN2;
1083 else
1084 line_mask = DSL_LINEMASK_GEN3;
1085
1086 line1 = I915_READ(reg) & line_mask;
1087 msleep(5);
1088 line2 = I915_READ(reg) & line_mask;
1089
1090 return line1 == line2;
1091 }
1092
1093 /*
1094 * intel_wait_for_pipe_off - wait for pipe to turn off
1095 * @crtc: crtc whose pipe to wait for
1096 *
1097 * After disabling a pipe, we can't wait for vblank in the usual way,
1098 * spinning on the vblank interrupt status bit, since we won't actually
1099 * see an interrupt when the pipe is disabled.
1100 *
1101 * On Gen4 and above:
1102 * wait for the pipe register state bit to turn off
1103 *
1104 * Otherwise:
1105 * wait for the display line value to settle (it usually
1106 * ends up stopping at the start of the next frame).
1107 *
1108 */
1109 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1110 {
1111 struct drm_device *dev = crtc->base.dev;
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1114 enum pipe pipe = crtc->pipe;
1115
1116 if (INTEL_INFO(dev)->gen >= 4) {
1117 i915_reg_t reg = PIPECONF(cpu_transcoder);
1118
1119 /* Wait for the Pipe State to go off */
1120 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1121 100))
1122 WARN(1, "pipe_off wait timed out\n");
1123 } else {
1124 /* Wait for the display line to settle */
1125 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1126 WARN(1, "pipe_off wait timed out\n");
1127 }
1128 }
1129
1130 /* Only for pre-ILK configs */
1131 void assert_pll(struct drm_i915_private *dev_priv,
1132 enum pipe pipe, bool state)
1133 {
1134 u32 val;
1135 bool cur_state;
1136
1137 val = I915_READ(DPLL(pipe));
1138 cur_state = !!(val & DPLL_VCO_ENABLE);
1139 I915_STATE_WARN(cur_state != state,
1140 "PLL state assertion failure (expected %s, current %s)\n",
1141 onoff(state), onoff(cur_state));
1142 }
1143
1144 /* XXX: the dsi pll is shared between MIPI DSI ports */
1145 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1146 {
1147 u32 val;
1148 bool cur_state;
1149
1150 mutex_lock(&dev_priv->sb_lock);
1151 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1152 mutex_unlock(&dev_priv->sb_lock);
1153
1154 cur_state = val & DSI_PLL_VCO_EN;
1155 I915_STATE_WARN(cur_state != state,
1156 "DSI PLL state assertion failure (expected %s, current %s)\n",
1157 onoff(state), onoff(cur_state));
1158 }
1159
1160 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1161 enum pipe pipe, bool state)
1162 {
1163 bool cur_state;
1164 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1165 pipe);
1166
1167 if (HAS_DDI(dev_priv)) {
1168 /* DDI does not have a specific FDI_TX register */
1169 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1170 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1171 } else {
1172 u32 val = I915_READ(FDI_TX_CTL(pipe));
1173 cur_state = !!(val & FDI_TX_ENABLE);
1174 }
1175 I915_STATE_WARN(cur_state != state,
1176 "FDI TX state assertion failure (expected %s, current %s)\n",
1177 onoff(state), onoff(cur_state));
1178 }
1179 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1180 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1181
1182 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1183 enum pipe pipe, bool state)
1184 {
1185 u32 val;
1186 bool cur_state;
1187
1188 val = I915_READ(FDI_RX_CTL(pipe));
1189 cur_state = !!(val & FDI_RX_ENABLE);
1190 I915_STATE_WARN(cur_state != state,
1191 "FDI RX state assertion failure (expected %s, current %s)\n",
1192 onoff(state), onoff(cur_state));
1193 }
1194 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1195 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1196
1197 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1198 enum pipe pipe)
1199 {
1200 u32 val;
1201
1202 /* ILK FDI PLL is always enabled */
1203 if (IS_GEN5(dev_priv))
1204 return;
1205
1206 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1207 if (HAS_DDI(dev_priv))
1208 return;
1209
1210 val = I915_READ(FDI_TX_CTL(pipe));
1211 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1212 }
1213
1214 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1215 enum pipe pipe, bool state)
1216 {
1217 u32 val;
1218 bool cur_state;
1219
1220 val = I915_READ(FDI_RX_CTL(pipe));
1221 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1222 I915_STATE_WARN(cur_state != state,
1223 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1224 onoff(state), onoff(cur_state));
1225 }
1226
1227 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229 {
1230 struct drm_device *dev = dev_priv->dev;
1231 i915_reg_t pp_reg;
1232 u32 val;
1233 enum pipe panel_pipe = PIPE_A;
1234 bool locked = true;
1235
1236 if (WARN_ON(HAS_DDI(dev)))
1237 return;
1238
1239 if (HAS_PCH_SPLIT(dev)) {
1240 u32 port_sel;
1241
1242 pp_reg = PCH_PP_CONTROL;
1243 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1244
1245 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1246 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1247 panel_pipe = PIPE_B;
1248 /* XXX: else fix for eDP */
1249 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1250 /* presumably write lock depends on pipe, not port select */
1251 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1252 panel_pipe = pipe;
1253 } else {
1254 pp_reg = PP_CONTROL;
1255 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1256 panel_pipe = PIPE_B;
1257 }
1258
1259 val = I915_READ(pp_reg);
1260 if (!(val & PANEL_POWER_ON) ||
1261 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1262 locked = false;
1263
1264 I915_STATE_WARN(panel_pipe == pipe && locked,
1265 "panel assertion failure, pipe %c regs locked\n",
1266 pipe_name(pipe));
1267 }
1268
1269 static void assert_cursor(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, bool state)
1271 {
1272 struct drm_device *dev = dev_priv->dev;
1273 bool cur_state;
1274
1275 if (IS_845G(dev) || IS_I865G(dev))
1276 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1277 else
1278 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1279
1280 I915_STATE_WARN(cur_state != state,
1281 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1282 pipe_name(pipe), onoff(state), onoff(cur_state));
1283 }
1284 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1285 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1286
1287 void assert_pipe(struct drm_i915_private *dev_priv,
1288 enum pipe pipe, bool state)
1289 {
1290 bool cur_state;
1291 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1292 pipe);
1293 enum intel_display_power_domain power_domain;
1294
1295 /* if we need the pipe quirk it must be always on */
1296 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1297 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1298 state = true;
1299
1300 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1301 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1302 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1303 cur_state = !!(val & PIPECONF_ENABLE);
1304
1305 intel_display_power_put(dev_priv, power_domain);
1306 } else {
1307 cur_state = false;
1308 }
1309
1310 I915_STATE_WARN(cur_state != state,
1311 "pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), onoff(state), onoff(cur_state));
1313 }
1314
1315 static void assert_plane(struct drm_i915_private *dev_priv,
1316 enum plane plane, bool state)
1317 {
1318 u32 val;
1319 bool cur_state;
1320
1321 val = I915_READ(DSPCNTR(plane));
1322 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1323 I915_STATE_WARN(cur_state != state,
1324 "plane %c assertion failure (expected %s, current %s)\n",
1325 plane_name(plane), onoff(state), onoff(cur_state));
1326 }
1327
1328 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1329 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1330
1331 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe)
1333 {
1334 struct drm_device *dev = dev_priv->dev;
1335 int i;
1336
1337 /* Primary planes are fixed to pipes on gen4+ */
1338 if (INTEL_INFO(dev)->gen >= 4) {
1339 u32 val = I915_READ(DSPCNTR(pipe));
1340 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1341 "plane %c assertion failure, should be disabled but not\n",
1342 plane_name(pipe));
1343 return;
1344 }
1345
1346 /* Need to check both planes against the pipe */
1347 for_each_pipe(dev_priv, i) {
1348 u32 val = I915_READ(DSPCNTR(i));
1349 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1350 DISPPLANE_SEL_PIPE_SHIFT;
1351 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1352 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1353 plane_name(i), pipe_name(pipe));
1354 }
1355 }
1356
1357 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359 {
1360 struct drm_device *dev = dev_priv->dev;
1361 int sprite;
1362
1363 if (INTEL_INFO(dev)->gen >= 9) {
1364 for_each_sprite(dev_priv, pipe, sprite) {
1365 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1366 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1367 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1368 sprite, pipe_name(pipe));
1369 }
1370 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1371 for_each_sprite(dev_priv, pipe, sprite) {
1372 u32 val = I915_READ(SPCNTR(pipe, sprite));
1373 I915_STATE_WARN(val & SP_ENABLE,
1374 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1375 sprite_name(pipe, sprite), pipe_name(pipe));
1376 }
1377 } else if (INTEL_INFO(dev)->gen >= 7) {
1378 u32 val = I915_READ(SPRCTL(pipe));
1379 I915_STATE_WARN(val & SPRITE_ENABLE,
1380 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1381 plane_name(pipe), pipe_name(pipe));
1382 } else if (INTEL_INFO(dev)->gen >= 5) {
1383 u32 val = I915_READ(DVSCNTR(pipe));
1384 I915_STATE_WARN(val & DVS_ENABLE,
1385 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(pipe), pipe_name(pipe));
1387 }
1388 }
1389
1390 static void assert_vblank_disabled(struct drm_crtc *crtc)
1391 {
1392 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1393 drm_crtc_vblank_put(crtc);
1394 }
1395
1396 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe)
1398 {
1399 u32 val;
1400 bool enabled;
1401
1402 val = I915_READ(PCH_TRANSCONF(pipe));
1403 enabled = !!(val & TRANS_ENABLE);
1404 I915_STATE_WARN(enabled,
1405 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1406 pipe_name(pipe));
1407 }
1408
1409 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 port_sel, u32 val)
1411 {
1412 if ((val & DP_PORT_EN) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv)) {
1416 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1417 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1418 return false;
1419 } else if (IS_CHERRYVIEW(dev_priv)) {
1420 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1421 return false;
1422 } else {
1423 if ((val & DP_PIPE_MASK) != (pipe << 30))
1424 return false;
1425 }
1426 return true;
1427 }
1428
1429 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1430 enum pipe pipe, u32 val)
1431 {
1432 if ((val & SDVO_ENABLE) == 0)
1433 return false;
1434
1435 if (HAS_PCH_CPT(dev_priv)) {
1436 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1437 return false;
1438 } else if (IS_CHERRYVIEW(dev_priv)) {
1439 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1440 return false;
1441 } else {
1442 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1443 return false;
1444 }
1445 return true;
1446 }
1447
1448 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1449 enum pipe pipe, u32 val)
1450 {
1451 if ((val & LVDS_PORT_EN) == 0)
1452 return false;
1453
1454 if (HAS_PCH_CPT(dev_priv)) {
1455 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1456 return false;
1457 } else {
1458 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1459 return false;
1460 }
1461 return true;
1462 }
1463
1464 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 val)
1466 {
1467 if ((val & ADPA_DAC_ENABLE) == 0)
1468 return false;
1469 if (HAS_PCH_CPT(dev_priv)) {
1470 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1471 return false;
1472 } else {
1473 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1474 return false;
1475 }
1476 return true;
1477 }
1478
1479 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, i915_reg_t reg,
1481 u32 port_sel)
1482 {
1483 u32 val = I915_READ(reg);
1484 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1485 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1486 i915_mmio_reg_offset(reg), pipe_name(pipe));
1487
1488 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1489 && (val & DP_PIPEB_SELECT),
1490 "IBX PCH dp port still using transcoder B\n");
1491 }
1492
1493 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe, i915_reg_t reg)
1495 {
1496 u32 val = I915_READ(reg);
1497 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1498 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1499 i915_mmio_reg_offset(reg), pipe_name(pipe));
1500
1501 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1502 && (val & SDVO_PIPE_B_SELECT),
1503 "IBX PCH hdmi port still using transcoder B\n");
1504 }
1505
1506 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1507 enum pipe pipe)
1508 {
1509 u32 val;
1510
1511 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1512 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1514
1515 val = I915_READ(PCH_ADPA);
1516 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1517 "PCH VGA enabled on transcoder %c, should be disabled\n",
1518 pipe_name(pipe));
1519
1520 val = I915_READ(PCH_LVDS);
1521 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1522 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1523 pipe_name(pipe));
1524
1525 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1526 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1527 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1528 }
1529
1530 static void _vlv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
1532 {
1533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534 enum pipe pipe = crtc->pipe;
1535
1536 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1537 POSTING_READ(DPLL(pipe));
1538 udelay(150);
1539
1540 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1541 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1542 }
1543
1544 static void vlv_enable_pll(struct intel_crtc *crtc,
1545 const struct intel_crtc_state *pipe_config)
1546 {
1547 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1548 enum pipe pipe = crtc->pipe;
1549
1550 assert_pipe_disabled(dev_priv, pipe);
1551
1552 /* PLL is protected by panel, make sure we can write it */
1553 assert_panel_unlocked(dev_priv, pipe);
1554
1555 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1556 _vlv_enable_pll(crtc, pipe_config);
1557
1558 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1559 POSTING_READ(DPLL_MD(pipe));
1560 }
1561
1562
1563 static void _chv_enable_pll(struct intel_crtc *crtc,
1564 const struct intel_crtc_state *pipe_config)
1565 {
1566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1567 enum pipe pipe = crtc->pipe;
1568 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1569 u32 tmp;
1570
1571 mutex_lock(&dev_priv->sb_lock);
1572
1573 /* Enable back the 10bit clock to display controller */
1574 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1575 tmp |= DPIO_DCLKP_EN;
1576 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1577
1578 mutex_unlock(&dev_priv->sb_lock);
1579
1580 /*
1581 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1582 */
1583 udelay(1);
1584
1585 /* Enable PLL */
1586 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1587
1588 /* Check PLL is locked */
1589 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1590 DRM_ERROR("PLL %d failed to lock\n", pipe);
1591 }
1592
1593 static void chv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1595 {
1596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1597 enum pipe pipe = crtc->pipe;
1598
1599 assert_pipe_disabled(dev_priv, pipe);
1600
1601 /* PLL is protected by panel, make sure we can write it */
1602 assert_panel_unlocked(dev_priv, pipe);
1603
1604 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1605 _chv_enable_pll(crtc, pipe_config);
1606
1607 if (pipe != PIPE_A) {
1608 /*
1609 * WaPixelRepeatModeFixForC0:chv
1610 *
1611 * DPLLCMD is AWOL. Use chicken bits to propagate
1612 * the value from DPLLBMD to either pipe B or C.
1613 */
1614 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1615 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1616 I915_WRITE(CBR4_VLV, 0);
1617 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1618
1619 /*
1620 * DPLLB VGA mode also seems to cause problems.
1621 * We should always have it disabled.
1622 */
1623 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1624 } else {
1625 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1626 POSTING_READ(DPLL_MD(pipe));
1627 }
1628 }
1629
1630 static int intel_num_dvo_pipes(struct drm_device *dev)
1631 {
1632 struct intel_crtc *crtc;
1633 int count = 0;
1634
1635 for_each_intel_crtc(dev, crtc)
1636 count += crtc->base.state->active &&
1637 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1638
1639 return count;
1640 }
1641
1642 static void i9xx_enable_pll(struct intel_crtc *crtc)
1643 {
1644 struct drm_device *dev = crtc->base.dev;
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646 i915_reg_t reg = DPLL(crtc->pipe);
1647 u32 dpll = crtc->config->dpll_hw_state.dpll;
1648
1649 assert_pipe_disabled(dev_priv, crtc->pipe);
1650
1651 /* PLL is protected by panel, make sure we can write it */
1652 if (IS_MOBILE(dev) && !IS_I830(dev))
1653 assert_panel_unlocked(dev_priv, crtc->pipe);
1654
1655 /* Enable DVO 2x clock on both PLLs if necessary */
1656 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1657 /*
1658 * It appears to be important that we don't enable this
1659 * for the current pipe before otherwise configuring the
1660 * PLL. No idea how this should be handled if multiple
1661 * DVO outputs are enabled simultaneosly.
1662 */
1663 dpll |= DPLL_DVO_2X_MODE;
1664 I915_WRITE(DPLL(!crtc->pipe),
1665 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1666 }
1667
1668 /*
1669 * Apparently we need to have VGA mode enabled prior to changing
1670 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1671 * dividers, even though the register value does change.
1672 */
1673 I915_WRITE(reg, 0);
1674
1675 I915_WRITE(reg, dpll);
1676
1677 /* Wait for the clocks to stabilize. */
1678 POSTING_READ(reg);
1679 udelay(150);
1680
1681 if (INTEL_INFO(dev)->gen >= 4) {
1682 I915_WRITE(DPLL_MD(crtc->pipe),
1683 crtc->config->dpll_hw_state.dpll_md);
1684 } else {
1685 /* The pixel multiplier can only be updated once the
1686 * DPLL is enabled and the clocks are stable.
1687 *
1688 * So write it again.
1689 */
1690 I915_WRITE(reg, dpll);
1691 }
1692
1693 /* We do this three times for luck */
1694 I915_WRITE(reg, dpll);
1695 POSTING_READ(reg);
1696 udelay(150); /* wait for warmup */
1697 I915_WRITE(reg, dpll);
1698 POSTING_READ(reg);
1699 udelay(150); /* wait for warmup */
1700 I915_WRITE(reg, dpll);
1701 POSTING_READ(reg);
1702 udelay(150); /* wait for warmup */
1703 }
1704
1705 /**
1706 * i9xx_disable_pll - disable a PLL
1707 * @dev_priv: i915 private structure
1708 * @pipe: pipe PLL to disable
1709 *
1710 * Disable the PLL for @pipe, making sure the pipe is off first.
1711 *
1712 * Note! This is for pre-ILK only.
1713 */
1714 static void i9xx_disable_pll(struct intel_crtc *crtc)
1715 {
1716 struct drm_device *dev = crtc->base.dev;
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718 enum pipe pipe = crtc->pipe;
1719
1720 /* Disable DVO 2x clock on both PLLs if necessary */
1721 if (IS_I830(dev) &&
1722 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1723 !intel_num_dvo_pipes(dev)) {
1724 I915_WRITE(DPLL(PIPE_B),
1725 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1726 I915_WRITE(DPLL(PIPE_A),
1727 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1728 }
1729
1730 /* Don't disable pipe or pipe PLLs if needed */
1731 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1732 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1733 return;
1734
1735 /* Make sure the pipe isn't still relying on us */
1736 assert_pipe_disabled(dev_priv, pipe);
1737
1738 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1739 POSTING_READ(DPLL(pipe));
1740 }
1741
1742 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1743 {
1744 u32 val;
1745
1746 /* Make sure the pipe isn't still relying on us */
1747 assert_pipe_disabled(dev_priv, pipe);
1748
1749 val = DPLL_INTEGRATED_REF_CLK_VLV |
1750 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1751 if (pipe != PIPE_A)
1752 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1753
1754 I915_WRITE(DPLL(pipe), val);
1755 POSTING_READ(DPLL(pipe));
1756 }
1757
1758 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1759 {
1760 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1761 u32 val;
1762
1763 /* Make sure the pipe isn't still relying on us */
1764 assert_pipe_disabled(dev_priv, pipe);
1765
1766 val = DPLL_SSC_REF_CLK_CHV |
1767 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1768 if (pipe != PIPE_A)
1769 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1770
1771 I915_WRITE(DPLL(pipe), val);
1772 POSTING_READ(DPLL(pipe));
1773
1774 mutex_lock(&dev_priv->sb_lock);
1775
1776 /* Disable 10bit clock to display controller */
1777 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1778 val &= ~DPIO_DCLKP_EN;
1779 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1780
1781 mutex_unlock(&dev_priv->sb_lock);
1782 }
1783
1784 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1785 struct intel_digital_port *dport,
1786 unsigned int expected_mask)
1787 {
1788 u32 port_mask;
1789 i915_reg_t dpll_reg;
1790
1791 switch (dport->port) {
1792 case PORT_B:
1793 port_mask = DPLL_PORTB_READY_MASK;
1794 dpll_reg = DPLL(0);
1795 break;
1796 case PORT_C:
1797 port_mask = DPLL_PORTC_READY_MASK;
1798 dpll_reg = DPLL(0);
1799 expected_mask <<= 4;
1800 break;
1801 case PORT_D:
1802 port_mask = DPLL_PORTD_READY_MASK;
1803 dpll_reg = DPIO_PHY_STATUS;
1804 break;
1805 default:
1806 BUG();
1807 }
1808
1809 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1810 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1811 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1812 }
1813
1814 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1815 enum pipe pipe)
1816 {
1817 struct drm_device *dev = dev_priv->dev;
1818 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1820 i915_reg_t reg;
1821 uint32_t val, pipeconf_val;
1822
1823 /* Make sure PCH DPLL is enabled */
1824 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1825
1826 /* FDI must be feeding us bits for PCH ports */
1827 assert_fdi_tx_enabled(dev_priv, pipe);
1828 assert_fdi_rx_enabled(dev_priv, pipe);
1829
1830 if (HAS_PCH_CPT(dev)) {
1831 /* Workaround: Set the timing override bit before enabling the
1832 * pch transcoder. */
1833 reg = TRANS_CHICKEN2(pipe);
1834 val = I915_READ(reg);
1835 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1836 I915_WRITE(reg, val);
1837 }
1838
1839 reg = PCH_TRANSCONF(pipe);
1840 val = I915_READ(reg);
1841 pipeconf_val = I915_READ(PIPECONF(pipe));
1842
1843 if (HAS_PCH_IBX(dev_priv)) {
1844 /*
1845 * Make the BPC in transcoder be consistent with
1846 * that in pipeconf reg. For HDMI we must use 8bpc
1847 * here for both 8bpc and 12bpc.
1848 */
1849 val &= ~PIPECONF_BPC_MASK;
1850 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1851 val |= PIPECONF_8BPC;
1852 else
1853 val |= pipeconf_val & PIPECONF_BPC_MASK;
1854 }
1855
1856 val &= ~TRANS_INTERLACE_MASK;
1857 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1858 if (HAS_PCH_IBX(dev_priv) &&
1859 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1860 val |= TRANS_LEGACY_INTERLACED_ILK;
1861 else
1862 val |= TRANS_INTERLACED;
1863 else
1864 val |= TRANS_PROGRESSIVE;
1865
1866 I915_WRITE(reg, val | TRANS_ENABLE);
1867 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1868 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1869 }
1870
1871 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1872 enum transcoder cpu_transcoder)
1873 {
1874 u32 val, pipeconf_val;
1875
1876 /* FDI must be feeding us bits for PCH ports */
1877 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1878 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1879
1880 /* Workaround: set timing override bit. */
1881 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1882 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1883 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1884
1885 val = TRANS_ENABLE;
1886 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1887
1888 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1889 PIPECONF_INTERLACED_ILK)
1890 val |= TRANS_INTERLACED;
1891 else
1892 val |= TRANS_PROGRESSIVE;
1893
1894 I915_WRITE(LPT_TRANSCONF, val);
1895 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1896 DRM_ERROR("Failed to enable PCH transcoder\n");
1897 }
1898
1899 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1900 enum pipe pipe)
1901 {
1902 struct drm_device *dev = dev_priv->dev;
1903 i915_reg_t reg;
1904 uint32_t val;
1905
1906 /* FDI relies on the transcoder */
1907 assert_fdi_tx_disabled(dev_priv, pipe);
1908 assert_fdi_rx_disabled(dev_priv, pipe);
1909
1910 /* Ports must be off as well */
1911 assert_pch_ports_disabled(dev_priv, pipe);
1912
1913 reg = PCH_TRANSCONF(pipe);
1914 val = I915_READ(reg);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(reg, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1919 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1920
1921 if (HAS_PCH_CPT(dev)) {
1922 /* Workaround: Clear the timing override chicken bit again. */
1923 reg = TRANS_CHICKEN2(pipe);
1924 val = I915_READ(reg);
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(reg, val);
1927 }
1928 }
1929
1930 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1931 {
1932 u32 val;
1933
1934 val = I915_READ(LPT_TRANSCONF);
1935 val &= ~TRANS_ENABLE;
1936 I915_WRITE(LPT_TRANSCONF, val);
1937 /* wait for PCH transcoder off, transcoder state */
1938 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1939 DRM_ERROR("Failed to disable PCH transcoder\n");
1940
1941 /* Workaround: clear timing override bit. */
1942 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1943 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1944 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1945 }
1946
1947 /**
1948 * intel_enable_pipe - enable a pipe, asserting requirements
1949 * @crtc: crtc responsible for the pipe
1950 *
1951 * Enable @crtc's pipe, making sure that various hardware specific requirements
1952 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1953 */
1954 static void intel_enable_pipe(struct intel_crtc *crtc)
1955 {
1956 struct drm_device *dev = crtc->base.dev;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958 enum pipe pipe = crtc->pipe;
1959 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1960 enum pipe pch_transcoder;
1961 i915_reg_t reg;
1962 u32 val;
1963
1964 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1965
1966 assert_planes_disabled(dev_priv, pipe);
1967 assert_cursor_disabled(dev_priv, pipe);
1968 assert_sprites_disabled(dev_priv, pipe);
1969
1970 if (HAS_PCH_LPT(dev_priv))
1971 pch_transcoder = TRANSCODER_A;
1972 else
1973 pch_transcoder = pipe;
1974
1975 /*
1976 * A pipe without a PLL won't actually be able to drive bits from
1977 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1978 * need the check.
1979 */
1980 if (HAS_GMCH_DISPLAY(dev_priv))
1981 if (crtc->config->has_dsi_encoder)
1982 assert_dsi_pll_enabled(dev_priv);
1983 else
1984 assert_pll_enabled(dev_priv, pipe);
1985 else {
1986 if (crtc->config->has_pch_encoder) {
1987 /* if driving the PCH, we need FDI enabled */
1988 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1989 assert_fdi_tx_pll_enabled(dev_priv,
1990 (enum pipe) cpu_transcoder);
1991 }
1992 /* FIXME: assert CPU port conditions for SNB+ */
1993 }
1994
1995 reg = PIPECONF(cpu_transcoder);
1996 val = I915_READ(reg);
1997 if (val & PIPECONF_ENABLE) {
1998 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1999 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2000 return;
2001 }
2002
2003 I915_WRITE(reg, val | PIPECONF_ENABLE);
2004 POSTING_READ(reg);
2005
2006 /*
2007 * Until the pipe starts DSL will read as 0, which would cause
2008 * an apparent vblank timestamp jump, which messes up also the
2009 * frame count when it's derived from the timestamps. So let's
2010 * wait for the pipe to start properly before we call
2011 * drm_crtc_vblank_on()
2012 */
2013 if (dev->max_vblank_count == 0 &&
2014 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2015 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2016 }
2017
2018 /**
2019 * intel_disable_pipe - disable a pipe, asserting requirements
2020 * @crtc: crtc whose pipes is to be disabled
2021 *
2022 * Disable the pipe of @crtc, making sure that various hardware
2023 * specific requirements are met, if applicable, e.g. plane
2024 * disabled, panel fitter off, etc.
2025 *
2026 * Will wait until the pipe has shut down before returning.
2027 */
2028 static void intel_disable_pipe(struct intel_crtc *crtc)
2029 {
2030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2031 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2032 enum pipe pipe = crtc->pipe;
2033 i915_reg_t reg;
2034 u32 val;
2035
2036 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2037
2038 /*
2039 * Make sure planes won't keep trying to pump pixels to us,
2040 * or we might hang the display.
2041 */
2042 assert_planes_disabled(dev_priv, pipe);
2043 assert_cursor_disabled(dev_priv, pipe);
2044 assert_sprites_disabled(dev_priv, pipe);
2045
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if ((val & PIPECONF_ENABLE) == 0)
2049 return;
2050
2051 /*
2052 * Double wide has implications for planes
2053 * so best keep it disabled when not needed.
2054 */
2055 if (crtc->config->double_wide)
2056 val &= ~PIPECONF_DOUBLE_WIDE;
2057
2058 /* Don't disable pipe or pipe PLLs if needed */
2059 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2060 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2061 val &= ~PIPECONF_ENABLE;
2062
2063 I915_WRITE(reg, val);
2064 if ((val & PIPECONF_ENABLE) == 0)
2065 intel_wait_for_pipe_off(crtc);
2066 }
2067
2068 static bool need_vtd_wa(struct drm_device *dev)
2069 {
2070 #ifdef CONFIG_INTEL_IOMMU
2071 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2072 return true;
2073 #endif
2074 return false;
2075 }
2076
2077 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2078 {
2079 return IS_GEN2(dev_priv) ? 2048 : 4096;
2080 }
2081
2082 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2083 uint64_t fb_modifier, unsigned int cpp)
2084 {
2085 switch (fb_modifier) {
2086 case DRM_FORMAT_MOD_NONE:
2087 return cpp;
2088 case I915_FORMAT_MOD_X_TILED:
2089 if (IS_GEN2(dev_priv))
2090 return 128;
2091 else
2092 return 512;
2093 case I915_FORMAT_MOD_Y_TILED:
2094 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2095 return 128;
2096 else
2097 return 512;
2098 case I915_FORMAT_MOD_Yf_TILED:
2099 switch (cpp) {
2100 case 1:
2101 return 64;
2102 case 2:
2103 case 4:
2104 return 128;
2105 case 8:
2106 case 16:
2107 return 256;
2108 default:
2109 MISSING_CASE(cpp);
2110 return cpp;
2111 }
2112 break;
2113 default:
2114 MISSING_CASE(fb_modifier);
2115 return cpp;
2116 }
2117 }
2118
2119 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2120 uint64_t fb_modifier, unsigned int cpp)
2121 {
2122 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2123 return 1;
2124 else
2125 return intel_tile_size(dev_priv) /
2126 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2127 }
2128
2129 /* Return the tile dimensions in pixel units */
2130 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2131 unsigned int *tile_width,
2132 unsigned int *tile_height,
2133 uint64_t fb_modifier,
2134 unsigned int cpp)
2135 {
2136 unsigned int tile_width_bytes =
2137 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2138
2139 *tile_width = tile_width_bytes / cpp;
2140 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2141 }
2142
2143 unsigned int
2144 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2145 uint32_t pixel_format, uint64_t fb_modifier)
2146 {
2147 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2148 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2149
2150 return ALIGN(height, tile_height);
2151 }
2152
2153 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2154 {
2155 unsigned int size = 0;
2156 int i;
2157
2158 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2159 size += rot_info->plane[i].width * rot_info->plane[i].height;
2160
2161 return size;
2162 }
2163
2164 static void
2165 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2166 const struct drm_framebuffer *fb,
2167 unsigned int rotation)
2168 {
2169 if (intel_rotation_90_or_270(rotation)) {
2170 *view = i915_ggtt_view_rotated;
2171 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2172 } else {
2173 *view = i915_ggtt_view_normal;
2174 }
2175 }
2176
2177 static void
2178 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2179 struct drm_framebuffer *fb)
2180 {
2181 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2182 unsigned int tile_size, tile_width, tile_height, cpp;
2183
2184 tile_size = intel_tile_size(dev_priv);
2185
2186 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2187 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2188 fb->modifier[0], cpp);
2189
2190 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2191 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2192
2193 if (info->pixel_format == DRM_FORMAT_NV12) {
2194 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2195 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2196 fb->modifier[1], cpp);
2197
2198 info->uv_offset = fb->offsets[1];
2199 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2200 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2201 }
2202 }
2203
2204 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2205 {
2206 if (INTEL_INFO(dev_priv)->gen >= 9)
2207 return 256 * 1024;
2208 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2209 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2210 return 128 * 1024;
2211 else if (INTEL_INFO(dev_priv)->gen >= 4)
2212 return 4 * 1024;
2213 else
2214 return 0;
2215 }
2216
2217 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2218 uint64_t fb_modifier)
2219 {
2220 switch (fb_modifier) {
2221 case DRM_FORMAT_MOD_NONE:
2222 return intel_linear_alignment(dev_priv);
2223 case I915_FORMAT_MOD_X_TILED:
2224 if (INTEL_INFO(dev_priv)->gen >= 9)
2225 return 256 * 1024;
2226 return 0;
2227 case I915_FORMAT_MOD_Y_TILED:
2228 case I915_FORMAT_MOD_Yf_TILED:
2229 return 1 * 1024 * 1024;
2230 default:
2231 MISSING_CASE(fb_modifier);
2232 return 0;
2233 }
2234 }
2235
2236 int
2237 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2238 unsigned int rotation)
2239 {
2240 struct drm_device *dev = fb->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2243 struct i915_ggtt_view view;
2244 u32 alignment;
2245 int ret;
2246
2247 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2248
2249 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2250
2251 intel_fill_fb_ggtt_view(&view, fb, rotation);
2252
2253 /* Note that the w/a also requires 64 PTE of padding following the
2254 * bo. We currently fill all unused PTE with the shadow page and so
2255 * we should always have valid PTE following the scanout preventing
2256 * the VT-d warning.
2257 */
2258 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2259 alignment = 256 * 1024;
2260
2261 /*
2262 * Global gtt pte registers are special registers which actually forward
2263 * writes to a chunk of system memory. Which means that there is no risk
2264 * that the register values disappear as soon as we call
2265 * intel_runtime_pm_put(), so it is correct to wrap only the
2266 * pin/unpin/fence and not more.
2267 */
2268 intel_runtime_pm_get(dev_priv);
2269
2270 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2271 &view);
2272 if (ret)
2273 goto err_pm;
2274
2275 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2276 * fence, whereas 965+ only requires a fence if using
2277 * framebuffer compression. For simplicity, we always install
2278 * a fence as the cost is not that onerous.
2279 */
2280 if (view.type == I915_GGTT_VIEW_NORMAL) {
2281 ret = i915_gem_object_get_fence(obj);
2282 if (ret == -EDEADLK) {
2283 /*
2284 * -EDEADLK means there are no free fences
2285 * no pending flips.
2286 *
2287 * This is propagated to atomic, but it uses
2288 * -EDEADLK to force a locking recovery, so
2289 * change the returned error to -EBUSY.
2290 */
2291 ret = -EBUSY;
2292 goto err_unpin;
2293 } else if (ret)
2294 goto err_unpin;
2295
2296 i915_gem_object_pin_fence(obj);
2297 }
2298
2299 intel_runtime_pm_put(dev_priv);
2300 return 0;
2301
2302 err_unpin:
2303 i915_gem_object_unpin_from_display_plane(obj, &view);
2304 err_pm:
2305 intel_runtime_pm_put(dev_priv);
2306 return ret;
2307 }
2308
2309 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2310 {
2311 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2312 struct i915_ggtt_view view;
2313
2314 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2315
2316 intel_fill_fb_ggtt_view(&view, fb, rotation);
2317
2318 if (view.type == I915_GGTT_VIEW_NORMAL)
2319 i915_gem_object_unpin_fence(obj);
2320
2321 i915_gem_object_unpin_from_display_plane(obj, &view);
2322 }
2323
2324 /*
2325 * Adjust the tile offset by moving the difference into
2326 * the x/y offsets.
2327 *
2328 * Input tile dimensions and pitch must already be
2329 * rotated to match x and y, and in pixel units.
2330 */
2331 static u32 intel_adjust_tile_offset(int *x, int *y,
2332 unsigned int tile_width,
2333 unsigned int tile_height,
2334 unsigned int tile_size,
2335 unsigned int pitch_tiles,
2336 u32 old_offset,
2337 u32 new_offset)
2338 {
2339 unsigned int tiles;
2340
2341 WARN_ON(old_offset & (tile_size - 1));
2342 WARN_ON(new_offset & (tile_size - 1));
2343 WARN_ON(new_offset > old_offset);
2344
2345 tiles = (old_offset - new_offset) / tile_size;
2346
2347 *y += tiles / pitch_tiles * tile_height;
2348 *x += tiles % pitch_tiles * tile_width;
2349
2350 return new_offset;
2351 }
2352
2353 /*
2354 * Computes the linear offset to the base tile and adjusts
2355 * x, y. bytes per pixel is assumed to be a power-of-two.
2356 *
2357 * In the 90/270 rotated case, x and y are assumed
2358 * to be already rotated to match the rotated GTT view, and
2359 * pitch is the tile_height aligned framebuffer height.
2360 */
2361 u32 intel_compute_tile_offset(int *x, int *y,
2362 const struct drm_framebuffer *fb, int plane,
2363 unsigned int pitch,
2364 unsigned int rotation)
2365 {
2366 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2367 uint64_t fb_modifier = fb->modifier[plane];
2368 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2369 u32 offset, offset_aligned, alignment;
2370
2371 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2372 if (alignment)
2373 alignment--;
2374
2375 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2376 unsigned int tile_size, tile_width, tile_height;
2377 unsigned int tile_rows, tiles, pitch_tiles;
2378
2379 tile_size = intel_tile_size(dev_priv);
2380 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2381 fb_modifier, cpp);
2382
2383 if (intel_rotation_90_or_270(rotation)) {
2384 pitch_tiles = pitch / tile_height;
2385 swap(tile_width, tile_height);
2386 } else {
2387 pitch_tiles = pitch / (tile_width * cpp);
2388 }
2389
2390 tile_rows = *y / tile_height;
2391 *y %= tile_height;
2392
2393 tiles = *x / tile_width;
2394 *x %= tile_width;
2395
2396 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2397 offset_aligned = offset & ~alignment;
2398
2399 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2400 tile_size, pitch_tiles,
2401 offset, offset_aligned);
2402 } else {
2403 offset = *y * pitch + *x * cpp;
2404 offset_aligned = offset & ~alignment;
2405
2406 *y = (offset & alignment) / pitch;
2407 *x = ((offset & alignment) - *y * pitch) / cpp;
2408 }
2409
2410 return offset_aligned;
2411 }
2412
2413 static int i9xx_format_to_fourcc(int format)
2414 {
2415 switch (format) {
2416 case DISPPLANE_8BPP:
2417 return DRM_FORMAT_C8;
2418 case DISPPLANE_BGRX555:
2419 return DRM_FORMAT_XRGB1555;
2420 case DISPPLANE_BGRX565:
2421 return DRM_FORMAT_RGB565;
2422 default:
2423 case DISPPLANE_BGRX888:
2424 return DRM_FORMAT_XRGB8888;
2425 case DISPPLANE_RGBX888:
2426 return DRM_FORMAT_XBGR8888;
2427 case DISPPLANE_BGRX101010:
2428 return DRM_FORMAT_XRGB2101010;
2429 case DISPPLANE_RGBX101010:
2430 return DRM_FORMAT_XBGR2101010;
2431 }
2432 }
2433
2434 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2435 {
2436 switch (format) {
2437 case PLANE_CTL_FORMAT_RGB_565:
2438 return DRM_FORMAT_RGB565;
2439 default:
2440 case PLANE_CTL_FORMAT_XRGB_8888:
2441 if (rgb_order) {
2442 if (alpha)
2443 return DRM_FORMAT_ABGR8888;
2444 else
2445 return DRM_FORMAT_XBGR8888;
2446 } else {
2447 if (alpha)
2448 return DRM_FORMAT_ARGB8888;
2449 else
2450 return DRM_FORMAT_XRGB8888;
2451 }
2452 case PLANE_CTL_FORMAT_XRGB_2101010:
2453 if (rgb_order)
2454 return DRM_FORMAT_XBGR2101010;
2455 else
2456 return DRM_FORMAT_XRGB2101010;
2457 }
2458 }
2459
2460 static bool
2461 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2462 struct intel_initial_plane_config *plane_config)
2463 {
2464 struct drm_device *dev = crtc->base.dev;
2465 struct drm_i915_private *dev_priv = to_i915(dev);
2466 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2467 struct drm_i915_gem_object *obj = NULL;
2468 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2469 struct drm_framebuffer *fb = &plane_config->fb->base;
2470 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2471 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2472 PAGE_SIZE);
2473
2474 size_aligned -= base_aligned;
2475
2476 if (plane_config->size == 0)
2477 return false;
2478
2479 /* If the FB is too big, just don't use it since fbdev is not very
2480 * important and we should probably use that space with FBC or other
2481 * features. */
2482 if (size_aligned * 2 > ggtt->stolen_usable_size)
2483 return false;
2484
2485 mutex_lock(&dev->struct_mutex);
2486
2487 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2488 base_aligned,
2489 base_aligned,
2490 size_aligned);
2491 if (!obj) {
2492 mutex_unlock(&dev->struct_mutex);
2493 return false;
2494 }
2495
2496 obj->tiling_mode = plane_config->tiling;
2497 if (obj->tiling_mode == I915_TILING_X)
2498 obj->stride = fb->pitches[0];
2499
2500 mode_cmd.pixel_format = fb->pixel_format;
2501 mode_cmd.width = fb->width;
2502 mode_cmd.height = fb->height;
2503 mode_cmd.pitches[0] = fb->pitches[0];
2504 mode_cmd.modifier[0] = fb->modifier[0];
2505 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2506
2507 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2508 &mode_cmd, obj)) {
2509 DRM_DEBUG_KMS("intel fb init failed\n");
2510 goto out_unref_obj;
2511 }
2512
2513 mutex_unlock(&dev->struct_mutex);
2514
2515 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2516 return true;
2517
2518 out_unref_obj:
2519 drm_gem_object_unreference(&obj->base);
2520 mutex_unlock(&dev->struct_mutex);
2521 return false;
2522 }
2523
2524 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2525 static void
2526 update_state_fb(struct drm_plane *plane)
2527 {
2528 if (plane->fb == plane->state->fb)
2529 return;
2530
2531 if (plane->state->fb)
2532 drm_framebuffer_unreference(plane->state->fb);
2533 plane->state->fb = plane->fb;
2534 if (plane->state->fb)
2535 drm_framebuffer_reference(plane->state->fb);
2536 }
2537
2538 static void
2539 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2540 struct intel_initial_plane_config *plane_config)
2541 {
2542 struct drm_device *dev = intel_crtc->base.dev;
2543 struct drm_i915_private *dev_priv = dev->dev_private;
2544 struct drm_crtc *c;
2545 struct intel_crtc *i;
2546 struct drm_i915_gem_object *obj;
2547 struct drm_plane *primary = intel_crtc->base.primary;
2548 struct drm_plane_state *plane_state = primary->state;
2549 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2550 struct intel_plane *intel_plane = to_intel_plane(primary);
2551 struct intel_plane_state *intel_state =
2552 to_intel_plane_state(plane_state);
2553 struct drm_framebuffer *fb;
2554
2555 if (!plane_config->fb)
2556 return;
2557
2558 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2559 fb = &plane_config->fb->base;
2560 goto valid_fb;
2561 }
2562
2563 kfree(plane_config->fb);
2564
2565 /*
2566 * Failed to alloc the obj, check to see if we should share
2567 * an fb with another CRTC instead
2568 */
2569 for_each_crtc(dev, c) {
2570 i = to_intel_crtc(c);
2571
2572 if (c == &intel_crtc->base)
2573 continue;
2574
2575 if (!i->active)
2576 continue;
2577
2578 fb = c->primary->fb;
2579 if (!fb)
2580 continue;
2581
2582 obj = intel_fb_obj(fb);
2583 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2584 drm_framebuffer_reference(fb);
2585 goto valid_fb;
2586 }
2587 }
2588
2589 /*
2590 * We've failed to reconstruct the BIOS FB. Current display state
2591 * indicates that the primary plane is visible, but has a NULL FB,
2592 * which will lead to problems later if we don't fix it up. The
2593 * simplest solution is to just disable the primary plane now and
2594 * pretend the BIOS never had it enabled.
2595 */
2596 to_intel_plane_state(plane_state)->visible = false;
2597 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2598 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2599 intel_plane->disable_plane(primary, &intel_crtc->base);
2600
2601 return;
2602
2603 valid_fb:
2604 plane_state->src_x = 0;
2605 plane_state->src_y = 0;
2606 plane_state->src_w = fb->width << 16;
2607 plane_state->src_h = fb->height << 16;
2608
2609 plane_state->crtc_x = 0;
2610 plane_state->crtc_y = 0;
2611 plane_state->crtc_w = fb->width;
2612 plane_state->crtc_h = fb->height;
2613
2614 intel_state->src.x1 = plane_state->src_x;
2615 intel_state->src.y1 = plane_state->src_y;
2616 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2617 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2618 intel_state->dst.x1 = plane_state->crtc_x;
2619 intel_state->dst.y1 = plane_state->crtc_y;
2620 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2621 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2622
2623 obj = intel_fb_obj(fb);
2624 if (obj->tiling_mode != I915_TILING_NONE)
2625 dev_priv->preserve_bios_swizzle = true;
2626
2627 drm_framebuffer_reference(fb);
2628 primary->fb = primary->state->fb = fb;
2629 primary->crtc = primary->state->crtc = &intel_crtc->base;
2630 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2631 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2632 }
2633
2634 static void i9xx_update_primary_plane(struct drm_plane *primary,
2635 const struct intel_crtc_state *crtc_state,
2636 const struct intel_plane_state *plane_state)
2637 {
2638 struct drm_device *dev = primary->dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2641 struct drm_framebuffer *fb = plane_state->base.fb;
2642 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2643 int plane = intel_crtc->plane;
2644 u32 linear_offset;
2645 u32 dspcntr;
2646 i915_reg_t reg = DSPCNTR(plane);
2647 unsigned int rotation = plane_state->base.rotation;
2648 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2649 int x = plane_state->src.x1 >> 16;
2650 int y = plane_state->src.y1 >> 16;
2651
2652 dspcntr = DISPPLANE_GAMMA_ENABLE;
2653
2654 dspcntr |= DISPLAY_PLANE_ENABLE;
2655
2656 if (INTEL_INFO(dev)->gen < 4) {
2657 if (intel_crtc->pipe == PIPE_B)
2658 dspcntr |= DISPPLANE_SEL_PIPE_B;
2659
2660 /* pipesrc and dspsize control the size that is scaled from,
2661 * which should always be the user's requested size.
2662 */
2663 I915_WRITE(DSPSIZE(plane),
2664 ((crtc_state->pipe_src_h - 1) << 16) |
2665 (crtc_state->pipe_src_w - 1));
2666 I915_WRITE(DSPPOS(plane), 0);
2667 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2668 I915_WRITE(PRIMSIZE(plane),
2669 ((crtc_state->pipe_src_h - 1) << 16) |
2670 (crtc_state->pipe_src_w - 1));
2671 I915_WRITE(PRIMPOS(plane), 0);
2672 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2673 }
2674
2675 switch (fb->pixel_format) {
2676 case DRM_FORMAT_C8:
2677 dspcntr |= DISPPLANE_8BPP;
2678 break;
2679 case DRM_FORMAT_XRGB1555:
2680 dspcntr |= DISPPLANE_BGRX555;
2681 break;
2682 case DRM_FORMAT_RGB565:
2683 dspcntr |= DISPPLANE_BGRX565;
2684 break;
2685 case DRM_FORMAT_XRGB8888:
2686 dspcntr |= DISPPLANE_BGRX888;
2687 break;
2688 case DRM_FORMAT_XBGR8888:
2689 dspcntr |= DISPPLANE_RGBX888;
2690 break;
2691 case DRM_FORMAT_XRGB2101010:
2692 dspcntr |= DISPPLANE_BGRX101010;
2693 break;
2694 case DRM_FORMAT_XBGR2101010:
2695 dspcntr |= DISPPLANE_RGBX101010;
2696 break;
2697 default:
2698 BUG();
2699 }
2700
2701 if (INTEL_INFO(dev)->gen >= 4 &&
2702 obj->tiling_mode != I915_TILING_NONE)
2703 dspcntr |= DISPPLANE_TILED;
2704
2705 if (IS_G4X(dev))
2706 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2707
2708 linear_offset = y * fb->pitches[0] + x * cpp;
2709
2710 if (INTEL_INFO(dev)->gen >= 4) {
2711 intel_crtc->dspaddr_offset =
2712 intel_compute_tile_offset(&x, &y, fb, 0,
2713 fb->pitches[0], rotation);
2714 linear_offset -= intel_crtc->dspaddr_offset;
2715 } else {
2716 intel_crtc->dspaddr_offset = linear_offset;
2717 }
2718
2719 if (rotation == BIT(DRM_ROTATE_180)) {
2720 dspcntr |= DISPPLANE_ROTATE_180;
2721
2722 x += (crtc_state->pipe_src_w - 1);
2723 y += (crtc_state->pipe_src_h - 1);
2724
2725 /* Finding the last pixel of the last line of the display
2726 data and adding to linear_offset*/
2727 linear_offset +=
2728 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2729 (crtc_state->pipe_src_w - 1) * cpp;
2730 }
2731
2732 intel_crtc->adjusted_x = x;
2733 intel_crtc->adjusted_y = y;
2734
2735 I915_WRITE(reg, dspcntr);
2736
2737 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2738 if (INTEL_INFO(dev)->gen >= 4) {
2739 I915_WRITE(DSPSURF(plane),
2740 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2741 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2742 I915_WRITE(DSPLINOFF(plane), linear_offset);
2743 } else
2744 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2745 POSTING_READ(reg);
2746 }
2747
2748 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2749 struct drm_crtc *crtc)
2750 {
2751 struct drm_device *dev = crtc->dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754 int plane = intel_crtc->plane;
2755
2756 I915_WRITE(DSPCNTR(plane), 0);
2757 if (INTEL_INFO(dev_priv)->gen >= 4)
2758 I915_WRITE(DSPSURF(plane), 0);
2759 else
2760 I915_WRITE(DSPADDR(plane), 0);
2761 POSTING_READ(DSPCNTR(plane));
2762 }
2763
2764 static void ironlake_update_primary_plane(struct drm_plane *primary,
2765 const struct intel_crtc_state *crtc_state,
2766 const struct intel_plane_state *plane_state)
2767 {
2768 struct drm_device *dev = primary->dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2771 struct drm_framebuffer *fb = plane_state->base.fb;
2772 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2773 int plane = intel_crtc->plane;
2774 u32 linear_offset;
2775 u32 dspcntr;
2776 i915_reg_t reg = DSPCNTR(plane);
2777 unsigned int rotation = plane_state->base.rotation;
2778 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2779 int x = plane_state->src.x1 >> 16;
2780 int y = plane_state->src.y1 >> 16;
2781
2782 dspcntr = DISPPLANE_GAMMA_ENABLE;
2783 dspcntr |= DISPLAY_PLANE_ENABLE;
2784
2785 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2786 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2787
2788 switch (fb->pixel_format) {
2789 case DRM_FORMAT_C8:
2790 dspcntr |= DISPPLANE_8BPP;
2791 break;
2792 case DRM_FORMAT_RGB565:
2793 dspcntr |= DISPPLANE_BGRX565;
2794 break;
2795 case DRM_FORMAT_XRGB8888:
2796 dspcntr |= DISPPLANE_BGRX888;
2797 break;
2798 case DRM_FORMAT_XBGR8888:
2799 dspcntr |= DISPPLANE_RGBX888;
2800 break;
2801 case DRM_FORMAT_XRGB2101010:
2802 dspcntr |= DISPPLANE_BGRX101010;
2803 break;
2804 case DRM_FORMAT_XBGR2101010:
2805 dspcntr |= DISPPLANE_RGBX101010;
2806 break;
2807 default:
2808 BUG();
2809 }
2810
2811 if (obj->tiling_mode != I915_TILING_NONE)
2812 dspcntr |= DISPPLANE_TILED;
2813
2814 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2815 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2816
2817 linear_offset = y * fb->pitches[0] + x * cpp;
2818 intel_crtc->dspaddr_offset =
2819 intel_compute_tile_offset(&x, &y, fb, 0,
2820 fb->pitches[0], rotation);
2821 linear_offset -= intel_crtc->dspaddr_offset;
2822 if (rotation == BIT(DRM_ROTATE_180)) {
2823 dspcntr |= DISPPLANE_ROTATE_180;
2824
2825 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2826 x += (crtc_state->pipe_src_w - 1);
2827 y += (crtc_state->pipe_src_h - 1);
2828
2829 /* Finding the last pixel of the last line of the display
2830 data and adding to linear_offset*/
2831 linear_offset +=
2832 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2833 (crtc_state->pipe_src_w - 1) * cpp;
2834 }
2835 }
2836
2837 intel_crtc->adjusted_x = x;
2838 intel_crtc->adjusted_y = y;
2839
2840 I915_WRITE(reg, dspcntr);
2841
2842 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2843 I915_WRITE(DSPSURF(plane),
2844 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2845 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2846 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2847 } else {
2848 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2849 I915_WRITE(DSPLINOFF(plane), linear_offset);
2850 }
2851 POSTING_READ(reg);
2852 }
2853
2854 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2855 uint64_t fb_modifier, uint32_t pixel_format)
2856 {
2857 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2858 return 64;
2859 } else {
2860 int cpp = drm_format_plane_cpp(pixel_format, 0);
2861
2862 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2863 }
2864 }
2865
2866 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2867 struct drm_i915_gem_object *obj,
2868 unsigned int plane)
2869 {
2870 struct i915_ggtt_view view;
2871 struct i915_vma *vma;
2872 u64 offset;
2873
2874 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2875 intel_plane->base.state->rotation);
2876
2877 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2878 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2879 view.type))
2880 return -1;
2881
2882 offset = vma->node.start;
2883
2884 if (plane == 1) {
2885 offset += vma->ggtt_view.params.rotated.uv_start_page *
2886 PAGE_SIZE;
2887 }
2888
2889 WARN_ON(upper_32_bits(offset));
2890
2891 return lower_32_bits(offset);
2892 }
2893
2894 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2895 {
2896 struct drm_device *dev = intel_crtc->base.dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898
2899 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2900 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2901 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2902 }
2903
2904 /*
2905 * This function detaches (aka. unbinds) unused scalers in hardware
2906 */
2907 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2908 {
2909 struct intel_crtc_scaler_state *scaler_state;
2910 int i;
2911
2912 scaler_state = &intel_crtc->config->scaler_state;
2913
2914 /* loop through and disable scalers that aren't in use */
2915 for (i = 0; i < intel_crtc->num_scalers; i++) {
2916 if (!scaler_state->scalers[i].in_use)
2917 skl_detach_scaler(intel_crtc, i);
2918 }
2919 }
2920
2921 u32 skl_plane_ctl_format(uint32_t pixel_format)
2922 {
2923 switch (pixel_format) {
2924 case DRM_FORMAT_C8:
2925 return PLANE_CTL_FORMAT_INDEXED;
2926 case DRM_FORMAT_RGB565:
2927 return PLANE_CTL_FORMAT_RGB_565;
2928 case DRM_FORMAT_XBGR8888:
2929 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2930 case DRM_FORMAT_XRGB8888:
2931 return PLANE_CTL_FORMAT_XRGB_8888;
2932 /*
2933 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2934 * to be already pre-multiplied. We need to add a knob (or a different
2935 * DRM_FORMAT) for user-space to configure that.
2936 */
2937 case DRM_FORMAT_ABGR8888:
2938 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2939 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2940 case DRM_FORMAT_ARGB8888:
2941 return PLANE_CTL_FORMAT_XRGB_8888 |
2942 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2943 case DRM_FORMAT_XRGB2101010:
2944 return PLANE_CTL_FORMAT_XRGB_2101010;
2945 case DRM_FORMAT_XBGR2101010:
2946 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2947 case DRM_FORMAT_YUYV:
2948 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2949 case DRM_FORMAT_YVYU:
2950 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2951 case DRM_FORMAT_UYVY:
2952 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2953 case DRM_FORMAT_VYUY:
2954 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2955 default:
2956 MISSING_CASE(pixel_format);
2957 }
2958
2959 return 0;
2960 }
2961
2962 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2963 {
2964 switch (fb_modifier) {
2965 case DRM_FORMAT_MOD_NONE:
2966 break;
2967 case I915_FORMAT_MOD_X_TILED:
2968 return PLANE_CTL_TILED_X;
2969 case I915_FORMAT_MOD_Y_TILED:
2970 return PLANE_CTL_TILED_Y;
2971 case I915_FORMAT_MOD_Yf_TILED:
2972 return PLANE_CTL_TILED_YF;
2973 default:
2974 MISSING_CASE(fb_modifier);
2975 }
2976
2977 return 0;
2978 }
2979
2980 u32 skl_plane_ctl_rotation(unsigned int rotation)
2981 {
2982 switch (rotation) {
2983 case BIT(DRM_ROTATE_0):
2984 break;
2985 /*
2986 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2987 * while i915 HW rotation is clockwise, thats why this swapping.
2988 */
2989 case BIT(DRM_ROTATE_90):
2990 return PLANE_CTL_ROTATE_270;
2991 case BIT(DRM_ROTATE_180):
2992 return PLANE_CTL_ROTATE_180;
2993 case BIT(DRM_ROTATE_270):
2994 return PLANE_CTL_ROTATE_90;
2995 default:
2996 MISSING_CASE(rotation);
2997 }
2998
2999 return 0;
3000 }
3001
3002 static void skylake_update_primary_plane(struct drm_plane *plane,
3003 const struct intel_crtc_state *crtc_state,
3004 const struct intel_plane_state *plane_state)
3005 {
3006 struct drm_device *dev = plane->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3009 struct drm_framebuffer *fb = plane_state->base.fb;
3010 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3011 int pipe = intel_crtc->pipe;
3012 u32 plane_ctl, stride_div, stride;
3013 u32 tile_height, plane_offset, plane_size;
3014 unsigned int rotation = plane_state->base.rotation;
3015 int x_offset, y_offset;
3016 u32 surf_addr;
3017 int scaler_id = plane_state->scaler_id;
3018 int src_x = plane_state->src.x1 >> 16;
3019 int src_y = plane_state->src.y1 >> 16;
3020 int src_w = drm_rect_width(&plane_state->src) >> 16;
3021 int src_h = drm_rect_height(&plane_state->src) >> 16;
3022 int dst_x = plane_state->dst.x1;
3023 int dst_y = plane_state->dst.y1;
3024 int dst_w = drm_rect_width(&plane_state->dst);
3025 int dst_h = drm_rect_height(&plane_state->dst);
3026
3027 plane_ctl = PLANE_CTL_ENABLE |
3028 PLANE_CTL_PIPE_GAMMA_ENABLE |
3029 PLANE_CTL_PIPE_CSC_ENABLE;
3030
3031 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3032 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3033 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3034 plane_ctl |= skl_plane_ctl_rotation(rotation);
3035
3036 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3037 fb->pixel_format);
3038 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3039
3040 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3041
3042 if (intel_rotation_90_or_270(rotation)) {
3043 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3044
3045 /* stride = Surface height in tiles */
3046 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3047 stride = DIV_ROUND_UP(fb->height, tile_height);
3048 x_offset = stride * tile_height - src_y - src_h;
3049 y_offset = src_x;
3050 plane_size = (src_w - 1) << 16 | (src_h - 1);
3051 } else {
3052 stride = fb->pitches[0] / stride_div;
3053 x_offset = src_x;
3054 y_offset = src_y;
3055 plane_size = (src_h - 1) << 16 | (src_w - 1);
3056 }
3057 plane_offset = y_offset << 16 | x_offset;
3058
3059 intel_crtc->adjusted_x = x_offset;
3060 intel_crtc->adjusted_y = y_offset;
3061
3062 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3063 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3064 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3065 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3066
3067 if (scaler_id >= 0) {
3068 uint32_t ps_ctrl = 0;
3069
3070 WARN_ON(!dst_w || !dst_h);
3071 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3072 crtc_state->scaler_state.scalers[scaler_id].mode;
3073 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3074 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3075 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3076 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3077 I915_WRITE(PLANE_POS(pipe, 0), 0);
3078 } else {
3079 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3080 }
3081
3082 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3083
3084 POSTING_READ(PLANE_SURF(pipe, 0));
3085 }
3086
3087 static void skylake_disable_primary_plane(struct drm_plane *primary,
3088 struct drm_crtc *crtc)
3089 {
3090 struct drm_device *dev = crtc->dev;
3091 struct drm_i915_private *dev_priv = dev->dev_private;
3092 int pipe = to_intel_crtc(crtc)->pipe;
3093
3094 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3095 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3096 POSTING_READ(PLANE_SURF(pipe, 0));
3097 }
3098
3099 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3100 static int
3101 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3102 int x, int y, enum mode_set_atomic state)
3103 {
3104 /* Support for kgdboc is disabled, this needs a major rework. */
3105 DRM_ERROR("legacy panic handler not supported any more.\n");
3106
3107 return -ENODEV;
3108 }
3109
3110 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3111 {
3112 struct drm_crtc *crtc;
3113
3114 for_each_crtc(dev_priv->dev, crtc) {
3115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116 enum plane plane = intel_crtc->plane;
3117
3118 intel_prepare_page_flip(dev_priv, plane);
3119 intel_finish_page_flip_plane(dev_priv, plane);
3120 }
3121 }
3122
3123 static void intel_update_primary_planes(struct drm_device *dev)
3124 {
3125 struct drm_crtc *crtc;
3126
3127 for_each_crtc(dev, crtc) {
3128 struct intel_plane *plane = to_intel_plane(crtc->primary);
3129 struct intel_plane_state *plane_state;
3130
3131 drm_modeset_lock_crtc(crtc, &plane->base);
3132 plane_state = to_intel_plane_state(plane->base.state);
3133
3134 if (plane_state->visible)
3135 plane->update_plane(&plane->base,
3136 to_intel_crtc_state(crtc->state),
3137 plane_state);
3138
3139 drm_modeset_unlock_crtc(crtc);
3140 }
3141 }
3142
3143 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3144 {
3145 /* no reset support for gen2 */
3146 if (IS_GEN2(dev_priv))
3147 return;
3148
3149 /* reset doesn't touch the display */
3150 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3151 return;
3152
3153 drm_modeset_lock_all(dev_priv->dev);
3154 /*
3155 * Disabling the crtcs gracefully seems nicer. Also the
3156 * g33 docs say we should at least disable all the planes.
3157 */
3158 intel_display_suspend(dev_priv->dev);
3159 }
3160
3161 void intel_finish_reset(struct drm_i915_private *dev_priv)
3162 {
3163 /*
3164 * Flips in the rings will be nuked by the reset,
3165 * so complete all pending flips so that user space
3166 * will get its events and not get stuck.
3167 */
3168 intel_complete_page_flips(dev_priv);
3169
3170 /* no reset support for gen2 */
3171 if (IS_GEN2(dev_priv))
3172 return;
3173
3174 /* reset doesn't touch the display */
3175 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3176 /*
3177 * Flips in the rings have been nuked by the reset,
3178 * so update the base address of all primary
3179 * planes to the the last fb to make sure we're
3180 * showing the correct fb after a reset.
3181 *
3182 * FIXME: Atomic will make this obsolete since we won't schedule
3183 * CS-based flips (which might get lost in gpu resets) any more.
3184 */
3185 intel_update_primary_planes(dev_priv->dev);
3186 return;
3187 }
3188
3189 /*
3190 * The display has been reset as well,
3191 * so need a full re-initialization.
3192 */
3193 intel_runtime_pm_disable_interrupts(dev_priv);
3194 intel_runtime_pm_enable_interrupts(dev_priv);
3195
3196 intel_modeset_init_hw(dev_priv->dev);
3197
3198 spin_lock_irq(&dev_priv->irq_lock);
3199 if (dev_priv->display.hpd_irq_setup)
3200 dev_priv->display.hpd_irq_setup(dev_priv);
3201 spin_unlock_irq(&dev_priv->irq_lock);
3202
3203 intel_display_resume(dev_priv->dev);
3204
3205 intel_hpd_init(dev_priv);
3206
3207 drm_modeset_unlock_all(dev_priv->dev);
3208 }
3209
3210 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3211 {
3212 struct drm_device *dev = crtc->dev;
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214 unsigned reset_counter;
3215 bool pending;
3216
3217 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3218 if (intel_crtc->reset_counter != reset_counter)
3219 return false;
3220
3221 spin_lock_irq(&dev->event_lock);
3222 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3223 spin_unlock_irq(&dev->event_lock);
3224
3225 return pending;
3226 }
3227
3228 static void intel_update_pipe_config(struct intel_crtc *crtc,
3229 struct intel_crtc_state *old_crtc_state)
3230 {
3231 struct drm_device *dev = crtc->base.dev;
3232 struct drm_i915_private *dev_priv = dev->dev_private;
3233 struct intel_crtc_state *pipe_config =
3234 to_intel_crtc_state(crtc->base.state);
3235
3236 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3237 crtc->base.mode = crtc->base.state->mode;
3238
3239 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3240 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3241 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3242
3243 /*
3244 * Update pipe size and adjust fitter if needed: the reason for this is
3245 * that in compute_mode_changes we check the native mode (not the pfit
3246 * mode) to see if we can flip rather than do a full mode set. In the
3247 * fastboot case, we'll flip, but if we don't update the pipesrc and
3248 * pfit state, we'll end up with a big fb scanned out into the wrong
3249 * sized surface.
3250 */
3251
3252 I915_WRITE(PIPESRC(crtc->pipe),
3253 ((pipe_config->pipe_src_w - 1) << 16) |
3254 (pipe_config->pipe_src_h - 1));
3255
3256 /* on skylake this is done by detaching scalers */
3257 if (INTEL_INFO(dev)->gen >= 9) {
3258 skl_detach_scalers(crtc);
3259
3260 if (pipe_config->pch_pfit.enabled)
3261 skylake_pfit_enable(crtc);
3262 } else if (HAS_PCH_SPLIT(dev)) {
3263 if (pipe_config->pch_pfit.enabled)
3264 ironlake_pfit_enable(crtc);
3265 else if (old_crtc_state->pch_pfit.enabled)
3266 ironlake_pfit_disable(crtc, true);
3267 }
3268 }
3269
3270 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3271 {
3272 struct drm_device *dev = crtc->dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275 int pipe = intel_crtc->pipe;
3276 i915_reg_t reg;
3277 u32 temp;
3278
3279 /* enable normal train */
3280 reg = FDI_TX_CTL(pipe);
3281 temp = I915_READ(reg);
3282 if (IS_IVYBRIDGE(dev)) {
3283 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3284 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3285 } else {
3286 temp &= ~FDI_LINK_TRAIN_NONE;
3287 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3288 }
3289 I915_WRITE(reg, temp);
3290
3291 reg = FDI_RX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 if (HAS_PCH_CPT(dev)) {
3294 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3295 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3296 } else {
3297 temp &= ~FDI_LINK_TRAIN_NONE;
3298 temp |= FDI_LINK_TRAIN_NONE;
3299 }
3300 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3301
3302 /* wait one idle pattern time */
3303 POSTING_READ(reg);
3304 udelay(1000);
3305
3306 /* IVB wants error correction enabled */
3307 if (IS_IVYBRIDGE(dev))
3308 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3309 FDI_FE_ERRC_ENABLE);
3310 }
3311
3312 /* The FDI link training functions for ILK/Ibexpeak. */
3313 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3314 {
3315 struct drm_device *dev = crtc->dev;
3316 struct drm_i915_private *dev_priv = dev->dev_private;
3317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3318 int pipe = intel_crtc->pipe;
3319 i915_reg_t reg;
3320 u32 temp, tries;
3321
3322 /* FDI needs bits from pipe first */
3323 assert_pipe_enabled(dev_priv, pipe);
3324
3325 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3326 for train result */
3327 reg = FDI_RX_IMR(pipe);
3328 temp = I915_READ(reg);
3329 temp &= ~FDI_RX_SYMBOL_LOCK;
3330 temp &= ~FDI_RX_BIT_LOCK;
3331 I915_WRITE(reg, temp);
3332 I915_READ(reg);
3333 udelay(150);
3334
3335 /* enable CPU FDI TX and PCH FDI RX */
3336 reg = FDI_TX_CTL(pipe);
3337 temp = I915_READ(reg);
3338 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3339 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3340 temp &= ~FDI_LINK_TRAIN_NONE;
3341 temp |= FDI_LINK_TRAIN_PATTERN_1;
3342 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3343
3344 reg = FDI_RX_CTL(pipe);
3345 temp = I915_READ(reg);
3346 temp &= ~FDI_LINK_TRAIN_NONE;
3347 temp |= FDI_LINK_TRAIN_PATTERN_1;
3348 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3349
3350 POSTING_READ(reg);
3351 udelay(150);
3352
3353 /* Ironlake workaround, enable clock pointer after FDI enable*/
3354 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3355 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3356 FDI_RX_PHASE_SYNC_POINTER_EN);
3357
3358 reg = FDI_RX_IIR(pipe);
3359 for (tries = 0; tries < 5; tries++) {
3360 temp = I915_READ(reg);
3361 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3362
3363 if ((temp & FDI_RX_BIT_LOCK)) {
3364 DRM_DEBUG_KMS("FDI train 1 done.\n");
3365 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3366 break;
3367 }
3368 }
3369 if (tries == 5)
3370 DRM_ERROR("FDI train 1 fail!\n");
3371
3372 /* Train 2 */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_PATTERN_2;
3377 I915_WRITE(reg, temp);
3378
3379 reg = FDI_RX_CTL(pipe);
3380 temp = I915_READ(reg);
3381 temp &= ~FDI_LINK_TRAIN_NONE;
3382 temp |= FDI_LINK_TRAIN_PATTERN_2;
3383 I915_WRITE(reg, temp);
3384
3385 POSTING_READ(reg);
3386 udelay(150);
3387
3388 reg = FDI_RX_IIR(pipe);
3389 for (tries = 0; tries < 5; tries++) {
3390 temp = I915_READ(reg);
3391 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3392
3393 if (temp & FDI_RX_SYMBOL_LOCK) {
3394 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3395 DRM_DEBUG_KMS("FDI train 2 done.\n");
3396 break;
3397 }
3398 }
3399 if (tries == 5)
3400 DRM_ERROR("FDI train 2 fail!\n");
3401
3402 DRM_DEBUG_KMS("FDI train done\n");
3403
3404 }
3405
3406 static const int snb_b_fdi_train_param[] = {
3407 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3408 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3409 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3410 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3411 };
3412
3413 /* The FDI link training functions for SNB/Cougarpoint. */
3414 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3415 {
3416 struct drm_device *dev = crtc->dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3419 int pipe = intel_crtc->pipe;
3420 i915_reg_t reg;
3421 u32 temp, i, retry;
3422
3423 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3424 for train result */
3425 reg = FDI_RX_IMR(pipe);
3426 temp = I915_READ(reg);
3427 temp &= ~FDI_RX_SYMBOL_LOCK;
3428 temp &= ~FDI_RX_BIT_LOCK;
3429 I915_WRITE(reg, temp);
3430
3431 POSTING_READ(reg);
3432 udelay(150);
3433
3434 /* enable CPU FDI TX and PCH FDI RX */
3435 reg = FDI_TX_CTL(pipe);
3436 temp = I915_READ(reg);
3437 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3438 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_1;
3441 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3442 /* SNB-B */
3443 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3444 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3445
3446 I915_WRITE(FDI_RX_MISC(pipe),
3447 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3448
3449 reg = FDI_RX_CTL(pipe);
3450 temp = I915_READ(reg);
3451 if (HAS_PCH_CPT(dev)) {
3452 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3453 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3454 } else {
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_1;
3457 }
3458 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3459
3460 POSTING_READ(reg);
3461 udelay(150);
3462
3463 for (i = 0; i < 4; i++) {
3464 reg = FDI_TX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3467 temp |= snb_b_fdi_train_param[i];
3468 I915_WRITE(reg, temp);
3469
3470 POSTING_READ(reg);
3471 udelay(500);
3472
3473 for (retry = 0; retry < 5; retry++) {
3474 reg = FDI_RX_IIR(pipe);
3475 temp = I915_READ(reg);
3476 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3477 if (temp & FDI_RX_BIT_LOCK) {
3478 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3479 DRM_DEBUG_KMS("FDI train 1 done.\n");
3480 break;
3481 }
3482 udelay(50);
3483 }
3484 if (retry < 5)
3485 break;
3486 }
3487 if (i == 4)
3488 DRM_ERROR("FDI train 1 fail!\n");
3489
3490 /* Train 2 */
3491 reg = FDI_TX_CTL(pipe);
3492 temp = I915_READ(reg);
3493 temp &= ~FDI_LINK_TRAIN_NONE;
3494 temp |= FDI_LINK_TRAIN_PATTERN_2;
3495 if (IS_GEN6(dev)) {
3496 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3497 /* SNB-B */
3498 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3499 }
3500 I915_WRITE(reg, temp);
3501
3502 reg = FDI_RX_CTL(pipe);
3503 temp = I915_READ(reg);
3504 if (HAS_PCH_CPT(dev)) {
3505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3506 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3507 } else {
3508 temp &= ~FDI_LINK_TRAIN_NONE;
3509 temp |= FDI_LINK_TRAIN_PATTERN_2;
3510 }
3511 I915_WRITE(reg, temp);
3512
3513 POSTING_READ(reg);
3514 udelay(150);
3515
3516 for (i = 0; i < 4; i++) {
3517 reg = FDI_TX_CTL(pipe);
3518 temp = I915_READ(reg);
3519 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3520 temp |= snb_b_fdi_train_param[i];
3521 I915_WRITE(reg, temp);
3522
3523 POSTING_READ(reg);
3524 udelay(500);
3525
3526 for (retry = 0; retry < 5; retry++) {
3527 reg = FDI_RX_IIR(pipe);
3528 temp = I915_READ(reg);
3529 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3530 if (temp & FDI_RX_SYMBOL_LOCK) {
3531 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3532 DRM_DEBUG_KMS("FDI train 2 done.\n");
3533 break;
3534 }
3535 udelay(50);
3536 }
3537 if (retry < 5)
3538 break;
3539 }
3540 if (i == 4)
3541 DRM_ERROR("FDI train 2 fail!\n");
3542
3543 DRM_DEBUG_KMS("FDI train done.\n");
3544 }
3545
3546 /* Manual link training for Ivy Bridge A0 parts */
3547 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3548 {
3549 struct drm_device *dev = crtc->dev;
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552 int pipe = intel_crtc->pipe;
3553 i915_reg_t reg;
3554 u32 temp, i, j;
3555
3556 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3557 for train result */
3558 reg = FDI_RX_IMR(pipe);
3559 temp = I915_READ(reg);
3560 temp &= ~FDI_RX_SYMBOL_LOCK;
3561 temp &= ~FDI_RX_BIT_LOCK;
3562 I915_WRITE(reg, temp);
3563
3564 POSTING_READ(reg);
3565 udelay(150);
3566
3567 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3568 I915_READ(FDI_RX_IIR(pipe)));
3569
3570 /* Try each vswing and preemphasis setting twice before moving on */
3571 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3572 /* disable first in case we need to retry */
3573 reg = FDI_TX_CTL(pipe);
3574 temp = I915_READ(reg);
3575 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3576 temp &= ~FDI_TX_ENABLE;
3577 I915_WRITE(reg, temp);
3578
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 temp &= ~FDI_LINK_TRAIN_AUTO;
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp &= ~FDI_RX_ENABLE;
3584 I915_WRITE(reg, temp);
3585
3586 /* enable CPU FDI TX and PCH FDI RX */
3587 reg = FDI_TX_CTL(pipe);
3588 temp = I915_READ(reg);
3589 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3590 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3591 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[j/2];
3594 temp |= FDI_COMPOSITE_SYNC;
3595 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3596
3597 I915_WRITE(FDI_RX_MISC(pipe),
3598 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3599
3600 reg = FDI_RX_CTL(pipe);
3601 temp = I915_READ(reg);
3602 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3603 temp |= FDI_COMPOSITE_SYNC;
3604 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3605
3606 POSTING_READ(reg);
3607 udelay(1); /* should be 0.5us */
3608
3609 for (i = 0; i < 4; i++) {
3610 reg = FDI_RX_IIR(pipe);
3611 temp = I915_READ(reg);
3612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3613
3614 if (temp & FDI_RX_BIT_LOCK ||
3615 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3616 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3617 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3618 i);
3619 break;
3620 }
3621 udelay(1); /* should be 0.5us */
3622 }
3623 if (i == 4) {
3624 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3625 continue;
3626 }
3627
3628 /* Train 2 */
3629 reg = FDI_TX_CTL(pipe);
3630 temp = I915_READ(reg);
3631 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3632 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3633 I915_WRITE(reg, temp);
3634
3635 reg = FDI_RX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3638 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3639 I915_WRITE(reg, temp);
3640
3641 POSTING_READ(reg);
3642 udelay(2); /* should be 1.5us */
3643
3644 for (i = 0; i < 4; i++) {
3645 reg = FDI_RX_IIR(pipe);
3646 temp = I915_READ(reg);
3647 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3648
3649 if (temp & FDI_RX_SYMBOL_LOCK ||
3650 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3651 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3652 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3653 i);
3654 goto train_done;
3655 }
3656 udelay(2); /* should be 1.5us */
3657 }
3658 if (i == 4)
3659 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3660 }
3661
3662 train_done:
3663 DRM_DEBUG_KMS("FDI train done.\n");
3664 }
3665
3666 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3667 {
3668 struct drm_device *dev = intel_crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 int pipe = intel_crtc->pipe;
3671 i915_reg_t reg;
3672 u32 temp;
3673
3674 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3675 reg = FDI_RX_CTL(pipe);
3676 temp = I915_READ(reg);
3677 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3678 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3679 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3680 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3681
3682 POSTING_READ(reg);
3683 udelay(200);
3684
3685 /* Switch from Rawclk to PCDclk */
3686 temp = I915_READ(reg);
3687 I915_WRITE(reg, temp | FDI_PCDCLK);
3688
3689 POSTING_READ(reg);
3690 udelay(200);
3691
3692 /* Enable CPU FDI TX PLL, always on for Ironlake */
3693 reg = FDI_TX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3696 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3697
3698 POSTING_READ(reg);
3699 udelay(100);
3700 }
3701 }
3702
3703 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3704 {
3705 struct drm_device *dev = intel_crtc->base.dev;
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707 int pipe = intel_crtc->pipe;
3708 i915_reg_t reg;
3709 u32 temp;
3710
3711 /* Switch from PCDclk to Rawclk */
3712 reg = FDI_RX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3715
3716 /* Disable CPU FDI TX PLL */
3717 reg = FDI_TX_CTL(pipe);
3718 temp = I915_READ(reg);
3719 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3720
3721 POSTING_READ(reg);
3722 udelay(100);
3723
3724 reg = FDI_RX_CTL(pipe);
3725 temp = I915_READ(reg);
3726 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3727
3728 /* Wait for the clocks to turn off. */
3729 POSTING_READ(reg);
3730 udelay(100);
3731 }
3732
3733 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3734 {
3735 struct drm_device *dev = crtc->dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3738 int pipe = intel_crtc->pipe;
3739 i915_reg_t reg;
3740 u32 temp;
3741
3742 /* disable CPU FDI tx and PCH FDI rx */
3743 reg = FDI_TX_CTL(pipe);
3744 temp = I915_READ(reg);
3745 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3746 POSTING_READ(reg);
3747
3748 reg = FDI_RX_CTL(pipe);
3749 temp = I915_READ(reg);
3750 temp &= ~(0x7 << 16);
3751 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3752 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3753
3754 POSTING_READ(reg);
3755 udelay(100);
3756
3757 /* Ironlake workaround, disable clock pointer after downing FDI */
3758 if (HAS_PCH_IBX(dev))
3759 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3760
3761 /* still set train pattern 1 */
3762 reg = FDI_TX_CTL(pipe);
3763 temp = I915_READ(reg);
3764 temp &= ~FDI_LINK_TRAIN_NONE;
3765 temp |= FDI_LINK_TRAIN_PATTERN_1;
3766 I915_WRITE(reg, temp);
3767
3768 reg = FDI_RX_CTL(pipe);
3769 temp = I915_READ(reg);
3770 if (HAS_PCH_CPT(dev)) {
3771 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3772 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3773 } else {
3774 temp &= ~FDI_LINK_TRAIN_NONE;
3775 temp |= FDI_LINK_TRAIN_PATTERN_1;
3776 }
3777 /* BPC in FDI rx is consistent with that in PIPECONF */
3778 temp &= ~(0x07 << 16);
3779 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3780 I915_WRITE(reg, temp);
3781
3782 POSTING_READ(reg);
3783 udelay(100);
3784 }
3785
3786 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3787 {
3788 struct intel_crtc *crtc;
3789
3790 /* Note that we don't need to be called with mode_config.lock here
3791 * as our list of CRTC objects is static for the lifetime of the
3792 * device and so cannot disappear as we iterate. Similarly, we can
3793 * happily treat the predicates as racy, atomic checks as userspace
3794 * cannot claim and pin a new fb without at least acquring the
3795 * struct_mutex and so serialising with us.
3796 */
3797 for_each_intel_crtc(dev, crtc) {
3798 if (atomic_read(&crtc->unpin_work_count) == 0)
3799 continue;
3800
3801 if (crtc->unpin_work)
3802 intel_wait_for_vblank(dev, crtc->pipe);
3803
3804 return true;
3805 }
3806
3807 return false;
3808 }
3809
3810 static void page_flip_completed(struct intel_crtc *intel_crtc)
3811 {
3812 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3813 struct intel_unpin_work *work = intel_crtc->unpin_work;
3814
3815 /* ensure that the unpin work is consistent wrt ->pending. */
3816 smp_rmb();
3817 intel_crtc->unpin_work = NULL;
3818
3819 if (work->event)
3820 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3821
3822 drm_crtc_vblank_put(&intel_crtc->base);
3823
3824 wake_up_all(&dev_priv->pending_flip_queue);
3825 queue_work(dev_priv->wq, &work->work);
3826
3827 trace_i915_flip_complete(intel_crtc->plane,
3828 work->pending_flip_obj);
3829 }
3830
3831 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3832 {
3833 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 long ret;
3836
3837 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3838
3839 ret = wait_event_interruptible_timeout(
3840 dev_priv->pending_flip_queue,
3841 !intel_crtc_has_pending_flip(crtc),
3842 60*HZ);
3843
3844 if (ret < 0)
3845 return ret;
3846
3847 if (ret == 0) {
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849
3850 spin_lock_irq(&dev->event_lock);
3851 if (intel_crtc->unpin_work) {
3852 WARN_ONCE(1, "Removing stuck page flip\n");
3853 page_flip_completed(intel_crtc);
3854 }
3855 spin_unlock_irq(&dev->event_lock);
3856 }
3857
3858 return 0;
3859 }
3860
3861 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3862 {
3863 u32 temp;
3864
3865 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3866
3867 mutex_lock(&dev_priv->sb_lock);
3868
3869 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3870 temp |= SBI_SSCCTL_DISABLE;
3871 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3872
3873 mutex_unlock(&dev_priv->sb_lock);
3874 }
3875
3876 /* Program iCLKIP clock to the desired frequency */
3877 static void lpt_program_iclkip(struct drm_crtc *crtc)
3878 {
3879 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3880 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3881 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3882 u32 temp;
3883
3884 lpt_disable_iclkip(dev_priv);
3885
3886 /* The iCLK virtual clock root frequency is in MHz,
3887 * but the adjusted_mode->crtc_clock in in KHz. To get the
3888 * divisors, it is necessary to divide one by another, so we
3889 * convert the virtual clock precision to KHz here for higher
3890 * precision.
3891 */
3892 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3893 u32 iclk_virtual_root_freq = 172800 * 1000;
3894 u32 iclk_pi_range = 64;
3895 u32 desired_divisor;
3896
3897 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3898 clock << auxdiv);
3899 divsel = (desired_divisor / iclk_pi_range) - 2;
3900 phaseinc = desired_divisor % iclk_pi_range;
3901
3902 /*
3903 * Near 20MHz is a corner case which is
3904 * out of range for the 7-bit divisor
3905 */
3906 if (divsel <= 0x7f)
3907 break;
3908 }
3909
3910 /* This should not happen with any sane values */
3911 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3912 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3913 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3914 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3915
3916 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3917 clock,
3918 auxdiv,
3919 divsel,
3920 phasedir,
3921 phaseinc);
3922
3923 mutex_lock(&dev_priv->sb_lock);
3924
3925 /* Program SSCDIVINTPHASE6 */
3926 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3927 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3928 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3929 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3930 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3931 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3932 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3933 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3934
3935 /* Program SSCAUXDIV */
3936 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3937 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3938 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3939 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3940
3941 /* Enable modulator and associated divider */
3942 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3943 temp &= ~SBI_SSCCTL_DISABLE;
3944 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3945
3946 mutex_unlock(&dev_priv->sb_lock);
3947
3948 /* Wait for initialization time */
3949 udelay(24);
3950
3951 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3952 }
3953
3954 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3955 {
3956 u32 divsel, phaseinc, auxdiv;
3957 u32 iclk_virtual_root_freq = 172800 * 1000;
3958 u32 iclk_pi_range = 64;
3959 u32 desired_divisor;
3960 u32 temp;
3961
3962 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3963 return 0;
3964
3965 mutex_lock(&dev_priv->sb_lock);
3966
3967 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3968 if (temp & SBI_SSCCTL_DISABLE) {
3969 mutex_unlock(&dev_priv->sb_lock);
3970 return 0;
3971 }
3972
3973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3974 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3975 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3976 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3977 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3978
3979 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3980 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3981 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3982
3983 mutex_unlock(&dev_priv->sb_lock);
3984
3985 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3986
3987 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3988 desired_divisor << auxdiv);
3989 }
3990
3991 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3992 enum pipe pch_transcoder)
3993 {
3994 struct drm_device *dev = crtc->base.dev;
3995 struct drm_i915_private *dev_priv = dev->dev_private;
3996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3997
3998 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3999 I915_READ(HTOTAL(cpu_transcoder)));
4000 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4001 I915_READ(HBLANK(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4003 I915_READ(HSYNC(cpu_transcoder)));
4004
4005 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4006 I915_READ(VTOTAL(cpu_transcoder)));
4007 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4008 I915_READ(VBLANK(cpu_transcoder)));
4009 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4010 I915_READ(VSYNC(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4012 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4013 }
4014
4015 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4016 {
4017 struct drm_i915_private *dev_priv = dev->dev_private;
4018 uint32_t temp;
4019
4020 temp = I915_READ(SOUTH_CHICKEN1);
4021 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4022 return;
4023
4024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4025 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4026
4027 temp &= ~FDI_BC_BIFURCATION_SELECT;
4028 if (enable)
4029 temp |= FDI_BC_BIFURCATION_SELECT;
4030
4031 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4032 I915_WRITE(SOUTH_CHICKEN1, temp);
4033 POSTING_READ(SOUTH_CHICKEN1);
4034 }
4035
4036 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4037 {
4038 struct drm_device *dev = intel_crtc->base.dev;
4039
4040 switch (intel_crtc->pipe) {
4041 case PIPE_A:
4042 break;
4043 case PIPE_B:
4044 if (intel_crtc->config->fdi_lanes > 2)
4045 cpt_set_fdi_bc_bifurcation(dev, false);
4046 else
4047 cpt_set_fdi_bc_bifurcation(dev, true);
4048
4049 break;
4050 case PIPE_C:
4051 cpt_set_fdi_bc_bifurcation(dev, true);
4052
4053 break;
4054 default:
4055 BUG();
4056 }
4057 }
4058
4059 /* Return which DP Port should be selected for Transcoder DP control */
4060 static enum port
4061 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4062 {
4063 struct drm_device *dev = crtc->dev;
4064 struct intel_encoder *encoder;
4065
4066 for_each_encoder_on_crtc(dev, crtc, encoder) {
4067 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4068 encoder->type == INTEL_OUTPUT_EDP)
4069 return enc_to_dig_port(&encoder->base)->port;
4070 }
4071
4072 return -1;
4073 }
4074
4075 /*
4076 * Enable PCH resources required for PCH ports:
4077 * - PCH PLLs
4078 * - FDI training & RX/TX
4079 * - update transcoder timings
4080 * - DP transcoding bits
4081 * - transcoder
4082 */
4083 static void ironlake_pch_enable(struct drm_crtc *crtc)
4084 {
4085 struct drm_device *dev = crtc->dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088 int pipe = intel_crtc->pipe;
4089 u32 temp;
4090
4091 assert_pch_transcoder_disabled(dev_priv, pipe);
4092
4093 if (IS_IVYBRIDGE(dev))
4094 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4095
4096 /* Write the TU size bits before fdi link training, so that error
4097 * detection works. */
4098 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4099 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4100
4101 /* For PCH output, training FDI link */
4102 dev_priv->display.fdi_link_train(crtc);
4103
4104 /* We need to program the right clock selection before writing the pixel
4105 * mutliplier into the DPLL. */
4106 if (HAS_PCH_CPT(dev)) {
4107 u32 sel;
4108
4109 temp = I915_READ(PCH_DPLL_SEL);
4110 temp |= TRANS_DPLL_ENABLE(pipe);
4111 sel = TRANS_DPLLB_SEL(pipe);
4112 if (intel_crtc->config->shared_dpll ==
4113 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4114 temp |= sel;
4115 else
4116 temp &= ~sel;
4117 I915_WRITE(PCH_DPLL_SEL, temp);
4118 }
4119
4120 /* XXX: pch pll's can be enabled any time before we enable the PCH
4121 * transcoder, and we actually should do this to not upset any PCH
4122 * transcoder that already use the clock when we share it.
4123 *
4124 * Note that enable_shared_dpll tries to do the right thing, but
4125 * get_shared_dpll unconditionally resets the pll - we need that to have
4126 * the right LVDS enable sequence. */
4127 intel_enable_shared_dpll(intel_crtc);
4128
4129 /* set transcoder timing, panel must allow it */
4130 assert_panel_unlocked(dev_priv, pipe);
4131 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4132
4133 intel_fdi_normal_train(crtc);
4134
4135 /* For PCH DP, enable TRANS_DP_CTL */
4136 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4137 const struct drm_display_mode *adjusted_mode =
4138 &intel_crtc->config->base.adjusted_mode;
4139 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4140 i915_reg_t reg = TRANS_DP_CTL(pipe);
4141 temp = I915_READ(reg);
4142 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4143 TRANS_DP_SYNC_MASK |
4144 TRANS_DP_BPC_MASK);
4145 temp |= TRANS_DP_OUTPUT_ENABLE;
4146 temp |= bpc << 9; /* same format but at 11:9 */
4147
4148 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4149 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4150 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4151 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4152
4153 switch (intel_trans_dp_port_sel(crtc)) {
4154 case PORT_B:
4155 temp |= TRANS_DP_PORT_SEL_B;
4156 break;
4157 case PORT_C:
4158 temp |= TRANS_DP_PORT_SEL_C;
4159 break;
4160 case PORT_D:
4161 temp |= TRANS_DP_PORT_SEL_D;
4162 break;
4163 default:
4164 BUG();
4165 }
4166
4167 I915_WRITE(reg, temp);
4168 }
4169
4170 ironlake_enable_pch_transcoder(dev_priv, pipe);
4171 }
4172
4173 static void lpt_pch_enable(struct drm_crtc *crtc)
4174 {
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4179
4180 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4181
4182 lpt_program_iclkip(crtc);
4183
4184 /* Set transcoder timing. */
4185 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4186
4187 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4188 }
4189
4190 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4191 {
4192 struct drm_i915_private *dev_priv = dev->dev_private;
4193 i915_reg_t dslreg = PIPEDSL(pipe);
4194 u32 temp;
4195
4196 temp = I915_READ(dslreg);
4197 udelay(500);
4198 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4199 if (wait_for(I915_READ(dslreg) != temp, 5))
4200 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4201 }
4202 }
4203
4204 static int
4205 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4206 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4207 int src_w, int src_h, int dst_w, int dst_h)
4208 {
4209 struct intel_crtc_scaler_state *scaler_state =
4210 &crtc_state->scaler_state;
4211 struct intel_crtc *intel_crtc =
4212 to_intel_crtc(crtc_state->base.crtc);
4213 int need_scaling;
4214
4215 need_scaling = intel_rotation_90_or_270(rotation) ?
4216 (src_h != dst_w || src_w != dst_h):
4217 (src_w != dst_w || src_h != dst_h);
4218
4219 /*
4220 * if plane is being disabled or scaler is no more required or force detach
4221 * - free scaler binded to this plane/crtc
4222 * - in order to do this, update crtc->scaler_usage
4223 *
4224 * Here scaler state in crtc_state is set free so that
4225 * scaler can be assigned to other user. Actual register
4226 * update to free the scaler is done in plane/panel-fit programming.
4227 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4228 */
4229 if (force_detach || !need_scaling) {
4230 if (*scaler_id >= 0) {
4231 scaler_state->scaler_users &= ~(1 << scaler_user);
4232 scaler_state->scalers[*scaler_id].in_use = 0;
4233
4234 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4235 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4236 intel_crtc->pipe, scaler_user, *scaler_id,
4237 scaler_state->scaler_users);
4238 *scaler_id = -1;
4239 }
4240 return 0;
4241 }
4242
4243 /* range checks */
4244 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4245 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4246
4247 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4248 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4249 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4250 "size is out of scaler range\n",
4251 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4252 return -EINVAL;
4253 }
4254
4255 /* mark this plane as a scaler user in crtc_state */
4256 scaler_state->scaler_users |= (1 << scaler_user);
4257 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4258 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4259 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4260 scaler_state->scaler_users);
4261
4262 return 0;
4263 }
4264
4265 /**
4266 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4267 *
4268 * @state: crtc's scaler state
4269 *
4270 * Return
4271 * 0 - scaler_usage updated successfully
4272 * error - requested scaling cannot be supported or other error condition
4273 */
4274 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4275 {
4276 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4277 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4278
4279 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4280 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4281
4282 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4283 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4284 state->pipe_src_w, state->pipe_src_h,
4285 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4286 }
4287
4288 /**
4289 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4290 *
4291 * @state: crtc's scaler state
4292 * @plane_state: atomic plane state to update
4293 *
4294 * Return
4295 * 0 - scaler_usage updated successfully
4296 * error - requested scaling cannot be supported or other error condition
4297 */
4298 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4299 struct intel_plane_state *plane_state)
4300 {
4301
4302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4303 struct intel_plane *intel_plane =
4304 to_intel_plane(plane_state->base.plane);
4305 struct drm_framebuffer *fb = plane_state->base.fb;
4306 int ret;
4307
4308 bool force_detach = !fb || !plane_state->visible;
4309
4310 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4311 intel_plane->base.base.id, intel_crtc->pipe,
4312 drm_plane_index(&intel_plane->base));
4313
4314 ret = skl_update_scaler(crtc_state, force_detach,
4315 drm_plane_index(&intel_plane->base),
4316 &plane_state->scaler_id,
4317 plane_state->base.rotation,
4318 drm_rect_width(&plane_state->src) >> 16,
4319 drm_rect_height(&plane_state->src) >> 16,
4320 drm_rect_width(&plane_state->dst),
4321 drm_rect_height(&plane_state->dst));
4322
4323 if (ret || plane_state->scaler_id < 0)
4324 return ret;
4325
4326 /* check colorkey */
4327 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4328 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4329 intel_plane->base.base.id);
4330 return -EINVAL;
4331 }
4332
4333 /* Check src format */
4334 switch (fb->pixel_format) {
4335 case DRM_FORMAT_RGB565:
4336 case DRM_FORMAT_XBGR8888:
4337 case DRM_FORMAT_XRGB8888:
4338 case DRM_FORMAT_ABGR8888:
4339 case DRM_FORMAT_ARGB8888:
4340 case DRM_FORMAT_XRGB2101010:
4341 case DRM_FORMAT_XBGR2101010:
4342 case DRM_FORMAT_YUYV:
4343 case DRM_FORMAT_YVYU:
4344 case DRM_FORMAT_UYVY:
4345 case DRM_FORMAT_VYUY:
4346 break;
4347 default:
4348 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4349 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4350 return -EINVAL;
4351 }
4352
4353 return 0;
4354 }
4355
4356 static void skylake_scaler_disable(struct intel_crtc *crtc)
4357 {
4358 int i;
4359
4360 for (i = 0; i < crtc->num_scalers; i++)
4361 skl_detach_scaler(crtc, i);
4362 }
4363
4364 static void skylake_pfit_enable(struct intel_crtc *crtc)
4365 {
4366 struct drm_device *dev = crtc->base.dev;
4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368 int pipe = crtc->pipe;
4369 struct intel_crtc_scaler_state *scaler_state =
4370 &crtc->config->scaler_state;
4371
4372 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4373
4374 if (crtc->config->pch_pfit.enabled) {
4375 int id;
4376
4377 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4378 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4379 return;
4380 }
4381
4382 id = scaler_state->scaler_id;
4383 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4384 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4385 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4386 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4387
4388 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4389 }
4390 }
4391
4392 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4393 {
4394 struct drm_device *dev = crtc->base.dev;
4395 struct drm_i915_private *dev_priv = dev->dev_private;
4396 int pipe = crtc->pipe;
4397
4398 if (crtc->config->pch_pfit.enabled) {
4399 /* Force use of hard-coded filter coefficients
4400 * as some pre-programmed values are broken,
4401 * e.g. x201.
4402 */
4403 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4404 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4405 PF_PIPE_SEL_IVB(pipe));
4406 else
4407 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4408 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4409 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4410 }
4411 }
4412
4413 void hsw_enable_ips(struct intel_crtc *crtc)
4414 {
4415 struct drm_device *dev = crtc->base.dev;
4416 struct drm_i915_private *dev_priv = dev->dev_private;
4417
4418 if (!crtc->config->ips_enabled)
4419 return;
4420
4421 /*
4422 * We can only enable IPS after we enable a plane and wait for a vblank
4423 * This function is called from post_plane_update, which is run after
4424 * a vblank wait.
4425 */
4426
4427 assert_plane_enabled(dev_priv, crtc->plane);
4428 if (IS_BROADWELL(dev)) {
4429 mutex_lock(&dev_priv->rps.hw_lock);
4430 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4431 mutex_unlock(&dev_priv->rps.hw_lock);
4432 /* Quoting Art Runyan: "its not safe to expect any particular
4433 * value in IPS_CTL bit 31 after enabling IPS through the
4434 * mailbox." Moreover, the mailbox may return a bogus state,
4435 * so we need to just enable it and continue on.
4436 */
4437 } else {
4438 I915_WRITE(IPS_CTL, IPS_ENABLE);
4439 /* The bit only becomes 1 in the next vblank, so this wait here
4440 * is essentially intel_wait_for_vblank. If we don't have this
4441 * and don't wait for vblanks until the end of crtc_enable, then
4442 * the HW state readout code will complain that the expected
4443 * IPS_CTL value is not the one we read. */
4444 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4445 DRM_ERROR("Timed out waiting for IPS enable\n");
4446 }
4447 }
4448
4449 void hsw_disable_ips(struct intel_crtc *crtc)
4450 {
4451 struct drm_device *dev = crtc->base.dev;
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453
4454 if (!crtc->config->ips_enabled)
4455 return;
4456
4457 assert_plane_enabled(dev_priv, crtc->plane);
4458 if (IS_BROADWELL(dev)) {
4459 mutex_lock(&dev_priv->rps.hw_lock);
4460 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4461 mutex_unlock(&dev_priv->rps.hw_lock);
4462 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4463 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4464 DRM_ERROR("Timed out waiting for IPS disable\n");
4465 } else {
4466 I915_WRITE(IPS_CTL, 0);
4467 POSTING_READ(IPS_CTL);
4468 }
4469
4470 /* We need to wait for a vblank before we can disable the plane. */
4471 intel_wait_for_vblank(dev, crtc->pipe);
4472 }
4473
4474 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4475 {
4476 if (intel_crtc->overlay) {
4477 struct drm_device *dev = intel_crtc->base.dev;
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479
4480 mutex_lock(&dev->struct_mutex);
4481 dev_priv->mm.interruptible = false;
4482 (void) intel_overlay_switch_off(intel_crtc->overlay);
4483 dev_priv->mm.interruptible = true;
4484 mutex_unlock(&dev->struct_mutex);
4485 }
4486
4487 /* Let userspace switch the overlay on again. In most cases userspace
4488 * has to recompute where to put it anyway.
4489 */
4490 }
4491
4492 /**
4493 * intel_post_enable_primary - Perform operations after enabling primary plane
4494 * @crtc: the CRTC whose primary plane was just enabled
4495 *
4496 * Performs potentially sleeping operations that must be done after the primary
4497 * plane is enabled, such as updating FBC and IPS. Note that this may be
4498 * called due to an explicit primary plane update, or due to an implicit
4499 * re-enable that is caused when a sprite plane is updated to no longer
4500 * completely hide the primary plane.
4501 */
4502 static void
4503 intel_post_enable_primary(struct drm_crtc *crtc)
4504 {
4505 struct drm_device *dev = crtc->dev;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4508 int pipe = intel_crtc->pipe;
4509
4510 /*
4511 * FIXME IPS should be fine as long as one plane is
4512 * enabled, but in practice it seems to have problems
4513 * when going from primary only to sprite only and vice
4514 * versa.
4515 */
4516 hsw_enable_ips(intel_crtc);
4517
4518 /*
4519 * Gen2 reports pipe underruns whenever all planes are disabled.
4520 * So don't enable underrun reporting before at least some planes
4521 * are enabled.
4522 * FIXME: Need to fix the logic to work when we turn off all planes
4523 * but leave the pipe running.
4524 */
4525 if (IS_GEN2(dev))
4526 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4527
4528 /* Underruns don't always raise interrupts, so check manually. */
4529 intel_check_cpu_fifo_underruns(dev_priv);
4530 intel_check_pch_fifo_underruns(dev_priv);
4531 }
4532
4533 /* FIXME move all this to pre_plane_update() with proper state tracking */
4534 static void
4535 intel_pre_disable_primary(struct drm_crtc *crtc)
4536 {
4537 struct drm_device *dev = crtc->dev;
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4540 int pipe = intel_crtc->pipe;
4541
4542 /*
4543 * Gen2 reports pipe underruns whenever all planes are disabled.
4544 * So diasble underrun reporting before all the planes get disabled.
4545 * FIXME: Need to fix the logic to work when we turn off all planes
4546 * but leave the pipe running.
4547 */
4548 if (IS_GEN2(dev))
4549 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4550
4551 /*
4552 * FIXME IPS should be fine as long as one plane is
4553 * enabled, but in practice it seems to have problems
4554 * when going from primary only to sprite only and vice
4555 * versa.
4556 */
4557 hsw_disable_ips(intel_crtc);
4558 }
4559
4560 /* FIXME get rid of this and use pre_plane_update */
4561 static void
4562 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4563 {
4564 struct drm_device *dev = crtc->dev;
4565 struct drm_i915_private *dev_priv = dev->dev_private;
4566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4567 int pipe = intel_crtc->pipe;
4568
4569 intel_pre_disable_primary(crtc);
4570
4571 /*
4572 * Vblank time updates from the shadow to live plane control register
4573 * are blocked if the memory self-refresh mode is active at that
4574 * moment. So to make sure the plane gets truly disabled, disable
4575 * first the self-refresh mode. The self-refresh enable bit in turn
4576 * will be checked/applied by the HW only at the next frame start
4577 * event which is after the vblank start event, so we need to have a
4578 * wait-for-vblank between disabling the plane and the pipe.
4579 */
4580 if (HAS_GMCH_DISPLAY(dev)) {
4581 intel_set_memory_cxsr(dev_priv, false);
4582 dev_priv->wm.vlv.cxsr = false;
4583 intel_wait_for_vblank(dev, pipe);
4584 }
4585 }
4586
4587 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4588 {
4589 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4590 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4591 struct intel_crtc_state *pipe_config =
4592 to_intel_crtc_state(crtc->base.state);
4593 struct drm_device *dev = crtc->base.dev;
4594 struct drm_plane *primary = crtc->base.primary;
4595 struct drm_plane_state *old_pri_state =
4596 drm_atomic_get_existing_plane_state(old_state, primary);
4597
4598 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4599
4600 crtc->wm.cxsr_allowed = true;
4601
4602 if (pipe_config->update_wm_post && pipe_config->base.active)
4603 intel_update_watermarks(&crtc->base);
4604
4605 if (old_pri_state) {
4606 struct intel_plane_state *primary_state =
4607 to_intel_plane_state(primary->state);
4608 struct intel_plane_state *old_primary_state =
4609 to_intel_plane_state(old_pri_state);
4610
4611 intel_fbc_post_update(crtc);
4612
4613 if (primary_state->visible &&
4614 (needs_modeset(&pipe_config->base) ||
4615 !old_primary_state->visible))
4616 intel_post_enable_primary(&crtc->base);
4617 }
4618 }
4619
4620 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4621 {
4622 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4623 struct drm_device *dev = crtc->base.dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625 struct intel_crtc_state *pipe_config =
4626 to_intel_crtc_state(crtc->base.state);
4627 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4628 struct drm_plane *primary = crtc->base.primary;
4629 struct drm_plane_state *old_pri_state =
4630 drm_atomic_get_existing_plane_state(old_state, primary);
4631 bool modeset = needs_modeset(&pipe_config->base);
4632
4633 if (old_pri_state) {
4634 struct intel_plane_state *primary_state =
4635 to_intel_plane_state(primary->state);
4636 struct intel_plane_state *old_primary_state =
4637 to_intel_plane_state(old_pri_state);
4638
4639 intel_fbc_pre_update(crtc);
4640
4641 if (old_primary_state->visible &&
4642 (modeset || !primary_state->visible))
4643 intel_pre_disable_primary(&crtc->base);
4644 }
4645
4646 if (pipe_config->disable_cxsr) {
4647 crtc->wm.cxsr_allowed = false;
4648
4649 /*
4650 * Vblank time updates from the shadow to live plane control register
4651 * are blocked if the memory self-refresh mode is active at that
4652 * moment. So to make sure the plane gets truly disabled, disable
4653 * first the self-refresh mode. The self-refresh enable bit in turn
4654 * will be checked/applied by the HW only at the next frame start
4655 * event which is after the vblank start event, so we need to have a
4656 * wait-for-vblank between disabling the plane and the pipe.
4657 */
4658 if (old_crtc_state->base.active) {
4659 intel_set_memory_cxsr(dev_priv, false);
4660 dev_priv->wm.vlv.cxsr = false;
4661 intel_wait_for_vblank(dev, crtc->pipe);
4662 }
4663 }
4664
4665 /*
4666 * IVB workaround: must disable low power watermarks for at least
4667 * one frame before enabling scaling. LP watermarks can be re-enabled
4668 * when scaling is disabled.
4669 *
4670 * WaCxSRDisabledForSpriteScaling:ivb
4671 */
4672 if (pipe_config->disable_lp_wm) {
4673 ilk_disable_lp_wm(dev);
4674 intel_wait_for_vblank(dev, crtc->pipe);
4675 }
4676
4677 /*
4678 * If we're doing a modeset, we're done. No need to do any pre-vblank
4679 * watermark programming here.
4680 */
4681 if (needs_modeset(&pipe_config->base))
4682 return;
4683
4684 /*
4685 * For platforms that support atomic watermarks, program the
4686 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4687 * will be the intermediate values that are safe for both pre- and
4688 * post- vblank; when vblank happens, the 'active' values will be set
4689 * to the final 'target' values and we'll do this again to get the
4690 * optimal watermarks. For gen9+ platforms, the values we program here
4691 * will be the final target values which will get automatically latched
4692 * at vblank time; no further programming will be necessary.
4693 *
4694 * If a platform hasn't been transitioned to atomic watermarks yet,
4695 * we'll continue to update watermarks the old way, if flags tell
4696 * us to.
4697 */
4698 if (dev_priv->display.initial_watermarks != NULL)
4699 dev_priv->display.initial_watermarks(pipe_config);
4700 else if (pipe_config->update_wm_pre)
4701 intel_update_watermarks(&crtc->base);
4702 }
4703
4704 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4705 {
4706 struct drm_device *dev = crtc->dev;
4707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4708 struct drm_plane *p;
4709 int pipe = intel_crtc->pipe;
4710
4711 intel_crtc_dpms_overlay_disable(intel_crtc);
4712
4713 drm_for_each_plane_mask(p, dev, plane_mask)
4714 to_intel_plane(p)->disable_plane(p, crtc);
4715
4716 /*
4717 * FIXME: Once we grow proper nuclear flip support out of this we need
4718 * to compute the mask of flip planes precisely. For the time being
4719 * consider this a flip to a NULL plane.
4720 */
4721 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4722 }
4723
4724 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4725 {
4726 struct drm_device *dev = crtc->dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729 struct intel_encoder *encoder;
4730 int pipe = intel_crtc->pipe;
4731 struct intel_crtc_state *pipe_config =
4732 to_intel_crtc_state(crtc->state);
4733
4734 if (WARN_ON(intel_crtc->active))
4735 return;
4736
4737 /*
4738 * Sometimes spurious CPU pipe underruns happen during FDI
4739 * training, at least with VGA+HDMI cloning. Suppress them.
4740 *
4741 * On ILK we get an occasional spurious CPU pipe underruns
4742 * between eDP port A enable and vdd enable. Also PCH port
4743 * enable seems to result in the occasional CPU pipe underrun.
4744 *
4745 * Spurious PCH underruns also occur during PCH enabling.
4746 */
4747 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4748 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4749 if (intel_crtc->config->has_pch_encoder)
4750 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4751
4752 if (intel_crtc->config->has_pch_encoder)
4753 intel_prepare_shared_dpll(intel_crtc);
4754
4755 if (intel_crtc->config->has_dp_encoder)
4756 intel_dp_set_m_n(intel_crtc, M1_N1);
4757
4758 intel_set_pipe_timings(intel_crtc);
4759 intel_set_pipe_src_size(intel_crtc);
4760
4761 if (intel_crtc->config->has_pch_encoder) {
4762 intel_cpu_transcoder_set_m_n(intel_crtc,
4763 &intel_crtc->config->fdi_m_n, NULL);
4764 }
4765
4766 ironlake_set_pipeconf(crtc);
4767
4768 intel_crtc->active = true;
4769
4770 for_each_encoder_on_crtc(dev, crtc, encoder)
4771 if (encoder->pre_enable)
4772 encoder->pre_enable(encoder);
4773
4774 if (intel_crtc->config->has_pch_encoder) {
4775 /* Note: FDI PLL enabling _must_ be done before we enable the
4776 * cpu pipes, hence this is separate from all the other fdi/pch
4777 * enabling. */
4778 ironlake_fdi_pll_enable(intel_crtc);
4779 } else {
4780 assert_fdi_tx_disabled(dev_priv, pipe);
4781 assert_fdi_rx_disabled(dev_priv, pipe);
4782 }
4783
4784 ironlake_pfit_enable(intel_crtc);
4785
4786 /*
4787 * On ILK+ LUT must be loaded before the pipe is running but with
4788 * clocks enabled
4789 */
4790 intel_color_load_luts(&pipe_config->base);
4791
4792 if (dev_priv->display.initial_watermarks != NULL)
4793 dev_priv->display.initial_watermarks(intel_crtc->config);
4794 intel_enable_pipe(intel_crtc);
4795
4796 if (intel_crtc->config->has_pch_encoder)
4797 ironlake_pch_enable(crtc);
4798
4799 assert_vblank_disabled(crtc);
4800 drm_crtc_vblank_on(crtc);
4801
4802 for_each_encoder_on_crtc(dev, crtc, encoder)
4803 encoder->enable(encoder);
4804
4805 if (HAS_PCH_CPT(dev))
4806 cpt_verify_modeset(dev, intel_crtc->pipe);
4807
4808 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4809 if (intel_crtc->config->has_pch_encoder)
4810 intel_wait_for_vblank(dev, pipe);
4811 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4812 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4813 }
4814
4815 /* IPS only exists on ULT machines and is tied to pipe A. */
4816 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4817 {
4818 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4819 }
4820
4821 static void haswell_crtc_enable(struct drm_crtc *crtc)
4822 {
4823 struct drm_device *dev = crtc->dev;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826 struct intel_encoder *encoder;
4827 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4828 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4829 struct intel_crtc_state *pipe_config =
4830 to_intel_crtc_state(crtc->state);
4831
4832 if (WARN_ON(intel_crtc->active))
4833 return;
4834
4835 if (intel_crtc->config->has_pch_encoder)
4836 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4837 false);
4838
4839 if (intel_crtc->config->shared_dpll)
4840 intel_enable_shared_dpll(intel_crtc);
4841
4842 if (intel_crtc->config->has_dp_encoder)
4843 intel_dp_set_m_n(intel_crtc, M1_N1);
4844
4845 if (!intel_crtc->config->has_dsi_encoder)
4846 intel_set_pipe_timings(intel_crtc);
4847
4848 intel_set_pipe_src_size(intel_crtc);
4849
4850 if (cpu_transcoder != TRANSCODER_EDP &&
4851 !transcoder_is_dsi(cpu_transcoder)) {
4852 I915_WRITE(PIPE_MULT(cpu_transcoder),
4853 intel_crtc->config->pixel_multiplier - 1);
4854 }
4855
4856 if (intel_crtc->config->has_pch_encoder) {
4857 intel_cpu_transcoder_set_m_n(intel_crtc,
4858 &intel_crtc->config->fdi_m_n, NULL);
4859 }
4860
4861 if (!intel_crtc->config->has_dsi_encoder)
4862 haswell_set_pipeconf(crtc);
4863
4864 haswell_set_pipemisc(crtc);
4865
4866 intel_color_set_csc(&pipe_config->base);
4867
4868 intel_crtc->active = true;
4869
4870 if (intel_crtc->config->has_pch_encoder)
4871 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4872 else
4873 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4874
4875 for_each_encoder_on_crtc(dev, crtc, encoder) {
4876 if (encoder->pre_enable)
4877 encoder->pre_enable(encoder);
4878 }
4879
4880 if (intel_crtc->config->has_pch_encoder)
4881 dev_priv->display.fdi_link_train(crtc);
4882
4883 if (!intel_crtc->config->has_dsi_encoder)
4884 intel_ddi_enable_pipe_clock(intel_crtc);
4885
4886 if (INTEL_INFO(dev)->gen >= 9)
4887 skylake_pfit_enable(intel_crtc);
4888 else
4889 ironlake_pfit_enable(intel_crtc);
4890
4891 /*
4892 * On ILK+ LUT must be loaded before the pipe is running but with
4893 * clocks enabled
4894 */
4895 intel_color_load_luts(&pipe_config->base);
4896
4897 intel_ddi_set_pipe_settings(crtc);
4898 if (!intel_crtc->config->has_dsi_encoder)
4899 intel_ddi_enable_transcoder_func(crtc);
4900
4901 if (dev_priv->display.initial_watermarks != NULL)
4902 dev_priv->display.initial_watermarks(pipe_config);
4903 else
4904 intel_update_watermarks(crtc);
4905
4906 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4907 if (!intel_crtc->config->has_dsi_encoder)
4908 intel_enable_pipe(intel_crtc);
4909
4910 if (intel_crtc->config->has_pch_encoder)
4911 lpt_pch_enable(crtc);
4912
4913 if (intel_crtc->config->dp_encoder_is_mst)
4914 intel_ddi_set_vc_payload_alloc(crtc, true);
4915
4916 assert_vblank_disabled(crtc);
4917 drm_crtc_vblank_on(crtc);
4918
4919 for_each_encoder_on_crtc(dev, crtc, encoder) {
4920 encoder->enable(encoder);
4921 intel_opregion_notify_encoder(encoder, true);
4922 }
4923
4924 if (intel_crtc->config->has_pch_encoder) {
4925 intel_wait_for_vblank(dev, pipe);
4926 intel_wait_for_vblank(dev, pipe);
4927 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4928 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4929 true);
4930 }
4931
4932 /* If we change the relative order between pipe/planes enabling, we need
4933 * to change the workaround. */
4934 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4935 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4936 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4937 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4938 }
4939 }
4940
4941 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4942 {
4943 struct drm_device *dev = crtc->base.dev;
4944 struct drm_i915_private *dev_priv = dev->dev_private;
4945 int pipe = crtc->pipe;
4946
4947 /* To avoid upsetting the power well on haswell only disable the pfit if
4948 * it's in use. The hw state code will make sure we get this right. */
4949 if (force || crtc->config->pch_pfit.enabled) {
4950 I915_WRITE(PF_CTL(pipe), 0);
4951 I915_WRITE(PF_WIN_POS(pipe), 0);
4952 I915_WRITE(PF_WIN_SZ(pipe), 0);
4953 }
4954 }
4955
4956 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4957 {
4958 struct drm_device *dev = crtc->dev;
4959 struct drm_i915_private *dev_priv = dev->dev_private;
4960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4961 struct intel_encoder *encoder;
4962 int pipe = intel_crtc->pipe;
4963
4964 /*
4965 * Sometimes spurious CPU pipe underruns happen when the
4966 * pipe is already disabled, but FDI RX/TX is still enabled.
4967 * Happens at least with VGA+HDMI cloning. Suppress them.
4968 */
4969 if (intel_crtc->config->has_pch_encoder) {
4970 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4971 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4972 }
4973
4974 for_each_encoder_on_crtc(dev, crtc, encoder)
4975 encoder->disable(encoder);
4976
4977 drm_crtc_vblank_off(crtc);
4978 assert_vblank_disabled(crtc);
4979
4980 intel_disable_pipe(intel_crtc);
4981
4982 ironlake_pfit_disable(intel_crtc, false);
4983
4984 if (intel_crtc->config->has_pch_encoder)
4985 ironlake_fdi_disable(crtc);
4986
4987 for_each_encoder_on_crtc(dev, crtc, encoder)
4988 if (encoder->post_disable)
4989 encoder->post_disable(encoder);
4990
4991 if (intel_crtc->config->has_pch_encoder) {
4992 ironlake_disable_pch_transcoder(dev_priv, pipe);
4993
4994 if (HAS_PCH_CPT(dev)) {
4995 i915_reg_t reg;
4996 u32 temp;
4997
4998 /* disable TRANS_DP_CTL */
4999 reg = TRANS_DP_CTL(pipe);
5000 temp = I915_READ(reg);
5001 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5002 TRANS_DP_PORT_SEL_MASK);
5003 temp |= TRANS_DP_PORT_SEL_NONE;
5004 I915_WRITE(reg, temp);
5005
5006 /* disable DPLL_SEL */
5007 temp = I915_READ(PCH_DPLL_SEL);
5008 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5009 I915_WRITE(PCH_DPLL_SEL, temp);
5010 }
5011
5012 ironlake_fdi_pll_disable(intel_crtc);
5013 }
5014
5015 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5016 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5017 }
5018
5019 static void haswell_crtc_disable(struct drm_crtc *crtc)
5020 {
5021 struct drm_device *dev = crtc->dev;
5022 struct drm_i915_private *dev_priv = dev->dev_private;
5023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5024 struct intel_encoder *encoder;
5025 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5026
5027 if (intel_crtc->config->has_pch_encoder)
5028 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5029 false);
5030
5031 for_each_encoder_on_crtc(dev, crtc, encoder) {
5032 intel_opregion_notify_encoder(encoder, false);
5033 encoder->disable(encoder);
5034 }
5035
5036 drm_crtc_vblank_off(crtc);
5037 assert_vblank_disabled(crtc);
5038
5039 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5040 if (!intel_crtc->config->has_dsi_encoder)
5041 intel_disable_pipe(intel_crtc);
5042
5043 if (intel_crtc->config->dp_encoder_is_mst)
5044 intel_ddi_set_vc_payload_alloc(crtc, false);
5045
5046 if (!intel_crtc->config->has_dsi_encoder)
5047 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5048
5049 if (INTEL_INFO(dev)->gen >= 9)
5050 skylake_scaler_disable(intel_crtc);
5051 else
5052 ironlake_pfit_disable(intel_crtc, false);
5053
5054 if (!intel_crtc->config->has_dsi_encoder)
5055 intel_ddi_disable_pipe_clock(intel_crtc);
5056
5057 for_each_encoder_on_crtc(dev, crtc, encoder)
5058 if (encoder->post_disable)
5059 encoder->post_disable(encoder);
5060
5061 if (intel_crtc->config->has_pch_encoder) {
5062 lpt_disable_pch_transcoder(dev_priv);
5063 lpt_disable_iclkip(dev_priv);
5064 intel_ddi_fdi_disable(crtc);
5065
5066 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5067 true);
5068 }
5069 }
5070
5071 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5072 {
5073 struct drm_device *dev = crtc->base.dev;
5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075 struct intel_crtc_state *pipe_config = crtc->config;
5076
5077 if (!pipe_config->gmch_pfit.control)
5078 return;
5079
5080 /*
5081 * The panel fitter should only be adjusted whilst the pipe is disabled,
5082 * according to register description and PRM.
5083 */
5084 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5085 assert_pipe_disabled(dev_priv, crtc->pipe);
5086
5087 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5088 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5089
5090 /* Border color in case we don't scale up to the full screen. Black by
5091 * default, change to something else for debugging. */
5092 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5093 }
5094
5095 static enum intel_display_power_domain port_to_power_domain(enum port port)
5096 {
5097 switch (port) {
5098 case PORT_A:
5099 return POWER_DOMAIN_PORT_DDI_A_LANES;
5100 case PORT_B:
5101 return POWER_DOMAIN_PORT_DDI_B_LANES;
5102 case PORT_C:
5103 return POWER_DOMAIN_PORT_DDI_C_LANES;
5104 case PORT_D:
5105 return POWER_DOMAIN_PORT_DDI_D_LANES;
5106 case PORT_E:
5107 return POWER_DOMAIN_PORT_DDI_E_LANES;
5108 default:
5109 MISSING_CASE(port);
5110 return POWER_DOMAIN_PORT_OTHER;
5111 }
5112 }
5113
5114 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5115 {
5116 switch (port) {
5117 case PORT_A:
5118 return POWER_DOMAIN_AUX_A;
5119 case PORT_B:
5120 return POWER_DOMAIN_AUX_B;
5121 case PORT_C:
5122 return POWER_DOMAIN_AUX_C;
5123 case PORT_D:
5124 return POWER_DOMAIN_AUX_D;
5125 case PORT_E:
5126 /* FIXME: Check VBT for actual wiring of PORT E */
5127 return POWER_DOMAIN_AUX_D;
5128 default:
5129 MISSING_CASE(port);
5130 return POWER_DOMAIN_AUX_A;
5131 }
5132 }
5133
5134 enum intel_display_power_domain
5135 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5136 {
5137 struct drm_device *dev = intel_encoder->base.dev;
5138 struct intel_digital_port *intel_dig_port;
5139
5140 switch (intel_encoder->type) {
5141 case INTEL_OUTPUT_UNKNOWN:
5142 /* Only DDI platforms should ever use this output type */
5143 WARN_ON_ONCE(!HAS_DDI(dev));
5144 case INTEL_OUTPUT_DISPLAYPORT:
5145 case INTEL_OUTPUT_HDMI:
5146 case INTEL_OUTPUT_EDP:
5147 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5148 return port_to_power_domain(intel_dig_port->port);
5149 case INTEL_OUTPUT_DP_MST:
5150 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5151 return port_to_power_domain(intel_dig_port->port);
5152 case INTEL_OUTPUT_ANALOG:
5153 return POWER_DOMAIN_PORT_CRT;
5154 case INTEL_OUTPUT_DSI:
5155 return POWER_DOMAIN_PORT_DSI;
5156 default:
5157 return POWER_DOMAIN_PORT_OTHER;
5158 }
5159 }
5160
5161 enum intel_display_power_domain
5162 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5163 {
5164 struct drm_device *dev = intel_encoder->base.dev;
5165 struct intel_digital_port *intel_dig_port;
5166
5167 switch (intel_encoder->type) {
5168 case INTEL_OUTPUT_UNKNOWN:
5169 case INTEL_OUTPUT_HDMI:
5170 /*
5171 * Only DDI platforms should ever use these output types.
5172 * We can get here after the HDMI detect code has already set
5173 * the type of the shared encoder. Since we can't be sure
5174 * what's the status of the given connectors, play safe and
5175 * run the DP detection too.
5176 */
5177 WARN_ON_ONCE(!HAS_DDI(dev));
5178 case INTEL_OUTPUT_DISPLAYPORT:
5179 case INTEL_OUTPUT_EDP:
5180 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5181 return port_to_aux_power_domain(intel_dig_port->port);
5182 case INTEL_OUTPUT_DP_MST:
5183 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5184 return port_to_aux_power_domain(intel_dig_port->port);
5185 default:
5186 MISSING_CASE(intel_encoder->type);
5187 return POWER_DOMAIN_AUX_A;
5188 }
5189 }
5190
5191 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5192 struct intel_crtc_state *crtc_state)
5193 {
5194 struct drm_device *dev = crtc->dev;
5195 struct drm_encoder *encoder;
5196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5197 enum pipe pipe = intel_crtc->pipe;
5198 unsigned long mask;
5199 enum transcoder transcoder = crtc_state->cpu_transcoder;
5200
5201 if (!crtc_state->base.active)
5202 return 0;
5203
5204 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5205 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5206 if (crtc_state->pch_pfit.enabled ||
5207 crtc_state->pch_pfit.force_thru)
5208 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5209
5210 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5211 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5212
5213 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5214 }
5215
5216 if (crtc_state->shared_dpll)
5217 mask |= BIT(POWER_DOMAIN_PLLS);
5218
5219 return mask;
5220 }
5221
5222 static unsigned long
5223 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5224 struct intel_crtc_state *crtc_state)
5225 {
5226 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 enum intel_display_power_domain domain;
5229 unsigned long domains, new_domains, old_domains;
5230
5231 old_domains = intel_crtc->enabled_power_domains;
5232 intel_crtc->enabled_power_domains = new_domains =
5233 get_crtc_power_domains(crtc, crtc_state);
5234
5235 domains = new_domains & ~old_domains;
5236
5237 for_each_power_domain(domain, domains)
5238 intel_display_power_get(dev_priv, domain);
5239
5240 return old_domains & ~new_domains;
5241 }
5242
5243 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5244 unsigned long domains)
5245 {
5246 enum intel_display_power_domain domain;
5247
5248 for_each_power_domain(domain, domains)
5249 intel_display_power_put(dev_priv, domain);
5250 }
5251
5252 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5253 {
5254 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5255
5256 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5257 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5258 return max_cdclk_freq;
5259 else if (IS_CHERRYVIEW(dev_priv))
5260 return max_cdclk_freq*95/100;
5261 else if (INTEL_INFO(dev_priv)->gen < 4)
5262 return 2*max_cdclk_freq*90/100;
5263 else
5264 return max_cdclk_freq*90/100;
5265 }
5266
5267 static void intel_update_max_cdclk(struct drm_device *dev)
5268 {
5269 struct drm_i915_private *dev_priv = dev->dev_private;
5270
5271 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5272 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5273
5274 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5275 dev_priv->max_cdclk_freq = 675000;
5276 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5277 dev_priv->max_cdclk_freq = 540000;
5278 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5279 dev_priv->max_cdclk_freq = 450000;
5280 else
5281 dev_priv->max_cdclk_freq = 337500;
5282 } else if (IS_BROXTON(dev)) {
5283 dev_priv->max_cdclk_freq = 624000;
5284 } else if (IS_BROADWELL(dev)) {
5285 /*
5286 * FIXME with extra cooling we can allow
5287 * 540 MHz for ULX and 675 Mhz for ULT.
5288 * How can we know if extra cooling is
5289 * available? PCI ID, VTB, something else?
5290 */
5291 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5292 dev_priv->max_cdclk_freq = 450000;
5293 else if (IS_BDW_ULX(dev))
5294 dev_priv->max_cdclk_freq = 450000;
5295 else if (IS_BDW_ULT(dev))
5296 dev_priv->max_cdclk_freq = 540000;
5297 else
5298 dev_priv->max_cdclk_freq = 675000;
5299 } else if (IS_CHERRYVIEW(dev)) {
5300 dev_priv->max_cdclk_freq = 320000;
5301 } else if (IS_VALLEYVIEW(dev)) {
5302 dev_priv->max_cdclk_freq = 400000;
5303 } else {
5304 /* otherwise assume cdclk is fixed */
5305 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5306 }
5307
5308 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5309
5310 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5311 dev_priv->max_cdclk_freq);
5312
5313 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5314 dev_priv->max_dotclk_freq);
5315 }
5316
5317 static void intel_update_cdclk(struct drm_device *dev)
5318 {
5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320
5321 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5322 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5323 dev_priv->cdclk_freq);
5324
5325 /*
5326 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5327 * Programmng [sic] note: bit[9:2] should be programmed to the number
5328 * of cdclk that generates 4MHz reference clock freq which is used to
5329 * generate GMBus clock. This will vary with the cdclk freq.
5330 */
5331 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5332 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5333
5334 if (dev_priv->max_cdclk_freq == 0)
5335 intel_update_max_cdclk(dev);
5336 }
5337
5338 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
5339 {
5340 uint32_t divider;
5341 uint32_t ratio;
5342 uint32_t current_freq;
5343 int ret;
5344
5345 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5346 switch (frequency) {
5347 case 144000:
5348 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5349 ratio = BXT_DE_PLL_RATIO(60);
5350 break;
5351 case 288000:
5352 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5353 ratio = BXT_DE_PLL_RATIO(60);
5354 break;
5355 case 384000:
5356 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5357 ratio = BXT_DE_PLL_RATIO(60);
5358 break;
5359 case 576000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 624000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5365 ratio = BXT_DE_PLL_RATIO(65);
5366 break;
5367 case 19200:
5368 /*
5369 * Bypass frequency with DE PLL disabled. Init ratio, divider
5370 * to suppress GCC warning.
5371 */
5372 ratio = 0;
5373 divider = 0;
5374 break;
5375 default:
5376 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5377
5378 return;
5379 }
5380
5381 mutex_lock(&dev_priv->rps.hw_lock);
5382 /* Inform power controller of upcoming frequency change */
5383 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5384 0x80000000);
5385 mutex_unlock(&dev_priv->rps.hw_lock);
5386
5387 if (ret) {
5388 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5389 ret, frequency);
5390 return;
5391 }
5392
5393 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5394 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5395 current_freq = current_freq * 500 + 1000;
5396
5397 /*
5398 * DE PLL has to be disabled when
5399 * - setting to 19.2MHz (bypass, PLL isn't used)
5400 * - before setting to 624MHz (PLL needs toggling)
5401 * - before setting to any frequency from 624MHz (PLL needs toggling)
5402 */
5403 if (frequency == 19200 || frequency == 624000 ||
5404 current_freq == 624000) {
5405 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5406 /* Timeout 200us */
5407 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5408 1))
5409 DRM_ERROR("timout waiting for DE PLL unlock\n");
5410 }
5411
5412 if (frequency != 19200) {
5413 uint32_t val;
5414
5415 val = I915_READ(BXT_DE_PLL_CTL);
5416 val &= ~BXT_DE_PLL_RATIO_MASK;
5417 val |= ratio;
5418 I915_WRITE(BXT_DE_PLL_CTL, val);
5419
5420 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5421 /* Timeout 200us */
5422 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5423 DRM_ERROR("timeout waiting for DE PLL lock\n");
5424
5425 val = I915_READ(CDCLK_CTL);
5426 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5427 val |= divider;
5428 /*
5429 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5430 * enable otherwise.
5431 */
5432 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5433 if (frequency >= 500000)
5434 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5435
5436 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5437 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5438 val |= (frequency - 1000) / 500;
5439 I915_WRITE(CDCLK_CTL, val);
5440 }
5441
5442 mutex_lock(&dev_priv->rps.hw_lock);
5443 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5444 DIV_ROUND_UP(frequency, 25000));
5445 mutex_unlock(&dev_priv->rps.hw_lock);
5446
5447 if (ret) {
5448 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5449 ret, frequency);
5450 return;
5451 }
5452
5453 intel_update_cdclk(dev_priv->dev);
5454 }
5455
5456 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5457 {
5458 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5459 return false;
5460
5461 /* TODO: Check for a valid CDCLK rate */
5462
5463 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5464 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5465
5466 return false;
5467 }
5468
5469 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5470 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5471
5472 return false;
5473 }
5474
5475 return true;
5476 }
5477
5478 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5479 {
5480 return broxton_cdclk_is_enabled(dev_priv);
5481 }
5482
5483 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5484 {
5485 /* check if cd clock is enabled */
5486 if (broxton_cdclk_is_enabled(dev_priv)) {
5487 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5488 return;
5489 }
5490
5491 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5492
5493 /*
5494 * FIXME:
5495 * - The initial CDCLK needs to be read from VBT.
5496 * Need to make this change after VBT has changes for BXT.
5497 * - check if setting the max (or any) cdclk freq is really necessary
5498 * here, it belongs to modeset time
5499 */
5500 broxton_set_cdclk(dev_priv, 624000);
5501
5502 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5503 POSTING_READ(DBUF_CTL);
5504
5505 udelay(10);
5506
5507 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5508 DRM_ERROR("DBuf power enable timeout!\n");
5509 }
5510
5511 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5512 {
5513 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5514 POSTING_READ(DBUF_CTL);
5515
5516 udelay(10);
5517
5518 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5519 DRM_ERROR("DBuf power disable timeout!\n");
5520
5521 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5522 broxton_set_cdclk(dev_priv, 19200);
5523 }
5524
5525 static const struct skl_cdclk_entry {
5526 unsigned int freq;
5527 unsigned int vco;
5528 } skl_cdclk_frequencies[] = {
5529 { .freq = 308570, .vco = 8640 },
5530 { .freq = 337500, .vco = 8100 },
5531 { .freq = 432000, .vco = 8640 },
5532 { .freq = 450000, .vco = 8100 },
5533 { .freq = 540000, .vco = 8100 },
5534 { .freq = 617140, .vco = 8640 },
5535 { .freq = 675000, .vco = 8100 },
5536 };
5537
5538 static unsigned int skl_cdclk_decimal(unsigned int freq)
5539 {
5540 return (freq - 1000) / 500;
5541 }
5542
5543 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5544 {
5545 unsigned int i;
5546
5547 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5548 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5549
5550 if (e->freq == freq)
5551 return e->vco;
5552 }
5553
5554 return 8100;
5555 }
5556
5557 static void
5558 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5559 {
5560 unsigned int min_freq;
5561 u32 val;
5562
5563 /* select the minimum CDCLK before enabling DPLL 0 */
5564 val = I915_READ(CDCLK_CTL);
5565 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5566 val |= CDCLK_FREQ_337_308;
5567
5568 if (required_vco == 8640)
5569 min_freq = 308570;
5570 else
5571 min_freq = 337500;
5572
5573 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5574
5575 I915_WRITE(CDCLK_CTL, val);
5576 POSTING_READ(CDCLK_CTL);
5577
5578 /*
5579 * We always enable DPLL0 with the lowest link rate possible, but still
5580 * taking into account the VCO required to operate the eDP panel at the
5581 * desired frequency. The usual DP link rates operate with a VCO of
5582 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5583 * The modeset code is responsible for the selection of the exact link
5584 * rate later on, with the constraint of choosing a frequency that
5585 * works with required_vco.
5586 */
5587 val = I915_READ(DPLL_CTRL1);
5588
5589 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5590 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5591 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5592 if (required_vco == 8640)
5593 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5594 SKL_DPLL0);
5595 else
5596 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5597 SKL_DPLL0);
5598
5599 I915_WRITE(DPLL_CTRL1, val);
5600 POSTING_READ(DPLL_CTRL1);
5601
5602 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5603
5604 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5605 DRM_ERROR("DPLL0 not locked\n");
5606 }
5607
5608 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5609 {
5610 int ret;
5611 u32 val;
5612
5613 /* inform PCU we want to change CDCLK */
5614 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5615 mutex_lock(&dev_priv->rps.hw_lock);
5616 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5617 mutex_unlock(&dev_priv->rps.hw_lock);
5618
5619 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5620 }
5621
5622 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5623 {
5624 unsigned int i;
5625
5626 for (i = 0; i < 15; i++) {
5627 if (skl_cdclk_pcu_ready(dev_priv))
5628 return true;
5629 udelay(10);
5630 }
5631
5632 return false;
5633 }
5634
5635 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5636 {
5637 struct drm_device *dev = dev_priv->dev;
5638 u32 freq_select, pcu_ack;
5639
5640 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5641
5642 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5643 DRM_ERROR("failed to inform PCU about cdclk change\n");
5644 return;
5645 }
5646
5647 /* set CDCLK_CTL */
5648 switch(freq) {
5649 case 450000:
5650 case 432000:
5651 freq_select = CDCLK_FREQ_450_432;
5652 pcu_ack = 1;
5653 break;
5654 case 540000:
5655 freq_select = CDCLK_FREQ_540;
5656 pcu_ack = 2;
5657 break;
5658 case 308570:
5659 case 337500:
5660 default:
5661 freq_select = CDCLK_FREQ_337_308;
5662 pcu_ack = 0;
5663 break;
5664 case 617140:
5665 case 675000:
5666 freq_select = CDCLK_FREQ_675_617;
5667 pcu_ack = 3;
5668 break;
5669 }
5670
5671 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5672 POSTING_READ(CDCLK_CTL);
5673
5674 /* inform PCU of the change */
5675 mutex_lock(&dev_priv->rps.hw_lock);
5676 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5677 mutex_unlock(&dev_priv->rps.hw_lock);
5678
5679 intel_update_cdclk(dev);
5680 }
5681
5682 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5683 {
5684 /* disable DBUF power */
5685 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5686 POSTING_READ(DBUF_CTL);
5687
5688 udelay(10);
5689
5690 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5691 DRM_ERROR("DBuf power disable timeout\n");
5692
5693 /* disable DPLL0 */
5694 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5695 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5696 DRM_ERROR("Couldn't disable DPLL0\n");
5697 }
5698
5699 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5700 {
5701 unsigned int required_vco;
5702
5703 /* DPLL0 not enabled (happens on early BIOS versions) */
5704 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5705 /* enable DPLL0 */
5706 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5707 skl_dpll0_enable(dev_priv, required_vco);
5708 }
5709
5710 /* set CDCLK to the frequency the BIOS chose */
5711 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5712
5713 /* enable DBUF power */
5714 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5715 POSTING_READ(DBUF_CTL);
5716
5717 udelay(10);
5718
5719 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5720 DRM_ERROR("DBuf power enable timeout\n");
5721 }
5722
5723 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5724 {
5725 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5726 uint32_t cdctl = I915_READ(CDCLK_CTL);
5727 int freq = dev_priv->skl_boot_cdclk;
5728
5729 /*
5730 * check if the pre-os intialized the display
5731 * There is SWF18 scratchpad register defined which is set by the
5732 * pre-os which can be used by the OS drivers to check the status
5733 */
5734 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5735 goto sanitize;
5736
5737 /* Is PLL enabled and locked ? */
5738 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5739 goto sanitize;
5740
5741 /* DPLL okay; verify the cdclock
5742 *
5743 * Noticed in some instances that the freq selection is correct but
5744 * decimal part is programmed wrong from BIOS where pre-os does not
5745 * enable display. Verify the same as well.
5746 */
5747 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5748 /* All well; nothing to sanitize */
5749 return false;
5750 sanitize:
5751 /*
5752 * As of now initialize with max cdclk till
5753 * we get dynamic cdclk support
5754 * */
5755 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5756 skl_init_cdclk(dev_priv);
5757
5758 /* we did have to sanitize */
5759 return true;
5760 }
5761
5762 /* Adjust CDclk dividers to allow high res or save power if possible */
5763 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5764 {
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 u32 val, cmd;
5767
5768 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5769 != dev_priv->cdclk_freq);
5770
5771 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5772 cmd = 2;
5773 else if (cdclk == 266667)
5774 cmd = 1;
5775 else
5776 cmd = 0;
5777
5778 mutex_lock(&dev_priv->rps.hw_lock);
5779 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5780 val &= ~DSPFREQGUAR_MASK;
5781 val |= (cmd << DSPFREQGUAR_SHIFT);
5782 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5783 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5784 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5785 50)) {
5786 DRM_ERROR("timed out waiting for CDclk change\n");
5787 }
5788 mutex_unlock(&dev_priv->rps.hw_lock);
5789
5790 mutex_lock(&dev_priv->sb_lock);
5791
5792 if (cdclk == 400000) {
5793 u32 divider;
5794
5795 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5796
5797 /* adjust cdclk divider */
5798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5799 val &= ~CCK_FREQUENCY_VALUES;
5800 val |= divider;
5801 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5802
5803 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5804 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5805 50))
5806 DRM_ERROR("timed out waiting for CDclk change\n");
5807 }
5808
5809 /* adjust self-refresh exit latency value */
5810 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5811 val &= ~0x7f;
5812
5813 /*
5814 * For high bandwidth configs, we set a higher latency in the bunit
5815 * so that the core display fetch happens in time to avoid underruns.
5816 */
5817 if (cdclk == 400000)
5818 val |= 4500 / 250; /* 4.5 usec */
5819 else
5820 val |= 3000 / 250; /* 3.0 usec */
5821 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5822
5823 mutex_unlock(&dev_priv->sb_lock);
5824
5825 intel_update_cdclk(dev);
5826 }
5827
5828 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5829 {
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831 u32 val, cmd;
5832
5833 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5834 != dev_priv->cdclk_freq);
5835
5836 switch (cdclk) {
5837 case 333333:
5838 case 320000:
5839 case 266667:
5840 case 200000:
5841 break;
5842 default:
5843 MISSING_CASE(cdclk);
5844 return;
5845 }
5846
5847 /*
5848 * Specs are full of misinformation, but testing on actual
5849 * hardware has shown that we just need to write the desired
5850 * CCK divider into the Punit register.
5851 */
5852 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5853
5854 mutex_lock(&dev_priv->rps.hw_lock);
5855 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5856 val &= ~DSPFREQGUAR_MASK_CHV;
5857 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5858 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5859 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5860 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5861 50)) {
5862 DRM_ERROR("timed out waiting for CDclk change\n");
5863 }
5864 mutex_unlock(&dev_priv->rps.hw_lock);
5865
5866 intel_update_cdclk(dev);
5867 }
5868
5869 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5870 int max_pixclk)
5871 {
5872 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5873 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5874
5875 /*
5876 * Really only a few cases to deal with, as only 4 CDclks are supported:
5877 * 200MHz
5878 * 267MHz
5879 * 320/333MHz (depends on HPLL freq)
5880 * 400MHz (VLV only)
5881 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5882 * of the lower bin and adjust if needed.
5883 *
5884 * We seem to get an unstable or solid color picture at 200MHz.
5885 * Not sure what's wrong. For now use 200MHz only when all pipes
5886 * are off.
5887 */
5888 if (!IS_CHERRYVIEW(dev_priv) &&
5889 max_pixclk > freq_320*limit/100)
5890 return 400000;
5891 else if (max_pixclk > 266667*limit/100)
5892 return freq_320;
5893 else if (max_pixclk > 0)
5894 return 266667;
5895 else
5896 return 200000;
5897 }
5898
5899 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5900 int max_pixclk)
5901 {
5902 /*
5903 * FIXME:
5904 * - remove the guardband, it's not needed on BXT
5905 * - set 19.2MHz bypass frequency if there are no active pipes
5906 */
5907 if (max_pixclk > 576000*9/10)
5908 return 624000;
5909 else if (max_pixclk > 384000*9/10)
5910 return 576000;
5911 else if (max_pixclk > 288000*9/10)
5912 return 384000;
5913 else if (max_pixclk > 144000*9/10)
5914 return 288000;
5915 else
5916 return 144000;
5917 }
5918
5919 /* Compute the max pixel clock for new configuration. */
5920 static int intel_mode_max_pixclk(struct drm_device *dev,
5921 struct drm_atomic_state *state)
5922 {
5923 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 struct drm_crtc *crtc;
5926 struct drm_crtc_state *crtc_state;
5927 unsigned max_pixclk = 0, i;
5928 enum pipe pipe;
5929
5930 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5931 sizeof(intel_state->min_pixclk));
5932
5933 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5934 int pixclk = 0;
5935
5936 if (crtc_state->enable)
5937 pixclk = crtc_state->adjusted_mode.crtc_clock;
5938
5939 intel_state->min_pixclk[i] = pixclk;
5940 }
5941
5942 for_each_pipe(dev_priv, pipe)
5943 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5944
5945 return max_pixclk;
5946 }
5947
5948 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5949 {
5950 struct drm_device *dev = state->dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 int max_pixclk = intel_mode_max_pixclk(dev, state);
5953 struct intel_atomic_state *intel_state =
5954 to_intel_atomic_state(state);
5955
5956 if (max_pixclk < 0)
5957 return max_pixclk;
5958
5959 intel_state->cdclk = intel_state->dev_cdclk =
5960 valleyview_calc_cdclk(dev_priv, max_pixclk);
5961
5962 if (!intel_state->active_crtcs)
5963 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5964
5965 return 0;
5966 }
5967
5968 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5969 {
5970 struct drm_device *dev = state->dev;
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 int max_pixclk = intel_mode_max_pixclk(dev, state);
5973 struct intel_atomic_state *intel_state =
5974 to_intel_atomic_state(state);
5975
5976 if (max_pixclk < 0)
5977 return max_pixclk;
5978
5979 intel_state->cdclk = intel_state->dev_cdclk =
5980 broxton_calc_cdclk(dev_priv, max_pixclk);
5981
5982 if (!intel_state->active_crtcs)
5983 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5984
5985 return 0;
5986 }
5987
5988 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5989 {
5990 unsigned int credits, default_credits;
5991
5992 if (IS_CHERRYVIEW(dev_priv))
5993 default_credits = PFI_CREDIT(12);
5994 else
5995 default_credits = PFI_CREDIT(8);
5996
5997 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5998 /* CHV suggested value is 31 or 63 */
5999 if (IS_CHERRYVIEW(dev_priv))
6000 credits = PFI_CREDIT_63;
6001 else
6002 credits = PFI_CREDIT(15);
6003 } else {
6004 credits = default_credits;
6005 }
6006
6007 /*
6008 * WA - write default credits before re-programming
6009 * FIXME: should we also set the resend bit here?
6010 */
6011 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6012 default_credits);
6013
6014 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6015 credits | PFI_CREDIT_RESEND);
6016
6017 /*
6018 * FIXME is this guaranteed to clear
6019 * immediately or should we poll for it?
6020 */
6021 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6022 }
6023
6024 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6025 {
6026 struct drm_device *dev = old_state->dev;
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028 struct intel_atomic_state *old_intel_state =
6029 to_intel_atomic_state(old_state);
6030 unsigned req_cdclk = old_intel_state->dev_cdclk;
6031
6032 /*
6033 * FIXME: We can end up here with all power domains off, yet
6034 * with a CDCLK frequency other than the minimum. To account
6035 * for this take the PIPE-A power domain, which covers the HW
6036 * blocks needed for the following programming. This can be
6037 * removed once it's guaranteed that we get here either with
6038 * the minimum CDCLK set, or the required power domains
6039 * enabled.
6040 */
6041 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6042
6043 if (IS_CHERRYVIEW(dev))
6044 cherryview_set_cdclk(dev, req_cdclk);
6045 else
6046 valleyview_set_cdclk(dev, req_cdclk);
6047
6048 vlv_program_pfi_credits(dev_priv);
6049
6050 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6051 }
6052
6053 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6054 {
6055 struct drm_device *dev = crtc->dev;
6056 struct drm_i915_private *dev_priv = to_i915(dev);
6057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6058 struct intel_encoder *encoder;
6059 struct intel_crtc_state *pipe_config =
6060 to_intel_crtc_state(crtc->state);
6061 int pipe = intel_crtc->pipe;
6062
6063 if (WARN_ON(intel_crtc->active))
6064 return;
6065
6066 if (intel_crtc->config->has_dp_encoder)
6067 intel_dp_set_m_n(intel_crtc, M1_N1);
6068
6069 intel_set_pipe_timings(intel_crtc);
6070 intel_set_pipe_src_size(intel_crtc);
6071
6072 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074
6075 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6076 I915_WRITE(CHV_CANVAS(pipe), 0);
6077 }
6078
6079 i9xx_set_pipeconf(intel_crtc);
6080
6081 intel_crtc->active = true;
6082
6083 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6084
6085 for_each_encoder_on_crtc(dev, crtc, encoder)
6086 if (encoder->pre_pll_enable)
6087 encoder->pre_pll_enable(encoder);
6088
6089 if (IS_CHERRYVIEW(dev)) {
6090 chv_prepare_pll(intel_crtc, intel_crtc->config);
6091 chv_enable_pll(intel_crtc, intel_crtc->config);
6092 } else {
6093 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6094 vlv_enable_pll(intel_crtc, intel_crtc->config);
6095 }
6096
6097 for_each_encoder_on_crtc(dev, crtc, encoder)
6098 if (encoder->pre_enable)
6099 encoder->pre_enable(encoder);
6100
6101 i9xx_pfit_enable(intel_crtc);
6102
6103 intel_color_load_luts(&pipe_config->base);
6104
6105 intel_update_watermarks(crtc);
6106 intel_enable_pipe(intel_crtc);
6107
6108 assert_vblank_disabled(crtc);
6109 drm_crtc_vblank_on(crtc);
6110
6111 for_each_encoder_on_crtc(dev, crtc, encoder)
6112 encoder->enable(encoder);
6113 }
6114
6115 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6116 {
6117 struct drm_device *dev = crtc->base.dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119
6120 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6121 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6122 }
6123
6124 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6125 {
6126 struct drm_device *dev = crtc->dev;
6127 struct drm_i915_private *dev_priv = to_i915(dev);
6128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6129 struct intel_encoder *encoder;
6130 struct intel_crtc_state *pipe_config =
6131 to_intel_crtc_state(crtc->state);
6132 enum pipe pipe = intel_crtc->pipe;
6133
6134 if (WARN_ON(intel_crtc->active))
6135 return;
6136
6137 i9xx_set_pll_dividers(intel_crtc);
6138
6139 if (intel_crtc->config->has_dp_encoder)
6140 intel_dp_set_m_n(intel_crtc, M1_N1);
6141
6142 intel_set_pipe_timings(intel_crtc);
6143 intel_set_pipe_src_size(intel_crtc);
6144
6145 i9xx_set_pipeconf(intel_crtc);
6146
6147 intel_crtc->active = true;
6148
6149 if (!IS_GEN2(dev))
6150 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6151
6152 for_each_encoder_on_crtc(dev, crtc, encoder)
6153 if (encoder->pre_enable)
6154 encoder->pre_enable(encoder);
6155
6156 i9xx_enable_pll(intel_crtc);
6157
6158 i9xx_pfit_enable(intel_crtc);
6159
6160 intel_color_load_luts(&pipe_config->base);
6161
6162 intel_update_watermarks(crtc);
6163 intel_enable_pipe(intel_crtc);
6164
6165 assert_vblank_disabled(crtc);
6166 drm_crtc_vblank_on(crtc);
6167
6168 for_each_encoder_on_crtc(dev, crtc, encoder)
6169 encoder->enable(encoder);
6170 }
6171
6172 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6173 {
6174 struct drm_device *dev = crtc->base.dev;
6175 struct drm_i915_private *dev_priv = dev->dev_private;
6176
6177 if (!crtc->config->gmch_pfit.control)
6178 return;
6179
6180 assert_pipe_disabled(dev_priv, crtc->pipe);
6181
6182 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6183 I915_READ(PFIT_CONTROL));
6184 I915_WRITE(PFIT_CONTROL, 0);
6185 }
6186
6187 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6188 {
6189 struct drm_device *dev = crtc->dev;
6190 struct drm_i915_private *dev_priv = dev->dev_private;
6191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6192 struct intel_encoder *encoder;
6193 int pipe = intel_crtc->pipe;
6194
6195 /*
6196 * On gen2 planes are double buffered but the pipe isn't, so we must
6197 * wait for planes to fully turn off before disabling the pipe.
6198 */
6199 if (IS_GEN2(dev))
6200 intel_wait_for_vblank(dev, pipe);
6201
6202 for_each_encoder_on_crtc(dev, crtc, encoder)
6203 encoder->disable(encoder);
6204
6205 drm_crtc_vblank_off(crtc);
6206 assert_vblank_disabled(crtc);
6207
6208 intel_disable_pipe(intel_crtc);
6209
6210 i9xx_pfit_disable(intel_crtc);
6211
6212 for_each_encoder_on_crtc(dev, crtc, encoder)
6213 if (encoder->post_disable)
6214 encoder->post_disable(encoder);
6215
6216 if (!intel_crtc->config->has_dsi_encoder) {
6217 if (IS_CHERRYVIEW(dev))
6218 chv_disable_pll(dev_priv, pipe);
6219 else if (IS_VALLEYVIEW(dev))
6220 vlv_disable_pll(dev_priv, pipe);
6221 else
6222 i9xx_disable_pll(intel_crtc);
6223 }
6224
6225 for_each_encoder_on_crtc(dev, crtc, encoder)
6226 if (encoder->post_pll_disable)
6227 encoder->post_pll_disable(encoder);
6228
6229 if (!IS_GEN2(dev))
6230 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6231 }
6232
6233 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6234 {
6235 struct intel_encoder *encoder;
6236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6238 enum intel_display_power_domain domain;
6239 unsigned long domains;
6240
6241 if (!intel_crtc->active)
6242 return;
6243
6244 if (to_intel_plane_state(crtc->primary->state)->visible) {
6245 WARN_ON(intel_crtc->unpin_work);
6246
6247 intel_pre_disable_primary_noatomic(crtc);
6248
6249 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6250 to_intel_plane_state(crtc->primary->state)->visible = false;
6251 }
6252
6253 dev_priv->display.crtc_disable(crtc);
6254
6255 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6256 crtc->base.id);
6257
6258 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6259 crtc->state->active = false;
6260 intel_crtc->active = false;
6261 crtc->enabled = false;
6262 crtc->state->connector_mask = 0;
6263 crtc->state->encoder_mask = 0;
6264
6265 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6266 encoder->base.crtc = NULL;
6267
6268 intel_fbc_disable(intel_crtc);
6269 intel_update_watermarks(crtc);
6270 intel_disable_shared_dpll(intel_crtc);
6271
6272 domains = intel_crtc->enabled_power_domains;
6273 for_each_power_domain(domain, domains)
6274 intel_display_power_put(dev_priv, domain);
6275 intel_crtc->enabled_power_domains = 0;
6276
6277 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6278 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6279 }
6280
6281 /*
6282 * turn all crtc's off, but do not adjust state
6283 * This has to be paired with a call to intel_modeset_setup_hw_state.
6284 */
6285 int intel_display_suspend(struct drm_device *dev)
6286 {
6287 struct drm_i915_private *dev_priv = to_i915(dev);
6288 struct drm_atomic_state *state;
6289 int ret;
6290
6291 state = drm_atomic_helper_suspend(dev);
6292 ret = PTR_ERR_OR_ZERO(state);
6293 if (ret)
6294 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6295 else
6296 dev_priv->modeset_restore_state = state;
6297 return ret;
6298 }
6299
6300 void intel_encoder_destroy(struct drm_encoder *encoder)
6301 {
6302 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6303
6304 drm_encoder_cleanup(encoder);
6305 kfree(intel_encoder);
6306 }
6307
6308 /* Cross check the actual hw state with our own modeset state tracking (and it's
6309 * internal consistency). */
6310 static void intel_connector_verify_state(struct intel_connector *connector)
6311 {
6312 struct drm_crtc *crtc = connector->base.state->crtc;
6313
6314 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6315 connector->base.base.id,
6316 connector->base.name);
6317
6318 if (connector->get_hw_state(connector)) {
6319 struct intel_encoder *encoder = connector->encoder;
6320 struct drm_connector_state *conn_state = connector->base.state;
6321
6322 I915_STATE_WARN(!crtc,
6323 "connector enabled without attached crtc\n");
6324
6325 if (!crtc)
6326 return;
6327
6328 I915_STATE_WARN(!crtc->state->active,
6329 "connector is active, but attached crtc isn't\n");
6330
6331 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6332 return;
6333
6334 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6335 "atomic encoder doesn't match attached encoder\n");
6336
6337 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6338 "attached encoder crtc differs from connector crtc\n");
6339 } else {
6340 I915_STATE_WARN(crtc && crtc->state->active,
6341 "attached crtc is active, but connector isn't\n");
6342 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6343 "best encoder set without crtc!\n");
6344 }
6345 }
6346
6347 int intel_connector_init(struct intel_connector *connector)
6348 {
6349 drm_atomic_helper_connector_reset(&connector->base);
6350
6351 if (!connector->base.state)
6352 return -ENOMEM;
6353
6354 return 0;
6355 }
6356
6357 struct intel_connector *intel_connector_alloc(void)
6358 {
6359 struct intel_connector *connector;
6360
6361 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6362 if (!connector)
6363 return NULL;
6364
6365 if (intel_connector_init(connector) < 0) {
6366 kfree(connector);
6367 return NULL;
6368 }
6369
6370 return connector;
6371 }
6372
6373 /* Simple connector->get_hw_state implementation for encoders that support only
6374 * one connector and no cloning and hence the encoder state determines the state
6375 * of the connector. */
6376 bool intel_connector_get_hw_state(struct intel_connector *connector)
6377 {
6378 enum pipe pipe = 0;
6379 struct intel_encoder *encoder = connector->encoder;
6380
6381 return encoder->get_hw_state(encoder, &pipe);
6382 }
6383
6384 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6385 {
6386 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6387 return crtc_state->fdi_lanes;
6388
6389 return 0;
6390 }
6391
6392 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6393 struct intel_crtc_state *pipe_config)
6394 {
6395 struct drm_atomic_state *state = pipe_config->base.state;
6396 struct intel_crtc *other_crtc;
6397 struct intel_crtc_state *other_crtc_state;
6398
6399 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6400 pipe_name(pipe), pipe_config->fdi_lanes);
6401 if (pipe_config->fdi_lanes > 4) {
6402 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6403 pipe_name(pipe), pipe_config->fdi_lanes);
6404 return -EINVAL;
6405 }
6406
6407 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6408 if (pipe_config->fdi_lanes > 2) {
6409 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6410 pipe_config->fdi_lanes);
6411 return -EINVAL;
6412 } else {
6413 return 0;
6414 }
6415 }
6416
6417 if (INTEL_INFO(dev)->num_pipes == 2)
6418 return 0;
6419
6420 /* Ivybridge 3 pipe is really complicated */
6421 switch (pipe) {
6422 case PIPE_A:
6423 return 0;
6424 case PIPE_B:
6425 if (pipe_config->fdi_lanes <= 2)
6426 return 0;
6427
6428 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6429 other_crtc_state =
6430 intel_atomic_get_crtc_state(state, other_crtc);
6431 if (IS_ERR(other_crtc_state))
6432 return PTR_ERR(other_crtc_state);
6433
6434 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6435 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6436 pipe_name(pipe), pipe_config->fdi_lanes);
6437 return -EINVAL;
6438 }
6439 return 0;
6440 case PIPE_C:
6441 if (pipe_config->fdi_lanes > 2) {
6442 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6443 pipe_name(pipe), pipe_config->fdi_lanes);
6444 return -EINVAL;
6445 }
6446
6447 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6448 other_crtc_state =
6449 intel_atomic_get_crtc_state(state, other_crtc);
6450 if (IS_ERR(other_crtc_state))
6451 return PTR_ERR(other_crtc_state);
6452
6453 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6454 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6455 return -EINVAL;
6456 }
6457 return 0;
6458 default:
6459 BUG();
6460 }
6461 }
6462
6463 #define RETRY 1
6464 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6465 struct intel_crtc_state *pipe_config)
6466 {
6467 struct drm_device *dev = intel_crtc->base.dev;
6468 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6469 int lane, link_bw, fdi_dotclock, ret;
6470 bool needs_recompute = false;
6471
6472 retry:
6473 /* FDI is a binary signal running at ~2.7GHz, encoding
6474 * each output octet as 10 bits. The actual frequency
6475 * is stored as a divider into a 100MHz clock, and the
6476 * mode pixel clock is stored in units of 1KHz.
6477 * Hence the bw of each lane in terms of the mode signal
6478 * is:
6479 */
6480 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6481
6482 fdi_dotclock = adjusted_mode->crtc_clock;
6483
6484 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6485 pipe_config->pipe_bpp);
6486
6487 pipe_config->fdi_lanes = lane;
6488
6489 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6490 link_bw, &pipe_config->fdi_m_n);
6491
6492 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6493 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6494 pipe_config->pipe_bpp -= 2*3;
6495 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6496 pipe_config->pipe_bpp);
6497 needs_recompute = true;
6498 pipe_config->bw_constrained = true;
6499
6500 goto retry;
6501 }
6502
6503 if (needs_recompute)
6504 return RETRY;
6505
6506 return ret;
6507 }
6508
6509 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6510 struct intel_crtc_state *pipe_config)
6511 {
6512 if (pipe_config->pipe_bpp > 24)
6513 return false;
6514
6515 /* HSW can handle pixel rate up to cdclk? */
6516 if (IS_HASWELL(dev_priv))
6517 return true;
6518
6519 /*
6520 * We compare against max which means we must take
6521 * the increased cdclk requirement into account when
6522 * calculating the new cdclk.
6523 *
6524 * Should measure whether using a lower cdclk w/o IPS
6525 */
6526 return ilk_pipe_pixel_rate(pipe_config) <=
6527 dev_priv->max_cdclk_freq * 95 / 100;
6528 }
6529
6530 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6531 struct intel_crtc_state *pipe_config)
6532 {
6533 struct drm_device *dev = crtc->base.dev;
6534 struct drm_i915_private *dev_priv = dev->dev_private;
6535
6536 pipe_config->ips_enabled = i915.enable_ips &&
6537 hsw_crtc_supports_ips(crtc) &&
6538 pipe_config_supports_ips(dev_priv, pipe_config);
6539 }
6540
6541 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6542 {
6543 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6544
6545 /* GDG double wide on either pipe, otherwise pipe A only */
6546 return INTEL_INFO(dev_priv)->gen < 4 &&
6547 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6548 }
6549
6550 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6551 struct intel_crtc_state *pipe_config)
6552 {
6553 struct drm_device *dev = crtc->base.dev;
6554 struct drm_i915_private *dev_priv = dev->dev_private;
6555 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6556
6557 /* FIXME should check pixel clock limits on all platforms */
6558 if (INTEL_INFO(dev)->gen < 4) {
6559 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6560
6561 /*
6562 * Enable double wide mode when the dot clock
6563 * is > 90% of the (display) core speed.
6564 */
6565 if (intel_crtc_supports_double_wide(crtc) &&
6566 adjusted_mode->crtc_clock > clock_limit) {
6567 clock_limit *= 2;
6568 pipe_config->double_wide = true;
6569 }
6570
6571 if (adjusted_mode->crtc_clock > clock_limit) {
6572 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6573 adjusted_mode->crtc_clock, clock_limit,
6574 yesno(pipe_config->double_wide));
6575 return -EINVAL;
6576 }
6577 }
6578
6579 /*
6580 * Pipe horizontal size must be even in:
6581 * - DVO ganged mode
6582 * - LVDS dual channel mode
6583 * - Double wide pipe
6584 */
6585 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6586 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6587 pipe_config->pipe_src_w &= ~1;
6588
6589 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6590 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6591 */
6592 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6593 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6594 return -EINVAL;
6595
6596 if (HAS_IPS(dev))
6597 hsw_compute_ips_config(crtc, pipe_config);
6598
6599 if (pipe_config->has_pch_encoder)
6600 return ironlake_fdi_compute_config(crtc, pipe_config);
6601
6602 return 0;
6603 }
6604
6605 static int skylake_get_display_clock_speed(struct drm_device *dev)
6606 {
6607 struct drm_i915_private *dev_priv = to_i915(dev);
6608 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6609 uint32_t cdctl = I915_READ(CDCLK_CTL);
6610 uint32_t linkrate;
6611
6612 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6613 return 24000; /* 24MHz is the cd freq with NSSC ref */
6614
6615 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6616 return 540000;
6617
6618 linkrate = (I915_READ(DPLL_CTRL1) &
6619 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6620
6621 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6622 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6623 /* vco 8640 */
6624 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6625 case CDCLK_FREQ_450_432:
6626 return 432000;
6627 case CDCLK_FREQ_337_308:
6628 return 308570;
6629 case CDCLK_FREQ_675_617:
6630 return 617140;
6631 default:
6632 WARN(1, "Unknown cd freq selection\n");
6633 }
6634 } else {
6635 /* vco 8100 */
6636 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6637 case CDCLK_FREQ_450_432:
6638 return 450000;
6639 case CDCLK_FREQ_337_308:
6640 return 337500;
6641 case CDCLK_FREQ_675_617:
6642 return 675000;
6643 default:
6644 WARN(1, "Unknown cd freq selection\n");
6645 }
6646 }
6647
6648 /* error case, do as if DPLL0 isn't enabled */
6649 return 24000;
6650 }
6651
6652 static int broxton_get_display_clock_speed(struct drm_device *dev)
6653 {
6654 struct drm_i915_private *dev_priv = to_i915(dev);
6655 uint32_t cdctl = I915_READ(CDCLK_CTL);
6656 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6657 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6658 int cdclk;
6659
6660 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6661 return 19200;
6662
6663 cdclk = 19200 * pll_ratio / 2;
6664
6665 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6666 case BXT_CDCLK_CD2X_DIV_SEL_1:
6667 return cdclk; /* 576MHz or 624MHz */
6668 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6669 return cdclk * 2 / 3; /* 384MHz */
6670 case BXT_CDCLK_CD2X_DIV_SEL_2:
6671 return cdclk / 2; /* 288MHz */
6672 case BXT_CDCLK_CD2X_DIV_SEL_4:
6673 return cdclk / 4; /* 144MHz */
6674 }
6675
6676 /* error case, do as if DE PLL isn't enabled */
6677 return 19200;
6678 }
6679
6680 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6681 {
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 uint32_t lcpll = I915_READ(LCPLL_CTL);
6684 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6685
6686 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6687 return 800000;
6688 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6689 return 450000;
6690 else if (freq == LCPLL_CLK_FREQ_450)
6691 return 450000;
6692 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6693 return 540000;
6694 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6695 return 337500;
6696 else
6697 return 675000;
6698 }
6699
6700 static int haswell_get_display_clock_speed(struct drm_device *dev)
6701 {
6702 struct drm_i915_private *dev_priv = dev->dev_private;
6703 uint32_t lcpll = I915_READ(LCPLL_CTL);
6704 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6705
6706 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6707 return 800000;
6708 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6709 return 450000;
6710 else if (freq == LCPLL_CLK_FREQ_450)
6711 return 450000;
6712 else if (IS_HSW_ULT(dev))
6713 return 337500;
6714 else
6715 return 540000;
6716 }
6717
6718 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6719 {
6720 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6721 CCK_DISPLAY_CLOCK_CONTROL);
6722 }
6723
6724 static int ilk_get_display_clock_speed(struct drm_device *dev)
6725 {
6726 return 450000;
6727 }
6728
6729 static int i945_get_display_clock_speed(struct drm_device *dev)
6730 {
6731 return 400000;
6732 }
6733
6734 static int i915_get_display_clock_speed(struct drm_device *dev)
6735 {
6736 return 333333;
6737 }
6738
6739 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6740 {
6741 return 200000;
6742 }
6743
6744 static int pnv_get_display_clock_speed(struct drm_device *dev)
6745 {
6746 u16 gcfgc = 0;
6747
6748 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6749
6750 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6751 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6752 return 266667;
6753 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6754 return 333333;
6755 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6756 return 444444;
6757 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6758 return 200000;
6759 default:
6760 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6761 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6762 return 133333;
6763 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6764 return 166667;
6765 }
6766 }
6767
6768 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6769 {
6770 u16 gcfgc = 0;
6771
6772 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6773
6774 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6775 return 133333;
6776 else {
6777 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6778 case GC_DISPLAY_CLOCK_333_MHZ:
6779 return 333333;
6780 default:
6781 case GC_DISPLAY_CLOCK_190_200_MHZ:
6782 return 190000;
6783 }
6784 }
6785 }
6786
6787 static int i865_get_display_clock_speed(struct drm_device *dev)
6788 {
6789 return 266667;
6790 }
6791
6792 static int i85x_get_display_clock_speed(struct drm_device *dev)
6793 {
6794 u16 hpllcc = 0;
6795
6796 /*
6797 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6798 * encoding is different :(
6799 * FIXME is this the right way to detect 852GM/852GMV?
6800 */
6801 if (dev->pdev->revision == 0x1)
6802 return 133333;
6803
6804 pci_bus_read_config_word(dev->pdev->bus,
6805 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6806
6807 /* Assume that the hardware is in the high speed state. This
6808 * should be the default.
6809 */
6810 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6811 case GC_CLOCK_133_200:
6812 case GC_CLOCK_133_200_2:
6813 case GC_CLOCK_100_200:
6814 return 200000;
6815 case GC_CLOCK_166_250:
6816 return 250000;
6817 case GC_CLOCK_100_133:
6818 return 133333;
6819 case GC_CLOCK_133_266:
6820 case GC_CLOCK_133_266_2:
6821 case GC_CLOCK_166_266:
6822 return 266667;
6823 }
6824
6825 /* Shouldn't happen */
6826 return 0;
6827 }
6828
6829 static int i830_get_display_clock_speed(struct drm_device *dev)
6830 {
6831 return 133333;
6832 }
6833
6834 static unsigned int intel_hpll_vco(struct drm_device *dev)
6835 {
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837 static const unsigned int blb_vco[8] = {
6838 [0] = 3200000,
6839 [1] = 4000000,
6840 [2] = 5333333,
6841 [3] = 4800000,
6842 [4] = 6400000,
6843 };
6844 static const unsigned int pnv_vco[8] = {
6845 [0] = 3200000,
6846 [1] = 4000000,
6847 [2] = 5333333,
6848 [3] = 4800000,
6849 [4] = 2666667,
6850 };
6851 static const unsigned int cl_vco[8] = {
6852 [0] = 3200000,
6853 [1] = 4000000,
6854 [2] = 5333333,
6855 [3] = 6400000,
6856 [4] = 3333333,
6857 [5] = 3566667,
6858 [6] = 4266667,
6859 };
6860 static const unsigned int elk_vco[8] = {
6861 [0] = 3200000,
6862 [1] = 4000000,
6863 [2] = 5333333,
6864 [3] = 4800000,
6865 };
6866 static const unsigned int ctg_vco[8] = {
6867 [0] = 3200000,
6868 [1] = 4000000,
6869 [2] = 5333333,
6870 [3] = 6400000,
6871 [4] = 2666667,
6872 [5] = 4266667,
6873 };
6874 const unsigned int *vco_table;
6875 unsigned int vco;
6876 uint8_t tmp = 0;
6877
6878 /* FIXME other chipsets? */
6879 if (IS_GM45(dev))
6880 vco_table = ctg_vco;
6881 else if (IS_G4X(dev))
6882 vco_table = elk_vco;
6883 else if (IS_CRESTLINE(dev))
6884 vco_table = cl_vco;
6885 else if (IS_PINEVIEW(dev))
6886 vco_table = pnv_vco;
6887 else if (IS_G33(dev))
6888 vco_table = blb_vco;
6889 else
6890 return 0;
6891
6892 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6893
6894 vco = vco_table[tmp & 0x7];
6895 if (vco == 0)
6896 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6897 else
6898 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6899
6900 return vco;
6901 }
6902
6903 static int gm45_get_display_clock_speed(struct drm_device *dev)
6904 {
6905 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6906 uint16_t tmp = 0;
6907
6908 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6909
6910 cdclk_sel = (tmp >> 12) & 0x1;
6911
6912 switch (vco) {
6913 case 2666667:
6914 case 4000000:
6915 case 5333333:
6916 return cdclk_sel ? 333333 : 222222;
6917 case 3200000:
6918 return cdclk_sel ? 320000 : 228571;
6919 default:
6920 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6921 return 222222;
6922 }
6923 }
6924
6925 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6926 {
6927 static const uint8_t div_3200[] = { 16, 10, 8 };
6928 static const uint8_t div_4000[] = { 20, 12, 10 };
6929 static const uint8_t div_5333[] = { 24, 16, 14 };
6930 const uint8_t *div_table;
6931 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6932 uint16_t tmp = 0;
6933
6934 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6935
6936 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6937
6938 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6939 goto fail;
6940
6941 switch (vco) {
6942 case 3200000:
6943 div_table = div_3200;
6944 break;
6945 case 4000000:
6946 div_table = div_4000;
6947 break;
6948 case 5333333:
6949 div_table = div_5333;
6950 break;
6951 default:
6952 goto fail;
6953 }
6954
6955 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6956
6957 fail:
6958 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6959 return 200000;
6960 }
6961
6962 static int g33_get_display_clock_speed(struct drm_device *dev)
6963 {
6964 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6965 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6966 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6967 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6968 const uint8_t *div_table;
6969 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6970 uint16_t tmp = 0;
6971
6972 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6973
6974 cdclk_sel = (tmp >> 4) & 0x7;
6975
6976 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6977 goto fail;
6978
6979 switch (vco) {
6980 case 3200000:
6981 div_table = div_3200;
6982 break;
6983 case 4000000:
6984 div_table = div_4000;
6985 break;
6986 case 4800000:
6987 div_table = div_4800;
6988 break;
6989 case 5333333:
6990 div_table = div_5333;
6991 break;
6992 default:
6993 goto fail;
6994 }
6995
6996 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6997
6998 fail:
6999 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7000 return 190476;
7001 }
7002
7003 static void
7004 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7005 {
7006 while (*num > DATA_LINK_M_N_MASK ||
7007 *den > DATA_LINK_M_N_MASK) {
7008 *num >>= 1;
7009 *den >>= 1;
7010 }
7011 }
7012
7013 static void compute_m_n(unsigned int m, unsigned int n,
7014 uint32_t *ret_m, uint32_t *ret_n)
7015 {
7016 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7017 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7018 intel_reduce_m_n_ratio(ret_m, ret_n);
7019 }
7020
7021 void
7022 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7023 int pixel_clock, int link_clock,
7024 struct intel_link_m_n *m_n)
7025 {
7026 m_n->tu = 64;
7027
7028 compute_m_n(bits_per_pixel * pixel_clock,
7029 link_clock * nlanes * 8,
7030 &m_n->gmch_m, &m_n->gmch_n);
7031
7032 compute_m_n(pixel_clock, link_clock,
7033 &m_n->link_m, &m_n->link_n);
7034 }
7035
7036 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7037 {
7038 if (i915.panel_use_ssc >= 0)
7039 return i915.panel_use_ssc != 0;
7040 return dev_priv->vbt.lvds_use_ssc
7041 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7042 }
7043
7044 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7045 {
7046 return (1 << dpll->n) << 16 | dpll->m2;
7047 }
7048
7049 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7050 {
7051 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7052 }
7053
7054 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7055 struct intel_crtc_state *crtc_state,
7056 struct dpll *reduced_clock)
7057 {
7058 struct drm_device *dev = crtc->base.dev;
7059 u32 fp, fp2 = 0;
7060
7061 if (IS_PINEVIEW(dev)) {
7062 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7063 if (reduced_clock)
7064 fp2 = pnv_dpll_compute_fp(reduced_clock);
7065 } else {
7066 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7067 if (reduced_clock)
7068 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7069 }
7070
7071 crtc_state->dpll_hw_state.fp0 = fp;
7072
7073 crtc->lowfreq_avail = false;
7074 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7075 reduced_clock) {
7076 crtc_state->dpll_hw_state.fp1 = fp2;
7077 crtc->lowfreq_avail = true;
7078 } else {
7079 crtc_state->dpll_hw_state.fp1 = fp;
7080 }
7081 }
7082
7083 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7084 pipe)
7085 {
7086 u32 reg_val;
7087
7088 /*
7089 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7090 * and set it to a reasonable value instead.
7091 */
7092 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7093 reg_val &= 0xffffff00;
7094 reg_val |= 0x00000030;
7095 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7096
7097 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7098 reg_val &= 0x8cffffff;
7099 reg_val = 0x8c000000;
7100 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7101
7102 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7103 reg_val &= 0xffffff00;
7104 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7105
7106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7107 reg_val &= 0x00ffffff;
7108 reg_val |= 0xb0000000;
7109 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7110 }
7111
7112 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7113 struct intel_link_m_n *m_n)
7114 {
7115 struct drm_device *dev = crtc->base.dev;
7116 struct drm_i915_private *dev_priv = dev->dev_private;
7117 int pipe = crtc->pipe;
7118
7119 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7120 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7121 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7122 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7123 }
7124
7125 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7126 struct intel_link_m_n *m_n,
7127 struct intel_link_m_n *m2_n2)
7128 {
7129 struct drm_device *dev = crtc->base.dev;
7130 struct drm_i915_private *dev_priv = dev->dev_private;
7131 int pipe = crtc->pipe;
7132 enum transcoder transcoder = crtc->config->cpu_transcoder;
7133
7134 if (INTEL_INFO(dev)->gen >= 5) {
7135 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7136 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7137 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7138 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7139 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7140 * for gen < 8) and if DRRS is supported (to make sure the
7141 * registers are not unnecessarily accessed).
7142 */
7143 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7144 crtc->config->has_drrs) {
7145 I915_WRITE(PIPE_DATA_M2(transcoder),
7146 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7147 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7148 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7149 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7150 }
7151 } else {
7152 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7153 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7154 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7155 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7156 }
7157 }
7158
7159 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7160 {
7161 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7162
7163 if (m_n == M1_N1) {
7164 dp_m_n = &crtc->config->dp_m_n;
7165 dp_m2_n2 = &crtc->config->dp_m2_n2;
7166 } else if (m_n == M2_N2) {
7167
7168 /*
7169 * M2_N2 registers are not supported. Hence m2_n2 divider value
7170 * needs to be programmed into M1_N1.
7171 */
7172 dp_m_n = &crtc->config->dp_m2_n2;
7173 } else {
7174 DRM_ERROR("Unsupported divider value\n");
7175 return;
7176 }
7177
7178 if (crtc->config->has_pch_encoder)
7179 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7180 else
7181 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7182 }
7183
7184 static void vlv_compute_dpll(struct intel_crtc *crtc,
7185 struct intel_crtc_state *pipe_config)
7186 {
7187 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7188 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7189 if (crtc->pipe != PIPE_A)
7190 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7191
7192 /* DPLL not used with DSI, but still need the rest set up */
7193 if (!pipe_config->has_dsi_encoder)
7194 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7195 DPLL_EXT_BUFFER_ENABLE_VLV;
7196
7197 pipe_config->dpll_hw_state.dpll_md =
7198 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7199 }
7200
7201 static void chv_compute_dpll(struct intel_crtc *crtc,
7202 struct intel_crtc_state *pipe_config)
7203 {
7204 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7205 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7206 if (crtc->pipe != PIPE_A)
7207 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7208
7209 /* DPLL not used with DSI, but still need the rest set up */
7210 if (!pipe_config->has_dsi_encoder)
7211 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7212
7213 pipe_config->dpll_hw_state.dpll_md =
7214 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7215 }
7216
7217 static void vlv_prepare_pll(struct intel_crtc *crtc,
7218 const struct intel_crtc_state *pipe_config)
7219 {
7220 struct drm_device *dev = crtc->base.dev;
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 enum pipe pipe = crtc->pipe;
7223 u32 mdiv;
7224 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7225 u32 coreclk, reg_val;
7226
7227 /* Enable Refclk */
7228 I915_WRITE(DPLL(pipe),
7229 pipe_config->dpll_hw_state.dpll &
7230 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7231
7232 /* No need to actually set up the DPLL with DSI */
7233 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7234 return;
7235
7236 mutex_lock(&dev_priv->sb_lock);
7237
7238 bestn = pipe_config->dpll.n;
7239 bestm1 = pipe_config->dpll.m1;
7240 bestm2 = pipe_config->dpll.m2;
7241 bestp1 = pipe_config->dpll.p1;
7242 bestp2 = pipe_config->dpll.p2;
7243
7244 /* See eDP HDMI DPIO driver vbios notes doc */
7245
7246 /* PLL B needs special handling */
7247 if (pipe == PIPE_B)
7248 vlv_pllb_recal_opamp(dev_priv, pipe);
7249
7250 /* Set up Tx target for periodic Rcomp update */
7251 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7252
7253 /* Disable target IRef on PLL */
7254 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7255 reg_val &= 0x00ffffff;
7256 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7257
7258 /* Disable fast lock */
7259 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7260
7261 /* Set idtafcrecal before PLL is enabled */
7262 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7263 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7264 mdiv |= ((bestn << DPIO_N_SHIFT));
7265 mdiv |= (1 << DPIO_K_SHIFT);
7266
7267 /*
7268 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7269 * but we don't support that).
7270 * Note: don't use the DAC post divider as it seems unstable.
7271 */
7272 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7274
7275 mdiv |= DPIO_ENABLE_CALIBRATION;
7276 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7277
7278 /* Set HBR and RBR LPF coefficients */
7279 if (pipe_config->port_clock == 162000 ||
7280 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7281 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7283 0x009f0003);
7284 else
7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7286 0x00d0000f);
7287
7288 if (pipe_config->has_dp_encoder) {
7289 /* Use SSC source */
7290 if (pipe == PIPE_A)
7291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7292 0x0df40000);
7293 else
7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7295 0x0df70000);
7296 } else { /* HDMI or VGA */
7297 /* Use bend source */
7298 if (pipe == PIPE_A)
7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7300 0x0df70000);
7301 else
7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7303 0x0df40000);
7304 }
7305
7306 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7307 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7308 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7309 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7310 coreclk |= 0x01000000;
7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7312
7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7314 mutex_unlock(&dev_priv->sb_lock);
7315 }
7316
7317 static void chv_prepare_pll(struct intel_crtc *crtc,
7318 const struct intel_crtc_state *pipe_config)
7319 {
7320 struct drm_device *dev = crtc->base.dev;
7321 struct drm_i915_private *dev_priv = dev->dev_private;
7322 enum pipe pipe = crtc->pipe;
7323 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7324 u32 loopfilter, tribuf_calcntr;
7325 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7326 u32 dpio_val;
7327 int vco;
7328
7329 /* Enable Refclk and SSC */
7330 I915_WRITE(DPLL(pipe),
7331 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7332
7333 /* No need to actually set up the DPLL with DSI */
7334 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7335 return;
7336
7337 bestn = pipe_config->dpll.n;
7338 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7339 bestm1 = pipe_config->dpll.m1;
7340 bestm2 = pipe_config->dpll.m2 >> 22;
7341 bestp1 = pipe_config->dpll.p1;
7342 bestp2 = pipe_config->dpll.p2;
7343 vco = pipe_config->dpll.vco;
7344 dpio_val = 0;
7345 loopfilter = 0;
7346
7347 mutex_lock(&dev_priv->sb_lock);
7348
7349 /* p1 and p2 divider */
7350 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7351 5 << DPIO_CHV_S1_DIV_SHIFT |
7352 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7353 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7354 1 << DPIO_CHV_K_DIV_SHIFT);
7355
7356 /* Feedback post-divider - m2 */
7357 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7358
7359 /* Feedback refclk divider - n and m1 */
7360 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7361 DPIO_CHV_M1_DIV_BY_2 |
7362 1 << DPIO_CHV_N_DIV_SHIFT);
7363
7364 /* M2 fraction division */
7365 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7366
7367 /* M2 fraction division enable */
7368 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7369 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7370 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7371 if (bestm2_frac)
7372 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7373 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7374
7375 /* Program digital lock detect threshold */
7376 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7377 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7378 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7379 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7380 if (!bestm2_frac)
7381 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7382 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7383
7384 /* Loop filter */
7385 if (vco == 5400000) {
7386 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7387 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7388 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7389 tribuf_calcntr = 0x9;
7390 } else if (vco <= 6200000) {
7391 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7392 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7393 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7394 tribuf_calcntr = 0x9;
7395 } else if (vco <= 6480000) {
7396 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7397 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7398 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7399 tribuf_calcntr = 0x8;
7400 } else {
7401 /* Not supported. Apply the same limits as in the max case */
7402 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7403 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7404 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405 tribuf_calcntr = 0;
7406 }
7407 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7408
7409 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7410 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7411 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7413
7414 /* AFC Recal */
7415 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7416 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7417 DPIO_AFC_RECAL);
7418
7419 mutex_unlock(&dev_priv->sb_lock);
7420 }
7421
7422 /**
7423 * vlv_force_pll_on - forcibly enable just the PLL
7424 * @dev_priv: i915 private structure
7425 * @pipe: pipe PLL to enable
7426 * @dpll: PLL configuration
7427 *
7428 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7429 * in cases where we need the PLL enabled even when @pipe is not going to
7430 * be enabled.
7431 */
7432 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7433 const struct dpll *dpll)
7434 {
7435 struct intel_crtc *crtc =
7436 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7437 struct intel_crtc_state *pipe_config;
7438
7439 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7440 if (!pipe_config)
7441 return -ENOMEM;
7442
7443 pipe_config->base.crtc = &crtc->base;
7444 pipe_config->pixel_multiplier = 1;
7445 pipe_config->dpll = *dpll;
7446
7447 if (IS_CHERRYVIEW(dev)) {
7448 chv_compute_dpll(crtc, pipe_config);
7449 chv_prepare_pll(crtc, pipe_config);
7450 chv_enable_pll(crtc, pipe_config);
7451 } else {
7452 vlv_compute_dpll(crtc, pipe_config);
7453 vlv_prepare_pll(crtc, pipe_config);
7454 vlv_enable_pll(crtc, pipe_config);
7455 }
7456
7457 kfree(pipe_config);
7458
7459 return 0;
7460 }
7461
7462 /**
7463 * vlv_force_pll_off - forcibly disable just the PLL
7464 * @dev_priv: i915 private structure
7465 * @pipe: pipe PLL to disable
7466 *
7467 * Disable the PLL for @pipe. To be used in cases where we need
7468 * the PLL enabled even when @pipe is not going to be enabled.
7469 */
7470 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7471 {
7472 if (IS_CHERRYVIEW(dev))
7473 chv_disable_pll(to_i915(dev), pipe);
7474 else
7475 vlv_disable_pll(to_i915(dev), pipe);
7476 }
7477
7478 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7479 struct intel_crtc_state *crtc_state,
7480 struct dpll *reduced_clock)
7481 {
7482 struct drm_device *dev = crtc->base.dev;
7483 struct drm_i915_private *dev_priv = dev->dev_private;
7484 u32 dpll;
7485 bool is_sdvo;
7486 struct dpll *clock = &crtc_state->dpll;
7487
7488 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7489
7490 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7491 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7492
7493 dpll = DPLL_VGA_MODE_DIS;
7494
7495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7496 dpll |= DPLLB_MODE_LVDS;
7497 else
7498 dpll |= DPLLB_MODE_DAC_SERIAL;
7499
7500 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7501 dpll |= (crtc_state->pixel_multiplier - 1)
7502 << SDVO_MULTIPLIER_SHIFT_HIRES;
7503 }
7504
7505 if (is_sdvo)
7506 dpll |= DPLL_SDVO_HIGH_SPEED;
7507
7508 if (crtc_state->has_dp_encoder)
7509 dpll |= DPLL_SDVO_HIGH_SPEED;
7510
7511 /* compute bitmask from p1 value */
7512 if (IS_PINEVIEW(dev))
7513 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7514 else {
7515 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7516 if (IS_G4X(dev) && reduced_clock)
7517 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7518 }
7519 switch (clock->p2) {
7520 case 5:
7521 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7522 break;
7523 case 7:
7524 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7525 break;
7526 case 10:
7527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7528 break;
7529 case 14:
7530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7531 break;
7532 }
7533 if (INTEL_INFO(dev)->gen >= 4)
7534 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7535
7536 if (crtc_state->sdvo_tv_clock)
7537 dpll |= PLL_REF_INPUT_TVCLKINBC;
7538 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7539 intel_panel_use_ssc(dev_priv))
7540 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7541 else
7542 dpll |= PLL_REF_INPUT_DREFCLK;
7543
7544 dpll |= DPLL_VCO_ENABLE;
7545 crtc_state->dpll_hw_state.dpll = dpll;
7546
7547 if (INTEL_INFO(dev)->gen >= 4) {
7548 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7549 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7550 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7551 }
7552 }
7553
7554 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7555 struct intel_crtc_state *crtc_state,
7556 struct dpll *reduced_clock)
7557 {
7558 struct drm_device *dev = crtc->base.dev;
7559 struct drm_i915_private *dev_priv = dev->dev_private;
7560 u32 dpll;
7561 struct dpll *clock = &crtc_state->dpll;
7562
7563 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7564
7565 dpll = DPLL_VGA_MODE_DIS;
7566
7567 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7568 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7569 } else {
7570 if (clock->p1 == 2)
7571 dpll |= PLL_P1_DIVIDE_BY_TWO;
7572 else
7573 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7574 if (clock->p2 == 4)
7575 dpll |= PLL_P2_DIVIDE_BY_4;
7576 }
7577
7578 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7579 dpll |= DPLL_DVO_2X_MODE;
7580
7581 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7582 intel_panel_use_ssc(dev_priv))
7583 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7584 else
7585 dpll |= PLL_REF_INPUT_DREFCLK;
7586
7587 dpll |= DPLL_VCO_ENABLE;
7588 crtc_state->dpll_hw_state.dpll = dpll;
7589 }
7590
7591 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7592 {
7593 struct drm_device *dev = intel_crtc->base.dev;
7594 struct drm_i915_private *dev_priv = dev->dev_private;
7595 enum pipe pipe = intel_crtc->pipe;
7596 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7597 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7598 uint32_t crtc_vtotal, crtc_vblank_end;
7599 int vsyncshift = 0;
7600
7601 /* We need to be careful not to changed the adjusted mode, for otherwise
7602 * the hw state checker will get angry at the mismatch. */
7603 crtc_vtotal = adjusted_mode->crtc_vtotal;
7604 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7605
7606 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7607 /* the chip adds 2 halflines automatically */
7608 crtc_vtotal -= 1;
7609 crtc_vblank_end -= 1;
7610
7611 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7612 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7613 else
7614 vsyncshift = adjusted_mode->crtc_hsync_start -
7615 adjusted_mode->crtc_htotal / 2;
7616 if (vsyncshift < 0)
7617 vsyncshift += adjusted_mode->crtc_htotal;
7618 }
7619
7620 if (INTEL_INFO(dev)->gen > 3)
7621 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7622
7623 I915_WRITE(HTOTAL(cpu_transcoder),
7624 (adjusted_mode->crtc_hdisplay - 1) |
7625 ((adjusted_mode->crtc_htotal - 1) << 16));
7626 I915_WRITE(HBLANK(cpu_transcoder),
7627 (adjusted_mode->crtc_hblank_start - 1) |
7628 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7629 I915_WRITE(HSYNC(cpu_transcoder),
7630 (adjusted_mode->crtc_hsync_start - 1) |
7631 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7632
7633 I915_WRITE(VTOTAL(cpu_transcoder),
7634 (adjusted_mode->crtc_vdisplay - 1) |
7635 ((crtc_vtotal - 1) << 16));
7636 I915_WRITE(VBLANK(cpu_transcoder),
7637 (adjusted_mode->crtc_vblank_start - 1) |
7638 ((crtc_vblank_end - 1) << 16));
7639 I915_WRITE(VSYNC(cpu_transcoder),
7640 (adjusted_mode->crtc_vsync_start - 1) |
7641 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7642
7643 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7644 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7645 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7646 * bits. */
7647 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7648 (pipe == PIPE_B || pipe == PIPE_C))
7649 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7650
7651 }
7652
7653 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7654 {
7655 struct drm_device *dev = intel_crtc->base.dev;
7656 struct drm_i915_private *dev_priv = dev->dev_private;
7657 enum pipe pipe = intel_crtc->pipe;
7658
7659 /* pipesrc controls the size that is scaled from, which should
7660 * always be the user's requested size.
7661 */
7662 I915_WRITE(PIPESRC(pipe),
7663 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7664 (intel_crtc->config->pipe_src_h - 1));
7665 }
7666
7667 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7668 struct intel_crtc_state *pipe_config)
7669 {
7670 struct drm_device *dev = crtc->base.dev;
7671 struct drm_i915_private *dev_priv = dev->dev_private;
7672 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7673 uint32_t tmp;
7674
7675 tmp = I915_READ(HTOTAL(cpu_transcoder));
7676 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7677 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7678 tmp = I915_READ(HBLANK(cpu_transcoder));
7679 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7681 tmp = I915_READ(HSYNC(cpu_transcoder));
7682 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7684
7685 tmp = I915_READ(VTOTAL(cpu_transcoder));
7686 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7687 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7688 tmp = I915_READ(VBLANK(cpu_transcoder));
7689 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7690 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7691 tmp = I915_READ(VSYNC(cpu_transcoder));
7692 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7693 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7694
7695 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7696 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7697 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7698 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7699 }
7700 }
7701
7702 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7703 struct intel_crtc_state *pipe_config)
7704 {
7705 struct drm_device *dev = crtc->base.dev;
7706 struct drm_i915_private *dev_priv = dev->dev_private;
7707 u32 tmp;
7708
7709 tmp = I915_READ(PIPESRC(crtc->pipe));
7710 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7711 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7712
7713 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7714 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7715 }
7716
7717 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7718 struct intel_crtc_state *pipe_config)
7719 {
7720 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7721 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7722 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7723 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7724
7725 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7726 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7727 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7728 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7729
7730 mode->flags = pipe_config->base.adjusted_mode.flags;
7731 mode->type = DRM_MODE_TYPE_DRIVER;
7732
7733 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7734 mode->flags |= pipe_config->base.adjusted_mode.flags;
7735
7736 mode->hsync = drm_mode_hsync(mode);
7737 mode->vrefresh = drm_mode_vrefresh(mode);
7738 drm_mode_set_name(mode);
7739 }
7740
7741 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7742 {
7743 struct drm_device *dev = intel_crtc->base.dev;
7744 struct drm_i915_private *dev_priv = dev->dev_private;
7745 uint32_t pipeconf;
7746
7747 pipeconf = 0;
7748
7749 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7750 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7751 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7752
7753 if (intel_crtc->config->double_wide)
7754 pipeconf |= PIPECONF_DOUBLE_WIDE;
7755
7756 /* only g4x and later have fancy bpc/dither controls */
7757 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7758 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7759 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7760 pipeconf |= PIPECONF_DITHER_EN |
7761 PIPECONF_DITHER_TYPE_SP;
7762
7763 switch (intel_crtc->config->pipe_bpp) {
7764 case 18:
7765 pipeconf |= PIPECONF_6BPC;
7766 break;
7767 case 24:
7768 pipeconf |= PIPECONF_8BPC;
7769 break;
7770 case 30:
7771 pipeconf |= PIPECONF_10BPC;
7772 break;
7773 default:
7774 /* Case prevented by intel_choose_pipe_bpp_dither. */
7775 BUG();
7776 }
7777 }
7778
7779 if (HAS_PIPE_CXSR(dev)) {
7780 if (intel_crtc->lowfreq_avail) {
7781 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7782 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7783 } else {
7784 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7785 }
7786 }
7787
7788 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7789 if (INTEL_INFO(dev)->gen < 4 ||
7790 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7791 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7792 else
7793 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7794 } else
7795 pipeconf |= PIPECONF_PROGRESSIVE;
7796
7797 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7798 intel_crtc->config->limited_color_range)
7799 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7800
7801 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7802 POSTING_READ(PIPECONF(intel_crtc->pipe));
7803 }
7804
7805 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7806 struct intel_crtc_state *crtc_state)
7807 {
7808 struct drm_device *dev = crtc->base.dev;
7809 struct drm_i915_private *dev_priv = dev->dev_private;
7810 const struct intel_limit *limit;
7811 int refclk = 48000;
7812
7813 memset(&crtc_state->dpll_hw_state, 0,
7814 sizeof(crtc_state->dpll_hw_state));
7815
7816 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7817 if (intel_panel_use_ssc(dev_priv)) {
7818 refclk = dev_priv->vbt.lvds_ssc_freq;
7819 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7820 }
7821
7822 limit = &intel_limits_i8xx_lvds;
7823 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7824 limit = &intel_limits_i8xx_dvo;
7825 } else {
7826 limit = &intel_limits_i8xx_dac;
7827 }
7828
7829 if (!crtc_state->clock_set &&
7830 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7831 refclk, NULL, &crtc_state->dpll)) {
7832 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7833 return -EINVAL;
7834 }
7835
7836 i8xx_compute_dpll(crtc, crtc_state, NULL);
7837
7838 return 0;
7839 }
7840
7841 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7842 struct intel_crtc_state *crtc_state)
7843 {
7844 struct drm_device *dev = crtc->base.dev;
7845 struct drm_i915_private *dev_priv = dev->dev_private;
7846 const struct intel_limit *limit;
7847 int refclk = 96000;
7848
7849 memset(&crtc_state->dpll_hw_state, 0,
7850 sizeof(crtc_state->dpll_hw_state));
7851
7852 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7853 if (intel_panel_use_ssc(dev_priv)) {
7854 refclk = dev_priv->vbt.lvds_ssc_freq;
7855 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7856 }
7857
7858 if (intel_is_dual_link_lvds(dev))
7859 limit = &intel_limits_g4x_dual_channel_lvds;
7860 else
7861 limit = &intel_limits_g4x_single_channel_lvds;
7862 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7863 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7864 limit = &intel_limits_g4x_hdmi;
7865 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7866 limit = &intel_limits_g4x_sdvo;
7867 } else {
7868 /* The option is for other outputs */
7869 limit = &intel_limits_i9xx_sdvo;
7870 }
7871
7872 if (!crtc_state->clock_set &&
7873 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7874 refclk, NULL, &crtc_state->dpll)) {
7875 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7876 return -EINVAL;
7877 }
7878
7879 i9xx_compute_dpll(crtc, crtc_state, NULL);
7880
7881 return 0;
7882 }
7883
7884 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7885 struct intel_crtc_state *crtc_state)
7886 {
7887 struct drm_device *dev = crtc->base.dev;
7888 struct drm_i915_private *dev_priv = dev->dev_private;
7889 const struct intel_limit *limit;
7890 int refclk = 96000;
7891
7892 memset(&crtc_state->dpll_hw_state, 0,
7893 sizeof(crtc_state->dpll_hw_state));
7894
7895 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7896 if (intel_panel_use_ssc(dev_priv)) {
7897 refclk = dev_priv->vbt.lvds_ssc_freq;
7898 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7899 }
7900
7901 limit = &intel_limits_pineview_lvds;
7902 } else {
7903 limit = &intel_limits_pineview_sdvo;
7904 }
7905
7906 if (!crtc_state->clock_set &&
7907 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7908 refclk, NULL, &crtc_state->dpll)) {
7909 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7910 return -EINVAL;
7911 }
7912
7913 i9xx_compute_dpll(crtc, crtc_state, NULL);
7914
7915 return 0;
7916 }
7917
7918 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7919 struct intel_crtc_state *crtc_state)
7920 {
7921 struct drm_device *dev = crtc->base.dev;
7922 struct drm_i915_private *dev_priv = dev->dev_private;
7923 const struct intel_limit *limit;
7924 int refclk = 96000;
7925
7926 memset(&crtc_state->dpll_hw_state, 0,
7927 sizeof(crtc_state->dpll_hw_state));
7928
7929 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7930 if (intel_panel_use_ssc(dev_priv)) {
7931 refclk = dev_priv->vbt.lvds_ssc_freq;
7932 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7933 }
7934
7935 limit = &intel_limits_i9xx_lvds;
7936 } else {
7937 limit = &intel_limits_i9xx_sdvo;
7938 }
7939
7940 if (!crtc_state->clock_set &&
7941 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7942 refclk, NULL, &crtc_state->dpll)) {
7943 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7944 return -EINVAL;
7945 }
7946
7947 i9xx_compute_dpll(crtc, crtc_state, NULL);
7948
7949 return 0;
7950 }
7951
7952 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7953 struct intel_crtc_state *crtc_state)
7954 {
7955 int refclk = 100000;
7956 const struct intel_limit *limit = &intel_limits_chv;
7957
7958 memset(&crtc_state->dpll_hw_state, 0,
7959 sizeof(crtc_state->dpll_hw_state));
7960
7961 if (!crtc_state->clock_set &&
7962 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7963 refclk, NULL, &crtc_state->dpll)) {
7964 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7965 return -EINVAL;
7966 }
7967
7968 chv_compute_dpll(crtc, crtc_state);
7969
7970 return 0;
7971 }
7972
7973 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7974 struct intel_crtc_state *crtc_state)
7975 {
7976 int refclk = 100000;
7977 const struct intel_limit *limit = &intel_limits_vlv;
7978
7979 memset(&crtc_state->dpll_hw_state, 0,
7980 sizeof(crtc_state->dpll_hw_state));
7981
7982 if (!crtc_state->clock_set &&
7983 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7984 refclk, NULL, &crtc_state->dpll)) {
7985 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7986 return -EINVAL;
7987 }
7988
7989 vlv_compute_dpll(crtc, crtc_state);
7990
7991 return 0;
7992 }
7993
7994 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7995 struct intel_crtc_state *pipe_config)
7996 {
7997 struct drm_device *dev = crtc->base.dev;
7998 struct drm_i915_private *dev_priv = dev->dev_private;
7999 uint32_t tmp;
8000
8001 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8002 return;
8003
8004 tmp = I915_READ(PFIT_CONTROL);
8005 if (!(tmp & PFIT_ENABLE))
8006 return;
8007
8008 /* Check whether the pfit is attached to our pipe. */
8009 if (INTEL_INFO(dev)->gen < 4) {
8010 if (crtc->pipe != PIPE_B)
8011 return;
8012 } else {
8013 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8014 return;
8015 }
8016
8017 pipe_config->gmch_pfit.control = tmp;
8018 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8019 }
8020
8021 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8022 struct intel_crtc_state *pipe_config)
8023 {
8024 struct drm_device *dev = crtc->base.dev;
8025 struct drm_i915_private *dev_priv = dev->dev_private;
8026 int pipe = pipe_config->cpu_transcoder;
8027 struct dpll clock;
8028 u32 mdiv;
8029 int refclk = 100000;
8030
8031 /* In case of DSI, DPLL will not be used */
8032 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8033 return;
8034
8035 mutex_lock(&dev_priv->sb_lock);
8036 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8037 mutex_unlock(&dev_priv->sb_lock);
8038
8039 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8040 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8041 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8042 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8043 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8044
8045 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8046 }
8047
8048 static void
8049 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8050 struct intel_initial_plane_config *plane_config)
8051 {
8052 struct drm_device *dev = crtc->base.dev;
8053 struct drm_i915_private *dev_priv = dev->dev_private;
8054 u32 val, base, offset;
8055 int pipe = crtc->pipe, plane = crtc->plane;
8056 int fourcc, pixel_format;
8057 unsigned int aligned_height;
8058 struct drm_framebuffer *fb;
8059 struct intel_framebuffer *intel_fb;
8060
8061 val = I915_READ(DSPCNTR(plane));
8062 if (!(val & DISPLAY_PLANE_ENABLE))
8063 return;
8064
8065 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8066 if (!intel_fb) {
8067 DRM_DEBUG_KMS("failed to alloc fb\n");
8068 return;
8069 }
8070
8071 fb = &intel_fb->base;
8072
8073 if (INTEL_INFO(dev)->gen >= 4) {
8074 if (val & DISPPLANE_TILED) {
8075 plane_config->tiling = I915_TILING_X;
8076 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8077 }
8078 }
8079
8080 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8081 fourcc = i9xx_format_to_fourcc(pixel_format);
8082 fb->pixel_format = fourcc;
8083 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8084
8085 if (INTEL_INFO(dev)->gen >= 4) {
8086 if (plane_config->tiling)
8087 offset = I915_READ(DSPTILEOFF(plane));
8088 else
8089 offset = I915_READ(DSPLINOFF(plane));
8090 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8091 } else {
8092 base = I915_READ(DSPADDR(plane));
8093 }
8094 plane_config->base = base;
8095
8096 val = I915_READ(PIPESRC(pipe));
8097 fb->width = ((val >> 16) & 0xfff) + 1;
8098 fb->height = ((val >> 0) & 0xfff) + 1;
8099
8100 val = I915_READ(DSPSTRIDE(pipe));
8101 fb->pitches[0] = val & 0xffffffc0;
8102
8103 aligned_height = intel_fb_align_height(dev, fb->height,
8104 fb->pixel_format,
8105 fb->modifier[0]);
8106
8107 plane_config->size = fb->pitches[0] * aligned_height;
8108
8109 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8110 pipe_name(pipe), plane, fb->width, fb->height,
8111 fb->bits_per_pixel, base, fb->pitches[0],
8112 plane_config->size);
8113
8114 plane_config->fb = intel_fb;
8115 }
8116
8117 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8118 struct intel_crtc_state *pipe_config)
8119 {
8120 struct drm_device *dev = crtc->base.dev;
8121 struct drm_i915_private *dev_priv = dev->dev_private;
8122 int pipe = pipe_config->cpu_transcoder;
8123 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8124 struct dpll clock;
8125 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8126 int refclk = 100000;
8127
8128 /* In case of DSI, DPLL will not be used */
8129 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8130 return;
8131
8132 mutex_lock(&dev_priv->sb_lock);
8133 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8134 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8135 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8136 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8137 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8138 mutex_unlock(&dev_priv->sb_lock);
8139
8140 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8141 clock.m2 = (pll_dw0 & 0xff) << 22;
8142 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8143 clock.m2 |= pll_dw2 & 0x3fffff;
8144 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8145 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8146 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8147
8148 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8149 }
8150
8151 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8152 struct intel_crtc_state *pipe_config)
8153 {
8154 struct drm_device *dev = crtc->base.dev;
8155 struct drm_i915_private *dev_priv = dev->dev_private;
8156 enum intel_display_power_domain power_domain;
8157 uint32_t tmp;
8158 bool ret;
8159
8160 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8161 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8162 return false;
8163
8164 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8165 pipe_config->shared_dpll = NULL;
8166
8167 ret = false;
8168
8169 tmp = I915_READ(PIPECONF(crtc->pipe));
8170 if (!(tmp & PIPECONF_ENABLE))
8171 goto out;
8172
8173 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8174 switch (tmp & PIPECONF_BPC_MASK) {
8175 case PIPECONF_6BPC:
8176 pipe_config->pipe_bpp = 18;
8177 break;
8178 case PIPECONF_8BPC:
8179 pipe_config->pipe_bpp = 24;
8180 break;
8181 case PIPECONF_10BPC:
8182 pipe_config->pipe_bpp = 30;
8183 break;
8184 default:
8185 break;
8186 }
8187 }
8188
8189 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8190 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8191 pipe_config->limited_color_range = true;
8192
8193 if (INTEL_INFO(dev)->gen < 4)
8194 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8195
8196 intel_get_pipe_timings(crtc, pipe_config);
8197 intel_get_pipe_src_size(crtc, pipe_config);
8198
8199 i9xx_get_pfit_config(crtc, pipe_config);
8200
8201 if (INTEL_INFO(dev)->gen >= 4) {
8202 /* No way to read it out on pipes B and C */
8203 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8204 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8205 else
8206 tmp = I915_READ(DPLL_MD(crtc->pipe));
8207 pipe_config->pixel_multiplier =
8208 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8209 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8210 pipe_config->dpll_hw_state.dpll_md = tmp;
8211 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8212 tmp = I915_READ(DPLL(crtc->pipe));
8213 pipe_config->pixel_multiplier =
8214 ((tmp & SDVO_MULTIPLIER_MASK)
8215 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8216 } else {
8217 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8218 * port and will be fixed up in the encoder->get_config
8219 * function. */
8220 pipe_config->pixel_multiplier = 1;
8221 }
8222 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8223 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8224 /*
8225 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8226 * on 830. Filter it out here so that we don't
8227 * report errors due to that.
8228 */
8229 if (IS_I830(dev))
8230 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8231
8232 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8233 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8234 } else {
8235 /* Mask out read-only status bits. */
8236 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8237 DPLL_PORTC_READY_MASK |
8238 DPLL_PORTB_READY_MASK);
8239 }
8240
8241 if (IS_CHERRYVIEW(dev))
8242 chv_crtc_clock_get(crtc, pipe_config);
8243 else if (IS_VALLEYVIEW(dev))
8244 vlv_crtc_clock_get(crtc, pipe_config);
8245 else
8246 i9xx_crtc_clock_get(crtc, pipe_config);
8247
8248 /*
8249 * Normally the dotclock is filled in by the encoder .get_config()
8250 * but in case the pipe is enabled w/o any ports we need a sane
8251 * default.
8252 */
8253 pipe_config->base.adjusted_mode.crtc_clock =
8254 pipe_config->port_clock / pipe_config->pixel_multiplier;
8255
8256 ret = true;
8257
8258 out:
8259 intel_display_power_put(dev_priv, power_domain);
8260
8261 return ret;
8262 }
8263
8264 static void ironlake_init_pch_refclk(struct drm_device *dev)
8265 {
8266 struct drm_i915_private *dev_priv = dev->dev_private;
8267 struct intel_encoder *encoder;
8268 u32 val, final;
8269 bool has_lvds = false;
8270 bool has_cpu_edp = false;
8271 bool has_panel = false;
8272 bool has_ck505 = false;
8273 bool can_ssc = false;
8274
8275 /* We need to take the global config into account */
8276 for_each_intel_encoder(dev, encoder) {
8277 switch (encoder->type) {
8278 case INTEL_OUTPUT_LVDS:
8279 has_panel = true;
8280 has_lvds = true;
8281 break;
8282 case INTEL_OUTPUT_EDP:
8283 has_panel = true;
8284 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8285 has_cpu_edp = true;
8286 break;
8287 default:
8288 break;
8289 }
8290 }
8291
8292 if (HAS_PCH_IBX(dev)) {
8293 has_ck505 = dev_priv->vbt.display_clock_mode;
8294 can_ssc = has_ck505;
8295 } else {
8296 has_ck505 = false;
8297 can_ssc = true;
8298 }
8299
8300 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8301 has_panel, has_lvds, has_ck505);
8302
8303 /* Ironlake: try to setup display ref clock before DPLL
8304 * enabling. This is only under driver's control after
8305 * PCH B stepping, previous chipset stepping should be
8306 * ignoring this setting.
8307 */
8308 val = I915_READ(PCH_DREF_CONTROL);
8309
8310 /* As we must carefully and slowly disable/enable each source in turn,
8311 * compute the final state we want first and check if we need to
8312 * make any changes at all.
8313 */
8314 final = val;
8315 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8316 if (has_ck505)
8317 final |= DREF_NONSPREAD_CK505_ENABLE;
8318 else
8319 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8320
8321 final &= ~DREF_SSC_SOURCE_MASK;
8322 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8323 final &= ~DREF_SSC1_ENABLE;
8324
8325 if (has_panel) {
8326 final |= DREF_SSC_SOURCE_ENABLE;
8327
8328 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8329 final |= DREF_SSC1_ENABLE;
8330
8331 if (has_cpu_edp) {
8332 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8333 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8334 else
8335 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8336 } else
8337 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8338 } else {
8339 final |= DREF_SSC_SOURCE_DISABLE;
8340 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8341 }
8342
8343 if (final == val)
8344 return;
8345
8346 /* Always enable nonspread source */
8347 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8348
8349 if (has_ck505)
8350 val |= DREF_NONSPREAD_CK505_ENABLE;
8351 else
8352 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8353
8354 if (has_panel) {
8355 val &= ~DREF_SSC_SOURCE_MASK;
8356 val |= DREF_SSC_SOURCE_ENABLE;
8357
8358 /* SSC must be turned on before enabling the CPU output */
8359 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8360 DRM_DEBUG_KMS("Using SSC on panel\n");
8361 val |= DREF_SSC1_ENABLE;
8362 } else
8363 val &= ~DREF_SSC1_ENABLE;
8364
8365 /* Get SSC going before enabling the outputs */
8366 I915_WRITE(PCH_DREF_CONTROL, val);
8367 POSTING_READ(PCH_DREF_CONTROL);
8368 udelay(200);
8369
8370 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8371
8372 /* Enable CPU source on CPU attached eDP */
8373 if (has_cpu_edp) {
8374 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8375 DRM_DEBUG_KMS("Using SSC on eDP\n");
8376 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8377 } else
8378 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8379 } else
8380 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8381
8382 I915_WRITE(PCH_DREF_CONTROL, val);
8383 POSTING_READ(PCH_DREF_CONTROL);
8384 udelay(200);
8385 } else {
8386 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8387
8388 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8389
8390 /* Turn off CPU output */
8391 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8392
8393 I915_WRITE(PCH_DREF_CONTROL, val);
8394 POSTING_READ(PCH_DREF_CONTROL);
8395 udelay(200);
8396
8397 /* Turn off the SSC source */
8398 val &= ~DREF_SSC_SOURCE_MASK;
8399 val |= DREF_SSC_SOURCE_DISABLE;
8400
8401 /* Turn off SSC1 */
8402 val &= ~DREF_SSC1_ENABLE;
8403
8404 I915_WRITE(PCH_DREF_CONTROL, val);
8405 POSTING_READ(PCH_DREF_CONTROL);
8406 udelay(200);
8407 }
8408
8409 BUG_ON(val != final);
8410 }
8411
8412 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8413 {
8414 uint32_t tmp;
8415
8416 tmp = I915_READ(SOUTH_CHICKEN2);
8417 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8418 I915_WRITE(SOUTH_CHICKEN2, tmp);
8419
8420 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8421 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8422 DRM_ERROR("FDI mPHY reset assert timeout\n");
8423
8424 tmp = I915_READ(SOUTH_CHICKEN2);
8425 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8426 I915_WRITE(SOUTH_CHICKEN2, tmp);
8427
8428 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8429 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8430 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8431 }
8432
8433 /* WaMPhyProgramming:hsw */
8434 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8435 {
8436 uint32_t tmp;
8437
8438 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8439 tmp &= ~(0xFF << 24);
8440 tmp |= (0x12 << 24);
8441 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8442
8443 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8444 tmp |= (1 << 11);
8445 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8446
8447 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8448 tmp |= (1 << 11);
8449 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8450
8451 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8452 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8453 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8454
8455 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8456 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8457 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8458
8459 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8460 tmp &= ~(7 << 13);
8461 tmp |= (5 << 13);
8462 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8463
8464 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8465 tmp &= ~(7 << 13);
8466 tmp |= (5 << 13);
8467 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8468
8469 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8470 tmp &= ~0xFF;
8471 tmp |= 0x1C;
8472 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8473
8474 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8475 tmp &= ~0xFF;
8476 tmp |= 0x1C;
8477 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8478
8479 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8480 tmp &= ~(0xFF << 16);
8481 tmp |= (0x1C << 16);
8482 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8483
8484 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8485 tmp &= ~(0xFF << 16);
8486 tmp |= (0x1C << 16);
8487 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8488
8489 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8490 tmp |= (1 << 27);
8491 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8492
8493 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8494 tmp |= (1 << 27);
8495 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8496
8497 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8498 tmp &= ~(0xF << 28);
8499 tmp |= (4 << 28);
8500 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8501
8502 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8503 tmp &= ~(0xF << 28);
8504 tmp |= (4 << 28);
8505 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8506 }
8507
8508 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8509 * Programming" based on the parameters passed:
8510 * - Sequence to enable CLKOUT_DP
8511 * - Sequence to enable CLKOUT_DP without spread
8512 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8513 */
8514 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8515 bool with_fdi)
8516 {
8517 struct drm_i915_private *dev_priv = dev->dev_private;
8518 uint32_t reg, tmp;
8519
8520 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8521 with_spread = true;
8522 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8523 with_fdi = false;
8524
8525 mutex_lock(&dev_priv->sb_lock);
8526
8527 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8528 tmp &= ~SBI_SSCCTL_DISABLE;
8529 tmp |= SBI_SSCCTL_PATHALT;
8530 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8531
8532 udelay(24);
8533
8534 if (with_spread) {
8535 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8536 tmp &= ~SBI_SSCCTL_PATHALT;
8537 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8538
8539 if (with_fdi) {
8540 lpt_reset_fdi_mphy(dev_priv);
8541 lpt_program_fdi_mphy(dev_priv);
8542 }
8543 }
8544
8545 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8546 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8547 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8548 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8549
8550 mutex_unlock(&dev_priv->sb_lock);
8551 }
8552
8553 /* Sequence to disable CLKOUT_DP */
8554 static void lpt_disable_clkout_dp(struct drm_device *dev)
8555 {
8556 struct drm_i915_private *dev_priv = dev->dev_private;
8557 uint32_t reg, tmp;
8558
8559 mutex_lock(&dev_priv->sb_lock);
8560
8561 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8562 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8563 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8564 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8565
8566 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8567 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8568 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8569 tmp |= SBI_SSCCTL_PATHALT;
8570 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8571 udelay(32);
8572 }
8573 tmp |= SBI_SSCCTL_DISABLE;
8574 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8575 }
8576
8577 mutex_unlock(&dev_priv->sb_lock);
8578 }
8579
8580 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8581
8582 static const uint16_t sscdivintphase[] = {
8583 [BEND_IDX( 50)] = 0x3B23,
8584 [BEND_IDX( 45)] = 0x3B23,
8585 [BEND_IDX( 40)] = 0x3C23,
8586 [BEND_IDX( 35)] = 0x3C23,
8587 [BEND_IDX( 30)] = 0x3D23,
8588 [BEND_IDX( 25)] = 0x3D23,
8589 [BEND_IDX( 20)] = 0x3E23,
8590 [BEND_IDX( 15)] = 0x3E23,
8591 [BEND_IDX( 10)] = 0x3F23,
8592 [BEND_IDX( 5)] = 0x3F23,
8593 [BEND_IDX( 0)] = 0x0025,
8594 [BEND_IDX( -5)] = 0x0025,
8595 [BEND_IDX(-10)] = 0x0125,
8596 [BEND_IDX(-15)] = 0x0125,
8597 [BEND_IDX(-20)] = 0x0225,
8598 [BEND_IDX(-25)] = 0x0225,
8599 [BEND_IDX(-30)] = 0x0325,
8600 [BEND_IDX(-35)] = 0x0325,
8601 [BEND_IDX(-40)] = 0x0425,
8602 [BEND_IDX(-45)] = 0x0425,
8603 [BEND_IDX(-50)] = 0x0525,
8604 };
8605
8606 /*
8607 * Bend CLKOUT_DP
8608 * steps -50 to 50 inclusive, in steps of 5
8609 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8610 * change in clock period = -(steps / 10) * 5.787 ps
8611 */
8612 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8613 {
8614 uint32_t tmp;
8615 int idx = BEND_IDX(steps);
8616
8617 if (WARN_ON(steps % 5 != 0))
8618 return;
8619
8620 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8621 return;
8622
8623 mutex_lock(&dev_priv->sb_lock);
8624
8625 if (steps % 10 != 0)
8626 tmp = 0xAAAAAAAB;
8627 else
8628 tmp = 0x00000000;
8629 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8630
8631 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8632 tmp &= 0xffff0000;
8633 tmp |= sscdivintphase[idx];
8634 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8635
8636 mutex_unlock(&dev_priv->sb_lock);
8637 }
8638
8639 #undef BEND_IDX
8640
8641 static void lpt_init_pch_refclk(struct drm_device *dev)
8642 {
8643 struct intel_encoder *encoder;
8644 bool has_vga = false;
8645
8646 for_each_intel_encoder(dev, encoder) {
8647 switch (encoder->type) {
8648 case INTEL_OUTPUT_ANALOG:
8649 has_vga = true;
8650 break;
8651 default:
8652 break;
8653 }
8654 }
8655
8656 if (has_vga) {
8657 lpt_bend_clkout_dp(to_i915(dev), 0);
8658 lpt_enable_clkout_dp(dev, true, true);
8659 } else {
8660 lpt_disable_clkout_dp(dev);
8661 }
8662 }
8663
8664 /*
8665 * Initialize reference clocks when the driver loads
8666 */
8667 void intel_init_pch_refclk(struct drm_device *dev)
8668 {
8669 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8670 ironlake_init_pch_refclk(dev);
8671 else if (HAS_PCH_LPT(dev))
8672 lpt_init_pch_refclk(dev);
8673 }
8674
8675 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8676 {
8677 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8679 int pipe = intel_crtc->pipe;
8680 uint32_t val;
8681
8682 val = 0;
8683
8684 switch (intel_crtc->config->pipe_bpp) {
8685 case 18:
8686 val |= PIPECONF_6BPC;
8687 break;
8688 case 24:
8689 val |= PIPECONF_8BPC;
8690 break;
8691 case 30:
8692 val |= PIPECONF_10BPC;
8693 break;
8694 case 36:
8695 val |= PIPECONF_12BPC;
8696 break;
8697 default:
8698 /* Case prevented by intel_choose_pipe_bpp_dither. */
8699 BUG();
8700 }
8701
8702 if (intel_crtc->config->dither)
8703 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8704
8705 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8706 val |= PIPECONF_INTERLACED_ILK;
8707 else
8708 val |= PIPECONF_PROGRESSIVE;
8709
8710 if (intel_crtc->config->limited_color_range)
8711 val |= PIPECONF_COLOR_RANGE_SELECT;
8712
8713 I915_WRITE(PIPECONF(pipe), val);
8714 POSTING_READ(PIPECONF(pipe));
8715 }
8716
8717 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8718 {
8719 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8721 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8722 u32 val = 0;
8723
8724 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8725 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8726
8727 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8728 val |= PIPECONF_INTERLACED_ILK;
8729 else
8730 val |= PIPECONF_PROGRESSIVE;
8731
8732 I915_WRITE(PIPECONF(cpu_transcoder), val);
8733 POSTING_READ(PIPECONF(cpu_transcoder));
8734 }
8735
8736 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8737 {
8738 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8740
8741 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8742 u32 val = 0;
8743
8744 switch (intel_crtc->config->pipe_bpp) {
8745 case 18:
8746 val |= PIPEMISC_DITHER_6_BPC;
8747 break;
8748 case 24:
8749 val |= PIPEMISC_DITHER_8_BPC;
8750 break;
8751 case 30:
8752 val |= PIPEMISC_DITHER_10_BPC;
8753 break;
8754 case 36:
8755 val |= PIPEMISC_DITHER_12_BPC;
8756 break;
8757 default:
8758 /* Case prevented by pipe_config_set_bpp. */
8759 BUG();
8760 }
8761
8762 if (intel_crtc->config->dither)
8763 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8764
8765 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8766 }
8767 }
8768
8769 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8770 {
8771 /*
8772 * Account for spread spectrum to avoid
8773 * oversubscribing the link. Max center spread
8774 * is 2.5%; use 5% for safety's sake.
8775 */
8776 u32 bps = target_clock * bpp * 21 / 20;
8777 return DIV_ROUND_UP(bps, link_bw * 8);
8778 }
8779
8780 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8781 {
8782 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8783 }
8784
8785 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8786 struct intel_crtc_state *crtc_state,
8787 struct dpll *reduced_clock)
8788 {
8789 struct drm_crtc *crtc = &intel_crtc->base;
8790 struct drm_device *dev = crtc->dev;
8791 struct drm_i915_private *dev_priv = dev->dev_private;
8792 struct drm_atomic_state *state = crtc_state->base.state;
8793 struct drm_connector *connector;
8794 struct drm_connector_state *connector_state;
8795 struct intel_encoder *encoder;
8796 u32 dpll, fp, fp2;
8797 int factor, i;
8798 bool is_lvds = false, is_sdvo = false;
8799
8800 for_each_connector_in_state(state, connector, connector_state, i) {
8801 if (connector_state->crtc != crtc_state->base.crtc)
8802 continue;
8803
8804 encoder = to_intel_encoder(connector_state->best_encoder);
8805
8806 switch (encoder->type) {
8807 case INTEL_OUTPUT_LVDS:
8808 is_lvds = true;
8809 break;
8810 case INTEL_OUTPUT_SDVO:
8811 case INTEL_OUTPUT_HDMI:
8812 is_sdvo = true;
8813 break;
8814 default:
8815 break;
8816 }
8817 }
8818
8819 /* Enable autotuning of the PLL clock (if permissible) */
8820 factor = 21;
8821 if (is_lvds) {
8822 if ((intel_panel_use_ssc(dev_priv) &&
8823 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8824 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8825 factor = 25;
8826 } else if (crtc_state->sdvo_tv_clock)
8827 factor = 20;
8828
8829 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8830
8831 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8832 fp |= FP_CB_TUNE;
8833
8834 if (reduced_clock) {
8835 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8836
8837 if (reduced_clock->m < factor * reduced_clock->n)
8838 fp2 |= FP_CB_TUNE;
8839 } else {
8840 fp2 = fp;
8841 }
8842
8843 dpll = 0;
8844
8845 if (is_lvds)
8846 dpll |= DPLLB_MODE_LVDS;
8847 else
8848 dpll |= DPLLB_MODE_DAC_SERIAL;
8849
8850 dpll |= (crtc_state->pixel_multiplier - 1)
8851 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8852
8853 if (is_sdvo)
8854 dpll |= DPLL_SDVO_HIGH_SPEED;
8855 if (crtc_state->has_dp_encoder)
8856 dpll |= DPLL_SDVO_HIGH_SPEED;
8857
8858 /* compute bitmask from p1 value */
8859 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8860 /* also FPA1 */
8861 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8862
8863 switch (crtc_state->dpll.p2) {
8864 case 5:
8865 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8866 break;
8867 case 7:
8868 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8869 break;
8870 case 10:
8871 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8872 break;
8873 case 14:
8874 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8875 break;
8876 }
8877
8878 if (is_lvds && intel_panel_use_ssc(dev_priv))
8879 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8880 else
8881 dpll |= PLL_REF_INPUT_DREFCLK;
8882
8883 dpll |= DPLL_VCO_ENABLE;
8884
8885 crtc_state->dpll_hw_state.dpll = dpll;
8886 crtc_state->dpll_hw_state.fp0 = fp;
8887 crtc_state->dpll_hw_state.fp1 = fp2;
8888 }
8889
8890 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8891 struct intel_crtc_state *crtc_state)
8892 {
8893 struct drm_device *dev = crtc->base.dev;
8894 struct drm_i915_private *dev_priv = dev->dev_private;
8895 struct dpll reduced_clock;
8896 bool has_reduced_clock = false;
8897 struct intel_shared_dpll *pll;
8898 const struct intel_limit *limit;
8899 int refclk = 120000;
8900
8901 memset(&crtc_state->dpll_hw_state, 0,
8902 sizeof(crtc_state->dpll_hw_state));
8903
8904 crtc->lowfreq_avail = false;
8905
8906 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8907 if (!crtc_state->has_pch_encoder)
8908 return 0;
8909
8910 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8911 if (intel_panel_use_ssc(dev_priv)) {
8912 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8913 dev_priv->vbt.lvds_ssc_freq);
8914 refclk = dev_priv->vbt.lvds_ssc_freq;
8915 }
8916
8917 if (intel_is_dual_link_lvds(dev)) {
8918 if (refclk == 100000)
8919 limit = &intel_limits_ironlake_dual_lvds_100m;
8920 else
8921 limit = &intel_limits_ironlake_dual_lvds;
8922 } else {
8923 if (refclk == 100000)
8924 limit = &intel_limits_ironlake_single_lvds_100m;
8925 else
8926 limit = &intel_limits_ironlake_single_lvds;
8927 }
8928 } else {
8929 limit = &intel_limits_ironlake_dac;
8930 }
8931
8932 if (!crtc_state->clock_set &&
8933 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8934 refclk, NULL, &crtc_state->dpll)) {
8935 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8936 return -EINVAL;
8937 }
8938
8939 ironlake_compute_dpll(crtc, crtc_state,
8940 has_reduced_clock ? &reduced_clock : NULL);
8941
8942 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8943 if (pll == NULL) {
8944 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8945 pipe_name(crtc->pipe));
8946 return -EINVAL;
8947 }
8948
8949 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8950 has_reduced_clock)
8951 crtc->lowfreq_avail = true;
8952
8953 return 0;
8954 }
8955
8956 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8957 struct intel_link_m_n *m_n)
8958 {
8959 struct drm_device *dev = crtc->base.dev;
8960 struct drm_i915_private *dev_priv = dev->dev_private;
8961 enum pipe pipe = crtc->pipe;
8962
8963 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8964 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8965 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8966 & ~TU_SIZE_MASK;
8967 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8968 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8969 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8970 }
8971
8972 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8973 enum transcoder transcoder,
8974 struct intel_link_m_n *m_n,
8975 struct intel_link_m_n *m2_n2)
8976 {
8977 struct drm_device *dev = crtc->base.dev;
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 enum pipe pipe = crtc->pipe;
8980
8981 if (INTEL_INFO(dev)->gen >= 5) {
8982 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8983 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8984 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8985 & ~TU_SIZE_MASK;
8986 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8987 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8988 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8989 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8990 * gen < 8) and if DRRS is supported (to make sure the
8991 * registers are not unnecessarily read).
8992 */
8993 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8994 crtc->config->has_drrs) {
8995 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8996 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8997 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8998 & ~TU_SIZE_MASK;
8999 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9000 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9001 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9002 }
9003 } else {
9004 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9005 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9006 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9007 & ~TU_SIZE_MASK;
9008 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9009 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9010 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9011 }
9012 }
9013
9014 void intel_dp_get_m_n(struct intel_crtc *crtc,
9015 struct intel_crtc_state *pipe_config)
9016 {
9017 if (pipe_config->has_pch_encoder)
9018 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9019 else
9020 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9021 &pipe_config->dp_m_n,
9022 &pipe_config->dp_m2_n2);
9023 }
9024
9025 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9026 struct intel_crtc_state *pipe_config)
9027 {
9028 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9029 &pipe_config->fdi_m_n, NULL);
9030 }
9031
9032 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9033 struct intel_crtc_state *pipe_config)
9034 {
9035 struct drm_device *dev = crtc->base.dev;
9036 struct drm_i915_private *dev_priv = dev->dev_private;
9037 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9038 uint32_t ps_ctrl = 0;
9039 int id = -1;
9040 int i;
9041
9042 /* find scaler attached to this pipe */
9043 for (i = 0; i < crtc->num_scalers; i++) {
9044 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9045 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9046 id = i;
9047 pipe_config->pch_pfit.enabled = true;
9048 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9049 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9050 break;
9051 }
9052 }
9053
9054 scaler_state->scaler_id = id;
9055 if (id >= 0) {
9056 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9057 } else {
9058 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9059 }
9060 }
9061
9062 static void
9063 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9064 struct intel_initial_plane_config *plane_config)
9065 {
9066 struct drm_device *dev = crtc->base.dev;
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 u32 val, base, offset, stride_mult, tiling;
9069 int pipe = crtc->pipe;
9070 int fourcc, pixel_format;
9071 unsigned int aligned_height;
9072 struct drm_framebuffer *fb;
9073 struct intel_framebuffer *intel_fb;
9074
9075 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9076 if (!intel_fb) {
9077 DRM_DEBUG_KMS("failed to alloc fb\n");
9078 return;
9079 }
9080
9081 fb = &intel_fb->base;
9082
9083 val = I915_READ(PLANE_CTL(pipe, 0));
9084 if (!(val & PLANE_CTL_ENABLE))
9085 goto error;
9086
9087 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9088 fourcc = skl_format_to_fourcc(pixel_format,
9089 val & PLANE_CTL_ORDER_RGBX,
9090 val & PLANE_CTL_ALPHA_MASK);
9091 fb->pixel_format = fourcc;
9092 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9093
9094 tiling = val & PLANE_CTL_TILED_MASK;
9095 switch (tiling) {
9096 case PLANE_CTL_TILED_LINEAR:
9097 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9098 break;
9099 case PLANE_CTL_TILED_X:
9100 plane_config->tiling = I915_TILING_X;
9101 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9102 break;
9103 case PLANE_CTL_TILED_Y:
9104 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9105 break;
9106 case PLANE_CTL_TILED_YF:
9107 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9108 break;
9109 default:
9110 MISSING_CASE(tiling);
9111 goto error;
9112 }
9113
9114 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9115 plane_config->base = base;
9116
9117 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9118
9119 val = I915_READ(PLANE_SIZE(pipe, 0));
9120 fb->height = ((val >> 16) & 0xfff) + 1;
9121 fb->width = ((val >> 0) & 0x1fff) + 1;
9122
9123 val = I915_READ(PLANE_STRIDE(pipe, 0));
9124 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9125 fb->pixel_format);
9126 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9127
9128 aligned_height = intel_fb_align_height(dev, fb->height,
9129 fb->pixel_format,
9130 fb->modifier[0]);
9131
9132 plane_config->size = fb->pitches[0] * aligned_height;
9133
9134 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9135 pipe_name(pipe), fb->width, fb->height,
9136 fb->bits_per_pixel, base, fb->pitches[0],
9137 plane_config->size);
9138
9139 plane_config->fb = intel_fb;
9140 return;
9141
9142 error:
9143 kfree(fb);
9144 }
9145
9146 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9147 struct intel_crtc_state *pipe_config)
9148 {
9149 struct drm_device *dev = crtc->base.dev;
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151 uint32_t tmp;
9152
9153 tmp = I915_READ(PF_CTL(crtc->pipe));
9154
9155 if (tmp & PF_ENABLE) {
9156 pipe_config->pch_pfit.enabled = true;
9157 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9158 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9159
9160 /* We currently do not free assignements of panel fitters on
9161 * ivb/hsw (since we don't use the higher upscaling modes which
9162 * differentiates them) so just WARN about this case for now. */
9163 if (IS_GEN7(dev)) {
9164 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9165 PF_PIPE_SEL_IVB(crtc->pipe));
9166 }
9167 }
9168 }
9169
9170 static void
9171 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9172 struct intel_initial_plane_config *plane_config)
9173 {
9174 struct drm_device *dev = crtc->base.dev;
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176 u32 val, base, offset;
9177 int pipe = crtc->pipe;
9178 int fourcc, pixel_format;
9179 unsigned int aligned_height;
9180 struct drm_framebuffer *fb;
9181 struct intel_framebuffer *intel_fb;
9182
9183 val = I915_READ(DSPCNTR(pipe));
9184 if (!(val & DISPLAY_PLANE_ENABLE))
9185 return;
9186
9187 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9188 if (!intel_fb) {
9189 DRM_DEBUG_KMS("failed to alloc fb\n");
9190 return;
9191 }
9192
9193 fb = &intel_fb->base;
9194
9195 if (INTEL_INFO(dev)->gen >= 4) {
9196 if (val & DISPPLANE_TILED) {
9197 plane_config->tiling = I915_TILING_X;
9198 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9199 }
9200 }
9201
9202 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9203 fourcc = i9xx_format_to_fourcc(pixel_format);
9204 fb->pixel_format = fourcc;
9205 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9206
9207 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9208 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9209 offset = I915_READ(DSPOFFSET(pipe));
9210 } else {
9211 if (plane_config->tiling)
9212 offset = I915_READ(DSPTILEOFF(pipe));
9213 else
9214 offset = I915_READ(DSPLINOFF(pipe));
9215 }
9216 plane_config->base = base;
9217
9218 val = I915_READ(PIPESRC(pipe));
9219 fb->width = ((val >> 16) & 0xfff) + 1;
9220 fb->height = ((val >> 0) & 0xfff) + 1;
9221
9222 val = I915_READ(DSPSTRIDE(pipe));
9223 fb->pitches[0] = val & 0xffffffc0;
9224
9225 aligned_height = intel_fb_align_height(dev, fb->height,
9226 fb->pixel_format,
9227 fb->modifier[0]);
9228
9229 plane_config->size = fb->pitches[0] * aligned_height;
9230
9231 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9232 pipe_name(pipe), fb->width, fb->height,
9233 fb->bits_per_pixel, base, fb->pitches[0],
9234 plane_config->size);
9235
9236 plane_config->fb = intel_fb;
9237 }
9238
9239 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9240 struct intel_crtc_state *pipe_config)
9241 {
9242 struct drm_device *dev = crtc->base.dev;
9243 struct drm_i915_private *dev_priv = dev->dev_private;
9244 enum intel_display_power_domain power_domain;
9245 uint32_t tmp;
9246 bool ret;
9247
9248 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9249 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9250 return false;
9251
9252 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9253 pipe_config->shared_dpll = NULL;
9254
9255 ret = false;
9256 tmp = I915_READ(PIPECONF(crtc->pipe));
9257 if (!(tmp & PIPECONF_ENABLE))
9258 goto out;
9259
9260 switch (tmp & PIPECONF_BPC_MASK) {
9261 case PIPECONF_6BPC:
9262 pipe_config->pipe_bpp = 18;
9263 break;
9264 case PIPECONF_8BPC:
9265 pipe_config->pipe_bpp = 24;
9266 break;
9267 case PIPECONF_10BPC:
9268 pipe_config->pipe_bpp = 30;
9269 break;
9270 case PIPECONF_12BPC:
9271 pipe_config->pipe_bpp = 36;
9272 break;
9273 default:
9274 break;
9275 }
9276
9277 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9278 pipe_config->limited_color_range = true;
9279
9280 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9281 struct intel_shared_dpll *pll;
9282 enum intel_dpll_id pll_id;
9283
9284 pipe_config->has_pch_encoder = true;
9285
9286 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9287 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9288 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9289
9290 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9291
9292 if (HAS_PCH_IBX(dev_priv)) {
9293 /*
9294 * The pipe->pch transcoder and pch transcoder->pll
9295 * mapping is fixed.
9296 */
9297 pll_id = (enum intel_dpll_id) crtc->pipe;
9298 } else {
9299 tmp = I915_READ(PCH_DPLL_SEL);
9300 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9301 pll_id = DPLL_ID_PCH_PLL_B;
9302 else
9303 pll_id= DPLL_ID_PCH_PLL_A;
9304 }
9305
9306 pipe_config->shared_dpll =
9307 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9308 pll = pipe_config->shared_dpll;
9309
9310 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9311 &pipe_config->dpll_hw_state));
9312
9313 tmp = pipe_config->dpll_hw_state.dpll;
9314 pipe_config->pixel_multiplier =
9315 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9316 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9317
9318 ironlake_pch_clock_get(crtc, pipe_config);
9319 } else {
9320 pipe_config->pixel_multiplier = 1;
9321 }
9322
9323 intel_get_pipe_timings(crtc, pipe_config);
9324 intel_get_pipe_src_size(crtc, pipe_config);
9325
9326 ironlake_get_pfit_config(crtc, pipe_config);
9327
9328 ret = true;
9329
9330 out:
9331 intel_display_power_put(dev_priv, power_domain);
9332
9333 return ret;
9334 }
9335
9336 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9337 {
9338 struct drm_device *dev = dev_priv->dev;
9339 struct intel_crtc *crtc;
9340
9341 for_each_intel_crtc(dev, crtc)
9342 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9343 pipe_name(crtc->pipe));
9344
9345 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9346 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9347 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9348 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9349 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9350 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9351 "CPU PWM1 enabled\n");
9352 if (IS_HASWELL(dev))
9353 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9354 "CPU PWM2 enabled\n");
9355 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9356 "PCH PWM1 enabled\n");
9357 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9358 "Utility pin enabled\n");
9359 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9360
9361 /*
9362 * In theory we can still leave IRQs enabled, as long as only the HPD
9363 * interrupts remain enabled. We used to check for that, but since it's
9364 * gen-specific and since we only disable LCPLL after we fully disable
9365 * the interrupts, the check below should be enough.
9366 */
9367 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9368 }
9369
9370 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9371 {
9372 struct drm_device *dev = dev_priv->dev;
9373
9374 if (IS_HASWELL(dev))
9375 return I915_READ(D_COMP_HSW);
9376 else
9377 return I915_READ(D_COMP_BDW);
9378 }
9379
9380 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9381 {
9382 struct drm_device *dev = dev_priv->dev;
9383
9384 if (IS_HASWELL(dev)) {
9385 mutex_lock(&dev_priv->rps.hw_lock);
9386 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9387 val))
9388 DRM_ERROR("Failed to write to D_COMP\n");
9389 mutex_unlock(&dev_priv->rps.hw_lock);
9390 } else {
9391 I915_WRITE(D_COMP_BDW, val);
9392 POSTING_READ(D_COMP_BDW);
9393 }
9394 }
9395
9396 /*
9397 * This function implements pieces of two sequences from BSpec:
9398 * - Sequence for display software to disable LCPLL
9399 * - Sequence for display software to allow package C8+
9400 * The steps implemented here are just the steps that actually touch the LCPLL
9401 * register. Callers should take care of disabling all the display engine
9402 * functions, doing the mode unset, fixing interrupts, etc.
9403 */
9404 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9405 bool switch_to_fclk, bool allow_power_down)
9406 {
9407 uint32_t val;
9408
9409 assert_can_disable_lcpll(dev_priv);
9410
9411 val = I915_READ(LCPLL_CTL);
9412
9413 if (switch_to_fclk) {
9414 val |= LCPLL_CD_SOURCE_FCLK;
9415 I915_WRITE(LCPLL_CTL, val);
9416
9417 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9418 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9419 DRM_ERROR("Switching to FCLK failed\n");
9420
9421 val = I915_READ(LCPLL_CTL);
9422 }
9423
9424 val |= LCPLL_PLL_DISABLE;
9425 I915_WRITE(LCPLL_CTL, val);
9426 POSTING_READ(LCPLL_CTL);
9427
9428 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9429 DRM_ERROR("LCPLL still locked\n");
9430
9431 val = hsw_read_dcomp(dev_priv);
9432 val |= D_COMP_COMP_DISABLE;
9433 hsw_write_dcomp(dev_priv, val);
9434 ndelay(100);
9435
9436 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9437 1))
9438 DRM_ERROR("D_COMP RCOMP still in progress\n");
9439
9440 if (allow_power_down) {
9441 val = I915_READ(LCPLL_CTL);
9442 val |= LCPLL_POWER_DOWN_ALLOW;
9443 I915_WRITE(LCPLL_CTL, val);
9444 POSTING_READ(LCPLL_CTL);
9445 }
9446 }
9447
9448 /*
9449 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9450 * source.
9451 */
9452 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9453 {
9454 uint32_t val;
9455
9456 val = I915_READ(LCPLL_CTL);
9457
9458 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9459 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9460 return;
9461
9462 /*
9463 * Make sure we're not on PC8 state before disabling PC8, otherwise
9464 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9465 */
9466 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9467
9468 if (val & LCPLL_POWER_DOWN_ALLOW) {
9469 val &= ~LCPLL_POWER_DOWN_ALLOW;
9470 I915_WRITE(LCPLL_CTL, val);
9471 POSTING_READ(LCPLL_CTL);
9472 }
9473
9474 val = hsw_read_dcomp(dev_priv);
9475 val |= D_COMP_COMP_FORCE;
9476 val &= ~D_COMP_COMP_DISABLE;
9477 hsw_write_dcomp(dev_priv, val);
9478
9479 val = I915_READ(LCPLL_CTL);
9480 val &= ~LCPLL_PLL_DISABLE;
9481 I915_WRITE(LCPLL_CTL, val);
9482
9483 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9484 DRM_ERROR("LCPLL not locked yet\n");
9485
9486 if (val & LCPLL_CD_SOURCE_FCLK) {
9487 val = I915_READ(LCPLL_CTL);
9488 val &= ~LCPLL_CD_SOURCE_FCLK;
9489 I915_WRITE(LCPLL_CTL, val);
9490
9491 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9492 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9493 DRM_ERROR("Switching back to LCPLL failed\n");
9494 }
9495
9496 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9497 intel_update_cdclk(dev_priv->dev);
9498 }
9499
9500 /*
9501 * Package states C8 and deeper are really deep PC states that can only be
9502 * reached when all the devices on the system allow it, so even if the graphics
9503 * device allows PC8+, it doesn't mean the system will actually get to these
9504 * states. Our driver only allows PC8+ when going into runtime PM.
9505 *
9506 * The requirements for PC8+ are that all the outputs are disabled, the power
9507 * well is disabled and most interrupts are disabled, and these are also
9508 * requirements for runtime PM. When these conditions are met, we manually do
9509 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9510 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9511 * hang the machine.
9512 *
9513 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9514 * the state of some registers, so when we come back from PC8+ we need to
9515 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9516 * need to take care of the registers kept by RC6. Notice that this happens even
9517 * if we don't put the device in PCI D3 state (which is what currently happens
9518 * because of the runtime PM support).
9519 *
9520 * For more, read "Display Sequences for Package C8" on the hardware
9521 * documentation.
9522 */
9523 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9524 {
9525 struct drm_device *dev = dev_priv->dev;
9526 uint32_t val;
9527
9528 DRM_DEBUG_KMS("Enabling package C8+\n");
9529
9530 if (HAS_PCH_LPT_LP(dev)) {
9531 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9532 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9533 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9534 }
9535
9536 lpt_disable_clkout_dp(dev);
9537 hsw_disable_lcpll(dev_priv, true, true);
9538 }
9539
9540 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9541 {
9542 struct drm_device *dev = dev_priv->dev;
9543 uint32_t val;
9544
9545 DRM_DEBUG_KMS("Disabling package C8+\n");
9546
9547 hsw_restore_lcpll(dev_priv);
9548 lpt_init_pch_refclk(dev);
9549
9550 if (HAS_PCH_LPT_LP(dev)) {
9551 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9552 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9553 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9554 }
9555 }
9556
9557 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9558 {
9559 struct drm_device *dev = old_state->dev;
9560 struct intel_atomic_state *old_intel_state =
9561 to_intel_atomic_state(old_state);
9562 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9563
9564 broxton_set_cdclk(to_i915(dev), req_cdclk);
9565 }
9566
9567 /* compute the max rate for new configuration */
9568 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9569 {
9570 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9571 struct drm_i915_private *dev_priv = state->dev->dev_private;
9572 struct drm_crtc *crtc;
9573 struct drm_crtc_state *cstate;
9574 struct intel_crtc_state *crtc_state;
9575 unsigned max_pixel_rate = 0, i;
9576 enum pipe pipe;
9577
9578 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9579 sizeof(intel_state->min_pixclk));
9580
9581 for_each_crtc_in_state(state, crtc, cstate, i) {
9582 int pixel_rate;
9583
9584 crtc_state = to_intel_crtc_state(cstate);
9585 if (!crtc_state->base.enable) {
9586 intel_state->min_pixclk[i] = 0;
9587 continue;
9588 }
9589
9590 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9591
9592 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9593 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9594 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9595
9596 intel_state->min_pixclk[i] = pixel_rate;
9597 }
9598
9599 for_each_pipe(dev_priv, pipe)
9600 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9601
9602 return max_pixel_rate;
9603 }
9604
9605 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9606 {
9607 struct drm_i915_private *dev_priv = dev->dev_private;
9608 uint32_t val, data;
9609 int ret;
9610
9611 if (WARN((I915_READ(LCPLL_CTL) &
9612 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9613 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9614 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9615 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9616 "trying to change cdclk frequency with cdclk not enabled\n"))
9617 return;
9618
9619 mutex_lock(&dev_priv->rps.hw_lock);
9620 ret = sandybridge_pcode_write(dev_priv,
9621 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9622 mutex_unlock(&dev_priv->rps.hw_lock);
9623 if (ret) {
9624 DRM_ERROR("failed to inform pcode about cdclk change\n");
9625 return;
9626 }
9627
9628 val = I915_READ(LCPLL_CTL);
9629 val |= LCPLL_CD_SOURCE_FCLK;
9630 I915_WRITE(LCPLL_CTL, val);
9631
9632 if (wait_for_us(I915_READ(LCPLL_CTL) &
9633 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9634 DRM_ERROR("Switching to FCLK failed\n");
9635
9636 val = I915_READ(LCPLL_CTL);
9637 val &= ~LCPLL_CLK_FREQ_MASK;
9638
9639 switch (cdclk) {
9640 case 450000:
9641 val |= LCPLL_CLK_FREQ_450;
9642 data = 0;
9643 break;
9644 case 540000:
9645 val |= LCPLL_CLK_FREQ_54O_BDW;
9646 data = 1;
9647 break;
9648 case 337500:
9649 val |= LCPLL_CLK_FREQ_337_5_BDW;
9650 data = 2;
9651 break;
9652 case 675000:
9653 val |= LCPLL_CLK_FREQ_675_BDW;
9654 data = 3;
9655 break;
9656 default:
9657 WARN(1, "invalid cdclk frequency\n");
9658 return;
9659 }
9660
9661 I915_WRITE(LCPLL_CTL, val);
9662
9663 val = I915_READ(LCPLL_CTL);
9664 val &= ~LCPLL_CD_SOURCE_FCLK;
9665 I915_WRITE(LCPLL_CTL, val);
9666
9667 if (wait_for_us((I915_READ(LCPLL_CTL) &
9668 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9669 DRM_ERROR("Switching back to LCPLL failed\n");
9670
9671 mutex_lock(&dev_priv->rps.hw_lock);
9672 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9673 mutex_unlock(&dev_priv->rps.hw_lock);
9674
9675 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9676
9677 intel_update_cdclk(dev);
9678
9679 WARN(cdclk != dev_priv->cdclk_freq,
9680 "cdclk requested %d kHz but got %d kHz\n",
9681 cdclk, dev_priv->cdclk_freq);
9682 }
9683
9684 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9685 {
9686 struct drm_i915_private *dev_priv = to_i915(state->dev);
9687 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9688 int max_pixclk = ilk_max_pixel_rate(state);
9689 int cdclk;
9690
9691 /*
9692 * FIXME should also account for plane ratio
9693 * once 64bpp pixel formats are supported.
9694 */
9695 if (max_pixclk > 540000)
9696 cdclk = 675000;
9697 else if (max_pixclk > 450000)
9698 cdclk = 540000;
9699 else if (max_pixclk > 337500)
9700 cdclk = 450000;
9701 else
9702 cdclk = 337500;
9703
9704 if (cdclk > dev_priv->max_cdclk_freq) {
9705 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9706 cdclk, dev_priv->max_cdclk_freq);
9707 return -EINVAL;
9708 }
9709
9710 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9711 if (!intel_state->active_crtcs)
9712 intel_state->dev_cdclk = 337500;
9713
9714 return 0;
9715 }
9716
9717 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9718 {
9719 struct drm_device *dev = old_state->dev;
9720 struct intel_atomic_state *old_intel_state =
9721 to_intel_atomic_state(old_state);
9722 unsigned req_cdclk = old_intel_state->dev_cdclk;
9723
9724 broadwell_set_cdclk(dev, req_cdclk);
9725 }
9726
9727 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9728 struct intel_crtc_state *crtc_state)
9729 {
9730 struct intel_encoder *intel_encoder =
9731 intel_ddi_get_crtc_new_encoder(crtc_state);
9732
9733 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9734 if (!intel_ddi_pll_select(crtc, crtc_state))
9735 return -EINVAL;
9736 }
9737
9738 crtc->lowfreq_avail = false;
9739
9740 return 0;
9741 }
9742
9743 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9744 enum port port,
9745 struct intel_crtc_state *pipe_config)
9746 {
9747 enum intel_dpll_id id;
9748
9749 switch (port) {
9750 case PORT_A:
9751 pipe_config->ddi_pll_sel = SKL_DPLL0;
9752 id = DPLL_ID_SKL_DPLL0;
9753 break;
9754 case PORT_B:
9755 pipe_config->ddi_pll_sel = SKL_DPLL1;
9756 id = DPLL_ID_SKL_DPLL1;
9757 break;
9758 case PORT_C:
9759 pipe_config->ddi_pll_sel = SKL_DPLL2;
9760 id = DPLL_ID_SKL_DPLL2;
9761 break;
9762 default:
9763 DRM_ERROR("Incorrect port type\n");
9764 return;
9765 }
9766
9767 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9768 }
9769
9770 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9771 enum port port,
9772 struct intel_crtc_state *pipe_config)
9773 {
9774 enum intel_dpll_id id;
9775 u32 temp;
9776
9777 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9778 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9779
9780 switch (pipe_config->ddi_pll_sel) {
9781 case SKL_DPLL0:
9782 id = DPLL_ID_SKL_DPLL0;
9783 break;
9784 case SKL_DPLL1:
9785 id = DPLL_ID_SKL_DPLL1;
9786 break;
9787 case SKL_DPLL2:
9788 id = DPLL_ID_SKL_DPLL2;
9789 break;
9790 case SKL_DPLL3:
9791 id = DPLL_ID_SKL_DPLL3;
9792 break;
9793 default:
9794 MISSING_CASE(pipe_config->ddi_pll_sel);
9795 return;
9796 }
9797
9798 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9799 }
9800
9801 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9802 enum port port,
9803 struct intel_crtc_state *pipe_config)
9804 {
9805 enum intel_dpll_id id;
9806
9807 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9808
9809 switch (pipe_config->ddi_pll_sel) {
9810 case PORT_CLK_SEL_WRPLL1:
9811 id = DPLL_ID_WRPLL1;
9812 break;
9813 case PORT_CLK_SEL_WRPLL2:
9814 id = DPLL_ID_WRPLL2;
9815 break;
9816 case PORT_CLK_SEL_SPLL:
9817 id = DPLL_ID_SPLL;
9818 break;
9819 case PORT_CLK_SEL_LCPLL_810:
9820 id = DPLL_ID_LCPLL_810;
9821 break;
9822 case PORT_CLK_SEL_LCPLL_1350:
9823 id = DPLL_ID_LCPLL_1350;
9824 break;
9825 case PORT_CLK_SEL_LCPLL_2700:
9826 id = DPLL_ID_LCPLL_2700;
9827 break;
9828 default:
9829 MISSING_CASE(pipe_config->ddi_pll_sel);
9830 /* fall through */
9831 case PORT_CLK_SEL_NONE:
9832 return;
9833 }
9834
9835 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9836 }
9837
9838 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9839 struct intel_crtc_state *pipe_config,
9840 unsigned long *power_domain_mask)
9841 {
9842 struct drm_device *dev = crtc->base.dev;
9843 struct drm_i915_private *dev_priv = dev->dev_private;
9844 enum intel_display_power_domain power_domain;
9845 u32 tmp;
9846
9847 /*
9848 * The pipe->transcoder mapping is fixed with the exception of the eDP
9849 * transcoder handled below.
9850 */
9851 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9852
9853 /*
9854 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9855 * consistency and less surprising code; it's in always on power).
9856 */
9857 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9858 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9859 enum pipe trans_edp_pipe;
9860 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9861 default:
9862 WARN(1, "unknown pipe linked to edp transcoder\n");
9863 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9864 case TRANS_DDI_EDP_INPUT_A_ON:
9865 trans_edp_pipe = PIPE_A;
9866 break;
9867 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9868 trans_edp_pipe = PIPE_B;
9869 break;
9870 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9871 trans_edp_pipe = PIPE_C;
9872 break;
9873 }
9874
9875 if (trans_edp_pipe == crtc->pipe)
9876 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9877 }
9878
9879 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9880 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9881 return false;
9882 *power_domain_mask |= BIT(power_domain);
9883
9884 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9885
9886 return tmp & PIPECONF_ENABLE;
9887 }
9888
9889 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9890 struct intel_crtc_state *pipe_config,
9891 unsigned long *power_domain_mask)
9892 {
9893 struct drm_device *dev = crtc->base.dev;
9894 struct drm_i915_private *dev_priv = dev->dev_private;
9895 enum intel_display_power_domain power_domain;
9896 enum port port;
9897 enum transcoder cpu_transcoder;
9898 u32 tmp;
9899
9900 pipe_config->has_dsi_encoder = false;
9901
9902 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9903 if (port == PORT_A)
9904 cpu_transcoder = TRANSCODER_DSI_A;
9905 else
9906 cpu_transcoder = TRANSCODER_DSI_C;
9907
9908 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9909 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9910 continue;
9911 *power_domain_mask |= BIT(power_domain);
9912
9913 /*
9914 * The PLL needs to be enabled with a valid divider
9915 * configuration, otherwise accessing DSI registers will hang
9916 * the machine. See BSpec North Display Engine
9917 * registers/MIPI[BXT]. We can break out here early, since we
9918 * need the same DSI PLL to be enabled for both DSI ports.
9919 */
9920 if (!intel_dsi_pll_is_enabled(dev_priv))
9921 break;
9922
9923 /* XXX: this works for video mode only */
9924 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9925 if (!(tmp & DPI_ENABLE))
9926 continue;
9927
9928 tmp = I915_READ(MIPI_CTRL(port));
9929 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9930 continue;
9931
9932 pipe_config->cpu_transcoder = cpu_transcoder;
9933 pipe_config->has_dsi_encoder = true;
9934 break;
9935 }
9936
9937 return pipe_config->has_dsi_encoder;
9938 }
9939
9940 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9941 struct intel_crtc_state *pipe_config)
9942 {
9943 struct drm_device *dev = crtc->base.dev;
9944 struct drm_i915_private *dev_priv = dev->dev_private;
9945 struct intel_shared_dpll *pll;
9946 enum port port;
9947 uint32_t tmp;
9948
9949 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9950
9951 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9952
9953 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9954 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9955 else if (IS_BROXTON(dev))
9956 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9957 else
9958 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9959
9960 pll = pipe_config->shared_dpll;
9961 if (pll) {
9962 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9963 &pipe_config->dpll_hw_state));
9964 }
9965
9966 /*
9967 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9968 * DDI E. So just check whether this pipe is wired to DDI E and whether
9969 * the PCH transcoder is on.
9970 */
9971 if (INTEL_INFO(dev)->gen < 9 &&
9972 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9973 pipe_config->has_pch_encoder = true;
9974
9975 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9976 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9977 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9978
9979 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9980 }
9981 }
9982
9983 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9984 struct intel_crtc_state *pipe_config)
9985 {
9986 struct drm_device *dev = crtc->base.dev;
9987 struct drm_i915_private *dev_priv = dev->dev_private;
9988 enum intel_display_power_domain power_domain;
9989 unsigned long power_domain_mask;
9990 bool active;
9991
9992 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9993 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9994 return false;
9995 power_domain_mask = BIT(power_domain);
9996
9997 pipe_config->shared_dpll = NULL;
9998
9999 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10000
10001 if (IS_BROXTON(dev_priv)) {
10002 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10003 &power_domain_mask);
10004 WARN_ON(active && pipe_config->has_dsi_encoder);
10005 if (pipe_config->has_dsi_encoder)
10006 active = true;
10007 }
10008
10009 if (!active)
10010 goto out;
10011
10012 if (!pipe_config->has_dsi_encoder) {
10013 haswell_get_ddi_port_state(crtc, pipe_config);
10014 intel_get_pipe_timings(crtc, pipe_config);
10015 }
10016
10017 intel_get_pipe_src_size(crtc, pipe_config);
10018
10019 pipe_config->gamma_mode =
10020 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10021
10022 if (INTEL_INFO(dev)->gen >= 9) {
10023 skl_init_scalers(dev, crtc, pipe_config);
10024 }
10025
10026 if (INTEL_INFO(dev)->gen >= 9) {
10027 pipe_config->scaler_state.scaler_id = -1;
10028 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10029 }
10030
10031 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10032 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10033 power_domain_mask |= BIT(power_domain);
10034 if (INTEL_INFO(dev)->gen >= 9)
10035 skylake_get_pfit_config(crtc, pipe_config);
10036 else
10037 ironlake_get_pfit_config(crtc, pipe_config);
10038 }
10039
10040 if (IS_HASWELL(dev))
10041 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10042 (I915_READ(IPS_CTL) & IPS_ENABLE);
10043
10044 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10045 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10046 pipe_config->pixel_multiplier =
10047 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10048 } else {
10049 pipe_config->pixel_multiplier = 1;
10050 }
10051
10052 out:
10053 for_each_power_domain(power_domain, power_domain_mask)
10054 intel_display_power_put(dev_priv, power_domain);
10055
10056 return active;
10057 }
10058
10059 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10060 const struct intel_plane_state *plane_state)
10061 {
10062 struct drm_device *dev = crtc->dev;
10063 struct drm_i915_private *dev_priv = dev->dev_private;
10064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10065 uint32_t cntl = 0, size = 0;
10066
10067 if (plane_state && plane_state->visible) {
10068 unsigned int width = plane_state->base.crtc_w;
10069 unsigned int height = plane_state->base.crtc_h;
10070 unsigned int stride = roundup_pow_of_two(width) * 4;
10071
10072 switch (stride) {
10073 default:
10074 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10075 width, stride);
10076 stride = 256;
10077 /* fallthrough */
10078 case 256:
10079 case 512:
10080 case 1024:
10081 case 2048:
10082 break;
10083 }
10084
10085 cntl |= CURSOR_ENABLE |
10086 CURSOR_GAMMA_ENABLE |
10087 CURSOR_FORMAT_ARGB |
10088 CURSOR_STRIDE(stride);
10089
10090 size = (height << 12) | width;
10091 }
10092
10093 if (intel_crtc->cursor_cntl != 0 &&
10094 (intel_crtc->cursor_base != base ||
10095 intel_crtc->cursor_size != size ||
10096 intel_crtc->cursor_cntl != cntl)) {
10097 /* On these chipsets we can only modify the base/size/stride
10098 * whilst the cursor is disabled.
10099 */
10100 I915_WRITE(CURCNTR(PIPE_A), 0);
10101 POSTING_READ(CURCNTR(PIPE_A));
10102 intel_crtc->cursor_cntl = 0;
10103 }
10104
10105 if (intel_crtc->cursor_base != base) {
10106 I915_WRITE(CURBASE(PIPE_A), base);
10107 intel_crtc->cursor_base = base;
10108 }
10109
10110 if (intel_crtc->cursor_size != size) {
10111 I915_WRITE(CURSIZE, size);
10112 intel_crtc->cursor_size = size;
10113 }
10114
10115 if (intel_crtc->cursor_cntl != cntl) {
10116 I915_WRITE(CURCNTR(PIPE_A), cntl);
10117 POSTING_READ(CURCNTR(PIPE_A));
10118 intel_crtc->cursor_cntl = cntl;
10119 }
10120 }
10121
10122 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10123 const struct intel_plane_state *plane_state)
10124 {
10125 struct drm_device *dev = crtc->dev;
10126 struct drm_i915_private *dev_priv = dev->dev_private;
10127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10128 int pipe = intel_crtc->pipe;
10129 uint32_t cntl = 0;
10130
10131 if (plane_state && plane_state->visible) {
10132 cntl = MCURSOR_GAMMA_ENABLE;
10133 switch (plane_state->base.crtc_w) {
10134 case 64:
10135 cntl |= CURSOR_MODE_64_ARGB_AX;
10136 break;
10137 case 128:
10138 cntl |= CURSOR_MODE_128_ARGB_AX;
10139 break;
10140 case 256:
10141 cntl |= CURSOR_MODE_256_ARGB_AX;
10142 break;
10143 default:
10144 MISSING_CASE(plane_state->base.crtc_w);
10145 return;
10146 }
10147 cntl |= pipe << 28; /* Connect to correct pipe */
10148
10149 if (HAS_DDI(dev))
10150 cntl |= CURSOR_PIPE_CSC_ENABLE;
10151
10152 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10153 cntl |= CURSOR_ROTATE_180;
10154 }
10155
10156 if (intel_crtc->cursor_cntl != cntl) {
10157 I915_WRITE(CURCNTR(pipe), cntl);
10158 POSTING_READ(CURCNTR(pipe));
10159 intel_crtc->cursor_cntl = cntl;
10160 }
10161
10162 /* and commit changes on next vblank */
10163 I915_WRITE(CURBASE(pipe), base);
10164 POSTING_READ(CURBASE(pipe));
10165
10166 intel_crtc->cursor_base = base;
10167 }
10168
10169 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10170 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10171 const struct intel_plane_state *plane_state)
10172 {
10173 struct drm_device *dev = crtc->dev;
10174 struct drm_i915_private *dev_priv = dev->dev_private;
10175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10176 int pipe = intel_crtc->pipe;
10177 u32 base = intel_crtc->cursor_addr;
10178 u32 pos = 0;
10179
10180 if (plane_state) {
10181 int x = plane_state->base.crtc_x;
10182 int y = plane_state->base.crtc_y;
10183
10184 if (x < 0) {
10185 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10186 x = -x;
10187 }
10188 pos |= x << CURSOR_X_SHIFT;
10189
10190 if (y < 0) {
10191 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10192 y = -y;
10193 }
10194 pos |= y << CURSOR_Y_SHIFT;
10195
10196 /* ILK+ do this automagically */
10197 if (HAS_GMCH_DISPLAY(dev) &&
10198 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10199 base += (plane_state->base.crtc_h *
10200 plane_state->base.crtc_w - 1) * 4;
10201 }
10202 }
10203
10204 I915_WRITE(CURPOS(pipe), pos);
10205
10206 if (IS_845G(dev) || IS_I865G(dev))
10207 i845_update_cursor(crtc, base, plane_state);
10208 else
10209 i9xx_update_cursor(crtc, base, plane_state);
10210 }
10211
10212 static bool cursor_size_ok(struct drm_device *dev,
10213 uint32_t width, uint32_t height)
10214 {
10215 if (width == 0 || height == 0)
10216 return false;
10217
10218 /*
10219 * 845g/865g are special in that they are only limited by
10220 * the width of their cursors, the height is arbitrary up to
10221 * the precision of the register. Everything else requires
10222 * square cursors, limited to a few power-of-two sizes.
10223 */
10224 if (IS_845G(dev) || IS_I865G(dev)) {
10225 if ((width & 63) != 0)
10226 return false;
10227
10228 if (width > (IS_845G(dev) ? 64 : 512))
10229 return false;
10230
10231 if (height > 1023)
10232 return false;
10233 } else {
10234 switch (width | height) {
10235 case 256:
10236 case 128:
10237 if (IS_GEN2(dev))
10238 return false;
10239 case 64:
10240 break;
10241 default:
10242 return false;
10243 }
10244 }
10245
10246 return true;
10247 }
10248
10249 /* VESA 640x480x72Hz mode to set on the pipe */
10250 static struct drm_display_mode load_detect_mode = {
10251 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10252 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10253 };
10254
10255 struct drm_framebuffer *
10256 __intel_framebuffer_create(struct drm_device *dev,
10257 struct drm_mode_fb_cmd2 *mode_cmd,
10258 struct drm_i915_gem_object *obj)
10259 {
10260 struct intel_framebuffer *intel_fb;
10261 int ret;
10262
10263 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10264 if (!intel_fb)
10265 return ERR_PTR(-ENOMEM);
10266
10267 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10268 if (ret)
10269 goto err;
10270
10271 return &intel_fb->base;
10272
10273 err:
10274 kfree(intel_fb);
10275 return ERR_PTR(ret);
10276 }
10277
10278 static struct drm_framebuffer *
10279 intel_framebuffer_create(struct drm_device *dev,
10280 struct drm_mode_fb_cmd2 *mode_cmd,
10281 struct drm_i915_gem_object *obj)
10282 {
10283 struct drm_framebuffer *fb;
10284 int ret;
10285
10286 ret = i915_mutex_lock_interruptible(dev);
10287 if (ret)
10288 return ERR_PTR(ret);
10289 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10290 mutex_unlock(&dev->struct_mutex);
10291
10292 return fb;
10293 }
10294
10295 static u32
10296 intel_framebuffer_pitch_for_width(int width, int bpp)
10297 {
10298 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10299 return ALIGN(pitch, 64);
10300 }
10301
10302 static u32
10303 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10304 {
10305 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10306 return PAGE_ALIGN(pitch * mode->vdisplay);
10307 }
10308
10309 static struct drm_framebuffer *
10310 intel_framebuffer_create_for_mode(struct drm_device *dev,
10311 struct drm_display_mode *mode,
10312 int depth, int bpp)
10313 {
10314 struct drm_framebuffer *fb;
10315 struct drm_i915_gem_object *obj;
10316 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10317
10318 obj = i915_gem_object_create(dev,
10319 intel_framebuffer_size_for_mode(mode, bpp));
10320 if (IS_ERR(obj))
10321 return ERR_CAST(obj);
10322
10323 mode_cmd.width = mode->hdisplay;
10324 mode_cmd.height = mode->vdisplay;
10325 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10326 bpp);
10327 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10328
10329 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10330 if (IS_ERR(fb))
10331 drm_gem_object_unreference_unlocked(&obj->base);
10332
10333 return fb;
10334 }
10335
10336 static struct drm_framebuffer *
10337 mode_fits_in_fbdev(struct drm_device *dev,
10338 struct drm_display_mode *mode)
10339 {
10340 #ifdef CONFIG_DRM_FBDEV_EMULATION
10341 struct drm_i915_private *dev_priv = dev->dev_private;
10342 struct drm_i915_gem_object *obj;
10343 struct drm_framebuffer *fb;
10344
10345 if (!dev_priv->fbdev)
10346 return NULL;
10347
10348 if (!dev_priv->fbdev->fb)
10349 return NULL;
10350
10351 obj = dev_priv->fbdev->fb->obj;
10352 BUG_ON(!obj);
10353
10354 fb = &dev_priv->fbdev->fb->base;
10355 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10356 fb->bits_per_pixel))
10357 return NULL;
10358
10359 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10360 return NULL;
10361
10362 drm_framebuffer_reference(fb);
10363 return fb;
10364 #else
10365 return NULL;
10366 #endif
10367 }
10368
10369 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10370 struct drm_crtc *crtc,
10371 struct drm_display_mode *mode,
10372 struct drm_framebuffer *fb,
10373 int x, int y)
10374 {
10375 struct drm_plane_state *plane_state;
10376 int hdisplay, vdisplay;
10377 int ret;
10378
10379 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10380 if (IS_ERR(plane_state))
10381 return PTR_ERR(plane_state);
10382
10383 if (mode)
10384 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10385 else
10386 hdisplay = vdisplay = 0;
10387
10388 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10389 if (ret)
10390 return ret;
10391 drm_atomic_set_fb_for_plane(plane_state, fb);
10392 plane_state->crtc_x = 0;
10393 plane_state->crtc_y = 0;
10394 plane_state->crtc_w = hdisplay;
10395 plane_state->crtc_h = vdisplay;
10396 plane_state->src_x = x << 16;
10397 plane_state->src_y = y << 16;
10398 plane_state->src_w = hdisplay << 16;
10399 plane_state->src_h = vdisplay << 16;
10400
10401 return 0;
10402 }
10403
10404 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10405 struct drm_display_mode *mode,
10406 struct intel_load_detect_pipe *old,
10407 struct drm_modeset_acquire_ctx *ctx)
10408 {
10409 struct intel_crtc *intel_crtc;
10410 struct intel_encoder *intel_encoder =
10411 intel_attached_encoder(connector);
10412 struct drm_crtc *possible_crtc;
10413 struct drm_encoder *encoder = &intel_encoder->base;
10414 struct drm_crtc *crtc = NULL;
10415 struct drm_device *dev = encoder->dev;
10416 struct drm_framebuffer *fb;
10417 struct drm_mode_config *config = &dev->mode_config;
10418 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10419 struct drm_connector_state *connector_state;
10420 struct intel_crtc_state *crtc_state;
10421 int ret, i = -1;
10422
10423 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10424 connector->base.id, connector->name,
10425 encoder->base.id, encoder->name);
10426
10427 old->restore_state = NULL;
10428
10429 retry:
10430 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10431 if (ret)
10432 goto fail;
10433
10434 /*
10435 * Algorithm gets a little messy:
10436 *
10437 * - if the connector already has an assigned crtc, use it (but make
10438 * sure it's on first)
10439 *
10440 * - try to find the first unused crtc that can drive this connector,
10441 * and use that if we find one
10442 */
10443
10444 /* See if we already have a CRTC for this connector */
10445 if (connector->state->crtc) {
10446 crtc = connector->state->crtc;
10447
10448 ret = drm_modeset_lock(&crtc->mutex, ctx);
10449 if (ret)
10450 goto fail;
10451
10452 /* Make sure the crtc and connector are running */
10453 goto found;
10454 }
10455
10456 /* Find an unused one (if possible) */
10457 for_each_crtc(dev, possible_crtc) {
10458 i++;
10459 if (!(encoder->possible_crtcs & (1 << i)))
10460 continue;
10461
10462 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10463 if (ret)
10464 goto fail;
10465
10466 if (possible_crtc->state->enable) {
10467 drm_modeset_unlock(&possible_crtc->mutex);
10468 continue;
10469 }
10470
10471 crtc = possible_crtc;
10472 break;
10473 }
10474
10475 /*
10476 * If we didn't find an unused CRTC, don't use any.
10477 */
10478 if (!crtc) {
10479 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10480 goto fail;
10481 }
10482
10483 found:
10484 intel_crtc = to_intel_crtc(crtc);
10485
10486 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10487 if (ret)
10488 goto fail;
10489
10490 state = drm_atomic_state_alloc(dev);
10491 restore_state = drm_atomic_state_alloc(dev);
10492 if (!state || !restore_state) {
10493 ret = -ENOMEM;
10494 goto fail;
10495 }
10496
10497 state->acquire_ctx = ctx;
10498 restore_state->acquire_ctx = ctx;
10499
10500 connector_state = drm_atomic_get_connector_state(state, connector);
10501 if (IS_ERR(connector_state)) {
10502 ret = PTR_ERR(connector_state);
10503 goto fail;
10504 }
10505
10506 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10507 if (ret)
10508 goto fail;
10509
10510 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10511 if (IS_ERR(crtc_state)) {
10512 ret = PTR_ERR(crtc_state);
10513 goto fail;
10514 }
10515
10516 crtc_state->base.active = crtc_state->base.enable = true;
10517
10518 if (!mode)
10519 mode = &load_detect_mode;
10520
10521 /* We need a framebuffer large enough to accommodate all accesses
10522 * that the plane may generate whilst we perform load detection.
10523 * We can not rely on the fbcon either being present (we get called
10524 * during its initialisation to detect all boot displays, or it may
10525 * not even exist) or that it is large enough to satisfy the
10526 * requested mode.
10527 */
10528 fb = mode_fits_in_fbdev(dev, mode);
10529 if (fb == NULL) {
10530 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10531 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10532 } else
10533 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10534 if (IS_ERR(fb)) {
10535 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10536 goto fail;
10537 }
10538
10539 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10540 if (ret)
10541 goto fail;
10542
10543 drm_framebuffer_unreference(fb);
10544
10545 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10546 if (ret)
10547 goto fail;
10548
10549 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10550 if (!ret)
10551 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10552 if (!ret)
10553 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10554 if (ret) {
10555 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10556 goto fail;
10557 }
10558
10559 ret = drm_atomic_commit(state);
10560 if (ret) {
10561 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10562 goto fail;
10563 }
10564
10565 old->restore_state = restore_state;
10566
10567 /* let the connector get through one full cycle before testing */
10568 intel_wait_for_vblank(dev, intel_crtc->pipe);
10569 return true;
10570
10571 fail:
10572 drm_atomic_state_free(state);
10573 drm_atomic_state_free(restore_state);
10574 restore_state = state = NULL;
10575
10576 if (ret == -EDEADLK) {
10577 drm_modeset_backoff(ctx);
10578 goto retry;
10579 }
10580
10581 return false;
10582 }
10583
10584 void intel_release_load_detect_pipe(struct drm_connector *connector,
10585 struct intel_load_detect_pipe *old,
10586 struct drm_modeset_acquire_ctx *ctx)
10587 {
10588 struct intel_encoder *intel_encoder =
10589 intel_attached_encoder(connector);
10590 struct drm_encoder *encoder = &intel_encoder->base;
10591 struct drm_atomic_state *state = old->restore_state;
10592 int ret;
10593
10594 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10595 connector->base.id, connector->name,
10596 encoder->base.id, encoder->name);
10597
10598 if (!state)
10599 return;
10600
10601 ret = drm_atomic_commit(state);
10602 if (ret) {
10603 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10604 drm_atomic_state_free(state);
10605 }
10606 }
10607
10608 static int i9xx_pll_refclk(struct drm_device *dev,
10609 const struct intel_crtc_state *pipe_config)
10610 {
10611 struct drm_i915_private *dev_priv = dev->dev_private;
10612 u32 dpll = pipe_config->dpll_hw_state.dpll;
10613
10614 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10615 return dev_priv->vbt.lvds_ssc_freq;
10616 else if (HAS_PCH_SPLIT(dev))
10617 return 120000;
10618 else if (!IS_GEN2(dev))
10619 return 96000;
10620 else
10621 return 48000;
10622 }
10623
10624 /* Returns the clock of the currently programmed mode of the given pipe. */
10625 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10626 struct intel_crtc_state *pipe_config)
10627 {
10628 struct drm_device *dev = crtc->base.dev;
10629 struct drm_i915_private *dev_priv = dev->dev_private;
10630 int pipe = pipe_config->cpu_transcoder;
10631 u32 dpll = pipe_config->dpll_hw_state.dpll;
10632 u32 fp;
10633 struct dpll clock;
10634 int port_clock;
10635 int refclk = i9xx_pll_refclk(dev, pipe_config);
10636
10637 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10638 fp = pipe_config->dpll_hw_state.fp0;
10639 else
10640 fp = pipe_config->dpll_hw_state.fp1;
10641
10642 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10643 if (IS_PINEVIEW(dev)) {
10644 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10645 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10646 } else {
10647 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10648 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10649 }
10650
10651 if (!IS_GEN2(dev)) {
10652 if (IS_PINEVIEW(dev))
10653 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10654 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10655 else
10656 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10657 DPLL_FPA01_P1_POST_DIV_SHIFT);
10658
10659 switch (dpll & DPLL_MODE_MASK) {
10660 case DPLLB_MODE_DAC_SERIAL:
10661 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10662 5 : 10;
10663 break;
10664 case DPLLB_MODE_LVDS:
10665 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10666 7 : 14;
10667 break;
10668 default:
10669 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10670 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10671 return;
10672 }
10673
10674 if (IS_PINEVIEW(dev))
10675 port_clock = pnv_calc_dpll_params(refclk, &clock);
10676 else
10677 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10678 } else {
10679 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10680 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10681
10682 if (is_lvds) {
10683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10684 DPLL_FPA01_P1_POST_DIV_SHIFT);
10685
10686 if (lvds & LVDS_CLKB_POWER_UP)
10687 clock.p2 = 7;
10688 else
10689 clock.p2 = 14;
10690 } else {
10691 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10692 clock.p1 = 2;
10693 else {
10694 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10695 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10696 }
10697 if (dpll & PLL_P2_DIVIDE_BY_4)
10698 clock.p2 = 4;
10699 else
10700 clock.p2 = 2;
10701 }
10702
10703 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10704 }
10705
10706 /*
10707 * This value includes pixel_multiplier. We will use
10708 * port_clock to compute adjusted_mode.crtc_clock in the
10709 * encoder's get_config() function.
10710 */
10711 pipe_config->port_clock = port_clock;
10712 }
10713
10714 int intel_dotclock_calculate(int link_freq,
10715 const struct intel_link_m_n *m_n)
10716 {
10717 /*
10718 * The calculation for the data clock is:
10719 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10720 * But we want to avoid losing precison if possible, so:
10721 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10722 *
10723 * and the link clock is simpler:
10724 * link_clock = (m * link_clock) / n
10725 */
10726
10727 if (!m_n->link_n)
10728 return 0;
10729
10730 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10731 }
10732
10733 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10734 struct intel_crtc_state *pipe_config)
10735 {
10736 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10737
10738 /* read out port_clock from the DPLL */
10739 i9xx_crtc_clock_get(crtc, pipe_config);
10740
10741 /*
10742 * In case there is an active pipe without active ports,
10743 * we may need some idea for the dotclock anyway.
10744 * Calculate one based on the FDI configuration.
10745 */
10746 pipe_config->base.adjusted_mode.crtc_clock =
10747 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10748 &pipe_config->fdi_m_n);
10749 }
10750
10751 /** Returns the currently programmed mode of the given pipe. */
10752 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10753 struct drm_crtc *crtc)
10754 {
10755 struct drm_i915_private *dev_priv = dev->dev_private;
10756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10757 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10758 struct drm_display_mode *mode;
10759 struct intel_crtc_state *pipe_config;
10760 int htot = I915_READ(HTOTAL(cpu_transcoder));
10761 int hsync = I915_READ(HSYNC(cpu_transcoder));
10762 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10763 int vsync = I915_READ(VSYNC(cpu_transcoder));
10764 enum pipe pipe = intel_crtc->pipe;
10765
10766 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10767 if (!mode)
10768 return NULL;
10769
10770 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10771 if (!pipe_config) {
10772 kfree(mode);
10773 return NULL;
10774 }
10775
10776 /*
10777 * Construct a pipe_config sufficient for getting the clock info
10778 * back out of crtc_clock_get.
10779 *
10780 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10781 * to use a real value here instead.
10782 */
10783 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10784 pipe_config->pixel_multiplier = 1;
10785 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10786 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10787 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10788 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10789
10790 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10791 mode->hdisplay = (htot & 0xffff) + 1;
10792 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10793 mode->hsync_start = (hsync & 0xffff) + 1;
10794 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10795 mode->vdisplay = (vtot & 0xffff) + 1;
10796 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10797 mode->vsync_start = (vsync & 0xffff) + 1;
10798 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10799
10800 drm_mode_set_name(mode);
10801
10802 kfree(pipe_config);
10803
10804 return mode;
10805 }
10806
10807 void intel_mark_busy(struct drm_i915_private *dev_priv)
10808 {
10809 if (dev_priv->mm.busy)
10810 return;
10811
10812 intel_runtime_pm_get(dev_priv);
10813 i915_update_gfx_val(dev_priv);
10814 if (INTEL_GEN(dev_priv) >= 6)
10815 gen6_rps_busy(dev_priv);
10816 dev_priv->mm.busy = true;
10817 }
10818
10819 void intel_mark_idle(struct drm_i915_private *dev_priv)
10820 {
10821 if (!dev_priv->mm.busy)
10822 return;
10823
10824 dev_priv->mm.busy = false;
10825
10826 if (INTEL_GEN(dev_priv) >= 6)
10827 gen6_rps_idle(dev_priv);
10828
10829 intel_runtime_pm_put(dev_priv);
10830 }
10831
10832 static void intel_crtc_destroy(struct drm_crtc *crtc)
10833 {
10834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10835 struct drm_device *dev = crtc->dev;
10836 struct intel_unpin_work *work;
10837
10838 spin_lock_irq(&dev->event_lock);
10839 work = intel_crtc->unpin_work;
10840 intel_crtc->unpin_work = NULL;
10841 spin_unlock_irq(&dev->event_lock);
10842
10843 if (work) {
10844 cancel_work_sync(&work->work);
10845 kfree(work);
10846 }
10847
10848 drm_crtc_cleanup(crtc);
10849
10850 kfree(intel_crtc);
10851 }
10852
10853 static void intel_unpin_work_fn(struct work_struct *__work)
10854 {
10855 struct intel_unpin_work *work =
10856 container_of(__work, struct intel_unpin_work, work);
10857 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10858 struct drm_device *dev = crtc->base.dev;
10859 struct drm_plane *primary = crtc->base.primary;
10860
10861 mutex_lock(&dev->struct_mutex);
10862 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10863 drm_gem_object_unreference(&work->pending_flip_obj->base);
10864
10865 if (work->flip_queued_req)
10866 i915_gem_request_assign(&work->flip_queued_req, NULL);
10867 mutex_unlock(&dev->struct_mutex);
10868
10869 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10870 intel_fbc_post_update(crtc);
10871 drm_framebuffer_unreference(work->old_fb);
10872
10873 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10874 atomic_dec(&crtc->unpin_work_count);
10875
10876 kfree(work);
10877 }
10878
10879 static void do_intel_finish_page_flip(struct drm_i915_private *dev_priv,
10880 struct drm_crtc *crtc)
10881 {
10882 struct drm_device *dev = dev_priv->dev;
10883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10884 struct intel_unpin_work *work;
10885 unsigned long flags;
10886
10887 /* Ignore early vblank irqs */
10888 if (intel_crtc == NULL)
10889 return;
10890
10891 /*
10892 * This is called both by irq handlers and the reset code (to complete
10893 * lost pageflips) so needs the full irqsave spinlocks.
10894 */
10895 spin_lock_irqsave(&dev->event_lock, flags);
10896 work = intel_crtc->unpin_work;
10897
10898 /* Ensure we don't miss a work->pending update ... */
10899 smp_rmb();
10900
10901 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10902 spin_unlock_irqrestore(&dev->event_lock, flags);
10903 return;
10904 }
10905
10906 page_flip_completed(intel_crtc);
10907
10908 spin_unlock_irqrestore(&dev->event_lock, flags);
10909 }
10910
10911 void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe)
10912 {
10913 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10914
10915 do_intel_finish_page_flip(dev_priv, crtc);
10916 }
10917
10918 void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane)
10919 {
10920 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10921
10922 do_intel_finish_page_flip(dev_priv, crtc);
10923 }
10924
10925 /* Is 'a' after or equal to 'b'? */
10926 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10927 {
10928 return !((a - b) & 0x80000000);
10929 }
10930
10931 static bool page_flip_finished(struct intel_crtc *crtc)
10932 {
10933 struct drm_device *dev = crtc->base.dev;
10934 struct drm_i915_private *dev_priv = dev->dev_private;
10935 unsigned reset_counter;
10936
10937 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10938 if (crtc->reset_counter != reset_counter)
10939 return true;
10940
10941 /*
10942 * The relevant registers doen't exist on pre-ctg.
10943 * As the flip done interrupt doesn't trigger for mmio
10944 * flips on gmch platforms, a flip count check isn't
10945 * really needed there. But since ctg has the registers,
10946 * include it in the check anyway.
10947 */
10948 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10949 return true;
10950
10951 /*
10952 * BDW signals flip done immediately if the plane
10953 * is disabled, even if the plane enable is already
10954 * armed to occur at the next vblank :(
10955 */
10956
10957 /*
10958 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10959 * used the same base address. In that case the mmio flip might
10960 * have completed, but the CS hasn't even executed the flip yet.
10961 *
10962 * A flip count check isn't enough as the CS might have updated
10963 * the base address just after start of vblank, but before we
10964 * managed to process the interrupt. This means we'd complete the
10965 * CS flip too soon.
10966 *
10967 * Combining both checks should get us a good enough result. It may
10968 * still happen that the CS flip has been executed, but has not
10969 * yet actually completed. But in case the base address is the same
10970 * anyway, we don't really care.
10971 */
10972 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10973 crtc->unpin_work->gtt_offset &&
10974 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10975 crtc->unpin_work->flip_count);
10976 }
10977
10978 void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane)
10979 {
10980 struct drm_device *dev = dev_priv->dev;
10981 struct intel_crtc *intel_crtc =
10982 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10983 unsigned long flags;
10984
10985
10986 /*
10987 * This is called both by irq handlers and the reset code (to complete
10988 * lost pageflips) so needs the full irqsave spinlocks.
10989 *
10990 * NB: An MMIO update of the plane base pointer will also
10991 * generate a page-flip completion irq, i.e. every modeset
10992 * is also accompanied by a spurious intel_prepare_page_flip().
10993 */
10994 spin_lock_irqsave(&dev->event_lock, flags);
10995 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10996 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10997 spin_unlock_irqrestore(&dev->event_lock, flags);
10998 }
10999
11000 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11001 {
11002 /* Ensure that the work item is consistent when activating it ... */
11003 smp_wmb();
11004 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11005 /* and that it is marked active as soon as the irq could fire. */
11006 smp_wmb();
11007 }
11008
11009 static int intel_gen2_queue_flip(struct drm_device *dev,
11010 struct drm_crtc *crtc,
11011 struct drm_framebuffer *fb,
11012 struct drm_i915_gem_object *obj,
11013 struct drm_i915_gem_request *req,
11014 uint32_t flags)
11015 {
11016 struct intel_engine_cs *engine = req->engine;
11017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11018 u32 flip_mask;
11019 int ret;
11020
11021 ret = intel_ring_begin(req, 6);
11022 if (ret)
11023 return ret;
11024
11025 /* Can't queue multiple flips, so wait for the previous
11026 * one to finish before executing the next.
11027 */
11028 if (intel_crtc->plane)
11029 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11030 else
11031 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11032 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11033 intel_ring_emit(engine, MI_NOOP);
11034 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11035 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11036 intel_ring_emit(engine, fb->pitches[0]);
11037 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11038 intel_ring_emit(engine, 0); /* aux display base address, unused */
11039
11040 intel_mark_page_flip_active(intel_crtc->unpin_work);
11041 return 0;
11042 }
11043
11044 static int intel_gen3_queue_flip(struct drm_device *dev,
11045 struct drm_crtc *crtc,
11046 struct drm_framebuffer *fb,
11047 struct drm_i915_gem_object *obj,
11048 struct drm_i915_gem_request *req,
11049 uint32_t flags)
11050 {
11051 struct intel_engine_cs *engine = req->engine;
11052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11053 u32 flip_mask;
11054 int ret;
11055
11056 ret = intel_ring_begin(req, 6);
11057 if (ret)
11058 return ret;
11059
11060 if (intel_crtc->plane)
11061 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11062 else
11063 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11064 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11065 intel_ring_emit(engine, MI_NOOP);
11066 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11068 intel_ring_emit(engine, fb->pitches[0]);
11069 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11070 intel_ring_emit(engine, MI_NOOP);
11071
11072 intel_mark_page_flip_active(intel_crtc->unpin_work);
11073 return 0;
11074 }
11075
11076 static int intel_gen4_queue_flip(struct drm_device *dev,
11077 struct drm_crtc *crtc,
11078 struct drm_framebuffer *fb,
11079 struct drm_i915_gem_object *obj,
11080 struct drm_i915_gem_request *req,
11081 uint32_t flags)
11082 {
11083 struct intel_engine_cs *engine = req->engine;
11084 struct drm_i915_private *dev_priv = dev->dev_private;
11085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11086 uint32_t pf, pipesrc;
11087 int ret;
11088
11089 ret = intel_ring_begin(req, 4);
11090 if (ret)
11091 return ret;
11092
11093 /* i965+ uses the linear or tiled offsets from the
11094 * Display Registers (which do not change across a page-flip)
11095 * so we need only reprogram the base address.
11096 */
11097 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11098 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11099 intel_ring_emit(engine, fb->pitches[0]);
11100 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11101 obj->tiling_mode);
11102
11103 /* XXX Enabling the panel-fitter across page-flip is so far
11104 * untested on non-native modes, so ignore it for now.
11105 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11106 */
11107 pf = 0;
11108 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11109 intel_ring_emit(engine, pf | pipesrc);
11110
11111 intel_mark_page_flip_active(intel_crtc->unpin_work);
11112 return 0;
11113 }
11114
11115 static int intel_gen6_queue_flip(struct drm_device *dev,
11116 struct drm_crtc *crtc,
11117 struct drm_framebuffer *fb,
11118 struct drm_i915_gem_object *obj,
11119 struct drm_i915_gem_request *req,
11120 uint32_t flags)
11121 {
11122 struct intel_engine_cs *engine = req->engine;
11123 struct drm_i915_private *dev_priv = dev->dev_private;
11124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11125 uint32_t pf, pipesrc;
11126 int ret;
11127
11128 ret = intel_ring_begin(req, 4);
11129 if (ret)
11130 return ret;
11131
11132 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11133 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11134 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11135 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11136
11137 /* Contrary to the suggestions in the documentation,
11138 * "Enable Panel Fitter" does not seem to be required when page
11139 * flipping with a non-native mode, and worse causes a normal
11140 * modeset to fail.
11141 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11142 */
11143 pf = 0;
11144 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11145 intel_ring_emit(engine, pf | pipesrc);
11146
11147 intel_mark_page_flip_active(intel_crtc->unpin_work);
11148 return 0;
11149 }
11150
11151 static int intel_gen7_queue_flip(struct drm_device *dev,
11152 struct drm_crtc *crtc,
11153 struct drm_framebuffer *fb,
11154 struct drm_i915_gem_object *obj,
11155 struct drm_i915_gem_request *req,
11156 uint32_t flags)
11157 {
11158 struct intel_engine_cs *engine = req->engine;
11159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11160 uint32_t plane_bit = 0;
11161 int len, ret;
11162
11163 switch (intel_crtc->plane) {
11164 case PLANE_A:
11165 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11166 break;
11167 case PLANE_B:
11168 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11169 break;
11170 case PLANE_C:
11171 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11172 break;
11173 default:
11174 WARN_ONCE(1, "unknown plane in flip command\n");
11175 return -ENODEV;
11176 }
11177
11178 len = 4;
11179 if (engine->id == RCS) {
11180 len += 6;
11181 /*
11182 * On Gen 8, SRM is now taking an extra dword to accommodate
11183 * 48bits addresses, and we need a NOOP for the batch size to
11184 * stay even.
11185 */
11186 if (IS_GEN8(dev))
11187 len += 2;
11188 }
11189
11190 /*
11191 * BSpec MI_DISPLAY_FLIP for IVB:
11192 * "The full packet must be contained within the same cache line."
11193 *
11194 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11195 * cacheline, if we ever start emitting more commands before
11196 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11197 * then do the cacheline alignment, and finally emit the
11198 * MI_DISPLAY_FLIP.
11199 */
11200 ret = intel_ring_cacheline_align(req);
11201 if (ret)
11202 return ret;
11203
11204 ret = intel_ring_begin(req, len);
11205 if (ret)
11206 return ret;
11207
11208 /* Unmask the flip-done completion message. Note that the bspec says that
11209 * we should do this for both the BCS and RCS, and that we must not unmask
11210 * more than one flip event at any time (or ensure that one flip message
11211 * can be sent by waiting for flip-done prior to queueing new flips).
11212 * Experimentation says that BCS works despite DERRMR masking all
11213 * flip-done completion events and that unmasking all planes at once
11214 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11215 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11216 */
11217 if (engine->id == RCS) {
11218 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11219 intel_ring_emit_reg(engine, DERRMR);
11220 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11221 DERRMR_PIPEB_PRI_FLIP_DONE |
11222 DERRMR_PIPEC_PRI_FLIP_DONE));
11223 if (IS_GEN8(dev))
11224 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11225 MI_SRM_LRM_GLOBAL_GTT);
11226 else
11227 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11228 MI_SRM_LRM_GLOBAL_GTT);
11229 intel_ring_emit_reg(engine, DERRMR);
11230 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11231 if (IS_GEN8(dev)) {
11232 intel_ring_emit(engine, 0);
11233 intel_ring_emit(engine, MI_NOOP);
11234 }
11235 }
11236
11237 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11238 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11239 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11240 intel_ring_emit(engine, (MI_NOOP));
11241
11242 intel_mark_page_flip_active(intel_crtc->unpin_work);
11243 return 0;
11244 }
11245
11246 static bool use_mmio_flip(struct intel_engine_cs *engine,
11247 struct drm_i915_gem_object *obj)
11248 {
11249 /*
11250 * This is not being used for older platforms, because
11251 * non-availability of flip done interrupt forces us to use
11252 * CS flips. Older platforms derive flip done using some clever
11253 * tricks involving the flip_pending status bits and vblank irqs.
11254 * So using MMIO flips there would disrupt this mechanism.
11255 */
11256
11257 if (engine == NULL)
11258 return true;
11259
11260 if (INTEL_GEN(engine->i915) < 5)
11261 return false;
11262
11263 if (i915.use_mmio_flip < 0)
11264 return false;
11265 else if (i915.use_mmio_flip > 0)
11266 return true;
11267 else if (i915.enable_execlists)
11268 return true;
11269 else if (obj->base.dma_buf &&
11270 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11271 false))
11272 return true;
11273 else
11274 return engine != i915_gem_request_get_engine(obj->last_write_req);
11275 }
11276
11277 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11278 unsigned int rotation,
11279 struct intel_unpin_work *work)
11280 {
11281 struct drm_device *dev = intel_crtc->base.dev;
11282 struct drm_i915_private *dev_priv = dev->dev_private;
11283 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11284 const enum pipe pipe = intel_crtc->pipe;
11285 u32 ctl, stride, tile_height;
11286
11287 ctl = I915_READ(PLANE_CTL(pipe, 0));
11288 ctl &= ~PLANE_CTL_TILED_MASK;
11289 switch (fb->modifier[0]) {
11290 case DRM_FORMAT_MOD_NONE:
11291 break;
11292 case I915_FORMAT_MOD_X_TILED:
11293 ctl |= PLANE_CTL_TILED_X;
11294 break;
11295 case I915_FORMAT_MOD_Y_TILED:
11296 ctl |= PLANE_CTL_TILED_Y;
11297 break;
11298 case I915_FORMAT_MOD_Yf_TILED:
11299 ctl |= PLANE_CTL_TILED_YF;
11300 break;
11301 default:
11302 MISSING_CASE(fb->modifier[0]);
11303 }
11304
11305 /*
11306 * The stride is either expressed as a multiple of 64 bytes chunks for
11307 * linear buffers or in number of tiles for tiled buffers.
11308 */
11309 if (intel_rotation_90_or_270(rotation)) {
11310 /* stride = Surface height in tiles */
11311 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11312 stride = DIV_ROUND_UP(fb->height, tile_height);
11313 } else {
11314 stride = fb->pitches[0] /
11315 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11316 fb->pixel_format);
11317 }
11318
11319 /*
11320 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11321 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11322 */
11323 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11324 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11325
11326 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11327 POSTING_READ(PLANE_SURF(pipe, 0));
11328 }
11329
11330 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11331 struct intel_unpin_work *work)
11332 {
11333 struct drm_device *dev = intel_crtc->base.dev;
11334 struct drm_i915_private *dev_priv = dev->dev_private;
11335 struct intel_framebuffer *intel_fb =
11336 to_intel_framebuffer(intel_crtc->base.primary->fb);
11337 struct drm_i915_gem_object *obj = intel_fb->obj;
11338 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11339 u32 dspcntr;
11340
11341 dspcntr = I915_READ(reg);
11342
11343 if (obj->tiling_mode != I915_TILING_NONE)
11344 dspcntr |= DISPPLANE_TILED;
11345 else
11346 dspcntr &= ~DISPPLANE_TILED;
11347
11348 I915_WRITE(reg, dspcntr);
11349
11350 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11351 POSTING_READ(DSPSURF(intel_crtc->plane));
11352 }
11353
11354 /*
11355 * XXX: This is the temporary way to update the plane registers until we get
11356 * around to using the usual plane update functions for MMIO flips
11357 */
11358 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11359 {
11360 struct intel_crtc *crtc = mmio_flip->crtc;
11361 struct intel_unpin_work *work;
11362
11363 spin_lock_irq(&crtc->base.dev->event_lock);
11364 work = crtc->unpin_work;
11365 spin_unlock_irq(&crtc->base.dev->event_lock);
11366 if (work == NULL)
11367 return;
11368
11369 intel_mark_page_flip_active(work);
11370
11371 intel_pipe_update_start(crtc);
11372
11373 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11374 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11375 else
11376 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11377 ilk_do_mmio_flip(crtc, work);
11378
11379 intel_pipe_update_end(crtc);
11380 }
11381
11382 static void intel_mmio_flip_work_func(struct work_struct *work)
11383 {
11384 struct intel_mmio_flip *mmio_flip =
11385 container_of(work, struct intel_mmio_flip, work);
11386 struct intel_framebuffer *intel_fb =
11387 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11388 struct drm_i915_gem_object *obj = intel_fb->obj;
11389
11390 if (mmio_flip->req) {
11391 WARN_ON(__i915_wait_request(mmio_flip->req,
11392 false, NULL,
11393 &mmio_flip->i915->rps.mmioflips));
11394 i915_gem_request_unreference(mmio_flip->req);
11395 }
11396
11397 /* For framebuffer backed by dmabuf, wait for fence */
11398 if (obj->base.dma_buf)
11399 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11400 false, false,
11401 MAX_SCHEDULE_TIMEOUT) < 0);
11402
11403 intel_do_mmio_flip(mmio_flip);
11404 kfree(mmio_flip);
11405 }
11406
11407 static int intel_queue_mmio_flip(struct drm_device *dev,
11408 struct drm_crtc *crtc,
11409 struct drm_i915_gem_object *obj)
11410 {
11411 struct intel_mmio_flip *mmio_flip;
11412
11413 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11414 if (mmio_flip == NULL)
11415 return -ENOMEM;
11416
11417 mmio_flip->i915 = to_i915(dev);
11418 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11419 mmio_flip->crtc = to_intel_crtc(crtc);
11420 mmio_flip->rotation = crtc->primary->state->rotation;
11421
11422 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11423 schedule_work(&mmio_flip->work);
11424
11425 return 0;
11426 }
11427
11428 static int intel_default_queue_flip(struct drm_device *dev,
11429 struct drm_crtc *crtc,
11430 struct drm_framebuffer *fb,
11431 struct drm_i915_gem_object *obj,
11432 struct drm_i915_gem_request *req,
11433 uint32_t flags)
11434 {
11435 return -ENODEV;
11436 }
11437
11438 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11439 struct drm_crtc *crtc)
11440 {
11441 struct drm_i915_private *dev_priv = dev->dev_private;
11442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11443 struct intel_unpin_work *work = intel_crtc->unpin_work;
11444 u32 addr;
11445
11446 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11447 return true;
11448
11449 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11450 return false;
11451
11452 if (!work->enable_stall_check)
11453 return false;
11454
11455 if (work->flip_ready_vblank == 0) {
11456 if (work->flip_queued_req &&
11457 !i915_gem_request_completed(work->flip_queued_req, true))
11458 return false;
11459
11460 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11461 }
11462
11463 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11464 return false;
11465
11466 /* Potential stall - if we see that the flip has happened,
11467 * assume a missed interrupt. */
11468 if (INTEL_INFO(dev)->gen >= 4)
11469 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11470 else
11471 addr = I915_READ(DSPADDR(intel_crtc->plane));
11472
11473 /* There is a potential issue here with a false positive after a flip
11474 * to the same address. We could address this by checking for a
11475 * non-incrementing frame counter.
11476 */
11477 return addr == work->gtt_offset;
11478 }
11479
11480 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11481 {
11482 struct drm_device *dev = dev_priv->dev;
11483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11485 struct intel_unpin_work *work;
11486
11487 WARN_ON(!in_interrupt());
11488
11489 if (crtc == NULL)
11490 return;
11491
11492 spin_lock(&dev->event_lock);
11493 work = intel_crtc->unpin_work;
11494 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11495 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11496 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11497 page_flip_completed(intel_crtc);
11498 work = NULL;
11499 }
11500 if (work != NULL &&
11501 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11502 intel_queue_rps_boost_for_request(work->flip_queued_req);
11503 spin_unlock(&dev->event_lock);
11504 }
11505
11506 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11507 struct drm_framebuffer *fb,
11508 struct drm_pending_vblank_event *event,
11509 uint32_t page_flip_flags)
11510 {
11511 struct drm_device *dev = crtc->dev;
11512 struct drm_i915_private *dev_priv = dev->dev_private;
11513 struct drm_framebuffer *old_fb = crtc->primary->fb;
11514 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11516 struct drm_plane *primary = crtc->primary;
11517 enum pipe pipe = intel_crtc->pipe;
11518 struct intel_unpin_work *work;
11519 struct intel_engine_cs *engine;
11520 bool mmio_flip;
11521 struct drm_i915_gem_request *request = NULL;
11522 int ret;
11523
11524 /*
11525 * drm_mode_page_flip_ioctl() should already catch this, but double
11526 * check to be safe. In the future we may enable pageflipping from
11527 * a disabled primary plane.
11528 */
11529 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11530 return -EBUSY;
11531
11532 /* Can't change pixel format via MI display flips. */
11533 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11534 return -EINVAL;
11535
11536 /*
11537 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11538 * Note that pitch changes could also affect these register.
11539 */
11540 if (INTEL_INFO(dev)->gen > 3 &&
11541 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11542 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11543 return -EINVAL;
11544
11545 if (i915_terminally_wedged(&dev_priv->gpu_error))
11546 goto out_hang;
11547
11548 work = kzalloc(sizeof(*work), GFP_KERNEL);
11549 if (work == NULL)
11550 return -ENOMEM;
11551
11552 work->event = event;
11553 work->crtc = crtc;
11554 work->old_fb = old_fb;
11555 INIT_WORK(&work->work, intel_unpin_work_fn);
11556
11557 ret = drm_crtc_vblank_get(crtc);
11558 if (ret)
11559 goto free_work;
11560
11561 /* We borrow the event spin lock for protecting unpin_work */
11562 spin_lock_irq(&dev->event_lock);
11563 if (intel_crtc->unpin_work) {
11564 /* Before declaring the flip queue wedged, check if
11565 * the hardware completed the operation behind our backs.
11566 */
11567 if (__intel_pageflip_stall_check(dev, crtc)) {
11568 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11569 page_flip_completed(intel_crtc);
11570 } else {
11571 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11572 spin_unlock_irq(&dev->event_lock);
11573
11574 drm_crtc_vblank_put(crtc);
11575 kfree(work);
11576 return -EBUSY;
11577 }
11578 }
11579 intel_crtc->unpin_work = work;
11580 spin_unlock_irq(&dev->event_lock);
11581
11582 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11583 flush_workqueue(dev_priv->wq);
11584
11585 /* Reference the objects for the scheduled work. */
11586 drm_framebuffer_reference(work->old_fb);
11587 drm_gem_object_reference(&obj->base);
11588
11589 crtc->primary->fb = fb;
11590 update_state_fb(crtc->primary);
11591 intel_fbc_pre_update(intel_crtc);
11592
11593 work->pending_flip_obj = obj;
11594
11595 ret = i915_mutex_lock_interruptible(dev);
11596 if (ret)
11597 goto cleanup;
11598
11599 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11600 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11601 ret = -EIO;
11602 goto cleanup;
11603 }
11604
11605 atomic_inc(&intel_crtc->unpin_work_count);
11606
11607 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11608 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11609
11610 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11611 engine = &dev_priv->engine[BCS];
11612 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11613 /* vlv: DISPLAY_FLIP fails to change tiling */
11614 engine = NULL;
11615 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11616 engine = &dev_priv->engine[BCS];
11617 } else if (INTEL_INFO(dev)->gen >= 7) {
11618 engine = i915_gem_request_get_engine(obj->last_write_req);
11619 if (engine == NULL || engine->id != RCS)
11620 engine = &dev_priv->engine[BCS];
11621 } else {
11622 engine = &dev_priv->engine[RCS];
11623 }
11624
11625 mmio_flip = use_mmio_flip(engine, obj);
11626
11627 /* When using CS flips, we want to emit semaphores between rings.
11628 * However, when using mmio flips we will create a task to do the
11629 * synchronisation, so all we want here is to pin the framebuffer
11630 * into the display plane and skip any waits.
11631 */
11632 if (!mmio_flip) {
11633 ret = i915_gem_object_sync(obj, engine, &request);
11634 if (ret)
11635 goto cleanup_pending;
11636 }
11637
11638 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11639 if (ret)
11640 goto cleanup_pending;
11641
11642 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11643 obj, 0);
11644 work->gtt_offset += intel_crtc->dspaddr_offset;
11645
11646 if (mmio_flip) {
11647 ret = intel_queue_mmio_flip(dev, crtc, obj);
11648 if (ret)
11649 goto cleanup_unpin;
11650
11651 i915_gem_request_assign(&work->flip_queued_req,
11652 obj->last_write_req);
11653 } else {
11654 if (!request) {
11655 request = i915_gem_request_alloc(engine, NULL);
11656 if (IS_ERR(request)) {
11657 ret = PTR_ERR(request);
11658 goto cleanup_unpin;
11659 }
11660 }
11661
11662 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11663 page_flip_flags);
11664 if (ret)
11665 goto cleanup_unpin;
11666
11667 i915_gem_request_assign(&work->flip_queued_req, request);
11668 }
11669
11670 if (request)
11671 i915_add_request_no_flush(request);
11672
11673 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11674 work->enable_stall_check = true;
11675
11676 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11677 to_intel_plane(primary)->frontbuffer_bit);
11678 mutex_unlock(&dev->struct_mutex);
11679
11680 intel_frontbuffer_flip_prepare(dev,
11681 to_intel_plane(primary)->frontbuffer_bit);
11682
11683 trace_i915_flip_request(intel_crtc->plane, obj);
11684
11685 return 0;
11686
11687 cleanup_unpin:
11688 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11689 cleanup_pending:
11690 if (!IS_ERR_OR_NULL(request))
11691 i915_add_request_no_flush(request);
11692 atomic_dec(&intel_crtc->unpin_work_count);
11693 mutex_unlock(&dev->struct_mutex);
11694 cleanup:
11695 crtc->primary->fb = old_fb;
11696 update_state_fb(crtc->primary);
11697
11698 drm_gem_object_unreference_unlocked(&obj->base);
11699 drm_framebuffer_unreference(work->old_fb);
11700
11701 spin_lock_irq(&dev->event_lock);
11702 intel_crtc->unpin_work = NULL;
11703 spin_unlock_irq(&dev->event_lock);
11704
11705 drm_crtc_vblank_put(crtc);
11706 free_work:
11707 kfree(work);
11708
11709 if (ret == -EIO) {
11710 struct drm_atomic_state *state;
11711 struct drm_plane_state *plane_state;
11712
11713 out_hang:
11714 state = drm_atomic_state_alloc(dev);
11715 if (!state)
11716 return -ENOMEM;
11717 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11718
11719 retry:
11720 plane_state = drm_atomic_get_plane_state(state, primary);
11721 ret = PTR_ERR_OR_ZERO(plane_state);
11722 if (!ret) {
11723 drm_atomic_set_fb_for_plane(plane_state, fb);
11724
11725 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11726 if (!ret)
11727 ret = drm_atomic_commit(state);
11728 }
11729
11730 if (ret == -EDEADLK) {
11731 drm_modeset_backoff(state->acquire_ctx);
11732 drm_atomic_state_clear(state);
11733 goto retry;
11734 }
11735
11736 if (ret)
11737 drm_atomic_state_free(state);
11738
11739 if (ret == 0 && event) {
11740 spin_lock_irq(&dev->event_lock);
11741 drm_crtc_send_vblank_event(crtc, event);
11742 spin_unlock_irq(&dev->event_lock);
11743 }
11744 }
11745 return ret;
11746 }
11747
11748
11749 /**
11750 * intel_wm_need_update - Check whether watermarks need updating
11751 * @plane: drm plane
11752 * @state: new plane state
11753 *
11754 * Check current plane state versus the new one to determine whether
11755 * watermarks need to be recalculated.
11756 *
11757 * Returns true or false.
11758 */
11759 static bool intel_wm_need_update(struct drm_plane *plane,
11760 struct drm_plane_state *state)
11761 {
11762 struct intel_plane_state *new = to_intel_plane_state(state);
11763 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11764
11765 /* Update watermarks on tiling or size changes. */
11766 if (new->visible != cur->visible)
11767 return true;
11768
11769 if (!cur->base.fb || !new->base.fb)
11770 return false;
11771
11772 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11773 cur->base.rotation != new->base.rotation ||
11774 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11775 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11776 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11777 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11778 return true;
11779
11780 return false;
11781 }
11782
11783 static bool needs_scaling(struct intel_plane_state *state)
11784 {
11785 int src_w = drm_rect_width(&state->src) >> 16;
11786 int src_h = drm_rect_height(&state->src) >> 16;
11787 int dst_w = drm_rect_width(&state->dst);
11788 int dst_h = drm_rect_height(&state->dst);
11789
11790 return (src_w != dst_w || src_h != dst_h);
11791 }
11792
11793 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11794 struct drm_plane_state *plane_state)
11795 {
11796 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11797 struct drm_crtc *crtc = crtc_state->crtc;
11798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11799 struct drm_plane *plane = plane_state->plane;
11800 struct drm_device *dev = crtc->dev;
11801 struct drm_i915_private *dev_priv = to_i915(dev);
11802 struct intel_plane_state *old_plane_state =
11803 to_intel_plane_state(plane->state);
11804 int idx = intel_crtc->base.base.id, ret;
11805 bool mode_changed = needs_modeset(crtc_state);
11806 bool was_crtc_enabled = crtc->state->active;
11807 bool is_crtc_enabled = crtc_state->active;
11808 bool turn_off, turn_on, visible, was_visible;
11809 struct drm_framebuffer *fb = plane_state->fb;
11810
11811 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11812 plane->type != DRM_PLANE_TYPE_CURSOR) {
11813 ret = skl_update_scaler_plane(
11814 to_intel_crtc_state(crtc_state),
11815 to_intel_plane_state(plane_state));
11816 if (ret)
11817 return ret;
11818 }
11819
11820 was_visible = old_plane_state->visible;
11821 visible = to_intel_plane_state(plane_state)->visible;
11822
11823 if (!was_crtc_enabled && WARN_ON(was_visible))
11824 was_visible = false;
11825
11826 /*
11827 * Visibility is calculated as if the crtc was on, but
11828 * after scaler setup everything depends on it being off
11829 * when the crtc isn't active.
11830 *
11831 * FIXME this is wrong for watermarks. Watermarks should also
11832 * be computed as if the pipe would be active. Perhaps move
11833 * per-plane wm computation to the .check_plane() hook, and
11834 * only combine the results from all planes in the current place?
11835 */
11836 if (!is_crtc_enabled)
11837 to_intel_plane_state(plane_state)->visible = visible = false;
11838
11839 if (!was_visible && !visible)
11840 return 0;
11841
11842 if (fb != old_plane_state->base.fb)
11843 pipe_config->fb_changed = true;
11844
11845 turn_off = was_visible && (!visible || mode_changed);
11846 turn_on = visible && (!was_visible || mode_changed);
11847
11848 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11849 plane->base.id, fb ? fb->base.id : -1);
11850
11851 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11852 plane->base.id, was_visible, visible,
11853 turn_off, turn_on, mode_changed);
11854
11855 if (turn_on) {
11856 pipe_config->update_wm_pre = true;
11857
11858 /* must disable cxsr around plane enable/disable */
11859 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11860 pipe_config->disable_cxsr = true;
11861 } else if (turn_off) {
11862 pipe_config->update_wm_post = true;
11863
11864 /* must disable cxsr around plane enable/disable */
11865 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11866 pipe_config->disable_cxsr = true;
11867 } else if (intel_wm_need_update(plane, plane_state)) {
11868 /* FIXME bollocks */
11869 pipe_config->update_wm_pre = true;
11870 pipe_config->update_wm_post = true;
11871 }
11872
11873 /* Pre-gen9 platforms need two-step watermark updates */
11874 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11875 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11876 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11877
11878 if (visible || was_visible)
11879 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11880
11881 /*
11882 * WaCxSRDisabledForSpriteScaling:ivb
11883 *
11884 * cstate->update_wm was already set above, so this flag will
11885 * take effect when we commit and program watermarks.
11886 */
11887 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11888 needs_scaling(to_intel_plane_state(plane_state)) &&
11889 !needs_scaling(old_plane_state))
11890 pipe_config->disable_lp_wm = true;
11891
11892 return 0;
11893 }
11894
11895 static bool encoders_cloneable(const struct intel_encoder *a,
11896 const struct intel_encoder *b)
11897 {
11898 /* masks could be asymmetric, so check both ways */
11899 return a == b || (a->cloneable & (1 << b->type) &&
11900 b->cloneable & (1 << a->type));
11901 }
11902
11903 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11904 struct intel_crtc *crtc,
11905 struct intel_encoder *encoder)
11906 {
11907 struct intel_encoder *source_encoder;
11908 struct drm_connector *connector;
11909 struct drm_connector_state *connector_state;
11910 int i;
11911
11912 for_each_connector_in_state(state, connector, connector_state, i) {
11913 if (connector_state->crtc != &crtc->base)
11914 continue;
11915
11916 source_encoder =
11917 to_intel_encoder(connector_state->best_encoder);
11918 if (!encoders_cloneable(encoder, source_encoder))
11919 return false;
11920 }
11921
11922 return true;
11923 }
11924
11925 static bool check_encoder_cloning(struct drm_atomic_state *state,
11926 struct intel_crtc *crtc)
11927 {
11928 struct intel_encoder *encoder;
11929 struct drm_connector *connector;
11930 struct drm_connector_state *connector_state;
11931 int i;
11932
11933 for_each_connector_in_state(state, connector, connector_state, i) {
11934 if (connector_state->crtc != &crtc->base)
11935 continue;
11936
11937 encoder = to_intel_encoder(connector_state->best_encoder);
11938 if (!check_single_encoder_cloning(state, crtc, encoder))
11939 return false;
11940 }
11941
11942 return true;
11943 }
11944
11945 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11946 struct drm_crtc_state *crtc_state)
11947 {
11948 struct drm_device *dev = crtc->dev;
11949 struct drm_i915_private *dev_priv = dev->dev_private;
11950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11951 struct intel_crtc_state *pipe_config =
11952 to_intel_crtc_state(crtc_state);
11953 struct drm_atomic_state *state = crtc_state->state;
11954 int ret;
11955 bool mode_changed = needs_modeset(crtc_state);
11956
11957 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11958 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11959 return -EINVAL;
11960 }
11961
11962 if (mode_changed && !crtc_state->active)
11963 pipe_config->update_wm_post = true;
11964
11965 if (mode_changed && crtc_state->enable &&
11966 dev_priv->display.crtc_compute_clock &&
11967 !WARN_ON(pipe_config->shared_dpll)) {
11968 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11969 pipe_config);
11970 if (ret)
11971 return ret;
11972 }
11973
11974 if (crtc_state->color_mgmt_changed) {
11975 ret = intel_color_check(crtc, crtc_state);
11976 if (ret)
11977 return ret;
11978 }
11979
11980 ret = 0;
11981 if (dev_priv->display.compute_pipe_wm) {
11982 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11983 if (ret) {
11984 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11985 return ret;
11986 }
11987 }
11988
11989 if (dev_priv->display.compute_intermediate_wm &&
11990 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11991 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11992 return 0;
11993
11994 /*
11995 * Calculate 'intermediate' watermarks that satisfy both the
11996 * old state and the new state. We can program these
11997 * immediately.
11998 */
11999 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12000 intel_crtc,
12001 pipe_config);
12002 if (ret) {
12003 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12004 return ret;
12005 }
12006 }
12007
12008 if (INTEL_INFO(dev)->gen >= 9) {
12009 if (mode_changed)
12010 ret = skl_update_scaler_crtc(pipe_config);
12011
12012 if (!ret)
12013 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12014 pipe_config);
12015 }
12016
12017 return ret;
12018 }
12019
12020 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12021 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12022 .atomic_begin = intel_begin_crtc_commit,
12023 .atomic_flush = intel_finish_crtc_commit,
12024 .atomic_check = intel_crtc_atomic_check,
12025 };
12026
12027 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12028 {
12029 struct intel_connector *connector;
12030
12031 for_each_intel_connector(dev, connector) {
12032 if (connector->base.encoder) {
12033 connector->base.state->best_encoder =
12034 connector->base.encoder;
12035 connector->base.state->crtc =
12036 connector->base.encoder->crtc;
12037 } else {
12038 connector->base.state->best_encoder = NULL;
12039 connector->base.state->crtc = NULL;
12040 }
12041 }
12042 }
12043
12044 static void
12045 connected_sink_compute_bpp(struct intel_connector *connector,
12046 struct intel_crtc_state *pipe_config)
12047 {
12048 int bpp = pipe_config->pipe_bpp;
12049
12050 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12051 connector->base.base.id,
12052 connector->base.name);
12053
12054 /* Don't use an invalid EDID bpc value */
12055 if (connector->base.display_info.bpc &&
12056 connector->base.display_info.bpc * 3 < bpp) {
12057 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12058 bpp, connector->base.display_info.bpc*3);
12059 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12060 }
12061
12062 /* Clamp bpp to default limit on screens without EDID 1.4 */
12063 if (connector->base.display_info.bpc == 0) {
12064 int type = connector->base.connector_type;
12065 int clamp_bpp = 24;
12066
12067 /* Fall back to 18 bpp when DP sink capability is unknown. */
12068 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12069 type == DRM_MODE_CONNECTOR_eDP)
12070 clamp_bpp = 18;
12071
12072 if (bpp > clamp_bpp) {
12073 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12074 bpp, clamp_bpp);
12075 pipe_config->pipe_bpp = clamp_bpp;
12076 }
12077 }
12078 }
12079
12080 static int
12081 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12082 struct intel_crtc_state *pipe_config)
12083 {
12084 struct drm_device *dev = crtc->base.dev;
12085 struct drm_atomic_state *state;
12086 struct drm_connector *connector;
12087 struct drm_connector_state *connector_state;
12088 int bpp, i;
12089
12090 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12091 bpp = 10*3;
12092 else if (INTEL_INFO(dev)->gen >= 5)
12093 bpp = 12*3;
12094 else
12095 bpp = 8*3;
12096
12097
12098 pipe_config->pipe_bpp = bpp;
12099
12100 state = pipe_config->base.state;
12101
12102 /* Clamp display bpp to EDID value */
12103 for_each_connector_in_state(state, connector, connector_state, i) {
12104 if (connector_state->crtc != &crtc->base)
12105 continue;
12106
12107 connected_sink_compute_bpp(to_intel_connector(connector),
12108 pipe_config);
12109 }
12110
12111 return bpp;
12112 }
12113
12114 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12115 {
12116 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12117 "type: 0x%x flags: 0x%x\n",
12118 mode->crtc_clock,
12119 mode->crtc_hdisplay, mode->crtc_hsync_start,
12120 mode->crtc_hsync_end, mode->crtc_htotal,
12121 mode->crtc_vdisplay, mode->crtc_vsync_start,
12122 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12123 }
12124
12125 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12126 struct intel_crtc_state *pipe_config,
12127 const char *context)
12128 {
12129 struct drm_device *dev = crtc->base.dev;
12130 struct drm_plane *plane;
12131 struct intel_plane *intel_plane;
12132 struct intel_plane_state *state;
12133 struct drm_framebuffer *fb;
12134
12135 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12136 context, pipe_config, pipe_name(crtc->pipe));
12137
12138 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12139 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12140 pipe_config->pipe_bpp, pipe_config->dither);
12141 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12142 pipe_config->has_pch_encoder,
12143 pipe_config->fdi_lanes,
12144 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12145 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12146 pipe_config->fdi_m_n.tu);
12147 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12148 pipe_config->has_dp_encoder,
12149 pipe_config->lane_count,
12150 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12151 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12152 pipe_config->dp_m_n.tu);
12153
12154 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12155 pipe_config->has_dp_encoder,
12156 pipe_config->lane_count,
12157 pipe_config->dp_m2_n2.gmch_m,
12158 pipe_config->dp_m2_n2.gmch_n,
12159 pipe_config->dp_m2_n2.link_m,
12160 pipe_config->dp_m2_n2.link_n,
12161 pipe_config->dp_m2_n2.tu);
12162
12163 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12164 pipe_config->has_audio,
12165 pipe_config->has_infoframe);
12166
12167 DRM_DEBUG_KMS("requested mode:\n");
12168 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12169 DRM_DEBUG_KMS("adjusted mode:\n");
12170 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12171 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12172 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12173 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12174 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12175 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12176 crtc->num_scalers,
12177 pipe_config->scaler_state.scaler_users,
12178 pipe_config->scaler_state.scaler_id);
12179 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12180 pipe_config->gmch_pfit.control,
12181 pipe_config->gmch_pfit.pgm_ratios,
12182 pipe_config->gmch_pfit.lvds_border_bits);
12183 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12184 pipe_config->pch_pfit.pos,
12185 pipe_config->pch_pfit.size,
12186 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12187 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12188 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12189
12190 if (IS_BROXTON(dev)) {
12191 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12192 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12193 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12194 pipe_config->ddi_pll_sel,
12195 pipe_config->dpll_hw_state.ebb0,
12196 pipe_config->dpll_hw_state.ebb4,
12197 pipe_config->dpll_hw_state.pll0,
12198 pipe_config->dpll_hw_state.pll1,
12199 pipe_config->dpll_hw_state.pll2,
12200 pipe_config->dpll_hw_state.pll3,
12201 pipe_config->dpll_hw_state.pll6,
12202 pipe_config->dpll_hw_state.pll8,
12203 pipe_config->dpll_hw_state.pll9,
12204 pipe_config->dpll_hw_state.pll10,
12205 pipe_config->dpll_hw_state.pcsdw12);
12206 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12207 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12208 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12209 pipe_config->ddi_pll_sel,
12210 pipe_config->dpll_hw_state.ctrl1,
12211 pipe_config->dpll_hw_state.cfgcr1,
12212 pipe_config->dpll_hw_state.cfgcr2);
12213 } else if (HAS_DDI(dev)) {
12214 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12215 pipe_config->ddi_pll_sel,
12216 pipe_config->dpll_hw_state.wrpll,
12217 pipe_config->dpll_hw_state.spll);
12218 } else {
12219 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12220 "fp0: 0x%x, fp1: 0x%x\n",
12221 pipe_config->dpll_hw_state.dpll,
12222 pipe_config->dpll_hw_state.dpll_md,
12223 pipe_config->dpll_hw_state.fp0,
12224 pipe_config->dpll_hw_state.fp1);
12225 }
12226
12227 DRM_DEBUG_KMS("planes on this crtc\n");
12228 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12229 intel_plane = to_intel_plane(plane);
12230 if (intel_plane->pipe != crtc->pipe)
12231 continue;
12232
12233 state = to_intel_plane_state(plane->state);
12234 fb = state->base.fb;
12235 if (!fb) {
12236 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12237 "disabled, scaler_id = %d\n",
12238 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12239 plane->base.id, intel_plane->pipe,
12240 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12241 drm_plane_index(plane), state->scaler_id);
12242 continue;
12243 }
12244
12245 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12246 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12247 plane->base.id, intel_plane->pipe,
12248 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12249 drm_plane_index(plane));
12250 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12251 fb->base.id, fb->width, fb->height, fb->pixel_format);
12252 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12253 state->scaler_id,
12254 state->src.x1 >> 16, state->src.y1 >> 16,
12255 drm_rect_width(&state->src) >> 16,
12256 drm_rect_height(&state->src) >> 16,
12257 state->dst.x1, state->dst.y1,
12258 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12259 }
12260 }
12261
12262 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12263 {
12264 struct drm_device *dev = state->dev;
12265 struct drm_connector *connector;
12266 unsigned int used_ports = 0;
12267
12268 /*
12269 * Walk the connector list instead of the encoder
12270 * list to detect the problem on ddi platforms
12271 * where there's just one encoder per digital port.
12272 */
12273 drm_for_each_connector(connector, dev) {
12274 struct drm_connector_state *connector_state;
12275 struct intel_encoder *encoder;
12276
12277 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12278 if (!connector_state)
12279 connector_state = connector->state;
12280
12281 if (!connector_state->best_encoder)
12282 continue;
12283
12284 encoder = to_intel_encoder(connector_state->best_encoder);
12285
12286 WARN_ON(!connector_state->crtc);
12287
12288 switch (encoder->type) {
12289 unsigned int port_mask;
12290 case INTEL_OUTPUT_UNKNOWN:
12291 if (WARN_ON(!HAS_DDI(dev)))
12292 break;
12293 case INTEL_OUTPUT_DISPLAYPORT:
12294 case INTEL_OUTPUT_HDMI:
12295 case INTEL_OUTPUT_EDP:
12296 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12297
12298 /* the same port mustn't appear more than once */
12299 if (used_ports & port_mask)
12300 return false;
12301
12302 used_ports |= port_mask;
12303 default:
12304 break;
12305 }
12306 }
12307
12308 return true;
12309 }
12310
12311 static void
12312 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12313 {
12314 struct drm_crtc_state tmp_state;
12315 struct intel_crtc_scaler_state scaler_state;
12316 struct intel_dpll_hw_state dpll_hw_state;
12317 struct intel_shared_dpll *shared_dpll;
12318 uint32_t ddi_pll_sel;
12319 bool force_thru;
12320
12321 /* FIXME: before the switch to atomic started, a new pipe_config was
12322 * kzalloc'd. Code that depends on any field being zero should be
12323 * fixed, so that the crtc_state can be safely duplicated. For now,
12324 * only fields that are know to not cause problems are preserved. */
12325
12326 tmp_state = crtc_state->base;
12327 scaler_state = crtc_state->scaler_state;
12328 shared_dpll = crtc_state->shared_dpll;
12329 dpll_hw_state = crtc_state->dpll_hw_state;
12330 ddi_pll_sel = crtc_state->ddi_pll_sel;
12331 force_thru = crtc_state->pch_pfit.force_thru;
12332
12333 memset(crtc_state, 0, sizeof *crtc_state);
12334
12335 crtc_state->base = tmp_state;
12336 crtc_state->scaler_state = scaler_state;
12337 crtc_state->shared_dpll = shared_dpll;
12338 crtc_state->dpll_hw_state = dpll_hw_state;
12339 crtc_state->ddi_pll_sel = ddi_pll_sel;
12340 crtc_state->pch_pfit.force_thru = force_thru;
12341 }
12342
12343 static int
12344 intel_modeset_pipe_config(struct drm_crtc *crtc,
12345 struct intel_crtc_state *pipe_config)
12346 {
12347 struct drm_atomic_state *state = pipe_config->base.state;
12348 struct intel_encoder *encoder;
12349 struct drm_connector *connector;
12350 struct drm_connector_state *connector_state;
12351 int base_bpp, ret = -EINVAL;
12352 int i;
12353 bool retry = true;
12354
12355 clear_intel_crtc_state(pipe_config);
12356
12357 pipe_config->cpu_transcoder =
12358 (enum transcoder) to_intel_crtc(crtc)->pipe;
12359
12360 /*
12361 * Sanitize sync polarity flags based on requested ones. If neither
12362 * positive or negative polarity is requested, treat this as meaning
12363 * negative polarity.
12364 */
12365 if (!(pipe_config->base.adjusted_mode.flags &
12366 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12367 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12368
12369 if (!(pipe_config->base.adjusted_mode.flags &
12370 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12371 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12372
12373 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12374 pipe_config);
12375 if (base_bpp < 0)
12376 goto fail;
12377
12378 /*
12379 * Determine the real pipe dimensions. Note that stereo modes can
12380 * increase the actual pipe size due to the frame doubling and
12381 * insertion of additional space for blanks between the frame. This
12382 * is stored in the crtc timings. We use the requested mode to do this
12383 * computation to clearly distinguish it from the adjusted mode, which
12384 * can be changed by the connectors in the below retry loop.
12385 */
12386 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12387 &pipe_config->pipe_src_w,
12388 &pipe_config->pipe_src_h);
12389
12390 encoder_retry:
12391 /* Ensure the port clock defaults are reset when retrying. */
12392 pipe_config->port_clock = 0;
12393 pipe_config->pixel_multiplier = 1;
12394
12395 /* Fill in default crtc timings, allow encoders to overwrite them. */
12396 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12397 CRTC_STEREO_DOUBLE);
12398
12399 /* Pass our mode to the connectors and the CRTC to give them a chance to
12400 * adjust it according to limitations or connector properties, and also
12401 * a chance to reject the mode entirely.
12402 */
12403 for_each_connector_in_state(state, connector, connector_state, i) {
12404 if (connector_state->crtc != crtc)
12405 continue;
12406
12407 encoder = to_intel_encoder(connector_state->best_encoder);
12408
12409 if (!(encoder->compute_config(encoder, pipe_config))) {
12410 DRM_DEBUG_KMS("Encoder config failure\n");
12411 goto fail;
12412 }
12413 }
12414
12415 /* Set default port clock if not overwritten by the encoder. Needs to be
12416 * done afterwards in case the encoder adjusts the mode. */
12417 if (!pipe_config->port_clock)
12418 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12419 * pipe_config->pixel_multiplier;
12420
12421 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12422 if (ret < 0) {
12423 DRM_DEBUG_KMS("CRTC fixup failed\n");
12424 goto fail;
12425 }
12426
12427 if (ret == RETRY) {
12428 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12429 ret = -EINVAL;
12430 goto fail;
12431 }
12432
12433 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12434 retry = false;
12435 goto encoder_retry;
12436 }
12437
12438 /* Dithering seems to not pass-through bits correctly when it should, so
12439 * only enable it on 6bpc panels. */
12440 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12441 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12442 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12443
12444 fail:
12445 return ret;
12446 }
12447
12448 static void
12449 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12450 {
12451 struct drm_crtc *crtc;
12452 struct drm_crtc_state *crtc_state;
12453 int i;
12454
12455 /* Double check state. */
12456 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12457 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12458
12459 /* Update hwmode for vblank functions */
12460 if (crtc->state->active)
12461 crtc->hwmode = crtc->state->adjusted_mode;
12462 else
12463 crtc->hwmode.crtc_clock = 0;
12464
12465 /*
12466 * Update legacy state to satisfy fbc code. This can
12467 * be removed when fbc uses the atomic state.
12468 */
12469 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12470 struct drm_plane_state *plane_state = crtc->primary->state;
12471
12472 crtc->primary->fb = plane_state->fb;
12473 crtc->x = plane_state->src_x >> 16;
12474 crtc->y = plane_state->src_y >> 16;
12475 }
12476 }
12477 }
12478
12479 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12480 {
12481 int diff;
12482
12483 if (clock1 == clock2)
12484 return true;
12485
12486 if (!clock1 || !clock2)
12487 return false;
12488
12489 diff = abs(clock1 - clock2);
12490
12491 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12492 return true;
12493
12494 return false;
12495 }
12496
12497 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12498 list_for_each_entry((intel_crtc), \
12499 &(dev)->mode_config.crtc_list, \
12500 base.head) \
12501 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12502
12503 static bool
12504 intel_compare_m_n(unsigned int m, unsigned int n,
12505 unsigned int m2, unsigned int n2,
12506 bool exact)
12507 {
12508 if (m == m2 && n == n2)
12509 return true;
12510
12511 if (exact || !m || !n || !m2 || !n2)
12512 return false;
12513
12514 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12515
12516 if (n > n2) {
12517 while (n > n2) {
12518 m2 <<= 1;
12519 n2 <<= 1;
12520 }
12521 } else if (n < n2) {
12522 while (n < n2) {
12523 m <<= 1;
12524 n <<= 1;
12525 }
12526 }
12527
12528 if (n != n2)
12529 return false;
12530
12531 return intel_fuzzy_clock_check(m, m2);
12532 }
12533
12534 static bool
12535 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12536 struct intel_link_m_n *m2_n2,
12537 bool adjust)
12538 {
12539 if (m_n->tu == m2_n2->tu &&
12540 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12541 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12542 intel_compare_m_n(m_n->link_m, m_n->link_n,
12543 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12544 if (adjust)
12545 *m2_n2 = *m_n;
12546
12547 return true;
12548 }
12549
12550 return false;
12551 }
12552
12553 static bool
12554 intel_pipe_config_compare(struct drm_device *dev,
12555 struct intel_crtc_state *current_config,
12556 struct intel_crtc_state *pipe_config,
12557 bool adjust)
12558 {
12559 bool ret = true;
12560
12561 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12562 do { \
12563 if (!adjust) \
12564 DRM_ERROR(fmt, ##__VA_ARGS__); \
12565 else \
12566 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12567 } while (0)
12568
12569 #define PIPE_CONF_CHECK_X(name) \
12570 if (current_config->name != pipe_config->name) { \
12571 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12572 "(expected 0x%08x, found 0x%08x)\n", \
12573 current_config->name, \
12574 pipe_config->name); \
12575 ret = false; \
12576 }
12577
12578 #define PIPE_CONF_CHECK_I(name) \
12579 if (current_config->name != pipe_config->name) { \
12580 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12581 "(expected %i, found %i)\n", \
12582 current_config->name, \
12583 pipe_config->name); \
12584 ret = false; \
12585 }
12586
12587 #define PIPE_CONF_CHECK_P(name) \
12588 if (current_config->name != pipe_config->name) { \
12589 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12590 "(expected %p, found %p)\n", \
12591 current_config->name, \
12592 pipe_config->name); \
12593 ret = false; \
12594 }
12595
12596 #define PIPE_CONF_CHECK_M_N(name) \
12597 if (!intel_compare_link_m_n(&current_config->name, \
12598 &pipe_config->name,\
12599 adjust)) { \
12600 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12601 "(expected tu %i gmch %i/%i link %i/%i, " \
12602 "found tu %i, gmch %i/%i link %i/%i)\n", \
12603 current_config->name.tu, \
12604 current_config->name.gmch_m, \
12605 current_config->name.gmch_n, \
12606 current_config->name.link_m, \
12607 current_config->name.link_n, \
12608 pipe_config->name.tu, \
12609 pipe_config->name.gmch_m, \
12610 pipe_config->name.gmch_n, \
12611 pipe_config->name.link_m, \
12612 pipe_config->name.link_n); \
12613 ret = false; \
12614 }
12615
12616 /* This is required for BDW+ where there is only one set of registers for
12617 * switching between high and low RR.
12618 * This macro can be used whenever a comparison has to be made between one
12619 * hw state and multiple sw state variables.
12620 */
12621 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12622 if (!intel_compare_link_m_n(&current_config->name, \
12623 &pipe_config->name, adjust) && \
12624 !intel_compare_link_m_n(&current_config->alt_name, \
12625 &pipe_config->name, adjust)) { \
12626 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12627 "(expected tu %i gmch %i/%i link %i/%i, " \
12628 "or tu %i gmch %i/%i link %i/%i, " \
12629 "found tu %i, gmch %i/%i link %i/%i)\n", \
12630 current_config->name.tu, \
12631 current_config->name.gmch_m, \
12632 current_config->name.gmch_n, \
12633 current_config->name.link_m, \
12634 current_config->name.link_n, \
12635 current_config->alt_name.tu, \
12636 current_config->alt_name.gmch_m, \
12637 current_config->alt_name.gmch_n, \
12638 current_config->alt_name.link_m, \
12639 current_config->alt_name.link_n, \
12640 pipe_config->name.tu, \
12641 pipe_config->name.gmch_m, \
12642 pipe_config->name.gmch_n, \
12643 pipe_config->name.link_m, \
12644 pipe_config->name.link_n); \
12645 ret = false; \
12646 }
12647
12648 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12649 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12650 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12651 "(expected %i, found %i)\n", \
12652 current_config->name & (mask), \
12653 pipe_config->name & (mask)); \
12654 ret = false; \
12655 }
12656
12657 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12658 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12659 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12660 "(expected %i, found %i)\n", \
12661 current_config->name, \
12662 pipe_config->name); \
12663 ret = false; \
12664 }
12665
12666 #define PIPE_CONF_QUIRK(quirk) \
12667 ((current_config->quirks | pipe_config->quirks) & (quirk))
12668
12669 PIPE_CONF_CHECK_I(cpu_transcoder);
12670
12671 PIPE_CONF_CHECK_I(has_pch_encoder);
12672 PIPE_CONF_CHECK_I(fdi_lanes);
12673 PIPE_CONF_CHECK_M_N(fdi_m_n);
12674
12675 PIPE_CONF_CHECK_I(has_dp_encoder);
12676 PIPE_CONF_CHECK_I(lane_count);
12677
12678 if (INTEL_INFO(dev)->gen < 8) {
12679 PIPE_CONF_CHECK_M_N(dp_m_n);
12680
12681 if (current_config->has_drrs)
12682 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12683 } else
12684 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12685
12686 PIPE_CONF_CHECK_I(has_dsi_encoder);
12687
12688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12690 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12691 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12694
12695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12697 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12698 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12699 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12700 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12701
12702 PIPE_CONF_CHECK_I(pixel_multiplier);
12703 PIPE_CONF_CHECK_I(has_hdmi_sink);
12704 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12705 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12706 PIPE_CONF_CHECK_I(limited_color_range);
12707 PIPE_CONF_CHECK_I(has_infoframe);
12708
12709 PIPE_CONF_CHECK_I(has_audio);
12710
12711 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12712 DRM_MODE_FLAG_INTERLACE);
12713
12714 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12715 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12716 DRM_MODE_FLAG_PHSYNC);
12717 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12718 DRM_MODE_FLAG_NHSYNC);
12719 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12720 DRM_MODE_FLAG_PVSYNC);
12721 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12722 DRM_MODE_FLAG_NVSYNC);
12723 }
12724
12725 PIPE_CONF_CHECK_X(gmch_pfit.control);
12726 /* pfit ratios are autocomputed by the hw on gen4+ */
12727 if (INTEL_INFO(dev)->gen < 4)
12728 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12729 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12730
12731 if (!adjust) {
12732 PIPE_CONF_CHECK_I(pipe_src_w);
12733 PIPE_CONF_CHECK_I(pipe_src_h);
12734
12735 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12736 if (current_config->pch_pfit.enabled) {
12737 PIPE_CONF_CHECK_X(pch_pfit.pos);
12738 PIPE_CONF_CHECK_X(pch_pfit.size);
12739 }
12740
12741 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12742 }
12743
12744 /* BDW+ don't expose a synchronous way to read the state */
12745 if (IS_HASWELL(dev))
12746 PIPE_CONF_CHECK_I(ips_enabled);
12747
12748 PIPE_CONF_CHECK_I(double_wide);
12749
12750 PIPE_CONF_CHECK_X(ddi_pll_sel);
12751
12752 PIPE_CONF_CHECK_P(shared_dpll);
12753 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12754 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12755 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12756 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12757 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12758 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12759 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12760 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12761 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12762
12763 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12764 PIPE_CONF_CHECK_X(dsi_pll.div);
12765
12766 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12767 PIPE_CONF_CHECK_I(pipe_bpp);
12768
12769 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12770 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12771
12772 #undef PIPE_CONF_CHECK_X
12773 #undef PIPE_CONF_CHECK_I
12774 #undef PIPE_CONF_CHECK_P
12775 #undef PIPE_CONF_CHECK_FLAGS
12776 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12777 #undef PIPE_CONF_QUIRK
12778 #undef INTEL_ERR_OR_DBG_KMS
12779
12780 return ret;
12781 }
12782
12783 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12784 const struct intel_crtc_state *pipe_config)
12785 {
12786 if (pipe_config->has_pch_encoder) {
12787 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12788 &pipe_config->fdi_m_n);
12789 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12790
12791 /*
12792 * FDI already provided one idea for the dotclock.
12793 * Yell if the encoder disagrees.
12794 */
12795 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12796 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12797 fdi_dotclock, dotclock);
12798 }
12799 }
12800
12801 static void verify_wm_state(struct drm_crtc *crtc,
12802 struct drm_crtc_state *new_state)
12803 {
12804 struct drm_device *dev = crtc->dev;
12805 struct drm_i915_private *dev_priv = dev->dev_private;
12806 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12807 struct skl_ddb_entry *hw_entry, *sw_entry;
12808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12809 const enum pipe pipe = intel_crtc->pipe;
12810 int plane;
12811
12812 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12813 return;
12814
12815 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12816 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12817
12818 /* planes */
12819 for_each_plane(dev_priv, pipe, plane) {
12820 hw_entry = &hw_ddb.plane[pipe][plane];
12821 sw_entry = &sw_ddb->plane[pipe][plane];
12822
12823 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12824 continue;
12825
12826 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12827 "(expected (%u,%u), found (%u,%u))\n",
12828 pipe_name(pipe), plane + 1,
12829 sw_entry->start, sw_entry->end,
12830 hw_entry->start, hw_entry->end);
12831 }
12832
12833 /* cursor */
12834 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12835 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12836
12837 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12838 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12839 "(expected (%u,%u), found (%u,%u))\n",
12840 pipe_name(pipe),
12841 sw_entry->start, sw_entry->end,
12842 hw_entry->start, hw_entry->end);
12843 }
12844 }
12845
12846 static void
12847 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12848 {
12849 struct drm_connector *connector;
12850
12851 drm_for_each_connector(connector, dev) {
12852 struct drm_encoder *encoder = connector->encoder;
12853 struct drm_connector_state *state = connector->state;
12854
12855 if (state->crtc != crtc)
12856 continue;
12857
12858 intel_connector_verify_state(to_intel_connector(connector));
12859
12860 I915_STATE_WARN(state->best_encoder != encoder,
12861 "connector's atomic encoder doesn't match legacy encoder\n");
12862 }
12863 }
12864
12865 static void
12866 verify_encoder_state(struct drm_device *dev)
12867 {
12868 struct intel_encoder *encoder;
12869 struct intel_connector *connector;
12870
12871 for_each_intel_encoder(dev, encoder) {
12872 bool enabled = false;
12873 enum pipe pipe;
12874
12875 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12876 encoder->base.base.id,
12877 encoder->base.name);
12878
12879 for_each_intel_connector(dev, connector) {
12880 if (connector->base.state->best_encoder != &encoder->base)
12881 continue;
12882 enabled = true;
12883
12884 I915_STATE_WARN(connector->base.state->crtc !=
12885 encoder->base.crtc,
12886 "connector's crtc doesn't match encoder crtc\n");
12887 }
12888
12889 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12890 "encoder's enabled state mismatch "
12891 "(expected %i, found %i)\n",
12892 !!encoder->base.crtc, enabled);
12893
12894 if (!encoder->base.crtc) {
12895 bool active;
12896
12897 active = encoder->get_hw_state(encoder, &pipe);
12898 I915_STATE_WARN(active,
12899 "encoder detached but still enabled on pipe %c.\n",
12900 pipe_name(pipe));
12901 }
12902 }
12903 }
12904
12905 static void
12906 verify_crtc_state(struct drm_crtc *crtc,
12907 struct drm_crtc_state *old_crtc_state,
12908 struct drm_crtc_state *new_crtc_state)
12909 {
12910 struct drm_device *dev = crtc->dev;
12911 struct drm_i915_private *dev_priv = dev->dev_private;
12912 struct intel_encoder *encoder;
12913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12914 struct intel_crtc_state *pipe_config, *sw_config;
12915 struct drm_atomic_state *old_state;
12916 bool active;
12917
12918 old_state = old_crtc_state->state;
12919 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12920 pipe_config = to_intel_crtc_state(old_crtc_state);
12921 memset(pipe_config, 0, sizeof(*pipe_config));
12922 pipe_config->base.crtc = crtc;
12923 pipe_config->base.state = old_state;
12924
12925 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12926
12927 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12928
12929 /* hw state is inconsistent with the pipe quirk */
12930 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12931 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12932 active = new_crtc_state->active;
12933
12934 I915_STATE_WARN(new_crtc_state->active != active,
12935 "crtc active state doesn't match with hw state "
12936 "(expected %i, found %i)\n", new_crtc_state->active, active);
12937
12938 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12939 "transitional active state does not match atomic hw state "
12940 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12941
12942 for_each_encoder_on_crtc(dev, crtc, encoder) {
12943 enum pipe pipe;
12944
12945 active = encoder->get_hw_state(encoder, &pipe);
12946 I915_STATE_WARN(active != new_crtc_state->active,
12947 "[ENCODER:%i] active %i with crtc active %i\n",
12948 encoder->base.base.id, active, new_crtc_state->active);
12949
12950 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12951 "Encoder connected to wrong pipe %c\n",
12952 pipe_name(pipe));
12953
12954 if (active)
12955 encoder->get_config(encoder, pipe_config);
12956 }
12957
12958 if (!new_crtc_state->active)
12959 return;
12960
12961 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12962
12963 sw_config = to_intel_crtc_state(crtc->state);
12964 if (!intel_pipe_config_compare(dev, sw_config,
12965 pipe_config, false)) {
12966 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12967 intel_dump_pipe_config(intel_crtc, pipe_config,
12968 "[hw state]");
12969 intel_dump_pipe_config(intel_crtc, sw_config,
12970 "[sw state]");
12971 }
12972 }
12973
12974 static void
12975 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12976 struct intel_shared_dpll *pll,
12977 struct drm_crtc *crtc,
12978 struct drm_crtc_state *new_state)
12979 {
12980 struct intel_dpll_hw_state dpll_hw_state;
12981 unsigned crtc_mask;
12982 bool active;
12983
12984 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12985
12986 DRM_DEBUG_KMS("%s\n", pll->name);
12987
12988 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12989
12990 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12991 I915_STATE_WARN(!pll->on && pll->active_mask,
12992 "pll in active use but not on in sw tracking\n");
12993 I915_STATE_WARN(pll->on && !pll->active_mask,
12994 "pll is on but not used by any active crtc\n");
12995 I915_STATE_WARN(pll->on != active,
12996 "pll on state mismatch (expected %i, found %i)\n",
12997 pll->on, active);
12998 }
12999
13000 if (!crtc) {
13001 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13002 "more active pll users than references: %x vs %x\n",
13003 pll->active_mask, pll->config.crtc_mask);
13004
13005 return;
13006 }
13007
13008 crtc_mask = 1 << drm_crtc_index(crtc);
13009
13010 if (new_state->active)
13011 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13012 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13013 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13014 else
13015 I915_STATE_WARN(pll->active_mask & crtc_mask,
13016 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13017 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13018
13019 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13020 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13021 crtc_mask, pll->config.crtc_mask);
13022
13023 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13024 &dpll_hw_state,
13025 sizeof(dpll_hw_state)),
13026 "pll hw state mismatch\n");
13027 }
13028
13029 static void
13030 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13031 struct drm_crtc_state *old_crtc_state,
13032 struct drm_crtc_state *new_crtc_state)
13033 {
13034 struct drm_i915_private *dev_priv = dev->dev_private;
13035 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13036 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13037
13038 if (new_state->shared_dpll)
13039 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13040
13041 if (old_state->shared_dpll &&
13042 old_state->shared_dpll != new_state->shared_dpll) {
13043 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13044 struct intel_shared_dpll *pll = old_state->shared_dpll;
13045
13046 I915_STATE_WARN(pll->active_mask & crtc_mask,
13047 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13048 pipe_name(drm_crtc_index(crtc)));
13049 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13050 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13051 pipe_name(drm_crtc_index(crtc)));
13052 }
13053 }
13054
13055 static void
13056 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13057 struct drm_crtc_state *old_state,
13058 struct drm_crtc_state *new_state)
13059 {
13060 if (!needs_modeset(new_state) &&
13061 !to_intel_crtc_state(new_state)->update_pipe)
13062 return;
13063
13064 verify_wm_state(crtc, new_state);
13065 verify_connector_state(crtc->dev, crtc);
13066 verify_crtc_state(crtc, old_state, new_state);
13067 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13068 }
13069
13070 static void
13071 verify_disabled_dpll_state(struct drm_device *dev)
13072 {
13073 struct drm_i915_private *dev_priv = dev->dev_private;
13074 int i;
13075
13076 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13077 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13078 }
13079
13080 static void
13081 intel_modeset_verify_disabled(struct drm_device *dev)
13082 {
13083 verify_encoder_state(dev);
13084 verify_connector_state(dev, NULL);
13085 verify_disabled_dpll_state(dev);
13086 }
13087
13088 static void update_scanline_offset(struct intel_crtc *crtc)
13089 {
13090 struct drm_device *dev = crtc->base.dev;
13091
13092 /*
13093 * The scanline counter increments at the leading edge of hsync.
13094 *
13095 * On most platforms it starts counting from vtotal-1 on the
13096 * first active line. That means the scanline counter value is
13097 * always one less than what we would expect. Ie. just after
13098 * start of vblank, which also occurs at start of hsync (on the
13099 * last active line), the scanline counter will read vblank_start-1.
13100 *
13101 * On gen2 the scanline counter starts counting from 1 instead
13102 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13103 * to keep the value positive), instead of adding one.
13104 *
13105 * On HSW+ the behaviour of the scanline counter depends on the output
13106 * type. For DP ports it behaves like most other platforms, but on HDMI
13107 * there's an extra 1 line difference. So we need to add two instead of
13108 * one to the value.
13109 */
13110 if (IS_GEN2(dev)) {
13111 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13112 int vtotal;
13113
13114 vtotal = adjusted_mode->crtc_vtotal;
13115 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13116 vtotal /= 2;
13117
13118 crtc->scanline_offset = vtotal - 1;
13119 } else if (HAS_DDI(dev) &&
13120 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13121 crtc->scanline_offset = 2;
13122 } else
13123 crtc->scanline_offset = 1;
13124 }
13125
13126 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13127 {
13128 struct drm_device *dev = state->dev;
13129 struct drm_i915_private *dev_priv = to_i915(dev);
13130 struct intel_shared_dpll_config *shared_dpll = NULL;
13131 struct drm_crtc *crtc;
13132 struct drm_crtc_state *crtc_state;
13133 int i;
13134
13135 if (!dev_priv->display.crtc_compute_clock)
13136 return;
13137
13138 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13140 struct intel_shared_dpll *old_dpll =
13141 to_intel_crtc_state(crtc->state)->shared_dpll;
13142
13143 if (!needs_modeset(crtc_state))
13144 continue;
13145
13146 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13147
13148 if (!old_dpll)
13149 continue;
13150
13151 if (!shared_dpll)
13152 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13153
13154 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13155 }
13156 }
13157
13158 /*
13159 * This implements the workaround described in the "notes" section of the mode
13160 * set sequence documentation. When going from no pipes or single pipe to
13161 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13162 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13163 */
13164 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13165 {
13166 struct drm_crtc_state *crtc_state;
13167 struct intel_crtc *intel_crtc;
13168 struct drm_crtc *crtc;
13169 struct intel_crtc_state *first_crtc_state = NULL;
13170 struct intel_crtc_state *other_crtc_state = NULL;
13171 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13172 int i;
13173
13174 /* look at all crtc's that are going to be enabled in during modeset */
13175 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13176 intel_crtc = to_intel_crtc(crtc);
13177
13178 if (!crtc_state->active || !needs_modeset(crtc_state))
13179 continue;
13180
13181 if (first_crtc_state) {
13182 other_crtc_state = to_intel_crtc_state(crtc_state);
13183 break;
13184 } else {
13185 first_crtc_state = to_intel_crtc_state(crtc_state);
13186 first_pipe = intel_crtc->pipe;
13187 }
13188 }
13189
13190 /* No workaround needed? */
13191 if (!first_crtc_state)
13192 return 0;
13193
13194 /* w/a possibly needed, check how many crtc's are already enabled. */
13195 for_each_intel_crtc(state->dev, intel_crtc) {
13196 struct intel_crtc_state *pipe_config;
13197
13198 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13199 if (IS_ERR(pipe_config))
13200 return PTR_ERR(pipe_config);
13201
13202 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13203
13204 if (!pipe_config->base.active ||
13205 needs_modeset(&pipe_config->base))
13206 continue;
13207
13208 /* 2 or more enabled crtcs means no need for w/a */
13209 if (enabled_pipe != INVALID_PIPE)
13210 return 0;
13211
13212 enabled_pipe = intel_crtc->pipe;
13213 }
13214
13215 if (enabled_pipe != INVALID_PIPE)
13216 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13217 else if (other_crtc_state)
13218 other_crtc_state->hsw_workaround_pipe = first_pipe;
13219
13220 return 0;
13221 }
13222
13223 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13224 {
13225 struct drm_crtc *crtc;
13226 struct drm_crtc_state *crtc_state;
13227 int ret = 0;
13228
13229 /* add all active pipes to the state */
13230 for_each_crtc(state->dev, crtc) {
13231 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13232 if (IS_ERR(crtc_state))
13233 return PTR_ERR(crtc_state);
13234
13235 if (!crtc_state->active || needs_modeset(crtc_state))
13236 continue;
13237
13238 crtc_state->mode_changed = true;
13239
13240 ret = drm_atomic_add_affected_connectors(state, crtc);
13241 if (ret)
13242 break;
13243
13244 ret = drm_atomic_add_affected_planes(state, crtc);
13245 if (ret)
13246 break;
13247 }
13248
13249 return ret;
13250 }
13251
13252 static int intel_modeset_checks(struct drm_atomic_state *state)
13253 {
13254 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13255 struct drm_i915_private *dev_priv = state->dev->dev_private;
13256 struct drm_crtc *crtc;
13257 struct drm_crtc_state *crtc_state;
13258 int ret = 0, i;
13259
13260 if (!check_digital_port_conflicts(state)) {
13261 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13262 return -EINVAL;
13263 }
13264
13265 intel_state->modeset = true;
13266 intel_state->active_crtcs = dev_priv->active_crtcs;
13267
13268 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13269 if (crtc_state->active)
13270 intel_state->active_crtcs |= 1 << i;
13271 else
13272 intel_state->active_crtcs &= ~(1 << i);
13273
13274 if (crtc_state->active != crtc->state->active)
13275 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13276 }
13277
13278 /*
13279 * See if the config requires any additional preparation, e.g.
13280 * to adjust global state with pipes off. We need to do this
13281 * here so we can get the modeset_pipe updated config for the new
13282 * mode set on this crtc. For other crtcs we need to use the
13283 * adjusted_mode bits in the crtc directly.
13284 */
13285 if (dev_priv->display.modeset_calc_cdclk) {
13286 ret = dev_priv->display.modeset_calc_cdclk(state);
13287
13288 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13289 ret = intel_modeset_all_pipes(state);
13290
13291 if (ret < 0)
13292 return ret;
13293
13294 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13295 intel_state->cdclk, intel_state->dev_cdclk);
13296 } else
13297 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13298
13299 intel_modeset_clear_plls(state);
13300
13301 if (IS_HASWELL(dev_priv))
13302 return haswell_mode_set_planes_workaround(state);
13303
13304 return 0;
13305 }
13306
13307 /*
13308 * Handle calculation of various watermark data at the end of the atomic check
13309 * phase. The code here should be run after the per-crtc and per-plane 'check'
13310 * handlers to ensure that all derived state has been updated.
13311 */
13312 static void calc_watermark_data(struct drm_atomic_state *state)
13313 {
13314 struct drm_device *dev = state->dev;
13315 struct drm_i915_private *dev_priv = to_i915(dev);
13316 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13317 struct drm_crtc *crtc;
13318 struct drm_crtc_state *cstate;
13319 struct drm_plane *plane;
13320 struct drm_plane_state *pstate;
13321
13322 /*
13323 * Calculate watermark configuration details now that derived
13324 * plane/crtc state is all properly updated.
13325 */
13326 drm_for_each_crtc(crtc, dev) {
13327 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13328 crtc->state;
13329
13330 if (cstate->active)
13331 intel_state->wm_config.num_pipes_active++;
13332 }
13333 drm_for_each_legacy_plane(plane, dev) {
13334 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13335 plane->state;
13336
13337 if (!to_intel_plane_state(pstate)->visible)
13338 continue;
13339
13340 intel_state->wm_config.sprites_enabled = true;
13341 if (pstate->crtc_w != pstate->src_w >> 16 ||
13342 pstate->crtc_h != pstate->src_h >> 16)
13343 intel_state->wm_config.sprites_scaled = true;
13344 }
13345
13346 /* Is there platform-specific watermark information to calculate? */
13347 if (dev_priv->display.compute_global_watermarks)
13348 dev_priv->display.compute_global_watermarks(state);
13349 }
13350
13351 /**
13352 * intel_atomic_check - validate state object
13353 * @dev: drm device
13354 * @state: state to validate
13355 */
13356 static int intel_atomic_check(struct drm_device *dev,
13357 struct drm_atomic_state *state)
13358 {
13359 struct drm_i915_private *dev_priv = to_i915(dev);
13360 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13361 struct drm_crtc *crtc;
13362 struct drm_crtc_state *crtc_state;
13363 int ret, i;
13364 bool any_ms = false;
13365
13366 ret = drm_atomic_helper_check_modeset(dev, state);
13367 if (ret)
13368 return ret;
13369
13370 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13371 struct intel_crtc_state *pipe_config =
13372 to_intel_crtc_state(crtc_state);
13373
13374 /* Catch I915_MODE_FLAG_INHERITED */
13375 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13376 crtc_state->mode_changed = true;
13377
13378 if (!crtc_state->enable) {
13379 if (needs_modeset(crtc_state))
13380 any_ms = true;
13381 continue;
13382 }
13383
13384 if (!needs_modeset(crtc_state))
13385 continue;
13386
13387 /* FIXME: For only active_changed we shouldn't need to do any
13388 * state recomputation at all. */
13389
13390 ret = drm_atomic_add_affected_connectors(state, crtc);
13391 if (ret)
13392 return ret;
13393
13394 ret = intel_modeset_pipe_config(crtc, pipe_config);
13395 if (ret) {
13396 intel_dump_pipe_config(to_intel_crtc(crtc),
13397 pipe_config, "[failed]");
13398 return ret;
13399 }
13400
13401 if (i915.fastboot &&
13402 intel_pipe_config_compare(dev,
13403 to_intel_crtc_state(crtc->state),
13404 pipe_config, true)) {
13405 crtc_state->mode_changed = false;
13406 to_intel_crtc_state(crtc_state)->update_pipe = true;
13407 }
13408
13409 if (needs_modeset(crtc_state)) {
13410 any_ms = true;
13411
13412 ret = drm_atomic_add_affected_planes(state, crtc);
13413 if (ret)
13414 return ret;
13415 }
13416
13417 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13418 needs_modeset(crtc_state) ?
13419 "[modeset]" : "[fastset]");
13420 }
13421
13422 if (any_ms) {
13423 ret = intel_modeset_checks(state);
13424
13425 if (ret)
13426 return ret;
13427 } else
13428 intel_state->cdclk = dev_priv->cdclk_freq;
13429
13430 ret = drm_atomic_helper_check_planes(dev, state);
13431 if (ret)
13432 return ret;
13433
13434 intel_fbc_choose_crtc(dev_priv, state);
13435 calc_watermark_data(state);
13436
13437 return 0;
13438 }
13439
13440 static int intel_atomic_prepare_commit(struct drm_device *dev,
13441 struct drm_atomic_state *state,
13442 bool async)
13443 {
13444 struct drm_i915_private *dev_priv = dev->dev_private;
13445 struct drm_plane_state *plane_state;
13446 struct drm_crtc_state *crtc_state;
13447 struct drm_plane *plane;
13448 struct drm_crtc *crtc;
13449 int i, ret;
13450
13451 if (async) {
13452 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13453 return -EINVAL;
13454 }
13455
13456 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13457 if (state->legacy_cursor_update)
13458 continue;
13459
13460 ret = intel_crtc_wait_for_pending_flips(crtc);
13461 if (ret)
13462 return ret;
13463
13464 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13465 flush_workqueue(dev_priv->wq);
13466 }
13467
13468 ret = mutex_lock_interruptible(&dev->struct_mutex);
13469 if (ret)
13470 return ret;
13471
13472 ret = drm_atomic_helper_prepare_planes(dev, state);
13473 mutex_unlock(&dev->struct_mutex);
13474
13475 if (!ret && !async) {
13476 for_each_plane_in_state(state, plane, plane_state, i) {
13477 struct intel_plane_state *intel_plane_state =
13478 to_intel_plane_state(plane_state);
13479
13480 if (!intel_plane_state->wait_req)
13481 continue;
13482
13483 ret = __i915_wait_request(intel_plane_state->wait_req,
13484 true, NULL, NULL);
13485 if (ret) {
13486 /* Any hang should be swallowed by the wait */
13487 WARN_ON(ret == -EIO);
13488 mutex_lock(&dev->struct_mutex);
13489 drm_atomic_helper_cleanup_planes(dev, state);
13490 mutex_unlock(&dev->struct_mutex);
13491 break;
13492 }
13493 }
13494 }
13495
13496 return ret;
13497 }
13498
13499 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13500 struct drm_i915_private *dev_priv,
13501 unsigned crtc_mask)
13502 {
13503 unsigned last_vblank_count[I915_MAX_PIPES];
13504 enum pipe pipe;
13505 int ret;
13506
13507 if (!crtc_mask)
13508 return;
13509
13510 for_each_pipe(dev_priv, pipe) {
13511 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13512
13513 if (!((1 << pipe) & crtc_mask))
13514 continue;
13515
13516 ret = drm_crtc_vblank_get(crtc);
13517 if (WARN_ON(ret != 0)) {
13518 crtc_mask &= ~(1 << pipe);
13519 continue;
13520 }
13521
13522 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13523 }
13524
13525 for_each_pipe(dev_priv, pipe) {
13526 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13527 long lret;
13528
13529 if (!((1 << pipe) & crtc_mask))
13530 continue;
13531
13532 lret = wait_event_timeout(dev->vblank[pipe].queue,
13533 last_vblank_count[pipe] !=
13534 drm_crtc_vblank_count(crtc),
13535 msecs_to_jiffies(50));
13536
13537 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13538
13539 drm_crtc_vblank_put(crtc);
13540 }
13541 }
13542
13543 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13544 {
13545 /* fb updated, need to unpin old fb */
13546 if (crtc_state->fb_changed)
13547 return true;
13548
13549 /* wm changes, need vblank before final wm's */
13550 if (crtc_state->update_wm_post)
13551 return true;
13552
13553 /*
13554 * cxsr is re-enabled after vblank.
13555 * This is already handled by crtc_state->update_wm_post,
13556 * but added for clarity.
13557 */
13558 if (crtc_state->disable_cxsr)
13559 return true;
13560
13561 return false;
13562 }
13563
13564 /**
13565 * intel_atomic_commit - commit validated state object
13566 * @dev: DRM device
13567 * @state: the top-level driver state object
13568 * @async: asynchronous commit
13569 *
13570 * This function commits a top-level state object that has been validated
13571 * with drm_atomic_helper_check().
13572 *
13573 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13574 * we can only handle plane-related operations and do not yet support
13575 * asynchronous commit.
13576 *
13577 * RETURNS
13578 * Zero for success or -errno.
13579 */
13580 static int intel_atomic_commit(struct drm_device *dev,
13581 struct drm_atomic_state *state,
13582 bool async)
13583 {
13584 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13585 struct drm_i915_private *dev_priv = dev->dev_private;
13586 struct drm_crtc_state *old_crtc_state;
13587 struct drm_crtc *crtc;
13588 struct intel_crtc_state *intel_cstate;
13589 int ret = 0, i;
13590 bool hw_check = intel_state->modeset;
13591 unsigned long put_domains[I915_MAX_PIPES] = {};
13592 unsigned crtc_vblank_mask = 0;
13593
13594 ret = intel_atomic_prepare_commit(dev, state, async);
13595 if (ret) {
13596 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13597 return ret;
13598 }
13599
13600 drm_atomic_helper_swap_state(dev, state);
13601 dev_priv->wm.config = intel_state->wm_config;
13602 dev_priv->wm.distrust_bios_wm = false;
13603 dev_priv->wm.skl_results.ddb = intel_state->ddb;
13604 intel_shared_dpll_commit(state);
13605
13606 if (intel_state->modeset) {
13607 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13608 sizeof(intel_state->min_pixclk));
13609 dev_priv->active_crtcs = intel_state->active_crtcs;
13610 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13611
13612 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13613 }
13614
13615 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13617
13618 if (needs_modeset(crtc->state) ||
13619 to_intel_crtc_state(crtc->state)->update_pipe) {
13620 hw_check = true;
13621
13622 put_domains[to_intel_crtc(crtc)->pipe] =
13623 modeset_get_crtc_power_domains(crtc,
13624 to_intel_crtc_state(crtc->state));
13625 }
13626
13627 if (!needs_modeset(crtc->state))
13628 continue;
13629
13630 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13631
13632 if (old_crtc_state->active) {
13633 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13634 dev_priv->display.crtc_disable(crtc);
13635 intel_crtc->active = false;
13636 intel_fbc_disable(intel_crtc);
13637 intel_disable_shared_dpll(intel_crtc);
13638
13639 /*
13640 * Underruns don't always raise
13641 * interrupts, so check manually.
13642 */
13643 intel_check_cpu_fifo_underruns(dev_priv);
13644 intel_check_pch_fifo_underruns(dev_priv);
13645
13646 if (!crtc->state->active)
13647 intel_update_watermarks(crtc);
13648 }
13649 }
13650
13651 /* Only after disabling all output pipelines that will be changed can we
13652 * update the the output configuration. */
13653 intel_modeset_update_crtc_state(state);
13654
13655 if (intel_state->modeset) {
13656 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13657
13658 if (dev_priv->display.modeset_commit_cdclk &&
13659 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13660 dev_priv->display.modeset_commit_cdclk(state);
13661
13662 intel_modeset_verify_disabled(dev);
13663 }
13664
13665 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13666 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13668 bool modeset = needs_modeset(crtc->state);
13669 struct intel_crtc_state *pipe_config =
13670 to_intel_crtc_state(crtc->state);
13671 bool update_pipe = !modeset && pipe_config->update_pipe;
13672
13673 if (modeset && crtc->state->active) {
13674 update_scanline_offset(to_intel_crtc(crtc));
13675 dev_priv->display.crtc_enable(crtc);
13676 }
13677
13678 if (!modeset)
13679 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13680
13681 if (crtc->state->active &&
13682 drm_atomic_get_existing_plane_state(state, crtc->primary))
13683 intel_fbc_enable(intel_crtc);
13684
13685 if (crtc->state->active &&
13686 (crtc->state->planes_changed || update_pipe))
13687 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13688
13689 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13690 crtc_vblank_mask |= 1 << i;
13691 }
13692
13693 /* FIXME: add subpixel order */
13694
13695 if (!state->legacy_cursor_update)
13696 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13697
13698 /*
13699 * Now that the vblank has passed, we can go ahead and program the
13700 * optimal watermarks on platforms that need two-step watermark
13701 * programming.
13702 *
13703 * TODO: Move this (and other cleanup) to an async worker eventually.
13704 */
13705 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13706 intel_cstate = to_intel_crtc_state(crtc->state);
13707
13708 if (dev_priv->display.optimize_watermarks)
13709 dev_priv->display.optimize_watermarks(intel_cstate);
13710 }
13711
13712 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13713 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13714
13715 if (put_domains[i])
13716 modeset_put_power_domains(dev_priv, put_domains[i]);
13717
13718 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13719 }
13720
13721 if (intel_state->modeset)
13722 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13723
13724 mutex_lock(&dev->struct_mutex);
13725 drm_atomic_helper_cleanup_planes(dev, state);
13726 mutex_unlock(&dev->struct_mutex);
13727
13728 drm_atomic_state_free(state);
13729
13730 /* As one of the primary mmio accessors, KMS has a high likelihood
13731 * of triggering bugs in unclaimed access. After we finish
13732 * modesetting, see if an error has been flagged, and if so
13733 * enable debugging for the next modeset - and hope we catch
13734 * the culprit.
13735 *
13736 * XXX note that we assume display power is on at this point.
13737 * This might hold true now but we need to add pm helper to check
13738 * unclaimed only when the hardware is on, as atomic commits
13739 * can happen also when the device is completely off.
13740 */
13741 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13742
13743 return 0;
13744 }
13745
13746 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13747 {
13748 struct drm_device *dev = crtc->dev;
13749 struct drm_atomic_state *state;
13750 struct drm_crtc_state *crtc_state;
13751 int ret;
13752
13753 state = drm_atomic_state_alloc(dev);
13754 if (!state) {
13755 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13756 crtc->base.id);
13757 return;
13758 }
13759
13760 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13761
13762 retry:
13763 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13764 ret = PTR_ERR_OR_ZERO(crtc_state);
13765 if (!ret) {
13766 if (!crtc_state->active)
13767 goto out;
13768
13769 crtc_state->mode_changed = true;
13770 ret = drm_atomic_commit(state);
13771 }
13772
13773 if (ret == -EDEADLK) {
13774 drm_atomic_state_clear(state);
13775 drm_modeset_backoff(state->acquire_ctx);
13776 goto retry;
13777 }
13778
13779 if (ret)
13780 out:
13781 drm_atomic_state_free(state);
13782 }
13783
13784 #undef for_each_intel_crtc_masked
13785
13786 static const struct drm_crtc_funcs intel_crtc_funcs = {
13787 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13788 .set_config = drm_atomic_helper_set_config,
13789 .set_property = drm_atomic_helper_crtc_set_property,
13790 .destroy = intel_crtc_destroy,
13791 .page_flip = intel_crtc_page_flip,
13792 .atomic_duplicate_state = intel_crtc_duplicate_state,
13793 .atomic_destroy_state = intel_crtc_destroy_state,
13794 };
13795
13796 /**
13797 * intel_prepare_plane_fb - Prepare fb for usage on plane
13798 * @plane: drm plane to prepare for
13799 * @fb: framebuffer to prepare for presentation
13800 *
13801 * Prepares a framebuffer for usage on a display plane. Generally this
13802 * involves pinning the underlying object and updating the frontbuffer tracking
13803 * bits. Some older platforms need special physical address handling for
13804 * cursor planes.
13805 *
13806 * Must be called with struct_mutex held.
13807 *
13808 * Returns 0 on success, negative error code on failure.
13809 */
13810 int
13811 intel_prepare_plane_fb(struct drm_plane *plane,
13812 const struct drm_plane_state *new_state)
13813 {
13814 struct drm_device *dev = plane->dev;
13815 struct drm_framebuffer *fb = new_state->fb;
13816 struct intel_plane *intel_plane = to_intel_plane(plane);
13817 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13818 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13819 int ret = 0;
13820
13821 if (!obj && !old_obj)
13822 return 0;
13823
13824 if (old_obj) {
13825 struct drm_crtc_state *crtc_state =
13826 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13827
13828 /* Big Hammer, we also need to ensure that any pending
13829 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13830 * current scanout is retired before unpinning the old
13831 * framebuffer. Note that we rely on userspace rendering
13832 * into the buffer attached to the pipe they are waiting
13833 * on. If not, userspace generates a GPU hang with IPEHR
13834 * point to the MI_WAIT_FOR_EVENT.
13835 *
13836 * This should only fail upon a hung GPU, in which case we
13837 * can safely continue.
13838 */
13839 if (needs_modeset(crtc_state))
13840 ret = i915_gem_object_wait_rendering(old_obj, true);
13841 if (ret) {
13842 /* GPU hangs should have been swallowed by the wait */
13843 WARN_ON(ret == -EIO);
13844 return ret;
13845 }
13846 }
13847
13848 /* For framebuffer backed by dmabuf, wait for fence */
13849 if (obj && obj->base.dma_buf) {
13850 long lret;
13851
13852 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13853 false, true,
13854 MAX_SCHEDULE_TIMEOUT);
13855 if (lret == -ERESTARTSYS)
13856 return lret;
13857
13858 WARN(lret < 0, "waiting returns %li\n", lret);
13859 }
13860
13861 if (!obj) {
13862 ret = 0;
13863 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13864 INTEL_INFO(dev)->cursor_needs_physical) {
13865 int align = IS_I830(dev) ? 16 * 1024 : 256;
13866 ret = i915_gem_object_attach_phys(obj, align);
13867 if (ret)
13868 DRM_DEBUG_KMS("failed to attach phys object\n");
13869 } else {
13870 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13871 }
13872
13873 if (ret == 0) {
13874 if (obj) {
13875 struct intel_plane_state *plane_state =
13876 to_intel_plane_state(new_state);
13877
13878 i915_gem_request_assign(&plane_state->wait_req,
13879 obj->last_write_req);
13880 }
13881
13882 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13883 }
13884
13885 return ret;
13886 }
13887
13888 /**
13889 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13890 * @plane: drm plane to clean up for
13891 * @fb: old framebuffer that was on plane
13892 *
13893 * Cleans up a framebuffer that has just been removed from a plane.
13894 *
13895 * Must be called with struct_mutex held.
13896 */
13897 void
13898 intel_cleanup_plane_fb(struct drm_plane *plane,
13899 const struct drm_plane_state *old_state)
13900 {
13901 struct drm_device *dev = plane->dev;
13902 struct intel_plane *intel_plane = to_intel_plane(plane);
13903 struct intel_plane_state *old_intel_state;
13904 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13905 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13906
13907 old_intel_state = to_intel_plane_state(old_state);
13908
13909 if (!obj && !old_obj)
13910 return;
13911
13912 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13913 !INTEL_INFO(dev)->cursor_needs_physical))
13914 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13915
13916 /* prepare_fb aborted? */
13917 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13918 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13919 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13920
13921 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13922 }
13923
13924 int
13925 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13926 {
13927 int max_scale;
13928 struct drm_device *dev;
13929 struct drm_i915_private *dev_priv;
13930 int crtc_clock, cdclk;
13931
13932 if (!intel_crtc || !crtc_state->base.enable)
13933 return DRM_PLANE_HELPER_NO_SCALING;
13934
13935 dev = intel_crtc->base.dev;
13936 dev_priv = dev->dev_private;
13937 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13938 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13939
13940 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13941 return DRM_PLANE_HELPER_NO_SCALING;
13942
13943 /*
13944 * skl max scale is lower of:
13945 * close to 3 but not 3, -1 is for that purpose
13946 * or
13947 * cdclk/crtc_clock
13948 */
13949 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13950
13951 return max_scale;
13952 }
13953
13954 static int
13955 intel_check_primary_plane(struct drm_plane *plane,
13956 struct intel_crtc_state *crtc_state,
13957 struct intel_plane_state *state)
13958 {
13959 struct drm_crtc *crtc = state->base.crtc;
13960 struct drm_framebuffer *fb = state->base.fb;
13961 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13962 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13963 bool can_position = false;
13964
13965 if (INTEL_INFO(plane->dev)->gen >= 9) {
13966 /* use scaler when colorkey is not required */
13967 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13968 min_scale = 1;
13969 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13970 }
13971 can_position = true;
13972 }
13973
13974 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13975 &state->dst, &state->clip,
13976 min_scale, max_scale,
13977 can_position, true,
13978 &state->visible);
13979 }
13980
13981 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13982 struct drm_crtc_state *old_crtc_state)
13983 {
13984 struct drm_device *dev = crtc->dev;
13985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13986 struct intel_crtc_state *old_intel_state =
13987 to_intel_crtc_state(old_crtc_state);
13988 bool modeset = needs_modeset(crtc->state);
13989
13990 /* Perform vblank evasion around commit operation */
13991 intel_pipe_update_start(intel_crtc);
13992
13993 if (modeset)
13994 return;
13995
13996 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13997 intel_color_set_csc(crtc->state);
13998 intel_color_load_luts(crtc->state);
13999 }
14000
14001 if (to_intel_crtc_state(crtc->state)->update_pipe)
14002 intel_update_pipe_config(intel_crtc, old_intel_state);
14003 else if (INTEL_INFO(dev)->gen >= 9)
14004 skl_detach_scalers(intel_crtc);
14005 }
14006
14007 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14008 struct drm_crtc_state *old_crtc_state)
14009 {
14010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14011
14012 intel_pipe_update_end(intel_crtc);
14013 }
14014
14015 /**
14016 * intel_plane_destroy - destroy a plane
14017 * @plane: plane to destroy
14018 *
14019 * Common destruction function for all types of planes (primary, cursor,
14020 * sprite).
14021 */
14022 void intel_plane_destroy(struct drm_plane *plane)
14023 {
14024 struct intel_plane *intel_plane = to_intel_plane(plane);
14025 drm_plane_cleanup(plane);
14026 kfree(intel_plane);
14027 }
14028
14029 const struct drm_plane_funcs intel_plane_funcs = {
14030 .update_plane = drm_atomic_helper_update_plane,
14031 .disable_plane = drm_atomic_helper_disable_plane,
14032 .destroy = intel_plane_destroy,
14033 .set_property = drm_atomic_helper_plane_set_property,
14034 .atomic_get_property = intel_plane_atomic_get_property,
14035 .atomic_set_property = intel_plane_atomic_set_property,
14036 .atomic_duplicate_state = intel_plane_duplicate_state,
14037 .atomic_destroy_state = intel_plane_destroy_state,
14038
14039 };
14040
14041 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14042 int pipe)
14043 {
14044 struct intel_plane *primary = NULL;
14045 struct intel_plane_state *state = NULL;
14046 const uint32_t *intel_primary_formats;
14047 unsigned int num_formats;
14048 int ret;
14049
14050 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14051 if (!primary)
14052 goto fail;
14053
14054 state = intel_create_plane_state(&primary->base);
14055 if (!state)
14056 goto fail;
14057 primary->base.state = &state->base;
14058
14059 primary->can_scale = false;
14060 primary->max_downscale = 1;
14061 if (INTEL_INFO(dev)->gen >= 9) {
14062 primary->can_scale = true;
14063 state->scaler_id = -1;
14064 }
14065 primary->pipe = pipe;
14066 primary->plane = pipe;
14067 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14068 primary->check_plane = intel_check_primary_plane;
14069 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14070 primary->plane = !pipe;
14071
14072 if (INTEL_INFO(dev)->gen >= 9) {
14073 intel_primary_formats = skl_primary_formats;
14074 num_formats = ARRAY_SIZE(skl_primary_formats);
14075
14076 primary->update_plane = skylake_update_primary_plane;
14077 primary->disable_plane = skylake_disable_primary_plane;
14078 } else if (HAS_PCH_SPLIT(dev)) {
14079 intel_primary_formats = i965_primary_formats;
14080 num_formats = ARRAY_SIZE(i965_primary_formats);
14081
14082 primary->update_plane = ironlake_update_primary_plane;
14083 primary->disable_plane = i9xx_disable_primary_plane;
14084 } else if (INTEL_INFO(dev)->gen >= 4) {
14085 intel_primary_formats = i965_primary_formats;
14086 num_formats = ARRAY_SIZE(i965_primary_formats);
14087
14088 primary->update_plane = i9xx_update_primary_plane;
14089 primary->disable_plane = i9xx_disable_primary_plane;
14090 } else {
14091 intel_primary_formats = i8xx_primary_formats;
14092 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14093
14094 primary->update_plane = i9xx_update_primary_plane;
14095 primary->disable_plane = i9xx_disable_primary_plane;
14096 }
14097
14098 ret = drm_universal_plane_init(dev, &primary->base, 0,
14099 &intel_plane_funcs,
14100 intel_primary_formats, num_formats,
14101 DRM_PLANE_TYPE_PRIMARY, NULL);
14102 if (ret)
14103 goto fail;
14104
14105 if (INTEL_INFO(dev)->gen >= 4)
14106 intel_create_rotation_property(dev, primary);
14107
14108 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14109
14110 return &primary->base;
14111
14112 fail:
14113 kfree(state);
14114 kfree(primary);
14115
14116 return NULL;
14117 }
14118
14119 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14120 {
14121 if (!dev->mode_config.rotation_property) {
14122 unsigned long flags = BIT(DRM_ROTATE_0) |
14123 BIT(DRM_ROTATE_180);
14124
14125 if (INTEL_INFO(dev)->gen >= 9)
14126 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14127
14128 dev->mode_config.rotation_property =
14129 drm_mode_create_rotation_property(dev, flags);
14130 }
14131 if (dev->mode_config.rotation_property)
14132 drm_object_attach_property(&plane->base.base,
14133 dev->mode_config.rotation_property,
14134 plane->base.state->rotation);
14135 }
14136
14137 static int
14138 intel_check_cursor_plane(struct drm_plane *plane,
14139 struct intel_crtc_state *crtc_state,
14140 struct intel_plane_state *state)
14141 {
14142 struct drm_crtc *crtc = crtc_state->base.crtc;
14143 struct drm_framebuffer *fb = state->base.fb;
14144 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14145 enum pipe pipe = to_intel_plane(plane)->pipe;
14146 unsigned stride;
14147 int ret;
14148
14149 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14150 &state->dst, &state->clip,
14151 DRM_PLANE_HELPER_NO_SCALING,
14152 DRM_PLANE_HELPER_NO_SCALING,
14153 true, true, &state->visible);
14154 if (ret)
14155 return ret;
14156
14157 /* if we want to turn off the cursor ignore width and height */
14158 if (!obj)
14159 return 0;
14160
14161 /* Check for which cursor types we support */
14162 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14163 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14164 state->base.crtc_w, state->base.crtc_h);
14165 return -EINVAL;
14166 }
14167
14168 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14169 if (obj->base.size < stride * state->base.crtc_h) {
14170 DRM_DEBUG_KMS("buffer is too small\n");
14171 return -ENOMEM;
14172 }
14173
14174 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14175 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14176 return -EINVAL;
14177 }
14178
14179 /*
14180 * There's something wrong with the cursor on CHV pipe C.
14181 * If it straddles the left edge of the screen then
14182 * moving it away from the edge or disabling it often
14183 * results in a pipe underrun, and often that can lead to
14184 * dead pipe (constant underrun reported, and it scans
14185 * out just a solid color). To recover from that, the
14186 * display power well must be turned off and on again.
14187 * Refuse the put the cursor into that compromised position.
14188 */
14189 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14190 state->visible && state->base.crtc_x < 0) {
14191 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14192 return -EINVAL;
14193 }
14194
14195 return 0;
14196 }
14197
14198 static void
14199 intel_disable_cursor_plane(struct drm_plane *plane,
14200 struct drm_crtc *crtc)
14201 {
14202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14203
14204 intel_crtc->cursor_addr = 0;
14205 intel_crtc_update_cursor(crtc, NULL);
14206 }
14207
14208 static void
14209 intel_update_cursor_plane(struct drm_plane *plane,
14210 const struct intel_crtc_state *crtc_state,
14211 const struct intel_plane_state *state)
14212 {
14213 struct drm_crtc *crtc = crtc_state->base.crtc;
14214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14215 struct drm_device *dev = plane->dev;
14216 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14217 uint32_t addr;
14218
14219 if (!obj)
14220 addr = 0;
14221 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14222 addr = i915_gem_obj_ggtt_offset(obj);
14223 else
14224 addr = obj->phys_handle->busaddr;
14225
14226 intel_crtc->cursor_addr = addr;
14227 intel_crtc_update_cursor(crtc, state);
14228 }
14229
14230 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14231 int pipe)
14232 {
14233 struct intel_plane *cursor = NULL;
14234 struct intel_plane_state *state = NULL;
14235 int ret;
14236
14237 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14238 if (!cursor)
14239 goto fail;
14240
14241 state = intel_create_plane_state(&cursor->base);
14242 if (!state)
14243 goto fail;
14244 cursor->base.state = &state->base;
14245
14246 cursor->can_scale = false;
14247 cursor->max_downscale = 1;
14248 cursor->pipe = pipe;
14249 cursor->plane = pipe;
14250 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14251 cursor->check_plane = intel_check_cursor_plane;
14252 cursor->update_plane = intel_update_cursor_plane;
14253 cursor->disable_plane = intel_disable_cursor_plane;
14254
14255 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14256 &intel_plane_funcs,
14257 intel_cursor_formats,
14258 ARRAY_SIZE(intel_cursor_formats),
14259 DRM_PLANE_TYPE_CURSOR, NULL);
14260 if (ret)
14261 goto fail;
14262
14263 if (INTEL_INFO(dev)->gen >= 4) {
14264 if (!dev->mode_config.rotation_property)
14265 dev->mode_config.rotation_property =
14266 drm_mode_create_rotation_property(dev,
14267 BIT(DRM_ROTATE_0) |
14268 BIT(DRM_ROTATE_180));
14269 if (dev->mode_config.rotation_property)
14270 drm_object_attach_property(&cursor->base.base,
14271 dev->mode_config.rotation_property,
14272 state->base.rotation);
14273 }
14274
14275 if (INTEL_INFO(dev)->gen >=9)
14276 state->scaler_id = -1;
14277
14278 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14279
14280 return &cursor->base;
14281
14282 fail:
14283 kfree(state);
14284 kfree(cursor);
14285
14286 return NULL;
14287 }
14288
14289 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14290 struct intel_crtc_state *crtc_state)
14291 {
14292 int i;
14293 struct intel_scaler *intel_scaler;
14294 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14295
14296 for (i = 0; i < intel_crtc->num_scalers; i++) {
14297 intel_scaler = &scaler_state->scalers[i];
14298 intel_scaler->in_use = 0;
14299 intel_scaler->mode = PS_SCALER_MODE_DYN;
14300 }
14301
14302 scaler_state->scaler_id = -1;
14303 }
14304
14305 static void intel_crtc_init(struct drm_device *dev, int pipe)
14306 {
14307 struct drm_i915_private *dev_priv = dev->dev_private;
14308 struct intel_crtc *intel_crtc;
14309 struct intel_crtc_state *crtc_state = NULL;
14310 struct drm_plane *primary = NULL;
14311 struct drm_plane *cursor = NULL;
14312 int ret;
14313
14314 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14315 if (intel_crtc == NULL)
14316 return;
14317
14318 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14319 if (!crtc_state)
14320 goto fail;
14321 intel_crtc->config = crtc_state;
14322 intel_crtc->base.state = &crtc_state->base;
14323 crtc_state->base.crtc = &intel_crtc->base;
14324
14325 /* initialize shared scalers */
14326 if (INTEL_INFO(dev)->gen >= 9) {
14327 if (pipe == PIPE_C)
14328 intel_crtc->num_scalers = 1;
14329 else
14330 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14331
14332 skl_init_scalers(dev, intel_crtc, crtc_state);
14333 }
14334
14335 primary = intel_primary_plane_create(dev, pipe);
14336 if (!primary)
14337 goto fail;
14338
14339 cursor = intel_cursor_plane_create(dev, pipe);
14340 if (!cursor)
14341 goto fail;
14342
14343 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14344 cursor, &intel_crtc_funcs, NULL);
14345 if (ret)
14346 goto fail;
14347
14348 /*
14349 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14350 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14351 */
14352 intel_crtc->pipe = pipe;
14353 intel_crtc->plane = pipe;
14354 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14355 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14356 intel_crtc->plane = !pipe;
14357 }
14358
14359 intel_crtc->cursor_base = ~0;
14360 intel_crtc->cursor_cntl = ~0;
14361 intel_crtc->cursor_size = ~0;
14362
14363 intel_crtc->wm.cxsr_allowed = true;
14364
14365 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14366 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14367 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14368 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14369
14370 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14371
14372 intel_color_init(&intel_crtc->base);
14373
14374 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14375 return;
14376
14377 fail:
14378 if (primary)
14379 drm_plane_cleanup(primary);
14380 if (cursor)
14381 drm_plane_cleanup(cursor);
14382 kfree(crtc_state);
14383 kfree(intel_crtc);
14384 }
14385
14386 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14387 {
14388 struct drm_encoder *encoder = connector->base.encoder;
14389 struct drm_device *dev = connector->base.dev;
14390
14391 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14392
14393 if (!encoder || WARN_ON(!encoder->crtc))
14394 return INVALID_PIPE;
14395
14396 return to_intel_crtc(encoder->crtc)->pipe;
14397 }
14398
14399 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14400 struct drm_file *file)
14401 {
14402 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14403 struct drm_crtc *drmmode_crtc;
14404 struct intel_crtc *crtc;
14405
14406 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14407
14408 if (!drmmode_crtc) {
14409 DRM_ERROR("no such CRTC id\n");
14410 return -ENOENT;
14411 }
14412
14413 crtc = to_intel_crtc(drmmode_crtc);
14414 pipe_from_crtc_id->pipe = crtc->pipe;
14415
14416 return 0;
14417 }
14418
14419 static int intel_encoder_clones(struct intel_encoder *encoder)
14420 {
14421 struct drm_device *dev = encoder->base.dev;
14422 struct intel_encoder *source_encoder;
14423 int index_mask = 0;
14424 int entry = 0;
14425
14426 for_each_intel_encoder(dev, source_encoder) {
14427 if (encoders_cloneable(encoder, source_encoder))
14428 index_mask |= (1 << entry);
14429
14430 entry++;
14431 }
14432
14433 return index_mask;
14434 }
14435
14436 static bool has_edp_a(struct drm_device *dev)
14437 {
14438 struct drm_i915_private *dev_priv = dev->dev_private;
14439
14440 if (!IS_MOBILE(dev))
14441 return false;
14442
14443 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14444 return false;
14445
14446 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14447 return false;
14448
14449 return true;
14450 }
14451
14452 static bool intel_crt_present(struct drm_device *dev)
14453 {
14454 struct drm_i915_private *dev_priv = dev->dev_private;
14455
14456 if (INTEL_INFO(dev)->gen >= 9)
14457 return false;
14458
14459 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14460 return false;
14461
14462 if (IS_CHERRYVIEW(dev))
14463 return false;
14464
14465 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14466 return false;
14467
14468 /* DDI E can't be used if DDI A requires 4 lanes */
14469 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14470 return false;
14471
14472 if (!dev_priv->vbt.int_crt_support)
14473 return false;
14474
14475 return true;
14476 }
14477
14478 static void intel_setup_outputs(struct drm_device *dev)
14479 {
14480 struct drm_i915_private *dev_priv = dev->dev_private;
14481 struct intel_encoder *encoder;
14482 bool dpd_is_edp = false;
14483
14484 intel_lvds_init(dev);
14485
14486 if (intel_crt_present(dev))
14487 intel_crt_init(dev);
14488
14489 if (IS_BROXTON(dev)) {
14490 /*
14491 * FIXME: Broxton doesn't support port detection via the
14492 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14493 * detect the ports.
14494 */
14495 intel_ddi_init(dev, PORT_A);
14496 intel_ddi_init(dev, PORT_B);
14497 intel_ddi_init(dev, PORT_C);
14498
14499 intel_dsi_init(dev);
14500 } else if (HAS_DDI(dev)) {
14501 int found;
14502
14503 /*
14504 * Haswell uses DDI functions to detect digital outputs.
14505 * On SKL pre-D0 the strap isn't connected, so we assume
14506 * it's there.
14507 */
14508 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14509 /* WaIgnoreDDIAStrap: skl */
14510 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14511 intel_ddi_init(dev, PORT_A);
14512
14513 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14514 * register */
14515 found = I915_READ(SFUSE_STRAP);
14516
14517 if (found & SFUSE_STRAP_DDIB_DETECTED)
14518 intel_ddi_init(dev, PORT_B);
14519 if (found & SFUSE_STRAP_DDIC_DETECTED)
14520 intel_ddi_init(dev, PORT_C);
14521 if (found & SFUSE_STRAP_DDID_DETECTED)
14522 intel_ddi_init(dev, PORT_D);
14523 /*
14524 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14525 */
14526 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14527 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14528 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14529 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14530 intel_ddi_init(dev, PORT_E);
14531
14532 } else if (HAS_PCH_SPLIT(dev)) {
14533 int found;
14534 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14535
14536 if (has_edp_a(dev))
14537 intel_dp_init(dev, DP_A, PORT_A);
14538
14539 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14540 /* PCH SDVOB multiplex with HDMIB */
14541 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14542 if (!found)
14543 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14544 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14545 intel_dp_init(dev, PCH_DP_B, PORT_B);
14546 }
14547
14548 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14549 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14550
14551 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14552 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14553
14554 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14555 intel_dp_init(dev, PCH_DP_C, PORT_C);
14556
14557 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14558 intel_dp_init(dev, PCH_DP_D, PORT_D);
14559 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14560 /*
14561 * The DP_DETECTED bit is the latched state of the DDC
14562 * SDA pin at boot. However since eDP doesn't require DDC
14563 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14564 * eDP ports may have been muxed to an alternate function.
14565 * Thus we can't rely on the DP_DETECTED bit alone to detect
14566 * eDP ports. Consult the VBT as well as DP_DETECTED to
14567 * detect eDP ports.
14568 */
14569 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14570 !intel_dp_is_edp(dev, PORT_B))
14571 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14572 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14573 intel_dp_is_edp(dev, PORT_B))
14574 intel_dp_init(dev, VLV_DP_B, PORT_B);
14575
14576 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14577 !intel_dp_is_edp(dev, PORT_C))
14578 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14579 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14580 intel_dp_is_edp(dev, PORT_C))
14581 intel_dp_init(dev, VLV_DP_C, PORT_C);
14582
14583 if (IS_CHERRYVIEW(dev)) {
14584 /* eDP not supported on port D, so don't check VBT */
14585 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14586 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14587 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14588 intel_dp_init(dev, CHV_DP_D, PORT_D);
14589 }
14590
14591 intel_dsi_init(dev);
14592 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14593 bool found = false;
14594
14595 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14596 DRM_DEBUG_KMS("probing SDVOB\n");
14597 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14598 if (!found && IS_G4X(dev)) {
14599 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14600 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14601 }
14602
14603 if (!found && IS_G4X(dev))
14604 intel_dp_init(dev, DP_B, PORT_B);
14605 }
14606
14607 /* Before G4X SDVOC doesn't have its own detect register */
14608
14609 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14610 DRM_DEBUG_KMS("probing SDVOC\n");
14611 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14612 }
14613
14614 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14615
14616 if (IS_G4X(dev)) {
14617 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14618 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14619 }
14620 if (IS_G4X(dev))
14621 intel_dp_init(dev, DP_C, PORT_C);
14622 }
14623
14624 if (IS_G4X(dev) &&
14625 (I915_READ(DP_D) & DP_DETECTED))
14626 intel_dp_init(dev, DP_D, PORT_D);
14627 } else if (IS_GEN2(dev))
14628 intel_dvo_init(dev);
14629
14630 if (SUPPORTS_TV(dev))
14631 intel_tv_init(dev);
14632
14633 intel_psr_init(dev);
14634
14635 for_each_intel_encoder(dev, encoder) {
14636 encoder->base.possible_crtcs = encoder->crtc_mask;
14637 encoder->base.possible_clones =
14638 intel_encoder_clones(encoder);
14639 }
14640
14641 intel_init_pch_refclk(dev);
14642
14643 drm_helper_move_panel_connectors_to_head(dev);
14644 }
14645
14646 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14647 {
14648 struct drm_device *dev = fb->dev;
14649 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14650
14651 drm_framebuffer_cleanup(fb);
14652 mutex_lock(&dev->struct_mutex);
14653 WARN_ON(!intel_fb->obj->framebuffer_references--);
14654 drm_gem_object_unreference(&intel_fb->obj->base);
14655 mutex_unlock(&dev->struct_mutex);
14656 kfree(intel_fb);
14657 }
14658
14659 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14660 struct drm_file *file,
14661 unsigned int *handle)
14662 {
14663 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14664 struct drm_i915_gem_object *obj = intel_fb->obj;
14665
14666 if (obj->userptr.mm) {
14667 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14668 return -EINVAL;
14669 }
14670
14671 return drm_gem_handle_create(file, &obj->base, handle);
14672 }
14673
14674 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14675 struct drm_file *file,
14676 unsigned flags, unsigned color,
14677 struct drm_clip_rect *clips,
14678 unsigned num_clips)
14679 {
14680 struct drm_device *dev = fb->dev;
14681 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14682 struct drm_i915_gem_object *obj = intel_fb->obj;
14683
14684 mutex_lock(&dev->struct_mutex);
14685 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14686 mutex_unlock(&dev->struct_mutex);
14687
14688 return 0;
14689 }
14690
14691 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14692 .destroy = intel_user_framebuffer_destroy,
14693 .create_handle = intel_user_framebuffer_create_handle,
14694 .dirty = intel_user_framebuffer_dirty,
14695 };
14696
14697 static
14698 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14699 uint32_t pixel_format)
14700 {
14701 u32 gen = INTEL_INFO(dev)->gen;
14702
14703 if (gen >= 9) {
14704 int cpp = drm_format_plane_cpp(pixel_format, 0);
14705
14706 /* "The stride in bytes must not exceed the of the size of 8K
14707 * pixels and 32K bytes."
14708 */
14709 return min(8192 * cpp, 32768);
14710 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14711 return 32*1024;
14712 } else if (gen >= 4) {
14713 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14714 return 16*1024;
14715 else
14716 return 32*1024;
14717 } else if (gen >= 3) {
14718 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14719 return 8*1024;
14720 else
14721 return 16*1024;
14722 } else {
14723 /* XXX DSPC is limited to 4k tiled */
14724 return 8*1024;
14725 }
14726 }
14727
14728 static int intel_framebuffer_init(struct drm_device *dev,
14729 struct intel_framebuffer *intel_fb,
14730 struct drm_mode_fb_cmd2 *mode_cmd,
14731 struct drm_i915_gem_object *obj)
14732 {
14733 struct drm_i915_private *dev_priv = to_i915(dev);
14734 unsigned int aligned_height;
14735 int ret;
14736 u32 pitch_limit, stride_alignment;
14737
14738 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14739
14740 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14741 /* Enforce that fb modifier and tiling mode match, but only for
14742 * X-tiled. This is needed for FBC. */
14743 if (!!(obj->tiling_mode == I915_TILING_X) !=
14744 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14745 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14746 return -EINVAL;
14747 }
14748 } else {
14749 if (obj->tiling_mode == I915_TILING_X)
14750 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14751 else if (obj->tiling_mode == I915_TILING_Y) {
14752 DRM_DEBUG("No Y tiling for legacy addfb\n");
14753 return -EINVAL;
14754 }
14755 }
14756
14757 /* Passed in modifier sanity checking. */
14758 switch (mode_cmd->modifier[0]) {
14759 case I915_FORMAT_MOD_Y_TILED:
14760 case I915_FORMAT_MOD_Yf_TILED:
14761 if (INTEL_INFO(dev)->gen < 9) {
14762 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14763 mode_cmd->modifier[0]);
14764 return -EINVAL;
14765 }
14766 case DRM_FORMAT_MOD_NONE:
14767 case I915_FORMAT_MOD_X_TILED:
14768 break;
14769 default:
14770 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14771 mode_cmd->modifier[0]);
14772 return -EINVAL;
14773 }
14774
14775 stride_alignment = intel_fb_stride_alignment(dev_priv,
14776 mode_cmd->modifier[0],
14777 mode_cmd->pixel_format);
14778 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14779 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14780 mode_cmd->pitches[0], stride_alignment);
14781 return -EINVAL;
14782 }
14783
14784 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14785 mode_cmd->pixel_format);
14786 if (mode_cmd->pitches[0] > pitch_limit) {
14787 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14788 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14789 "tiled" : "linear",
14790 mode_cmd->pitches[0], pitch_limit);
14791 return -EINVAL;
14792 }
14793
14794 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14795 mode_cmd->pitches[0] != obj->stride) {
14796 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14797 mode_cmd->pitches[0], obj->stride);
14798 return -EINVAL;
14799 }
14800
14801 /* Reject formats not supported by any plane early. */
14802 switch (mode_cmd->pixel_format) {
14803 case DRM_FORMAT_C8:
14804 case DRM_FORMAT_RGB565:
14805 case DRM_FORMAT_XRGB8888:
14806 case DRM_FORMAT_ARGB8888:
14807 break;
14808 case DRM_FORMAT_XRGB1555:
14809 if (INTEL_INFO(dev)->gen > 3) {
14810 DRM_DEBUG("unsupported pixel format: %s\n",
14811 drm_get_format_name(mode_cmd->pixel_format));
14812 return -EINVAL;
14813 }
14814 break;
14815 case DRM_FORMAT_ABGR8888:
14816 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14817 INTEL_INFO(dev)->gen < 9) {
14818 DRM_DEBUG("unsupported pixel format: %s\n",
14819 drm_get_format_name(mode_cmd->pixel_format));
14820 return -EINVAL;
14821 }
14822 break;
14823 case DRM_FORMAT_XBGR8888:
14824 case DRM_FORMAT_XRGB2101010:
14825 case DRM_FORMAT_XBGR2101010:
14826 if (INTEL_INFO(dev)->gen < 4) {
14827 DRM_DEBUG("unsupported pixel format: %s\n",
14828 drm_get_format_name(mode_cmd->pixel_format));
14829 return -EINVAL;
14830 }
14831 break;
14832 case DRM_FORMAT_ABGR2101010:
14833 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14834 DRM_DEBUG("unsupported pixel format: %s\n",
14835 drm_get_format_name(mode_cmd->pixel_format));
14836 return -EINVAL;
14837 }
14838 break;
14839 case DRM_FORMAT_YUYV:
14840 case DRM_FORMAT_UYVY:
14841 case DRM_FORMAT_YVYU:
14842 case DRM_FORMAT_VYUY:
14843 if (INTEL_INFO(dev)->gen < 5) {
14844 DRM_DEBUG("unsupported pixel format: %s\n",
14845 drm_get_format_name(mode_cmd->pixel_format));
14846 return -EINVAL;
14847 }
14848 break;
14849 default:
14850 DRM_DEBUG("unsupported pixel format: %s\n",
14851 drm_get_format_name(mode_cmd->pixel_format));
14852 return -EINVAL;
14853 }
14854
14855 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14856 if (mode_cmd->offsets[0] != 0)
14857 return -EINVAL;
14858
14859 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14860 mode_cmd->pixel_format,
14861 mode_cmd->modifier[0]);
14862 /* FIXME drm helper for size checks (especially planar formats)? */
14863 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14864 return -EINVAL;
14865
14866 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14867 intel_fb->obj = obj;
14868
14869 intel_fill_fb_info(dev_priv, &intel_fb->base);
14870
14871 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14872 if (ret) {
14873 DRM_ERROR("framebuffer init failed %d\n", ret);
14874 return ret;
14875 }
14876
14877 intel_fb->obj->framebuffer_references++;
14878
14879 return 0;
14880 }
14881
14882 static struct drm_framebuffer *
14883 intel_user_framebuffer_create(struct drm_device *dev,
14884 struct drm_file *filp,
14885 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14886 {
14887 struct drm_framebuffer *fb;
14888 struct drm_i915_gem_object *obj;
14889 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14890
14891 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14892 mode_cmd.handles[0]));
14893 if (&obj->base == NULL)
14894 return ERR_PTR(-ENOENT);
14895
14896 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14897 if (IS_ERR(fb))
14898 drm_gem_object_unreference_unlocked(&obj->base);
14899
14900 return fb;
14901 }
14902
14903 #ifndef CONFIG_DRM_FBDEV_EMULATION
14904 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14905 {
14906 }
14907 #endif
14908
14909 static const struct drm_mode_config_funcs intel_mode_funcs = {
14910 .fb_create = intel_user_framebuffer_create,
14911 .output_poll_changed = intel_fbdev_output_poll_changed,
14912 .atomic_check = intel_atomic_check,
14913 .atomic_commit = intel_atomic_commit,
14914 .atomic_state_alloc = intel_atomic_state_alloc,
14915 .atomic_state_clear = intel_atomic_state_clear,
14916 };
14917
14918 /**
14919 * intel_init_display_hooks - initialize the display modesetting hooks
14920 * @dev_priv: device private
14921 */
14922 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14923 {
14924 if (INTEL_INFO(dev_priv)->gen >= 9) {
14925 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14926 dev_priv->display.get_initial_plane_config =
14927 skylake_get_initial_plane_config;
14928 dev_priv->display.crtc_compute_clock =
14929 haswell_crtc_compute_clock;
14930 dev_priv->display.crtc_enable = haswell_crtc_enable;
14931 dev_priv->display.crtc_disable = haswell_crtc_disable;
14932 } else if (HAS_DDI(dev_priv)) {
14933 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14934 dev_priv->display.get_initial_plane_config =
14935 ironlake_get_initial_plane_config;
14936 dev_priv->display.crtc_compute_clock =
14937 haswell_crtc_compute_clock;
14938 dev_priv->display.crtc_enable = haswell_crtc_enable;
14939 dev_priv->display.crtc_disable = haswell_crtc_disable;
14940 } else if (HAS_PCH_SPLIT(dev_priv)) {
14941 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14942 dev_priv->display.get_initial_plane_config =
14943 ironlake_get_initial_plane_config;
14944 dev_priv->display.crtc_compute_clock =
14945 ironlake_crtc_compute_clock;
14946 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14947 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14948 } else if (IS_CHERRYVIEW(dev_priv)) {
14949 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14950 dev_priv->display.get_initial_plane_config =
14951 i9xx_get_initial_plane_config;
14952 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14953 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14954 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14955 } else if (IS_VALLEYVIEW(dev_priv)) {
14956 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14957 dev_priv->display.get_initial_plane_config =
14958 i9xx_get_initial_plane_config;
14959 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14960 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14961 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14962 } else if (IS_G4X(dev_priv)) {
14963 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14964 dev_priv->display.get_initial_plane_config =
14965 i9xx_get_initial_plane_config;
14966 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14967 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14968 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14969 } else if (IS_PINEVIEW(dev_priv)) {
14970 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14971 dev_priv->display.get_initial_plane_config =
14972 i9xx_get_initial_plane_config;
14973 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14974 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14975 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14976 } else if (!IS_GEN2(dev_priv)) {
14977 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14978 dev_priv->display.get_initial_plane_config =
14979 i9xx_get_initial_plane_config;
14980 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14981 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14982 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14983 } else {
14984 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14985 dev_priv->display.get_initial_plane_config =
14986 i9xx_get_initial_plane_config;
14987 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14988 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14989 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14990 }
14991
14992 /* Returns the core display clock speed */
14993 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14994 dev_priv->display.get_display_clock_speed =
14995 skylake_get_display_clock_speed;
14996 else if (IS_BROXTON(dev_priv))
14997 dev_priv->display.get_display_clock_speed =
14998 broxton_get_display_clock_speed;
14999 else if (IS_BROADWELL(dev_priv))
15000 dev_priv->display.get_display_clock_speed =
15001 broadwell_get_display_clock_speed;
15002 else if (IS_HASWELL(dev_priv))
15003 dev_priv->display.get_display_clock_speed =
15004 haswell_get_display_clock_speed;
15005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15006 dev_priv->display.get_display_clock_speed =
15007 valleyview_get_display_clock_speed;
15008 else if (IS_GEN5(dev_priv))
15009 dev_priv->display.get_display_clock_speed =
15010 ilk_get_display_clock_speed;
15011 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15012 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15013 dev_priv->display.get_display_clock_speed =
15014 i945_get_display_clock_speed;
15015 else if (IS_GM45(dev_priv))
15016 dev_priv->display.get_display_clock_speed =
15017 gm45_get_display_clock_speed;
15018 else if (IS_CRESTLINE(dev_priv))
15019 dev_priv->display.get_display_clock_speed =
15020 i965gm_get_display_clock_speed;
15021 else if (IS_PINEVIEW(dev_priv))
15022 dev_priv->display.get_display_clock_speed =
15023 pnv_get_display_clock_speed;
15024 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15025 dev_priv->display.get_display_clock_speed =
15026 g33_get_display_clock_speed;
15027 else if (IS_I915G(dev_priv))
15028 dev_priv->display.get_display_clock_speed =
15029 i915_get_display_clock_speed;
15030 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15031 dev_priv->display.get_display_clock_speed =
15032 i9xx_misc_get_display_clock_speed;
15033 else if (IS_I915GM(dev_priv))
15034 dev_priv->display.get_display_clock_speed =
15035 i915gm_get_display_clock_speed;
15036 else if (IS_I865G(dev_priv))
15037 dev_priv->display.get_display_clock_speed =
15038 i865_get_display_clock_speed;
15039 else if (IS_I85X(dev_priv))
15040 dev_priv->display.get_display_clock_speed =
15041 i85x_get_display_clock_speed;
15042 else { /* 830 */
15043 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15044 dev_priv->display.get_display_clock_speed =
15045 i830_get_display_clock_speed;
15046 }
15047
15048 if (IS_GEN5(dev_priv)) {
15049 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15050 } else if (IS_GEN6(dev_priv)) {
15051 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15052 } else if (IS_IVYBRIDGE(dev_priv)) {
15053 /* FIXME: detect B0+ stepping and use auto training */
15054 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15055 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15056 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15057 if (IS_BROADWELL(dev_priv)) {
15058 dev_priv->display.modeset_commit_cdclk =
15059 broadwell_modeset_commit_cdclk;
15060 dev_priv->display.modeset_calc_cdclk =
15061 broadwell_modeset_calc_cdclk;
15062 }
15063 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15064 dev_priv->display.modeset_commit_cdclk =
15065 valleyview_modeset_commit_cdclk;
15066 dev_priv->display.modeset_calc_cdclk =
15067 valleyview_modeset_calc_cdclk;
15068 } else if (IS_BROXTON(dev_priv)) {
15069 dev_priv->display.modeset_commit_cdclk =
15070 broxton_modeset_commit_cdclk;
15071 dev_priv->display.modeset_calc_cdclk =
15072 broxton_modeset_calc_cdclk;
15073 }
15074
15075 switch (INTEL_INFO(dev_priv)->gen) {
15076 case 2:
15077 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15078 break;
15079
15080 case 3:
15081 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15082 break;
15083
15084 case 4:
15085 case 5:
15086 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15087 break;
15088
15089 case 6:
15090 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15091 break;
15092 case 7:
15093 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15094 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15095 break;
15096 case 9:
15097 /* Drop through - unsupported since execlist only. */
15098 default:
15099 /* Default just returns -ENODEV to indicate unsupported */
15100 dev_priv->display.queue_flip = intel_default_queue_flip;
15101 }
15102 }
15103
15104 /*
15105 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15106 * resume, or other times. This quirk makes sure that's the case for
15107 * affected systems.
15108 */
15109 static void quirk_pipea_force(struct drm_device *dev)
15110 {
15111 struct drm_i915_private *dev_priv = dev->dev_private;
15112
15113 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15114 DRM_INFO("applying pipe a force quirk\n");
15115 }
15116
15117 static void quirk_pipeb_force(struct drm_device *dev)
15118 {
15119 struct drm_i915_private *dev_priv = dev->dev_private;
15120
15121 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15122 DRM_INFO("applying pipe b force quirk\n");
15123 }
15124
15125 /*
15126 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15127 */
15128 static void quirk_ssc_force_disable(struct drm_device *dev)
15129 {
15130 struct drm_i915_private *dev_priv = dev->dev_private;
15131 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15132 DRM_INFO("applying lvds SSC disable quirk\n");
15133 }
15134
15135 /*
15136 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15137 * brightness value
15138 */
15139 static void quirk_invert_brightness(struct drm_device *dev)
15140 {
15141 struct drm_i915_private *dev_priv = dev->dev_private;
15142 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15143 DRM_INFO("applying inverted panel brightness quirk\n");
15144 }
15145
15146 /* Some VBT's incorrectly indicate no backlight is present */
15147 static void quirk_backlight_present(struct drm_device *dev)
15148 {
15149 struct drm_i915_private *dev_priv = dev->dev_private;
15150 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15151 DRM_INFO("applying backlight present quirk\n");
15152 }
15153
15154 struct intel_quirk {
15155 int device;
15156 int subsystem_vendor;
15157 int subsystem_device;
15158 void (*hook)(struct drm_device *dev);
15159 };
15160
15161 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15162 struct intel_dmi_quirk {
15163 void (*hook)(struct drm_device *dev);
15164 const struct dmi_system_id (*dmi_id_list)[];
15165 };
15166
15167 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15168 {
15169 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15170 return 1;
15171 }
15172
15173 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15174 {
15175 .dmi_id_list = &(const struct dmi_system_id[]) {
15176 {
15177 .callback = intel_dmi_reverse_brightness,
15178 .ident = "NCR Corporation",
15179 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15180 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15181 },
15182 },
15183 { } /* terminating entry */
15184 },
15185 .hook = quirk_invert_brightness,
15186 },
15187 };
15188
15189 static struct intel_quirk intel_quirks[] = {
15190 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15191 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15192
15193 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15194 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15195
15196 /* 830 needs to leave pipe A & dpll A up */
15197 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15198
15199 /* 830 needs to leave pipe B & dpll B up */
15200 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15201
15202 /* Lenovo U160 cannot use SSC on LVDS */
15203 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15204
15205 /* Sony Vaio Y cannot use SSC on LVDS */
15206 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15207
15208 /* Acer Aspire 5734Z must invert backlight brightness */
15209 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15210
15211 /* Acer/eMachines G725 */
15212 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15213
15214 /* Acer/eMachines e725 */
15215 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15216
15217 /* Acer/Packard Bell NCL20 */
15218 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15219
15220 /* Acer Aspire 4736Z */
15221 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15222
15223 /* Acer Aspire 5336 */
15224 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15225
15226 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15227 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15228
15229 /* Acer C720 Chromebook (Core i3 4005U) */
15230 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15231
15232 /* Apple Macbook 2,1 (Core 2 T7400) */
15233 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15234
15235 /* Apple Macbook 4,1 */
15236 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15237
15238 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15239 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15240
15241 /* HP Chromebook 14 (Celeron 2955U) */
15242 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15243
15244 /* Dell Chromebook 11 */
15245 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15246
15247 /* Dell Chromebook 11 (2015 version) */
15248 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15249 };
15250
15251 static void intel_init_quirks(struct drm_device *dev)
15252 {
15253 struct pci_dev *d = dev->pdev;
15254 int i;
15255
15256 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15257 struct intel_quirk *q = &intel_quirks[i];
15258
15259 if (d->device == q->device &&
15260 (d->subsystem_vendor == q->subsystem_vendor ||
15261 q->subsystem_vendor == PCI_ANY_ID) &&
15262 (d->subsystem_device == q->subsystem_device ||
15263 q->subsystem_device == PCI_ANY_ID))
15264 q->hook(dev);
15265 }
15266 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15267 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15268 intel_dmi_quirks[i].hook(dev);
15269 }
15270 }
15271
15272 /* Disable the VGA plane that we never use */
15273 static void i915_disable_vga(struct drm_device *dev)
15274 {
15275 struct drm_i915_private *dev_priv = dev->dev_private;
15276 u8 sr1;
15277 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15278
15279 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15280 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15281 outb(SR01, VGA_SR_INDEX);
15282 sr1 = inb(VGA_SR_DATA);
15283 outb(sr1 | 1<<5, VGA_SR_DATA);
15284 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15285 udelay(300);
15286
15287 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15288 POSTING_READ(vga_reg);
15289 }
15290
15291 void intel_modeset_init_hw(struct drm_device *dev)
15292 {
15293 struct drm_i915_private *dev_priv = dev->dev_private;
15294
15295 intel_update_cdclk(dev);
15296
15297 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15298
15299 intel_init_clock_gating(dev);
15300 intel_enable_gt_powersave(dev_priv);
15301 }
15302
15303 /*
15304 * Calculate what we think the watermarks should be for the state we've read
15305 * out of the hardware and then immediately program those watermarks so that
15306 * we ensure the hardware settings match our internal state.
15307 *
15308 * We can calculate what we think WM's should be by creating a duplicate of the
15309 * current state (which was constructed during hardware readout) and running it
15310 * through the atomic check code to calculate new watermark values in the
15311 * state object.
15312 */
15313 static void sanitize_watermarks(struct drm_device *dev)
15314 {
15315 struct drm_i915_private *dev_priv = to_i915(dev);
15316 struct drm_atomic_state *state;
15317 struct drm_crtc *crtc;
15318 struct drm_crtc_state *cstate;
15319 struct drm_modeset_acquire_ctx ctx;
15320 int ret;
15321 int i;
15322
15323 /* Only supported on platforms that use atomic watermark design */
15324 if (!dev_priv->display.optimize_watermarks)
15325 return;
15326
15327 /*
15328 * We need to hold connection_mutex before calling duplicate_state so
15329 * that the connector loop is protected.
15330 */
15331 drm_modeset_acquire_init(&ctx, 0);
15332 retry:
15333 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15334 if (ret == -EDEADLK) {
15335 drm_modeset_backoff(&ctx);
15336 goto retry;
15337 } else if (WARN_ON(ret)) {
15338 goto fail;
15339 }
15340
15341 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15342 if (WARN_ON(IS_ERR(state)))
15343 goto fail;
15344
15345 /*
15346 * Hardware readout is the only time we don't want to calculate
15347 * intermediate watermarks (since we don't trust the current
15348 * watermarks).
15349 */
15350 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15351
15352 ret = intel_atomic_check(dev, state);
15353 if (ret) {
15354 /*
15355 * If we fail here, it means that the hardware appears to be
15356 * programmed in a way that shouldn't be possible, given our
15357 * understanding of watermark requirements. This might mean a
15358 * mistake in the hardware readout code or a mistake in the
15359 * watermark calculations for a given platform. Raise a WARN
15360 * so that this is noticeable.
15361 *
15362 * If this actually happens, we'll have to just leave the
15363 * BIOS-programmed watermarks untouched and hope for the best.
15364 */
15365 WARN(true, "Could not determine valid watermarks for inherited state\n");
15366 goto fail;
15367 }
15368
15369 /* Write calculated watermark values back */
15370 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15371 for_each_crtc_in_state(state, crtc, cstate, i) {
15372 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15373
15374 cs->wm.need_postvbl_update = true;
15375 dev_priv->display.optimize_watermarks(cs);
15376 }
15377
15378 drm_atomic_state_free(state);
15379 fail:
15380 drm_modeset_drop_locks(&ctx);
15381 drm_modeset_acquire_fini(&ctx);
15382 }
15383
15384 void intel_modeset_init(struct drm_device *dev)
15385 {
15386 struct drm_i915_private *dev_priv = to_i915(dev);
15387 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15388 int sprite, ret;
15389 enum pipe pipe;
15390 struct intel_crtc *crtc;
15391
15392 drm_mode_config_init(dev);
15393
15394 dev->mode_config.min_width = 0;
15395 dev->mode_config.min_height = 0;
15396
15397 dev->mode_config.preferred_depth = 24;
15398 dev->mode_config.prefer_shadow = 1;
15399
15400 dev->mode_config.allow_fb_modifiers = true;
15401
15402 dev->mode_config.funcs = &intel_mode_funcs;
15403
15404 intel_init_quirks(dev);
15405
15406 intel_init_pm(dev);
15407
15408 if (INTEL_INFO(dev)->num_pipes == 0)
15409 return;
15410
15411 /*
15412 * There may be no VBT; and if the BIOS enabled SSC we can
15413 * just keep using it to avoid unnecessary flicker. Whereas if the
15414 * BIOS isn't using it, don't assume it will work even if the VBT
15415 * indicates as much.
15416 */
15417 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15418 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15419 DREF_SSC1_ENABLE);
15420
15421 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15422 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15423 bios_lvds_use_ssc ? "en" : "dis",
15424 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15425 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15426 }
15427 }
15428
15429 if (IS_GEN2(dev)) {
15430 dev->mode_config.max_width = 2048;
15431 dev->mode_config.max_height = 2048;
15432 } else if (IS_GEN3(dev)) {
15433 dev->mode_config.max_width = 4096;
15434 dev->mode_config.max_height = 4096;
15435 } else {
15436 dev->mode_config.max_width = 8192;
15437 dev->mode_config.max_height = 8192;
15438 }
15439
15440 if (IS_845G(dev) || IS_I865G(dev)) {
15441 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15442 dev->mode_config.cursor_height = 1023;
15443 } else if (IS_GEN2(dev)) {
15444 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15445 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15446 } else {
15447 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15448 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15449 }
15450
15451 dev->mode_config.fb_base = ggtt->mappable_base;
15452
15453 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15454 INTEL_INFO(dev)->num_pipes,
15455 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15456
15457 for_each_pipe(dev_priv, pipe) {
15458 intel_crtc_init(dev, pipe);
15459 for_each_sprite(dev_priv, pipe, sprite) {
15460 ret = intel_plane_init(dev, pipe, sprite);
15461 if (ret)
15462 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15463 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15464 }
15465 }
15466
15467 intel_update_czclk(dev_priv);
15468 intel_update_cdclk(dev);
15469
15470 intel_shared_dpll_init(dev);
15471
15472 /* Just disable it once at startup */
15473 i915_disable_vga(dev);
15474 intel_setup_outputs(dev);
15475
15476 drm_modeset_lock_all(dev);
15477 intel_modeset_setup_hw_state(dev);
15478 drm_modeset_unlock_all(dev);
15479
15480 for_each_intel_crtc(dev, crtc) {
15481 struct intel_initial_plane_config plane_config = {};
15482
15483 if (!crtc->active)
15484 continue;
15485
15486 /*
15487 * Note that reserving the BIOS fb up front prevents us
15488 * from stuffing other stolen allocations like the ring
15489 * on top. This prevents some ugliness at boot time, and
15490 * can even allow for smooth boot transitions if the BIOS
15491 * fb is large enough for the active pipe configuration.
15492 */
15493 dev_priv->display.get_initial_plane_config(crtc,
15494 &plane_config);
15495
15496 /*
15497 * If the fb is shared between multiple heads, we'll
15498 * just get the first one.
15499 */
15500 intel_find_initial_plane_obj(crtc, &plane_config);
15501 }
15502
15503 /*
15504 * Make sure hardware watermarks really match the state we read out.
15505 * Note that we need to do this after reconstructing the BIOS fb's
15506 * since the watermark calculation done here will use pstate->fb.
15507 */
15508 sanitize_watermarks(dev);
15509 }
15510
15511 static void intel_enable_pipe_a(struct drm_device *dev)
15512 {
15513 struct intel_connector *connector;
15514 struct drm_connector *crt = NULL;
15515 struct intel_load_detect_pipe load_detect_temp;
15516 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15517
15518 /* We can't just switch on the pipe A, we need to set things up with a
15519 * proper mode and output configuration. As a gross hack, enable pipe A
15520 * by enabling the load detect pipe once. */
15521 for_each_intel_connector(dev, connector) {
15522 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15523 crt = &connector->base;
15524 break;
15525 }
15526 }
15527
15528 if (!crt)
15529 return;
15530
15531 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15532 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15533 }
15534
15535 static bool
15536 intel_check_plane_mapping(struct intel_crtc *crtc)
15537 {
15538 struct drm_device *dev = crtc->base.dev;
15539 struct drm_i915_private *dev_priv = dev->dev_private;
15540 u32 val;
15541
15542 if (INTEL_INFO(dev)->num_pipes == 1)
15543 return true;
15544
15545 val = I915_READ(DSPCNTR(!crtc->plane));
15546
15547 if ((val & DISPLAY_PLANE_ENABLE) &&
15548 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15549 return false;
15550
15551 return true;
15552 }
15553
15554 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15555 {
15556 struct drm_device *dev = crtc->base.dev;
15557 struct intel_encoder *encoder;
15558
15559 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15560 return true;
15561
15562 return false;
15563 }
15564
15565 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15566 {
15567 struct drm_device *dev = encoder->base.dev;
15568 struct intel_connector *connector;
15569
15570 for_each_connector_on_encoder(dev, &encoder->base, connector)
15571 return true;
15572
15573 return false;
15574 }
15575
15576 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15577 {
15578 struct drm_device *dev = crtc->base.dev;
15579 struct drm_i915_private *dev_priv = dev->dev_private;
15580 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15581
15582 /* Clear any frame start delays used for debugging left by the BIOS */
15583 if (!transcoder_is_dsi(cpu_transcoder)) {
15584 i915_reg_t reg = PIPECONF(cpu_transcoder);
15585
15586 I915_WRITE(reg,
15587 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15588 }
15589
15590 /* restore vblank interrupts to correct state */
15591 drm_crtc_vblank_reset(&crtc->base);
15592 if (crtc->active) {
15593 struct intel_plane *plane;
15594
15595 drm_crtc_vblank_on(&crtc->base);
15596
15597 /* Disable everything but the primary plane */
15598 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15599 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15600 continue;
15601
15602 plane->disable_plane(&plane->base, &crtc->base);
15603 }
15604 }
15605
15606 /* We need to sanitize the plane -> pipe mapping first because this will
15607 * disable the crtc (and hence change the state) if it is wrong. Note
15608 * that gen4+ has a fixed plane -> pipe mapping. */
15609 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15610 bool plane;
15611
15612 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15613 crtc->base.base.id);
15614
15615 /* Pipe has the wrong plane attached and the plane is active.
15616 * Temporarily change the plane mapping and disable everything
15617 * ... */
15618 plane = crtc->plane;
15619 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15620 crtc->plane = !plane;
15621 intel_crtc_disable_noatomic(&crtc->base);
15622 crtc->plane = plane;
15623 }
15624
15625 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15626 crtc->pipe == PIPE_A && !crtc->active) {
15627 /* BIOS forgot to enable pipe A, this mostly happens after
15628 * resume. Force-enable the pipe to fix this, the update_dpms
15629 * call below we restore the pipe to the right state, but leave
15630 * the required bits on. */
15631 intel_enable_pipe_a(dev);
15632 }
15633
15634 /* Adjust the state of the output pipe according to whether we
15635 * have active connectors/encoders. */
15636 if (crtc->active && !intel_crtc_has_encoders(crtc))
15637 intel_crtc_disable_noatomic(&crtc->base);
15638
15639 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15640 /*
15641 * We start out with underrun reporting disabled to avoid races.
15642 * For correct bookkeeping mark this on active crtcs.
15643 *
15644 * Also on gmch platforms we dont have any hardware bits to
15645 * disable the underrun reporting. Which means we need to start
15646 * out with underrun reporting disabled also on inactive pipes,
15647 * since otherwise we'll complain about the garbage we read when
15648 * e.g. coming up after runtime pm.
15649 *
15650 * No protection against concurrent access is required - at
15651 * worst a fifo underrun happens which also sets this to false.
15652 */
15653 crtc->cpu_fifo_underrun_disabled = true;
15654 crtc->pch_fifo_underrun_disabled = true;
15655 }
15656 }
15657
15658 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15659 {
15660 struct intel_connector *connector;
15661 struct drm_device *dev = encoder->base.dev;
15662
15663 /* We need to check both for a crtc link (meaning that the
15664 * encoder is active and trying to read from a pipe) and the
15665 * pipe itself being active. */
15666 bool has_active_crtc = encoder->base.crtc &&
15667 to_intel_crtc(encoder->base.crtc)->active;
15668
15669 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15670 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15671 encoder->base.base.id,
15672 encoder->base.name);
15673
15674 /* Connector is active, but has no active pipe. This is
15675 * fallout from our resume register restoring. Disable
15676 * the encoder manually again. */
15677 if (encoder->base.crtc) {
15678 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15679 encoder->base.base.id,
15680 encoder->base.name);
15681 encoder->disable(encoder);
15682 if (encoder->post_disable)
15683 encoder->post_disable(encoder);
15684 }
15685 encoder->base.crtc = NULL;
15686
15687 /* Inconsistent output/port/pipe state happens presumably due to
15688 * a bug in one of the get_hw_state functions. Or someplace else
15689 * in our code, like the register restore mess on resume. Clamp
15690 * things to off as a safer default. */
15691 for_each_intel_connector(dev, connector) {
15692 if (connector->encoder != encoder)
15693 continue;
15694 connector->base.dpms = DRM_MODE_DPMS_OFF;
15695 connector->base.encoder = NULL;
15696 }
15697 }
15698 /* Enabled encoders without active connectors will be fixed in
15699 * the crtc fixup. */
15700 }
15701
15702 void i915_redisable_vga_power_on(struct drm_device *dev)
15703 {
15704 struct drm_i915_private *dev_priv = dev->dev_private;
15705 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15706
15707 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15708 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15709 i915_disable_vga(dev);
15710 }
15711 }
15712
15713 void i915_redisable_vga(struct drm_device *dev)
15714 {
15715 struct drm_i915_private *dev_priv = dev->dev_private;
15716
15717 /* This function can be called both from intel_modeset_setup_hw_state or
15718 * at a very early point in our resume sequence, where the power well
15719 * structures are not yet restored. Since this function is at a very
15720 * paranoid "someone might have enabled VGA while we were not looking"
15721 * level, just check if the power well is enabled instead of trying to
15722 * follow the "don't touch the power well if we don't need it" policy
15723 * the rest of the driver uses. */
15724 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15725 return;
15726
15727 i915_redisable_vga_power_on(dev);
15728
15729 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15730 }
15731
15732 static bool primary_get_hw_state(struct intel_plane *plane)
15733 {
15734 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15735
15736 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15737 }
15738
15739 /* FIXME read out full plane state for all planes */
15740 static void readout_plane_state(struct intel_crtc *crtc)
15741 {
15742 struct drm_plane *primary = crtc->base.primary;
15743 struct intel_plane_state *plane_state =
15744 to_intel_plane_state(primary->state);
15745
15746 plane_state->visible = crtc->active &&
15747 primary_get_hw_state(to_intel_plane(primary));
15748
15749 if (plane_state->visible)
15750 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15751 }
15752
15753 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15754 {
15755 struct drm_i915_private *dev_priv = dev->dev_private;
15756 enum pipe pipe;
15757 struct intel_crtc *crtc;
15758 struct intel_encoder *encoder;
15759 struct intel_connector *connector;
15760 int i;
15761
15762 dev_priv->active_crtcs = 0;
15763
15764 for_each_intel_crtc(dev, crtc) {
15765 struct intel_crtc_state *crtc_state = crtc->config;
15766 int pixclk = 0;
15767
15768 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15769 memset(crtc_state, 0, sizeof(*crtc_state));
15770 crtc_state->base.crtc = &crtc->base;
15771
15772 crtc_state->base.active = crtc_state->base.enable =
15773 dev_priv->display.get_pipe_config(crtc, crtc_state);
15774
15775 crtc->base.enabled = crtc_state->base.enable;
15776 crtc->active = crtc_state->base.active;
15777
15778 if (crtc_state->base.active) {
15779 dev_priv->active_crtcs |= 1 << crtc->pipe;
15780
15781 if (IS_BROADWELL(dev_priv)) {
15782 pixclk = ilk_pipe_pixel_rate(crtc_state);
15783
15784 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15785 if (crtc_state->ips_enabled)
15786 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15787 } else if (IS_VALLEYVIEW(dev_priv) ||
15788 IS_CHERRYVIEW(dev_priv) ||
15789 IS_BROXTON(dev_priv))
15790 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15791 else
15792 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15793 }
15794
15795 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15796
15797 readout_plane_state(crtc);
15798
15799 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15800 crtc->base.base.id,
15801 crtc->active ? "enabled" : "disabled");
15802 }
15803
15804 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15805 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15806
15807 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15808 &pll->config.hw_state);
15809 pll->config.crtc_mask = 0;
15810 for_each_intel_crtc(dev, crtc) {
15811 if (crtc->active && crtc->config->shared_dpll == pll)
15812 pll->config.crtc_mask |= 1 << crtc->pipe;
15813 }
15814 pll->active_mask = pll->config.crtc_mask;
15815
15816 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15817 pll->name, pll->config.crtc_mask, pll->on);
15818 }
15819
15820 for_each_intel_encoder(dev, encoder) {
15821 pipe = 0;
15822
15823 if (encoder->get_hw_state(encoder, &pipe)) {
15824 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15825 encoder->base.crtc = &crtc->base;
15826 encoder->get_config(encoder, crtc->config);
15827 } else {
15828 encoder->base.crtc = NULL;
15829 }
15830
15831 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15832 encoder->base.base.id,
15833 encoder->base.name,
15834 encoder->base.crtc ? "enabled" : "disabled",
15835 pipe_name(pipe));
15836 }
15837
15838 for_each_intel_connector(dev, connector) {
15839 if (connector->get_hw_state(connector)) {
15840 connector->base.dpms = DRM_MODE_DPMS_ON;
15841
15842 encoder = connector->encoder;
15843 connector->base.encoder = &encoder->base;
15844
15845 if (encoder->base.crtc &&
15846 encoder->base.crtc->state->active) {
15847 /*
15848 * This has to be done during hardware readout
15849 * because anything calling .crtc_disable may
15850 * rely on the connector_mask being accurate.
15851 */
15852 encoder->base.crtc->state->connector_mask |=
15853 1 << drm_connector_index(&connector->base);
15854 encoder->base.crtc->state->encoder_mask |=
15855 1 << drm_encoder_index(&encoder->base);
15856 }
15857
15858 } else {
15859 connector->base.dpms = DRM_MODE_DPMS_OFF;
15860 connector->base.encoder = NULL;
15861 }
15862 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15863 connector->base.base.id,
15864 connector->base.name,
15865 connector->base.encoder ? "enabled" : "disabled");
15866 }
15867
15868 for_each_intel_crtc(dev, crtc) {
15869 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15870
15871 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15872 if (crtc->base.state->active) {
15873 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15874 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15875 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15876
15877 /*
15878 * The initial mode needs to be set in order to keep
15879 * the atomic core happy. It wants a valid mode if the
15880 * crtc's enabled, so we do the above call.
15881 *
15882 * At this point some state updated by the connectors
15883 * in their ->detect() callback has not run yet, so
15884 * no recalculation can be done yet.
15885 *
15886 * Even if we could do a recalculation and modeset
15887 * right now it would cause a double modeset if
15888 * fbdev or userspace chooses a different initial mode.
15889 *
15890 * If that happens, someone indicated they wanted a
15891 * mode change, which means it's safe to do a full
15892 * recalculation.
15893 */
15894 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15895
15896 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15897 update_scanline_offset(crtc);
15898 }
15899
15900 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15901 }
15902 }
15903
15904 /* Scan out the current hw modeset state,
15905 * and sanitizes it to the current state
15906 */
15907 static void
15908 intel_modeset_setup_hw_state(struct drm_device *dev)
15909 {
15910 struct drm_i915_private *dev_priv = dev->dev_private;
15911 enum pipe pipe;
15912 struct intel_crtc *crtc;
15913 struct intel_encoder *encoder;
15914 int i;
15915
15916 intel_modeset_readout_hw_state(dev);
15917
15918 /* HW state is read out, now we need to sanitize this mess. */
15919 for_each_intel_encoder(dev, encoder) {
15920 intel_sanitize_encoder(encoder);
15921 }
15922
15923 for_each_pipe(dev_priv, pipe) {
15924 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15925 intel_sanitize_crtc(crtc);
15926 intel_dump_pipe_config(crtc, crtc->config,
15927 "[setup_hw_state]");
15928 }
15929
15930 intel_modeset_update_connector_atomic_state(dev);
15931
15932 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15933 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15934
15935 if (!pll->on || pll->active_mask)
15936 continue;
15937
15938 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15939
15940 pll->funcs.disable(dev_priv, pll);
15941 pll->on = false;
15942 }
15943
15944 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15945 vlv_wm_get_hw_state(dev);
15946 else if (IS_GEN9(dev))
15947 skl_wm_get_hw_state(dev);
15948 else if (HAS_PCH_SPLIT(dev))
15949 ilk_wm_get_hw_state(dev);
15950
15951 for_each_intel_crtc(dev, crtc) {
15952 unsigned long put_domains;
15953
15954 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15955 if (WARN_ON(put_domains))
15956 modeset_put_power_domains(dev_priv, put_domains);
15957 }
15958 intel_display_set_init_power(dev_priv, false);
15959
15960 intel_fbc_init_pipe_state(dev_priv);
15961 }
15962
15963 void intel_display_resume(struct drm_device *dev)
15964 {
15965 struct drm_i915_private *dev_priv = to_i915(dev);
15966 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15967 struct drm_modeset_acquire_ctx ctx;
15968 int ret;
15969 bool setup = false;
15970
15971 dev_priv->modeset_restore_state = NULL;
15972
15973 /*
15974 * This is a cludge because with real atomic modeset mode_config.mutex
15975 * won't be taken. Unfortunately some probed state like
15976 * audio_codec_enable is still protected by mode_config.mutex, so lock
15977 * it here for now.
15978 */
15979 mutex_lock(&dev->mode_config.mutex);
15980 drm_modeset_acquire_init(&ctx, 0);
15981
15982 retry:
15983 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15984
15985 if (ret == 0 && !setup) {
15986 setup = true;
15987
15988 intel_modeset_setup_hw_state(dev);
15989 i915_redisable_vga(dev);
15990 }
15991
15992 if (ret == 0 && state) {
15993 struct drm_crtc_state *crtc_state;
15994 struct drm_crtc *crtc;
15995 int i;
15996
15997 state->acquire_ctx = &ctx;
15998
15999 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16000 /*
16001 * Force recalculation even if we restore
16002 * current state. With fast modeset this may not result
16003 * in a modeset when the state is compatible.
16004 */
16005 crtc_state->mode_changed = true;
16006 }
16007
16008 ret = drm_atomic_commit(state);
16009 }
16010
16011 if (ret == -EDEADLK) {
16012 drm_modeset_backoff(&ctx);
16013 goto retry;
16014 }
16015
16016 drm_modeset_drop_locks(&ctx);
16017 drm_modeset_acquire_fini(&ctx);
16018 mutex_unlock(&dev->mode_config.mutex);
16019
16020 if (ret) {
16021 DRM_ERROR("Restoring old state failed with %i\n", ret);
16022 drm_atomic_state_free(state);
16023 }
16024 }
16025
16026 void intel_modeset_gem_init(struct drm_device *dev)
16027 {
16028 struct drm_i915_private *dev_priv = to_i915(dev);
16029 struct drm_crtc *c;
16030 struct drm_i915_gem_object *obj;
16031 int ret;
16032
16033 intel_init_gt_powersave(dev_priv);
16034
16035 intel_modeset_init_hw(dev);
16036
16037 intel_setup_overlay(dev_priv);
16038
16039 /*
16040 * Make sure any fbs we allocated at startup are properly
16041 * pinned & fenced. When we do the allocation it's too early
16042 * for this.
16043 */
16044 for_each_crtc(dev, c) {
16045 obj = intel_fb_obj(c->primary->fb);
16046 if (obj == NULL)
16047 continue;
16048
16049 mutex_lock(&dev->struct_mutex);
16050 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16051 c->primary->state->rotation);
16052 mutex_unlock(&dev->struct_mutex);
16053 if (ret) {
16054 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16055 to_intel_crtc(c)->pipe);
16056 drm_framebuffer_unreference(c->primary->fb);
16057 c->primary->fb = NULL;
16058 c->primary->crtc = c->primary->state->crtc = NULL;
16059 update_state_fb(c->primary);
16060 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16061 }
16062 }
16063
16064 intel_backlight_register(dev);
16065 }
16066
16067 void intel_connector_unregister(struct intel_connector *intel_connector)
16068 {
16069 struct drm_connector *connector = &intel_connector->base;
16070
16071 intel_panel_destroy_backlight(connector);
16072 drm_connector_unregister(connector);
16073 }
16074
16075 void intel_modeset_cleanup(struct drm_device *dev)
16076 {
16077 struct drm_i915_private *dev_priv = dev->dev_private;
16078 struct intel_connector *connector;
16079
16080 intel_disable_gt_powersave(dev_priv);
16081
16082 intel_backlight_unregister(dev);
16083
16084 /*
16085 * Interrupts and polling as the first thing to avoid creating havoc.
16086 * Too much stuff here (turning of connectors, ...) would
16087 * experience fancy races otherwise.
16088 */
16089 intel_irq_uninstall(dev_priv);
16090
16091 /*
16092 * Due to the hpd irq storm handling the hotplug work can re-arm the
16093 * poll handlers. Hence disable polling after hpd handling is shut down.
16094 */
16095 drm_kms_helper_poll_fini(dev);
16096
16097 intel_unregister_dsm_handler();
16098
16099 intel_fbc_global_disable(dev_priv);
16100
16101 /* flush any delayed tasks or pending work */
16102 flush_scheduled_work();
16103
16104 /* destroy the backlight and sysfs files before encoders/connectors */
16105 for_each_intel_connector(dev, connector)
16106 connector->unregister(connector);
16107
16108 drm_mode_config_cleanup(dev);
16109
16110 intel_cleanup_overlay(dev_priv);
16111
16112 intel_cleanup_gt_powersave(dev_priv);
16113
16114 intel_teardown_gmbus(dev);
16115 }
16116
16117 /*
16118 * Return which encoder is currently attached for connector.
16119 */
16120 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16121 {
16122 return &intel_attached_encoder(connector)->base;
16123 }
16124
16125 void intel_connector_attach_encoder(struct intel_connector *connector,
16126 struct intel_encoder *encoder)
16127 {
16128 connector->encoder = encoder;
16129 drm_mode_connector_attach_encoder(&connector->base,
16130 &encoder->base);
16131 }
16132
16133 /*
16134 * set vga decode state - true == enable VGA decode
16135 */
16136 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16137 {
16138 struct drm_i915_private *dev_priv = dev->dev_private;
16139 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16140 u16 gmch_ctrl;
16141
16142 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16143 DRM_ERROR("failed to read control word\n");
16144 return -EIO;
16145 }
16146
16147 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16148 return 0;
16149
16150 if (state)
16151 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16152 else
16153 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16154
16155 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16156 DRM_ERROR("failed to write control word\n");
16157 return -EIO;
16158 }
16159
16160 return 0;
16161 }
16162
16163 struct intel_display_error_state {
16164
16165 u32 power_well_driver;
16166
16167 int num_transcoders;
16168
16169 struct intel_cursor_error_state {
16170 u32 control;
16171 u32 position;
16172 u32 base;
16173 u32 size;
16174 } cursor[I915_MAX_PIPES];
16175
16176 struct intel_pipe_error_state {
16177 bool power_domain_on;
16178 u32 source;
16179 u32 stat;
16180 } pipe[I915_MAX_PIPES];
16181
16182 struct intel_plane_error_state {
16183 u32 control;
16184 u32 stride;
16185 u32 size;
16186 u32 pos;
16187 u32 addr;
16188 u32 surface;
16189 u32 tile_offset;
16190 } plane[I915_MAX_PIPES];
16191
16192 struct intel_transcoder_error_state {
16193 bool power_domain_on;
16194 enum transcoder cpu_transcoder;
16195
16196 u32 conf;
16197
16198 u32 htotal;
16199 u32 hblank;
16200 u32 hsync;
16201 u32 vtotal;
16202 u32 vblank;
16203 u32 vsync;
16204 } transcoder[4];
16205 };
16206
16207 struct intel_display_error_state *
16208 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16209 {
16210 struct intel_display_error_state *error;
16211 int transcoders[] = {
16212 TRANSCODER_A,
16213 TRANSCODER_B,
16214 TRANSCODER_C,
16215 TRANSCODER_EDP,
16216 };
16217 int i;
16218
16219 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16220 return NULL;
16221
16222 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16223 if (error == NULL)
16224 return NULL;
16225
16226 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16227 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16228
16229 for_each_pipe(dev_priv, i) {
16230 error->pipe[i].power_domain_on =
16231 __intel_display_power_is_enabled(dev_priv,
16232 POWER_DOMAIN_PIPE(i));
16233 if (!error->pipe[i].power_domain_on)
16234 continue;
16235
16236 error->cursor[i].control = I915_READ(CURCNTR(i));
16237 error->cursor[i].position = I915_READ(CURPOS(i));
16238 error->cursor[i].base = I915_READ(CURBASE(i));
16239
16240 error->plane[i].control = I915_READ(DSPCNTR(i));
16241 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16242 if (INTEL_GEN(dev_priv) <= 3) {
16243 error->plane[i].size = I915_READ(DSPSIZE(i));
16244 error->plane[i].pos = I915_READ(DSPPOS(i));
16245 }
16246 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16247 error->plane[i].addr = I915_READ(DSPADDR(i));
16248 if (INTEL_GEN(dev_priv) >= 4) {
16249 error->plane[i].surface = I915_READ(DSPSURF(i));
16250 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16251 }
16252
16253 error->pipe[i].source = I915_READ(PIPESRC(i));
16254
16255 if (HAS_GMCH_DISPLAY(dev_priv))
16256 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16257 }
16258
16259 /* Note: this does not include DSI transcoders. */
16260 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16261 if (HAS_DDI(dev_priv))
16262 error->num_transcoders++; /* Account for eDP. */
16263
16264 for (i = 0; i < error->num_transcoders; i++) {
16265 enum transcoder cpu_transcoder = transcoders[i];
16266
16267 error->transcoder[i].power_domain_on =
16268 __intel_display_power_is_enabled(dev_priv,
16269 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16270 if (!error->transcoder[i].power_domain_on)
16271 continue;
16272
16273 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16274
16275 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16276 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16277 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16278 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16279 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16280 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16281 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16282 }
16283
16284 return error;
16285 }
16286
16287 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16288
16289 void
16290 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16291 struct drm_device *dev,
16292 struct intel_display_error_state *error)
16293 {
16294 struct drm_i915_private *dev_priv = dev->dev_private;
16295 int i;
16296
16297 if (!error)
16298 return;
16299
16300 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16301 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16302 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16303 error->power_well_driver);
16304 for_each_pipe(dev_priv, i) {
16305 err_printf(m, "Pipe [%d]:\n", i);
16306 err_printf(m, " Power: %s\n",
16307 onoff(error->pipe[i].power_domain_on));
16308 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16309 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16310
16311 err_printf(m, "Plane [%d]:\n", i);
16312 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16313 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16314 if (INTEL_INFO(dev)->gen <= 3) {
16315 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16316 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16317 }
16318 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16319 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16320 if (INTEL_INFO(dev)->gen >= 4) {
16321 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16322 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16323 }
16324
16325 err_printf(m, "Cursor [%d]:\n", i);
16326 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16327 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16328 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16329 }
16330
16331 for (i = 0; i < error->num_transcoders; i++) {
16332 err_printf(m, "CPU transcoder: %s\n",
16333 transcoder_name(error->transcoder[i].cpu_transcoder));
16334 err_printf(m, " Power: %s\n",
16335 onoff(error->transcoder[i].power_domain_on));
16336 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16337 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16338 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16339 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16340 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16341 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16342 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16343 }
16344 }
Ubuntu Artful kernel mirror