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drm/i915: Limit calling mark-busy only for potential scanouts
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static inline u32 /* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device *dev)
103 {
104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
109 }
110
111 static const intel_limit_t intel_limits_i8xx_dvo = {
112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
122 .find_pll = intel_find_best_PLL,
123 };
124
125 static const intel_limit_t intel_limits_i8xx_lvds = {
126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
136 .find_pll = intel_find_best_PLL,
137 };
138
139 static const intel_limit_t intel_limits_i9xx_sdvo = {
140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
150 .find_pll = intel_find_best_PLL,
151 };
152
153 static const intel_limit_t intel_limits_i9xx_lvds = {
154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
164 .find_pll = intel_find_best_PLL,
165 };
166
167
168 static const intel_limit_t intel_limits_g4x_sdvo = {
169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
180 },
181 .find_pll = intel_g4x_find_best_PLL,
182 };
183
184 static const intel_limit_t intel_limits_g4x_hdmi = {
185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
195 .find_pll = intel_g4x_find_best_PLL,
196 };
197
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
224 },
225 .find_pll = intel_g4x_find_best_PLL,
226 };
227
228 static const intel_limit_t intel_limits_g4x_display_port = {
229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 10, .p2_fast = 10 },
239 .find_pll = intel_find_pll_g4x_dp,
240 };
241
242 static const intel_limit_t intel_limits_pineview_sdvo = {
243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
255 .find_pll = intel_find_best_PLL,
256 };
257
258 static const intel_limit_t intel_limits_pineview_lvds = {
259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
269 .find_pll = intel_find_best_PLL,
270 };
271
272 /* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
277 static const intel_limit_t intel_limits_ironlake_dac = {
278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
288 .find_pll = intel_g4x_find_best_PLL,
289 };
290
291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
302 .find_pll = intel_g4x_find_best_PLL,
303 };
304
305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
316 .find_pll = intel_g4x_find_best_PLL,
317 };
318
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 static const intel_limit_t intel_limits_ironlake_display_port = {
349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 10, .p2_fast = 10 },
359 .find_pll = intel_find_pll_ironlake_dp,
360 };
361
362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363 {
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382 out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385 }
386
387 static void vlv_init_dpio(struct drm_device *dev)
388 {
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396 }
397
398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399 {
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402 }
403
404 static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414 };
415
416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418 {
419 unsigned int val;
420
421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
453 /* LVDS dual channel */
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
459 if (refclk == 100000)
460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
467 else
468 limit = &intel_limits_ironlake_dac;
469
470 return limit;
471 }
472
473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474 {
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
480 if (is_dual_link_lvds(dev_priv, LVDS))
481 /* LVDS with dual channel */
482 limit = &intel_limits_g4x_dual_channel_lvds;
483 else
484 /* LVDS with dual channel */
485 limit = &intel_limits_g4x_single_channel_lvds;
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
488 limit = &intel_limits_g4x_hdmi;
489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
490 limit = &intel_limits_g4x_sdvo;
491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
492 limit = &intel_limits_g4x_display_port;
493 } else /* The option is for other outputs */
494 limit = &intel_limits_i9xx_sdvo;
495
496 return limit;
497 }
498
499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
500 {
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
504 if (HAS_PCH_SPLIT(dev))
505 limit = intel_ironlake_limit(crtc, refclk);
506 else if (IS_G4X(dev)) {
507 limit = intel_g4x_limit(crtc);
508 } else if (IS_PINEVIEW(dev)) {
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_pineview_lvds;
511 else
512 limit = &intel_limits_pineview_sdvo;
513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
520 limit = &intel_limits_i8xx_lvds;
521 else
522 limit = &intel_limits_i8xx_dvo;
523 }
524 return limit;
525 }
526
527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
528 static void pineview_clock(int refclk, intel_clock_t *clock)
529 {
530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534 }
535
536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537 {
538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
540 return;
541 }
542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
552 {
553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
562 }
563
564 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
565 /**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
570 static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
573 {
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->p < limit->p.min || limit->p.max < clock->p)
577 INTELPllInvalid("p out of range\n");
578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
579 INTELPllInvalid("m2 out of range\n");
580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
581 INTELPllInvalid("m1 out of range\n");
582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
583 INTELPllInvalid("m1 <= m2\n");
584 if (clock->m < limit->m.min || limit->m.max < clock->m)
585 INTELPllInvalid("m out of range\n");
586 if (clock->n < limit->n.min || limit->n.max < clock->n)
587 INTELPllInvalid("n out of range\n");
588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
589 INTELPllInvalid("vco out of range\n");
590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
594 INTELPllInvalid("dot out of range\n");
595
596 return true;
597 }
598
599 static bool
600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
603
604 {
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
611 (I915_READ(LVDS)) != 0) {
612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
618 if (is_dual_link_lvds(dev_priv, LVDS))
619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
629 memset(best_clock, 0, sizeof(*best_clock));
630
631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
642 int this_err;
643
644 intel_clock(dev, refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
647 continue;
648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663 }
664
665 static bool
666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
680 int lvds_reg;
681
682 if (HAS_PCH_SPLIT(dev))
683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
700 /* based on hardware requirement, prefer smaller n to precision */
701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
702 /* based on hardware requirement, prefere larger m1,m2 */
703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
711 intel_clock(dev, refclk, &clock);
712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
730 return found;
731 }
732
733 static bool
734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
737 {
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
740
741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757 }
758
759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
760 static bool
761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
785 }
786
787 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788 {
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796 }
797
798 /**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
807 {
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 int pipestat_reg = PIPESTAT(pipe);
810
811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
832 /* Wait for vblank interrupt bit to set */
833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
836 DRM_DEBUG_KMS("vblank wait timed out\n");
837 }
838
839 /*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
854 *
855 */
856 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
857 {
858 struct drm_i915_private *dev_priv = dev->dev_private;
859
860 if (INTEL_INFO(dev)->gen >= 4) {
861 int reg = PIPECONF(pipe);
862
863 /* Wait for the Pipe State to go off */
864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
868 u32 last_line, line_mask;
869 int reg = PIPEDSL(pipe);
870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
877 /* Wait for the display line to settle */
878 do {
879 last_line = I915_READ(reg) & line_mask;
880 mdelay(5);
881 } while (((I915_READ(reg) & line_mask) != last_line) &&
882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
886 }
887
888 static const char *state_string(bool enabled)
889 {
890 return enabled ? "on" : "off";
891 }
892
893 /* Only for pre-ILK configs */
894 static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896 {
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907 }
908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
911 /* For ILK+ */
912 static void assert_pch_pll(struct drm_i915_private *dev_priv,
913 struct intel_crtc *intel_crtc, bool state)
914 {
915 int reg;
916 u32 val;
917 bool cur_state;
918
919 if (!intel_crtc->pch_pll) {
920 WARN(1, "asserting PCH PLL enabled with no PLL\n");
921 return;
922 }
923
924 if (HAS_PCH_CPT(dev_priv->dev)) {
925 u32 pch_dpll;
926
927 pch_dpll = I915_READ(PCH_DPLL_SEL);
928
929 /* Make sure the selected PLL is enabled to the transcoder */
930 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
931 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
932 }
933
934 reg = intel_crtc->pch_pll->pll_reg;
935 val = I915_READ(reg);
936 cur_state = !!(val & DPLL_VCO_ENABLE);
937 WARN(cur_state != state,
938 "PCH PLL state assertion failure (expected %s, current %s)\n",
939 state_string(state), state_string(cur_state));
940 }
941 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
942 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
943
944 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946 {
947 int reg;
948 u32 val;
949 bool cur_state;
950
951 reg = FDI_TX_CTL(pipe);
952 val = I915_READ(reg);
953 cur_state = !!(val & FDI_TX_ENABLE);
954 WARN(cur_state != state,
955 "FDI TX state assertion failure (expected %s, current %s)\n",
956 state_string(state), state_string(cur_state));
957 }
958 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
959 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
960
961 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
962 enum pipe pipe, bool state)
963 {
964 int reg;
965 u32 val;
966 bool cur_state;
967
968 reg = FDI_RX_CTL(pipe);
969 val = I915_READ(reg);
970 cur_state = !!(val & FDI_RX_ENABLE);
971 WARN(cur_state != state,
972 "FDI RX state assertion failure (expected %s, current %s)\n",
973 state_string(state), state_string(cur_state));
974 }
975 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
976 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
977
978 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
979 enum pipe pipe)
980 {
981 int reg;
982 u32 val;
983
984 /* ILK FDI PLL is always enabled */
985 if (dev_priv->info->gen == 5)
986 return;
987
988 reg = FDI_TX_CTL(pipe);
989 val = I915_READ(reg);
990 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
991 }
992
993 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
994 enum pipe pipe)
995 {
996 int reg;
997 u32 val;
998
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002 }
1003
1004 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006 {
1007 int pp_reg, lvds_reg;
1008 u32 val;
1009 enum pipe panel_pipe = PIPE_A;
1010 bool locked = true;
1011
1012 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013 pp_reg = PCH_PP_CONTROL;
1014 lvds_reg = PCH_LVDS;
1015 } else {
1016 pp_reg = PP_CONTROL;
1017 lvds_reg = LVDS;
1018 }
1019
1020 val = I915_READ(pp_reg);
1021 if (!(val & PANEL_POWER_ON) ||
1022 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023 locked = false;
1024
1025 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026 panel_pipe = PIPE_B;
1027
1028 WARN(panel_pipe == pipe && locked,
1029 "panel assertion failure, pipe %c regs locked\n",
1030 pipe_name(pipe));
1031 }
1032
1033 void assert_pipe(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
1035 {
1036 int reg;
1037 u32 val;
1038 bool cur_state;
1039
1040 /* if we need the pipe A quirk it must be always on */
1041 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042 state = true;
1043
1044 reg = PIPECONF(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & PIPECONF_ENABLE);
1047 WARN(cur_state != state,
1048 "pipe %c assertion failure (expected %s, current %s)\n",
1049 pipe_name(pipe), state_string(state), state_string(cur_state));
1050 }
1051
1052 static void assert_plane(struct drm_i915_private *dev_priv,
1053 enum plane plane, bool state)
1054 {
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DSPCNTR(plane);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062 WARN(cur_state != state,
1063 "plane %c assertion failure (expected %s, current %s)\n",
1064 plane_name(plane), state_string(state), state_string(cur_state));
1065 }
1066
1067 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
1070 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe)
1072 {
1073 int reg, i;
1074 u32 val;
1075 int cur_pipe;
1076
1077 /* Planes are fixed to pipes on ILK+ */
1078 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079 reg = DSPCNTR(pipe);
1080 val = I915_READ(reg);
1081 WARN((val & DISPLAY_PLANE_ENABLE),
1082 "plane %c assertion failure, should be disabled but not\n",
1083 plane_name(pipe));
1084 return;
1085 }
1086
1087 /* Need to check both planes against the pipe */
1088 for (i = 0; i < 2; i++) {
1089 reg = DSPCNTR(i);
1090 val = I915_READ(reg);
1091 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092 DISPPLANE_SEL_PIPE_SHIFT;
1093 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1094 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095 plane_name(i), pipe_name(pipe));
1096 }
1097 }
1098
1099 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100 {
1101 u32 val;
1102 bool enabled;
1103
1104 val = I915_READ(PCH_DREF_CONTROL);
1105 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106 DREF_SUPERSPREAD_SOURCE_MASK));
1107 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108 }
1109
1110 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111 enum pipe pipe)
1112 {
1113 int reg;
1114 u32 val;
1115 bool enabled;
1116
1117 reg = TRANSCONF(pipe);
1118 val = I915_READ(reg);
1119 enabled = !!(val & TRANS_ENABLE);
1120 WARN(enabled,
1121 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122 pipe_name(pipe));
1123 }
1124
1125 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe, u32 port_sel, u32 val)
1127 {
1128 if ((val & DP_PORT_EN) == 0)
1129 return false;
1130
1131 if (HAS_PCH_CPT(dev_priv->dev)) {
1132 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135 return false;
1136 } else {
1137 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138 return false;
1139 }
1140 return true;
1141 }
1142
1143 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, u32 val)
1145 {
1146 if ((val & PORT_ENABLE) == 0)
1147 return false;
1148
1149 if (HAS_PCH_CPT(dev_priv->dev)) {
1150 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151 return false;
1152 } else {
1153 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154 return false;
1155 }
1156 return true;
1157 }
1158
1159 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, u32 val)
1161 {
1162 if ((val & LVDS_PORT_EN) == 0)
1163 return false;
1164
1165 if (HAS_PCH_CPT(dev_priv->dev)) {
1166 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167 return false;
1168 } else {
1169 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170 return false;
1171 }
1172 return true;
1173 }
1174
1175 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176 enum pipe pipe, u32 val)
1177 {
1178 if ((val & ADPA_DAC_ENABLE) == 0)
1179 return false;
1180 if (HAS_PCH_CPT(dev_priv->dev)) {
1181 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182 return false;
1183 } else {
1184 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185 return false;
1186 }
1187 return true;
1188 }
1189
1190 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1191 enum pipe pipe, int reg, u32 port_sel)
1192 {
1193 u32 val = I915_READ(reg);
1194 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1195 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1196 reg, pipe_name(pipe));
1197 }
1198
1199 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, int reg)
1201 {
1202 u32 val = I915_READ(reg);
1203 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1204 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1205 reg, pipe_name(pipe));
1206 }
1207
1208 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210 {
1211 int reg;
1212 u32 val;
1213
1214 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1217
1218 reg = PCH_ADPA;
1219 val = I915_READ(reg);
1220 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1221 "PCH VGA enabled on transcoder %c, should be disabled\n",
1222 pipe_name(pipe));
1223
1224 reg = PCH_LVDS;
1225 val = I915_READ(reg);
1226 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1227 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1228 pipe_name(pipe));
1229
1230 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233 }
1234
1235 /**
1236 * intel_enable_pll - enable a PLL
1237 * @dev_priv: i915 private structure
1238 * @pipe: pipe PLL to enable
1239 *
1240 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1241 * make sure the PLL reg is writable first though, since the panel write
1242 * protect mechanism may be enabled.
1243 *
1244 * Note! This is for pre-ILK only.
1245 */
1246 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247 {
1248 int reg;
1249 u32 val;
1250
1251 /* No really, not for ILK+ */
1252 BUG_ON(dev_priv->info->gen >= 5);
1253
1254 /* PLL is protected by panel, make sure we can write it */
1255 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256 assert_panel_unlocked(dev_priv, pipe);
1257
1258 reg = DPLL(pipe);
1259 val = I915_READ(reg);
1260 val |= DPLL_VCO_ENABLE;
1261
1262 /* We do this three times for luck */
1263 I915_WRITE(reg, val);
1264 POSTING_READ(reg);
1265 udelay(150); /* wait for warmup */
1266 I915_WRITE(reg, val);
1267 POSTING_READ(reg);
1268 udelay(150); /* wait for warmup */
1269 I915_WRITE(reg, val);
1270 POSTING_READ(reg);
1271 udelay(150); /* wait for warmup */
1272 }
1273
1274 /**
1275 * intel_disable_pll - disable a PLL
1276 * @dev_priv: i915 private structure
1277 * @pipe: pipe PLL to disable
1278 *
1279 * Disable the PLL for @pipe, making sure the pipe is off first.
1280 *
1281 * Note! This is for pre-ILK only.
1282 */
1283 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284 {
1285 int reg;
1286 u32 val;
1287
1288 /* Don't disable pipe A or pipe A PLLs if needed */
1289 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290 return;
1291
1292 /* Make sure the pipe isn't still relying on us */
1293 assert_pipe_disabled(dev_priv, pipe);
1294
1295 reg = DPLL(pipe);
1296 val = I915_READ(reg);
1297 val &= ~DPLL_VCO_ENABLE;
1298 I915_WRITE(reg, val);
1299 POSTING_READ(reg);
1300 }
1301
1302 /**
1303 * intel_enable_pch_pll - enable PCH PLL
1304 * @dev_priv: i915 private structure
1305 * @pipe: pipe PLL to enable
1306 *
1307 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1308 * drives the transcoder clock.
1309 */
1310 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1311 {
1312 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1313 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1314 int reg;
1315 u32 val;
1316
1317 /* PCH only available on ILK+ */
1318 BUG_ON(dev_priv->info->gen < 5);
1319 BUG_ON(pll == NULL);
1320 BUG_ON(pll->refcount == 0);
1321
1322 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1323 pll->pll_reg, pll->active, pll->on,
1324 intel_crtc->base.base.id);
1325
1326 /* PCH refclock must be enabled first */
1327 assert_pch_refclk_enabled(dev_priv);
1328
1329 if (pll->active++ && pll->on) {
1330 assert_pch_pll_enabled(dev_priv, intel_crtc);
1331 return;
1332 }
1333
1334 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1335
1336 reg = pll->pll_reg;
1337 val = I915_READ(reg);
1338 val |= DPLL_VCO_ENABLE;
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(200);
1342
1343 pll->on = true;
1344 }
1345
1346 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1347 {
1348 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1349 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1350 int reg;
1351 u32 val;
1352
1353 /* PCH only available on ILK+ */
1354 BUG_ON(dev_priv->info->gen < 5);
1355 if (pll == NULL)
1356 return;
1357
1358 BUG_ON(pll->refcount == 0);
1359
1360 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1361 pll->pll_reg, pll->active, pll->on,
1362 intel_crtc->base.base.id);
1363
1364 BUG_ON(pll->active == 0);
1365 if (--pll->active) {
1366 assert_pch_pll_enabled(dev_priv, intel_crtc);
1367 return;
1368 }
1369
1370 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1371
1372 /* Make sure transcoder isn't still depending on us */
1373 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1374
1375 reg = pll->pll_reg;
1376 val = I915_READ(reg);
1377 val &= ~DPLL_VCO_ENABLE;
1378 I915_WRITE(reg, val);
1379 POSTING_READ(reg);
1380 udelay(200);
1381
1382 pll->on = false;
1383 }
1384
1385 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 int reg;
1389 u32 val, pipeconf_val;
1390 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1391
1392 /* PCH only available on ILK+ */
1393 BUG_ON(dev_priv->info->gen < 5);
1394
1395 /* Make sure PCH DPLL is enabled */
1396 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1397
1398 /* FDI must be feeding us bits for PCH ports */
1399 assert_fdi_tx_enabled(dev_priv, pipe);
1400 assert_fdi_rx_enabled(dev_priv, pipe);
1401
1402 reg = TRANSCONF(pipe);
1403 val = I915_READ(reg);
1404 pipeconf_val = I915_READ(PIPECONF(pipe));
1405
1406 if (HAS_PCH_IBX(dev_priv->dev)) {
1407 /*
1408 * make the BPC in transcoder be consistent with
1409 * that in pipeconf reg.
1410 */
1411 val &= ~PIPE_BPC_MASK;
1412 val |= pipeconf_val & PIPE_BPC_MASK;
1413 }
1414
1415 val &= ~TRANS_INTERLACE_MASK;
1416 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1417 if (HAS_PCH_IBX(dev_priv->dev) &&
1418 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1419 val |= TRANS_LEGACY_INTERLACED_ILK;
1420 else
1421 val |= TRANS_INTERLACED;
1422 else
1423 val |= TRANS_PROGRESSIVE;
1424
1425 I915_WRITE(reg, val | TRANS_ENABLE);
1426 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1427 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1428 }
1429
1430 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1431 enum pipe pipe)
1432 {
1433 int reg;
1434 u32 val;
1435
1436 /* FDI relies on the transcoder */
1437 assert_fdi_tx_disabled(dev_priv, pipe);
1438 assert_fdi_rx_disabled(dev_priv, pipe);
1439
1440 /* Ports must be off as well */
1441 assert_pch_ports_disabled(dev_priv, pipe);
1442
1443 reg = TRANSCONF(pipe);
1444 val = I915_READ(reg);
1445 val &= ~TRANS_ENABLE;
1446 I915_WRITE(reg, val);
1447 /* wait for PCH transcoder off, transcoder state */
1448 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1449 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1450 }
1451
1452 /**
1453 * intel_enable_pipe - enable a pipe, asserting requirements
1454 * @dev_priv: i915 private structure
1455 * @pipe: pipe to enable
1456 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1457 *
1458 * Enable @pipe, making sure that various hardware specific requirements
1459 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1460 *
1461 * @pipe should be %PIPE_A or %PIPE_B.
1462 *
1463 * Will wait until the pipe is actually running (i.e. first vblank) before
1464 * returning.
1465 */
1466 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1467 bool pch_port)
1468 {
1469 int reg;
1470 u32 val;
1471
1472 /*
1473 * A pipe without a PLL won't actually be able to drive bits from
1474 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1475 * need the check.
1476 */
1477 if (!HAS_PCH_SPLIT(dev_priv->dev))
1478 assert_pll_enabled(dev_priv, pipe);
1479 else {
1480 if (pch_port) {
1481 /* if driving the PCH, we need FDI enabled */
1482 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1483 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1484 }
1485 /* FIXME: assert CPU port conditions for SNB+ */
1486 }
1487
1488 reg = PIPECONF(pipe);
1489 val = I915_READ(reg);
1490 if (val & PIPECONF_ENABLE)
1491 return;
1492
1493 I915_WRITE(reg, val | PIPECONF_ENABLE);
1494 intel_wait_for_vblank(dev_priv->dev, pipe);
1495 }
1496
1497 /**
1498 * intel_disable_pipe - disable a pipe, asserting requirements
1499 * @dev_priv: i915 private structure
1500 * @pipe: pipe to disable
1501 *
1502 * Disable @pipe, making sure that various hardware specific requirements
1503 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1504 *
1505 * @pipe should be %PIPE_A or %PIPE_B.
1506 *
1507 * Will wait until the pipe has shut down before returning.
1508 */
1509 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1510 enum pipe pipe)
1511 {
1512 int reg;
1513 u32 val;
1514
1515 /*
1516 * Make sure planes won't keep trying to pump pixels to us,
1517 * or we might hang the display.
1518 */
1519 assert_planes_disabled(dev_priv, pipe);
1520
1521 /* Don't disable pipe A or pipe A PLLs if needed */
1522 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1523 return;
1524
1525 reg = PIPECONF(pipe);
1526 val = I915_READ(reg);
1527 if ((val & PIPECONF_ENABLE) == 0)
1528 return;
1529
1530 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1531 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1532 }
1533
1534 /*
1535 * Plane regs are double buffered, going from enabled->disabled needs a
1536 * trigger in order to latch. The display address reg provides this.
1537 */
1538 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1539 enum plane plane)
1540 {
1541 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1542 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1543 }
1544
1545 /**
1546 * intel_enable_plane - enable a display plane on a given pipe
1547 * @dev_priv: i915 private structure
1548 * @plane: plane to enable
1549 * @pipe: pipe being fed
1550 *
1551 * Enable @plane on @pipe, making sure that @pipe is running first.
1552 */
1553 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1554 enum plane plane, enum pipe pipe)
1555 {
1556 int reg;
1557 u32 val;
1558
1559 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1560 assert_pipe_enabled(dev_priv, pipe);
1561
1562 reg = DSPCNTR(plane);
1563 val = I915_READ(reg);
1564 if (val & DISPLAY_PLANE_ENABLE)
1565 return;
1566
1567 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1568 intel_flush_display_plane(dev_priv, plane);
1569 intel_wait_for_vblank(dev_priv->dev, pipe);
1570 }
1571
1572 /**
1573 * intel_disable_plane - disable a display plane
1574 * @dev_priv: i915 private structure
1575 * @plane: plane to disable
1576 * @pipe: pipe consuming the data
1577 *
1578 * Disable @plane; should be an independent operation.
1579 */
1580 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1581 enum plane plane, enum pipe pipe)
1582 {
1583 int reg;
1584 u32 val;
1585
1586 reg = DSPCNTR(plane);
1587 val = I915_READ(reg);
1588 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1589 return;
1590
1591 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1592 intel_flush_display_plane(dev_priv, plane);
1593 intel_wait_for_vblank(dev_priv->dev, pipe);
1594 }
1595
1596 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1597 enum pipe pipe, int reg, u32 port_sel)
1598 {
1599 u32 val = I915_READ(reg);
1600 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1601 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1602 I915_WRITE(reg, val & ~DP_PORT_EN);
1603 }
1604 }
1605
1606 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1607 enum pipe pipe, int reg)
1608 {
1609 u32 val = I915_READ(reg);
1610 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1611 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1612 reg, pipe);
1613 I915_WRITE(reg, val & ~PORT_ENABLE);
1614 }
1615 }
1616
1617 /* Disable any ports connected to this transcoder */
1618 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1619 enum pipe pipe)
1620 {
1621 u32 reg, val;
1622
1623 val = I915_READ(PCH_PP_CONTROL);
1624 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1625
1626 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1627 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1628 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1629
1630 reg = PCH_ADPA;
1631 val = I915_READ(reg);
1632 if (adpa_pipe_enabled(dev_priv, val, pipe))
1633 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1634
1635 reg = PCH_LVDS;
1636 val = I915_READ(reg);
1637 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1638 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1639 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1640 POSTING_READ(reg);
1641 udelay(100);
1642 }
1643
1644 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1645 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1646 disable_pch_hdmi(dev_priv, pipe, HDMID);
1647 }
1648
1649 int
1650 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1651 struct drm_i915_gem_object *obj,
1652 struct intel_ring_buffer *pipelined)
1653 {
1654 struct drm_i915_private *dev_priv = dev->dev_private;
1655 u32 alignment;
1656 int ret;
1657
1658 switch (obj->tiling_mode) {
1659 case I915_TILING_NONE:
1660 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1661 alignment = 128 * 1024;
1662 else if (INTEL_INFO(dev)->gen >= 4)
1663 alignment = 4 * 1024;
1664 else
1665 alignment = 64 * 1024;
1666 break;
1667 case I915_TILING_X:
1668 /* pin() will align the object as required by fence */
1669 alignment = 0;
1670 break;
1671 case I915_TILING_Y:
1672 /* FIXME: Is this true? */
1673 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1674 return -EINVAL;
1675 default:
1676 BUG();
1677 }
1678
1679 dev_priv->mm.interruptible = false;
1680 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1681 if (ret)
1682 goto err_interruptible;
1683
1684 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1685 * fence, whereas 965+ only requires a fence if using
1686 * framebuffer compression. For simplicity, we always install
1687 * a fence as the cost is not that onerous.
1688 */
1689 ret = i915_gem_object_get_fence(obj);
1690 if (ret)
1691 goto err_unpin;
1692
1693 i915_gem_object_pin_fence(obj);
1694
1695 dev_priv->mm.interruptible = true;
1696 return 0;
1697
1698 err_unpin:
1699 i915_gem_object_unpin(obj);
1700 err_interruptible:
1701 dev_priv->mm.interruptible = true;
1702 return ret;
1703 }
1704
1705 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1706 {
1707 i915_gem_object_unpin_fence(obj);
1708 i915_gem_object_unpin(obj);
1709 }
1710
1711 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1712 int x, int y)
1713 {
1714 struct drm_device *dev = crtc->dev;
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1717 struct intel_framebuffer *intel_fb;
1718 struct drm_i915_gem_object *obj;
1719 int plane = intel_crtc->plane;
1720 unsigned long Start, Offset;
1721 u32 dspcntr;
1722 u32 reg;
1723
1724 switch (plane) {
1725 case 0:
1726 case 1:
1727 break;
1728 default:
1729 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1730 return -EINVAL;
1731 }
1732
1733 intel_fb = to_intel_framebuffer(fb);
1734 obj = intel_fb->obj;
1735
1736 reg = DSPCNTR(plane);
1737 dspcntr = I915_READ(reg);
1738 /* Mask out pixel format bits in case we change it */
1739 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1740 switch (fb->bits_per_pixel) {
1741 case 8:
1742 dspcntr |= DISPPLANE_8BPP;
1743 break;
1744 case 16:
1745 if (fb->depth == 15)
1746 dspcntr |= DISPPLANE_15_16BPP;
1747 else
1748 dspcntr |= DISPPLANE_16BPP;
1749 break;
1750 case 24:
1751 case 32:
1752 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1753 break;
1754 default:
1755 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1756 return -EINVAL;
1757 }
1758 if (INTEL_INFO(dev)->gen >= 4) {
1759 if (obj->tiling_mode != I915_TILING_NONE)
1760 dspcntr |= DISPPLANE_TILED;
1761 else
1762 dspcntr &= ~DISPPLANE_TILED;
1763 }
1764
1765 I915_WRITE(reg, dspcntr);
1766
1767 Start = obj->gtt_offset;
1768 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1769
1770 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1771 Start, Offset, x, y, fb->pitches[0]);
1772 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1773 if (INTEL_INFO(dev)->gen >= 4) {
1774 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1775 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1776 I915_WRITE(DSPADDR(plane), Offset);
1777 } else
1778 I915_WRITE(DSPADDR(plane), Start + Offset);
1779 POSTING_READ(reg);
1780
1781 return 0;
1782 }
1783
1784 static int ironlake_update_plane(struct drm_crtc *crtc,
1785 struct drm_framebuffer *fb, int x, int y)
1786 {
1787 struct drm_device *dev = crtc->dev;
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1790 struct intel_framebuffer *intel_fb;
1791 struct drm_i915_gem_object *obj;
1792 int plane = intel_crtc->plane;
1793 unsigned long Start, Offset;
1794 u32 dspcntr;
1795 u32 reg;
1796
1797 switch (plane) {
1798 case 0:
1799 case 1:
1800 case 2:
1801 break;
1802 default:
1803 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1804 return -EINVAL;
1805 }
1806
1807 intel_fb = to_intel_framebuffer(fb);
1808 obj = intel_fb->obj;
1809
1810 reg = DSPCNTR(plane);
1811 dspcntr = I915_READ(reg);
1812 /* Mask out pixel format bits in case we change it */
1813 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1814 switch (fb->bits_per_pixel) {
1815 case 8:
1816 dspcntr |= DISPPLANE_8BPP;
1817 break;
1818 case 16:
1819 if (fb->depth != 16)
1820 return -EINVAL;
1821
1822 dspcntr |= DISPPLANE_16BPP;
1823 break;
1824 case 24:
1825 case 32:
1826 if (fb->depth == 24)
1827 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1828 else if (fb->depth == 30)
1829 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1830 else
1831 return -EINVAL;
1832 break;
1833 default:
1834 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1835 return -EINVAL;
1836 }
1837
1838 if (obj->tiling_mode != I915_TILING_NONE)
1839 dspcntr |= DISPPLANE_TILED;
1840 else
1841 dspcntr &= ~DISPPLANE_TILED;
1842
1843 /* must disable */
1844 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1845
1846 I915_WRITE(reg, dspcntr);
1847
1848 Start = obj->gtt_offset;
1849 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1850
1851 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1852 Start, Offset, x, y, fb->pitches[0]);
1853 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1854 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1856 I915_WRITE(DSPADDR(plane), Offset);
1857 POSTING_READ(reg);
1858
1859 return 0;
1860 }
1861
1862 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1863 static int
1864 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1865 int x, int y, enum mode_set_atomic state)
1866 {
1867 struct drm_device *dev = crtc->dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869
1870 if (dev_priv->display.disable_fbc)
1871 dev_priv->display.disable_fbc(dev);
1872 intel_increase_pllclock(crtc);
1873
1874 return dev_priv->display.update_plane(crtc, fb, x, y);
1875 }
1876
1877 static int
1878 intel_finish_fb(struct drm_framebuffer *old_fb)
1879 {
1880 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1881 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1882 bool was_interruptible = dev_priv->mm.interruptible;
1883 int ret;
1884
1885 wait_event(dev_priv->pending_flip_queue,
1886 atomic_read(&dev_priv->mm.wedged) ||
1887 atomic_read(&obj->pending_flip) == 0);
1888
1889 /* Big Hammer, we also need to ensure that any pending
1890 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1891 * current scanout is retired before unpinning the old
1892 * framebuffer.
1893 *
1894 * This should only fail upon a hung GPU, in which case we
1895 * can safely continue.
1896 */
1897 dev_priv->mm.interruptible = false;
1898 ret = i915_gem_object_finish_gpu(obj);
1899 dev_priv->mm.interruptible = was_interruptible;
1900
1901 return ret;
1902 }
1903
1904 static int
1905 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1906 struct drm_framebuffer *old_fb)
1907 {
1908 struct drm_device *dev = crtc->dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct drm_i915_master_private *master_priv;
1911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1912 int ret;
1913
1914 /* no fb bound */
1915 if (!crtc->fb) {
1916 DRM_ERROR("No FB bound\n");
1917 return 0;
1918 }
1919
1920 switch (intel_crtc->plane) {
1921 case 0:
1922 case 1:
1923 break;
1924 case 2:
1925 if (IS_IVYBRIDGE(dev))
1926 break;
1927 /* fall through otherwise */
1928 default:
1929 DRM_ERROR("no plane for crtc\n");
1930 return -EINVAL;
1931 }
1932
1933 mutex_lock(&dev->struct_mutex);
1934 ret = intel_pin_and_fence_fb_obj(dev,
1935 to_intel_framebuffer(crtc->fb)->obj,
1936 NULL);
1937 if (ret != 0) {
1938 mutex_unlock(&dev->struct_mutex);
1939 DRM_ERROR("pin & fence failed\n");
1940 return ret;
1941 }
1942
1943 if (old_fb)
1944 intel_finish_fb(old_fb);
1945
1946 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
1947 if (ret) {
1948 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1949 mutex_unlock(&dev->struct_mutex);
1950 DRM_ERROR("failed to update base address\n");
1951 return ret;
1952 }
1953
1954 if (old_fb) {
1955 intel_wait_for_vblank(dev, intel_crtc->pipe);
1956 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1957 }
1958
1959 intel_update_fbc(dev);
1960 mutex_unlock(&dev->struct_mutex);
1961
1962 if (!dev->primary->master)
1963 return 0;
1964
1965 master_priv = dev->primary->master->driver_priv;
1966 if (!master_priv->sarea_priv)
1967 return 0;
1968
1969 if (intel_crtc->pipe) {
1970 master_priv->sarea_priv->pipeB_x = x;
1971 master_priv->sarea_priv->pipeB_y = y;
1972 } else {
1973 master_priv->sarea_priv->pipeA_x = x;
1974 master_priv->sarea_priv->pipeA_y = y;
1975 }
1976
1977 return 0;
1978 }
1979
1980 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1981 {
1982 struct drm_device *dev = crtc->dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984 u32 dpa_ctl;
1985
1986 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1987 dpa_ctl = I915_READ(DP_A);
1988 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1989
1990 if (clock < 200000) {
1991 u32 temp;
1992 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1993 /* workaround for 160Mhz:
1994 1) program 0x4600c bits 15:0 = 0x8124
1995 2) program 0x46010 bit 0 = 1
1996 3) program 0x46034 bit 24 = 1
1997 4) program 0x64000 bit 14 = 1
1998 */
1999 temp = I915_READ(0x4600c);
2000 temp &= 0xffff0000;
2001 I915_WRITE(0x4600c, temp | 0x8124);
2002
2003 temp = I915_READ(0x46010);
2004 I915_WRITE(0x46010, temp | 1);
2005
2006 temp = I915_READ(0x46034);
2007 I915_WRITE(0x46034, temp | (1 << 24));
2008 } else {
2009 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2010 }
2011 I915_WRITE(DP_A, dpa_ctl);
2012
2013 POSTING_READ(DP_A);
2014 udelay(500);
2015 }
2016
2017 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2018 {
2019 struct drm_device *dev = crtc->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022 int pipe = intel_crtc->pipe;
2023 u32 reg, temp;
2024
2025 /* enable normal train */
2026 reg = FDI_TX_CTL(pipe);
2027 temp = I915_READ(reg);
2028 if (IS_IVYBRIDGE(dev)) {
2029 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2030 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2031 } else {
2032 temp &= ~FDI_LINK_TRAIN_NONE;
2033 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2034 }
2035 I915_WRITE(reg, temp);
2036
2037 reg = FDI_RX_CTL(pipe);
2038 temp = I915_READ(reg);
2039 if (HAS_PCH_CPT(dev)) {
2040 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2041 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2042 } else {
2043 temp &= ~FDI_LINK_TRAIN_NONE;
2044 temp |= FDI_LINK_TRAIN_NONE;
2045 }
2046 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2047
2048 /* wait one idle pattern time */
2049 POSTING_READ(reg);
2050 udelay(1000);
2051
2052 /* IVB wants error correction enabled */
2053 if (IS_IVYBRIDGE(dev))
2054 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2055 FDI_FE_ERRC_ENABLE);
2056 }
2057
2058 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2059 {
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061 u32 flags = I915_READ(SOUTH_CHICKEN1);
2062
2063 flags |= FDI_PHASE_SYNC_OVR(pipe);
2064 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2065 flags |= FDI_PHASE_SYNC_EN(pipe);
2066 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2067 POSTING_READ(SOUTH_CHICKEN1);
2068 }
2069
2070 /* The FDI link training functions for ILK/Ibexpeak. */
2071 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2072 {
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2076 int pipe = intel_crtc->pipe;
2077 int plane = intel_crtc->plane;
2078 u32 reg, temp, tries;
2079
2080 /* FDI needs bits from pipe & plane first */
2081 assert_pipe_enabled(dev_priv, pipe);
2082 assert_plane_enabled(dev_priv, plane);
2083
2084 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2085 for train result */
2086 reg = FDI_RX_IMR(pipe);
2087 temp = I915_READ(reg);
2088 temp &= ~FDI_RX_SYMBOL_LOCK;
2089 temp &= ~FDI_RX_BIT_LOCK;
2090 I915_WRITE(reg, temp);
2091 I915_READ(reg);
2092 udelay(150);
2093
2094 /* enable CPU FDI TX and PCH FDI RX */
2095 reg = FDI_TX_CTL(pipe);
2096 temp = I915_READ(reg);
2097 temp &= ~(7 << 19);
2098 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2099 temp &= ~FDI_LINK_TRAIN_NONE;
2100 temp |= FDI_LINK_TRAIN_PATTERN_1;
2101 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2102
2103 reg = FDI_RX_CTL(pipe);
2104 temp = I915_READ(reg);
2105 temp &= ~FDI_LINK_TRAIN_NONE;
2106 temp |= FDI_LINK_TRAIN_PATTERN_1;
2107 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2108
2109 POSTING_READ(reg);
2110 udelay(150);
2111
2112 /* Ironlake workaround, enable clock pointer after FDI enable*/
2113 if (HAS_PCH_IBX(dev)) {
2114 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2115 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2116 FDI_RX_PHASE_SYNC_POINTER_EN);
2117 }
2118
2119 reg = FDI_RX_IIR(pipe);
2120 for (tries = 0; tries < 5; tries++) {
2121 temp = I915_READ(reg);
2122 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2123
2124 if ((temp & FDI_RX_BIT_LOCK)) {
2125 DRM_DEBUG_KMS("FDI train 1 done.\n");
2126 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2127 break;
2128 }
2129 }
2130 if (tries == 5)
2131 DRM_ERROR("FDI train 1 fail!\n");
2132
2133 /* Train 2 */
2134 reg = FDI_TX_CTL(pipe);
2135 temp = I915_READ(reg);
2136 temp &= ~FDI_LINK_TRAIN_NONE;
2137 temp |= FDI_LINK_TRAIN_PATTERN_2;
2138 I915_WRITE(reg, temp);
2139
2140 reg = FDI_RX_CTL(pipe);
2141 temp = I915_READ(reg);
2142 temp &= ~FDI_LINK_TRAIN_NONE;
2143 temp |= FDI_LINK_TRAIN_PATTERN_2;
2144 I915_WRITE(reg, temp);
2145
2146 POSTING_READ(reg);
2147 udelay(150);
2148
2149 reg = FDI_RX_IIR(pipe);
2150 for (tries = 0; tries < 5; tries++) {
2151 temp = I915_READ(reg);
2152 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2153
2154 if (temp & FDI_RX_SYMBOL_LOCK) {
2155 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2156 DRM_DEBUG_KMS("FDI train 2 done.\n");
2157 break;
2158 }
2159 }
2160 if (tries == 5)
2161 DRM_ERROR("FDI train 2 fail!\n");
2162
2163 DRM_DEBUG_KMS("FDI train done\n");
2164
2165 }
2166
2167 static const int snb_b_fdi_train_param[] = {
2168 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2169 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2170 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2171 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2172 };
2173
2174 /* The FDI link training functions for SNB/Cougarpoint. */
2175 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2176 {
2177 struct drm_device *dev = crtc->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180 int pipe = intel_crtc->pipe;
2181 u32 reg, temp, i, retry;
2182
2183 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2184 for train result */
2185 reg = FDI_RX_IMR(pipe);
2186 temp = I915_READ(reg);
2187 temp &= ~FDI_RX_SYMBOL_LOCK;
2188 temp &= ~FDI_RX_BIT_LOCK;
2189 I915_WRITE(reg, temp);
2190
2191 POSTING_READ(reg);
2192 udelay(150);
2193
2194 /* enable CPU FDI TX and PCH FDI RX */
2195 reg = FDI_TX_CTL(pipe);
2196 temp = I915_READ(reg);
2197 temp &= ~(7 << 19);
2198 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2199 temp &= ~FDI_LINK_TRAIN_NONE;
2200 temp |= FDI_LINK_TRAIN_PATTERN_1;
2201 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2202 /* SNB-B */
2203 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2204 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2205
2206 reg = FDI_RX_CTL(pipe);
2207 temp = I915_READ(reg);
2208 if (HAS_PCH_CPT(dev)) {
2209 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2210 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2211 } else {
2212 temp &= ~FDI_LINK_TRAIN_NONE;
2213 temp |= FDI_LINK_TRAIN_PATTERN_1;
2214 }
2215 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2216
2217 POSTING_READ(reg);
2218 udelay(150);
2219
2220 if (HAS_PCH_CPT(dev))
2221 cpt_phase_pointer_enable(dev, pipe);
2222
2223 for (i = 0; i < 4; i++) {
2224 reg = FDI_TX_CTL(pipe);
2225 temp = I915_READ(reg);
2226 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2227 temp |= snb_b_fdi_train_param[i];
2228 I915_WRITE(reg, temp);
2229
2230 POSTING_READ(reg);
2231 udelay(500);
2232
2233 for (retry = 0; retry < 5; retry++) {
2234 reg = FDI_RX_IIR(pipe);
2235 temp = I915_READ(reg);
2236 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2237 if (temp & FDI_RX_BIT_LOCK) {
2238 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2239 DRM_DEBUG_KMS("FDI train 1 done.\n");
2240 break;
2241 }
2242 udelay(50);
2243 }
2244 if (retry < 5)
2245 break;
2246 }
2247 if (i == 4)
2248 DRM_ERROR("FDI train 1 fail!\n");
2249
2250 /* Train 2 */
2251 reg = FDI_TX_CTL(pipe);
2252 temp = I915_READ(reg);
2253 temp &= ~FDI_LINK_TRAIN_NONE;
2254 temp |= FDI_LINK_TRAIN_PATTERN_2;
2255 if (IS_GEN6(dev)) {
2256 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2257 /* SNB-B */
2258 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2259 }
2260 I915_WRITE(reg, temp);
2261
2262 reg = FDI_RX_CTL(pipe);
2263 temp = I915_READ(reg);
2264 if (HAS_PCH_CPT(dev)) {
2265 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2267 } else {
2268 temp &= ~FDI_LINK_TRAIN_NONE;
2269 temp |= FDI_LINK_TRAIN_PATTERN_2;
2270 }
2271 I915_WRITE(reg, temp);
2272
2273 POSTING_READ(reg);
2274 udelay(150);
2275
2276 for (i = 0; i < 4; i++) {
2277 reg = FDI_TX_CTL(pipe);
2278 temp = I915_READ(reg);
2279 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2280 temp |= snb_b_fdi_train_param[i];
2281 I915_WRITE(reg, temp);
2282
2283 POSTING_READ(reg);
2284 udelay(500);
2285
2286 for (retry = 0; retry < 5; retry++) {
2287 reg = FDI_RX_IIR(pipe);
2288 temp = I915_READ(reg);
2289 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2290 if (temp & FDI_RX_SYMBOL_LOCK) {
2291 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2292 DRM_DEBUG_KMS("FDI train 2 done.\n");
2293 break;
2294 }
2295 udelay(50);
2296 }
2297 if (retry < 5)
2298 break;
2299 }
2300 if (i == 4)
2301 DRM_ERROR("FDI train 2 fail!\n");
2302
2303 DRM_DEBUG_KMS("FDI train done.\n");
2304 }
2305
2306 /* Manual link training for Ivy Bridge A0 parts */
2307 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2308 {
2309 struct drm_device *dev = crtc->dev;
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2312 int pipe = intel_crtc->pipe;
2313 u32 reg, temp, i;
2314
2315 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2316 for train result */
2317 reg = FDI_RX_IMR(pipe);
2318 temp = I915_READ(reg);
2319 temp &= ~FDI_RX_SYMBOL_LOCK;
2320 temp &= ~FDI_RX_BIT_LOCK;
2321 I915_WRITE(reg, temp);
2322
2323 POSTING_READ(reg);
2324 udelay(150);
2325
2326 /* enable CPU FDI TX and PCH FDI RX */
2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
2329 temp &= ~(7 << 19);
2330 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2331 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2332 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2333 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2334 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2335 temp |= FDI_COMPOSITE_SYNC;
2336 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2337
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 temp &= ~FDI_LINK_TRAIN_AUTO;
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2343 temp |= FDI_COMPOSITE_SYNC;
2344 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2345
2346 POSTING_READ(reg);
2347 udelay(150);
2348
2349 if (HAS_PCH_CPT(dev))
2350 cpt_phase_pointer_enable(dev, pipe);
2351
2352 for (i = 0; i < 4; i++) {
2353 reg = FDI_TX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2356 temp |= snb_b_fdi_train_param[i];
2357 I915_WRITE(reg, temp);
2358
2359 POSTING_READ(reg);
2360 udelay(500);
2361
2362 reg = FDI_RX_IIR(pipe);
2363 temp = I915_READ(reg);
2364 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2365
2366 if (temp & FDI_RX_BIT_LOCK ||
2367 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2368 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2369 DRM_DEBUG_KMS("FDI train 1 done.\n");
2370 break;
2371 }
2372 }
2373 if (i == 4)
2374 DRM_ERROR("FDI train 1 fail!\n");
2375
2376 /* Train 2 */
2377 reg = FDI_TX_CTL(pipe);
2378 temp = I915_READ(reg);
2379 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2380 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2381 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2382 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2383 I915_WRITE(reg, temp);
2384
2385 reg = FDI_RX_CTL(pipe);
2386 temp = I915_READ(reg);
2387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2388 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2389 I915_WRITE(reg, temp);
2390
2391 POSTING_READ(reg);
2392 udelay(150);
2393
2394 for (i = 0; i < 4; i++) {
2395 reg = FDI_TX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2398 temp |= snb_b_fdi_train_param[i];
2399 I915_WRITE(reg, temp);
2400
2401 POSTING_READ(reg);
2402 udelay(500);
2403
2404 reg = FDI_RX_IIR(pipe);
2405 temp = I915_READ(reg);
2406 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2407
2408 if (temp & FDI_RX_SYMBOL_LOCK) {
2409 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2410 DRM_DEBUG_KMS("FDI train 2 done.\n");
2411 break;
2412 }
2413 }
2414 if (i == 4)
2415 DRM_ERROR("FDI train 2 fail!\n");
2416
2417 DRM_DEBUG_KMS("FDI train done.\n");
2418 }
2419
2420 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2421 {
2422 struct drm_device *dev = crtc->dev;
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2425 int pipe = intel_crtc->pipe;
2426 u32 reg, temp;
2427
2428 /* Write the TU size bits so error detection works */
2429 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2430 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2431
2432 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2433 reg = FDI_RX_CTL(pipe);
2434 temp = I915_READ(reg);
2435 temp &= ~((0x7 << 19) | (0x7 << 16));
2436 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2437 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2438 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2439
2440 POSTING_READ(reg);
2441 udelay(200);
2442
2443 /* Switch from Rawclk to PCDclk */
2444 temp = I915_READ(reg);
2445 I915_WRITE(reg, temp | FDI_PCDCLK);
2446
2447 POSTING_READ(reg);
2448 udelay(200);
2449
2450 /* Enable CPU FDI TX PLL, always on for Ironlake */
2451 reg = FDI_TX_CTL(pipe);
2452 temp = I915_READ(reg);
2453 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2454 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2455
2456 POSTING_READ(reg);
2457 udelay(100);
2458 }
2459 }
2460
2461 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2462 {
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 u32 flags = I915_READ(SOUTH_CHICKEN1);
2465
2466 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2467 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2468 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2469 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2470 POSTING_READ(SOUTH_CHICKEN1);
2471 }
2472 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2473 {
2474 struct drm_device *dev = crtc->dev;
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2477 int pipe = intel_crtc->pipe;
2478 u32 reg, temp;
2479
2480 /* disable CPU FDI tx and PCH FDI rx */
2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
2483 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2484 POSTING_READ(reg);
2485
2486 reg = FDI_RX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~(0x7 << 16);
2489 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2490 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2491
2492 POSTING_READ(reg);
2493 udelay(100);
2494
2495 /* Ironlake workaround, disable clock pointer after downing FDI */
2496 if (HAS_PCH_IBX(dev)) {
2497 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2498 I915_WRITE(FDI_RX_CHICKEN(pipe),
2499 I915_READ(FDI_RX_CHICKEN(pipe) &
2500 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2501 } else if (HAS_PCH_CPT(dev)) {
2502 cpt_phase_pointer_disable(dev, pipe);
2503 }
2504
2505 /* still set train pattern 1 */
2506 reg = FDI_TX_CTL(pipe);
2507 temp = I915_READ(reg);
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 I915_WRITE(reg, temp);
2511
2512 reg = FDI_RX_CTL(pipe);
2513 temp = I915_READ(reg);
2514 if (HAS_PCH_CPT(dev)) {
2515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2517 } else {
2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_1;
2520 }
2521 /* BPC in FDI rx is consistent with that in PIPECONF */
2522 temp &= ~(0x07 << 16);
2523 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2524 I915_WRITE(reg, temp);
2525
2526 POSTING_READ(reg);
2527 udelay(100);
2528 }
2529
2530 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2531 {
2532 struct drm_device *dev = crtc->dev;
2533
2534 if (crtc->fb == NULL)
2535 return;
2536
2537 mutex_lock(&dev->struct_mutex);
2538 intel_finish_fb(crtc->fb);
2539 mutex_unlock(&dev->struct_mutex);
2540 }
2541
2542 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2543 {
2544 struct drm_device *dev = crtc->dev;
2545 struct drm_mode_config *mode_config = &dev->mode_config;
2546 struct intel_encoder *encoder;
2547
2548 /*
2549 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2550 * must be driven by its own crtc; no sharing is possible.
2551 */
2552 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2553 if (encoder->base.crtc != crtc)
2554 continue;
2555
2556 switch (encoder->type) {
2557 case INTEL_OUTPUT_EDP:
2558 if (!intel_encoder_is_pch_edp(&encoder->base))
2559 return false;
2560 continue;
2561 }
2562 }
2563
2564 return true;
2565 }
2566
2567 /*
2568 * Enable PCH resources required for PCH ports:
2569 * - PCH PLLs
2570 * - FDI training & RX/TX
2571 * - update transcoder timings
2572 * - DP transcoding bits
2573 * - transcoder
2574 */
2575 static void ironlake_pch_enable(struct drm_crtc *crtc)
2576 {
2577 struct drm_device *dev = crtc->dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580 int pipe = intel_crtc->pipe;
2581 u32 reg, temp;
2582
2583 /* For PCH output, training FDI link */
2584 dev_priv->display.fdi_link_train(crtc);
2585
2586 intel_enable_pch_pll(intel_crtc);
2587
2588 if (HAS_PCH_CPT(dev)) {
2589 u32 sel;
2590
2591 temp = I915_READ(PCH_DPLL_SEL);
2592 switch (pipe) {
2593 default:
2594 case 0:
2595 temp |= TRANSA_DPLL_ENABLE;
2596 sel = TRANSA_DPLLB_SEL;
2597 break;
2598 case 1:
2599 temp |= TRANSB_DPLL_ENABLE;
2600 sel = TRANSB_DPLLB_SEL;
2601 break;
2602 case 2:
2603 temp |= TRANSC_DPLL_ENABLE;
2604 sel = TRANSC_DPLLB_SEL;
2605 break;
2606 }
2607 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2608 temp |= sel;
2609 else
2610 temp &= ~sel;
2611 I915_WRITE(PCH_DPLL_SEL, temp);
2612 }
2613
2614 /* set transcoder timing, panel must allow it */
2615 assert_panel_unlocked(dev_priv, pipe);
2616 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2617 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2618 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2619
2620 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2621 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2622 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2623 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2624
2625 intel_fdi_normal_train(crtc);
2626
2627 /* For PCH DP, enable TRANS_DP_CTL */
2628 if (HAS_PCH_CPT(dev) &&
2629 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2630 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2631 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2632 reg = TRANS_DP_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2635 TRANS_DP_SYNC_MASK |
2636 TRANS_DP_BPC_MASK);
2637 temp |= (TRANS_DP_OUTPUT_ENABLE |
2638 TRANS_DP_ENH_FRAMING);
2639 temp |= bpc << 9; /* same format but at 11:9 */
2640
2641 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2642 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2643 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2644 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2645
2646 switch (intel_trans_dp_port_sel(crtc)) {
2647 case PCH_DP_B:
2648 temp |= TRANS_DP_PORT_SEL_B;
2649 break;
2650 case PCH_DP_C:
2651 temp |= TRANS_DP_PORT_SEL_C;
2652 break;
2653 case PCH_DP_D:
2654 temp |= TRANS_DP_PORT_SEL_D;
2655 break;
2656 default:
2657 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2658 temp |= TRANS_DP_PORT_SEL_B;
2659 break;
2660 }
2661
2662 I915_WRITE(reg, temp);
2663 }
2664
2665 intel_enable_transcoder(dev_priv, pipe);
2666 }
2667
2668 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2669 {
2670 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2671
2672 if (pll == NULL)
2673 return;
2674
2675 if (pll->refcount == 0) {
2676 WARN(1, "bad PCH PLL refcount\n");
2677 return;
2678 }
2679
2680 --pll->refcount;
2681 intel_crtc->pch_pll = NULL;
2682 }
2683
2684 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2685 {
2686 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2687 struct intel_pch_pll *pll;
2688 int i;
2689
2690 pll = intel_crtc->pch_pll;
2691 if (pll) {
2692 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2693 intel_crtc->base.base.id, pll->pll_reg);
2694 goto prepare;
2695 }
2696
2697 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2698 pll = &dev_priv->pch_plls[i];
2699
2700 /* Only want to check enabled timings first */
2701 if (pll->refcount == 0)
2702 continue;
2703
2704 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2705 fp == I915_READ(pll->fp0_reg)) {
2706 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2707 intel_crtc->base.base.id,
2708 pll->pll_reg, pll->refcount, pll->active);
2709
2710 goto found;
2711 }
2712 }
2713
2714 /* Ok no matching timings, maybe there's a free one? */
2715 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2716 pll = &dev_priv->pch_plls[i];
2717 if (pll->refcount == 0) {
2718 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2719 intel_crtc->base.base.id, pll->pll_reg);
2720 goto found;
2721 }
2722 }
2723
2724 return NULL;
2725
2726 found:
2727 intel_crtc->pch_pll = pll;
2728 pll->refcount++;
2729 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2730 prepare: /* separate function? */
2731 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2732
2733 /* Wait for the clocks to stabilize before rewriting the regs */
2734 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2735 POSTING_READ(pll->pll_reg);
2736 udelay(150);
2737
2738 I915_WRITE(pll->fp0_reg, fp);
2739 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2740 pll->on = false;
2741 return pll;
2742 }
2743
2744 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2745 {
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2748 u32 temp;
2749
2750 temp = I915_READ(dslreg);
2751 udelay(500);
2752 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2753 /* Without this, mode sets may fail silently on FDI */
2754 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2755 udelay(250);
2756 I915_WRITE(tc2reg, 0);
2757 if (wait_for(I915_READ(dslreg) != temp, 5))
2758 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2759 }
2760 }
2761
2762 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2763 {
2764 struct drm_device *dev = crtc->dev;
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2767 int pipe = intel_crtc->pipe;
2768 int plane = intel_crtc->plane;
2769 u32 temp;
2770 bool is_pch_port;
2771
2772 if (intel_crtc->active)
2773 return;
2774
2775 intel_crtc->active = true;
2776 intel_update_watermarks(dev);
2777
2778 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2779 temp = I915_READ(PCH_LVDS);
2780 if ((temp & LVDS_PORT_EN) == 0)
2781 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2782 }
2783
2784 is_pch_port = intel_crtc_driving_pch(crtc);
2785
2786 if (is_pch_port)
2787 ironlake_fdi_pll_enable(crtc);
2788 else
2789 ironlake_fdi_disable(crtc);
2790
2791 /* Enable panel fitting for LVDS */
2792 if (dev_priv->pch_pf_size &&
2793 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2794 /* Force use of hard-coded filter coefficients
2795 * as some pre-programmed values are broken,
2796 * e.g. x201.
2797 */
2798 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2799 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2800 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2801 }
2802
2803 /*
2804 * On ILK+ LUT must be loaded before the pipe is running but with
2805 * clocks enabled
2806 */
2807 intel_crtc_load_lut(crtc);
2808
2809 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2810 intel_enable_plane(dev_priv, plane, pipe);
2811
2812 if (is_pch_port)
2813 ironlake_pch_enable(crtc);
2814
2815 mutex_lock(&dev->struct_mutex);
2816 intel_update_fbc(dev);
2817 mutex_unlock(&dev->struct_mutex);
2818
2819 intel_crtc_update_cursor(crtc, true);
2820 }
2821
2822 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2823 {
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 int plane = intel_crtc->plane;
2829 u32 reg, temp;
2830
2831 if (!intel_crtc->active)
2832 return;
2833
2834 intel_crtc_wait_for_pending_flips(crtc);
2835 drm_vblank_off(dev, pipe);
2836 intel_crtc_update_cursor(crtc, false);
2837
2838 intel_disable_plane(dev_priv, plane, pipe);
2839
2840 if (dev_priv->cfb_plane == plane)
2841 intel_disable_fbc(dev);
2842
2843 intel_disable_pipe(dev_priv, pipe);
2844
2845 /* Disable PF */
2846 I915_WRITE(PF_CTL(pipe), 0);
2847 I915_WRITE(PF_WIN_SZ(pipe), 0);
2848
2849 ironlake_fdi_disable(crtc);
2850
2851 /* This is a horrible layering violation; we should be doing this in
2852 * the connector/encoder ->prepare instead, but we don't always have
2853 * enough information there about the config to know whether it will
2854 * actually be necessary or just cause undesired flicker.
2855 */
2856 intel_disable_pch_ports(dev_priv, pipe);
2857
2858 intel_disable_transcoder(dev_priv, pipe);
2859
2860 if (HAS_PCH_CPT(dev)) {
2861 /* disable TRANS_DP_CTL */
2862 reg = TRANS_DP_CTL(pipe);
2863 temp = I915_READ(reg);
2864 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2865 temp |= TRANS_DP_PORT_SEL_NONE;
2866 I915_WRITE(reg, temp);
2867
2868 /* disable DPLL_SEL */
2869 temp = I915_READ(PCH_DPLL_SEL);
2870 switch (pipe) {
2871 case 0:
2872 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2873 break;
2874 case 1:
2875 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2876 break;
2877 case 2:
2878 /* C shares PLL A or B */
2879 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2880 break;
2881 default:
2882 BUG(); /* wtf */
2883 }
2884 I915_WRITE(PCH_DPLL_SEL, temp);
2885 }
2886
2887 /* disable PCH DPLL */
2888 intel_disable_pch_pll(intel_crtc);
2889
2890 /* Switch from PCDclk to Rawclk */
2891 reg = FDI_RX_CTL(pipe);
2892 temp = I915_READ(reg);
2893 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2894
2895 /* Disable CPU FDI TX PLL */
2896 reg = FDI_TX_CTL(pipe);
2897 temp = I915_READ(reg);
2898 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2899
2900 POSTING_READ(reg);
2901 udelay(100);
2902
2903 reg = FDI_RX_CTL(pipe);
2904 temp = I915_READ(reg);
2905 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2906
2907 /* Wait for the clocks to turn off. */
2908 POSTING_READ(reg);
2909 udelay(100);
2910
2911 intel_crtc->active = false;
2912 intel_update_watermarks(dev);
2913
2914 mutex_lock(&dev->struct_mutex);
2915 intel_update_fbc(dev);
2916 mutex_unlock(&dev->struct_mutex);
2917 }
2918
2919 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2920 {
2921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2922 int pipe = intel_crtc->pipe;
2923 int plane = intel_crtc->plane;
2924
2925 /* XXX: When our outputs are all unaware of DPMS modes other than off
2926 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2927 */
2928 switch (mode) {
2929 case DRM_MODE_DPMS_ON:
2930 case DRM_MODE_DPMS_STANDBY:
2931 case DRM_MODE_DPMS_SUSPEND:
2932 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2933 ironlake_crtc_enable(crtc);
2934 break;
2935
2936 case DRM_MODE_DPMS_OFF:
2937 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2938 ironlake_crtc_disable(crtc);
2939 break;
2940 }
2941 }
2942
2943 static void ironlake_crtc_off(struct drm_crtc *crtc)
2944 {
2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946 intel_put_pch_pll(intel_crtc);
2947 }
2948
2949 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2950 {
2951 if (!enable && intel_crtc->overlay) {
2952 struct drm_device *dev = intel_crtc->base.dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954
2955 mutex_lock(&dev->struct_mutex);
2956 dev_priv->mm.interruptible = false;
2957 (void) intel_overlay_switch_off(intel_crtc->overlay);
2958 dev_priv->mm.interruptible = true;
2959 mutex_unlock(&dev->struct_mutex);
2960 }
2961
2962 /* Let userspace switch the overlay on again. In most cases userspace
2963 * has to recompute where to put it anyway.
2964 */
2965 }
2966
2967 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2968 {
2969 struct drm_device *dev = crtc->dev;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972 int pipe = intel_crtc->pipe;
2973 int plane = intel_crtc->plane;
2974
2975 if (intel_crtc->active)
2976 return;
2977
2978 intel_crtc->active = true;
2979 intel_update_watermarks(dev);
2980
2981 intel_enable_pll(dev_priv, pipe);
2982 intel_enable_pipe(dev_priv, pipe, false);
2983 intel_enable_plane(dev_priv, plane, pipe);
2984
2985 intel_crtc_load_lut(crtc);
2986 intel_update_fbc(dev);
2987
2988 /* Give the overlay scaler a chance to enable if it's on this pipe */
2989 intel_crtc_dpms_overlay(intel_crtc, true);
2990 intel_crtc_update_cursor(crtc, true);
2991 }
2992
2993 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2994 {
2995 struct drm_device *dev = crtc->dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998 int pipe = intel_crtc->pipe;
2999 int plane = intel_crtc->plane;
3000
3001 if (!intel_crtc->active)
3002 return;
3003
3004 /* Give the overlay scaler a chance to disable if it's on this pipe */
3005 intel_crtc_wait_for_pending_flips(crtc);
3006 drm_vblank_off(dev, pipe);
3007 intel_crtc_dpms_overlay(intel_crtc, false);
3008 intel_crtc_update_cursor(crtc, false);
3009
3010 if (dev_priv->cfb_plane == plane)
3011 intel_disable_fbc(dev);
3012
3013 intel_disable_plane(dev_priv, plane, pipe);
3014 intel_disable_pipe(dev_priv, pipe);
3015 intel_disable_pll(dev_priv, pipe);
3016
3017 intel_crtc->active = false;
3018 intel_update_fbc(dev);
3019 intel_update_watermarks(dev);
3020 }
3021
3022 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3023 {
3024 /* XXX: When our outputs are all unaware of DPMS modes other than off
3025 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3026 */
3027 switch (mode) {
3028 case DRM_MODE_DPMS_ON:
3029 case DRM_MODE_DPMS_STANDBY:
3030 case DRM_MODE_DPMS_SUSPEND:
3031 i9xx_crtc_enable(crtc);
3032 break;
3033 case DRM_MODE_DPMS_OFF:
3034 i9xx_crtc_disable(crtc);
3035 break;
3036 }
3037 }
3038
3039 static void i9xx_crtc_off(struct drm_crtc *crtc)
3040 {
3041 }
3042
3043 /**
3044 * Sets the power management mode of the pipe and plane.
3045 */
3046 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3047 {
3048 struct drm_device *dev = crtc->dev;
3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050 struct drm_i915_master_private *master_priv;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 int pipe = intel_crtc->pipe;
3053 bool enabled;
3054
3055 if (intel_crtc->dpms_mode == mode)
3056 return;
3057
3058 intel_crtc->dpms_mode = mode;
3059
3060 dev_priv->display.dpms(crtc, mode);
3061
3062 if (!dev->primary->master)
3063 return;
3064
3065 master_priv = dev->primary->master->driver_priv;
3066 if (!master_priv->sarea_priv)
3067 return;
3068
3069 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3070
3071 switch (pipe) {
3072 case 0:
3073 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3074 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3075 break;
3076 case 1:
3077 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3078 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3079 break;
3080 default:
3081 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3082 break;
3083 }
3084 }
3085
3086 static void intel_crtc_disable(struct drm_crtc *crtc)
3087 {
3088 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3089 struct drm_device *dev = crtc->dev;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091
3092 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3093 dev_priv->display.off(crtc);
3094
3095 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3096 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3097
3098 if (crtc->fb) {
3099 mutex_lock(&dev->struct_mutex);
3100 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3101 mutex_unlock(&dev->struct_mutex);
3102 }
3103 }
3104
3105 /* Prepare for a mode set.
3106 *
3107 * Note we could be a lot smarter here. We need to figure out which outputs
3108 * will be enabled, which disabled (in short, how the config will changes)
3109 * and perform the minimum necessary steps to accomplish that, e.g. updating
3110 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3111 * panel fitting is in the proper state, etc.
3112 */
3113 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3114 {
3115 i9xx_crtc_disable(crtc);
3116 }
3117
3118 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3119 {
3120 i9xx_crtc_enable(crtc);
3121 }
3122
3123 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3124 {
3125 ironlake_crtc_disable(crtc);
3126 }
3127
3128 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3129 {
3130 ironlake_crtc_enable(crtc);
3131 }
3132
3133 void intel_encoder_prepare(struct drm_encoder *encoder)
3134 {
3135 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3136 /* lvds has its own version of prepare see intel_lvds_prepare */
3137 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3138 }
3139
3140 void intel_encoder_commit(struct drm_encoder *encoder)
3141 {
3142 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3143 struct drm_device *dev = encoder->dev;
3144 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3145
3146 /* lvds has its own version of commit see intel_lvds_commit */
3147 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3148
3149 if (HAS_PCH_CPT(dev))
3150 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3151 }
3152
3153 void intel_encoder_destroy(struct drm_encoder *encoder)
3154 {
3155 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3156
3157 drm_encoder_cleanup(encoder);
3158 kfree(intel_encoder);
3159 }
3160
3161 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3162 struct drm_display_mode *mode,
3163 struct drm_display_mode *adjusted_mode)
3164 {
3165 struct drm_device *dev = crtc->dev;
3166
3167 if (HAS_PCH_SPLIT(dev)) {
3168 /* FDI link clock is fixed at 2.7G */
3169 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3170 return false;
3171 }
3172
3173 /* All interlaced capable intel hw wants timings in frames. Note though
3174 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3175 * timings, so we need to be careful not to clobber these.*/
3176 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3177 drm_mode_set_crtcinfo(adjusted_mode, 0);
3178
3179 return true;
3180 }
3181
3182 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3183 {
3184 return 400000; /* FIXME */
3185 }
3186
3187 static int i945_get_display_clock_speed(struct drm_device *dev)
3188 {
3189 return 400000;
3190 }
3191
3192 static int i915_get_display_clock_speed(struct drm_device *dev)
3193 {
3194 return 333000;
3195 }
3196
3197 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3198 {
3199 return 200000;
3200 }
3201
3202 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3203 {
3204 u16 gcfgc = 0;
3205
3206 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3207
3208 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3209 return 133000;
3210 else {
3211 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3212 case GC_DISPLAY_CLOCK_333_MHZ:
3213 return 333000;
3214 default:
3215 case GC_DISPLAY_CLOCK_190_200_MHZ:
3216 return 190000;
3217 }
3218 }
3219 }
3220
3221 static int i865_get_display_clock_speed(struct drm_device *dev)
3222 {
3223 return 266000;
3224 }
3225
3226 static int i855_get_display_clock_speed(struct drm_device *dev)
3227 {
3228 u16 hpllcc = 0;
3229 /* Assume that the hardware is in the high speed state. This
3230 * should be the default.
3231 */
3232 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3233 case GC_CLOCK_133_200:
3234 case GC_CLOCK_100_200:
3235 return 200000;
3236 case GC_CLOCK_166_250:
3237 return 250000;
3238 case GC_CLOCK_100_133:
3239 return 133000;
3240 }
3241
3242 /* Shouldn't happen */
3243 return 0;
3244 }
3245
3246 static int i830_get_display_clock_speed(struct drm_device *dev)
3247 {
3248 return 133000;
3249 }
3250
3251 struct fdi_m_n {
3252 u32 tu;
3253 u32 gmch_m;
3254 u32 gmch_n;
3255 u32 link_m;
3256 u32 link_n;
3257 };
3258
3259 static void
3260 fdi_reduce_ratio(u32 *num, u32 *den)
3261 {
3262 while (*num > 0xffffff || *den > 0xffffff) {
3263 *num >>= 1;
3264 *den >>= 1;
3265 }
3266 }
3267
3268 static void
3269 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3270 int link_clock, struct fdi_m_n *m_n)
3271 {
3272 m_n->tu = 64; /* default size */
3273
3274 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3275 m_n->gmch_m = bits_per_pixel * pixel_clock;
3276 m_n->gmch_n = link_clock * nlanes * 8;
3277 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3278
3279 m_n->link_m = pixel_clock;
3280 m_n->link_n = link_clock;
3281 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3282 }
3283
3284 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3285 {
3286 if (i915_panel_use_ssc >= 0)
3287 return i915_panel_use_ssc != 0;
3288 return dev_priv->lvds_use_ssc
3289 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3290 }
3291
3292 /**
3293 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3294 * @crtc: CRTC structure
3295 * @mode: requested mode
3296 *
3297 * A pipe may be connected to one or more outputs. Based on the depth of the
3298 * attached framebuffer, choose a good color depth to use on the pipe.
3299 *
3300 * If possible, match the pipe depth to the fb depth. In some cases, this
3301 * isn't ideal, because the connected output supports a lesser or restricted
3302 * set of depths. Resolve that here:
3303 * LVDS typically supports only 6bpc, so clamp down in that case
3304 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3305 * Displays may support a restricted set as well, check EDID and clamp as
3306 * appropriate.
3307 * DP may want to dither down to 6bpc to fit larger modes
3308 *
3309 * RETURNS:
3310 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3311 * true if they don't match).
3312 */
3313 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3314 unsigned int *pipe_bpp,
3315 struct drm_display_mode *mode)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct drm_encoder *encoder;
3320 struct drm_connector *connector;
3321 unsigned int display_bpc = UINT_MAX, bpc;
3322
3323 /* Walk the encoders & connectors on this crtc, get min bpc */
3324 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3325 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3326
3327 if (encoder->crtc != crtc)
3328 continue;
3329
3330 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3331 unsigned int lvds_bpc;
3332
3333 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3334 LVDS_A3_POWER_UP)
3335 lvds_bpc = 8;
3336 else
3337 lvds_bpc = 6;
3338
3339 if (lvds_bpc < display_bpc) {
3340 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3341 display_bpc = lvds_bpc;
3342 }
3343 continue;
3344 }
3345
3346 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3347 /* Use VBT settings if we have an eDP panel */
3348 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3349
3350 if (edp_bpc < display_bpc) {
3351 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3352 display_bpc = edp_bpc;
3353 }
3354 continue;
3355 }
3356
3357 /* Not one of the known troublemakers, check the EDID */
3358 list_for_each_entry(connector, &dev->mode_config.connector_list,
3359 head) {
3360 if (connector->encoder != encoder)
3361 continue;
3362
3363 /* Don't use an invalid EDID bpc value */
3364 if (connector->display_info.bpc &&
3365 connector->display_info.bpc < display_bpc) {
3366 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3367 display_bpc = connector->display_info.bpc;
3368 }
3369 }
3370
3371 /*
3372 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3373 * through, clamp it down. (Note: >12bpc will be caught below.)
3374 */
3375 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3376 if (display_bpc > 8 && display_bpc < 12) {
3377 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3378 display_bpc = 12;
3379 } else {
3380 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3381 display_bpc = 8;
3382 }
3383 }
3384 }
3385
3386 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3387 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3388 display_bpc = 6;
3389 }
3390
3391 /*
3392 * We could just drive the pipe at the highest bpc all the time and
3393 * enable dithering as needed, but that costs bandwidth. So choose
3394 * the minimum value that expresses the full color range of the fb but
3395 * also stays within the max display bpc discovered above.
3396 */
3397
3398 switch (crtc->fb->depth) {
3399 case 8:
3400 bpc = 8; /* since we go through a colormap */
3401 break;
3402 case 15:
3403 case 16:
3404 bpc = 6; /* min is 18bpp */
3405 break;
3406 case 24:
3407 bpc = 8;
3408 break;
3409 case 30:
3410 bpc = 10;
3411 break;
3412 case 48:
3413 bpc = 12;
3414 break;
3415 default:
3416 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3417 bpc = min((unsigned int)8, display_bpc);
3418 break;
3419 }
3420
3421 display_bpc = min(display_bpc, bpc);
3422
3423 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3424 bpc, display_bpc);
3425
3426 *pipe_bpp = display_bpc * 3;
3427
3428 return display_bpc != bpc;
3429 }
3430
3431 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3432 {
3433 struct drm_device *dev = crtc->dev;
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435 int refclk;
3436
3437 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3438 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3439 refclk = dev_priv->lvds_ssc_freq * 1000;
3440 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3441 refclk / 1000);
3442 } else if (!IS_GEN2(dev)) {
3443 refclk = 96000;
3444 } else {
3445 refclk = 48000;
3446 }
3447
3448 return refclk;
3449 }
3450
3451 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3452 intel_clock_t *clock)
3453 {
3454 /* SDVO TV has fixed PLL values depend on its clock range,
3455 this mirrors vbios setting. */
3456 if (adjusted_mode->clock >= 100000
3457 && adjusted_mode->clock < 140500) {
3458 clock->p1 = 2;
3459 clock->p2 = 10;
3460 clock->n = 3;
3461 clock->m1 = 16;
3462 clock->m2 = 8;
3463 } else if (adjusted_mode->clock >= 140500
3464 && adjusted_mode->clock <= 200000) {
3465 clock->p1 = 1;
3466 clock->p2 = 10;
3467 clock->n = 6;
3468 clock->m1 = 12;
3469 clock->m2 = 8;
3470 }
3471 }
3472
3473 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3474 intel_clock_t *clock,
3475 intel_clock_t *reduced_clock)
3476 {
3477 struct drm_device *dev = crtc->dev;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480 int pipe = intel_crtc->pipe;
3481 u32 fp, fp2 = 0;
3482
3483 if (IS_PINEVIEW(dev)) {
3484 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3485 if (reduced_clock)
3486 fp2 = (1 << reduced_clock->n) << 16 |
3487 reduced_clock->m1 << 8 | reduced_clock->m2;
3488 } else {
3489 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3490 if (reduced_clock)
3491 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3492 reduced_clock->m2;
3493 }
3494
3495 I915_WRITE(FP0(pipe), fp);
3496
3497 intel_crtc->lowfreq_avail = false;
3498 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3499 reduced_clock && i915_powersave) {
3500 I915_WRITE(FP1(pipe), fp2);
3501 intel_crtc->lowfreq_avail = true;
3502 } else {
3503 I915_WRITE(FP1(pipe), fp);
3504 }
3505 }
3506
3507 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3508 struct drm_display_mode *adjusted_mode)
3509 {
3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513 int pipe = intel_crtc->pipe;
3514 u32 temp;
3515
3516 temp = I915_READ(LVDS);
3517 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3518 if (pipe == 1) {
3519 temp |= LVDS_PIPEB_SELECT;
3520 } else {
3521 temp &= ~LVDS_PIPEB_SELECT;
3522 }
3523 /* set the corresponsding LVDS_BORDER bit */
3524 temp |= dev_priv->lvds_border_bits;
3525 /* Set the B0-B3 data pairs corresponding to whether we're going to
3526 * set the DPLLs for dual-channel mode or not.
3527 */
3528 if (clock->p2 == 7)
3529 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3530 else
3531 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3532
3533 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3534 * appropriately here, but we need to look more thoroughly into how
3535 * panels behave in the two modes.
3536 */
3537 /* set the dithering flag on LVDS as needed */
3538 if (INTEL_INFO(dev)->gen >= 4) {
3539 if (dev_priv->lvds_dither)
3540 temp |= LVDS_ENABLE_DITHER;
3541 else
3542 temp &= ~LVDS_ENABLE_DITHER;
3543 }
3544 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3545 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3546 temp |= LVDS_HSYNC_POLARITY;
3547 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3548 temp |= LVDS_VSYNC_POLARITY;
3549 I915_WRITE(LVDS, temp);
3550 }
3551
3552 static void i9xx_update_pll(struct drm_crtc *crtc,
3553 struct drm_display_mode *mode,
3554 struct drm_display_mode *adjusted_mode,
3555 intel_clock_t *clock, intel_clock_t *reduced_clock,
3556 int num_connectors)
3557 {
3558 struct drm_device *dev = crtc->dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561 int pipe = intel_crtc->pipe;
3562 u32 dpll;
3563 bool is_sdvo;
3564
3565 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3566 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3567
3568 dpll = DPLL_VGA_MODE_DIS;
3569
3570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3571 dpll |= DPLLB_MODE_LVDS;
3572 else
3573 dpll |= DPLLB_MODE_DAC_SERIAL;
3574 if (is_sdvo) {
3575 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3576 if (pixel_multiplier > 1) {
3577 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3578 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3579 }
3580 dpll |= DPLL_DVO_HIGH_SPEED;
3581 }
3582 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3583 dpll |= DPLL_DVO_HIGH_SPEED;
3584
3585 /* compute bitmask from p1 value */
3586 if (IS_PINEVIEW(dev))
3587 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3588 else {
3589 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3590 if (IS_G4X(dev) && reduced_clock)
3591 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3592 }
3593 switch (clock->p2) {
3594 case 5:
3595 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3596 break;
3597 case 7:
3598 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3599 break;
3600 case 10:
3601 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3602 break;
3603 case 14:
3604 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3605 break;
3606 }
3607 if (INTEL_INFO(dev)->gen >= 4)
3608 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3609
3610 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3611 dpll |= PLL_REF_INPUT_TVCLKINBC;
3612 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3613 /* XXX: just matching BIOS for now */
3614 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3615 dpll |= 3;
3616 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3617 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3618 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3619 else
3620 dpll |= PLL_REF_INPUT_DREFCLK;
3621
3622 dpll |= DPLL_VCO_ENABLE;
3623 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3624 POSTING_READ(DPLL(pipe));
3625 udelay(150);
3626
3627 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3628 * This is an exception to the general rule that mode_set doesn't turn
3629 * things on.
3630 */
3631 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3632 intel_update_lvds(crtc, clock, adjusted_mode);
3633
3634 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3635 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3636
3637 I915_WRITE(DPLL(pipe), dpll);
3638
3639 /* Wait for the clocks to stabilize. */
3640 POSTING_READ(DPLL(pipe));
3641 udelay(150);
3642
3643 if (INTEL_INFO(dev)->gen >= 4) {
3644 u32 temp = 0;
3645 if (is_sdvo) {
3646 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3647 if (temp > 1)
3648 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3649 else
3650 temp = 0;
3651 }
3652 I915_WRITE(DPLL_MD(pipe), temp);
3653 } else {
3654 /* The pixel multiplier can only be updated once the
3655 * DPLL is enabled and the clocks are stable.
3656 *
3657 * So write it again.
3658 */
3659 I915_WRITE(DPLL(pipe), dpll);
3660 }
3661 }
3662
3663 static void i8xx_update_pll(struct drm_crtc *crtc,
3664 struct drm_display_mode *adjusted_mode,
3665 intel_clock_t *clock,
3666 int num_connectors)
3667 {
3668 struct drm_device *dev = crtc->dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671 int pipe = intel_crtc->pipe;
3672 u32 dpll;
3673
3674 dpll = DPLL_VGA_MODE_DIS;
3675
3676 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3677 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3678 } else {
3679 if (clock->p1 == 2)
3680 dpll |= PLL_P1_DIVIDE_BY_TWO;
3681 else
3682 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3683 if (clock->p2 == 4)
3684 dpll |= PLL_P2_DIVIDE_BY_4;
3685 }
3686
3687 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3688 /* XXX: just matching BIOS for now */
3689 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3690 dpll |= 3;
3691 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3692 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3693 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3694 else
3695 dpll |= PLL_REF_INPUT_DREFCLK;
3696
3697 dpll |= DPLL_VCO_ENABLE;
3698 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3699 POSTING_READ(DPLL(pipe));
3700 udelay(150);
3701
3702 I915_WRITE(DPLL(pipe), dpll);
3703
3704 /* Wait for the clocks to stabilize. */
3705 POSTING_READ(DPLL(pipe));
3706 udelay(150);
3707
3708 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3709 * This is an exception to the general rule that mode_set doesn't turn
3710 * things on.
3711 */
3712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3713 intel_update_lvds(crtc, clock, adjusted_mode);
3714
3715 /* The pixel multiplier can only be updated once the
3716 * DPLL is enabled and the clocks are stable.
3717 *
3718 * So write it again.
3719 */
3720 I915_WRITE(DPLL(pipe), dpll);
3721 }
3722
3723 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3724 struct drm_display_mode *mode,
3725 struct drm_display_mode *adjusted_mode,
3726 int x, int y,
3727 struct drm_framebuffer *old_fb)
3728 {
3729 struct drm_device *dev = crtc->dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3732 int pipe = intel_crtc->pipe;
3733 int plane = intel_crtc->plane;
3734 int refclk, num_connectors = 0;
3735 intel_clock_t clock, reduced_clock;
3736 u32 dspcntr, pipeconf, vsyncshift;
3737 bool ok, has_reduced_clock = false, is_sdvo = false;
3738 bool is_lvds = false, is_tv = false, is_dp = false;
3739 struct drm_mode_config *mode_config = &dev->mode_config;
3740 struct intel_encoder *encoder;
3741 const intel_limit_t *limit;
3742 int ret;
3743
3744 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3745 if (encoder->base.crtc != crtc)
3746 continue;
3747
3748 switch (encoder->type) {
3749 case INTEL_OUTPUT_LVDS:
3750 is_lvds = true;
3751 break;
3752 case INTEL_OUTPUT_SDVO:
3753 case INTEL_OUTPUT_HDMI:
3754 is_sdvo = true;
3755 if (encoder->needs_tv_clock)
3756 is_tv = true;
3757 break;
3758 case INTEL_OUTPUT_TVOUT:
3759 is_tv = true;
3760 break;
3761 case INTEL_OUTPUT_DISPLAYPORT:
3762 is_dp = true;
3763 break;
3764 }
3765
3766 num_connectors++;
3767 }
3768
3769 refclk = i9xx_get_refclk(crtc, num_connectors);
3770
3771 /*
3772 * Returns a set of divisors for the desired target clock with the given
3773 * refclk, or FALSE. The returned values represent the clock equation:
3774 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3775 */
3776 limit = intel_limit(crtc, refclk);
3777 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3778 &clock);
3779 if (!ok) {
3780 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3781 return -EINVAL;
3782 }
3783
3784 /* Ensure that the cursor is valid for the new mode before changing... */
3785 intel_crtc_update_cursor(crtc, true);
3786
3787 if (is_lvds && dev_priv->lvds_downclock_avail) {
3788 /*
3789 * Ensure we match the reduced clock's P to the target clock.
3790 * If the clocks don't match, we can't switch the display clock
3791 * by using the FP0/FP1. In such case we will disable the LVDS
3792 * downclock feature.
3793 */
3794 has_reduced_clock = limit->find_pll(limit, crtc,
3795 dev_priv->lvds_downclock,
3796 refclk,
3797 &clock,
3798 &reduced_clock);
3799 }
3800
3801 if (is_sdvo && is_tv)
3802 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3803
3804 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3805 &reduced_clock : NULL);
3806
3807 if (IS_GEN2(dev))
3808 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3809 else
3810 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3811 has_reduced_clock ? &reduced_clock : NULL,
3812 num_connectors);
3813
3814 /* setup pipeconf */
3815 pipeconf = I915_READ(PIPECONF(pipe));
3816
3817 /* Set up the display plane register */
3818 dspcntr = DISPPLANE_GAMMA_ENABLE;
3819
3820 if (pipe == 0)
3821 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3822 else
3823 dspcntr |= DISPPLANE_SEL_PIPE_B;
3824
3825 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3826 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3827 * core speed.
3828 *
3829 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3830 * pipe == 0 check?
3831 */
3832 if (mode->clock >
3833 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3834 pipeconf |= PIPECONF_DOUBLE_WIDE;
3835 else
3836 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3837 }
3838
3839 /* default to 8bpc */
3840 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3841 if (is_dp) {
3842 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3843 pipeconf |= PIPECONF_BPP_6 |
3844 PIPECONF_DITHER_EN |
3845 PIPECONF_DITHER_TYPE_SP;
3846 }
3847 }
3848
3849 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3850 drm_mode_debug_printmodeline(mode);
3851
3852 if (HAS_PIPE_CXSR(dev)) {
3853 if (intel_crtc->lowfreq_avail) {
3854 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3855 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3856 } else {
3857 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3858 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3859 }
3860 }
3861
3862 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3863 if (!IS_GEN2(dev) &&
3864 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3865 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3866 /* the chip adds 2 halflines automatically */
3867 adjusted_mode->crtc_vtotal -= 1;
3868 adjusted_mode->crtc_vblank_end -= 1;
3869 vsyncshift = adjusted_mode->crtc_hsync_start
3870 - adjusted_mode->crtc_htotal/2;
3871 } else {
3872 pipeconf |= PIPECONF_PROGRESSIVE;
3873 vsyncshift = 0;
3874 }
3875
3876 if (!IS_GEN3(dev))
3877 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3878
3879 I915_WRITE(HTOTAL(pipe),
3880 (adjusted_mode->crtc_hdisplay - 1) |
3881 ((adjusted_mode->crtc_htotal - 1) << 16));
3882 I915_WRITE(HBLANK(pipe),
3883 (adjusted_mode->crtc_hblank_start - 1) |
3884 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3885 I915_WRITE(HSYNC(pipe),
3886 (adjusted_mode->crtc_hsync_start - 1) |
3887 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3888
3889 I915_WRITE(VTOTAL(pipe),
3890 (adjusted_mode->crtc_vdisplay - 1) |
3891 ((adjusted_mode->crtc_vtotal - 1) << 16));
3892 I915_WRITE(VBLANK(pipe),
3893 (adjusted_mode->crtc_vblank_start - 1) |
3894 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3895 I915_WRITE(VSYNC(pipe),
3896 (adjusted_mode->crtc_vsync_start - 1) |
3897 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3898
3899 /* pipesrc and dspsize control the size that is scaled from,
3900 * which should always be the user's requested size.
3901 */
3902 I915_WRITE(DSPSIZE(plane),
3903 ((mode->vdisplay - 1) << 16) |
3904 (mode->hdisplay - 1));
3905 I915_WRITE(DSPPOS(plane), 0);
3906 I915_WRITE(PIPESRC(pipe),
3907 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3908
3909 I915_WRITE(PIPECONF(pipe), pipeconf);
3910 POSTING_READ(PIPECONF(pipe));
3911 intel_enable_pipe(dev_priv, pipe, false);
3912
3913 intel_wait_for_vblank(dev, pipe);
3914
3915 I915_WRITE(DSPCNTR(plane), dspcntr);
3916 POSTING_READ(DSPCNTR(plane));
3917
3918 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3919
3920 intel_update_watermarks(dev);
3921
3922 return ret;
3923 }
3924
3925 /*
3926 * Initialize reference clocks when the driver loads
3927 */
3928 void ironlake_init_pch_refclk(struct drm_device *dev)
3929 {
3930 struct drm_i915_private *dev_priv = dev->dev_private;
3931 struct drm_mode_config *mode_config = &dev->mode_config;
3932 struct intel_encoder *encoder;
3933 u32 temp;
3934 bool has_lvds = false;
3935 bool has_cpu_edp = false;
3936 bool has_pch_edp = false;
3937 bool has_panel = false;
3938 bool has_ck505 = false;
3939 bool can_ssc = false;
3940
3941 /* We need to take the global config into account */
3942 list_for_each_entry(encoder, &mode_config->encoder_list,
3943 base.head) {
3944 switch (encoder->type) {
3945 case INTEL_OUTPUT_LVDS:
3946 has_panel = true;
3947 has_lvds = true;
3948 break;
3949 case INTEL_OUTPUT_EDP:
3950 has_panel = true;
3951 if (intel_encoder_is_pch_edp(&encoder->base))
3952 has_pch_edp = true;
3953 else
3954 has_cpu_edp = true;
3955 break;
3956 }
3957 }
3958
3959 if (HAS_PCH_IBX(dev)) {
3960 has_ck505 = dev_priv->display_clock_mode;
3961 can_ssc = has_ck505;
3962 } else {
3963 has_ck505 = false;
3964 can_ssc = true;
3965 }
3966
3967 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3968 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3969 has_ck505);
3970
3971 /* Ironlake: try to setup display ref clock before DPLL
3972 * enabling. This is only under driver's control after
3973 * PCH B stepping, previous chipset stepping should be
3974 * ignoring this setting.
3975 */
3976 temp = I915_READ(PCH_DREF_CONTROL);
3977 /* Always enable nonspread source */
3978 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3979
3980 if (has_ck505)
3981 temp |= DREF_NONSPREAD_CK505_ENABLE;
3982 else
3983 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3984
3985 if (has_panel) {
3986 temp &= ~DREF_SSC_SOURCE_MASK;
3987 temp |= DREF_SSC_SOURCE_ENABLE;
3988
3989 /* SSC must be turned on before enabling the CPU output */
3990 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3991 DRM_DEBUG_KMS("Using SSC on panel\n");
3992 temp |= DREF_SSC1_ENABLE;
3993 } else
3994 temp &= ~DREF_SSC1_ENABLE;
3995
3996 /* Get SSC going before enabling the outputs */
3997 I915_WRITE(PCH_DREF_CONTROL, temp);
3998 POSTING_READ(PCH_DREF_CONTROL);
3999 udelay(200);
4000
4001 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4002
4003 /* Enable CPU source on CPU attached eDP */
4004 if (has_cpu_edp) {
4005 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4006 DRM_DEBUG_KMS("Using SSC on eDP\n");
4007 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4008 }
4009 else
4010 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4011 } else
4012 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4013
4014 I915_WRITE(PCH_DREF_CONTROL, temp);
4015 POSTING_READ(PCH_DREF_CONTROL);
4016 udelay(200);
4017 } else {
4018 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4019
4020 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4021
4022 /* Turn off CPU output */
4023 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4024
4025 I915_WRITE(PCH_DREF_CONTROL, temp);
4026 POSTING_READ(PCH_DREF_CONTROL);
4027 udelay(200);
4028
4029 /* Turn off the SSC source */
4030 temp &= ~DREF_SSC_SOURCE_MASK;
4031 temp |= DREF_SSC_SOURCE_DISABLE;
4032
4033 /* Turn off SSC1 */
4034 temp &= ~ DREF_SSC1_ENABLE;
4035
4036 I915_WRITE(PCH_DREF_CONTROL, temp);
4037 POSTING_READ(PCH_DREF_CONTROL);
4038 udelay(200);
4039 }
4040 }
4041
4042 static int ironlake_get_refclk(struct drm_crtc *crtc)
4043 {
4044 struct drm_device *dev = crtc->dev;
4045 struct drm_i915_private *dev_priv = dev->dev_private;
4046 struct intel_encoder *encoder;
4047 struct drm_mode_config *mode_config = &dev->mode_config;
4048 struct intel_encoder *edp_encoder = NULL;
4049 int num_connectors = 0;
4050 bool is_lvds = false;
4051
4052 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4053 if (encoder->base.crtc != crtc)
4054 continue;
4055
4056 switch (encoder->type) {
4057 case INTEL_OUTPUT_LVDS:
4058 is_lvds = true;
4059 break;
4060 case INTEL_OUTPUT_EDP:
4061 edp_encoder = encoder;
4062 break;
4063 }
4064 num_connectors++;
4065 }
4066
4067 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4068 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4069 dev_priv->lvds_ssc_freq);
4070 return dev_priv->lvds_ssc_freq * 1000;
4071 }
4072
4073 return 120000;
4074 }
4075
4076 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4077 struct drm_display_mode *mode,
4078 struct drm_display_mode *adjusted_mode,
4079 int x, int y,
4080 struct drm_framebuffer *old_fb)
4081 {
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4085 int pipe = intel_crtc->pipe;
4086 int plane = intel_crtc->plane;
4087 int refclk, num_connectors = 0;
4088 intel_clock_t clock, reduced_clock;
4089 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4090 bool ok, has_reduced_clock = false, is_sdvo = false;
4091 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4092 struct drm_mode_config *mode_config = &dev->mode_config;
4093 struct intel_encoder *encoder, *edp_encoder = NULL;
4094 const intel_limit_t *limit;
4095 int ret;
4096 struct fdi_m_n m_n = {0};
4097 u32 temp;
4098 int target_clock, pixel_multiplier, lane, link_bw, factor;
4099 unsigned int pipe_bpp;
4100 bool dither;
4101 bool is_cpu_edp = false, is_pch_edp = false;
4102
4103 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4104 if (encoder->base.crtc != crtc)
4105 continue;
4106
4107 switch (encoder->type) {
4108 case INTEL_OUTPUT_LVDS:
4109 is_lvds = true;
4110 break;
4111 case INTEL_OUTPUT_SDVO:
4112 case INTEL_OUTPUT_HDMI:
4113 is_sdvo = true;
4114 if (encoder->needs_tv_clock)
4115 is_tv = true;
4116 break;
4117 case INTEL_OUTPUT_TVOUT:
4118 is_tv = true;
4119 break;
4120 case INTEL_OUTPUT_ANALOG:
4121 is_crt = true;
4122 break;
4123 case INTEL_OUTPUT_DISPLAYPORT:
4124 is_dp = true;
4125 break;
4126 case INTEL_OUTPUT_EDP:
4127 is_dp = true;
4128 if (intel_encoder_is_pch_edp(&encoder->base))
4129 is_pch_edp = true;
4130 else
4131 is_cpu_edp = true;
4132 edp_encoder = encoder;
4133 break;
4134 }
4135
4136 num_connectors++;
4137 }
4138
4139 refclk = ironlake_get_refclk(crtc);
4140
4141 /*
4142 * Returns a set of divisors for the desired target clock with the given
4143 * refclk, or FALSE. The returned values represent the clock equation:
4144 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4145 */
4146 limit = intel_limit(crtc, refclk);
4147 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4148 &clock);
4149 if (!ok) {
4150 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4151 return -EINVAL;
4152 }
4153
4154 /* Ensure that the cursor is valid for the new mode before changing... */
4155 intel_crtc_update_cursor(crtc, true);
4156
4157 if (is_lvds && dev_priv->lvds_downclock_avail) {
4158 /*
4159 * Ensure we match the reduced clock's P to the target clock.
4160 * If the clocks don't match, we can't switch the display clock
4161 * by using the FP0/FP1. In such case we will disable the LVDS
4162 * downclock feature.
4163 */
4164 has_reduced_clock = limit->find_pll(limit, crtc,
4165 dev_priv->lvds_downclock,
4166 refclk,
4167 &clock,
4168 &reduced_clock);
4169 }
4170 /* SDVO TV has fixed PLL values depend on its clock range,
4171 this mirrors vbios setting. */
4172 if (is_sdvo && is_tv) {
4173 if (adjusted_mode->clock >= 100000
4174 && adjusted_mode->clock < 140500) {
4175 clock.p1 = 2;
4176 clock.p2 = 10;
4177 clock.n = 3;
4178 clock.m1 = 16;
4179 clock.m2 = 8;
4180 } else if (adjusted_mode->clock >= 140500
4181 && adjusted_mode->clock <= 200000) {
4182 clock.p1 = 1;
4183 clock.p2 = 10;
4184 clock.n = 6;
4185 clock.m1 = 12;
4186 clock.m2 = 8;
4187 }
4188 }
4189
4190 /* FDI link */
4191 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4192 lane = 0;
4193 /* CPU eDP doesn't require FDI link, so just set DP M/N
4194 according to current link config */
4195 if (is_cpu_edp) {
4196 target_clock = mode->clock;
4197 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4198 } else {
4199 /* [e]DP over FDI requires target mode clock
4200 instead of link clock */
4201 if (is_dp)
4202 target_clock = mode->clock;
4203 else
4204 target_clock = adjusted_mode->clock;
4205
4206 /* FDI is a binary signal running at ~2.7GHz, encoding
4207 * each output octet as 10 bits. The actual frequency
4208 * is stored as a divider into a 100MHz clock, and the
4209 * mode pixel clock is stored in units of 1KHz.
4210 * Hence the bw of each lane in terms of the mode signal
4211 * is:
4212 */
4213 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4214 }
4215
4216 /* determine panel color depth */
4217 temp = I915_READ(PIPECONF(pipe));
4218 temp &= ~PIPE_BPC_MASK;
4219 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4220 switch (pipe_bpp) {
4221 case 18:
4222 temp |= PIPE_6BPC;
4223 break;
4224 case 24:
4225 temp |= PIPE_8BPC;
4226 break;
4227 case 30:
4228 temp |= PIPE_10BPC;
4229 break;
4230 case 36:
4231 temp |= PIPE_12BPC;
4232 break;
4233 default:
4234 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4235 pipe_bpp);
4236 temp |= PIPE_8BPC;
4237 pipe_bpp = 24;
4238 break;
4239 }
4240
4241 intel_crtc->bpp = pipe_bpp;
4242 I915_WRITE(PIPECONF(pipe), temp);
4243
4244 if (!lane) {
4245 /*
4246 * Account for spread spectrum to avoid
4247 * oversubscribing the link. Max center spread
4248 * is 2.5%; use 5% for safety's sake.
4249 */
4250 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4251 lane = bps / (link_bw * 8) + 1;
4252 }
4253
4254 intel_crtc->fdi_lanes = lane;
4255
4256 if (pixel_multiplier > 1)
4257 link_bw *= pixel_multiplier;
4258 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4259 &m_n);
4260
4261 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4262 if (has_reduced_clock)
4263 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4264 reduced_clock.m2;
4265
4266 /* Enable autotuning of the PLL clock (if permissible) */
4267 factor = 21;
4268 if (is_lvds) {
4269 if ((intel_panel_use_ssc(dev_priv) &&
4270 dev_priv->lvds_ssc_freq == 100) ||
4271 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4272 factor = 25;
4273 } else if (is_sdvo && is_tv)
4274 factor = 20;
4275
4276 if (clock.m < factor * clock.n)
4277 fp |= FP_CB_TUNE;
4278
4279 dpll = 0;
4280
4281 if (is_lvds)
4282 dpll |= DPLLB_MODE_LVDS;
4283 else
4284 dpll |= DPLLB_MODE_DAC_SERIAL;
4285 if (is_sdvo) {
4286 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4287 if (pixel_multiplier > 1) {
4288 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4289 }
4290 dpll |= DPLL_DVO_HIGH_SPEED;
4291 }
4292 if (is_dp && !is_cpu_edp)
4293 dpll |= DPLL_DVO_HIGH_SPEED;
4294
4295 /* compute bitmask from p1 value */
4296 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4297 /* also FPA1 */
4298 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4299
4300 switch (clock.p2) {
4301 case 5:
4302 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4303 break;
4304 case 7:
4305 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4306 break;
4307 case 10:
4308 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4309 break;
4310 case 14:
4311 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4312 break;
4313 }
4314
4315 if (is_sdvo && is_tv)
4316 dpll |= PLL_REF_INPUT_TVCLKINBC;
4317 else if (is_tv)
4318 /* XXX: just matching BIOS for now */
4319 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4320 dpll |= 3;
4321 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4322 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4323 else
4324 dpll |= PLL_REF_INPUT_DREFCLK;
4325
4326 /* setup pipeconf */
4327 pipeconf = I915_READ(PIPECONF(pipe));
4328
4329 /* Set up the display plane register */
4330 dspcntr = DISPPLANE_GAMMA_ENABLE;
4331
4332 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4333 drm_mode_debug_printmodeline(mode);
4334
4335 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4336 if (!is_cpu_edp) {
4337 struct intel_pch_pll *pll;
4338
4339 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4340 if (pll == NULL) {
4341 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4342 pipe);
4343 return -EINVAL;
4344 }
4345 } else
4346 intel_put_pch_pll(intel_crtc);
4347
4348 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4349 * This is an exception to the general rule that mode_set doesn't turn
4350 * things on.
4351 */
4352 if (is_lvds) {
4353 temp = I915_READ(PCH_LVDS);
4354 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4355 if (HAS_PCH_CPT(dev)) {
4356 temp &= ~PORT_TRANS_SEL_MASK;
4357 temp |= PORT_TRANS_SEL_CPT(pipe);
4358 } else {
4359 if (pipe == 1)
4360 temp |= LVDS_PIPEB_SELECT;
4361 else
4362 temp &= ~LVDS_PIPEB_SELECT;
4363 }
4364
4365 /* set the corresponsding LVDS_BORDER bit */
4366 temp |= dev_priv->lvds_border_bits;
4367 /* Set the B0-B3 data pairs corresponding to whether we're going to
4368 * set the DPLLs for dual-channel mode or not.
4369 */
4370 if (clock.p2 == 7)
4371 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4372 else
4373 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4374
4375 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4376 * appropriately here, but we need to look more thoroughly into how
4377 * panels behave in the two modes.
4378 */
4379 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4380 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4381 temp |= LVDS_HSYNC_POLARITY;
4382 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4383 temp |= LVDS_VSYNC_POLARITY;
4384 I915_WRITE(PCH_LVDS, temp);
4385 }
4386
4387 pipeconf &= ~PIPECONF_DITHER_EN;
4388 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4389 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4390 pipeconf |= PIPECONF_DITHER_EN;
4391 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4392 }
4393 if (is_dp && !is_cpu_edp) {
4394 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4395 } else {
4396 /* For non-DP output, clear any trans DP clock recovery setting.*/
4397 I915_WRITE(TRANSDATA_M1(pipe), 0);
4398 I915_WRITE(TRANSDATA_N1(pipe), 0);
4399 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4400 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4401 }
4402
4403 if (intel_crtc->pch_pll) {
4404 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4405
4406 /* Wait for the clocks to stabilize. */
4407 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4408 udelay(150);
4409
4410 /* The pixel multiplier can only be updated once the
4411 * DPLL is enabled and the clocks are stable.
4412 *
4413 * So write it again.
4414 */
4415 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4416 }
4417
4418 intel_crtc->lowfreq_avail = false;
4419 if (intel_crtc->pch_pll) {
4420 if (is_lvds && has_reduced_clock && i915_powersave) {
4421 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4422 intel_crtc->lowfreq_avail = true;
4423 if (HAS_PIPE_CXSR(dev)) {
4424 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4425 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4426 }
4427 } else {
4428 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4429 if (HAS_PIPE_CXSR(dev)) {
4430 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4431 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4432 }
4433 }
4434 }
4435
4436 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4437 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4438 pipeconf |= PIPECONF_INTERLACED_ILK;
4439 /* the chip adds 2 halflines automatically */
4440 adjusted_mode->crtc_vtotal -= 1;
4441 adjusted_mode->crtc_vblank_end -= 1;
4442 I915_WRITE(VSYNCSHIFT(pipe),
4443 adjusted_mode->crtc_hsync_start
4444 - adjusted_mode->crtc_htotal/2);
4445 } else {
4446 pipeconf |= PIPECONF_PROGRESSIVE;
4447 I915_WRITE(VSYNCSHIFT(pipe), 0);
4448 }
4449
4450 I915_WRITE(HTOTAL(pipe),
4451 (adjusted_mode->crtc_hdisplay - 1) |
4452 ((adjusted_mode->crtc_htotal - 1) << 16));
4453 I915_WRITE(HBLANK(pipe),
4454 (adjusted_mode->crtc_hblank_start - 1) |
4455 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4456 I915_WRITE(HSYNC(pipe),
4457 (adjusted_mode->crtc_hsync_start - 1) |
4458 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4459
4460 I915_WRITE(VTOTAL(pipe),
4461 (adjusted_mode->crtc_vdisplay - 1) |
4462 ((adjusted_mode->crtc_vtotal - 1) << 16));
4463 I915_WRITE(VBLANK(pipe),
4464 (adjusted_mode->crtc_vblank_start - 1) |
4465 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4466 I915_WRITE(VSYNC(pipe),
4467 (adjusted_mode->crtc_vsync_start - 1) |
4468 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4469
4470 /* pipesrc controls the size that is scaled from, which should
4471 * always be the user's requested size.
4472 */
4473 I915_WRITE(PIPESRC(pipe),
4474 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4475
4476 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4477 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4478 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4479 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4480
4481 if (is_cpu_edp)
4482 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4483
4484 I915_WRITE(PIPECONF(pipe), pipeconf);
4485 POSTING_READ(PIPECONF(pipe));
4486
4487 intel_wait_for_vblank(dev, pipe);
4488
4489 I915_WRITE(DSPCNTR(plane), dspcntr);
4490 POSTING_READ(DSPCNTR(plane));
4491
4492 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4493
4494 intel_update_watermarks(dev);
4495
4496 return ret;
4497 }
4498
4499 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4500 struct drm_display_mode *mode,
4501 struct drm_display_mode *adjusted_mode,
4502 int x, int y,
4503 struct drm_framebuffer *old_fb)
4504 {
4505 struct drm_device *dev = crtc->dev;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4508 int pipe = intel_crtc->pipe;
4509 int ret;
4510
4511 drm_vblank_pre_modeset(dev, pipe);
4512
4513 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4514 x, y, old_fb);
4515 drm_vblank_post_modeset(dev, pipe);
4516
4517 if (ret)
4518 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4519 else
4520 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4521
4522 return ret;
4523 }
4524
4525 static bool intel_eld_uptodate(struct drm_connector *connector,
4526 int reg_eldv, uint32_t bits_eldv,
4527 int reg_elda, uint32_t bits_elda,
4528 int reg_edid)
4529 {
4530 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4531 uint8_t *eld = connector->eld;
4532 uint32_t i;
4533
4534 i = I915_READ(reg_eldv);
4535 i &= bits_eldv;
4536
4537 if (!eld[0])
4538 return !i;
4539
4540 if (!i)
4541 return false;
4542
4543 i = I915_READ(reg_elda);
4544 i &= ~bits_elda;
4545 I915_WRITE(reg_elda, i);
4546
4547 for (i = 0; i < eld[2]; i++)
4548 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4549 return false;
4550
4551 return true;
4552 }
4553
4554 static void g4x_write_eld(struct drm_connector *connector,
4555 struct drm_crtc *crtc)
4556 {
4557 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4558 uint8_t *eld = connector->eld;
4559 uint32_t eldv;
4560 uint32_t len;
4561 uint32_t i;
4562
4563 i = I915_READ(G4X_AUD_VID_DID);
4564
4565 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4566 eldv = G4X_ELDV_DEVCL_DEVBLC;
4567 else
4568 eldv = G4X_ELDV_DEVCTG;
4569
4570 if (intel_eld_uptodate(connector,
4571 G4X_AUD_CNTL_ST, eldv,
4572 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4573 G4X_HDMIW_HDMIEDID))
4574 return;
4575
4576 i = I915_READ(G4X_AUD_CNTL_ST);
4577 i &= ~(eldv | G4X_ELD_ADDR);
4578 len = (i >> 9) & 0x1f; /* ELD buffer size */
4579 I915_WRITE(G4X_AUD_CNTL_ST, i);
4580
4581 if (!eld[0])
4582 return;
4583
4584 len = min_t(uint8_t, eld[2], len);
4585 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4586 for (i = 0; i < len; i++)
4587 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4588
4589 i = I915_READ(G4X_AUD_CNTL_ST);
4590 i |= eldv;
4591 I915_WRITE(G4X_AUD_CNTL_ST, i);
4592 }
4593
4594 static void ironlake_write_eld(struct drm_connector *connector,
4595 struct drm_crtc *crtc)
4596 {
4597 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4598 uint8_t *eld = connector->eld;
4599 uint32_t eldv;
4600 uint32_t i;
4601 int len;
4602 int hdmiw_hdmiedid;
4603 int aud_config;
4604 int aud_cntl_st;
4605 int aud_cntrl_st2;
4606
4607 if (HAS_PCH_IBX(connector->dev)) {
4608 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4609 aud_config = IBX_AUD_CONFIG_A;
4610 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4611 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4612 } else {
4613 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4614 aud_config = CPT_AUD_CONFIG_A;
4615 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4616 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4617 }
4618
4619 i = to_intel_crtc(crtc)->pipe;
4620 hdmiw_hdmiedid += i * 0x100;
4621 aud_cntl_st += i * 0x100;
4622 aud_config += i * 0x100;
4623
4624 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4625
4626 i = I915_READ(aud_cntl_st);
4627 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4628 if (!i) {
4629 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4630 /* operate blindly on all ports */
4631 eldv = IBX_ELD_VALIDB;
4632 eldv |= IBX_ELD_VALIDB << 4;
4633 eldv |= IBX_ELD_VALIDB << 8;
4634 } else {
4635 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4636 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4637 }
4638
4639 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4640 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4641 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4642 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4643 } else
4644 I915_WRITE(aud_config, 0);
4645
4646 if (intel_eld_uptodate(connector,
4647 aud_cntrl_st2, eldv,
4648 aud_cntl_st, IBX_ELD_ADDRESS,
4649 hdmiw_hdmiedid))
4650 return;
4651
4652 i = I915_READ(aud_cntrl_st2);
4653 i &= ~eldv;
4654 I915_WRITE(aud_cntrl_st2, i);
4655
4656 if (!eld[0])
4657 return;
4658
4659 i = I915_READ(aud_cntl_st);
4660 i &= ~IBX_ELD_ADDRESS;
4661 I915_WRITE(aud_cntl_st, i);
4662
4663 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4664 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4665 for (i = 0; i < len; i++)
4666 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4667
4668 i = I915_READ(aud_cntrl_st2);
4669 i |= eldv;
4670 I915_WRITE(aud_cntrl_st2, i);
4671 }
4672
4673 void intel_write_eld(struct drm_encoder *encoder,
4674 struct drm_display_mode *mode)
4675 {
4676 struct drm_crtc *crtc = encoder->crtc;
4677 struct drm_connector *connector;
4678 struct drm_device *dev = encoder->dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680
4681 connector = drm_select_eld(encoder, mode);
4682 if (!connector)
4683 return;
4684
4685 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4686 connector->base.id,
4687 drm_get_connector_name(connector),
4688 connector->encoder->base.id,
4689 drm_get_encoder_name(connector->encoder));
4690
4691 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4692
4693 if (dev_priv->display.write_eld)
4694 dev_priv->display.write_eld(connector, crtc);
4695 }
4696
4697 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4698 void intel_crtc_load_lut(struct drm_crtc *crtc)
4699 {
4700 struct drm_device *dev = crtc->dev;
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703 int palreg = PALETTE(intel_crtc->pipe);
4704 int i;
4705
4706 /* The clocks have to be on to load the palette. */
4707 if (!crtc->enabled || !intel_crtc->active)
4708 return;
4709
4710 /* use legacy palette for Ironlake */
4711 if (HAS_PCH_SPLIT(dev))
4712 palreg = LGC_PALETTE(intel_crtc->pipe);
4713
4714 for (i = 0; i < 256; i++) {
4715 I915_WRITE(palreg + 4 * i,
4716 (intel_crtc->lut_r[i] << 16) |
4717 (intel_crtc->lut_g[i] << 8) |
4718 intel_crtc->lut_b[i]);
4719 }
4720 }
4721
4722 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4723 {
4724 struct drm_device *dev = crtc->dev;
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4727 bool visible = base != 0;
4728 u32 cntl;
4729
4730 if (intel_crtc->cursor_visible == visible)
4731 return;
4732
4733 cntl = I915_READ(_CURACNTR);
4734 if (visible) {
4735 /* On these chipsets we can only modify the base whilst
4736 * the cursor is disabled.
4737 */
4738 I915_WRITE(_CURABASE, base);
4739
4740 cntl &= ~(CURSOR_FORMAT_MASK);
4741 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4742 cntl |= CURSOR_ENABLE |
4743 CURSOR_GAMMA_ENABLE |
4744 CURSOR_FORMAT_ARGB;
4745 } else
4746 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4747 I915_WRITE(_CURACNTR, cntl);
4748
4749 intel_crtc->cursor_visible = visible;
4750 }
4751
4752 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4753 {
4754 struct drm_device *dev = crtc->dev;
4755 struct drm_i915_private *dev_priv = dev->dev_private;
4756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4757 int pipe = intel_crtc->pipe;
4758 bool visible = base != 0;
4759
4760 if (intel_crtc->cursor_visible != visible) {
4761 uint32_t cntl = I915_READ(CURCNTR(pipe));
4762 if (base) {
4763 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4764 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4765 cntl |= pipe << 28; /* Connect to correct pipe */
4766 } else {
4767 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4768 cntl |= CURSOR_MODE_DISABLE;
4769 }
4770 I915_WRITE(CURCNTR(pipe), cntl);
4771
4772 intel_crtc->cursor_visible = visible;
4773 }
4774 /* and commit changes on next vblank */
4775 I915_WRITE(CURBASE(pipe), base);
4776 }
4777
4778 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4779 {
4780 struct drm_device *dev = crtc->dev;
4781 struct drm_i915_private *dev_priv = dev->dev_private;
4782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4783 int pipe = intel_crtc->pipe;
4784 bool visible = base != 0;
4785
4786 if (intel_crtc->cursor_visible != visible) {
4787 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4788 if (base) {
4789 cntl &= ~CURSOR_MODE;
4790 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4791 } else {
4792 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4793 cntl |= CURSOR_MODE_DISABLE;
4794 }
4795 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4796
4797 intel_crtc->cursor_visible = visible;
4798 }
4799 /* and commit changes on next vblank */
4800 I915_WRITE(CURBASE_IVB(pipe), base);
4801 }
4802
4803 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4804 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4805 bool on)
4806 {
4807 struct drm_device *dev = crtc->dev;
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4810 int pipe = intel_crtc->pipe;
4811 int x = intel_crtc->cursor_x;
4812 int y = intel_crtc->cursor_y;
4813 u32 base, pos;
4814 bool visible;
4815
4816 pos = 0;
4817
4818 if (on && crtc->enabled && crtc->fb) {
4819 base = intel_crtc->cursor_addr;
4820 if (x > (int) crtc->fb->width)
4821 base = 0;
4822
4823 if (y > (int) crtc->fb->height)
4824 base = 0;
4825 } else
4826 base = 0;
4827
4828 if (x < 0) {
4829 if (x + intel_crtc->cursor_width < 0)
4830 base = 0;
4831
4832 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4833 x = -x;
4834 }
4835 pos |= x << CURSOR_X_SHIFT;
4836
4837 if (y < 0) {
4838 if (y + intel_crtc->cursor_height < 0)
4839 base = 0;
4840
4841 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4842 y = -y;
4843 }
4844 pos |= y << CURSOR_Y_SHIFT;
4845
4846 visible = base != 0;
4847 if (!visible && !intel_crtc->cursor_visible)
4848 return;
4849
4850 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4851 I915_WRITE(CURPOS_IVB(pipe), pos);
4852 ivb_update_cursor(crtc, base);
4853 } else {
4854 I915_WRITE(CURPOS(pipe), pos);
4855 if (IS_845G(dev) || IS_I865G(dev))
4856 i845_update_cursor(crtc, base);
4857 else
4858 i9xx_update_cursor(crtc, base);
4859 }
4860 }
4861
4862 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4863 struct drm_file *file,
4864 uint32_t handle,
4865 uint32_t width, uint32_t height)
4866 {
4867 struct drm_device *dev = crtc->dev;
4868 struct drm_i915_private *dev_priv = dev->dev_private;
4869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4870 struct drm_i915_gem_object *obj;
4871 uint32_t addr;
4872 int ret;
4873
4874 DRM_DEBUG_KMS("\n");
4875
4876 /* if we want to turn off the cursor ignore width and height */
4877 if (!handle) {
4878 DRM_DEBUG_KMS("cursor off\n");
4879 addr = 0;
4880 obj = NULL;
4881 mutex_lock(&dev->struct_mutex);
4882 goto finish;
4883 }
4884
4885 /* Currently we only support 64x64 cursors */
4886 if (width != 64 || height != 64) {
4887 DRM_ERROR("we currently only support 64x64 cursors\n");
4888 return -EINVAL;
4889 }
4890
4891 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4892 if (&obj->base == NULL)
4893 return -ENOENT;
4894
4895 if (obj->base.size < width * height * 4) {
4896 DRM_ERROR("buffer is to small\n");
4897 ret = -ENOMEM;
4898 goto fail;
4899 }
4900
4901 /* we only need to pin inside GTT if cursor is non-phy */
4902 mutex_lock(&dev->struct_mutex);
4903 if (!dev_priv->info->cursor_needs_physical) {
4904 if (obj->tiling_mode) {
4905 DRM_ERROR("cursor cannot be tiled\n");
4906 ret = -EINVAL;
4907 goto fail_locked;
4908 }
4909
4910 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4911 if (ret) {
4912 DRM_ERROR("failed to move cursor bo into the GTT\n");
4913 goto fail_locked;
4914 }
4915
4916 ret = i915_gem_object_put_fence(obj);
4917 if (ret) {
4918 DRM_ERROR("failed to release fence for cursor");
4919 goto fail_unpin;
4920 }
4921
4922 addr = obj->gtt_offset;
4923 } else {
4924 int align = IS_I830(dev) ? 16 * 1024 : 256;
4925 ret = i915_gem_attach_phys_object(dev, obj,
4926 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4927 align);
4928 if (ret) {
4929 DRM_ERROR("failed to attach phys object\n");
4930 goto fail_locked;
4931 }
4932 addr = obj->phys_obj->handle->busaddr;
4933 }
4934
4935 if (IS_GEN2(dev))
4936 I915_WRITE(CURSIZE, (height << 12) | width);
4937
4938 finish:
4939 if (intel_crtc->cursor_bo) {
4940 if (dev_priv->info->cursor_needs_physical) {
4941 if (intel_crtc->cursor_bo != obj)
4942 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4943 } else
4944 i915_gem_object_unpin(intel_crtc->cursor_bo);
4945 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4946 }
4947
4948 mutex_unlock(&dev->struct_mutex);
4949
4950 intel_crtc->cursor_addr = addr;
4951 intel_crtc->cursor_bo = obj;
4952 intel_crtc->cursor_width = width;
4953 intel_crtc->cursor_height = height;
4954
4955 intel_crtc_update_cursor(crtc, true);
4956
4957 return 0;
4958 fail_unpin:
4959 i915_gem_object_unpin(obj);
4960 fail_locked:
4961 mutex_unlock(&dev->struct_mutex);
4962 fail:
4963 drm_gem_object_unreference_unlocked(&obj->base);
4964 return ret;
4965 }
4966
4967 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4968 {
4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970
4971 intel_crtc->cursor_x = x;
4972 intel_crtc->cursor_y = y;
4973
4974 intel_crtc_update_cursor(crtc, true);
4975
4976 return 0;
4977 }
4978
4979 /** Sets the color ramps on behalf of RandR */
4980 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4981 u16 blue, int regno)
4982 {
4983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4984
4985 intel_crtc->lut_r[regno] = red >> 8;
4986 intel_crtc->lut_g[regno] = green >> 8;
4987 intel_crtc->lut_b[regno] = blue >> 8;
4988 }
4989
4990 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4991 u16 *blue, int regno)
4992 {
4993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4994
4995 *red = intel_crtc->lut_r[regno] << 8;
4996 *green = intel_crtc->lut_g[regno] << 8;
4997 *blue = intel_crtc->lut_b[regno] << 8;
4998 }
4999
5000 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5001 u16 *blue, uint32_t start, uint32_t size)
5002 {
5003 int end = (start + size > 256) ? 256 : start + size, i;
5004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005
5006 for (i = start; i < end; i++) {
5007 intel_crtc->lut_r[i] = red[i] >> 8;
5008 intel_crtc->lut_g[i] = green[i] >> 8;
5009 intel_crtc->lut_b[i] = blue[i] >> 8;
5010 }
5011
5012 intel_crtc_load_lut(crtc);
5013 }
5014
5015 /**
5016 * Get a pipe with a simple mode set on it for doing load-based monitor
5017 * detection.
5018 *
5019 * It will be up to the load-detect code to adjust the pipe as appropriate for
5020 * its requirements. The pipe will be connected to no other encoders.
5021 *
5022 * Currently this code will only succeed if there is a pipe with no encoders
5023 * configured for it. In the future, it could choose to temporarily disable
5024 * some outputs to free up a pipe for its use.
5025 *
5026 * \return crtc, or NULL if no pipes are available.
5027 */
5028
5029 /* VESA 640x480x72Hz mode to set on the pipe */
5030 static struct drm_display_mode load_detect_mode = {
5031 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5032 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5033 };
5034
5035 static struct drm_framebuffer *
5036 intel_framebuffer_create(struct drm_device *dev,
5037 struct drm_mode_fb_cmd2 *mode_cmd,
5038 struct drm_i915_gem_object *obj)
5039 {
5040 struct intel_framebuffer *intel_fb;
5041 int ret;
5042
5043 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5044 if (!intel_fb) {
5045 drm_gem_object_unreference_unlocked(&obj->base);
5046 return ERR_PTR(-ENOMEM);
5047 }
5048
5049 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5050 if (ret) {
5051 drm_gem_object_unreference_unlocked(&obj->base);
5052 kfree(intel_fb);
5053 return ERR_PTR(ret);
5054 }
5055
5056 return &intel_fb->base;
5057 }
5058
5059 static u32
5060 intel_framebuffer_pitch_for_width(int width, int bpp)
5061 {
5062 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5063 return ALIGN(pitch, 64);
5064 }
5065
5066 static u32
5067 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5068 {
5069 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5070 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5071 }
5072
5073 static struct drm_framebuffer *
5074 intel_framebuffer_create_for_mode(struct drm_device *dev,
5075 struct drm_display_mode *mode,
5076 int depth, int bpp)
5077 {
5078 struct drm_i915_gem_object *obj;
5079 struct drm_mode_fb_cmd2 mode_cmd;
5080
5081 obj = i915_gem_alloc_object(dev,
5082 intel_framebuffer_size_for_mode(mode, bpp));
5083 if (obj == NULL)
5084 return ERR_PTR(-ENOMEM);
5085
5086 mode_cmd.width = mode->hdisplay;
5087 mode_cmd.height = mode->vdisplay;
5088 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5089 bpp);
5090 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5091
5092 return intel_framebuffer_create(dev, &mode_cmd, obj);
5093 }
5094
5095 static struct drm_framebuffer *
5096 mode_fits_in_fbdev(struct drm_device *dev,
5097 struct drm_display_mode *mode)
5098 {
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 struct drm_i915_gem_object *obj;
5101 struct drm_framebuffer *fb;
5102
5103 if (dev_priv->fbdev == NULL)
5104 return NULL;
5105
5106 obj = dev_priv->fbdev->ifb.obj;
5107 if (obj == NULL)
5108 return NULL;
5109
5110 fb = &dev_priv->fbdev->ifb.base;
5111 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5112 fb->bits_per_pixel))
5113 return NULL;
5114
5115 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5116 return NULL;
5117
5118 return fb;
5119 }
5120
5121 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5122 struct drm_connector *connector,
5123 struct drm_display_mode *mode,
5124 struct intel_load_detect_pipe *old)
5125 {
5126 struct intel_crtc *intel_crtc;
5127 struct drm_crtc *possible_crtc;
5128 struct drm_encoder *encoder = &intel_encoder->base;
5129 struct drm_crtc *crtc = NULL;
5130 struct drm_device *dev = encoder->dev;
5131 struct drm_framebuffer *old_fb;
5132 int i = -1;
5133
5134 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5135 connector->base.id, drm_get_connector_name(connector),
5136 encoder->base.id, drm_get_encoder_name(encoder));
5137
5138 /*
5139 * Algorithm gets a little messy:
5140 *
5141 * - if the connector already has an assigned crtc, use it (but make
5142 * sure it's on first)
5143 *
5144 * - try to find the first unused crtc that can drive this connector,
5145 * and use that if we find one
5146 */
5147
5148 /* See if we already have a CRTC for this connector */
5149 if (encoder->crtc) {
5150 crtc = encoder->crtc;
5151
5152 intel_crtc = to_intel_crtc(crtc);
5153 old->dpms_mode = intel_crtc->dpms_mode;
5154 old->load_detect_temp = false;
5155
5156 /* Make sure the crtc and connector are running */
5157 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5158 struct drm_encoder_helper_funcs *encoder_funcs;
5159 struct drm_crtc_helper_funcs *crtc_funcs;
5160
5161 crtc_funcs = crtc->helper_private;
5162 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5163
5164 encoder_funcs = encoder->helper_private;
5165 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5166 }
5167
5168 return true;
5169 }
5170
5171 /* Find an unused one (if possible) */
5172 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5173 i++;
5174 if (!(encoder->possible_crtcs & (1 << i)))
5175 continue;
5176 if (!possible_crtc->enabled) {
5177 crtc = possible_crtc;
5178 break;
5179 }
5180 }
5181
5182 /*
5183 * If we didn't find an unused CRTC, don't use any.
5184 */
5185 if (!crtc) {
5186 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5187 return false;
5188 }
5189
5190 encoder->crtc = crtc;
5191 connector->encoder = encoder;
5192
5193 intel_crtc = to_intel_crtc(crtc);
5194 old->dpms_mode = intel_crtc->dpms_mode;
5195 old->load_detect_temp = true;
5196 old->release_fb = NULL;
5197
5198 if (!mode)
5199 mode = &load_detect_mode;
5200
5201 old_fb = crtc->fb;
5202
5203 /* We need a framebuffer large enough to accommodate all accesses
5204 * that the plane may generate whilst we perform load detection.
5205 * We can not rely on the fbcon either being present (we get called
5206 * during its initialisation to detect all boot displays, or it may
5207 * not even exist) or that it is large enough to satisfy the
5208 * requested mode.
5209 */
5210 crtc->fb = mode_fits_in_fbdev(dev, mode);
5211 if (crtc->fb == NULL) {
5212 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5213 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5214 old->release_fb = crtc->fb;
5215 } else
5216 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5217 if (IS_ERR(crtc->fb)) {
5218 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5219 crtc->fb = old_fb;
5220 return false;
5221 }
5222
5223 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5224 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5225 if (old->release_fb)
5226 old->release_fb->funcs->destroy(old->release_fb);
5227 crtc->fb = old_fb;
5228 return false;
5229 }
5230
5231 /* let the connector get through one full cycle before testing */
5232 intel_wait_for_vblank(dev, intel_crtc->pipe);
5233
5234 return true;
5235 }
5236
5237 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5238 struct drm_connector *connector,
5239 struct intel_load_detect_pipe *old)
5240 {
5241 struct drm_encoder *encoder = &intel_encoder->base;
5242 struct drm_device *dev = encoder->dev;
5243 struct drm_crtc *crtc = encoder->crtc;
5244 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5245 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5246
5247 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5248 connector->base.id, drm_get_connector_name(connector),
5249 encoder->base.id, drm_get_encoder_name(encoder));
5250
5251 if (old->load_detect_temp) {
5252 connector->encoder = NULL;
5253 drm_helper_disable_unused_functions(dev);
5254
5255 if (old->release_fb)
5256 old->release_fb->funcs->destroy(old->release_fb);
5257
5258 return;
5259 }
5260
5261 /* Switch crtc and encoder back off if necessary */
5262 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5263 encoder_funcs->dpms(encoder, old->dpms_mode);
5264 crtc_funcs->dpms(crtc, old->dpms_mode);
5265 }
5266 }
5267
5268 /* Returns the clock of the currently programmed mode of the given pipe. */
5269 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5270 {
5271 struct drm_i915_private *dev_priv = dev->dev_private;
5272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5273 int pipe = intel_crtc->pipe;
5274 u32 dpll = I915_READ(DPLL(pipe));
5275 u32 fp;
5276 intel_clock_t clock;
5277
5278 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5279 fp = I915_READ(FP0(pipe));
5280 else
5281 fp = I915_READ(FP1(pipe));
5282
5283 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5284 if (IS_PINEVIEW(dev)) {
5285 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5286 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5287 } else {
5288 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5289 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5290 }
5291
5292 if (!IS_GEN2(dev)) {
5293 if (IS_PINEVIEW(dev))
5294 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5295 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5296 else
5297 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5298 DPLL_FPA01_P1_POST_DIV_SHIFT);
5299
5300 switch (dpll & DPLL_MODE_MASK) {
5301 case DPLLB_MODE_DAC_SERIAL:
5302 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5303 5 : 10;
5304 break;
5305 case DPLLB_MODE_LVDS:
5306 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5307 7 : 14;
5308 break;
5309 default:
5310 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5311 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5312 return 0;
5313 }
5314
5315 /* XXX: Handle the 100Mhz refclk */
5316 intel_clock(dev, 96000, &clock);
5317 } else {
5318 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5319
5320 if (is_lvds) {
5321 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5322 DPLL_FPA01_P1_POST_DIV_SHIFT);
5323 clock.p2 = 14;
5324
5325 if ((dpll & PLL_REF_INPUT_MASK) ==
5326 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5327 /* XXX: might not be 66MHz */
5328 intel_clock(dev, 66000, &clock);
5329 } else
5330 intel_clock(dev, 48000, &clock);
5331 } else {
5332 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5333 clock.p1 = 2;
5334 else {
5335 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5336 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5337 }
5338 if (dpll & PLL_P2_DIVIDE_BY_4)
5339 clock.p2 = 4;
5340 else
5341 clock.p2 = 2;
5342
5343 intel_clock(dev, 48000, &clock);
5344 }
5345 }
5346
5347 /* XXX: It would be nice to validate the clocks, but we can't reuse
5348 * i830PllIsValid() because it relies on the xf86_config connector
5349 * configuration being accurate, which it isn't necessarily.
5350 */
5351
5352 return clock.dot;
5353 }
5354
5355 /** Returns the currently programmed mode of the given pipe. */
5356 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5357 struct drm_crtc *crtc)
5358 {
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5361 int pipe = intel_crtc->pipe;
5362 struct drm_display_mode *mode;
5363 int htot = I915_READ(HTOTAL(pipe));
5364 int hsync = I915_READ(HSYNC(pipe));
5365 int vtot = I915_READ(VTOTAL(pipe));
5366 int vsync = I915_READ(VSYNC(pipe));
5367
5368 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5369 if (!mode)
5370 return NULL;
5371
5372 mode->clock = intel_crtc_clock_get(dev, crtc);
5373 mode->hdisplay = (htot & 0xffff) + 1;
5374 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5375 mode->hsync_start = (hsync & 0xffff) + 1;
5376 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5377 mode->vdisplay = (vtot & 0xffff) + 1;
5378 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5379 mode->vsync_start = (vsync & 0xffff) + 1;
5380 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5381
5382 drm_mode_set_name(mode);
5383
5384 return mode;
5385 }
5386
5387 #define GPU_IDLE_TIMEOUT 500 /* ms */
5388
5389 /* When this timer fires, we've been idle for awhile */
5390 static void intel_gpu_idle_timer(unsigned long arg)
5391 {
5392 struct drm_device *dev = (struct drm_device *)arg;
5393 drm_i915_private_t *dev_priv = dev->dev_private;
5394
5395 if (!list_empty(&dev_priv->mm.active_list)) {
5396 /* Still processing requests, so just re-arm the timer. */
5397 mod_timer(&dev_priv->idle_timer, jiffies +
5398 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5399 return;
5400 }
5401
5402 dev_priv->busy = false;
5403 queue_work(dev_priv->wq, &dev_priv->idle_work);
5404 }
5405
5406 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5407
5408 static void intel_crtc_idle_timer(unsigned long arg)
5409 {
5410 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5411 struct drm_crtc *crtc = &intel_crtc->base;
5412 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5413 struct intel_framebuffer *intel_fb;
5414
5415 intel_fb = to_intel_framebuffer(crtc->fb);
5416 if (intel_fb && intel_fb->obj->active) {
5417 /* The framebuffer is still being accessed by the GPU. */
5418 mod_timer(&intel_crtc->idle_timer, jiffies +
5419 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5420 return;
5421 }
5422
5423 intel_crtc->busy = false;
5424 queue_work(dev_priv->wq, &dev_priv->idle_work);
5425 }
5426
5427 static void intel_increase_pllclock(struct drm_crtc *crtc)
5428 {
5429 struct drm_device *dev = crtc->dev;
5430 drm_i915_private_t *dev_priv = dev->dev_private;
5431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5432 int pipe = intel_crtc->pipe;
5433 int dpll_reg = DPLL(pipe);
5434 int dpll;
5435
5436 if (HAS_PCH_SPLIT(dev))
5437 return;
5438
5439 if (!dev_priv->lvds_downclock_avail)
5440 return;
5441
5442 dpll = I915_READ(dpll_reg);
5443 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5444 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5445
5446 assert_panel_unlocked(dev_priv, pipe);
5447
5448 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5449 I915_WRITE(dpll_reg, dpll);
5450 intel_wait_for_vblank(dev, pipe);
5451
5452 dpll = I915_READ(dpll_reg);
5453 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5454 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5455 }
5456
5457 /* Schedule downclock */
5458 mod_timer(&intel_crtc->idle_timer, jiffies +
5459 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5460 }
5461
5462 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5463 {
5464 struct drm_device *dev = crtc->dev;
5465 drm_i915_private_t *dev_priv = dev->dev_private;
5466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5467
5468 if (HAS_PCH_SPLIT(dev))
5469 return;
5470
5471 if (!dev_priv->lvds_downclock_avail)
5472 return;
5473
5474 /*
5475 * Since this is called by a timer, we should never get here in
5476 * the manual case.
5477 */
5478 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5479 int pipe = intel_crtc->pipe;
5480 int dpll_reg = DPLL(pipe);
5481 int dpll;
5482
5483 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5484
5485 assert_panel_unlocked(dev_priv, pipe);
5486
5487 dpll = I915_READ(dpll_reg);
5488 dpll |= DISPLAY_RATE_SELECT_FPA1;
5489 I915_WRITE(dpll_reg, dpll);
5490 intel_wait_for_vblank(dev, pipe);
5491 dpll = I915_READ(dpll_reg);
5492 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5493 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5494 }
5495
5496 }
5497
5498 /**
5499 * intel_idle_update - adjust clocks for idleness
5500 * @work: work struct
5501 *
5502 * Either the GPU or display (or both) went idle. Check the busy status
5503 * here and adjust the CRTC and GPU clocks as necessary.
5504 */
5505 static void intel_idle_update(struct work_struct *work)
5506 {
5507 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5508 idle_work);
5509 struct drm_device *dev = dev_priv->dev;
5510 struct drm_crtc *crtc;
5511 struct intel_crtc *intel_crtc;
5512
5513 if (!i915_powersave)
5514 return;
5515
5516 mutex_lock(&dev->struct_mutex);
5517
5518 i915_update_gfx_val(dev_priv);
5519
5520 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5521 /* Skip inactive CRTCs */
5522 if (!crtc->fb)
5523 continue;
5524
5525 intel_crtc = to_intel_crtc(crtc);
5526 if (!intel_crtc->busy)
5527 intel_decrease_pllclock(crtc);
5528 }
5529
5530
5531 mutex_unlock(&dev->struct_mutex);
5532 }
5533
5534 /**
5535 * intel_mark_busy - mark the GPU and possibly the display busy
5536 * @dev: drm device
5537 * @obj: object we're operating on
5538 *
5539 * Callers can use this function to indicate that the GPU is busy processing
5540 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5541 * buffer), we'll also mark the display as busy, so we know to increase its
5542 * clock frequency.
5543 */
5544 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5545 {
5546 drm_i915_private_t *dev_priv = dev->dev_private;
5547 struct drm_crtc *crtc = NULL;
5548 struct intel_framebuffer *intel_fb;
5549 struct intel_crtc *intel_crtc;
5550
5551 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5552 return;
5553
5554 if (!dev_priv->busy) {
5555 intel_sanitize_pm(dev);
5556 dev_priv->busy = true;
5557 } else
5558 mod_timer(&dev_priv->idle_timer, jiffies +
5559 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5560
5561 if (obj == NULL)
5562 return;
5563
5564 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5565 if (!crtc->fb)
5566 continue;
5567
5568 intel_crtc = to_intel_crtc(crtc);
5569 intel_fb = to_intel_framebuffer(crtc->fb);
5570 if (intel_fb->obj == obj) {
5571 if (!intel_crtc->busy) {
5572 /* Non-busy -> busy, upclock */
5573 intel_increase_pllclock(crtc);
5574 intel_crtc->busy = true;
5575 } else {
5576 /* Busy -> busy, put off timer */
5577 mod_timer(&intel_crtc->idle_timer, jiffies +
5578 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5579 }
5580 }
5581 }
5582 }
5583
5584 static void intel_crtc_destroy(struct drm_crtc *crtc)
5585 {
5586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5587 struct drm_device *dev = crtc->dev;
5588 struct intel_unpin_work *work;
5589 unsigned long flags;
5590
5591 spin_lock_irqsave(&dev->event_lock, flags);
5592 work = intel_crtc->unpin_work;
5593 intel_crtc->unpin_work = NULL;
5594 spin_unlock_irqrestore(&dev->event_lock, flags);
5595
5596 if (work) {
5597 cancel_work_sync(&work->work);
5598 kfree(work);
5599 }
5600
5601 drm_crtc_cleanup(crtc);
5602
5603 kfree(intel_crtc);
5604 }
5605
5606 static void intel_unpin_work_fn(struct work_struct *__work)
5607 {
5608 struct intel_unpin_work *work =
5609 container_of(__work, struct intel_unpin_work, work);
5610
5611 mutex_lock(&work->dev->struct_mutex);
5612 intel_unpin_fb_obj(work->old_fb_obj);
5613 drm_gem_object_unreference(&work->pending_flip_obj->base);
5614 drm_gem_object_unreference(&work->old_fb_obj->base);
5615
5616 intel_update_fbc(work->dev);
5617 mutex_unlock(&work->dev->struct_mutex);
5618 kfree(work);
5619 }
5620
5621 static void do_intel_finish_page_flip(struct drm_device *dev,
5622 struct drm_crtc *crtc)
5623 {
5624 drm_i915_private_t *dev_priv = dev->dev_private;
5625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5626 struct intel_unpin_work *work;
5627 struct drm_i915_gem_object *obj;
5628 struct drm_pending_vblank_event *e;
5629 struct timeval tnow, tvbl;
5630 unsigned long flags;
5631
5632 /* Ignore early vblank irqs */
5633 if (intel_crtc == NULL)
5634 return;
5635
5636 do_gettimeofday(&tnow);
5637
5638 spin_lock_irqsave(&dev->event_lock, flags);
5639 work = intel_crtc->unpin_work;
5640 if (work == NULL || !work->pending) {
5641 spin_unlock_irqrestore(&dev->event_lock, flags);
5642 return;
5643 }
5644
5645 intel_crtc->unpin_work = NULL;
5646
5647 if (work->event) {
5648 e = work->event;
5649 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5650
5651 /* Called before vblank count and timestamps have
5652 * been updated for the vblank interval of flip
5653 * completion? Need to increment vblank count and
5654 * add one videorefresh duration to returned timestamp
5655 * to account for this. We assume this happened if we
5656 * get called over 0.9 frame durations after the last
5657 * timestamped vblank.
5658 *
5659 * This calculation can not be used with vrefresh rates
5660 * below 5Hz (10Hz to be on the safe side) without
5661 * promoting to 64 integers.
5662 */
5663 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5664 9 * crtc->framedur_ns) {
5665 e->event.sequence++;
5666 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5667 crtc->framedur_ns);
5668 }
5669
5670 e->event.tv_sec = tvbl.tv_sec;
5671 e->event.tv_usec = tvbl.tv_usec;
5672
5673 list_add_tail(&e->base.link,
5674 &e->base.file_priv->event_list);
5675 wake_up_interruptible(&e->base.file_priv->event_wait);
5676 }
5677
5678 drm_vblank_put(dev, intel_crtc->pipe);
5679
5680 spin_unlock_irqrestore(&dev->event_lock, flags);
5681
5682 obj = work->old_fb_obj;
5683
5684 atomic_clear_mask(1 << intel_crtc->plane,
5685 &obj->pending_flip.counter);
5686 if (atomic_read(&obj->pending_flip) == 0)
5687 wake_up(&dev_priv->pending_flip_queue);
5688
5689 schedule_work(&work->work);
5690
5691 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5692 }
5693
5694 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5695 {
5696 drm_i915_private_t *dev_priv = dev->dev_private;
5697 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5698
5699 do_intel_finish_page_flip(dev, crtc);
5700 }
5701
5702 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5703 {
5704 drm_i915_private_t *dev_priv = dev->dev_private;
5705 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5706
5707 do_intel_finish_page_flip(dev, crtc);
5708 }
5709
5710 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5711 {
5712 drm_i915_private_t *dev_priv = dev->dev_private;
5713 struct intel_crtc *intel_crtc =
5714 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5715 unsigned long flags;
5716
5717 spin_lock_irqsave(&dev->event_lock, flags);
5718 if (intel_crtc->unpin_work) {
5719 if ((++intel_crtc->unpin_work->pending) > 1)
5720 DRM_ERROR("Prepared flip multiple times\n");
5721 } else {
5722 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5723 }
5724 spin_unlock_irqrestore(&dev->event_lock, flags);
5725 }
5726
5727 static int intel_gen2_queue_flip(struct drm_device *dev,
5728 struct drm_crtc *crtc,
5729 struct drm_framebuffer *fb,
5730 struct drm_i915_gem_object *obj)
5731 {
5732 struct drm_i915_private *dev_priv = dev->dev_private;
5733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5734 unsigned long offset;
5735 u32 flip_mask;
5736 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5737 int ret;
5738
5739 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5740 if (ret)
5741 goto err;
5742
5743 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5744 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5745
5746 ret = intel_ring_begin(ring, 6);
5747 if (ret)
5748 goto err_unpin;
5749
5750 /* Can't queue multiple flips, so wait for the previous
5751 * one to finish before executing the next.
5752 */
5753 if (intel_crtc->plane)
5754 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5755 else
5756 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5757 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5758 intel_ring_emit(ring, MI_NOOP);
5759 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5760 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5761 intel_ring_emit(ring, fb->pitches[0]);
5762 intel_ring_emit(ring, obj->gtt_offset + offset);
5763 intel_ring_emit(ring, 0); /* aux display base address, unused */
5764 intel_ring_advance(ring);
5765 return 0;
5766
5767 err_unpin:
5768 intel_unpin_fb_obj(obj);
5769 err:
5770 return ret;
5771 }
5772
5773 static int intel_gen3_queue_flip(struct drm_device *dev,
5774 struct drm_crtc *crtc,
5775 struct drm_framebuffer *fb,
5776 struct drm_i915_gem_object *obj)
5777 {
5778 struct drm_i915_private *dev_priv = dev->dev_private;
5779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5780 unsigned long offset;
5781 u32 flip_mask;
5782 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5783 int ret;
5784
5785 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5786 if (ret)
5787 goto err;
5788
5789 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5790 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5791
5792 ret = intel_ring_begin(ring, 6);
5793 if (ret)
5794 goto err_unpin;
5795
5796 if (intel_crtc->plane)
5797 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5798 else
5799 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5800 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5801 intel_ring_emit(ring, MI_NOOP);
5802 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5803 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5804 intel_ring_emit(ring, fb->pitches[0]);
5805 intel_ring_emit(ring, obj->gtt_offset + offset);
5806 intel_ring_emit(ring, MI_NOOP);
5807
5808 intel_ring_advance(ring);
5809 return 0;
5810
5811 err_unpin:
5812 intel_unpin_fb_obj(obj);
5813 err:
5814 return ret;
5815 }
5816
5817 static int intel_gen4_queue_flip(struct drm_device *dev,
5818 struct drm_crtc *crtc,
5819 struct drm_framebuffer *fb,
5820 struct drm_i915_gem_object *obj)
5821 {
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5824 uint32_t pf, pipesrc;
5825 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5826 int ret;
5827
5828 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5829 if (ret)
5830 goto err;
5831
5832 ret = intel_ring_begin(ring, 4);
5833 if (ret)
5834 goto err_unpin;
5835
5836 /* i965+ uses the linear or tiled offsets from the
5837 * Display Registers (which do not change across a page-flip)
5838 * so we need only reprogram the base address.
5839 */
5840 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5841 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5842 intel_ring_emit(ring, fb->pitches[0]);
5843 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
5844
5845 /* XXX Enabling the panel-fitter across page-flip is so far
5846 * untested on non-native modes, so ignore it for now.
5847 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5848 */
5849 pf = 0;
5850 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5851 intel_ring_emit(ring, pf | pipesrc);
5852 intel_ring_advance(ring);
5853 return 0;
5854
5855 err_unpin:
5856 intel_unpin_fb_obj(obj);
5857 err:
5858 return ret;
5859 }
5860
5861 static int intel_gen6_queue_flip(struct drm_device *dev,
5862 struct drm_crtc *crtc,
5863 struct drm_framebuffer *fb,
5864 struct drm_i915_gem_object *obj)
5865 {
5866 struct drm_i915_private *dev_priv = dev->dev_private;
5867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5868 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5869 uint32_t pf, pipesrc;
5870 int ret;
5871
5872 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5873 if (ret)
5874 goto err;
5875
5876 ret = intel_ring_begin(ring, 4);
5877 if (ret)
5878 goto err_unpin;
5879
5880 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5881 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5882 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5883 intel_ring_emit(ring, obj->gtt_offset);
5884
5885 /* Contrary to the suggestions in the documentation,
5886 * "Enable Panel Fitter" does not seem to be required when page
5887 * flipping with a non-native mode, and worse causes a normal
5888 * modeset to fail.
5889 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5890 */
5891 pf = 0;
5892 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5893 intel_ring_emit(ring, pf | pipesrc);
5894 intel_ring_advance(ring);
5895 return 0;
5896
5897 err_unpin:
5898 intel_unpin_fb_obj(obj);
5899 err:
5900 return ret;
5901 }
5902
5903 /*
5904 * On gen7 we currently use the blit ring because (in early silicon at least)
5905 * the render ring doesn't give us interrpts for page flip completion, which
5906 * means clients will hang after the first flip is queued. Fortunately the
5907 * blit ring generates interrupts properly, so use it instead.
5908 */
5909 static int intel_gen7_queue_flip(struct drm_device *dev,
5910 struct drm_crtc *crtc,
5911 struct drm_framebuffer *fb,
5912 struct drm_i915_gem_object *obj)
5913 {
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5917 int ret;
5918
5919 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5920 if (ret)
5921 goto err;
5922
5923 ret = intel_ring_begin(ring, 4);
5924 if (ret)
5925 goto err_unpin;
5926
5927 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5928 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5929 intel_ring_emit(ring, (obj->gtt_offset));
5930 intel_ring_emit(ring, (MI_NOOP));
5931 intel_ring_advance(ring);
5932 return 0;
5933
5934 err_unpin:
5935 intel_unpin_fb_obj(obj);
5936 err:
5937 return ret;
5938 }
5939
5940 static int intel_default_queue_flip(struct drm_device *dev,
5941 struct drm_crtc *crtc,
5942 struct drm_framebuffer *fb,
5943 struct drm_i915_gem_object *obj)
5944 {
5945 return -ENODEV;
5946 }
5947
5948 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5949 struct drm_framebuffer *fb,
5950 struct drm_pending_vblank_event *event)
5951 {
5952 struct drm_device *dev = crtc->dev;
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954 struct intel_framebuffer *intel_fb;
5955 struct drm_i915_gem_object *obj;
5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 struct intel_unpin_work *work;
5958 unsigned long flags;
5959 int ret;
5960
5961 work = kzalloc(sizeof *work, GFP_KERNEL);
5962 if (work == NULL)
5963 return -ENOMEM;
5964
5965 work->event = event;
5966 work->dev = crtc->dev;
5967 intel_fb = to_intel_framebuffer(crtc->fb);
5968 work->old_fb_obj = intel_fb->obj;
5969 INIT_WORK(&work->work, intel_unpin_work_fn);
5970
5971 ret = drm_vblank_get(dev, intel_crtc->pipe);
5972 if (ret)
5973 goto free_work;
5974
5975 /* We borrow the event spin lock for protecting unpin_work */
5976 spin_lock_irqsave(&dev->event_lock, flags);
5977 if (intel_crtc->unpin_work) {
5978 spin_unlock_irqrestore(&dev->event_lock, flags);
5979 kfree(work);
5980 drm_vblank_put(dev, intel_crtc->pipe);
5981
5982 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5983 return -EBUSY;
5984 }
5985 intel_crtc->unpin_work = work;
5986 spin_unlock_irqrestore(&dev->event_lock, flags);
5987
5988 intel_fb = to_intel_framebuffer(fb);
5989 obj = intel_fb->obj;
5990
5991 mutex_lock(&dev->struct_mutex);
5992
5993 /* Reference the objects for the scheduled work. */
5994 drm_gem_object_reference(&work->old_fb_obj->base);
5995 drm_gem_object_reference(&obj->base);
5996
5997 crtc->fb = fb;
5998
5999 work->pending_flip_obj = obj;
6000
6001 work->enable_stall_check = true;
6002
6003 /* Block clients from rendering to the new back buffer until
6004 * the flip occurs and the object is no longer visible.
6005 */
6006 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6007
6008 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6009 if (ret)
6010 goto cleanup_pending;
6011
6012 intel_disable_fbc(dev);
6013 intel_mark_busy(dev, obj);
6014 mutex_unlock(&dev->struct_mutex);
6015
6016 trace_i915_flip_request(intel_crtc->plane, obj);
6017
6018 return 0;
6019
6020 cleanup_pending:
6021 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6022 drm_gem_object_unreference(&work->old_fb_obj->base);
6023 drm_gem_object_unreference(&obj->base);
6024 mutex_unlock(&dev->struct_mutex);
6025
6026 spin_lock_irqsave(&dev->event_lock, flags);
6027 intel_crtc->unpin_work = NULL;
6028 spin_unlock_irqrestore(&dev->event_lock, flags);
6029
6030 drm_vblank_put(dev, intel_crtc->pipe);
6031 free_work:
6032 kfree(work);
6033
6034 return ret;
6035 }
6036
6037 static void intel_sanitize_modesetting(struct drm_device *dev,
6038 int pipe, int plane)
6039 {
6040 struct drm_i915_private *dev_priv = dev->dev_private;
6041 u32 reg, val;
6042
6043 /* Clear any frame start delays used for debugging left by the BIOS */
6044 for_each_pipe(pipe) {
6045 reg = PIPECONF(pipe);
6046 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6047 }
6048
6049 if (HAS_PCH_SPLIT(dev))
6050 return;
6051
6052 /* Who knows what state these registers were left in by the BIOS or
6053 * grub?
6054 *
6055 * If we leave the registers in a conflicting state (e.g. with the
6056 * display plane reading from the other pipe than the one we intend
6057 * to use) then when we attempt to teardown the active mode, we will
6058 * not disable the pipes and planes in the correct order -- leaving
6059 * a plane reading from a disabled pipe and possibly leading to
6060 * undefined behaviour.
6061 */
6062
6063 reg = DSPCNTR(plane);
6064 val = I915_READ(reg);
6065
6066 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6067 return;
6068 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6069 return;
6070
6071 /* This display plane is active and attached to the other CPU pipe. */
6072 pipe = !pipe;
6073
6074 /* Disable the plane and wait for it to stop reading from the pipe. */
6075 intel_disable_plane(dev_priv, plane, pipe);
6076 intel_disable_pipe(dev_priv, pipe);
6077 }
6078
6079 static void intel_crtc_reset(struct drm_crtc *crtc)
6080 {
6081 struct drm_device *dev = crtc->dev;
6082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083
6084 /* Reset flags back to the 'unknown' status so that they
6085 * will be correctly set on the initial modeset.
6086 */
6087 intel_crtc->dpms_mode = -1;
6088
6089 /* We need to fix up any BIOS configuration that conflicts with
6090 * our expectations.
6091 */
6092 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6093 }
6094
6095 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6096 .dpms = intel_crtc_dpms,
6097 .mode_fixup = intel_crtc_mode_fixup,
6098 .mode_set = intel_crtc_mode_set,
6099 .mode_set_base = intel_pipe_set_base,
6100 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6101 .load_lut = intel_crtc_load_lut,
6102 .disable = intel_crtc_disable,
6103 };
6104
6105 static const struct drm_crtc_funcs intel_crtc_funcs = {
6106 .reset = intel_crtc_reset,
6107 .cursor_set = intel_crtc_cursor_set,
6108 .cursor_move = intel_crtc_cursor_move,
6109 .gamma_set = intel_crtc_gamma_set,
6110 .set_config = drm_crtc_helper_set_config,
6111 .destroy = intel_crtc_destroy,
6112 .page_flip = intel_crtc_page_flip,
6113 };
6114
6115 static void intel_pch_pll_init(struct drm_device *dev)
6116 {
6117 drm_i915_private_t *dev_priv = dev->dev_private;
6118 int i;
6119
6120 if (dev_priv->num_pch_pll == 0) {
6121 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6122 return;
6123 }
6124
6125 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6126 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6127 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6128 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6129 }
6130 }
6131
6132 static void intel_crtc_init(struct drm_device *dev, int pipe)
6133 {
6134 drm_i915_private_t *dev_priv = dev->dev_private;
6135 struct intel_crtc *intel_crtc;
6136 int i;
6137
6138 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6139 if (intel_crtc == NULL)
6140 return;
6141
6142 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6143
6144 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6145 for (i = 0; i < 256; i++) {
6146 intel_crtc->lut_r[i] = i;
6147 intel_crtc->lut_g[i] = i;
6148 intel_crtc->lut_b[i] = i;
6149 }
6150
6151 /* Swap pipes & planes for FBC on pre-965 */
6152 intel_crtc->pipe = pipe;
6153 intel_crtc->plane = pipe;
6154 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6155 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6156 intel_crtc->plane = !pipe;
6157 }
6158
6159 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6160 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6161 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6162 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6163
6164 intel_crtc_reset(&intel_crtc->base);
6165 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6166 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6167
6168 if (HAS_PCH_SPLIT(dev)) {
6169 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6170 intel_helper_funcs.commit = ironlake_crtc_commit;
6171 } else {
6172 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6173 intel_helper_funcs.commit = i9xx_crtc_commit;
6174 }
6175
6176 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6177
6178 intel_crtc->busy = false;
6179
6180 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6181 (unsigned long)intel_crtc);
6182 }
6183
6184 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6185 struct drm_file *file)
6186 {
6187 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6188 struct drm_mode_object *drmmode_obj;
6189 struct intel_crtc *crtc;
6190
6191 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6192 return -ENODEV;
6193
6194 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6195 DRM_MODE_OBJECT_CRTC);
6196
6197 if (!drmmode_obj) {
6198 DRM_ERROR("no such CRTC id\n");
6199 return -EINVAL;
6200 }
6201
6202 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6203 pipe_from_crtc_id->pipe = crtc->pipe;
6204
6205 return 0;
6206 }
6207
6208 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6209 {
6210 struct intel_encoder *encoder;
6211 int index_mask = 0;
6212 int entry = 0;
6213
6214 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6215 if (type_mask & encoder->clone_mask)
6216 index_mask |= (1 << entry);
6217 entry++;
6218 }
6219
6220 return index_mask;
6221 }
6222
6223 static bool has_edp_a(struct drm_device *dev)
6224 {
6225 struct drm_i915_private *dev_priv = dev->dev_private;
6226
6227 if (!IS_MOBILE(dev))
6228 return false;
6229
6230 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6231 return false;
6232
6233 if (IS_GEN5(dev) &&
6234 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6235 return false;
6236
6237 return true;
6238 }
6239
6240 static void intel_setup_outputs(struct drm_device *dev)
6241 {
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 struct intel_encoder *encoder;
6244 bool dpd_is_edp = false;
6245 bool has_lvds;
6246
6247 has_lvds = intel_lvds_init(dev);
6248 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6249 /* disable the panel fitter on everything but LVDS */
6250 I915_WRITE(PFIT_CONTROL, 0);
6251 }
6252
6253 if (HAS_PCH_SPLIT(dev)) {
6254 dpd_is_edp = intel_dpd_is_edp(dev);
6255
6256 if (has_edp_a(dev))
6257 intel_dp_init(dev, DP_A);
6258
6259 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6260 intel_dp_init(dev, PCH_DP_D);
6261 }
6262
6263 intel_crt_init(dev);
6264
6265 if (HAS_PCH_SPLIT(dev)) {
6266 int found;
6267
6268 if (I915_READ(HDMIB) & PORT_DETECTED) {
6269 /* PCH SDVOB multiplex with HDMIB */
6270 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6271 if (!found)
6272 intel_hdmi_init(dev, HDMIB);
6273 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6274 intel_dp_init(dev, PCH_DP_B);
6275 }
6276
6277 if (I915_READ(HDMIC) & PORT_DETECTED)
6278 intel_hdmi_init(dev, HDMIC);
6279
6280 if (I915_READ(HDMID) & PORT_DETECTED)
6281 intel_hdmi_init(dev, HDMID);
6282
6283 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6284 intel_dp_init(dev, PCH_DP_C);
6285
6286 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6287 intel_dp_init(dev, PCH_DP_D);
6288
6289 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6290 bool found = false;
6291
6292 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6293 DRM_DEBUG_KMS("probing SDVOB\n");
6294 found = intel_sdvo_init(dev, SDVOB, true);
6295 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6296 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6297 intel_hdmi_init(dev, SDVOB);
6298 }
6299
6300 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6301 DRM_DEBUG_KMS("probing DP_B\n");
6302 intel_dp_init(dev, DP_B);
6303 }
6304 }
6305
6306 /* Before G4X SDVOC doesn't have its own detect register */
6307
6308 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6309 DRM_DEBUG_KMS("probing SDVOC\n");
6310 found = intel_sdvo_init(dev, SDVOC, false);
6311 }
6312
6313 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6314
6315 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6316 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6317 intel_hdmi_init(dev, SDVOC);
6318 }
6319 if (SUPPORTS_INTEGRATED_DP(dev)) {
6320 DRM_DEBUG_KMS("probing DP_C\n");
6321 intel_dp_init(dev, DP_C);
6322 }
6323 }
6324
6325 if (SUPPORTS_INTEGRATED_DP(dev) &&
6326 (I915_READ(DP_D) & DP_DETECTED)) {
6327 DRM_DEBUG_KMS("probing DP_D\n");
6328 intel_dp_init(dev, DP_D);
6329 }
6330 } else if (IS_GEN2(dev))
6331 intel_dvo_init(dev);
6332
6333 if (SUPPORTS_TV(dev))
6334 intel_tv_init(dev);
6335
6336 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6337 encoder->base.possible_crtcs = encoder->crtc_mask;
6338 encoder->base.possible_clones =
6339 intel_encoder_clones(dev, encoder->clone_mask);
6340 }
6341
6342 /* disable all the possible outputs/crtcs before entering KMS mode */
6343 drm_helper_disable_unused_functions(dev);
6344
6345 if (HAS_PCH_SPLIT(dev))
6346 ironlake_init_pch_refclk(dev);
6347 }
6348
6349 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6350 {
6351 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6352
6353 drm_framebuffer_cleanup(fb);
6354 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6355
6356 kfree(intel_fb);
6357 }
6358
6359 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6360 struct drm_file *file,
6361 unsigned int *handle)
6362 {
6363 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6364 struct drm_i915_gem_object *obj = intel_fb->obj;
6365
6366 return drm_gem_handle_create(file, &obj->base, handle);
6367 }
6368
6369 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6370 .destroy = intel_user_framebuffer_destroy,
6371 .create_handle = intel_user_framebuffer_create_handle,
6372 };
6373
6374 int intel_framebuffer_init(struct drm_device *dev,
6375 struct intel_framebuffer *intel_fb,
6376 struct drm_mode_fb_cmd2 *mode_cmd,
6377 struct drm_i915_gem_object *obj)
6378 {
6379 int ret;
6380
6381 if (obj->tiling_mode == I915_TILING_Y)
6382 return -EINVAL;
6383
6384 if (mode_cmd->pitches[0] & 63)
6385 return -EINVAL;
6386
6387 switch (mode_cmd->pixel_format) {
6388 case DRM_FORMAT_RGB332:
6389 case DRM_FORMAT_RGB565:
6390 case DRM_FORMAT_XRGB8888:
6391 case DRM_FORMAT_XBGR8888:
6392 case DRM_FORMAT_ARGB8888:
6393 case DRM_FORMAT_XRGB2101010:
6394 case DRM_FORMAT_ARGB2101010:
6395 /* RGB formats are common across chipsets */
6396 break;
6397 case DRM_FORMAT_YUYV:
6398 case DRM_FORMAT_UYVY:
6399 case DRM_FORMAT_YVYU:
6400 case DRM_FORMAT_VYUY:
6401 break;
6402 default:
6403 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6404 mode_cmd->pixel_format);
6405 return -EINVAL;
6406 }
6407
6408 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6409 if (ret) {
6410 DRM_ERROR("framebuffer init failed %d\n", ret);
6411 return ret;
6412 }
6413
6414 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6415 intel_fb->obj = obj;
6416 return 0;
6417 }
6418
6419 static struct drm_framebuffer *
6420 intel_user_framebuffer_create(struct drm_device *dev,
6421 struct drm_file *filp,
6422 struct drm_mode_fb_cmd2 *mode_cmd)
6423 {
6424 struct drm_i915_gem_object *obj;
6425
6426 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6427 mode_cmd->handles[0]));
6428 if (&obj->base == NULL)
6429 return ERR_PTR(-ENOENT);
6430
6431 return intel_framebuffer_create(dev, mode_cmd, obj);
6432 }
6433
6434 static const struct drm_mode_config_funcs intel_mode_funcs = {
6435 .fb_create = intel_user_framebuffer_create,
6436 .output_poll_changed = intel_fb_output_poll_changed,
6437 };
6438
6439 /* Set up chip specific display functions */
6440 static void intel_init_display(struct drm_device *dev)
6441 {
6442 struct drm_i915_private *dev_priv = dev->dev_private;
6443
6444 /* We always want a DPMS function */
6445 if (HAS_PCH_SPLIT(dev)) {
6446 dev_priv->display.dpms = ironlake_crtc_dpms;
6447 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6448 dev_priv->display.off = ironlake_crtc_off;
6449 dev_priv->display.update_plane = ironlake_update_plane;
6450 } else {
6451 dev_priv->display.dpms = i9xx_crtc_dpms;
6452 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6453 dev_priv->display.off = i9xx_crtc_off;
6454 dev_priv->display.update_plane = i9xx_update_plane;
6455 }
6456
6457 /* Returns the core display clock speed */
6458 if (IS_VALLEYVIEW(dev))
6459 dev_priv->display.get_display_clock_speed =
6460 valleyview_get_display_clock_speed;
6461 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6462 dev_priv->display.get_display_clock_speed =
6463 i945_get_display_clock_speed;
6464 else if (IS_I915G(dev))
6465 dev_priv->display.get_display_clock_speed =
6466 i915_get_display_clock_speed;
6467 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6468 dev_priv->display.get_display_clock_speed =
6469 i9xx_misc_get_display_clock_speed;
6470 else if (IS_I915GM(dev))
6471 dev_priv->display.get_display_clock_speed =
6472 i915gm_get_display_clock_speed;
6473 else if (IS_I865G(dev))
6474 dev_priv->display.get_display_clock_speed =
6475 i865_get_display_clock_speed;
6476 else if (IS_I85X(dev))
6477 dev_priv->display.get_display_clock_speed =
6478 i855_get_display_clock_speed;
6479 else /* 852, 830 */
6480 dev_priv->display.get_display_clock_speed =
6481 i830_get_display_clock_speed;
6482
6483 if (HAS_PCH_SPLIT(dev)) {
6484 if (IS_GEN5(dev)) {
6485 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6486 dev_priv->display.write_eld = ironlake_write_eld;
6487 } else if (IS_GEN6(dev)) {
6488 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6489 dev_priv->display.write_eld = ironlake_write_eld;
6490 } else if (IS_IVYBRIDGE(dev)) {
6491 /* FIXME: detect B0+ stepping and use auto training */
6492 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6493 dev_priv->display.write_eld = ironlake_write_eld;
6494 } else
6495 dev_priv->display.update_wm = NULL;
6496 } else if (IS_VALLEYVIEW(dev)) {
6497 dev_priv->display.force_wake_get = vlv_force_wake_get;
6498 dev_priv->display.force_wake_put = vlv_force_wake_put;
6499 } else if (IS_G4X(dev)) {
6500 dev_priv->display.write_eld = g4x_write_eld;
6501 }
6502
6503 /* Default just returns -ENODEV to indicate unsupported */
6504 dev_priv->display.queue_flip = intel_default_queue_flip;
6505
6506 switch (INTEL_INFO(dev)->gen) {
6507 case 2:
6508 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6509 break;
6510
6511 case 3:
6512 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6513 break;
6514
6515 case 4:
6516 case 5:
6517 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6518 break;
6519
6520 case 6:
6521 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6522 break;
6523 case 7:
6524 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6525 break;
6526 }
6527 }
6528
6529 /*
6530 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6531 * resume, or other times. This quirk makes sure that's the case for
6532 * affected systems.
6533 */
6534 static void quirk_pipea_force(struct drm_device *dev)
6535 {
6536 struct drm_i915_private *dev_priv = dev->dev_private;
6537
6538 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6539 DRM_INFO("applying pipe a force quirk\n");
6540 }
6541
6542 /*
6543 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6544 */
6545 static void quirk_ssc_force_disable(struct drm_device *dev)
6546 {
6547 struct drm_i915_private *dev_priv = dev->dev_private;
6548 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6549 DRM_INFO("applying lvds SSC disable quirk\n");
6550 }
6551
6552 /*
6553 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6554 * brightness value
6555 */
6556 static void quirk_invert_brightness(struct drm_device *dev)
6557 {
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6560 DRM_INFO("applying inverted panel brightness quirk\n");
6561 }
6562
6563 struct intel_quirk {
6564 int device;
6565 int subsystem_vendor;
6566 int subsystem_device;
6567 void (*hook)(struct drm_device *dev);
6568 };
6569
6570 static struct intel_quirk intel_quirks[] = {
6571 /* HP Mini needs pipe A force quirk (LP: #322104) */
6572 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6573
6574 /* Thinkpad R31 needs pipe A force quirk */
6575 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6576 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6577 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6578
6579 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6580 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6581 /* ThinkPad X40 needs pipe A force quirk */
6582
6583 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6584 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6585
6586 /* 855 & before need to leave pipe A & dpll A up */
6587 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6588 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6589
6590 /* Lenovo U160 cannot use SSC on LVDS */
6591 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6592
6593 /* Sony Vaio Y cannot use SSC on LVDS */
6594 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6595
6596 /* Acer Aspire 5734Z must invert backlight brightness */
6597 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6598 };
6599
6600 static void intel_init_quirks(struct drm_device *dev)
6601 {
6602 struct pci_dev *d = dev->pdev;
6603 int i;
6604
6605 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6606 struct intel_quirk *q = &intel_quirks[i];
6607
6608 if (d->device == q->device &&
6609 (d->subsystem_vendor == q->subsystem_vendor ||
6610 q->subsystem_vendor == PCI_ANY_ID) &&
6611 (d->subsystem_device == q->subsystem_device ||
6612 q->subsystem_device == PCI_ANY_ID))
6613 q->hook(dev);
6614 }
6615 }
6616
6617 /* Disable the VGA plane that we never use */
6618 static void i915_disable_vga(struct drm_device *dev)
6619 {
6620 struct drm_i915_private *dev_priv = dev->dev_private;
6621 u8 sr1;
6622 u32 vga_reg;
6623
6624 if (HAS_PCH_SPLIT(dev))
6625 vga_reg = CPU_VGACNTRL;
6626 else
6627 vga_reg = VGACNTRL;
6628
6629 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6630 outb(SR01, VGA_SR_INDEX);
6631 sr1 = inb(VGA_SR_DATA);
6632 outb(sr1 | 1<<5, VGA_SR_DATA);
6633 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6634 udelay(300);
6635
6636 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6637 POSTING_READ(vga_reg);
6638 }
6639
6640 static void ivb_pch_pwm_override(struct drm_device *dev)
6641 {
6642 struct drm_i915_private *dev_priv = dev->dev_private;
6643
6644 /*
6645 * IVB has CPU eDP backlight regs too, set things up to let the
6646 * PCH regs control the backlight
6647 */
6648 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6649 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6650 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6651 }
6652
6653 void intel_modeset_init_hw(struct drm_device *dev)
6654 {
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656
6657 intel_init_clock_gating(dev);
6658
6659 if (IS_IRONLAKE_M(dev)) {
6660 ironlake_enable_drps(dev);
6661 intel_init_emon(dev);
6662 }
6663
6664 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6665 gen6_enable_rps(dev_priv);
6666 gen6_update_ring_freq(dev_priv);
6667 }
6668
6669 if (IS_IVYBRIDGE(dev))
6670 ivb_pch_pwm_override(dev);
6671 }
6672
6673 void intel_modeset_init(struct drm_device *dev)
6674 {
6675 struct drm_i915_private *dev_priv = dev->dev_private;
6676 int i, ret;
6677
6678 drm_mode_config_init(dev);
6679
6680 dev->mode_config.min_width = 0;
6681 dev->mode_config.min_height = 0;
6682
6683 dev->mode_config.preferred_depth = 24;
6684 dev->mode_config.prefer_shadow = 1;
6685
6686 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6687
6688 intel_init_quirks(dev);
6689
6690 intel_init_pm(dev);
6691
6692 intel_init_display(dev);
6693
6694 if (IS_GEN2(dev)) {
6695 dev->mode_config.max_width = 2048;
6696 dev->mode_config.max_height = 2048;
6697 } else if (IS_GEN3(dev)) {
6698 dev->mode_config.max_width = 4096;
6699 dev->mode_config.max_height = 4096;
6700 } else {
6701 dev->mode_config.max_width = 8192;
6702 dev->mode_config.max_height = 8192;
6703 }
6704 dev->mode_config.fb_base = dev->agp->base;
6705
6706 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6707 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6708
6709 for (i = 0; i < dev_priv->num_pipe; i++) {
6710 intel_crtc_init(dev, i);
6711 ret = intel_plane_init(dev, i);
6712 if (ret)
6713 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6714 }
6715
6716 intel_pch_pll_init(dev);
6717
6718 /* Just disable it once at startup */
6719 i915_disable_vga(dev);
6720 intel_setup_outputs(dev);
6721
6722 intel_modeset_init_hw(dev);
6723
6724 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6725 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6726 (unsigned long)dev);
6727 }
6728
6729 void intel_modeset_gem_init(struct drm_device *dev)
6730 {
6731 if (IS_IRONLAKE_M(dev))
6732 ironlake_enable_rc6(dev);
6733
6734 intel_setup_overlay(dev);
6735 }
6736
6737 void intel_modeset_cleanup(struct drm_device *dev)
6738 {
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740 struct drm_crtc *crtc;
6741 struct intel_crtc *intel_crtc;
6742
6743 drm_kms_helper_poll_fini(dev);
6744 mutex_lock(&dev->struct_mutex);
6745
6746 intel_unregister_dsm_handler();
6747
6748
6749 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6750 /* Skip inactive CRTCs */
6751 if (!crtc->fb)
6752 continue;
6753
6754 intel_crtc = to_intel_crtc(crtc);
6755 intel_increase_pllclock(crtc);
6756 }
6757
6758 intel_disable_fbc(dev);
6759
6760 if (IS_IRONLAKE_M(dev))
6761 ironlake_disable_drps(dev);
6762 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6763 gen6_disable_rps(dev);
6764
6765 if (IS_IRONLAKE_M(dev))
6766 ironlake_disable_rc6(dev);
6767
6768 if (IS_VALLEYVIEW(dev))
6769 vlv_init_dpio(dev);
6770
6771 mutex_unlock(&dev->struct_mutex);
6772
6773 /* Disable the irq before mode object teardown, for the irq might
6774 * enqueue unpin/hotplug work. */
6775 drm_irq_uninstall(dev);
6776 cancel_work_sync(&dev_priv->hotplug_work);
6777 cancel_work_sync(&dev_priv->rps_work);
6778
6779 /* flush any delayed tasks or pending work */
6780 flush_scheduled_work();
6781
6782 /* Shut off idle work before the crtcs get freed. */
6783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6784 intel_crtc = to_intel_crtc(crtc);
6785 del_timer_sync(&intel_crtc->idle_timer);
6786 }
6787 del_timer_sync(&dev_priv->idle_timer);
6788 cancel_work_sync(&dev_priv->idle_work);
6789
6790 drm_mode_config_cleanup(dev);
6791 }
6792
6793 /*
6794 * Return which encoder is currently attached for connector.
6795 */
6796 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6797 {
6798 return &intel_attached_encoder(connector)->base;
6799 }
6800
6801 void intel_connector_attach_encoder(struct intel_connector *connector,
6802 struct intel_encoder *encoder)
6803 {
6804 connector->encoder = encoder;
6805 drm_mode_connector_attach_encoder(&connector->base,
6806 &encoder->base);
6807 }
6808
6809 /*
6810 * set vga decode state - true == enable VGA decode
6811 */
6812 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6813 {
6814 struct drm_i915_private *dev_priv = dev->dev_private;
6815 u16 gmch_ctrl;
6816
6817 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6818 if (state)
6819 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6820 else
6821 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6822 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6823 return 0;
6824 }
6825
6826 #ifdef CONFIG_DEBUG_FS
6827 #include <linux/seq_file.h>
6828
6829 struct intel_display_error_state {
6830 struct intel_cursor_error_state {
6831 u32 control;
6832 u32 position;
6833 u32 base;
6834 u32 size;
6835 } cursor[2];
6836
6837 struct intel_pipe_error_state {
6838 u32 conf;
6839 u32 source;
6840
6841 u32 htotal;
6842 u32 hblank;
6843 u32 hsync;
6844 u32 vtotal;
6845 u32 vblank;
6846 u32 vsync;
6847 } pipe[2];
6848
6849 struct intel_plane_error_state {
6850 u32 control;
6851 u32 stride;
6852 u32 size;
6853 u32 pos;
6854 u32 addr;
6855 u32 surface;
6856 u32 tile_offset;
6857 } plane[2];
6858 };
6859
6860 struct intel_display_error_state *
6861 intel_display_capture_error_state(struct drm_device *dev)
6862 {
6863 drm_i915_private_t *dev_priv = dev->dev_private;
6864 struct intel_display_error_state *error;
6865 int i;
6866
6867 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6868 if (error == NULL)
6869 return NULL;
6870
6871 for (i = 0; i < 2; i++) {
6872 error->cursor[i].control = I915_READ(CURCNTR(i));
6873 error->cursor[i].position = I915_READ(CURPOS(i));
6874 error->cursor[i].base = I915_READ(CURBASE(i));
6875
6876 error->plane[i].control = I915_READ(DSPCNTR(i));
6877 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6878 error->plane[i].size = I915_READ(DSPSIZE(i));
6879 error->plane[i].pos = I915_READ(DSPPOS(i));
6880 error->plane[i].addr = I915_READ(DSPADDR(i));
6881 if (INTEL_INFO(dev)->gen >= 4) {
6882 error->plane[i].surface = I915_READ(DSPSURF(i));
6883 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6884 }
6885
6886 error->pipe[i].conf = I915_READ(PIPECONF(i));
6887 error->pipe[i].source = I915_READ(PIPESRC(i));
6888 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6889 error->pipe[i].hblank = I915_READ(HBLANK(i));
6890 error->pipe[i].hsync = I915_READ(HSYNC(i));
6891 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6892 error->pipe[i].vblank = I915_READ(VBLANK(i));
6893 error->pipe[i].vsync = I915_READ(VSYNC(i));
6894 }
6895
6896 return error;
6897 }
6898
6899 void
6900 intel_display_print_error_state(struct seq_file *m,
6901 struct drm_device *dev,
6902 struct intel_display_error_state *error)
6903 {
6904 int i;
6905
6906 for (i = 0; i < 2; i++) {
6907 seq_printf(m, "Pipe [%d]:\n", i);
6908 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6909 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6910 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6911 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6912 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6913 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6914 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6915 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6916
6917 seq_printf(m, "Plane [%d]:\n", i);
6918 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6919 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6920 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6921 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6922 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6923 if (INTEL_INFO(dev)->gen >= 4) {
6924 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6925 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6926 }
6927
6928 seq_printf(m, "Cursor [%d]:\n", i);
6929 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6930 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6931 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6932 }
6933 }
6934 #endif
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