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drm/i915: Power gating display wells during i915_pm_suspend
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 typedef struct {
105 int min, max;
106 } intel_range_t;
107
108 typedef struct {
109 int dot_limit;
110 int p2_slow, p2_fast;
111 } intel_p2_t;
112
113 typedef struct intel_limit intel_limit_t;
114 struct intel_limit {
115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
117 };
118
119 int
120 intel_pch_rawclk(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127 }
128
129 static inline u32 /* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device *dev)
131 {
132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
137 }
138
139 static const intel_limit_t intel_limits_i8xx_dac = {
140 .dot = { .min = 25000, .max = 350000 },
141 .vco = { .min = 908000, .max = 1512000 },
142 .n = { .min = 2, .max = 16 },
143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
150 };
151
152 static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
154 .vco = { .min = 908000, .max = 1512000 },
155 .n = { .min = 2, .max = 16 },
156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163 };
164
165 static const intel_limit_t intel_limits_i8xx_lvds = {
166 .dot = { .min = 25000, .max = 350000 },
167 .vco = { .min = 908000, .max = 1512000 },
168 .n = { .min = 2, .max = 16 },
169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
176 };
177
178 static const intel_limit_t intel_limits_i9xx_sdvo = {
179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
189 };
190
191 static const intel_limit_t intel_limits_i9xx_lvds = {
192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
202 };
203
204
205 static const intel_limit_t intel_limits_g4x_sdvo = {
206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
217 },
218 };
219
220 static const intel_limit_t intel_limits_g4x_hdmi = {
221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
231 };
232
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
244 },
245 };
246
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
258 },
259 };
260
261 static const intel_limit_t intel_limits_pineview_sdvo = {
262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
274 };
275
276 static const intel_limit_t intel_limits_pineview_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
287 };
288
289 /* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
294 static const intel_limit_t intel_limits_ironlake_dac = {
295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 };
332
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 };
359
360 static const intel_limit_t intel_limits_vlv = {
361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
368 .vco = { .min = 4000000, .max = 6000000 },
369 .n = { .min = 1, .max = 7 },
370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
372 .p1 = { .min = 2, .max = 3 },
373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
374 };
375
376 static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390 };
391
392 static void vlv_clock(int refclk, intel_clock_t *clock)
393 {
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
400 }
401
402 /**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406 {
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415 }
416
417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
419 {
420 struct drm_device *dev = crtc->dev;
421 const intel_limit_t *limit;
422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (intel_is_dual_link_lvds(dev)) {
425 if (refclk == 100000)
426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
430 if (refclk == 100000)
431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
435 } else
436 limit = &intel_limits_ironlake_dac;
437
438 return limit;
439 }
440
441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442 {
443 struct drm_device *dev = crtc->dev;
444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
447 if (intel_is_dual_link_lvds(dev))
448 limit = &intel_limits_g4x_dual_channel_lvds;
449 else
450 limit = &intel_limits_g4x_single_channel_lvds;
451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
453 limit = &intel_limits_g4x_hdmi;
454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
455 limit = &intel_limits_g4x_sdvo;
456 } else /* The option is for other outputs */
457 limit = &intel_limits_i9xx_sdvo;
458
459 return limit;
460 }
461
462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
463 {
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
467 if (HAS_PCH_SPLIT(dev))
468 limit = intel_ironlake_limit(crtc, refclk);
469 else if (IS_G4X(dev)) {
470 limit = intel_g4x_limit(crtc);
471 } else if (IS_PINEVIEW(dev)) {
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
473 limit = &intel_limits_pineview_lvds;
474 else
475 limit = &intel_limits_pineview_sdvo;
476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
478 } else if (IS_VALLEYVIEW(dev)) {
479 limit = &intel_limits_vlv;
480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
487 limit = &intel_limits_i8xx_lvds;
488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
489 limit = &intel_limits_i8xx_dvo;
490 else
491 limit = &intel_limits_i8xx_dac;
492 }
493 return limit;
494 }
495
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk, intel_clock_t *clock)
498 {
499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
505 }
506
507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508 {
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510 }
511
512 static void i9xx_clock(int refclk, intel_clock_t *clock)
513 {
514 clock->m = i9xx_dpll_compute_m(clock);
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520 }
521
522 static void chv_clock(int refclk, intel_clock_t *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
569 INTELPllInvalid("dot out of range\n");
570
571 return true;
572 }
573
574 static bool
575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
578 {
579 struct drm_device *dev = crtc->dev;
580 intel_clock_t clock;
581 int err = target;
582
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
600 memset(best_clock, 0, sizeof(*best_clock));
601
602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
606 if (clock.m2 >= clock.m1)
607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
612 int this_err;
613
614 i9xx_clock(refclk, &clock);
615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
617 continue;
618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633 }
634
635 static bool
636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
639 {
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692 }
693
694 static bool
695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
698 {
699 struct drm_device *dev = crtc->dev;
700 intel_clock_t clock;
701 int max_n;
702 bool found;
703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 i9xx_clock(refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
748 return found;
749 }
750
751 static bool
752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
755 {
756 struct drm_device *dev = crtc->dev;
757 intel_clock_t clock;
758 unsigned int bestppm = 1000000;
759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
761 bool found = false;
762
763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
772 clock.p = clock.p1 * clock.p2;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
775 unsigned int ppm, diff;
776
777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
779
780 vlv_clock(refclk, &clock);
781
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
784 continue;
785
786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
790 bestppm = 0;
791 *best_clock = clock;
792 found = true;
793 }
794
795 if (bestppm >= 10 && ppm < bestppm - 10) {
796 bestppm = ppm;
797 *best_clock = clock;
798 found = true;
799 }
800 }
801 }
802 }
803 }
804
805 return found;
806 }
807
808 static bool
809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858 }
859
860 bool intel_crtc_active(struct drm_crtc *crtc)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
869 *
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
872 */
873 return intel_crtc->active && crtc->primary->fb &&
874 intel_crtc->config.adjusted_mode.crtc_clock;
875 }
876
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
883 return intel_crtc->config.cpu_transcoder;
884 }
885
886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
887 {
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 WARN(1, "vblank wait timed out\n");
895 }
896
897 /**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
909
910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
912 return;
913 }
914
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
935 DRM_DEBUG_KMS("vblank wait timed out\n");
936 }
937
938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955 }
956
957 /*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
972 *
973 */
974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
979
980 if (INTEL_INFO(dev)->gen >= 4) {
981 int reg = PIPECONF(cpu_transcoder);
982
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
986 WARN(1, "pipe_off wait timed out\n");
987 } else {
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
990 WARN(1, "pipe_off wait timed out\n");
991 }
992 }
993
994 /*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003 {
1004 u32 bit;
1005
1006 if (HAS_PCH_IBX(dev_priv->dev)) {
1007 switch (port->port) {
1008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
1021 switch (port->port) {
1022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
1034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041 return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083 if (crtc->config.shared_dpll < 0)
1084 return NULL;
1085
1086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
1093 {
1094 bool cur_state;
1095 struct intel_dpll_hw_state hw_state;
1096
1097 if (WARN (!pll,
1098 "asserting DPLL %s with no DPLL\n", state_string(state)))
1099 return;
1100
1101 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1102 WARN(cur_state != state,
1103 "%s assertion failure (expected %s, current %s)\n",
1104 pll->name, state_string(state), state_string(cur_state));
1105 }
1106
1107 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1114 pipe);
1115
1116 if (HAS_DDI(dev_priv->dev)) {
1117 /* DDI does not have a specific FDI_TX register */
1118 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1119 val = I915_READ(reg);
1120 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1121 } else {
1122 reg = FDI_TX_CTL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & FDI_TX_ENABLE);
1125 }
1126 WARN(cur_state != state,
1127 "FDI TX state assertion failure (expected %s, current %s)\n",
1128 state_string(state), state_string(cur_state));
1129 }
1130 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1131 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1132
1133 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1134 enum pipe pipe, bool state)
1135 {
1136 int reg;
1137 u32 val;
1138 bool cur_state;
1139
1140 reg = FDI_RX_CTL(pipe);
1141 val = I915_READ(reg);
1142 cur_state = !!(val & FDI_RX_ENABLE);
1143 WARN(cur_state != state,
1144 "FDI RX state assertion failure (expected %s, current %s)\n",
1145 state_string(state), state_string(cur_state));
1146 }
1147 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1148 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1149
1150 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1151 enum pipe pipe)
1152 {
1153 int reg;
1154 u32 val;
1155
1156 /* ILK FDI PLL is always enabled */
1157 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1158 return;
1159
1160 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1161 if (HAS_DDI(dev_priv->dev))
1162 return;
1163
1164 reg = FDI_TX_CTL(pipe);
1165 val = I915_READ(reg);
1166 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1167 }
1168
1169 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171 {
1172 int reg;
1173 u32 val;
1174 bool cur_state;
1175
1176 reg = FDI_RX_CTL(pipe);
1177 val = I915_READ(reg);
1178 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1179 WARN(cur_state != state,
1180 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1181 state_string(state), state_string(cur_state));
1182 }
1183
1184 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186 {
1187 int pp_reg, lvds_reg;
1188 u32 val;
1189 enum pipe panel_pipe = PIPE_A;
1190 bool locked = true;
1191
1192 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1193 pp_reg = PCH_PP_CONTROL;
1194 lvds_reg = PCH_LVDS;
1195 } else {
1196 pp_reg = PP_CONTROL;
1197 lvds_reg = LVDS;
1198 }
1199
1200 val = I915_READ(pp_reg);
1201 if (!(val & PANEL_POWER_ON) ||
1202 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1203 locked = false;
1204
1205 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1206 panel_pipe = PIPE_B;
1207
1208 WARN(panel_pipe == pipe && locked,
1209 "panel assertion failure, pipe %c regs locked\n",
1210 pipe_name(pipe));
1211 }
1212
1213 static void assert_cursor(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 struct drm_device *dev = dev_priv->dev;
1217 bool cur_state;
1218
1219 if (IS_845G(dev) || IS_I865G(dev))
1220 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1221 else
1222 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1223
1224 WARN(cur_state != state,
1225 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1226 pipe_name(pipe), state_string(state), state_string(cur_state));
1227 }
1228 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1229 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1230
1231 void assert_pipe(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
1233 {
1234 int reg;
1235 u32 val;
1236 bool cur_state;
1237 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1238 pipe);
1239
1240 /* if we need the pipe A quirk it must be always on */
1241 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1242 state = true;
1243
1244 if (!intel_display_power_enabled(dev_priv,
1245 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1246 cur_state = false;
1247 } else {
1248 reg = PIPECONF(cpu_transcoder);
1249 val = I915_READ(reg);
1250 cur_state = !!(val & PIPECONF_ENABLE);
1251 }
1252
1253 WARN(cur_state != state,
1254 "pipe %c assertion failure (expected %s, current %s)\n",
1255 pipe_name(pipe), state_string(state), state_string(cur_state));
1256 }
1257
1258 static void assert_plane(struct drm_i915_private *dev_priv,
1259 enum plane plane, bool state)
1260 {
1261 int reg;
1262 u32 val;
1263 bool cur_state;
1264
1265 reg = DSPCNTR(plane);
1266 val = I915_READ(reg);
1267 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1268 WARN(cur_state != state,
1269 "plane %c assertion failure (expected %s, current %s)\n",
1270 plane_name(plane), state_string(state), state_string(cur_state));
1271 }
1272
1273 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1274 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1275
1276 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe)
1278 {
1279 struct drm_device *dev = dev_priv->dev;
1280 int reg, i;
1281 u32 val;
1282 int cur_pipe;
1283
1284 /* Primary planes are fixed to pipes on gen4+ */
1285 if (INTEL_INFO(dev)->gen >= 4) {
1286 reg = DSPCNTR(pipe);
1287 val = I915_READ(reg);
1288 WARN(val & DISPLAY_PLANE_ENABLE,
1289 "plane %c assertion failure, should be disabled but not\n",
1290 plane_name(pipe));
1291 return;
1292 }
1293
1294 /* Need to check both planes against the pipe */
1295 for_each_pipe(i) {
1296 reg = DSPCNTR(i);
1297 val = I915_READ(reg);
1298 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1299 DISPPLANE_SEL_PIPE_SHIFT;
1300 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1301 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1302 plane_name(i), pipe_name(pipe));
1303 }
1304 }
1305
1306 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe)
1308 {
1309 struct drm_device *dev = dev_priv->dev;
1310 int reg, sprite;
1311 u32 val;
1312
1313 if (IS_VALLEYVIEW(dev)) {
1314 for_each_sprite(pipe, sprite) {
1315 reg = SPCNTR(pipe, sprite);
1316 val = I915_READ(reg);
1317 WARN(val & SP_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 sprite_name(pipe, sprite), pipe_name(pipe));
1320 }
1321 } else if (INTEL_INFO(dev)->gen >= 7) {
1322 reg = SPRCTL(pipe);
1323 val = I915_READ(reg);
1324 WARN(val & SPRITE_ENABLE,
1325 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(pipe), pipe_name(pipe));
1327 } else if (INTEL_INFO(dev)->gen >= 5) {
1328 reg = DVSCNTR(pipe);
1329 val = I915_READ(reg);
1330 WARN(val & DVS_ENABLE,
1331 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332 plane_name(pipe), pipe_name(pipe));
1333 }
1334 }
1335
1336 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1337 {
1338 u32 val;
1339 bool enabled;
1340
1341 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1342
1343 val = I915_READ(PCH_DREF_CONTROL);
1344 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1345 DREF_SUPERSPREAD_SOURCE_MASK));
1346 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1347 }
1348
1349 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe)
1351 {
1352 int reg;
1353 u32 val;
1354 bool enabled;
1355
1356 reg = PCH_TRANSCONF(pipe);
1357 val = I915_READ(reg);
1358 enabled = !!(val & TRANS_ENABLE);
1359 WARN(enabled,
1360 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1361 pipe_name(pipe));
1362 }
1363
1364 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe, u32 port_sel, u32 val)
1366 {
1367 if ((val & DP_PORT_EN) == 0)
1368 return false;
1369
1370 if (HAS_PCH_CPT(dev_priv->dev)) {
1371 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1372 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1373 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1374 return false;
1375 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1376 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1377 return false;
1378 } else {
1379 if ((val & DP_PIPE_MASK) != (pipe << 30))
1380 return false;
1381 }
1382 return true;
1383 }
1384
1385 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, u32 val)
1387 {
1388 if ((val & SDVO_ENABLE) == 0)
1389 return false;
1390
1391 if (HAS_PCH_CPT(dev_priv->dev)) {
1392 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1393 return false;
1394 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1395 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1396 return false;
1397 } else {
1398 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1399 return false;
1400 }
1401 return true;
1402 }
1403
1404 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe, u32 val)
1406 {
1407 if ((val & LVDS_PORT_EN) == 0)
1408 return false;
1409
1410 if (HAS_PCH_CPT(dev_priv->dev)) {
1411 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1412 return false;
1413 } else {
1414 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1415 return false;
1416 }
1417 return true;
1418 }
1419
1420 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, u32 val)
1422 {
1423 if ((val & ADPA_DAC_ENABLE) == 0)
1424 return false;
1425 if (HAS_PCH_CPT(dev_priv->dev)) {
1426 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1427 return false;
1428 } else {
1429 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, int reg, u32 port_sel)
1437 {
1438 u32 val = I915_READ(reg);
1439 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1440 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1441 reg, pipe_name(pipe));
1442
1443 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1444 && (val & DP_PIPEB_SELECT),
1445 "IBX PCH dp port still using transcoder B\n");
1446 }
1447
1448 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1449 enum pipe pipe, int reg)
1450 {
1451 u32 val = I915_READ(reg);
1452 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1453 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1454 reg, pipe_name(pipe));
1455
1456 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1457 && (val & SDVO_PIPE_B_SELECT),
1458 "IBX PCH hdmi port still using transcoder B\n");
1459 }
1460
1461 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe)
1463 {
1464 int reg;
1465 u32 val;
1466
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1470
1471 reg = PCH_ADPA;
1472 val = I915_READ(reg);
1473 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1474 "PCH VGA enabled on transcoder %c, should be disabled\n",
1475 pipe_name(pipe));
1476
1477 reg = PCH_LVDS;
1478 val = I915_READ(reg);
1479 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void intel_init_dpio(struct drm_device *dev)
1489 {
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491
1492 if (!IS_VALLEYVIEW(dev))
1493 return;
1494
1495 /*
1496 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1497 * CHV x1 PHY (DP/HDMI D)
1498 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 */
1500 if (IS_CHERRYVIEW(dev)) {
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1503 } else {
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1505 }
1506 }
1507
1508 static void intel_reset_dpio(struct drm_device *dev)
1509 {
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
1512 if (IS_CHERRYVIEW(dev)) {
1513 enum dpio_phy phy;
1514 u32 val;
1515
1516 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1517 /* Poll for phypwrgood signal */
1518 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1519 PHY_POWERGOOD(phy), 1))
1520 DRM_ERROR("Display PHY %d is not power up\n", phy);
1521
1522 /*
1523 * Deassert common lane reset for PHY.
1524 *
1525 * This should only be done on init and resume from S3
1526 * with both PLLs disabled, or we risk losing DPIO and
1527 * PLL synchronization.
1528 */
1529 val = I915_READ(DISPLAY_PHY_CONTROL);
1530 I915_WRITE(DISPLAY_PHY_CONTROL,
1531 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1532 }
1533 }
1534 }
1535
1536 static void vlv_enable_pll(struct intel_crtc *crtc)
1537 {
1538 struct drm_device *dev = crtc->base.dev;
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 int reg = DPLL(crtc->pipe);
1541 u32 dpll = crtc->config.dpll_hw_state.dpll;
1542
1543 assert_pipe_disabled(dev_priv, crtc->pipe);
1544
1545 /* No really, not for ILK+ */
1546 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1547
1548 /* PLL is protected by panel, make sure we can write it */
1549 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1550 assert_panel_unlocked(dev_priv, crtc->pipe);
1551
1552 I915_WRITE(reg, dpll);
1553 POSTING_READ(reg);
1554 udelay(150);
1555
1556 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1557 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1558
1559 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1560 POSTING_READ(DPLL_MD(crtc->pipe));
1561
1562 /* We do this three times for luck */
1563 I915_WRITE(reg, dpll);
1564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg, dpll);
1570 POSTING_READ(reg);
1571 udelay(150); /* wait for warmup */
1572 }
1573
1574 static void chv_enable_pll(struct intel_crtc *crtc)
1575 {
1576 struct drm_device *dev = crtc->base.dev;
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int pipe = crtc->pipe;
1579 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1580 u32 tmp;
1581
1582 assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1585
1586 mutex_lock(&dev_priv->dpio_lock);
1587
1588 /* Enable back the 10bit clock to display controller */
1589 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1590 tmp |= DPIO_DCLKP_EN;
1591 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1592
1593 /*
1594 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595 */
1596 udelay(1);
1597
1598 /* Enable PLL */
1599 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1600
1601 /* Check PLL is locked */
1602 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1603 DRM_ERROR("PLL %d failed to lock\n", pipe);
1604
1605 /* not sure when this should be written */
1606 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1607 POSTING_READ(DPLL_MD(pipe));
1608
1609 mutex_unlock(&dev_priv->dpio_lock);
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 int reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config.dpll_hw_state.dpll;
1618
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621 /* No really, not for ILK+ */
1622 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1623
1624 /* PLL is protected by panel, make sure we can write it */
1625 if (IS_MOBILE(dev) && !IS_I830(dev))
1626 assert_panel_unlocked(dev_priv, crtc->pipe);
1627
1628 I915_WRITE(reg, dpll);
1629
1630 /* Wait for the clocks to stabilize. */
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (INTEL_INFO(dev)->gen >= 4) {
1635 I915_WRITE(DPLL_MD(crtc->pipe),
1636 crtc->config.dpll_hw_state.dpll_md);
1637 } else {
1638 /* The pixel multiplier can only be updated once the
1639 * DPLL is enabled and the clocks are stable.
1640 *
1641 * So write it again.
1642 */
1643 I915_WRITE(reg, dpll);
1644 }
1645
1646 /* We do this three times for luck */
1647 I915_WRITE(reg, dpll);
1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 }
1657
1658 /**
1659 * i9xx_disable_pll - disable a PLL
1660 * @dev_priv: i915 private structure
1661 * @pipe: pipe PLL to disable
1662 *
1663 * Disable the PLL for @pipe, making sure the pipe is off first.
1664 *
1665 * Note! This is for pre-ILK only.
1666 */
1667 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1668 {
1669 /* Don't disable pipe A or pipe A PLLs if needed */
1670 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1671 return;
1672
1673 /* Make sure the pipe isn't still relying on us */
1674 assert_pipe_disabled(dev_priv, pipe);
1675
1676 I915_WRITE(DPLL(pipe), 0);
1677 POSTING_READ(DPLL(pipe));
1678 }
1679
1680 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1681 {
1682 u32 val = 0;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 /*
1688 * Leave integrated clock source and reference clock enabled for pipe B.
1689 * The latter is needed for VGA hotplug / manual detection.
1690 */
1691 if (pipe == PIPE_B)
1692 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1693 I915_WRITE(DPLL(pipe), val);
1694 POSTING_READ(DPLL(pipe));
1695
1696 }
1697
1698 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699 {
1700 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1701 u32 val;
1702
1703 /* Make sure the pipe isn't still relying on us */
1704 assert_pipe_disabled(dev_priv, pipe);
1705
1706 /* Set PLL en = 0 */
1707 val = DPLL_SSC_REF_CLOCK_CHV;
1708 if (pipe != PIPE_A)
1709 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1710 I915_WRITE(DPLL(pipe), val);
1711 POSTING_READ(DPLL(pipe));
1712
1713 mutex_lock(&dev_priv->dpio_lock);
1714
1715 /* Disable 10bit clock to display controller */
1716 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1717 val &= ~DPIO_DCLKP_EN;
1718 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1719
1720 /* disable left/right clock distribution */
1721 if (pipe != PIPE_B) {
1722 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1723 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1724 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1725 } else {
1726 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1727 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1728 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1729 }
1730
1731 mutex_unlock(&dev_priv->dpio_lock);
1732 }
1733
1734 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1735 struct intel_digital_port *dport)
1736 {
1737 u32 port_mask;
1738 int dpll_reg;
1739
1740 switch (dport->port) {
1741 case PORT_B:
1742 port_mask = DPLL_PORTB_READY_MASK;
1743 dpll_reg = DPLL(0);
1744 break;
1745 case PORT_C:
1746 port_mask = DPLL_PORTC_READY_MASK;
1747 dpll_reg = DPLL(0);
1748 break;
1749 case PORT_D:
1750 port_mask = DPLL_PORTD_READY_MASK;
1751 dpll_reg = DPIO_PHY_STATUS;
1752 break;
1753 default:
1754 BUG();
1755 }
1756
1757 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1758 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1759 port_name(dport->port), I915_READ(dpll_reg));
1760 }
1761
1762 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1763 {
1764 struct drm_device *dev = crtc->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1767
1768 if (WARN_ON(pll == NULL))
1769 return;
1770
1771 WARN_ON(!pll->refcount);
1772 if (pll->active == 0) {
1773 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1774 WARN_ON(pll->on);
1775 assert_shared_dpll_disabled(dev_priv, pll);
1776
1777 pll->mode_set(dev_priv, pll);
1778 }
1779 }
1780
1781 /**
1782 * intel_enable_shared_dpll - enable PCH PLL
1783 * @dev_priv: i915 private structure
1784 * @pipe: pipe PLL to enable
1785 *
1786 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1787 * drives the transcoder clock.
1788 */
1789 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1790 {
1791 struct drm_device *dev = crtc->base.dev;
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1794
1795 if (WARN_ON(pll == NULL))
1796 return;
1797
1798 if (WARN_ON(pll->refcount == 0))
1799 return;
1800
1801 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1802 pll->name, pll->active, pll->on,
1803 crtc->base.base.id);
1804
1805 if (pll->active++) {
1806 WARN_ON(!pll->on);
1807 assert_shared_dpll_enabled(dev_priv, pll);
1808 return;
1809 }
1810 WARN_ON(pll->on);
1811
1812 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1813
1814 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1815 pll->enable(dev_priv, pll);
1816 pll->on = true;
1817 }
1818
1819 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1820 {
1821 struct drm_device *dev = crtc->base.dev;
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1824
1825 /* PCH only available on ILK+ */
1826 BUG_ON(INTEL_INFO(dev)->gen < 5);
1827 if (WARN_ON(pll == NULL))
1828 return;
1829
1830 if (WARN_ON(pll->refcount == 0))
1831 return;
1832
1833 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1834 pll->name, pll->active, pll->on,
1835 crtc->base.base.id);
1836
1837 if (WARN_ON(pll->active == 0)) {
1838 assert_shared_dpll_disabled(dev_priv, pll);
1839 return;
1840 }
1841
1842 assert_shared_dpll_enabled(dev_priv, pll);
1843 WARN_ON(!pll->on);
1844 if (--pll->active)
1845 return;
1846
1847 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1848 pll->disable(dev_priv, pll);
1849 pll->on = false;
1850
1851 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1852 }
1853
1854 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1855 enum pipe pipe)
1856 {
1857 struct drm_device *dev = dev_priv->dev;
1858 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1860 uint32_t reg, val, pipeconf_val;
1861
1862 /* PCH only available on ILK+ */
1863 BUG_ON(INTEL_INFO(dev)->gen < 5);
1864
1865 /* Make sure PCH DPLL is enabled */
1866 assert_shared_dpll_enabled(dev_priv,
1867 intel_crtc_to_shared_dpll(intel_crtc));
1868
1869 /* FDI must be feeding us bits for PCH ports */
1870 assert_fdi_tx_enabled(dev_priv, pipe);
1871 assert_fdi_rx_enabled(dev_priv, pipe);
1872
1873 if (HAS_PCH_CPT(dev)) {
1874 /* Workaround: Set the timing override bit before enabling the
1875 * pch transcoder. */
1876 reg = TRANS_CHICKEN2(pipe);
1877 val = I915_READ(reg);
1878 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1879 I915_WRITE(reg, val);
1880 }
1881
1882 reg = PCH_TRANSCONF(pipe);
1883 val = I915_READ(reg);
1884 pipeconf_val = I915_READ(PIPECONF(pipe));
1885
1886 if (HAS_PCH_IBX(dev_priv->dev)) {
1887 /*
1888 * make the BPC in transcoder be consistent with
1889 * that in pipeconf reg.
1890 */
1891 val &= ~PIPECONF_BPC_MASK;
1892 val |= pipeconf_val & PIPECONF_BPC_MASK;
1893 }
1894
1895 val &= ~TRANS_INTERLACE_MASK;
1896 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1897 if (HAS_PCH_IBX(dev_priv->dev) &&
1898 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1899 val |= TRANS_LEGACY_INTERLACED_ILK;
1900 else
1901 val |= TRANS_INTERLACED;
1902 else
1903 val |= TRANS_PROGRESSIVE;
1904
1905 I915_WRITE(reg, val | TRANS_ENABLE);
1906 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1907 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1908 }
1909
1910 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1911 enum transcoder cpu_transcoder)
1912 {
1913 u32 val, pipeconf_val;
1914
1915 /* PCH only available on ILK+ */
1916 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1917
1918 /* FDI must be feeding us bits for PCH ports */
1919 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1920 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1921
1922 /* Workaround: set timing override bit. */
1923 val = I915_READ(_TRANSA_CHICKEN2);
1924 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1925 I915_WRITE(_TRANSA_CHICKEN2, val);
1926
1927 val = TRANS_ENABLE;
1928 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1929
1930 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1931 PIPECONF_INTERLACED_ILK)
1932 val |= TRANS_INTERLACED;
1933 else
1934 val |= TRANS_PROGRESSIVE;
1935
1936 I915_WRITE(LPT_TRANSCONF, val);
1937 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1938 DRM_ERROR("Failed to enable PCH transcoder\n");
1939 }
1940
1941 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
1943 {
1944 struct drm_device *dev = dev_priv->dev;
1945 uint32_t reg, val;
1946
1947 /* FDI relies on the transcoder */
1948 assert_fdi_tx_disabled(dev_priv, pipe);
1949 assert_fdi_rx_disabled(dev_priv, pipe);
1950
1951 /* Ports must be off as well */
1952 assert_pch_ports_disabled(dev_priv, pipe);
1953
1954 reg = PCH_TRANSCONF(pipe);
1955 val = I915_READ(reg);
1956 val &= ~TRANS_ENABLE;
1957 I915_WRITE(reg, val);
1958 /* wait for PCH transcoder off, transcoder state */
1959 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1960 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1961
1962 if (!HAS_PCH_IBX(dev)) {
1963 /* Workaround: Clear the timing override chicken bit again. */
1964 reg = TRANS_CHICKEN2(pipe);
1965 val = I915_READ(reg);
1966 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1967 I915_WRITE(reg, val);
1968 }
1969 }
1970
1971 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1972 {
1973 u32 val;
1974
1975 val = I915_READ(LPT_TRANSCONF);
1976 val &= ~TRANS_ENABLE;
1977 I915_WRITE(LPT_TRANSCONF, val);
1978 /* wait for PCH transcoder off, transcoder state */
1979 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1980 DRM_ERROR("Failed to disable PCH transcoder\n");
1981
1982 /* Workaround: clear timing override bit. */
1983 val = I915_READ(_TRANSA_CHICKEN2);
1984 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(_TRANSA_CHICKEN2, val);
1986 }
1987
1988 /**
1989 * intel_enable_pipe - enable a pipe, asserting requirements
1990 * @crtc: crtc responsible for the pipe
1991 *
1992 * Enable @crtc's pipe, making sure that various hardware specific requirements
1993 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1994 */
1995 static void intel_enable_pipe(struct intel_crtc *crtc)
1996 {
1997 struct drm_device *dev = crtc->base.dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 enum pipe pipe = crtc->pipe;
2000 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2001 pipe);
2002 enum pipe pch_transcoder;
2003 int reg;
2004 u32 val;
2005
2006 assert_planes_disabled(dev_priv, pipe);
2007 assert_cursor_disabled(dev_priv, pipe);
2008 assert_sprites_disabled(dev_priv, pipe);
2009
2010 if (HAS_PCH_LPT(dev_priv->dev))
2011 pch_transcoder = TRANSCODER_A;
2012 else
2013 pch_transcoder = pipe;
2014
2015 /*
2016 * A pipe without a PLL won't actually be able to drive bits from
2017 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2018 * need the check.
2019 */
2020 if (!HAS_PCH_SPLIT(dev_priv->dev))
2021 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2022 assert_dsi_pll_enabled(dev_priv);
2023 else
2024 assert_pll_enabled(dev_priv, pipe);
2025 else {
2026 if (crtc->config.has_pch_encoder) {
2027 /* if driving the PCH, we need FDI enabled */
2028 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2029 assert_fdi_tx_pll_enabled(dev_priv,
2030 (enum pipe) cpu_transcoder);
2031 }
2032 /* FIXME: assert CPU port conditions for SNB+ */
2033 }
2034
2035 reg = PIPECONF(cpu_transcoder);
2036 val = I915_READ(reg);
2037 if (val & PIPECONF_ENABLE) {
2038 WARN_ON(!(pipe == PIPE_A &&
2039 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2040 return;
2041 }
2042
2043 I915_WRITE(reg, val | PIPECONF_ENABLE);
2044 POSTING_READ(reg);
2045 }
2046
2047 /**
2048 * intel_disable_pipe - disable a pipe, asserting requirements
2049 * @dev_priv: i915 private structure
2050 * @pipe: pipe to disable
2051 *
2052 * Disable @pipe, making sure that various hardware specific requirements
2053 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2054 *
2055 * @pipe should be %PIPE_A or %PIPE_B.
2056 *
2057 * Will wait until the pipe has shut down before returning.
2058 */
2059 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
2061 {
2062 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2063 pipe);
2064 int reg;
2065 u32 val;
2066
2067 /*
2068 * Make sure planes won't keep trying to pump pixels to us,
2069 * or we might hang the display.
2070 */
2071 assert_planes_disabled(dev_priv, pipe);
2072 assert_cursor_disabled(dev_priv, pipe);
2073 assert_sprites_disabled(dev_priv, pipe);
2074
2075 /* Don't disable pipe A or pipe A PLLs if needed */
2076 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2077 return;
2078
2079 reg = PIPECONF(cpu_transcoder);
2080 val = I915_READ(reg);
2081 if ((val & PIPECONF_ENABLE) == 0)
2082 return;
2083
2084 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2085 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2086 }
2087
2088 /*
2089 * Plane regs are double buffered, going from enabled->disabled needs a
2090 * trigger in order to latch. The display address reg provides this.
2091 */
2092 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2093 enum plane plane)
2094 {
2095 struct drm_device *dev = dev_priv->dev;
2096 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2097
2098 I915_WRITE(reg, I915_READ(reg));
2099 POSTING_READ(reg);
2100 }
2101
2102 /**
2103 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2104 * @dev_priv: i915 private structure
2105 * @plane: plane to enable
2106 * @pipe: pipe being fed
2107 *
2108 * Enable @plane on @pipe, making sure that @pipe is running first.
2109 */
2110 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane, enum pipe pipe)
2112 {
2113 struct drm_device *dev = dev_priv->dev;
2114 struct intel_crtc *intel_crtc =
2115 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2116 int reg;
2117 u32 val;
2118
2119 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2120 assert_pipe_enabled(dev_priv, pipe);
2121
2122 if (intel_crtc->primary_enabled)
2123 return;
2124
2125 intel_crtc->primary_enabled = true;
2126
2127 reg = DSPCNTR(plane);
2128 val = I915_READ(reg);
2129 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2130
2131 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2132 intel_flush_primary_plane(dev_priv, plane);
2133
2134 /*
2135 * BDW signals flip done immediately if the plane
2136 * is disabled, even if the plane enable is already
2137 * armed to occur at the next vblank :(
2138 */
2139 if (IS_BROADWELL(dev))
2140 intel_wait_for_vblank(dev, intel_crtc->pipe);
2141 }
2142
2143 /**
2144 * intel_disable_primary_hw_plane - disable the primary hardware plane
2145 * @dev_priv: i915 private structure
2146 * @plane: plane to disable
2147 * @pipe: pipe consuming the data
2148 *
2149 * Disable @plane; should be an independent operation.
2150 */
2151 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2152 enum plane plane, enum pipe pipe)
2153 {
2154 struct intel_crtc *intel_crtc =
2155 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2156 int reg;
2157 u32 val;
2158
2159 if (!intel_crtc->primary_enabled)
2160 return;
2161
2162 intel_crtc->primary_enabled = false;
2163
2164 reg = DSPCNTR(plane);
2165 val = I915_READ(reg);
2166 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2167
2168 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2169 intel_flush_primary_plane(dev_priv, plane);
2170 }
2171
2172 static bool need_vtd_wa(struct drm_device *dev)
2173 {
2174 #ifdef CONFIG_INTEL_IOMMU
2175 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2176 return true;
2177 #endif
2178 return false;
2179 }
2180
2181 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2182 {
2183 int tile_height;
2184
2185 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2186 return ALIGN(height, tile_height);
2187 }
2188
2189 int
2190 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2191 struct drm_i915_gem_object *obj,
2192 struct intel_engine_cs *pipelined)
2193 {
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2195 u32 alignment;
2196 int ret;
2197
2198 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2199
2200 switch (obj->tiling_mode) {
2201 case I915_TILING_NONE:
2202 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2203 alignment = 128 * 1024;
2204 else if (INTEL_INFO(dev)->gen >= 4)
2205 alignment = 4 * 1024;
2206 else
2207 alignment = 64 * 1024;
2208 break;
2209 case I915_TILING_X:
2210 /* pin() will align the object as required by fence */
2211 alignment = 0;
2212 break;
2213 case I915_TILING_Y:
2214 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2215 return -EINVAL;
2216 default:
2217 BUG();
2218 }
2219
2220 /* Note that the w/a also requires 64 PTE of padding following the
2221 * bo. We currently fill all unused PTE with the shadow page and so
2222 * we should always have valid PTE following the scanout preventing
2223 * the VT-d warning.
2224 */
2225 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2226 alignment = 256 * 1024;
2227
2228 dev_priv->mm.interruptible = false;
2229 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2230 if (ret)
2231 goto err_interruptible;
2232
2233 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234 * fence, whereas 965+ only requires a fence if using
2235 * framebuffer compression. For simplicity, we always install
2236 * a fence as the cost is not that onerous.
2237 */
2238 ret = i915_gem_object_get_fence(obj);
2239 if (ret)
2240 goto err_unpin;
2241
2242 i915_gem_object_pin_fence(obj);
2243
2244 dev_priv->mm.interruptible = true;
2245 return 0;
2246
2247 err_unpin:
2248 i915_gem_object_unpin_from_display_plane(obj);
2249 err_interruptible:
2250 dev_priv->mm.interruptible = true;
2251 return ret;
2252 }
2253
2254 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2255 {
2256 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2257
2258 i915_gem_object_unpin_fence(obj);
2259 i915_gem_object_unpin_from_display_plane(obj);
2260 }
2261
2262 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2263 * is assumed to be a power-of-two. */
2264 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2265 unsigned int tiling_mode,
2266 unsigned int cpp,
2267 unsigned int pitch)
2268 {
2269 if (tiling_mode != I915_TILING_NONE) {
2270 unsigned int tile_rows, tiles;
2271
2272 tile_rows = *y / 8;
2273 *y %= 8;
2274
2275 tiles = *x / (512/cpp);
2276 *x %= 512/cpp;
2277
2278 return tile_rows * pitch * 8 + tiles * 4096;
2279 } else {
2280 unsigned int offset;
2281
2282 offset = *y * pitch + *x * cpp;
2283 *y = 0;
2284 *x = (offset & 4095) / cpp;
2285 return offset & -4096;
2286 }
2287 }
2288
2289 int intel_format_to_fourcc(int format)
2290 {
2291 switch (format) {
2292 case DISPPLANE_8BPP:
2293 return DRM_FORMAT_C8;
2294 case DISPPLANE_BGRX555:
2295 return DRM_FORMAT_XRGB1555;
2296 case DISPPLANE_BGRX565:
2297 return DRM_FORMAT_RGB565;
2298 default:
2299 case DISPPLANE_BGRX888:
2300 return DRM_FORMAT_XRGB8888;
2301 case DISPPLANE_RGBX888:
2302 return DRM_FORMAT_XBGR8888;
2303 case DISPPLANE_BGRX101010:
2304 return DRM_FORMAT_XRGB2101010;
2305 case DISPPLANE_RGBX101010:
2306 return DRM_FORMAT_XBGR2101010;
2307 }
2308 }
2309
2310 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2311 struct intel_plane_config *plane_config)
2312 {
2313 struct drm_device *dev = crtc->base.dev;
2314 struct drm_i915_gem_object *obj = NULL;
2315 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2316 u32 base = plane_config->base;
2317
2318 if (plane_config->size == 0)
2319 return false;
2320
2321 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2322 plane_config->size);
2323 if (!obj)
2324 return false;
2325
2326 if (plane_config->tiled) {
2327 obj->tiling_mode = I915_TILING_X;
2328 obj->stride = crtc->base.primary->fb->pitches[0];
2329 }
2330
2331 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2332 mode_cmd.width = crtc->base.primary->fb->width;
2333 mode_cmd.height = crtc->base.primary->fb->height;
2334 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2335
2336 mutex_lock(&dev->struct_mutex);
2337
2338 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2339 &mode_cmd, obj)) {
2340 DRM_DEBUG_KMS("intel fb init failed\n");
2341 goto out_unref_obj;
2342 }
2343
2344 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2345 mutex_unlock(&dev->struct_mutex);
2346
2347 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2348 return true;
2349
2350 out_unref_obj:
2351 drm_gem_object_unreference(&obj->base);
2352 mutex_unlock(&dev->struct_mutex);
2353 return false;
2354 }
2355
2356 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2357 struct intel_plane_config *plane_config)
2358 {
2359 struct drm_device *dev = intel_crtc->base.dev;
2360 struct drm_crtc *c;
2361 struct intel_crtc *i;
2362 struct drm_i915_gem_object *obj;
2363
2364 if (!intel_crtc->base.primary->fb)
2365 return;
2366
2367 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2368 return;
2369
2370 kfree(intel_crtc->base.primary->fb);
2371 intel_crtc->base.primary->fb = NULL;
2372
2373 /*
2374 * Failed to alloc the obj, check to see if we should share
2375 * an fb with another CRTC instead
2376 */
2377 for_each_crtc(dev, c) {
2378 i = to_intel_crtc(c);
2379
2380 if (c == &intel_crtc->base)
2381 continue;
2382
2383 if (!i->active)
2384 continue;
2385
2386 obj = intel_fb_obj(c->primary->fb);
2387 if (obj == NULL)
2388 continue;
2389
2390 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2391 drm_framebuffer_reference(c->primary->fb);
2392 intel_crtc->base.primary->fb = c->primary->fb;
2393 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2394 break;
2395 }
2396 }
2397 }
2398
2399 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2400 struct drm_framebuffer *fb,
2401 int x, int y)
2402 {
2403 struct drm_device *dev = crtc->dev;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2406 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2407 int plane = intel_crtc->plane;
2408 unsigned long linear_offset;
2409 u32 dspcntr;
2410 u32 reg;
2411
2412 reg = DSPCNTR(plane);
2413 dspcntr = I915_READ(reg);
2414 /* Mask out pixel format bits in case we change it */
2415 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2416 switch (fb->pixel_format) {
2417 case DRM_FORMAT_C8:
2418 dspcntr |= DISPPLANE_8BPP;
2419 break;
2420 case DRM_FORMAT_XRGB1555:
2421 case DRM_FORMAT_ARGB1555:
2422 dspcntr |= DISPPLANE_BGRX555;
2423 break;
2424 case DRM_FORMAT_RGB565:
2425 dspcntr |= DISPPLANE_BGRX565;
2426 break;
2427 case DRM_FORMAT_XRGB8888:
2428 case DRM_FORMAT_ARGB8888:
2429 dspcntr |= DISPPLANE_BGRX888;
2430 break;
2431 case DRM_FORMAT_XBGR8888:
2432 case DRM_FORMAT_ABGR8888:
2433 dspcntr |= DISPPLANE_RGBX888;
2434 break;
2435 case DRM_FORMAT_XRGB2101010:
2436 case DRM_FORMAT_ARGB2101010:
2437 dspcntr |= DISPPLANE_BGRX101010;
2438 break;
2439 case DRM_FORMAT_XBGR2101010:
2440 case DRM_FORMAT_ABGR2101010:
2441 dspcntr |= DISPPLANE_RGBX101010;
2442 break;
2443 default:
2444 BUG();
2445 }
2446
2447 if (INTEL_INFO(dev)->gen >= 4) {
2448 if (obj->tiling_mode != I915_TILING_NONE)
2449 dspcntr |= DISPPLANE_TILED;
2450 else
2451 dspcntr &= ~DISPPLANE_TILED;
2452 }
2453
2454 if (IS_G4X(dev))
2455 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2456
2457 I915_WRITE(reg, dspcntr);
2458
2459 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2460
2461 if (INTEL_INFO(dev)->gen >= 4) {
2462 intel_crtc->dspaddr_offset =
2463 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2464 fb->bits_per_pixel / 8,
2465 fb->pitches[0]);
2466 linear_offset -= intel_crtc->dspaddr_offset;
2467 } else {
2468 intel_crtc->dspaddr_offset = linear_offset;
2469 }
2470
2471 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2472 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2473 fb->pitches[0]);
2474 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2475 if (INTEL_INFO(dev)->gen >= 4) {
2476 I915_WRITE(DSPSURF(plane),
2477 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2478 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2479 I915_WRITE(DSPLINOFF(plane), linear_offset);
2480 } else
2481 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2482 POSTING_READ(reg);
2483 }
2484
2485 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2486 struct drm_framebuffer *fb,
2487 int x, int y)
2488 {
2489 struct drm_device *dev = crtc->dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2492 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2493 int plane = intel_crtc->plane;
2494 unsigned long linear_offset;
2495 u32 dspcntr;
2496 u32 reg;
2497
2498 reg = DSPCNTR(plane);
2499 dspcntr = I915_READ(reg);
2500 /* Mask out pixel format bits in case we change it */
2501 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2502 switch (fb->pixel_format) {
2503 case DRM_FORMAT_C8:
2504 dspcntr |= DISPPLANE_8BPP;
2505 break;
2506 case DRM_FORMAT_RGB565:
2507 dspcntr |= DISPPLANE_BGRX565;
2508 break;
2509 case DRM_FORMAT_XRGB8888:
2510 case DRM_FORMAT_ARGB8888:
2511 dspcntr |= DISPPLANE_BGRX888;
2512 break;
2513 case DRM_FORMAT_XBGR8888:
2514 case DRM_FORMAT_ABGR8888:
2515 dspcntr |= DISPPLANE_RGBX888;
2516 break;
2517 case DRM_FORMAT_XRGB2101010:
2518 case DRM_FORMAT_ARGB2101010:
2519 dspcntr |= DISPPLANE_BGRX101010;
2520 break;
2521 case DRM_FORMAT_XBGR2101010:
2522 case DRM_FORMAT_ABGR2101010:
2523 dspcntr |= DISPPLANE_RGBX101010;
2524 break;
2525 default:
2526 BUG();
2527 }
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dspcntr |= DISPPLANE_TILED;
2531 else
2532 dspcntr &= ~DISPPLANE_TILED;
2533
2534 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2535 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2536 else
2537 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2538
2539 I915_WRITE(reg, dspcntr);
2540
2541 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2542 intel_crtc->dspaddr_offset =
2543 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2544 fb->bits_per_pixel / 8,
2545 fb->pitches[0]);
2546 linear_offset -= intel_crtc->dspaddr_offset;
2547
2548 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2549 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2550 fb->pitches[0]);
2551 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2555 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2556 } else {
2557 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2558 I915_WRITE(DSPLINOFF(plane), linear_offset);
2559 }
2560 POSTING_READ(reg);
2561 }
2562
2563 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2564 static int
2565 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2566 int x, int y, enum mode_set_atomic state)
2567 {
2568 struct drm_device *dev = crtc->dev;
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570
2571 if (dev_priv->display.disable_fbc)
2572 dev_priv->display.disable_fbc(dev);
2573 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2574
2575 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2576
2577 return 0;
2578 }
2579
2580 void intel_display_handle_reset(struct drm_device *dev)
2581 {
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct drm_crtc *crtc;
2584
2585 /*
2586 * Flips in the rings have been nuked by the reset,
2587 * so complete all pending flips so that user space
2588 * will get its events and not get stuck.
2589 *
2590 * Also update the base address of all primary
2591 * planes to the the last fb to make sure we're
2592 * showing the correct fb after a reset.
2593 *
2594 * Need to make two loops over the crtcs so that we
2595 * don't try to grab a crtc mutex before the
2596 * pending_flip_queue really got woken up.
2597 */
2598
2599 for_each_crtc(dev, crtc) {
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 enum plane plane = intel_crtc->plane;
2602
2603 intel_prepare_page_flip(dev, plane);
2604 intel_finish_page_flip_plane(dev, plane);
2605 }
2606
2607 for_each_crtc(dev, crtc) {
2608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2609
2610 drm_modeset_lock(&crtc->mutex, NULL);
2611 /*
2612 * FIXME: Once we have proper support for primary planes (and
2613 * disabling them without disabling the entire crtc) allow again
2614 * a NULL crtc->primary->fb.
2615 */
2616 if (intel_crtc->active && crtc->primary->fb)
2617 dev_priv->display.update_primary_plane(crtc,
2618 crtc->primary->fb,
2619 crtc->x,
2620 crtc->y);
2621 drm_modeset_unlock(&crtc->mutex);
2622 }
2623 }
2624
2625 static int
2626 intel_finish_fb(struct drm_framebuffer *old_fb)
2627 {
2628 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2629 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2630 bool was_interruptible = dev_priv->mm.interruptible;
2631 int ret;
2632
2633 /* Big Hammer, we also need to ensure that any pending
2634 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2635 * current scanout is retired before unpinning the old
2636 * framebuffer.
2637 *
2638 * This should only fail upon a hung GPU, in which case we
2639 * can safely continue.
2640 */
2641 dev_priv->mm.interruptible = false;
2642 ret = i915_gem_object_finish_gpu(obj);
2643 dev_priv->mm.interruptible = was_interruptible;
2644
2645 return ret;
2646 }
2647
2648 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2649 {
2650 struct drm_device *dev = crtc->dev;
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653 unsigned long flags;
2654 bool pending;
2655
2656 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2657 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2658 return false;
2659
2660 spin_lock_irqsave(&dev->event_lock, flags);
2661 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2662 spin_unlock_irqrestore(&dev->event_lock, flags);
2663
2664 return pending;
2665 }
2666
2667 static int
2668 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2669 struct drm_framebuffer *fb)
2670 {
2671 struct drm_device *dev = crtc->dev;
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2674 enum pipe pipe = intel_crtc->pipe;
2675 struct drm_framebuffer *old_fb = crtc->primary->fb;
2676 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2677 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2678 int ret;
2679
2680 if (intel_crtc_has_pending_flip(crtc)) {
2681 DRM_ERROR("pipe is still busy with an old pageflip\n");
2682 return -EBUSY;
2683 }
2684
2685 /* no fb bound */
2686 if (!fb) {
2687 DRM_ERROR("No FB bound\n");
2688 return 0;
2689 }
2690
2691 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2692 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2693 plane_name(intel_crtc->plane),
2694 INTEL_INFO(dev)->num_pipes);
2695 return -EINVAL;
2696 }
2697
2698 mutex_lock(&dev->struct_mutex);
2699 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2700 if (ret == 0)
2701 i915_gem_track_fb(old_obj, obj,
2702 INTEL_FRONTBUFFER_PRIMARY(pipe));
2703 mutex_unlock(&dev->struct_mutex);
2704 if (ret != 0) {
2705 DRM_ERROR("pin & fence failed\n");
2706 return ret;
2707 }
2708
2709 /*
2710 * Update pipe size and adjust fitter if needed: the reason for this is
2711 * that in compute_mode_changes we check the native mode (not the pfit
2712 * mode) to see if we can flip rather than do a full mode set. In the
2713 * fastboot case, we'll flip, but if we don't update the pipesrc and
2714 * pfit state, we'll end up with a big fb scanned out into the wrong
2715 * sized surface.
2716 *
2717 * To fix this properly, we need to hoist the checks up into
2718 * compute_mode_changes (or above), check the actual pfit state and
2719 * whether the platform allows pfit disable with pipe active, and only
2720 * then update the pipesrc and pfit state, even on the flip path.
2721 */
2722 if (i915.fastboot) {
2723 const struct drm_display_mode *adjusted_mode =
2724 &intel_crtc->config.adjusted_mode;
2725
2726 I915_WRITE(PIPESRC(intel_crtc->pipe),
2727 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2728 (adjusted_mode->crtc_vdisplay - 1));
2729 if (!intel_crtc->config.pch_pfit.enabled &&
2730 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2731 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2732 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2733 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2734 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2735 }
2736 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2737 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2738 }
2739
2740 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2741
2742 if (intel_crtc->active)
2743 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2744
2745 crtc->primary->fb = fb;
2746 crtc->x = x;
2747 crtc->y = y;
2748
2749 if (old_fb) {
2750 if (intel_crtc->active && old_fb != fb)
2751 intel_wait_for_vblank(dev, intel_crtc->pipe);
2752 mutex_lock(&dev->struct_mutex);
2753 intel_unpin_fb_obj(old_obj);
2754 mutex_unlock(&dev->struct_mutex);
2755 }
2756
2757 mutex_lock(&dev->struct_mutex);
2758 intel_update_fbc(dev);
2759 mutex_unlock(&dev->struct_mutex);
2760
2761 return 0;
2762 }
2763
2764 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2765 {
2766 struct drm_device *dev = crtc->dev;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 int pipe = intel_crtc->pipe;
2770 u32 reg, temp;
2771
2772 /* enable normal train */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 if (IS_IVYBRIDGE(dev)) {
2776 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2778 } else {
2779 temp &= ~FDI_LINK_TRAIN_NONE;
2780 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2781 }
2782 I915_WRITE(reg, temp);
2783
2784 reg = FDI_RX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 if (HAS_PCH_CPT(dev)) {
2787 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2788 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2789 } else {
2790 temp &= ~FDI_LINK_TRAIN_NONE;
2791 temp |= FDI_LINK_TRAIN_NONE;
2792 }
2793 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2794
2795 /* wait one idle pattern time */
2796 POSTING_READ(reg);
2797 udelay(1000);
2798
2799 /* IVB wants error correction enabled */
2800 if (IS_IVYBRIDGE(dev))
2801 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2802 FDI_FE_ERRC_ENABLE);
2803 }
2804
2805 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2806 {
2807 return crtc->base.enabled && crtc->active &&
2808 crtc->config.has_pch_encoder;
2809 }
2810
2811 static void ivb_modeset_global_resources(struct drm_device *dev)
2812 {
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *pipe_B_crtc =
2815 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2816 struct intel_crtc *pipe_C_crtc =
2817 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2818 uint32_t temp;
2819
2820 /*
2821 * When everything is off disable fdi C so that we could enable fdi B
2822 * with all lanes. Note that we don't care about enabled pipes without
2823 * an enabled pch encoder.
2824 */
2825 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2826 !pipe_has_enabled_pch(pipe_C_crtc)) {
2827 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2828 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2829
2830 temp = I915_READ(SOUTH_CHICKEN1);
2831 temp &= ~FDI_BC_BIFURCATION_SELECT;
2832 DRM_DEBUG_KMS("disabling fdi C rx\n");
2833 I915_WRITE(SOUTH_CHICKEN1, temp);
2834 }
2835 }
2836
2837 /* The FDI link training functions for ILK/Ibexpeak. */
2838 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2839 {
2840 struct drm_device *dev = crtc->dev;
2841 struct drm_i915_private *dev_priv = dev->dev_private;
2842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2843 int pipe = intel_crtc->pipe;
2844 u32 reg, temp, tries;
2845
2846 /* FDI needs bits from pipe first */
2847 assert_pipe_enabled(dev_priv, pipe);
2848
2849 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2850 for train result */
2851 reg = FDI_RX_IMR(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_RX_SYMBOL_LOCK;
2854 temp &= ~FDI_RX_BIT_LOCK;
2855 I915_WRITE(reg, temp);
2856 I915_READ(reg);
2857 udelay(150);
2858
2859 /* enable CPU FDI TX and PCH FDI RX */
2860 reg = FDI_TX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2863 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2864 temp &= ~FDI_LINK_TRAIN_NONE;
2865 temp |= FDI_LINK_TRAIN_PATTERN_1;
2866 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2867
2868 reg = FDI_RX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 temp &= ~FDI_LINK_TRAIN_NONE;
2871 temp |= FDI_LINK_TRAIN_PATTERN_1;
2872 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2873
2874 POSTING_READ(reg);
2875 udelay(150);
2876
2877 /* Ironlake workaround, enable clock pointer after FDI enable*/
2878 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2879 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2880 FDI_RX_PHASE_SYNC_POINTER_EN);
2881
2882 reg = FDI_RX_IIR(pipe);
2883 for (tries = 0; tries < 5; tries++) {
2884 temp = I915_READ(reg);
2885 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2886
2887 if ((temp & FDI_RX_BIT_LOCK)) {
2888 DRM_DEBUG_KMS("FDI train 1 done.\n");
2889 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2890 break;
2891 }
2892 }
2893 if (tries == 5)
2894 DRM_ERROR("FDI train 1 fail!\n");
2895
2896 /* Train 2 */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 temp &= ~FDI_LINK_TRAIN_NONE;
2900 temp |= FDI_LINK_TRAIN_PATTERN_2;
2901 I915_WRITE(reg, temp);
2902
2903 reg = FDI_RX_CTL(pipe);
2904 temp = I915_READ(reg);
2905 temp &= ~FDI_LINK_TRAIN_NONE;
2906 temp |= FDI_LINK_TRAIN_PATTERN_2;
2907 I915_WRITE(reg, temp);
2908
2909 POSTING_READ(reg);
2910 udelay(150);
2911
2912 reg = FDI_RX_IIR(pipe);
2913 for (tries = 0; tries < 5; tries++) {
2914 temp = I915_READ(reg);
2915 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2916
2917 if (temp & FDI_RX_SYMBOL_LOCK) {
2918 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2919 DRM_DEBUG_KMS("FDI train 2 done.\n");
2920 break;
2921 }
2922 }
2923 if (tries == 5)
2924 DRM_ERROR("FDI train 2 fail!\n");
2925
2926 DRM_DEBUG_KMS("FDI train done\n");
2927
2928 }
2929
2930 static const int snb_b_fdi_train_param[] = {
2931 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2932 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2933 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2934 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2935 };
2936
2937 /* The FDI link training functions for SNB/Cougarpoint. */
2938 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2939 {
2940 struct drm_device *dev = crtc->dev;
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2943 int pipe = intel_crtc->pipe;
2944 u32 reg, temp, i, retry;
2945
2946 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2947 for train result */
2948 reg = FDI_RX_IMR(pipe);
2949 temp = I915_READ(reg);
2950 temp &= ~FDI_RX_SYMBOL_LOCK;
2951 temp &= ~FDI_RX_BIT_LOCK;
2952 I915_WRITE(reg, temp);
2953
2954 POSTING_READ(reg);
2955 udelay(150);
2956
2957 /* enable CPU FDI TX and PCH FDI RX */
2958 reg = FDI_TX_CTL(pipe);
2959 temp = I915_READ(reg);
2960 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2961 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2962 temp &= ~FDI_LINK_TRAIN_NONE;
2963 temp |= FDI_LINK_TRAIN_PATTERN_1;
2964 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2965 /* SNB-B */
2966 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2967 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2968
2969 I915_WRITE(FDI_RX_MISC(pipe),
2970 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2971
2972 reg = FDI_RX_CTL(pipe);
2973 temp = I915_READ(reg);
2974 if (HAS_PCH_CPT(dev)) {
2975 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2976 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2977 } else {
2978 temp &= ~FDI_LINK_TRAIN_NONE;
2979 temp |= FDI_LINK_TRAIN_PATTERN_1;
2980 }
2981 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2982
2983 POSTING_READ(reg);
2984 udelay(150);
2985
2986 for (i = 0; i < 4; i++) {
2987 reg = FDI_TX_CTL(pipe);
2988 temp = I915_READ(reg);
2989 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2990 temp |= snb_b_fdi_train_param[i];
2991 I915_WRITE(reg, temp);
2992
2993 POSTING_READ(reg);
2994 udelay(500);
2995
2996 for (retry = 0; retry < 5; retry++) {
2997 reg = FDI_RX_IIR(pipe);
2998 temp = I915_READ(reg);
2999 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3000 if (temp & FDI_RX_BIT_LOCK) {
3001 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3002 DRM_DEBUG_KMS("FDI train 1 done.\n");
3003 break;
3004 }
3005 udelay(50);
3006 }
3007 if (retry < 5)
3008 break;
3009 }
3010 if (i == 4)
3011 DRM_ERROR("FDI train 1 fail!\n");
3012
3013 /* Train 2 */
3014 reg = FDI_TX_CTL(pipe);
3015 temp = I915_READ(reg);
3016 temp &= ~FDI_LINK_TRAIN_NONE;
3017 temp |= FDI_LINK_TRAIN_PATTERN_2;
3018 if (IS_GEN6(dev)) {
3019 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3020 /* SNB-B */
3021 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3022 }
3023 I915_WRITE(reg, temp);
3024
3025 reg = FDI_RX_CTL(pipe);
3026 temp = I915_READ(reg);
3027 if (HAS_PCH_CPT(dev)) {
3028 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3029 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3030 } else {
3031 temp &= ~FDI_LINK_TRAIN_NONE;
3032 temp |= FDI_LINK_TRAIN_PATTERN_2;
3033 }
3034 I915_WRITE(reg, temp);
3035
3036 POSTING_READ(reg);
3037 udelay(150);
3038
3039 for (i = 0; i < 4; i++) {
3040 reg = FDI_TX_CTL(pipe);
3041 temp = I915_READ(reg);
3042 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3043 temp |= snb_b_fdi_train_param[i];
3044 I915_WRITE(reg, temp);
3045
3046 POSTING_READ(reg);
3047 udelay(500);
3048
3049 for (retry = 0; retry < 5; retry++) {
3050 reg = FDI_RX_IIR(pipe);
3051 temp = I915_READ(reg);
3052 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3053 if (temp & FDI_RX_SYMBOL_LOCK) {
3054 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3055 DRM_DEBUG_KMS("FDI train 2 done.\n");
3056 break;
3057 }
3058 udelay(50);
3059 }
3060 if (retry < 5)
3061 break;
3062 }
3063 if (i == 4)
3064 DRM_ERROR("FDI train 2 fail!\n");
3065
3066 DRM_DEBUG_KMS("FDI train done.\n");
3067 }
3068
3069 /* Manual link training for Ivy Bridge A0 parts */
3070 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3071 {
3072 struct drm_device *dev = crtc->dev;
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075 int pipe = intel_crtc->pipe;
3076 u32 reg, temp, i, j;
3077
3078 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3079 for train result */
3080 reg = FDI_RX_IMR(pipe);
3081 temp = I915_READ(reg);
3082 temp &= ~FDI_RX_SYMBOL_LOCK;
3083 temp &= ~FDI_RX_BIT_LOCK;
3084 I915_WRITE(reg, temp);
3085
3086 POSTING_READ(reg);
3087 udelay(150);
3088
3089 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3090 I915_READ(FDI_RX_IIR(pipe)));
3091
3092 /* Try each vswing and preemphasis setting twice before moving on */
3093 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3094 /* disable first in case we need to retry */
3095 reg = FDI_TX_CTL(pipe);
3096 temp = I915_READ(reg);
3097 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3098 temp &= ~FDI_TX_ENABLE;
3099 I915_WRITE(reg, temp);
3100
3101 reg = FDI_RX_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~FDI_LINK_TRAIN_AUTO;
3104 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3105 temp &= ~FDI_RX_ENABLE;
3106 I915_WRITE(reg, temp);
3107
3108 /* enable CPU FDI TX and PCH FDI RX */
3109 reg = FDI_TX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3112 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3113 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3114 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3115 temp |= snb_b_fdi_train_param[j/2];
3116 temp |= FDI_COMPOSITE_SYNC;
3117 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3118
3119 I915_WRITE(FDI_RX_MISC(pipe),
3120 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3121
3122 reg = FDI_RX_CTL(pipe);
3123 temp = I915_READ(reg);
3124 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3125 temp |= FDI_COMPOSITE_SYNC;
3126 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3127
3128 POSTING_READ(reg);
3129 udelay(1); /* should be 0.5us */
3130
3131 for (i = 0; i < 4; i++) {
3132 reg = FDI_RX_IIR(pipe);
3133 temp = I915_READ(reg);
3134 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3135
3136 if (temp & FDI_RX_BIT_LOCK ||
3137 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3138 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3139 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3140 i);
3141 break;
3142 }
3143 udelay(1); /* should be 0.5us */
3144 }
3145 if (i == 4) {
3146 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3147 continue;
3148 }
3149
3150 /* Train 2 */
3151 reg = FDI_TX_CTL(pipe);
3152 temp = I915_READ(reg);
3153 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3154 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3155 I915_WRITE(reg, temp);
3156
3157 reg = FDI_RX_CTL(pipe);
3158 temp = I915_READ(reg);
3159 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3160 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3161 I915_WRITE(reg, temp);
3162
3163 POSTING_READ(reg);
3164 udelay(2); /* should be 1.5us */
3165
3166 for (i = 0; i < 4; i++) {
3167 reg = FDI_RX_IIR(pipe);
3168 temp = I915_READ(reg);
3169 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3170
3171 if (temp & FDI_RX_SYMBOL_LOCK ||
3172 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3173 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3174 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3175 i);
3176 goto train_done;
3177 }
3178 udelay(2); /* should be 1.5us */
3179 }
3180 if (i == 4)
3181 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3182 }
3183
3184 train_done:
3185 DRM_DEBUG_KMS("FDI train done.\n");
3186 }
3187
3188 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3189 {
3190 struct drm_device *dev = intel_crtc->base.dev;
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int pipe = intel_crtc->pipe;
3193 u32 reg, temp;
3194
3195
3196 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3200 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3201 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3202 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3203
3204 POSTING_READ(reg);
3205 udelay(200);
3206
3207 /* Switch from Rawclk to PCDclk */
3208 temp = I915_READ(reg);
3209 I915_WRITE(reg, temp | FDI_PCDCLK);
3210
3211 POSTING_READ(reg);
3212 udelay(200);
3213
3214 /* Enable CPU FDI TX PLL, always on for Ironlake */
3215 reg = FDI_TX_CTL(pipe);
3216 temp = I915_READ(reg);
3217 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3218 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3219
3220 POSTING_READ(reg);
3221 udelay(100);
3222 }
3223 }
3224
3225 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3226 {
3227 struct drm_device *dev = intel_crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int pipe = intel_crtc->pipe;
3230 u32 reg, temp;
3231
3232 /* Switch from PCDclk to Rawclk */
3233 reg = FDI_RX_CTL(pipe);
3234 temp = I915_READ(reg);
3235 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3236
3237 /* Disable CPU FDI TX PLL */
3238 reg = FDI_TX_CTL(pipe);
3239 temp = I915_READ(reg);
3240 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3241
3242 POSTING_READ(reg);
3243 udelay(100);
3244
3245 reg = FDI_RX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3248
3249 /* Wait for the clocks to turn off. */
3250 POSTING_READ(reg);
3251 udelay(100);
3252 }
3253
3254 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3255 {
3256 struct drm_device *dev = crtc->dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3259 int pipe = intel_crtc->pipe;
3260 u32 reg, temp;
3261
3262 /* disable CPU FDI tx and PCH FDI rx */
3263 reg = FDI_TX_CTL(pipe);
3264 temp = I915_READ(reg);
3265 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3266 POSTING_READ(reg);
3267
3268 reg = FDI_RX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 temp &= ~(0x7 << 16);
3271 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3272 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3273
3274 POSTING_READ(reg);
3275 udelay(100);
3276
3277 /* Ironlake workaround, disable clock pointer after downing FDI */
3278 if (HAS_PCH_IBX(dev))
3279 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3280
3281 /* still set train pattern 1 */
3282 reg = FDI_TX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 temp &= ~FDI_LINK_TRAIN_NONE;
3285 temp |= FDI_LINK_TRAIN_PATTERN_1;
3286 I915_WRITE(reg, temp);
3287
3288 reg = FDI_RX_CTL(pipe);
3289 temp = I915_READ(reg);
3290 if (HAS_PCH_CPT(dev)) {
3291 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3292 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3293 } else {
3294 temp &= ~FDI_LINK_TRAIN_NONE;
3295 temp |= FDI_LINK_TRAIN_PATTERN_1;
3296 }
3297 /* BPC in FDI rx is consistent with that in PIPECONF */
3298 temp &= ~(0x07 << 16);
3299 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3300 I915_WRITE(reg, temp);
3301
3302 POSTING_READ(reg);
3303 udelay(100);
3304 }
3305
3306 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3307 {
3308 struct intel_crtc *crtc;
3309
3310 /* Note that we don't need to be called with mode_config.lock here
3311 * as our list of CRTC objects is static for the lifetime of the
3312 * device and so cannot disappear as we iterate. Similarly, we can
3313 * happily treat the predicates as racy, atomic checks as userspace
3314 * cannot claim and pin a new fb without at least acquring the
3315 * struct_mutex and so serialising with us.
3316 */
3317 for_each_intel_crtc(dev, crtc) {
3318 if (atomic_read(&crtc->unpin_work_count) == 0)
3319 continue;
3320
3321 if (crtc->unpin_work)
3322 intel_wait_for_vblank(dev, crtc->pipe);
3323
3324 return true;
3325 }
3326
3327 return false;
3328 }
3329
3330 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3331 {
3332 struct drm_device *dev = crtc->dev;
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335 if (crtc->primary->fb == NULL)
3336 return;
3337
3338 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3339
3340 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3341 !intel_crtc_has_pending_flip(crtc),
3342 60*HZ) == 0);
3343
3344 mutex_lock(&dev->struct_mutex);
3345 intel_finish_fb(crtc->primary->fb);
3346 mutex_unlock(&dev->struct_mutex);
3347 }
3348
3349 /* Program iCLKIP clock to the desired frequency */
3350 static void lpt_program_iclkip(struct drm_crtc *crtc)
3351 {
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3355 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3356 u32 temp;
3357
3358 mutex_lock(&dev_priv->dpio_lock);
3359
3360 /* It is necessary to ungate the pixclk gate prior to programming
3361 * the divisors, and gate it back when it is done.
3362 */
3363 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3364
3365 /* Disable SSCCTL */
3366 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3367 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3368 SBI_SSCCTL_DISABLE,
3369 SBI_ICLK);
3370
3371 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3372 if (clock == 20000) {
3373 auxdiv = 1;
3374 divsel = 0x41;
3375 phaseinc = 0x20;
3376 } else {
3377 /* The iCLK virtual clock root frequency is in MHz,
3378 * but the adjusted_mode->crtc_clock in in KHz. To get the
3379 * divisors, it is necessary to divide one by another, so we
3380 * convert the virtual clock precision to KHz here for higher
3381 * precision.
3382 */
3383 u32 iclk_virtual_root_freq = 172800 * 1000;
3384 u32 iclk_pi_range = 64;
3385 u32 desired_divisor, msb_divisor_value, pi_value;
3386
3387 desired_divisor = (iclk_virtual_root_freq / clock);
3388 msb_divisor_value = desired_divisor / iclk_pi_range;
3389 pi_value = desired_divisor % iclk_pi_range;
3390
3391 auxdiv = 0;
3392 divsel = msb_divisor_value - 2;
3393 phaseinc = pi_value;
3394 }
3395
3396 /* This should not happen with any sane values */
3397 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3398 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3399 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3400 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3401
3402 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3403 clock,
3404 auxdiv,
3405 divsel,
3406 phasedir,
3407 phaseinc);
3408
3409 /* Program SSCDIVINTPHASE6 */
3410 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3411 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3412 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3413 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3414 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3415 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3416 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3417 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3418
3419 /* Program SSCAUXDIV */
3420 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3421 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3422 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3423 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3424
3425 /* Enable modulator and associated divider */
3426 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3427 temp &= ~SBI_SSCCTL_DISABLE;
3428 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3429
3430 /* Wait for initialization time */
3431 udelay(24);
3432
3433 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3434
3435 mutex_unlock(&dev_priv->dpio_lock);
3436 }
3437
3438 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3439 enum pipe pch_transcoder)
3440 {
3441 struct drm_device *dev = crtc->base.dev;
3442 struct drm_i915_private *dev_priv = dev->dev_private;
3443 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3444
3445 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3446 I915_READ(HTOTAL(cpu_transcoder)));
3447 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3448 I915_READ(HBLANK(cpu_transcoder)));
3449 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3450 I915_READ(HSYNC(cpu_transcoder)));
3451
3452 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3453 I915_READ(VTOTAL(cpu_transcoder)));
3454 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3455 I915_READ(VBLANK(cpu_transcoder)));
3456 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3457 I915_READ(VSYNC(cpu_transcoder)));
3458 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3459 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3460 }
3461
3462 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3463 {
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 uint32_t temp;
3466
3467 temp = I915_READ(SOUTH_CHICKEN1);
3468 if (temp & FDI_BC_BIFURCATION_SELECT)
3469 return;
3470
3471 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3472 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3473
3474 temp |= FDI_BC_BIFURCATION_SELECT;
3475 DRM_DEBUG_KMS("enabling fdi C rx\n");
3476 I915_WRITE(SOUTH_CHICKEN1, temp);
3477 POSTING_READ(SOUTH_CHICKEN1);
3478 }
3479
3480 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3481 {
3482 struct drm_device *dev = intel_crtc->base.dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484
3485 switch (intel_crtc->pipe) {
3486 case PIPE_A:
3487 break;
3488 case PIPE_B:
3489 if (intel_crtc->config.fdi_lanes > 2)
3490 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3491 else
3492 cpt_enable_fdi_bc_bifurcation(dev);
3493
3494 break;
3495 case PIPE_C:
3496 cpt_enable_fdi_bc_bifurcation(dev);
3497
3498 break;
3499 default:
3500 BUG();
3501 }
3502 }
3503
3504 /*
3505 * Enable PCH resources required for PCH ports:
3506 * - PCH PLLs
3507 * - FDI training & RX/TX
3508 * - update transcoder timings
3509 * - DP transcoding bits
3510 * - transcoder
3511 */
3512 static void ironlake_pch_enable(struct drm_crtc *crtc)
3513 {
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 int pipe = intel_crtc->pipe;
3518 u32 reg, temp;
3519
3520 assert_pch_transcoder_disabled(dev_priv, pipe);
3521
3522 if (IS_IVYBRIDGE(dev))
3523 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3524
3525 /* Write the TU size bits before fdi link training, so that error
3526 * detection works. */
3527 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3528 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3529
3530 /* For PCH output, training FDI link */
3531 dev_priv->display.fdi_link_train(crtc);
3532
3533 /* We need to program the right clock selection before writing the pixel
3534 * mutliplier into the DPLL. */
3535 if (HAS_PCH_CPT(dev)) {
3536 u32 sel;
3537
3538 temp = I915_READ(PCH_DPLL_SEL);
3539 temp |= TRANS_DPLL_ENABLE(pipe);
3540 sel = TRANS_DPLLB_SEL(pipe);
3541 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3542 temp |= sel;
3543 else
3544 temp &= ~sel;
3545 I915_WRITE(PCH_DPLL_SEL, temp);
3546 }
3547
3548 /* XXX: pch pll's can be enabled any time before we enable the PCH
3549 * transcoder, and we actually should do this to not upset any PCH
3550 * transcoder that already use the clock when we share it.
3551 *
3552 * Note that enable_shared_dpll tries to do the right thing, but
3553 * get_shared_dpll unconditionally resets the pll - we need that to have
3554 * the right LVDS enable sequence. */
3555 intel_enable_shared_dpll(intel_crtc);
3556
3557 /* set transcoder timing, panel must allow it */
3558 assert_panel_unlocked(dev_priv, pipe);
3559 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3560
3561 intel_fdi_normal_train(crtc);
3562
3563 /* For PCH DP, enable TRANS_DP_CTL */
3564 if (HAS_PCH_CPT(dev) &&
3565 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3566 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3567 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3568 reg = TRANS_DP_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3571 TRANS_DP_SYNC_MASK |
3572 TRANS_DP_BPC_MASK);
3573 temp |= (TRANS_DP_OUTPUT_ENABLE |
3574 TRANS_DP_ENH_FRAMING);
3575 temp |= bpc << 9; /* same format but at 11:9 */
3576
3577 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3578 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3579 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3580 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3581
3582 switch (intel_trans_dp_port_sel(crtc)) {
3583 case PCH_DP_B:
3584 temp |= TRANS_DP_PORT_SEL_B;
3585 break;
3586 case PCH_DP_C:
3587 temp |= TRANS_DP_PORT_SEL_C;
3588 break;
3589 case PCH_DP_D:
3590 temp |= TRANS_DP_PORT_SEL_D;
3591 break;
3592 default:
3593 BUG();
3594 }
3595
3596 I915_WRITE(reg, temp);
3597 }
3598
3599 ironlake_enable_pch_transcoder(dev_priv, pipe);
3600 }
3601
3602 static void lpt_pch_enable(struct drm_crtc *crtc)
3603 {
3604 struct drm_device *dev = crtc->dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3608
3609 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3610
3611 lpt_program_iclkip(crtc);
3612
3613 /* Set transcoder timing. */
3614 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3615
3616 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3617 }
3618
3619 void intel_put_shared_dpll(struct intel_crtc *crtc)
3620 {
3621 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3622
3623 if (pll == NULL)
3624 return;
3625
3626 if (pll->refcount == 0) {
3627 WARN(1, "bad %s refcount\n", pll->name);
3628 return;
3629 }
3630
3631 if (--pll->refcount == 0) {
3632 WARN_ON(pll->on);
3633 WARN_ON(pll->active);
3634 }
3635
3636 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3637 }
3638
3639 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3640 {
3641 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3642 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3643 enum intel_dpll_id i;
3644
3645 if (pll) {
3646 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3647 crtc->base.base.id, pll->name);
3648 intel_put_shared_dpll(crtc);
3649 }
3650
3651 if (HAS_PCH_IBX(dev_priv->dev)) {
3652 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3653 i = (enum intel_dpll_id) crtc->pipe;
3654 pll = &dev_priv->shared_dplls[i];
3655
3656 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3657 crtc->base.base.id, pll->name);
3658
3659 WARN_ON(pll->refcount);
3660
3661 goto found;
3662 }
3663
3664 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3665 pll = &dev_priv->shared_dplls[i];
3666
3667 /* Only want to check enabled timings first */
3668 if (pll->refcount == 0)
3669 continue;
3670
3671 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3672 sizeof(pll->hw_state)) == 0) {
3673 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3674 crtc->base.base.id,
3675 pll->name, pll->refcount, pll->active);
3676
3677 goto found;
3678 }
3679 }
3680
3681 /* Ok no matching timings, maybe there's a free one? */
3682 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3683 pll = &dev_priv->shared_dplls[i];
3684 if (pll->refcount == 0) {
3685 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3686 crtc->base.base.id, pll->name);
3687 goto found;
3688 }
3689 }
3690
3691 return NULL;
3692
3693 found:
3694 if (pll->refcount == 0)
3695 pll->hw_state = crtc->config.dpll_hw_state;
3696
3697 crtc->config.shared_dpll = i;
3698 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3699 pipe_name(crtc->pipe));
3700
3701 pll->refcount++;
3702
3703 return pll;
3704 }
3705
3706 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3707 {
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 int dslreg = PIPEDSL(pipe);
3710 u32 temp;
3711
3712 temp = I915_READ(dslreg);
3713 udelay(500);
3714 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3715 if (wait_for(I915_READ(dslreg) != temp, 5))
3716 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3717 }
3718 }
3719
3720 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3721 {
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 int pipe = crtc->pipe;
3725
3726 if (crtc->config.pch_pfit.enabled) {
3727 /* Force use of hard-coded filter coefficients
3728 * as some pre-programmed values are broken,
3729 * e.g. x201.
3730 */
3731 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3732 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3733 PF_PIPE_SEL_IVB(pipe));
3734 else
3735 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3736 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3737 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3738 }
3739 }
3740
3741 static void intel_enable_planes(struct drm_crtc *crtc)
3742 {
3743 struct drm_device *dev = crtc->dev;
3744 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3745 struct drm_plane *plane;
3746 struct intel_plane *intel_plane;
3747
3748 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3749 intel_plane = to_intel_plane(plane);
3750 if (intel_plane->pipe == pipe)
3751 intel_plane_restore(&intel_plane->base);
3752 }
3753 }
3754
3755 static void intel_disable_planes(struct drm_crtc *crtc)
3756 {
3757 struct drm_device *dev = crtc->dev;
3758 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3759 struct drm_plane *plane;
3760 struct intel_plane *intel_plane;
3761
3762 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3763 intel_plane = to_intel_plane(plane);
3764 if (intel_plane->pipe == pipe)
3765 intel_plane_disable(&intel_plane->base);
3766 }
3767 }
3768
3769 void hsw_enable_ips(struct intel_crtc *crtc)
3770 {
3771 struct drm_device *dev = crtc->base.dev;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3773
3774 if (!crtc->config.ips_enabled)
3775 return;
3776
3777 /* We can only enable IPS after we enable a plane and wait for a vblank */
3778 intel_wait_for_vblank(dev, crtc->pipe);
3779
3780 assert_plane_enabled(dev_priv, crtc->plane);
3781 if (IS_BROADWELL(dev)) {
3782 mutex_lock(&dev_priv->rps.hw_lock);
3783 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3784 mutex_unlock(&dev_priv->rps.hw_lock);
3785 /* Quoting Art Runyan: "its not safe to expect any particular
3786 * value in IPS_CTL bit 31 after enabling IPS through the
3787 * mailbox." Moreover, the mailbox may return a bogus state,
3788 * so we need to just enable it and continue on.
3789 */
3790 } else {
3791 I915_WRITE(IPS_CTL, IPS_ENABLE);
3792 /* The bit only becomes 1 in the next vblank, so this wait here
3793 * is essentially intel_wait_for_vblank. If we don't have this
3794 * and don't wait for vblanks until the end of crtc_enable, then
3795 * the HW state readout code will complain that the expected
3796 * IPS_CTL value is not the one we read. */
3797 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3798 DRM_ERROR("Timed out waiting for IPS enable\n");
3799 }
3800 }
3801
3802 void hsw_disable_ips(struct intel_crtc *crtc)
3803 {
3804 struct drm_device *dev = crtc->base.dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806
3807 if (!crtc->config.ips_enabled)
3808 return;
3809
3810 assert_plane_enabled(dev_priv, crtc->plane);
3811 if (IS_BROADWELL(dev)) {
3812 mutex_lock(&dev_priv->rps.hw_lock);
3813 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3814 mutex_unlock(&dev_priv->rps.hw_lock);
3815 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3816 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3817 DRM_ERROR("Timed out waiting for IPS disable\n");
3818 } else {
3819 I915_WRITE(IPS_CTL, 0);
3820 POSTING_READ(IPS_CTL);
3821 }
3822
3823 /* We need to wait for a vblank before we can disable the plane. */
3824 intel_wait_for_vblank(dev, crtc->pipe);
3825 }
3826
3827 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3828 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3829 {
3830 struct drm_device *dev = crtc->dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3833 enum pipe pipe = intel_crtc->pipe;
3834 int palreg = PALETTE(pipe);
3835 int i;
3836 bool reenable_ips = false;
3837
3838 /* The clocks have to be on to load the palette. */
3839 if (!crtc->enabled || !intel_crtc->active)
3840 return;
3841
3842 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3843 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3844 assert_dsi_pll_enabled(dev_priv);
3845 else
3846 assert_pll_enabled(dev_priv, pipe);
3847 }
3848
3849 /* use legacy palette for Ironlake */
3850 if (HAS_PCH_SPLIT(dev))
3851 palreg = LGC_PALETTE(pipe);
3852
3853 /* Workaround : Do not read or write the pipe palette/gamma data while
3854 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3855 */
3856 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3857 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3858 GAMMA_MODE_MODE_SPLIT)) {
3859 hsw_disable_ips(intel_crtc);
3860 reenable_ips = true;
3861 }
3862
3863 for (i = 0; i < 256; i++) {
3864 I915_WRITE(palreg + 4 * i,
3865 (intel_crtc->lut_r[i] << 16) |
3866 (intel_crtc->lut_g[i] << 8) |
3867 intel_crtc->lut_b[i]);
3868 }
3869
3870 if (reenable_ips)
3871 hsw_enable_ips(intel_crtc);
3872 }
3873
3874 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3875 {
3876 if (!enable && intel_crtc->overlay) {
3877 struct drm_device *dev = intel_crtc->base.dev;
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879
3880 mutex_lock(&dev->struct_mutex);
3881 dev_priv->mm.interruptible = false;
3882 (void) intel_overlay_switch_off(intel_crtc->overlay);
3883 dev_priv->mm.interruptible = true;
3884 mutex_unlock(&dev->struct_mutex);
3885 }
3886
3887 /* Let userspace switch the overlay on again. In most cases userspace
3888 * has to recompute where to put it anyway.
3889 */
3890 }
3891
3892 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3893 {
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897 int pipe = intel_crtc->pipe;
3898 int plane = intel_crtc->plane;
3899
3900 drm_vblank_on(dev, pipe);
3901
3902 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3903 intel_enable_planes(crtc);
3904 intel_crtc_update_cursor(crtc, true);
3905 intel_crtc_dpms_overlay(intel_crtc, true);
3906
3907 hsw_enable_ips(intel_crtc);
3908
3909 mutex_lock(&dev->struct_mutex);
3910 intel_update_fbc(dev);
3911 mutex_unlock(&dev->struct_mutex);
3912
3913 /*
3914 * FIXME: Once we grow proper nuclear flip support out of this we need
3915 * to compute the mask of flip planes precisely. For the time being
3916 * consider this a flip from a NULL plane.
3917 */
3918 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3919 }
3920
3921 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3922 {
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3926 int pipe = intel_crtc->pipe;
3927 int plane = intel_crtc->plane;
3928
3929 intel_crtc_wait_for_pending_flips(crtc);
3930
3931 if (dev_priv->fbc.plane == plane)
3932 intel_disable_fbc(dev);
3933
3934 hsw_disable_ips(intel_crtc);
3935
3936 intel_crtc_dpms_overlay(intel_crtc, false);
3937 intel_crtc_update_cursor(crtc, false);
3938 intel_disable_planes(crtc);
3939 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3940
3941 /*
3942 * FIXME: Once we grow proper nuclear flip support out of this we need
3943 * to compute the mask of flip planes precisely. For the time being
3944 * consider this a flip to a NULL plane.
3945 */
3946 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3947
3948 drm_vblank_off(dev, pipe);
3949 }
3950
3951 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3952 {
3953 struct drm_device *dev = crtc->dev;
3954 struct drm_i915_private *dev_priv = dev->dev_private;
3955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3956 struct intel_encoder *encoder;
3957 int pipe = intel_crtc->pipe;
3958 enum plane plane = intel_crtc->plane;
3959
3960 WARN_ON(!crtc->enabled);
3961
3962 if (intel_crtc->active)
3963 return;
3964
3965 if (intel_crtc->config.has_pch_encoder)
3966 intel_prepare_shared_dpll(intel_crtc);
3967
3968 if (intel_crtc->config.has_dp_encoder)
3969 intel_dp_set_m_n(intel_crtc);
3970
3971 intel_set_pipe_timings(intel_crtc);
3972
3973 if (intel_crtc->config.has_pch_encoder) {
3974 intel_cpu_transcoder_set_m_n(intel_crtc,
3975 &intel_crtc->config.fdi_m_n);
3976 }
3977
3978 ironlake_set_pipeconf(crtc);
3979
3980 /* Set up the display plane register */
3981 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3982 POSTING_READ(DSPCNTR(plane));
3983
3984 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3985 crtc->x, crtc->y);
3986
3987 intel_crtc->active = true;
3988
3989 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3990 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3991
3992 for_each_encoder_on_crtc(dev, crtc, encoder)
3993 if (encoder->pre_enable)
3994 encoder->pre_enable(encoder);
3995
3996 if (intel_crtc->config.has_pch_encoder) {
3997 /* Note: FDI PLL enabling _must_ be done before we enable the
3998 * cpu pipes, hence this is separate from all the other fdi/pch
3999 * enabling. */
4000 ironlake_fdi_pll_enable(intel_crtc);
4001 } else {
4002 assert_fdi_tx_disabled(dev_priv, pipe);
4003 assert_fdi_rx_disabled(dev_priv, pipe);
4004 }
4005
4006 ironlake_pfit_enable(intel_crtc);
4007
4008 /*
4009 * On ILK+ LUT must be loaded before the pipe is running but with
4010 * clocks enabled
4011 */
4012 intel_crtc_load_lut(crtc);
4013
4014 intel_update_watermarks(crtc);
4015 intel_enable_pipe(intel_crtc);
4016
4017 if (intel_crtc->config.has_pch_encoder)
4018 ironlake_pch_enable(crtc);
4019
4020 for_each_encoder_on_crtc(dev, crtc, encoder)
4021 encoder->enable(encoder);
4022
4023 if (HAS_PCH_CPT(dev))
4024 cpt_verify_modeset(dev, intel_crtc->pipe);
4025
4026 intel_crtc_enable_planes(crtc);
4027 }
4028
4029 /* IPS only exists on ULT machines and is tied to pipe A. */
4030 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4031 {
4032 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4033 }
4034
4035 /*
4036 * This implements the workaround described in the "notes" section of the mode
4037 * set sequence documentation. When going from no pipes or single pipe to
4038 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4039 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4040 */
4041 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4042 {
4043 struct drm_device *dev = crtc->base.dev;
4044 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4045
4046 /* We want to get the other_active_crtc only if there's only 1 other
4047 * active crtc. */
4048 for_each_intel_crtc(dev, crtc_it) {
4049 if (!crtc_it->active || crtc_it == crtc)
4050 continue;
4051
4052 if (other_active_crtc)
4053 return;
4054
4055 other_active_crtc = crtc_it;
4056 }
4057 if (!other_active_crtc)
4058 return;
4059
4060 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4061 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4062 }
4063
4064 static void haswell_crtc_enable(struct drm_crtc *crtc)
4065 {
4066 struct drm_device *dev = crtc->dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069 struct intel_encoder *encoder;
4070 int pipe = intel_crtc->pipe;
4071 enum plane plane = intel_crtc->plane;
4072
4073 WARN_ON(!crtc->enabled);
4074
4075 if (intel_crtc->active)
4076 return;
4077
4078 if (intel_crtc_to_shared_dpll(intel_crtc))
4079 intel_enable_shared_dpll(intel_crtc);
4080
4081 if (intel_crtc->config.has_dp_encoder)
4082 intel_dp_set_m_n(intel_crtc);
4083
4084 intel_set_pipe_timings(intel_crtc);
4085
4086 if (intel_crtc->config.has_pch_encoder) {
4087 intel_cpu_transcoder_set_m_n(intel_crtc,
4088 &intel_crtc->config.fdi_m_n);
4089 }
4090
4091 haswell_set_pipeconf(crtc);
4092
4093 intel_set_pipe_csc(crtc);
4094
4095 /* Set up the display plane register */
4096 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4097 POSTING_READ(DSPCNTR(plane));
4098
4099 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4100 crtc->x, crtc->y);
4101
4102 intel_crtc->active = true;
4103
4104 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4105 for_each_encoder_on_crtc(dev, crtc, encoder)
4106 if (encoder->pre_enable)
4107 encoder->pre_enable(encoder);
4108
4109 if (intel_crtc->config.has_pch_encoder) {
4110 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4111 dev_priv->display.fdi_link_train(crtc);
4112 }
4113
4114 intel_ddi_enable_pipe_clock(intel_crtc);
4115
4116 ironlake_pfit_enable(intel_crtc);
4117
4118 /*
4119 * On ILK+ LUT must be loaded before the pipe is running but with
4120 * clocks enabled
4121 */
4122 intel_crtc_load_lut(crtc);
4123
4124 intel_ddi_set_pipe_settings(crtc);
4125 intel_ddi_enable_transcoder_func(crtc);
4126
4127 intel_update_watermarks(crtc);
4128 intel_enable_pipe(intel_crtc);
4129
4130 if (intel_crtc->config.has_pch_encoder)
4131 lpt_pch_enable(crtc);
4132
4133 for_each_encoder_on_crtc(dev, crtc, encoder) {
4134 encoder->enable(encoder);
4135 intel_opregion_notify_encoder(encoder, true);
4136 }
4137
4138 /* If we change the relative order between pipe/planes enabling, we need
4139 * to change the workaround. */
4140 haswell_mode_set_planes_workaround(intel_crtc);
4141 intel_crtc_enable_planes(crtc);
4142 }
4143
4144 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4145 {
4146 struct drm_device *dev = crtc->base.dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int pipe = crtc->pipe;
4149
4150 /* To avoid upsetting the power well on haswell only disable the pfit if
4151 * it's in use. The hw state code will make sure we get this right. */
4152 if (crtc->config.pch_pfit.enabled) {
4153 I915_WRITE(PF_CTL(pipe), 0);
4154 I915_WRITE(PF_WIN_POS(pipe), 0);
4155 I915_WRITE(PF_WIN_SZ(pipe), 0);
4156 }
4157 }
4158
4159 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4160 {
4161 struct drm_device *dev = crtc->dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4164 struct intel_encoder *encoder;
4165 int pipe = intel_crtc->pipe;
4166 u32 reg, temp;
4167
4168 if (!intel_crtc->active)
4169 return;
4170
4171 intel_crtc_disable_planes(crtc);
4172
4173 for_each_encoder_on_crtc(dev, crtc, encoder)
4174 encoder->disable(encoder);
4175
4176 if (intel_crtc->config.has_pch_encoder)
4177 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4178
4179 intel_disable_pipe(dev_priv, pipe);
4180
4181 ironlake_pfit_disable(intel_crtc);
4182
4183 for_each_encoder_on_crtc(dev, crtc, encoder)
4184 if (encoder->post_disable)
4185 encoder->post_disable(encoder);
4186
4187 if (intel_crtc->config.has_pch_encoder) {
4188 ironlake_fdi_disable(crtc);
4189
4190 ironlake_disable_pch_transcoder(dev_priv, pipe);
4191 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4192
4193 if (HAS_PCH_CPT(dev)) {
4194 /* disable TRANS_DP_CTL */
4195 reg = TRANS_DP_CTL(pipe);
4196 temp = I915_READ(reg);
4197 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4198 TRANS_DP_PORT_SEL_MASK);
4199 temp |= TRANS_DP_PORT_SEL_NONE;
4200 I915_WRITE(reg, temp);
4201
4202 /* disable DPLL_SEL */
4203 temp = I915_READ(PCH_DPLL_SEL);
4204 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4205 I915_WRITE(PCH_DPLL_SEL, temp);
4206 }
4207
4208 /* disable PCH DPLL */
4209 intel_disable_shared_dpll(intel_crtc);
4210
4211 ironlake_fdi_pll_disable(intel_crtc);
4212 }
4213
4214 intel_crtc->active = false;
4215 intel_update_watermarks(crtc);
4216
4217 mutex_lock(&dev->struct_mutex);
4218 intel_update_fbc(dev);
4219 mutex_unlock(&dev->struct_mutex);
4220 }
4221
4222 static void haswell_crtc_disable(struct drm_crtc *crtc)
4223 {
4224 struct drm_device *dev = crtc->dev;
4225 struct drm_i915_private *dev_priv = dev->dev_private;
4226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4227 struct intel_encoder *encoder;
4228 int pipe = intel_crtc->pipe;
4229 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4230
4231 if (!intel_crtc->active)
4232 return;
4233
4234 intel_crtc_disable_planes(crtc);
4235
4236 for_each_encoder_on_crtc(dev, crtc, encoder) {
4237 intel_opregion_notify_encoder(encoder, false);
4238 encoder->disable(encoder);
4239 }
4240
4241 if (intel_crtc->config.has_pch_encoder)
4242 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4243 intel_disable_pipe(dev_priv, pipe);
4244
4245 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4246
4247 ironlake_pfit_disable(intel_crtc);
4248
4249 intel_ddi_disable_pipe_clock(intel_crtc);
4250
4251 if (intel_crtc->config.has_pch_encoder) {
4252 lpt_disable_pch_transcoder(dev_priv);
4253 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4254 intel_ddi_fdi_disable(crtc);
4255 }
4256
4257 for_each_encoder_on_crtc(dev, crtc, encoder)
4258 if (encoder->post_disable)
4259 encoder->post_disable(encoder);
4260
4261 intel_crtc->active = false;
4262 intel_update_watermarks(crtc);
4263
4264 mutex_lock(&dev->struct_mutex);
4265 intel_update_fbc(dev);
4266 mutex_unlock(&dev->struct_mutex);
4267
4268 if (intel_crtc_to_shared_dpll(intel_crtc))
4269 intel_disable_shared_dpll(intel_crtc);
4270 }
4271
4272 static void ironlake_crtc_off(struct drm_crtc *crtc)
4273 {
4274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4275 intel_put_shared_dpll(intel_crtc);
4276 }
4277
4278
4279 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4280 {
4281 struct drm_device *dev = crtc->base.dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc_config *pipe_config = &crtc->config;
4284
4285 if (!crtc->config.gmch_pfit.control)
4286 return;
4287
4288 /*
4289 * The panel fitter should only be adjusted whilst the pipe is disabled,
4290 * according to register description and PRM.
4291 */
4292 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4293 assert_pipe_disabled(dev_priv, crtc->pipe);
4294
4295 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4296 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4297
4298 /* Border color in case we don't scale up to the full screen. Black by
4299 * default, change to something else for debugging. */
4300 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4301 }
4302
4303 enum intel_display_power_domain
4304 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4305 {
4306 struct drm_device *dev = intel_encoder->base.dev;
4307 struct intel_digital_port *intel_dig_port;
4308
4309 switch (intel_encoder->type) {
4310 case INTEL_OUTPUT_UNKNOWN:
4311 /* Only DDI platforms should ever use this output type */
4312 WARN_ON_ONCE(!HAS_DDI(dev));
4313 case INTEL_OUTPUT_DISPLAYPORT:
4314 case INTEL_OUTPUT_HDMI:
4315 case INTEL_OUTPUT_EDP:
4316 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4317 switch (intel_dig_port->port) {
4318 case PORT_A:
4319 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4320 case PORT_B:
4321 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4322 case PORT_C:
4323 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4324 case PORT_D:
4325 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4326 default:
4327 WARN_ON_ONCE(1);
4328 return POWER_DOMAIN_PORT_OTHER;
4329 }
4330 case INTEL_OUTPUT_ANALOG:
4331 return POWER_DOMAIN_PORT_CRT;
4332 case INTEL_OUTPUT_DSI:
4333 return POWER_DOMAIN_PORT_DSI;
4334 default:
4335 return POWER_DOMAIN_PORT_OTHER;
4336 }
4337 }
4338
4339 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4340 {
4341 struct drm_device *dev = crtc->dev;
4342 struct intel_encoder *intel_encoder;
4343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344 enum pipe pipe = intel_crtc->pipe;
4345 unsigned long mask;
4346 enum transcoder transcoder;
4347
4348 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4349
4350 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4351 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4352 if (intel_crtc->config.pch_pfit.enabled ||
4353 intel_crtc->config.pch_pfit.force_thru)
4354 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4355
4356 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4357 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4358
4359 return mask;
4360 }
4361
4362 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4363 bool enable)
4364 {
4365 if (dev_priv->power_domains.init_power_on == enable)
4366 return;
4367
4368 if (enable)
4369 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4370 else
4371 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4372
4373 dev_priv->power_domains.init_power_on = enable;
4374 }
4375
4376 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4377 {
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4380 struct intel_crtc *crtc;
4381
4382 /*
4383 * First get all needed power domains, then put all unneeded, to avoid
4384 * any unnecessary toggling of the power wells.
4385 */
4386 for_each_intel_crtc(dev, crtc) {
4387 enum intel_display_power_domain domain;
4388
4389 if (!crtc->base.enabled)
4390 continue;
4391
4392 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4393
4394 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4395 intel_display_power_get(dev_priv, domain);
4396 }
4397
4398 for_each_intel_crtc(dev, crtc) {
4399 enum intel_display_power_domain domain;
4400
4401 for_each_power_domain(domain, crtc->enabled_power_domains)
4402 intel_display_power_put(dev_priv, domain);
4403
4404 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4405 }
4406
4407 intel_display_set_init_power(dev_priv, false);
4408 }
4409
4410 /* returns HPLL frequency in kHz */
4411 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4412 {
4413 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4414
4415 /* Obtain SKU information */
4416 mutex_lock(&dev_priv->dpio_lock);
4417 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4418 CCK_FUSE_HPLL_FREQ_MASK;
4419 mutex_unlock(&dev_priv->dpio_lock);
4420
4421 return vco_freq[hpll_freq] * 1000;
4422 }
4423
4424 static void vlv_update_cdclk(struct drm_device *dev)
4425 {
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427
4428 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4429 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4430 dev_priv->vlv_cdclk_freq);
4431
4432 /*
4433 * Program the gmbus_freq based on the cdclk frequency.
4434 * BSpec erroneously claims we should aim for 4MHz, but
4435 * in fact 1MHz is the correct frequency.
4436 */
4437 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4438 }
4439
4440 /* Adjust CDclk dividers to allow high res or save power if possible */
4441 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4442 {
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444 u32 val, cmd;
4445
4446 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4447
4448 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4449 cmd = 2;
4450 else if (cdclk == 266667)
4451 cmd = 1;
4452 else
4453 cmd = 0;
4454
4455 mutex_lock(&dev_priv->rps.hw_lock);
4456 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4457 val &= ~DSPFREQGUAR_MASK;
4458 val |= (cmd << DSPFREQGUAR_SHIFT);
4459 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4460 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4461 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4462 50)) {
4463 DRM_ERROR("timed out waiting for CDclk change\n");
4464 }
4465 mutex_unlock(&dev_priv->rps.hw_lock);
4466
4467 if (cdclk == 400000) {
4468 u32 divider, vco;
4469
4470 vco = valleyview_get_vco(dev_priv);
4471 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4472
4473 mutex_lock(&dev_priv->dpio_lock);
4474 /* adjust cdclk divider */
4475 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4476 val &= ~DISPLAY_FREQUENCY_VALUES;
4477 val |= divider;
4478 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4479
4480 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4481 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4482 50))
4483 DRM_ERROR("timed out waiting for CDclk change\n");
4484 mutex_unlock(&dev_priv->dpio_lock);
4485 }
4486
4487 mutex_lock(&dev_priv->dpio_lock);
4488 /* adjust self-refresh exit latency value */
4489 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4490 val &= ~0x7f;
4491
4492 /*
4493 * For high bandwidth configs, we set a higher latency in the bunit
4494 * so that the core display fetch happens in time to avoid underruns.
4495 */
4496 if (cdclk == 400000)
4497 val |= 4500 / 250; /* 4.5 usec */
4498 else
4499 val |= 3000 / 250; /* 3.0 usec */
4500 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4501 mutex_unlock(&dev_priv->dpio_lock);
4502
4503 vlv_update_cdclk(dev);
4504 }
4505
4506 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4507 int max_pixclk)
4508 {
4509 int vco = valleyview_get_vco(dev_priv);
4510 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4511
4512 /*
4513 * Really only a few cases to deal with, as only 4 CDclks are supported:
4514 * 200MHz
4515 * 267MHz
4516 * 320/333MHz (depends on HPLL freq)
4517 * 400MHz
4518 * So we check to see whether we're above 90% of the lower bin and
4519 * adjust if needed.
4520 *
4521 * We seem to get an unstable or solid color picture at 200MHz.
4522 * Not sure what's wrong. For now use 200MHz only when all pipes
4523 * are off.
4524 */
4525 if (max_pixclk > freq_320*9/10)
4526 return 400000;
4527 else if (max_pixclk > 266667*9/10)
4528 return freq_320;
4529 else if (max_pixclk > 0)
4530 return 266667;
4531 else
4532 return 200000;
4533 }
4534
4535 /* compute the max pixel clock for new configuration */
4536 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4537 {
4538 struct drm_device *dev = dev_priv->dev;
4539 struct intel_crtc *intel_crtc;
4540 int max_pixclk = 0;
4541
4542 for_each_intel_crtc(dev, intel_crtc) {
4543 if (intel_crtc->new_enabled)
4544 max_pixclk = max(max_pixclk,
4545 intel_crtc->new_config->adjusted_mode.crtc_clock);
4546 }
4547
4548 return max_pixclk;
4549 }
4550
4551 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4552 unsigned *prepare_pipes)
4553 {
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4555 struct intel_crtc *intel_crtc;
4556 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4557
4558 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4559 dev_priv->vlv_cdclk_freq)
4560 return;
4561
4562 /* disable/enable all currently active pipes while we change cdclk */
4563 for_each_intel_crtc(dev, intel_crtc)
4564 if (intel_crtc->base.enabled)
4565 *prepare_pipes |= (1 << intel_crtc->pipe);
4566 }
4567
4568 static void valleyview_modeset_global_resources(struct drm_device *dev)
4569 {
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4572 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4573
4574 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4575 valleyview_set_cdclk(dev, req_cdclk);
4576 modeset_update_crtc_power_domains(dev);
4577 }
4578
4579 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4580 {
4581 struct drm_device *dev = crtc->dev;
4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4584 struct intel_encoder *encoder;
4585 int pipe = intel_crtc->pipe;
4586 int plane = intel_crtc->plane;
4587 bool is_dsi;
4588 u32 dspcntr;
4589
4590 WARN_ON(!crtc->enabled);
4591
4592 if (intel_crtc->active)
4593 return;
4594
4595 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4596
4597 if (!is_dsi && !IS_CHERRYVIEW(dev))
4598 vlv_prepare_pll(intel_crtc);
4599
4600 /* Set up the display plane register */
4601 dspcntr = DISPPLANE_GAMMA_ENABLE;
4602
4603 if (intel_crtc->config.has_dp_encoder)
4604 intel_dp_set_m_n(intel_crtc);
4605
4606 intel_set_pipe_timings(intel_crtc);
4607
4608 /* pipesrc and dspsize control the size that is scaled from,
4609 * which should always be the user's requested size.
4610 */
4611 I915_WRITE(DSPSIZE(plane),
4612 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4613 (intel_crtc->config.pipe_src_w - 1));
4614 I915_WRITE(DSPPOS(plane), 0);
4615
4616 i9xx_set_pipeconf(intel_crtc);
4617
4618 I915_WRITE(DSPCNTR(plane), dspcntr);
4619 POSTING_READ(DSPCNTR(plane));
4620
4621 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4622 crtc->x, crtc->y);
4623
4624 intel_crtc->active = true;
4625
4626 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4627
4628 for_each_encoder_on_crtc(dev, crtc, encoder)
4629 if (encoder->pre_pll_enable)
4630 encoder->pre_pll_enable(encoder);
4631
4632 if (!is_dsi) {
4633 if (IS_CHERRYVIEW(dev))
4634 chv_enable_pll(intel_crtc);
4635 else
4636 vlv_enable_pll(intel_crtc);
4637 }
4638
4639 for_each_encoder_on_crtc(dev, crtc, encoder)
4640 if (encoder->pre_enable)
4641 encoder->pre_enable(encoder);
4642
4643 i9xx_pfit_enable(intel_crtc);
4644
4645 intel_crtc_load_lut(crtc);
4646
4647 intel_update_watermarks(crtc);
4648 intel_enable_pipe(intel_crtc);
4649
4650 for_each_encoder_on_crtc(dev, crtc, encoder)
4651 encoder->enable(encoder);
4652
4653 intel_crtc_enable_planes(crtc);
4654
4655 /* Underruns don't raise interrupts, so check manually. */
4656 i9xx_check_fifo_underruns(dev);
4657 }
4658
4659 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4660 {
4661 struct drm_device *dev = crtc->base.dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663
4664 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4665 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4666 }
4667
4668 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4669 {
4670 struct drm_device *dev = crtc->dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4673 struct intel_encoder *encoder;
4674 int pipe = intel_crtc->pipe;
4675 int plane = intel_crtc->plane;
4676 u32 dspcntr;
4677
4678 WARN_ON(!crtc->enabled);
4679
4680 if (intel_crtc->active)
4681 return;
4682
4683 i9xx_set_pll_dividers(intel_crtc);
4684
4685 /* Set up the display plane register */
4686 dspcntr = DISPPLANE_GAMMA_ENABLE;
4687
4688 if (pipe == 0)
4689 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4690 else
4691 dspcntr |= DISPPLANE_SEL_PIPE_B;
4692
4693 if (intel_crtc->config.has_dp_encoder)
4694 intel_dp_set_m_n(intel_crtc);
4695
4696 intel_set_pipe_timings(intel_crtc);
4697
4698 /* pipesrc and dspsize control the size that is scaled from,
4699 * which should always be the user's requested size.
4700 */
4701 I915_WRITE(DSPSIZE(plane),
4702 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4703 (intel_crtc->config.pipe_src_w - 1));
4704 I915_WRITE(DSPPOS(plane), 0);
4705
4706 i9xx_set_pipeconf(intel_crtc);
4707
4708 I915_WRITE(DSPCNTR(plane), dspcntr);
4709 POSTING_READ(DSPCNTR(plane));
4710
4711 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4712 crtc->x, crtc->y);
4713
4714 intel_crtc->active = true;
4715
4716 if (!IS_GEN2(dev))
4717 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4718
4719 for_each_encoder_on_crtc(dev, crtc, encoder)
4720 if (encoder->pre_enable)
4721 encoder->pre_enable(encoder);
4722
4723 i9xx_enable_pll(intel_crtc);
4724
4725 i9xx_pfit_enable(intel_crtc);
4726
4727 intel_crtc_load_lut(crtc);
4728
4729 intel_update_watermarks(crtc);
4730 intel_enable_pipe(intel_crtc);
4731
4732 for_each_encoder_on_crtc(dev, crtc, encoder)
4733 encoder->enable(encoder);
4734
4735 intel_crtc_enable_planes(crtc);
4736
4737 /*
4738 * Gen2 reports pipe underruns whenever all planes are disabled.
4739 * So don't enable underrun reporting before at least some planes
4740 * are enabled.
4741 * FIXME: Need to fix the logic to work when we turn off all planes
4742 * but leave the pipe running.
4743 */
4744 if (IS_GEN2(dev))
4745 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4746
4747 /* Underruns don't raise interrupts, so check manually. */
4748 i9xx_check_fifo_underruns(dev);
4749 }
4750
4751 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4752 {
4753 struct drm_device *dev = crtc->base.dev;
4754 struct drm_i915_private *dev_priv = dev->dev_private;
4755
4756 if (!crtc->config.gmch_pfit.control)
4757 return;
4758
4759 assert_pipe_disabled(dev_priv, crtc->pipe);
4760
4761 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4762 I915_READ(PFIT_CONTROL));
4763 I915_WRITE(PFIT_CONTROL, 0);
4764 }
4765
4766 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4767 {
4768 struct drm_device *dev = crtc->dev;
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4771 struct intel_encoder *encoder;
4772 int pipe = intel_crtc->pipe;
4773
4774 if (!intel_crtc->active)
4775 return;
4776
4777 /*
4778 * Gen2 reports pipe underruns whenever all planes are disabled.
4779 * So diasble underrun reporting before all the planes get disabled.
4780 * FIXME: Need to fix the logic to work when we turn off all planes
4781 * but leave the pipe running.
4782 */
4783 if (IS_GEN2(dev))
4784 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4785
4786 /*
4787 * Vblank time updates from the shadow to live plane control register
4788 * are blocked if the memory self-refresh mode is active at that
4789 * moment. So to make sure the plane gets truly disabled, disable
4790 * first the self-refresh mode. The self-refresh enable bit in turn
4791 * will be checked/applied by the HW only at the next frame start
4792 * event which is after the vblank start event, so we need to have a
4793 * wait-for-vblank between disabling the plane and the pipe.
4794 */
4795 intel_set_memory_cxsr(dev_priv, false);
4796 intel_crtc_disable_planes(crtc);
4797
4798 for_each_encoder_on_crtc(dev, crtc, encoder)
4799 encoder->disable(encoder);
4800
4801 /*
4802 * On gen2 planes are double buffered but the pipe isn't, so we must
4803 * wait for planes to fully turn off before disabling the pipe.
4804 * We also need to wait on all gmch platforms because of the
4805 * self-refresh mode constraint explained above.
4806 */
4807 intel_wait_for_vblank(dev, pipe);
4808
4809 intel_disable_pipe(dev_priv, pipe);
4810
4811 i9xx_pfit_disable(intel_crtc);
4812
4813 for_each_encoder_on_crtc(dev, crtc, encoder)
4814 if (encoder->post_disable)
4815 encoder->post_disable(encoder);
4816
4817 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4818 if (IS_CHERRYVIEW(dev))
4819 chv_disable_pll(dev_priv, pipe);
4820 else if (IS_VALLEYVIEW(dev))
4821 vlv_disable_pll(dev_priv, pipe);
4822 else
4823 i9xx_disable_pll(dev_priv, pipe);
4824 }
4825
4826 if (!IS_GEN2(dev))
4827 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4828
4829 intel_crtc->active = false;
4830 intel_update_watermarks(crtc);
4831
4832 mutex_lock(&dev->struct_mutex);
4833 intel_update_fbc(dev);
4834 mutex_unlock(&dev->struct_mutex);
4835 }
4836
4837 static void i9xx_crtc_off(struct drm_crtc *crtc)
4838 {
4839 }
4840
4841 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4842 bool enabled)
4843 {
4844 struct drm_device *dev = crtc->dev;
4845 struct drm_i915_master_private *master_priv;
4846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4847 int pipe = intel_crtc->pipe;
4848
4849 if (!dev->primary->master)
4850 return;
4851
4852 master_priv = dev->primary->master->driver_priv;
4853 if (!master_priv->sarea_priv)
4854 return;
4855
4856 switch (pipe) {
4857 case 0:
4858 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4859 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4860 break;
4861 case 1:
4862 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4863 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4864 break;
4865 default:
4866 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4867 break;
4868 }
4869 }
4870
4871 /* Master function to enable/disable CRTC and corresponding power wells */
4872 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4873 {
4874 struct drm_device *dev = crtc->dev;
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4877 enum intel_display_power_domain domain;
4878 unsigned long domains;
4879
4880 if (enable) {
4881 if (!intel_crtc->active) {
4882 domains = get_crtc_power_domains(crtc);
4883 for_each_power_domain(domain, domains)
4884 intel_display_power_get(dev_priv, domain);
4885 intel_crtc->enabled_power_domains = domains;
4886
4887 dev_priv->display.crtc_enable(crtc);
4888 }
4889 } else {
4890 if (intel_crtc->active) {
4891 dev_priv->display.crtc_disable(crtc);
4892
4893 domains = intel_crtc->enabled_power_domains;
4894 for_each_power_domain(domain, domains)
4895 intel_display_power_put(dev_priv, domain);
4896 intel_crtc->enabled_power_domains = 0;
4897 }
4898 }
4899 }
4900
4901 /**
4902 * Sets the power management mode of the pipe and plane.
4903 */
4904 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4905 {
4906 struct drm_device *dev = crtc->dev;
4907 struct intel_encoder *intel_encoder;
4908 bool enable = false;
4909
4910 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4911 enable |= intel_encoder->connectors_active;
4912
4913 intel_crtc_control(crtc, enable);
4914
4915 intel_crtc_update_sarea(crtc, enable);
4916 }
4917
4918 static void intel_crtc_disable(struct drm_crtc *crtc)
4919 {
4920 struct drm_device *dev = crtc->dev;
4921 struct drm_connector *connector;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4924 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4925
4926 /* crtc should still be enabled when we disable it. */
4927 WARN_ON(!crtc->enabled);
4928
4929 dev_priv->display.crtc_disable(crtc);
4930 intel_crtc_update_sarea(crtc, false);
4931 dev_priv->display.off(crtc);
4932
4933 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4934 assert_cursor_disabled(dev_priv, pipe);
4935 assert_pipe_disabled(dev->dev_private, pipe);
4936
4937 if (crtc->primary->fb) {
4938 mutex_lock(&dev->struct_mutex);
4939 intel_unpin_fb_obj(old_obj);
4940 i915_gem_track_fb(old_obj, NULL,
4941 INTEL_FRONTBUFFER_PRIMARY(pipe));
4942 mutex_unlock(&dev->struct_mutex);
4943 crtc->primary->fb = NULL;
4944 }
4945
4946 /* Update computed state. */
4947 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4948 if (!connector->encoder || !connector->encoder->crtc)
4949 continue;
4950
4951 if (connector->encoder->crtc != crtc)
4952 continue;
4953
4954 connector->dpms = DRM_MODE_DPMS_OFF;
4955 to_intel_encoder(connector->encoder)->connectors_active = false;
4956 }
4957 }
4958
4959 void intel_encoder_destroy(struct drm_encoder *encoder)
4960 {
4961 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4962
4963 drm_encoder_cleanup(encoder);
4964 kfree(intel_encoder);
4965 }
4966
4967 /* Simple dpms helper for encoders with just one connector, no cloning and only
4968 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4969 * state of the entire output pipe. */
4970 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4971 {
4972 if (mode == DRM_MODE_DPMS_ON) {
4973 encoder->connectors_active = true;
4974
4975 intel_crtc_update_dpms(encoder->base.crtc);
4976 } else {
4977 encoder->connectors_active = false;
4978
4979 intel_crtc_update_dpms(encoder->base.crtc);
4980 }
4981 }
4982
4983 /* Cross check the actual hw state with our own modeset state tracking (and it's
4984 * internal consistency). */
4985 static void intel_connector_check_state(struct intel_connector *connector)
4986 {
4987 if (connector->get_hw_state(connector)) {
4988 struct intel_encoder *encoder = connector->encoder;
4989 struct drm_crtc *crtc;
4990 bool encoder_enabled;
4991 enum pipe pipe;
4992
4993 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4994 connector->base.base.id,
4995 connector->base.name);
4996
4997 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4998 "wrong connector dpms state\n");
4999 WARN(connector->base.encoder != &encoder->base,
5000 "active connector not linked to encoder\n");
5001 WARN(!encoder->connectors_active,
5002 "encoder->connectors_active not set\n");
5003
5004 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5005 WARN(!encoder_enabled, "encoder not enabled\n");
5006 if (WARN_ON(!encoder->base.crtc))
5007 return;
5008
5009 crtc = encoder->base.crtc;
5010
5011 WARN(!crtc->enabled, "crtc not enabled\n");
5012 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5013 WARN(pipe != to_intel_crtc(crtc)->pipe,
5014 "encoder active on the wrong pipe\n");
5015 }
5016 }
5017
5018 /* Even simpler default implementation, if there's really no special case to
5019 * consider. */
5020 void intel_connector_dpms(struct drm_connector *connector, int mode)
5021 {
5022 /* All the simple cases only support two dpms states. */
5023 if (mode != DRM_MODE_DPMS_ON)
5024 mode = DRM_MODE_DPMS_OFF;
5025
5026 if (mode == connector->dpms)
5027 return;
5028
5029 connector->dpms = mode;
5030
5031 /* Only need to change hw state when actually enabled */
5032 if (connector->encoder)
5033 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5034
5035 intel_modeset_check_state(connector->dev);
5036 }
5037
5038 /* Simple connector->get_hw_state implementation for encoders that support only
5039 * one connector and no cloning and hence the encoder state determines the state
5040 * of the connector. */
5041 bool intel_connector_get_hw_state(struct intel_connector *connector)
5042 {
5043 enum pipe pipe = 0;
5044 struct intel_encoder *encoder = connector->encoder;
5045
5046 return encoder->get_hw_state(encoder, &pipe);
5047 }
5048
5049 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5050 struct intel_crtc_config *pipe_config)
5051 {
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 struct intel_crtc *pipe_B_crtc =
5054 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5055
5056 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5057 pipe_name(pipe), pipe_config->fdi_lanes);
5058 if (pipe_config->fdi_lanes > 4) {
5059 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5060 pipe_name(pipe), pipe_config->fdi_lanes);
5061 return false;
5062 }
5063
5064 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5065 if (pipe_config->fdi_lanes > 2) {
5066 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5067 pipe_config->fdi_lanes);
5068 return false;
5069 } else {
5070 return true;
5071 }
5072 }
5073
5074 if (INTEL_INFO(dev)->num_pipes == 2)
5075 return true;
5076
5077 /* Ivybridge 3 pipe is really complicated */
5078 switch (pipe) {
5079 case PIPE_A:
5080 return true;
5081 case PIPE_B:
5082 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5083 pipe_config->fdi_lanes > 2) {
5084 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5085 pipe_name(pipe), pipe_config->fdi_lanes);
5086 return false;
5087 }
5088 return true;
5089 case PIPE_C:
5090 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5091 pipe_B_crtc->config.fdi_lanes <= 2) {
5092 if (pipe_config->fdi_lanes > 2) {
5093 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5094 pipe_name(pipe), pipe_config->fdi_lanes);
5095 return false;
5096 }
5097 } else {
5098 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5099 return false;
5100 }
5101 return true;
5102 default:
5103 BUG();
5104 }
5105 }
5106
5107 #define RETRY 1
5108 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5109 struct intel_crtc_config *pipe_config)
5110 {
5111 struct drm_device *dev = intel_crtc->base.dev;
5112 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5113 int lane, link_bw, fdi_dotclock;
5114 bool setup_ok, needs_recompute = false;
5115
5116 retry:
5117 /* FDI is a binary signal running at ~2.7GHz, encoding
5118 * each output octet as 10 bits. The actual frequency
5119 * is stored as a divider into a 100MHz clock, and the
5120 * mode pixel clock is stored in units of 1KHz.
5121 * Hence the bw of each lane in terms of the mode signal
5122 * is:
5123 */
5124 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5125
5126 fdi_dotclock = adjusted_mode->crtc_clock;
5127
5128 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5129 pipe_config->pipe_bpp);
5130
5131 pipe_config->fdi_lanes = lane;
5132
5133 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5134 link_bw, &pipe_config->fdi_m_n);
5135
5136 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5137 intel_crtc->pipe, pipe_config);
5138 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5139 pipe_config->pipe_bpp -= 2*3;
5140 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5141 pipe_config->pipe_bpp);
5142 needs_recompute = true;
5143 pipe_config->bw_constrained = true;
5144
5145 goto retry;
5146 }
5147
5148 if (needs_recompute)
5149 return RETRY;
5150
5151 return setup_ok ? 0 : -EINVAL;
5152 }
5153
5154 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5155 struct intel_crtc_config *pipe_config)
5156 {
5157 pipe_config->ips_enabled = i915.enable_ips &&
5158 hsw_crtc_supports_ips(crtc) &&
5159 pipe_config->pipe_bpp <= 24;
5160 }
5161
5162 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5163 struct intel_crtc_config *pipe_config)
5164 {
5165 struct drm_device *dev = crtc->base.dev;
5166 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5167
5168 /* FIXME should check pixel clock limits on all platforms */
5169 if (INTEL_INFO(dev)->gen < 4) {
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 int clock_limit =
5172 dev_priv->display.get_display_clock_speed(dev);
5173
5174 /*
5175 * Enable pixel doubling when the dot clock
5176 * is > 90% of the (display) core speed.
5177 *
5178 * GDG double wide on either pipe,
5179 * otherwise pipe A only.
5180 */
5181 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5182 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5183 clock_limit *= 2;
5184 pipe_config->double_wide = true;
5185 }
5186
5187 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5188 return -EINVAL;
5189 }
5190
5191 /*
5192 * Pipe horizontal size must be even in:
5193 * - DVO ganged mode
5194 * - LVDS dual channel mode
5195 * - Double wide pipe
5196 */
5197 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5198 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5199 pipe_config->pipe_src_w &= ~1;
5200
5201 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5202 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5203 */
5204 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5205 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5206 return -EINVAL;
5207
5208 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5209 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5210 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5211 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5212 * for lvds. */
5213 pipe_config->pipe_bpp = 8*3;
5214 }
5215
5216 if (HAS_IPS(dev))
5217 hsw_compute_ips_config(crtc, pipe_config);
5218
5219 /*
5220 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5221 * old clock survives for now.
5222 */
5223 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5224 pipe_config->shared_dpll = crtc->config.shared_dpll;
5225
5226 if (pipe_config->has_pch_encoder)
5227 return ironlake_fdi_compute_config(crtc, pipe_config);
5228
5229 return 0;
5230 }
5231
5232 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5233 {
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 int vco = valleyview_get_vco(dev_priv);
5236 u32 val;
5237 int divider;
5238
5239 mutex_lock(&dev_priv->dpio_lock);
5240 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5241 mutex_unlock(&dev_priv->dpio_lock);
5242
5243 divider = val & DISPLAY_FREQUENCY_VALUES;
5244
5245 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5246 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5247 "cdclk change in progress\n");
5248
5249 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5250 }
5251
5252 static int i945_get_display_clock_speed(struct drm_device *dev)
5253 {
5254 return 400000;
5255 }
5256
5257 static int i915_get_display_clock_speed(struct drm_device *dev)
5258 {
5259 return 333000;
5260 }
5261
5262 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5263 {
5264 return 200000;
5265 }
5266
5267 static int pnv_get_display_clock_speed(struct drm_device *dev)
5268 {
5269 u16 gcfgc = 0;
5270
5271 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5272
5273 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5274 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5275 return 267000;
5276 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5277 return 333000;
5278 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5279 return 444000;
5280 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5281 return 200000;
5282 default:
5283 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5284 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5285 return 133000;
5286 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5287 return 167000;
5288 }
5289 }
5290
5291 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5292 {
5293 u16 gcfgc = 0;
5294
5295 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5296
5297 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5298 return 133000;
5299 else {
5300 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5301 case GC_DISPLAY_CLOCK_333_MHZ:
5302 return 333000;
5303 default:
5304 case GC_DISPLAY_CLOCK_190_200_MHZ:
5305 return 190000;
5306 }
5307 }
5308 }
5309
5310 static int i865_get_display_clock_speed(struct drm_device *dev)
5311 {
5312 return 266000;
5313 }
5314
5315 static int i855_get_display_clock_speed(struct drm_device *dev)
5316 {
5317 u16 hpllcc = 0;
5318 /* Assume that the hardware is in the high speed state. This
5319 * should be the default.
5320 */
5321 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5322 case GC_CLOCK_133_200:
5323 case GC_CLOCK_100_200:
5324 return 200000;
5325 case GC_CLOCK_166_250:
5326 return 250000;
5327 case GC_CLOCK_100_133:
5328 return 133000;
5329 }
5330
5331 /* Shouldn't happen */
5332 return 0;
5333 }
5334
5335 static int i830_get_display_clock_speed(struct drm_device *dev)
5336 {
5337 return 133000;
5338 }
5339
5340 static void
5341 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5342 {
5343 while (*num > DATA_LINK_M_N_MASK ||
5344 *den > DATA_LINK_M_N_MASK) {
5345 *num >>= 1;
5346 *den >>= 1;
5347 }
5348 }
5349
5350 static void compute_m_n(unsigned int m, unsigned int n,
5351 uint32_t *ret_m, uint32_t *ret_n)
5352 {
5353 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5354 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5355 intel_reduce_m_n_ratio(ret_m, ret_n);
5356 }
5357
5358 void
5359 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5360 int pixel_clock, int link_clock,
5361 struct intel_link_m_n *m_n)
5362 {
5363 m_n->tu = 64;
5364
5365 compute_m_n(bits_per_pixel * pixel_clock,
5366 link_clock * nlanes * 8,
5367 &m_n->gmch_m, &m_n->gmch_n);
5368
5369 compute_m_n(pixel_clock, link_clock,
5370 &m_n->link_m, &m_n->link_n);
5371 }
5372
5373 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5374 {
5375 if (i915.panel_use_ssc >= 0)
5376 return i915.panel_use_ssc != 0;
5377 return dev_priv->vbt.lvds_use_ssc
5378 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5379 }
5380
5381 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5382 {
5383 struct drm_device *dev = crtc->dev;
5384 struct drm_i915_private *dev_priv = dev->dev_private;
5385 int refclk;
5386
5387 if (IS_VALLEYVIEW(dev)) {
5388 refclk = 100000;
5389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5390 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5391 refclk = dev_priv->vbt.lvds_ssc_freq;
5392 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5393 } else if (!IS_GEN2(dev)) {
5394 refclk = 96000;
5395 } else {
5396 refclk = 48000;
5397 }
5398
5399 return refclk;
5400 }
5401
5402 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5403 {
5404 return (1 << dpll->n) << 16 | dpll->m2;
5405 }
5406
5407 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5408 {
5409 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5410 }
5411
5412 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5413 intel_clock_t *reduced_clock)
5414 {
5415 struct drm_device *dev = crtc->base.dev;
5416 u32 fp, fp2 = 0;
5417
5418 if (IS_PINEVIEW(dev)) {
5419 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5420 if (reduced_clock)
5421 fp2 = pnv_dpll_compute_fp(reduced_clock);
5422 } else {
5423 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5424 if (reduced_clock)
5425 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5426 }
5427
5428 crtc->config.dpll_hw_state.fp0 = fp;
5429
5430 crtc->lowfreq_avail = false;
5431 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5432 reduced_clock && i915.powersave) {
5433 crtc->config.dpll_hw_state.fp1 = fp2;
5434 crtc->lowfreq_avail = true;
5435 } else {
5436 crtc->config.dpll_hw_state.fp1 = fp;
5437 }
5438 }
5439
5440 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5441 pipe)
5442 {
5443 u32 reg_val;
5444
5445 /*
5446 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5447 * and set it to a reasonable value instead.
5448 */
5449 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5450 reg_val &= 0xffffff00;
5451 reg_val |= 0x00000030;
5452 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5453
5454 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5455 reg_val &= 0x8cffffff;
5456 reg_val = 0x8c000000;
5457 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5458
5459 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5460 reg_val &= 0xffffff00;
5461 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5462
5463 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5464 reg_val &= 0x00ffffff;
5465 reg_val |= 0xb0000000;
5466 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5467 }
5468
5469 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5470 struct intel_link_m_n *m_n)
5471 {
5472 struct drm_device *dev = crtc->base.dev;
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 int pipe = crtc->pipe;
5475
5476 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5477 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5478 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5479 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5480 }
5481
5482 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5483 struct intel_link_m_n *m_n)
5484 {
5485 struct drm_device *dev = crtc->base.dev;
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487 int pipe = crtc->pipe;
5488 enum transcoder transcoder = crtc->config.cpu_transcoder;
5489
5490 if (INTEL_INFO(dev)->gen >= 5) {
5491 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5492 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5493 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5494 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5495 } else {
5496 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5497 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5498 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5499 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5500 }
5501 }
5502
5503 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5504 {
5505 if (crtc->config.has_pch_encoder)
5506 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5507 else
5508 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5509 }
5510
5511 static void vlv_update_pll(struct intel_crtc *crtc)
5512 {
5513 u32 dpll, dpll_md;
5514
5515 /*
5516 * Enable DPIO clock input. We should never disable the reference
5517 * clock for pipe B, since VGA hotplug / manual detection depends
5518 * on it.
5519 */
5520 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5521 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5522 /* We should never disable this, set it here for state tracking */
5523 if (crtc->pipe == PIPE_B)
5524 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5525 dpll |= DPLL_VCO_ENABLE;
5526 crtc->config.dpll_hw_state.dpll = dpll;
5527
5528 dpll_md = (crtc->config.pixel_multiplier - 1)
5529 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5530 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5531 }
5532
5533 static void vlv_prepare_pll(struct intel_crtc *crtc)
5534 {
5535 struct drm_device *dev = crtc->base.dev;
5536 struct drm_i915_private *dev_priv = dev->dev_private;
5537 int pipe = crtc->pipe;
5538 u32 mdiv;
5539 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5540 u32 coreclk, reg_val;
5541
5542 mutex_lock(&dev_priv->dpio_lock);
5543
5544 bestn = crtc->config.dpll.n;
5545 bestm1 = crtc->config.dpll.m1;
5546 bestm2 = crtc->config.dpll.m2;
5547 bestp1 = crtc->config.dpll.p1;
5548 bestp2 = crtc->config.dpll.p2;
5549
5550 /* See eDP HDMI DPIO driver vbios notes doc */
5551
5552 /* PLL B needs special handling */
5553 if (pipe == PIPE_B)
5554 vlv_pllb_recal_opamp(dev_priv, pipe);
5555
5556 /* Set up Tx target for periodic Rcomp update */
5557 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5558
5559 /* Disable target IRef on PLL */
5560 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5561 reg_val &= 0x00ffffff;
5562 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5563
5564 /* Disable fast lock */
5565 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5566
5567 /* Set idtafcrecal before PLL is enabled */
5568 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5569 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5570 mdiv |= ((bestn << DPIO_N_SHIFT));
5571 mdiv |= (1 << DPIO_K_SHIFT);
5572
5573 /*
5574 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5575 * but we don't support that).
5576 * Note: don't use the DAC post divider as it seems unstable.
5577 */
5578 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5579 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5580
5581 mdiv |= DPIO_ENABLE_CALIBRATION;
5582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5583
5584 /* Set HBR and RBR LPF coefficients */
5585 if (crtc->config.port_clock == 162000 ||
5586 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5587 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5588 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5589 0x009f0003);
5590 else
5591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5592 0x00d0000f);
5593
5594 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5595 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5596 /* Use SSC source */
5597 if (pipe == PIPE_A)
5598 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5599 0x0df40000);
5600 else
5601 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5602 0x0df70000);
5603 } else { /* HDMI or VGA */
5604 /* Use bend source */
5605 if (pipe == PIPE_A)
5606 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5607 0x0df70000);
5608 else
5609 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5610 0x0df40000);
5611 }
5612
5613 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5614 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5615 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5616 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5617 coreclk |= 0x01000000;
5618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5619
5620 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5621 mutex_unlock(&dev_priv->dpio_lock);
5622 }
5623
5624 static void chv_update_pll(struct intel_crtc *crtc)
5625 {
5626 struct drm_device *dev = crtc->base.dev;
5627 struct drm_i915_private *dev_priv = dev->dev_private;
5628 int pipe = crtc->pipe;
5629 int dpll_reg = DPLL(crtc->pipe);
5630 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5631 u32 loopfilter, intcoeff;
5632 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5633 int refclk;
5634
5635 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5636 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5637 DPLL_VCO_ENABLE;
5638 if (pipe != PIPE_A)
5639 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5640
5641 crtc->config.dpll_hw_state.dpll_md =
5642 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5643
5644 bestn = crtc->config.dpll.n;
5645 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5646 bestm1 = crtc->config.dpll.m1;
5647 bestm2 = crtc->config.dpll.m2 >> 22;
5648 bestp1 = crtc->config.dpll.p1;
5649 bestp2 = crtc->config.dpll.p2;
5650
5651 /*
5652 * Enable Refclk and SSC
5653 */
5654 I915_WRITE(dpll_reg,
5655 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5656
5657 mutex_lock(&dev_priv->dpio_lock);
5658
5659 /* p1 and p2 divider */
5660 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5661 5 << DPIO_CHV_S1_DIV_SHIFT |
5662 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5663 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5664 1 << DPIO_CHV_K_DIV_SHIFT);
5665
5666 /* Feedback post-divider - m2 */
5667 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5668
5669 /* Feedback refclk divider - n and m1 */
5670 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5671 DPIO_CHV_M1_DIV_BY_2 |
5672 1 << DPIO_CHV_N_DIV_SHIFT);
5673
5674 /* M2 fraction division */
5675 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5676
5677 /* M2 fraction division enable */
5678 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5679 DPIO_CHV_FRAC_DIV_EN |
5680 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5681
5682 /* Loop filter */
5683 refclk = i9xx_get_refclk(&crtc->base, 0);
5684 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5685 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5686 if (refclk == 100000)
5687 intcoeff = 11;
5688 else if (refclk == 38400)
5689 intcoeff = 10;
5690 else
5691 intcoeff = 9;
5692 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5693 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5694
5695 /* AFC Recal */
5696 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5697 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5698 DPIO_AFC_RECAL);
5699
5700 mutex_unlock(&dev_priv->dpio_lock);
5701 }
5702
5703 static void i9xx_update_pll(struct intel_crtc *crtc,
5704 intel_clock_t *reduced_clock,
5705 int num_connectors)
5706 {
5707 struct drm_device *dev = crtc->base.dev;
5708 struct drm_i915_private *dev_priv = dev->dev_private;
5709 u32 dpll;
5710 bool is_sdvo;
5711 struct dpll *clock = &crtc->config.dpll;
5712
5713 i9xx_update_pll_dividers(crtc, reduced_clock);
5714
5715 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5716 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5717
5718 dpll = DPLL_VGA_MODE_DIS;
5719
5720 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5721 dpll |= DPLLB_MODE_LVDS;
5722 else
5723 dpll |= DPLLB_MODE_DAC_SERIAL;
5724
5725 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5726 dpll |= (crtc->config.pixel_multiplier - 1)
5727 << SDVO_MULTIPLIER_SHIFT_HIRES;
5728 }
5729
5730 if (is_sdvo)
5731 dpll |= DPLL_SDVO_HIGH_SPEED;
5732
5733 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5734 dpll |= DPLL_SDVO_HIGH_SPEED;
5735
5736 /* compute bitmask from p1 value */
5737 if (IS_PINEVIEW(dev))
5738 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5739 else {
5740 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5741 if (IS_G4X(dev) && reduced_clock)
5742 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5743 }
5744 switch (clock->p2) {
5745 case 5:
5746 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5747 break;
5748 case 7:
5749 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5750 break;
5751 case 10:
5752 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5753 break;
5754 case 14:
5755 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5756 break;
5757 }
5758 if (INTEL_INFO(dev)->gen >= 4)
5759 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5760
5761 if (crtc->config.sdvo_tv_clock)
5762 dpll |= PLL_REF_INPUT_TVCLKINBC;
5763 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5764 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5765 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5766 else
5767 dpll |= PLL_REF_INPUT_DREFCLK;
5768
5769 dpll |= DPLL_VCO_ENABLE;
5770 crtc->config.dpll_hw_state.dpll = dpll;
5771
5772 if (INTEL_INFO(dev)->gen >= 4) {
5773 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5774 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5775 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5776 }
5777 }
5778
5779 static void i8xx_update_pll(struct intel_crtc *crtc,
5780 intel_clock_t *reduced_clock,
5781 int num_connectors)
5782 {
5783 struct drm_device *dev = crtc->base.dev;
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 u32 dpll;
5786 struct dpll *clock = &crtc->config.dpll;
5787
5788 i9xx_update_pll_dividers(crtc, reduced_clock);
5789
5790 dpll = DPLL_VGA_MODE_DIS;
5791
5792 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5793 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5794 } else {
5795 if (clock->p1 == 2)
5796 dpll |= PLL_P1_DIVIDE_BY_TWO;
5797 else
5798 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5799 if (clock->p2 == 4)
5800 dpll |= PLL_P2_DIVIDE_BY_4;
5801 }
5802
5803 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5804 dpll |= DPLL_DVO_2X_MODE;
5805
5806 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5807 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5808 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5809 else
5810 dpll |= PLL_REF_INPUT_DREFCLK;
5811
5812 dpll |= DPLL_VCO_ENABLE;
5813 crtc->config.dpll_hw_state.dpll = dpll;
5814 }
5815
5816 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5817 {
5818 struct drm_device *dev = intel_crtc->base.dev;
5819 struct drm_i915_private *dev_priv = dev->dev_private;
5820 enum pipe pipe = intel_crtc->pipe;
5821 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5822 struct drm_display_mode *adjusted_mode =
5823 &intel_crtc->config.adjusted_mode;
5824 uint32_t crtc_vtotal, crtc_vblank_end;
5825 int vsyncshift = 0;
5826
5827 /* We need to be careful not to changed the adjusted mode, for otherwise
5828 * the hw state checker will get angry at the mismatch. */
5829 crtc_vtotal = adjusted_mode->crtc_vtotal;
5830 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5831
5832 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5833 /* the chip adds 2 halflines automatically */
5834 crtc_vtotal -= 1;
5835 crtc_vblank_end -= 1;
5836
5837 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5838 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5839 else
5840 vsyncshift = adjusted_mode->crtc_hsync_start -
5841 adjusted_mode->crtc_htotal / 2;
5842 if (vsyncshift < 0)
5843 vsyncshift += adjusted_mode->crtc_htotal;
5844 }
5845
5846 if (INTEL_INFO(dev)->gen > 3)
5847 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5848
5849 I915_WRITE(HTOTAL(cpu_transcoder),
5850 (adjusted_mode->crtc_hdisplay - 1) |
5851 ((adjusted_mode->crtc_htotal - 1) << 16));
5852 I915_WRITE(HBLANK(cpu_transcoder),
5853 (adjusted_mode->crtc_hblank_start - 1) |
5854 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5855 I915_WRITE(HSYNC(cpu_transcoder),
5856 (adjusted_mode->crtc_hsync_start - 1) |
5857 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5858
5859 I915_WRITE(VTOTAL(cpu_transcoder),
5860 (adjusted_mode->crtc_vdisplay - 1) |
5861 ((crtc_vtotal - 1) << 16));
5862 I915_WRITE(VBLANK(cpu_transcoder),
5863 (adjusted_mode->crtc_vblank_start - 1) |
5864 ((crtc_vblank_end - 1) << 16));
5865 I915_WRITE(VSYNC(cpu_transcoder),
5866 (adjusted_mode->crtc_vsync_start - 1) |
5867 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5868
5869 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5870 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5871 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5872 * bits. */
5873 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5874 (pipe == PIPE_B || pipe == PIPE_C))
5875 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5876
5877 /* pipesrc controls the size that is scaled from, which should
5878 * always be the user's requested size.
5879 */
5880 I915_WRITE(PIPESRC(pipe),
5881 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5882 (intel_crtc->config.pipe_src_h - 1));
5883 }
5884
5885 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5886 struct intel_crtc_config *pipe_config)
5887 {
5888 struct drm_device *dev = crtc->base.dev;
5889 struct drm_i915_private *dev_priv = dev->dev_private;
5890 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5891 uint32_t tmp;
5892
5893 tmp = I915_READ(HTOTAL(cpu_transcoder));
5894 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5895 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5896 tmp = I915_READ(HBLANK(cpu_transcoder));
5897 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5898 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5899 tmp = I915_READ(HSYNC(cpu_transcoder));
5900 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5901 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5902
5903 tmp = I915_READ(VTOTAL(cpu_transcoder));
5904 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5905 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5906 tmp = I915_READ(VBLANK(cpu_transcoder));
5907 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5908 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5909 tmp = I915_READ(VSYNC(cpu_transcoder));
5910 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5911 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5912
5913 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5914 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5915 pipe_config->adjusted_mode.crtc_vtotal += 1;
5916 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5917 }
5918
5919 tmp = I915_READ(PIPESRC(crtc->pipe));
5920 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5921 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5922
5923 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5924 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5925 }
5926
5927 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5928 struct intel_crtc_config *pipe_config)
5929 {
5930 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5931 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5932 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5933 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5934
5935 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5936 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5937 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5938 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5939
5940 mode->flags = pipe_config->adjusted_mode.flags;
5941
5942 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5943 mode->flags |= pipe_config->adjusted_mode.flags;
5944 }
5945
5946 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5947 {
5948 struct drm_device *dev = intel_crtc->base.dev;
5949 struct drm_i915_private *dev_priv = dev->dev_private;
5950 uint32_t pipeconf;
5951
5952 pipeconf = 0;
5953
5954 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5955 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5956 pipeconf |= PIPECONF_ENABLE;
5957
5958 if (intel_crtc->config.double_wide)
5959 pipeconf |= PIPECONF_DOUBLE_WIDE;
5960
5961 /* only g4x and later have fancy bpc/dither controls */
5962 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5963 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5964 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5965 pipeconf |= PIPECONF_DITHER_EN |
5966 PIPECONF_DITHER_TYPE_SP;
5967
5968 switch (intel_crtc->config.pipe_bpp) {
5969 case 18:
5970 pipeconf |= PIPECONF_6BPC;
5971 break;
5972 case 24:
5973 pipeconf |= PIPECONF_8BPC;
5974 break;
5975 case 30:
5976 pipeconf |= PIPECONF_10BPC;
5977 break;
5978 default:
5979 /* Case prevented by intel_choose_pipe_bpp_dither. */
5980 BUG();
5981 }
5982 }
5983
5984 if (HAS_PIPE_CXSR(dev)) {
5985 if (intel_crtc->lowfreq_avail) {
5986 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5987 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5988 } else {
5989 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5990 }
5991 }
5992
5993 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5994 if (INTEL_INFO(dev)->gen < 4 ||
5995 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5996 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5997 else
5998 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5999 } else
6000 pipeconf |= PIPECONF_PROGRESSIVE;
6001
6002 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6003 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6004
6005 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6006 POSTING_READ(PIPECONF(intel_crtc->pipe));
6007 }
6008
6009 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6010 int x, int y,
6011 struct drm_framebuffer *fb)
6012 {
6013 struct drm_device *dev = crtc->dev;
6014 struct drm_i915_private *dev_priv = dev->dev_private;
6015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6016 int refclk, num_connectors = 0;
6017 intel_clock_t clock, reduced_clock;
6018 bool ok, has_reduced_clock = false;
6019 bool is_lvds = false, is_dsi = false;
6020 struct intel_encoder *encoder;
6021 const intel_limit_t *limit;
6022
6023 for_each_encoder_on_crtc(dev, crtc, encoder) {
6024 switch (encoder->type) {
6025 case INTEL_OUTPUT_LVDS:
6026 is_lvds = true;
6027 break;
6028 case INTEL_OUTPUT_DSI:
6029 is_dsi = true;
6030 break;
6031 }
6032
6033 num_connectors++;
6034 }
6035
6036 if (is_dsi)
6037 return 0;
6038
6039 if (!intel_crtc->config.clock_set) {
6040 refclk = i9xx_get_refclk(crtc, num_connectors);
6041
6042 /*
6043 * Returns a set of divisors for the desired target clock with
6044 * the given refclk, or FALSE. The returned values represent
6045 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6046 * 2) / p1 / p2.
6047 */
6048 limit = intel_limit(crtc, refclk);
6049 ok = dev_priv->display.find_dpll(limit, crtc,
6050 intel_crtc->config.port_clock,
6051 refclk, NULL, &clock);
6052 if (!ok) {
6053 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6054 return -EINVAL;
6055 }
6056
6057 if (is_lvds && dev_priv->lvds_downclock_avail) {
6058 /*
6059 * Ensure we match the reduced clock's P to the target
6060 * clock. If the clocks don't match, we can't switch
6061 * the display clock by using the FP0/FP1. In such case
6062 * we will disable the LVDS downclock feature.
6063 */
6064 has_reduced_clock =
6065 dev_priv->display.find_dpll(limit, crtc,
6066 dev_priv->lvds_downclock,
6067 refclk, &clock,
6068 &reduced_clock);
6069 }
6070 /* Compat-code for transition, will disappear. */
6071 intel_crtc->config.dpll.n = clock.n;
6072 intel_crtc->config.dpll.m1 = clock.m1;
6073 intel_crtc->config.dpll.m2 = clock.m2;
6074 intel_crtc->config.dpll.p1 = clock.p1;
6075 intel_crtc->config.dpll.p2 = clock.p2;
6076 }
6077
6078 if (IS_GEN2(dev)) {
6079 i8xx_update_pll(intel_crtc,
6080 has_reduced_clock ? &reduced_clock : NULL,
6081 num_connectors);
6082 } else if (IS_CHERRYVIEW(dev)) {
6083 chv_update_pll(intel_crtc);
6084 } else if (IS_VALLEYVIEW(dev)) {
6085 vlv_update_pll(intel_crtc);
6086 } else {
6087 i9xx_update_pll(intel_crtc,
6088 has_reduced_clock ? &reduced_clock : NULL,
6089 num_connectors);
6090 }
6091
6092 return 0;
6093 }
6094
6095 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6096 struct intel_crtc_config *pipe_config)
6097 {
6098 struct drm_device *dev = crtc->base.dev;
6099 struct drm_i915_private *dev_priv = dev->dev_private;
6100 uint32_t tmp;
6101
6102 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6103 return;
6104
6105 tmp = I915_READ(PFIT_CONTROL);
6106 if (!(tmp & PFIT_ENABLE))
6107 return;
6108
6109 /* Check whether the pfit is attached to our pipe. */
6110 if (INTEL_INFO(dev)->gen < 4) {
6111 if (crtc->pipe != PIPE_B)
6112 return;
6113 } else {
6114 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6115 return;
6116 }
6117
6118 pipe_config->gmch_pfit.control = tmp;
6119 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6120 if (INTEL_INFO(dev)->gen < 5)
6121 pipe_config->gmch_pfit.lvds_border_bits =
6122 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6123 }
6124
6125 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6126 struct intel_crtc_config *pipe_config)
6127 {
6128 struct drm_device *dev = crtc->base.dev;
6129 struct drm_i915_private *dev_priv = dev->dev_private;
6130 int pipe = pipe_config->cpu_transcoder;
6131 intel_clock_t clock;
6132 u32 mdiv;
6133 int refclk = 100000;
6134
6135 mutex_lock(&dev_priv->dpio_lock);
6136 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6137 mutex_unlock(&dev_priv->dpio_lock);
6138
6139 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6140 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6141 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6142 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6143 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6144
6145 vlv_clock(refclk, &clock);
6146
6147 /* clock.dot is the fast clock */
6148 pipe_config->port_clock = clock.dot / 5;
6149 }
6150
6151 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6152 struct intel_plane_config *plane_config)
6153 {
6154 struct drm_device *dev = crtc->base.dev;
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6156 u32 val, base, offset;
6157 int pipe = crtc->pipe, plane = crtc->plane;
6158 int fourcc, pixel_format;
6159 int aligned_height;
6160
6161 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6162 if (!crtc->base.primary->fb) {
6163 DRM_DEBUG_KMS("failed to alloc fb\n");
6164 return;
6165 }
6166
6167 val = I915_READ(DSPCNTR(plane));
6168
6169 if (INTEL_INFO(dev)->gen >= 4)
6170 if (val & DISPPLANE_TILED)
6171 plane_config->tiled = true;
6172
6173 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6174 fourcc = intel_format_to_fourcc(pixel_format);
6175 crtc->base.primary->fb->pixel_format = fourcc;
6176 crtc->base.primary->fb->bits_per_pixel =
6177 drm_format_plane_cpp(fourcc, 0) * 8;
6178
6179 if (INTEL_INFO(dev)->gen >= 4) {
6180 if (plane_config->tiled)
6181 offset = I915_READ(DSPTILEOFF(plane));
6182 else
6183 offset = I915_READ(DSPLINOFF(plane));
6184 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6185 } else {
6186 base = I915_READ(DSPADDR(plane));
6187 }
6188 plane_config->base = base;
6189
6190 val = I915_READ(PIPESRC(pipe));
6191 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6192 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6193
6194 val = I915_READ(DSPSTRIDE(pipe));
6195 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6196
6197 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6198 plane_config->tiled);
6199
6200 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6201 aligned_height);
6202
6203 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6204 pipe, plane, crtc->base.primary->fb->width,
6205 crtc->base.primary->fb->height,
6206 crtc->base.primary->fb->bits_per_pixel, base,
6207 crtc->base.primary->fb->pitches[0],
6208 plane_config->size);
6209
6210 }
6211
6212 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6213 struct intel_crtc_config *pipe_config)
6214 {
6215 struct drm_device *dev = crtc->base.dev;
6216 struct drm_i915_private *dev_priv = dev->dev_private;
6217 int pipe = pipe_config->cpu_transcoder;
6218 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6219 intel_clock_t clock;
6220 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6221 int refclk = 100000;
6222
6223 mutex_lock(&dev_priv->dpio_lock);
6224 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6225 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6226 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6227 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6228 mutex_unlock(&dev_priv->dpio_lock);
6229
6230 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6231 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6232 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6233 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6234 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6235
6236 chv_clock(refclk, &clock);
6237
6238 /* clock.dot is the fast clock */
6239 pipe_config->port_clock = clock.dot / 5;
6240 }
6241
6242 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6243 struct intel_crtc_config *pipe_config)
6244 {
6245 struct drm_device *dev = crtc->base.dev;
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247 uint32_t tmp;
6248
6249 if (!intel_display_power_enabled(dev_priv,
6250 POWER_DOMAIN_PIPE(crtc->pipe)))
6251 return false;
6252
6253 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6254 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6255
6256 tmp = I915_READ(PIPECONF(crtc->pipe));
6257 if (!(tmp & PIPECONF_ENABLE))
6258 return false;
6259
6260 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6261 switch (tmp & PIPECONF_BPC_MASK) {
6262 case PIPECONF_6BPC:
6263 pipe_config->pipe_bpp = 18;
6264 break;
6265 case PIPECONF_8BPC:
6266 pipe_config->pipe_bpp = 24;
6267 break;
6268 case PIPECONF_10BPC:
6269 pipe_config->pipe_bpp = 30;
6270 break;
6271 default:
6272 break;
6273 }
6274 }
6275
6276 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6277 pipe_config->limited_color_range = true;
6278
6279 if (INTEL_INFO(dev)->gen < 4)
6280 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6281
6282 intel_get_pipe_timings(crtc, pipe_config);
6283
6284 i9xx_get_pfit_config(crtc, pipe_config);
6285
6286 if (INTEL_INFO(dev)->gen >= 4) {
6287 tmp = I915_READ(DPLL_MD(crtc->pipe));
6288 pipe_config->pixel_multiplier =
6289 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6290 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6291 pipe_config->dpll_hw_state.dpll_md = tmp;
6292 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6293 tmp = I915_READ(DPLL(crtc->pipe));
6294 pipe_config->pixel_multiplier =
6295 ((tmp & SDVO_MULTIPLIER_MASK)
6296 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6297 } else {
6298 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6299 * port and will be fixed up in the encoder->get_config
6300 * function. */
6301 pipe_config->pixel_multiplier = 1;
6302 }
6303 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6304 if (!IS_VALLEYVIEW(dev)) {
6305 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6306 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6307 } else {
6308 /* Mask out read-only status bits. */
6309 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6310 DPLL_PORTC_READY_MASK |
6311 DPLL_PORTB_READY_MASK);
6312 }
6313
6314 if (IS_CHERRYVIEW(dev))
6315 chv_crtc_clock_get(crtc, pipe_config);
6316 else if (IS_VALLEYVIEW(dev))
6317 vlv_crtc_clock_get(crtc, pipe_config);
6318 else
6319 i9xx_crtc_clock_get(crtc, pipe_config);
6320
6321 return true;
6322 }
6323
6324 static void ironlake_init_pch_refclk(struct drm_device *dev)
6325 {
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327 struct drm_mode_config *mode_config = &dev->mode_config;
6328 struct intel_encoder *encoder;
6329 u32 val, final;
6330 bool has_lvds = false;
6331 bool has_cpu_edp = false;
6332 bool has_panel = false;
6333 bool has_ck505 = false;
6334 bool can_ssc = false;
6335
6336 /* We need to take the global config into account */
6337 list_for_each_entry(encoder, &mode_config->encoder_list,
6338 base.head) {
6339 switch (encoder->type) {
6340 case INTEL_OUTPUT_LVDS:
6341 has_panel = true;
6342 has_lvds = true;
6343 break;
6344 case INTEL_OUTPUT_EDP:
6345 has_panel = true;
6346 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6347 has_cpu_edp = true;
6348 break;
6349 }
6350 }
6351
6352 if (HAS_PCH_IBX(dev)) {
6353 has_ck505 = dev_priv->vbt.display_clock_mode;
6354 can_ssc = has_ck505;
6355 } else {
6356 has_ck505 = false;
6357 can_ssc = true;
6358 }
6359
6360 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6361 has_panel, has_lvds, has_ck505);
6362
6363 /* Ironlake: try to setup display ref clock before DPLL
6364 * enabling. This is only under driver's control after
6365 * PCH B stepping, previous chipset stepping should be
6366 * ignoring this setting.
6367 */
6368 val = I915_READ(PCH_DREF_CONTROL);
6369
6370 /* As we must carefully and slowly disable/enable each source in turn,
6371 * compute the final state we want first and check if we need to
6372 * make any changes at all.
6373 */
6374 final = val;
6375 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6376 if (has_ck505)
6377 final |= DREF_NONSPREAD_CK505_ENABLE;
6378 else
6379 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6380
6381 final &= ~DREF_SSC_SOURCE_MASK;
6382 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6383 final &= ~DREF_SSC1_ENABLE;
6384
6385 if (has_panel) {
6386 final |= DREF_SSC_SOURCE_ENABLE;
6387
6388 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6389 final |= DREF_SSC1_ENABLE;
6390
6391 if (has_cpu_edp) {
6392 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6393 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6394 else
6395 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6396 } else
6397 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6398 } else {
6399 final |= DREF_SSC_SOURCE_DISABLE;
6400 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6401 }
6402
6403 if (final == val)
6404 return;
6405
6406 /* Always enable nonspread source */
6407 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6408
6409 if (has_ck505)
6410 val |= DREF_NONSPREAD_CK505_ENABLE;
6411 else
6412 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6413
6414 if (has_panel) {
6415 val &= ~DREF_SSC_SOURCE_MASK;
6416 val |= DREF_SSC_SOURCE_ENABLE;
6417
6418 /* SSC must be turned on before enabling the CPU output */
6419 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6420 DRM_DEBUG_KMS("Using SSC on panel\n");
6421 val |= DREF_SSC1_ENABLE;
6422 } else
6423 val &= ~DREF_SSC1_ENABLE;
6424
6425 /* Get SSC going before enabling the outputs */
6426 I915_WRITE(PCH_DREF_CONTROL, val);
6427 POSTING_READ(PCH_DREF_CONTROL);
6428 udelay(200);
6429
6430 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6431
6432 /* Enable CPU source on CPU attached eDP */
6433 if (has_cpu_edp) {
6434 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6435 DRM_DEBUG_KMS("Using SSC on eDP\n");
6436 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6437 } else
6438 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6439 } else
6440 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6441
6442 I915_WRITE(PCH_DREF_CONTROL, val);
6443 POSTING_READ(PCH_DREF_CONTROL);
6444 udelay(200);
6445 } else {
6446 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6447
6448 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6449
6450 /* Turn off CPU output */
6451 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6452
6453 I915_WRITE(PCH_DREF_CONTROL, val);
6454 POSTING_READ(PCH_DREF_CONTROL);
6455 udelay(200);
6456
6457 /* Turn off the SSC source */
6458 val &= ~DREF_SSC_SOURCE_MASK;
6459 val |= DREF_SSC_SOURCE_DISABLE;
6460
6461 /* Turn off SSC1 */
6462 val &= ~DREF_SSC1_ENABLE;
6463
6464 I915_WRITE(PCH_DREF_CONTROL, val);
6465 POSTING_READ(PCH_DREF_CONTROL);
6466 udelay(200);
6467 }
6468
6469 BUG_ON(val != final);
6470 }
6471
6472 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6473 {
6474 uint32_t tmp;
6475
6476 tmp = I915_READ(SOUTH_CHICKEN2);
6477 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6478 I915_WRITE(SOUTH_CHICKEN2, tmp);
6479
6480 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6481 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6482 DRM_ERROR("FDI mPHY reset assert timeout\n");
6483
6484 tmp = I915_READ(SOUTH_CHICKEN2);
6485 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6486 I915_WRITE(SOUTH_CHICKEN2, tmp);
6487
6488 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6489 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6490 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6491 }
6492
6493 /* WaMPhyProgramming:hsw */
6494 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6495 {
6496 uint32_t tmp;
6497
6498 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6499 tmp &= ~(0xFF << 24);
6500 tmp |= (0x12 << 24);
6501 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6502
6503 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6504 tmp |= (1 << 11);
6505 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6506
6507 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6508 tmp |= (1 << 11);
6509 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6510
6511 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6512 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6513 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6514
6515 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6516 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6517 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6518
6519 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6520 tmp &= ~(7 << 13);
6521 tmp |= (5 << 13);
6522 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6523
6524 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6525 tmp &= ~(7 << 13);
6526 tmp |= (5 << 13);
6527 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6528
6529 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6530 tmp &= ~0xFF;
6531 tmp |= 0x1C;
6532 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6533
6534 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6535 tmp &= ~0xFF;
6536 tmp |= 0x1C;
6537 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6538
6539 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6540 tmp &= ~(0xFF << 16);
6541 tmp |= (0x1C << 16);
6542 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6543
6544 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6545 tmp &= ~(0xFF << 16);
6546 tmp |= (0x1C << 16);
6547 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6548
6549 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6550 tmp |= (1 << 27);
6551 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6552
6553 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6554 tmp |= (1 << 27);
6555 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6556
6557 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6558 tmp &= ~(0xF << 28);
6559 tmp |= (4 << 28);
6560 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6561
6562 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6563 tmp &= ~(0xF << 28);
6564 tmp |= (4 << 28);
6565 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6566 }
6567
6568 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6569 * Programming" based on the parameters passed:
6570 * - Sequence to enable CLKOUT_DP
6571 * - Sequence to enable CLKOUT_DP without spread
6572 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6573 */
6574 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6575 bool with_fdi)
6576 {
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578 uint32_t reg, tmp;
6579
6580 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6581 with_spread = true;
6582 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6583 with_fdi, "LP PCH doesn't have FDI\n"))
6584 with_fdi = false;
6585
6586 mutex_lock(&dev_priv->dpio_lock);
6587
6588 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6589 tmp &= ~SBI_SSCCTL_DISABLE;
6590 tmp |= SBI_SSCCTL_PATHALT;
6591 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6592
6593 udelay(24);
6594
6595 if (with_spread) {
6596 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6597 tmp &= ~SBI_SSCCTL_PATHALT;
6598 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6599
6600 if (with_fdi) {
6601 lpt_reset_fdi_mphy(dev_priv);
6602 lpt_program_fdi_mphy(dev_priv);
6603 }
6604 }
6605
6606 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6607 SBI_GEN0 : SBI_DBUFF0;
6608 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6609 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6610 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6611
6612 mutex_unlock(&dev_priv->dpio_lock);
6613 }
6614
6615 /* Sequence to disable CLKOUT_DP */
6616 static void lpt_disable_clkout_dp(struct drm_device *dev)
6617 {
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619 uint32_t reg, tmp;
6620
6621 mutex_lock(&dev_priv->dpio_lock);
6622
6623 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6624 SBI_GEN0 : SBI_DBUFF0;
6625 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6626 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6627 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6628
6629 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6630 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6631 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6632 tmp |= SBI_SSCCTL_PATHALT;
6633 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6634 udelay(32);
6635 }
6636 tmp |= SBI_SSCCTL_DISABLE;
6637 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6638 }
6639
6640 mutex_unlock(&dev_priv->dpio_lock);
6641 }
6642
6643 static void lpt_init_pch_refclk(struct drm_device *dev)
6644 {
6645 struct drm_mode_config *mode_config = &dev->mode_config;
6646 struct intel_encoder *encoder;
6647 bool has_vga = false;
6648
6649 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6650 switch (encoder->type) {
6651 case INTEL_OUTPUT_ANALOG:
6652 has_vga = true;
6653 break;
6654 }
6655 }
6656
6657 if (has_vga)
6658 lpt_enable_clkout_dp(dev, true, true);
6659 else
6660 lpt_disable_clkout_dp(dev);
6661 }
6662
6663 /*
6664 * Initialize reference clocks when the driver loads
6665 */
6666 void intel_init_pch_refclk(struct drm_device *dev)
6667 {
6668 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6669 ironlake_init_pch_refclk(dev);
6670 else if (HAS_PCH_LPT(dev))
6671 lpt_init_pch_refclk(dev);
6672 }
6673
6674 static int ironlake_get_refclk(struct drm_crtc *crtc)
6675 {
6676 struct drm_device *dev = crtc->dev;
6677 struct drm_i915_private *dev_priv = dev->dev_private;
6678 struct intel_encoder *encoder;
6679 int num_connectors = 0;
6680 bool is_lvds = false;
6681
6682 for_each_encoder_on_crtc(dev, crtc, encoder) {
6683 switch (encoder->type) {
6684 case INTEL_OUTPUT_LVDS:
6685 is_lvds = true;
6686 break;
6687 }
6688 num_connectors++;
6689 }
6690
6691 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6692 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6693 dev_priv->vbt.lvds_ssc_freq);
6694 return dev_priv->vbt.lvds_ssc_freq;
6695 }
6696
6697 return 120000;
6698 }
6699
6700 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6701 {
6702 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6704 int pipe = intel_crtc->pipe;
6705 uint32_t val;
6706
6707 val = 0;
6708
6709 switch (intel_crtc->config.pipe_bpp) {
6710 case 18:
6711 val |= PIPECONF_6BPC;
6712 break;
6713 case 24:
6714 val |= PIPECONF_8BPC;
6715 break;
6716 case 30:
6717 val |= PIPECONF_10BPC;
6718 break;
6719 case 36:
6720 val |= PIPECONF_12BPC;
6721 break;
6722 default:
6723 /* Case prevented by intel_choose_pipe_bpp_dither. */
6724 BUG();
6725 }
6726
6727 if (intel_crtc->config.dither)
6728 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6729
6730 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6731 val |= PIPECONF_INTERLACED_ILK;
6732 else
6733 val |= PIPECONF_PROGRESSIVE;
6734
6735 if (intel_crtc->config.limited_color_range)
6736 val |= PIPECONF_COLOR_RANGE_SELECT;
6737
6738 I915_WRITE(PIPECONF(pipe), val);
6739 POSTING_READ(PIPECONF(pipe));
6740 }
6741
6742 /*
6743 * Set up the pipe CSC unit.
6744 *
6745 * Currently only full range RGB to limited range RGB conversion
6746 * is supported, but eventually this should handle various
6747 * RGB<->YCbCr scenarios as well.
6748 */
6749 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6750 {
6751 struct drm_device *dev = crtc->dev;
6752 struct drm_i915_private *dev_priv = dev->dev_private;
6753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6754 int pipe = intel_crtc->pipe;
6755 uint16_t coeff = 0x7800; /* 1.0 */
6756
6757 /*
6758 * TODO: Check what kind of values actually come out of the pipe
6759 * with these coeff/postoff values and adjust to get the best
6760 * accuracy. Perhaps we even need to take the bpc value into
6761 * consideration.
6762 */
6763
6764 if (intel_crtc->config.limited_color_range)
6765 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6766
6767 /*
6768 * GY/GU and RY/RU should be the other way around according
6769 * to BSpec, but reality doesn't agree. Just set them up in
6770 * a way that results in the correct picture.
6771 */
6772 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6773 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6774
6775 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6776 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6777
6778 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6779 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6780
6781 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6782 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6783 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6784
6785 if (INTEL_INFO(dev)->gen > 6) {
6786 uint16_t postoff = 0;
6787
6788 if (intel_crtc->config.limited_color_range)
6789 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6790
6791 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6792 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6793 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6794
6795 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6796 } else {
6797 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6798
6799 if (intel_crtc->config.limited_color_range)
6800 mode |= CSC_BLACK_SCREEN_OFFSET;
6801
6802 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6803 }
6804 }
6805
6806 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6807 {
6808 struct drm_device *dev = crtc->dev;
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6811 enum pipe pipe = intel_crtc->pipe;
6812 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6813 uint32_t val;
6814
6815 val = 0;
6816
6817 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6818 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6819
6820 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6821 val |= PIPECONF_INTERLACED_ILK;
6822 else
6823 val |= PIPECONF_PROGRESSIVE;
6824
6825 I915_WRITE(PIPECONF(cpu_transcoder), val);
6826 POSTING_READ(PIPECONF(cpu_transcoder));
6827
6828 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6829 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6830
6831 if (IS_BROADWELL(dev)) {
6832 val = 0;
6833
6834 switch (intel_crtc->config.pipe_bpp) {
6835 case 18:
6836 val |= PIPEMISC_DITHER_6_BPC;
6837 break;
6838 case 24:
6839 val |= PIPEMISC_DITHER_8_BPC;
6840 break;
6841 case 30:
6842 val |= PIPEMISC_DITHER_10_BPC;
6843 break;
6844 case 36:
6845 val |= PIPEMISC_DITHER_12_BPC;
6846 break;
6847 default:
6848 /* Case prevented by pipe_config_set_bpp. */
6849 BUG();
6850 }
6851
6852 if (intel_crtc->config.dither)
6853 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6854
6855 I915_WRITE(PIPEMISC(pipe), val);
6856 }
6857 }
6858
6859 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6860 intel_clock_t *clock,
6861 bool *has_reduced_clock,
6862 intel_clock_t *reduced_clock)
6863 {
6864 struct drm_device *dev = crtc->dev;
6865 struct drm_i915_private *dev_priv = dev->dev_private;
6866 struct intel_encoder *intel_encoder;
6867 int refclk;
6868 const intel_limit_t *limit;
6869 bool ret, is_lvds = false;
6870
6871 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6872 switch (intel_encoder->type) {
6873 case INTEL_OUTPUT_LVDS:
6874 is_lvds = true;
6875 break;
6876 }
6877 }
6878
6879 refclk = ironlake_get_refclk(crtc);
6880
6881 /*
6882 * Returns a set of divisors for the desired target clock with the given
6883 * refclk, or FALSE. The returned values represent the clock equation:
6884 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6885 */
6886 limit = intel_limit(crtc, refclk);
6887 ret = dev_priv->display.find_dpll(limit, crtc,
6888 to_intel_crtc(crtc)->config.port_clock,
6889 refclk, NULL, clock);
6890 if (!ret)
6891 return false;
6892
6893 if (is_lvds && dev_priv->lvds_downclock_avail) {
6894 /*
6895 * Ensure we match the reduced clock's P to the target clock.
6896 * If the clocks don't match, we can't switch the display clock
6897 * by using the FP0/FP1. In such case we will disable the LVDS
6898 * downclock feature.
6899 */
6900 *has_reduced_clock =
6901 dev_priv->display.find_dpll(limit, crtc,
6902 dev_priv->lvds_downclock,
6903 refclk, clock,
6904 reduced_clock);
6905 }
6906
6907 return true;
6908 }
6909
6910 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6911 {
6912 /*
6913 * Account for spread spectrum to avoid
6914 * oversubscribing the link. Max center spread
6915 * is 2.5%; use 5% for safety's sake.
6916 */
6917 u32 bps = target_clock * bpp * 21 / 20;
6918 return DIV_ROUND_UP(bps, link_bw * 8);
6919 }
6920
6921 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6922 {
6923 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6924 }
6925
6926 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6927 u32 *fp,
6928 intel_clock_t *reduced_clock, u32 *fp2)
6929 {
6930 struct drm_crtc *crtc = &intel_crtc->base;
6931 struct drm_device *dev = crtc->dev;
6932 struct drm_i915_private *dev_priv = dev->dev_private;
6933 struct intel_encoder *intel_encoder;
6934 uint32_t dpll;
6935 int factor, num_connectors = 0;
6936 bool is_lvds = false, is_sdvo = false;
6937
6938 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6939 switch (intel_encoder->type) {
6940 case INTEL_OUTPUT_LVDS:
6941 is_lvds = true;
6942 break;
6943 case INTEL_OUTPUT_SDVO:
6944 case INTEL_OUTPUT_HDMI:
6945 is_sdvo = true;
6946 break;
6947 }
6948
6949 num_connectors++;
6950 }
6951
6952 /* Enable autotuning of the PLL clock (if permissible) */
6953 factor = 21;
6954 if (is_lvds) {
6955 if ((intel_panel_use_ssc(dev_priv) &&
6956 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6957 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6958 factor = 25;
6959 } else if (intel_crtc->config.sdvo_tv_clock)
6960 factor = 20;
6961
6962 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6963 *fp |= FP_CB_TUNE;
6964
6965 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6966 *fp2 |= FP_CB_TUNE;
6967
6968 dpll = 0;
6969
6970 if (is_lvds)
6971 dpll |= DPLLB_MODE_LVDS;
6972 else
6973 dpll |= DPLLB_MODE_DAC_SERIAL;
6974
6975 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6976 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6977
6978 if (is_sdvo)
6979 dpll |= DPLL_SDVO_HIGH_SPEED;
6980 if (intel_crtc->config.has_dp_encoder)
6981 dpll |= DPLL_SDVO_HIGH_SPEED;
6982
6983 /* compute bitmask from p1 value */
6984 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6985 /* also FPA1 */
6986 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6987
6988 switch (intel_crtc->config.dpll.p2) {
6989 case 5:
6990 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6991 break;
6992 case 7:
6993 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6994 break;
6995 case 10:
6996 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6997 break;
6998 case 14:
6999 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7000 break;
7001 }
7002
7003 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7004 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7005 else
7006 dpll |= PLL_REF_INPUT_DREFCLK;
7007
7008 return dpll | DPLL_VCO_ENABLE;
7009 }
7010
7011 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7012 int x, int y,
7013 struct drm_framebuffer *fb)
7014 {
7015 struct drm_device *dev = crtc->dev;
7016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017 int num_connectors = 0;
7018 intel_clock_t clock, reduced_clock;
7019 u32 dpll = 0, fp = 0, fp2 = 0;
7020 bool ok, has_reduced_clock = false;
7021 bool is_lvds = false;
7022 struct intel_encoder *encoder;
7023 struct intel_shared_dpll *pll;
7024
7025 for_each_encoder_on_crtc(dev, crtc, encoder) {
7026 switch (encoder->type) {
7027 case INTEL_OUTPUT_LVDS:
7028 is_lvds = true;
7029 break;
7030 }
7031
7032 num_connectors++;
7033 }
7034
7035 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7036 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7037
7038 ok = ironlake_compute_clocks(crtc, &clock,
7039 &has_reduced_clock, &reduced_clock);
7040 if (!ok && !intel_crtc->config.clock_set) {
7041 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7042 return -EINVAL;
7043 }
7044 /* Compat-code for transition, will disappear. */
7045 if (!intel_crtc->config.clock_set) {
7046 intel_crtc->config.dpll.n = clock.n;
7047 intel_crtc->config.dpll.m1 = clock.m1;
7048 intel_crtc->config.dpll.m2 = clock.m2;
7049 intel_crtc->config.dpll.p1 = clock.p1;
7050 intel_crtc->config.dpll.p2 = clock.p2;
7051 }
7052
7053 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7054 if (intel_crtc->config.has_pch_encoder) {
7055 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7056 if (has_reduced_clock)
7057 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7058
7059 dpll = ironlake_compute_dpll(intel_crtc,
7060 &fp, &reduced_clock,
7061 has_reduced_clock ? &fp2 : NULL);
7062
7063 intel_crtc->config.dpll_hw_state.dpll = dpll;
7064 intel_crtc->config.dpll_hw_state.fp0 = fp;
7065 if (has_reduced_clock)
7066 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7067 else
7068 intel_crtc->config.dpll_hw_state.fp1 = fp;
7069
7070 pll = intel_get_shared_dpll(intel_crtc);
7071 if (pll == NULL) {
7072 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7073 pipe_name(intel_crtc->pipe));
7074 return -EINVAL;
7075 }
7076 } else
7077 intel_put_shared_dpll(intel_crtc);
7078
7079 if (is_lvds && has_reduced_clock && i915.powersave)
7080 intel_crtc->lowfreq_avail = true;
7081 else
7082 intel_crtc->lowfreq_avail = false;
7083
7084 return 0;
7085 }
7086
7087 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7088 struct intel_link_m_n *m_n)
7089 {
7090 struct drm_device *dev = crtc->base.dev;
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092 enum pipe pipe = crtc->pipe;
7093
7094 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7095 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7096 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7097 & ~TU_SIZE_MASK;
7098 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7099 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7100 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7101 }
7102
7103 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7104 enum transcoder transcoder,
7105 struct intel_link_m_n *m_n)
7106 {
7107 struct drm_device *dev = crtc->base.dev;
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 enum pipe pipe = crtc->pipe;
7110
7111 if (INTEL_INFO(dev)->gen >= 5) {
7112 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7113 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7114 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7115 & ~TU_SIZE_MASK;
7116 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7117 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7118 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7119 } else {
7120 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7121 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7122 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7123 & ~TU_SIZE_MASK;
7124 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7125 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7126 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7127 }
7128 }
7129
7130 void intel_dp_get_m_n(struct intel_crtc *crtc,
7131 struct intel_crtc_config *pipe_config)
7132 {
7133 if (crtc->config.has_pch_encoder)
7134 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7135 else
7136 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7137 &pipe_config->dp_m_n);
7138 }
7139
7140 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7141 struct intel_crtc_config *pipe_config)
7142 {
7143 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7144 &pipe_config->fdi_m_n);
7145 }
7146
7147 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7148 struct intel_crtc_config *pipe_config)
7149 {
7150 struct drm_device *dev = crtc->base.dev;
7151 struct drm_i915_private *dev_priv = dev->dev_private;
7152 uint32_t tmp;
7153
7154 tmp = I915_READ(PF_CTL(crtc->pipe));
7155
7156 if (tmp & PF_ENABLE) {
7157 pipe_config->pch_pfit.enabled = true;
7158 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7159 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7160
7161 /* We currently do not free assignements of panel fitters on
7162 * ivb/hsw (since we don't use the higher upscaling modes which
7163 * differentiates them) so just WARN about this case for now. */
7164 if (IS_GEN7(dev)) {
7165 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7166 PF_PIPE_SEL_IVB(crtc->pipe));
7167 }
7168 }
7169 }
7170
7171 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7172 struct intel_plane_config *plane_config)
7173 {
7174 struct drm_device *dev = crtc->base.dev;
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 u32 val, base, offset;
7177 int pipe = crtc->pipe, plane = crtc->plane;
7178 int fourcc, pixel_format;
7179 int aligned_height;
7180
7181 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7182 if (!crtc->base.primary->fb) {
7183 DRM_DEBUG_KMS("failed to alloc fb\n");
7184 return;
7185 }
7186
7187 val = I915_READ(DSPCNTR(plane));
7188
7189 if (INTEL_INFO(dev)->gen >= 4)
7190 if (val & DISPPLANE_TILED)
7191 plane_config->tiled = true;
7192
7193 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7194 fourcc = intel_format_to_fourcc(pixel_format);
7195 crtc->base.primary->fb->pixel_format = fourcc;
7196 crtc->base.primary->fb->bits_per_pixel =
7197 drm_format_plane_cpp(fourcc, 0) * 8;
7198
7199 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7200 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7201 offset = I915_READ(DSPOFFSET(plane));
7202 } else {
7203 if (plane_config->tiled)
7204 offset = I915_READ(DSPTILEOFF(plane));
7205 else
7206 offset = I915_READ(DSPLINOFF(plane));
7207 }
7208 plane_config->base = base;
7209
7210 val = I915_READ(PIPESRC(pipe));
7211 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7212 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7213
7214 val = I915_READ(DSPSTRIDE(pipe));
7215 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7216
7217 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7218 plane_config->tiled);
7219
7220 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7221 aligned_height);
7222
7223 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7224 pipe, plane, crtc->base.primary->fb->width,
7225 crtc->base.primary->fb->height,
7226 crtc->base.primary->fb->bits_per_pixel, base,
7227 crtc->base.primary->fb->pitches[0],
7228 plane_config->size);
7229 }
7230
7231 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7232 struct intel_crtc_config *pipe_config)
7233 {
7234 struct drm_device *dev = crtc->base.dev;
7235 struct drm_i915_private *dev_priv = dev->dev_private;
7236 uint32_t tmp;
7237
7238 if (!intel_display_power_enabled(dev_priv,
7239 POWER_DOMAIN_PIPE(crtc->pipe)))
7240 return false;
7241
7242 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7243 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7244
7245 tmp = I915_READ(PIPECONF(crtc->pipe));
7246 if (!(tmp & PIPECONF_ENABLE))
7247 return false;
7248
7249 switch (tmp & PIPECONF_BPC_MASK) {
7250 case PIPECONF_6BPC:
7251 pipe_config->pipe_bpp = 18;
7252 break;
7253 case PIPECONF_8BPC:
7254 pipe_config->pipe_bpp = 24;
7255 break;
7256 case PIPECONF_10BPC:
7257 pipe_config->pipe_bpp = 30;
7258 break;
7259 case PIPECONF_12BPC:
7260 pipe_config->pipe_bpp = 36;
7261 break;
7262 default:
7263 break;
7264 }
7265
7266 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7267 pipe_config->limited_color_range = true;
7268
7269 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7270 struct intel_shared_dpll *pll;
7271
7272 pipe_config->has_pch_encoder = true;
7273
7274 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7275 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7276 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7277
7278 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7279
7280 if (HAS_PCH_IBX(dev_priv->dev)) {
7281 pipe_config->shared_dpll =
7282 (enum intel_dpll_id) crtc->pipe;
7283 } else {
7284 tmp = I915_READ(PCH_DPLL_SEL);
7285 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7286 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7287 else
7288 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7289 }
7290
7291 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7292
7293 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7294 &pipe_config->dpll_hw_state));
7295
7296 tmp = pipe_config->dpll_hw_state.dpll;
7297 pipe_config->pixel_multiplier =
7298 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7299 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7300
7301 ironlake_pch_clock_get(crtc, pipe_config);
7302 } else {
7303 pipe_config->pixel_multiplier = 1;
7304 }
7305
7306 intel_get_pipe_timings(crtc, pipe_config);
7307
7308 ironlake_get_pfit_config(crtc, pipe_config);
7309
7310 return true;
7311 }
7312
7313 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7314 {
7315 struct drm_device *dev = dev_priv->dev;
7316 struct intel_crtc *crtc;
7317
7318 for_each_intel_crtc(dev, crtc)
7319 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7320 pipe_name(crtc->pipe));
7321
7322 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7323 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7324 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7325 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7326 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7327 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7328 "CPU PWM1 enabled\n");
7329 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7330 "CPU PWM2 enabled\n");
7331 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7332 "PCH PWM1 enabled\n");
7333 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7334 "Utility pin enabled\n");
7335 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7336
7337 /*
7338 * In theory we can still leave IRQs enabled, as long as only the HPD
7339 * interrupts remain enabled. We used to check for that, but since it's
7340 * gen-specific and since we only disable LCPLL after we fully disable
7341 * the interrupts, the check below should be enough.
7342 */
7343 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7344 }
7345
7346 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7347 {
7348 struct drm_device *dev = dev_priv->dev;
7349
7350 if (IS_HASWELL(dev))
7351 return I915_READ(D_COMP_HSW);
7352 else
7353 return I915_READ(D_COMP_BDW);
7354 }
7355
7356 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7357 {
7358 struct drm_device *dev = dev_priv->dev;
7359
7360 if (IS_HASWELL(dev)) {
7361 mutex_lock(&dev_priv->rps.hw_lock);
7362 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7363 val))
7364 DRM_ERROR("Failed to write to D_COMP\n");
7365 mutex_unlock(&dev_priv->rps.hw_lock);
7366 } else {
7367 I915_WRITE(D_COMP_BDW, val);
7368 POSTING_READ(D_COMP_BDW);
7369 }
7370 }
7371
7372 /*
7373 * This function implements pieces of two sequences from BSpec:
7374 * - Sequence for display software to disable LCPLL
7375 * - Sequence for display software to allow package C8+
7376 * The steps implemented here are just the steps that actually touch the LCPLL
7377 * register. Callers should take care of disabling all the display engine
7378 * functions, doing the mode unset, fixing interrupts, etc.
7379 */
7380 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7381 bool switch_to_fclk, bool allow_power_down)
7382 {
7383 uint32_t val;
7384
7385 assert_can_disable_lcpll(dev_priv);
7386
7387 val = I915_READ(LCPLL_CTL);
7388
7389 if (switch_to_fclk) {
7390 val |= LCPLL_CD_SOURCE_FCLK;
7391 I915_WRITE(LCPLL_CTL, val);
7392
7393 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7394 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7395 DRM_ERROR("Switching to FCLK failed\n");
7396
7397 val = I915_READ(LCPLL_CTL);
7398 }
7399
7400 val |= LCPLL_PLL_DISABLE;
7401 I915_WRITE(LCPLL_CTL, val);
7402 POSTING_READ(LCPLL_CTL);
7403
7404 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7405 DRM_ERROR("LCPLL still locked\n");
7406
7407 val = hsw_read_dcomp(dev_priv);
7408 val |= D_COMP_COMP_DISABLE;
7409 hsw_write_dcomp(dev_priv, val);
7410 ndelay(100);
7411
7412 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7413 1))
7414 DRM_ERROR("D_COMP RCOMP still in progress\n");
7415
7416 if (allow_power_down) {
7417 val = I915_READ(LCPLL_CTL);
7418 val |= LCPLL_POWER_DOWN_ALLOW;
7419 I915_WRITE(LCPLL_CTL, val);
7420 POSTING_READ(LCPLL_CTL);
7421 }
7422 }
7423
7424 /*
7425 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7426 * source.
7427 */
7428 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7429 {
7430 uint32_t val;
7431 unsigned long irqflags;
7432
7433 val = I915_READ(LCPLL_CTL);
7434
7435 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7436 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7437 return;
7438
7439 /*
7440 * Make sure we're not on PC8 state before disabling PC8, otherwise
7441 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7442 *
7443 * The other problem is that hsw_restore_lcpll() is called as part of
7444 * the runtime PM resume sequence, so we can't just call
7445 * gen6_gt_force_wake_get() because that function calls
7446 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7447 * while we are on the resume sequence. So to solve this problem we have
7448 * to call special forcewake code that doesn't touch runtime PM and
7449 * doesn't enable the forcewake delayed work.
7450 */
7451 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7452 if (dev_priv->uncore.forcewake_count++ == 0)
7453 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7454 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7455
7456 if (val & LCPLL_POWER_DOWN_ALLOW) {
7457 val &= ~LCPLL_POWER_DOWN_ALLOW;
7458 I915_WRITE(LCPLL_CTL, val);
7459 POSTING_READ(LCPLL_CTL);
7460 }
7461
7462 val = hsw_read_dcomp(dev_priv);
7463 val |= D_COMP_COMP_FORCE;
7464 val &= ~D_COMP_COMP_DISABLE;
7465 hsw_write_dcomp(dev_priv, val);
7466
7467 val = I915_READ(LCPLL_CTL);
7468 val &= ~LCPLL_PLL_DISABLE;
7469 I915_WRITE(LCPLL_CTL, val);
7470
7471 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7472 DRM_ERROR("LCPLL not locked yet\n");
7473
7474 if (val & LCPLL_CD_SOURCE_FCLK) {
7475 val = I915_READ(LCPLL_CTL);
7476 val &= ~LCPLL_CD_SOURCE_FCLK;
7477 I915_WRITE(LCPLL_CTL, val);
7478
7479 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7480 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7481 DRM_ERROR("Switching back to LCPLL failed\n");
7482 }
7483
7484 /* See the big comment above. */
7485 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7486 if (--dev_priv->uncore.forcewake_count == 0)
7487 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7489 }
7490
7491 /*
7492 * Package states C8 and deeper are really deep PC states that can only be
7493 * reached when all the devices on the system allow it, so even if the graphics
7494 * device allows PC8+, it doesn't mean the system will actually get to these
7495 * states. Our driver only allows PC8+ when going into runtime PM.
7496 *
7497 * The requirements for PC8+ are that all the outputs are disabled, the power
7498 * well is disabled and most interrupts are disabled, and these are also
7499 * requirements for runtime PM. When these conditions are met, we manually do
7500 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7501 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7502 * hang the machine.
7503 *
7504 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7505 * the state of some registers, so when we come back from PC8+ we need to
7506 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7507 * need to take care of the registers kept by RC6. Notice that this happens even
7508 * if we don't put the device in PCI D3 state (which is what currently happens
7509 * because of the runtime PM support).
7510 *
7511 * For more, read "Display Sequences for Package C8" on the hardware
7512 * documentation.
7513 */
7514 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7515 {
7516 struct drm_device *dev = dev_priv->dev;
7517 uint32_t val;
7518
7519 DRM_DEBUG_KMS("Enabling package C8+\n");
7520
7521 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7522 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7523 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7524 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7525 }
7526
7527 lpt_disable_clkout_dp(dev);
7528 hsw_disable_lcpll(dev_priv, true, true);
7529 }
7530
7531 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7532 {
7533 struct drm_device *dev = dev_priv->dev;
7534 uint32_t val;
7535
7536 DRM_DEBUG_KMS("Disabling package C8+\n");
7537
7538 hsw_restore_lcpll(dev_priv);
7539 lpt_init_pch_refclk(dev);
7540
7541 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7542 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7543 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7544 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7545 }
7546
7547 intel_prepare_ddi(dev);
7548 }
7549
7550 static void snb_modeset_global_resources(struct drm_device *dev)
7551 {
7552 modeset_update_crtc_power_domains(dev);
7553 }
7554
7555 static void haswell_modeset_global_resources(struct drm_device *dev)
7556 {
7557 modeset_update_crtc_power_domains(dev);
7558 }
7559
7560 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7561 int x, int y,
7562 struct drm_framebuffer *fb)
7563 {
7564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7565
7566 if (!intel_ddi_pll_select(intel_crtc))
7567 return -EINVAL;
7568
7569 intel_crtc->lowfreq_avail = false;
7570
7571 return 0;
7572 }
7573
7574 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7575 struct intel_crtc_config *pipe_config)
7576 {
7577 struct drm_device *dev = crtc->base.dev;
7578 struct drm_i915_private *dev_priv = dev->dev_private;
7579 struct intel_shared_dpll *pll;
7580 enum port port;
7581 uint32_t tmp;
7582
7583 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7584
7585 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7586
7587 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7588
7589 switch (pipe_config->ddi_pll_sel) {
7590 case PORT_CLK_SEL_WRPLL1:
7591 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7592 break;
7593 case PORT_CLK_SEL_WRPLL2:
7594 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7595 break;
7596 }
7597
7598 if (pipe_config->shared_dpll >= 0) {
7599 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7600
7601 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7602 &pipe_config->dpll_hw_state));
7603 }
7604
7605 /*
7606 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7607 * DDI E. So just check whether this pipe is wired to DDI E and whether
7608 * the PCH transcoder is on.
7609 */
7610 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7611 pipe_config->has_pch_encoder = true;
7612
7613 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7614 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7615 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7616
7617 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7618 }
7619 }
7620
7621 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7622 struct intel_crtc_config *pipe_config)
7623 {
7624 struct drm_device *dev = crtc->base.dev;
7625 struct drm_i915_private *dev_priv = dev->dev_private;
7626 enum intel_display_power_domain pfit_domain;
7627 uint32_t tmp;
7628
7629 if (!intel_display_power_enabled(dev_priv,
7630 POWER_DOMAIN_PIPE(crtc->pipe)))
7631 return false;
7632
7633 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7634 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7635
7636 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7637 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7638 enum pipe trans_edp_pipe;
7639 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7640 default:
7641 WARN(1, "unknown pipe linked to edp transcoder\n");
7642 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7643 case TRANS_DDI_EDP_INPUT_A_ON:
7644 trans_edp_pipe = PIPE_A;
7645 break;
7646 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7647 trans_edp_pipe = PIPE_B;
7648 break;
7649 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7650 trans_edp_pipe = PIPE_C;
7651 break;
7652 }
7653
7654 if (trans_edp_pipe == crtc->pipe)
7655 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7656 }
7657
7658 if (!intel_display_power_enabled(dev_priv,
7659 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7660 return false;
7661
7662 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7663 if (!(tmp & PIPECONF_ENABLE))
7664 return false;
7665
7666 haswell_get_ddi_port_state(crtc, pipe_config);
7667
7668 intel_get_pipe_timings(crtc, pipe_config);
7669
7670 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7671 if (intel_display_power_enabled(dev_priv, pfit_domain))
7672 ironlake_get_pfit_config(crtc, pipe_config);
7673
7674 if (IS_HASWELL(dev))
7675 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7676 (I915_READ(IPS_CTL) & IPS_ENABLE);
7677
7678 pipe_config->pixel_multiplier = 1;
7679
7680 return true;
7681 }
7682
7683 static struct {
7684 int clock;
7685 u32 config;
7686 } hdmi_audio_clock[] = {
7687 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7688 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7689 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7690 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7691 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7692 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7693 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7694 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7695 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7696 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7697 };
7698
7699 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7700 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7701 {
7702 int i;
7703
7704 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7705 if (mode->clock == hdmi_audio_clock[i].clock)
7706 break;
7707 }
7708
7709 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7710 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7711 i = 1;
7712 }
7713
7714 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7715 hdmi_audio_clock[i].clock,
7716 hdmi_audio_clock[i].config);
7717
7718 return hdmi_audio_clock[i].config;
7719 }
7720
7721 static bool intel_eld_uptodate(struct drm_connector *connector,
7722 int reg_eldv, uint32_t bits_eldv,
7723 int reg_elda, uint32_t bits_elda,
7724 int reg_edid)
7725 {
7726 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7727 uint8_t *eld = connector->eld;
7728 uint32_t i;
7729
7730 i = I915_READ(reg_eldv);
7731 i &= bits_eldv;
7732
7733 if (!eld[0])
7734 return !i;
7735
7736 if (!i)
7737 return false;
7738
7739 i = I915_READ(reg_elda);
7740 i &= ~bits_elda;
7741 I915_WRITE(reg_elda, i);
7742
7743 for (i = 0; i < eld[2]; i++)
7744 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7745 return false;
7746
7747 return true;
7748 }
7749
7750 static void g4x_write_eld(struct drm_connector *connector,
7751 struct drm_crtc *crtc,
7752 struct drm_display_mode *mode)
7753 {
7754 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7755 uint8_t *eld = connector->eld;
7756 uint32_t eldv;
7757 uint32_t len;
7758 uint32_t i;
7759
7760 i = I915_READ(G4X_AUD_VID_DID);
7761
7762 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7763 eldv = G4X_ELDV_DEVCL_DEVBLC;
7764 else
7765 eldv = G4X_ELDV_DEVCTG;
7766
7767 if (intel_eld_uptodate(connector,
7768 G4X_AUD_CNTL_ST, eldv,
7769 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7770 G4X_HDMIW_HDMIEDID))
7771 return;
7772
7773 i = I915_READ(G4X_AUD_CNTL_ST);
7774 i &= ~(eldv | G4X_ELD_ADDR);
7775 len = (i >> 9) & 0x1f; /* ELD buffer size */
7776 I915_WRITE(G4X_AUD_CNTL_ST, i);
7777
7778 if (!eld[0])
7779 return;
7780
7781 len = min_t(uint8_t, eld[2], len);
7782 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7783 for (i = 0; i < len; i++)
7784 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7785
7786 i = I915_READ(G4X_AUD_CNTL_ST);
7787 i |= eldv;
7788 I915_WRITE(G4X_AUD_CNTL_ST, i);
7789 }
7790
7791 static void haswell_write_eld(struct drm_connector *connector,
7792 struct drm_crtc *crtc,
7793 struct drm_display_mode *mode)
7794 {
7795 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7796 uint8_t *eld = connector->eld;
7797 uint32_t eldv;
7798 uint32_t i;
7799 int len;
7800 int pipe = to_intel_crtc(crtc)->pipe;
7801 int tmp;
7802
7803 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7804 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7805 int aud_config = HSW_AUD_CFG(pipe);
7806 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7807
7808 /* Audio output enable */
7809 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7810 tmp = I915_READ(aud_cntrl_st2);
7811 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7812 I915_WRITE(aud_cntrl_st2, tmp);
7813 POSTING_READ(aud_cntrl_st2);
7814
7815 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7816
7817 /* Set ELD valid state */
7818 tmp = I915_READ(aud_cntrl_st2);
7819 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7820 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7821 I915_WRITE(aud_cntrl_st2, tmp);
7822 tmp = I915_READ(aud_cntrl_st2);
7823 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7824
7825 /* Enable HDMI mode */
7826 tmp = I915_READ(aud_config);
7827 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7828 /* clear N_programing_enable and N_value_index */
7829 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7830 I915_WRITE(aud_config, tmp);
7831
7832 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7833
7834 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7835
7836 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7837 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7838 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7839 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7840 } else {
7841 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7842 }
7843
7844 if (intel_eld_uptodate(connector,
7845 aud_cntrl_st2, eldv,
7846 aud_cntl_st, IBX_ELD_ADDRESS,
7847 hdmiw_hdmiedid))
7848 return;
7849
7850 i = I915_READ(aud_cntrl_st2);
7851 i &= ~eldv;
7852 I915_WRITE(aud_cntrl_st2, i);
7853
7854 if (!eld[0])
7855 return;
7856
7857 i = I915_READ(aud_cntl_st);
7858 i &= ~IBX_ELD_ADDRESS;
7859 I915_WRITE(aud_cntl_st, i);
7860 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7861 DRM_DEBUG_DRIVER("port num:%d\n", i);
7862
7863 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7864 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7865 for (i = 0; i < len; i++)
7866 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7867
7868 i = I915_READ(aud_cntrl_st2);
7869 i |= eldv;
7870 I915_WRITE(aud_cntrl_st2, i);
7871
7872 }
7873
7874 static void ironlake_write_eld(struct drm_connector *connector,
7875 struct drm_crtc *crtc,
7876 struct drm_display_mode *mode)
7877 {
7878 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7879 uint8_t *eld = connector->eld;
7880 uint32_t eldv;
7881 uint32_t i;
7882 int len;
7883 int hdmiw_hdmiedid;
7884 int aud_config;
7885 int aud_cntl_st;
7886 int aud_cntrl_st2;
7887 int pipe = to_intel_crtc(crtc)->pipe;
7888
7889 if (HAS_PCH_IBX(connector->dev)) {
7890 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7891 aud_config = IBX_AUD_CFG(pipe);
7892 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7893 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7894 } else if (IS_VALLEYVIEW(connector->dev)) {
7895 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7896 aud_config = VLV_AUD_CFG(pipe);
7897 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7898 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7899 } else {
7900 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7901 aud_config = CPT_AUD_CFG(pipe);
7902 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7903 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7904 }
7905
7906 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7907
7908 if (IS_VALLEYVIEW(connector->dev)) {
7909 struct intel_encoder *intel_encoder;
7910 struct intel_digital_port *intel_dig_port;
7911
7912 intel_encoder = intel_attached_encoder(connector);
7913 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7914 i = intel_dig_port->port;
7915 } else {
7916 i = I915_READ(aud_cntl_st);
7917 i = (i >> 29) & DIP_PORT_SEL_MASK;
7918 /* DIP_Port_Select, 0x1 = PortB */
7919 }
7920
7921 if (!i) {
7922 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7923 /* operate blindly on all ports */
7924 eldv = IBX_ELD_VALIDB;
7925 eldv |= IBX_ELD_VALIDB << 4;
7926 eldv |= IBX_ELD_VALIDB << 8;
7927 } else {
7928 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7929 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7930 }
7931
7932 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7933 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7934 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7935 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7936 } else {
7937 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7938 }
7939
7940 if (intel_eld_uptodate(connector,
7941 aud_cntrl_st2, eldv,
7942 aud_cntl_st, IBX_ELD_ADDRESS,
7943 hdmiw_hdmiedid))
7944 return;
7945
7946 i = I915_READ(aud_cntrl_st2);
7947 i &= ~eldv;
7948 I915_WRITE(aud_cntrl_st2, i);
7949
7950 if (!eld[0])
7951 return;
7952
7953 i = I915_READ(aud_cntl_st);
7954 i &= ~IBX_ELD_ADDRESS;
7955 I915_WRITE(aud_cntl_st, i);
7956
7957 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7958 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7959 for (i = 0; i < len; i++)
7960 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7961
7962 i = I915_READ(aud_cntrl_st2);
7963 i |= eldv;
7964 I915_WRITE(aud_cntrl_st2, i);
7965 }
7966
7967 void intel_write_eld(struct drm_encoder *encoder,
7968 struct drm_display_mode *mode)
7969 {
7970 struct drm_crtc *crtc = encoder->crtc;
7971 struct drm_connector *connector;
7972 struct drm_device *dev = encoder->dev;
7973 struct drm_i915_private *dev_priv = dev->dev_private;
7974
7975 connector = drm_select_eld(encoder, mode);
7976 if (!connector)
7977 return;
7978
7979 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7980 connector->base.id,
7981 connector->name,
7982 connector->encoder->base.id,
7983 connector->encoder->name);
7984
7985 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7986
7987 if (dev_priv->display.write_eld)
7988 dev_priv->display.write_eld(connector, crtc, mode);
7989 }
7990
7991 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7992 {
7993 struct drm_device *dev = crtc->dev;
7994 struct drm_i915_private *dev_priv = dev->dev_private;
7995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7996 uint32_t cntl;
7997
7998 if (base != intel_crtc->cursor_base) {
7999 /* On these chipsets we can only modify the base whilst
8000 * the cursor is disabled.
8001 */
8002 if (intel_crtc->cursor_cntl) {
8003 I915_WRITE(_CURACNTR, 0);
8004 POSTING_READ(_CURACNTR);
8005 intel_crtc->cursor_cntl = 0;
8006 }
8007
8008 I915_WRITE(_CURABASE, base);
8009 POSTING_READ(_CURABASE);
8010 }
8011
8012 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8013 cntl = 0;
8014 if (base)
8015 cntl = (CURSOR_ENABLE |
8016 CURSOR_GAMMA_ENABLE |
8017 CURSOR_FORMAT_ARGB);
8018 if (intel_crtc->cursor_cntl != cntl) {
8019 I915_WRITE(_CURACNTR, cntl);
8020 POSTING_READ(_CURACNTR);
8021 intel_crtc->cursor_cntl = cntl;
8022 }
8023 }
8024
8025 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8026 {
8027 struct drm_device *dev = crtc->dev;
8028 struct drm_i915_private *dev_priv = dev->dev_private;
8029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8030 int pipe = intel_crtc->pipe;
8031 uint32_t cntl;
8032
8033 cntl = 0;
8034 if (base) {
8035 cntl = MCURSOR_GAMMA_ENABLE;
8036 switch (intel_crtc->cursor_width) {
8037 case 64:
8038 cntl |= CURSOR_MODE_64_ARGB_AX;
8039 break;
8040 case 128:
8041 cntl |= CURSOR_MODE_128_ARGB_AX;
8042 break;
8043 case 256:
8044 cntl |= CURSOR_MODE_256_ARGB_AX;
8045 break;
8046 default:
8047 WARN_ON(1);
8048 return;
8049 }
8050 cntl |= pipe << 28; /* Connect to correct pipe */
8051 }
8052 if (intel_crtc->cursor_cntl != cntl) {
8053 I915_WRITE(CURCNTR(pipe), cntl);
8054 POSTING_READ(CURCNTR(pipe));
8055 intel_crtc->cursor_cntl = cntl;
8056 }
8057
8058 /* and commit changes on next vblank */
8059 I915_WRITE(CURBASE(pipe), base);
8060 POSTING_READ(CURBASE(pipe));
8061 }
8062
8063 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8064 {
8065 struct drm_device *dev = crtc->dev;
8066 struct drm_i915_private *dev_priv = dev->dev_private;
8067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8068 int pipe = intel_crtc->pipe;
8069 uint32_t cntl;
8070
8071 cntl = 0;
8072 if (base) {
8073 cntl = MCURSOR_GAMMA_ENABLE;
8074 switch (intel_crtc->cursor_width) {
8075 case 64:
8076 cntl |= CURSOR_MODE_64_ARGB_AX;
8077 break;
8078 case 128:
8079 cntl |= CURSOR_MODE_128_ARGB_AX;
8080 break;
8081 case 256:
8082 cntl |= CURSOR_MODE_256_ARGB_AX;
8083 break;
8084 default:
8085 WARN_ON(1);
8086 return;
8087 }
8088 }
8089 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8090 cntl |= CURSOR_PIPE_CSC_ENABLE;
8091
8092 if (intel_crtc->cursor_cntl != cntl) {
8093 I915_WRITE(CURCNTR(pipe), cntl);
8094 POSTING_READ(CURCNTR(pipe));
8095 intel_crtc->cursor_cntl = cntl;
8096 }
8097
8098 /* and commit changes on next vblank */
8099 I915_WRITE(CURBASE(pipe), base);
8100 POSTING_READ(CURBASE(pipe));
8101 }
8102
8103 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8104 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8105 bool on)
8106 {
8107 struct drm_device *dev = crtc->dev;
8108 struct drm_i915_private *dev_priv = dev->dev_private;
8109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8110 int pipe = intel_crtc->pipe;
8111 int x = crtc->cursor_x;
8112 int y = crtc->cursor_y;
8113 u32 base = 0, pos = 0;
8114
8115 if (on)
8116 base = intel_crtc->cursor_addr;
8117
8118 if (x >= intel_crtc->config.pipe_src_w)
8119 base = 0;
8120
8121 if (y >= intel_crtc->config.pipe_src_h)
8122 base = 0;
8123
8124 if (x < 0) {
8125 if (x + intel_crtc->cursor_width <= 0)
8126 base = 0;
8127
8128 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8129 x = -x;
8130 }
8131 pos |= x << CURSOR_X_SHIFT;
8132
8133 if (y < 0) {
8134 if (y + intel_crtc->cursor_height <= 0)
8135 base = 0;
8136
8137 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8138 y = -y;
8139 }
8140 pos |= y << CURSOR_Y_SHIFT;
8141
8142 if (base == 0 && intel_crtc->cursor_base == 0)
8143 return;
8144
8145 I915_WRITE(CURPOS(pipe), pos);
8146
8147 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8148 ivb_update_cursor(crtc, base);
8149 else if (IS_845G(dev) || IS_I865G(dev))
8150 i845_update_cursor(crtc, base);
8151 else
8152 i9xx_update_cursor(crtc, base);
8153 intel_crtc->cursor_base = base;
8154 }
8155
8156 /*
8157 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8158 *
8159 * Note that the object's reference will be consumed if the update fails. If
8160 * the update succeeds, the reference of the old object (if any) will be
8161 * consumed.
8162 */
8163 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8164 struct drm_i915_gem_object *obj,
8165 uint32_t width, uint32_t height)
8166 {
8167 struct drm_device *dev = crtc->dev;
8168 struct drm_i915_private *dev_priv = dev->dev_private;
8169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8170 enum pipe pipe = intel_crtc->pipe;
8171 unsigned old_width;
8172 uint32_t addr;
8173 int ret;
8174
8175 /* if we want to turn off the cursor ignore width and height */
8176 if (!obj) {
8177 DRM_DEBUG_KMS("cursor off\n");
8178 addr = 0;
8179 obj = NULL;
8180 mutex_lock(&dev->struct_mutex);
8181 goto finish;
8182 }
8183
8184 /* Check for which cursor types we support */
8185 if (!((width == 64 && height == 64) ||
8186 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8187 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8188 DRM_DEBUG("Cursor dimension not supported\n");
8189 return -EINVAL;
8190 }
8191
8192 if (obj->base.size < width * height * 4) {
8193 DRM_DEBUG_KMS("buffer is too small\n");
8194 ret = -ENOMEM;
8195 goto fail;
8196 }
8197
8198 /* we only need to pin inside GTT if cursor is non-phy */
8199 mutex_lock(&dev->struct_mutex);
8200 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8201 unsigned alignment;
8202
8203 if (obj->tiling_mode) {
8204 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8205 ret = -EINVAL;
8206 goto fail_locked;
8207 }
8208
8209 /* Note that the w/a also requires 2 PTE of padding following
8210 * the bo. We currently fill all unused PTE with the shadow
8211 * page and so we should always have valid PTE following the
8212 * cursor preventing the VT-d warning.
8213 */
8214 alignment = 0;
8215 if (need_vtd_wa(dev))
8216 alignment = 64*1024;
8217
8218 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8219 if (ret) {
8220 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8221 goto fail_locked;
8222 }
8223
8224 ret = i915_gem_object_put_fence(obj);
8225 if (ret) {
8226 DRM_DEBUG_KMS("failed to release fence for cursor");
8227 goto fail_unpin;
8228 }
8229
8230 addr = i915_gem_obj_ggtt_offset(obj);
8231 } else {
8232 int align = IS_I830(dev) ? 16 * 1024 : 256;
8233 ret = i915_gem_object_attach_phys(obj, align);
8234 if (ret) {
8235 DRM_DEBUG_KMS("failed to attach phys object\n");
8236 goto fail_locked;
8237 }
8238 addr = obj->phys_handle->busaddr;
8239 }
8240
8241 if (IS_GEN2(dev))
8242 I915_WRITE(CURSIZE, (height << 12) | width);
8243
8244 finish:
8245 if (intel_crtc->cursor_bo) {
8246 if (!INTEL_INFO(dev)->cursor_needs_physical)
8247 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8248 }
8249
8250 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8251 INTEL_FRONTBUFFER_CURSOR(pipe));
8252 mutex_unlock(&dev->struct_mutex);
8253
8254 old_width = intel_crtc->cursor_width;
8255
8256 intel_crtc->cursor_addr = addr;
8257 intel_crtc->cursor_bo = obj;
8258 intel_crtc->cursor_width = width;
8259 intel_crtc->cursor_height = height;
8260
8261 if (intel_crtc->active) {
8262 if (old_width != width)
8263 intel_update_watermarks(crtc);
8264 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8265 }
8266
8267 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8268
8269 return 0;
8270 fail_unpin:
8271 i915_gem_object_unpin_from_display_plane(obj);
8272 fail_locked:
8273 mutex_unlock(&dev->struct_mutex);
8274 fail:
8275 drm_gem_object_unreference_unlocked(&obj->base);
8276 return ret;
8277 }
8278
8279 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8280 u16 *blue, uint32_t start, uint32_t size)
8281 {
8282 int end = (start + size > 256) ? 256 : start + size, i;
8283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8284
8285 for (i = start; i < end; i++) {
8286 intel_crtc->lut_r[i] = red[i] >> 8;
8287 intel_crtc->lut_g[i] = green[i] >> 8;
8288 intel_crtc->lut_b[i] = blue[i] >> 8;
8289 }
8290
8291 intel_crtc_load_lut(crtc);
8292 }
8293
8294 /* VESA 640x480x72Hz mode to set on the pipe */
8295 static struct drm_display_mode load_detect_mode = {
8296 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8297 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8298 };
8299
8300 struct drm_framebuffer *
8301 __intel_framebuffer_create(struct drm_device *dev,
8302 struct drm_mode_fb_cmd2 *mode_cmd,
8303 struct drm_i915_gem_object *obj)
8304 {
8305 struct intel_framebuffer *intel_fb;
8306 int ret;
8307
8308 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8309 if (!intel_fb) {
8310 drm_gem_object_unreference_unlocked(&obj->base);
8311 return ERR_PTR(-ENOMEM);
8312 }
8313
8314 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8315 if (ret)
8316 goto err;
8317
8318 return &intel_fb->base;
8319 err:
8320 drm_gem_object_unreference_unlocked(&obj->base);
8321 kfree(intel_fb);
8322
8323 return ERR_PTR(ret);
8324 }
8325
8326 static struct drm_framebuffer *
8327 intel_framebuffer_create(struct drm_device *dev,
8328 struct drm_mode_fb_cmd2 *mode_cmd,
8329 struct drm_i915_gem_object *obj)
8330 {
8331 struct drm_framebuffer *fb;
8332 int ret;
8333
8334 ret = i915_mutex_lock_interruptible(dev);
8335 if (ret)
8336 return ERR_PTR(ret);
8337 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8338 mutex_unlock(&dev->struct_mutex);
8339
8340 return fb;
8341 }
8342
8343 static u32
8344 intel_framebuffer_pitch_for_width(int width, int bpp)
8345 {
8346 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8347 return ALIGN(pitch, 64);
8348 }
8349
8350 static u32
8351 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8352 {
8353 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8354 return PAGE_ALIGN(pitch * mode->vdisplay);
8355 }
8356
8357 static struct drm_framebuffer *
8358 intel_framebuffer_create_for_mode(struct drm_device *dev,
8359 struct drm_display_mode *mode,
8360 int depth, int bpp)
8361 {
8362 struct drm_i915_gem_object *obj;
8363 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8364
8365 obj = i915_gem_alloc_object(dev,
8366 intel_framebuffer_size_for_mode(mode, bpp));
8367 if (obj == NULL)
8368 return ERR_PTR(-ENOMEM);
8369
8370 mode_cmd.width = mode->hdisplay;
8371 mode_cmd.height = mode->vdisplay;
8372 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8373 bpp);
8374 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8375
8376 return intel_framebuffer_create(dev, &mode_cmd, obj);
8377 }
8378
8379 static struct drm_framebuffer *
8380 mode_fits_in_fbdev(struct drm_device *dev,
8381 struct drm_display_mode *mode)
8382 {
8383 #ifdef CONFIG_DRM_I915_FBDEV
8384 struct drm_i915_private *dev_priv = dev->dev_private;
8385 struct drm_i915_gem_object *obj;
8386 struct drm_framebuffer *fb;
8387
8388 if (!dev_priv->fbdev)
8389 return NULL;
8390
8391 if (!dev_priv->fbdev->fb)
8392 return NULL;
8393
8394 obj = dev_priv->fbdev->fb->obj;
8395 BUG_ON(!obj);
8396
8397 fb = &dev_priv->fbdev->fb->base;
8398 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8399 fb->bits_per_pixel))
8400 return NULL;
8401
8402 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8403 return NULL;
8404
8405 return fb;
8406 #else
8407 return NULL;
8408 #endif
8409 }
8410
8411 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8412 struct drm_display_mode *mode,
8413 struct intel_load_detect_pipe *old,
8414 struct drm_modeset_acquire_ctx *ctx)
8415 {
8416 struct intel_crtc *intel_crtc;
8417 struct intel_encoder *intel_encoder =
8418 intel_attached_encoder(connector);
8419 struct drm_crtc *possible_crtc;
8420 struct drm_encoder *encoder = &intel_encoder->base;
8421 struct drm_crtc *crtc = NULL;
8422 struct drm_device *dev = encoder->dev;
8423 struct drm_framebuffer *fb;
8424 struct drm_mode_config *config = &dev->mode_config;
8425 int ret, i = -1;
8426
8427 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8428 connector->base.id, connector->name,
8429 encoder->base.id, encoder->name);
8430
8431 drm_modeset_acquire_init(ctx, 0);
8432
8433 retry:
8434 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8435 if (ret)
8436 goto fail_unlock;
8437
8438 /*
8439 * Algorithm gets a little messy:
8440 *
8441 * - if the connector already has an assigned crtc, use it (but make
8442 * sure it's on first)
8443 *
8444 * - try to find the first unused crtc that can drive this connector,
8445 * and use that if we find one
8446 */
8447
8448 /* See if we already have a CRTC for this connector */
8449 if (encoder->crtc) {
8450 crtc = encoder->crtc;
8451
8452 ret = drm_modeset_lock(&crtc->mutex, ctx);
8453 if (ret)
8454 goto fail_unlock;
8455
8456 old->dpms_mode = connector->dpms;
8457 old->load_detect_temp = false;
8458
8459 /* Make sure the crtc and connector are running */
8460 if (connector->dpms != DRM_MODE_DPMS_ON)
8461 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8462
8463 return true;
8464 }
8465
8466 /* Find an unused one (if possible) */
8467 for_each_crtc(dev, possible_crtc) {
8468 i++;
8469 if (!(encoder->possible_crtcs & (1 << i)))
8470 continue;
8471 if (!possible_crtc->enabled) {
8472 crtc = possible_crtc;
8473 break;
8474 }
8475 }
8476
8477 /*
8478 * If we didn't find an unused CRTC, don't use any.
8479 */
8480 if (!crtc) {
8481 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8482 goto fail_unlock;
8483 }
8484
8485 ret = drm_modeset_lock(&crtc->mutex, ctx);
8486 if (ret)
8487 goto fail_unlock;
8488 intel_encoder->new_crtc = to_intel_crtc(crtc);
8489 to_intel_connector(connector)->new_encoder = intel_encoder;
8490
8491 intel_crtc = to_intel_crtc(crtc);
8492 intel_crtc->new_enabled = true;
8493 intel_crtc->new_config = &intel_crtc->config;
8494 old->dpms_mode = connector->dpms;
8495 old->load_detect_temp = true;
8496 old->release_fb = NULL;
8497
8498 if (!mode)
8499 mode = &load_detect_mode;
8500
8501 /* We need a framebuffer large enough to accommodate all accesses
8502 * that the plane may generate whilst we perform load detection.
8503 * We can not rely on the fbcon either being present (we get called
8504 * during its initialisation to detect all boot displays, or it may
8505 * not even exist) or that it is large enough to satisfy the
8506 * requested mode.
8507 */
8508 fb = mode_fits_in_fbdev(dev, mode);
8509 if (fb == NULL) {
8510 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8511 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8512 old->release_fb = fb;
8513 } else
8514 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8515 if (IS_ERR(fb)) {
8516 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8517 goto fail;
8518 }
8519
8520 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8521 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8522 if (old->release_fb)
8523 old->release_fb->funcs->destroy(old->release_fb);
8524 goto fail;
8525 }
8526
8527 /* let the connector get through one full cycle before testing */
8528 intel_wait_for_vblank(dev, intel_crtc->pipe);
8529 return true;
8530
8531 fail:
8532 intel_crtc->new_enabled = crtc->enabled;
8533 if (intel_crtc->new_enabled)
8534 intel_crtc->new_config = &intel_crtc->config;
8535 else
8536 intel_crtc->new_config = NULL;
8537 fail_unlock:
8538 if (ret == -EDEADLK) {
8539 drm_modeset_backoff(ctx);
8540 goto retry;
8541 }
8542
8543 drm_modeset_drop_locks(ctx);
8544 drm_modeset_acquire_fini(ctx);
8545
8546 return false;
8547 }
8548
8549 void intel_release_load_detect_pipe(struct drm_connector *connector,
8550 struct intel_load_detect_pipe *old,
8551 struct drm_modeset_acquire_ctx *ctx)
8552 {
8553 struct intel_encoder *intel_encoder =
8554 intel_attached_encoder(connector);
8555 struct drm_encoder *encoder = &intel_encoder->base;
8556 struct drm_crtc *crtc = encoder->crtc;
8557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8558
8559 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8560 connector->base.id, connector->name,
8561 encoder->base.id, encoder->name);
8562
8563 if (old->load_detect_temp) {
8564 to_intel_connector(connector)->new_encoder = NULL;
8565 intel_encoder->new_crtc = NULL;
8566 intel_crtc->new_enabled = false;
8567 intel_crtc->new_config = NULL;
8568 intel_set_mode(crtc, NULL, 0, 0, NULL);
8569
8570 if (old->release_fb) {
8571 drm_framebuffer_unregister_private(old->release_fb);
8572 drm_framebuffer_unreference(old->release_fb);
8573 }
8574
8575 goto unlock;
8576 return;
8577 }
8578
8579 /* Switch crtc and encoder back off if necessary */
8580 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8581 connector->funcs->dpms(connector, old->dpms_mode);
8582
8583 unlock:
8584 drm_modeset_drop_locks(ctx);
8585 drm_modeset_acquire_fini(ctx);
8586 }
8587
8588 static int i9xx_pll_refclk(struct drm_device *dev,
8589 const struct intel_crtc_config *pipe_config)
8590 {
8591 struct drm_i915_private *dev_priv = dev->dev_private;
8592 u32 dpll = pipe_config->dpll_hw_state.dpll;
8593
8594 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8595 return dev_priv->vbt.lvds_ssc_freq;
8596 else if (HAS_PCH_SPLIT(dev))
8597 return 120000;
8598 else if (!IS_GEN2(dev))
8599 return 96000;
8600 else
8601 return 48000;
8602 }
8603
8604 /* Returns the clock of the currently programmed mode of the given pipe. */
8605 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8606 struct intel_crtc_config *pipe_config)
8607 {
8608 struct drm_device *dev = crtc->base.dev;
8609 struct drm_i915_private *dev_priv = dev->dev_private;
8610 int pipe = pipe_config->cpu_transcoder;
8611 u32 dpll = pipe_config->dpll_hw_state.dpll;
8612 u32 fp;
8613 intel_clock_t clock;
8614 int refclk = i9xx_pll_refclk(dev, pipe_config);
8615
8616 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8617 fp = pipe_config->dpll_hw_state.fp0;
8618 else
8619 fp = pipe_config->dpll_hw_state.fp1;
8620
8621 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8622 if (IS_PINEVIEW(dev)) {
8623 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8624 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8625 } else {
8626 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8627 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8628 }
8629
8630 if (!IS_GEN2(dev)) {
8631 if (IS_PINEVIEW(dev))
8632 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8633 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8634 else
8635 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8636 DPLL_FPA01_P1_POST_DIV_SHIFT);
8637
8638 switch (dpll & DPLL_MODE_MASK) {
8639 case DPLLB_MODE_DAC_SERIAL:
8640 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8641 5 : 10;
8642 break;
8643 case DPLLB_MODE_LVDS:
8644 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8645 7 : 14;
8646 break;
8647 default:
8648 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8649 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8650 return;
8651 }
8652
8653 if (IS_PINEVIEW(dev))
8654 pineview_clock(refclk, &clock);
8655 else
8656 i9xx_clock(refclk, &clock);
8657 } else {
8658 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8659 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8660
8661 if (is_lvds) {
8662 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8663 DPLL_FPA01_P1_POST_DIV_SHIFT);
8664
8665 if (lvds & LVDS_CLKB_POWER_UP)
8666 clock.p2 = 7;
8667 else
8668 clock.p2 = 14;
8669 } else {
8670 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8671 clock.p1 = 2;
8672 else {
8673 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8674 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8675 }
8676 if (dpll & PLL_P2_DIVIDE_BY_4)
8677 clock.p2 = 4;
8678 else
8679 clock.p2 = 2;
8680 }
8681
8682 i9xx_clock(refclk, &clock);
8683 }
8684
8685 /*
8686 * This value includes pixel_multiplier. We will use
8687 * port_clock to compute adjusted_mode.crtc_clock in the
8688 * encoder's get_config() function.
8689 */
8690 pipe_config->port_clock = clock.dot;
8691 }
8692
8693 int intel_dotclock_calculate(int link_freq,
8694 const struct intel_link_m_n *m_n)
8695 {
8696 /*
8697 * The calculation for the data clock is:
8698 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8699 * But we want to avoid losing precison if possible, so:
8700 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8701 *
8702 * and the link clock is simpler:
8703 * link_clock = (m * link_clock) / n
8704 */
8705
8706 if (!m_n->link_n)
8707 return 0;
8708
8709 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8710 }
8711
8712 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8713 struct intel_crtc_config *pipe_config)
8714 {
8715 struct drm_device *dev = crtc->base.dev;
8716
8717 /* read out port_clock from the DPLL */
8718 i9xx_crtc_clock_get(crtc, pipe_config);
8719
8720 /*
8721 * This value does not include pixel_multiplier.
8722 * We will check that port_clock and adjusted_mode.crtc_clock
8723 * agree once we know their relationship in the encoder's
8724 * get_config() function.
8725 */
8726 pipe_config->adjusted_mode.crtc_clock =
8727 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8728 &pipe_config->fdi_m_n);
8729 }
8730
8731 /** Returns the currently programmed mode of the given pipe. */
8732 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8733 struct drm_crtc *crtc)
8734 {
8735 struct drm_i915_private *dev_priv = dev->dev_private;
8736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8737 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8738 struct drm_display_mode *mode;
8739 struct intel_crtc_config pipe_config;
8740 int htot = I915_READ(HTOTAL(cpu_transcoder));
8741 int hsync = I915_READ(HSYNC(cpu_transcoder));
8742 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8743 int vsync = I915_READ(VSYNC(cpu_transcoder));
8744 enum pipe pipe = intel_crtc->pipe;
8745
8746 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8747 if (!mode)
8748 return NULL;
8749
8750 /*
8751 * Construct a pipe_config sufficient for getting the clock info
8752 * back out of crtc_clock_get.
8753 *
8754 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8755 * to use a real value here instead.
8756 */
8757 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8758 pipe_config.pixel_multiplier = 1;
8759 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8760 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8761 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8762 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8763
8764 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8765 mode->hdisplay = (htot & 0xffff) + 1;
8766 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8767 mode->hsync_start = (hsync & 0xffff) + 1;
8768 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8769 mode->vdisplay = (vtot & 0xffff) + 1;
8770 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8771 mode->vsync_start = (vsync & 0xffff) + 1;
8772 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8773
8774 drm_mode_set_name(mode);
8775
8776 return mode;
8777 }
8778
8779 static void intel_increase_pllclock(struct drm_device *dev,
8780 enum pipe pipe)
8781 {
8782 struct drm_i915_private *dev_priv = dev->dev_private;
8783 int dpll_reg = DPLL(pipe);
8784 int dpll;
8785
8786 if (HAS_PCH_SPLIT(dev))
8787 return;
8788
8789 if (!dev_priv->lvds_downclock_avail)
8790 return;
8791
8792 dpll = I915_READ(dpll_reg);
8793 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8794 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8795
8796 assert_panel_unlocked(dev_priv, pipe);
8797
8798 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8799 I915_WRITE(dpll_reg, dpll);
8800 intel_wait_for_vblank(dev, pipe);
8801
8802 dpll = I915_READ(dpll_reg);
8803 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8804 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8805 }
8806 }
8807
8808 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8809 {
8810 struct drm_device *dev = crtc->dev;
8811 struct drm_i915_private *dev_priv = dev->dev_private;
8812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8813
8814 if (HAS_PCH_SPLIT(dev))
8815 return;
8816
8817 if (!dev_priv->lvds_downclock_avail)
8818 return;
8819
8820 /*
8821 * Since this is called by a timer, we should never get here in
8822 * the manual case.
8823 */
8824 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8825 int pipe = intel_crtc->pipe;
8826 int dpll_reg = DPLL(pipe);
8827 int dpll;
8828
8829 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8830
8831 assert_panel_unlocked(dev_priv, pipe);
8832
8833 dpll = I915_READ(dpll_reg);
8834 dpll |= DISPLAY_RATE_SELECT_FPA1;
8835 I915_WRITE(dpll_reg, dpll);
8836 intel_wait_for_vblank(dev, pipe);
8837 dpll = I915_READ(dpll_reg);
8838 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8839 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8840 }
8841
8842 }
8843
8844 void intel_mark_busy(struct drm_device *dev)
8845 {
8846 struct drm_i915_private *dev_priv = dev->dev_private;
8847
8848 if (dev_priv->mm.busy)
8849 return;
8850
8851 intel_runtime_pm_get(dev_priv);
8852 i915_update_gfx_val(dev_priv);
8853 dev_priv->mm.busy = true;
8854 }
8855
8856 void intel_mark_idle(struct drm_device *dev)
8857 {
8858 struct drm_i915_private *dev_priv = dev->dev_private;
8859 struct drm_crtc *crtc;
8860
8861 if (!dev_priv->mm.busy)
8862 return;
8863
8864 dev_priv->mm.busy = false;
8865
8866 if (!i915.powersave)
8867 goto out;
8868
8869 for_each_crtc(dev, crtc) {
8870 if (!crtc->primary->fb)
8871 continue;
8872
8873 intel_decrease_pllclock(crtc);
8874 }
8875
8876 if (INTEL_INFO(dev)->gen >= 6)
8877 gen6_rps_idle(dev->dev_private);
8878
8879 out:
8880 intel_runtime_pm_put(dev_priv);
8881 }
8882
8883
8884 /**
8885 * intel_mark_fb_busy - mark given planes as busy
8886 * @dev: DRM device
8887 * @frontbuffer_bits: bits for the affected planes
8888 * @ring: optional ring for asynchronous commands
8889 *
8890 * This function gets called every time the screen contents change. It can be
8891 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8892 */
8893 static void intel_mark_fb_busy(struct drm_device *dev,
8894 unsigned frontbuffer_bits,
8895 struct intel_engine_cs *ring)
8896 {
8897 enum pipe pipe;
8898
8899 if (!i915.powersave)
8900 return;
8901
8902 for_each_pipe(pipe) {
8903 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8904 continue;
8905
8906 intel_increase_pllclock(dev, pipe);
8907 if (ring && intel_fbc_enabled(dev))
8908 ring->fbc_dirty = true;
8909 }
8910 }
8911
8912 /**
8913 * intel_fb_obj_invalidate - invalidate frontbuffer object
8914 * @obj: GEM object to invalidate
8915 * @ring: set for asynchronous rendering
8916 *
8917 * This function gets called every time rendering on the given object starts and
8918 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8919 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8920 * until the rendering completes or a flip on this frontbuffer plane is
8921 * scheduled.
8922 */
8923 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8924 struct intel_engine_cs *ring)
8925 {
8926 struct drm_device *dev = obj->base.dev;
8927 struct drm_i915_private *dev_priv = dev->dev_private;
8928
8929 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8930
8931 if (!obj->frontbuffer_bits)
8932 return;
8933
8934 if (ring) {
8935 mutex_lock(&dev_priv->fb_tracking.lock);
8936 dev_priv->fb_tracking.busy_bits
8937 |= obj->frontbuffer_bits;
8938 dev_priv->fb_tracking.flip_bits
8939 &= ~obj->frontbuffer_bits;
8940 mutex_unlock(&dev_priv->fb_tracking.lock);
8941 }
8942
8943 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8944
8945 intel_edp_psr_exit(dev);
8946 }
8947
8948 /**
8949 * intel_frontbuffer_flush - flush frontbuffer
8950 * @dev: DRM device
8951 * @frontbuffer_bits: frontbuffer plane tracking bits
8952 *
8953 * This function gets called every time rendering on the given planes has
8954 * completed and frontbuffer caching can be started again. Flushes will get
8955 * delayed if they're blocked by some oustanding asynchronous rendering.
8956 *
8957 * Can be called without any locks held.
8958 */
8959 void intel_frontbuffer_flush(struct drm_device *dev,
8960 unsigned frontbuffer_bits)
8961 {
8962 struct drm_i915_private *dev_priv = dev->dev_private;
8963
8964 /* Delay flushing when rings are still busy.*/
8965 mutex_lock(&dev_priv->fb_tracking.lock);
8966 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8967 mutex_unlock(&dev_priv->fb_tracking.lock);
8968
8969 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8970
8971 intel_edp_psr_exit(dev);
8972 }
8973
8974 /**
8975 * intel_fb_obj_flush - flush frontbuffer object
8976 * @obj: GEM object to flush
8977 * @retire: set when retiring asynchronous rendering
8978 *
8979 * This function gets called every time rendering on the given object has
8980 * completed and frontbuffer caching can be started again. If @retire is true
8981 * then any delayed flushes will be unblocked.
8982 */
8983 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8984 bool retire)
8985 {
8986 struct drm_device *dev = obj->base.dev;
8987 struct drm_i915_private *dev_priv = dev->dev_private;
8988 unsigned frontbuffer_bits;
8989
8990 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8991
8992 if (!obj->frontbuffer_bits)
8993 return;
8994
8995 frontbuffer_bits = obj->frontbuffer_bits;
8996
8997 if (retire) {
8998 mutex_lock(&dev_priv->fb_tracking.lock);
8999 /* Filter out new bits since rendering started. */
9000 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9001
9002 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9003 mutex_unlock(&dev_priv->fb_tracking.lock);
9004 }
9005
9006 intel_frontbuffer_flush(dev, frontbuffer_bits);
9007 }
9008
9009 /**
9010 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9011 * @dev: DRM device
9012 * @frontbuffer_bits: frontbuffer plane tracking bits
9013 *
9014 * This function gets called after scheduling a flip on @obj. The actual
9015 * frontbuffer flushing will be delayed until completion is signalled with
9016 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9017 * flush will be cancelled.
9018 *
9019 * Can be called without any locks held.
9020 */
9021 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9022 unsigned frontbuffer_bits)
9023 {
9024 struct drm_i915_private *dev_priv = dev->dev_private;
9025
9026 mutex_lock(&dev_priv->fb_tracking.lock);
9027 dev_priv->fb_tracking.flip_bits
9028 |= frontbuffer_bits;
9029 mutex_unlock(&dev_priv->fb_tracking.lock);
9030 }
9031
9032 /**
9033 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9034 * @dev: DRM device
9035 * @frontbuffer_bits: frontbuffer plane tracking bits
9036 *
9037 * This function gets called after the flip has been latched and will complete
9038 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9039 *
9040 * Can be called without any locks held.
9041 */
9042 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9043 unsigned frontbuffer_bits)
9044 {
9045 struct drm_i915_private *dev_priv = dev->dev_private;
9046
9047 mutex_lock(&dev_priv->fb_tracking.lock);
9048 /* Mask any cancelled flips. */
9049 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9050 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9051 mutex_unlock(&dev_priv->fb_tracking.lock);
9052
9053 intel_frontbuffer_flush(dev, frontbuffer_bits);
9054 }
9055
9056 static void intel_crtc_destroy(struct drm_crtc *crtc)
9057 {
9058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9059 struct drm_device *dev = crtc->dev;
9060 struct intel_unpin_work *work;
9061 unsigned long flags;
9062
9063 spin_lock_irqsave(&dev->event_lock, flags);
9064 work = intel_crtc->unpin_work;
9065 intel_crtc->unpin_work = NULL;
9066 spin_unlock_irqrestore(&dev->event_lock, flags);
9067
9068 if (work) {
9069 cancel_work_sync(&work->work);
9070 kfree(work);
9071 }
9072
9073 drm_crtc_cleanup(crtc);
9074
9075 kfree(intel_crtc);
9076 }
9077
9078 static void intel_unpin_work_fn(struct work_struct *__work)
9079 {
9080 struct intel_unpin_work *work =
9081 container_of(__work, struct intel_unpin_work, work);
9082 struct drm_device *dev = work->crtc->dev;
9083 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9084
9085 mutex_lock(&dev->struct_mutex);
9086 intel_unpin_fb_obj(work->old_fb_obj);
9087 drm_gem_object_unreference(&work->pending_flip_obj->base);
9088 drm_gem_object_unreference(&work->old_fb_obj->base);
9089
9090 intel_update_fbc(dev);
9091 mutex_unlock(&dev->struct_mutex);
9092
9093 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9094
9095 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9096 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9097
9098 kfree(work);
9099 }
9100
9101 static void do_intel_finish_page_flip(struct drm_device *dev,
9102 struct drm_crtc *crtc)
9103 {
9104 struct drm_i915_private *dev_priv = dev->dev_private;
9105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9106 struct intel_unpin_work *work;
9107 unsigned long flags;
9108
9109 /* Ignore early vblank irqs */
9110 if (intel_crtc == NULL)
9111 return;
9112
9113 spin_lock_irqsave(&dev->event_lock, flags);
9114 work = intel_crtc->unpin_work;
9115
9116 /* Ensure we don't miss a work->pending update ... */
9117 smp_rmb();
9118
9119 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9120 spin_unlock_irqrestore(&dev->event_lock, flags);
9121 return;
9122 }
9123
9124 /* and that the unpin work is consistent wrt ->pending. */
9125 smp_rmb();
9126
9127 intel_crtc->unpin_work = NULL;
9128
9129 if (work->event)
9130 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9131
9132 drm_crtc_vblank_put(crtc);
9133
9134 spin_unlock_irqrestore(&dev->event_lock, flags);
9135
9136 wake_up_all(&dev_priv->pending_flip_queue);
9137
9138 queue_work(dev_priv->wq, &work->work);
9139
9140 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9141 }
9142
9143 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9144 {
9145 struct drm_i915_private *dev_priv = dev->dev_private;
9146 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9147
9148 do_intel_finish_page_flip(dev, crtc);
9149 }
9150
9151 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9152 {
9153 struct drm_i915_private *dev_priv = dev->dev_private;
9154 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9155
9156 do_intel_finish_page_flip(dev, crtc);
9157 }
9158
9159 /* Is 'a' after or equal to 'b'? */
9160 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9161 {
9162 return !((a - b) & 0x80000000);
9163 }
9164
9165 static bool page_flip_finished(struct intel_crtc *crtc)
9166 {
9167 struct drm_device *dev = crtc->base.dev;
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169
9170 /*
9171 * The relevant registers doen't exist on pre-ctg.
9172 * As the flip done interrupt doesn't trigger for mmio
9173 * flips on gmch platforms, a flip count check isn't
9174 * really needed there. But since ctg has the registers,
9175 * include it in the check anyway.
9176 */
9177 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9178 return true;
9179
9180 /*
9181 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9182 * used the same base address. In that case the mmio flip might
9183 * have completed, but the CS hasn't even executed the flip yet.
9184 *
9185 * A flip count check isn't enough as the CS might have updated
9186 * the base address just after start of vblank, but before we
9187 * managed to process the interrupt. This means we'd complete the
9188 * CS flip too soon.
9189 *
9190 * Combining both checks should get us a good enough result. It may
9191 * still happen that the CS flip has been executed, but has not
9192 * yet actually completed. But in case the base address is the same
9193 * anyway, we don't really care.
9194 */
9195 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9196 crtc->unpin_work->gtt_offset &&
9197 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9198 crtc->unpin_work->flip_count);
9199 }
9200
9201 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9202 {
9203 struct drm_i915_private *dev_priv = dev->dev_private;
9204 struct intel_crtc *intel_crtc =
9205 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9206 unsigned long flags;
9207
9208 /* NB: An MMIO update of the plane base pointer will also
9209 * generate a page-flip completion irq, i.e. every modeset
9210 * is also accompanied by a spurious intel_prepare_page_flip().
9211 */
9212 spin_lock_irqsave(&dev->event_lock, flags);
9213 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9214 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9215 spin_unlock_irqrestore(&dev->event_lock, flags);
9216 }
9217
9218 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9219 {
9220 /* Ensure that the work item is consistent when activating it ... */
9221 smp_wmb();
9222 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9223 /* and that it is marked active as soon as the irq could fire. */
9224 smp_wmb();
9225 }
9226
9227 static int intel_gen2_queue_flip(struct drm_device *dev,
9228 struct drm_crtc *crtc,
9229 struct drm_framebuffer *fb,
9230 struct drm_i915_gem_object *obj,
9231 struct intel_engine_cs *ring,
9232 uint32_t flags)
9233 {
9234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9235 u32 flip_mask;
9236 int ret;
9237
9238 ret = intel_ring_begin(ring, 6);
9239 if (ret)
9240 return ret;
9241
9242 /* Can't queue multiple flips, so wait for the previous
9243 * one to finish before executing the next.
9244 */
9245 if (intel_crtc->plane)
9246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9247 else
9248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9250 intel_ring_emit(ring, MI_NOOP);
9251 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9253 intel_ring_emit(ring, fb->pitches[0]);
9254 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9255 intel_ring_emit(ring, 0); /* aux display base address, unused */
9256
9257 intel_mark_page_flip_active(intel_crtc);
9258 __intel_ring_advance(ring);
9259 return 0;
9260 }
9261
9262 static int intel_gen3_queue_flip(struct drm_device *dev,
9263 struct drm_crtc *crtc,
9264 struct drm_framebuffer *fb,
9265 struct drm_i915_gem_object *obj,
9266 struct intel_engine_cs *ring,
9267 uint32_t flags)
9268 {
9269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9270 u32 flip_mask;
9271 int ret;
9272
9273 ret = intel_ring_begin(ring, 6);
9274 if (ret)
9275 return ret;
9276
9277 if (intel_crtc->plane)
9278 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9279 else
9280 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9281 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9282 intel_ring_emit(ring, MI_NOOP);
9283 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9284 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9285 intel_ring_emit(ring, fb->pitches[0]);
9286 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9287 intel_ring_emit(ring, MI_NOOP);
9288
9289 intel_mark_page_flip_active(intel_crtc);
9290 __intel_ring_advance(ring);
9291 return 0;
9292 }
9293
9294 static int intel_gen4_queue_flip(struct drm_device *dev,
9295 struct drm_crtc *crtc,
9296 struct drm_framebuffer *fb,
9297 struct drm_i915_gem_object *obj,
9298 struct intel_engine_cs *ring,
9299 uint32_t flags)
9300 {
9301 struct drm_i915_private *dev_priv = dev->dev_private;
9302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9303 uint32_t pf, pipesrc;
9304 int ret;
9305
9306 ret = intel_ring_begin(ring, 4);
9307 if (ret)
9308 return ret;
9309
9310 /* i965+ uses the linear or tiled offsets from the
9311 * Display Registers (which do not change across a page-flip)
9312 * so we need only reprogram the base address.
9313 */
9314 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9315 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9316 intel_ring_emit(ring, fb->pitches[0]);
9317 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9318 obj->tiling_mode);
9319
9320 /* XXX Enabling the panel-fitter across page-flip is so far
9321 * untested on non-native modes, so ignore it for now.
9322 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9323 */
9324 pf = 0;
9325 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9326 intel_ring_emit(ring, pf | pipesrc);
9327
9328 intel_mark_page_flip_active(intel_crtc);
9329 __intel_ring_advance(ring);
9330 return 0;
9331 }
9332
9333 static int intel_gen6_queue_flip(struct drm_device *dev,
9334 struct drm_crtc *crtc,
9335 struct drm_framebuffer *fb,
9336 struct drm_i915_gem_object *obj,
9337 struct intel_engine_cs *ring,
9338 uint32_t flags)
9339 {
9340 struct drm_i915_private *dev_priv = dev->dev_private;
9341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9342 uint32_t pf, pipesrc;
9343 int ret;
9344
9345 ret = intel_ring_begin(ring, 4);
9346 if (ret)
9347 return ret;
9348
9349 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9350 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9351 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9352 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9353
9354 /* Contrary to the suggestions in the documentation,
9355 * "Enable Panel Fitter" does not seem to be required when page
9356 * flipping with a non-native mode, and worse causes a normal
9357 * modeset to fail.
9358 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9359 */
9360 pf = 0;
9361 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9362 intel_ring_emit(ring, pf | pipesrc);
9363
9364 intel_mark_page_flip_active(intel_crtc);
9365 __intel_ring_advance(ring);
9366 return 0;
9367 }
9368
9369 static int intel_gen7_queue_flip(struct drm_device *dev,
9370 struct drm_crtc *crtc,
9371 struct drm_framebuffer *fb,
9372 struct drm_i915_gem_object *obj,
9373 struct intel_engine_cs *ring,
9374 uint32_t flags)
9375 {
9376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9377 uint32_t plane_bit = 0;
9378 int len, ret;
9379
9380 switch (intel_crtc->plane) {
9381 case PLANE_A:
9382 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9383 break;
9384 case PLANE_B:
9385 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9386 break;
9387 case PLANE_C:
9388 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9389 break;
9390 default:
9391 WARN_ONCE(1, "unknown plane in flip command\n");
9392 return -ENODEV;
9393 }
9394
9395 len = 4;
9396 if (ring->id == RCS) {
9397 len += 6;
9398 /*
9399 * On Gen 8, SRM is now taking an extra dword to accommodate
9400 * 48bits addresses, and we need a NOOP for the batch size to
9401 * stay even.
9402 */
9403 if (IS_GEN8(dev))
9404 len += 2;
9405 }
9406
9407 /*
9408 * BSpec MI_DISPLAY_FLIP for IVB:
9409 * "The full packet must be contained within the same cache line."
9410 *
9411 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9412 * cacheline, if we ever start emitting more commands before
9413 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9414 * then do the cacheline alignment, and finally emit the
9415 * MI_DISPLAY_FLIP.
9416 */
9417 ret = intel_ring_cacheline_align(ring);
9418 if (ret)
9419 return ret;
9420
9421 ret = intel_ring_begin(ring, len);
9422 if (ret)
9423 return ret;
9424
9425 /* Unmask the flip-done completion message. Note that the bspec says that
9426 * we should do this for both the BCS and RCS, and that we must not unmask
9427 * more than one flip event at any time (or ensure that one flip message
9428 * can be sent by waiting for flip-done prior to queueing new flips).
9429 * Experimentation says that BCS works despite DERRMR masking all
9430 * flip-done completion events and that unmasking all planes at once
9431 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9432 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9433 */
9434 if (ring->id == RCS) {
9435 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9436 intel_ring_emit(ring, DERRMR);
9437 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9438 DERRMR_PIPEB_PRI_FLIP_DONE |
9439 DERRMR_PIPEC_PRI_FLIP_DONE));
9440 if (IS_GEN8(dev))
9441 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9442 MI_SRM_LRM_GLOBAL_GTT);
9443 else
9444 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9445 MI_SRM_LRM_GLOBAL_GTT);
9446 intel_ring_emit(ring, DERRMR);
9447 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9448 if (IS_GEN8(dev)) {
9449 intel_ring_emit(ring, 0);
9450 intel_ring_emit(ring, MI_NOOP);
9451 }
9452 }
9453
9454 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9455 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9456 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9457 intel_ring_emit(ring, (MI_NOOP));
9458
9459 intel_mark_page_flip_active(intel_crtc);
9460 __intel_ring_advance(ring);
9461 return 0;
9462 }
9463
9464 static bool use_mmio_flip(struct intel_engine_cs *ring,
9465 struct drm_i915_gem_object *obj)
9466 {
9467 /*
9468 * This is not being used for older platforms, because
9469 * non-availability of flip done interrupt forces us to use
9470 * CS flips. Older platforms derive flip done using some clever
9471 * tricks involving the flip_pending status bits and vblank irqs.
9472 * So using MMIO flips there would disrupt this mechanism.
9473 */
9474
9475 if (ring == NULL)
9476 return true;
9477
9478 if (INTEL_INFO(ring->dev)->gen < 5)
9479 return false;
9480
9481 if (i915.use_mmio_flip < 0)
9482 return false;
9483 else if (i915.use_mmio_flip > 0)
9484 return true;
9485 else
9486 return ring != obj->ring;
9487 }
9488
9489 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9490 {
9491 struct drm_device *dev = intel_crtc->base.dev;
9492 struct drm_i915_private *dev_priv = dev->dev_private;
9493 struct intel_framebuffer *intel_fb =
9494 to_intel_framebuffer(intel_crtc->base.primary->fb);
9495 struct drm_i915_gem_object *obj = intel_fb->obj;
9496 u32 dspcntr;
9497 u32 reg;
9498
9499 intel_mark_page_flip_active(intel_crtc);
9500
9501 reg = DSPCNTR(intel_crtc->plane);
9502 dspcntr = I915_READ(reg);
9503
9504 if (INTEL_INFO(dev)->gen >= 4) {
9505 if (obj->tiling_mode != I915_TILING_NONE)
9506 dspcntr |= DISPPLANE_TILED;
9507 else
9508 dspcntr &= ~DISPPLANE_TILED;
9509 }
9510 I915_WRITE(reg, dspcntr);
9511
9512 I915_WRITE(DSPSURF(intel_crtc->plane),
9513 intel_crtc->unpin_work->gtt_offset);
9514 POSTING_READ(DSPSURF(intel_crtc->plane));
9515 }
9516
9517 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9518 {
9519 struct intel_engine_cs *ring;
9520 int ret;
9521
9522 lockdep_assert_held(&obj->base.dev->struct_mutex);
9523
9524 if (!obj->last_write_seqno)
9525 return 0;
9526
9527 ring = obj->ring;
9528
9529 if (i915_seqno_passed(ring->get_seqno(ring, true),
9530 obj->last_write_seqno))
9531 return 0;
9532
9533 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9534 if (ret)
9535 return ret;
9536
9537 if (WARN_ON(!ring->irq_get(ring)))
9538 return 0;
9539
9540 return 1;
9541 }
9542
9543 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9544 {
9545 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9546 struct intel_crtc *intel_crtc;
9547 unsigned long irq_flags;
9548 u32 seqno;
9549
9550 seqno = ring->get_seqno(ring, false);
9551
9552 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9553 for_each_intel_crtc(ring->dev, intel_crtc) {
9554 struct intel_mmio_flip *mmio_flip;
9555
9556 mmio_flip = &intel_crtc->mmio_flip;
9557 if (mmio_flip->seqno == 0)
9558 continue;
9559
9560 if (ring->id != mmio_flip->ring_id)
9561 continue;
9562
9563 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9564 intel_do_mmio_flip(intel_crtc);
9565 mmio_flip->seqno = 0;
9566 ring->irq_put(ring);
9567 }
9568 }
9569 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9570 }
9571
9572 static int intel_queue_mmio_flip(struct drm_device *dev,
9573 struct drm_crtc *crtc,
9574 struct drm_framebuffer *fb,
9575 struct drm_i915_gem_object *obj,
9576 struct intel_engine_cs *ring,
9577 uint32_t flags)
9578 {
9579 struct drm_i915_private *dev_priv = dev->dev_private;
9580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9581 unsigned long irq_flags;
9582 int ret;
9583
9584 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9585 return -EBUSY;
9586
9587 ret = intel_postpone_flip(obj);
9588 if (ret < 0)
9589 return ret;
9590 if (ret == 0) {
9591 intel_do_mmio_flip(intel_crtc);
9592 return 0;
9593 }
9594
9595 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9596 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9597 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9598 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9599
9600 /*
9601 * Double check to catch cases where irq fired before
9602 * mmio flip data was ready
9603 */
9604 intel_notify_mmio_flip(obj->ring);
9605 return 0;
9606 }
9607
9608 static int intel_default_queue_flip(struct drm_device *dev,
9609 struct drm_crtc *crtc,
9610 struct drm_framebuffer *fb,
9611 struct drm_i915_gem_object *obj,
9612 struct intel_engine_cs *ring,
9613 uint32_t flags)
9614 {
9615 return -ENODEV;
9616 }
9617
9618 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9619 struct drm_framebuffer *fb,
9620 struct drm_pending_vblank_event *event,
9621 uint32_t page_flip_flags)
9622 {
9623 struct drm_device *dev = crtc->dev;
9624 struct drm_i915_private *dev_priv = dev->dev_private;
9625 struct drm_framebuffer *old_fb = crtc->primary->fb;
9626 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9628 enum pipe pipe = intel_crtc->pipe;
9629 struct intel_unpin_work *work;
9630 struct intel_engine_cs *ring;
9631 unsigned long flags;
9632 int ret;
9633
9634 /*
9635 * drm_mode_page_flip_ioctl() should already catch this, but double
9636 * check to be safe. In the future we may enable pageflipping from
9637 * a disabled primary plane.
9638 */
9639 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9640 return -EBUSY;
9641
9642 /* Can't change pixel format via MI display flips. */
9643 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9644 return -EINVAL;
9645
9646 /*
9647 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9648 * Note that pitch changes could also affect these register.
9649 */
9650 if (INTEL_INFO(dev)->gen > 3 &&
9651 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9652 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9653 return -EINVAL;
9654
9655 if (i915_terminally_wedged(&dev_priv->gpu_error))
9656 goto out_hang;
9657
9658 work = kzalloc(sizeof(*work), GFP_KERNEL);
9659 if (work == NULL)
9660 return -ENOMEM;
9661
9662 work->event = event;
9663 work->crtc = crtc;
9664 work->old_fb_obj = intel_fb_obj(old_fb);
9665 INIT_WORK(&work->work, intel_unpin_work_fn);
9666
9667 ret = drm_crtc_vblank_get(crtc);
9668 if (ret)
9669 goto free_work;
9670
9671 /* We borrow the event spin lock for protecting unpin_work */
9672 spin_lock_irqsave(&dev->event_lock, flags);
9673 if (intel_crtc->unpin_work) {
9674 spin_unlock_irqrestore(&dev->event_lock, flags);
9675 kfree(work);
9676 drm_crtc_vblank_put(crtc);
9677
9678 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9679 return -EBUSY;
9680 }
9681 intel_crtc->unpin_work = work;
9682 spin_unlock_irqrestore(&dev->event_lock, flags);
9683
9684 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9685 flush_workqueue(dev_priv->wq);
9686
9687 ret = i915_mutex_lock_interruptible(dev);
9688 if (ret)
9689 goto cleanup;
9690
9691 /* Reference the objects for the scheduled work. */
9692 drm_gem_object_reference(&work->old_fb_obj->base);
9693 drm_gem_object_reference(&obj->base);
9694
9695 crtc->primary->fb = fb;
9696
9697 work->pending_flip_obj = obj;
9698
9699 work->enable_stall_check = true;
9700
9701 atomic_inc(&intel_crtc->unpin_work_count);
9702 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9703
9704 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9705 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9706
9707 if (IS_VALLEYVIEW(dev)) {
9708 ring = &dev_priv->ring[BCS];
9709 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9710 /* vlv: DISPLAY_FLIP fails to change tiling */
9711 ring = NULL;
9712 } else if (IS_IVYBRIDGE(dev)) {
9713 ring = &dev_priv->ring[BCS];
9714 } else if (INTEL_INFO(dev)->gen >= 7) {
9715 ring = obj->ring;
9716 if (ring == NULL || ring->id != RCS)
9717 ring = &dev_priv->ring[BCS];
9718 } else {
9719 ring = &dev_priv->ring[RCS];
9720 }
9721
9722 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9723 if (ret)
9724 goto cleanup_pending;
9725
9726 work->gtt_offset =
9727 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9728
9729 if (use_mmio_flip(ring, obj))
9730 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9731 page_flip_flags);
9732 else
9733 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9734 page_flip_flags);
9735 if (ret)
9736 goto cleanup_unpin;
9737
9738 i915_gem_track_fb(work->old_fb_obj, obj,
9739 INTEL_FRONTBUFFER_PRIMARY(pipe));
9740
9741 intel_disable_fbc(dev);
9742 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9743 mutex_unlock(&dev->struct_mutex);
9744
9745 trace_i915_flip_request(intel_crtc->plane, obj);
9746
9747 return 0;
9748
9749 cleanup_unpin:
9750 intel_unpin_fb_obj(obj);
9751 cleanup_pending:
9752 atomic_dec(&intel_crtc->unpin_work_count);
9753 crtc->primary->fb = old_fb;
9754 drm_gem_object_unreference(&work->old_fb_obj->base);
9755 drm_gem_object_unreference(&obj->base);
9756 mutex_unlock(&dev->struct_mutex);
9757
9758 cleanup:
9759 spin_lock_irqsave(&dev->event_lock, flags);
9760 intel_crtc->unpin_work = NULL;
9761 spin_unlock_irqrestore(&dev->event_lock, flags);
9762
9763 drm_crtc_vblank_put(crtc);
9764 free_work:
9765 kfree(work);
9766
9767 if (ret == -EIO) {
9768 out_hang:
9769 intel_crtc_wait_for_pending_flips(crtc);
9770 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9771 if (ret == 0 && event)
9772 drm_send_vblank_event(dev, pipe, event);
9773 }
9774 return ret;
9775 }
9776
9777 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9778 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9779 .load_lut = intel_crtc_load_lut,
9780 };
9781
9782 /**
9783 * intel_modeset_update_staged_output_state
9784 *
9785 * Updates the staged output configuration state, e.g. after we've read out the
9786 * current hw state.
9787 */
9788 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9789 {
9790 struct intel_crtc *crtc;
9791 struct intel_encoder *encoder;
9792 struct intel_connector *connector;
9793
9794 list_for_each_entry(connector, &dev->mode_config.connector_list,
9795 base.head) {
9796 connector->new_encoder =
9797 to_intel_encoder(connector->base.encoder);
9798 }
9799
9800 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9801 base.head) {
9802 encoder->new_crtc =
9803 to_intel_crtc(encoder->base.crtc);
9804 }
9805
9806 for_each_intel_crtc(dev, crtc) {
9807 crtc->new_enabled = crtc->base.enabled;
9808
9809 if (crtc->new_enabled)
9810 crtc->new_config = &crtc->config;
9811 else
9812 crtc->new_config = NULL;
9813 }
9814 }
9815
9816 /**
9817 * intel_modeset_commit_output_state
9818 *
9819 * This function copies the stage display pipe configuration to the real one.
9820 */
9821 static void intel_modeset_commit_output_state(struct drm_device *dev)
9822 {
9823 struct intel_crtc *crtc;
9824 struct intel_encoder *encoder;
9825 struct intel_connector *connector;
9826
9827 list_for_each_entry(connector, &dev->mode_config.connector_list,
9828 base.head) {
9829 connector->base.encoder = &connector->new_encoder->base;
9830 }
9831
9832 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9833 base.head) {
9834 encoder->base.crtc = &encoder->new_crtc->base;
9835 }
9836
9837 for_each_intel_crtc(dev, crtc) {
9838 crtc->base.enabled = crtc->new_enabled;
9839 }
9840 }
9841
9842 static void
9843 connected_sink_compute_bpp(struct intel_connector *connector,
9844 struct intel_crtc_config *pipe_config)
9845 {
9846 int bpp = pipe_config->pipe_bpp;
9847
9848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9849 connector->base.base.id,
9850 connector->base.name);
9851
9852 /* Don't use an invalid EDID bpc value */
9853 if (connector->base.display_info.bpc &&
9854 connector->base.display_info.bpc * 3 < bpp) {
9855 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9856 bpp, connector->base.display_info.bpc*3);
9857 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9858 }
9859
9860 /* Clamp bpp to 8 on screens without EDID 1.4 */
9861 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9862 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9863 bpp);
9864 pipe_config->pipe_bpp = 24;
9865 }
9866 }
9867
9868 static int
9869 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9870 struct drm_framebuffer *fb,
9871 struct intel_crtc_config *pipe_config)
9872 {
9873 struct drm_device *dev = crtc->base.dev;
9874 struct intel_connector *connector;
9875 int bpp;
9876
9877 switch (fb->pixel_format) {
9878 case DRM_FORMAT_C8:
9879 bpp = 8*3; /* since we go through a colormap */
9880 break;
9881 case DRM_FORMAT_XRGB1555:
9882 case DRM_FORMAT_ARGB1555:
9883 /* checked in intel_framebuffer_init already */
9884 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9885 return -EINVAL;
9886 case DRM_FORMAT_RGB565:
9887 bpp = 6*3; /* min is 18bpp */
9888 break;
9889 case DRM_FORMAT_XBGR8888:
9890 case DRM_FORMAT_ABGR8888:
9891 /* checked in intel_framebuffer_init already */
9892 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9893 return -EINVAL;
9894 case DRM_FORMAT_XRGB8888:
9895 case DRM_FORMAT_ARGB8888:
9896 bpp = 8*3;
9897 break;
9898 case DRM_FORMAT_XRGB2101010:
9899 case DRM_FORMAT_ARGB2101010:
9900 case DRM_FORMAT_XBGR2101010:
9901 case DRM_FORMAT_ABGR2101010:
9902 /* checked in intel_framebuffer_init already */
9903 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9904 return -EINVAL;
9905 bpp = 10*3;
9906 break;
9907 /* TODO: gen4+ supports 16 bpc floating point, too. */
9908 default:
9909 DRM_DEBUG_KMS("unsupported depth\n");
9910 return -EINVAL;
9911 }
9912
9913 pipe_config->pipe_bpp = bpp;
9914
9915 /* Clamp display bpp to EDID value */
9916 list_for_each_entry(connector, &dev->mode_config.connector_list,
9917 base.head) {
9918 if (!connector->new_encoder ||
9919 connector->new_encoder->new_crtc != crtc)
9920 continue;
9921
9922 connected_sink_compute_bpp(connector, pipe_config);
9923 }
9924
9925 return bpp;
9926 }
9927
9928 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9929 {
9930 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9931 "type: 0x%x flags: 0x%x\n",
9932 mode->crtc_clock,
9933 mode->crtc_hdisplay, mode->crtc_hsync_start,
9934 mode->crtc_hsync_end, mode->crtc_htotal,
9935 mode->crtc_vdisplay, mode->crtc_vsync_start,
9936 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9937 }
9938
9939 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9940 struct intel_crtc_config *pipe_config,
9941 const char *context)
9942 {
9943 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9944 context, pipe_name(crtc->pipe));
9945
9946 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9947 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9948 pipe_config->pipe_bpp, pipe_config->dither);
9949 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9950 pipe_config->has_pch_encoder,
9951 pipe_config->fdi_lanes,
9952 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9953 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9954 pipe_config->fdi_m_n.tu);
9955 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9956 pipe_config->has_dp_encoder,
9957 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9958 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9959 pipe_config->dp_m_n.tu);
9960 DRM_DEBUG_KMS("requested mode:\n");
9961 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9962 DRM_DEBUG_KMS("adjusted mode:\n");
9963 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9964 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9965 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9966 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9967 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9968 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9969 pipe_config->gmch_pfit.control,
9970 pipe_config->gmch_pfit.pgm_ratios,
9971 pipe_config->gmch_pfit.lvds_border_bits);
9972 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9973 pipe_config->pch_pfit.pos,
9974 pipe_config->pch_pfit.size,
9975 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9976 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9977 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9978 }
9979
9980 static bool encoders_cloneable(const struct intel_encoder *a,
9981 const struct intel_encoder *b)
9982 {
9983 /* masks could be asymmetric, so check both ways */
9984 return a == b || (a->cloneable & (1 << b->type) &&
9985 b->cloneable & (1 << a->type));
9986 }
9987
9988 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9989 struct intel_encoder *encoder)
9990 {
9991 struct drm_device *dev = crtc->base.dev;
9992 struct intel_encoder *source_encoder;
9993
9994 list_for_each_entry(source_encoder,
9995 &dev->mode_config.encoder_list, base.head) {
9996 if (source_encoder->new_crtc != crtc)
9997 continue;
9998
9999 if (!encoders_cloneable(encoder, source_encoder))
10000 return false;
10001 }
10002
10003 return true;
10004 }
10005
10006 static bool check_encoder_cloning(struct intel_crtc *crtc)
10007 {
10008 struct drm_device *dev = crtc->base.dev;
10009 struct intel_encoder *encoder;
10010
10011 list_for_each_entry(encoder,
10012 &dev->mode_config.encoder_list, base.head) {
10013 if (encoder->new_crtc != crtc)
10014 continue;
10015
10016 if (!check_single_encoder_cloning(crtc, encoder))
10017 return false;
10018 }
10019
10020 return true;
10021 }
10022
10023 static struct intel_crtc_config *
10024 intel_modeset_pipe_config(struct drm_crtc *crtc,
10025 struct drm_framebuffer *fb,
10026 struct drm_display_mode *mode)
10027 {
10028 struct drm_device *dev = crtc->dev;
10029 struct intel_encoder *encoder;
10030 struct intel_crtc_config *pipe_config;
10031 int plane_bpp, ret = -EINVAL;
10032 bool retry = true;
10033
10034 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10035 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10036 return ERR_PTR(-EINVAL);
10037 }
10038
10039 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10040 if (!pipe_config)
10041 return ERR_PTR(-ENOMEM);
10042
10043 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10044 drm_mode_copy(&pipe_config->requested_mode, mode);
10045
10046 pipe_config->cpu_transcoder =
10047 (enum transcoder) to_intel_crtc(crtc)->pipe;
10048 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10049
10050 /*
10051 * Sanitize sync polarity flags based on requested ones. If neither
10052 * positive or negative polarity is requested, treat this as meaning
10053 * negative polarity.
10054 */
10055 if (!(pipe_config->adjusted_mode.flags &
10056 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10057 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10058
10059 if (!(pipe_config->adjusted_mode.flags &
10060 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10061 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10062
10063 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10064 * plane pixel format and any sink constraints into account. Returns the
10065 * source plane bpp so that dithering can be selected on mismatches
10066 * after encoders and crtc also have had their say. */
10067 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10068 fb, pipe_config);
10069 if (plane_bpp < 0)
10070 goto fail;
10071
10072 /*
10073 * Determine the real pipe dimensions. Note that stereo modes can
10074 * increase the actual pipe size due to the frame doubling and
10075 * insertion of additional space for blanks between the frame. This
10076 * is stored in the crtc timings. We use the requested mode to do this
10077 * computation to clearly distinguish it from the adjusted mode, which
10078 * can be changed by the connectors in the below retry loop.
10079 */
10080 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10081 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10082 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10083
10084 encoder_retry:
10085 /* Ensure the port clock defaults are reset when retrying. */
10086 pipe_config->port_clock = 0;
10087 pipe_config->pixel_multiplier = 1;
10088
10089 /* Fill in default crtc timings, allow encoders to overwrite them. */
10090 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10091
10092 /* Pass our mode to the connectors and the CRTC to give them a chance to
10093 * adjust it according to limitations or connector properties, and also
10094 * a chance to reject the mode entirely.
10095 */
10096 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10097 base.head) {
10098
10099 if (&encoder->new_crtc->base != crtc)
10100 continue;
10101
10102 if (!(encoder->compute_config(encoder, pipe_config))) {
10103 DRM_DEBUG_KMS("Encoder config failure\n");
10104 goto fail;
10105 }
10106 }
10107
10108 /* Set default port clock if not overwritten by the encoder. Needs to be
10109 * done afterwards in case the encoder adjusts the mode. */
10110 if (!pipe_config->port_clock)
10111 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10112 * pipe_config->pixel_multiplier;
10113
10114 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10115 if (ret < 0) {
10116 DRM_DEBUG_KMS("CRTC fixup failed\n");
10117 goto fail;
10118 }
10119
10120 if (ret == RETRY) {
10121 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10122 ret = -EINVAL;
10123 goto fail;
10124 }
10125
10126 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10127 retry = false;
10128 goto encoder_retry;
10129 }
10130
10131 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10132 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10133 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10134
10135 return pipe_config;
10136 fail:
10137 kfree(pipe_config);
10138 return ERR_PTR(ret);
10139 }
10140
10141 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10142 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10143 static void
10144 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10145 unsigned *prepare_pipes, unsigned *disable_pipes)
10146 {
10147 struct intel_crtc *intel_crtc;
10148 struct drm_device *dev = crtc->dev;
10149 struct intel_encoder *encoder;
10150 struct intel_connector *connector;
10151 struct drm_crtc *tmp_crtc;
10152
10153 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10154
10155 /* Check which crtcs have changed outputs connected to them, these need
10156 * to be part of the prepare_pipes mask. We don't (yet) support global
10157 * modeset across multiple crtcs, so modeset_pipes will only have one
10158 * bit set at most. */
10159 list_for_each_entry(connector, &dev->mode_config.connector_list,
10160 base.head) {
10161 if (connector->base.encoder == &connector->new_encoder->base)
10162 continue;
10163
10164 if (connector->base.encoder) {
10165 tmp_crtc = connector->base.encoder->crtc;
10166
10167 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10168 }
10169
10170 if (connector->new_encoder)
10171 *prepare_pipes |=
10172 1 << connector->new_encoder->new_crtc->pipe;
10173 }
10174
10175 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10176 base.head) {
10177 if (encoder->base.crtc == &encoder->new_crtc->base)
10178 continue;
10179
10180 if (encoder->base.crtc) {
10181 tmp_crtc = encoder->base.crtc;
10182
10183 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10184 }
10185
10186 if (encoder->new_crtc)
10187 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10188 }
10189
10190 /* Check for pipes that will be enabled/disabled ... */
10191 for_each_intel_crtc(dev, intel_crtc) {
10192 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10193 continue;
10194
10195 if (!intel_crtc->new_enabled)
10196 *disable_pipes |= 1 << intel_crtc->pipe;
10197 else
10198 *prepare_pipes |= 1 << intel_crtc->pipe;
10199 }
10200
10201
10202 /* set_mode is also used to update properties on life display pipes. */
10203 intel_crtc = to_intel_crtc(crtc);
10204 if (intel_crtc->new_enabled)
10205 *prepare_pipes |= 1 << intel_crtc->pipe;
10206
10207 /*
10208 * For simplicity do a full modeset on any pipe where the output routing
10209 * changed. We could be more clever, but that would require us to be
10210 * more careful with calling the relevant encoder->mode_set functions.
10211 */
10212 if (*prepare_pipes)
10213 *modeset_pipes = *prepare_pipes;
10214
10215 /* ... and mask these out. */
10216 *modeset_pipes &= ~(*disable_pipes);
10217 *prepare_pipes &= ~(*disable_pipes);
10218
10219 /*
10220 * HACK: We don't (yet) fully support global modesets. intel_set_config
10221 * obies this rule, but the modeset restore mode of
10222 * intel_modeset_setup_hw_state does not.
10223 */
10224 *modeset_pipes &= 1 << intel_crtc->pipe;
10225 *prepare_pipes &= 1 << intel_crtc->pipe;
10226
10227 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10228 *modeset_pipes, *prepare_pipes, *disable_pipes);
10229 }
10230
10231 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10232 {
10233 struct drm_encoder *encoder;
10234 struct drm_device *dev = crtc->dev;
10235
10236 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10237 if (encoder->crtc == crtc)
10238 return true;
10239
10240 return false;
10241 }
10242
10243 static void
10244 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10245 {
10246 struct intel_encoder *intel_encoder;
10247 struct intel_crtc *intel_crtc;
10248 struct drm_connector *connector;
10249
10250 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10251 base.head) {
10252 if (!intel_encoder->base.crtc)
10253 continue;
10254
10255 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10256
10257 if (prepare_pipes & (1 << intel_crtc->pipe))
10258 intel_encoder->connectors_active = false;
10259 }
10260
10261 intel_modeset_commit_output_state(dev);
10262
10263 /* Double check state. */
10264 for_each_intel_crtc(dev, intel_crtc) {
10265 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10266 WARN_ON(intel_crtc->new_config &&
10267 intel_crtc->new_config != &intel_crtc->config);
10268 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10269 }
10270
10271 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10272 if (!connector->encoder || !connector->encoder->crtc)
10273 continue;
10274
10275 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10276
10277 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10278 struct drm_property *dpms_property =
10279 dev->mode_config.dpms_property;
10280
10281 connector->dpms = DRM_MODE_DPMS_ON;
10282 drm_object_property_set_value(&connector->base,
10283 dpms_property,
10284 DRM_MODE_DPMS_ON);
10285
10286 intel_encoder = to_intel_encoder(connector->encoder);
10287 intel_encoder->connectors_active = true;
10288 }
10289 }
10290
10291 }
10292
10293 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10294 {
10295 int diff;
10296
10297 if (clock1 == clock2)
10298 return true;
10299
10300 if (!clock1 || !clock2)
10301 return false;
10302
10303 diff = abs(clock1 - clock2);
10304
10305 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10306 return true;
10307
10308 return false;
10309 }
10310
10311 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10312 list_for_each_entry((intel_crtc), \
10313 &(dev)->mode_config.crtc_list, \
10314 base.head) \
10315 if (mask & (1 <<(intel_crtc)->pipe))
10316
10317 static bool
10318 intel_pipe_config_compare(struct drm_device *dev,
10319 struct intel_crtc_config *current_config,
10320 struct intel_crtc_config *pipe_config)
10321 {
10322 #define PIPE_CONF_CHECK_X(name) \
10323 if (current_config->name != pipe_config->name) { \
10324 DRM_ERROR("mismatch in " #name " " \
10325 "(expected 0x%08x, found 0x%08x)\n", \
10326 current_config->name, \
10327 pipe_config->name); \
10328 return false; \
10329 }
10330
10331 #define PIPE_CONF_CHECK_I(name) \
10332 if (current_config->name != pipe_config->name) { \
10333 DRM_ERROR("mismatch in " #name " " \
10334 "(expected %i, found %i)\n", \
10335 current_config->name, \
10336 pipe_config->name); \
10337 return false; \
10338 }
10339
10340 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10341 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10342 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10343 "(expected %i, found %i)\n", \
10344 current_config->name & (mask), \
10345 pipe_config->name & (mask)); \
10346 return false; \
10347 }
10348
10349 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10350 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10351 DRM_ERROR("mismatch in " #name " " \
10352 "(expected %i, found %i)\n", \
10353 current_config->name, \
10354 pipe_config->name); \
10355 return false; \
10356 }
10357
10358 #define PIPE_CONF_QUIRK(quirk) \
10359 ((current_config->quirks | pipe_config->quirks) & (quirk))
10360
10361 PIPE_CONF_CHECK_I(cpu_transcoder);
10362
10363 PIPE_CONF_CHECK_I(has_pch_encoder);
10364 PIPE_CONF_CHECK_I(fdi_lanes);
10365 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10366 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10367 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10368 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10369 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10370
10371 PIPE_CONF_CHECK_I(has_dp_encoder);
10372 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10373 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10374 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10375 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10376 PIPE_CONF_CHECK_I(dp_m_n.tu);
10377
10378 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10379 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10380 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10381 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10382 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10383 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10384
10385 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10386 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10387 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10388 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10389 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10390 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10391
10392 PIPE_CONF_CHECK_I(pixel_multiplier);
10393 PIPE_CONF_CHECK_I(has_hdmi_sink);
10394 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10395 IS_VALLEYVIEW(dev))
10396 PIPE_CONF_CHECK_I(limited_color_range);
10397
10398 PIPE_CONF_CHECK_I(has_audio);
10399
10400 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10401 DRM_MODE_FLAG_INTERLACE);
10402
10403 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10404 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10405 DRM_MODE_FLAG_PHSYNC);
10406 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10407 DRM_MODE_FLAG_NHSYNC);
10408 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10409 DRM_MODE_FLAG_PVSYNC);
10410 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10411 DRM_MODE_FLAG_NVSYNC);
10412 }
10413
10414 PIPE_CONF_CHECK_I(pipe_src_w);
10415 PIPE_CONF_CHECK_I(pipe_src_h);
10416
10417 /*
10418 * FIXME: BIOS likes to set up a cloned config with lvds+external
10419 * screen. Since we don't yet re-compute the pipe config when moving
10420 * just the lvds port away to another pipe the sw tracking won't match.
10421 *
10422 * Proper atomic modesets with recomputed global state will fix this.
10423 * Until then just don't check gmch state for inherited modes.
10424 */
10425 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10426 PIPE_CONF_CHECK_I(gmch_pfit.control);
10427 /* pfit ratios are autocomputed by the hw on gen4+ */
10428 if (INTEL_INFO(dev)->gen < 4)
10429 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10430 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10431 }
10432
10433 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10434 if (current_config->pch_pfit.enabled) {
10435 PIPE_CONF_CHECK_I(pch_pfit.pos);
10436 PIPE_CONF_CHECK_I(pch_pfit.size);
10437 }
10438
10439 /* BDW+ don't expose a synchronous way to read the state */
10440 if (IS_HASWELL(dev))
10441 PIPE_CONF_CHECK_I(ips_enabled);
10442
10443 PIPE_CONF_CHECK_I(double_wide);
10444
10445 PIPE_CONF_CHECK_X(ddi_pll_sel);
10446
10447 PIPE_CONF_CHECK_I(shared_dpll);
10448 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10449 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10450 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10451 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10452 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10453
10454 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10455 PIPE_CONF_CHECK_I(pipe_bpp);
10456
10457 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10458 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10459
10460 #undef PIPE_CONF_CHECK_X
10461 #undef PIPE_CONF_CHECK_I
10462 #undef PIPE_CONF_CHECK_FLAGS
10463 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10464 #undef PIPE_CONF_QUIRK
10465
10466 return true;
10467 }
10468
10469 static void
10470 check_connector_state(struct drm_device *dev)
10471 {
10472 struct intel_connector *connector;
10473
10474 list_for_each_entry(connector, &dev->mode_config.connector_list,
10475 base.head) {
10476 /* This also checks the encoder/connector hw state with the
10477 * ->get_hw_state callbacks. */
10478 intel_connector_check_state(connector);
10479
10480 WARN(&connector->new_encoder->base != connector->base.encoder,
10481 "connector's staged encoder doesn't match current encoder\n");
10482 }
10483 }
10484
10485 static void
10486 check_encoder_state(struct drm_device *dev)
10487 {
10488 struct intel_encoder *encoder;
10489 struct intel_connector *connector;
10490
10491 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10492 base.head) {
10493 bool enabled = false;
10494 bool active = false;
10495 enum pipe pipe, tracked_pipe;
10496
10497 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10498 encoder->base.base.id,
10499 encoder->base.name);
10500
10501 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10502 "encoder's stage crtc doesn't match current crtc\n");
10503 WARN(encoder->connectors_active && !encoder->base.crtc,
10504 "encoder's active_connectors set, but no crtc\n");
10505
10506 list_for_each_entry(connector, &dev->mode_config.connector_list,
10507 base.head) {
10508 if (connector->base.encoder != &encoder->base)
10509 continue;
10510 enabled = true;
10511 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10512 active = true;
10513 }
10514 WARN(!!encoder->base.crtc != enabled,
10515 "encoder's enabled state mismatch "
10516 "(expected %i, found %i)\n",
10517 !!encoder->base.crtc, enabled);
10518 WARN(active && !encoder->base.crtc,
10519 "active encoder with no crtc\n");
10520
10521 WARN(encoder->connectors_active != active,
10522 "encoder's computed active state doesn't match tracked active state "
10523 "(expected %i, found %i)\n", active, encoder->connectors_active);
10524
10525 active = encoder->get_hw_state(encoder, &pipe);
10526 WARN(active != encoder->connectors_active,
10527 "encoder's hw state doesn't match sw tracking "
10528 "(expected %i, found %i)\n",
10529 encoder->connectors_active, active);
10530
10531 if (!encoder->base.crtc)
10532 continue;
10533
10534 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10535 WARN(active && pipe != tracked_pipe,
10536 "active encoder's pipe doesn't match"
10537 "(expected %i, found %i)\n",
10538 tracked_pipe, pipe);
10539
10540 }
10541 }
10542
10543 static void
10544 check_crtc_state(struct drm_device *dev)
10545 {
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547 struct intel_crtc *crtc;
10548 struct intel_encoder *encoder;
10549 struct intel_crtc_config pipe_config;
10550
10551 for_each_intel_crtc(dev, crtc) {
10552 bool enabled = false;
10553 bool active = false;
10554
10555 memset(&pipe_config, 0, sizeof(pipe_config));
10556
10557 DRM_DEBUG_KMS("[CRTC:%d]\n",
10558 crtc->base.base.id);
10559
10560 WARN(crtc->active && !crtc->base.enabled,
10561 "active crtc, but not enabled in sw tracking\n");
10562
10563 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10564 base.head) {
10565 if (encoder->base.crtc != &crtc->base)
10566 continue;
10567 enabled = true;
10568 if (encoder->connectors_active)
10569 active = true;
10570 }
10571
10572 WARN(active != crtc->active,
10573 "crtc's computed active state doesn't match tracked active state "
10574 "(expected %i, found %i)\n", active, crtc->active);
10575 WARN(enabled != crtc->base.enabled,
10576 "crtc's computed enabled state doesn't match tracked enabled state "
10577 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10578
10579 active = dev_priv->display.get_pipe_config(crtc,
10580 &pipe_config);
10581
10582 /* hw state is inconsistent with the pipe A quirk */
10583 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10584 active = crtc->active;
10585
10586 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10587 base.head) {
10588 enum pipe pipe;
10589 if (encoder->base.crtc != &crtc->base)
10590 continue;
10591 if (encoder->get_hw_state(encoder, &pipe))
10592 encoder->get_config(encoder, &pipe_config);
10593 }
10594
10595 WARN(crtc->active != active,
10596 "crtc active state doesn't match with hw state "
10597 "(expected %i, found %i)\n", crtc->active, active);
10598
10599 if (active &&
10600 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10601 WARN(1, "pipe state doesn't match!\n");
10602 intel_dump_pipe_config(crtc, &pipe_config,
10603 "[hw state]");
10604 intel_dump_pipe_config(crtc, &crtc->config,
10605 "[sw state]");
10606 }
10607 }
10608 }
10609
10610 static void
10611 check_shared_dpll_state(struct drm_device *dev)
10612 {
10613 struct drm_i915_private *dev_priv = dev->dev_private;
10614 struct intel_crtc *crtc;
10615 struct intel_dpll_hw_state dpll_hw_state;
10616 int i;
10617
10618 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10619 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10620 int enabled_crtcs = 0, active_crtcs = 0;
10621 bool active;
10622
10623 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10624
10625 DRM_DEBUG_KMS("%s\n", pll->name);
10626
10627 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10628
10629 WARN(pll->active > pll->refcount,
10630 "more active pll users than references: %i vs %i\n",
10631 pll->active, pll->refcount);
10632 WARN(pll->active && !pll->on,
10633 "pll in active use but not on in sw tracking\n");
10634 WARN(pll->on && !pll->active,
10635 "pll in on but not on in use in sw tracking\n");
10636 WARN(pll->on != active,
10637 "pll on state mismatch (expected %i, found %i)\n",
10638 pll->on, active);
10639
10640 for_each_intel_crtc(dev, crtc) {
10641 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10642 enabled_crtcs++;
10643 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10644 active_crtcs++;
10645 }
10646 WARN(pll->active != active_crtcs,
10647 "pll active crtcs mismatch (expected %i, found %i)\n",
10648 pll->active, active_crtcs);
10649 WARN(pll->refcount != enabled_crtcs,
10650 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10651 pll->refcount, enabled_crtcs);
10652
10653 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10654 sizeof(dpll_hw_state)),
10655 "pll hw state mismatch\n");
10656 }
10657 }
10658
10659 void
10660 intel_modeset_check_state(struct drm_device *dev)
10661 {
10662 check_connector_state(dev);
10663 check_encoder_state(dev);
10664 check_crtc_state(dev);
10665 check_shared_dpll_state(dev);
10666 }
10667
10668 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10669 int dotclock)
10670 {
10671 /*
10672 * FDI already provided one idea for the dotclock.
10673 * Yell if the encoder disagrees.
10674 */
10675 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10676 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10677 pipe_config->adjusted_mode.crtc_clock, dotclock);
10678 }
10679
10680 static void update_scanline_offset(struct intel_crtc *crtc)
10681 {
10682 struct drm_device *dev = crtc->base.dev;
10683
10684 /*
10685 * The scanline counter increments at the leading edge of hsync.
10686 *
10687 * On most platforms it starts counting from vtotal-1 on the
10688 * first active line. That means the scanline counter value is
10689 * always one less than what we would expect. Ie. just after
10690 * start of vblank, which also occurs at start of hsync (on the
10691 * last active line), the scanline counter will read vblank_start-1.
10692 *
10693 * On gen2 the scanline counter starts counting from 1 instead
10694 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10695 * to keep the value positive), instead of adding one.
10696 *
10697 * On HSW+ the behaviour of the scanline counter depends on the output
10698 * type. For DP ports it behaves like most other platforms, but on HDMI
10699 * there's an extra 1 line difference. So we need to add two instead of
10700 * one to the value.
10701 */
10702 if (IS_GEN2(dev)) {
10703 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10704 int vtotal;
10705
10706 vtotal = mode->crtc_vtotal;
10707 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10708 vtotal /= 2;
10709
10710 crtc->scanline_offset = vtotal - 1;
10711 } else if (HAS_DDI(dev) &&
10712 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10713 crtc->scanline_offset = 2;
10714 } else
10715 crtc->scanline_offset = 1;
10716 }
10717
10718 static int __intel_set_mode(struct drm_crtc *crtc,
10719 struct drm_display_mode *mode,
10720 int x, int y, struct drm_framebuffer *fb)
10721 {
10722 struct drm_device *dev = crtc->dev;
10723 struct drm_i915_private *dev_priv = dev->dev_private;
10724 struct drm_display_mode *saved_mode;
10725 struct intel_crtc_config *pipe_config = NULL;
10726 struct intel_crtc *intel_crtc;
10727 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10728 int ret = 0;
10729
10730 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10731 if (!saved_mode)
10732 return -ENOMEM;
10733
10734 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10735 &prepare_pipes, &disable_pipes);
10736
10737 *saved_mode = crtc->mode;
10738
10739 /* Hack: Because we don't (yet) support global modeset on multiple
10740 * crtcs, we don't keep track of the new mode for more than one crtc.
10741 * Hence simply check whether any bit is set in modeset_pipes in all the
10742 * pieces of code that are not yet converted to deal with mutliple crtcs
10743 * changing their mode at the same time. */
10744 if (modeset_pipes) {
10745 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10746 if (IS_ERR(pipe_config)) {
10747 ret = PTR_ERR(pipe_config);
10748 pipe_config = NULL;
10749
10750 goto out;
10751 }
10752 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10753 "[modeset]");
10754 to_intel_crtc(crtc)->new_config = pipe_config;
10755 }
10756
10757 /*
10758 * See if the config requires any additional preparation, e.g.
10759 * to adjust global state with pipes off. We need to do this
10760 * here so we can get the modeset_pipe updated config for the new
10761 * mode set on this crtc. For other crtcs we need to use the
10762 * adjusted_mode bits in the crtc directly.
10763 */
10764 if (IS_VALLEYVIEW(dev)) {
10765 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10766
10767 /* may have added more to prepare_pipes than we should */
10768 prepare_pipes &= ~disable_pipes;
10769 }
10770
10771 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10772 intel_crtc_disable(&intel_crtc->base);
10773
10774 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10775 if (intel_crtc->base.enabled)
10776 dev_priv->display.crtc_disable(&intel_crtc->base);
10777 }
10778
10779 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10780 * to set it here already despite that we pass it down the callchain.
10781 */
10782 if (modeset_pipes) {
10783 crtc->mode = *mode;
10784 /* mode_set/enable/disable functions rely on a correct pipe
10785 * config. */
10786 to_intel_crtc(crtc)->config = *pipe_config;
10787 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10788
10789 /*
10790 * Calculate and store various constants which
10791 * are later needed by vblank and swap-completion
10792 * timestamping. They are derived from true hwmode.
10793 */
10794 drm_calc_timestamping_constants(crtc,
10795 &pipe_config->adjusted_mode);
10796 }
10797
10798 /* Only after disabling all output pipelines that will be changed can we
10799 * update the the output configuration. */
10800 intel_modeset_update_state(dev, prepare_pipes);
10801
10802 if (dev_priv->display.modeset_global_resources)
10803 dev_priv->display.modeset_global_resources(dev);
10804
10805 /* Set up the DPLL and any encoders state that needs to adjust or depend
10806 * on the DPLL.
10807 */
10808 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10809 struct drm_framebuffer *old_fb = crtc->primary->fb;
10810 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10811 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10812
10813 mutex_lock(&dev->struct_mutex);
10814 ret = intel_pin_and_fence_fb_obj(dev,
10815 obj,
10816 NULL);
10817 if (ret != 0) {
10818 DRM_ERROR("pin & fence failed\n");
10819 mutex_unlock(&dev->struct_mutex);
10820 goto done;
10821 }
10822 if (old_fb)
10823 intel_unpin_fb_obj(old_obj);
10824 i915_gem_track_fb(old_obj, obj,
10825 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10826 mutex_unlock(&dev->struct_mutex);
10827
10828 crtc->primary->fb = fb;
10829 crtc->x = x;
10830 crtc->y = y;
10831
10832 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10833 x, y, fb);
10834 if (ret)
10835 goto done;
10836 }
10837
10838 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10839 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10840 update_scanline_offset(intel_crtc);
10841
10842 dev_priv->display.crtc_enable(&intel_crtc->base);
10843 }
10844
10845 /* FIXME: add subpixel order */
10846 done:
10847 if (ret && crtc->enabled)
10848 crtc->mode = *saved_mode;
10849
10850 out:
10851 kfree(pipe_config);
10852 kfree(saved_mode);
10853 return ret;
10854 }
10855
10856 static int intel_set_mode(struct drm_crtc *crtc,
10857 struct drm_display_mode *mode,
10858 int x, int y, struct drm_framebuffer *fb)
10859 {
10860 int ret;
10861
10862 ret = __intel_set_mode(crtc, mode, x, y, fb);
10863
10864 if (ret == 0)
10865 intel_modeset_check_state(crtc->dev);
10866
10867 return ret;
10868 }
10869
10870 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10871 {
10872 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10873 }
10874
10875 #undef for_each_intel_crtc_masked
10876
10877 static void intel_set_config_free(struct intel_set_config *config)
10878 {
10879 if (!config)
10880 return;
10881
10882 kfree(config->save_connector_encoders);
10883 kfree(config->save_encoder_crtcs);
10884 kfree(config->save_crtc_enabled);
10885 kfree(config);
10886 }
10887
10888 static int intel_set_config_save_state(struct drm_device *dev,
10889 struct intel_set_config *config)
10890 {
10891 struct drm_crtc *crtc;
10892 struct drm_encoder *encoder;
10893 struct drm_connector *connector;
10894 int count;
10895
10896 config->save_crtc_enabled =
10897 kcalloc(dev->mode_config.num_crtc,
10898 sizeof(bool), GFP_KERNEL);
10899 if (!config->save_crtc_enabled)
10900 return -ENOMEM;
10901
10902 config->save_encoder_crtcs =
10903 kcalloc(dev->mode_config.num_encoder,
10904 sizeof(struct drm_crtc *), GFP_KERNEL);
10905 if (!config->save_encoder_crtcs)
10906 return -ENOMEM;
10907
10908 config->save_connector_encoders =
10909 kcalloc(dev->mode_config.num_connector,
10910 sizeof(struct drm_encoder *), GFP_KERNEL);
10911 if (!config->save_connector_encoders)
10912 return -ENOMEM;
10913
10914 /* Copy data. Note that driver private data is not affected.
10915 * Should anything bad happen only the expected state is
10916 * restored, not the drivers personal bookkeeping.
10917 */
10918 count = 0;
10919 for_each_crtc(dev, crtc) {
10920 config->save_crtc_enabled[count++] = crtc->enabled;
10921 }
10922
10923 count = 0;
10924 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10925 config->save_encoder_crtcs[count++] = encoder->crtc;
10926 }
10927
10928 count = 0;
10929 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10930 config->save_connector_encoders[count++] = connector->encoder;
10931 }
10932
10933 return 0;
10934 }
10935
10936 static void intel_set_config_restore_state(struct drm_device *dev,
10937 struct intel_set_config *config)
10938 {
10939 struct intel_crtc *crtc;
10940 struct intel_encoder *encoder;
10941 struct intel_connector *connector;
10942 int count;
10943
10944 count = 0;
10945 for_each_intel_crtc(dev, crtc) {
10946 crtc->new_enabled = config->save_crtc_enabled[count++];
10947
10948 if (crtc->new_enabled)
10949 crtc->new_config = &crtc->config;
10950 else
10951 crtc->new_config = NULL;
10952 }
10953
10954 count = 0;
10955 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10956 encoder->new_crtc =
10957 to_intel_crtc(config->save_encoder_crtcs[count++]);
10958 }
10959
10960 count = 0;
10961 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10962 connector->new_encoder =
10963 to_intel_encoder(config->save_connector_encoders[count++]);
10964 }
10965 }
10966
10967 static bool
10968 is_crtc_connector_off(struct drm_mode_set *set)
10969 {
10970 int i;
10971
10972 if (set->num_connectors == 0)
10973 return false;
10974
10975 if (WARN_ON(set->connectors == NULL))
10976 return false;
10977
10978 for (i = 0; i < set->num_connectors; i++)
10979 if (set->connectors[i]->encoder &&
10980 set->connectors[i]->encoder->crtc == set->crtc &&
10981 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10982 return true;
10983
10984 return false;
10985 }
10986
10987 static void
10988 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10989 struct intel_set_config *config)
10990 {
10991
10992 /* We should be able to check here if the fb has the same properties
10993 * and then just flip_or_move it */
10994 if (is_crtc_connector_off(set)) {
10995 config->mode_changed = true;
10996 } else if (set->crtc->primary->fb != set->fb) {
10997 /*
10998 * If we have no fb, we can only flip as long as the crtc is
10999 * active, otherwise we need a full mode set. The crtc may
11000 * be active if we've only disabled the primary plane, or
11001 * in fastboot situations.
11002 */
11003 if (set->crtc->primary->fb == NULL) {
11004 struct intel_crtc *intel_crtc =
11005 to_intel_crtc(set->crtc);
11006
11007 if (intel_crtc->active) {
11008 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11009 config->fb_changed = true;
11010 } else {
11011 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11012 config->mode_changed = true;
11013 }
11014 } else if (set->fb == NULL) {
11015 config->mode_changed = true;
11016 } else if (set->fb->pixel_format !=
11017 set->crtc->primary->fb->pixel_format) {
11018 config->mode_changed = true;
11019 } else {
11020 config->fb_changed = true;
11021 }
11022 }
11023
11024 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11025 config->fb_changed = true;
11026
11027 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11028 DRM_DEBUG_KMS("modes are different, full mode set\n");
11029 drm_mode_debug_printmodeline(&set->crtc->mode);
11030 drm_mode_debug_printmodeline(set->mode);
11031 config->mode_changed = true;
11032 }
11033
11034 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11035 set->crtc->base.id, config->mode_changed, config->fb_changed);
11036 }
11037
11038 static int
11039 intel_modeset_stage_output_state(struct drm_device *dev,
11040 struct drm_mode_set *set,
11041 struct intel_set_config *config)
11042 {
11043 struct intel_connector *connector;
11044 struct intel_encoder *encoder;
11045 struct intel_crtc *crtc;
11046 int ro;
11047
11048 /* The upper layers ensure that we either disable a crtc or have a list
11049 * of connectors. For paranoia, double-check this. */
11050 WARN_ON(!set->fb && (set->num_connectors != 0));
11051 WARN_ON(set->fb && (set->num_connectors == 0));
11052
11053 list_for_each_entry(connector, &dev->mode_config.connector_list,
11054 base.head) {
11055 /* Otherwise traverse passed in connector list and get encoders
11056 * for them. */
11057 for (ro = 0; ro < set->num_connectors; ro++) {
11058 if (set->connectors[ro] == &connector->base) {
11059 connector->new_encoder = connector->encoder;
11060 break;
11061 }
11062 }
11063
11064 /* If we disable the crtc, disable all its connectors. Also, if
11065 * the connector is on the changing crtc but not on the new
11066 * connector list, disable it. */
11067 if ((!set->fb || ro == set->num_connectors) &&
11068 connector->base.encoder &&
11069 connector->base.encoder->crtc == set->crtc) {
11070 connector->new_encoder = NULL;
11071
11072 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11073 connector->base.base.id,
11074 connector->base.name);
11075 }
11076
11077
11078 if (&connector->new_encoder->base != connector->base.encoder) {
11079 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11080 config->mode_changed = true;
11081 }
11082 }
11083 /* connector->new_encoder is now updated for all connectors. */
11084
11085 /* Update crtc of enabled connectors. */
11086 list_for_each_entry(connector, &dev->mode_config.connector_list,
11087 base.head) {
11088 struct drm_crtc *new_crtc;
11089
11090 if (!connector->new_encoder)
11091 continue;
11092
11093 new_crtc = connector->new_encoder->base.crtc;
11094
11095 for (ro = 0; ro < set->num_connectors; ro++) {
11096 if (set->connectors[ro] == &connector->base)
11097 new_crtc = set->crtc;
11098 }
11099
11100 /* Make sure the new CRTC will work with the encoder */
11101 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11102 new_crtc)) {
11103 return -EINVAL;
11104 }
11105 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11106
11107 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11108 connector->base.base.id,
11109 connector->base.name,
11110 new_crtc->base.id);
11111 }
11112
11113 /* Check for any encoders that needs to be disabled. */
11114 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11115 base.head) {
11116 int num_connectors = 0;
11117 list_for_each_entry(connector,
11118 &dev->mode_config.connector_list,
11119 base.head) {
11120 if (connector->new_encoder == encoder) {
11121 WARN_ON(!connector->new_encoder->new_crtc);
11122 num_connectors++;
11123 }
11124 }
11125
11126 if (num_connectors == 0)
11127 encoder->new_crtc = NULL;
11128 else if (num_connectors > 1)
11129 return -EINVAL;
11130
11131 /* Only now check for crtc changes so we don't miss encoders
11132 * that will be disabled. */
11133 if (&encoder->new_crtc->base != encoder->base.crtc) {
11134 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11135 config->mode_changed = true;
11136 }
11137 }
11138 /* Now we've also updated encoder->new_crtc for all encoders. */
11139
11140 for_each_intel_crtc(dev, crtc) {
11141 crtc->new_enabled = false;
11142
11143 list_for_each_entry(encoder,
11144 &dev->mode_config.encoder_list,
11145 base.head) {
11146 if (encoder->new_crtc == crtc) {
11147 crtc->new_enabled = true;
11148 break;
11149 }
11150 }
11151
11152 if (crtc->new_enabled != crtc->base.enabled) {
11153 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11154 crtc->new_enabled ? "en" : "dis");
11155 config->mode_changed = true;
11156 }
11157
11158 if (crtc->new_enabled)
11159 crtc->new_config = &crtc->config;
11160 else
11161 crtc->new_config = NULL;
11162 }
11163
11164 return 0;
11165 }
11166
11167 static void disable_crtc_nofb(struct intel_crtc *crtc)
11168 {
11169 struct drm_device *dev = crtc->base.dev;
11170 struct intel_encoder *encoder;
11171 struct intel_connector *connector;
11172
11173 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11174 pipe_name(crtc->pipe));
11175
11176 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11177 if (connector->new_encoder &&
11178 connector->new_encoder->new_crtc == crtc)
11179 connector->new_encoder = NULL;
11180 }
11181
11182 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11183 if (encoder->new_crtc == crtc)
11184 encoder->new_crtc = NULL;
11185 }
11186
11187 crtc->new_enabled = false;
11188 crtc->new_config = NULL;
11189 }
11190
11191 static int intel_crtc_set_config(struct drm_mode_set *set)
11192 {
11193 struct drm_device *dev;
11194 struct drm_mode_set save_set;
11195 struct intel_set_config *config;
11196 int ret;
11197
11198 BUG_ON(!set);
11199 BUG_ON(!set->crtc);
11200 BUG_ON(!set->crtc->helper_private);
11201
11202 /* Enforce sane interface api - has been abused by the fb helper. */
11203 BUG_ON(!set->mode && set->fb);
11204 BUG_ON(set->fb && set->num_connectors == 0);
11205
11206 if (set->fb) {
11207 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11208 set->crtc->base.id, set->fb->base.id,
11209 (int)set->num_connectors, set->x, set->y);
11210 } else {
11211 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11212 }
11213
11214 dev = set->crtc->dev;
11215
11216 ret = -ENOMEM;
11217 config = kzalloc(sizeof(*config), GFP_KERNEL);
11218 if (!config)
11219 goto out_config;
11220
11221 ret = intel_set_config_save_state(dev, config);
11222 if (ret)
11223 goto out_config;
11224
11225 save_set.crtc = set->crtc;
11226 save_set.mode = &set->crtc->mode;
11227 save_set.x = set->crtc->x;
11228 save_set.y = set->crtc->y;
11229 save_set.fb = set->crtc->primary->fb;
11230
11231 /* Compute whether we need a full modeset, only an fb base update or no
11232 * change at all. In the future we might also check whether only the
11233 * mode changed, e.g. for LVDS where we only change the panel fitter in
11234 * such cases. */
11235 intel_set_config_compute_mode_changes(set, config);
11236
11237 ret = intel_modeset_stage_output_state(dev, set, config);
11238 if (ret)
11239 goto fail;
11240
11241 if (config->mode_changed) {
11242 ret = intel_set_mode(set->crtc, set->mode,
11243 set->x, set->y, set->fb);
11244 } else if (config->fb_changed) {
11245 struct drm_i915_private *dev_priv = dev->dev_private;
11246 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11247
11248 intel_crtc_wait_for_pending_flips(set->crtc);
11249
11250 ret = intel_pipe_set_base(set->crtc,
11251 set->x, set->y, set->fb);
11252
11253 /*
11254 * We need to make sure the primary plane is re-enabled if it
11255 * has previously been turned off.
11256 */
11257 if (!intel_crtc->primary_enabled && ret == 0) {
11258 WARN_ON(!intel_crtc->active);
11259 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11260 intel_crtc->pipe);
11261 }
11262
11263 /*
11264 * In the fastboot case this may be our only check of the
11265 * state after boot. It would be better to only do it on
11266 * the first update, but we don't have a nice way of doing that
11267 * (and really, set_config isn't used much for high freq page
11268 * flipping, so increasing its cost here shouldn't be a big
11269 * deal).
11270 */
11271 if (i915.fastboot && ret == 0)
11272 intel_modeset_check_state(set->crtc->dev);
11273 }
11274
11275 if (ret) {
11276 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11277 set->crtc->base.id, ret);
11278 fail:
11279 intel_set_config_restore_state(dev, config);
11280
11281 /*
11282 * HACK: if the pipe was on, but we didn't have a framebuffer,
11283 * force the pipe off to avoid oopsing in the modeset code
11284 * due to fb==NULL. This should only happen during boot since
11285 * we don't yet reconstruct the FB from the hardware state.
11286 */
11287 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11288 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11289
11290 /* Try to restore the config */
11291 if (config->mode_changed &&
11292 intel_set_mode(save_set.crtc, save_set.mode,
11293 save_set.x, save_set.y, save_set.fb))
11294 DRM_ERROR("failed to restore config after modeset failure\n");
11295 }
11296
11297 out_config:
11298 intel_set_config_free(config);
11299 return ret;
11300 }
11301
11302 static const struct drm_crtc_funcs intel_crtc_funcs = {
11303 .gamma_set = intel_crtc_gamma_set,
11304 .set_config = intel_crtc_set_config,
11305 .destroy = intel_crtc_destroy,
11306 .page_flip = intel_crtc_page_flip,
11307 };
11308
11309 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11310 struct intel_shared_dpll *pll,
11311 struct intel_dpll_hw_state *hw_state)
11312 {
11313 uint32_t val;
11314
11315 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11316 return false;
11317
11318 val = I915_READ(PCH_DPLL(pll->id));
11319 hw_state->dpll = val;
11320 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11321 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11322
11323 return val & DPLL_VCO_ENABLE;
11324 }
11325
11326 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11327 struct intel_shared_dpll *pll)
11328 {
11329 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11330 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11331 }
11332
11333 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11334 struct intel_shared_dpll *pll)
11335 {
11336 /* PCH refclock must be enabled first */
11337 ibx_assert_pch_refclk_enabled(dev_priv);
11338
11339 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11340
11341 /* Wait for the clocks to stabilize. */
11342 POSTING_READ(PCH_DPLL(pll->id));
11343 udelay(150);
11344
11345 /* The pixel multiplier can only be updated once the
11346 * DPLL is enabled and the clocks are stable.
11347 *
11348 * So write it again.
11349 */
11350 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11351 POSTING_READ(PCH_DPLL(pll->id));
11352 udelay(200);
11353 }
11354
11355 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11356 struct intel_shared_dpll *pll)
11357 {
11358 struct drm_device *dev = dev_priv->dev;
11359 struct intel_crtc *crtc;
11360
11361 /* Make sure no transcoder isn't still depending on us. */
11362 for_each_intel_crtc(dev, crtc) {
11363 if (intel_crtc_to_shared_dpll(crtc) == pll)
11364 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11365 }
11366
11367 I915_WRITE(PCH_DPLL(pll->id), 0);
11368 POSTING_READ(PCH_DPLL(pll->id));
11369 udelay(200);
11370 }
11371
11372 static char *ibx_pch_dpll_names[] = {
11373 "PCH DPLL A",
11374 "PCH DPLL B",
11375 };
11376
11377 static void ibx_pch_dpll_init(struct drm_device *dev)
11378 {
11379 struct drm_i915_private *dev_priv = dev->dev_private;
11380 int i;
11381
11382 dev_priv->num_shared_dpll = 2;
11383
11384 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11385 dev_priv->shared_dplls[i].id = i;
11386 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11387 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11388 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11389 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11390 dev_priv->shared_dplls[i].get_hw_state =
11391 ibx_pch_dpll_get_hw_state;
11392 }
11393 }
11394
11395 static void intel_shared_dpll_init(struct drm_device *dev)
11396 {
11397 struct drm_i915_private *dev_priv = dev->dev_private;
11398
11399 if (HAS_DDI(dev))
11400 intel_ddi_pll_init(dev);
11401 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11402 ibx_pch_dpll_init(dev);
11403 else
11404 dev_priv->num_shared_dpll = 0;
11405
11406 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11407 }
11408
11409 static int
11410 intel_primary_plane_disable(struct drm_plane *plane)
11411 {
11412 struct drm_device *dev = plane->dev;
11413 struct drm_i915_private *dev_priv = dev->dev_private;
11414 struct intel_plane *intel_plane = to_intel_plane(plane);
11415 struct intel_crtc *intel_crtc;
11416
11417 if (!plane->fb)
11418 return 0;
11419
11420 BUG_ON(!plane->crtc);
11421
11422 intel_crtc = to_intel_crtc(plane->crtc);
11423
11424 /*
11425 * Even though we checked plane->fb above, it's still possible that
11426 * the primary plane has been implicitly disabled because the crtc
11427 * coordinates given weren't visible, or because we detected
11428 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11429 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11430 * In either case, we need to unpin the FB and let the fb pointer get
11431 * updated, but otherwise we don't need to touch the hardware.
11432 */
11433 if (!intel_crtc->primary_enabled)
11434 goto disable_unpin;
11435
11436 intel_crtc_wait_for_pending_flips(plane->crtc);
11437 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11438 intel_plane->pipe);
11439 disable_unpin:
11440 mutex_lock(&dev->struct_mutex);
11441 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11442 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11443 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11444 mutex_unlock(&dev->struct_mutex);
11445 plane->fb = NULL;
11446
11447 return 0;
11448 }
11449
11450 static int
11451 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11452 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11453 unsigned int crtc_w, unsigned int crtc_h,
11454 uint32_t src_x, uint32_t src_y,
11455 uint32_t src_w, uint32_t src_h)
11456 {
11457 struct drm_device *dev = crtc->dev;
11458 struct drm_i915_private *dev_priv = dev->dev_private;
11459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11460 struct intel_plane *intel_plane = to_intel_plane(plane);
11461 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11462 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11463 struct drm_rect dest = {
11464 /* integer pixels */
11465 .x1 = crtc_x,
11466 .y1 = crtc_y,
11467 .x2 = crtc_x + crtc_w,
11468 .y2 = crtc_y + crtc_h,
11469 };
11470 struct drm_rect src = {
11471 /* 16.16 fixed point */
11472 .x1 = src_x,
11473 .y1 = src_y,
11474 .x2 = src_x + src_w,
11475 .y2 = src_y + src_h,
11476 };
11477 const struct drm_rect clip = {
11478 /* integer pixels */
11479 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11480 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11481 };
11482 bool visible;
11483 int ret;
11484
11485 ret = drm_plane_helper_check_update(plane, crtc, fb,
11486 &src, &dest, &clip,
11487 DRM_PLANE_HELPER_NO_SCALING,
11488 DRM_PLANE_HELPER_NO_SCALING,
11489 false, true, &visible);
11490
11491 if (ret)
11492 return ret;
11493
11494 /*
11495 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11496 * updating the fb pointer, and returning without touching the
11497 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11498 * turn on the display with all planes setup as desired.
11499 */
11500 if (!crtc->enabled) {
11501 mutex_lock(&dev->struct_mutex);
11502
11503 /*
11504 * If we already called setplane while the crtc was disabled,
11505 * we may have an fb pinned; unpin it.
11506 */
11507 if (plane->fb)
11508 intel_unpin_fb_obj(old_obj);
11509
11510 i915_gem_track_fb(old_obj, obj,
11511 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11512
11513 /* Pin and return without programming hardware */
11514 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11515 mutex_unlock(&dev->struct_mutex);
11516
11517 return ret;
11518 }
11519
11520 intel_crtc_wait_for_pending_flips(crtc);
11521
11522 /*
11523 * If clipping results in a non-visible primary plane, we'll disable
11524 * the primary plane. Note that this is a bit different than what
11525 * happens if userspace explicitly disables the plane by passing fb=0
11526 * because plane->fb still gets set and pinned.
11527 */
11528 if (!visible) {
11529 mutex_lock(&dev->struct_mutex);
11530
11531 /*
11532 * Try to pin the new fb first so that we can bail out if we
11533 * fail.
11534 */
11535 if (plane->fb != fb) {
11536 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11537 if (ret) {
11538 mutex_unlock(&dev->struct_mutex);
11539 return ret;
11540 }
11541 }
11542
11543 i915_gem_track_fb(old_obj, obj,
11544 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11545
11546 if (intel_crtc->primary_enabled)
11547 intel_disable_primary_hw_plane(dev_priv,
11548 intel_plane->plane,
11549 intel_plane->pipe);
11550
11551
11552 if (plane->fb != fb)
11553 if (plane->fb)
11554 intel_unpin_fb_obj(old_obj);
11555
11556 mutex_unlock(&dev->struct_mutex);
11557
11558 return 0;
11559 }
11560
11561 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11562 if (ret)
11563 return ret;
11564
11565 if (!intel_crtc->primary_enabled)
11566 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11567 intel_crtc->pipe);
11568
11569 return 0;
11570 }
11571
11572 /* Common destruction function for both primary and cursor planes */
11573 static void intel_plane_destroy(struct drm_plane *plane)
11574 {
11575 struct intel_plane *intel_plane = to_intel_plane(plane);
11576 drm_plane_cleanup(plane);
11577 kfree(intel_plane);
11578 }
11579
11580 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11581 .update_plane = intel_primary_plane_setplane,
11582 .disable_plane = intel_primary_plane_disable,
11583 .destroy = intel_plane_destroy,
11584 };
11585
11586 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11587 int pipe)
11588 {
11589 struct intel_plane *primary;
11590 const uint32_t *intel_primary_formats;
11591 int num_formats;
11592
11593 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11594 if (primary == NULL)
11595 return NULL;
11596
11597 primary->can_scale = false;
11598 primary->max_downscale = 1;
11599 primary->pipe = pipe;
11600 primary->plane = pipe;
11601 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11602 primary->plane = !pipe;
11603
11604 if (INTEL_INFO(dev)->gen <= 3) {
11605 intel_primary_formats = intel_primary_formats_gen2;
11606 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11607 } else {
11608 intel_primary_formats = intel_primary_formats_gen4;
11609 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11610 }
11611
11612 drm_universal_plane_init(dev, &primary->base, 0,
11613 &intel_primary_plane_funcs,
11614 intel_primary_formats, num_formats,
11615 DRM_PLANE_TYPE_PRIMARY);
11616 return &primary->base;
11617 }
11618
11619 static int
11620 intel_cursor_plane_disable(struct drm_plane *plane)
11621 {
11622 if (!plane->fb)
11623 return 0;
11624
11625 BUG_ON(!plane->crtc);
11626
11627 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11628 }
11629
11630 static int
11631 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11632 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11633 unsigned int crtc_w, unsigned int crtc_h,
11634 uint32_t src_x, uint32_t src_y,
11635 uint32_t src_w, uint32_t src_h)
11636 {
11637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11638 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11639 struct drm_i915_gem_object *obj = intel_fb->obj;
11640 struct drm_rect dest = {
11641 /* integer pixels */
11642 .x1 = crtc_x,
11643 .y1 = crtc_y,
11644 .x2 = crtc_x + crtc_w,
11645 .y2 = crtc_y + crtc_h,
11646 };
11647 struct drm_rect src = {
11648 /* 16.16 fixed point */
11649 .x1 = src_x,
11650 .y1 = src_y,
11651 .x2 = src_x + src_w,
11652 .y2 = src_y + src_h,
11653 };
11654 const struct drm_rect clip = {
11655 /* integer pixels */
11656 .x2 = intel_crtc->config.pipe_src_w,
11657 .y2 = intel_crtc->config.pipe_src_h,
11658 };
11659 bool visible;
11660 int ret;
11661
11662 ret = drm_plane_helper_check_update(plane, crtc, fb,
11663 &src, &dest, &clip,
11664 DRM_PLANE_HELPER_NO_SCALING,
11665 DRM_PLANE_HELPER_NO_SCALING,
11666 true, true, &visible);
11667 if (ret)
11668 return ret;
11669
11670 crtc->cursor_x = crtc_x;
11671 crtc->cursor_y = crtc_y;
11672 if (fb != crtc->cursor->fb) {
11673 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11674 } else {
11675 intel_crtc_update_cursor(crtc, visible);
11676 return 0;
11677 }
11678 }
11679 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11680 .update_plane = intel_cursor_plane_update,
11681 .disable_plane = intel_cursor_plane_disable,
11682 .destroy = intel_plane_destroy,
11683 };
11684
11685 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11686 int pipe)
11687 {
11688 struct intel_plane *cursor;
11689
11690 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11691 if (cursor == NULL)
11692 return NULL;
11693
11694 cursor->can_scale = false;
11695 cursor->max_downscale = 1;
11696 cursor->pipe = pipe;
11697 cursor->plane = pipe;
11698
11699 drm_universal_plane_init(dev, &cursor->base, 0,
11700 &intel_cursor_plane_funcs,
11701 intel_cursor_formats,
11702 ARRAY_SIZE(intel_cursor_formats),
11703 DRM_PLANE_TYPE_CURSOR);
11704 return &cursor->base;
11705 }
11706
11707 static void intel_crtc_init(struct drm_device *dev, int pipe)
11708 {
11709 struct drm_i915_private *dev_priv = dev->dev_private;
11710 struct intel_crtc *intel_crtc;
11711 struct drm_plane *primary = NULL;
11712 struct drm_plane *cursor = NULL;
11713 int i, ret;
11714
11715 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11716 if (intel_crtc == NULL)
11717 return;
11718
11719 primary = intel_primary_plane_create(dev, pipe);
11720 if (!primary)
11721 goto fail;
11722
11723 cursor = intel_cursor_plane_create(dev, pipe);
11724 if (!cursor)
11725 goto fail;
11726
11727 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11728 cursor, &intel_crtc_funcs);
11729 if (ret)
11730 goto fail;
11731
11732 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11733 for (i = 0; i < 256; i++) {
11734 intel_crtc->lut_r[i] = i;
11735 intel_crtc->lut_g[i] = i;
11736 intel_crtc->lut_b[i] = i;
11737 }
11738
11739 /*
11740 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11741 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11742 */
11743 intel_crtc->pipe = pipe;
11744 intel_crtc->plane = pipe;
11745 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11746 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11747 intel_crtc->plane = !pipe;
11748 }
11749
11750 intel_crtc->cursor_base = ~0;
11751 intel_crtc->cursor_cntl = ~0;
11752
11753 init_waitqueue_head(&intel_crtc->vbl_wait);
11754
11755 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11756 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11757 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11758 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11759
11760 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11761
11762 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11763 return;
11764
11765 fail:
11766 if (primary)
11767 drm_plane_cleanup(primary);
11768 if (cursor)
11769 drm_plane_cleanup(cursor);
11770 kfree(intel_crtc);
11771 }
11772
11773 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11774 {
11775 struct drm_encoder *encoder = connector->base.encoder;
11776 struct drm_device *dev = connector->base.dev;
11777
11778 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11779
11780 if (!encoder)
11781 return INVALID_PIPE;
11782
11783 return to_intel_crtc(encoder->crtc)->pipe;
11784 }
11785
11786 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11787 struct drm_file *file)
11788 {
11789 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11790 struct drm_mode_object *drmmode_obj;
11791 struct intel_crtc *crtc;
11792
11793 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11794 return -ENODEV;
11795
11796 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11797 DRM_MODE_OBJECT_CRTC);
11798
11799 if (!drmmode_obj) {
11800 DRM_ERROR("no such CRTC id\n");
11801 return -ENOENT;
11802 }
11803
11804 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11805 pipe_from_crtc_id->pipe = crtc->pipe;
11806
11807 return 0;
11808 }
11809
11810 static int intel_encoder_clones(struct intel_encoder *encoder)
11811 {
11812 struct drm_device *dev = encoder->base.dev;
11813 struct intel_encoder *source_encoder;
11814 int index_mask = 0;
11815 int entry = 0;
11816
11817 list_for_each_entry(source_encoder,
11818 &dev->mode_config.encoder_list, base.head) {
11819 if (encoders_cloneable(encoder, source_encoder))
11820 index_mask |= (1 << entry);
11821
11822 entry++;
11823 }
11824
11825 return index_mask;
11826 }
11827
11828 static bool has_edp_a(struct drm_device *dev)
11829 {
11830 struct drm_i915_private *dev_priv = dev->dev_private;
11831
11832 if (!IS_MOBILE(dev))
11833 return false;
11834
11835 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11836 return false;
11837
11838 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11839 return false;
11840
11841 return true;
11842 }
11843
11844 const char *intel_output_name(int output)
11845 {
11846 static const char *names[] = {
11847 [INTEL_OUTPUT_UNUSED] = "Unused",
11848 [INTEL_OUTPUT_ANALOG] = "Analog",
11849 [INTEL_OUTPUT_DVO] = "DVO",
11850 [INTEL_OUTPUT_SDVO] = "SDVO",
11851 [INTEL_OUTPUT_LVDS] = "LVDS",
11852 [INTEL_OUTPUT_TVOUT] = "TV",
11853 [INTEL_OUTPUT_HDMI] = "HDMI",
11854 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11855 [INTEL_OUTPUT_EDP] = "eDP",
11856 [INTEL_OUTPUT_DSI] = "DSI",
11857 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11858 };
11859
11860 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11861 return "Invalid";
11862
11863 return names[output];
11864 }
11865
11866 static bool intel_crt_present(struct drm_device *dev)
11867 {
11868 struct drm_i915_private *dev_priv = dev->dev_private;
11869
11870 if (IS_ULT(dev))
11871 return false;
11872
11873 if (IS_CHERRYVIEW(dev))
11874 return false;
11875
11876 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11877 return false;
11878
11879 return true;
11880 }
11881
11882 static void intel_setup_outputs(struct drm_device *dev)
11883 {
11884 struct drm_i915_private *dev_priv = dev->dev_private;
11885 struct intel_encoder *encoder;
11886 bool dpd_is_edp = false;
11887
11888 intel_lvds_init(dev);
11889
11890 if (intel_crt_present(dev))
11891 intel_crt_init(dev);
11892
11893 if (HAS_DDI(dev)) {
11894 int found;
11895
11896 /* Haswell uses DDI functions to detect digital outputs */
11897 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11898 /* DDI A only supports eDP */
11899 if (found)
11900 intel_ddi_init(dev, PORT_A);
11901
11902 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11903 * register */
11904 found = I915_READ(SFUSE_STRAP);
11905
11906 if (found & SFUSE_STRAP_DDIB_DETECTED)
11907 intel_ddi_init(dev, PORT_B);
11908 if (found & SFUSE_STRAP_DDIC_DETECTED)
11909 intel_ddi_init(dev, PORT_C);
11910 if (found & SFUSE_STRAP_DDID_DETECTED)
11911 intel_ddi_init(dev, PORT_D);
11912 } else if (HAS_PCH_SPLIT(dev)) {
11913 int found;
11914 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11915
11916 if (has_edp_a(dev))
11917 intel_dp_init(dev, DP_A, PORT_A);
11918
11919 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11920 /* PCH SDVOB multiplex with HDMIB */
11921 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11922 if (!found)
11923 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11924 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11925 intel_dp_init(dev, PCH_DP_B, PORT_B);
11926 }
11927
11928 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11929 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11930
11931 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11932 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11933
11934 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11935 intel_dp_init(dev, PCH_DP_C, PORT_C);
11936
11937 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11938 intel_dp_init(dev, PCH_DP_D, PORT_D);
11939 } else if (IS_VALLEYVIEW(dev)) {
11940 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11941 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11942 PORT_B);
11943 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11944 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11945 }
11946
11947 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11948 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11949 PORT_C);
11950 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11951 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11952 }
11953
11954 if (IS_CHERRYVIEW(dev)) {
11955 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11956 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11957 PORT_D);
11958 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11959 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11960 }
11961 }
11962
11963 intel_dsi_init(dev);
11964 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11965 bool found = false;
11966
11967 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11968 DRM_DEBUG_KMS("probing SDVOB\n");
11969 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11970 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11971 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11972 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11973 }
11974
11975 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11976 intel_dp_init(dev, DP_B, PORT_B);
11977 }
11978
11979 /* Before G4X SDVOC doesn't have its own detect register */
11980
11981 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11982 DRM_DEBUG_KMS("probing SDVOC\n");
11983 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11984 }
11985
11986 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11987
11988 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11989 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11990 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11991 }
11992 if (SUPPORTS_INTEGRATED_DP(dev))
11993 intel_dp_init(dev, DP_C, PORT_C);
11994 }
11995
11996 if (SUPPORTS_INTEGRATED_DP(dev) &&
11997 (I915_READ(DP_D) & DP_DETECTED))
11998 intel_dp_init(dev, DP_D, PORT_D);
11999 } else if (IS_GEN2(dev))
12000 intel_dvo_init(dev);
12001
12002 if (SUPPORTS_TV(dev))
12003 intel_tv_init(dev);
12004
12005 intel_edp_psr_init(dev);
12006
12007 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12008 encoder->base.possible_crtcs = encoder->crtc_mask;
12009 encoder->base.possible_clones =
12010 intel_encoder_clones(encoder);
12011 }
12012
12013 intel_init_pch_refclk(dev);
12014
12015 drm_helper_move_panel_connectors_to_head(dev);
12016 }
12017
12018 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12019 {
12020 struct drm_device *dev = fb->dev;
12021 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12022
12023 drm_framebuffer_cleanup(fb);
12024 mutex_lock(&dev->struct_mutex);
12025 WARN_ON(!intel_fb->obj->framebuffer_references--);
12026 drm_gem_object_unreference(&intel_fb->obj->base);
12027 mutex_unlock(&dev->struct_mutex);
12028 kfree(intel_fb);
12029 }
12030
12031 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12032 struct drm_file *file,
12033 unsigned int *handle)
12034 {
12035 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12036 struct drm_i915_gem_object *obj = intel_fb->obj;
12037
12038 return drm_gem_handle_create(file, &obj->base, handle);
12039 }
12040
12041 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12042 .destroy = intel_user_framebuffer_destroy,
12043 .create_handle = intel_user_framebuffer_create_handle,
12044 };
12045
12046 static int intel_framebuffer_init(struct drm_device *dev,
12047 struct intel_framebuffer *intel_fb,
12048 struct drm_mode_fb_cmd2 *mode_cmd,
12049 struct drm_i915_gem_object *obj)
12050 {
12051 int aligned_height;
12052 int pitch_limit;
12053 int ret;
12054
12055 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12056
12057 if (obj->tiling_mode == I915_TILING_Y) {
12058 DRM_DEBUG("hardware does not support tiling Y\n");
12059 return -EINVAL;
12060 }
12061
12062 if (mode_cmd->pitches[0] & 63) {
12063 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12064 mode_cmd->pitches[0]);
12065 return -EINVAL;
12066 }
12067
12068 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12069 pitch_limit = 32*1024;
12070 } else if (INTEL_INFO(dev)->gen >= 4) {
12071 if (obj->tiling_mode)
12072 pitch_limit = 16*1024;
12073 else
12074 pitch_limit = 32*1024;
12075 } else if (INTEL_INFO(dev)->gen >= 3) {
12076 if (obj->tiling_mode)
12077 pitch_limit = 8*1024;
12078 else
12079 pitch_limit = 16*1024;
12080 } else
12081 /* XXX DSPC is limited to 4k tiled */
12082 pitch_limit = 8*1024;
12083
12084 if (mode_cmd->pitches[0] > pitch_limit) {
12085 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12086 obj->tiling_mode ? "tiled" : "linear",
12087 mode_cmd->pitches[0], pitch_limit);
12088 return -EINVAL;
12089 }
12090
12091 if (obj->tiling_mode != I915_TILING_NONE &&
12092 mode_cmd->pitches[0] != obj->stride) {
12093 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12094 mode_cmd->pitches[0], obj->stride);
12095 return -EINVAL;
12096 }
12097
12098 /* Reject formats not supported by any plane early. */
12099 switch (mode_cmd->pixel_format) {
12100 case DRM_FORMAT_C8:
12101 case DRM_FORMAT_RGB565:
12102 case DRM_FORMAT_XRGB8888:
12103 case DRM_FORMAT_ARGB8888:
12104 break;
12105 case DRM_FORMAT_XRGB1555:
12106 case DRM_FORMAT_ARGB1555:
12107 if (INTEL_INFO(dev)->gen > 3) {
12108 DRM_DEBUG("unsupported pixel format: %s\n",
12109 drm_get_format_name(mode_cmd->pixel_format));
12110 return -EINVAL;
12111 }
12112 break;
12113 case DRM_FORMAT_XBGR8888:
12114 case DRM_FORMAT_ABGR8888:
12115 case DRM_FORMAT_XRGB2101010:
12116 case DRM_FORMAT_ARGB2101010:
12117 case DRM_FORMAT_XBGR2101010:
12118 case DRM_FORMAT_ABGR2101010:
12119 if (INTEL_INFO(dev)->gen < 4) {
12120 DRM_DEBUG("unsupported pixel format: %s\n",
12121 drm_get_format_name(mode_cmd->pixel_format));
12122 return -EINVAL;
12123 }
12124 break;
12125 case DRM_FORMAT_YUYV:
12126 case DRM_FORMAT_UYVY:
12127 case DRM_FORMAT_YVYU:
12128 case DRM_FORMAT_VYUY:
12129 if (INTEL_INFO(dev)->gen < 5) {
12130 DRM_DEBUG("unsupported pixel format: %s\n",
12131 drm_get_format_name(mode_cmd->pixel_format));
12132 return -EINVAL;
12133 }
12134 break;
12135 default:
12136 DRM_DEBUG("unsupported pixel format: %s\n",
12137 drm_get_format_name(mode_cmd->pixel_format));
12138 return -EINVAL;
12139 }
12140
12141 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12142 if (mode_cmd->offsets[0] != 0)
12143 return -EINVAL;
12144
12145 aligned_height = intel_align_height(dev, mode_cmd->height,
12146 obj->tiling_mode);
12147 /* FIXME drm helper for size checks (especially planar formats)? */
12148 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12149 return -EINVAL;
12150
12151 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12152 intel_fb->obj = obj;
12153 intel_fb->obj->framebuffer_references++;
12154
12155 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12156 if (ret) {
12157 DRM_ERROR("framebuffer init failed %d\n", ret);
12158 return ret;
12159 }
12160
12161 return 0;
12162 }
12163
12164 static struct drm_framebuffer *
12165 intel_user_framebuffer_create(struct drm_device *dev,
12166 struct drm_file *filp,
12167 struct drm_mode_fb_cmd2 *mode_cmd)
12168 {
12169 struct drm_i915_gem_object *obj;
12170
12171 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12172 mode_cmd->handles[0]));
12173 if (&obj->base == NULL)
12174 return ERR_PTR(-ENOENT);
12175
12176 return intel_framebuffer_create(dev, mode_cmd, obj);
12177 }
12178
12179 #ifndef CONFIG_DRM_I915_FBDEV
12180 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12181 {
12182 }
12183 #endif
12184
12185 static const struct drm_mode_config_funcs intel_mode_funcs = {
12186 .fb_create = intel_user_framebuffer_create,
12187 .output_poll_changed = intel_fbdev_output_poll_changed,
12188 };
12189
12190 /* Set up chip specific display functions */
12191 static void intel_init_display(struct drm_device *dev)
12192 {
12193 struct drm_i915_private *dev_priv = dev->dev_private;
12194
12195 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12196 dev_priv->display.find_dpll = g4x_find_best_dpll;
12197 else if (IS_CHERRYVIEW(dev))
12198 dev_priv->display.find_dpll = chv_find_best_dpll;
12199 else if (IS_VALLEYVIEW(dev))
12200 dev_priv->display.find_dpll = vlv_find_best_dpll;
12201 else if (IS_PINEVIEW(dev))
12202 dev_priv->display.find_dpll = pnv_find_best_dpll;
12203 else
12204 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12205
12206 if (HAS_DDI(dev)) {
12207 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12208 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12209 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12210 dev_priv->display.crtc_enable = haswell_crtc_enable;
12211 dev_priv->display.crtc_disable = haswell_crtc_disable;
12212 dev_priv->display.off = ironlake_crtc_off;
12213 dev_priv->display.update_primary_plane =
12214 ironlake_update_primary_plane;
12215 } else if (HAS_PCH_SPLIT(dev)) {
12216 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12217 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12218 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12219 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12220 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12221 dev_priv->display.off = ironlake_crtc_off;
12222 dev_priv->display.update_primary_plane =
12223 ironlake_update_primary_plane;
12224 } else if (IS_VALLEYVIEW(dev)) {
12225 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12226 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12227 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12228 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12229 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12230 dev_priv->display.off = i9xx_crtc_off;
12231 dev_priv->display.update_primary_plane =
12232 i9xx_update_primary_plane;
12233 } else {
12234 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12235 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12236 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12237 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12238 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12239 dev_priv->display.off = i9xx_crtc_off;
12240 dev_priv->display.update_primary_plane =
12241 i9xx_update_primary_plane;
12242 }
12243
12244 /* Returns the core display clock speed */
12245 if (IS_VALLEYVIEW(dev))
12246 dev_priv->display.get_display_clock_speed =
12247 valleyview_get_display_clock_speed;
12248 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12249 dev_priv->display.get_display_clock_speed =
12250 i945_get_display_clock_speed;
12251 else if (IS_I915G(dev))
12252 dev_priv->display.get_display_clock_speed =
12253 i915_get_display_clock_speed;
12254 else if (IS_I945GM(dev) || IS_845G(dev))
12255 dev_priv->display.get_display_clock_speed =
12256 i9xx_misc_get_display_clock_speed;
12257 else if (IS_PINEVIEW(dev))
12258 dev_priv->display.get_display_clock_speed =
12259 pnv_get_display_clock_speed;
12260 else if (IS_I915GM(dev))
12261 dev_priv->display.get_display_clock_speed =
12262 i915gm_get_display_clock_speed;
12263 else if (IS_I865G(dev))
12264 dev_priv->display.get_display_clock_speed =
12265 i865_get_display_clock_speed;
12266 else if (IS_I85X(dev))
12267 dev_priv->display.get_display_clock_speed =
12268 i855_get_display_clock_speed;
12269 else /* 852, 830 */
12270 dev_priv->display.get_display_clock_speed =
12271 i830_get_display_clock_speed;
12272
12273 if (HAS_PCH_SPLIT(dev)) {
12274 if (IS_GEN5(dev)) {
12275 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12276 dev_priv->display.write_eld = ironlake_write_eld;
12277 } else if (IS_GEN6(dev)) {
12278 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12279 dev_priv->display.write_eld = ironlake_write_eld;
12280 dev_priv->display.modeset_global_resources =
12281 snb_modeset_global_resources;
12282 } else if (IS_IVYBRIDGE(dev)) {
12283 /* FIXME: detect B0+ stepping and use auto training */
12284 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12285 dev_priv->display.write_eld = ironlake_write_eld;
12286 dev_priv->display.modeset_global_resources =
12287 ivb_modeset_global_resources;
12288 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12289 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12290 dev_priv->display.write_eld = haswell_write_eld;
12291 dev_priv->display.modeset_global_resources =
12292 haswell_modeset_global_resources;
12293 }
12294 } else if (IS_G4X(dev)) {
12295 dev_priv->display.write_eld = g4x_write_eld;
12296 } else if (IS_VALLEYVIEW(dev)) {
12297 dev_priv->display.modeset_global_resources =
12298 valleyview_modeset_global_resources;
12299 dev_priv->display.write_eld = ironlake_write_eld;
12300 }
12301
12302 /* Default just returns -ENODEV to indicate unsupported */
12303 dev_priv->display.queue_flip = intel_default_queue_flip;
12304
12305 switch (INTEL_INFO(dev)->gen) {
12306 case 2:
12307 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12308 break;
12309
12310 case 3:
12311 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12312 break;
12313
12314 case 4:
12315 case 5:
12316 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12317 break;
12318
12319 case 6:
12320 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12321 break;
12322 case 7:
12323 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12324 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12325 break;
12326 }
12327
12328 intel_panel_init_backlight_funcs(dev);
12329 }
12330
12331 /*
12332 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12333 * resume, or other times. This quirk makes sure that's the case for
12334 * affected systems.
12335 */
12336 static void quirk_pipea_force(struct drm_device *dev)
12337 {
12338 struct drm_i915_private *dev_priv = dev->dev_private;
12339
12340 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12341 DRM_INFO("applying pipe a force quirk\n");
12342 }
12343
12344 /*
12345 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12346 */
12347 static void quirk_ssc_force_disable(struct drm_device *dev)
12348 {
12349 struct drm_i915_private *dev_priv = dev->dev_private;
12350 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12351 DRM_INFO("applying lvds SSC disable quirk\n");
12352 }
12353
12354 /*
12355 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12356 * brightness value
12357 */
12358 static void quirk_invert_brightness(struct drm_device *dev)
12359 {
12360 struct drm_i915_private *dev_priv = dev->dev_private;
12361 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12362 DRM_INFO("applying inverted panel brightness quirk\n");
12363 }
12364
12365 struct intel_quirk {
12366 int device;
12367 int subsystem_vendor;
12368 int subsystem_device;
12369 void (*hook)(struct drm_device *dev);
12370 };
12371
12372 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12373 struct intel_dmi_quirk {
12374 void (*hook)(struct drm_device *dev);
12375 const struct dmi_system_id (*dmi_id_list)[];
12376 };
12377
12378 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12379 {
12380 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12381 return 1;
12382 }
12383
12384 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12385 {
12386 .dmi_id_list = &(const struct dmi_system_id[]) {
12387 {
12388 .callback = intel_dmi_reverse_brightness,
12389 .ident = "NCR Corporation",
12390 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12391 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12392 },
12393 },
12394 { } /* terminating entry */
12395 },
12396 .hook = quirk_invert_brightness,
12397 },
12398 };
12399
12400 static struct intel_quirk intel_quirks[] = {
12401 /* HP Mini needs pipe A force quirk (LP: #322104) */
12402 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12403
12404 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12405 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12406
12407 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12408 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12409
12410 /* Lenovo U160 cannot use SSC on LVDS */
12411 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12412
12413 /* Sony Vaio Y cannot use SSC on LVDS */
12414 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12415
12416 /* Acer Aspire 5734Z must invert backlight brightness */
12417 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12418
12419 /* Acer/eMachines G725 */
12420 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12421
12422 /* Acer/eMachines e725 */
12423 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12424
12425 /* Acer/Packard Bell NCL20 */
12426 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12427
12428 /* Acer Aspire 4736Z */
12429 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12430
12431 /* Acer Aspire 5336 */
12432 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12433 };
12434
12435 static void intel_init_quirks(struct drm_device *dev)
12436 {
12437 struct pci_dev *d = dev->pdev;
12438 int i;
12439
12440 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12441 struct intel_quirk *q = &intel_quirks[i];
12442
12443 if (d->device == q->device &&
12444 (d->subsystem_vendor == q->subsystem_vendor ||
12445 q->subsystem_vendor == PCI_ANY_ID) &&
12446 (d->subsystem_device == q->subsystem_device ||
12447 q->subsystem_device == PCI_ANY_ID))
12448 q->hook(dev);
12449 }
12450 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12451 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12452 intel_dmi_quirks[i].hook(dev);
12453 }
12454 }
12455
12456 /* Disable the VGA plane that we never use */
12457 static void i915_disable_vga(struct drm_device *dev)
12458 {
12459 struct drm_i915_private *dev_priv = dev->dev_private;
12460 u8 sr1;
12461 u32 vga_reg = i915_vgacntrl_reg(dev);
12462
12463 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12464 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12465 outb(SR01, VGA_SR_INDEX);
12466 sr1 = inb(VGA_SR_DATA);
12467 outb(sr1 | 1<<5, VGA_SR_DATA);
12468 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12469 udelay(300);
12470
12471 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12472 POSTING_READ(vga_reg);
12473 }
12474
12475 void intel_modeset_init_hw(struct drm_device *dev)
12476 {
12477 intel_prepare_ddi(dev);
12478
12479 if (IS_VALLEYVIEW(dev))
12480 vlv_update_cdclk(dev);
12481
12482 intel_init_clock_gating(dev);
12483
12484 intel_reset_dpio(dev);
12485
12486 intel_enable_gt_powersave(dev);
12487 }
12488
12489 void intel_modeset_suspend_hw(struct drm_device *dev)
12490 {
12491 intel_suspend_hw(dev);
12492 }
12493
12494 void intel_modeset_init(struct drm_device *dev)
12495 {
12496 struct drm_i915_private *dev_priv = dev->dev_private;
12497 int sprite, ret;
12498 enum pipe pipe;
12499 struct intel_crtc *crtc;
12500
12501 drm_mode_config_init(dev);
12502
12503 dev->mode_config.min_width = 0;
12504 dev->mode_config.min_height = 0;
12505
12506 dev->mode_config.preferred_depth = 24;
12507 dev->mode_config.prefer_shadow = 1;
12508
12509 dev->mode_config.funcs = &intel_mode_funcs;
12510
12511 intel_init_quirks(dev);
12512
12513 intel_init_pm(dev);
12514
12515 if (INTEL_INFO(dev)->num_pipes == 0)
12516 return;
12517
12518 intel_init_display(dev);
12519
12520 if (IS_GEN2(dev)) {
12521 dev->mode_config.max_width = 2048;
12522 dev->mode_config.max_height = 2048;
12523 } else if (IS_GEN3(dev)) {
12524 dev->mode_config.max_width = 4096;
12525 dev->mode_config.max_height = 4096;
12526 } else {
12527 dev->mode_config.max_width = 8192;
12528 dev->mode_config.max_height = 8192;
12529 }
12530
12531 if (IS_GEN2(dev)) {
12532 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12533 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12534 } else {
12535 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12536 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12537 }
12538
12539 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12540
12541 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12542 INTEL_INFO(dev)->num_pipes,
12543 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12544
12545 for_each_pipe(pipe) {
12546 intel_crtc_init(dev, pipe);
12547 for_each_sprite(pipe, sprite) {
12548 ret = intel_plane_init(dev, pipe, sprite);
12549 if (ret)
12550 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12551 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12552 }
12553 }
12554
12555 intel_init_dpio(dev);
12556 intel_reset_dpio(dev);
12557
12558 intel_shared_dpll_init(dev);
12559
12560 /* Just disable it once at startup */
12561 i915_disable_vga(dev);
12562 intel_setup_outputs(dev);
12563
12564 /* Just in case the BIOS is doing something questionable. */
12565 intel_disable_fbc(dev);
12566
12567 drm_modeset_lock_all(dev);
12568 intel_modeset_setup_hw_state(dev, false);
12569 drm_modeset_unlock_all(dev);
12570
12571 for_each_intel_crtc(dev, crtc) {
12572 if (!crtc->active)
12573 continue;
12574
12575 /*
12576 * Note that reserving the BIOS fb up front prevents us
12577 * from stuffing other stolen allocations like the ring
12578 * on top. This prevents some ugliness at boot time, and
12579 * can even allow for smooth boot transitions if the BIOS
12580 * fb is large enough for the active pipe configuration.
12581 */
12582 if (dev_priv->display.get_plane_config) {
12583 dev_priv->display.get_plane_config(crtc,
12584 &crtc->plane_config);
12585 /*
12586 * If the fb is shared between multiple heads, we'll
12587 * just get the first one.
12588 */
12589 intel_find_plane_obj(crtc, &crtc->plane_config);
12590 }
12591 }
12592 }
12593
12594 static void intel_enable_pipe_a(struct drm_device *dev)
12595 {
12596 struct intel_connector *connector;
12597 struct drm_connector *crt = NULL;
12598 struct intel_load_detect_pipe load_detect_temp;
12599 struct drm_modeset_acquire_ctx ctx;
12600
12601 /* We can't just switch on the pipe A, we need to set things up with a
12602 * proper mode and output configuration. As a gross hack, enable pipe A
12603 * by enabling the load detect pipe once. */
12604 list_for_each_entry(connector,
12605 &dev->mode_config.connector_list,
12606 base.head) {
12607 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12608 crt = &connector->base;
12609 break;
12610 }
12611 }
12612
12613 if (!crt)
12614 return;
12615
12616 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12617 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12618
12619
12620 }
12621
12622 static bool
12623 intel_check_plane_mapping(struct intel_crtc *crtc)
12624 {
12625 struct drm_device *dev = crtc->base.dev;
12626 struct drm_i915_private *dev_priv = dev->dev_private;
12627 u32 reg, val;
12628
12629 if (INTEL_INFO(dev)->num_pipes == 1)
12630 return true;
12631
12632 reg = DSPCNTR(!crtc->plane);
12633 val = I915_READ(reg);
12634
12635 if ((val & DISPLAY_PLANE_ENABLE) &&
12636 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12637 return false;
12638
12639 return true;
12640 }
12641
12642 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12643 {
12644 struct drm_device *dev = crtc->base.dev;
12645 struct drm_i915_private *dev_priv = dev->dev_private;
12646 u32 reg;
12647
12648 /* Clear any frame start delays used for debugging left by the BIOS */
12649 reg = PIPECONF(crtc->config.cpu_transcoder);
12650 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12651
12652 /* restore vblank interrupts to correct state */
12653 if (crtc->active)
12654 drm_vblank_on(dev, crtc->pipe);
12655 else
12656 drm_vblank_off(dev, crtc->pipe);
12657
12658 /* We need to sanitize the plane -> pipe mapping first because this will
12659 * disable the crtc (and hence change the state) if it is wrong. Note
12660 * that gen4+ has a fixed plane -> pipe mapping. */
12661 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12662 struct intel_connector *connector;
12663 bool plane;
12664
12665 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12666 crtc->base.base.id);
12667
12668 /* Pipe has the wrong plane attached and the plane is active.
12669 * Temporarily change the plane mapping and disable everything
12670 * ... */
12671 plane = crtc->plane;
12672 crtc->plane = !plane;
12673 dev_priv->display.crtc_disable(&crtc->base);
12674 crtc->plane = plane;
12675
12676 /* ... and break all links. */
12677 list_for_each_entry(connector, &dev->mode_config.connector_list,
12678 base.head) {
12679 if (connector->encoder->base.crtc != &crtc->base)
12680 continue;
12681
12682 connector->base.dpms = DRM_MODE_DPMS_OFF;
12683 connector->base.encoder = NULL;
12684 }
12685 /* multiple connectors may have the same encoder:
12686 * handle them and break crtc link separately */
12687 list_for_each_entry(connector, &dev->mode_config.connector_list,
12688 base.head)
12689 if (connector->encoder->base.crtc == &crtc->base) {
12690 connector->encoder->base.crtc = NULL;
12691 connector->encoder->connectors_active = false;
12692 }
12693
12694 WARN_ON(crtc->active);
12695 crtc->base.enabled = false;
12696 }
12697
12698 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12699 crtc->pipe == PIPE_A && !crtc->active) {
12700 /* BIOS forgot to enable pipe A, this mostly happens after
12701 * resume. Force-enable the pipe to fix this, the update_dpms
12702 * call below we restore the pipe to the right state, but leave
12703 * the required bits on. */
12704 intel_enable_pipe_a(dev);
12705 }
12706
12707 /* Adjust the state of the output pipe according to whether we
12708 * have active connectors/encoders. */
12709 intel_crtc_update_dpms(&crtc->base);
12710
12711 if (crtc->active != crtc->base.enabled) {
12712 struct intel_encoder *encoder;
12713
12714 /* This can happen either due to bugs in the get_hw_state
12715 * functions or because the pipe is force-enabled due to the
12716 * pipe A quirk. */
12717 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12718 crtc->base.base.id,
12719 crtc->base.enabled ? "enabled" : "disabled",
12720 crtc->active ? "enabled" : "disabled");
12721
12722 crtc->base.enabled = crtc->active;
12723
12724 /* Because we only establish the connector -> encoder ->
12725 * crtc links if something is active, this means the
12726 * crtc is now deactivated. Break the links. connector
12727 * -> encoder links are only establish when things are
12728 * actually up, hence no need to break them. */
12729 WARN_ON(crtc->active);
12730
12731 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12732 WARN_ON(encoder->connectors_active);
12733 encoder->base.crtc = NULL;
12734 }
12735 }
12736
12737 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12738 /*
12739 * We start out with underrun reporting disabled to avoid races.
12740 * For correct bookkeeping mark this on active crtcs.
12741 *
12742 * Also on gmch platforms we dont have any hardware bits to
12743 * disable the underrun reporting. Which means we need to start
12744 * out with underrun reporting disabled also on inactive pipes,
12745 * since otherwise we'll complain about the garbage we read when
12746 * e.g. coming up after runtime pm.
12747 *
12748 * No protection against concurrent access is required - at
12749 * worst a fifo underrun happens which also sets this to false.
12750 */
12751 crtc->cpu_fifo_underrun_disabled = true;
12752 crtc->pch_fifo_underrun_disabled = true;
12753
12754 update_scanline_offset(crtc);
12755 }
12756 }
12757
12758 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12759 {
12760 struct intel_connector *connector;
12761 struct drm_device *dev = encoder->base.dev;
12762
12763 /* We need to check both for a crtc link (meaning that the
12764 * encoder is active and trying to read from a pipe) and the
12765 * pipe itself being active. */
12766 bool has_active_crtc = encoder->base.crtc &&
12767 to_intel_crtc(encoder->base.crtc)->active;
12768
12769 if (encoder->connectors_active && !has_active_crtc) {
12770 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12771 encoder->base.base.id,
12772 encoder->base.name);
12773
12774 /* Connector is active, but has no active pipe. This is
12775 * fallout from our resume register restoring. Disable
12776 * the encoder manually again. */
12777 if (encoder->base.crtc) {
12778 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12779 encoder->base.base.id,
12780 encoder->base.name);
12781 encoder->disable(encoder);
12782 if (encoder->post_disable)
12783 encoder->post_disable(encoder);
12784 }
12785 encoder->base.crtc = NULL;
12786 encoder->connectors_active = false;
12787
12788 /* Inconsistent output/port/pipe state happens presumably due to
12789 * a bug in one of the get_hw_state functions. Or someplace else
12790 * in our code, like the register restore mess on resume. Clamp
12791 * things to off as a safer default. */
12792 list_for_each_entry(connector,
12793 &dev->mode_config.connector_list,
12794 base.head) {
12795 if (connector->encoder != encoder)
12796 continue;
12797 connector->base.dpms = DRM_MODE_DPMS_OFF;
12798 connector->base.encoder = NULL;
12799 }
12800 }
12801 /* Enabled encoders without active connectors will be fixed in
12802 * the crtc fixup. */
12803 }
12804
12805 void i915_redisable_vga_power_on(struct drm_device *dev)
12806 {
12807 struct drm_i915_private *dev_priv = dev->dev_private;
12808 u32 vga_reg = i915_vgacntrl_reg(dev);
12809
12810 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12811 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12812 i915_disable_vga(dev);
12813 }
12814 }
12815
12816 void i915_redisable_vga(struct drm_device *dev)
12817 {
12818 struct drm_i915_private *dev_priv = dev->dev_private;
12819
12820 /* This function can be called both from intel_modeset_setup_hw_state or
12821 * at a very early point in our resume sequence, where the power well
12822 * structures are not yet restored. Since this function is at a very
12823 * paranoid "someone might have enabled VGA while we were not looking"
12824 * level, just check if the power well is enabled instead of trying to
12825 * follow the "don't touch the power well if we don't need it" policy
12826 * the rest of the driver uses. */
12827 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12828 return;
12829
12830 i915_redisable_vga_power_on(dev);
12831 }
12832
12833 static bool primary_get_hw_state(struct intel_crtc *crtc)
12834 {
12835 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12836
12837 if (!crtc->active)
12838 return false;
12839
12840 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12841 }
12842
12843 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12844 {
12845 struct drm_i915_private *dev_priv = dev->dev_private;
12846 enum pipe pipe;
12847 struct intel_crtc *crtc;
12848 struct intel_encoder *encoder;
12849 struct intel_connector *connector;
12850 int i;
12851
12852 for_each_intel_crtc(dev, crtc) {
12853 memset(&crtc->config, 0, sizeof(crtc->config));
12854
12855 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12856
12857 crtc->active = dev_priv->display.get_pipe_config(crtc,
12858 &crtc->config);
12859
12860 crtc->base.enabled = crtc->active;
12861 crtc->primary_enabled = primary_get_hw_state(crtc);
12862
12863 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12864 crtc->base.base.id,
12865 crtc->active ? "enabled" : "disabled");
12866 }
12867
12868 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12869 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12870
12871 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12872 pll->active = 0;
12873 for_each_intel_crtc(dev, crtc) {
12874 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12875 pll->active++;
12876 }
12877 pll->refcount = pll->active;
12878
12879 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12880 pll->name, pll->refcount, pll->on);
12881
12882 if (pll->refcount)
12883 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12884 }
12885
12886 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12887 base.head) {
12888 pipe = 0;
12889
12890 if (encoder->get_hw_state(encoder, &pipe)) {
12891 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12892 encoder->base.crtc = &crtc->base;
12893 encoder->get_config(encoder, &crtc->config);
12894 } else {
12895 encoder->base.crtc = NULL;
12896 }
12897
12898 encoder->connectors_active = false;
12899 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12900 encoder->base.base.id,
12901 encoder->base.name,
12902 encoder->base.crtc ? "enabled" : "disabled",
12903 pipe_name(pipe));
12904 }
12905
12906 list_for_each_entry(connector, &dev->mode_config.connector_list,
12907 base.head) {
12908 if (connector->get_hw_state(connector)) {
12909 connector->base.dpms = DRM_MODE_DPMS_ON;
12910 connector->encoder->connectors_active = true;
12911 connector->base.encoder = &connector->encoder->base;
12912 } else {
12913 connector->base.dpms = DRM_MODE_DPMS_OFF;
12914 connector->base.encoder = NULL;
12915 }
12916 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12917 connector->base.base.id,
12918 connector->base.name,
12919 connector->base.encoder ? "enabled" : "disabled");
12920 }
12921 }
12922
12923 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12924 * and i915 state tracking structures. */
12925 void intel_modeset_setup_hw_state(struct drm_device *dev,
12926 bool force_restore)
12927 {
12928 struct drm_i915_private *dev_priv = dev->dev_private;
12929 enum pipe pipe;
12930 struct intel_crtc *crtc;
12931 struct intel_encoder *encoder;
12932 int i;
12933
12934 intel_modeset_readout_hw_state(dev);
12935
12936 /*
12937 * Now that we have the config, copy it to each CRTC struct
12938 * Note that this could go away if we move to using crtc_config
12939 * checking everywhere.
12940 */
12941 for_each_intel_crtc(dev, crtc) {
12942 if (crtc->active && i915.fastboot) {
12943 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12944 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12945 crtc->base.base.id);
12946 drm_mode_debug_printmodeline(&crtc->base.mode);
12947 }
12948 }
12949
12950 /* HW state is read out, now we need to sanitize this mess. */
12951 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12952 base.head) {
12953 intel_sanitize_encoder(encoder);
12954 }
12955
12956 for_each_pipe(pipe) {
12957 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12958 intel_sanitize_crtc(crtc);
12959 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12960 }
12961
12962 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12963 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12964
12965 if (!pll->on || pll->active)
12966 continue;
12967
12968 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12969
12970 pll->disable(dev_priv, pll);
12971 pll->on = false;
12972 }
12973
12974 if (HAS_PCH_SPLIT(dev))
12975 ilk_wm_get_hw_state(dev);
12976
12977 if (force_restore) {
12978 i915_redisable_vga(dev);
12979
12980 /*
12981 * We need to use raw interfaces for restoring state to avoid
12982 * checking (bogus) intermediate states.
12983 */
12984 for_each_pipe(pipe) {
12985 struct drm_crtc *crtc =
12986 dev_priv->pipe_to_crtc_mapping[pipe];
12987
12988 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12989 crtc->primary->fb);
12990 }
12991 } else {
12992 intel_modeset_update_staged_output_state(dev);
12993 }
12994
12995 intel_modeset_check_state(dev);
12996 }
12997
12998 void intel_modeset_gem_init(struct drm_device *dev)
12999 {
13000 struct drm_crtc *c;
13001 struct drm_i915_gem_object *obj;
13002
13003 mutex_lock(&dev->struct_mutex);
13004 intel_init_gt_powersave(dev);
13005 mutex_unlock(&dev->struct_mutex);
13006
13007 intel_modeset_init_hw(dev);
13008
13009 intel_setup_overlay(dev);
13010
13011 /*
13012 * Make sure any fbs we allocated at startup are properly
13013 * pinned & fenced. When we do the allocation it's too early
13014 * for this.
13015 */
13016 mutex_lock(&dev->struct_mutex);
13017 for_each_crtc(dev, c) {
13018 obj = intel_fb_obj(c->primary->fb);
13019 if (obj == NULL)
13020 continue;
13021
13022 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13023 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13024 to_intel_crtc(c)->pipe);
13025 drm_framebuffer_unreference(c->primary->fb);
13026 c->primary->fb = NULL;
13027 }
13028 }
13029 mutex_unlock(&dev->struct_mutex);
13030 }
13031
13032 void intel_connector_unregister(struct intel_connector *intel_connector)
13033 {
13034 struct drm_connector *connector = &intel_connector->base;
13035
13036 intel_panel_destroy_backlight(connector);
13037 drm_sysfs_connector_remove(connector);
13038 }
13039
13040 void intel_modeset_cleanup(struct drm_device *dev)
13041 {
13042 struct drm_i915_private *dev_priv = dev->dev_private;
13043 struct drm_connector *connector;
13044
13045 /*
13046 * Interrupts and polling as the first thing to avoid creating havoc.
13047 * Too much stuff here (turning of rps, connectors, ...) would
13048 * experience fancy races otherwise.
13049 */
13050 drm_irq_uninstall(dev);
13051 cancel_work_sync(&dev_priv->hotplug_work);
13052 /*
13053 * Due to the hpd irq storm handling the hotplug work can re-arm the
13054 * poll handlers. Hence disable polling after hpd handling is shut down.
13055 */
13056 drm_kms_helper_poll_fini(dev);
13057
13058 mutex_lock(&dev->struct_mutex);
13059
13060 intel_unregister_dsm_handler();
13061
13062 intel_disable_fbc(dev);
13063
13064 intel_disable_gt_powersave(dev);
13065
13066 ironlake_teardown_rc6(dev);
13067
13068 mutex_unlock(&dev->struct_mutex);
13069
13070 /* flush any delayed tasks or pending work */
13071 flush_scheduled_work();
13072
13073 /* destroy the backlight and sysfs files before encoders/connectors */
13074 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13075 struct intel_connector *intel_connector;
13076
13077 intel_connector = to_intel_connector(connector);
13078 intel_connector->unregister(intel_connector);
13079 }
13080
13081 drm_mode_config_cleanup(dev);
13082
13083 intel_cleanup_overlay(dev);
13084
13085 mutex_lock(&dev->struct_mutex);
13086 intel_cleanup_gt_powersave(dev);
13087 mutex_unlock(&dev->struct_mutex);
13088 }
13089
13090 /*
13091 * Return which encoder is currently attached for connector.
13092 */
13093 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13094 {
13095 return &intel_attached_encoder(connector)->base;
13096 }
13097
13098 void intel_connector_attach_encoder(struct intel_connector *connector,
13099 struct intel_encoder *encoder)
13100 {
13101 connector->encoder = encoder;
13102 drm_mode_connector_attach_encoder(&connector->base,
13103 &encoder->base);
13104 }
13105
13106 /*
13107 * set vga decode state - true == enable VGA decode
13108 */
13109 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13110 {
13111 struct drm_i915_private *dev_priv = dev->dev_private;
13112 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13113 u16 gmch_ctrl;
13114
13115 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13116 DRM_ERROR("failed to read control word\n");
13117 return -EIO;
13118 }
13119
13120 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13121 return 0;
13122
13123 if (state)
13124 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13125 else
13126 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13127
13128 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13129 DRM_ERROR("failed to write control word\n");
13130 return -EIO;
13131 }
13132
13133 return 0;
13134 }
13135
13136 struct intel_display_error_state {
13137
13138 u32 power_well_driver;
13139
13140 int num_transcoders;
13141
13142 struct intel_cursor_error_state {
13143 u32 control;
13144 u32 position;
13145 u32 base;
13146 u32 size;
13147 } cursor[I915_MAX_PIPES];
13148
13149 struct intel_pipe_error_state {
13150 bool power_domain_on;
13151 u32 source;
13152 u32 stat;
13153 } pipe[I915_MAX_PIPES];
13154
13155 struct intel_plane_error_state {
13156 u32 control;
13157 u32 stride;
13158 u32 size;
13159 u32 pos;
13160 u32 addr;
13161 u32 surface;
13162 u32 tile_offset;
13163 } plane[I915_MAX_PIPES];
13164
13165 struct intel_transcoder_error_state {
13166 bool power_domain_on;
13167 enum transcoder cpu_transcoder;
13168
13169 u32 conf;
13170
13171 u32 htotal;
13172 u32 hblank;
13173 u32 hsync;
13174 u32 vtotal;
13175 u32 vblank;
13176 u32 vsync;
13177 } transcoder[4];
13178 };
13179
13180 struct intel_display_error_state *
13181 intel_display_capture_error_state(struct drm_device *dev)
13182 {
13183 struct drm_i915_private *dev_priv = dev->dev_private;
13184 struct intel_display_error_state *error;
13185 int transcoders[] = {
13186 TRANSCODER_A,
13187 TRANSCODER_B,
13188 TRANSCODER_C,
13189 TRANSCODER_EDP,
13190 };
13191 int i;
13192
13193 if (INTEL_INFO(dev)->num_pipes == 0)
13194 return NULL;
13195
13196 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13197 if (error == NULL)
13198 return NULL;
13199
13200 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13201 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13202
13203 for_each_pipe(i) {
13204 error->pipe[i].power_domain_on =
13205 intel_display_power_enabled_unlocked(dev_priv,
13206 POWER_DOMAIN_PIPE(i));
13207 if (!error->pipe[i].power_domain_on)
13208 continue;
13209
13210 error->cursor[i].control = I915_READ(CURCNTR(i));
13211 error->cursor[i].position = I915_READ(CURPOS(i));
13212 error->cursor[i].base = I915_READ(CURBASE(i));
13213
13214 error->plane[i].control = I915_READ(DSPCNTR(i));
13215 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13216 if (INTEL_INFO(dev)->gen <= 3) {
13217 error->plane[i].size = I915_READ(DSPSIZE(i));
13218 error->plane[i].pos = I915_READ(DSPPOS(i));
13219 }
13220 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13221 error->plane[i].addr = I915_READ(DSPADDR(i));
13222 if (INTEL_INFO(dev)->gen >= 4) {
13223 error->plane[i].surface = I915_READ(DSPSURF(i));
13224 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13225 }
13226
13227 error->pipe[i].source = I915_READ(PIPESRC(i));
13228
13229 if (!HAS_PCH_SPLIT(dev))
13230 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13231 }
13232
13233 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13234 if (HAS_DDI(dev_priv->dev))
13235 error->num_transcoders++; /* Account for eDP. */
13236
13237 for (i = 0; i < error->num_transcoders; i++) {
13238 enum transcoder cpu_transcoder = transcoders[i];
13239
13240 error->transcoder[i].power_domain_on =
13241 intel_display_power_enabled_unlocked(dev_priv,
13242 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13243 if (!error->transcoder[i].power_domain_on)
13244 continue;
13245
13246 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13247
13248 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13249 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13250 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13251 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13252 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13253 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13254 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13255 }
13256
13257 return error;
13258 }
13259
13260 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13261
13262 void
13263 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13264 struct drm_device *dev,
13265 struct intel_display_error_state *error)
13266 {
13267 int i;
13268
13269 if (!error)
13270 return;
13271
13272 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13273 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13274 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13275 error->power_well_driver);
13276 for_each_pipe(i) {
13277 err_printf(m, "Pipe [%d]:\n", i);
13278 err_printf(m, " Power: %s\n",
13279 error->pipe[i].power_domain_on ? "on" : "off");
13280 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13281 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13282
13283 err_printf(m, "Plane [%d]:\n", i);
13284 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13285 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13286 if (INTEL_INFO(dev)->gen <= 3) {
13287 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13288 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13289 }
13290 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13291 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13292 if (INTEL_INFO(dev)->gen >= 4) {
13293 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13294 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13295 }
13296
13297 err_printf(m, "Cursor [%d]:\n", i);
13298 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13299 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13300 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13301 }
13302
13303 for (i = 0; i < error->num_transcoders; i++) {
13304 err_printf(m, "CPU transcoder: %c\n",
13305 transcoder_name(error->transcoder[i].cpu_transcoder));
13306 err_printf(m, " Power: %s\n",
13307 error->transcoder[i].power_domain_on ? "on" : "off");
13308 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13309 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13310 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13311 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13312 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13313 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13314 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13315 }
13316 }
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