2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
33 #include "intel_drv.h"
36 #include "drm_dp_helper.h"
38 #include "drm_crtc_helper.h"
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
43 static void intel_update_watermarks(struct drm_device
*dev
);
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
67 #define INTEL_P2_NUM 2
68 typedef struct intel_limit intel_limit_t
;
70 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
73 int, int, intel_clock_t
*);
76 #define I8XX_DOT_MIN 25000
77 #define I8XX_DOT_MAX 350000
78 #define I8XX_VCO_MIN 930000
79 #define I8XX_VCO_MAX 1400000
83 #define I8XX_M_MAX 140
84 #define I8XX_M1_MIN 18
85 #define I8XX_M1_MAX 26
87 #define I8XX_M2_MAX 16
89 #define I8XX_P_MAX 128
91 #define I8XX_P1_MAX 33
92 #define I8XX_P1_LVDS_MIN 1
93 #define I8XX_P1_LVDS_MAX 6
94 #define I8XX_P2_SLOW 4
95 #define I8XX_P2_FAST 2
96 #define I8XX_P2_LVDS_SLOW 14
97 #define I8XX_P2_LVDS_FAST 7
98 #define I8XX_P2_SLOW_LIMIT 165000
100 #define I9XX_DOT_MIN 20000
101 #define I9XX_DOT_MAX 400000
102 #define I9XX_VCO_MIN 1400000
103 #define I9XX_VCO_MAX 2800000
104 #define PINEVIEW_VCO_MIN 1700000
105 #define PINEVIEW_VCO_MAX 3500000
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN 3
110 #define PINEVIEW_N_MAX 6
111 #define I9XX_M_MIN 70
112 #define I9XX_M_MAX 120
113 #define PINEVIEW_M_MIN 2
114 #define PINEVIEW_M_MAX 256
115 #define I9XX_M1_MIN 10
116 #define I9XX_M1_MAX 22
117 #define I9XX_M2_MIN 5
118 #define I9XX_M2_MAX 9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN 0
121 #define PINEVIEW_M1_MAX 0
122 #define PINEVIEW_M2_MIN 0
123 #define PINEVIEW_M2_MAX 254
124 #define I9XX_P_SDVO_DAC_MIN 5
125 #define I9XX_P_SDVO_DAC_MAX 80
126 #define I9XX_P_LVDS_MIN 7
127 #define I9XX_P_LVDS_MAX 98
128 #define PINEVIEW_P_LVDS_MIN 7
129 #define PINEVIEW_P_LVDS_MAX 112
130 #define I9XX_P1_MIN 1
131 #define I9XX_P1_MAX 8
132 #define I9XX_P2_SDVO_DAC_SLOW 10
133 #define I9XX_P2_SDVO_DAC_FAST 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135 #define I9XX_P2_LVDS_SLOW 14
136 #define I9XX_P2_LVDS_FAST 7
137 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN 25000
141 #define G4X_DOT_SDVO_MAX 270000
142 #define G4X_VCO_MIN 1750000
143 #define G4X_VCO_MAX 3500000
144 #define G4X_N_SDVO_MIN 1
145 #define G4X_N_SDVO_MAX 4
146 #define G4X_M_SDVO_MIN 104
147 #define G4X_M_SDVO_MAX 138
148 #define G4X_M1_SDVO_MIN 17
149 #define G4X_M1_SDVO_MAX 23
150 #define G4X_M2_SDVO_MIN 5
151 #define G4X_M2_SDVO_MAX 11
152 #define G4X_P_SDVO_MIN 10
153 #define G4X_P_SDVO_MAX 30
154 #define G4X_P1_SDVO_MIN 1
155 #define G4X_P1_SDVO_MAX 3
156 #define G4X_P2_SDVO_SLOW 10
157 #define G4X_P2_SDVO_FAST 10
158 #define G4X_P2_SDVO_LIMIT 270000
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN 22000
162 #define G4X_DOT_HDMI_DAC_MAX 400000
163 #define G4X_N_HDMI_DAC_MIN 1
164 #define G4X_N_HDMI_DAC_MAX 4
165 #define G4X_M_HDMI_DAC_MIN 104
166 #define G4X_M_HDMI_DAC_MAX 138
167 #define G4X_M1_HDMI_DAC_MIN 16
168 #define G4X_M1_HDMI_DAC_MAX 23
169 #define G4X_M2_HDMI_DAC_MIN 5
170 #define G4X_M2_HDMI_DAC_MAX 11
171 #define G4X_P_HDMI_DAC_MIN 5
172 #define G4X_P_HDMI_DAC_MAX 80
173 #define G4X_P1_HDMI_DAC_MIN 1
174 #define G4X_P1_HDMI_DAC_MAX 8
175 #define G4X_P2_HDMI_DAC_SLOW 10
176 #define G4X_P2_HDMI_DAC_FAST 5
177 #define G4X_P2_HDMI_DAC_LIMIT 165000
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN 161670
219 #define G4X_DOT_DISPLAY_PORT_MAX 227000
220 #define G4X_N_DISPLAY_PORT_MIN 1
221 #define G4X_N_DISPLAY_PORT_MAX 2
222 #define G4X_M_DISPLAY_PORT_MIN 97
223 #define G4X_M_DISPLAY_PORT_MAX 108
224 #define G4X_M1_DISPLAY_PORT_MIN 0x10
225 #define G4X_M1_DISPLAY_PORT_MAX 0x12
226 #define G4X_M2_DISPLAY_PORT_MIN 0x05
227 #define G4X_M2_DISPLAY_PORT_MAX 0x06
228 #define G4X_P_DISPLAY_PORT_MIN 10
229 #define G4X_P_DISPLAY_PORT_MAX 20
230 #define G4X_P1_DISPLAY_PORT_MIN 1
231 #define G4X_P1_DISPLAY_PORT_MAX 2
232 #define G4X_P2_DISPLAY_PORT_SLOW 10
233 #define G4X_P2_DISPLAY_PORT_FAST 10
234 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
240 #define IRONLAKE_DOT_MIN 25000
241 #define IRONLAKE_DOT_MAX 350000
242 #define IRONLAKE_VCO_MIN 1760000
243 #define IRONLAKE_VCO_MAX 3510000
244 #define IRONLAKE_M1_MIN 12
245 #define IRONLAKE_M1_MAX 22
246 #define IRONLAKE_M2_MIN 5
247 #define IRONLAKE_M2_MAX 9
248 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
250 /* We have parameter ranges for different type of outputs. */
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN 1
254 #define IRONLAKE_DAC_N_MAX 5
255 #define IRONLAKE_DAC_M_MIN 79
256 #define IRONLAKE_DAC_M_MAX 127
257 #define IRONLAKE_DAC_P_MIN 5
258 #define IRONLAKE_DAC_P_MAX 80
259 #define IRONLAKE_DAC_P1_MIN 1
260 #define IRONLAKE_DAC_P1_MAX 8
261 #define IRONLAKE_DAC_P2_SLOW 10
262 #define IRONLAKE_DAC_P2_FAST 5
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN 1
266 #define IRONLAKE_LVDS_S_N_MAX 3
267 #define IRONLAKE_LVDS_S_M_MIN 79
268 #define IRONLAKE_LVDS_S_M_MAX 118
269 #define IRONLAKE_LVDS_S_P_MIN 28
270 #define IRONLAKE_LVDS_S_P_MAX 112
271 #define IRONLAKE_LVDS_S_P1_MIN 2
272 #define IRONLAKE_LVDS_S_P1_MAX 8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN 1
278 #define IRONLAKE_LVDS_D_N_MAX 3
279 #define IRONLAKE_LVDS_D_M_MIN 79
280 #define IRONLAKE_LVDS_D_M_MAX 127
281 #define IRONLAKE_LVDS_D_P_MIN 14
282 #define IRONLAKE_LVDS_D_P_MAX 56
283 #define IRONLAKE_LVDS_D_P1_MIN 2
284 #define IRONLAKE_LVDS_D_P1_MAX 8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313 #define IRONLAKE_DP_N_MIN 1
314 #define IRONLAKE_DP_N_MAX 2
315 #define IRONLAKE_DP_M_MIN 81
316 #define IRONLAKE_DP_M_MAX 90
317 #define IRONLAKE_DP_P_MIN 10
318 #define IRONLAKE_DP_P_MAX 20
319 #define IRONLAKE_DP_P2_FAST 10
320 #define IRONLAKE_DP_P2_SLOW 10
321 #define IRONLAKE_DP_P2_LIMIT 0
322 #define IRONLAKE_DP_P1_MIN 1
323 #define IRONLAKE_DP_P1_MAX 2
326 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
327 int target
, int refclk
, intel_clock_t
*best_clock
);
329 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
330 int target
, int refclk
, intel_clock_t
*best_clock
);
333 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
334 int target
, int refclk
, intel_clock_t
*best_clock
);
336 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
337 int target
, int refclk
, intel_clock_t
*best_clock
);
339 static const intel_limit_t intel_limits_i8xx_dvo
= {
340 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
341 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
342 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
343 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
344 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
345 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
346 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
347 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
348 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
349 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
350 .find_pll
= intel_find_best_PLL
,
353 static const intel_limit_t intel_limits_i8xx_lvds
= {
354 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
355 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
356 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
357 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
358 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
359 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
360 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
361 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
362 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
363 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
364 .find_pll
= intel_find_best_PLL
,
367 static const intel_limit_t intel_limits_i9xx_sdvo
= {
368 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
369 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
370 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
371 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
372 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
373 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
374 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
375 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
376 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
377 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
378 .find_pll
= intel_find_best_PLL
,
381 static const intel_limit_t intel_limits_i9xx_lvds
= {
382 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
383 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
384 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
385 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
386 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
387 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
388 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
389 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
393 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
394 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
395 .find_pll
= intel_find_best_PLL
,
398 /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo
= {
400 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
401 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
402 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
403 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
404 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
405 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
406 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
407 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
408 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
409 .p2_slow
= G4X_P2_SDVO_SLOW
,
410 .p2_fast
= G4X_P2_SDVO_FAST
412 .find_pll
= intel_g4x_find_best_PLL
,
415 static const intel_limit_t intel_limits_g4x_hdmi
= {
416 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
417 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
418 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
419 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
420 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
421 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
422 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
423 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
424 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
425 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
426 .p2_fast
= G4X_P2_HDMI_DAC_FAST
428 .find_pll
= intel_g4x_find_best_PLL
,
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
432 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
433 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
434 .vco
= { .min
= G4X_VCO_MIN
,
435 .max
= G4X_VCO_MAX
},
436 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
437 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
438 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
439 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
440 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
441 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
442 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
443 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
444 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
445 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
446 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
447 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
448 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
449 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
450 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
452 .find_pll
= intel_g4x_find_best_PLL
,
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
456 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
457 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
458 .vco
= { .min
= G4X_VCO_MIN
,
459 .max
= G4X_VCO_MAX
},
460 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
461 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
462 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
463 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
464 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
465 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
466 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
467 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
468 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
469 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
470 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
471 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
472 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
473 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
474 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
476 .find_pll
= intel_g4x_find_best_PLL
,
479 static const intel_limit_t intel_limits_g4x_display_port
= {
480 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
481 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
482 .vco
= { .min
= G4X_VCO_MIN
,
484 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
485 .max
= G4X_N_DISPLAY_PORT_MAX
},
486 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
487 .max
= G4X_M_DISPLAY_PORT_MAX
},
488 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
489 .max
= G4X_M1_DISPLAY_PORT_MAX
},
490 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
491 .max
= G4X_M2_DISPLAY_PORT_MAX
},
492 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
493 .max
= G4X_P_DISPLAY_PORT_MAX
},
494 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
495 .max
= G4X_P1_DISPLAY_PORT_MAX
},
496 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
497 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
498 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
499 .find_pll
= intel_find_pll_g4x_dp
,
502 static const intel_limit_t intel_limits_pineview_sdvo
= {
503 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
504 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
505 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
506 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
507 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
508 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
509 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
510 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
511 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
512 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
513 .find_pll
= intel_find_best_PLL
,
516 static const intel_limit_t intel_limits_pineview_lvds
= {
517 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
518 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
519 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
520 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
521 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
522 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
523 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
524 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
525 /* Pineview only supports single-channel mode. */
526 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
527 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
528 .find_pll
= intel_find_best_PLL
,
531 static const intel_limit_t intel_limits_ironlake_dac
= {
532 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
533 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
534 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
535 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
536 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
537 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
538 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
539 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
540 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
541 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
542 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
543 .find_pll
= intel_g4x_find_best_PLL
,
546 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
547 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
548 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
549 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
550 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
551 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
552 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
553 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
554 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
555 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
556 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
557 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
558 .find_pll
= intel_g4x_find_best_PLL
,
561 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
562 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
563 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
564 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
565 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
566 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
567 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
568 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
569 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
570 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
571 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
572 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
573 .find_pll
= intel_g4x_find_best_PLL
,
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
577 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
578 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
579 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
580 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
581 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
582 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
583 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
584 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
585 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
586 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
587 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
588 .find_pll
= intel_g4x_find_best_PLL
,
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
592 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
593 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
594 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
595 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
596 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
597 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
598 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
599 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
600 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
601 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
602 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
603 .find_pll
= intel_g4x_find_best_PLL
,
606 static const intel_limit_t intel_limits_ironlake_display_port
= {
607 .dot
= { .min
= IRONLAKE_DOT_MIN
,
608 .max
= IRONLAKE_DOT_MAX
},
609 .vco
= { .min
= IRONLAKE_VCO_MIN
,
610 .max
= IRONLAKE_VCO_MAX
},
611 .n
= { .min
= IRONLAKE_DP_N_MIN
,
612 .max
= IRONLAKE_DP_N_MAX
},
613 .m
= { .min
= IRONLAKE_DP_M_MIN
,
614 .max
= IRONLAKE_DP_M_MAX
},
615 .m1
= { .min
= IRONLAKE_M1_MIN
,
616 .max
= IRONLAKE_M1_MAX
},
617 .m2
= { .min
= IRONLAKE_M2_MIN
,
618 .max
= IRONLAKE_M2_MAX
},
619 .p
= { .min
= IRONLAKE_DP_P_MIN
,
620 .max
= IRONLAKE_DP_P_MAX
},
621 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
622 .max
= IRONLAKE_DP_P1_MAX
},
623 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
624 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
625 .p2_fast
= IRONLAKE_DP_P2_FAST
},
626 .find_pll
= intel_find_pll_ironlake_dp
,
629 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
631 struct drm_device
*dev
= crtc
->dev
;
632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 const intel_limit_t
*limit
;
636 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
637 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
640 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
641 LVDS_CLKB_POWER_UP
) {
642 /* LVDS dual channel */
644 limit
= &intel_limits_ironlake_dual_lvds_100m
;
646 limit
= &intel_limits_ironlake_dual_lvds
;
649 limit
= &intel_limits_ironlake_single_lvds_100m
;
651 limit
= &intel_limits_ironlake_single_lvds
;
653 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
655 limit
= &intel_limits_ironlake_display_port
;
657 limit
= &intel_limits_ironlake_dac
;
662 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
664 struct drm_device
*dev
= crtc
->dev
;
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 const intel_limit_t
*limit
;
668 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
669 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
671 /* LVDS with dual channel */
672 limit
= &intel_limits_g4x_dual_channel_lvds
;
674 /* LVDS with dual channel */
675 limit
= &intel_limits_g4x_single_channel_lvds
;
676 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
677 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
678 limit
= &intel_limits_g4x_hdmi
;
679 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
680 limit
= &intel_limits_g4x_sdvo
;
681 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
682 limit
= &intel_limits_g4x_display_port
;
683 } else /* The option is for other outputs */
684 limit
= &intel_limits_i9xx_sdvo
;
689 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
691 struct drm_device
*dev
= crtc
->dev
;
692 const intel_limit_t
*limit
;
694 if (HAS_PCH_SPLIT(dev
))
695 limit
= intel_ironlake_limit(crtc
);
696 else if (IS_G4X(dev
)) {
697 limit
= intel_g4x_limit(crtc
);
698 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
699 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
700 limit
= &intel_limits_i9xx_lvds
;
702 limit
= &intel_limits_i9xx_sdvo
;
703 } else if (IS_PINEVIEW(dev
)) {
704 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
705 limit
= &intel_limits_pineview_lvds
;
707 limit
= &intel_limits_pineview_sdvo
;
709 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
710 limit
= &intel_limits_i8xx_lvds
;
712 limit
= &intel_limits_i8xx_dvo
;
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
720 clock
->m
= clock
->m2
+ 2;
721 clock
->p
= clock
->p1
* clock
->p2
;
722 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
723 clock
->dot
= clock
->vco
/ clock
->p
;
726 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
728 if (IS_PINEVIEW(dev
)) {
729 pineview_clock(refclk
, clock
);
732 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
733 clock
->p
= clock
->p1
* clock
->p2
;
734 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
735 clock
->dot
= clock
->vco
/ clock
->p
;
739 * Returns whether any output on the specified pipe is of the specified type
741 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
743 struct drm_device
*dev
= crtc
->dev
;
744 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
745 struct drm_encoder
*l_entry
;
747 list_for_each_entry(l_entry
, &mode_config
->encoder_list
, head
) {
748 if (l_entry
&& l_entry
->crtc
== crtc
) {
749 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(l_entry
);
750 if (intel_encoder
->type
== type
)
757 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
759 * Returns whether the given set of divisors are valid for a given refclk with
760 * the given connectors.
763 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
765 const intel_limit_t
*limit
= intel_limit (crtc
);
766 struct drm_device
*dev
= crtc
->dev
;
768 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
769 INTELPllInvalid ("p1 out of range\n");
770 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
771 INTELPllInvalid ("p out of range\n");
772 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
773 INTELPllInvalid ("m2 out of range\n");
774 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
775 INTELPllInvalid ("m1 out of range\n");
776 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
777 INTELPllInvalid ("m1 <= m2\n");
778 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
779 INTELPllInvalid ("m out of range\n");
780 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
781 INTELPllInvalid ("n out of range\n");
782 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
783 INTELPllInvalid ("vco out of range\n");
784 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785 * connector, etc., rather than just a single range.
787 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
788 INTELPllInvalid ("dot out of range\n");
794 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
795 int target
, int refclk
, intel_clock_t
*best_clock
)
798 struct drm_device
*dev
= crtc
->dev
;
799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
804 (I915_READ(LVDS
)) != 0) {
806 * For LVDS, if the panel is on, just rely on its current
807 * settings for dual-channel. We haven't figured out how to
808 * reliably set up different single/dual channel state, if we
811 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
813 clock
.p2
= limit
->p2
.p2_fast
;
815 clock
.p2
= limit
->p2
.p2_slow
;
817 if (target
< limit
->p2
.dot_limit
)
818 clock
.p2
= limit
->p2
.p2_slow
;
820 clock
.p2
= limit
->p2
.p2_fast
;
823 memset (best_clock
, 0, sizeof (*best_clock
));
825 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
827 for (clock
.m2
= limit
->m2
.min
;
828 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
829 /* m1 is always 0 in Pineview */
830 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
832 for (clock
.n
= limit
->n
.min
;
833 clock
.n
<= limit
->n
.max
; clock
.n
++) {
834 for (clock
.p1
= limit
->p1
.min
;
835 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
838 intel_clock(dev
, refclk
, &clock
);
840 if (!intel_PLL_is_valid(crtc
, &clock
))
843 this_err
= abs(clock
.dot
- target
);
844 if (this_err
< err
) {
853 return (err
!= target
);
857 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
858 int target
, int refclk
, intel_clock_t
*best_clock
)
860 struct drm_device
*dev
= crtc
->dev
;
861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
865 /* approximately equals target * 0.00488 */
866 int err_most
= (target
>> 8) + (target
>> 10);
869 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
872 if (HAS_PCH_SPLIT(dev
))
876 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
878 clock
.p2
= limit
->p2
.p2_fast
;
880 clock
.p2
= limit
->p2
.p2_slow
;
882 if (target
< limit
->p2
.dot_limit
)
883 clock
.p2
= limit
->p2
.p2_slow
;
885 clock
.p2
= limit
->p2
.p2_fast
;
888 memset(best_clock
, 0, sizeof(*best_clock
));
889 max_n
= limit
->n
.max
;
890 /* based on hardware requirement, prefer smaller n to precision */
891 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
892 /* based on hardware requirement, prefere larger m1,m2 */
893 for (clock
.m1
= limit
->m1
.max
;
894 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
895 for (clock
.m2
= limit
->m2
.max
;
896 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
897 for (clock
.p1
= limit
->p1
.max
;
898 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
901 intel_clock(dev
, refclk
, &clock
);
902 if (!intel_PLL_is_valid(crtc
, &clock
))
904 this_err
= abs(clock
.dot
- target
) ;
905 if (this_err
< err_most
) {
919 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
920 int target
, int refclk
, intel_clock_t
*best_clock
)
922 struct drm_device
*dev
= crtc
->dev
;
925 /* return directly when it is eDP */
929 if (target
< 200000) {
942 intel_clock(dev
, refclk
, &clock
);
943 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
949 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
950 int target
, int refclk
, intel_clock_t
*best_clock
)
953 if (target
< 200000) {
966 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
967 clock
.p
= (clock
.p1
* clock
.p2
);
968 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
970 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
975 intel_wait_for_vblank(struct drm_device
*dev
)
977 /* Wait for 20ms, i.e. one cycle at 50hz. */
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
984 struct drm_device
*dev
= crtc
->dev
;
985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
986 struct drm_framebuffer
*fb
= crtc
->fb
;
987 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
988 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
991 u32 fbc_ctl
, fbc_ctl2
;
993 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
995 if (fb
->pitch
< dev_priv
->cfb_pitch
)
996 dev_priv
->cfb_pitch
= fb
->pitch
;
998 /* FBC_CTL wants 64B units */
999 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1000 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1001 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1002 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1004 /* Clear old tags */
1005 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1006 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1009 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1010 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1011 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1012 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1013 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1016 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1018 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1019 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1020 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1021 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1022 fbc_ctl
|= dev_priv
->cfb_fence
;
1023 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1025 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1029 void i8xx_disable_fbc(struct drm_device
*dev
)
1031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1034 if (!I915_HAS_FBC(dev
))
1037 /* Disable compression */
1038 fbc_ctl
= I915_READ(FBC_CONTROL
);
1039 fbc_ctl
&= ~FBC_CTL_EN
;
1040 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1042 /* Wait for compressing bit to clear */
1043 while (I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
)
1046 intel_wait_for_vblank(dev
);
1048 DRM_DEBUG_KMS("disabled FBC\n");
1051 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1055 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1058 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1060 struct drm_device
*dev
= crtc
->dev
;
1061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1062 struct drm_framebuffer
*fb
= crtc
->fb
;
1063 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1064 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1066 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
1068 unsigned long stall_watermark
= 200;
1071 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1072 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1073 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1075 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1076 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1077 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1078 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1080 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1083 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1084 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1085 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1086 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1087 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1090 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1092 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1095 void g4x_disable_fbc(struct drm_device
*dev
)
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1100 /* Disable compression */
1101 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1102 dpfc_ctl
&= ~DPFC_CTL_EN
;
1103 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1104 intel_wait_for_vblank(dev
);
1106 DRM_DEBUG_KMS("disabled FBC\n");
1109 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1113 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1116 bool intel_fbc_enabled(struct drm_device
*dev
)
1118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1120 if (!dev_priv
->display
.fbc_enabled
)
1123 return dev_priv
->display
.fbc_enabled(dev
);
1126 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1128 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1130 if (!dev_priv
->display
.enable_fbc
)
1133 dev_priv
->display
.enable_fbc(crtc
, interval
);
1136 void intel_disable_fbc(struct drm_device
*dev
)
1138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1140 if (!dev_priv
->display
.disable_fbc
)
1143 dev_priv
->display
.disable_fbc(dev
);
1147 * intel_update_fbc - enable/disable FBC as needed
1148 * @crtc: CRTC to point the compressor at
1149 * @mode: mode in use
1151 * Set up the framebuffer compression hardware at mode set time. We
1152 * enable it if possible:
1153 * - plane A only (on pre-965)
1154 * - no pixel mulitply/line duplication
1155 * - no alpha buffer discard
1157 * - framebuffer <= 2048 in width, 1536 in height
1159 * We can't assume that any compression will take place (worst case),
1160 * so the compressed buffer has to be the same size as the uncompressed
1161 * one. It also must reside (along with the line length buffer) in
1164 * We need to enable/disable FBC on a global basis.
1166 static void intel_update_fbc(struct drm_crtc
*crtc
,
1167 struct drm_display_mode
*mode
)
1169 struct drm_device
*dev
= crtc
->dev
;
1170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1171 struct drm_framebuffer
*fb
= crtc
->fb
;
1172 struct intel_framebuffer
*intel_fb
;
1173 struct drm_i915_gem_object
*obj_priv
;
1174 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1175 int plane
= intel_crtc
->plane
;
1177 if (!i915_powersave
)
1180 if (!I915_HAS_FBC(dev
))
1186 intel_fb
= to_intel_framebuffer(fb
);
1187 obj_priv
= to_intel_bo(intel_fb
->obj
);
1190 * If FBC is already on, we just have to verify that we can
1191 * keep it that way...
1192 * Need to disable if:
1193 * - changing FBC params (stride, fence, mode)
1194 * - new fb is too large to fit in compressed buffer
1195 * - going to an unsupported config (interlace, pixel multiply, etc.)
1197 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1198 DRM_DEBUG_KMS("framebuffer too large, disabling "
1200 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1203 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1204 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1205 DRM_DEBUG_KMS("mode incompatible with compression, "
1207 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1210 if ((mode
->hdisplay
> 2048) ||
1211 (mode
->vdisplay
> 1536)) {
1212 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1213 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1216 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1217 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1218 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1221 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1222 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1223 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1227 if (intel_fbc_enabled(dev
)) {
1228 /* We can re-enable it in this case, but need to update pitch */
1229 if ((fb
->pitch
> dev_priv
->cfb_pitch
) ||
1230 (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
) ||
1231 (plane
!= dev_priv
->cfb_plane
))
1232 intel_disable_fbc(dev
);
1235 /* Now try to turn it back on if possible */
1236 if (!intel_fbc_enabled(dev
))
1237 intel_enable_fbc(crtc
, 500);
1242 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1243 /* Multiple disables should be harmless */
1244 if (intel_fbc_enabled(dev
))
1245 intel_disable_fbc(dev
);
1249 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1251 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1255 switch (obj_priv
->tiling_mode
) {
1256 case I915_TILING_NONE
:
1257 alignment
= 64 * 1024;
1260 /* pin() will align the object as required by fence */
1264 /* FIXME: Is this true? */
1265 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1271 ret
= i915_gem_object_pin(obj
, alignment
);
1275 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1276 * fence, whereas 965+ only requires a fence if using
1277 * framebuffer compression. For simplicity, we always install
1278 * a fence as the cost is not that onerous.
1280 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1281 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1282 ret
= i915_gem_object_get_fence_reg(obj
);
1284 i915_gem_object_unpin(obj
);
1293 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1294 struct drm_framebuffer
*old_fb
)
1296 struct drm_device
*dev
= crtc
->dev
;
1297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1298 struct drm_i915_master_private
*master_priv
;
1299 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1300 struct intel_framebuffer
*intel_fb
;
1301 struct drm_i915_gem_object
*obj_priv
;
1302 struct drm_gem_object
*obj
;
1303 int pipe
= intel_crtc
->pipe
;
1304 int plane
= intel_crtc
->plane
;
1305 unsigned long Start
, Offset
;
1306 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1307 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1308 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1309 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1310 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1316 DRM_DEBUG_KMS("No FB bound\n");
1325 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1329 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1330 obj
= intel_fb
->obj
;
1331 obj_priv
= to_intel_bo(obj
);
1333 mutex_lock(&dev
->struct_mutex
);
1334 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1336 mutex_unlock(&dev
->struct_mutex
);
1340 ret
= i915_gem_object_set_to_display_plane(obj
);
1342 i915_gem_object_unpin(obj
);
1343 mutex_unlock(&dev
->struct_mutex
);
1347 dspcntr
= I915_READ(dspcntr_reg
);
1348 /* Mask out pixel format bits in case we change it */
1349 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1350 switch (crtc
->fb
->bits_per_pixel
) {
1352 dspcntr
|= DISPPLANE_8BPP
;
1355 if (crtc
->fb
->depth
== 15)
1356 dspcntr
|= DISPPLANE_15_16BPP
;
1358 dspcntr
|= DISPPLANE_16BPP
;
1362 if (crtc
->fb
->depth
== 30)
1363 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
1365 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1368 DRM_ERROR("Unknown color depth\n");
1369 i915_gem_object_unpin(obj
);
1370 mutex_unlock(&dev
->struct_mutex
);
1373 if (IS_I965G(dev
)) {
1374 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1375 dspcntr
|= DISPPLANE_TILED
;
1377 dspcntr
&= ~DISPPLANE_TILED
;
1380 if (HAS_PCH_SPLIT(dev
))
1382 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1384 I915_WRITE(dspcntr_reg
, dspcntr
);
1386 Start
= obj_priv
->gtt_offset
;
1387 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1389 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
1390 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1391 if (IS_I965G(dev
)) {
1392 I915_WRITE(dspbase
, Offset
);
1394 I915_WRITE(dspsurf
, Start
);
1396 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1398 I915_WRITE(dspbase
, Start
+ Offset
);
1402 if ((IS_I965G(dev
) || plane
== 0))
1403 intel_update_fbc(crtc
, &crtc
->mode
);
1405 intel_wait_for_vblank(dev
);
1408 intel_fb
= to_intel_framebuffer(old_fb
);
1409 obj_priv
= to_intel_bo(intel_fb
->obj
);
1410 i915_gem_object_unpin(intel_fb
->obj
);
1412 intel_increase_pllclock(crtc
, true);
1414 mutex_unlock(&dev
->struct_mutex
);
1416 if (!dev
->primary
->master
)
1419 master_priv
= dev
->primary
->master
->driver_priv
;
1420 if (!master_priv
->sarea_priv
)
1424 master_priv
->sarea_priv
->pipeB_x
= x
;
1425 master_priv
->sarea_priv
->pipeB_y
= y
;
1427 master_priv
->sarea_priv
->pipeA_x
= x
;
1428 master_priv
->sarea_priv
->pipeA_y
= y
;
1434 /* Disable the VGA plane that we never use */
1435 static void i915_disable_vga (struct drm_device
*dev
)
1437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1441 if (HAS_PCH_SPLIT(dev
))
1442 vga_reg
= CPU_VGACNTRL
;
1446 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1449 I915_WRITE8(VGA_SR_INDEX
, 1);
1450 sr1
= I915_READ8(VGA_SR_DATA
);
1451 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1454 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1457 static void ironlake_disable_pll_edp (struct drm_crtc
*crtc
)
1459 struct drm_device
*dev
= crtc
->dev
;
1460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1463 DRM_DEBUG_KMS("\n");
1464 dpa_ctl
= I915_READ(DP_A
);
1465 dpa_ctl
&= ~DP_PLL_ENABLE
;
1466 I915_WRITE(DP_A
, dpa_ctl
);
1469 static void ironlake_enable_pll_edp (struct drm_crtc
*crtc
)
1471 struct drm_device
*dev
= crtc
->dev
;
1472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1475 dpa_ctl
= I915_READ(DP_A
);
1476 dpa_ctl
|= DP_PLL_ENABLE
;
1477 I915_WRITE(DP_A
, dpa_ctl
);
1482 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1484 struct drm_device
*dev
= crtc
->dev
;
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1488 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1489 dpa_ctl
= I915_READ(DP_A
);
1490 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1492 if (clock
< 200000) {
1494 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1495 /* workaround for 160Mhz:
1496 1) program 0x4600c bits 15:0 = 0x8124
1497 2) program 0x46010 bit 0 = 1
1498 3) program 0x46034 bit 24 = 1
1499 4) program 0x64000 bit 14 = 1
1501 temp
= I915_READ(0x4600c);
1503 I915_WRITE(0x4600c, temp
| 0x8124);
1505 temp
= I915_READ(0x46010);
1506 I915_WRITE(0x46010, temp
| 1);
1508 temp
= I915_READ(0x46034);
1509 I915_WRITE(0x46034, temp
| (1 << 24));
1511 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1513 I915_WRITE(DP_A
, dpa_ctl
);
1518 /* The FDI link training functions for ILK/Ibexpeak. */
1519 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1521 struct drm_device
*dev
= crtc
->dev
;
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1524 int pipe
= intel_crtc
->pipe
;
1525 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1526 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1527 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1528 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1529 u32 temp
, tries
= 0;
1531 /* enable CPU FDI TX and PCH FDI RX */
1532 temp
= I915_READ(fdi_tx_reg
);
1533 temp
|= FDI_TX_ENABLE
;
1535 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1536 temp
&= ~FDI_LINK_TRAIN_NONE
;
1537 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1538 I915_WRITE(fdi_tx_reg
, temp
);
1539 I915_READ(fdi_tx_reg
);
1541 temp
= I915_READ(fdi_rx_reg
);
1542 temp
&= ~FDI_LINK_TRAIN_NONE
;
1543 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1544 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1545 I915_READ(fdi_rx_reg
);
1548 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1550 temp
= I915_READ(fdi_rx_imr_reg
);
1551 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1552 temp
&= ~FDI_RX_BIT_LOCK
;
1553 I915_WRITE(fdi_rx_imr_reg
, temp
);
1554 I915_READ(fdi_rx_imr_reg
);
1558 temp
= I915_READ(fdi_rx_iir_reg
);
1559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1561 if ((temp
& FDI_RX_BIT_LOCK
)) {
1562 DRM_DEBUG_KMS("FDI train 1 done.\n");
1563 I915_WRITE(fdi_rx_iir_reg
,
1564 temp
| FDI_RX_BIT_LOCK
);
1571 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1577 temp
= I915_READ(fdi_tx_reg
);
1578 temp
&= ~FDI_LINK_TRAIN_NONE
;
1579 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1580 I915_WRITE(fdi_tx_reg
, temp
);
1582 temp
= I915_READ(fdi_rx_reg
);
1583 temp
&= ~FDI_LINK_TRAIN_NONE
;
1584 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1585 I915_WRITE(fdi_rx_reg
, temp
);
1591 temp
= I915_READ(fdi_rx_iir_reg
);
1592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1594 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1595 I915_WRITE(fdi_rx_iir_reg
,
1596 temp
| FDI_RX_SYMBOL_LOCK
);
1597 DRM_DEBUG_KMS("FDI train 2 done.\n");
1604 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1609 DRM_DEBUG_KMS("FDI train done\n");
1612 static int snb_b_fdi_train_param
[] = {
1613 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1614 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1615 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1616 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1619 /* The FDI link training functions for SNB/Cougarpoint. */
1620 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1622 struct drm_device
*dev
= crtc
->dev
;
1623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1624 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1625 int pipe
= intel_crtc
->pipe
;
1626 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1627 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1628 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1629 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1632 /* enable CPU FDI TX and PCH FDI RX */
1633 temp
= I915_READ(fdi_tx_reg
);
1634 temp
|= FDI_TX_ENABLE
;
1636 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1637 temp
&= ~FDI_LINK_TRAIN_NONE
;
1638 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1639 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1641 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1642 I915_WRITE(fdi_tx_reg
, temp
);
1643 I915_READ(fdi_tx_reg
);
1645 temp
= I915_READ(fdi_rx_reg
);
1646 if (HAS_PCH_CPT(dev
)) {
1647 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1648 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1650 temp
&= ~FDI_LINK_TRAIN_NONE
;
1651 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1653 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1654 I915_READ(fdi_rx_reg
);
1657 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1659 temp
= I915_READ(fdi_rx_imr_reg
);
1660 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1661 temp
&= ~FDI_RX_BIT_LOCK
;
1662 I915_WRITE(fdi_rx_imr_reg
, temp
);
1663 I915_READ(fdi_rx_imr_reg
);
1666 for (i
= 0; i
< 4; i
++ ) {
1667 temp
= I915_READ(fdi_tx_reg
);
1668 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1669 temp
|= snb_b_fdi_train_param
[i
];
1670 I915_WRITE(fdi_tx_reg
, temp
);
1673 temp
= I915_READ(fdi_rx_iir_reg
);
1674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1676 if (temp
& FDI_RX_BIT_LOCK
) {
1677 I915_WRITE(fdi_rx_iir_reg
,
1678 temp
| FDI_RX_BIT_LOCK
);
1679 DRM_DEBUG_KMS("FDI train 1 done.\n");
1684 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1687 temp
= I915_READ(fdi_tx_reg
);
1688 temp
&= ~FDI_LINK_TRAIN_NONE
;
1689 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1691 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1693 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1695 I915_WRITE(fdi_tx_reg
, temp
);
1697 temp
= I915_READ(fdi_rx_reg
);
1698 if (HAS_PCH_CPT(dev
)) {
1699 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1700 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1702 temp
&= ~FDI_LINK_TRAIN_NONE
;
1703 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1705 I915_WRITE(fdi_rx_reg
, temp
);
1708 for (i
= 0; i
< 4; i
++ ) {
1709 temp
= I915_READ(fdi_tx_reg
);
1710 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1711 temp
|= snb_b_fdi_train_param
[i
];
1712 I915_WRITE(fdi_tx_reg
, temp
);
1715 temp
= I915_READ(fdi_rx_iir_reg
);
1716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1718 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1719 I915_WRITE(fdi_rx_iir_reg
,
1720 temp
| FDI_RX_SYMBOL_LOCK
);
1721 DRM_DEBUG_KMS("FDI train 2 done.\n");
1726 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1728 DRM_DEBUG_KMS("FDI train done.\n");
1731 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1733 struct drm_device
*dev
= crtc
->dev
;
1734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1735 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1736 int pipe
= intel_crtc
->pipe
;
1737 int plane
= intel_crtc
->plane
;
1738 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1739 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1740 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1741 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1742 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1743 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1744 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1745 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1746 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1747 int pf_win_pos
= (pipe
== 0) ? PFA_WIN_POS
: PFB_WIN_POS
;
1748 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1749 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1750 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1751 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1752 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1753 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1754 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1755 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1756 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1757 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1758 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1759 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1760 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
1765 temp
= I915_READ(pipeconf_reg
);
1766 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1768 /* XXX: When our outputs are all unaware of DPMS modes other than off
1769 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1772 case DRM_MODE_DPMS_ON
:
1773 case DRM_MODE_DPMS_STANDBY
:
1774 case DRM_MODE_DPMS_SUSPEND
:
1775 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe
);
1777 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1778 temp
= I915_READ(PCH_LVDS
);
1779 if ((temp
& LVDS_PORT_EN
) == 0) {
1780 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1781 POSTING_READ(PCH_LVDS
);
1786 /* enable eDP PLL */
1787 ironlake_enable_pll_edp(crtc
);
1790 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1791 temp
= I915_READ(fdi_rx_reg
);
1793 * make the BPC in FDI Rx be consistent with that in
1796 temp
&= ~(0x7 << 16);
1797 temp
|= (pipe_bpc
<< 11);
1799 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1800 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
1801 I915_READ(fdi_rx_reg
);
1804 /* Switch from Rawclk to PCDclk */
1805 temp
= I915_READ(fdi_rx_reg
);
1806 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
1807 I915_READ(fdi_rx_reg
);
1810 /* Enable CPU FDI TX PLL, always on for Ironlake */
1811 temp
= I915_READ(fdi_tx_reg
);
1812 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1813 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1814 I915_READ(fdi_tx_reg
);
1819 /* Enable panel fitting for LVDS */
1820 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1821 temp
= I915_READ(pf_ctl_reg
);
1822 I915_WRITE(pf_ctl_reg
, temp
| PF_ENABLE
| PF_FILTER_MED_3x3
);
1824 /* currently full aspect */
1825 I915_WRITE(pf_win_pos
, 0);
1827 I915_WRITE(pf_win_size
,
1828 (dev_priv
->panel_fixed_mode
->hdisplay
<< 16) |
1829 (dev_priv
->panel_fixed_mode
->vdisplay
));
1832 /* Enable CPU pipe */
1833 temp
= I915_READ(pipeconf_reg
);
1834 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1835 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1836 I915_READ(pipeconf_reg
);
1840 /* configure and enable CPU plane */
1841 temp
= I915_READ(dspcntr_reg
);
1842 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1843 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1844 /* Flush the plane changes */
1845 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1849 /* For PCH output, training FDI link */
1851 gen6_fdi_link_train(crtc
);
1853 ironlake_fdi_link_train(crtc
);
1855 /* enable PCH DPLL */
1856 temp
= I915_READ(pch_dpll_reg
);
1857 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1858 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1859 I915_READ(pch_dpll_reg
);
1863 if (HAS_PCH_CPT(dev
)) {
1864 /* Be sure PCH DPLL SEL is set */
1865 temp
= I915_READ(PCH_DPLL_SEL
);
1866 if (trans_dpll_sel
== 0 &&
1867 (temp
& TRANSA_DPLL_ENABLE
) == 0)
1868 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
1869 else if (trans_dpll_sel
== 1 &&
1870 (temp
& TRANSB_DPLL_ENABLE
) == 0)
1871 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
1872 I915_WRITE(PCH_DPLL_SEL
, temp
);
1873 I915_READ(PCH_DPLL_SEL
);
1876 /* set transcoder timing */
1877 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1878 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1879 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
1881 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
1882 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
1883 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
1885 /* enable normal train */
1886 temp
= I915_READ(fdi_tx_reg
);
1887 temp
&= ~FDI_LINK_TRAIN_NONE
;
1888 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1889 FDI_TX_ENHANCE_FRAME_ENABLE
);
1890 I915_READ(fdi_tx_reg
);
1892 temp
= I915_READ(fdi_rx_reg
);
1893 if (HAS_PCH_CPT(dev
)) {
1894 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1895 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
1897 temp
&= ~FDI_LINK_TRAIN_NONE
;
1898 temp
|= FDI_LINK_TRAIN_NONE
;
1900 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
1901 I915_READ(fdi_rx_reg
);
1903 /* wait one idle pattern time */
1906 /* For PCH DP, enable TRANS_DP_CTL */
1907 if (HAS_PCH_CPT(dev
) &&
1908 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
1909 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
1912 reg
= I915_READ(trans_dp_ctl
);
1913 reg
&= ~TRANS_DP_PORT_SEL_MASK
;
1914 reg
= TRANS_DP_OUTPUT_ENABLE
|
1915 TRANS_DP_ENH_FRAMING
|
1916 TRANS_DP_VSYNC_ACTIVE_HIGH
|
1917 TRANS_DP_HSYNC_ACTIVE_HIGH
;
1919 switch (intel_trans_dp_port_sel(crtc
)) {
1921 reg
|= TRANS_DP_PORT_SEL_B
;
1924 reg
|= TRANS_DP_PORT_SEL_C
;
1927 reg
|= TRANS_DP_PORT_SEL_D
;
1930 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1931 reg
|= TRANS_DP_PORT_SEL_B
;
1935 I915_WRITE(trans_dp_ctl
, reg
);
1936 POSTING_READ(trans_dp_ctl
);
1939 /* enable PCH transcoder */
1940 temp
= I915_READ(transconf_reg
);
1942 * make the BPC in transcoder be consistent with
1943 * that in pipeconf reg.
1945 temp
&= ~PIPE_BPC_MASK
;
1947 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
1948 I915_READ(transconf_reg
);
1950 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
1955 intel_crtc_load_lut(crtc
);
1958 case DRM_MODE_DPMS_OFF
:
1959 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe
);
1961 drm_vblank_off(dev
, pipe
);
1962 /* Disable display plane */
1963 temp
= I915_READ(dspcntr_reg
);
1964 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1965 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1966 /* Flush the plane changes */
1967 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1968 I915_READ(dspbase_reg
);
1971 i915_disable_vga(dev
);
1973 /* disable cpu pipe, disable after all planes disabled */
1974 temp
= I915_READ(pipeconf_reg
);
1975 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1976 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1977 I915_READ(pipeconf_reg
);
1979 /* wait for cpu pipe off, pipe state */
1980 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
1986 DRM_DEBUG_KMS("pipe %d off delay\n",
1992 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
1997 temp
= I915_READ(pf_ctl_reg
);
1998 if ((temp
& PF_ENABLE
) != 0) {
1999 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
2000 I915_READ(pf_ctl_reg
);
2002 I915_WRITE(pf_win_size
, 0);
2003 POSTING_READ(pf_win_size
);
2006 /* disable CPU FDI tx and PCH FDI rx */
2007 temp
= I915_READ(fdi_tx_reg
);
2008 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
2009 I915_READ(fdi_tx_reg
);
2011 temp
= I915_READ(fdi_rx_reg
);
2012 /* BPC in FDI rx is consistent with that in pipeconf */
2013 temp
&= ~(0x07 << 16);
2014 temp
|= (pipe_bpc
<< 11);
2015 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
2016 I915_READ(fdi_rx_reg
);
2020 /* still set train pattern 1 */
2021 temp
= I915_READ(fdi_tx_reg
);
2022 temp
&= ~FDI_LINK_TRAIN_NONE
;
2023 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2024 I915_WRITE(fdi_tx_reg
, temp
);
2025 POSTING_READ(fdi_tx_reg
);
2027 temp
= I915_READ(fdi_rx_reg
);
2028 if (HAS_PCH_CPT(dev
)) {
2029 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2030 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2032 temp
&= ~FDI_LINK_TRAIN_NONE
;
2033 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2035 I915_WRITE(fdi_rx_reg
, temp
);
2036 POSTING_READ(fdi_rx_reg
);
2040 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2041 temp
= I915_READ(PCH_LVDS
);
2042 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2043 I915_READ(PCH_LVDS
);
2047 /* disable PCH transcoder */
2048 temp
= I915_READ(transconf_reg
);
2049 if ((temp
& TRANS_ENABLE
) != 0) {
2050 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
2051 I915_READ(transconf_reg
);
2053 /* wait for PCH transcoder off, transcoder state */
2054 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
2060 DRM_DEBUG_KMS("transcoder %d off "
2067 temp
= I915_READ(transconf_reg
);
2068 /* BPC in transcoder is consistent with that in pipeconf */
2069 temp
&= ~PIPE_BPC_MASK
;
2071 I915_WRITE(transconf_reg
, temp
);
2072 I915_READ(transconf_reg
);
2075 if (HAS_PCH_CPT(dev
)) {
2076 /* disable TRANS_DP_CTL */
2077 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2080 reg
= I915_READ(trans_dp_ctl
);
2081 reg
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2082 I915_WRITE(trans_dp_ctl
, reg
);
2083 POSTING_READ(trans_dp_ctl
);
2085 /* disable DPLL_SEL */
2086 temp
= I915_READ(PCH_DPLL_SEL
);
2087 if (trans_dpll_sel
== 0)
2088 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2090 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2091 I915_WRITE(PCH_DPLL_SEL
, temp
);
2092 I915_READ(PCH_DPLL_SEL
);
2096 /* disable PCH DPLL */
2097 temp
= I915_READ(pch_dpll_reg
);
2098 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2099 I915_READ(pch_dpll_reg
);
2102 ironlake_disable_pll_edp(crtc
);
2105 /* Switch from PCDclk to Rawclk */
2106 temp
= I915_READ(fdi_rx_reg
);
2107 temp
&= ~FDI_SEL_PCDCLK
;
2108 I915_WRITE(fdi_rx_reg
, temp
);
2109 I915_READ(fdi_rx_reg
);
2111 /* Disable CPU FDI TX PLL */
2112 temp
= I915_READ(fdi_tx_reg
);
2113 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2114 I915_READ(fdi_tx_reg
);
2117 temp
= I915_READ(fdi_rx_reg
);
2118 temp
&= ~FDI_RX_PLL_ENABLE
;
2119 I915_WRITE(fdi_rx_reg
, temp
);
2120 I915_READ(fdi_rx_reg
);
2122 /* Wait for the clocks to turn off. */
2128 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2130 struct intel_overlay
*overlay
;
2133 if (!enable
&& intel_crtc
->overlay
) {
2134 overlay
= intel_crtc
->overlay
;
2135 mutex_lock(&overlay
->dev
->struct_mutex
);
2137 ret
= intel_overlay_switch_off(overlay
);
2141 ret
= intel_overlay_recover_from_interrupt(overlay
, 0);
2143 /* overlay doesn't react anymore. Usually
2144 * results in a black screen and an unkillable
2147 overlay
->hw_wedged
= HW_WEDGED
;
2151 mutex_unlock(&overlay
->dev
->struct_mutex
);
2153 /* Let userspace switch the overlay on again. In most cases userspace
2154 * has to recompute where to put it anyway. */
2159 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2161 struct drm_device
*dev
= crtc
->dev
;
2162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2164 int pipe
= intel_crtc
->pipe
;
2165 int plane
= intel_crtc
->plane
;
2166 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2167 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2168 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2169 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2172 /* XXX: When our outputs are all unaware of DPMS modes other than off
2173 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2176 case DRM_MODE_DPMS_ON
:
2177 case DRM_MODE_DPMS_STANDBY
:
2178 case DRM_MODE_DPMS_SUSPEND
:
2179 intel_update_watermarks(dev
);
2181 /* Enable the DPLL */
2182 temp
= I915_READ(dpll_reg
);
2183 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2184 I915_WRITE(dpll_reg
, temp
);
2185 I915_READ(dpll_reg
);
2186 /* Wait for the clocks to stabilize. */
2188 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2189 I915_READ(dpll_reg
);
2190 /* Wait for the clocks to stabilize. */
2192 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2193 I915_READ(dpll_reg
);
2194 /* Wait for the clocks to stabilize. */
2198 /* Enable the pipe */
2199 temp
= I915_READ(pipeconf_reg
);
2200 if ((temp
& PIPEACONF_ENABLE
) == 0)
2201 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
2203 /* Enable the plane */
2204 temp
= I915_READ(dspcntr_reg
);
2205 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2206 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
2207 /* Flush the plane changes */
2208 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2211 intel_crtc_load_lut(crtc
);
2213 if ((IS_I965G(dev
) || plane
== 0))
2214 intel_update_fbc(crtc
, &crtc
->mode
);
2216 /* Give the overlay scaler a chance to enable if it's on this pipe */
2217 intel_crtc_dpms_overlay(intel_crtc
, true);
2219 case DRM_MODE_DPMS_OFF
:
2220 intel_update_watermarks(dev
);
2222 /* Give the overlay scaler a chance to disable if it's on this pipe */
2223 intel_crtc_dpms_overlay(intel_crtc
, false);
2224 drm_vblank_off(dev
, pipe
);
2226 if (dev_priv
->cfb_plane
== plane
&&
2227 dev_priv
->display
.disable_fbc
)
2228 dev_priv
->display
.disable_fbc(dev
);
2230 /* Disable the VGA plane that we never use */
2231 i915_disable_vga(dev
);
2233 /* Disable display plane */
2234 temp
= I915_READ(dspcntr_reg
);
2235 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2236 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2237 /* Flush the plane changes */
2238 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2239 I915_READ(dspbase_reg
);
2242 if (!IS_I9XX(dev
)) {
2243 /* Wait for vblank for the disable to take effect */
2244 intel_wait_for_vblank(dev
);
2247 /* Next, disable display pipes */
2248 temp
= I915_READ(pipeconf_reg
);
2249 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2250 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2251 I915_READ(pipeconf_reg
);
2254 /* Wait for vblank for the disable to take effect. */
2255 intel_wait_for_vblank(dev
);
2257 temp
= I915_READ(dpll_reg
);
2258 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
2259 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2260 I915_READ(dpll_reg
);
2263 /* Wait for the clocks to turn off. */
2270 * Sets the power management mode of the pipe and plane.
2272 * This code should probably grow support for turning the cursor off and back
2273 * on appropriately at the same time as we're turning the pipe off/on.
2275 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2277 struct drm_device
*dev
= crtc
->dev
;
2278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2279 struct drm_i915_master_private
*master_priv
;
2280 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2281 int pipe
= intel_crtc
->pipe
;
2284 dev_priv
->display
.dpms(crtc
, mode
);
2286 intel_crtc
->dpms_mode
= mode
;
2288 if (!dev
->primary
->master
)
2291 master_priv
= dev
->primary
->master
->driver_priv
;
2292 if (!master_priv
->sarea_priv
)
2295 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2299 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2300 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2303 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2304 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2307 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2312 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
2314 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2315 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2318 static void intel_crtc_commit (struct drm_crtc
*crtc
)
2320 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2321 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2324 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2326 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2327 /* lvds has its own version of prepare see intel_lvds_prepare */
2328 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2331 void intel_encoder_commit (struct drm_encoder
*encoder
)
2333 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2334 /* lvds has its own version of commit see intel_lvds_commit */
2335 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2338 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2339 struct drm_display_mode
*mode
,
2340 struct drm_display_mode
*adjusted_mode
)
2342 struct drm_device
*dev
= crtc
->dev
;
2343 if (HAS_PCH_SPLIT(dev
)) {
2344 /* FDI link clock is fixed at 2.7G */
2345 if (mode
->clock
* 3 > 27000 * 4)
2346 return MODE_CLOCK_HIGH
;
2351 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2356 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2361 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2366 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2370 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2372 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2375 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2376 case GC_DISPLAY_CLOCK_333_MHZ
:
2379 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2385 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2390 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2393 /* Assume that the hardware is in the high speed state. This
2394 * should be the default.
2396 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2397 case GC_CLOCK_133_200
:
2398 case GC_CLOCK_100_200
:
2400 case GC_CLOCK_166_250
:
2402 case GC_CLOCK_100_133
:
2406 /* Shouldn't happen */
2410 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2416 * Return the pipe currently connected to the panel fitter,
2417 * or -1 if the panel fitter is not present or not in use
2419 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2424 /* i830 doesn't have a panel fitter */
2428 pfit_control
= I915_READ(PFIT_CONTROL
);
2430 /* See if the panel fitter is in use */
2431 if ((pfit_control
& PFIT_ENABLE
) == 0)
2434 /* 965 can place panel fitter on either pipe */
2436 return (pfit_control
>> 29) & 0x3;
2438 /* older chips can only use pipe 1 */
2451 fdi_reduce_ratio(u32
*num
, u32
*den
)
2453 while (*num
> 0xffffff || *den
> 0xffffff) {
2459 #define DATA_N 0x800000
2460 #define LINK_N 0x80000
2463 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2464 int link_clock
, struct fdi_m_n
*m_n
)
2468 m_n
->tu
= 64; /* default size */
2470 temp
= (u64
) DATA_N
* pixel_clock
;
2471 temp
= div_u64(temp
, link_clock
);
2472 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2473 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2474 m_n
->gmch_n
= DATA_N
;
2475 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2477 temp
= (u64
) LINK_N
* pixel_clock
;
2478 m_n
->link_m
= div_u64(temp
, link_clock
);
2479 m_n
->link_n
= LINK_N
;
2480 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2484 struct intel_watermark_params
{
2485 unsigned long fifo_size
;
2486 unsigned long max_wm
;
2487 unsigned long default_wm
;
2488 unsigned long guard_size
;
2489 unsigned long cacheline_size
;
2492 /* Pineview has different values for various configs */
2493 static struct intel_watermark_params pineview_display_wm
= {
2494 PINEVIEW_DISPLAY_FIFO
,
2498 PINEVIEW_FIFO_LINE_SIZE
2500 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2501 PINEVIEW_DISPLAY_FIFO
,
2503 PINEVIEW_DFT_HPLLOFF_WM
,
2505 PINEVIEW_FIFO_LINE_SIZE
2507 static struct intel_watermark_params pineview_cursor_wm
= {
2508 PINEVIEW_CURSOR_FIFO
,
2509 PINEVIEW_CURSOR_MAX_WM
,
2510 PINEVIEW_CURSOR_DFT_WM
,
2511 PINEVIEW_CURSOR_GUARD_WM
,
2512 PINEVIEW_FIFO_LINE_SIZE
,
2514 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2515 PINEVIEW_CURSOR_FIFO
,
2516 PINEVIEW_CURSOR_MAX_WM
,
2517 PINEVIEW_CURSOR_DFT_WM
,
2518 PINEVIEW_CURSOR_GUARD_WM
,
2519 PINEVIEW_FIFO_LINE_SIZE
2521 static struct intel_watermark_params g4x_wm_info
= {
2528 static struct intel_watermark_params i945_wm_info
= {
2535 static struct intel_watermark_params i915_wm_info
= {
2542 static struct intel_watermark_params i855_wm_info
= {
2549 static struct intel_watermark_params i830_wm_info
= {
2557 static struct intel_watermark_params ironlake_display_wm_info
= {
2565 static struct intel_watermark_params ironlake_display_srwm_info
= {
2566 ILK_DISPLAY_SR_FIFO
,
2567 ILK_DISPLAY_MAX_SRWM
,
2568 ILK_DISPLAY_DFT_SRWM
,
2573 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2575 ILK_CURSOR_MAX_SRWM
,
2576 ILK_CURSOR_DFT_SRWM
,
2582 * intel_calculate_wm - calculate watermark level
2583 * @clock_in_khz: pixel clock
2584 * @wm: chip FIFO params
2585 * @pixel_size: display pixel size
2586 * @latency_ns: memory latency for the platform
2588 * Calculate the watermark level (the level at which the display plane will
2589 * start fetching from memory again). Each chip has a different display
2590 * FIFO size and allocation, so the caller needs to figure that out and pass
2591 * in the correct intel_watermark_params structure.
2593 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2594 * on the pixel size. When it reaches the watermark level, it'll start
2595 * fetching FIFO line sized based chunks from memory until the FIFO fills
2596 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2597 * will occur, and a display engine hang could result.
2599 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2600 struct intel_watermark_params
*wm
,
2602 unsigned long latency_ns
)
2604 long entries_required
, wm_size
;
2607 * Note: we need to make sure we don't overflow for various clock &
2609 * clocks go from a few thousand to several hundred thousand.
2610 * latency is usually a few thousand
2612 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2614 entries_required
/= wm
->cacheline_size
;
2616 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2618 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2620 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2622 /* Don't promote wm_size to unsigned... */
2623 if (wm_size
> (long)wm
->max_wm
)
2624 wm_size
= wm
->max_wm
;
2626 wm_size
= wm
->default_wm
;
2630 struct cxsr_latency
{
2632 unsigned long fsb_freq
;
2633 unsigned long mem_freq
;
2634 unsigned long display_sr
;
2635 unsigned long display_hpll_disable
;
2636 unsigned long cursor_sr
;
2637 unsigned long cursor_hpll_disable
;
2640 static struct cxsr_latency cxsr_latency_table
[] = {
2641 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2642 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2643 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2645 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2646 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2647 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2649 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2650 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2651 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2653 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2654 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2655 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2657 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2658 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2659 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2661 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2662 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2663 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2666 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int fsb
,
2670 struct cxsr_latency
*latency
;
2672 if (fsb
== 0 || mem
== 0)
2675 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2676 latency
= &cxsr_latency_table
[i
];
2677 if (is_desktop
== latency
->is_desktop
&&
2678 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2682 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2687 static void pineview_disable_cxsr(struct drm_device
*dev
)
2689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2692 /* deactivate cxsr */
2693 reg
= I915_READ(DSPFW3
);
2694 reg
&= ~(PINEVIEW_SELF_REFRESH_EN
);
2695 I915_WRITE(DSPFW3
, reg
);
2696 DRM_INFO("Big FIFO is disabled\n");
2700 * Latency for FIFO fetches is dependent on several factors:
2701 * - memory configuration (speed, channels)
2703 * - current MCH state
2704 * It can be fairly high in some situations, so here we assume a fairly
2705 * pessimal value. It's a tradeoff between extra memory fetches (if we
2706 * set this value too high, the FIFO will fetch frequently to stay full)
2707 * and power consumption (set it too low to save power and we might see
2708 * FIFO underruns and display "flicker").
2710 * A value of 5us seems to be a good balance; safe for very low end
2711 * platforms but not overly aggressive on lower latency configs.
2713 static const int latency_ns
= 5000;
2715 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2718 uint32_t dsparb
= I915_READ(DSPARB
);
2722 size
= dsparb
& 0x7f;
2724 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) -
2727 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2728 plane
? "B" : "A", size
);
2733 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2736 uint32_t dsparb
= I915_READ(DSPARB
);
2740 size
= dsparb
& 0x1ff;
2742 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) -
2744 size
>>= 1; /* Convert to cachelines */
2746 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2747 plane
? "B" : "A", size
);
2752 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2755 uint32_t dsparb
= I915_READ(DSPARB
);
2758 size
= dsparb
& 0x7f;
2759 size
>>= 2; /* Convert to cachelines */
2761 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2768 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
2770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2771 uint32_t dsparb
= I915_READ(DSPARB
);
2774 size
= dsparb
& 0x7f;
2775 size
>>= 1; /* Convert to cachelines */
2777 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2778 plane
? "B" : "A", size
);
2783 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
2784 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2789 struct cxsr_latency
*latency
;
2792 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->fsb_freq
,
2793 dev_priv
->mem_freq
);
2795 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2796 pineview_disable_cxsr(dev
);
2800 if (!planea_clock
|| !planeb_clock
) {
2801 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2804 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
2805 pixel_size
, latency
->display_sr
);
2806 reg
= I915_READ(DSPFW1
);
2807 reg
&= ~DSPFW_SR_MASK
;
2808 reg
|= wm
<< DSPFW_SR_SHIFT
;
2809 I915_WRITE(DSPFW1
, reg
);
2810 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
2813 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
2814 pixel_size
, latency
->cursor_sr
);
2815 reg
= I915_READ(DSPFW3
);
2816 reg
&= ~DSPFW_CURSOR_SR_MASK
;
2817 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
2818 I915_WRITE(DSPFW3
, reg
);
2820 /* Display HPLL off SR */
2821 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
2822 pixel_size
, latency
->display_hpll_disable
);
2823 reg
= I915_READ(DSPFW3
);
2824 reg
&= ~DSPFW_HPLL_SR_MASK
;
2825 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
2826 I915_WRITE(DSPFW3
, reg
);
2828 /* cursor HPLL off SR */
2829 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
2830 pixel_size
, latency
->cursor_hpll_disable
);
2831 reg
= I915_READ(DSPFW3
);
2832 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
2833 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
2834 I915_WRITE(DSPFW3
, reg
);
2835 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
2838 reg
= I915_READ(DSPFW3
);
2839 reg
|= PINEVIEW_SELF_REFRESH_EN
;
2840 I915_WRITE(DSPFW3
, reg
);
2841 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2843 pineview_disable_cxsr(dev
);
2844 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2848 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
2849 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2852 int total_size
, cacheline_size
;
2853 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
2854 struct intel_watermark_params planea_params
, planeb_params
;
2855 unsigned long line_time_us
;
2856 int sr_clock
, sr_entries
= 0, entries_required
;
2858 /* Create copies of the base settings for each pipe */
2859 planea_params
= planeb_params
= g4x_wm_info
;
2861 /* Grab a couple of global values before we overwrite them */
2862 total_size
= planea_params
.fifo_size
;
2863 cacheline_size
= planea_params
.cacheline_size
;
2866 * Note: we need to make sure we don't overflow for various clock &
2868 * clocks go from a few thousand to several hundred thousand.
2869 * latency is usually a few thousand
2871 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
2873 entries_required
/= G4X_FIFO_LINE_SIZE
;
2874 planea_wm
= entries_required
+ planea_params
.guard_size
;
2876 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
2878 entries_required
/= G4X_FIFO_LINE_SIZE
;
2879 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
2881 cursora_wm
= cursorb_wm
= 16;
2884 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2886 /* Calc sr entries for one plane configs */
2887 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2888 /* self-refresh has much higher latency */
2889 static const int sr_latency_ns
= 12000;
2891 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2892 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2894 /* Use ns/us then divide to preserve precision */
2895 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2896 pixel_size
* sr_hdisplay
) / 1000;
2897 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2898 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2899 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2901 /* Turn off self refresh if both pipes are enabled */
2902 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2906 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2907 planea_wm
, planeb_wm
, sr_entries
);
2912 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
2913 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
2914 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
2915 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
2916 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
2917 /* HPLL off in SR has some issues on G4x... disable it */
2918 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
2919 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
2922 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
2923 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2926 unsigned long line_time_us
;
2927 int sr_clock
, sr_entries
, srwm
= 1;
2929 /* Calc sr entries for one plane configs */
2930 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2931 /* self-refresh has much higher latency */
2932 static const int sr_latency_ns
= 12000;
2934 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2935 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2937 /* Use ns/us then divide to preserve precision */
2938 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2939 pixel_size
* sr_hdisplay
) / 1000;
2940 sr_entries
= roundup(sr_entries
/ I915_FIFO_LINE_SIZE
, 1);
2941 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2942 srwm
= I945_FIFO_SIZE
- sr_entries
;
2946 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
2948 /* Turn off self refresh if both pipes are enabled */
2949 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
2953 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2956 /* 965 has limitations... */
2957 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
2959 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
2962 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
2963 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2968 int total_size
, cacheline_size
, cwm
, srwm
= 1;
2969 int planea_wm
, planeb_wm
;
2970 struct intel_watermark_params planea_params
, planeb_params
;
2971 unsigned long line_time_us
;
2972 int sr_clock
, sr_entries
= 0;
2974 /* Create copies of the base settings for each pipe */
2975 if (IS_I965GM(dev
) || IS_I945GM(dev
))
2976 planea_params
= planeb_params
= i945_wm_info
;
2977 else if (IS_I9XX(dev
))
2978 planea_params
= planeb_params
= i915_wm_info
;
2980 planea_params
= planeb_params
= i855_wm_info
;
2982 /* Grab a couple of global values before we overwrite them */
2983 total_size
= planea_params
.fifo_size
;
2984 cacheline_size
= planea_params
.cacheline_size
;
2986 /* Update per-plane FIFO sizes */
2987 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
2988 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
2990 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
2991 pixel_size
, latency_ns
);
2992 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
2993 pixel_size
, latency_ns
);
2994 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2997 * Overlay gets an aggressive default since video jitter is bad.
3001 /* Calc sr entries for one plane configs */
3002 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3003 (!planea_clock
|| !planeb_clock
)) {
3004 /* self-refresh has much higher latency */
3005 static const int sr_latency_ns
= 6000;
3007 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3008 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
3010 /* Use ns/us then divide to preserve precision */
3011 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
3012 pixel_size
* sr_hdisplay
) / 1000;
3013 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
3014 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3015 srwm
= total_size
- sr_entries
;
3019 if (IS_I945G(dev
) || IS_I945GM(dev
))
3020 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3021 else if (IS_I915GM(dev
)) {
3022 /* 915M has a smaller SRWM field */
3023 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3024 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3027 /* Turn off self refresh if both pipes are enabled */
3028 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3029 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3031 } else if (IS_I915GM(dev
)) {
3032 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3036 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3037 planea_wm
, planeb_wm
, cwm
, srwm
);
3039 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3040 fwater_hi
= (cwm
& 0x1f);
3042 /* Set request length to 8 cachelines per fetch */
3043 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3044 fwater_hi
= fwater_hi
| (1 << 8);
3046 I915_WRITE(FW_BLC
, fwater_lo
);
3047 I915_WRITE(FW_BLC2
, fwater_hi
);
3050 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3051 int unused2
, int pixel_size
)
3053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3054 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3057 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3059 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3060 pixel_size
, latency_ns
);
3061 fwater_lo
|= (3<<8) | planea_wm
;
3063 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3065 I915_WRITE(FW_BLC
, fwater_lo
);
3068 #define ILK_LP0_PLANE_LATENCY 700
3070 static void ironlake_update_wm(struct drm_device
*dev
, int planea_clock
,
3071 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
3073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3074 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3075 int sr_wm
, cursor_wm
;
3076 unsigned long line_time_us
;
3077 int sr_clock
, entries_required
;
3080 /* Calculate and update the watermark for plane A */
3082 entries_required
= ((planea_clock
/ 1000) * pixel_size
*
3083 ILK_LP0_PLANE_LATENCY
) / 1000;
3084 entries_required
= DIV_ROUND_UP(entries_required
,
3085 ironlake_display_wm_info
.cacheline_size
);
3086 planea_wm
= entries_required
+
3087 ironlake_display_wm_info
.guard_size
;
3089 if (planea_wm
> (int)ironlake_display_wm_info
.max_wm
)
3090 planea_wm
= ironlake_display_wm_info
.max_wm
;
3093 reg_value
= I915_READ(WM0_PIPEA_ILK
);
3094 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3095 reg_value
|= (planea_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3096 (cursora_wm
& WM0_PIPE_CURSOR_MASK
);
3097 I915_WRITE(WM0_PIPEA_ILK
, reg_value
);
3098 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3099 "cursor: %d\n", planea_wm
, cursora_wm
);
3101 /* Calculate and update the watermark for plane B */
3103 entries_required
= ((planeb_clock
/ 1000) * pixel_size
*
3104 ILK_LP0_PLANE_LATENCY
) / 1000;
3105 entries_required
= DIV_ROUND_UP(entries_required
,
3106 ironlake_display_wm_info
.cacheline_size
);
3107 planeb_wm
= entries_required
+
3108 ironlake_display_wm_info
.guard_size
;
3110 if (planeb_wm
> (int)ironlake_display_wm_info
.max_wm
)
3111 planeb_wm
= ironlake_display_wm_info
.max_wm
;
3114 reg_value
= I915_READ(WM0_PIPEB_ILK
);
3115 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3116 reg_value
|= (planeb_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3117 (cursorb_wm
& WM0_PIPE_CURSOR_MASK
);
3118 I915_WRITE(WM0_PIPEB_ILK
, reg_value
);
3119 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3120 "cursor: %d\n", planeb_wm
, cursorb_wm
);
3124 * Calculate and update the self-refresh watermark only when one
3125 * display plane is used.
3127 if (!planea_clock
|| !planeb_clock
) {
3129 /* Read the self-refresh latency. The unit is 0.5us */
3130 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3132 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3133 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
3135 /* Use ns/us then divide to preserve precision */
3136 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3139 /* calculate the self-refresh watermark for display plane */
3140 entries_required
= line_count
* sr_hdisplay
* pixel_size
;
3141 entries_required
= DIV_ROUND_UP(entries_required
,
3142 ironlake_display_srwm_info
.cacheline_size
);
3143 sr_wm
= entries_required
+
3144 ironlake_display_srwm_info
.guard_size
;
3146 /* calculate the self-refresh watermark for display cursor */
3147 entries_required
= line_count
* pixel_size
* 64;
3148 entries_required
= DIV_ROUND_UP(entries_required
,
3149 ironlake_cursor_srwm_info
.cacheline_size
);
3150 cursor_wm
= entries_required
+
3151 ironlake_cursor_srwm_info
.guard_size
;
3153 /* configure watermark and enable self-refresh */
3154 reg_value
= I915_READ(WM1_LP_ILK
);
3155 reg_value
&= ~(WM1_LP_LATENCY_MASK
| WM1_LP_SR_MASK
|
3156 WM1_LP_CURSOR_MASK
);
3157 reg_value
|= WM1_LP_SR_EN
|
3158 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3159 (sr_wm
<< WM1_LP_SR_SHIFT
) | cursor_wm
;
3161 I915_WRITE(WM1_LP_ILK
, reg_value
);
3162 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3163 "cursor %d\n", sr_wm
, cursor_wm
);
3166 /* Turn off self refresh if both pipes are enabled */
3167 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
3171 * intel_update_watermarks - update FIFO watermark values based on current modes
3173 * Calculate watermark values for the various WM regs based on current mode
3174 * and plane configuration.
3176 * There are several cases to deal with here:
3177 * - normal (i.e. non-self-refresh)
3178 * - self-refresh (SR) mode
3179 * - lines are large relative to FIFO size (buffer can hold up to 2)
3180 * - lines are small relative to FIFO size (buffer can hold more than 2
3181 * lines), so need to account for TLB latency
3183 * The normal calculation is:
3184 * watermark = dotclock * bytes per pixel * latency
3185 * where latency is platform & configuration dependent (we assume pessimal
3188 * The SR calculation is:
3189 * watermark = (trunc(latency/line time)+1) * surface width *
3192 * line time = htotal / dotclock
3193 * and latency is assumed to be high, as above.
3195 * The final value programmed to the register should always be rounded up,
3196 * and include an extra 2 entries to account for clock crossings.
3198 * We don't use the sprite, so we can ignore that. And on Crestline we have
3199 * to set the non-SR watermarks to 8.
3201 static void intel_update_watermarks(struct drm_device
*dev
)
3203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3204 struct drm_crtc
*crtc
;
3205 struct intel_crtc
*intel_crtc
;
3206 int sr_hdisplay
= 0;
3207 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3208 int enabled
= 0, pixel_size
= 0;
3210 if (!dev_priv
->display
.update_wm
)
3213 /* Get the clock config from both planes */
3214 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3215 intel_crtc
= to_intel_crtc(crtc
);
3216 if (crtc
->enabled
) {
3218 if (intel_crtc
->plane
== 0) {
3219 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3220 intel_crtc
->pipe
, crtc
->mode
.clock
);
3221 planea_clock
= crtc
->mode
.clock
;
3223 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3224 intel_crtc
->pipe
, crtc
->mode
.clock
);
3225 planeb_clock
= crtc
->mode
.clock
;
3227 sr_hdisplay
= crtc
->mode
.hdisplay
;
3228 sr_clock
= crtc
->mode
.clock
;
3230 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3232 pixel_size
= 4; /* by default */
3239 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3240 sr_hdisplay
, pixel_size
);
3243 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3244 struct drm_display_mode
*mode
,
3245 struct drm_display_mode
*adjusted_mode
,
3247 struct drm_framebuffer
*old_fb
)
3249 struct drm_device
*dev
= crtc
->dev
;
3250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3251 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3252 int pipe
= intel_crtc
->pipe
;
3253 int plane
= intel_crtc
->plane
;
3254 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
3255 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3256 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
3257 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
3258 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
3259 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
3260 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
3261 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
3262 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
3263 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
3264 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
3265 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
3266 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
3267 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
3268 int refclk
, num_connectors
= 0;
3269 intel_clock_t clock
, reduced_clock
;
3270 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3271 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3272 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3273 bool is_edp
= false;
3274 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3275 struct drm_encoder
*encoder
;
3276 struct intel_encoder
*intel_encoder
= NULL
;
3277 const intel_limit_t
*limit
;
3279 struct fdi_m_n m_n
= {0};
3280 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
3281 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
3282 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
3283 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
3284 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
3285 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
3286 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
3287 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
3288 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
3289 int lvds_reg
= LVDS
;
3291 int sdvo_pixel_multiply
;
3294 drm_vblank_pre_modeset(dev
, pipe
);
3296 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
3298 if (!encoder
|| encoder
->crtc
!= crtc
)
3301 intel_encoder
= enc_to_intel_encoder(encoder
);
3303 switch (intel_encoder
->type
) {
3304 case INTEL_OUTPUT_LVDS
:
3307 case INTEL_OUTPUT_SDVO
:
3308 case INTEL_OUTPUT_HDMI
:
3310 if (intel_encoder
->needs_tv_clock
)
3313 case INTEL_OUTPUT_DVO
:
3316 case INTEL_OUTPUT_TVOUT
:
3319 case INTEL_OUTPUT_ANALOG
:
3322 case INTEL_OUTPUT_DISPLAYPORT
:
3325 case INTEL_OUTPUT_EDP
:
3333 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3334 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3335 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3337 } else if (IS_I9XX(dev
)) {
3339 if (HAS_PCH_SPLIT(dev
))
3340 refclk
= 120000; /* 120Mhz refclk */
3347 * Returns a set of divisors for the desired target clock with the given
3348 * refclk, or FALSE. The returned values represent the clock equation:
3349 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3351 limit
= intel_limit(crtc
);
3352 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3354 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3355 drm_vblank_post_modeset(dev
, pipe
);
3359 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3360 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3361 dev_priv
->lvds_downclock
,
3364 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3366 * If the different P is found, it means that we can't
3367 * switch the display clock by using the FP0/FP1.
3368 * In such case we will disable the LVDS downclock
3371 DRM_DEBUG_KMS("Different P is found for "
3372 "LVDS clock/downclock\n");
3373 has_reduced_clock
= 0;
3376 /* SDVO TV has fixed PLL values depend on its clock range,
3377 this mirrors vbios setting. */
3378 if (is_sdvo
&& is_tv
) {
3379 if (adjusted_mode
->clock
>= 100000
3380 && adjusted_mode
->clock
< 140500) {
3386 } else if (adjusted_mode
->clock
>= 140500
3387 && adjusted_mode
->clock
<= 200000) {
3397 if (HAS_PCH_SPLIT(dev
)) {
3398 int lane
= 0, link_bw
, bpp
;
3399 /* eDP doesn't require FDI link, so just set DP M/N
3400 according to current link config */
3402 target_clock
= mode
->clock
;
3403 intel_edp_link_config(intel_encoder
,
3406 /* DP over FDI requires target mode clock
3407 instead of link clock */
3409 target_clock
= mode
->clock
;
3411 target_clock
= adjusted_mode
->clock
;
3415 /* determine panel color depth */
3416 temp
= I915_READ(pipeconf_reg
);
3417 temp
&= ~PIPE_BPC_MASK
;
3419 int lvds_reg
= I915_READ(PCH_LVDS
);
3420 /* the BPC will be 6 if it is 18-bit LVDS panel */
3421 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3425 } else if (is_edp
) {
3426 switch (dev_priv
->edp_bpp
/3) {
3442 I915_WRITE(pipeconf_reg
, temp
);
3443 I915_READ(pipeconf_reg
);
3445 switch (temp
& PIPE_BPC_MASK
) {
3459 DRM_ERROR("unknown pipe bpc value\n");
3465 * Account for spread spectrum to avoid
3466 * oversubscribing the link. Max center spread
3467 * is 2.5%; use 5% for safety's sake.
3469 u32 bps
= target_clock
* bpp
* 21 / 20;
3470 lane
= bps
/ (link_bw
* 8) + 1;
3473 intel_crtc
->fdi_lanes
= lane
;
3475 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3478 /* Ironlake: try to setup display ref clock before DPLL
3479 * enabling. This is only under driver's control after
3480 * PCH B stepping, previous chipset stepping should be
3481 * ignoring this setting.
3483 if (HAS_PCH_SPLIT(dev
)) {
3484 temp
= I915_READ(PCH_DREF_CONTROL
);
3485 /* Always enable nonspread source */
3486 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3487 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3488 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3489 POSTING_READ(PCH_DREF_CONTROL
);
3491 temp
&= ~DREF_SSC_SOURCE_MASK
;
3492 temp
|= DREF_SSC_SOURCE_ENABLE
;
3493 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3494 POSTING_READ(PCH_DREF_CONTROL
);
3499 if (dev_priv
->lvds_use_ssc
) {
3500 temp
|= DREF_SSC1_ENABLE
;
3501 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3502 POSTING_READ(PCH_DREF_CONTROL
);
3506 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3507 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3508 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3509 POSTING_READ(PCH_DREF_CONTROL
);
3511 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3512 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3513 POSTING_READ(PCH_DREF_CONTROL
);
3518 if (IS_PINEVIEW(dev
)) {
3519 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3520 if (has_reduced_clock
)
3521 fp2
= (1 << reduced_clock
.n
) << 16 |
3522 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3524 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3525 if (has_reduced_clock
)
3526 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3530 if (!HAS_PCH_SPLIT(dev
))
3531 dpll
= DPLL_VGA_MODE_DIS
;
3535 dpll
|= DPLLB_MODE_LVDS
;
3537 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3539 dpll
|= DPLL_DVO_HIGH_SPEED
;
3540 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3541 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3542 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3543 else if (HAS_PCH_SPLIT(dev
))
3544 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3547 dpll
|= DPLL_DVO_HIGH_SPEED
;
3549 /* compute bitmask from p1 value */
3550 if (IS_PINEVIEW(dev
))
3551 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3553 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3555 if (HAS_PCH_SPLIT(dev
))
3556 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3557 if (IS_G4X(dev
) && has_reduced_clock
)
3558 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3562 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3565 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3568 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3571 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3574 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
))
3575 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3578 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3581 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3583 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3585 dpll
|= PLL_P2_DIVIDE_BY_4
;
3589 if (is_sdvo
&& is_tv
)
3590 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3592 /* XXX: just matching BIOS for now */
3593 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3595 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3596 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3598 dpll
|= PLL_REF_INPUT_DREFCLK
;
3600 /* setup pipeconf */
3601 pipeconf
= I915_READ(pipeconf_reg
);
3603 /* Set up the display plane register */
3604 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3606 /* Ironlake's plane is forced to pipe, bit 24 is to
3607 enable color space conversion */
3608 if (!HAS_PCH_SPLIT(dev
)) {
3610 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3612 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3615 if (pipe
== 0 && !IS_I965G(dev
)) {
3616 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3619 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3623 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3624 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3626 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3629 /* Disable the panel fitter if it was on our pipe */
3630 if (!HAS_PCH_SPLIT(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3631 I915_WRITE(PFIT_CONTROL
, 0);
3633 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3634 drm_mode_debug_printmodeline(mode
);
3636 /* assign to Ironlake registers */
3637 if (HAS_PCH_SPLIT(dev
)) {
3638 fp_reg
= pch_fp_reg
;
3639 dpll_reg
= pch_dpll_reg
;
3643 ironlake_disable_pll_edp(crtc
);
3644 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
3645 I915_WRITE(fp_reg
, fp
);
3646 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3647 I915_READ(dpll_reg
);
3651 /* enable transcoder DPLL */
3652 if (HAS_PCH_CPT(dev
)) {
3653 temp
= I915_READ(PCH_DPLL_SEL
);
3654 if (trans_dpll_sel
== 0)
3655 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
3657 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3658 I915_WRITE(PCH_DPLL_SEL
, temp
);
3659 I915_READ(PCH_DPLL_SEL
);
3663 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3664 * This is an exception to the general rule that mode_set doesn't turn
3670 if (HAS_PCH_SPLIT(dev
))
3671 lvds_reg
= PCH_LVDS
;
3673 lvds
= I915_READ(lvds_reg
);
3674 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3676 if (HAS_PCH_CPT(dev
))
3677 lvds
|= PORT_TRANS_B_SEL_CPT
;
3679 lvds
|= LVDS_PIPEB_SELECT
;
3681 if (HAS_PCH_CPT(dev
))
3682 lvds
&= ~PORT_TRANS_SEL_MASK
;
3684 lvds
&= ~LVDS_PIPEB_SELECT
;
3686 /* set the corresponsding LVDS_BORDER bit */
3687 lvds
|= dev_priv
->lvds_border_bits
;
3688 /* Set the B0-B3 data pairs corresponding to whether we're going to
3689 * set the DPLLs for dual-channel mode or not.
3692 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3694 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3696 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3697 * appropriately here, but we need to look more thoroughly into how
3698 * panels behave in the two modes.
3700 /* set the dithering flag */
3701 if (IS_I965G(dev
)) {
3702 if (dev_priv
->lvds_dither
) {
3703 if (HAS_PCH_SPLIT(dev
)) {
3704 pipeconf
|= PIPE_ENABLE_DITHER
;
3705 pipeconf
|= PIPE_DITHER_TYPE_ST01
;
3707 lvds
|= LVDS_ENABLE_DITHER
;
3709 if (HAS_PCH_SPLIT(dev
)) {
3710 pipeconf
&= ~PIPE_ENABLE_DITHER
;
3711 pipeconf
&= ~PIPE_DITHER_TYPE_MASK
;
3713 lvds
&= ~LVDS_ENABLE_DITHER
;
3716 I915_WRITE(lvds_reg
, lvds
);
3717 I915_READ(lvds_reg
);
3720 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3721 else if (HAS_PCH_SPLIT(dev
)) {
3722 /* For non-DP output, clear any trans DP clock recovery setting.*/
3724 I915_WRITE(TRANSA_DATA_M1
, 0);
3725 I915_WRITE(TRANSA_DATA_N1
, 0);
3726 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
3727 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
3729 I915_WRITE(TRANSB_DATA_M1
, 0);
3730 I915_WRITE(TRANSB_DATA_N1
, 0);
3731 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
3732 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
3737 I915_WRITE(fp_reg
, fp
);
3738 I915_WRITE(dpll_reg
, dpll
);
3739 I915_READ(dpll_reg
);
3740 /* Wait for the clocks to stabilize. */
3743 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
)) {
3745 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3746 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
3747 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
3749 I915_WRITE(dpll_md_reg
, 0);
3751 /* write it again -- the BIOS does, after all */
3752 I915_WRITE(dpll_reg
, dpll
);
3754 I915_READ(dpll_reg
);
3755 /* Wait for the clocks to stabilize. */
3759 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
3760 I915_WRITE(fp_reg
+ 4, fp2
);
3761 intel_crtc
->lowfreq_avail
= true;
3762 if (HAS_PIPE_CXSR(dev
)) {
3763 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3764 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
3767 I915_WRITE(fp_reg
+ 4, fp
);
3768 intel_crtc
->lowfreq_avail
= false;
3769 if (HAS_PIPE_CXSR(dev
)) {
3770 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3771 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
3775 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
3776 ((adjusted_mode
->crtc_htotal
- 1) << 16));
3777 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
3778 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
3779 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
3780 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
3781 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
3782 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
3783 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
3784 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
3785 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
3786 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
3787 /* pipesrc and dspsize control the size that is scaled from, which should
3788 * always be the user's requested size.
3790 if (!HAS_PCH_SPLIT(dev
)) {
3791 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
3792 (mode
->hdisplay
- 1));
3793 I915_WRITE(dsppos_reg
, 0);
3795 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
3797 if (HAS_PCH_SPLIT(dev
)) {
3798 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
3799 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
3800 I915_WRITE(link_m1_reg
, m_n
.link_m
);
3801 I915_WRITE(link_n1_reg
, m_n
.link_n
);
3804 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
3806 /* enable FDI RX PLL too */
3807 temp
= I915_READ(fdi_rx_reg
);
3808 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
3809 I915_READ(fdi_rx_reg
);
3812 /* enable FDI TX PLL too */
3813 temp
= I915_READ(fdi_tx_reg
);
3814 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
3815 I915_READ(fdi_tx_reg
);
3817 /* enable FDI RX PCDCLK */
3818 temp
= I915_READ(fdi_rx_reg
);
3819 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
3820 I915_READ(fdi_rx_reg
);
3825 I915_WRITE(pipeconf_reg
, pipeconf
);
3826 I915_READ(pipeconf_reg
);
3828 intel_wait_for_vblank(dev
);
3830 if (IS_IRONLAKE(dev
)) {
3831 /* enable address swizzle for tiling buffer */
3832 temp
= I915_READ(DISP_ARB_CTL
);
3833 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
3836 I915_WRITE(dspcntr_reg
, dspcntr
);
3838 /* Flush the plane changes */
3839 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
3841 if ((IS_I965G(dev
) || plane
== 0))
3842 intel_update_fbc(crtc
, &crtc
->mode
);
3844 intel_update_watermarks(dev
);
3846 drm_vblank_post_modeset(dev
, pipe
);
3851 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3852 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3854 struct drm_device
*dev
= crtc
->dev
;
3855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3856 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3857 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
3860 /* The clocks have to be on to load the palette. */
3864 /* use legacy palette for Ironlake */
3865 if (HAS_PCH_SPLIT(dev
))
3866 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
3869 for (i
= 0; i
< 256; i
++) {
3870 I915_WRITE(palreg
+ 4 * i
,
3871 (intel_crtc
->lut_r
[i
] << 16) |
3872 (intel_crtc
->lut_g
[i
] << 8) |
3873 intel_crtc
->lut_b
[i
]);
3877 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
3878 struct drm_file
*file_priv
,
3880 uint32_t width
, uint32_t height
)
3882 struct drm_device
*dev
= crtc
->dev
;
3883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3884 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3885 struct drm_gem_object
*bo
;
3886 struct drm_i915_gem_object
*obj_priv
;
3887 int pipe
= intel_crtc
->pipe
;
3888 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
3889 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
3890 uint32_t temp
= I915_READ(control
);
3894 DRM_DEBUG_KMS("\n");
3896 /* if we want to turn off the cursor ignore width and height */
3898 DRM_DEBUG_KMS("cursor off\n");
3899 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3900 temp
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
3901 temp
|= CURSOR_MODE_DISABLE
;
3903 temp
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
3907 mutex_lock(&dev
->struct_mutex
);
3911 /* Currently we only support 64x64 cursors */
3912 if (width
!= 64 || height
!= 64) {
3913 DRM_ERROR("we currently only support 64x64 cursors\n");
3917 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
3921 obj_priv
= to_intel_bo(bo
);
3923 if (bo
->size
< width
* height
* 4) {
3924 DRM_ERROR("buffer is to small\n");
3929 /* we only need to pin inside GTT if cursor is non-phy */
3930 mutex_lock(&dev
->struct_mutex
);
3931 if (!dev_priv
->info
->cursor_needs_physical
) {
3932 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
3934 DRM_ERROR("failed to pin cursor bo\n");
3937 addr
= obj_priv
->gtt_offset
;
3939 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
3941 DRM_ERROR("failed to attach phys object\n");
3944 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
3948 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
3950 /* Hooray for CUR*CNTR differences */
3951 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
3952 temp
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
3953 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
3954 temp
|= (pipe
<< 28); /* Connect to correct pipe */
3956 temp
&= ~(CURSOR_FORMAT_MASK
);
3957 temp
|= CURSOR_ENABLE
;
3958 temp
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
3962 I915_WRITE(control
, temp
);
3963 I915_WRITE(base
, addr
);
3965 if (intel_crtc
->cursor_bo
) {
3966 if (dev_priv
->info
->cursor_needs_physical
) {
3967 if (intel_crtc
->cursor_bo
!= bo
)
3968 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
3970 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
3971 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
3974 mutex_unlock(&dev
->struct_mutex
);
3976 intel_crtc
->cursor_addr
= addr
;
3977 intel_crtc
->cursor_bo
= bo
;
3981 mutex_unlock(&dev
->struct_mutex
);
3983 drm_gem_object_unreference_unlocked(bo
);
3987 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
3989 struct drm_device
*dev
= crtc
->dev
;
3990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3991 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3992 struct intel_framebuffer
*intel_fb
;
3993 int pipe
= intel_crtc
->pipe
;
3998 intel_fb
= to_intel_framebuffer(crtc
->fb
);
3999 intel_mark_busy(dev
, intel_fb
->obj
);
4003 temp
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
4007 temp
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
4011 temp
|= x
<< CURSOR_X_SHIFT
;
4012 temp
|= y
<< CURSOR_Y_SHIFT
;
4014 adder
= intel_crtc
->cursor_addr
;
4015 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
4016 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
4021 /** Sets the color ramps on behalf of RandR */
4022 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
4023 u16 blue
, int regno
)
4025 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4027 intel_crtc
->lut_r
[regno
] = red
>> 8;
4028 intel_crtc
->lut_g
[regno
] = green
>> 8;
4029 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4032 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4033 u16
*blue
, int regno
)
4035 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4037 *red
= intel_crtc
->lut_r
[regno
] << 8;
4038 *green
= intel_crtc
->lut_g
[regno
] << 8;
4039 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4042 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4043 u16
*blue
, uint32_t size
)
4045 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4051 for (i
= 0; i
< 256; i
++) {
4052 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4053 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4054 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4057 intel_crtc_load_lut(crtc
);
4061 * Get a pipe with a simple mode set on it for doing load-based monitor
4064 * It will be up to the load-detect code to adjust the pipe as appropriate for
4065 * its requirements. The pipe will be connected to no other encoders.
4067 * Currently this code will only succeed if there is a pipe with no encoders
4068 * configured for it. In the future, it could choose to temporarily disable
4069 * some outputs to free up a pipe for its use.
4071 * \return crtc, or NULL if no pipes are available.
4074 /* VESA 640x480x72Hz mode to set on the pipe */
4075 static struct drm_display_mode load_detect_mode
= {
4076 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4077 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4080 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4081 struct drm_connector
*connector
,
4082 struct drm_display_mode
*mode
,
4085 struct intel_crtc
*intel_crtc
;
4086 struct drm_crtc
*possible_crtc
;
4087 struct drm_crtc
*supported_crtc
=NULL
;
4088 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4089 struct drm_crtc
*crtc
= NULL
;
4090 struct drm_device
*dev
= encoder
->dev
;
4091 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4092 struct drm_crtc_helper_funcs
*crtc_funcs
;
4096 * Algorithm gets a little messy:
4097 * - if the connector already has an assigned crtc, use it (but make
4098 * sure it's on first)
4099 * - try to find the first unused crtc that can drive this connector,
4100 * and use that if we find one
4101 * - if there are no unused crtcs available, try to use the first
4102 * one we found that supports the connector
4105 /* See if we already have a CRTC for this connector */
4106 if (encoder
->crtc
) {
4107 crtc
= encoder
->crtc
;
4108 /* Make sure the crtc and connector are running */
4109 intel_crtc
= to_intel_crtc(crtc
);
4110 *dpms_mode
= intel_crtc
->dpms_mode
;
4111 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4112 crtc_funcs
= crtc
->helper_private
;
4113 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4114 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4119 /* Find an unused one (if possible) */
4120 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4122 if (!(encoder
->possible_crtcs
& (1 << i
)))
4124 if (!possible_crtc
->enabled
) {
4125 crtc
= possible_crtc
;
4128 if (!supported_crtc
)
4129 supported_crtc
= possible_crtc
;
4133 * If we didn't find an unused CRTC, don't use any.
4139 encoder
->crtc
= crtc
;
4140 connector
->encoder
= encoder
;
4141 intel_encoder
->load_detect_temp
= true;
4143 intel_crtc
= to_intel_crtc(crtc
);
4144 *dpms_mode
= intel_crtc
->dpms_mode
;
4146 if (!crtc
->enabled
) {
4148 mode
= &load_detect_mode
;
4149 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4151 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4152 crtc_funcs
= crtc
->helper_private
;
4153 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4156 /* Add this connector to the crtc */
4157 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4158 encoder_funcs
->commit(encoder
);
4160 /* let the connector get through one full cycle before testing */
4161 intel_wait_for_vblank(dev
);
4166 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4167 struct drm_connector
*connector
, int dpms_mode
)
4169 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4170 struct drm_device
*dev
= encoder
->dev
;
4171 struct drm_crtc
*crtc
= encoder
->crtc
;
4172 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4173 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4175 if (intel_encoder
->load_detect_temp
) {
4176 encoder
->crtc
= NULL
;
4177 connector
->encoder
= NULL
;
4178 intel_encoder
->load_detect_temp
= false;
4179 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4180 drm_helper_disable_unused_functions(dev
);
4183 /* Switch crtc and encoder back off if necessary */
4184 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4185 if (encoder
->crtc
== crtc
)
4186 encoder_funcs
->dpms(encoder
, dpms_mode
);
4187 crtc_funcs
->dpms(crtc
, dpms_mode
);
4191 /* Returns the clock of the currently programmed mode of the given pipe. */
4192 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4196 int pipe
= intel_crtc
->pipe
;
4197 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4199 intel_clock_t clock
;
4201 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4202 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4204 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4206 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4207 if (IS_PINEVIEW(dev
)) {
4208 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4209 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4211 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4212 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4216 if (IS_PINEVIEW(dev
))
4217 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4218 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4220 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4221 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4223 switch (dpll
& DPLL_MODE_MASK
) {
4224 case DPLLB_MODE_DAC_SERIAL
:
4225 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4228 case DPLLB_MODE_LVDS
:
4229 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4233 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4234 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4238 /* XXX: Handle the 100Mhz refclk */
4239 intel_clock(dev
, 96000, &clock
);
4241 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4244 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4245 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4248 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4249 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4250 /* XXX: might not be 66MHz */
4251 intel_clock(dev
, 66000, &clock
);
4253 intel_clock(dev
, 48000, &clock
);
4255 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4258 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4259 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4261 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4266 intel_clock(dev
, 48000, &clock
);
4270 /* XXX: It would be nice to validate the clocks, but we can't reuse
4271 * i830PllIsValid() because it relies on the xf86_config connector
4272 * configuration being accurate, which it isn't necessarily.
4278 /** Returns the currently programmed mode of the given pipe. */
4279 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4280 struct drm_crtc
*crtc
)
4282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4283 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4284 int pipe
= intel_crtc
->pipe
;
4285 struct drm_display_mode
*mode
;
4286 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4287 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4288 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4289 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4291 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4295 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4296 mode
->hdisplay
= (htot
& 0xffff) + 1;
4297 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4298 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4299 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4300 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4301 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4302 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4303 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4305 drm_mode_set_name(mode
);
4306 drm_mode_set_crtcinfo(mode
, 0);
4311 #define GPU_IDLE_TIMEOUT 500 /* ms */
4313 /* When this timer fires, we've been idle for awhile */
4314 static void intel_gpu_idle_timer(unsigned long arg
)
4316 struct drm_device
*dev
= (struct drm_device
*)arg
;
4317 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4319 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4321 dev_priv
->busy
= false;
4323 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4326 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4328 static void intel_crtc_idle_timer(unsigned long arg
)
4330 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4331 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4332 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4334 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4336 intel_crtc
->busy
= false;
4338 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4341 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
4343 struct drm_device
*dev
= crtc
->dev
;
4344 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4346 int pipe
= intel_crtc
->pipe
;
4347 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4348 int dpll
= I915_READ(dpll_reg
);
4350 if (HAS_PCH_SPLIT(dev
))
4353 if (!dev_priv
->lvds_downclock_avail
)
4356 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4357 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4359 /* Unlock panel regs */
4360 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
4362 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4363 I915_WRITE(dpll_reg
, dpll
);
4364 dpll
= I915_READ(dpll_reg
);
4365 intel_wait_for_vblank(dev
);
4366 dpll
= I915_READ(dpll_reg
);
4367 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4368 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4370 /* ...and lock them again */
4371 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4374 /* Schedule downclock */
4376 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4377 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4380 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4382 struct drm_device
*dev
= crtc
->dev
;
4383 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4384 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4385 int pipe
= intel_crtc
->pipe
;
4386 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4387 int dpll
= I915_READ(dpll_reg
);
4389 if (HAS_PCH_SPLIT(dev
))
4392 if (!dev_priv
->lvds_downclock_avail
)
4396 * Since this is called by a timer, we should never get here in
4399 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4400 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4402 /* Unlock panel regs */
4403 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
4405 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4406 I915_WRITE(dpll_reg
, dpll
);
4407 dpll
= I915_READ(dpll_reg
);
4408 intel_wait_for_vblank(dev
);
4409 dpll
= I915_READ(dpll_reg
);
4410 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4411 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4413 /* ...and lock them again */
4414 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4420 * intel_idle_update - adjust clocks for idleness
4421 * @work: work struct
4423 * Either the GPU or display (or both) went idle. Check the busy status
4424 * here and adjust the CRTC and GPU clocks as necessary.
4426 static void intel_idle_update(struct work_struct
*work
)
4428 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4430 struct drm_device
*dev
= dev_priv
->dev
;
4431 struct drm_crtc
*crtc
;
4432 struct intel_crtc
*intel_crtc
;
4434 if (!i915_powersave
)
4437 mutex_lock(&dev
->struct_mutex
);
4439 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4440 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4441 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4444 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4445 /* Skip inactive CRTCs */
4449 intel_crtc
= to_intel_crtc(crtc
);
4450 if (!intel_crtc
->busy
)
4451 intel_decrease_pllclock(crtc
);
4454 mutex_unlock(&dev
->struct_mutex
);
4458 * intel_mark_busy - mark the GPU and possibly the display busy
4460 * @obj: object we're operating on
4462 * Callers can use this function to indicate that the GPU is busy processing
4463 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4464 * buffer), we'll also mark the display as busy, so we know to increase its
4467 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4469 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4470 struct drm_crtc
*crtc
= NULL
;
4471 struct intel_framebuffer
*intel_fb
;
4472 struct intel_crtc
*intel_crtc
;
4474 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4477 if (!dev_priv
->busy
) {
4478 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4481 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4482 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4483 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4484 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4486 dev_priv
->busy
= true;
4488 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4489 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4491 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4495 intel_crtc
= to_intel_crtc(crtc
);
4496 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4497 if (intel_fb
->obj
== obj
) {
4498 if (!intel_crtc
->busy
) {
4499 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4502 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4503 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4504 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4505 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4507 /* Non-busy -> busy, upclock */
4508 intel_increase_pllclock(crtc
, true);
4509 intel_crtc
->busy
= true;
4511 /* Busy -> busy, put off timer */
4512 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4513 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4519 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4521 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4523 drm_crtc_cleanup(crtc
);
4527 struct intel_unpin_work
{
4528 struct work_struct work
;
4529 struct drm_device
*dev
;
4530 struct drm_gem_object
*old_fb_obj
;
4531 struct drm_gem_object
*pending_flip_obj
;
4532 struct drm_pending_vblank_event
*event
;
4536 static void intel_unpin_work_fn(struct work_struct
*__work
)
4538 struct intel_unpin_work
*work
=
4539 container_of(__work
, struct intel_unpin_work
, work
);
4541 mutex_lock(&work
->dev
->struct_mutex
);
4542 i915_gem_object_unpin(work
->old_fb_obj
);
4543 drm_gem_object_unreference(work
->pending_flip_obj
);
4544 drm_gem_object_unreference(work
->old_fb_obj
);
4545 mutex_unlock(&work
->dev
->struct_mutex
);
4549 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
4551 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4552 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
4553 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4554 struct intel_unpin_work
*work
;
4555 struct drm_i915_gem_object
*obj_priv
;
4556 struct drm_pending_vblank_event
*e
;
4558 unsigned long flags
;
4560 /* Ignore early vblank irqs */
4561 if (intel_crtc
== NULL
)
4564 spin_lock_irqsave(&dev
->event_lock
, flags
);
4565 work
= intel_crtc
->unpin_work
;
4566 if (work
== NULL
|| !work
->pending
) {
4567 if (work
&& !work
->pending
) {
4568 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4569 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4571 atomic_read(&obj_priv
->pending_flip
));
4573 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4577 intel_crtc
->unpin_work
= NULL
;
4578 drm_vblank_put(dev
, intel_crtc
->pipe
);
4582 do_gettimeofday(&now
);
4583 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4584 e
->event
.tv_sec
= now
.tv_sec
;
4585 e
->event
.tv_usec
= now
.tv_usec
;
4586 list_add_tail(&e
->base
.link
,
4587 &e
->base
.file_priv
->event_list
);
4588 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4591 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4593 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4595 /* Initial scanout buffer will have a 0 pending flip count */
4596 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4597 atomic_dec_and_test(&obj_priv
->pending_flip
))
4598 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4599 schedule_work(&work
->work
);
4602 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
4604 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4605 struct intel_crtc
*intel_crtc
=
4606 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
4607 unsigned long flags
;
4609 spin_lock_irqsave(&dev
->event_lock
, flags
);
4610 if (intel_crtc
->unpin_work
) {
4611 intel_crtc
->unpin_work
->pending
= 1;
4613 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4615 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4618 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
4619 struct drm_framebuffer
*fb
,
4620 struct drm_pending_vblank_event
*event
)
4622 struct drm_device
*dev
= crtc
->dev
;
4623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4624 struct intel_framebuffer
*intel_fb
;
4625 struct drm_i915_gem_object
*obj_priv
;
4626 struct drm_gem_object
*obj
;
4627 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4628 struct intel_unpin_work
*work
;
4629 unsigned long flags
;
4630 int pipesrc_reg
= (intel_crtc
->pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
4634 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
4638 mutex_lock(&dev
->struct_mutex
);
4640 work
->event
= event
;
4641 work
->dev
= crtc
->dev
;
4642 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4643 work
->old_fb_obj
= intel_fb
->obj
;
4644 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
4646 /* We borrow the event spin lock for protecting unpin_work */
4647 spin_lock_irqsave(&dev
->event_lock
, flags
);
4648 if (intel_crtc
->unpin_work
) {
4649 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4650 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4652 mutex_unlock(&dev
->struct_mutex
);
4655 intel_crtc
->unpin_work
= work
;
4656 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4658 intel_fb
= to_intel_framebuffer(fb
);
4659 obj
= intel_fb
->obj
;
4661 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
4663 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4666 intel_crtc
->unpin_work
= NULL
;
4667 mutex_unlock(&dev
->struct_mutex
);
4671 /* Reference the objects for the scheduled work. */
4672 drm_gem_object_reference(work
->old_fb_obj
);
4673 drm_gem_object_reference(obj
);
4676 i915_gem_object_flush_write_domain(obj
);
4677 drm_vblank_get(dev
, intel_crtc
->pipe
);
4678 obj_priv
= to_intel_bo(obj
);
4679 atomic_inc(&obj_priv
->pending_flip
);
4680 work
->pending_flip_obj
= obj
;
4683 OUT_RING(MI_DISPLAY_FLIP
|
4684 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
4685 OUT_RING(fb
->pitch
);
4686 if (IS_I965G(dev
)) {
4687 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
4688 pipesrc
= I915_READ(pipesrc_reg
);
4689 OUT_RING(pipesrc
& 0x0fff0fff);
4691 OUT_RING(obj_priv
->gtt_offset
);
4696 mutex_unlock(&dev
->struct_mutex
);
4701 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
4702 .dpms
= intel_crtc_dpms
,
4703 .mode_fixup
= intel_crtc_mode_fixup
,
4704 .mode_set
= intel_crtc_mode_set
,
4705 .mode_set_base
= intel_pipe_set_base
,
4706 .prepare
= intel_crtc_prepare
,
4707 .commit
= intel_crtc_commit
,
4708 .load_lut
= intel_crtc_load_lut
,
4711 static const struct drm_crtc_funcs intel_crtc_funcs
= {
4712 .cursor_set
= intel_crtc_cursor_set
,
4713 .cursor_move
= intel_crtc_cursor_move
,
4714 .gamma_set
= intel_crtc_gamma_set
,
4715 .set_config
= drm_crtc_helper_set_config
,
4716 .destroy
= intel_crtc_destroy
,
4717 .page_flip
= intel_crtc_page_flip
,
4721 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
4723 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4724 struct intel_crtc
*intel_crtc
;
4727 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
4728 if (intel_crtc
== NULL
)
4731 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
4733 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
4734 intel_crtc
->pipe
= pipe
;
4735 intel_crtc
->plane
= pipe
;
4736 for (i
= 0; i
< 256; i
++) {
4737 intel_crtc
->lut_r
[i
] = i
;
4738 intel_crtc
->lut_g
[i
] = i
;
4739 intel_crtc
->lut_b
[i
] = i
;
4742 /* Swap pipes & planes for FBC on pre-965 */
4743 intel_crtc
->pipe
= pipe
;
4744 intel_crtc
->plane
= pipe
;
4745 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
4746 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4747 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
4750 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
4751 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
4752 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
4753 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
4755 intel_crtc
->cursor_addr
= 0;
4756 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4757 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
4759 intel_crtc
->busy
= false;
4761 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
4762 (unsigned long)intel_crtc
);
4765 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
4766 struct drm_file
*file_priv
)
4768 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4769 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
4770 struct drm_mode_object
*drmmode_obj
;
4771 struct intel_crtc
*crtc
;
4774 DRM_ERROR("called with no initialization\n");
4778 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
4779 DRM_MODE_OBJECT_CRTC
);
4782 DRM_ERROR("no such CRTC id\n");
4786 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
4787 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
4792 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
4794 struct drm_crtc
*crtc
= NULL
;
4796 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4797 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4798 if (intel_crtc
->pipe
== pipe
)
4804 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
4807 struct drm_encoder
*encoder
;
4810 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4811 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
4812 if (type_mask
& intel_encoder
->clone_mask
)
4813 index_mask
|= (1 << entry
);
4820 static void intel_setup_outputs(struct drm_device
*dev
)
4822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4823 struct drm_encoder
*encoder
;
4825 intel_crt_init(dev
);
4827 /* Set up integrated LVDS */
4828 if (IS_MOBILE(dev
) && !IS_I830(dev
))
4829 intel_lvds_init(dev
);
4831 if (HAS_PCH_SPLIT(dev
)) {
4834 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
4835 intel_dp_init(dev
, DP_A
);
4837 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
4838 /* PCH SDVOB multiplex with HDMIB */
4839 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
4841 intel_hdmi_init(dev
, HDMIB
);
4842 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
4843 intel_dp_init(dev
, PCH_DP_B
);
4846 if (I915_READ(HDMIC
) & PORT_DETECTED
)
4847 intel_hdmi_init(dev
, HDMIC
);
4849 if (I915_READ(HDMID
) & PORT_DETECTED
)
4850 intel_hdmi_init(dev
, HDMID
);
4852 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
4853 intel_dp_init(dev
, PCH_DP_C
);
4855 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
4856 intel_dp_init(dev
, PCH_DP_D
);
4858 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
4861 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4862 DRM_DEBUG_KMS("probing SDVOB\n");
4863 found
= intel_sdvo_init(dev
, SDVOB
);
4864 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
4865 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4866 intel_hdmi_init(dev
, SDVOB
);
4869 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
4870 DRM_DEBUG_KMS("probing DP_B\n");
4871 intel_dp_init(dev
, DP_B
);
4875 /* Before G4X SDVOC doesn't have its own detect register */
4877 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
4878 DRM_DEBUG_KMS("probing SDVOC\n");
4879 found
= intel_sdvo_init(dev
, SDVOC
);
4882 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
4884 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
4885 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4886 intel_hdmi_init(dev
, SDVOC
);
4888 if (SUPPORTS_INTEGRATED_DP(dev
)) {
4889 DRM_DEBUG_KMS("probing DP_C\n");
4890 intel_dp_init(dev
, DP_C
);
4894 if (SUPPORTS_INTEGRATED_DP(dev
) &&
4895 (I915_READ(DP_D
) & DP_DETECTED
)) {
4896 DRM_DEBUG_KMS("probing DP_D\n");
4897 intel_dp_init(dev
, DP_D
);
4899 } else if (IS_GEN2(dev
))
4900 intel_dvo_init(dev
);
4902 if (SUPPORTS_TV(dev
))
4905 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4906 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
4908 encoder
->possible_crtcs
= intel_encoder
->crtc_mask
;
4909 encoder
->possible_clones
= intel_encoder_clones(dev
,
4910 intel_encoder
->clone_mask
);
4914 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
4916 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4918 drm_framebuffer_cleanup(fb
);
4919 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
4924 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
4925 struct drm_file
*file_priv
,
4926 unsigned int *handle
)
4928 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
4929 struct drm_gem_object
*object
= intel_fb
->obj
;
4931 return drm_gem_handle_create(file_priv
, object
, handle
);
4934 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
4935 .destroy
= intel_user_framebuffer_destroy
,
4936 .create_handle
= intel_user_framebuffer_create_handle
,
4939 int intel_framebuffer_init(struct drm_device
*dev
,
4940 struct intel_framebuffer
*intel_fb
,
4941 struct drm_mode_fb_cmd
*mode_cmd
,
4942 struct drm_gem_object
*obj
)
4946 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
4948 DRM_ERROR("framebuffer init failed %d\n", ret
);
4952 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
4953 intel_fb
->obj
= obj
;
4957 static struct drm_framebuffer
*
4958 intel_user_framebuffer_create(struct drm_device
*dev
,
4959 struct drm_file
*filp
,
4960 struct drm_mode_fb_cmd
*mode_cmd
)
4962 struct drm_gem_object
*obj
;
4963 struct intel_framebuffer
*intel_fb
;
4966 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
4970 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
4974 ret
= intel_framebuffer_init(dev
, intel_fb
,
4977 drm_gem_object_unreference_unlocked(obj
);
4982 return &intel_fb
->base
;
4985 static const struct drm_mode_config_funcs intel_mode_funcs
= {
4986 .fb_create
= intel_user_framebuffer_create
,
4987 .output_poll_changed
= intel_fb_output_poll_changed
,
4990 static struct drm_gem_object
*
4991 intel_alloc_power_context(struct drm_device
*dev
)
4993 struct drm_gem_object
*pwrctx
;
4996 pwrctx
= i915_gem_alloc_object(dev
, 4096);
4998 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5002 mutex_lock(&dev
->struct_mutex
);
5003 ret
= i915_gem_object_pin(pwrctx
, 4096);
5005 DRM_ERROR("failed to pin power context: %d\n", ret
);
5009 ret
= i915_gem_object_set_to_gtt_domain(pwrctx
, 1);
5011 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
5014 mutex_unlock(&dev
->struct_mutex
);
5019 i915_gem_object_unpin(pwrctx
);
5021 drm_gem_object_unreference(pwrctx
);
5022 mutex_unlock(&dev
->struct_mutex
);
5026 void ironlake_enable_drps(struct drm_device
*dev
)
5028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5029 u32 rgvmodectl
= I915_READ(MEMMODECTL
), rgvswctl
;
5030 u8 fmax
, fmin
, fstart
, vstart
;
5033 /* 100ms RC evaluation intervals */
5034 I915_WRITE(RCUPEI
, 100000);
5035 I915_WRITE(RCDNEI
, 100000);
5037 /* Set max/min thresholds to 90ms and 80ms respectively */
5038 I915_WRITE(RCBMAXAVG
, 90000);
5039 I915_WRITE(RCBMINAVG
, 80000);
5041 I915_WRITE(MEMIHYST
, 1);
5043 /* Set up min, max, and cur for interrupt handling */
5044 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5045 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5046 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5047 MEMMODE_FSTART_SHIFT
;
5048 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5051 dev_priv
->max_delay
= fstart
; /* can't go to fmax w/o IPS */
5052 dev_priv
->min_delay
= fmin
;
5053 dev_priv
->cur_delay
= fstart
;
5055 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5058 * Interrupts will be enabled in ironlake_irq_postinstall
5061 I915_WRITE(VIDSTART
, vstart
);
5062 POSTING_READ(VIDSTART
);
5064 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5065 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5067 while (I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) {
5069 DRM_ERROR("stuck trying to change perf mode\n");
5076 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5077 (fstart
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5078 I915_WRITE(MEMSWCTL
, rgvswctl
);
5079 POSTING_READ(MEMSWCTL
);
5081 rgvswctl
|= MEMCTL_CMD_STS
;
5082 I915_WRITE(MEMSWCTL
, rgvswctl
);
5085 void ironlake_disable_drps(struct drm_device
*dev
)
5087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5091 /* Ack interrupts, disable EFC interrupt */
5092 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5093 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5094 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5095 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5096 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5098 /* Go back to the starting frequency */
5099 fstart
= (I915_READ(MEMMODECTL
) & MEMMODE_FSTART_MASK
) >>
5100 MEMMODE_FSTART_SHIFT
;
5101 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5102 (fstart
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5103 I915_WRITE(MEMSWCTL
, rgvswctl
);
5105 rgvswctl
|= MEMCTL_CMD_STS
;
5106 I915_WRITE(MEMSWCTL
, rgvswctl
);
5111 void intel_init_clock_gating(struct drm_device
*dev
)
5113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5116 * Disable clock gating reported to work incorrectly according to the
5117 * specs, but enable as much else as we can.
5119 if (HAS_PCH_SPLIT(dev
)) {
5120 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5122 if (IS_IRONLAKE(dev
)) {
5123 /* Required for FBC */
5124 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5125 /* Required for CxSR */
5126 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5128 I915_WRITE(PCH_3DCGDIS0
,
5129 MARIUNIT_CLOCK_GATE_DISABLE
|
5130 SVSMUNIT_CLOCK_GATE_DISABLE
);
5133 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5136 * According to the spec the following bits should be set in
5137 * order to enable memory self-refresh
5138 * The bit 22/21 of 0x42004
5139 * The bit 5 of 0x42020
5140 * The bit 15 of 0x45000
5142 if (IS_IRONLAKE(dev
)) {
5143 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5144 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5145 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5146 I915_WRITE(ILK_DSPCLK_GATE
,
5147 (I915_READ(ILK_DSPCLK_GATE
) |
5148 ILK_DPARB_CLK_GATE
));
5149 I915_WRITE(DISP_ARB_CTL
,
5150 (I915_READ(DISP_ARB_CTL
) |
5154 } else if (IS_G4X(dev
)) {
5155 uint32_t dspclk_gate
;
5156 I915_WRITE(RENCLK_GATE_D1
, 0);
5157 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5158 GS_UNIT_CLOCK_GATE_DISABLE
|
5159 CL_UNIT_CLOCK_GATE_DISABLE
);
5160 I915_WRITE(RAMCLK_GATE_D
, 0);
5161 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5162 OVRUNIT_CLOCK_GATE_DISABLE
|
5163 OVCUNIT_CLOCK_GATE_DISABLE
;
5165 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5166 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5167 } else if (IS_I965GM(dev
)) {
5168 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5169 I915_WRITE(RENCLK_GATE_D2
, 0);
5170 I915_WRITE(DSPCLK_GATE_D
, 0);
5171 I915_WRITE(RAMCLK_GATE_D
, 0);
5172 I915_WRITE16(DEUC
, 0);
5173 } else if (IS_I965G(dev
)) {
5174 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5175 I965_RCC_CLOCK_GATE_DISABLE
|
5176 I965_RCPB_CLOCK_GATE_DISABLE
|
5177 I965_ISC_CLOCK_GATE_DISABLE
|
5178 I965_FBC_CLOCK_GATE_DISABLE
);
5179 I915_WRITE(RENCLK_GATE_D2
, 0);
5180 } else if (IS_I9XX(dev
)) {
5181 u32 dstate
= I915_READ(D_STATE
);
5183 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5184 DSTATE_DOT_CLOCK_GATING
;
5185 I915_WRITE(D_STATE
, dstate
);
5186 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5187 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5188 } else if (IS_I830(dev
)) {
5189 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5193 * GPU can automatically power down the render unit if given a page
5196 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5197 struct drm_i915_gem_object
*obj_priv
= NULL
;
5199 if (dev_priv
->pwrctx
) {
5200 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5202 struct drm_gem_object
*pwrctx
;
5204 pwrctx
= intel_alloc_power_context(dev
);
5206 dev_priv
->pwrctx
= pwrctx
;
5207 obj_priv
= to_intel_bo(pwrctx
);
5212 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5213 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5214 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5219 /* Set up chip specific display functions */
5220 static void intel_init_display(struct drm_device
*dev
)
5222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5224 /* We always want a DPMS function */
5225 if (HAS_PCH_SPLIT(dev
))
5226 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5228 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5230 if (I915_HAS_FBC(dev
)) {
5232 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5233 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5234 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5235 } else if (IS_I965GM(dev
)) {
5236 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5237 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5238 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5240 /* 855GM needs testing */
5243 /* Returns the core display clock speed */
5244 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5245 dev_priv
->display
.get_display_clock_speed
=
5246 i945_get_display_clock_speed
;
5247 else if (IS_I915G(dev
))
5248 dev_priv
->display
.get_display_clock_speed
=
5249 i915_get_display_clock_speed
;
5250 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5251 dev_priv
->display
.get_display_clock_speed
=
5252 i9xx_misc_get_display_clock_speed
;
5253 else if (IS_I915GM(dev
))
5254 dev_priv
->display
.get_display_clock_speed
=
5255 i915gm_get_display_clock_speed
;
5256 else if (IS_I865G(dev
))
5257 dev_priv
->display
.get_display_clock_speed
=
5258 i865_get_display_clock_speed
;
5259 else if (IS_I85X(dev
))
5260 dev_priv
->display
.get_display_clock_speed
=
5261 i855_get_display_clock_speed
;
5263 dev_priv
->display
.get_display_clock_speed
=
5264 i830_get_display_clock_speed
;
5266 /* For FIFO watermark updates */
5267 if (HAS_PCH_SPLIT(dev
)) {
5268 if (IS_IRONLAKE(dev
)) {
5269 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5270 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5272 DRM_DEBUG_KMS("Failed to get proper latency. "
5274 dev_priv
->display
.update_wm
= NULL
;
5277 dev_priv
->display
.update_wm
= NULL
;
5278 } else if (IS_PINEVIEW(dev
)) {
5279 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5281 dev_priv
->mem_freq
)) {
5282 DRM_INFO("failed to find known CxSR latency "
5283 "(found fsb freq %d, mem freq %d), "
5285 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5286 /* Disable CxSR and never update its watermark again */
5287 pineview_disable_cxsr(dev
);
5288 dev_priv
->display
.update_wm
= NULL
;
5290 dev_priv
->display
.update_wm
= pineview_update_wm
;
5291 } else if (IS_G4X(dev
))
5292 dev_priv
->display
.update_wm
= g4x_update_wm
;
5293 else if (IS_I965G(dev
))
5294 dev_priv
->display
.update_wm
= i965_update_wm
;
5295 else if (IS_I9XX(dev
)) {
5296 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5297 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5298 } else if (IS_I85X(dev
)) {
5299 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5300 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5302 dev_priv
->display
.update_wm
= i830_update_wm
;
5304 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5306 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5310 void intel_modeset_init(struct drm_device
*dev
)
5312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5316 drm_mode_config_init(dev
);
5318 dev
->mode_config
.min_width
= 0;
5319 dev
->mode_config
.min_height
= 0;
5321 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
5323 intel_init_display(dev
);
5325 if (IS_I965G(dev
)) {
5326 dev
->mode_config
.max_width
= 8192;
5327 dev
->mode_config
.max_height
= 8192;
5328 } else if (IS_I9XX(dev
)) {
5329 dev
->mode_config
.max_width
= 4096;
5330 dev
->mode_config
.max_height
= 4096;
5332 dev
->mode_config
.max_width
= 2048;
5333 dev
->mode_config
.max_height
= 2048;
5336 /* set memory base */
5338 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
5340 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
5342 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
5346 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5347 num_pipe
, num_pipe
> 1 ? "s" : "");
5349 for (i
= 0; i
< num_pipe
; i
++) {
5350 intel_crtc_init(dev
, i
);
5353 intel_setup_outputs(dev
);
5355 intel_init_clock_gating(dev
);
5357 if (IS_IRONLAKE_M(dev
))
5358 ironlake_enable_drps(dev
);
5360 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
5361 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
5362 (unsigned long)dev
);
5364 intel_setup_overlay(dev
);
5367 void intel_modeset_cleanup(struct drm_device
*dev
)
5369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5370 struct drm_crtc
*crtc
;
5371 struct intel_crtc
*intel_crtc
;
5373 mutex_lock(&dev
->struct_mutex
);
5375 drm_kms_helper_poll_fini(dev
);
5376 intel_fbdev_fini(dev
);
5378 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5379 /* Skip inactive CRTCs */
5383 intel_crtc
= to_intel_crtc(crtc
);
5384 intel_increase_pllclock(crtc
, false);
5385 del_timer_sync(&intel_crtc
->idle_timer
);
5388 del_timer_sync(&dev_priv
->idle_timer
);
5390 if (dev_priv
->display
.disable_fbc
)
5391 dev_priv
->display
.disable_fbc(dev
);
5393 if (dev_priv
->pwrctx
) {
5394 struct drm_i915_gem_object
*obj_priv
;
5396 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5397 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
5399 i915_gem_object_unpin(dev_priv
->pwrctx
);
5400 drm_gem_object_unreference(dev_priv
->pwrctx
);
5403 if (IS_IRONLAKE_M(dev
))
5404 ironlake_disable_drps(dev
);
5406 mutex_unlock(&dev
->struct_mutex
);
5408 drm_mode_config_cleanup(dev
);
5413 * Return which encoder is currently attached for connector.
5415 struct drm_encoder
*intel_attached_encoder (struct drm_connector
*connector
)
5417 struct drm_mode_object
*obj
;
5418 struct drm_encoder
*encoder
;
5421 for (i
= 0; i
< DRM_CONNECTOR_MAX_ENCODER
; i
++) {
5422 if (connector
->encoder_ids
[i
] == 0)
5425 obj
= drm_mode_object_find(connector
->dev
,
5426 connector
->encoder_ids
[i
],
5427 DRM_MODE_OBJECT_ENCODER
);
5431 encoder
= obj_to_encoder(obj
);
5438 * set vga decode state - true == enable VGA decode
5440 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
5442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5445 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
5447 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
5449 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
5450 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);