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drm/i915: Cache current cdclk frequency in dev_priv
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_crtc *crtc,
90 struct drm_atomic_state *state);
91 static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
100 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
101 static void haswell_set_pipeconf(struct drm_crtc *crtc);
102 static void intel_set_pipe_csc(struct drm_crtc *crtc);
103 static void vlv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void chv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
109 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
111 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
113 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
115
116 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117 {
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122 }
123
124 typedef struct {
125 int min, max;
126 } intel_range_t;
127
128 typedef struct {
129 int dot_limit;
130 int p2_slow, p2_fast;
131 } intel_p2_t;
132
133 typedef struct intel_limit intel_limit_t;
134 struct intel_limit {
135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
137 };
138
139 int
140 intel_pch_rawclk(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147 }
148
149 static inline u32 /* units of 100MHz */
150 intel_fdi_link_freq(struct drm_device *dev)
151 {
152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
157 }
158
159 static const intel_limit_t intel_limits_i8xx_dac = {
160 .dot = { .min = 25000, .max = 350000 },
161 .vco = { .min = 908000, .max = 1512000 },
162 .n = { .min = 2, .max = 16 },
163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
170 };
171
172 static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
174 .vco = { .min = 908000, .max = 1512000 },
175 .n = { .min = 2, .max = 16 },
176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183 };
184
185 static const intel_limit_t intel_limits_i8xx_lvds = {
186 .dot = { .min = 25000, .max = 350000 },
187 .vco = { .min = 908000, .max = 1512000 },
188 .n = { .min = 2, .max = 16 },
189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
196 };
197
198 static const intel_limit_t intel_limits_i9xx_sdvo = {
199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
209 };
210
211 static const intel_limit_t intel_limits_i9xx_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
222 };
223
224
225 static const intel_limit_t intel_limits_g4x_sdvo = {
226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
237 },
238 };
239
240 static const intel_limit_t intel_limits_g4x_hdmi = {
241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
264 },
265 };
266
267 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
278 },
279 };
280
281 static const intel_limit_t intel_limits_pineview_sdvo = {
282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
284 /* Pineview's Ncounter is a ring counter */
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 /* Pineview only has one combined m divider, which we treat as m2. */
288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
294 };
295
296 static const intel_limit_t intel_limits_pineview_lvds = {
297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
307 };
308
309 /* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
314 static const intel_limit_t intel_limits_ironlake_dac = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
325 };
326
327 static const intel_limit_t intel_limits_ironlake_single_lvds = {
328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
338 };
339
340 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
351 };
352
353 /* LVDS 100mhz refclk limits. */
354 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
362 .p1 = { .min = 2, .max = 8 },
363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
365 };
366
367 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
375 .p1 = { .min = 2, .max = 6 },
376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
378 };
379
380 static const intel_limit_t intel_limits_vlv = {
381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
388 .vco = { .min = 4000000, .max = 6000000 },
389 .n = { .min = 1, .max = 7 },
390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
392 .p1 = { .min = 2, .max = 3 },
393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
394 };
395
396 static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
404 .vco = { .min = 4800000, .max = 6480000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410 };
411
412 static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422 };
423
424 static void vlv_clock(int refclk, intel_clock_t *clock)
425 {
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
432 }
433
434 /**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
437 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
438 {
439 struct drm_device *dev = crtc->base.dev;
440 struct intel_encoder *encoder;
441
442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
443 if (encoder->type == type)
444 return true;
445
446 return false;
447 }
448
449 /**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
455 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
457 {
458 struct drm_atomic_state *state = crtc_state->base.state;
459 struct drm_connector *connector;
460 struct drm_connector_state *connector_state;
461 struct intel_encoder *encoder;
462 int i, num_connectors = 0;
463
464 for_each_connector_in_state(state, connector, connector_state, i) {
465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
469
470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
472 return true;
473 }
474
475 WARN_ON(num_connectors == 0);
476
477 return false;
478 }
479
480 static const intel_limit_t *
481 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
482 {
483 struct drm_device *dev = crtc_state->base.crtc->dev;
484 const intel_limit_t *limit;
485
486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
487 if (intel_is_dual_link_lvds(dev)) {
488 if (refclk == 100000)
489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
498 } else
499 limit = &intel_limits_ironlake_dac;
500
501 return limit;
502 }
503
504 static const intel_limit_t *
505 intel_g4x_limit(struct intel_crtc_state *crtc_state)
506 {
507 struct drm_device *dev = crtc_state->base.crtc->dev;
508 const intel_limit_t *limit;
509
510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
511 if (intel_is_dual_link_lvds(dev))
512 limit = &intel_limits_g4x_dual_channel_lvds;
513 else
514 limit = &intel_limits_g4x_single_channel_lvds;
515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
517 limit = &intel_limits_g4x_hdmi;
518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
519 limit = &intel_limits_g4x_sdvo;
520 } else /* The option is for other outputs */
521 limit = &intel_limits_i9xx_sdvo;
522
523 return limit;
524 }
525
526 static const intel_limit_t *
527 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
528 {
529 struct drm_device *dev = crtc_state->base.crtc->dev;
530 const intel_limit_t *limit;
531
532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
535 limit = intel_ironlake_limit(crtc_state, refclk);
536 else if (IS_G4X(dev)) {
537 limit = intel_g4x_limit(crtc_state);
538 } else if (IS_PINEVIEW(dev)) {
539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
540 limit = &intel_limits_pineview_lvds;
541 else
542 limit = &intel_limits_pineview_sdvo;
543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
545 } else if (IS_VALLEYVIEW(dev)) {
546 limit = &intel_limits_vlv;
547 } else if (!IS_GEN2(dev)) {
548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
552 } else {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i8xx_lvds;
555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
556 limit = &intel_limits_i8xx_dvo;
557 else
558 limit = &intel_limits_i8xx_dac;
559 }
560 return limit;
561 }
562
563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
564 static void pineview_clock(int refclk, intel_clock_t *clock)
565 {
566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
572 }
573
574 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575 {
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577 }
578
579 static void i9xx_clock(int refclk, intel_clock_t *clock)
580 {
581 clock->m = i9xx_dpll_compute_m(clock);
582 clock->p = clock->p1 * clock->p2;
583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587 }
588
589 static void chv_clock(int refclk, intel_clock_t *clock)
590 {
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598 }
599
600 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
601 /**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
606 static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
609 {
610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
613 INTELPllInvalid("p1 out of range\n");
614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
615 INTELPllInvalid("m2 out of range\n");
616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
617 INTELPllInvalid("m1 out of range\n");
618
619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
636 INTELPllInvalid("dot out of range\n");
637
638 return true;
639 }
640
641 static bool
642 i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
646 {
647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
648 struct drm_device *dev = crtc->base.dev;
649 intel_clock_t clock;
650 int err = target;
651
652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
653 /*
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
657 */
658 if (intel_is_dual_link_lvds(dev))
659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
669 memset(best_clock, 0, sizeof(*best_clock));
670
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
675 if (clock.m2 >= clock.m1)
676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
681 int this_err;
682
683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702 }
703
704 static bool
705 pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
709 {
710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
711 struct drm_device *dev = crtc->base.dev;
712 intel_clock_t clock;
713 int err = target;
714
715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
716 /*
717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
720 */
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733
734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
742 int this_err;
743
744 pineview_clock(refclk, &clock);
745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
747 continue;
748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763 }
764
765 static bool
766 g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
770 {
771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
772 struct drm_device *dev = crtc->base.dev;
773 intel_clock_t clock;
774 int max_n;
775 bool found;
776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
778 found = false;
779
780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
781 if (intel_is_dual_link_lvds(dev))
782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 /* based on hardware requirement, prefere larger m1,m2 */
797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
805 i9xx_clock(refclk, &clock);
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 this_err = abs(clock.dot - target);
811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
821 return found;
822 }
823
824 /*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833 {
834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862 }
863
864 static bool
865 vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
869 {
870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
871 struct drm_device *dev = crtc->base.dev;
872 intel_clock_t clock;
873 unsigned int bestppm = 1000000;
874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
876 bool found = false;
877
878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
881
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
887 clock.p = clock.p1 * clock.p2;
888 /* based on hardware requirement, prefer bigger m1,m2 values */
889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
890 unsigned int ppm;
891
892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
896
897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
899 continue;
900
901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
906
907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
910 }
911 }
912 }
913 }
914
915 return found;
916 }
917
918 static bool
919 chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923 {
924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
925 struct drm_device *dev = crtc->base.dev;
926 unsigned int best_error_ppm;
927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
932 best_error_ppm = 1000000;
933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
946 unsigned int error_ppm;
947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
970 }
971 }
972
973 return found;
974 }
975
976 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978 {
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983 }
984
985 bool intel_crtc_active(struct drm_crtc *crtc)
986 {
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
992 * We can ditch the adjusted_mode.crtc_clock check as soon
993 * as Haswell has gained clock readout/fastboot support.
994 *
995 * We can ditch the crtc->primary->fb check as soon as we can
996 * properly reconstruct framebuffers.
997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
1001 */
1002 return intel_crtc->active && crtc->primary->state->fb &&
1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
1004 }
1005
1006 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008 {
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
1012 return intel_crtc->config->cpu_transcoder;
1013 }
1014
1015 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016 {
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032 }
1033
1034 /*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
1036 * @crtc: crtc whose pipe to wait for
1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
1048 *
1049 */
1050 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1051 {
1052 struct drm_device *dev = crtc->base.dev;
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1055 enum pipe pipe = crtc->pipe;
1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
1058 int reg = PIPECONF(cpu_transcoder);
1059
1060 /* Wait for the Pipe State to go off */
1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 } else {
1065 /* Wait for the display line to settle */
1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1067 WARN(1, "pipe_off wait timed out\n");
1068 }
1069 }
1070
1071 /*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080 {
1081 u32 bit;
1082
1083 if (HAS_PCH_IBX(dev_priv->dev)) {
1084 switch (port->port) {
1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
1098 switch (port->port) {
1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114 }
1115
1116 static const char *state_string(bool enabled)
1117 {
1118 return enabled ? "on" : "off";
1119 }
1120
1121 /* Only for pre-ILK configs */
1122 void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
1124 {
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
1132 I915_STATE_WARN(cur_state != state,
1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135 }
1136
1137 /* XXX: the dsi pll is shared between MIPI DSI ports */
1138 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139 {
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->sb_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->sb_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
1148 I915_STATE_WARN(cur_state != state,
1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
1155 struct intel_shared_dpll *
1156 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157 {
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
1160 if (crtc->config->shared_dpll < 0)
1161 return NULL;
1162
1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1164 }
1165
1166 /* For ILK+ */
1167 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
1170 {
1171 bool cur_state;
1172 struct intel_dpll_hw_state hw_state;
1173
1174 if (WARN (!pll,
1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
1176 return;
1177
1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1179 I915_STATE_WARN(cur_state != state,
1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
1182 }
1183
1184 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186 {
1187 int reg;
1188 u32 val;
1189 bool cur_state;
1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
1192
1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206 }
1207 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212 {
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
1220 I915_STATE_WARN(cur_state != state,
1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223 }
1224 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229 {
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1235 return;
1236
1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1238 if (HAS_DDI(dev_priv->dev))
1239 return;
1240
1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1244 }
1245
1246 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1256 I915_STATE_WARN(cur_state != state,
1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
1259 }
1260
1261 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
1263 {
1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
1268 bool locked = true;
1269
1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
1276 pp_reg = PCH_PP_CONTROL;
1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
1287 } else {
1288 pp_reg = PP_CONTROL;
1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1296 locked = false;
1297
1298 I915_STATE_WARN(panel_pipe == pipe && locked,
1299 "panel assertion failure, pipe %c regs locked\n",
1300 pipe_name(pipe));
1301 }
1302
1303 static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305 {
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
1309 if (IS_845G(dev) || IS_I865G(dev))
1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1311 else
1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1313
1314 I915_STATE_WARN(cur_state != state,
1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317 }
1318 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
1321 void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
1323 {
1324 int reg;
1325 u32 val;
1326 bool cur_state;
1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
1329
1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1333 state = true;
1334
1335 if (!intel_display_power_is_enabled(dev_priv,
1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
1344 I915_STATE_WARN(cur_state != state,
1345 "pipe %c assertion failure (expected %s, current %s)\n",
1346 pipe_name(pipe), state_string(state), state_string(cur_state));
1347 }
1348
1349 static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
1351 {
1352 int reg;
1353 u32 val;
1354 bool cur_state;
1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1359 I915_STATE_WARN(cur_state != state,
1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
1362 }
1363
1364 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
1367 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369 {
1370 struct drm_device *dev = dev_priv->dev;
1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
1382 return;
1383 }
1384
1385 /* Need to check both planes against the pipe */
1386 for_each_pipe(dev_priv, i) {
1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399 {
1400 struct drm_device *dev = dev_priv->dev;
1401 int reg, sprite;
1402 u32 val;
1403
1404 if (INTEL_INFO(dev)->gen >= 9) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 val = I915_READ(PLANE_CTL(pipe, sprite));
1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
1412 for_each_sprite(dev_priv, pipe, sprite) {
1413 reg = SPCNTR(pipe, sprite);
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SP_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 sprite_name(pipe, sprite), pipe_name(pipe));
1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
1421 val = I915_READ(reg);
1422 I915_STATE_WARN(val & SPRITE_ENABLE,
1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
1427 val = I915_READ(reg);
1428 I915_STATE_WARN(val & DVS_ENABLE,
1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1430 plane_name(pipe), pipe_name(pipe));
1431 }
1432 }
1433
1434 static void assert_vblank_disabled(struct drm_crtc *crtc)
1435 {
1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1437 drm_crtc_vblank_put(crtc);
1438 }
1439
1440 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1441 {
1442 u32 val;
1443 bool enabled;
1444
1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1446
1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1451 }
1452
1453 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
1455 {
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
1460 reg = PCH_TRANSCONF(pipe);
1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
1463 I915_STATE_WARN(enabled,
1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
1466 }
1467
1468 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
1470 {
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487 }
1488
1489 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491 {
1492 if ((val & SDVO_ENABLE) == 0)
1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1497 return false;
1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1501 } else {
1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1503 return false;
1504 }
1505 return true;
1506 }
1507
1508 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510 {
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522 }
1523
1524 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526 {
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537 }
1538
1539 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1540 enum pipe pipe, int reg, u32 port_sel)
1541 {
1542 u32 val = I915_READ(reg);
1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1545 reg, pipe_name(pipe));
1546
1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1548 && (val & DP_PIPEB_SELECT),
1549 "IBX PCH dp port still using transcoder B\n");
1550 }
1551
1552 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554 {
1555 u32 val = I915_READ(reg);
1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1558 reg, pipe_name(pipe));
1559
1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1561 && (val & SDVO_PIPE_B_SELECT),
1562 "IBX PCH hdmi port still using transcoder B\n");
1563 }
1564
1565 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567 {
1568 int reg;
1569 u32 val;
1570
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
1579 pipe_name(pipe));
1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1590 }
1591
1592 static void intel_init_dpio(struct drm_device *dev)
1593 {
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
1610 }
1611
1612 static void vlv_enable_pll(struct intel_crtc *crtc,
1613 const struct intel_crtc_state *pipe_config)
1614 {
1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
1619
1620 assert_pipe_disabled(dev_priv, crtc->pipe);
1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
1626 if (IS_MOBILE(dev_priv->dev))
1627 assert_panel_unlocked(dev_priv, crtc->pipe);
1628
1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1637 POSTING_READ(DPLL_MD(crtc->pipe));
1638
1639 /* We do this three times for luck */
1640 I915_WRITE(reg, dpll);
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 }
1650
1651 static void chv_enable_pll(struct intel_crtc *crtc,
1652 const struct intel_crtc_state *pipe_config)
1653 {
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->sb_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 mutex_unlock(&dev_priv->sb_lock);
1672
1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1680
1681 /* Check PLL is locked */
1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
1685 /* not sure when this should be written */
1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1687 POSTING_READ(DPLL_MD(pipe));
1688 }
1689
1690 static int intel_num_dvo_pipes(struct drm_device *dev)
1691 {
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1698
1699 return count;
1700 }
1701
1702 static void i9xx_enable_pll(struct intel_crtc *crtc)
1703 {
1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
1708
1709 assert_pipe_disabled(dev_priv, crtc->pipe);
1710
1711 /* No really, not for ILK+ */
1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1713
1714 /* PLL is protected by panel, make sure we can write it */
1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
1717
1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
1737 crtc->config->dpll_hw_state.dpll_md);
1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
1746
1747 /* We do this three times for luck */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg, dpll);
1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
1754 I915_WRITE(reg, dpll);
1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757 }
1758
1759 /**
1760 * i9xx_disable_pll - disable a PLL
1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1768 static void i9xx_disable_pll(struct intel_crtc *crtc)
1769 {
1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
1794 }
1795
1796 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797 {
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
1807 if (pipe == PIPE_B)
1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
1811
1812 }
1813
1814 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815 {
1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1817 u32 val;
1818
1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
1821
1822 /* Set PLL en = 0 */
1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
1828
1829 mutex_lock(&dev_priv->sb_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
1847 mutex_unlock(&dev_priv->sb_lock);
1848 }
1849
1850 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
1853 {
1854 u32 port_mask;
1855 int dpll_reg;
1856
1857 switch (dport->port) {
1858 case PORT_B:
1859 port_mask = DPLL_PORTB_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 break;
1862 case PORT_C:
1863 port_mask = DPLL_PORTC_READY_MASK;
1864 dpll_reg = DPLL(0);
1865 expected_mask <<= 4;
1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
1870 break;
1871 default:
1872 BUG();
1873 }
1874
1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1878 }
1879
1880 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881 {
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
1886 if (WARN_ON(pll == NULL))
1887 return;
1888
1889 WARN_ON(!pll->config.crtc_mask);
1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897 }
1898
1899 /**
1900 * intel_enable_shared_dpll - enable PCH PLL
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
1907 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1908 {
1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1912
1913 if (WARN_ON(pll == NULL))
1914 return;
1915
1916 if (WARN_ON(pll->config.crtc_mask == 0))
1917 return;
1918
1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920 pll->name, pll->active, pll->on,
1921 crtc->base.base.id);
1922
1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
1925 assert_shared_dpll_enabled(dev_priv, pll);
1926 return;
1927 }
1928 WARN_ON(pll->on);
1929
1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1933 pll->enable(dev_priv, pll);
1934 pll->on = true;
1935 }
1936
1937 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1938 {
1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1942
1943 /* PCH only available on ILK+ */
1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
1945 if (WARN_ON(pll == NULL))
1946 return;
1947
1948 if (WARN_ON(pll->config.crtc_mask == 0))
1949 return;
1950
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
1953 crtc->base.base.id);
1954
1955 if (WARN_ON(pll->active == 0)) {
1956 assert_shared_dpll_disabled(dev_priv, pll);
1957 return;
1958 }
1959
1960 assert_shared_dpll_enabled(dev_priv, pll);
1961 WARN_ON(!pll->on);
1962 if (--pll->active)
1963 return;
1964
1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966 pll->disable(dev_priv, pll);
1967 pll->on = false;
1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1970 }
1971
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
1974 {
1975 struct drm_device *dev = dev_priv->dev;
1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 uint32_t reg, val, pipeconf_val;
1979
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev));
1982
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv,
1985 intel_crtc_to_shared_dpll(intel_crtc));
1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
1998 }
1999
2000 reg = PCH_TRANSCONF(pipe);
2001 val = I915_READ(reg);
2002 pipeconf_val = I915_READ(PIPECONF(pipe));
2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
2011 }
2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2015 if (HAS_PCH_IBX(dev_priv->dev) &&
2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2026 }
2027
2028 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum transcoder cpu_transcoder)
2030 {
2031 u32 val, pipeconf_val;
2032
2033 /* PCH only available on ILK+ */
2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2035
2036 /* FDI must be feeding us bits for PCH ports */
2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2039
2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
2045 val = TRANS_ENABLE;
2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2047
2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
2050 val |= TRANS_INTERLACED;
2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2056 DRM_ERROR("Failed to enable PCH transcoder\n");
2057 }
2058
2059 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
2061 {
2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
2072 reg = PCH_TRANSCONF(pipe);
2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
2087 }
2088
2089 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2090 {
2091 u32 val;
2092
2093 val = I915_READ(LPT_TRANSCONF);
2094 val &= ~TRANS_ENABLE;
2095 I915_WRITE(LPT_TRANSCONF, val);
2096 /* wait for PCH transcoder off, transcoder state */
2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2098 DRM_ERROR("Failed to disable PCH transcoder\n");
2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2103 I915_WRITE(_TRANSA_CHICKEN2, val);
2104 }
2105
2106 /**
2107 * intel_enable_pipe - enable a pipe, asserting requirements
2108 * @crtc: crtc responsible for the pipe
2109 *
2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2112 */
2113 static void intel_enable_pipe(struct intel_crtc *crtc)
2114 {
2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
2120 enum pipe pch_transcoder;
2121 int reg;
2122 u32 val;
2123
2124 assert_planes_disabled(dev_priv, pipe);
2125 assert_cursor_disabled(dev_priv, pipe);
2126 assert_sprites_disabled(dev_priv, pipe);
2127
2128 if (HAS_PCH_LPT(dev_priv->dev))
2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
2143 else {
2144 if (crtc->config->has_pch_encoder) {
2145 /* if driving the PCH, we need FDI enabled */
2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
2152
2153 reg = PIPECONF(cpu_transcoder);
2154 val = I915_READ(reg);
2155 if (val & PIPECONF_ENABLE) {
2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2158 return;
2159 }
2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
2162 POSTING_READ(reg);
2163 }
2164
2165 /**
2166 * intel_disable_pipe - disable a pipe, asserting requirements
2167 * @crtc: crtc whose pipes is to be disabled
2168 *
2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
2175 static void intel_disable_pipe(struct intel_crtc *crtc)
2176 {
2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2179 enum pipe pipe = crtc->pipe;
2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
2188 assert_cursor_disabled(dev_priv, pipe);
2189 assert_sprites_disabled(dev_priv, pipe);
2190
2191 reg = PIPECONF(cpu_transcoder);
2192 val = I915_READ(reg);
2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
2200 if (crtc->config->double_wide)
2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
2211 }
2212
2213 /**
2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
2217 *
2218 * Enable @plane on @crtc, making sure that the pipe is running first.
2219 */
2220 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
2222 {
2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2229 to_intel_plane_state(plane->state)->visible = true;
2230
2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
2233 }
2234
2235 static bool need_vtd_wa(struct drm_device *dev)
2236 {
2237 #ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240 #endif
2241 return false;
2242 }
2243
2244 unsigned int
2245 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
2247 {
2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
2250
2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
2264 default:
2265 case 1:
2266 tile_height = 64;
2267 break;
2268 case 2:
2269 case 4:
2270 tile_height = 32;
2271 break;
2272 case 8:
2273 tile_height = 16;
2274 break;
2275 case 16:
2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
2287
2288 return tile_height;
2289 }
2290
2291 unsigned int
2292 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294 {
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
2297 }
2298
2299 static int
2300 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302 {
2303 struct intel_rotation_info *info = &view->rotation_info;
2304
2305 *view = i915_ggtt_view_normal;
2306
2307 if (!plane_state)
2308 return 0;
2309
2310 if (!intel_rotation_90_or_270(plane_state->rotation))
2311 return 0;
2312
2313 *view = i915_ggtt_view_rotated;
2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
2320 return 0;
2321 }
2322
2323 int
2324 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
2326 const struct drm_plane_state *plane_state,
2327 struct intel_engine_cs *pipelined)
2328 {
2329 struct drm_device *dev = fb->dev;
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2332 struct i915_ggtt_view view;
2333 u32 alignment;
2334 int ret;
2335
2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2343 alignment = 128 * 1024;
2344 else if (INTEL_INFO(dev)->gen >= 4)
2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
2348 break;
2349 case I915_FORMAT_MOD_X_TILED:
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
2356 break;
2357 case I915_FORMAT_MOD_Y_TILED:
2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
2364 default:
2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
2367 }
2368
2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
2390 dev_priv->mm.interruptible = false;
2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392 &view);
2393 if (ret)
2394 goto err_interruptible;
2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
2401 ret = i915_gem_object_get_fence(obj);
2402 if (ret)
2403 goto err_unpin;
2404
2405 i915_gem_object_pin_fence(obj);
2406
2407 dev_priv->mm.interruptible = true;
2408 intel_runtime_pm_put(dev_priv);
2409 return 0;
2410
2411 err_unpin:
2412 i915_gem_object_unpin_from_display_plane(obj, &view);
2413 err_interruptible:
2414 dev_priv->mm.interruptible = true;
2415 intel_runtime_pm_put(dev_priv);
2416 return ret;
2417 }
2418
2419 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
2421 {
2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2423 struct i915_ggtt_view view;
2424 int ret;
2425
2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
2431 i915_gem_object_unpin_fence(obj);
2432 i915_gem_object_unpin_from_display_plane(obj, &view);
2433 }
2434
2435 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
2437 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
2441 {
2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
2444
2445 tile_rows = *y / 8;
2446 *y %= 8;
2447
2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
2460 }
2461
2462 static int i9xx_format_to_fourcc(int format)
2463 {
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481 }
2482
2483 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484 {
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507 }
2508
2509 static bool
2510 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
2512 {
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2516 struct drm_framebuffer *fb = &plane_config->fb->base;
2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
2522
2523 if (plane_config->size == 0)
2524 return false;
2525
2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
2530 if (!obj)
2531 return false;
2532
2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
2535 obj->stride = fb->pitches[0];
2536
2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2543
2544 mutex_lock(&dev->struct_mutex);
2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2546 &mode_cmd, obj)) {
2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
2550 mutex_unlock(&dev->struct_mutex);
2551
2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2553 return true;
2554
2555 out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
2558 return false;
2559 }
2560
2561 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2562 static void
2563 update_state_fb(struct drm_plane *plane)
2564 {
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573 }
2574
2575 static void
2576 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
2578 {
2579 struct drm_device *dev = intel_crtc->base.dev;
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2583 struct drm_i915_gem_object *obj;
2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
2586
2587 if (!plane_config->fb)
2588 return;
2589
2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
2593 }
2594
2595 kfree(plane_config->fb);
2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
2601 for_each_crtc(dev, c) {
2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2607 if (!i->active)
2608 continue;
2609
2610 fb = c->primary->fb;
2611 if (!fb)
2612 continue;
2613
2614 obj = intel_fb_obj(fb);
2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
2618 }
2619 }
2620
2621 return;
2622
2623 valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2633 }
2634
2635 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
2638 {
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
2644 struct drm_i915_gem_object *obj;
2645 int plane = intel_crtc->plane;
2646 unsigned long linear_offset;
2647 u32 dspcntr;
2648 u32 reg = DSPCNTR(plane);
2649 int pixel_size;
2650
2651 if (!visible || !fb) {
2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
2669 dspcntr |= DISPLAY_PLANE_ENABLE;
2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
2681 I915_WRITE(DSPPOS(plane), 0);
2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2688 }
2689
2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
2694 case DRM_FORMAT_XRGB1555:
2695 dspcntr |= DISPPLANE_BGRX555;
2696 break;
2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
2710 dspcntr |= DISPPLANE_RGBX101010;
2711 break;
2712 default:
2713 BUG();
2714 }
2715
2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
2719
2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
2724
2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2728 pixel_size,
2729 fb->pitches[0]);
2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
2732 intel_crtc->dspaddr_offset = linear_offset;
2733 }
2734
2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2751 if (INTEL_INFO(dev)->gen >= 4) {
2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
2756 } else
2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2758 POSTING_READ(reg);
2759 }
2760
2761 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
2764 {
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
2770 struct drm_i915_gem_object *obj;
2771 int plane = intel_crtc->plane;
2772 unsigned long linear_offset;
2773 u32 dspcntr;
2774 u32 reg = DSPCNTR(plane);
2775 int pixel_size;
2776
2777 if (!visible || !fb) {
2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
2792 dspcntr |= DISPLAY_PLANE_ENABLE;
2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2796
2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
2803 break;
2804 case DRM_FORMAT_XRGB8888:
2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
2814 dspcntr |= DISPPLANE_RGBX101010;
2815 break;
2816 default:
2817 BUG();
2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
2822
2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2825
2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
2827 intel_crtc->dspaddr_offset =
2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2829 pixel_size,
2830 fb->pitches[0]);
2831 linear_offset -= intel_crtc->dspaddr_offset;
2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
2848
2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
2858 POSTING_READ(reg);
2859 }
2860
2861 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863 {
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893 }
2894
2895 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897 {
2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2901 view = &i915_ggtt_view_rotated;
2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904 }
2905
2906 /*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910 {
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933 }
2934
2935 u32 skl_plane_ctl_format(uint32_t pixel_format)
2936 {
2937 switch (pixel_format) {
2938 case DRM_FORMAT_C8:
2939 return PLANE_CTL_FORMAT_INDEXED;
2940 case DRM_FORMAT_RGB565:
2941 return PLANE_CTL_FORMAT_RGB_565;
2942 case DRM_FORMAT_XBGR8888:
2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2944 case DRM_FORMAT_XRGB8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888;
2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
2951 case DRM_FORMAT_ABGR8888:
2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2954 case DRM_FORMAT_ARGB8888:
2955 return PLANE_CTL_FORMAT_XRGB_8888 |
2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2957 case DRM_FORMAT_XRGB2101010:
2958 return PLANE_CTL_FORMAT_XRGB_2101010;
2959 case DRM_FORMAT_XBGR2101010:
2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2961 case DRM_FORMAT_YUYV:
2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2963 case DRM_FORMAT_YVYU:
2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2965 case DRM_FORMAT_UYVY:
2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2967 case DRM_FORMAT_VYUY:
2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2969 default:
2970 MISSING_CASE(pixel_format);
2971 }
2972
2973 return 0;
2974 }
2975
2976 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977 {
2978 switch (fb_modifier) {
2979 case DRM_FORMAT_MOD_NONE:
2980 break;
2981 case I915_FORMAT_MOD_X_TILED:
2982 return PLANE_CTL_TILED_X;
2983 case I915_FORMAT_MOD_Y_TILED:
2984 return PLANE_CTL_TILED_Y;
2985 case I915_FORMAT_MOD_Yf_TILED:
2986 return PLANE_CTL_TILED_YF;
2987 default:
2988 MISSING_CASE(fb_modifier);
2989 }
2990
2991 return 0;
2992 }
2993
2994 u32 skl_plane_ctl_rotation(unsigned int rotation)
2995 {
2996 switch (rotation) {
2997 case BIT(DRM_ROTATE_0):
2998 break;
2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3003 case BIT(DRM_ROTATE_90):
3004 return PLANE_CTL_ROTATE_270;
3005 case BIT(DRM_ROTATE_180):
3006 return PLANE_CTL_ROTATE_180;
3007 case BIT(DRM_ROTATE_270):
3008 return PLANE_CTL_ROTATE_90;
3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
3013 return 0;
3014 }
3015
3016 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019 {
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
3038 plane_state = to_intel_plane_state(plane->state);
3039
3040 if (!visible || !fb) {
3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3045 }
3046
3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
3090 x_offset = stride * tile_height - y - src_h;
3091 y_offset = x;
3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3098 }
3099 plane_offset = y_offset << 16 | x_offset;
3100
3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124 }
3125
3126 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3127 static int
3128 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130 {
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133
3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
3136
3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
3140 }
3141
3142 static void intel_complete_page_flips(struct drm_device *dev)
3143 {
3144 struct drm_crtc *crtc;
3145
3146 for_each_crtc(dev, crtc) {
3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
3153 }
3154
3155 static void intel_update_primary_planes(struct drm_device *dev)
3156 {
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
3159
3160 for_each_crtc(dev, crtc) {
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
3163 drm_modeset_lock(&crtc->mutex, NULL);
3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
3167 * a NULL crtc->primary->fb.
3168 */
3169 if (intel_crtc->active && crtc->primary->fb)
3170 dev_priv->display.update_primary_plane(crtc,
3171 crtc->primary->fb,
3172 crtc->x,
3173 crtc->y);
3174 drm_modeset_unlock(&crtc->mutex);
3175 }
3176 }
3177
3178 void intel_crtc_reset(struct intel_crtc *crtc)
3179 {
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189 }
3190
3191 void intel_prepare_reset(struct drm_device *dev)
3192 {
3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
3216 }
3217 }
3218
3219 void intel_finish_reset(struct drm_device *dev)
3220 {
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265 }
3266
3267 static void
3268 intel_finish_fb(struct drm_framebuffer *old_fb)
3269 {
3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
3287 ret = i915_gem_object_wait_rendering(obj, true);
3288 dev_priv->mm.interruptible = was_interruptible;
3289
3290 WARN_ON(ret);
3291 }
3292
3293 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294 {
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
3304 spin_lock_irq(&dev->event_lock);
3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3306 spin_unlock_irq(&dev->event_lock);
3307
3308 return pending;
3309 }
3310
3311 static void intel_update_pipe_size(struct intel_crtc *crtc)
3312 {
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
3334 adjusted_mode = &crtc->config->base.adjusted_mode;
3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
3339 if (!crtc->config->pch_pfit.enabled &&
3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3348 }
3349
3350 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351 {
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
3361 if (IS_IVYBRIDGE(dev)) {
3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3367 }
3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
3389 }
3390
3391 /* The FDI link training functions for ILK/Ibexpeak. */
3392 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393 {
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
3398 u32 reg, temp, tries;
3399
3400 /* FDI needs bits from pipe first */
3401 assert_pipe_enabled(dev_priv, pipe);
3402
3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
3411 udelay(150);
3412
3413 /* enable CPU FDI TX and PCH FDI RX */
3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3421
3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
3429 udelay(150);
3430
3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
3435
3436 reg = FDI_RX_IIR(pipe);
3437 for (tries = 0; tries < 5; tries++) {
3438 temp = I915_READ(reg);
3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3444 break;
3445 }
3446 }
3447 if (tries == 5)
3448 DRM_ERROR("FDI train 1 fail!\n");
3449
3450 /* Train 2 */
3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
3455 I915_WRITE(reg, temp);
3456
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
3461 I915_WRITE(reg, temp);
3462
3463 POSTING_READ(reg);
3464 udelay(150);
3465
3466 reg = FDI_RX_IIR(pipe);
3467 for (tries = 0; tries < 5; tries++) {
3468 temp = I915_READ(reg);
3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
3476 }
3477 if (tries == 5)
3478 DRM_ERROR("FDI train 2 fail!\n");
3479
3480 DRM_DEBUG_KMS("FDI train done\n");
3481
3482 }
3483
3484 static const int snb_b_fdi_train_param[] = {
3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489 };
3490
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493 {
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
3498 u32 reg, temp, i, retry;
3499
3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
3509 udelay(150);
3510
3511 /* enable CPU FDI TX and PCH FDI RX */
3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3522
3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
3538 udelay(150);
3539
3540 for (i = 0; i < 4; i++) {
3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
3548 udelay(500);
3549
3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
3560 }
3561 if (retry < 5)
3562 break;
3563 }
3564 if (i == 4)
3565 DRM_ERROR("FDI train 1 fail!\n");
3566
3567 /* Train 2 */
3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
3577 I915_WRITE(reg, temp);
3578
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
3591 udelay(150);
3592
3593 for (i = 0; i < 4; i++) {
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
3601 udelay(500);
3602
3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
3613 }
3614 if (retry < 5)
3615 break;
3616 }
3617 if (i == 4)
3618 DRM_ERROR("FDI train 2 fail!\n");
3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621 }
3622
3623 /* Manual link training for Ivy Bridge A0 parts */
3624 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625 {
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
3630 u32 reg, temp, i, j;
3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
3654
3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
3661
3662 /* enable CPU FDI TX and PCH FDI RX */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3672
3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3675
3676 reg = FDI_RX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3681
3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
3684
3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3689
3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
3703
3704 /* Train 2 */
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
3718 udelay(2); /* should be 1.5us */
3719
3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3724
3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
3733 }
3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3736 }
3737
3738 train_done:
3739 DRM_DEBUG_KMS("FDI train done.\n");
3740 }
3741
3742 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3743 {
3744 struct drm_device *dev = intel_crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 int pipe = intel_crtc->pipe;
3747 u32 reg, temp;
3748
3749
3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
3766 udelay(200);
3767
3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3773
3774 POSTING_READ(reg);
3775 udelay(100);
3776 }
3777 }
3778
3779 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780 {
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806 }
3807
3808 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
3832 if (HAS_PCH_IBX(dev))
3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858 }
3859
3860 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861 {
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
3871 for_each_intel_crtc(dev, crtc) {
3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882 }
3883
3884 static void page_flip_completed(struct intel_crtc *intel_crtc)
3885 {
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905 }
3906
3907 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3908 {
3909 struct drm_device *dev = crtc->dev;
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911
3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917
3918 spin_lock_irq(&dev->event_lock);
3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
3923 spin_unlock_irq(&dev->event_lock);
3924 }
3925
3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
3931 }
3932
3933 /* Program iCLKIP clock to the desired frequency */
3934 static void lpt_program_iclkip(struct drm_crtc *crtc)
3935 {
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
3942 mutex_lock(&dev_priv->sb_lock);
3943
3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3956 if (clock == 20000) {
3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
3971 desired_divisor = (iclk_virtual_root_freq / clock);
3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3987 clock,
3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4002
4003 /* Program SSCAUXDIV */
4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4008
4009 /* Enable modulator and associated divider */
4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4011 temp &= ~SBI_SSCCTL_DISABLE;
4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4018
4019 mutex_unlock(&dev_priv->sb_lock);
4020 }
4021
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024 {
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044 }
4045
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4047 {
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065 }
4066
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068 {
4069 struct drm_device *dev = intel_crtc->base.dev;
4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
4075 if (intel_crtc->config->fdi_lanes > 2)
4076 cpt_set_fdi_bc_bifurcation(dev, false);
4077 else
4078 cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080 break;
4081 case PIPE_C:
4082 cpt_set_fdi_bc_bifurcation(dev, true);
4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088 }
4089
4090 /*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098 static void ironlake_pch_enable(struct drm_crtc *crtc)
4099 {
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
4104 u32 reg, temp;
4105
4106 assert_pch_transcoder_disabled(dev_priv, pipe);
4107
4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
4116 /* For PCH output, training FDI link */
4117 dev_priv->display.fdi_link_train(crtc);
4118
4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
4121 if (HAS_PCH_CPT(dev)) {
4122 u32 sel;
4123
4124 temp = I915_READ(PCH_DPLL_SEL);
4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4128 temp |= sel;
4129 else
4130 temp &= ~sel;
4131 I915_WRITE(PCH_DPLL_SEL, temp);
4132 }
4133
4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
4141 intel_enable_shared_dpll(intel_crtc);
4142
4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4146
4147 intel_fdi_normal_train(crtc);
4148
4149 /* For PCH DP, enable TRANS_DP_CTL */
4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
4157 temp |= TRANS_DP_OUTPUT_ENABLE;
4158 temp |= bpc << 9; /* same format but at 11:9 */
4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
4167 temp |= TRANS_DP_PORT_SEL_B;
4168 break;
4169 case PCH_DP_C:
4170 temp |= TRANS_DP_PORT_SEL_C;
4171 break;
4172 case PCH_DP_D:
4173 temp |= TRANS_DP_PORT_SEL_D;
4174 break;
4175 default:
4176 BUG();
4177 }
4178
4179 I915_WRITE(reg, temp);
4180 }
4181
4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
4183 }
4184
4185 static void lpt_pch_enable(struct drm_crtc *crtc)
4186 {
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4191
4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4193
4194 lpt_program_iclkip(crtc);
4195
4196 /* Set transcoder timing. */
4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4198
4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4200 }
4201
4202 void intel_put_shared_dpll(struct intel_crtc *crtc)
4203 {
4204 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4205
4206 if (pll == NULL)
4207 return;
4208
4209 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4210 WARN(1, "bad %s crtc mask\n", pll->name);
4211 return;
4212 }
4213
4214 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4215 if (pll->config.crtc_mask == 0) {
4216 WARN_ON(pll->on);
4217 WARN_ON(pll->active);
4218 }
4219
4220 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4221 }
4222
4223 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4224 struct intel_crtc_state *crtc_state)
4225 {
4226 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4227 struct intel_shared_dpll *pll;
4228 enum intel_dpll_id i;
4229
4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4232 i = (enum intel_dpll_id) crtc->pipe;
4233 pll = &dev_priv->shared_dplls[i];
4234
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
4237
4238 WARN_ON(pll->new_config->crtc_mask);
4239
4240 goto found;
4241 }
4242
4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(pll->new_config->crtc_mask);
4259
4260 goto found;
4261 }
4262
4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
4265
4266 /* Only want to check enabled timings first */
4267 if (pll->new_config->crtc_mask == 0)
4268 continue;
4269
4270 if (memcmp(&crtc_state->dpll_hw_state,
4271 &pll->new_config->hw_state,
4272 sizeof(pll->new_config->hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4274 crtc->base.base.id, pll->name,
4275 pll->new_config->crtc_mask,
4276 pll->active);
4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284 if (pll->new_config->crtc_mask == 0) {
4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293 found:
4294 if (pll->new_config->crtc_mask == 0)
4295 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4296
4297 crtc_state->shared_dpll = i;
4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4299 pipe_name(crtc->pipe));
4300
4301 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4302
4303 return pll;
4304 }
4305
4306 /**
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4310 *
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4313 */
4314 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4315 unsigned clear_pipes)
4316 {
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4324 GFP_KERNEL);
4325 if (!pll->new_config)
4326 goto cleanup;
4327
4328 pll->new_config->crtc_mask &= ~clear_pipes;
4329 }
4330
4331 return 0;
4332
4333 cleanup:
4334 while (--i >= 0) {
4335 pll = &dev_priv->shared_dplls[i];
4336 kfree(pll->new_config);
4337 pll->new_config = NULL;
4338 }
4339
4340 return -ENOMEM;
4341 }
4342
4343 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4344 {
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 WARN_ON(pll->new_config == &pll->config);
4352
4353 pll->config = *pll->new_config;
4354 kfree(pll->new_config);
4355 pll->new_config = NULL;
4356 }
4357 }
4358
4359 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4360 {
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372 }
4373
4374 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4375 {
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377 int dslreg = PIPEDSL(pipe);
4378 u32 temp;
4379
4380 temp = I915_READ(dslreg);
4381 udelay(500);
4382 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4383 if (wait_for(I915_READ(dslreg) != temp, 5))
4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4385 }
4386 }
4387
4388 /**
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4390 * @intel_crtc: crtc
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4395 *
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4399 * as NULL.
4400 *
4401 * Return
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4404 */
4405 int
4406 skl_update_scaler_users(
4407 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4408 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4409 int force_detach)
4410 {
4411 int need_scaling;
4412 int idx;
4413 int src_w, src_h, dst_w, dst_h;
4414 int *scaler_id;
4415 struct drm_framebuffer *fb;
4416 struct intel_crtc_scaler_state *scaler_state;
4417 unsigned int rotation;
4418
4419 if (!intel_crtc || !crtc_state)
4420 return 0;
4421
4422 scaler_state = &crtc_state->scaler_state;
4423
4424 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4425 fb = intel_plane ? plane_state->base.fb : NULL;
4426
4427 if (intel_plane) {
4428 src_w = drm_rect_width(&plane_state->src) >> 16;
4429 src_h = drm_rect_height(&plane_state->src) >> 16;
4430 dst_w = drm_rect_width(&plane_state->dst);
4431 dst_h = drm_rect_height(&plane_state->dst);
4432 scaler_id = &plane_state->scaler_id;
4433 rotation = plane_state->base.rotation;
4434 } else {
4435 struct drm_display_mode *adjusted_mode =
4436 &crtc_state->base.adjusted_mode;
4437 src_w = crtc_state->pipe_src_w;
4438 src_h = crtc_state->pipe_src_h;
4439 dst_w = adjusted_mode->hdisplay;
4440 dst_h = adjusted_mode->vdisplay;
4441 scaler_id = &scaler_state->scaler_id;
4442 rotation = DRM_ROTATE_0;
4443 }
4444
4445 need_scaling = intel_rotation_90_or_270(rotation) ?
4446 (src_h != dst_w || src_w != dst_h):
4447 (src_w != dst_w || src_h != dst_h);
4448
4449 /*
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4453 *
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4458 */
4459 if (force_detach || !need_scaling || (intel_plane &&
4460 (!fb || !plane_state->visible))) {
4461 if (*scaler_id >= 0) {
4462 scaler_state->scaler_users &= ~(1 << idx);
4463 scaler_state->scalers[*scaler_id].in_use = 0;
4464
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4468 intel_plane ? intel_plane->base.base.id :
4469 intel_crtc->base.base.id, crtc_state,
4470 scaler_state->scaler_users);
4471 *scaler_id = -1;
4472 }
4473 return 0;
4474 }
4475
4476 /* range checks */
4477 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4478 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4479
4480 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4481 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane ? "PLANE" : "CRTC",
4485 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4486 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4487 return -EINVAL;
4488 }
4489
4490 /* check colorkey */
4491 if (WARN_ON(intel_plane &&
4492 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
4499 if (intel_plane) {
4500 switch (fb->pixel_format) {
4501 case DRM_FORMAT_RGB565:
4502 case DRM_FORMAT_XBGR8888:
4503 case DRM_FORMAT_XRGB8888:
4504 case DRM_FORMAT_ABGR8888:
4505 case DRM_FORMAT_ARGB8888:
4506 case DRM_FORMAT_XRGB2101010:
4507 case DRM_FORMAT_XBGR2101010:
4508 case DRM_FORMAT_YUYV:
4509 case DRM_FORMAT_YVYU:
4510 case DRM_FORMAT_UYVY:
4511 case DRM_FORMAT_VYUY:
4512 break;
4513 default:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4516 return -EINVAL;
4517 }
4518 }
4519
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state->scaler_users |= (1 << idx);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4527 return 0;
4528 }
4529
4530 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4531 {
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int pipe = crtc->pipe;
4535 struct intel_crtc_scaler_state *scaler_state =
4536 &crtc->config->scaler_state;
4537
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4542 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4543 skl_detach_scalers(crtc);
4544 if (!enable)
4545 return;
4546
4547 if (crtc->config->pch_pfit.enabled) {
4548 int id;
4549
4550 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4552 return;
4553 }
4554
4555 id = scaler_state->scaler_id;
4556 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4557 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4562 }
4563 }
4564
4565 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566 {
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 int pipe = crtc->pipe;
4570
4571 if (crtc->config->pch_pfit.enabled) {
4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4574 * e.g. x201.
4575 */
4576 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4577 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4578 PF_PIPE_SEL_IVB(pipe));
4579 else
4580 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4581 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4582 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4583 }
4584 }
4585
4586 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4587 {
4588 struct drm_device *dev = crtc->dev;
4589 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4590 struct drm_plane *plane;
4591 struct intel_plane *intel_plane;
4592
4593 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4594 intel_plane = to_intel_plane(plane);
4595 if (intel_plane->pipe == pipe)
4596 intel_plane_restore(&intel_plane->base);
4597 }
4598 }
4599
4600 void hsw_enable_ips(struct intel_crtc *crtc)
4601 {
4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604
4605 if (!crtc->config->ips_enabled)
4606 return;
4607
4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev, crtc->pipe);
4610
4611 assert_plane_enabled(dev_priv, crtc->plane);
4612 if (IS_BROADWELL(dev)) {
4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
4620 */
4621 } else {
4622 I915_WRITE(IPS_CTL, IPS_ENABLE);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4630 }
4631 }
4632
4633 void hsw_disable_ips(struct intel_crtc *crtc)
4634 {
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
4638 if (!crtc->config->ips_enabled)
4639 return;
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
4642 if (IS_BROADWELL(dev)) {
4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
4649 } else {
4650 I915_WRITE(IPS_CTL, 0);
4651 POSTING_READ(IPS_CTL);
4652 }
4653
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev, crtc->pipe);
4656 }
4657
4658 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4659 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4660 {
4661 struct drm_device *dev = crtc->dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 enum pipe pipe = intel_crtc->pipe;
4665 int palreg = PALETTE(pipe);
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
4670 if (!crtc->state->enable || !intel_crtc->active)
4671 return;
4672
4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4674 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* use legacy palette for Ironlake */
4681 if (!HAS_GMCH_DISPLAY(dev))
4682 palreg = LGC_PALETTE(pipe);
4683
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4686 */
4687 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4689 GAMMA_MODE_MODE_SPLIT)) {
4690 hsw_disable_ips(intel_crtc);
4691 reenable_ips = true;
4692 }
4693
4694 for (i = 0; i < 256; i++) {
4695 I915_WRITE(palreg + 4 * i,
4696 (intel_crtc->lut_r[i] << 16) |
4697 (intel_crtc->lut_g[i] << 8) |
4698 intel_crtc->lut_b[i]);
4699 }
4700
4701 if (reenable_ips)
4702 hsw_enable_ips(intel_crtc);
4703 }
4704
4705 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4706 {
4707 if (intel_crtc->overlay) {
4708 struct drm_device *dev = intel_crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710
4711 mutex_lock(&dev->struct_mutex);
4712 dev_priv->mm.interruptible = false;
4713 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 dev_priv->mm.interruptible = true;
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4720 */
4721 }
4722
4723 /**
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4726 *
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4732 */
4733 static void
4734 intel_post_enable_primary(struct drm_crtc *crtc)
4735 {
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
4740
4741 /*
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4745 */
4746 if (IS_BROADWELL(dev))
4747 intel_wait_for_vblank(dev, pipe);
4748
4749 /*
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4753 * versa.
4754 */
4755 hsw_enable_ips(intel_crtc);
4756
4757 mutex_lock(&dev->struct_mutex);
4758 intel_fbc_update(dev);
4759 mutex_unlock(&dev->struct_mutex);
4760
4761 /*
4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4764 * are enabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
4767 */
4768 if (IS_GEN2(dev))
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4770
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev))
4773 i9xx_check_fifo_underruns(dev_priv);
4774 }
4775
4776 /**
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4779 *
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4784 * plane.
4785 */
4786 static void
4787 intel_pre_disable_primary(struct drm_crtc *crtc)
4788 {
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4792 int pipe = intel_crtc->pipe;
4793
4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4802
4803 /*
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4811 */
4812 if (HAS_GMCH_DISPLAY(dev))
4813 intel_set_memory_cxsr(dev_priv, false);
4814
4815 mutex_lock(&dev->struct_mutex);
4816 if (dev_priv->fbc.crtc == intel_crtc)
4817 intel_fbc_disable(dev);
4818 mutex_unlock(&dev->struct_mutex);
4819
4820 /*
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4824 * versa.
4825 */
4826 hsw_disable_ips(intel_crtc);
4827 }
4828
4829 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4830 {
4831 struct drm_device *dev = crtc->dev;
4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833 int pipe = intel_crtc->pipe;
4834
4835 intel_enable_primary_hw_plane(crtc->primary, crtc);
4836 intel_enable_sprite_planes(crtc);
4837 intel_crtc_update_cursor(crtc, true);
4838
4839 intel_post_enable_primary(crtc);
4840
4841 /*
4842 * FIXME: Once we grow proper nuclear flip support out of this we need
4843 * to compute the mask of flip planes precisely. For the time being
4844 * consider this a flip to a NULL plane.
4845 */
4846 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4847 }
4848
4849 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4850 {
4851 struct drm_device *dev = crtc->dev;
4852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4853 struct intel_plane *intel_plane;
4854 int pipe = intel_crtc->pipe;
4855
4856 intel_crtc_wait_for_pending_flips(crtc);
4857
4858 intel_pre_disable_primary(crtc);
4859
4860 intel_crtc_dpms_overlay_disable(intel_crtc);
4861 for_each_intel_plane(dev, intel_plane) {
4862 if (intel_plane->pipe == pipe) {
4863 struct drm_crtc *from = intel_plane->base.crtc;
4864
4865 intel_plane->disable_plane(&intel_plane->base,
4866 from ?: crtc, true);
4867 }
4868 }
4869
4870 /*
4871 * FIXME: Once we grow proper nuclear flip support out of this we need
4872 * to compute the mask of flip planes precisely. For the time being
4873 * consider this a flip to a NULL plane.
4874 */
4875 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4876 }
4877
4878 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4879 {
4880 struct drm_device *dev = crtc->dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883 struct intel_encoder *encoder;
4884 int pipe = intel_crtc->pipe;
4885
4886 WARN_ON(!crtc->state->enable);
4887
4888 if (intel_crtc->active)
4889 return;
4890
4891 if (intel_crtc->config->has_pch_encoder)
4892 intel_prepare_shared_dpll(intel_crtc);
4893
4894 if (intel_crtc->config->has_dp_encoder)
4895 intel_dp_set_m_n(intel_crtc, M1_N1);
4896
4897 intel_set_pipe_timings(intel_crtc);
4898
4899 if (intel_crtc->config->has_pch_encoder) {
4900 intel_cpu_transcoder_set_m_n(intel_crtc,
4901 &intel_crtc->config->fdi_m_n, NULL);
4902 }
4903
4904 ironlake_set_pipeconf(crtc);
4905
4906 intel_crtc->active = true;
4907
4908 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4909 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4910
4911 for_each_encoder_on_crtc(dev, crtc, encoder)
4912 if (encoder->pre_enable)
4913 encoder->pre_enable(encoder);
4914
4915 if (intel_crtc->config->has_pch_encoder) {
4916 /* Note: FDI PLL enabling _must_ be done before we enable the
4917 * cpu pipes, hence this is separate from all the other fdi/pch
4918 * enabling. */
4919 ironlake_fdi_pll_enable(intel_crtc);
4920 } else {
4921 assert_fdi_tx_disabled(dev_priv, pipe);
4922 assert_fdi_rx_disabled(dev_priv, pipe);
4923 }
4924
4925 ironlake_pfit_enable(intel_crtc);
4926
4927 /*
4928 * On ILK+ LUT must be loaded before the pipe is running but with
4929 * clocks enabled
4930 */
4931 intel_crtc_load_lut(crtc);
4932
4933 intel_update_watermarks(crtc);
4934 intel_enable_pipe(intel_crtc);
4935
4936 if (intel_crtc->config->has_pch_encoder)
4937 ironlake_pch_enable(crtc);
4938
4939 assert_vblank_disabled(crtc);
4940 drm_crtc_vblank_on(crtc);
4941
4942 for_each_encoder_on_crtc(dev, crtc, encoder)
4943 encoder->enable(encoder);
4944
4945 if (HAS_PCH_CPT(dev))
4946 cpt_verify_modeset(dev, intel_crtc->pipe);
4947 }
4948
4949 /* IPS only exists on ULT machines and is tied to pipe A. */
4950 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4951 {
4952 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4953 }
4954
4955 /*
4956 * This implements the workaround described in the "notes" section of the mode
4957 * set sequence documentation. When going from no pipes or single pipe to
4958 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4959 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4960 */
4961 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4962 {
4963 struct drm_device *dev = crtc->base.dev;
4964 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4965
4966 /* We want to get the other_active_crtc only if there's only 1 other
4967 * active crtc. */
4968 for_each_intel_crtc(dev, crtc_it) {
4969 if (!crtc_it->active || crtc_it == crtc)
4970 continue;
4971
4972 if (other_active_crtc)
4973 return;
4974
4975 other_active_crtc = crtc_it;
4976 }
4977 if (!other_active_crtc)
4978 return;
4979
4980 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4981 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4982 }
4983
4984 static void haswell_crtc_enable(struct drm_crtc *crtc)
4985 {
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4989 struct intel_encoder *encoder;
4990 int pipe = intel_crtc->pipe;
4991
4992 WARN_ON(!crtc->state->enable);
4993
4994 if (intel_crtc->active)
4995 return;
4996
4997 if (intel_crtc_to_shared_dpll(intel_crtc))
4998 intel_enable_shared_dpll(intel_crtc);
4999
5000 if (intel_crtc->config->has_dp_encoder)
5001 intel_dp_set_m_n(intel_crtc, M1_N1);
5002
5003 intel_set_pipe_timings(intel_crtc);
5004
5005 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5006 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5007 intel_crtc->config->pixel_multiplier - 1);
5008 }
5009
5010 if (intel_crtc->config->has_pch_encoder) {
5011 intel_cpu_transcoder_set_m_n(intel_crtc,
5012 &intel_crtc->config->fdi_m_n, NULL);
5013 }
5014
5015 haswell_set_pipeconf(crtc);
5016
5017 intel_set_pipe_csc(crtc);
5018
5019 intel_crtc->active = true;
5020
5021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5022 for_each_encoder_on_crtc(dev, crtc, encoder)
5023 if (encoder->pre_enable)
5024 encoder->pre_enable(encoder);
5025
5026 if (intel_crtc->config->has_pch_encoder) {
5027 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5028 true);
5029 dev_priv->display.fdi_link_train(crtc);
5030 }
5031
5032 intel_ddi_enable_pipe_clock(intel_crtc);
5033
5034 if (INTEL_INFO(dev)->gen == 9)
5035 skylake_pfit_update(intel_crtc, 1);
5036 else if (INTEL_INFO(dev)->gen < 9)
5037 ironlake_pfit_enable(intel_crtc);
5038 else
5039 MISSING_CASE(INTEL_INFO(dev)->gen);
5040
5041 /*
5042 * On ILK+ LUT must be loaded before the pipe is running but with
5043 * clocks enabled
5044 */
5045 intel_crtc_load_lut(crtc);
5046
5047 intel_ddi_set_pipe_settings(crtc);
5048 intel_ddi_enable_transcoder_func(crtc);
5049
5050 intel_update_watermarks(crtc);
5051 intel_enable_pipe(intel_crtc);
5052
5053 if (intel_crtc->config->has_pch_encoder)
5054 lpt_pch_enable(crtc);
5055
5056 if (intel_crtc->config->dp_encoder_is_mst)
5057 intel_ddi_set_vc_payload_alloc(crtc, true);
5058
5059 assert_vblank_disabled(crtc);
5060 drm_crtc_vblank_on(crtc);
5061
5062 for_each_encoder_on_crtc(dev, crtc, encoder) {
5063 encoder->enable(encoder);
5064 intel_opregion_notify_encoder(encoder, true);
5065 }
5066
5067 /* If we change the relative order between pipe/planes enabling, we need
5068 * to change the workaround. */
5069 haswell_mode_set_planes_workaround(intel_crtc);
5070 }
5071
5072 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5073 {
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 int pipe = crtc->pipe;
5077
5078 /* To avoid upsetting the power well on haswell only disable the pfit if
5079 * it's in use. The hw state code will make sure we get this right. */
5080 if (crtc->config->pch_pfit.enabled) {
5081 I915_WRITE(PF_CTL(pipe), 0);
5082 I915_WRITE(PF_WIN_POS(pipe), 0);
5083 I915_WRITE(PF_WIN_SZ(pipe), 0);
5084 }
5085 }
5086
5087 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5088 {
5089 struct drm_device *dev = crtc->dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5092 struct intel_encoder *encoder;
5093 int pipe = intel_crtc->pipe;
5094 u32 reg, temp;
5095
5096 if (!intel_crtc->active)
5097 return;
5098
5099 for_each_encoder_on_crtc(dev, crtc, encoder)
5100 encoder->disable(encoder);
5101
5102 drm_crtc_vblank_off(crtc);
5103 assert_vblank_disabled(crtc);
5104
5105 if (intel_crtc->config->has_pch_encoder)
5106 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5107
5108 intel_disable_pipe(intel_crtc);
5109
5110 ironlake_pfit_disable(intel_crtc);
5111
5112 if (intel_crtc->config->has_pch_encoder)
5113 ironlake_fdi_disable(crtc);
5114
5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
5118
5119 if (intel_crtc->config->has_pch_encoder) {
5120 ironlake_disable_pch_transcoder(dev_priv, pipe);
5121
5122 if (HAS_PCH_CPT(dev)) {
5123 /* disable TRANS_DP_CTL */
5124 reg = TRANS_DP_CTL(pipe);
5125 temp = I915_READ(reg);
5126 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5127 TRANS_DP_PORT_SEL_MASK);
5128 temp |= TRANS_DP_PORT_SEL_NONE;
5129 I915_WRITE(reg, temp);
5130
5131 /* disable DPLL_SEL */
5132 temp = I915_READ(PCH_DPLL_SEL);
5133 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5134 I915_WRITE(PCH_DPLL_SEL, temp);
5135 }
5136
5137 /* disable PCH DPLL */
5138 intel_disable_shared_dpll(intel_crtc);
5139
5140 ironlake_fdi_pll_disable(intel_crtc);
5141 }
5142
5143 intel_crtc->active = false;
5144 intel_update_watermarks(crtc);
5145
5146 mutex_lock(&dev->struct_mutex);
5147 intel_fbc_update(dev);
5148 mutex_unlock(&dev->struct_mutex);
5149 }
5150
5151 static void haswell_crtc_disable(struct drm_crtc *crtc)
5152 {
5153 struct drm_device *dev = crtc->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5156 struct intel_encoder *encoder;
5157 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5158
5159 if (!intel_crtc->active)
5160 return;
5161
5162 for_each_encoder_on_crtc(dev, crtc, encoder) {
5163 intel_opregion_notify_encoder(encoder, false);
5164 encoder->disable(encoder);
5165 }
5166
5167 drm_crtc_vblank_off(crtc);
5168 assert_vblank_disabled(crtc);
5169
5170 if (intel_crtc->config->has_pch_encoder)
5171 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5172 false);
5173 intel_disable_pipe(intel_crtc);
5174
5175 if (intel_crtc->config->dp_encoder_is_mst)
5176 intel_ddi_set_vc_payload_alloc(crtc, false);
5177
5178 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5179
5180 if (INTEL_INFO(dev)->gen == 9)
5181 skylake_pfit_update(intel_crtc, 0);
5182 else if (INTEL_INFO(dev)->gen < 9)
5183 ironlake_pfit_disable(intel_crtc);
5184 else
5185 MISSING_CASE(INTEL_INFO(dev)->gen);
5186
5187 intel_ddi_disable_pipe_clock(intel_crtc);
5188
5189 if (intel_crtc->config->has_pch_encoder) {
5190 lpt_disable_pch_transcoder(dev_priv);
5191 intel_ddi_fdi_disable(crtc);
5192 }
5193
5194 for_each_encoder_on_crtc(dev, crtc, encoder)
5195 if (encoder->post_disable)
5196 encoder->post_disable(encoder);
5197
5198 intel_crtc->active = false;
5199 intel_update_watermarks(crtc);
5200
5201 mutex_lock(&dev->struct_mutex);
5202 intel_fbc_update(dev);
5203 mutex_unlock(&dev->struct_mutex);
5204
5205 if (intel_crtc_to_shared_dpll(intel_crtc))
5206 intel_disable_shared_dpll(intel_crtc);
5207 }
5208
5209 static void ironlake_crtc_off(struct drm_crtc *crtc)
5210 {
5211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5212 intel_put_shared_dpll(intel_crtc);
5213 }
5214
5215
5216 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5217 {
5218 struct drm_device *dev = crtc->base.dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 struct intel_crtc_state *pipe_config = crtc->config;
5221
5222 if (!pipe_config->gmch_pfit.control)
5223 return;
5224
5225 /*
5226 * The panel fitter should only be adjusted whilst the pipe is disabled,
5227 * according to register description and PRM.
5228 */
5229 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5230 assert_pipe_disabled(dev_priv, crtc->pipe);
5231
5232 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5233 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5234
5235 /* Border color in case we don't scale up to the full screen. Black by
5236 * default, change to something else for debugging. */
5237 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5238 }
5239
5240 static enum intel_display_power_domain port_to_power_domain(enum port port)
5241 {
5242 switch (port) {
5243 case PORT_A:
5244 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5245 case PORT_B:
5246 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5247 case PORT_C:
5248 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5249 case PORT_D:
5250 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5251 default:
5252 WARN_ON_ONCE(1);
5253 return POWER_DOMAIN_PORT_OTHER;
5254 }
5255 }
5256
5257 #define for_each_power_domain(domain, mask) \
5258 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5259 if ((1 << (domain)) & (mask))
5260
5261 enum intel_display_power_domain
5262 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5263 {
5264 struct drm_device *dev = intel_encoder->base.dev;
5265 struct intel_digital_port *intel_dig_port;
5266
5267 switch (intel_encoder->type) {
5268 case INTEL_OUTPUT_UNKNOWN:
5269 /* Only DDI platforms should ever use this output type */
5270 WARN_ON_ONCE(!HAS_DDI(dev));
5271 case INTEL_OUTPUT_DISPLAYPORT:
5272 case INTEL_OUTPUT_HDMI:
5273 case INTEL_OUTPUT_EDP:
5274 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5275 return port_to_power_domain(intel_dig_port->port);
5276 case INTEL_OUTPUT_DP_MST:
5277 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5278 return port_to_power_domain(intel_dig_port->port);
5279 case INTEL_OUTPUT_ANALOG:
5280 return POWER_DOMAIN_PORT_CRT;
5281 case INTEL_OUTPUT_DSI:
5282 return POWER_DOMAIN_PORT_DSI;
5283 default:
5284 return POWER_DOMAIN_PORT_OTHER;
5285 }
5286 }
5287
5288 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5289 {
5290 struct drm_device *dev = crtc->dev;
5291 struct intel_encoder *intel_encoder;
5292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293 enum pipe pipe = intel_crtc->pipe;
5294 unsigned long mask;
5295 enum transcoder transcoder;
5296
5297 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5298
5299 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5300 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5301 if (intel_crtc->config->pch_pfit.enabled ||
5302 intel_crtc->config->pch_pfit.force_thru)
5303 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5304
5305 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5306 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5307
5308 return mask;
5309 }
5310
5311 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5312 {
5313 struct drm_device *dev = state->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5316 struct intel_crtc *crtc;
5317
5318 /*
5319 * First get all needed power domains, then put all unneeded, to avoid
5320 * any unnecessary toggling of the power wells.
5321 */
5322 for_each_intel_crtc(dev, crtc) {
5323 enum intel_display_power_domain domain;
5324
5325 if (!crtc->base.state->enable)
5326 continue;
5327
5328 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5329
5330 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5331 intel_display_power_get(dev_priv, domain);
5332 }
5333
5334 if (dev_priv->display.modeset_global_resources)
5335 dev_priv->display.modeset_global_resources(state);
5336
5337 for_each_intel_crtc(dev, crtc) {
5338 enum intel_display_power_domain domain;
5339
5340 for_each_power_domain(domain, crtc->enabled_power_domains)
5341 intel_display_power_put(dev_priv, domain);
5342
5343 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5344 }
5345
5346 intel_display_set_init_power(dev_priv, false);
5347 }
5348
5349 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5350 {
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t divider;
5353 uint32_t ratio;
5354 uint32_t current_freq;
5355 int ret;
5356
5357 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5358 switch (frequency) {
5359 case 144000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 288000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 384000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 576000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 624000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(65);
5378 break;
5379 case 19200:
5380 /*
5381 * Bypass frequency with DE PLL disabled. Init ratio, divider
5382 * to suppress GCC warning.
5383 */
5384 ratio = 0;
5385 divider = 0;
5386 break;
5387 default:
5388 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5389
5390 return;
5391 }
5392
5393 mutex_lock(&dev_priv->rps.hw_lock);
5394 /* Inform power controller of upcoming frequency change */
5395 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396 0x80000000);
5397 mutex_unlock(&dev_priv->rps.hw_lock);
5398
5399 if (ret) {
5400 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5401 ret, frequency);
5402 return;
5403 }
5404
5405 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5406 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5407 current_freq = current_freq * 500 + 1000;
5408
5409 /*
5410 * DE PLL has to be disabled when
5411 * - setting to 19.2MHz (bypass, PLL isn't used)
5412 * - before setting to 624MHz (PLL needs toggling)
5413 * - before setting to any frequency from 624MHz (PLL needs toggling)
5414 */
5415 if (frequency == 19200 || frequency == 624000 ||
5416 current_freq == 624000) {
5417 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418 /* Timeout 200us */
5419 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420 1))
5421 DRM_ERROR("timout waiting for DE PLL unlock\n");
5422 }
5423
5424 if (frequency != 19200) {
5425 uint32_t val;
5426
5427 val = I915_READ(BXT_DE_PLL_CTL);
5428 val &= ~BXT_DE_PLL_RATIO_MASK;
5429 val |= ratio;
5430 I915_WRITE(BXT_DE_PLL_CTL, val);
5431
5432 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433 /* Timeout 200us */
5434 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5435 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437 val = I915_READ(CDCLK_CTL);
5438 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5439 val |= divider;
5440 /*
5441 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5442 * enable otherwise.
5443 */
5444 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445 if (frequency >= 500000)
5446 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447
5448 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5449 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5450 val |= (frequency - 1000) / 500;
5451 I915_WRITE(CDCLK_CTL, val);
5452 }
5453
5454 mutex_lock(&dev_priv->rps.hw_lock);
5455 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5456 DIV_ROUND_UP(frequency, 25000));
5457 mutex_unlock(&dev_priv->rps.hw_lock);
5458
5459 if (ret) {
5460 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5461 ret, frequency);
5462 return;
5463 }
5464
5465 dev_priv->cdclk_freq = frequency;
5466 }
5467
5468 void broxton_init_cdclk(struct drm_device *dev)
5469 {
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 uint32_t val;
5472
5473 /*
5474 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5475 * or else the reset will hang because there is no PCH to respond.
5476 * Move the handshake programming to initialization sequence.
5477 * Previously was left up to BIOS.
5478 */
5479 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5480 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5481 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482
5483 /* Enable PG1 for cdclk */
5484 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485
5486 /* check if cd clock is enabled */
5487 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5488 DRM_DEBUG_KMS("Display already initialized\n");
5489 return;
5490 }
5491
5492 /*
5493 * FIXME:
5494 * - The initial CDCLK needs to be read from VBT.
5495 * Need to make this change after VBT has changes for BXT.
5496 * - check if setting the max (or any) cdclk freq is really necessary
5497 * here, it belongs to modeset time
5498 */
5499 broxton_set_cdclk(dev, 624000);
5500
5501 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5502 POSTING_READ(DBUF_CTL);
5503
5504 udelay(10);
5505
5506 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5507 DRM_ERROR("DBuf power enable timeout!\n");
5508 }
5509
5510 void broxton_uninit_cdclk(struct drm_device *dev)
5511 {
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5515 POSTING_READ(DBUF_CTL);
5516
5517 udelay(10);
5518
5519 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523 broxton_set_cdclk(dev, 19200);
5524
5525 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5526 }
5527
5528 static const struct skl_cdclk_entry {
5529 unsigned int freq;
5530 unsigned int vco;
5531 } skl_cdclk_frequencies[] = {
5532 { .freq = 308570, .vco = 8640 },
5533 { .freq = 337500, .vco = 8100 },
5534 { .freq = 432000, .vco = 8640 },
5535 { .freq = 450000, .vco = 8100 },
5536 { .freq = 540000, .vco = 8100 },
5537 { .freq = 617140, .vco = 8640 },
5538 { .freq = 675000, .vco = 8100 },
5539 };
5540
5541 static unsigned int skl_cdclk_decimal(unsigned int freq)
5542 {
5543 return (freq - 1000) / 500;
5544 }
5545
5546 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5547 {
5548 unsigned int i;
5549
5550 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5551 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552
5553 if (e->freq == freq)
5554 return e->vco;
5555 }
5556
5557 return 8100;
5558 }
5559
5560 static void
5561 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562 {
5563 unsigned int min_freq;
5564 u32 val;
5565
5566 /* select the minimum CDCLK before enabling DPLL 0 */
5567 val = I915_READ(CDCLK_CTL);
5568 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5569 val |= CDCLK_FREQ_337_308;
5570
5571 if (required_vco == 8640)
5572 min_freq = 308570;
5573 else
5574 min_freq = 337500;
5575
5576 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577
5578 I915_WRITE(CDCLK_CTL, val);
5579 POSTING_READ(CDCLK_CTL);
5580
5581 /*
5582 * We always enable DPLL0 with the lowest link rate possible, but still
5583 * taking into account the VCO required to operate the eDP panel at the
5584 * desired frequency. The usual DP link rates operate with a VCO of
5585 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5586 * The modeset code is responsible for the selection of the exact link
5587 * rate later on, with the constraint of choosing a frequency that
5588 * works with required_vco.
5589 */
5590 val = I915_READ(DPLL_CTRL1);
5591
5592 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5593 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5594 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5595 if (required_vco == 8640)
5596 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5597 SKL_DPLL0);
5598 else
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5600 SKL_DPLL0);
5601
5602 I915_WRITE(DPLL_CTRL1, val);
5603 POSTING_READ(DPLL_CTRL1);
5604
5605 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606
5607 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5608 DRM_ERROR("DPLL0 not locked\n");
5609 }
5610
5611 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612 {
5613 int ret;
5614 u32 val;
5615
5616 /* inform PCU we want to change CDCLK */
5617 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618 mutex_lock(&dev_priv->rps.hw_lock);
5619 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620 mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623 }
5624
5625 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626 {
5627 unsigned int i;
5628
5629 for (i = 0; i < 15; i++) {
5630 if (skl_cdclk_pcu_ready(dev_priv))
5631 return true;
5632 udelay(10);
5633 }
5634
5635 return false;
5636 }
5637
5638 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639 {
5640 u32 freq_select, pcu_ack;
5641
5642 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5643
5644 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5645 DRM_ERROR("failed to inform PCU about cdclk change\n");
5646 return;
5647 }
5648
5649 /* set CDCLK_CTL */
5650 switch(freq) {
5651 case 450000:
5652 case 432000:
5653 freq_select = CDCLK_FREQ_450_432;
5654 pcu_ack = 1;
5655 break;
5656 case 540000:
5657 freq_select = CDCLK_FREQ_540;
5658 pcu_ack = 2;
5659 break;
5660 case 308570:
5661 case 337500:
5662 default:
5663 freq_select = CDCLK_FREQ_337_308;
5664 pcu_ack = 0;
5665 break;
5666 case 617140:
5667 case 675000:
5668 freq_select = CDCLK_FREQ_675_617;
5669 pcu_ack = 3;
5670 break;
5671 }
5672
5673 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5674 POSTING_READ(CDCLK_CTL);
5675
5676 /* inform PCU of the change */
5677 mutex_lock(&dev_priv->rps.hw_lock);
5678 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5679 mutex_unlock(&dev_priv->rps.hw_lock);
5680 }
5681
5682 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5683 {
5684 /* disable DBUF power */
5685 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5686 POSTING_READ(DBUF_CTL);
5687
5688 udelay(10);
5689
5690 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5691 DRM_ERROR("DBuf power disable timeout\n");
5692
5693 /* disable DPLL0 */
5694 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5695 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5696 DRM_ERROR("Couldn't disable DPLL0\n");
5697
5698 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5699 }
5700
5701 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5702 {
5703 u32 val;
5704 unsigned int required_vco;
5705
5706 /* enable PCH reset handshake */
5707 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5708 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5709
5710 /* enable PG1 and Misc I/O */
5711 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5712
5713 /* DPLL0 already enabed !? */
5714 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5715 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5716 return;
5717 }
5718
5719 /* enable DPLL0 */
5720 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5721 skl_dpll0_enable(dev_priv, required_vco);
5722
5723 /* set CDCLK to the frequency the BIOS chose */
5724 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725
5726 /* enable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5733 DRM_ERROR("DBuf power enable timeout\n");
5734 }
5735
5736 /* returns HPLL frequency in kHz */
5737 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5738 {
5739 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5740
5741 /* Obtain SKU information */
5742 mutex_lock(&dev_priv->sb_lock);
5743 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5744 CCK_FUSE_HPLL_FREQ_MASK;
5745 mutex_unlock(&dev_priv->sb_lock);
5746
5747 return vco_freq[hpll_freq] * 1000;
5748 }
5749
5750 static void intel_update_cdclk(struct drm_device *dev)
5751 {
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753
5754 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5755 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5756 dev_priv->cdclk_freq);
5757
5758 /*
5759 * Program the gmbus_freq based on the cdclk frequency.
5760 * BSpec erroneously claims we should aim for 4MHz, but
5761 * in fact 1MHz is the correct frequency.
5762 */
5763 if (IS_VALLEYVIEW(dev)) {
5764 /*
5765 * Program the gmbus_freq based on the cdclk frequency.
5766 * BSpec erroneously claims we should aim for 4MHz, but
5767 * in fact 1MHz is the correct frequency.
5768 */
5769 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5770 }
5771 }
5772
5773 /* Adjust CDclk dividers to allow high res or save power if possible */
5774 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5775 {
5776 struct drm_i915_private *dev_priv = dev->dev_private;
5777 u32 val, cmd;
5778
5779 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5780 != dev_priv->cdclk_freq);
5781
5782 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5783 cmd = 2;
5784 else if (cdclk == 266667)
5785 cmd = 1;
5786 else
5787 cmd = 0;
5788
5789 mutex_lock(&dev_priv->rps.hw_lock);
5790 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5791 val &= ~DSPFREQGUAR_MASK;
5792 val |= (cmd << DSPFREQGUAR_SHIFT);
5793 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5794 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5795 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5796 50)) {
5797 DRM_ERROR("timed out waiting for CDclk change\n");
5798 }
5799 mutex_unlock(&dev_priv->rps.hw_lock);
5800
5801 mutex_lock(&dev_priv->sb_lock);
5802
5803 if (cdclk == 400000) {
5804 u32 divider;
5805
5806 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5807
5808 /* adjust cdclk divider */
5809 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5810 val &= ~DISPLAY_FREQUENCY_VALUES;
5811 val |= divider;
5812 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5813
5814 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5815 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5816 50))
5817 DRM_ERROR("timed out waiting for CDclk change\n");
5818 }
5819
5820 /* adjust self-refresh exit latency value */
5821 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5822 val &= ~0x7f;
5823
5824 /*
5825 * For high bandwidth configs, we set a higher latency in the bunit
5826 * so that the core display fetch happens in time to avoid underruns.
5827 */
5828 if (cdclk == 400000)
5829 val |= 4500 / 250; /* 4.5 usec */
5830 else
5831 val |= 3000 / 250; /* 3.0 usec */
5832 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5833
5834 mutex_unlock(&dev_priv->sb_lock);
5835
5836 intel_update_cdclk(dev);
5837 }
5838
5839 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5840 {
5841 struct drm_i915_private *dev_priv = dev->dev_private;
5842 u32 val, cmd;
5843
5844 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5845 != dev_priv->cdclk_freq);
5846
5847 switch (cdclk) {
5848 case 333333:
5849 case 320000:
5850 case 266667:
5851 case 200000:
5852 break;
5853 default:
5854 MISSING_CASE(cdclk);
5855 return;
5856 }
5857
5858 /*
5859 * Specs are full of misinformation, but testing on actual
5860 * hardware has shown that we just need to write the desired
5861 * CCK divider into the Punit register.
5862 */
5863 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5864
5865 mutex_lock(&dev_priv->rps.hw_lock);
5866 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5867 val &= ~DSPFREQGUAR_MASK_CHV;
5868 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5869 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5870 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5871 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5872 50)) {
5873 DRM_ERROR("timed out waiting for CDclk change\n");
5874 }
5875 mutex_unlock(&dev_priv->rps.hw_lock);
5876
5877 intel_update_cdclk(dev);
5878 }
5879
5880 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5881 int max_pixclk)
5882 {
5883 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5884 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5885
5886 /*
5887 * Really only a few cases to deal with, as only 4 CDclks are supported:
5888 * 200MHz
5889 * 267MHz
5890 * 320/333MHz (depends on HPLL freq)
5891 * 400MHz (VLV only)
5892 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5893 * of the lower bin and adjust if needed.
5894 *
5895 * We seem to get an unstable or solid color picture at 200MHz.
5896 * Not sure what's wrong. For now use 200MHz only when all pipes
5897 * are off.
5898 */
5899 if (!IS_CHERRYVIEW(dev_priv) &&
5900 max_pixclk > freq_320*limit/100)
5901 return 400000;
5902 else if (max_pixclk > 266667*limit/100)
5903 return freq_320;
5904 else if (max_pixclk > 0)
5905 return 266667;
5906 else
5907 return 200000;
5908 }
5909
5910 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5911 int max_pixclk)
5912 {
5913 /*
5914 * FIXME:
5915 * - remove the guardband, it's not needed on BXT
5916 * - set 19.2MHz bypass frequency if there are no active pipes
5917 */
5918 if (max_pixclk > 576000*9/10)
5919 return 624000;
5920 else if (max_pixclk > 384000*9/10)
5921 return 576000;
5922 else if (max_pixclk > 288000*9/10)
5923 return 384000;
5924 else if (max_pixclk > 144000*9/10)
5925 return 288000;
5926 else
5927 return 144000;
5928 }
5929
5930 /* Compute the max pixel clock for new configuration. Uses atomic state if
5931 * that's non-NULL, look at current state otherwise. */
5932 static int intel_mode_max_pixclk(struct drm_device *dev,
5933 struct drm_atomic_state *state)
5934 {
5935 struct intel_crtc *intel_crtc;
5936 struct intel_crtc_state *crtc_state;
5937 int max_pixclk = 0;
5938
5939 for_each_intel_crtc(dev, intel_crtc) {
5940 if (state)
5941 crtc_state =
5942 intel_atomic_get_crtc_state(state, intel_crtc);
5943 else
5944 crtc_state = intel_crtc->config;
5945 if (IS_ERR(crtc_state))
5946 return PTR_ERR(crtc_state);
5947
5948 if (!crtc_state->base.enable)
5949 continue;
5950
5951 max_pixclk = max(max_pixclk,
5952 crtc_state->base.adjusted_mode.crtc_clock);
5953 }
5954
5955 return max_pixclk;
5956 }
5957
5958 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5959 {
5960 struct drm_i915_private *dev_priv = to_i915(state->dev);
5961 struct drm_crtc *crtc;
5962 struct drm_crtc_state *crtc_state;
5963 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5964 int cdclk, i;
5965
5966 if (max_pixclk < 0)
5967 return max_pixclk;
5968
5969 if (IS_VALLEYVIEW(dev_priv))
5970 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5971 else
5972 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5973
5974 if (cdclk == dev_priv->cdclk_freq)
5975 return 0;
5976
5977 /* add all active pipes to the state */
5978 for_each_crtc(state->dev, crtc) {
5979 if (!crtc->state->enable)
5980 continue;
5981
5982 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5983 if (IS_ERR(crtc_state))
5984 return PTR_ERR(crtc_state);
5985 }
5986
5987 /* disable/enable all currently active pipes while we change cdclk */
5988 for_each_crtc_in_state(state, crtc, crtc_state, i)
5989 if (crtc_state->enable)
5990 crtc_state->mode_changed = true;
5991
5992 return 0;
5993 }
5994
5995 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5996 {
5997 unsigned int credits, default_credits;
5998
5999 if (IS_CHERRYVIEW(dev_priv))
6000 default_credits = PFI_CREDIT(12);
6001 else
6002 default_credits = PFI_CREDIT(8);
6003
6004 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
6005 /* CHV suggested value is 31 or 63 */
6006 if (IS_CHERRYVIEW(dev_priv))
6007 credits = PFI_CREDIT_31;
6008 else
6009 credits = PFI_CREDIT(15);
6010 } else {
6011 credits = default_credits;
6012 }
6013
6014 /*
6015 * WA - write default credits before re-programming
6016 * FIXME: should we also set the resend bit here?
6017 */
6018 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6019 default_credits);
6020
6021 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6022 credits | PFI_CREDIT_RESEND);
6023
6024 /*
6025 * FIXME is this guaranteed to clear
6026 * immediately or should we poll for it?
6027 */
6028 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6029 }
6030
6031 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6032 {
6033 struct drm_device *dev = old_state->dev;
6034 struct drm_i915_private *dev_priv = dev->dev_private;
6035 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6036 int req_cdclk;
6037
6038 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6039 * never fail. */
6040 if (WARN_ON(max_pixclk < 0))
6041 return;
6042
6043 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6044
6045 if (req_cdclk != dev_priv->cdclk_freq) {
6046 /*
6047 * FIXME: We can end up here with all power domains off, yet
6048 * with a CDCLK frequency other than the minimum. To account
6049 * for this take the PIPE-A power domain, which covers the HW
6050 * blocks needed for the following programming. This can be
6051 * removed once it's guaranteed that we get here either with
6052 * the minimum CDCLK set, or the required power domains
6053 * enabled.
6054 */
6055 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6056
6057 if (IS_CHERRYVIEW(dev))
6058 cherryview_set_cdclk(dev, req_cdclk);
6059 else
6060 valleyview_set_cdclk(dev, req_cdclk);
6061
6062 vlv_program_pfi_credits(dev_priv);
6063
6064 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6065 }
6066 }
6067
6068 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6069 {
6070 struct drm_device *dev = crtc->dev;
6071 struct drm_i915_private *dev_priv = to_i915(dev);
6072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6073 struct intel_encoder *encoder;
6074 int pipe = intel_crtc->pipe;
6075 bool is_dsi;
6076
6077 WARN_ON(!crtc->state->enable);
6078
6079 if (intel_crtc->active)
6080 return;
6081
6082 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6083
6084 if (!is_dsi) {
6085 if (IS_CHERRYVIEW(dev))
6086 chv_prepare_pll(intel_crtc, intel_crtc->config);
6087 else
6088 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6089 }
6090
6091 if (intel_crtc->config->has_dp_encoder)
6092 intel_dp_set_m_n(intel_crtc, M1_N1);
6093
6094 intel_set_pipe_timings(intel_crtc);
6095
6096 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098
6099 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6100 I915_WRITE(CHV_CANVAS(pipe), 0);
6101 }
6102
6103 i9xx_set_pipeconf(intel_crtc);
6104
6105 intel_crtc->active = true;
6106
6107 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6108
6109 for_each_encoder_on_crtc(dev, crtc, encoder)
6110 if (encoder->pre_pll_enable)
6111 encoder->pre_pll_enable(encoder);
6112
6113 if (!is_dsi) {
6114 if (IS_CHERRYVIEW(dev))
6115 chv_enable_pll(intel_crtc, intel_crtc->config);
6116 else
6117 vlv_enable_pll(intel_crtc, intel_crtc->config);
6118 }
6119
6120 for_each_encoder_on_crtc(dev, crtc, encoder)
6121 if (encoder->pre_enable)
6122 encoder->pre_enable(encoder);
6123
6124 i9xx_pfit_enable(intel_crtc);
6125
6126 intel_crtc_load_lut(crtc);
6127
6128 intel_update_watermarks(crtc);
6129 intel_enable_pipe(intel_crtc);
6130
6131 assert_vblank_disabled(crtc);
6132 drm_crtc_vblank_on(crtc);
6133
6134 for_each_encoder_on_crtc(dev, crtc, encoder)
6135 encoder->enable(encoder);
6136 }
6137
6138 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6139 {
6140 struct drm_device *dev = crtc->base.dev;
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6142
6143 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6144 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6145 }
6146
6147 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6148 {
6149 struct drm_device *dev = crtc->dev;
6150 struct drm_i915_private *dev_priv = to_i915(dev);
6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 struct intel_encoder *encoder;
6153 int pipe = intel_crtc->pipe;
6154
6155 WARN_ON(!crtc->state->enable);
6156
6157 if (intel_crtc->active)
6158 return;
6159
6160 i9xx_set_pll_dividers(intel_crtc);
6161
6162 if (intel_crtc->config->has_dp_encoder)
6163 intel_dp_set_m_n(intel_crtc, M1_N1);
6164
6165 intel_set_pipe_timings(intel_crtc);
6166
6167 i9xx_set_pipeconf(intel_crtc);
6168
6169 intel_crtc->active = true;
6170
6171 if (!IS_GEN2(dev))
6172 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6173
6174 for_each_encoder_on_crtc(dev, crtc, encoder)
6175 if (encoder->pre_enable)
6176 encoder->pre_enable(encoder);
6177
6178 i9xx_enable_pll(intel_crtc);
6179
6180 i9xx_pfit_enable(intel_crtc);
6181
6182 intel_crtc_load_lut(crtc);
6183
6184 intel_update_watermarks(crtc);
6185 intel_enable_pipe(intel_crtc);
6186
6187 assert_vblank_disabled(crtc);
6188 drm_crtc_vblank_on(crtc);
6189
6190 for_each_encoder_on_crtc(dev, crtc, encoder)
6191 encoder->enable(encoder);
6192 }
6193
6194 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6195 {
6196 struct drm_device *dev = crtc->base.dev;
6197 struct drm_i915_private *dev_priv = dev->dev_private;
6198
6199 if (!crtc->config->gmch_pfit.control)
6200 return;
6201
6202 assert_pipe_disabled(dev_priv, crtc->pipe);
6203
6204 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6205 I915_READ(PFIT_CONTROL));
6206 I915_WRITE(PFIT_CONTROL, 0);
6207 }
6208
6209 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6210 {
6211 struct drm_device *dev = crtc->dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6214 struct intel_encoder *encoder;
6215 int pipe = intel_crtc->pipe;
6216
6217 if (!intel_crtc->active)
6218 return;
6219
6220 /*
6221 * On gen2 planes are double buffered but the pipe isn't, so we must
6222 * wait for planes to fully turn off before disabling the pipe.
6223 * We also need to wait on all gmch platforms because of the
6224 * self-refresh mode constraint explained above.
6225 */
6226 intel_wait_for_vblank(dev, pipe);
6227
6228 for_each_encoder_on_crtc(dev, crtc, encoder)
6229 encoder->disable(encoder);
6230
6231 drm_crtc_vblank_off(crtc);
6232 assert_vblank_disabled(crtc);
6233
6234 intel_disable_pipe(intel_crtc);
6235
6236 i9xx_pfit_disable(intel_crtc);
6237
6238 for_each_encoder_on_crtc(dev, crtc, encoder)
6239 if (encoder->post_disable)
6240 encoder->post_disable(encoder);
6241
6242 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6243 if (IS_CHERRYVIEW(dev))
6244 chv_disable_pll(dev_priv, pipe);
6245 else if (IS_VALLEYVIEW(dev))
6246 vlv_disable_pll(dev_priv, pipe);
6247 else
6248 i9xx_disable_pll(intel_crtc);
6249 }
6250
6251 if (!IS_GEN2(dev))
6252 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6253
6254 intel_crtc->active = false;
6255 intel_update_watermarks(crtc);
6256
6257 mutex_lock(&dev->struct_mutex);
6258 intel_fbc_update(dev);
6259 mutex_unlock(&dev->struct_mutex);
6260 }
6261
6262 static void i9xx_crtc_off(struct drm_crtc *crtc)
6263 {
6264 }
6265
6266 /* Master function to enable/disable CRTC and corresponding power wells */
6267 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6268 {
6269 struct drm_device *dev = crtc->dev;
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272 enum intel_display_power_domain domain;
6273 unsigned long domains;
6274
6275 if (enable) {
6276 if (!intel_crtc->active) {
6277 domains = get_crtc_power_domains(crtc);
6278 for_each_power_domain(domain, domains)
6279 intel_display_power_get(dev_priv, domain);
6280 intel_crtc->enabled_power_domains = domains;
6281
6282 dev_priv->display.crtc_enable(crtc);
6283 intel_crtc_enable_planes(crtc);
6284 }
6285 } else {
6286 if (intel_crtc->active) {
6287 intel_crtc_disable_planes(crtc);
6288 dev_priv->display.crtc_disable(crtc);
6289
6290 domains = intel_crtc->enabled_power_domains;
6291 for_each_power_domain(domain, domains)
6292 intel_display_power_put(dev_priv, domain);
6293 intel_crtc->enabled_power_domains = 0;
6294 }
6295 }
6296 }
6297
6298 /**
6299 * Sets the power management mode of the pipe and plane.
6300 */
6301 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6302 {
6303 struct drm_device *dev = crtc->dev;
6304 struct intel_encoder *intel_encoder;
6305 bool enable = false;
6306
6307 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6308 enable |= intel_encoder->connectors_active;
6309
6310 intel_crtc_control(crtc, enable);
6311
6312 crtc->state->active = enable;
6313 }
6314
6315 static void intel_crtc_disable(struct drm_crtc *crtc)
6316 {
6317 struct drm_device *dev = crtc->dev;
6318 struct drm_connector *connector;
6319 struct drm_i915_private *dev_priv = dev->dev_private;
6320
6321 /* crtc should still be enabled when we disable it. */
6322 WARN_ON(!crtc->state->enable);
6323
6324 intel_crtc_disable_planes(crtc);
6325 dev_priv->display.crtc_disable(crtc);
6326 dev_priv->display.off(crtc);
6327
6328 drm_plane_helper_disable(crtc->primary);
6329
6330 /* Update computed state. */
6331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6332 if (!connector->encoder || !connector->encoder->crtc)
6333 continue;
6334
6335 if (connector->encoder->crtc != crtc)
6336 continue;
6337
6338 connector->dpms = DRM_MODE_DPMS_OFF;
6339 to_intel_encoder(connector->encoder)->connectors_active = false;
6340 }
6341 }
6342
6343 void intel_encoder_destroy(struct drm_encoder *encoder)
6344 {
6345 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6346
6347 drm_encoder_cleanup(encoder);
6348 kfree(intel_encoder);
6349 }
6350
6351 /* Simple dpms helper for encoders with just one connector, no cloning and only
6352 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6353 * state of the entire output pipe. */
6354 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6355 {
6356 if (mode == DRM_MODE_DPMS_ON) {
6357 encoder->connectors_active = true;
6358
6359 intel_crtc_update_dpms(encoder->base.crtc);
6360 } else {
6361 encoder->connectors_active = false;
6362
6363 intel_crtc_update_dpms(encoder->base.crtc);
6364 }
6365 }
6366
6367 /* Cross check the actual hw state with our own modeset state tracking (and it's
6368 * internal consistency). */
6369 static void intel_connector_check_state(struct intel_connector *connector)
6370 {
6371 if (connector->get_hw_state(connector)) {
6372 struct intel_encoder *encoder = connector->encoder;
6373 struct drm_crtc *crtc;
6374 bool encoder_enabled;
6375 enum pipe pipe;
6376
6377 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6378 connector->base.base.id,
6379 connector->base.name);
6380
6381 /* there is no real hw state for MST connectors */
6382 if (connector->mst_port)
6383 return;
6384
6385 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6386 "wrong connector dpms state\n");
6387 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6388 "active connector not linked to encoder\n");
6389
6390 if (encoder) {
6391 I915_STATE_WARN(!encoder->connectors_active,
6392 "encoder->connectors_active not set\n");
6393
6394 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6395 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6396 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6397 return;
6398
6399 crtc = encoder->base.crtc;
6400
6401 I915_STATE_WARN(!crtc->state->enable,
6402 "crtc not enabled\n");
6403 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6404 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6405 "encoder active on the wrong pipe\n");
6406 }
6407 }
6408 }
6409
6410 int intel_connector_init(struct intel_connector *connector)
6411 {
6412 struct drm_connector_state *connector_state;
6413
6414 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6415 if (!connector_state)
6416 return -ENOMEM;
6417
6418 connector->base.state = connector_state;
6419 return 0;
6420 }
6421
6422 struct intel_connector *intel_connector_alloc(void)
6423 {
6424 struct intel_connector *connector;
6425
6426 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6427 if (!connector)
6428 return NULL;
6429
6430 if (intel_connector_init(connector) < 0) {
6431 kfree(connector);
6432 return NULL;
6433 }
6434
6435 return connector;
6436 }
6437
6438 /* Even simpler default implementation, if there's really no special case to
6439 * consider. */
6440 void intel_connector_dpms(struct drm_connector *connector, int mode)
6441 {
6442 /* All the simple cases only support two dpms states. */
6443 if (mode != DRM_MODE_DPMS_ON)
6444 mode = DRM_MODE_DPMS_OFF;
6445
6446 if (mode == connector->dpms)
6447 return;
6448
6449 connector->dpms = mode;
6450
6451 /* Only need to change hw state when actually enabled */
6452 if (connector->encoder)
6453 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6454
6455 intel_modeset_check_state(connector->dev);
6456 }
6457
6458 /* Simple connector->get_hw_state implementation for encoders that support only
6459 * one connector and no cloning and hence the encoder state determines the state
6460 * of the connector. */
6461 bool intel_connector_get_hw_state(struct intel_connector *connector)
6462 {
6463 enum pipe pipe = 0;
6464 struct intel_encoder *encoder = connector->encoder;
6465
6466 return encoder->get_hw_state(encoder, &pipe);
6467 }
6468
6469 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6470 {
6471 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6472 return crtc_state->fdi_lanes;
6473
6474 return 0;
6475 }
6476
6477 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6478 struct intel_crtc_state *pipe_config)
6479 {
6480 struct drm_atomic_state *state = pipe_config->base.state;
6481 struct intel_crtc *other_crtc;
6482 struct intel_crtc_state *other_crtc_state;
6483
6484 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6485 pipe_name(pipe), pipe_config->fdi_lanes);
6486 if (pipe_config->fdi_lanes > 4) {
6487 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6488 pipe_name(pipe), pipe_config->fdi_lanes);
6489 return -EINVAL;
6490 }
6491
6492 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6493 if (pipe_config->fdi_lanes > 2) {
6494 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6495 pipe_config->fdi_lanes);
6496 return -EINVAL;
6497 } else {
6498 return 0;
6499 }
6500 }
6501
6502 if (INTEL_INFO(dev)->num_pipes == 2)
6503 return 0;
6504
6505 /* Ivybridge 3 pipe is really complicated */
6506 switch (pipe) {
6507 case PIPE_A:
6508 return 0;
6509 case PIPE_B:
6510 if (pipe_config->fdi_lanes <= 2)
6511 return 0;
6512
6513 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6514 other_crtc_state =
6515 intel_atomic_get_crtc_state(state, other_crtc);
6516 if (IS_ERR(other_crtc_state))
6517 return PTR_ERR(other_crtc_state);
6518
6519 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6520 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6521 pipe_name(pipe), pipe_config->fdi_lanes);
6522 return -EINVAL;
6523 }
6524 return 0;
6525 case PIPE_C:
6526 if (pipe_config->fdi_lanes > 2) {
6527 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6528 pipe_name(pipe), pipe_config->fdi_lanes);
6529 return -EINVAL;
6530 }
6531
6532 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6533 other_crtc_state =
6534 intel_atomic_get_crtc_state(state, other_crtc);
6535 if (IS_ERR(other_crtc_state))
6536 return PTR_ERR(other_crtc_state);
6537
6538 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6539 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6540 return -EINVAL;
6541 }
6542 return 0;
6543 default:
6544 BUG();
6545 }
6546 }
6547
6548 #define RETRY 1
6549 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6550 struct intel_crtc_state *pipe_config)
6551 {
6552 struct drm_device *dev = intel_crtc->base.dev;
6553 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6554 int lane, link_bw, fdi_dotclock, ret;
6555 bool needs_recompute = false;
6556
6557 retry:
6558 /* FDI is a binary signal running at ~2.7GHz, encoding
6559 * each output octet as 10 bits. The actual frequency
6560 * is stored as a divider into a 100MHz clock, and the
6561 * mode pixel clock is stored in units of 1KHz.
6562 * Hence the bw of each lane in terms of the mode signal
6563 * is:
6564 */
6565 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6566
6567 fdi_dotclock = adjusted_mode->crtc_clock;
6568
6569 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6570 pipe_config->pipe_bpp);
6571
6572 pipe_config->fdi_lanes = lane;
6573
6574 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6575 link_bw, &pipe_config->fdi_m_n);
6576
6577 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6578 intel_crtc->pipe, pipe_config);
6579 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6580 pipe_config->pipe_bpp -= 2*3;
6581 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6582 pipe_config->pipe_bpp);
6583 needs_recompute = true;
6584 pipe_config->bw_constrained = true;
6585
6586 goto retry;
6587 }
6588
6589 if (needs_recompute)
6590 return RETRY;
6591
6592 return ret;
6593 }
6594
6595 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6596 struct intel_crtc_state *pipe_config)
6597 {
6598 pipe_config->ips_enabled = i915.enable_ips &&
6599 hsw_crtc_supports_ips(crtc) &&
6600 pipe_config->pipe_bpp <= 24;
6601 }
6602
6603 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6604 struct intel_crtc_state *pipe_config)
6605 {
6606 struct drm_device *dev = crtc->base.dev;
6607 struct drm_i915_private *dev_priv = dev->dev_private;
6608 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6609 int ret;
6610
6611 /* FIXME should check pixel clock limits on all platforms */
6612 if (INTEL_INFO(dev)->gen < 4) {
6613 int clock_limit =
6614 dev_priv->display.get_display_clock_speed(dev);
6615
6616 /*
6617 * Enable pixel doubling when the dot clock
6618 * is > 90% of the (display) core speed.
6619 *
6620 * GDG double wide on either pipe,
6621 * otherwise pipe A only.
6622 */
6623 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6624 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6625 clock_limit *= 2;
6626 pipe_config->double_wide = true;
6627 }
6628
6629 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6630 return -EINVAL;
6631 }
6632
6633 /*
6634 * Pipe horizontal size must be even in:
6635 * - DVO ganged mode
6636 * - LVDS dual channel mode
6637 * - Double wide pipe
6638 */
6639 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6640 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6641 pipe_config->pipe_src_w &= ~1;
6642
6643 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6644 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6645 */
6646 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6647 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6648 return -EINVAL;
6649
6650 if (HAS_IPS(dev))
6651 hsw_compute_ips_config(crtc, pipe_config);
6652
6653 if (pipe_config->has_pch_encoder)
6654 return ironlake_fdi_compute_config(crtc, pipe_config);
6655
6656 /* FIXME: remove below call once atomic mode set is place and all crtc
6657 * related checks called from atomic_crtc_check function */
6658 ret = 0;
6659 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6660 crtc, pipe_config->base.state);
6661 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6662
6663 return ret;
6664 }
6665
6666 static int skylake_get_display_clock_speed(struct drm_device *dev)
6667 {
6668 struct drm_i915_private *dev_priv = to_i915(dev);
6669 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6670 uint32_t cdctl = I915_READ(CDCLK_CTL);
6671 uint32_t linkrate;
6672
6673 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6674 WARN(1, "LCPLL1 not enabled\n");
6675 return 24000; /* 24MHz is the cd freq with NSSC ref */
6676 }
6677
6678 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6679 return 540000;
6680
6681 linkrate = (I915_READ(DPLL_CTRL1) &
6682 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6683
6684 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6685 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6686 /* vco 8640 */
6687 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6688 case CDCLK_FREQ_450_432:
6689 return 432000;
6690 case CDCLK_FREQ_337_308:
6691 return 308570;
6692 case CDCLK_FREQ_675_617:
6693 return 617140;
6694 default:
6695 WARN(1, "Unknown cd freq selection\n");
6696 }
6697 } else {
6698 /* vco 8100 */
6699 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6700 case CDCLK_FREQ_450_432:
6701 return 450000;
6702 case CDCLK_FREQ_337_308:
6703 return 337500;
6704 case CDCLK_FREQ_675_617:
6705 return 675000;
6706 default:
6707 WARN(1, "Unknown cd freq selection\n");
6708 }
6709 }
6710
6711 /* error case, do as if DPLL0 isn't enabled */
6712 return 24000;
6713 }
6714
6715 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6716 {
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718 uint32_t lcpll = I915_READ(LCPLL_CTL);
6719 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6720
6721 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6722 return 800000;
6723 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6724 return 450000;
6725 else if (freq == LCPLL_CLK_FREQ_450)
6726 return 450000;
6727 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6728 return 540000;
6729 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6730 return 337500;
6731 else
6732 return 675000;
6733 }
6734
6735 static int haswell_get_display_clock_speed(struct drm_device *dev)
6736 {
6737 struct drm_i915_private *dev_priv = dev->dev_private;
6738 uint32_t lcpll = I915_READ(LCPLL_CTL);
6739 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6740
6741 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6742 return 800000;
6743 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6744 return 450000;
6745 else if (freq == LCPLL_CLK_FREQ_450)
6746 return 450000;
6747 else if (IS_HSW_ULT(dev))
6748 return 337500;
6749 else
6750 return 540000;
6751 }
6752
6753 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6754 {
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756 u32 val;
6757 int divider;
6758
6759 if (dev_priv->hpll_freq == 0)
6760 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6761
6762 mutex_lock(&dev_priv->sb_lock);
6763 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6764 mutex_unlock(&dev_priv->sb_lock);
6765
6766 divider = val & DISPLAY_FREQUENCY_VALUES;
6767
6768 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6769 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6770 "cdclk change in progress\n");
6771
6772 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6773 }
6774
6775 static int ilk_get_display_clock_speed(struct drm_device *dev)
6776 {
6777 return 450000;
6778 }
6779
6780 static int i945_get_display_clock_speed(struct drm_device *dev)
6781 {
6782 return 400000;
6783 }
6784
6785 static int i915_get_display_clock_speed(struct drm_device *dev)
6786 {
6787 return 333333;
6788 }
6789
6790 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6791 {
6792 return 200000;
6793 }
6794
6795 static int pnv_get_display_clock_speed(struct drm_device *dev)
6796 {
6797 u16 gcfgc = 0;
6798
6799 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6800
6801 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6802 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6803 return 266667;
6804 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6805 return 333333;
6806 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6807 return 444444;
6808 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6809 return 200000;
6810 default:
6811 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6812 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6813 return 133333;
6814 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6815 return 166667;
6816 }
6817 }
6818
6819 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6820 {
6821 u16 gcfgc = 0;
6822
6823 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6824
6825 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6826 return 133333;
6827 else {
6828 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6829 case GC_DISPLAY_CLOCK_333_MHZ:
6830 return 333333;
6831 default:
6832 case GC_DISPLAY_CLOCK_190_200_MHZ:
6833 return 190000;
6834 }
6835 }
6836 }
6837
6838 static int i865_get_display_clock_speed(struct drm_device *dev)
6839 {
6840 return 266667;
6841 }
6842
6843 static int i85x_get_display_clock_speed(struct drm_device *dev)
6844 {
6845 u16 hpllcc = 0;
6846
6847 /*
6848 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6849 * encoding is different :(
6850 * FIXME is this the right way to detect 852GM/852GMV?
6851 */
6852 if (dev->pdev->revision == 0x1)
6853 return 133333;
6854
6855 pci_bus_read_config_word(dev->pdev->bus,
6856 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6857
6858 /* Assume that the hardware is in the high speed state. This
6859 * should be the default.
6860 */
6861 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6862 case GC_CLOCK_133_200:
6863 case GC_CLOCK_133_200_2:
6864 case GC_CLOCK_100_200:
6865 return 200000;
6866 case GC_CLOCK_166_250:
6867 return 250000;
6868 case GC_CLOCK_100_133:
6869 return 133333;
6870 case GC_CLOCK_133_266:
6871 case GC_CLOCK_133_266_2:
6872 case GC_CLOCK_166_266:
6873 return 266667;
6874 }
6875
6876 /* Shouldn't happen */
6877 return 0;
6878 }
6879
6880 static int i830_get_display_clock_speed(struct drm_device *dev)
6881 {
6882 return 133333;
6883 }
6884
6885 static unsigned int intel_hpll_vco(struct drm_device *dev)
6886 {
6887 struct drm_i915_private *dev_priv = dev->dev_private;
6888 static const unsigned int blb_vco[8] = {
6889 [0] = 3200000,
6890 [1] = 4000000,
6891 [2] = 5333333,
6892 [3] = 4800000,
6893 [4] = 6400000,
6894 };
6895 static const unsigned int pnv_vco[8] = {
6896 [0] = 3200000,
6897 [1] = 4000000,
6898 [2] = 5333333,
6899 [3] = 4800000,
6900 [4] = 2666667,
6901 };
6902 static const unsigned int cl_vco[8] = {
6903 [0] = 3200000,
6904 [1] = 4000000,
6905 [2] = 5333333,
6906 [3] = 6400000,
6907 [4] = 3333333,
6908 [5] = 3566667,
6909 [6] = 4266667,
6910 };
6911 static const unsigned int elk_vco[8] = {
6912 [0] = 3200000,
6913 [1] = 4000000,
6914 [2] = 5333333,
6915 [3] = 4800000,
6916 };
6917 static const unsigned int ctg_vco[8] = {
6918 [0] = 3200000,
6919 [1] = 4000000,
6920 [2] = 5333333,
6921 [3] = 6400000,
6922 [4] = 2666667,
6923 [5] = 4266667,
6924 };
6925 const unsigned int *vco_table;
6926 unsigned int vco;
6927 uint8_t tmp = 0;
6928
6929 /* FIXME other chipsets? */
6930 if (IS_GM45(dev))
6931 vco_table = ctg_vco;
6932 else if (IS_G4X(dev))
6933 vco_table = elk_vco;
6934 else if (IS_CRESTLINE(dev))
6935 vco_table = cl_vco;
6936 else if (IS_PINEVIEW(dev))
6937 vco_table = pnv_vco;
6938 else if (IS_G33(dev))
6939 vco_table = blb_vco;
6940 else
6941 return 0;
6942
6943 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6944
6945 vco = vco_table[tmp & 0x7];
6946 if (vco == 0)
6947 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6948 else
6949 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6950
6951 return vco;
6952 }
6953
6954 static int gm45_get_display_clock_speed(struct drm_device *dev)
6955 {
6956 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6957 uint16_t tmp = 0;
6958
6959 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6960
6961 cdclk_sel = (tmp >> 12) & 0x1;
6962
6963 switch (vco) {
6964 case 2666667:
6965 case 4000000:
6966 case 5333333:
6967 return cdclk_sel ? 333333 : 222222;
6968 case 3200000:
6969 return cdclk_sel ? 320000 : 228571;
6970 default:
6971 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6972 return 222222;
6973 }
6974 }
6975
6976 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6977 {
6978 static const uint8_t div_3200[] = { 16, 10, 8 };
6979 static const uint8_t div_4000[] = { 20, 12, 10 };
6980 static const uint8_t div_5333[] = { 24, 16, 14 };
6981 const uint8_t *div_table;
6982 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6983 uint16_t tmp = 0;
6984
6985 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6986
6987 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6988
6989 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6990 goto fail;
6991
6992 switch (vco) {
6993 case 3200000:
6994 div_table = div_3200;
6995 break;
6996 case 4000000:
6997 div_table = div_4000;
6998 break;
6999 case 5333333:
7000 div_table = div_5333;
7001 break;
7002 default:
7003 goto fail;
7004 }
7005
7006 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7007
7008 fail:
7009 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7010 return 200000;
7011 }
7012
7013 static int g33_get_display_clock_speed(struct drm_device *dev)
7014 {
7015 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7016 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7017 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7018 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7019 const uint8_t *div_table;
7020 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7021 uint16_t tmp = 0;
7022
7023 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7024
7025 cdclk_sel = (tmp >> 4) & 0x7;
7026
7027 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7028 goto fail;
7029
7030 switch (vco) {
7031 case 3200000:
7032 div_table = div_3200;
7033 break;
7034 case 4000000:
7035 div_table = div_4000;
7036 break;
7037 case 4800000:
7038 div_table = div_4800;
7039 break;
7040 case 5333333:
7041 div_table = div_5333;
7042 break;
7043 default:
7044 goto fail;
7045 }
7046
7047 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7048
7049 fail:
7050 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7051 return 190476;
7052 }
7053
7054 static void
7055 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7056 {
7057 while (*num > DATA_LINK_M_N_MASK ||
7058 *den > DATA_LINK_M_N_MASK) {
7059 *num >>= 1;
7060 *den >>= 1;
7061 }
7062 }
7063
7064 static void compute_m_n(unsigned int m, unsigned int n,
7065 uint32_t *ret_m, uint32_t *ret_n)
7066 {
7067 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7068 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7069 intel_reduce_m_n_ratio(ret_m, ret_n);
7070 }
7071
7072 void
7073 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7074 int pixel_clock, int link_clock,
7075 struct intel_link_m_n *m_n)
7076 {
7077 m_n->tu = 64;
7078
7079 compute_m_n(bits_per_pixel * pixel_clock,
7080 link_clock * nlanes * 8,
7081 &m_n->gmch_m, &m_n->gmch_n);
7082
7083 compute_m_n(pixel_clock, link_clock,
7084 &m_n->link_m, &m_n->link_n);
7085 }
7086
7087 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7088 {
7089 if (i915.panel_use_ssc >= 0)
7090 return i915.panel_use_ssc != 0;
7091 return dev_priv->vbt.lvds_use_ssc
7092 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7093 }
7094
7095 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7096 int num_connectors)
7097 {
7098 struct drm_device *dev = crtc_state->base.crtc->dev;
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 int refclk;
7101
7102 WARN_ON(!crtc_state->base.state);
7103
7104 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7105 refclk = 100000;
7106 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7107 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7108 refclk = dev_priv->vbt.lvds_ssc_freq;
7109 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7110 } else if (!IS_GEN2(dev)) {
7111 refclk = 96000;
7112 } else {
7113 refclk = 48000;
7114 }
7115
7116 return refclk;
7117 }
7118
7119 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7120 {
7121 return (1 << dpll->n) << 16 | dpll->m2;
7122 }
7123
7124 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7125 {
7126 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7127 }
7128
7129 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7130 struct intel_crtc_state *crtc_state,
7131 intel_clock_t *reduced_clock)
7132 {
7133 struct drm_device *dev = crtc->base.dev;
7134 u32 fp, fp2 = 0;
7135
7136 if (IS_PINEVIEW(dev)) {
7137 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7138 if (reduced_clock)
7139 fp2 = pnv_dpll_compute_fp(reduced_clock);
7140 } else {
7141 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7142 if (reduced_clock)
7143 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7144 }
7145
7146 crtc_state->dpll_hw_state.fp0 = fp;
7147
7148 crtc->lowfreq_avail = false;
7149 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7150 reduced_clock) {
7151 crtc_state->dpll_hw_state.fp1 = fp2;
7152 crtc->lowfreq_avail = true;
7153 } else {
7154 crtc_state->dpll_hw_state.fp1 = fp;
7155 }
7156 }
7157
7158 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7159 pipe)
7160 {
7161 u32 reg_val;
7162
7163 /*
7164 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7165 * and set it to a reasonable value instead.
7166 */
7167 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7168 reg_val &= 0xffffff00;
7169 reg_val |= 0x00000030;
7170 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7171
7172 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7173 reg_val &= 0x8cffffff;
7174 reg_val = 0x8c000000;
7175 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7176
7177 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7178 reg_val &= 0xffffff00;
7179 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7180
7181 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7182 reg_val &= 0x00ffffff;
7183 reg_val |= 0xb0000000;
7184 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7185 }
7186
7187 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7188 struct intel_link_m_n *m_n)
7189 {
7190 struct drm_device *dev = crtc->base.dev;
7191 struct drm_i915_private *dev_priv = dev->dev_private;
7192 int pipe = crtc->pipe;
7193
7194 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7195 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7196 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7197 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7198 }
7199
7200 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7201 struct intel_link_m_n *m_n,
7202 struct intel_link_m_n *m2_n2)
7203 {
7204 struct drm_device *dev = crtc->base.dev;
7205 struct drm_i915_private *dev_priv = dev->dev_private;
7206 int pipe = crtc->pipe;
7207 enum transcoder transcoder = crtc->config->cpu_transcoder;
7208
7209 if (INTEL_INFO(dev)->gen >= 5) {
7210 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7211 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7212 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7213 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7214 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7215 * for gen < 8) and if DRRS is supported (to make sure the
7216 * registers are not unnecessarily accessed).
7217 */
7218 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7219 crtc->config->has_drrs) {
7220 I915_WRITE(PIPE_DATA_M2(transcoder),
7221 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7222 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7223 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7224 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7225 }
7226 } else {
7227 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7228 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7229 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7230 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7231 }
7232 }
7233
7234 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7235 {
7236 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7237
7238 if (m_n == M1_N1) {
7239 dp_m_n = &crtc->config->dp_m_n;
7240 dp_m2_n2 = &crtc->config->dp_m2_n2;
7241 } else if (m_n == M2_N2) {
7242
7243 /*
7244 * M2_N2 registers are not supported. Hence m2_n2 divider value
7245 * needs to be programmed into M1_N1.
7246 */
7247 dp_m_n = &crtc->config->dp_m2_n2;
7248 } else {
7249 DRM_ERROR("Unsupported divider value\n");
7250 return;
7251 }
7252
7253 if (crtc->config->has_pch_encoder)
7254 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7255 else
7256 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7257 }
7258
7259 static void vlv_update_pll(struct intel_crtc *crtc,
7260 struct intel_crtc_state *pipe_config)
7261 {
7262 u32 dpll, dpll_md;
7263
7264 /*
7265 * Enable DPIO clock input. We should never disable the reference
7266 * clock for pipe B, since VGA hotplug / manual detection depends
7267 * on it.
7268 */
7269 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7270 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7271 /* We should never disable this, set it here for state tracking */
7272 if (crtc->pipe == PIPE_B)
7273 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7274 dpll |= DPLL_VCO_ENABLE;
7275 pipe_config->dpll_hw_state.dpll = dpll;
7276
7277 dpll_md = (pipe_config->pixel_multiplier - 1)
7278 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7279 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7280 }
7281
7282 static void vlv_prepare_pll(struct intel_crtc *crtc,
7283 const struct intel_crtc_state *pipe_config)
7284 {
7285 struct drm_device *dev = crtc->base.dev;
7286 struct drm_i915_private *dev_priv = dev->dev_private;
7287 int pipe = crtc->pipe;
7288 u32 mdiv;
7289 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7290 u32 coreclk, reg_val;
7291
7292 mutex_lock(&dev_priv->sb_lock);
7293
7294 bestn = pipe_config->dpll.n;
7295 bestm1 = pipe_config->dpll.m1;
7296 bestm2 = pipe_config->dpll.m2;
7297 bestp1 = pipe_config->dpll.p1;
7298 bestp2 = pipe_config->dpll.p2;
7299
7300 /* See eDP HDMI DPIO driver vbios notes doc */
7301
7302 /* PLL B needs special handling */
7303 if (pipe == PIPE_B)
7304 vlv_pllb_recal_opamp(dev_priv, pipe);
7305
7306 /* Set up Tx target for periodic Rcomp update */
7307 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7308
7309 /* Disable target IRef on PLL */
7310 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7311 reg_val &= 0x00ffffff;
7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7313
7314 /* Disable fast lock */
7315 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7316
7317 /* Set idtafcrecal before PLL is enabled */
7318 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7319 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7320 mdiv |= ((bestn << DPIO_N_SHIFT));
7321 mdiv |= (1 << DPIO_K_SHIFT);
7322
7323 /*
7324 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7325 * but we don't support that).
7326 * Note: don't use the DAC post divider as it seems unstable.
7327 */
7328 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7330
7331 mdiv |= DPIO_ENABLE_CALIBRATION;
7332 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7333
7334 /* Set HBR and RBR LPF coefficients */
7335 if (pipe_config->port_clock == 162000 ||
7336 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7337 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7338 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7339 0x009f0003);
7340 else
7341 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7342 0x00d0000f);
7343
7344 if (pipe_config->has_dp_encoder) {
7345 /* Use SSC source */
7346 if (pipe == PIPE_A)
7347 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7348 0x0df40000);
7349 else
7350 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7351 0x0df70000);
7352 } else { /* HDMI or VGA */
7353 /* Use bend source */
7354 if (pipe == PIPE_A)
7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7356 0x0df70000);
7357 else
7358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7359 0x0df40000);
7360 }
7361
7362 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7363 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7365 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7366 coreclk |= 0x01000000;
7367 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7368
7369 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7370 mutex_unlock(&dev_priv->sb_lock);
7371 }
7372
7373 static void chv_update_pll(struct intel_crtc *crtc,
7374 struct intel_crtc_state *pipe_config)
7375 {
7376 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7377 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7378 DPLL_VCO_ENABLE;
7379 if (crtc->pipe != PIPE_A)
7380 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7381
7382 pipe_config->dpll_hw_state.dpll_md =
7383 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7384 }
7385
7386 static void chv_prepare_pll(struct intel_crtc *crtc,
7387 const struct intel_crtc_state *pipe_config)
7388 {
7389 struct drm_device *dev = crtc->base.dev;
7390 struct drm_i915_private *dev_priv = dev->dev_private;
7391 int pipe = crtc->pipe;
7392 int dpll_reg = DPLL(crtc->pipe);
7393 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7394 u32 loopfilter, tribuf_calcntr;
7395 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7396 u32 dpio_val;
7397 int vco;
7398
7399 bestn = pipe_config->dpll.n;
7400 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7401 bestm1 = pipe_config->dpll.m1;
7402 bestm2 = pipe_config->dpll.m2 >> 22;
7403 bestp1 = pipe_config->dpll.p1;
7404 bestp2 = pipe_config->dpll.p2;
7405 vco = pipe_config->dpll.vco;
7406 dpio_val = 0;
7407 loopfilter = 0;
7408
7409 /*
7410 * Enable Refclk and SSC
7411 */
7412 I915_WRITE(dpll_reg,
7413 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7414
7415 mutex_lock(&dev_priv->sb_lock);
7416
7417 /* p1 and p2 divider */
7418 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7419 5 << DPIO_CHV_S1_DIV_SHIFT |
7420 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7421 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7422 1 << DPIO_CHV_K_DIV_SHIFT);
7423
7424 /* Feedback post-divider - m2 */
7425 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7426
7427 /* Feedback refclk divider - n and m1 */
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7429 DPIO_CHV_M1_DIV_BY_2 |
7430 1 << DPIO_CHV_N_DIV_SHIFT);
7431
7432 /* M2 fraction division */
7433 if (bestm2_frac)
7434 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7435
7436 /* M2 fraction division enable */
7437 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7438 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7439 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7440 if (bestm2_frac)
7441 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7442 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7443
7444 /* Program digital lock detect threshold */
7445 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7446 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7447 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7448 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7449 if (!bestm2_frac)
7450 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7451 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7452
7453 /* Loop filter */
7454 if (vco == 5400000) {
7455 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7456 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7457 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7458 tribuf_calcntr = 0x9;
7459 } else if (vco <= 6200000) {
7460 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7461 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7462 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7463 tribuf_calcntr = 0x9;
7464 } else if (vco <= 6480000) {
7465 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7466 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7467 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7468 tribuf_calcntr = 0x8;
7469 } else {
7470 /* Not supported. Apply the same limits as in the max case */
7471 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7472 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7473 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7474 tribuf_calcntr = 0;
7475 }
7476 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7477
7478 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7479 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7480 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7481 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7482
7483 /* AFC Recal */
7484 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7485 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7486 DPIO_AFC_RECAL);
7487
7488 mutex_unlock(&dev_priv->sb_lock);
7489 }
7490
7491 /**
7492 * vlv_force_pll_on - forcibly enable just the PLL
7493 * @dev_priv: i915 private structure
7494 * @pipe: pipe PLL to enable
7495 * @dpll: PLL configuration
7496 *
7497 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7498 * in cases where we need the PLL enabled even when @pipe is not going to
7499 * be enabled.
7500 */
7501 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7502 const struct dpll *dpll)
7503 {
7504 struct intel_crtc *crtc =
7505 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7506 struct intel_crtc_state pipe_config = {
7507 .base.crtc = &crtc->base,
7508 .pixel_multiplier = 1,
7509 .dpll = *dpll,
7510 };
7511
7512 if (IS_CHERRYVIEW(dev)) {
7513 chv_update_pll(crtc, &pipe_config);
7514 chv_prepare_pll(crtc, &pipe_config);
7515 chv_enable_pll(crtc, &pipe_config);
7516 } else {
7517 vlv_update_pll(crtc, &pipe_config);
7518 vlv_prepare_pll(crtc, &pipe_config);
7519 vlv_enable_pll(crtc, &pipe_config);
7520 }
7521 }
7522
7523 /**
7524 * vlv_force_pll_off - forcibly disable just the PLL
7525 * @dev_priv: i915 private structure
7526 * @pipe: pipe PLL to disable
7527 *
7528 * Disable the PLL for @pipe. To be used in cases where we need
7529 * the PLL enabled even when @pipe is not going to be enabled.
7530 */
7531 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7532 {
7533 if (IS_CHERRYVIEW(dev))
7534 chv_disable_pll(to_i915(dev), pipe);
7535 else
7536 vlv_disable_pll(to_i915(dev), pipe);
7537 }
7538
7539 static void i9xx_update_pll(struct intel_crtc *crtc,
7540 struct intel_crtc_state *crtc_state,
7541 intel_clock_t *reduced_clock,
7542 int num_connectors)
7543 {
7544 struct drm_device *dev = crtc->base.dev;
7545 struct drm_i915_private *dev_priv = dev->dev_private;
7546 u32 dpll;
7547 bool is_sdvo;
7548 struct dpll *clock = &crtc_state->dpll;
7549
7550 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7551
7552 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7553 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7554
7555 dpll = DPLL_VGA_MODE_DIS;
7556
7557 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7558 dpll |= DPLLB_MODE_LVDS;
7559 else
7560 dpll |= DPLLB_MODE_DAC_SERIAL;
7561
7562 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7563 dpll |= (crtc_state->pixel_multiplier - 1)
7564 << SDVO_MULTIPLIER_SHIFT_HIRES;
7565 }
7566
7567 if (is_sdvo)
7568 dpll |= DPLL_SDVO_HIGH_SPEED;
7569
7570 if (crtc_state->has_dp_encoder)
7571 dpll |= DPLL_SDVO_HIGH_SPEED;
7572
7573 /* compute bitmask from p1 value */
7574 if (IS_PINEVIEW(dev))
7575 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7576 else {
7577 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7578 if (IS_G4X(dev) && reduced_clock)
7579 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7580 }
7581 switch (clock->p2) {
7582 case 5:
7583 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7584 break;
7585 case 7:
7586 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7587 break;
7588 case 10:
7589 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7590 break;
7591 case 14:
7592 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7593 break;
7594 }
7595 if (INTEL_INFO(dev)->gen >= 4)
7596 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7597
7598 if (crtc_state->sdvo_tv_clock)
7599 dpll |= PLL_REF_INPUT_TVCLKINBC;
7600 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7601 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7602 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7603 else
7604 dpll |= PLL_REF_INPUT_DREFCLK;
7605
7606 dpll |= DPLL_VCO_ENABLE;
7607 crtc_state->dpll_hw_state.dpll = dpll;
7608
7609 if (INTEL_INFO(dev)->gen >= 4) {
7610 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7611 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7612 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7613 }
7614 }
7615
7616 static void i8xx_update_pll(struct intel_crtc *crtc,
7617 struct intel_crtc_state *crtc_state,
7618 intel_clock_t *reduced_clock,
7619 int num_connectors)
7620 {
7621 struct drm_device *dev = crtc->base.dev;
7622 struct drm_i915_private *dev_priv = dev->dev_private;
7623 u32 dpll;
7624 struct dpll *clock = &crtc_state->dpll;
7625
7626 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7627
7628 dpll = DPLL_VGA_MODE_DIS;
7629
7630 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7631 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7632 } else {
7633 if (clock->p1 == 2)
7634 dpll |= PLL_P1_DIVIDE_BY_TWO;
7635 else
7636 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7637 if (clock->p2 == 4)
7638 dpll |= PLL_P2_DIVIDE_BY_4;
7639 }
7640
7641 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7642 dpll |= DPLL_DVO_2X_MODE;
7643
7644 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7645 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7646 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7647 else
7648 dpll |= PLL_REF_INPUT_DREFCLK;
7649
7650 dpll |= DPLL_VCO_ENABLE;
7651 crtc_state->dpll_hw_state.dpll = dpll;
7652 }
7653
7654 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7655 {
7656 struct drm_device *dev = intel_crtc->base.dev;
7657 struct drm_i915_private *dev_priv = dev->dev_private;
7658 enum pipe pipe = intel_crtc->pipe;
7659 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7660 struct drm_display_mode *adjusted_mode =
7661 &intel_crtc->config->base.adjusted_mode;
7662 uint32_t crtc_vtotal, crtc_vblank_end;
7663 int vsyncshift = 0;
7664
7665 /* We need to be careful not to changed the adjusted mode, for otherwise
7666 * the hw state checker will get angry at the mismatch. */
7667 crtc_vtotal = adjusted_mode->crtc_vtotal;
7668 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7669
7670 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7671 /* the chip adds 2 halflines automatically */
7672 crtc_vtotal -= 1;
7673 crtc_vblank_end -= 1;
7674
7675 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7676 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7677 else
7678 vsyncshift = adjusted_mode->crtc_hsync_start -
7679 adjusted_mode->crtc_htotal / 2;
7680 if (vsyncshift < 0)
7681 vsyncshift += adjusted_mode->crtc_htotal;
7682 }
7683
7684 if (INTEL_INFO(dev)->gen > 3)
7685 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7686
7687 I915_WRITE(HTOTAL(cpu_transcoder),
7688 (adjusted_mode->crtc_hdisplay - 1) |
7689 ((adjusted_mode->crtc_htotal - 1) << 16));
7690 I915_WRITE(HBLANK(cpu_transcoder),
7691 (adjusted_mode->crtc_hblank_start - 1) |
7692 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7693 I915_WRITE(HSYNC(cpu_transcoder),
7694 (adjusted_mode->crtc_hsync_start - 1) |
7695 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7696
7697 I915_WRITE(VTOTAL(cpu_transcoder),
7698 (adjusted_mode->crtc_vdisplay - 1) |
7699 ((crtc_vtotal - 1) << 16));
7700 I915_WRITE(VBLANK(cpu_transcoder),
7701 (adjusted_mode->crtc_vblank_start - 1) |
7702 ((crtc_vblank_end - 1) << 16));
7703 I915_WRITE(VSYNC(cpu_transcoder),
7704 (adjusted_mode->crtc_vsync_start - 1) |
7705 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7706
7707 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7708 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7709 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7710 * bits. */
7711 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7712 (pipe == PIPE_B || pipe == PIPE_C))
7713 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7714
7715 /* pipesrc controls the size that is scaled from, which should
7716 * always be the user's requested size.
7717 */
7718 I915_WRITE(PIPESRC(pipe),
7719 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7720 (intel_crtc->config->pipe_src_h - 1));
7721 }
7722
7723 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7724 struct intel_crtc_state *pipe_config)
7725 {
7726 struct drm_device *dev = crtc->base.dev;
7727 struct drm_i915_private *dev_priv = dev->dev_private;
7728 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7729 uint32_t tmp;
7730
7731 tmp = I915_READ(HTOTAL(cpu_transcoder));
7732 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7733 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7734 tmp = I915_READ(HBLANK(cpu_transcoder));
7735 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7736 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7737 tmp = I915_READ(HSYNC(cpu_transcoder));
7738 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7739 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7740
7741 tmp = I915_READ(VTOTAL(cpu_transcoder));
7742 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7743 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7744 tmp = I915_READ(VBLANK(cpu_transcoder));
7745 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7746 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7747 tmp = I915_READ(VSYNC(cpu_transcoder));
7748 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7749 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7750
7751 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7752 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7753 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7754 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7755 }
7756
7757 tmp = I915_READ(PIPESRC(crtc->pipe));
7758 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7759 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7760
7761 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7762 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7763 }
7764
7765 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7766 struct intel_crtc_state *pipe_config)
7767 {
7768 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7769 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7770 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7771 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7772
7773 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7774 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7775 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7776 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7777
7778 mode->flags = pipe_config->base.adjusted_mode.flags;
7779
7780 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7781 mode->flags |= pipe_config->base.adjusted_mode.flags;
7782 }
7783
7784 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7785 {
7786 struct drm_device *dev = intel_crtc->base.dev;
7787 struct drm_i915_private *dev_priv = dev->dev_private;
7788 uint32_t pipeconf;
7789
7790 pipeconf = 0;
7791
7792 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7793 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7794 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7795
7796 if (intel_crtc->config->double_wide)
7797 pipeconf |= PIPECONF_DOUBLE_WIDE;
7798
7799 /* only g4x and later have fancy bpc/dither controls */
7800 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7801 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7802 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7803 pipeconf |= PIPECONF_DITHER_EN |
7804 PIPECONF_DITHER_TYPE_SP;
7805
7806 switch (intel_crtc->config->pipe_bpp) {
7807 case 18:
7808 pipeconf |= PIPECONF_6BPC;
7809 break;
7810 case 24:
7811 pipeconf |= PIPECONF_8BPC;
7812 break;
7813 case 30:
7814 pipeconf |= PIPECONF_10BPC;
7815 break;
7816 default:
7817 /* Case prevented by intel_choose_pipe_bpp_dither. */
7818 BUG();
7819 }
7820 }
7821
7822 if (HAS_PIPE_CXSR(dev)) {
7823 if (intel_crtc->lowfreq_avail) {
7824 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7825 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7826 } else {
7827 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7828 }
7829 }
7830
7831 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7832 if (INTEL_INFO(dev)->gen < 4 ||
7833 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7834 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7835 else
7836 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7837 } else
7838 pipeconf |= PIPECONF_PROGRESSIVE;
7839
7840 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7841 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7842
7843 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7844 POSTING_READ(PIPECONF(intel_crtc->pipe));
7845 }
7846
7847 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7848 struct intel_crtc_state *crtc_state)
7849 {
7850 struct drm_device *dev = crtc->base.dev;
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852 int refclk, num_connectors = 0;
7853 intel_clock_t clock, reduced_clock;
7854 bool ok, has_reduced_clock = false;
7855 bool is_lvds = false, is_dsi = false;
7856 struct intel_encoder *encoder;
7857 const intel_limit_t *limit;
7858 struct drm_atomic_state *state = crtc_state->base.state;
7859 struct drm_connector *connector;
7860 struct drm_connector_state *connector_state;
7861 int i;
7862
7863 memset(&crtc_state->dpll_hw_state, 0,
7864 sizeof(crtc_state->dpll_hw_state));
7865
7866 for_each_connector_in_state(state, connector, connector_state, i) {
7867 if (connector_state->crtc != &crtc->base)
7868 continue;
7869
7870 encoder = to_intel_encoder(connector_state->best_encoder);
7871
7872 switch (encoder->type) {
7873 case INTEL_OUTPUT_LVDS:
7874 is_lvds = true;
7875 break;
7876 case INTEL_OUTPUT_DSI:
7877 is_dsi = true;
7878 break;
7879 default:
7880 break;
7881 }
7882
7883 num_connectors++;
7884 }
7885
7886 if (is_dsi)
7887 return 0;
7888
7889 if (!crtc_state->clock_set) {
7890 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7891
7892 /*
7893 * Returns a set of divisors for the desired target clock with
7894 * the given refclk, or FALSE. The returned values represent
7895 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7896 * 2) / p1 / p2.
7897 */
7898 limit = intel_limit(crtc_state, refclk);
7899 ok = dev_priv->display.find_dpll(limit, crtc_state,
7900 crtc_state->port_clock,
7901 refclk, NULL, &clock);
7902 if (!ok) {
7903 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7904 return -EINVAL;
7905 }
7906
7907 if (is_lvds && dev_priv->lvds_downclock_avail) {
7908 /*
7909 * Ensure we match the reduced clock's P to the target
7910 * clock. If the clocks don't match, we can't switch
7911 * the display clock by using the FP0/FP1. In such case
7912 * we will disable the LVDS downclock feature.
7913 */
7914 has_reduced_clock =
7915 dev_priv->display.find_dpll(limit, crtc_state,
7916 dev_priv->lvds_downclock,
7917 refclk, &clock,
7918 &reduced_clock);
7919 }
7920 /* Compat-code for transition, will disappear. */
7921 crtc_state->dpll.n = clock.n;
7922 crtc_state->dpll.m1 = clock.m1;
7923 crtc_state->dpll.m2 = clock.m2;
7924 crtc_state->dpll.p1 = clock.p1;
7925 crtc_state->dpll.p2 = clock.p2;
7926 }
7927
7928 if (IS_GEN2(dev)) {
7929 i8xx_update_pll(crtc, crtc_state,
7930 has_reduced_clock ? &reduced_clock : NULL,
7931 num_connectors);
7932 } else if (IS_CHERRYVIEW(dev)) {
7933 chv_update_pll(crtc, crtc_state);
7934 } else if (IS_VALLEYVIEW(dev)) {
7935 vlv_update_pll(crtc, crtc_state);
7936 } else {
7937 i9xx_update_pll(crtc, crtc_state,
7938 has_reduced_clock ? &reduced_clock : NULL,
7939 num_connectors);
7940 }
7941
7942 return 0;
7943 }
7944
7945 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7946 struct intel_crtc_state *pipe_config)
7947 {
7948 struct drm_device *dev = crtc->base.dev;
7949 struct drm_i915_private *dev_priv = dev->dev_private;
7950 uint32_t tmp;
7951
7952 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7953 return;
7954
7955 tmp = I915_READ(PFIT_CONTROL);
7956 if (!(tmp & PFIT_ENABLE))
7957 return;
7958
7959 /* Check whether the pfit is attached to our pipe. */
7960 if (INTEL_INFO(dev)->gen < 4) {
7961 if (crtc->pipe != PIPE_B)
7962 return;
7963 } else {
7964 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7965 return;
7966 }
7967
7968 pipe_config->gmch_pfit.control = tmp;
7969 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7970 if (INTEL_INFO(dev)->gen < 5)
7971 pipe_config->gmch_pfit.lvds_border_bits =
7972 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7973 }
7974
7975 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7976 struct intel_crtc_state *pipe_config)
7977 {
7978 struct drm_device *dev = crtc->base.dev;
7979 struct drm_i915_private *dev_priv = dev->dev_private;
7980 int pipe = pipe_config->cpu_transcoder;
7981 intel_clock_t clock;
7982 u32 mdiv;
7983 int refclk = 100000;
7984
7985 /* In case of MIPI DPLL will not even be used */
7986 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7987 return;
7988
7989 mutex_lock(&dev_priv->sb_lock);
7990 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7991 mutex_unlock(&dev_priv->sb_lock);
7992
7993 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7994 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7995 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7996 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7997 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7998
7999 vlv_clock(refclk, &clock);
8000
8001 /* clock.dot is the fast clock */
8002 pipe_config->port_clock = clock.dot / 5;
8003 }
8004
8005 static void
8006 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8007 struct intel_initial_plane_config *plane_config)
8008 {
8009 struct drm_device *dev = crtc->base.dev;
8010 struct drm_i915_private *dev_priv = dev->dev_private;
8011 u32 val, base, offset;
8012 int pipe = crtc->pipe, plane = crtc->plane;
8013 int fourcc, pixel_format;
8014 unsigned int aligned_height;
8015 struct drm_framebuffer *fb;
8016 struct intel_framebuffer *intel_fb;
8017
8018 val = I915_READ(DSPCNTR(plane));
8019 if (!(val & DISPLAY_PLANE_ENABLE))
8020 return;
8021
8022 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8023 if (!intel_fb) {
8024 DRM_DEBUG_KMS("failed to alloc fb\n");
8025 return;
8026 }
8027
8028 fb = &intel_fb->base;
8029
8030 if (INTEL_INFO(dev)->gen >= 4) {
8031 if (val & DISPPLANE_TILED) {
8032 plane_config->tiling = I915_TILING_X;
8033 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8034 }
8035 }
8036
8037 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8038 fourcc = i9xx_format_to_fourcc(pixel_format);
8039 fb->pixel_format = fourcc;
8040 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8041
8042 if (INTEL_INFO(dev)->gen >= 4) {
8043 if (plane_config->tiling)
8044 offset = I915_READ(DSPTILEOFF(plane));
8045 else
8046 offset = I915_READ(DSPLINOFF(plane));
8047 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8048 } else {
8049 base = I915_READ(DSPADDR(plane));
8050 }
8051 plane_config->base = base;
8052
8053 val = I915_READ(PIPESRC(pipe));
8054 fb->width = ((val >> 16) & 0xfff) + 1;
8055 fb->height = ((val >> 0) & 0xfff) + 1;
8056
8057 val = I915_READ(DSPSTRIDE(pipe));
8058 fb->pitches[0] = val & 0xffffffc0;
8059
8060 aligned_height = intel_fb_align_height(dev, fb->height,
8061 fb->pixel_format,
8062 fb->modifier[0]);
8063
8064 plane_config->size = fb->pitches[0] * aligned_height;
8065
8066 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8067 pipe_name(pipe), plane, fb->width, fb->height,
8068 fb->bits_per_pixel, base, fb->pitches[0],
8069 plane_config->size);
8070
8071 plane_config->fb = intel_fb;
8072 }
8073
8074 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8075 struct intel_crtc_state *pipe_config)
8076 {
8077 struct drm_device *dev = crtc->base.dev;
8078 struct drm_i915_private *dev_priv = dev->dev_private;
8079 int pipe = pipe_config->cpu_transcoder;
8080 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8081 intel_clock_t clock;
8082 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8083 int refclk = 100000;
8084
8085 mutex_lock(&dev_priv->sb_lock);
8086 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8087 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8088 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8089 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8090 mutex_unlock(&dev_priv->sb_lock);
8091
8092 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8093 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8094 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8095 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8096 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8097
8098 chv_clock(refclk, &clock);
8099
8100 /* clock.dot is the fast clock */
8101 pipe_config->port_clock = clock.dot / 5;
8102 }
8103
8104 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8105 struct intel_crtc_state *pipe_config)
8106 {
8107 struct drm_device *dev = crtc->base.dev;
8108 struct drm_i915_private *dev_priv = dev->dev_private;
8109 uint32_t tmp;
8110
8111 if (!intel_display_power_is_enabled(dev_priv,
8112 POWER_DOMAIN_PIPE(crtc->pipe)))
8113 return false;
8114
8115 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8116 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8117
8118 tmp = I915_READ(PIPECONF(crtc->pipe));
8119 if (!(tmp & PIPECONF_ENABLE))
8120 return false;
8121
8122 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8123 switch (tmp & PIPECONF_BPC_MASK) {
8124 case PIPECONF_6BPC:
8125 pipe_config->pipe_bpp = 18;
8126 break;
8127 case PIPECONF_8BPC:
8128 pipe_config->pipe_bpp = 24;
8129 break;
8130 case PIPECONF_10BPC:
8131 pipe_config->pipe_bpp = 30;
8132 break;
8133 default:
8134 break;
8135 }
8136 }
8137
8138 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8139 pipe_config->limited_color_range = true;
8140
8141 if (INTEL_INFO(dev)->gen < 4)
8142 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8143
8144 intel_get_pipe_timings(crtc, pipe_config);
8145
8146 i9xx_get_pfit_config(crtc, pipe_config);
8147
8148 if (INTEL_INFO(dev)->gen >= 4) {
8149 tmp = I915_READ(DPLL_MD(crtc->pipe));
8150 pipe_config->pixel_multiplier =
8151 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8152 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8153 pipe_config->dpll_hw_state.dpll_md = tmp;
8154 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8155 tmp = I915_READ(DPLL(crtc->pipe));
8156 pipe_config->pixel_multiplier =
8157 ((tmp & SDVO_MULTIPLIER_MASK)
8158 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8159 } else {
8160 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8161 * port and will be fixed up in the encoder->get_config
8162 * function. */
8163 pipe_config->pixel_multiplier = 1;
8164 }
8165 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8166 if (!IS_VALLEYVIEW(dev)) {
8167 /*
8168 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8169 * on 830. Filter it out here so that we don't
8170 * report errors due to that.
8171 */
8172 if (IS_I830(dev))
8173 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8174
8175 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8176 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8177 } else {
8178 /* Mask out read-only status bits. */
8179 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8180 DPLL_PORTC_READY_MASK |
8181 DPLL_PORTB_READY_MASK);
8182 }
8183
8184 if (IS_CHERRYVIEW(dev))
8185 chv_crtc_clock_get(crtc, pipe_config);
8186 else if (IS_VALLEYVIEW(dev))
8187 vlv_crtc_clock_get(crtc, pipe_config);
8188 else
8189 i9xx_crtc_clock_get(crtc, pipe_config);
8190
8191 return true;
8192 }
8193
8194 static void ironlake_init_pch_refclk(struct drm_device *dev)
8195 {
8196 struct drm_i915_private *dev_priv = dev->dev_private;
8197 struct intel_encoder *encoder;
8198 u32 val, final;
8199 bool has_lvds = false;
8200 bool has_cpu_edp = false;
8201 bool has_panel = false;
8202 bool has_ck505 = false;
8203 bool can_ssc = false;
8204
8205 /* We need to take the global config into account */
8206 for_each_intel_encoder(dev, encoder) {
8207 switch (encoder->type) {
8208 case INTEL_OUTPUT_LVDS:
8209 has_panel = true;
8210 has_lvds = true;
8211 break;
8212 case INTEL_OUTPUT_EDP:
8213 has_panel = true;
8214 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8215 has_cpu_edp = true;
8216 break;
8217 default:
8218 break;
8219 }
8220 }
8221
8222 if (HAS_PCH_IBX(dev)) {
8223 has_ck505 = dev_priv->vbt.display_clock_mode;
8224 can_ssc = has_ck505;
8225 } else {
8226 has_ck505 = false;
8227 can_ssc = true;
8228 }
8229
8230 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8231 has_panel, has_lvds, has_ck505);
8232
8233 /* Ironlake: try to setup display ref clock before DPLL
8234 * enabling. This is only under driver's control after
8235 * PCH B stepping, previous chipset stepping should be
8236 * ignoring this setting.
8237 */
8238 val = I915_READ(PCH_DREF_CONTROL);
8239
8240 /* As we must carefully and slowly disable/enable each source in turn,
8241 * compute the final state we want first and check if we need to
8242 * make any changes at all.
8243 */
8244 final = val;
8245 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8246 if (has_ck505)
8247 final |= DREF_NONSPREAD_CK505_ENABLE;
8248 else
8249 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8250
8251 final &= ~DREF_SSC_SOURCE_MASK;
8252 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8253 final &= ~DREF_SSC1_ENABLE;
8254
8255 if (has_panel) {
8256 final |= DREF_SSC_SOURCE_ENABLE;
8257
8258 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8259 final |= DREF_SSC1_ENABLE;
8260
8261 if (has_cpu_edp) {
8262 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8263 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8264 else
8265 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8266 } else
8267 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8268 } else {
8269 final |= DREF_SSC_SOURCE_DISABLE;
8270 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8271 }
8272
8273 if (final == val)
8274 return;
8275
8276 /* Always enable nonspread source */
8277 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8278
8279 if (has_ck505)
8280 val |= DREF_NONSPREAD_CK505_ENABLE;
8281 else
8282 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8283
8284 if (has_panel) {
8285 val &= ~DREF_SSC_SOURCE_MASK;
8286 val |= DREF_SSC_SOURCE_ENABLE;
8287
8288 /* SSC must be turned on before enabling the CPU output */
8289 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8290 DRM_DEBUG_KMS("Using SSC on panel\n");
8291 val |= DREF_SSC1_ENABLE;
8292 } else
8293 val &= ~DREF_SSC1_ENABLE;
8294
8295 /* Get SSC going before enabling the outputs */
8296 I915_WRITE(PCH_DREF_CONTROL, val);
8297 POSTING_READ(PCH_DREF_CONTROL);
8298 udelay(200);
8299
8300 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8301
8302 /* Enable CPU source on CPU attached eDP */
8303 if (has_cpu_edp) {
8304 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8305 DRM_DEBUG_KMS("Using SSC on eDP\n");
8306 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8307 } else
8308 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8309 } else
8310 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8311
8312 I915_WRITE(PCH_DREF_CONTROL, val);
8313 POSTING_READ(PCH_DREF_CONTROL);
8314 udelay(200);
8315 } else {
8316 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8317
8318 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8319
8320 /* Turn off CPU output */
8321 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8322
8323 I915_WRITE(PCH_DREF_CONTROL, val);
8324 POSTING_READ(PCH_DREF_CONTROL);
8325 udelay(200);
8326
8327 /* Turn off the SSC source */
8328 val &= ~DREF_SSC_SOURCE_MASK;
8329 val |= DREF_SSC_SOURCE_DISABLE;
8330
8331 /* Turn off SSC1 */
8332 val &= ~DREF_SSC1_ENABLE;
8333
8334 I915_WRITE(PCH_DREF_CONTROL, val);
8335 POSTING_READ(PCH_DREF_CONTROL);
8336 udelay(200);
8337 }
8338
8339 BUG_ON(val != final);
8340 }
8341
8342 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8343 {
8344 uint32_t tmp;
8345
8346 tmp = I915_READ(SOUTH_CHICKEN2);
8347 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8348 I915_WRITE(SOUTH_CHICKEN2, tmp);
8349
8350 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8351 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8352 DRM_ERROR("FDI mPHY reset assert timeout\n");
8353
8354 tmp = I915_READ(SOUTH_CHICKEN2);
8355 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8356 I915_WRITE(SOUTH_CHICKEN2, tmp);
8357
8358 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8359 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8360 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8361 }
8362
8363 /* WaMPhyProgramming:hsw */
8364 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8365 {
8366 uint32_t tmp;
8367
8368 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8369 tmp &= ~(0xFF << 24);
8370 tmp |= (0x12 << 24);
8371 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8372
8373 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8374 tmp |= (1 << 11);
8375 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8376
8377 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8378 tmp |= (1 << 11);
8379 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8380
8381 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8382 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8383 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8384
8385 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8386 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8387 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8388
8389 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8390 tmp &= ~(7 << 13);
8391 tmp |= (5 << 13);
8392 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8393
8394 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8395 tmp &= ~(7 << 13);
8396 tmp |= (5 << 13);
8397 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8398
8399 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8400 tmp &= ~0xFF;
8401 tmp |= 0x1C;
8402 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8403
8404 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8405 tmp &= ~0xFF;
8406 tmp |= 0x1C;
8407 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8408
8409 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8410 tmp &= ~(0xFF << 16);
8411 tmp |= (0x1C << 16);
8412 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8413
8414 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8415 tmp &= ~(0xFF << 16);
8416 tmp |= (0x1C << 16);
8417 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8418
8419 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8420 tmp |= (1 << 27);
8421 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8422
8423 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8424 tmp |= (1 << 27);
8425 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8426
8427 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8428 tmp &= ~(0xF << 28);
8429 tmp |= (4 << 28);
8430 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8431
8432 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8433 tmp &= ~(0xF << 28);
8434 tmp |= (4 << 28);
8435 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8436 }
8437
8438 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8439 * Programming" based on the parameters passed:
8440 * - Sequence to enable CLKOUT_DP
8441 * - Sequence to enable CLKOUT_DP without spread
8442 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8443 */
8444 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8445 bool with_fdi)
8446 {
8447 struct drm_i915_private *dev_priv = dev->dev_private;
8448 uint32_t reg, tmp;
8449
8450 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8451 with_spread = true;
8452 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8453 with_fdi, "LP PCH doesn't have FDI\n"))
8454 with_fdi = false;
8455
8456 mutex_lock(&dev_priv->sb_lock);
8457
8458 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8459 tmp &= ~SBI_SSCCTL_DISABLE;
8460 tmp |= SBI_SSCCTL_PATHALT;
8461 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8462
8463 udelay(24);
8464
8465 if (with_spread) {
8466 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8467 tmp &= ~SBI_SSCCTL_PATHALT;
8468 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8469
8470 if (with_fdi) {
8471 lpt_reset_fdi_mphy(dev_priv);
8472 lpt_program_fdi_mphy(dev_priv);
8473 }
8474 }
8475
8476 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8477 SBI_GEN0 : SBI_DBUFF0;
8478 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8479 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8480 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8481
8482 mutex_unlock(&dev_priv->sb_lock);
8483 }
8484
8485 /* Sequence to disable CLKOUT_DP */
8486 static void lpt_disable_clkout_dp(struct drm_device *dev)
8487 {
8488 struct drm_i915_private *dev_priv = dev->dev_private;
8489 uint32_t reg, tmp;
8490
8491 mutex_lock(&dev_priv->sb_lock);
8492
8493 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8494 SBI_GEN0 : SBI_DBUFF0;
8495 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8496 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8497 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8498
8499 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8500 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8501 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8502 tmp |= SBI_SSCCTL_PATHALT;
8503 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8504 udelay(32);
8505 }
8506 tmp |= SBI_SSCCTL_DISABLE;
8507 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8508 }
8509
8510 mutex_unlock(&dev_priv->sb_lock);
8511 }
8512
8513 static void lpt_init_pch_refclk(struct drm_device *dev)
8514 {
8515 struct intel_encoder *encoder;
8516 bool has_vga = false;
8517
8518 for_each_intel_encoder(dev, encoder) {
8519 switch (encoder->type) {
8520 case INTEL_OUTPUT_ANALOG:
8521 has_vga = true;
8522 break;
8523 default:
8524 break;
8525 }
8526 }
8527
8528 if (has_vga)
8529 lpt_enable_clkout_dp(dev, true, true);
8530 else
8531 lpt_disable_clkout_dp(dev);
8532 }
8533
8534 /*
8535 * Initialize reference clocks when the driver loads
8536 */
8537 void intel_init_pch_refclk(struct drm_device *dev)
8538 {
8539 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8540 ironlake_init_pch_refclk(dev);
8541 else if (HAS_PCH_LPT(dev))
8542 lpt_init_pch_refclk(dev);
8543 }
8544
8545 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8546 {
8547 struct drm_device *dev = crtc_state->base.crtc->dev;
8548 struct drm_i915_private *dev_priv = dev->dev_private;
8549 struct drm_atomic_state *state = crtc_state->base.state;
8550 struct drm_connector *connector;
8551 struct drm_connector_state *connector_state;
8552 struct intel_encoder *encoder;
8553 int num_connectors = 0, i;
8554 bool is_lvds = false;
8555
8556 for_each_connector_in_state(state, connector, connector_state, i) {
8557 if (connector_state->crtc != crtc_state->base.crtc)
8558 continue;
8559
8560 encoder = to_intel_encoder(connector_state->best_encoder);
8561
8562 switch (encoder->type) {
8563 case INTEL_OUTPUT_LVDS:
8564 is_lvds = true;
8565 break;
8566 default:
8567 break;
8568 }
8569 num_connectors++;
8570 }
8571
8572 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8573 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8574 dev_priv->vbt.lvds_ssc_freq);
8575 return dev_priv->vbt.lvds_ssc_freq;
8576 }
8577
8578 return 120000;
8579 }
8580
8581 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8582 {
8583 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8585 int pipe = intel_crtc->pipe;
8586 uint32_t val;
8587
8588 val = 0;
8589
8590 switch (intel_crtc->config->pipe_bpp) {
8591 case 18:
8592 val |= PIPECONF_6BPC;
8593 break;
8594 case 24:
8595 val |= PIPECONF_8BPC;
8596 break;
8597 case 30:
8598 val |= PIPECONF_10BPC;
8599 break;
8600 case 36:
8601 val |= PIPECONF_12BPC;
8602 break;
8603 default:
8604 /* Case prevented by intel_choose_pipe_bpp_dither. */
8605 BUG();
8606 }
8607
8608 if (intel_crtc->config->dither)
8609 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8610
8611 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8612 val |= PIPECONF_INTERLACED_ILK;
8613 else
8614 val |= PIPECONF_PROGRESSIVE;
8615
8616 if (intel_crtc->config->limited_color_range)
8617 val |= PIPECONF_COLOR_RANGE_SELECT;
8618
8619 I915_WRITE(PIPECONF(pipe), val);
8620 POSTING_READ(PIPECONF(pipe));
8621 }
8622
8623 /*
8624 * Set up the pipe CSC unit.
8625 *
8626 * Currently only full range RGB to limited range RGB conversion
8627 * is supported, but eventually this should handle various
8628 * RGB<->YCbCr scenarios as well.
8629 */
8630 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8631 {
8632 struct drm_device *dev = crtc->dev;
8633 struct drm_i915_private *dev_priv = dev->dev_private;
8634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8635 int pipe = intel_crtc->pipe;
8636 uint16_t coeff = 0x7800; /* 1.0 */
8637
8638 /*
8639 * TODO: Check what kind of values actually come out of the pipe
8640 * with these coeff/postoff values and adjust to get the best
8641 * accuracy. Perhaps we even need to take the bpc value into
8642 * consideration.
8643 */
8644
8645 if (intel_crtc->config->limited_color_range)
8646 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8647
8648 /*
8649 * GY/GU and RY/RU should be the other way around according
8650 * to BSpec, but reality doesn't agree. Just set them up in
8651 * a way that results in the correct picture.
8652 */
8653 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8654 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8655
8656 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8657 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8658
8659 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8660 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8661
8662 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8663 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8664 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8665
8666 if (INTEL_INFO(dev)->gen > 6) {
8667 uint16_t postoff = 0;
8668
8669 if (intel_crtc->config->limited_color_range)
8670 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8671
8672 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8673 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8674 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8675
8676 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8677 } else {
8678 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8679
8680 if (intel_crtc->config->limited_color_range)
8681 mode |= CSC_BLACK_SCREEN_OFFSET;
8682
8683 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8684 }
8685 }
8686
8687 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8688 {
8689 struct drm_device *dev = crtc->dev;
8690 struct drm_i915_private *dev_priv = dev->dev_private;
8691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8692 enum pipe pipe = intel_crtc->pipe;
8693 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8694 uint32_t val;
8695
8696 val = 0;
8697
8698 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8699 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8700
8701 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8702 val |= PIPECONF_INTERLACED_ILK;
8703 else
8704 val |= PIPECONF_PROGRESSIVE;
8705
8706 I915_WRITE(PIPECONF(cpu_transcoder), val);
8707 POSTING_READ(PIPECONF(cpu_transcoder));
8708
8709 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8710 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8711
8712 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8713 val = 0;
8714
8715 switch (intel_crtc->config->pipe_bpp) {
8716 case 18:
8717 val |= PIPEMISC_DITHER_6_BPC;
8718 break;
8719 case 24:
8720 val |= PIPEMISC_DITHER_8_BPC;
8721 break;
8722 case 30:
8723 val |= PIPEMISC_DITHER_10_BPC;
8724 break;
8725 case 36:
8726 val |= PIPEMISC_DITHER_12_BPC;
8727 break;
8728 default:
8729 /* Case prevented by pipe_config_set_bpp. */
8730 BUG();
8731 }
8732
8733 if (intel_crtc->config->dither)
8734 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8735
8736 I915_WRITE(PIPEMISC(pipe), val);
8737 }
8738 }
8739
8740 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8741 struct intel_crtc_state *crtc_state,
8742 intel_clock_t *clock,
8743 bool *has_reduced_clock,
8744 intel_clock_t *reduced_clock)
8745 {
8746 struct drm_device *dev = crtc->dev;
8747 struct drm_i915_private *dev_priv = dev->dev_private;
8748 int refclk;
8749 const intel_limit_t *limit;
8750 bool ret, is_lvds = false;
8751
8752 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8753
8754 refclk = ironlake_get_refclk(crtc_state);
8755
8756 /*
8757 * Returns a set of divisors for the desired target clock with the given
8758 * refclk, or FALSE. The returned values represent the clock equation:
8759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8760 */
8761 limit = intel_limit(crtc_state, refclk);
8762 ret = dev_priv->display.find_dpll(limit, crtc_state,
8763 crtc_state->port_clock,
8764 refclk, NULL, clock);
8765 if (!ret)
8766 return false;
8767
8768 if (is_lvds && dev_priv->lvds_downclock_avail) {
8769 /*
8770 * Ensure we match the reduced clock's P to the target clock.
8771 * If the clocks don't match, we can't switch the display clock
8772 * by using the FP0/FP1. In such case we will disable the LVDS
8773 * downclock feature.
8774 */
8775 *has_reduced_clock =
8776 dev_priv->display.find_dpll(limit, crtc_state,
8777 dev_priv->lvds_downclock,
8778 refclk, clock,
8779 reduced_clock);
8780 }
8781
8782 return true;
8783 }
8784
8785 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8786 {
8787 /*
8788 * Account for spread spectrum to avoid
8789 * oversubscribing the link. Max center spread
8790 * is 2.5%; use 5% for safety's sake.
8791 */
8792 u32 bps = target_clock * bpp * 21 / 20;
8793 return DIV_ROUND_UP(bps, link_bw * 8);
8794 }
8795
8796 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8797 {
8798 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8799 }
8800
8801 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8802 struct intel_crtc_state *crtc_state,
8803 u32 *fp,
8804 intel_clock_t *reduced_clock, u32 *fp2)
8805 {
8806 struct drm_crtc *crtc = &intel_crtc->base;
8807 struct drm_device *dev = crtc->dev;
8808 struct drm_i915_private *dev_priv = dev->dev_private;
8809 struct drm_atomic_state *state = crtc_state->base.state;
8810 struct drm_connector *connector;
8811 struct drm_connector_state *connector_state;
8812 struct intel_encoder *encoder;
8813 uint32_t dpll;
8814 int factor, num_connectors = 0, i;
8815 bool is_lvds = false, is_sdvo = false;
8816
8817 for_each_connector_in_state(state, connector, connector_state, i) {
8818 if (connector_state->crtc != crtc_state->base.crtc)
8819 continue;
8820
8821 encoder = to_intel_encoder(connector_state->best_encoder);
8822
8823 switch (encoder->type) {
8824 case INTEL_OUTPUT_LVDS:
8825 is_lvds = true;
8826 break;
8827 case INTEL_OUTPUT_SDVO:
8828 case INTEL_OUTPUT_HDMI:
8829 is_sdvo = true;
8830 break;
8831 default:
8832 break;
8833 }
8834
8835 num_connectors++;
8836 }
8837
8838 /* Enable autotuning of the PLL clock (if permissible) */
8839 factor = 21;
8840 if (is_lvds) {
8841 if ((intel_panel_use_ssc(dev_priv) &&
8842 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8843 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8844 factor = 25;
8845 } else if (crtc_state->sdvo_tv_clock)
8846 factor = 20;
8847
8848 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8849 *fp |= FP_CB_TUNE;
8850
8851 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8852 *fp2 |= FP_CB_TUNE;
8853
8854 dpll = 0;
8855
8856 if (is_lvds)
8857 dpll |= DPLLB_MODE_LVDS;
8858 else
8859 dpll |= DPLLB_MODE_DAC_SERIAL;
8860
8861 dpll |= (crtc_state->pixel_multiplier - 1)
8862 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8863
8864 if (is_sdvo)
8865 dpll |= DPLL_SDVO_HIGH_SPEED;
8866 if (crtc_state->has_dp_encoder)
8867 dpll |= DPLL_SDVO_HIGH_SPEED;
8868
8869 /* compute bitmask from p1 value */
8870 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8871 /* also FPA1 */
8872 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8873
8874 switch (crtc_state->dpll.p2) {
8875 case 5:
8876 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8877 break;
8878 case 7:
8879 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8880 break;
8881 case 10:
8882 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8883 break;
8884 case 14:
8885 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8886 break;
8887 }
8888
8889 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8890 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8891 else
8892 dpll |= PLL_REF_INPUT_DREFCLK;
8893
8894 return dpll | DPLL_VCO_ENABLE;
8895 }
8896
8897 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8898 struct intel_crtc_state *crtc_state)
8899 {
8900 struct drm_device *dev = crtc->base.dev;
8901 intel_clock_t clock, reduced_clock;
8902 u32 dpll = 0, fp = 0, fp2 = 0;
8903 bool ok, has_reduced_clock = false;
8904 bool is_lvds = false;
8905 struct intel_shared_dpll *pll;
8906
8907 memset(&crtc_state->dpll_hw_state, 0,
8908 sizeof(crtc_state->dpll_hw_state));
8909
8910 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8911
8912 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8913 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8914
8915 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8916 &has_reduced_clock, &reduced_clock);
8917 if (!ok && !crtc_state->clock_set) {
8918 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8919 return -EINVAL;
8920 }
8921 /* Compat-code for transition, will disappear. */
8922 if (!crtc_state->clock_set) {
8923 crtc_state->dpll.n = clock.n;
8924 crtc_state->dpll.m1 = clock.m1;
8925 crtc_state->dpll.m2 = clock.m2;
8926 crtc_state->dpll.p1 = clock.p1;
8927 crtc_state->dpll.p2 = clock.p2;
8928 }
8929
8930 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8931 if (crtc_state->has_pch_encoder) {
8932 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8933 if (has_reduced_clock)
8934 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8935
8936 dpll = ironlake_compute_dpll(crtc, crtc_state,
8937 &fp, &reduced_clock,
8938 has_reduced_clock ? &fp2 : NULL);
8939
8940 crtc_state->dpll_hw_state.dpll = dpll;
8941 crtc_state->dpll_hw_state.fp0 = fp;
8942 if (has_reduced_clock)
8943 crtc_state->dpll_hw_state.fp1 = fp2;
8944 else
8945 crtc_state->dpll_hw_state.fp1 = fp;
8946
8947 pll = intel_get_shared_dpll(crtc, crtc_state);
8948 if (pll == NULL) {
8949 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8950 pipe_name(crtc->pipe));
8951 return -EINVAL;
8952 }
8953 }
8954
8955 if (is_lvds && has_reduced_clock)
8956 crtc->lowfreq_avail = true;
8957 else
8958 crtc->lowfreq_avail = false;
8959
8960 return 0;
8961 }
8962
8963 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8964 struct intel_link_m_n *m_n)
8965 {
8966 struct drm_device *dev = crtc->base.dev;
8967 struct drm_i915_private *dev_priv = dev->dev_private;
8968 enum pipe pipe = crtc->pipe;
8969
8970 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8971 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8972 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8973 & ~TU_SIZE_MASK;
8974 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8975 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8976 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8977 }
8978
8979 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8980 enum transcoder transcoder,
8981 struct intel_link_m_n *m_n,
8982 struct intel_link_m_n *m2_n2)
8983 {
8984 struct drm_device *dev = crtc->base.dev;
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 enum pipe pipe = crtc->pipe;
8987
8988 if (INTEL_INFO(dev)->gen >= 5) {
8989 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8990 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8991 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8992 & ~TU_SIZE_MASK;
8993 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8994 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8995 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8996 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8997 * gen < 8) and if DRRS is supported (to make sure the
8998 * registers are not unnecessarily read).
8999 */
9000 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9001 crtc->config->has_drrs) {
9002 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9003 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9004 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9005 & ~TU_SIZE_MASK;
9006 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9007 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9008 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9009 }
9010 } else {
9011 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9012 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9013 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9014 & ~TU_SIZE_MASK;
9015 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9016 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9017 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9018 }
9019 }
9020
9021 void intel_dp_get_m_n(struct intel_crtc *crtc,
9022 struct intel_crtc_state *pipe_config)
9023 {
9024 if (pipe_config->has_pch_encoder)
9025 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9026 else
9027 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9028 &pipe_config->dp_m_n,
9029 &pipe_config->dp_m2_n2);
9030 }
9031
9032 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9033 struct intel_crtc_state *pipe_config)
9034 {
9035 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9036 &pipe_config->fdi_m_n, NULL);
9037 }
9038
9039 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9040 struct intel_crtc_state *pipe_config)
9041 {
9042 struct drm_device *dev = crtc->base.dev;
9043 struct drm_i915_private *dev_priv = dev->dev_private;
9044 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9045 uint32_t ps_ctrl = 0;
9046 int id = -1;
9047 int i;
9048
9049 /* find scaler attached to this pipe */
9050 for (i = 0; i < crtc->num_scalers; i++) {
9051 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9052 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9053 id = i;
9054 pipe_config->pch_pfit.enabled = true;
9055 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9056 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9057 break;
9058 }
9059 }
9060
9061 scaler_state->scaler_id = id;
9062 if (id >= 0) {
9063 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9064 } else {
9065 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9066 }
9067 }
9068
9069 static void
9070 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9071 struct intel_initial_plane_config *plane_config)
9072 {
9073 struct drm_device *dev = crtc->base.dev;
9074 struct drm_i915_private *dev_priv = dev->dev_private;
9075 u32 val, base, offset, stride_mult, tiling;
9076 int pipe = crtc->pipe;
9077 int fourcc, pixel_format;
9078 unsigned int aligned_height;
9079 struct drm_framebuffer *fb;
9080 struct intel_framebuffer *intel_fb;
9081
9082 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9083 if (!intel_fb) {
9084 DRM_DEBUG_KMS("failed to alloc fb\n");
9085 return;
9086 }
9087
9088 fb = &intel_fb->base;
9089
9090 val = I915_READ(PLANE_CTL(pipe, 0));
9091 if (!(val & PLANE_CTL_ENABLE))
9092 goto error;
9093
9094 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9095 fourcc = skl_format_to_fourcc(pixel_format,
9096 val & PLANE_CTL_ORDER_RGBX,
9097 val & PLANE_CTL_ALPHA_MASK);
9098 fb->pixel_format = fourcc;
9099 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9100
9101 tiling = val & PLANE_CTL_TILED_MASK;
9102 switch (tiling) {
9103 case PLANE_CTL_TILED_LINEAR:
9104 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9105 break;
9106 case PLANE_CTL_TILED_X:
9107 plane_config->tiling = I915_TILING_X;
9108 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9109 break;
9110 case PLANE_CTL_TILED_Y:
9111 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9112 break;
9113 case PLANE_CTL_TILED_YF:
9114 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9115 break;
9116 default:
9117 MISSING_CASE(tiling);
9118 goto error;
9119 }
9120
9121 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9122 plane_config->base = base;
9123
9124 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9125
9126 val = I915_READ(PLANE_SIZE(pipe, 0));
9127 fb->height = ((val >> 16) & 0xfff) + 1;
9128 fb->width = ((val >> 0) & 0x1fff) + 1;
9129
9130 val = I915_READ(PLANE_STRIDE(pipe, 0));
9131 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9132 fb->pixel_format);
9133 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9134
9135 aligned_height = intel_fb_align_height(dev, fb->height,
9136 fb->pixel_format,
9137 fb->modifier[0]);
9138
9139 plane_config->size = fb->pitches[0] * aligned_height;
9140
9141 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9142 pipe_name(pipe), fb->width, fb->height,
9143 fb->bits_per_pixel, base, fb->pitches[0],
9144 plane_config->size);
9145
9146 plane_config->fb = intel_fb;
9147 return;
9148
9149 error:
9150 kfree(fb);
9151 }
9152
9153 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9154 struct intel_crtc_state *pipe_config)
9155 {
9156 struct drm_device *dev = crtc->base.dev;
9157 struct drm_i915_private *dev_priv = dev->dev_private;
9158 uint32_t tmp;
9159
9160 tmp = I915_READ(PF_CTL(crtc->pipe));
9161
9162 if (tmp & PF_ENABLE) {
9163 pipe_config->pch_pfit.enabled = true;
9164 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9165 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9166
9167 /* We currently do not free assignements of panel fitters on
9168 * ivb/hsw (since we don't use the higher upscaling modes which
9169 * differentiates them) so just WARN about this case for now. */
9170 if (IS_GEN7(dev)) {
9171 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9172 PF_PIPE_SEL_IVB(crtc->pipe));
9173 }
9174 }
9175 }
9176
9177 static void
9178 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9179 struct intel_initial_plane_config *plane_config)
9180 {
9181 struct drm_device *dev = crtc->base.dev;
9182 struct drm_i915_private *dev_priv = dev->dev_private;
9183 u32 val, base, offset;
9184 int pipe = crtc->pipe;
9185 int fourcc, pixel_format;
9186 unsigned int aligned_height;
9187 struct drm_framebuffer *fb;
9188 struct intel_framebuffer *intel_fb;
9189
9190 val = I915_READ(DSPCNTR(pipe));
9191 if (!(val & DISPLAY_PLANE_ENABLE))
9192 return;
9193
9194 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9195 if (!intel_fb) {
9196 DRM_DEBUG_KMS("failed to alloc fb\n");
9197 return;
9198 }
9199
9200 fb = &intel_fb->base;
9201
9202 if (INTEL_INFO(dev)->gen >= 4) {
9203 if (val & DISPPLANE_TILED) {
9204 plane_config->tiling = I915_TILING_X;
9205 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9206 }
9207 }
9208
9209 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9210 fourcc = i9xx_format_to_fourcc(pixel_format);
9211 fb->pixel_format = fourcc;
9212 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9213
9214 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9215 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9216 offset = I915_READ(DSPOFFSET(pipe));
9217 } else {
9218 if (plane_config->tiling)
9219 offset = I915_READ(DSPTILEOFF(pipe));
9220 else
9221 offset = I915_READ(DSPLINOFF(pipe));
9222 }
9223 plane_config->base = base;
9224
9225 val = I915_READ(PIPESRC(pipe));
9226 fb->width = ((val >> 16) & 0xfff) + 1;
9227 fb->height = ((val >> 0) & 0xfff) + 1;
9228
9229 val = I915_READ(DSPSTRIDE(pipe));
9230 fb->pitches[0] = val & 0xffffffc0;
9231
9232 aligned_height = intel_fb_align_height(dev, fb->height,
9233 fb->pixel_format,
9234 fb->modifier[0]);
9235
9236 plane_config->size = fb->pitches[0] * aligned_height;
9237
9238 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9239 pipe_name(pipe), fb->width, fb->height,
9240 fb->bits_per_pixel, base, fb->pitches[0],
9241 plane_config->size);
9242
9243 plane_config->fb = intel_fb;
9244 }
9245
9246 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9247 struct intel_crtc_state *pipe_config)
9248 {
9249 struct drm_device *dev = crtc->base.dev;
9250 struct drm_i915_private *dev_priv = dev->dev_private;
9251 uint32_t tmp;
9252
9253 if (!intel_display_power_is_enabled(dev_priv,
9254 POWER_DOMAIN_PIPE(crtc->pipe)))
9255 return false;
9256
9257 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9258 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9259
9260 tmp = I915_READ(PIPECONF(crtc->pipe));
9261 if (!(tmp & PIPECONF_ENABLE))
9262 return false;
9263
9264 switch (tmp & PIPECONF_BPC_MASK) {
9265 case PIPECONF_6BPC:
9266 pipe_config->pipe_bpp = 18;
9267 break;
9268 case PIPECONF_8BPC:
9269 pipe_config->pipe_bpp = 24;
9270 break;
9271 case PIPECONF_10BPC:
9272 pipe_config->pipe_bpp = 30;
9273 break;
9274 case PIPECONF_12BPC:
9275 pipe_config->pipe_bpp = 36;
9276 break;
9277 default:
9278 break;
9279 }
9280
9281 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9282 pipe_config->limited_color_range = true;
9283
9284 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9285 struct intel_shared_dpll *pll;
9286
9287 pipe_config->has_pch_encoder = true;
9288
9289 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9290 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9291 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9292
9293 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9294
9295 if (HAS_PCH_IBX(dev_priv->dev)) {
9296 pipe_config->shared_dpll =
9297 (enum intel_dpll_id) crtc->pipe;
9298 } else {
9299 tmp = I915_READ(PCH_DPLL_SEL);
9300 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9301 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9302 else
9303 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9304 }
9305
9306 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9307
9308 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9309 &pipe_config->dpll_hw_state));
9310
9311 tmp = pipe_config->dpll_hw_state.dpll;
9312 pipe_config->pixel_multiplier =
9313 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9314 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9315
9316 ironlake_pch_clock_get(crtc, pipe_config);
9317 } else {
9318 pipe_config->pixel_multiplier = 1;
9319 }
9320
9321 intel_get_pipe_timings(crtc, pipe_config);
9322
9323 ironlake_get_pfit_config(crtc, pipe_config);
9324
9325 return true;
9326 }
9327
9328 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9329 {
9330 struct drm_device *dev = dev_priv->dev;
9331 struct intel_crtc *crtc;
9332
9333 for_each_intel_crtc(dev, crtc)
9334 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9335 pipe_name(crtc->pipe));
9336
9337 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9338 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9339 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9340 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9341 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9342 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9343 "CPU PWM1 enabled\n");
9344 if (IS_HASWELL(dev))
9345 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9346 "CPU PWM2 enabled\n");
9347 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9348 "PCH PWM1 enabled\n");
9349 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9350 "Utility pin enabled\n");
9351 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9352
9353 /*
9354 * In theory we can still leave IRQs enabled, as long as only the HPD
9355 * interrupts remain enabled. We used to check for that, but since it's
9356 * gen-specific and since we only disable LCPLL after we fully disable
9357 * the interrupts, the check below should be enough.
9358 */
9359 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9360 }
9361
9362 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9363 {
9364 struct drm_device *dev = dev_priv->dev;
9365
9366 if (IS_HASWELL(dev))
9367 return I915_READ(D_COMP_HSW);
9368 else
9369 return I915_READ(D_COMP_BDW);
9370 }
9371
9372 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9373 {
9374 struct drm_device *dev = dev_priv->dev;
9375
9376 if (IS_HASWELL(dev)) {
9377 mutex_lock(&dev_priv->rps.hw_lock);
9378 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9379 val))
9380 DRM_ERROR("Failed to write to D_COMP\n");
9381 mutex_unlock(&dev_priv->rps.hw_lock);
9382 } else {
9383 I915_WRITE(D_COMP_BDW, val);
9384 POSTING_READ(D_COMP_BDW);
9385 }
9386 }
9387
9388 /*
9389 * This function implements pieces of two sequences from BSpec:
9390 * - Sequence for display software to disable LCPLL
9391 * - Sequence for display software to allow package C8+
9392 * The steps implemented here are just the steps that actually touch the LCPLL
9393 * register. Callers should take care of disabling all the display engine
9394 * functions, doing the mode unset, fixing interrupts, etc.
9395 */
9396 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9397 bool switch_to_fclk, bool allow_power_down)
9398 {
9399 uint32_t val;
9400
9401 assert_can_disable_lcpll(dev_priv);
9402
9403 val = I915_READ(LCPLL_CTL);
9404
9405 if (switch_to_fclk) {
9406 val |= LCPLL_CD_SOURCE_FCLK;
9407 I915_WRITE(LCPLL_CTL, val);
9408
9409 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9410 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9411 DRM_ERROR("Switching to FCLK failed\n");
9412
9413 val = I915_READ(LCPLL_CTL);
9414 }
9415
9416 val |= LCPLL_PLL_DISABLE;
9417 I915_WRITE(LCPLL_CTL, val);
9418 POSTING_READ(LCPLL_CTL);
9419
9420 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9421 DRM_ERROR("LCPLL still locked\n");
9422
9423 val = hsw_read_dcomp(dev_priv);
9424 val |= D_COMP_COMP_DISABLE;
9425 hsw_write_dcomp(dev_priv, val);
9426 ndelay(100);
9427
9428 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9429 1))
9430 DRM_ERROR("D_COMP RCOMP still in progress\n");
9431
9432 if (allow_power_down) {
9433 val = I915_READ(LCPLL_CTL);
9434 val |= LCPLL_POWER_DOWN_ALLOW;
9435 I915_WRITE(LCPLL_CTL, val);
9436 POSTING_READ(LCPLL_CTL);
9437 }
9438 }
9439
9440 /*
9441 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9442 * source.
9443 */
9444 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9445 {
9446 uint32_t val;
9447
9448 val = I915_READ(LCPLL_CTL);
9449
9450 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9451 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9452 return;
9453
9454 /*
9455 * Make sure we're not on PC8 state before disabling PC8, otherwise
9456 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9457 */
9458 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9459
9460 if (val & LCPLL_POWER_DOWN_ALLOW) {
9461 val &= ~LCPLL_POWER_DOWN_ALLOW;
9462 I915_WRITE(LCPLL_CTL, val);
9463 POSTING_READ(LCPLL_CTL);
9464 }
9465
9466 val = hsw_read_dcomp(dev_priv);
9467 val |= D_COMP_COMP_FORCE;
9468 val &= ~D_COMP_COMP_DISABLE;
9469 hsw_write_dcomp(dev_priv, val);
9470
9471 val = I915_READ(LCPLL_CTL);
9472 val &= ~LCPLL_PLL_DISABLE;
9473 I915_WRITE(LCPLL_CTL, val);
9474
9475 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9476 DRM_ERROR("LCPLL not locked yet\n");
9477
9478 if (val & LCPLL_CD_SOURCE_FCLK) {
9479 val = I915_READ(LCPLL_CTL);
9480 val &= ~LCPLL_CD_SOURCE_FCLK;
9481 I915_WRITE(LCPLL_CTL, val);
9482
9483 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9484 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9485 DRM_ERROR("Switching back to LCPLL failed\n");
9486 }
9487
9488 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9489 intel_update_cdclk(dev_priv->dev);
9490 }
9491
9492 /*
9493 * Package states C8 and deeper are really deep PC states that can only be
9494 * reached when all the devices on the system allow it, so even if the graphics
9495 * device allows PC8+, it doesn't mean the system will actually get to these
9496 * states. Our driver only allows PC8+ when going into runtime PM.
9497 *
9498 * The requirements for PC8+ are that all the outputs are disabled, the power
9499 * well is disabled and most interrupts are disabled, and these are also
9500 * requirements for runtime PM. When these conditions are met, we manually do
9501 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9502 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9503 * hang the machine.
9504 *
9505 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9506 * the state of some registers, so when we come back from PC8+ we need to
9507 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9508 * need to take care of the registers kept by RC6. Notice that this happens even
9509 * if we don't put the device in PCI D3 state (which is what currently happens
9510 * because of the runtime PM support).
9511 *
9512 * For more, read "Display Sequences for Package C8" on the hardware
9513 * documentation.
9514 */
9515 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9516 {
9517 struct drm_device *dev = dev_priv->dev;
9518 uint32_t val;
9519
9520 DRM_DEBUG_KMS("Enabling package C8+\n");
9521
9522 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9523 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9524 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9525 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9526 }
9527
9528 lpt_disable_clkout_dp(dev);
9529 hsw_disable_lcpll(dev_priv, true, true);
9530 }
9531
9532 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9533 {
9534 struct drm_device *dev = dev_priv->dev;
9535 uint32_t val;
9536
9537 DRM_DEBUG_KMS("Disabling package C8+\n");
9538
9539 hsw_restore_lcpll(dev_priv);
9540 lpt_init_pch_refclk(dev);
9541
9542 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9543 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9544 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9545 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9546 }
9547
9548 intel_prepare_ddi(dev);
9549 }
9550
9551 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9552 {
9553 struct drm_device *dev = old_state->dev;
9554 struct drm_i915_private *dev_priv = dev->dev_private;
9555 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9556 int req_cdclk;
9557
9558 /* see the comment in valleyview_modeset_global_resources */
9559 if (WARN_ON(max_pixclk < 0))
9560 return;
9561
9562 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9563
9564 if (req_cdclk != dev_priv->cdclk_freq)
9565 broxton_set_cdclk(dev, req_cdclk);
9566 }
9567
9568 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9569 struct intel_crtc_state *crtc_state)
9570 {
9571 if (!intel_ddi_pll_select(crtc, crtc_state))
9572 return -EINVAL;
9573
9574 crtc->lowfreq_avail = false;
9575
9576 return 0;
9577 }
9578
9579 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9580 enum port port,
9581 struct intel_crtc_state *pipe_config)
9582 {
9583 switch (port) {
9584 case PORT_A:
9585 pipe_config->ddi_pll_sel = SKL_DPLL0;
9586 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9587 break;
9588 case PORT_B:
9589 pipe_config->ddi_pll_sel = SKL_DPLL1;
9590 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9591 break;
9592 case PORT_C:
9593 pipe_config->ddi_pll_sel = SKL_DPLL2;
9594 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9595 break;
9596 default:
9597 DRM_ERROR("Incorrect port type\n");
9598 }
9599 }
9600
9601 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9602 enum port port,
9603 struct intel_crtc_state *pipe_config)
9604 {
9605 u32 temp, dpll_ctl1;
9606
9607 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9608 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9609
9610 switch (pipe_config->ddi_pll_sel) {
9611 case SKL_DPLL0:
9612 /*
9613 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9614 * of the shared DPLL framework and thus needs to be read out
9615 * separately
9616 */
9617 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9618 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9619 break;
9620 case SKL_DPLL1:
9621 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9622 break;
9623 case SKL_DPLL2:
9624 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9625 break;
9626 case SKL_DPLL3:
9627 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9628 break;
9629 }
9630 }
9631
9632 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9633 enum port port,
9634 struct intel_crtc_state *pipe_config)
9635 {
9636 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9637
9638 switch (pipe_config->ddi_pll_sel) {
9639 case PORT_CLK_SEL_WRPLL1:
9640 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9641 break;
9642 case PORT_CLK_SEL_WRPLL2:
9643 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9644 break;
9645 }
9646 }
9647
9648 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9649 struct intel_crtc_state *pipe_config)
9650 {
9651 struct drm_device *dev = crtc->base.dev;
9652 struct drm_i915_private *dev_priv = dev->dev_private;
9653 struct intel_shared_dpll *pll;
9654 enum port port;
9655 uint32_t tmp;
9656
9657 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9658
9659 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9660
9661 if (IS_SKYLAKE(dev))
9662 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9663 else if (IS_BROXTON(dev))
9664 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9665 else
9666 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9667
9668 if (pipe_config->shared_dpll >= 0) {
9669 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9670
9671 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9672 &pipe_config->dpll_hw_state));
9673 }
9674
9675 /*
9676 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9677 * DDI E. So just check whether this pipe is wired to DDI E and whether
9678 * the PCH transcoder is on.
9679 */
9680 if (INTEL_INFO(dev)->gen < 9 &&
9681 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9682 pipe_config->has_pch_encoder = true;
9683
9684 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9685 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9686 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9687
9688 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9689 }
9690 }
9691
9692 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9693 struct intel_crtc_state *pipe_config)
9694 {
9695 struct drm_device *dev = crtc->base.dev;
9696 struct drm_i915_private *dev_priv = dev->dev_private;
9697 enum intel_display_power_domain pfit_domain;
9698 uint32_t tmp;
9699
9700 if (!intel_display_power_is_enabled(dev_priv,
9701 POWER_DOMAIN_PIPE(crtc->pipe)))
9702 return false;
9703
9704 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9705 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9706
9707 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9708 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9709 enum pipe trans_edp_pipe;
9710 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9711 default:
9712 WARN(1, "unknown pipe linked to edp transcoder\n");
9713 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9714 case TRANS_DDI_EDP_INPUT_A_ON:
9715 trans_edp_pipe = PIPE_A;
9716 break;
9717 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9718 trans_edp_pipe = PIPE_B;
9719 break;
9720 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9721 trans_edp_pipe = PIPE_C;
9722 break;
9723 }
9724
9725 if (trans_edp_pipe == crtc->pipe)
9726 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9727 }
9728
9729 if (!intel_display_power_is_enabled(dev_priv,
9730 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9731 return false;
9732
9733 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9734 if (!(tmp & PIPECONF_ENABLE))
9735 return false;
9736
9737 haswell_get_ddi_port_state(crtc, pipe_config);
9738
9739 intel_get_pipe_timings(crtc, pipe_config);
9740
9741 if (INTEL_INFO(dev)->gen >= 9) {
9742 skl_init_scalers(dev, crtc, pipe_config);
9743 }
9744
9745 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9746
9747 if (INTEL_INFO(dev)->gen >= 9) {
9748 pipe_config->scaler_state.scaler_id = -1;
9749 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9750 }
9751
9752 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9753 if (INTEL_INFO(dev)->gen == 9)
9754 skylake_get_pfit_config(crtc, pipe_config);
9755 else if (INTEL_INFO(dev)->gen < 9)
9756 ironlake_get_pfit_config(crtc, pipe_config);
9757 else
9758 MISSING_CASE(INTEL_INFO(dev)->gen);
9759 }
9760
9761 if (IS_HASWELL(dev))
9762 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9763 (I915_READ(IPS_CTL) & IPS_ENABLE);
9764
9765 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9766 pipe_config->pixel_multiplier =
9767 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9768 } else {
9769 pipe_config->pixel_multiplier = 1;
9770 }
9771
9772 return true;
9773 }
9774
9775 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9776 {
9777 struct drm_device *dev = crtc->dev;
9778 struct drm_i915_private *dev_priv = dev->dev_private;
9779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9780 uint32_t cntl = 0, size = 0;
9781
9782 if (base) {
9783 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9784 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9785 unsigned int stride = roundup_pow_of_two(width) * 4;
9786
9787 switch (stride) {
9788 default:
9789 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9790 width, stride);
9791 stride = 256;
9792 /* fallthrough */
9793 case 256:
9794 case 512:
9795 case 1024:
9796 case 2048:
9797 break;
9798 }
9799
9800 cntl |= CURSOR_ENABLE |
9801 CURSOR_GAMMA_ENABLE |
9802 CURSOR_FORMAT_ARGB |
9803 CURSOR_STRIDE(stride);
9804
9805 size = (height << 12) | width;
9806 }
9807
9808 if (intel_crtc->cursor_cntl != 0 &&
9809 (intel_crtc->cursor_base != base ||
9810 intel_crtc->cursor_size != size ||
9811 intel_crtc->cursor_cntl != cntl)) {
9812 /* On these chipsets we can only modify the base/size/stride
9813 * whilst the cursor is disabled.
9814 */
9815 I915_WRITE(_CURACNTR, 0);
9816 POSTING_READ(_CURACNTR);
9817 intel_crtc->cursor_cntl = 0;
9818 }
9819
9820 if (intel_crtc->cursor_base != base) {
9821 I915_WRITE(_CURABASE, base);
9822 intel_crtc->cursor_base = base;
9823 }
9824
9825 if (intel_crtc->cursor_size != size) {
9826 I915_WRITE(CURSIZE, size);
9827 intel_crtc->cursor_size = size;
9828 }
9829
9830 if (intel_crtc->cursor_cntl != cntl) {
9831 I915_WRITE(_CURACNTR, cntl);
9832 POSTING_READ(_CURACNTR);
9833 intel_crtc->cursor_cntl = cntl;
9834 }
9835 }
9836
9837 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9838 {
9839 struct drm_device *dev = crtc->dev;
9840 struct drm_i915_private *dev_priv = dev->dev_private;
9841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9842 int pipe = intel_crtc->pipe;
9843 uint32_t cntl;
9844
9845 cntl = 0;
9846 if (base) {
9847 cntl = MCURSOR_GAMMA_ENABLE;
9848 switch (intel_crtc->base.cursor->state->crtc_w) {
9849 case 64:
9850 cntl |= CURSOR_MODE_64_ARGB_AX;
9851 break;
9852 case 128:
9853 cntl |= CURSOR_MODE_128_ARGB_AX;
9854 break;
9855 case 256:
9856 cntl |= CURSOR_MODE_256_ARGB_AX;
9857 break;
9858 default:
9859 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9860 return;
9861 }
9862 cntl |= pipe << 28; /* Connect to correct pipe */
9863
9864 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9865 cntl |= CURSOR_PIPE_CSC_ENABLE;
9866 }
9867
9868 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9869 cntl |= CURSOR_ROTATE_180;
9870
9871 if (intel_crtc->cursor_cntl != cntl) {
9872 I915_WRITE(CURCNTR(pipe), cntl);
9873 POSTING_READ(CURCNTR(pipe));
9874 intel_crtc->cursor_cntl = cntl;
9875 }
9876
9877 /* and commit changes on next vblank */
9878 I915_WRITE(CURBASE(pipe), base);
9879 POSTING_READ(CURBASE(pipe));
9880
9881 intel_crtc->cursor_base = base;
9882 }
9883
9884 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9885 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9886 bool on)
9887 {
9888 struct drm_device *dev = crtc->dev;
9889 struct drm_i915_private *dev_priv = dev->dev_private;
9890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9891 int pipe = intel_crtc->pipe;
9892 int x = crtc->cursor_x;
9893 int y = crtc->cursor_y;
9894 u32 base = 0, pos = 0;
9895
9896 if (on)
9897 base = intel_crtc->cursor_addr;
9898
9899 if (x >= intel_crtc->config->pipe_src_w)
9900 base = 0;
9901
9902 if (y >= intel_crtc->config->pipe_src_h)
9903 base = 0;
9904
9905 if (x < 0) {
9906 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9907 base = 0;
9908
9909 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9910 x = -x;
9911 }
9912 pos |= x << CURSOR_X_SHIFT;
9913
9914 if (y < 0) {
9915 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9916 base = 0;
9917
9918 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9919 y = -y;
9920 }
9921 pos |= y << CURSOR_Y_SHIFT;
9922
9923 if (base == 0 && intel_crtc->cursor_base == 0)
9924 return;
9925
9926 I915_WRITE(CURPOS(pipe), pos);
9927
9928 /* ILK+ do this automagically */
9929 if (HAS_GMCH_DISPLAY(dev) &&
9930 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9931 base += (intel_crtc->base.cursor->state->crtc_h *
9932 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9933 }
9934
9935 if (IS_845G(dev) || IS_I865G(dev))
9936 i845_update_cursor(crtc, base);
9937 else
9938 i9xx_update_cursor(crtc, base);
9939 }
9940
9941 static bool cursor_size_ok(struct drm_device *dev,
9942 uint32_t width, uint32_t height)
9943 {
9944 if (width == 0 || height == 0)
9945 return false;
9946
9947 /*
9948 * 845g/865g are special in that they are only limited by
9949 * the width of their cursors, the height is arbitrary up to
9950 * the precision of the register. Everything else requires
9951 * square cursors, limited to a few power-of-two sizes.
9952 */
9953 if (IS_845G(dev) || IS_I865G(dev)) {
9954 if ((width & 63) != 0)
9955 return false;
9956
9957 if (width > (IS_845G(dev) ? 64 : 512))
9958 return false;
9959
9960 if (height > 1023)
9961 return false;
9962 } else {
9963 switch (width | height) {
9964 case 256:
9965 case 128:
9966 if (IS_GEN2(dev))
9967 return false;
9968 case 64:
9969 break;
9970 default:
9971 return false;
9972 }
9973 }
9974
9975 return true;
9976 }
9977
9978 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9979 u16 *blue, uint32_t start, uint32_t size)
9980 {
9981 int end = (start + size > 256) ? 256 : start + size, i;
9982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9983
9984 for (i = start; i < end; i++) {
9985 intel_crtc->lut_r[i] = red[i] >> 8;
9986 intel_crtc->lut_g[i] = green[i] >> 8;
9987 intel_crtc->lut_b[i] = blue[i] >> 8;
9988 }
9989
9990 intel_crtc_load_lut(crtc);
9991 }
9992
9993 /* VESA 640x480x72Hz mode to set on the pipe */
9994 static struct drm_display_mode load_detect_mode = {
9995 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9996 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9997 };
9998
9999 struct drm_framebuffer *
10000 __intel_framebuffer_create(struct drm_device *dev,
10001 struct drm_mode_fb_cmd2 *mode_cmd,
10002 struct drm_i915_gem_object *obj)
10003 {
10004 struct intel_framebuffer *intel_fb;
10005 int ret;
10006
10007 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10008 if (!intel_fb) {
10009 drm_gem_object_unreference(&obj->base);
10010 return ERR_PTR(-ENOMEM);
10011 }
10012
10013 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10014 if (ret)
10015 goto err;
10016
10017 return &intel_fb->base;
10018 err:
10019 drm_gem_object_unreference(&obj->base);
10020 kfree(intel_fb);
10021
10022 return ERR_PTR(ret);
10023 }
10024
10025 static struct drm_framebuffer *
10026 intel_framebuffer_create(struct drm_device *dev,
10027 struct drm_mode_fb_cmd2 *mode_cmd,
10028 struct drm_i915_gem_object *obj)
10029 {
10030 struct drm_framebuffer *fb;
10031 int ret;
10032
10033 ret = i915_mutex_lock_interruptible(dev);
10034 if (ret)
10035 return ERR_PTR(ret);
10036 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10037 mutex_unlock(&dev->struct_mutex);
10038
10039 return fb;
10040 }
10041
10042 static u32
10043 intel_framebuffer_pitch_for_width(int width, int bpp)
10044 {
10045 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10046 return ALIGN(pitch, 64);
10047 }
10048
10049 static u32
10050 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10051 {
10052 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10053 return PAGE_ALIGN(pitch * mode->vdisplay);
10054 }
10055
10056 static struct drm_framebuffer *
10057 intel_framebuffer_create_for_mode(struct drm_device *dev,
10058 struct drm_display_mode *mode,
10059 int depth, int bpp)
10060 {
10061 struct drm_i915_gem_object *obj;
10062 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10063
10064 obj = i915_gem_alloc_object(dev,
10065 intel_framebuffer_size_for_mode(mode, bpp));
10066 if (obj == NULL)
10067 return ERR_PTR(-ENOMEM);
10068
10069 mode_cmd.width = mode->hdisplay;
10070 mode_cmd.height = mode->vdisplay;
10071 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10072 bpp);
10073 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10074
10075 return intel_framebuffer_create(dev, &mode_cmd, obj);
10076 }
10077
10078 static struct drm_framebuffer *
10079 mode_fits_in_fbdev(struct drm_device *dev,
10080 struct drm_display_mode *mode)
10081 {
10082 #ifdef CONFIG_DRM_I915_FBDEV
10083 struct drm_i915_private *dev_priv = dev->dev_private;
10084 struct drm_i915_gem_object *obj;
10085 struct drm_framebuffer *fb;
10086
10087 if (!dev_priv->fbdev)
10088 return NULL;
10089
10090 if (!dev_priv->fbdev->fb)
10091 return NULL;
10092
10093 obj = dev_priv->fbdev->fb->obj;
10094 BUG_ON(!obj);
10095
10096 fb = &dev_priv->fbdev->fb->base;
10097 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10098 fb->bits_per_pixel))
10099 return NULL;
10100
10101 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10102 return NULL;
10103
10104 return fb;
10105 #else
10106 return NULL;
10107 #endif
10108 }
10109
10110 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10111 struct drm_crtc *crtc,
10112 struct drm_display_mode *mode,
10113 struct drm_framebuffer *fb,
10114 int x, int y)
10115 {
10116 struct drm_plane_state *plane_state;
10117 int hdisplay, vdisplay;
10118 int ret;
10119
10120 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10121 if (IS_ERR(plane_state))
10122 return PTR_ERR(plane_state);
10123
10124 if (mode)
10125 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10126 else
10127 hdisplay = vdisplay = 0;
10128
10129 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10130 if (ret)
10131 return ret;
10132 drm_atomic_set_fb_for_plane(plane_state, fb);
10133 plane_state->crtc_x = 0;
10134 plane_state->crtc_y = 0;
10135 plane_state->crtc_w = hdisplay;
10136 plane_state->crtc_h = vdisplay;
10137 plane_state->src_x = x << 16;
10138 plane_state->src_y = y << 16;
10139 plane_state->src_w = hdisplay << 16;
10140 plane_state->src_h = vdisplay << 16;
10141
10142 return 0;
10143 }
10144
10145 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10146 struct drm_display_mode *mode,
10147 struct intel_load_detect_pipe *old,
10148 struct drm_modeset_acquire_ctx *ctx)
10149 {
10150 struct intel_crtc *intel_crtc;
10151 struct intel_encoder *intel_encoder =
10152 intel_attached_encoder(connector);
10153 struct drm_crtc *possible_crtc;
10154 struct drm_encoder *encoder = &intel_encoder->base;
10155 struct drm_crtc *crtc = NULL;
10156 struct drm_device *dev = encoder->dev;
10157 struct drm_framebuffer *fb;
10158 struct drm_mode_config *config = &dev->mode_config;
10159 struct drm_atomic_state *state = NULL;
10160 struct drm_connector_state *connector_state;
10161 struct intel_crtc_state *crtc_state;
10162 int ret, i = -1;
10163
10164 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10165 connector->base.id, connector->name,
10166 encoder->base.id, encoder->name);
10167
10168 retry:
10169 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10170 if (ret)
10171 goto fail_unlock;
10172
10173 /*
10174 * Algorithm gets a little messy:
10175 *
10176 * - if the connector already has an assigned crtc, use it (but make
10177 * sure it's on first)
10178 *
10179 * - try to find the first unused crtc that can drive this connector,
10180 * and use that if we find one
10181 */
10182
10183 /* See if we already have a CRTC for this connector */
10184 if (encoder->crtc) {
10185 crtc = encoder->crtc;
10186
10187 ret = drm_modeset_lock(&crtc->mutex, ctx);
10188 if (ret)
10189 goto fail_unlock;
10190 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10191 if (ret)
10192 goto fail_unlock;
10193
10194 old->dpms_mode = connector->dpms;
10195 old->load_detect_temp = false;
10196
10197 /* Make sure the crtc and connector are running */
10198 if (connector->dpms != DRM_MODE_DPMS_ON)
10199 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10200
10201 return true;
10202 }
10203
10204 /* Find an unused one (if possible) */
10205 for_each_crtc(dev, possible_crtc) {
10206 i++;
10207 if (!(encoder->possible_crtcs & (1 << i)))
10208 continue;
10209 if (possible_crtc->state->enable)
10210 continue;
10211 /* This can occur when applying the pipe A quirk on resume. */
10212 if (to_intel_crtc(possible_crtc)->new_enabled)
10213 continue;
10214
10215 crtc = possible_crtc;
10216 break;
10217 }
10218
10219 /*
10220 * If we didn't find an unused CRTC, don't use any.
10221 */
10222 if (!crtc) {
10223 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10224 goto fail_unlock;
10225 }
10226
10227 ret = drm_modeset_lock(&crtc->mutex, ctx);
10228 if (ret)
10229 goto fail_unlock;
10230 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10231 if (ret)
10232 goto fail_unlock;
10233 intel_encoder->new_crtc = to_intel_crtc(crtc);
10234 to_intel_connector(connector)->new_encoder = intel_encoder;
10235
10236 intel_crtc = to_intel_crtc(crtc);
10237 intel_crtc->new_enabled = true;
10238 old->dpms_mode = connector->dpms;
10239 old->load_detect_temp = true;
10240 old->release_fb = NULL;
10241
10242 state = drm_atomic_state_alloc(dev);
10243 if (!state)
10244 return false;
10245
10246 state->acquire_ctx = ctx;
10247
10248 connector_state = drm_atomic_get_connector_state(state, connector);
10249 if (IS_ERR(connector_state)) {
10250 ret = PTR_ERR(connector_state);
10251 goto fail;
10252 }
10253
10254 connector_state->crtc = crtc;
10255 connector_state->best_encoder = &intel_encoder->base;
10256
10257 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10258 if (IS_ERR(crtc_state)) {
10259 ret = PTR_ERR(crtc_state);
10260 goto fail;
10261 }
10262
10263 crtc_state->base.active = crtc_state->base.enable = true;
10264
10265 if (!mode)
10266 mode = &load_detect_mode;
10267
10268 /* We need a framebuffer large enough to accommodate all accesses
10269 * that the plane may generate whilst we perform load detection.
10270 * We can not rely on the fbcon either being present (we get called
10271 * during its initialisation to detect all boot displays, or it may
10272 * not even exist) or that it is large enough to satisfy the
10273 * requested mode.
10274 */
10275 fb = mode_fits_in_fbdev(dev, mode);
10276 if (fb == NULL) {
10277 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10278 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10279 old->release_fb = fb;
10280 } else
10281 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10282 if (IS_ERR(fb)) {
10283 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10284 goto fail;
10285 }
10286
10287 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10288 if (ret)
10289 goto fail;
10290
10291 drm_mode_copy(&crtc_state->base.mode, mode);
10292
10293 if (intel_set_mode(crtc, state)) {
10294 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10295 if (old->release_fb)
10296 old->release_fb->funcs->destroy(old->release_fb);
10297 goto fail;
10298 }
10299 crtc->primary->crtc = crtc;
10300
10301 /* let the connector get through one full cycle before testing */
10302 intel_wait_for_vblank(dev, intel_crtc->pipe);
10303 return true;
10304
10305 fail:
10306 intel_crtc->new_enabled = crtc->state->enable;
10307 fail_unlock:
10308 drm_atomic_state_free(state);
10309 state = NULL;
10310
10311 if (ret == -EDEADLK) {
10312 drm_modeset_backoff(ctx);
10313 goto retry;
10314 }
10315
10316 return false;
10317 }
10318
10319 void intel_release_load_detect_pipe(struct drm_connector *connector,
10320 struct intel_load_detect_pipe *old,
10321 struct drm_modeset_acquire_ctx *ctx)
10322 {
10323 struct drm_device *dev = connector->dev;
10324 struct intel_encoder *intel_encoder =
10325 intel_attached_encoder(connector);
10326 struct drm_encoder *encoder = &intel_encoder->base;
10327 struct drm_crtc *crtc = encoder->crtc;
10328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10329 struct drm_atomic_state *state;
10330 struct drm_connector_state *connector_state;
10331 struct intel_crtc_state *crtc_state;
10332 int ret;
10333
10334 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10335 connector->base.id, connector->name,
10336 encoder->base.id, encoder->name);
10337
10338 if (old->load_detect_temp) {
10339 state = drm_atomic_state_alloc(dev);
10340 if (!state)
10341 goto fail;
10342
10343 state->acquire_ctx = ctx;
10344
10345 connector_state = drm_atomic_get_connector_state(state, connector);
10346 if (IS_ERR(connector_state))
10347 goto fail;
10348
10349 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10350 if (IS_ERR(crtc_state))
10351 goto fail;
10352
10353 to_intel_connector(connector)->new_encoder = NULL;
10354 intel_encoder->new_crtc = NULL;
10355 intel_crtc->new_enabled = false;
10356
10357 connector_state->best_encoder = NULL;
10358 connector_state->crtc = NULL;
10359
10360 crtc_state->base.enable = crtc_state->base.active = false;
10361
10362 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10363 0, 0);
10364 if (ret)
10365 goto fail;
10366
10367 ret = intel_set_mode(crtc, state);
10368 if (ret)
10369 goto fail;
10370
10371 if (old->release_fb) {
10372 drm_framebuffer_unregister_private(old->release_fb);
10373 drm_framebuffer_unreference(old->release_fb);
10374 }
10375
10376 return;
10377 }
10378
10379 /* Switch crtc and encoder back off if necessary */
10380 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10381 connector->funcs->dpms(connector, old->dpms_mode);
10382
10383 return;
10384 fail:
10385 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10386 drm_atomic_state_free(state);
10387 }
10388
10389 static int i9xx_pll_refclk(struct drm_device *dev,
10390 const struct intel_crtc_state *pipe_config)
10391 {
10392 struct drm_i915_private *dev_priv = dev->dev_private;
10393 u32 dpll = pipe_config->dpll_hw_state.dpll;
10394
10395 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10396 return dev_priv->vbt.lvds_ssc_freq;
10397 else if (HAS_PCH_SPLIT(dev))
10398 return 120000;
10399 else if (!IS_GEN2(dev))
10400 return 96000;
10401 else
10402 return 48000;
10403 }
10404
10405 /* Returns the clock of the currently programmed mode of the given pipe. */
10406 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10407 struct intel_crtc_state *pipe_config)
10408 {
10409 struct drm_device *dev = crtc->base.dev;
10410 struct drm_i915_private *dev_priv = dev->dev_private;
10411 int pipe = pipe_config->cpu_transcoder;
10412 u32 dpll = pipe_config->dpll_hw_state.dpll;
10413 u32 fp;
10414 intel_clock_t clock;
10415 int refclk = i9xx_pll_refclk(dev, pipe_config);
10416
10417 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10418 fp = pipe_config->dpll_hw_state.fp0;
10419 else
10420 fp = pipe_config->dpll_hw_state.fp1;
10421
10422 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10423 if (IS_PINEVIEW(dev)) {
10424 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10425 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10426 } else {
10427 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10428 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10429 }
10430
10431 if (!IS_GEN2(dev)) {
10432 if (IS_PINEVIEW(dev))
10433 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10434 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10435 else
10436 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10437 DPLL_FPA01_P1_POST_DIV_SHIFT);
10438
10439 switch (dpll & DPLL_MODE_MASK) {
10440 case DPLLB_MODE_DAC_SERIAL:
10441 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10442 5 : 10;
10443 break;
10444 case DPLLB_MODE_LVDS:
10445 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10446 7 : 14;
10447 break;
10448 default:
10449 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10450 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10451 return;
10452 }
10453
10454 if (IS_PINEVIEW(dev))
10455 pineview_clock(refclk, &clock);
10456 else
10457 i9xx_clock(refclk, &clock);
10458 } else {
10459 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10460 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10461
10462 if (is_lvds) {
10463 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10464 DPLL_FPA01_P1_POST_DIV_SHIFT);
10465
10466 if (lvds & LVDS_CLKB_POWER_UP)
10467 clock.p2 = 7;
10468 else
10469 clock.p2 = 14;
10470 } else {
10471 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10472 clock.p1 = 2;
10473 else {
10474 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10475 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10476 }
10477 if (dpll & PLL_P2_DIVIDE_BY_4)
10478 clock.p2 = 4;
10479 else
10480 clock.p2 = 2;
10481 }
10482
10483 i9xx_clock(refclk, &clock);
10484 }
10485
10486 /*
10487 * This value includes pixel_multiplier. We will use
10488 * port_clock to compute adjusted_mode.crtc_clock in the
10489 * encoder's get_config() function.
10490 */
10491 pipe_config->port_clock = clock.dot;
10492 }
10493
10494 int intel_dotclock_calculate(int link_freq,
10495 const struct intel_link_m_n *m_n)
10496 {
10497 /*
10498 * The calculation for the data clock is:
10499 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10500 * But we want to avoid losing precison if possible, so:
10501 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10502 *
10503 * and the link clock is simpler:
10504 * link_clock = (m * link_clock) / n
10505 */
10506
10507 if (!m_n->link_n)
10508 return 0;
10509
10510 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10511 }
10512
10513 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10514 struct intel_crtc_state *pipe_config)
10515 {
10516 struct drm_device *dev = crtc->base.dev;
10517
10518 /* read out port_clock from the DPLL */
10519 i9xx_crtc_clock_get(crtc, pipe_config);
10520
10521 /*
10522 * This value does not include pixel_multiplier.
10523 * We will check that port_clock and adjusted_mode.crtc_clock
10524 * agree once we know their relationship in the encoder's
10525 * get_config() function.
10526 */
10527 pipe_config->base.adjusted_mode.crtc_clock =
10528 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10529 &pipe_config->fdi_m_n);
10530 }
10531
10532 /** Returns the currently programmed mode of the given pipe. */
10533 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10534 struct drm_crtc *crtc)
10535 {
10536 struct drm_i915_private *dev_priv = dev->dev_private;
10537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10538 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10539 struct drm_display_mode *mode;
10540 struct intel_crtc_state pipe_config;
10541 int htot = I915_READ(HTOTAL(cpu_transcoder));
10542 int hsync = I915_READ(HSYNC(cpu_transcoder));
10543 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10544 int vsync = I915_READ(VSYNC(cpu_transcoder));
10545 enum pipe pipe = intel_crtc->pipe;
10546
10547 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10548 if (!mode)
10549 return NULL;
10550
10551 /*
10552 * Construct a pipe_config sufficient for getting the clock info
10553 * back out of crtc_clock_get.
10554 *
10555 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10556 * to use a real value here instead.
10557 */
10558 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10559 pipe_config.pixel_multiplier = 1;
10560 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10561 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10562 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10563 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10564
10565 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10566 mode->hdisplay = (htot & 0xffff) + 1;
10567 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10568 mode->hsync_start = (hsync & 0xffff) + 1;
10569 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10570 mode->vdisplay = (vtot & 0xffff) + 1;
10571 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10572 mode->vsync_start = (vsync & 0xffff) + 1;
10573 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10574
10575 drm_mode_set_name(mode);
10576
10577 return mode;
10578 }
10579
10580 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10581 {
10582 struct drm_device *dev = crtc->dev;
10583 struct drm_i915_private *dev_priv = dev->dev_private;
10584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10585
10586 if (!HAS_GMCH_DISPLAY(dev))
10587 return;
10588
10589 if (!dev_priv->lvds_downclock_avail)
10590 return;
10591
10592 /*
10593 * Since this is called by a timer, we should never get here in
10594 * the manual case.
10595 */
10596 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10597 int pipe = intel_crtc->pipe;
10598 int dpll_reg = DPLL(pipe);
10599 int dpll;
10600
10601 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10602
10603 assert_panel_unlocked(dev_priv, pipe);
10604
10605 dpll = I915_READ(dpll_reg);
10606 dpll |= DISPLAY_RATE_SELECT_FPA1;
10607 I915_WRITE(dpll_reg, dpll);
10608 intel_wait_for_vblank(dev, pipe);
10609 dpll = I915_READ(dpll_reg);
10610 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10611 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10612 }
10613
10614 }
10615
10616 void intel_mark_busy(struct drm_device *dev)
10617 {
10618 struct drm_i915_private *dev_priv = dev->dev_private;
10619
10620 if (dev_priv->mm.busy)
10621 return;
10622
10623 intel_runtime_pm_get(dev_priv);
10624 i915_update_gfx_val(dev_priv);
10625 if (INTEL_INFO(dev)->gen >= 6)
10626 gen6_rps_busy(dev_priv);
10627 dev_priv->mm.busy = true;
10628 }
10629
10630 void intel_mark_idle(struct drm_device *dev)
10631 {
10632 struct drm_i915_private *dev_priv = dev->dev_private;
10633 struct drm_crtc *crtc;
10634
10635 if (!dev_priv->mm.busy)
10636 return;
10637
10638 dev_priv->mm.busy = false;
10639
10640 for_each_crtc(dev, crtc) {
10641 if (!crtc->primary->fb)
10642 continue;
10643
10644 intel_decrease_pllclock(crtc);
10645 }
10646
10647 if (INTEL_INFO(dev)->gen >= 6)
10648 gen6_rps_idle(dev->dev_private);
10649
10650 intel_runtime_pm_put(dev_priv);
10651 }
10652
10653 static void intel_crtc_destroy(struct drm_crtc *crtc)
10654 {
10655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10656 struct drm_device *dev = crtc->dev;
10657 struct intel_unpin_work *work;
10658
10659 spin_lock_irq(&dev->event_lock);
10660 work = intel_crtc->unpin_work;
10661 intel_crtc->unpin_work = NULL;
10662 spin_unlock_irq(&dev->event_lock);
10663
10664 if (work) {
10665 cancel_work_sync(&work->work);
10666 kfree(work);
10667 }
10668
10669 drm_crtc_cleanup(crtc);
10670
10671 kfree(intel_crtc);
10672 }
10673
10674 static void intel_unpin_work_fn(struct work_struct *__work)
10675 {
10676 struct intel_unpin_work *work =
10677 container_of(__work, struct intel_unpin_work, work);
10678 struct drm_device *dev = work->crtc->dev;
10679 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10680
10681 mutex_lock(&dev->struct_mutex);
10682 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10683 drm_gem_object_unreference(&work->pending_flip_obj->base);
10684
10685 intel_fbc_update(dev);
10686
10687 if (work->flip_queued_req)
10688 i915_gem_request_assign(&work->flip_queued_req, NULL);
10689 mutex_unlock(&dev->struct_mutex);
10690
10691 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10692 drm_framebuffer_unreference(work->old_fb);
10693
10694 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10695 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10696
10697 kfree(work);
10698 }
10699
10700 static void do_intel_finish_page_flip(struct drm_device *dev,
10701 struct drm_crtc *crtc)
10702 {
10703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10704 struct intel_unpin_work *work;
10705 unsigned long flags;
10706
10707 /* Ignore early vblank irqs */
10708 if (intel_crtc == NULL)
10709 return;
10710
10711 /*
10712 * This is called both by irq handlers and the reset code (to complete
10713 * lost pageflips) so needs the full irqsave spinlocks.
10714 */
10715 spin_lock_irqsave(&dev->event_lock, flags);
10716 work = intel_crtc->unpin_work;
10717
10718 /* Ensure we don't miss a work->pending update ... */
10719 smp_rmb();
10720
10721 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10722 spin_unlock_irqrestore(&dev->event_lock, flags);
10723 return;
10724 }
10725
10726 page_flip_completed(intel_crtc);
10727
10728 spin_unlock_irqrestore(&dev->event_lock, flags);
10729 }
10730
10731 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10732 {
10733 struct drm_i915_private *dev_priv = dev->dev_private;
10734 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10735
10736 do_intel_finish_page_flip(dev, crtc);
10737 }
10738
10739 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10740 {
10741 struct drm_i915_private *dev_priv = dev->dev_private;
10742 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10743
10744 do_intel_finish_page_flip(dev, crtc);
10745 }
10746
10747 /* Is 'a' after or equal to 'b'? */
10748 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10749 {
10750 return !((a - b) & 0x80000000);
10751 }
10752
10753 static bool page_flip_finished(struct intel_crtc *crtc)
10754 {
10755 struct drm_device *dev = crtc->base.dev;
10756 struct drm_i915_private *dev_priv = dev->dev_private;
10757
10758 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10759 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10760 return true;
10761
10762 /*
10763 * The relevant registers doen't exist on pre-ctg.
10764 * As the flip done interrupt doesn't trigger for mmio
10765 * flips on gmch platforms, a flip count check isn't
10766 * really needed there. But since ctg has the registers,
10767 * include it in the check anyway.
10768 */
10769 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10770 return true;
10771
10772 /*
10773 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10774 * used the same base address. In that case the mmio flip might
10775 * have completed, but the CS hasn't even executed the flip yet.
10776 *
10777 * A flip count check isn't enough as the CS might have updated
10778 * the base address just after start of vblank, but before we
10779 * managed to process the interrupt. This means we'd complete the
10780 * CS flip too soon.
10781 *
10782 * Combining both checks should get us a good enough result. It may
10783 * still happen that the CS flip has been executed, but has not
10784 * yet actually completed. But in case the base address is the same
10785 * anyway, we don't really care.
10786 */
10787 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10788 crtc->unpin_work->gtt_offset &&
10789 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10790 crtc->unpin_work->flip_count);
10791 }
10792
10793 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10794 {
10795 struct drm_i915_private *dev_priv = dev->dev_private;
10796 struct intel_crtc *intel_crtc =
10797 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10798 unsigned long flags;
10799
10800
10801 /*
10802 * This is called both by irq handlers and the reset code (to complete
10803 * lost pageflips) so needs the full irqsave spinlocks.
10804 *
10805 * NB: An MMIO update of the plane base pointer will also
10806 * generate a page-flip completion irq, i.e. every modeset
10807 * is also accompanied by a spurious intel_prepare_page_flip().
10808 */
10809 spin_lock_irqsave(&dev->event_lock, flags);
10810 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10811 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10812 spin_unlock_irqrestore(&dev->event_lock, flags);
10813 }
10814
10815 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10816 {
10817 /* Ensure that the work item is consistent when activating it ... */
10818 smp_wmb();
10819 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10820 /* and that it is marked active as soon as the irq could fire. */
10821 smp_wmb();
10822 }
10823
10824 static int intel_gen2_queue_flip(struct drm_device *dev,
10825 struct drm_crtc *crtc,
10826 struct drm_framebuffer *fb,
10827 struct drm_i915_gem_object *obj,
10828 struct intel_engine_cs *ring,
10829 uint32_t flags)
10830 {
10831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10832 u32 flip_mask;
10833 int ret;
10834
10835 ret = intel_ring_begin(ring, 6);
10836 if (ret)
10837 return ret;
10838
10839 /* Can't queue multiple flips, so wait for the previous
10840 * one to finish before executing the next.
10841 */
10842 if (intel_crtc->plane)
10843 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10844 else
10845 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10846 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10847 intel_ring_emit(ring, MI_NOOP);
10848 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10849 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10850 intel_ring_emit(ring, fb->pitches[0]);
10851 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10852 intel_ring_emit(ring, 0); /* aux display base address, unused */
10853
10854 intel_mark_page_flip_active(intel_crtc);
10855 __intel_ring_advance(ring);
10856 return 0;
10857 }
10858
10859 static int intel_gen3_queue_flip(struct drm_device *dev,
10860 struct drm_crtc *crtc,
10861 struct drm_framebuffer *fb,
10862 struct drm_i915_gem_object *obj,
10863 struct intel_engine_cs *ring,
10864 uint32_t flags)
10865 {
10866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10867 u32 flip_mask;
10868 int ret;
10869
10870 ret = intel_ring_begin(ring, 6);
10871 if (ret)
10872 return ret;
10873
10874 if (intel_crtc->plane)
10875 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10876 else
10877 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10878 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10879 intel_ring_emit(ring, MI_NOOP);
10880 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10881 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10882 intel_ring_emit(ring, fb->pitches[0]);
10883 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10884 intel_ring_emit(ring, MI_NOOP);
10885
10886 intel_mark_page_flip_active(intel_crtc);
10887 __intel_ring_advance(ring);
10888 return 0;
10889 }
10890
10891 static int intel_gen4_queue_flip(struct drm_device *dev,
10892 struct drm_crtc *crtc,
10893 struct drm_framebuffer *fb,
10894 struct drm_i915_gem_object *obj,
10895 struct intel_engine_cs *ring,
10896 uint32_t flags)
10897 {
10898 struct drm_i915_private *dev_priv = dev->dev_private;
10899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10900 uint32_t pf, pipesrc;
10901 int ret;
10902
10903 ret = intel_ring_begin(ring, 4);
10904 if (ret)
10905 return ret;
10906
10907 /* i965+ uses the linear or tiled offsets from the
10908 * Display Registers (which do not change across a page-flip)
10909 * so we need only reprogram the base address.
10910 */
10911 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10912 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10913 intel_ring_emit(ring, fb->pitches[0]);
10914 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10915 obj->tiling_mode);
10916
10917 /* XXX Enabling the panel-fitter across page-flip is so far
10918 * untested on non-native modes, so ignore it for now.
10919 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10920 */
10921 pf = 0;
10922 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10923 intel_ring_emit(ring, pf | pipesrc);
10924
10925 intel_mark_page_flip_active(intel_crtc);
10926 __intel_ring_advance(ring);
10927 return 0;
10928 }
10929
10930 static int intel_gen6_queue_flip(struct drm_device *dev,
10931 struct drm_crtc *crtc,
10932 struct drm_framebuffer *fb,
10933 struct drm_i915_gem_object *obj,
10934 struct intel_engine_cs *ring,
10935 uint32_t flags)
10936 {
10937 struct drm_i915_private *dev_priv = dev->dev_private;
10938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10939 uint32_t pf, pipesrc;
10940 int ret;
10941
10942 ret = intel_ring_begin(ring, 4);
10943 if (ret)
10944 return ret;
10945
10946 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10947 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10948 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10949 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10950
10951 /* Contrary to the suggestions in the documentation,
10952 * "Enable Panel Fitter" does not seem to be required when page
10953 * flipping with a non-native mode, and worse causes a normal
10954 * modeset to fail.
10955 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10956 */
10957 pf = 0;
10958 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10959 intel_ring_emit(ring, pf | pipesrc);
10960
10961 intel_mark_page_flip_active(intel_crtc);
10962 __intel_ring_advance(ring);
10963 return 0;
10964 }
10965
10966 static int intel_gen7_queue_flip(struct drm_device *dev,
10967 struct drm_crtc *crtc,
10968 struct drm_framebuffer *fb,
10969 struct drm_i915_gem_object *obj,
10970 struct intel_engine_cs *ring,
10971 uint32_t flags)
10972 {
10973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10974 uint32_t plane_bit = 0;
10975 int len, ret;
10976
10977 switch (intel_crtc->plane) {
10978 case PLANE_A:
10979 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10980 break;
10981 case PLANE_B:
10982 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10983 break;
10984 case PLANE_C:
10985 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10986 break;
10987 default:
10988 WARN_ONCE(1, "unknown plane in flip command\n");
10989 return -ENODEV;
10990 }
10991
10992 len = 4;
10993 if (ring->id == RCS) {
10994 len += 6;
10995 /*
10996 * On Gen 8, SRM is now taking an extra dword to accommodate
10997 * 48bits addresses, and we need a NOOP for the batch size to
10998 * stay even.
10999 */
11000 if (IS_GEN8(dev))
11001 len += 2;
11002 }
11003
11004 /*
11005 * BSpec MI_DISPLAY_FLIP for IVB:
11006 * "The full packet must be contained within the same cache line."
11007 *
11008 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11009 * cacheline, if we ever start emitting more commands before
11010 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11011 * then do the cacheline alignment, and finally emit the
11012 * MI_DISPLAY_FLIP.
11013 */
11014 ret = intel_ring_cacheline_align(ring);
11015 if (ret)
11016 return ret;
11017
11018 ret = intel_ring_begin(ring, len);
11019 if (ret)
11020 return ret;
11021
11022 /* Unmask the flip-done completion message. Note that the bspec says that
11023 * we should do this for both the BCS and RCS, and that we must not unmask
11024 * more than one flip event at any time (or ensure that one flip message
11025 * can be sent by waiting for flip-done prior to queueing new flips).
11026 * Experimentation says that BCS works despite DERRMR masking all
11027 * flip-done completion events and that unmasking all planes at once
11028 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11029 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11030 */
11031 if (ring->id == RCS) {
11032 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11033 intel_ring_emit(ring, DERRMR);
11034 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11035 DERRMR_PIPEB_PRI_FLIP_DONE |
11036 DERRMR_PIPEC_PRI_FLIP_DONE));
11037 if (IS_GEN8(dev))
11038 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11039 MI_SRM_LRM_GLOBAL_GTT);
11040 else
11041 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11042 MI_SRM_LRM_GLOBAL_GTT);
11043 intel_ring_emit(ring, DERRMR);
11044 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11045 if (IS_GEN8(dev)) {
11046 intel_ring_emit(ring, 0);
11047 intel_ring_emit(ring, MI_NOOP);
11048 }
11049 }
11050
11051 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11052 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11053 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11054 intel_ring_emit(ring, (MI_NOOP));
11055
11056 intel_mark_page_flip_active(intel_crtc);
11057 __intel_ring_advance(ring);
11058 return 0;
11059 }
11060
11061 static bool use_mmio_flip(struct intel_engine_cs *ring,
11062 struct drm_i915_gem_object *obj)
11063 {
11064 /*
11065 * This is not being used for older platforms, because
11066 * non-availability of flip done interrupt forces us to use
11067 * CS flips. Older platforms derive flip done using some clever
11068 * tricks involving the flip_pending status bits and vblank irqs.
11069 * So using MMIO flips there would disrupt this mechanism.
11070 */
11071
11072 if (ring == NULL)
11073 return true;
11074
11075 if (INTEL_INFO(ring->dev)->gen < 5)
11076 return false;
11077
11078 if (i915.use_mmio_flip < 0)
11079 return false;
11080 else if (i915.use_mmio_flip > 0)
11081 return true;
11082 else if (i915.enable_execlists)
11083 return true;
11084 else
11085 return ring != i915_gem_request_get_ring(obj->last_write_req);
11086 }
11087
11088 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11089 {
11090 struct drm_device *dev = intel_crtc->base.dev;
11091 struct drm_i915_private *dev_priv = dev->dev_private;
11092 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11093 const enum pipe pipe = intel_crtc->pipe;
11094 u32 ctl, stride;
11095
11096 ctl = I915_READ(PLANE_CTL(pipe, 0));
11097 ctl &= ~PLANE_CTL_TILED_MASK;
11098 switch (fb->modifier[0]) {
11099 case DRM_FORMAT_MOD_NONE:
11100 break;
11101 case I915_FORMAT_MOD_X_TILED:
11102 ctl |= PLANE_CTL_TILED_X;
11103 break;
11104 case I915_FORMAT_MOD_Y_TILED:
11105 ctl |= PLANE_CTL_TILED_Y;
11106 break;
11107 case I915_FORMAT_MOD_Yf_TILED:
11108 ctl |= PLANE_CTL_TILED_YF;
11109 break;
11110 default:
11111 MISSING_CASE(fb->modifier[0]);
11112 }
11113
11114 /*
11115 * The stride is either expressed as a multiple of 64 bytes chunks for
11116 * linear buffers or in number of tiles for tiled buffers.
11117 */
11118 stride = fb->pitches[0] /
11119 intel_fb_stride_alignment(dev, fb->modifier[0],
11120 fb->pixel_format);
11121
11122 /*
11123 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11124 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11125 */
11126 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11127 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11128
11129 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11130 POSTING_READ(PLANE_SURF(pipe, 0));
11131 }
11132
11133 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11134 {
11135 struct drm_device *dev = intel_crtc->base.dev;
11136 struct drm_i915_private *dev_priv = dev->dev_private;
11137 struct intel_framebuffer *intel_fb =
11138 to_intel_framebuffer(intel_crtc->base.primary->fb);
11139 struct drm_i915_gem_object *obj = intel_fb->obj;
11140 u32 dspcntr;
11141 u32 reg;
11142
11143 reg = DSPCNTR(intel_crtc->plane);
11144 dspcntr = I915_READ(reg);
11145
11146 if (obj->tiling_mode != I915_TILING_NONE)
11147 dspcntr |= DISPPLANE_TILED;
11148 else
11149 dspcntr &= ~DISPPLANE_TILED;
11150
11151 I915_WRITE(reg, dspcntr);
11152
11153 I915_WRITE(DSPSURF(intel_crtc->plane),
11154 intel_crtc->unpin_work->gtt_offset);
11155 POSTING_READ(DSPSURF(intel_crtc->plane));
11156
11157 }
11158
11159 /*
11160 * XXX: This is the temporary way to update the plane registers until we get
11161 * around to using the usual plane update functions for MMIO flips
11162 */
11163 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11164 {
11165 struct drm_device *dev = intel_crtc->base.dev;
11166 bool atomic_update;
11167 u32 start_vbl_count;
11168
11169 intel_mark_page_flip_active(intel_crtc);
11170
11171 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11172
11173 if (INTEL_INFO(dev)->gen >= 9)
11174 skl_do_mmio_flip(intel_crtc);
11175 else
11176 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11177 ilk_do_mmio_flip(intel_crtc);
11178
11179 if (atomic_update)
11180 intel_pipe_update_end(intel_crtc, start_vbl_count);
11181 }
11182
11183 static void intel_mmio_flip_work_func(struct work_struct *work)
11184 {
11185 struct intel_mmio_flip *mmio_flip =
11186 container_of(work, struct intel_mmio_flip, work);
11187
11188 if (mmio_flip->req)
11189 WARN_ON(__i915_wait_request(mmio_flip->req,
11190 mmio_flip->crtc->reset_counter,
11191 false, NULL,
11192 &mmio_flip->i915->rps.mmioflips));
11193
11194 intel_do_mmio_flip(mmio_flip->crtc);
11195
11196 i915_gem_request_unreference__unlocked(mmio_flip->req);
11197 kfree(mmio_flip);
11198 }
11199
11200 static int intel_queue_mmio_flip(struct drm_device *dev,
11201 struct drm_crtc *crtc,
11202 struct drm_framebuffer *fb,
11203 struct drm_i915_gem_object *obj,
11204 struct intel_engine_cs *ring,
11205 uint32_t flags)
11206 {
11207 struct intel_mmio_flip *mmio_flip;
11208
11209 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11210 if (mmio_flip == NULL)
11211 return -ENOMEM;
11212
11213 mmio_flip->i915 = to_i915(dev);
11214 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11215 mmio_flip->crtc = to_intel_crtc(crtc);
11216
11217 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11218 schedule_work(&mmio_flip->work);
11219
11220 return 0;
11221 }
11222
11223 static int intel_default_queue_flip(struct drm_device *dev,
11224 struct drm_crtc *crtc,
11225 struct drm_framebuffer *fb,
11226 struct drm_i915_gem_object *obj,
11227 struct intel_engine_cs *ring,
11228 uint32_t flags)
11229 {
11230 return -ENODEV;
11231 }
11232
11233 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11234 struct drm_crtc *crtc)
11235 {
11236 struct drm_i915_private *dev_priv = dev->dev_private;
11237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11238 struct intel_unpin_work *work = intel_crtc->unpin_work;
11239 u32 addr;
11240
11241 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11242 return true;
11243
11244 if (!work->enable_stall_check)
11245 return false;
11246
11247 if (work->flip_ready_vblank == 0) {
11248 if (work->flip_queued_req &&
11249 !i915_gem_request_completed(work->flip_queued_req, true))
11250 return false;
11251
11252 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11253 }
11254
11255 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11256 return false;
11257
11258 /* Potential stall - if we see that the flip has happened,
11259 * assume a missed interrupt. */
11260 if (INTEL_INFO(dev)->gen >= 4)
11261 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11262 else
11263 addr = I915_READ(DSPADDR(intel_crtc->plane));
11264
11265 /* There is a potential issue here with a false positive after a flip
11266 * to the same address. We could address this by checking for a
11267 * non-incrementing frame counter.
11268 */
11269 return addr == work->gtt_offset;
11270 }
11271
11272 void intel_check_page_flip(struct drm_device *dev, int pipe)
11273 {
11274 struct drm_i915_private *dev_priv = dev->dev_private;
11275 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11277 struct intel_unpin_work *work;
11278
11279 WARN_ON(!in_interrupt());
11280
11281 if (crtc == NULL)
11282 return;
11283
11284 spin_lock(&dev->event_lock);
11285 work = intel_crtc->unpin_work;
11286 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11287 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11288 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11289 page_flip_completed(intel_crtc);
11290 work = NULL;
11291 }
11292 if (work != NULL &&
11293 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11294 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11295 spin_unlock(&dev->event_lock);
11296 }
11297
11298 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11299 struct drm_framebuffer *fb,
11300 struct drm_pending_vblank_event *event,
11301 uint32_t page_flip_flags)
11302 {
11303 struct drm_device *dev = crtc->dev;
11304 struct drm_i915_private *dev_priv = dev->dev_private;
11305 struct drm_framebuffer *old_fb = crtc->primary->fb;
11306 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11308 struct drm_plane *primary = crtc->primary;
11309 enum pipe pipe = intel_crtc->pipe;
11310 struct intel_unpin_work *work;
11311 struct intel_engine_cs *ring;
11312 bool mmio_flip;
11313 int ret;
11314
11315 /*
11316 * drm_mode_page_flip_ioctl() should already catch this, but double
11317 * check to be safe. In the future we may enable pageflipping from
11318 * a disabled primary plane.
11319 */
11320 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11321 return -EBUSY;
11322
11323 /* Can't change pixel format via MI display flips. */
11324 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11325 return -EINVAL;
11326
11327 /*
11328 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11329 * Note that pitch changes could also affect these register.
11330 */
11331 if (INTEL_INFO(dev)->gen > 3 &&
11332 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11333 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11334 return -EINVAL;
11335
11336 if (i915_terminally_wedged(&dev_priv->gpu_error))
11337 goto out_hang;
11338
11339 work = kzalloc(sizeof(*work), GFP_KERNEL);
11340 if (work == NULL)
11341 return -ENOMEM;
11342
11343 work->event = event;
11344 work->crtc = crtc;
11345 work->old_fb = old_fb;
11346 INIT_WORK(&work->work, intel_unpin_work_fn);
11347
11348 ret = drm_crtc_vblank_get(crtc);
11349 if (ret)
11350 goto free_work;
11351
11352 /* We borrow the event spin lock for protecting unpin_work */
11353 spin_lock_irq(&dev->event_lock);
11354 if (intel_crtc->unpin_work) {
11355 /* Before declaring the flip queue wedged, check if
11356 * the hardware completed the operation behind our backs.
11357 */
11358 if (__intel_pageflip_stall_check(dev, crtc)) {
11359 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11360 page_flip_completed(intel_crtc);
11361 } else {
11362 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11363 spin_unlock_irq(&dev->event_lock);
11364
11365 drm_crtc_vblank_put(crtc);
11366 kfree(work);
11367 return -EBUSY;
11368 }
11369 }
11370 intel_crtc->unpin_work = work;
11371 spin_unlock_irq(&dev->event_lock);
11372
11373 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11374 flush_workqueue(dev_priv->wq);
11375
11376 /* Reference the objects for the scheduled work. */
11377 drm_framebuffer_reference(work->old_fb);
11378 drm_gem_object_reference(&obj->base);
11379
11380 crtc->primary->fb = fb;
11381 update_state_fb(crtc->primary);
11382
11383 work->pending_flip_obj = obj;
11384
11385 ret = i915_mutex_lock_interruptible(dev);
11386 if (ret)
11387 goto cleanup;
11388
11389 atomic_inc(&intel_crtc->unpin_work_count);
11390 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11391
11392 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11393 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11394
11395 if (IS_VALLEYVIEW(dev)) {
11396 ring = &dev_priv->ring[BCS];
11397 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11398 /* vlv: DISPLAY_FLIP fails to change tiling */
11399 ring = NULL;
11400 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11401 ring = &dev_priv->ring[BCS];
11402 } else if (INTEL_INFO(dev)->gen >= 7) {
11403 ring = i915_gem_request_get_ring(obj->last_write_req);
11404 if (ring == NULL || ring->id != RCS)
11405 ring = &dev_priv->ring[BCS];
11406 } else {
11407 ring = &dev_priv->ring[RCS];
11408 }
11409
11410 mmio_flip = use_mmio_flip(ring, obj);
11411
11412 /* When using CS flips, we want to emit semaphores between rings.
11413 * However, when using mmio flips we will create a task to do the
11414 * synchronisation, so all we want here is to pin the framebuffer
11415 * into the display plane and skip any waits.
11416 */
11417 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11418 crtc->primary->state,
11419 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11420 if (ret)
11421 goto cleanup_pending;
11422
11423 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11424 + intel_crtc->dspaddr_offset;
11425
11426 if (mmio_flip) {
11427 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11428 page_flip_flags);
11429 if (ret)
11430 goto cleanup_unpin;
11431
11432 i915_gem_request_assign(&work->flip_queued_req,
11433 obj->last_write_req);
11434 } else {
11435 if (obj->last_write_req) {
11436 ret = i915_gem_check_olr(obj->last_write_req);
11437 if (ret)
11438 goto cleanup_unpin;
11439 }
11440
11441 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11442 page_flip_flags);
11443 if (ret)
11444 goto cleanup_unpin;
11445
11446 i915_gem_request_assign(&work->flip_queued_req,
11447 intel_ring_get_request(ring));
11448 }
11449
11450 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11451 work->enable_stall_check = true;
11452
11453 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11454 INTEL_FRONTBUFFER_PRIMARY(pipe));
11455
11456 intel_fbc_disable(dev);
11457 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11458 mutex_unlock(&dev->struct_mutex);
11459
11460 trace_i915_flip_request(intel_crtc->plane, obj);
11461
11462 return 0;
11463
11464 cleanup_unpin:
11465 intel_unpin_fb_obj(fb, crtc->primary->state);
11466 cleanup_pending:
11467 atomic_dec(&intel_crtc->unpin_work_count);
11468 mutex_unlock(&dev->struct_mutex);
11469 cleanup:
11470 crtc->primary->fb = old_fb;
11471 update_state_fb(crtc->primary);
11472
11473 drm_gem_object_unreference_unlocked(&obj->base);
11474 drm_framebuffer_unreference(work->old_fb);
11475
11476 spin_lock_irq(&dev->event_lock);
11477 intel_crtc->unpin_work = NULL;
11478 spin_unlock_irq(&dev->event_lock);
11479
11480 drm_crtc_vblank_put(crtc);
11481 free_work:
11482 kfree(work);
11483
11484 if (ret == -EIO) {
11485 out_hang:
11486 ret = intel_plane_restore(primary);
11487 if (ret == 0 && event) {
11488 spin_lock_irq(&dev->event_lock);
11489 drm_send_vblank_event(dev, pipe, event);
11490 spin_unlock_irq(&dev->event_lock);
11491 }
11492 }
11493 return ret;
11494 }
11495
11496 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11497 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11498 .load_lut = intel_crtc_load_lut,
11499 .atomic_begin = intel_begin_crtc_commit,
11500 .atomic_flush = intel_finish_crtc_commit,
11501 };
11502
11503 /**
11504 * intel_modeset_update_staged_output_state
11505 *
11506 * Updates the staged output configuration state, e.g. after we've read out the
11507 * current hw state.
11508 */
11509 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11510 {
11511 struct intel_crtc *crtc;
11512 struct intel_encoder *encoder;
11513 struct intel_connector *connector;
11514
11515 for_each_intel_connector(dev, connector) {
11516 connector->new_encoder =
11517 to_intel_encoder(connector->base.encoder);
11518 }
11519
11520 for_each_intel_encoder(dev, encoder) {
11521 encoder->new_crtc =
11522 to_intel_crtc(encoder->base.crtc);
11523 }
11524
11525 for_each_intel_crtc(dev, crtc) {
11526 crtc->new_enabled = crtc->base.state->enable;
11527 }
11528 }
11529
11530 /* Transitional helper to copy current connector/encoder state to
11531 * connector->state. This is needed so that code that is partially
11532 * converted to atomic does the right thing.
11533 */
11534 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11535 {
11536 struct intel_connector *connector;
11537
11538 for_each_intel_connector(dev, connector) {
11539 if (connector->base.encoder) {
11540 connector->base.state->best_encoder =
11541 connector->base.encoder;
11542 connector->base.state->crtc =
11543 connector->base.encoder->crtc;
11544 } else {
11545 connector->base.state->best_encoder = NULL;
11546 connector->base.state->crtc = NULL;
11547 }
11548 }
11549 }
11550
11551 /* Fixup legacy state after an atomic state swap.
11552 */
11553 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11554 {
11555 struct intel_crtc *crtc;
11556 struct intel_encoder *encoder;
11557 struct intel_connector *connector;
11558
11559 for_each_intel_connector(state->dev, connector) {
11560 connector->base.encoder = connector->base.state->best_encoder;
11561 if (connector->base.encoder)
11562 connector->base.encoder->crtc =
11563 connector->base.state->crtc;
11564 }
11565
11566 /* Update crtc of disabled encoders */
11567 for_each_intel_encoder(state->dev, encoder) {
11568 int num_connectors = 0;
11569
11570 for_each_intel_connector(state->dev, connector)
11571 if (connector->base.encoder == &encoder->base)
11572 num_connectors++;
11573
11574 if (num_connectors == 0)
11575 encoder->base.crtc = NULL;
11576 }
11577
11578 for_each_intel_crtc(state->dev, crtc) {
11579 crtc->base.enabled = crtc->base.state->enable;
11580 crtc->config = to_intel_crtc_state(crtc->base.state);
11581 }
11582
11583 /* Copy the new configuration to the staged state, to keep the few
11584 * pieces of code that haven't been converted yet happy */
11585 intel_modeset_update_staged_output_state(state->dev);
11586 }
11587
11588 static void
11589 connected_sink_compute_bpp(struct intel_connector *connector,
11590 struct intel_crtc_state *pipe_config)
11591 {
11592 int bpp = pipe_config->pipe_bpp;
11593
11594 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11595 connector->base.base.id,
11596 connector->base.name);
11597
11598 /* Don't use an invalid EDID bpc value */
11599 if (connector->base.display_info.bpc &&
11600 connector->base.display_info.bpc * 3 < bpp) {
11601 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11602 bpp, connector->base.display_info.bpc*3);
11603 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11604 }
11605
11606 /* Clamp bpp to 8 on screens without EDID 1.4 */
11607 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11608 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11609 bpp);
11610 pipe_config->pipe_bpp = 24;
11611 }
11612 }
11613
11614 static int
11615 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11616 struct intel_crtc_state *pipe_config)
11617 {
11618 struct drm_device *dev = crtc->base.dev;
11619 struct drm_atomic_state *state;
11620 struct drm_connector *connector;
11621 struct drm_connector_state *connector_state;
11622 int bpp, i;
11623
11624 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11625 bpp = 10*3;
11626 else if (INTEL_INFO(dev)->gen >= 5)
11627 bpp = 12*3;
11628 else
11629 bpp = 8*3;
11630
11631
11632 pipe_config->pipe_bpp = bpp;
11633
11634 state = pipe_config->base.state;
11635
11636 /* Clamp display bpp to EDID value */
11637 for_each_connector_in_state(state, connector, connector_state, i) {
11638 if (connector_state->crtc != &crtc->base)
11639 continue;
11640
11641 connected_sink_compute_bpp(to_intel_connector(connector),
11642 pipe_config);
11643 }
11644
11645 return bpp;
11646 }
11647
11648 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11649 {
11650 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11651 "type: 0x%x flags: 0x%x\n",
11652 mode->crtc_clock,
11653 mode->crtc_hdisplay, mode->crtc_hsync_start,
11654 mode->crtc_hsync_end, mode->crtc_htotal,
11655 mode->crtc_vdisplay, mode->crtc_vsync_start,
11656 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11657 }
11658
11659 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11660 struct intel_crtc_state *pipe_config,
11661 const char *context)
11662 {
11663 struct drm_device *dev = crtc->base.dev;
11664 struct drm_plane *plane;
11665 struct intel_plane *intel_plane;
11666 struct intel_plane_state *state;
11667 struct drm_framebuffer *fb;
11668
11669 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11670 context, pipe_config, pipe_name(crtc->pipe));
11671
11672 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11673 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11674 pipe_config->pipe_bpp, pipe_config->dither);
11675 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11676 pipe_config->has_pch_encoder,
11677 pipe_config->fdi_lanes,
11678 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11679 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11680 pipe_config->fdi_m_n.tu);
11681 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11682 pipe_config->has_dp_encoder,
11683 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11684 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11685 pipe_config->dp_m_n.tu);
11686
11687 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11688 pipe_config->has_dp_encoder,
11689 pipe_config->dp_m2_n2.gmch_m,
11690 pipe_config->dp_m2_n2.gmch_n,
11691 pipe_config->dp_m2_n2.link_m,
11692 pipe_config->dp_m2_n2.link_n,
11693 pipe_config->dp_m2_n2.tu);
11694
11695 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11696 pipe_config->has_audio,
11697 pipe_config->has_infoframe);
11698
11699 DRM_DEBUG_KMS("requested mode:\n");
11700 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11701 DRM_DEBUG_KMS("adjusted mode:\n");
11702 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11703 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11704 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11705 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11706 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11707 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11708 crtc->num_scalers,
11709 pipe_config->scaler_state.scaler_users,
11710 pipe_config->scaler_state.scaler_id);
11711 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11712 pipe_config->gmch_pfit.control,
11713 pipe_config->gmch_pfit.pgm_ratios,
11714 pipe_config->gmch_pfit.lvds_border_bits);
11715 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11716 pipe_config->pch_pfit.pos,
11717 pipe_config->pch_pfit.size,
11718 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11719 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11720 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11721
11722 if (IS_BROXTON(dev)) {
11723 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11724 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11725 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11726 pipe_config->ddi_pll_sel,
11727 pipe_config->dpll_hw_state.ebb0,
11728 pipe_config->dpll_hw_state.pll0,
11729 pipe_config->dpll_hw_state.pll1,
11730 pipe_config->dpll_hw_state.pll2,
11731 pipe_config->dpll_hw_state.pll3,
11732 pipe_config->dpll_hw_state.pll6,
11733 pipe_config->dpll_hw_state.pll8,
11734 pipe_config->dpll_hw_state.pcsdw12);
11735 } else if (IS_SKYLAKE(dev)) {
11736 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11737 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11738 pipe_config->ddi_pll_sel,
11739 pipe_config->dpll_hw_state.ctrl1,
11740 pipe_config->dpll_hw_state.cfgcr1,
11741 pipe_config->dpll_hw_state.cfgcr2);
11742 } else if (HAS_DDI(dev)) {
11743 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11744 pipe_config->ddi_pll_sel,
11745 pipe_config->dpll_hw_state.wrpll);
11746 } else {
11747 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11748 "fp0: 0x%x, fp1: 0x%x\n",
11749 pipe_config->dpll_hw_state.dpll,
11750 pipe_config->dpll_hw_state.dpll_md,
11751 pipe_config->dpll_hw_state.fp0,
11752 pipe_config->dpll_hw_state.fp1);
11753 }
11754
11755 DRM_DEBUG_KMS("planes on this crtc\n");
11756 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11757 intel_plane = to_intel_plane(plane);
11758 if (intel_plane->pipe != crtc->pipe)
11759 continue;
11760
11761 state = to_intel_plane_state(plane->state);
11762 fb = state->base.fb;
11763 if (!fb) {
11764 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11765 "disabled, scaler_id = %d\n",
11766 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11767 plane->base.id, intel_plane->pipe,
11768 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11769 drm_plane_index(plane), state->scaler_id);
11770 continue;
11771 }
11772
11773 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11774 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11775 plane->base.id, intel_plane->pipe,
11776 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11777 drm_plane_index(plane));
11778 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11779 fb->base.id, fb->width, fb->height, fb->pixel_format);
11780 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11781 state->scaler_id,
11782 state->src.x1 >> 16, state->src.y1 >> 16,
11783 drm_rect_width(&state->src) >> 16,
11784 drm_rect_height(&state->src) >> 16,
11785 state->dst.x1, state->dst.y1,
11786 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11787 }
11788 }
11789
11790 static bool encoders_cloneable(const struct intel_encoder *a,
11791 const struct intel_encoder *b)
11792 {
11793 /* masks could be asymmetric, so check both ways */
11794 return a == b || (a->cloneable & (1 << b->type) &&
11795 b->cloneable & (1 << a->type));
11796 }
11797
11798 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11799 struct intel_crtc *crtc,
11800 struct intel_encoder *encoder)
11801 {
11802 struct intel_encoder *source_encoder;
11803 struct drm_connector *connector;
11804 struct drm_connector_state *connector_state;
11805 int i;
11806
11807 for_each_connector_in_state(state, connector, connector_state, i) {
11808 if (connector_state->crtc != &crtc->base)
11809 continue;
11810
11811 source_encoder =
11812 to_intel_encoder(connector_state->best_encoder);
11813 if (!encoders_cloneable(encoder, source_encoder))
11814 return false;
11815 }
11816
11817 return true;
11818 }
11819
11820 static bool check_encoder_cloning(struct drm_atomic_state *state,
11821 struct intel_crtc *crtc)
11822 {
11823 struct intel_encoder *encoder;
11824 struct drm_connector *connector;
11825 struct drm_connector_state *connector_state;
11826 int i;
11827
11828 for_each_connector_in_state(state, connector, connector_state, i) {
11829 if (connector_state->crtc != &crtc->base)
11830 continue;
11831
11832 encoder = to_intel_encoder(connector_state->best_encoder);
11833 if (!check_single_encoder_cloning(state, crtc, encoder))
11834 return false;
11835 }
11836
11837 return true;
11838 }
11839
11840 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11841 {
11842 struct drm_device *dev = state->dev;
11843 struct intel_encoder *encoder;
11844 struct drm_connector *connector;
11845 struct drm_connector_state *connector_state;
11846 unsigned int used_ports = 0;
11847 int i;
11848
11849 /*
11850 * Walk the connector list instead of the encoder
11851 * list to detect the problem on ddi platforms
11852 * where there's just one encoder per digital port.
11853 */
11854 for_each_connector_in_state(state, connector, connector_state, i) {
11855 if (!connector_state->best_encoder)
11856 continue;
11857
11858 encoder = to_intel_encoder(connector_state->best_encoder);
11859
11860 WARN_ON(!connector_state->crtc);
11861
11862 switch (encoder->type) {
11863 unsigned int port_mask;
11864 case INTEL_OUTPUT_UNKNOWN:
11865 if (WARN_ON(!HAS_DDI(dev)))
11866 break;
11867 case INTEL_OUTPUT_DISPLAYPORT:
11868 case INTEL_OUTPUT_HDMI:
11869 case INTEL_OUTPUT_EDP:
11870 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11871
11872 /* the same port mustn't appear more than once */
11873 if (used_ports & port_mask)
11874 return false;
11875
11876 used_ports |= port_mask;
11877 default:
11878 break;
11879 }
11880 }
11881
11882 return true;
11883 }
11884
11885 static void
11886 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11887 {
11888 struct drm_crtc_state tmp_state;
11889 struct intel_crtc_scaler_state scaler_state;
11890 struct intel_dpll_hw_state dpll_hw_state;
11891 enum intel_dpll_id shared_dpll;
11892 uint32_t ddi_pll_sel;
11893
11894 /* FIXME: before the switch to atomic started, a new pipe_config was
11895 * kzalloc'd. Code that depends on any field being zero should be
11896 * fixed, so that the crtc_state can be safely duplicated. For now,
11897 * only fields that are know to not cause problems are preserved. */
11898
11899 tmp_state = crtc_state->base;
11900 scaler_state = crtc_state->scaler_state;
11901 shared_dpll = crtc_state->shared_dpll;
11902 dpll_hw_state = crtc_state->dpll_hw_state;
11903 ddi_pll_sel = crtc_state->ddi_pll_sel;
11904
11905 memset(crtc_state, 0, sizeof *crtc_state);
11906
11907 crtc_state->base = tmp_state;
11908 crtc_state->scaler_state = scaler_state;
11909 crtc_state->shared_dpll = shared_dpll;
11910 crtc_state->dpll_hw_state = dpll_hw_state;
11911 crtc_state->ddi_pll_sel = ddi_pll_sel;
11912 }
11913
11914 static int
11915 intel_modeset_pipe_config(struct drm_crtc *crtc,
11916 struct drm_atomic_state *state,
11917 struct intel_crtc_state *pipe_config)
11918 {
11919 struct intel_encoder *encoder;
11920 struct drm_connector *connector;
11921 struct drm_connector_state *connector_state;
11922 int base_bpp, ret = -EINVAL;
11923 int i;
11924 bool retry = true;
11925
11926 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11927 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11928 return -EINVAL;
11929 }
11930
11931 if (!check_digital_port_conflicts(state)) {
11932 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11933 return -EINVAL;
11934 }
11935
11936 clear_intel_crtc_state(pipe_config);
11937
11938 pipe_config->cpu_transcoder =
11939 (enum transcoder) to_intel_crtc(crtc)->pipe;
11940
11941 /*
11942 * Sanitize sync polarity flags based on requested ones. If neither
11943 * positive or negative polarity is requested, treat this as meaning
11944 * negative polarity.
11945 */
11946 if (!(pipe_config->base.adjusted_mode.flags &
11947 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11948 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11949
11950 if (!(pipe_config->base.adjusted_mode.flags &
11951 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11952 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11953
11954 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11955 * plane pixel format and any sink constraints into account. Returns the
11956 * source plane bpp so that dithering can be selected on mismatches
11957 * after encoders and crtc also have had their say. */
11958 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11959 pipe_config);
11960 if (base_bpp < 0)
11961 goto fail;
11962
11963 /*
11964 * Determine the real pipe dimensions. Note that stereo modes can
11965 * increase the actual pipe size due to the frame doubling and
11966 * insertion of additional space for blanks between the frame. This
11967 * is stored in the crtc timings. We use the requested mode to do this
11968 * computation to clearly distinguish it from the adjusted mode, which
11969 * can be changed by the connectors in the below retry loop.
11970 */
11971 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11972 &pipe_config->pipe_src_w,
11973 &pipe_config->pipe_src_h);
11974
11975 encoder_retry:
11976 /* Ensure the port clock defaults are reset when retrying. */
11977 pipe_config->port_clock = 0;
11978 pipe_config->pixel_multiplier = 1;
11979
11980 /* Fill in default crtc timings, allow encoders to overwrite them. */
11981 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11982 CRTC_STEREO_DOUBLE);
11983
11984 /* Pass our mode to the connectors and the CRTC to give them a chance to
11985 * adjust it according to limitations or connector properties, and also
11986 * a chance to reject the mode entirely.
11987 */
11988 for_each_connector_in_state(state, connector, connector_state, i) {
11989 if (connector_state->crtc != crtc)
11990 continue;
11991
11992 encoder = to_intel_encoder(connector_state->best_encoder);
11993
11994 if (!(encoder->compute_config(encoder, pipe_config))) {
11995 DRM_DEBUG_KMS("Encoder config failure\n");
11996 goto fail;
11997 }
11998 }
11999
12000 /* Set default port clock if not overwritten by the encoder. Needs to be
12001 * done afterwards in case the encoder adjusts the mode. */
12002 if (!pipe_config->port_clock)
12003 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12004 * pipe_config->pixel_multiplier;
12005
12006 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12007 if (ret < 0) {
12008 DRM_DEBUG_KMS("CRTC fixup failed\n");
12009 goto fail;
12010 }
12011
12012 if (ret == RETRY) {
12013 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12014 ret = -EINVAL;
12015 goto fail;
12016 }
12017
12018 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12019 retry = false;
12020 goto encoder_retry;
12021 }
12022
12023 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12024 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12025 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12026
12027 return 0;
12028 fail:
12029 return ret;
12030 }
12031
12032 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12033 {
12034 struct drm_encoder *encoder;
12035 struct drm_device *dev = crtc->dev;
12036
12037 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12038 if (encoder->crtc == crtc)
12039 return true;
12040
12041 return false;
12042 }
12043
12044 static bool
12045 needs_modeset(struct drm_crtc_state *state)
12046 {
12047 return state->mode_changed || state->active_changed;
12048 }
12049
12050 static void
12051 intel_modeset_update_state(struct drm_atomic_state *state)
12052 {
12053 struct drm_device *dev = state->dev;
12054 struct drm_i915_private *dev_priv = dev->dev_private;
12055 struct intel_encoder *intel_encoder;
12056 struct drm_crtc *crtc;
12057 struct drm_crtc_state *crtc_state;
12058 struct drm_connector *connector;
12059 int i;
12060
12061 intel_shared_dpll_commit(dev_priv);
12062
12063 for_each_intel_encoder(dev, intel_encoder) {
12064 if (!intel_encoder->base.crtc)
12065 continue;
12066
12067 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12068 if (crtc != intel_encoder->base.crtc)
12069 continue;
12070
12071 if (crtc_state->enable && needs_modeset(crtc_state))
12072 intel_encoder->connectors_active = false;
12073
12074 break;
12075 }
12076 }
12077
12078 drm_atomic_helper_swap_state(state->dev, state);
12079 intel_modeset_fixup_state(state);
12080
12081 /* Double check state. */
12082 for_each_crtc(dev, crtc) {
12083 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12084 }
12085
12086 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12087 if (!connector->encoder || !connector->encoder->crtc)
12088 continue;
12089
12090 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12091 if (crtc != connector->encoder->crtc)
12092 continue;
12093
12094 if (crtc->state->enable && needs_modeset(crtc->state)) {
12095 struct drm_property *dpms_property =
12096 dev->mode_config.dpms_property;
12097
12098 connector->dpms = DRM_MODE_DPMS_ON;
12099 drm_object_property_set_value(&connector->base,
12100 dpms_property,
12101 DRM_MODE_DPMS_ON);
12102
12103 intel_encoder = to_intel_encoder(connector->encoder);
12104 intel_encoder->connectors_active = true;
12105 }
12106
12107 break;
12108 }
12109 }
12110
12111 }
12112
12113 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12114 {
12115 int diff;
12116
12117 if (clock1 == clock2)
12118 return true;
12119
12120 if (!clock1 || !clock2)
12121 return false;
12122
12123 diff = abs(clock1 - clock2);
12124
12125 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12126 return true;
12127
12128 return false;
12129 }
12130
12131 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12132 list_for_each_entry((intel_crtc), \
12133 &(dev)->mode_config.crtc_list, \
12134 base.head) \
12135 if (mask & (1 <<(intel_crtc)->pipe))
12136
12137 static bool
12138 intel_pipe_config_compare(struct drm_device *dev,
12139 struct intel_crtc_state *current_config,
12140 struct intel_crtc_state *pipe_config)
12141 {
12142 #define PIPE_CONF_CHECK_X(name) \
12143 if (current_config->name != pipe_config->name) { \
12144 DRM_ERROR("mismatch in " #name " " \
12145 "(expected 0x%08x, found 0x%08x)\n", \
12146 current_config->name, \
12147 pipe_config->name); \
12148 return false; \
12149 }
12150
12151 #define PIPE_CONF_CHECK_I(name) \
12152 if (current_config->name != pipe_config->name) { \
12153 DRM_ERROR("mismatch in " #name " " \
12154 "(expected %i, found %i)\n", \
12155 current_config->name, \
12156 pipe_config->name); \
12157 return false; \
12158 }
12159
12160 /* This is required for BDW+ where there is only one set of registers for
12161 * switching between high and low RR.
12162 * This macro can be used whenever a comparison has to be made between one
12163 * hw state and multiple sw state variables.
12164 */
12165 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12166 if ((current_config->name != pipe_config->name) && \
12167 (current_config->alt_name != pipe_config->name)) { \
12168 DRM_ERROR("mismatch in " #name " " \
12169 "(expected %i or %i, found %i)\n", \
12170 current_config->name, \
12171 current_config->alt_name, \
12172 pipe_config->name); \
12173 return false; \
12174 }
12175
12176 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12177 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12178 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12179 "(expected %i, found %i)\n", \
12180 current_config->name & (mask), \
12181 pipe_config->name & (mask)); \
12182 return false; \
12183 }
12184
12185 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12186 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12187 DRM_ERROR("mismatch in " #name " " \
12188 "(expected %i, found %i)\n", \
12189 current_config->name, \
12190 pipe_config->name); \
12191 return false; \
12192 }
12193
12194 #define PIPE_CONF_QUIRK(quirk) \
12195 ((current_config->quirks | pipe_config->quirks) & (quirk))
12196
12197 PIPE_CONF_CHECK_I(cpu_transcoder);
12198
12199 PIPE_CONF_CHECK_I(has_pch_encoder);
12200 PIPE_CONF_CHECK_I(fdi_lanes);
12201 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12202 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12203 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12204 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12205 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12206
12207 PIPE_CONF_CHECK_I(has_dp_encoder);
12208
12209 if (INTEL_INFO(dev)->gen < 8) {
12210 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12211 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12212 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12213 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12214 PIPE_CONF_CHECK_I(dp_m_n.tu);
12215
12216 if (current_config->has_drrs) {
12217 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12218 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12219 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12220 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12221 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12222 }
12223 } else {
12224 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12225 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12226 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12227 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12228 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12229 }
12230
12231 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12232 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12233 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12234 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12235 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12236 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12237
12238 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12239 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12240 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12241 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12242 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12243 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12244
12245 PIPE_CONF_CHECK_I(pixel_multiplier);
12246 PIPE_CONF_CHECK_I(has_hdmi_sink);
12247 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12248 IS_VALLEYVIEW(dev))
12249 PIPE_CONF_CHECK_I(limited_color_range);
12250 PIPE_CONF_CHECK_I(has_infoframe);
12251
12252 PIPE_CONF_CHECK_I(has_audio);
12253
12254 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12255 DRM_MODE_FLAG_INTERLACE);
12256
12257 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12258 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12259 DRM_MODE_FLAG_PHSYNC);
12260 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12261 DRM_MODE_FLAG_NHSYNC);
12262 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12263 DRM_MODE_FLAG_PVSYNC);
12264 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12265 DRM_MODE_FLAG_NVSYNC);
12266 }
12267
12268 PIPE_CONF_CHECK_I(pipe_src_w);
12269 PIPE_CONF_CHECK_I(pipe_src_h);
12270
12271 /*
12272 * FIXME: BIOS likes to set up a cloned config with lvds+external
12273 * screen. Since we don't yet re-compute the pipe config when moving
12274 * just the lvds port away to another pipe the sw tracking won't match.
12275 *
12276 * Proper atomic modesets with recomputed global state will fix this.
12277 * Until then just don't check gmch state for inherited modes.
12278 */
12279 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12280 PIPE_CONF_CHECK_I(gmch_pfit.control);
12281 /* pfit ratios are autocomputed by the hw on gen4+ */
12282 if (INTEL_INFO(dev)->gen < 4)
12283 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12284 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12285 }
12286
12287 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12288 if (current_config->pch_pfit.enabled) {
12289 PIPE_CONF_CHECK_I(pch_pfit.pos);
12290 PIPE_CONF_CHECK_I(pch_pfit.size);
12291 }
12292
12293 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12294
12295 /* BDW+ don't expose a synchronous way to read the state */
12296 if (IS_HASWELL(dev))
12297 PIPE_CONF_CHECK_I(ips_enabled);
12298
12299 PIPE_CONF_CHECK_I(double_wide);
12300
12301 PIPE_CONF_CHECK_X(ddi_pll_sel);
12302
12303 PIPE_CONF_CHECK_I(shared_dpll);
12304 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12305 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12306 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12307 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12308 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12309 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12310 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12311 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12312
12313 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12314 PIPE_CONF_CHECK_I(pipe_bpp);
12315
12316 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12317 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12318
12319 #undef PIPE_CONF_CHECK_X
12320 #undef PIPE_CONF_CHECK_I
12321 #undef PIPE_CONF_CHECK_I_ALT
12322 #undef PIPE_CONF_CHECK_FLAGS
12323 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12324 #undef PIPE_CONF_QUIRK
12325
12326 return true;
12327 }
12328
12329 static void check_wm_state(struct drm_device *dev)
12330 {
12331 struct drm_i915_private *dev_priv = dev->dev_private;
12332 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12333 struct intel_crtc *intel_crtc;
12334 int plane;
12335
12336 if (INTEL_INFO(dev)->gen < 9)
12337 return;
12338
12339 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12340 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12341
12342 for_each_intel_crtc(dev, intel_crtc) {
12343 struct skl_ddb_entry *hw_entry, *sw_entry;
12344 const enum pipe pipe = intel_crtc->pipe;
12345
12346 if (!intel_crtc->active)
12347 continue;
12348
12349 /* planes */
12350 for_each_plane(dev_priv, pipe, plane) {
12351 hw_entry = &hw_ddb.plane[pipe][plane];
12352 sw_entry = &sw_ddb->plane[pipe][plane];
12353
12354 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12355 continue;
12356
12357 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12358 "(expected (%u,%u), found (%u,%u))\n",
12359 pipe_name(pipe), plane + 1,
12360 sw_entry->start, sw_entry->end,
12361 hw_entry->start, hw_entry->end);
12362 }
12363
12364 /* cursor */
12365 hw_entry = &hw_ddb.cursor[pipe];
12366 sw_entry = &sw_ddb->cursor[pipe];
12367
12368 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12369 continue;
12370
12371 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12372 "(expected (%u,%u), found (%u,%u))\n",
12373 pipe_name(pipe),
12374 sw_entry->start, sw_entry->end,
12375 hw_entry->start, hw_entry->end);
12376 }
12377 }
12378
12379 static void
12380 check_connector_state(struct drm_device *dev)
12381 {
12382 struct intel_connector *connector;
12383
12384 for_each_intel_connector(dev, connector) {
12385 /* This also checks the encoder/connector hw state with the
12386 * ->get_hw_state callbacks. */
12387 intel_connector_check_state(connector);
12388
12389 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12390 "connector's staged encoder doesn't match current encoder\n");
12391 }
12392 }
12393
12394 static void
12395 check_encoder_state(struct drm_device *dev)
12396 {
12397 struct intel_encoder *encoder;
12398 struct intel_connector *connector;
12399
12400 for_each_intel_encoder(dev, encoder) {
12401 bool enabled = false;
12402 bool active = false;
12403 enum pipe pipe, tracked_pipe;
12404
12405 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12406 encoder->base.base.id,
12407 encoder->base.name);
12408
12409 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12410 "encoder's stage crtc doesn't match current crtc\n");
12411 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12412 "encoder's active_connectors set, but no crtc\n");
12413
12414 for_each_intel_connector(dev, connector) {
12415 if (connector->base.encoder != &encoder->base)
12416 continue;
12417 enabled = true;
12418 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12419 active = true;
12420 }
12421 /*
12422 * for MST connectors if we unplug the connector is gone
12423 * away but the encoder is still connected to a crtc
12424 * until a modeset happens in response to the hotplug.
12425 */
12426 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12427 continue;
12428
12429 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12430 "encoder's enabled state mismatch "
12431 "(expected %i, found %i)\n",
12432 !!encoder->base.crtc, enabled);
12433 I915_STATE_WARN(active && !encoder->base.crtc,
12434 "active encoder with no crtc\n");
12435
12436 I915_STATE_WARN(encoder->connectors_active != active,
12437 "encoder's computed active state doesn't match tracked active state "
12438 "(expected %i, found %i)\n", active, encoder->connectors_active);
12439
12440 active = encoder->get_hw_state(encoder, &pipe);
12441 I915_STATE_WARN(active != encoder->connectors_active,
12442 "encoder's hw state doesn't match sw tracking "
12443 "(expected %i, found %i)\n",
12444 encoder->connectors_active, active);
12445
12446 if (!encoder->base.crtc)
12447 continue;
12448
12449 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12450 I915_STATE_WARN(active && pipe != tracked_pipe,
12451 "active encoder's pipe doesn't match"
12452 "(expected %i, found %i)\n",
12453 tracked_pipe, pipe);
12454
12455 }
12456 }
12457
12458 static void
12459 check_crtc_state(struct drm_device *dev)
12460 {
12461 struct drm_i915_private *dev_priv = dev->dev_private;
12462 struct intel_crtc *crtc;
12463 struct intel_encoder *encoder;
12464 struct intel_crtc_state pipe_config;
12465
12466 for_each_intel_crtc(dev, crtc) {
12467 bool enabled = false;
12468 bool active = false;
12469
12470 memset(&pipe_config, 0, sizeof(pipe_config));
12471
12472 DRM_DEBUG_KMS("[CRTC:%d]\n",
12473 crtc->base.base.id);
12474
12475 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12476 "active crtc, but not enabled in sw tracking\n");
12477
12478 for_each_intel_encoder(dev, encoder) {
12479 if (encoder->base.crtc != &crtc->base)
12480 continue;
12481 enabled = true;
12482 if (encoder->connectors_active)
12483 active = true;
12484 }
12485
12486 I915_STATE_WARN(active != crtc->active,
12487 "crtc's computed active state doesn't match tracked active state "
12488 "(expected %i, found %i)\n", active, crtc->active);
12489 I915_STATE_WARN(enabled != crtc->base.state->enable,
12490 "crtc's computed enabled state doesn't match tracked enabled state "
12491 "(expected %i, found %i)\n", enabled,
12492 crtc->base.state->enable);
12493
12494 active = dev_priv->display.get_pipe_config(crtc,
12495 &pipe_config);
12496
12497 /* hw state is inconsistent with the pipe quirk */
12498 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12499 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12500 active = crtc->active;
12501
12502 for_each_intel_encoder(dev, encoder) {
12503 enum pipe pipe;
12504 if (encoder->base.crtc != &crtc->base)
12505 continue;
12506 if (encoder->get_hw_state(encoder, &pipe))
12507 encoder->get_config(encoder, &pipe_config);
12508 }
12509
12510 I915_STATE_WARN(crtc->active != active,
12511 "crtc active state doesn't match with hw state "
12512 "(expected %i, found %i)\n", crtc->active, active);
12513
12514 if (active &&
12515 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12516 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12517 intel_dump_pipe_config(crtc, &pipe_config,
12518 "[hw state]");
12519 intel_dump_pipe_config(crtc, crtc->config,
12520 "[sw state]");
12521 }
12522 }
12523 }
12524
12525 static void
12526 check_shared_dpll_state(struct drm_device *dev)
12527 {
12528 struct drm_i915_private *dev_priv = dev->dev_private;
12529 struct intel_crtc *crtc;
12530 struct intel_dpll_hw_state dpll_hw_state;
12531 int i;
12532
12533 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12534 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12535 int enabled_crtcs = 0, active_crtcs = 0;
12536 bool active;
12537
12538 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12539
12540 DRM_DEBUG_KMS("%s\n", pll->name);
12541
12542 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12543
12544 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12545 "more active pll users than references: %i vs %i\n",
12546 pll->active, hweight32(pll->config.crtc_mask));
12547 I915_STATE_WARN(pll->active && !pll->on,
12548 "pll in active use but not on in sw tracking\n");
12549 I915_STATE_WARN(pll->on && !pll->active,
12550 "pll in on but not on in use in sw tracking\n");
12551 I915_STATE_WARN(pll->on != active,
12552 "pll on state mismatch (expected %i, found %i)\n",
12553 pll->on, active);
12554
12555 for_each_intel_crtc(dev, crtc) {
12556 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12557 enabled_crtcs++;
12558 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12559 active_crtcs++;
12560 }
12561 I915_STATE_WARN(pll->active != active_crtcs,
12562 "pll active crtcs mismatch (expected %i, found %i)\n",
12563 pll->active, active_crtcs);
12564 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12565 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12566 hweight32(pll->config.crtc_mask), enabled_crtcs);
12567
12568 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12569 sizeof(dpll_hw_state)),
12570 "pll hw state mismatch\n");
12571 }
12572 }
12573
12574 void
12575 intel_modeset_check_state(struct drm_device *dev)
12576 {
12577 check_wm_state(dev);
12578 check_connector_state(dev);
12579 check_encoder_state(dev);
12580 check_crtc_state(dev);
12581 check_shared_dpll_state(dev);
12582 }
12583
12584 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12585 int dotclock)
12586 {
12587 /*
12588 * FDI already provided one idea for the dotclock.
12589 * Yell if the encoder disagrees.
12590 */
12591 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12592 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12593 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12594 }
12595
12596 static void update_scanline_offset(struct intel_crtc *crtc)
12597 {
12598 struct drm_device *dev = crtc->base.dev;
12599
12600 /*
12601 * The scanline counter increments at the leading edge of hsync.
12602 *
12603 * On most platforms it starts counting from vtotal-1 on the
12604 * first active line. That means the scanline counter value is
12605 * always one less than what we would expect. Ie. just after
12606 * start of vblank, which also occurs at start of hsync (on the
12607 * last active line), the scanline counter will read vblank_start-1.
12608 *
12609 * On gen2 the scanline counter starts counting from 1 instead
12610 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12611 * to keep the value positive), instead of adding one.
12612 *
12613 * On HSW+ the behaviour of the scanline counter depends on the output
12614 * type. For DP ports it behaves like most other platforms, but on HDMI
12615 * there's an extra 1 line difference. So we need to add two instead of
12616 * one to the value.
12617 */
12618 if (IS_GEN2(dev)) {
12619 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12620 int vtotal;
12621
12622 vtotal = mode->crtc_vtotal;
12623 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12624 vtotal /= 2;
12625
12626 crtc->scanline_offset = vtotal - 1;
12627 } else if (HAS_DDI(dev) &&
12628 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12629 crtc->scanline_offset = 2;
12630 } else
12631 crtc->scanline_offset = 1;
12632 }
12633
12634 static struct intel_crtc_state *
12635 intel_modeset_compute_config(struct drm_crtc *crtc,
12636 struct drm_atomic_state *state)
12637 {
12638 struct intel_crtc_state *pipe_config;
12639 int ret = 0;
12640
12641 ret = drm_atomic_add_affected_connectors(state, crtc);
12642 if (ret)
12643 return ERR_PTR(ret);
12644
12645 ret = drm_atomic_helper_check_modeset(state->dev, state);
12646 if (ret)
12647 return ERR_PTR(ret);
12648
12649 /*
12650 * Note this needs changes when we start tracking multiple modes
12651 * and crtcs. At that point we'll need to compute the whole config
12652 * (i.e. one pipe_config for each crtc) rather than just the one
12653 * for this crtc.
12654 */
12655 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12656 if (IS_ERR(pipe_config))
12657 return pipe_config;
12658
12659 if (!pipe_config->base.enable)
12660 return pipe_config;
12661
12662 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12663 if (ret)
12664 return ERR_PTR(ret);
12665
12666 /* Check things that can only be changed through modeset */
12667 if (pipe_config->has_audio !=
12668 to_intel_crtc(crtc)->config->has_audio)
12669 pipe_config->base.mode_changed = true;
12670
12671 /*
12672 * Note we have an issue here with infoframes: current code
12673 * only updates them on the full mode set path per hw
12674 * requirements. So here we should be checking for any
12675 * required changes and forcing a mode set.
12676 */
12677
12678 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12679
12680 ret = drm_atomic_helper_check_planes(state->dev, state);
12681 if (ret)
12682 return ERR_PTR(ret);
12683
12684 return pipe_config;
12685 }
12686
12687 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12688 {
12689 struct drm_device *dev = state->dev;
12690 struct drm_i915_private *dev_priv = to_i915(dev);
12691 unsigned clear_pipes = 0;
12692 struct intel_crtc *intel_crtc;
12693 struct intel_crtc_state *intel_crtc_state;
12694 struct drm_crtc *crtc;
12695 struct drm_crtc_state *crtc_state;
12696 int ret = 0;
12697 int i;
12698
12699 if (!dev_priv->display.crtc_compute_clock)
12700 return 0;
12701
12702 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12703 intel_crtc = to_intel_crtc(crtc);
12704 intel_crtc_state = to_intel_crtc_state(crtc_state);
12705
12706 if (needs_modeset(crtc_state)) {
12707 clear_pipes |= 1 << intel_crtc->pipe;
12708 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12709 }
12710 }
12711
12712 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12713 if (ret)
12714 goto done;
12715
12716 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12717 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12718 continue;
12719
12720 intel_crtc = to_intel_crtc(crtc);
12721 intel_crtc_state = to_intel_crtc_state(crtc_state);
12722
12723 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12724 intel_crtc_state);
12725 if (ret) {
12726 intel_shared_dpll_abort_config(dev_priv);
12727 goto done;
12728 }
12729 }
12730
12731 done:
12732 return ret;
12733 }
12734
12735 /* Code that should eventually be part of atomic_check() */
12736 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12737 {
12738 struct drm_device *dev = state->dev;
12739 int ret;
12740
12741 /*
12742 * See if the config requires any additional preparation, e.g.
12743 * to adjust global state with pipes off. We need to do this
12744 * here so we can get the modeset_pipe updated config for the new
12745 * mode set on this crtc. For other crtcs we need to use the
12746 * adjusted_mode bits in the crtc directly.
12747 */
12748 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12749 ret = valleyview_modeset_global_pipes(state);
12750 if (ret)
12751 return ret;
12752 }
12753
12754 ret = __intel_set_mode_setup_plls(state);
12755 if (ret)
12756 return ret;
12757
12758 return 0;
12759 }
12760
12761 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12762 struct intel_crtc_state *pipe_config)
12763 {
12764 struct drm_device *dev = modeset_crtc->dev;
12765 struct drm_i915_private *dev_priv = dev->dev_private;
12766 struct drm_atomic_state *state = pipe_config->base.state;
12767 struct drm_crtc *crtc;
12768 struct drm_crtc_state *crtc_state;
12769 int ret = 0;
12770 int i;
12771
12772 ret = __intel_set_mode_checks(state);
12773 if (ret < 0)
12774 return ret;
12775
12776 ret = drm_atomic_helper_prepare_planes(dev, state);
12777 if (ret)
12778 return ret;
12779
12780 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12781 if (!needs_modeset(crtc_state))
12782 continue;
12783
12784 if (!crtc_state->enable) {
12785 intel_crtc_disable(crtc);
12786 } else if (crtc->state->enable) {
12787 intel_crtc_disable_planes(crtc);
12788 dev_priv->display.crtc_disable(crtc);
12789 }
12790 }
12791
12792 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12793 * to set it here already despite that we pass it down the callchain.
12794 *
12795 * Note we'll need to fix this up when we start tracking multiple
12796 * pipes; here we assume a single modeset_pipe and only track the
12797 * single crtc and mode.
12798 */
12799 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12800 modeset_crtc->mode = pipe_config->base.mode;
12801
12802 /*
12803 * Calculate and store various constants which
12804 * are later needed by vblank and swap-completion
12805 * timestamping. They are derived from true hwmode.
12806 */
12807 drm_calc_timestamping_constants(modeset_crtc,
12808 &pipe_config->base.adjusted_mode);
12809 }
12810
12811 /* Only after disabling all output pipelines that will be changed can we
12812 * update the the output configuration. */
12813 intel_modeset_update_state(state);
12814
12815 /* The state has been swaped above, so state actually contains the
12816 * old state now. */
12817
12818 modeset_update_crtc_power_domains(state);
12819
12820 drm_atomic_helper_commit_planes(dev, state);
12821
12822 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12823 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12824 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12825 continue;
12826
12827 update_scanline_offset(to_intel_crtc(crtc));
12828
12829 dev_priv->display.crtc_enable(crtc);
12830 intel_crtc_enable_planes(crtc);
12831 }
12832
12833 /* FIXME: add subpixel order */
12834
12835 drm_atomic_helper_cleanup_planes(dev, state);
12836
12837 drm_atomic_state_free(state);
12838
12839 return 0;
12840 }
12841
12842 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12843 struct intel_crtc_state *pipe_config)
12844 {
12845 int ret;
12846
12847 ret = __intel_set_mode(crtc, pipe_config);
12848
12849 if (ret == 0)
12850 intel_modeset_check_state(crtc->dev);
12851
12852 return ret;
12853 }
12854
12855 static int intel_set_mode(struct drm_crtc *crtc,
12856 struct drm_atomic_state *state)
12857 {
12858 struct intel_crtc_state *pipe_config;
12859 int ret = 0;
12860
12861 pipe_config = intel_modeset_compute_config(crtc, state);
12862 if (IS_ERR(pipe_config)) {
12863 ret = PTR_ERR(pipe_config);
12864 goto out;
12865 }
12866
12867 ret = intel_set_mode_with_config(crtc, pipe_config);
12868 if (ret)
12869 goto out;
12870
12871 out:
12872 return ret;
12873 }
12874
12875 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12876 {
12877 struct drm_device *dev = crtc->dev;
12878 struct drm_atomic_state *state;
12879 struct intel_crtc *intel_crtc;
12880 struct intel_encoder *encoder;
12881 struct intel_connector *connector;
12882 struct drm_connector_state *connector_state;
12883 struct intel_crtc_state *crtc_state;
12884 int ret;
12885
12886 state = drm_atomic_state_alloc(dev);
12887 if (!state) {
12888 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12889 crtc->base.id);
12890 return;
12891 }
12892
12893 state->acquire_ctx = dev->mode_config.acquire_ctx;
12894
12895 /* The force restore path in the HW readout code relies on the staged
12896 * config still keeping the user requested config while the actual
12897 * state has been overwritten by the configuration read from HW. We
12898 * need to copy the staged config to the atomic state, otherwise the
12899 * mode set will just reapply the state the HW is already in. */
12900 for_each_intel_encoder(dev, encoder) {
12901 if (&encoder->new_crtc->base != crtc)
12902 continue;
12903
12904 for_each_intel_connector(dev, connector) {
12905 if (connector->new_encoder != encoder)
12906 continue;
12907
12908 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12909 if (IS_ERR(connector_state)) {
12910 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12911 connector->base.base.id,
12912 connector->base.name,
12913 PTR_ERR(connector_state));
12914 continue;
12915 }
12916
12917 connector_state->crtc = crtc;
12918 connector_state->best_encoder = &encoder->base;
12919 }
12920 }
12921
12922 for_each_intel_crtc(dev, intel_crtc) {
12923 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12924 continue;
12925
12926 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12927 if (IS_ERR(crtc_state)) {
12928 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12929 intel_crtc->base.base.id,
12930 PTR_ERR(crtc_state));
12931 continue;
12932 }
12933
12934 crtc_state->base.active = crtc_state->base.enable =
12935 intel_crtc->new_enabled;
12936
12937 if (&intel_crtc->base == crtc)
12938 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12939 }
12940
12941 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12942 crtc->primary->fb, crtc->x, crtc->y);
12943
12944 ret = intel_set_mode(crtc, state);
12945 if (ret)
12946 drm_atomic_state_free(state);
12947 }
12948
12949 #undef for_each_intel_crtc_masked
12950
12951 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12952 struct drm_mode_set *set)
12953 {
12954 int ro;
12955
12956 for (ro = 0; ro < set->num_connectors; ro++)
12957 if (set->connectors[ro] == &connector->base)
12958 return true;
12959
12960 return false;
12961 }
12962
12963 static int
12964 intel_modeset_stage_output_state(struct drm_device *dev,
12965 struct drm_mode_set *set,
12966 struct drm_atomic_state *state)
12967 {
12968 struct intel_connector *connector;
12969 struct drm_connector *drm_connector;
12970 struct drm_connector_state *connector_state;
12971 struct drm_crtc *crtc;
12972 struct drm_crtc_state *crtc_state;
12973 int i, ret;
12974
12975 /* The upper layers ensure that we either disable a crtc or have a list
12976 * of connectors. For paranoia, double-check this. */
12977 WARN_ON(!set->fb && (set->num_connectors != 0));
12978 WARN_ON(set->fb && (set->num_connectors == 0));
12979
12980 for_each_intel_connector(dev, connector) {
12981 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12982
12983 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12984 continue;
12985
12986 connector_state =
12987 drm_atomic_get_connector_state(state, &connector->base);
12988 if (IS_ERR(connector_state))
12989 return PTR_ERR(connector_state);
12990
12991 if (in_mode_set) {
12992 int pipe = to_intel_crtc(set->crtc)->pipe;
12993 connector_state->best_encoder =
12994 &intel_find_encoder(connector, pipe)->base;
12995 }
12996
12997 if (connector->base.state->crtc != set->crtc)
12998 continue;
12999
13000 /* If we disable the crtc, disable all its connectors. Also, if
13001 * the connector is on the changing crtc but not on the new
13002 * connector list, disable it. */
13003 if (!set->fb || !in_mode_set) {
13004 connector_state->best_encoder = NULL;
13005
13006 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13007 connector->base.base.id,
13008 connector->base.name);
13009 }
13010 }
13011 /* connector->new_encoder is now updated for all connectors. */
13012
13013 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13014 connector = to_intel_connector(drm_connector);
13015
13016 if (!connector_state->best_encoder) {
13017 ret = drm_atomic_set_crtc_for_connector(connector_state,
13018 NULL);
13019 if (ret)
13020 return ret;
13021
13022 continue;
13023 }
13024
13025 if (intel_connector_in_mode_set(connector, set)) {
13026 struct drm_crtc *crtc = connector->base.state->crtc;
13027
13028 /* If this connector was in a previous crtc, add it
13029 * to the state. We might need to disable it. */
13030 if (crtc) {
13031 crtc_state =
13032 drm_atomic_get_crtc_state(state, crtc);
13033 if (IS_ERR(crtc_state))
13034 return PTR_ERR(crtc_state);
13035 }
13036
13037 ret = drm_atomic_set_crtc_for_connector(connector_state,
13038 set->crtc);
13039 if (ret)
13040 return ret;
13041 }
13042
13043 /* Make sure the new CRTC will work with the encoder */
13044 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13045 connector_state->crtc)) {
13046 return -EINVAL;
13047 }
13048
13049 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13050 connector->base.base.id,
13051 connector->base.name,
13052 connector_state->crtc->base.id);
13053
13054 if (connector_state->best_encoder != &connector->encoder->base)
13055 connector->encoder =
13056 to_intel_encoder(connector_state->best_encoder);
13057 }
13058
13059 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13060 bool has_connectors;
13061
13062 ret = drm_atomic_add_affected_connectors(state, crtc);
13063 if (ret)
13064 return ret;
13065
13066 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13067 if (has_connectors != crtc_state->enable)
13068 crtc_state->enable =
13069 crtc_state->active = has_connectors;
13070 }
13071
13072 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13073 set->fb, set->x, set->y);
13074 if (ret)
13075 return ret;
13076
13077 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13078 if (IS_ERR(crtc_state))
13079 return PTR_ERR(crtc_state);
13080
13081 if (set->mode)
13082 drm_mode_copy(&crtc_state->mode, set->mode);
13083
13084 if (set->num_connectors)
13085 crtc_state->active = true;
13086
13087 return 0;
13088 }
13089
13090 static bool primary_plane_visible(struct drm_crtc *crtc)
13091 {
13092 struct intel_plane_state *plane_state =
13093 to_intel_plane_state(crtc->primary->state);
13094
13095 return plane_state->visible;
13096 }
13097
13098 static int intel_crtc_set_config(struct drm_mode_set *set)
13099 {
13100 struct drm_device *dev;
13101 struct drm_atomic_state *state = NULL;
13102 struct intel_crtc_state *pipe_config;
13103 bool primary_plane_was_visible;
13104 int ret;
13105
13106 BUG_ON(!set);
13107 BUG_ON(!set->crtc);
13108 BUG_ON(!set->crtc->helper_private);
13109
13110 /* Enforce sane interface api - has been abused by the fb helper. */
13111 BUG_ON(!set->mode && set->fb);
13112 BUG_ON(set->fb && set->num_connectors == 0);
13113
13114 if (set->fb) {
13115 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13116 set->crtc->base.id, set->fb->base.id,
13117 (int)set->num_connectors, set->x, set->y);
13118 } else {
13119 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13120 }
13121
13122 dev = set->crtc->dev;
13123
13124 state = drm_atomic_state_alloc(dev);
13125 if (!state)
13126 return -ENOMEM;
13127
13128 state->acquire_ctx = dev->mode_config.acquire_ctx;
13129
13130 ret = intel_modeset_stage_output_state(dev, set, state);
13131 if (ret)
13132 goto out;
13133
13134 pipe_config = intel_modeset_compute_config(set->crtc, state);
13135 if (IS_ERR(pipe_config)) {
13136 ret = PTR_ERR(pipe_config);
13137 goto out;
13138 }
13139
13140 intel_update_pipe_size(to_intel_crtc(set->crtc));
13141
13142 primary_plane_was_visible = primary_plane_visible(set->crtc);
13143
13144 ret = intel_set_mode_with_config(set->crtc, pipe_config);
13145
13146 if (ret == 0 &&
13147 pipe_config->base.enable &&
13148 pipe_config->base.planes_changed &&
13149 !needs_modeset(&pipe_config->base)) {
13150 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
13151
13152 /*
13153 * We need to make sure the primary plane is re-enabled if it
13154 * has previously been turned off.
13155 */
13156 if (ret == 0 && !primary_plane_was_visible &&
13157 primary_plane_visible(set->crtc)) {
13158 WARN_ON(!intel_crtc->active);
13159 intel_post_enable_primary(set->crtc);
13160 }
13161
13162 /*
13163 * In the fastboot case this may be our only check of the
13164 * state after boot. It would be better to only do it on
13165 * the first update, but we don't have a nice way of doing that
13166 * (and really, set_config isn't used much for high freq page
13167 * flipping, so increasing its cost here shouldn't be a big
13168 * deal).
13169 */
13170 if (i915.fastboot && ret == 0)
13171 intel_modeset_check_state(set->crtc->dev);
13172 }
13173
13174 if (ret) {
13175 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13176 set->crtc->base.id, ret);
13177 }
13178
13179 out:
13180 if (ret)
13181 drm_atomic_state_free(state);
13182 return ret;
13183 }
13184
13185 static const struct drm_crtc_funcs intel_crtc_funcs = {
13186 .gamma_set = intel_crtc_gamma_set,
13187 .set_config = intel_crtc_set_config,
13188 .destroy = intel_crtc_destroy,
13189 .page_flip = intel_crtc_page_flip,
13190 .atomic_duplicate_state = intel_crtc_duplicate_state,
13191 .atomic_destroy_state = intel_crtc_destroy_state,
13192 };
13193
13194 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13195 struct intel_shared_dpll *pll,
13196 struct intel_dpll_hw_state *hw_state)
13197 {
13198 uint32_t val;
13199
13200 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13201 return false;
13202
13203 val = I915_READ(PCH_DPLL(pll->id));
13204 hw_state->dpll = val;
13205 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13206 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13207
13208 return val & DPLL_VCO_ENABLE;
13209 }
13210
13211 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13212 struct intel_shared_dpll *pll)
13213 {
13214 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13215 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13216 }
13217
13218 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13219 struct intel_shared_dpll *pll)
13220 {
13221 /* PCH refclock must be enabled first */
13222 ibx_assert_pch_refclk_enabled(dev_priv);
13223
13224 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13225
13226 /* Wait for the clocks to stabilize. */
13227 POSTING_READ(PCH_DPLL(pll->id));
13228 udelay(150);
13229
13230 /* The pixel multiplier can only be updated once the
13231 * DPLL is enabled and the clocks are stable.
13232 *
13233 * So write it again.
13234 */
13235 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13236 POSTING_READ(PCH_DPLL(pll->id));
13237 udelay(200);
13238 }
13239
13240 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13241 struct intel_shared_dpll *pll)
13242 {
13243 struct drm_device *dev = dev_priv->dev;
13244 struct intel_crtc *crtc;
13245
13246 /* Make sure no transcoder isn't still depending on us. */
13247 for_each_intel_crtc(dev, crtc) {
13248 if (intel_crtc_to_shared_dpll(crtc) == pll)
13249 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13250 }
13251
13252 I915_WRITE(PCH_DPLL(pll->id), 0);
13253 POSTING_READ(PCH_DPLL(pll->id));
13254 udelay(200);
13255 }
13256
13257 static char *ibx_pch_dpll_names[] = {
13258 "PCH DPLL A",
13259 "PCH DPLL B",
13260 };
13261
13262 static void ibx_pch_dpll_init(struct drm_device *dev)
13263 {
13264 struct drm_i915_private *dev_priv = dev->dev_private;
13265 int i;
13266
13267 dev_priv->num_shared_dpll = 2;
13268
13269 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13270 dev_priv->shared_dplls[i].id = i;
13271 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13272 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13273 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13274 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13275 dev_priv->shared_dplls[i].get_hw_state =
13276 ibx_pch_dpll_get_hw_state;
13277 }
13278 }
13279
13280 static void intel_shared_dpll_init(struct drm_device *dev)
13281 {
13282 struct drm_i915_private *dev_priv = dev->dev_private;
13283
13284 intel_update_cdclk(dev);
13285
13286 if (HAS_DDI(dev))
13287 intel_ddi_pll_init(dev);
13288 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13289 ibx_pch_dpll_init(dev);
13290 else
13291 dev_priv->num_shared_dpll = 0;
13292
13293 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13294 }
13295
13296 /**
13297 * intel_wm_need_update - Check whether watermarks need updating
13298 * @plane: drm plane
13299 * @state: new plane state
13300 *
13301 * Check current plane state versus the new one to determine whether
13302 * watermarks need to be recalculated.
13303 *
13304 * Returns true or false.
13305 */
13306 bool intel_wm_need_update(struct drm_plane *plane,
13307 struct drm_plane_state *state)
13308 {
13309 /* Update watermarks on tiling changes. */
13310 if (!plane->state->fb || !state->fb ||
13311 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13312 plane->state->rotation != state->rotation)
13313 return true;
13314
13315 return false;
13316 }
13317
13318 /**
13319 * intel_prepare_plane_fb - Prepare fb for usage on plane
13320 * @plane: drm plane to prepare for
13321 * @fb: framebuffer to prepare for presentation
13322 *
13323 * Prepares a framebuffer for usage on a display plane. Generally this
13324 * involves pinning the underlying object and updating the frontbuffer tracking
13325 * bits. Some older platforms need special physical address handling for
13326 * cursor planes.
13327 *
13328 * Returns 0 on success, negative error code on failure.
13329 */
13330 int
13331 intel_prepare_plane_fb(struct drm_plane *plane,
13332 struct drm_framebuffer *fb,
13333 const struct drm_plane_state *new_state)
13334 {
13335 struct drm_device *dev = plane->dev;
13336 struct intel_plane *intel_plane = to_intel_plane(plane);
13337 enum pipe pipe = intel_plane->pipe;
13338 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13339 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13340 unsigned frontbuffer_bits = 0;
13341 int ret = 0;
13342
13343 if (!obj)
13344 return 0;
13345
13346 switch (plane->type) {
13347 case DRM_PLANE_TYPE_PRIMARY:
13348 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13349 break;
13350 case DRM_PLANE_TYPE_CURSOR:
13351 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13352 break;
13353 case DRM_PLANE_TYPE_OVERLAY:
13354 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13355 break;
13356 }
13357
13358 mutex_lock(&dev->struct_mutex);
13359
13360 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13361 INTEL_INFO(dev)->cursor_needs_physical) {
13362 int align = IS_I830(dev) ? 16 * 1024 : 256;
13363 ret = i915_gem_object_attach_phys(obj, align);
13364 if (ret)
13365 DRM_DEBUG_KMS("failed to attach phys object\n");
13366 } else {
13367 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13368 }
13369
13370 if (ret == 0)
13371 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13372
13373 mutex_unlock(&dev->struct_mutex);
13374
13375 return ret;
13376 }
13377
13378 /**
13379 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13380 * @plane: drm plane to clean up for
13381 * @fb: old framebuffer that was on plane
13382 *
13383 * Cleans up a framebuffer that has just been removed from a plane.
13384 */
13385 void
13386 intel_cleanup_plane_fb(struct drm_plane *plane,
13387 struct drm_framebuffer *fb,
13388 const struct drm_plane_state *old_state)
13389 {
13390 struct drm_device *dev = plane->dev;
13391 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13392
13393 if (WARN_ON(!obj))
13394 return;
13395
13396 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13397 !INTEL_INFO(dev)->cursor_needs_physical) {
13398 mutex_lock(&dev->struct_mutex);
13399 intel_unpin_fb_obj(fb, old_state);
13400 mutex_unlock(&dev->struct_mutex);
13401 }
13402 }
13403
13404 int
13405 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13406 {
13407 int max_scale;
13408 struct drm_device *dev;
13409 struct drm_i915_private *dev_priv;
13410 int crtc_clock, cdclk;
13411
13412 if (!intel_crtc || !crtc_state)
13413 return DRM_PLANE_HELPER_NO_SCALING;
13414
13415 dev = intel_crtc->base.dev;
13416 dev_priv = dev->dev_private;
13417 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13418 cdclk = dev_priv->display.get_display_clock_speed(dev);
13419
13420 if (!crtc_clock || !cdclk)
13421 return DRM_PLANE_HELPER_NO_SCALING;
13422
13423 /*
13424 * skl max scale is lower of:
13425 * close to 3 but not 3, -1 is for that purpose
13426 * or
13427 * cdclk/crtc_clock
13428 */
13429 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13430
13431 return max_scale;
13432 }
13433
13434 static int
13435 intel_check_primary_plane(struct drm_plane *plane,
13436 struct intel_plane_state *state)
13437 {
13438 struct drm_device *dev = plane->dev;
13439 struct drm_i915_private *dev_priv = dev->dev_private;
13440 struct drm_crtc *crtc = state->base.crtc;
13441 struct intel_crtc *intel_crtc;
13442 struct intel_crtc_state *crtc_state;
13443 struct drm_framebuffer *fb = state->base.fb;
13444 struct drm_rect *dest = &state->dst;
13445 struct drm_rect *src = &state->src;
13446 const struct drm_rect *clip = &state->clip;
13447 bool can_position = false;
13448 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13449 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13450 int ret;
13451
13452 crtc = crtc ? crtc : plane->crtc;
13453 intel_crtc = to_intel_crtc(crtc);
13454 crtc_state = state->base.state ?
13455 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13456
13457 if (INTEL_INFO(dev)->gen >= 9) {
13458 /* use scaler when colorkey is not required */
13459 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13460 min_scale = 1;
13461 max_scale = skl_max_scale(intel_crtc, crtc_state);
13462 }
13463 can_position = true;
13464 }
13465
13466 ret = drm_plane_helper_check_update(plane, crtc, fb,
13467 src, dest, clip,
13468 min_scale,
13469 max_scale,
13470 can_position, true,
13471 &state->visible);
13472 if (ret)
13473 return ret;
13474
13475 if (intel_crtc->active) {
13476 struct intel_plane_state *old_state =
13477 to_intel_plane_state(plane->state);
13478
13479 intel_crtc->atomic.wait_for_flips = true;
13480
13481 /*
13482 * FBC does not work on some platforms for rotated
13483 * planes, so disable it when rotation is not 0 and
13484 * update it when rotation is set back to 0.
13485 *
13486 * FIXME: This is redundant with the fbc update done in
13487 * the primary plane enable function except that that
13488 * one is done too late. We eventually need to unify
13489 * this.
13490 */
13491 if (state->visible &&
13492 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13493 dev_priv->fbc.crtc == intel_crtc &&
13494 state->base.rotation != BIT(DRM_ROTATE_0)) {
13495 intel_crtc->atomic.disable_fbc = true;
13496 }
13497
13498 if (state->visible && !old_state->visible) {
13499 /*
13500 * BDW signals flip done immediately if the plane
13501 * is disabled, even if the plane enable is already
13502 * armed to occur at the next vblank :(
13503 */
13504 if (IS_BROADWELL(dev))
13505 intel_crtc->atomic.wait_vblank = true;
13506 }
13507
13508 intel_crtc->atomic.fb_bits |=
13509 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13510
13511 intel_crtc->atomic.update_fbc = true;
13512
13513 if (intel_wm_need_update(plane, &state->base))
13514 intel_crtc->atomic.update_wm = true;
13515 }
13516
13517 if (INTEL_INFO(dev)->gen >= 9) {
13518 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13519 to_intel_plane(plane), state, 0);
13520 if (ret)
13521 return ret;
13522 }
13523
13524 return 0;
13525 }
13526
13527 static void
13528 intel_commit_primary_plane(struct drm_plane *plane,
13529 struct intel_plane_state *state)
13530 {
13531 struct drm_crtc *crtc = state->base.crtc;
13532 struct drm_framebuffer *fb = state->base.fb;
13533 struct drm_device *dev = plane->dev;
13534 struct drm_i915_private *dev_priv = dev->dev_private;
13535 struct intel_crtc *intel_crtc;
13536 struct drm_rect *src = &state->src;
13537
13538 crtc = crtc ? crtc : plane->crtc;
13539 intel_crtc = to_intel_crtc(crtc);
13540
13541 plane->fb = fb;
13542 crtc->x = src->x1 >> 16;
13543 crtc->y = src->y1 >> 16;
13544
13545 if (intel_crtc->active) {
13546 if (state->visible)
13547 /* FIXME: kill this fastboot hack */
13548 intel_update_pipe_size(intel_crtc);
13549
13550 dev_priv->display.update_primary_plane(crtc, plane->fb,
13551 crtc->x, crtc->y);
13552 }
13553 }
13554
13555 static void
13556 intel_disable_primary_plane(struct drm_plane *plane,
13557 struct drm_crtc *crtc,
13558 bool force)
13559 {
13560 struct drm_device *dev = plane->dev;
13561 struct drm_i915_private *dev_priv = dev->dev_private;
13562
13563 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13564 }
13565
13566 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13567 {
13568 struct drm_device *dev = crtc->dev;
13569 struct drm_i915_private *dev_priv = dev->dev_private;
13570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13571 struct intel_plane *intel_plane;
13572 struct drm_plane *p;
13573 unsigned fb_bits = 0;
13574
13575 /* Track fb's for any planes being disabled */
13576 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13577 intel_plane = to_intel_plane(p);
13578
13579 if (intel_crtc->atomic.disabled_planes &
13580 (1 << drm_plane_index(p))) {
13581 switch (p->type) {
13582 case DRM_PLANE_TYPE_PRIMARY:
13583 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13584 break;
13585 case DRM_PLANE_TYPE_CURSOR:
13586 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13587 break;
13588 case DRM_PLANE_TYPE_OVERLAY:
13589 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13590 break;
13591 }
13592
13593 mutex_lock(&dev->struct_mutex);
13594 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13595 mutex_unlock(&dev->struct_mutex);
13596 }
13597 }
13598
13599 if (intel_crtc->atomic.wait_for_flips)
13600 intel_crtc_wait_for_pending_flips(crtc);
13601
13602 if (intel_crtc->atomic.disable_fbc)
13603 intel_fbc_disable(dev);
13604
13605 if (intel_crtc->atomic.pre_disable_primary)
13606 intel_pre_disable_primary(crtc);
13607
13608 if (intel_crtc->atomic.update_wm)
13609 intel_update_watermarks(crtc);
13610
13611 intel_runtime_pm_get(dev_priv);
13612
13613 /* Perform vblank evasion around commit operation */
13614 if (intel_crtc->active)
13615 intel_crtc->atomic.evade =
13616 intel_pipe_update_start(intel_crtc,
13617 &intel_crtc->atomic.start_vbl_count);
13618 }
13619
13620 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13621 {
13622 struct drm_device *dev = crtc->dev;
13623 struct drm_i915_private *dev_priv = dev->dev_private;
13624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13625 struct drm_plane *p;
13626
13627 if (intel_crtc->atomic.evade)
13628 intel_pipe_update_end(intel_crtc,
13629 intel_crtc->atomic.start_vbl_count);
13630
13631 intel_runtime_pm_put(dev_priv);
13632
13633 if (intel_crtc->atomic.wait_vblank)
13634 intel_wait_for_vblank(dev, intel_crtc->pipe);
13635
13636 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13637
13638 if (intel_crtc->atomic.update_fbc) {
13639 mutex_lock(&dev->struct_mutex);
13640 intel_fbc_update(dev);
13641 mutex_unlock(&dev->struct_mutex);
13642 }
13643
13644 if (intel_crtc->atomic.post_enable_primary)
13645 intel_post_enable_primary(crtc);
13646
13647 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13648 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13649 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13650 false, false);
13651
13652 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13653 }
13654
13655 /**
13656 * intel_plane_destroy - destroy a plane
13657 * @plane: plane to destroy
13658 *
13659 * Common destruction function for all types of planes (primary, cursor,
13660 * sprite).
13661 */
13662 void intel_plane_destroy(struct drm_plane *plane)
13663 {
13664 struct intel_plane *intel_plane = to_intel_plane(plane);
13665 drm_plane_cleanup(plane);
13666 kfree(intel_plane);
13667 }
13668
13669 const struct drm_plane_funcs intel_plane_funcs = {
13670 .update_plane = drm_atomic_helper_update_plane,
13671 .disable_plane = drm_atomic_helper_disable_plane,
13672 .destroy = intel_plane_destroy,
13673 .set_property = drm_atomic_helper_plane_set_property,
13674 .atomic_get_property = intel_plane_atomic_get_property,
13675 .atomic_set_property = intel_plane_atomic_set_property,
13676 .atomic_duplicate_state = intel_plane_duplicate_state,
13677 .atomic_destroy_state = intel_plane_destroy_state,
13678
13679 };
13680
13681 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13682 int pipe)
13683 {
13684 struct intel_plane *primary;
13685 struct intel_plane_state *state;
13686 const uint32_t *intel_primary_formats;
13687 int num_formats;
13688
13689 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13690 if (primary == NULL)
13691 return NULL;
13692
13693 state = intel_create_plane_state(&primary->base);
13694 if (!state) {
13695 kfree(primary);
13696 return NULL;
13697 }
13698 primary->base.state = &state->base;
13699
13700 primary->can_scale = false;
13701 primary->max_downscale = 1;
13702 if (INTEL_INFO(dev)->gen >= 9) {
13703 primary->can_scale = true;
13704 state->scaler_id = -1;
13705 }
13706 primary->pipe = pipe;
13707 primary->plane = pipe;
13708 primary->check_plane = intel_check_primary_plane;
13709 primary->commit_plane = intel_commit_primary_plane;
13710 primary->disable_plane = intel_disable_primary_plane;
13711 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13712 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13713 primary->plane = !pipe;
13714
13715 if (INTEL_INFO(dev)->gen >= 9) {
13716 intel_primary_formats = skl_primary_formats;
13717 num_formats = ARRAY_SIZE(skl_primary_formats);
13718 } else if (INTEL_INFO(dev)->gen >= 4) {
13719 intel_primary_formats = i965_primary_formats;
13720 num_formats = ARRAY_SIZE(i965_primary_formats);
13721 } else {
13722 intel_primary_formats = i8xx_primary_formats;
13723 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13724 }
13725
13726 drm_universal_plane_init(dev, &primary->base, 0,
13727 &intel_plane_funcs,
13728 intel_primary_formats, num_formats,
13729 DRM_PLANE_TYPE_PRIMARY);
13730
13731 if (INTEL_INFO(dev)->gen >= 4)
13732 intel_create_rotation_property(dev, primary);
13733
13734 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13735
13736 return &primary->base;
13737 }
13738
13739 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13740 {
13741 if (!dev->mode_config.rotation_property) {
13742 unsigned long flags = BIT(DRM_ROTATE_0) |
13743 BIT(DRM_ROTATE_180);
13744
13745 if (INTEL_INFO(dev)->gen >= 9)
13746 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13747
13748 dev->mode_config.rotation_property =
13749 drm_mode_create_rotation_property(dev, flags);
13750 }
13751 if (dev->mode_config.rotation_property)
13752 drm_object_attach_property(&plane->base.base,
13753 dev->mode_config.rotation_property,
13754 plane->base.state->rotation);
13755 }
13756
13757 static int
13758 intel_check_cursor_plane(struct drm_plane *plane,
13759 struct intel_plane_state *state)
13760 {
13761 struct drm_crtc *crtc = state->base.crtc;
13762 struct drm_device *dev = plane->dev;
13763 struct drm_framebuffer *fb = state->base.fb;
13764 struct drm_rect *dest = &state->dst;
13765 struct drm_rect *src = &state->src;
13766 const struct drm_rect *clip = &state->clip;
13767 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13768 struct intel_crtc *intel_crtc;
13769 unsigned stride;
13770 int ret;
13771
13772 crtc = crtc ? crtc : plane->crtc;
13773 intel_crtc = to_intel_crtc(crtc);
13774
13775 ret = drm_plane_helper_check_update(plane, crtc, fb,
13776 src, dest, clip,
13777 DRM_PLANE_HELPER_NO_SCALING,
13778 DRM_PLANE_HELPER_NO_SCALING,
13779 true, true, &state->visible);
13780 if (ret)
13781 return ret;
13782
13783
13784 /* if we want to turn off the cursor ignore width and height */
13785 if (!obj)
13786 goto finish;
13787
13788 /* Check for which cursor types we support */
13789 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13790 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13791 state->base.crtc_w, state->base.crtc_h);
13792 return -EINVAL;
13793 }
13794
13795 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13796 if (obj->base.size < stride * state->base.crtc_h) {
13797 DRM_DEBUG_KMS("buffer is too small\n");
13798 return -ENOMEM;
13799 }
13800
13801 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13802 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13803 ret = -EINVAL;
13804 }
13805
13806 finish:
13807 if (intel_crtc->active) {
13808 if (plane->state->crtc_w != state->base.crtc_w)
13809 intel_crtc->atomic.update_wm = true;
13810
13811 intel_crtc->atomic.fb_bits |=
13812 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13813 }
13814
13815 return ret;
13816 }
13817
13818 static void
13819 intel_disable_cursor_plane(struct drm_plane *plane,
13820 struct drm_crtc *crtc,
13821 bool force)
13822 {
13823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13824
13825 if (!force) {
13826 plane->fb = NULL;
13827 intel_crtc->cursor_bo = NULL;
13828 intel_crtc->cursor_addr = 0;
13829 }
13830
13831 intel_crtc_update_cursor(crtc, false);
13832 }
13833
13834 static void
13835 intel_commit_cursor_plane(struct drm_plane *plane,
13836 struct intel_plane_state *state)
13837 {
13838 struct drm_crtc *crtc = state->base.crtc;
13839 struct drm_device *dev = plane->dev;
13840 struct intel_crtc *intel_crtc;
13841 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13842 uint32_t addr;
13843
13844 crtc = crtc ? crtc : plane->crtc;
13845 intel_crtc = to_intel_crtc(crtc);
13846
13847 plane->fb = state->base.fb;
13848 crtc->cursor_x = state->base.crtc_x;
13849 crtc->cursor_y = state->base.crtc_y;
13850
13851 if (intel_crtc->cursor_bo == obj)
13852 goto update;
13853
13854 if (!obj)
13855 addr = 0;
13856 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13857 addr = i915_gem_obj_ggtt_offset(obj);
13858 else
13859 addr = obj->phys_handle->busaddr;
13860
13861 intel_crtc->cursor_addr = addr;
13862 intel_crtc->cursor_bo = obj;
13863 update:
13864
13865 if (intel_crtc->active)
13866 intel_crtc_update_cursor(crtc, state->visible);
13867 }
13868
13869 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13870 int pipe)
13871 {
13872 struct intel_plane *cursor;
13873 struct intel_plane_state *state;
13874
13875 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13876 if (cursor == NULL)
13877 return NULL;
13878
13879 state = intel_create_plane_state(&cursor->base);
13880 if (!state) {
13881 kfree(cursor);
13882 return NULL;
13883 }
13884 cursor->base.state = &state->base;
13885
13886 cursor->can_scale = false;
13887 cursor->max_downscale = 1;
13888 cursor->pipe = pipe;
13889 cursor->plane = pipe;
13890 cursor->check_plane = intel_check_cursor_plane;
13891 cursor->commit_plane = intel_commit_cursor_plane;
13892 cursor->disable_plane = intel_disable_cursor_plane;
13893
13894 drm_universal_plane_init(dev, &cursor->base, 0,
13895 &intel_plane_funcs,
13896 intel_cursor_formats,
13897 ARRAY_SIZE(intel_cursor_formats),
13898 DRM_PLANE_TYPE_CURSOR);
13899
13900 if (INTEL_INFO(dev)->gen >= 4) {
13901 if (!dev->mode_config.rotation_property)
13902 dev->mode_config.rotation_property =
13903 drm_mode_create_rotation_property(dev,
13904 BIT(DRM_ROTATE_0) |
13905 BIT(DRM_ROTATE_180));
13906 if (dev->mode_config.rotation_property)
13907 drm_object_attach_property(&cursor->base.base,
13908 dev->mode_config.rotation_property,
13909 state->base.rotation);
13910 }
13911
13912 if (INTEL_INFO(dev)->gen >=9)
13913 state->scaler_id = -1;
13914
13915 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13916
13917 return &cursor->base;
13918 }
13919
13920 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13921 struct intel_crtc_state *crtc_state)
13922 {
13923 int i;
13924 struct intel_scaler *intel_scaler;
13925 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13926
13927 for (i = 0; i < intel_crtc->num_scalers; i++) {
13928 intel_scaler = &scaler_state->scalers[i];
13929 intel_scaler->in_use = 0;
13930 intel_scaler->id = i;
13931
13932 intel_scaler->mode = PS_SCALER_MODE_DYN;
13933 }
13934
13935 scaler_state->scaler_id = -1;
13936 }
13937
13938 static void intel_crtc_init(struct drm_device *dev, int pipe)
13939 {
13940 struct drm_i915_private *dev_priv = dev->dev_private;
13941 struct intel_crtc *intel_crtc;
13942 struct intel_crtc_state *crtc_state = NULL;
13943 struct drm_plane *primary = NULL;
13944 struct drm_plane *cursor = NULL;
13945 int i, ret;
13946
13947 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13948 if (intel_crtc == NULL)
13949 return;
13950
13951 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13952 if (!crtc_state)
13953 goto fail;
13954 intel_crtc->config = crtc_state;
13955 intel_crtc->base.state = &crtc_state->base;
13956 crtc_state->base.crtc = &intel_crtc->base;
13957
13958 /* initialize shared scalers */
13959 if (INTEL_INFO(dev)->gen >= 9) {
13960 if (pipe == PIPE_C)
13961 intel_crtc->num_scalers = 1;
13962 else
13963 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13964
13965 skl_init_scalers(dev, intel_crtc, crtc_state);
13966 }
13967
13968 primary = intel_primary_plane_create(dev, pipe);
13969 if (!primary)
13970 goto fail;
13971
13972 cursor = intel_cursor_plane_create(dev, pipe);
13973 if (!cursor)
13974 goto fail;
13975
13976 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13977 cursor, &intel_crtc_funcs);
13978 if (ret)
13979 goto fail;
13980
13981 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13982 for (i = 0; i < 256; i++) {
13983 intel_crtc->lut_r[i] = i;
13984 intel_crtc->lut_g[i] = i;
13985 intel_crtc->lut_b[i] = i;
13986 }
13987
13988 /*
13989 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13990 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13991 */
13992 intel_crtc->pipe = pipe;
13993 intel_crtc->plane = pipe;
13994 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13995 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13996 intel_crtc->plane = !pipe;
13997 }
13998
13999 intel_crtc->cursor_base = ~0;
14000 intel_crtc->cursor_cntl = ~0;
14001 intel_crtc->cursor_size = ~0;
14002
14003 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14004 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14005 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14006 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14007
14008 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14009
14010 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14011 return;
14012
14013 fail:
14014 if (primary)
14015 drm_plane_cleanup(primary);
14016 if (cursor)
14017 drm_plane_cleanup(cursor);
14018 kfree(crtc_state);
14019 kfree(intel_crtc);
14020 }
14021
14022 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14023 {
14024 struct drm_encoder *encoder = connector->base.encoder;
14025 struct drm_device *dev = connector->base.dev;
14026
14027 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14028
14029 if (!encoder || WARN_ON(!encoder->crtc))
14030 return INVALID_PIPE;
14031
14032 return to_intel_crtc(encoder->crtc)->pipe;
14033 }
14034
14035 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14036 struct drm_file *file)
14037 {
14038 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14039 struct drm_crtc *drmmode_crtc;
14040 struct intel_crtc *crtc;
14041
14042 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14043
14044 if (!drmmode_crtc) {
14045 DRM_ERROR("no such CRTC id\n");
14046 return -ENOENT;
14047 }
14048
14049 crtc = to_intel_crtc(drmmode_crtc);
14050 pipe_from_crtc_id->pipe = crtc->pipe;
14051
14052 return 0;
14053 }
14054
14055 static int intel_encoder_clones(struct intel_encoder *encoder)
14056 {
14057 struct drm_device *dev = encoder->base.dev;
14058 struct intel_encoder *source_encoder;
14059 int index_mask = 0;
14060 int entry = 0;
14061
14062 for_each_intel_encoder(dev, source_encoder) {
14063 if (encoders_cloneable(encoder, source_encoder))
14064 index_mask |= (1 << entry);
14065
14066 entry++;
14067 }
14068
14069 return index_mask;
14070 }
14071
14072 static bool has_edp_a(struct drm_device *dev)
14073 {
14074 struct drm_i915_private *dev_priv = dev->dev_private;
14075
14076 if (!IS_MOBILE(dev))
14077 return false;
14078
14079 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14080 return false;
14081
14082 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14083 return false;
14084
14085 return true;
14086 }
14087
14088 static bool intel_crt_present(struct drm_device *dev)
14089 {
14090 struct drm_i915_private *dev_priv = dev->dev_private;
14091
14092 if (INTEL_INFO(dev)->gen >= 9)
14093 return false;
14094
14095 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14096 return false;
14097
14098 if (IS_CHERRYVIEW(dev))
14099 return false;
14100
14101 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14102 return false;
14103
14104 return true;
14105 }
14106
14107 static void intel_setup_outputs(struct drm_device *dev)
14108 {
14109 struct drm_i915_private *dev_priv = dev->dev_private;
14110 struct intel_encoder *encoder;
14111 bool dpd_is_edp = false;
14112
14113 intel_lvds_init(dev);
14114
14115 if (intel_crt_present(dev))
14116 intel_crt_init(dev);
14117
14118 if (IS_BROXTON(dev)) {
14119 /*
14120 * FIXME: Broxton doesn't support port detection via the
14121 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14122 * detect the ports.
14123 */
14124 intel_ddi_init(dev, PORT_A);
14125 intel_ddi_init(dev, PORT_B);
14126 intel_ddi_init(dev, PORT_C);
14127 } else if (HAS_DDI(dev)) {
14128 int found;
14129
14130 /*
14131 * Haswell uses DDI functions to detect digital outputs.
14132 * On SKL pre-D0 the strap isn't connected, so we assume
14133 * it's there.
14134 */
14135 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14136 /* WaIgnoreDDIAStrap: skl */
14137 if (found ||
14138 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14139 intel_ddi_init(dev, PORT_A);
14140
14141 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14142 * register */
14143 found = I915_READ(SFUSE_STRAP);
14144
14145 if (found & SFUSE_STRAP_DDIB_DETECTED)
14146 intel_ddi_init(dev, PORT_B);
14147 if (found & SFUSE_STRAP_DDIC_DETECTED)
14148 intel_ddi_init(dev, PORT_C);
14149 if (found & SFUSE_STRAP_DDID_DETECTED)
14150 intel_ddi_init(dev, PORT_D);
14151 } else if (HAS_PCH_SPLIT(dev)) {
14152 int found;
14153 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14154
14155 if (has_edp_a(dev))
14156 intel_dp_init(dev, DP_A, PORT_A);
14157
14158 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14159 /* PCH SDVOB multiplex with HDMIB */
14160 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14161 if (!found)
14162 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14163 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14164 intel_dp_init(dev, PCH_DP_B, PORT_B);
14165 }
14166
14167 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14168 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14169
14170 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14171 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14172
14173 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14174 intel_dp_init(dev, PCH_DP_C, PORT_C);
14175
14176 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14177 intel_dp_init(dev, PCH_DP_D, PORT_D);
14178 } else if (IS_VALLEYVIEW(dev)) {
14179 /*
14180 * The DP_DETECTED bit is the latched state of the DDC
14181 * SDA pin at boot. However since eDP doesn't require DDC
14182 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14183 * eDP ports may have been muxed to an alternate function.
14184 * Thus we can't rely on the DP_DETECTED bit alone to detect
14185 * eDP ports. Consult the VBT as well as DP_DETECTED to
14186 * detect eDP ports.
14187 */
14188 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14189 !intel_dp_is_edp(dev, PORT_B))
14190 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14191 PORT_B);
14192 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14193 intel_dp_is_edp(dev, PORT_B))
14194 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14195
14196 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14197 !intel_dp_is_edp(dev, PORT_C))
14198 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14199 PORT_C);
14200 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14201 intel_dp_is_edp(dev, PORT_C))
14202 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14203
14204 if (IS_CHERRYVIEW(dev)) {
14205 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14206 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14207 PORT_D);
14208 /* eDP not supported on port D, so don't check VBT */
14209 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14210 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14211 }
14212
14213 intel_dsi_init(dev);
14214 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14215 bool found = false;
14216
14217 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14218 DRM_DEBUG_KMS("probing SDVOB\n");
14219 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14220 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14221 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14222 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14223 }
14224
14225 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14226 intel_dp_init(dev, DP_B, PORT_B);
14227 }
14228
14229 /* Before G4X SDVOC doesn't have its own detect register */
14230
14231 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14232 DRM_DEBUG_KMS("probing SDVOC\n");
14233 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14234 }
14235
14236 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14237
14238 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14239 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14240 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14241 }
14242 if (SUPPORTS_INTEGRATED_DP(dev))
14243 intel_dp_init(dev, DP_C, PORT_C);
14244 }
14245
14246 if (SUPPORTS_INTEGRATED_DP(dev) &&
14247 (I915_READ(DP_D) & DP_DETECTED))
14248 intel_dp_init(dev, DP_D, PORT_D);
14249 } else if (IS_GEN2(dev))
14250 intel_dvo_init(dev);
14251
14252 if (SUPPORTS_TV(dev))
14253 intel_tv_init(dev);
14254
14255 intel_psr_init(dev);
14256
14257 for_each_intel_encoder(dev, encoder) {
14258 encoder->base.possible_crtcs = encoder->crtc_mask;
14259 encoder->base.possible_clones =
14260 intel_encoder_clones(encoder);
14261 }
14262
14263 intel_init_pch_refclk(dev);
14264
14265 drm_helper_move_panel_connectors_to_head(dev);
14266 }
14267
14268 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14269 {
14270 struct drm_device *dev = fb->dev;
14271 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14272
14273 drm_framebuffer_cleanup(fb);
14274 mutex_lock(&dev->struct_mutex);
14275 WARN_ON(!intel_fb->obj->framebuffer_references--);
14276 drm_gem_object_unreference(&intel_fb->obj->base);
14277 mutex_unlock(&dev->struct_mutex);
14278 kfree(intel_fb);
14279 }
14280
14281 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14282 struct drm_file *file,
14283 unsigned int *handle)
14284 {
14285 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14286 struct drm_i915_gem_object *obj = intel_fb->obj;
14287
14288 return drm_gem_handle_create(file, &obj->base, handle);
14289 }
14290
14291 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14292 .destroy = intel_user_framebuffer_destroy,
14293 .create_handle = intel_user_framebuffer_create_handle,
14294 };
14295
14296 static
14297 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14298 uint32_t pixel_format)
14299 {
14300 u32 gen = INTEL_INFO(dev)->gen;
14301
14302 if (gen >= 9) {
14303 /* "The stride in bytes must not exceed the of the size of 8K
14304 * pixels and 32K bytes."
14305 */
14306 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14307 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14308 return 32*1024;
14309 } else if (gen >= 4) {
14310 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14311 return 16*1024;
14312 else
14313 return 32*1024;
14314 } else if (gen >= 3) {
14315 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14316 return 8*1024;
14317 else
14318 return 16*1024;
14319 } else {
14320 /* XXX DSPC is limited to 4k tiled */
14321 return 8*1024;
14322 }
14323 }
14324
14325 static int intel_framebuffer_init(struct drm_device *dev,
14326 struct intel_framebuffer *intel_fb,
14327 struct drm_mode_fb_cmd2 *mode_cmd,
14328 struct drm_i915_gem_object *obj)
14329 {
14330 unsigned int aligned_height;
14331 int ret;
14332 u32 pitch_limit, stride_alignment;
14333
14334 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14335
14336 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14337 /* Enforce that fb modifier and tiling mode match, but only for
14338 * X-tiled. This is needed for FBC. */
14339 if (!!(obj->tiling_mode == I915_TILING_X) !=
14340 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14341 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14342 return -EINVAL;
14343 }
14344 } else {
14345 if (obj->tiling_mode == I915_TILING_X)
14346 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14347 else if (obj->tiling_mode == I915_TILING_Y) {
14348 DRM_DEBUG("No Y tiling for legacy addfb\n");
14349 return -EINVAL;
14350 }
14351 }
14352
14353 /* Passed in modifier sanity checking. */
14354 switch (mode_cmd->modifier[0]) {
14355 case I915_FORMAT_MOD_Y_TILED:
14356 case I915_FORMAT_MOD_Yf_TILED:
14357 if (INTEL_INFO(dev)->gen < 9) {
14358 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14359 mode_cmd->modifier[0]);
14360 return -EINVAL;
14361 }
14362 case DRM_FORMAT_MOD_NONE:
14363 case I915_FORMAT_MOD_X_TILED:
14364 break;
14365 default:
14366 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14367 mode_cmd->modifier[0]);
14368 return -EINVAL;
14369 }
14370
14371 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14372 mode_cmd->pixel_format);
14373 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14374 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14375 mode_cmd->pitches[0], stride_alignment);
14376 return -EINVAL;
14377 }
14378
14379 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14380 mode_cmd->pixel_format);
14381 if (mode_cmd->pitches[0] > pitch_limit) {
14382 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14383 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14384 "tiled" : "linear",
14385 mode_cmd->pitches[0], pitch_limit);
14386 return -EINVAL;
14387 }
14388
14389 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14390 mode_cmd->pitches[0] != obj->stride) {
14391 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14392 mode_cmd->pitches[0], obj->stride);
14393 return -EINVAL;
14394 }
14395
14396 /* Reject formats not supported by any plane early. */
14397 switch (mode_cmd->pixel_format) {
14398 case DRM_FORMAT_C8:
14399 case DRM_FORMAT_RGB565:
14400 case DRM_FORMAT_XRGB8888:
14401 case DRM_FORMAT_ARGB8888:
14402 break;
14403 case DRM_FORMAT_XRGB1555:
14404 if (INTEL_INFO(dev)->gen > 3) {
14405 DRM_DEBUG("unsupported pixel format: %s\n",
14406 drm_get_format_name(mode_cmd->pixel_format));
14407 return -EINVAL;
14408 }
14409 break;
14410 case DRM_FORMAT_ABGR8888:
14411 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14412 DRM_DEBUG("unsupported pixel format: %s\n",
14413 drm_get_format_name(mode_cmd->pixel_format));
14414 return -EINVAL;
14415 }
14416 break;
14417 case DRM_FORMAT_XBGR8888:
14418 case DRM_FORMAT_XRGB2101010:
14419 case DRM_FORMAT_XBGR2101010:
14420 if (INTEL_INFO(dev)->gen < 4) {
14421 DRM_DEBUG("unsupported pixel format: %s\n",
14422 drm_get_format_name(mode_cmd->pixel_format));
14423 return -EINVAL;
14424 }
14425 break;
14426 case DRM_FORMAT_ABGR2101010:
14427 if (!IS_VALLEYVIEW(dev)) {
14428 DRM_DEBUG("unsupported pixel format: %s\n",
14429 drm_get_format_name(mode_cmd->pixel_format));
14430 return -EINVAL;
14431 }
14432 break;
14433 case DRM_FORMAT_YUYV:
14434 case DRM_FORMAT_UYVY:
14435 case DRM_FORMAT_YVYU:
14436 case DRM_FORMAT_VYUY:
14437 if (INTEL_INFO(dev)->gen < 5) {
14438 DRM_DEBUG("unsupported pixel format: %s\n",
14439 drm_get_format_name(mode_cmd->pixel_format));
14440 return -EINVAL;
14441 }
14442 break;
14443 default:
14444 DRM_DEBUG("unsupported pixel format: %s\n",
14445 drm_get_format_name(mode_cmd->pixel_format));
14446 return -EINVAL;
14447 }
14448
14449 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14450 if (mode_cmd->offsets[0] != 0)
14451 return -EINVAL;
14452
14453 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14454 mode_cmd->pixel_format,
14455 mode_cmd->modifier[0]);
14456 /* FIXME drm helper for size checks (especially planar formats)? */
14457 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14458 return -EINVAL;
14459
14460 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14461 intel_fb->obj = obj;
14462 intel_fb->obj->framebuffer_references++;
14463
14464 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14465 if (ret) {
14466 DRM_ERROR("framebuffer init failed %d\n", ret);
14467 return ret;
14468 }
14469
14470 return 0;
14471 }
14472
14473 static struct drm_framebuffer *
14474 intel_user_framebuffer_create(struct drm_device *dev,
14475 struct drm_file *filp,
14476 struct drm_mode_fb_cmd2 *mode_cmd)
14477 {
14478 struct drm_i915_gem_object *obj;
14479
14480 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14481 mode_cmd->handles[0]));
14482 if (&obj->base == NULL)
14483 return ERR_PTR(-ENOENT);
14484
14485 return intel_framebuffer_create(dev, mode_cmd, obj);
14486 }
14487
14488 #ifndef CONFIG_DRM_I915_FBDEV
14489 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14490 {
14491 }
14492 #endif
14493
14494 static const struct drm_mode_config_funcs intel_mode_funcs = {
14495 .fb_create = intel_user_framebuffer_create,
14496 .output_poll_changed = intel_fbdev_output_poll_changed,
14497 .atomic_check = intel_atomic_check,
14498 .atomic_commit = intel_atomic_commit,
14499 };
14500
14501 /* Set up chip specific display functions */
14502 static void intel_init_display(struct drm_device *dev)
14503 {
14504 struct drm_i915_private *dev_priv = dev->dev_private;
14505
14506 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14507 dev_priv->display.find_dpll = g4x_find_best_dpll;
14508 else if (IS_CHERRYVIEW(dev))
14509 dev_priv->display.find_dpll = chv_find_best_dpll;
14510 else if (IS_VALLEYVIEW(dev))
14511 dev_priv->display.find_dpll = vlv_find_best_dpll;
14512 else if (IS_PINEVIEW(dev))
14513 dev_priv->display.find_dpll = pnv_find_best_dpll;
14514 else
14515 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14516
14517 if (INTEL_INFO(dev)->gen >= 9) {
14518 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14519 dev_priv->display.get_initial_plane_config =
14520 skylake_get_initial_plane_config;
14521 dev_priv->display.crtc_compute_clock =
14522 haswell_crtc_compute_clock;
14523 dev_priv->display.crtc_enable = haswell_crtc_enable;
14524 dev_priv->display.crtc_disable = haswell_crtc_disable;
14525 dev_priv->display.off = ironlake_crtc_off;
14526 dev_priv->display.update_primary_plane =
14527 skylake_update_primary_plane;
14528 } else if (HAS_DDI(dev)) {
14529 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14530 dev_priv->display.get_initial_plane_config =
14531 ironlake_get_initial_plane_config;
14532 dev_priv->display.crtc_compute_clock =
14533 haswell_crtc_compute_clock;
14534 dev_priv->display.crtc_enable = haswell_crtc_enable;
14535 dev_priv->display.crtc_disable = haswell_crtc_disable;
14536 dev_priv->display.off = ironlake_crtc_off;
14537 dev_priv->display.update_primary_plane =
14538 ironlake_update_primary_plane;
14539 } else if (HAS_PCH_SPLIT(dev)) {
14540 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14541 dev_priv->display.get_initial_plane_config =
14542 ironlake_get_initial_plane_config;
14543 dev_priv->display.crtc_compute_clock =
14544 ironlake_crtc_compute_clock;
14545 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14546 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14547 dev_priv->display.off = ironlake_crtc_off;
14548 dev_priv->display.update_primary_plane =
14549 ironlake_update_primary_plane;
14550 } else if (IS_VALLEYVIEW(dev)) {
14551 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14552 dev_priv->display.get_initial_plane_config =
14553 i9xx_get_initial_plane_config;
14554 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14555 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14556 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14557 dev_priv->display.off = i9xx_crtc_off;
14558 dev_priv->display.update_primary_plane =
14559 i9xx_update_primary_plane;
14560 } else {
14561 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14562 dev_priv->display.get_initial_plane_config =
14563 i9xx_get_initial_plane_config;
14564 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14565 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14566 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14567 dev_priv->display.off = i9xx_crtc_off;
14568 dev_priv->display.update_primary_plane =
14569 i9xx_update_primary_plane;
14570 }
14571
14572 /* Returns the core display clock speed */
14573 if (IS_SKYLAKE(dev))
14574 dev_priv->display.get_display_clock_speed =
14575 skylake_get_display_clock_speed;
14576 else if (IS_BROADWELL(dev))
14577 dev_priv->display.get_display_clock_speed =
14578 broadwell_get_display_clock_speed;
14579 else if (IS_HASWELL(dev))
14580 dev_priv->display.get_display_clock_speed =
14581 haswell_get_display_clock_speed;
14582 else if (IS_VALLEYVIEW(dev))
14583 dev_priv->display.get_display_clock_speed =
14584 valleyview_get_display_clock_speed;
14585 else if (IS_GEN5(dev))
14586 dev_priv->display.get_display_clock_speed =
14587 ilk_get_display_clock_speed;
14588 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14589 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14590 dev_priv->display.get_display_clock_speed =
14591 i945_get_display_clock_speed;
14592 else if (IS_GM45(dev))
14593 dev_priv->display.get_display_clock_speed =
14594 gm45_get_display_clock_speed;
14595 else if (IS_CRESTLINE(dev))
14596 dev_priv->display.get_display_clock_speed =
14597 i965gm_get_display_clock_speed;
14598 else if (IS_PINEVIEW(dev))
14599 dev_priv->display.get_display_clock_speed =
14600 pnv_get_display_clock_speed;
14601 else if (IS_G33(dev) || IS_G4X(dev))
14602 dev_priv->display.get_display_clock_speed =
14603 g33_get_display_clock_speed;
14604 else if (IS_I915G(dev))
14605 dev_priv->display.get_display_clock_speed =
14606 i915_get_display_clock_speed;
14607 else if (IS_I945GM(dev) || IS_845G(dev))
14608 dev_priv->display.get_display_clock_speed =
14609 i9xx_misc_get_display_clock_speed;
14610 else if (IS_PINEVIEW(dev))
14611 dev_priv->display.get_display_clock_speed =
14612 pnv_get_display_clock_speed;
14613 else if (IS_I915GM(dev))
14614 dev_priv->display.get_display_clock_speed =
14615 i915gm_get_display_clock_speed;
14616 else if (IS_I865G(dev))
14617 dev_priv->display.get_display_clock_speed =
14618 i865_get_display_clock_speed;
14619 else if (IS_I85X(dev))
14620 dev_priv->display.get_display_clock_speed =
14621 i85x_get_display_clock_speed;
14622 else { /* 830 */
14623 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14624 dev_priv->display.get_display_clock_speed =
14625 i830_get_display_clock_speed;
14626 }
14627
14628 if (IS_GEN5(dev)) {
14629 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14630 } else if (IS_GEN6(dev)) {
14631 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14632 } else if (IS_IVYBRIDGE(dev)) {
14633 /* FIXME: detect B0+ stepping and use auto training */
14634 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14635 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14636 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14637 } else if (IS_VALLEYVIEW(dev)) {
14638 dev_priv->display.modeset_global_resources =
14639 valleyview_modeset_global_resources;
14640 } else if (IS_BROXTON(dev)) {
14641 dev_priv->display.modeset_global_resources =
14642 broxton_modeset_global_resources;
14643 }
14644
14645 switch (INTEL_INFO(dev)->gen) {
14646 case 2:
14647 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14648 break;
14649
14650 case 3:
14651 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14652 break;
14653
14654 case 4:
14655 case 5:
14656 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14657 break;
14658
14659 case 6:
14660 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14661 break;
14662 case 7:
14663 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14664 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14665 break;
14666 case 9:
14667 /* Drop through - unsupported since execlist only. */
14668 default:
14669 /* Default just returns -ENODEV to indicate unsupported */
14670 dev_priv->display.queue_flip = intel_default_queue_flip;
14671 }
14672
14673 intel_panel_init_backlight_funcs(dev);
14674
14675 mutex_init(&dev_priv->pps_mutex);
14676 }
14677
14678 /*
14679 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14680 * resume, or other times. This quirk makes sure that's the case for
14681 * affected systems.
14682 */
14683 static void quirk_pipea_force(struct drm_device *dev)
14684 {
14685 struct drm_i915_private *dev_priv = dev->dev_private;
14686
14687 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14688 DRM_INFO("applying pipe a force quirk\n");
14689 }
14690
14691 static void quirk_pipeb_force(struct drm_device *dev)
14692 {
14693 struct drm_i915_private *dev_priv = dev->dev_private;
14694
14695 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14696 DRM_INFO("applying pipe b force quirk\n");
14697 }
14698
14699 /*
14700 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14701 */
14702 static void quirk_ssc_force_disable(struct drm_device *dev)
14703 {
14704 struct drm_i915_private *dev_priv = dev->dev_private;
14705 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14706 DRM_INFO("applying lvds SSC disable quirk\n");
14707 }
14708
14709 /*
14710 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14711 * brightness value
14712 */
14713 static void quirk_invert_brightness(struct drm_device *dev)
14714 {
14715 struct drm_i915_private *dev_priv = dev->dev_private;
14716 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14717 DRM_INFO("applying inverted panel brightness quirk\n");
14718 }
14719
14720 /* Some VBT's incorrectly indicate no backlight is present */
14721 static void quirk_backlight_present(struct drm_device *dev)
14722 {
14723 struct drm_i915_private *dev_priv = dev->dev_private;
14724 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14725 DRM_INFO("applying backlight present quirk\n");
14726 }
14727
14728 struct intel_quirk {
14729 int device;
14730 int subsystem_vendor;
14731 int subsystem_device;
14732 void (*hook)(struct drm_device *dev);
14733 };
14734
14735 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14736 struct intel_dmi_quirk {
14737 void (*hook)(struct drm_device *dev);
14738 const struct dmi_system_id (*dmi_id_list)[];
14739 };
14740
14741 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14742 {
14743 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14744 return 1;
14745 }
14746
14747 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14748 {
14749 .dmi_id_list = &(const struct dmi_system_id[]) {
14750 {
14751 .callback = intel_dmi_reverse_brightness,
14752 .ident = "NCR Corporation",
14753 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14754 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14755 },
14756 },
14757 { } /* terminating entry */
14758 },
14759 .hook = quirk_invert_brightness,
14760 },
14761 };
14762
14763 static struct intel_quirk intel_quirks[] = {
14764 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14765 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14766
14767 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14768 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14769
14770 /* 830 needs to leave pipe A & dpll A up */
14771 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14772
14773 /* 830 needs to leave pipe B & dpll B up */
14774 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14775
14776 /* Lenovo U160 cannot use SSC on LVDS */
14777 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14778
14779 /* Sony Vaio Y cannot use SSC on LVDS */
14780 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14781
14782 /* Acer Aspire 5734Z must invert backlight brightness */
14783 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14784
14785 /* Acer/eMachines G725 */
14786 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14787
14788 /* Acer/eMachines e725 */
14789 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14790
14791 /* Acer/Packard Bell NCL20 */
14792 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14793
14794 /* Acer Aspire 4736Z */
14795 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14796
14797 /* Acer Aspire 5336 */
14798 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14799
14800 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14801 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14802
14803 /* Acer C720 Chromebook (Core i3 4005U) */
14804 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14805
14806 /* Apple Macbook 2,1 (Core 2 T7400) */
14807 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14808
14809 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14810 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14811
14812 /* HP Chromebook 14 (Celeron 2955U) */
14813 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14814
14815 /* Dell Chromebook 11 */
14816 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14817 };
14818
14819 static void intel_init_quirks(struct drm_device *dev)
14820 {
14821 struct pci_dev *d = dev->pdev;
14822 int i;
14823
14824 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14825 struct intel_quirk *q = &intel_quirks[i];
14826
14827 if (d->device == q->device &&
14828 (d->subsystem_vendor == q->subsystem_vendor ||
14829 q->subsystem_vendor == PCI_ANY_ID) &&
14830 (d->subsystem_device == q->subsystem_device ||
14831 q->subsystem_device == PCI_ANY_ID))
14832 q->hook(dev);
14833 }
14834 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14835 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14836 intel_dmi_quirks[i].hook(dev);
14837 }
14838 }
14839
14840 /* Disable the VGA plane that we never use */
14841 static void i915_disable_vga(struct drm_device *dev)
14842 {
14843 struct drm_i915_private *dev_priv = dev->dev_private;
14844 u8 sr1;
14845 u32 vga_reg = i915_vgacntrl_reg(dev);
14846
14847 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14848 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14849 outb(SR01, VGA_SR_INDEX);
14850 sr1 = inb(VGA_SR_DATA);
14851 outb(sr1 | 1<<5, VGA_SR_DATA);
14852 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14853 udelay(300);
14854
14855 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14856 POSTING_READ(vga_reg);
14857 }
14858
14859 void intel_modeset_init_hw(struct drm_device *dev)
14860 {
14861 intel_update_cdclk(dev);
14862 intel_prepare_ddi(dev);
14863 intel_init_clock_gating(dev);
14864 intel_enable_gt_powersave(dev);
14865 }
14866
14867 void intel_modeset_init(struct drm_device *dev)
14868 {
14869 struct drm_i915_private *dev_priv = dev->dev_private;
14870 int sprite, ret;
14871 enum pipe pipe;
14872 struct intel_crtc *crtc;
14873
14874 drm_mode_config_init(dev);
14875
14876 dev->mode_config.min_width = 0;
14877 dev->mode_config.min_height = 0;
14878
14879 dev->mode_config.preferred_depth = 24;
14880 dev->mode_config.prefer_shadow = 1;
14881
14882 dev->mode_config.allow_fb_modifiers = true;
14883
14884 dev->mode_config.funcs = &intel_mode_funcs;
14885
14886 intel_init_quirks(dev);
14887
14888 intel_init_pm(dev);
14889
14890 if (INTEL_INFO(dev)->num_pipes == 0)
14891 return;
14892
14893 intel_init_display(dev);
14894 intel_init_audio(dev);
14895
14896 if (IS_GEN2(dev)) {
14897 dev->mode_config.max_width = 2048;
14898 dev->mode_config.max_height = 2048;
14899 } else if (IS_GEN3(dev)) {
14900 dev->mode_config.max_width = 4096;
14901 dev->mode_config.max_height = 4096;
14902 } else {
14903 dev->mode_config.max_width = 8192;
14904 dev->mode_config.max_height = 8192;
14905 }
14906
14907 if (IS_845G(dev) || IS_I865G(dev)) {
14908 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14909 dev->mode_config.cursor_height = 1023;
14910 } else if (IS_GEN2(dev)) {
14911 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14912 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14913 } else {
14914 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14915 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14916 }
14917
14918 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14919
14920 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14921 INTEL_INFO(dev)->num_pipes,
14922 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14923
14924 for_each_pipe(dev_priv, pipe) {
14925 intel_crtc_init(dev, pipe);
14926 for_each_sprite(dev_priv, pipe, sprite) {
14927 ret = intel_plane_init(dev, pipe, sprite);
14928 if (ret)
14929 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14930 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14931 }
14932 }
14933
14934 intel_init_dpio(dev);
14935
14936 intel_shared_dpll_init(dev);
14937
14938 /* Just disable it once at startup */
14939 i915_disable_vga(dev);
14940 intel_setup_outputs(dev);
14941
14942 /* Just in case the BIOS is doing something questionable. */
14943 intel_fbc_disable(dev);
14944
14945 drm_modeset_lock_all(dev);
14946 intel_modeset_setup_hw_state(dev, false);
14947 drm_modeset_unlock_all(dev);
14948
14949 for_each_intel_crtc(dev, crtc) {
14950 if (!crtc->active)
14951 continue;
14952
14953 /*
14954 * Note that reserving the BIOS fb up front prevents us
14955 * from stuffing other stolen allocations like the ring
14956 * on top. This prevents some ugliness at boot time, and
14957 * can even allow for smooth boot transitions if the BIOS
14958 * fb is large enough for the active pipe configuration.
14959 */
14960 if (dev_priv->display.get_initial_plane_config) {
14961 dev_priv->display.get_initial_plane_config(crtc,
14962 &crtc->plane_config);
14963 /*
14964 * If the fb is shared between multiple heads, we'll
14965 * just get the first one.
14966 */
14967 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14968 }
14969 }
14970 }
14971
14972 static void intel_enable_pipe_a(struct drm_device *dev)
14973 {
14974 struct intel_connector *connector;
14975 struct drm_connector *crt = NULL;
14976 struct intel_load_detect_pipe load_detect_temp;
14977 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14978
14979 /* We can't just switch on the pipe A, we need to set things up with a
14980 * proper mode and output configuration. As a gross hack, enable pipe A
14981 * by enabling the load detect pipe once. */
14982 for_each_intel_connector(dev, connector) {
14983 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14984 crt = &connector->base;
14985 break;
14986 }
14987 }
14988
14989 if (!crt)
14990 return;
14991
14992 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14993 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14994 }
14995
14996 static bool
14997 intel_check_plane_mapping(struct intel_crtc *crtc)
14998 {
14999 struct drm_device *dev = crtc->base.dev;
15000 struct drm_i915_private *dev_priv = dev->dev_private;
15001 u32 reg, val;
15002
15003 if (INTEL_INFO(dev)->num_pipes == 1)
15004 return true;
15005
15006 reg = DSPCNTR(!crtc->plane);
15007 val = I915_READ(reg);
15008
15009 if ((val & DISPLAY_PLANE_ENABLE) &&
15010 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15011 return false;
15012
15013 return true;
15014 }
15015
15016 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15017 {
15018 struct drm_device *dev = crtc->base.dev;
15019 struct drm_i915_private *dev_priv = dev->dev_private;
15020 u32 reg;
15021
15022 /* Clear any frame start delays used for debugging left by the BIOS */
15023 reg = PIPECONF(crtc->config->cpu_transcoder);
15024 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15025
15026 /* restore vblank interrupts to correct state */
15027 drm_crtc_vblank_reset(&crtc->base);
15028 if (crtc->active) {
15029 update_scanline_offset(crtc);
15030 drm_crtc_vblank_on(&crtc->base);
15031 }
15032
15033 /* We need to sanitize the plane -> pipe mapping first because this will
15034 * disable the crtc (and hence change the state) if it is wrong. Note
15035 * that gen4+ has a fixed plane -> pipe mapping. */
15036 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15037 struct intel_connector *connector;
15038 bool plane;
15039
15040 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15041 crtc->base.base.id);
15042
15043 /* Pipe has the wrong plane attached and the plane is active.
15044 * Temporarily change the plane mapping and disable everything
15045 * ... */
15046 plane = crtc->plane;
15047 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15048 crtc->plane = !plane;
15049 intel_crtc_disable_planes(&crtc->base);
15050 dev_priv->display.crtc_disable(&crtc->base);
15051 crtc->plane = plane;
15052
15053 /* ... and break all links. */
15054 for_each_intel_connector(dev, connector) {
15055 if (connector->encoder->base.crtc != &crtc->base)
15056 continue;
15057
15058 connector->base.dpms = DRM_MODE_DPMS_OFF;
15059 connector->base.encoder = NULL;
15060 }
15061 /* multiple connectors may have the same encoder:
15062 * handle them and break crtc link separately */
15063 for_each_intel_connector(dev, connector)
15064 if (connector->encoder->base.crtc == &crtc->base) {
15065 connector->encoder->base.crtc = NULL;
15066 connector->encoder->connectors_active = false;
15067 }
15068
15069 WARN_ON(crtc->active);
15070 crtc->base.state->enable = false;
15071 crtc->base.state->active = false;
15072 crtc->base.enabled = false;
15073 }
15074
15075 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15076 crtc->pipe == PIPE_A && !crtc->active) {
15077 /* BIOS forgot to enable pipe A, this mostly happens after
15078 * resume. Force-enable the pipe to fix this, the update_dpms
15079 * call below we restore the pipe to the right state, but leave
15080 * the required bits on. */
15081 intel_enable_pipe_a(dev);
15082 }
15083
15084 /* Adjust the state of the output pipe according to whether we
15085 * have active connectors/encoders. */
15086 intel_crtc_update_dpms(&crtc->base);
15087
15088 if (crtc->active != crtc->base.state->enable) {
15089 struct intel_encoder *encoder;
15090
15091 /* This can happen either due to bugs in the get_hw_state
15092 * functions or because the pipe is force-enabled due to the
15093 * pipe A quirk. */
15094 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15095 crtc->base.base.id,
15096 crtc->base.state->enable ? "enabled" : "disabled",
15097 crtc->active ? "enabled" : "disabled");
15098
15099 crtc->base.state->enable = crtc->active;
15100 crtc->base.state->active = crtc->active;
15101 crtc->base.enabled = crtc->active;
15102
15103 /* Because we only establish the connector -> encoder ->
15104 * crtc links if something is active, this means the
15105 * crtc is now deactivated. Break the links. connector
15106 * -> encoder links are only establish when things are
15107 * actually up, hence no need to break them. */
15108 WARN_ON(crtc->active);
15109
15110 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15111 WARN_ON(encoder->connectors_active);
15112 encoder->base.crtc = NULL;
15113 }
15114 }
15115
15116 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15117 /*
15118 * We start out with underrun reporting disabled to avoid races.
15119 * For correct bookkeeping mark this on active crtcs.
15120 *
15121 * Also on gmch platforms we dont have any hardware bits to
15122 * disable the underrun reporting. Which means we need to start
15123 * out with underrun reporting disabled also on inactive pipes,
15124 * since otherwise we'll complain about the garbage we read when
15125 * e.g. coming up after runtime pm.
15126 *
15127 * No protection against concurrent access is required - at
15128 * worst a fifo underrun happens which also sets this to false.
15129 */
15130 crtc->cpu_fifo_underrun_disabled = true;
15131 crtc->pch_fifo_underrun_disabled = true;
15132 }
15133 }
15134
15135 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15136 {
15137 struct intel_connector *connector;
15138 struct drm_device *dev = encoder->base.dev;
15139
15140 /* We need to check both for a crtc link (meaning that the
15141 * encoder is active and trying to read from a pipe) and the
15142 * pipe itself being active. */
15143 bool has_active_crtc = encoder->base.crtc &&
15144 to_intel_crtc(encoder->base.crtc)->active;
15145
15146 if (encoder->connectors_active && !has_active_crtc) {
15147 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15148 encoder->base.base.id,
15149 encoder->base.name);
15150
15151 /* Connector is active, but has no active pipe. This is
15152 * fallout from our resume register restoring. Disable
15153 * the encoder manually again. */
15154 if (encoder->base.crtc) {
15155 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15156 encoder->base.base.id,
15157 encoder->base.name);
15158 encoder->disable(encoder);
15159 if (encoder->post_disable)
15160 encoder->post_disable(encoder);
15161 }
15162 encoder->base.crtc = NULL;
15163 encoder->connectors_active = false;
15164
15165 /* Inconsistent output/port/pipe state happens presumably due to
15166 * a bug in one of the get_hw_state functions. Or someplace else
15167 * in our code, like the register restore mess on resume. Clamp
15168 * things to off as a safer default. */
15169 for_each_intel_connector(dev, connector) {
15170 if (connector->encoder != encoder)
15171 continue;
15172 connector->base.dpms = DRM_MODE_DPMS_OFF;
15173 connector->base.encoder = NULL;
15174 }
15175 }
15176 /* Enabled encoders without active connectors will be fixed in
15177 * the crtc fixup. */
15178 }
15179
15180 void i915_redisable_vga_power_on(struct drm_device *dev)
15181 {
15182 struct drm_i915_private *dev_priv = dev->dev_private;
15183 u32 vga_reg = i915_vgacntrl_reg(dev);
15184
15185 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15186 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15187 i915_disable_vga(dev);
15188 }
15189 }
15190
15191 void i915_redisable_vga(struct drm_device *dev)
15192 {
15193 struct drm_i915_private *dev_priv = dev->dev_private;
15194
15195 /* This function can be called both from intel_modeset_setup_hw_state or
15196 * at a very early point in our resume sequence, where the power well
15197 * structures are not yet restored. Since this function is at a very
15198 * paranoid "someone might have enabled VGA while we were not looking"
15199 * level, just check if the power well is enabled instead of trying to
15200 * follow the "don't touch the power well if we don't need it" policy
15201 * the rest of the driver uses. */
15202 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15203 return;
15204
15205 i915_redisable_vga_power_on(dev);
15206 }
15207
15208 static bool primary_get_hw_state(struct intel_crtc *crtc)
15209 {
15210 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15211
15212 if (!crtc->active)
15213 return false;
15214
15215 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15216 }
15217
15218 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15219 {
15220 struct drm_i915_private *dev_priv = dev->dev_private;
15221 enum pipe pipe;
15222 struct intel_crtc *crtc;
15223 struct intel_encoder *encoder;
15224 struct intel_connector *connector;
15225 int i;
15226
15227 for_each_intel_crtc(dev, crtc) {
15228 struct drm_plane *primary = crtc->base.primary;
15229 struct intel_plane_state *plane_state;
15230
15231 memset(crtc->config, 0, sizeof(*crtc->config));
15232
15233 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15234
15235 crtc->active = dev_priv->display.get_pipe_config(crtc,
15236 crtc->config);
15237
15238 crtc->base.state->enable = crtc->active;
15239 crtc->base.state->active = crtc->active;
15240 crtc->base.enabled = crtc->active;
15241
15242 plane_state = to_intel_plane_state(primary->state);
15243 plane_state->visible = primary_get_hw_state(crtc);
15244
15245 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15246 crtc->base.base.id,
15247 crtc->active ? "enabled" : "disabled");
15248 }
15249
15250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15251 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15252
15253 pll->on = pll->get_hw_state(dev_priv, pll,
15254 &pll->config.hw_state);
15255 pll->active = 0;
15256 pll->config.crtc_mask = 0;
15257 for_each_intel_crtc(dev, crtc) {
15258 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15259 pll->active++;
15260 pll->config.crtc_mask |= 1 << crtc->pipe;
15261 }
15262 }
15263
15264 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15265 pll->name, pll->config.crtc_mask, pll->on);
15266
15267 if (pll->config.crtc_mask)
15268 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15269 }
15270
15271 for_each_intel_encoder(dev, encoder) {
15272 pipe = 0;
15273
15274 if (encoder->get_hw_state(encoder, &pipe)) {
15275 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15276 encoder->base.crtc = &crtc->base;
15277 encoder->get_config(encoder, crtc->config);
15278 } else {
15279 encoder->base.crtc = NULL;
15280 }
15281
15282 encoder->connectors_active = false;
15283 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15284 encoder->base.base.id,
15285 encoder->base.name,
15286 encoder->base.crtc ? "enabled" : "disabled",
15287 pipe_name(pipe));
15288 }
15289
15290 for_each_intel_connector(dev, connector) {
15291 if (connector->get_hw_state(connector)) {
15292 connector->base.dpms = DRM_MODE_DPMS_ON;
15293 connector->encoder->connectors_active = true;
15294 connector->base.encoder = &connector->encoder->base;
15295 } else {
15296 connector->base.dpms = DRM_MODE_DPMS_OFF;
15297 connector->base.encoder = NULL;
15298 }
15299 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15300 connector->base.base.id,
15301 connector->base.name,
15302 connector->base.encoder ? "enabled" : "disabled");
15303 }
15304 }
15305
15306 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15307 * and i915 state tracking structures. */
15308 void intel_modeset_setup_hw_state(struct drm_device *dev,
15309 bool force_restore)
15310 {
15311 struct drm_i915_private *dev_priv = dev->dev_private;
15312 enum pipe pipe;
15313 struct intel_crtc *crtc;
15314 struct intel_encoder *encoder;
15315 int i;
15316
15317 intel_modeset_readout_hw_state(dev);
15318
15319 /*
15320 * Now that we have the config, copy it to each CRTC struct
15321 * Note that this could go away if we move to using crtc_config
15322 * checking everywhere.
15323 */
15324 for_each_intel_crtc(dev, crtc) {
15325 if (crtc->active && i915.fastboot) {
15326 intel_mode_from_pipe_config(&crtc->base.mode,
15327 crtc->config);
15328 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15329 crtc->base.base.id);
15330 drm_mode_debug_printmodeline(&crtc->base.mode);
15331 }
15332 }
15333
15334 /* HW state is read out, now we need to sanitize this mess. */
15335 for_each_intel_encoder(dev, encoder) {
15336 intel_sanitize_encoder(encoder);
15337 }
15338
15339 for_each_pipe(dev_priv, pipe) {
15340 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15341 intel_sanitize_crtc(crtc);
15342 intel_dump_pipe_config(crtc, crtc->config,
15343 "[setup_hw_state]");
15344 }
15345
15346 intel_modeset_update_connector_atomic_state(dev);
15347
15348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15349 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15350
15351 if (!pll->on || pll->active)
15352 continue;
15353
15354 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15355
15356 pll->disable(dev_priv, pll);
15357 pll->on = false;
15358 }
15359
15360 if (IS_GEN9(dev))
15361 skl_wm_get_hw_state(dev);
15362 else if (HAS_PCH_SPLIT(dev))
15363 ilk_wm_get_hw_state(dev);
15364
15365 if (force_restore) {
15366 i915_redisable_vga(dev);
15367
15368 /*
15369 * We need to use raw interfaces for restoring state to avoid
15370 * checking (bogus) intermediate states.
15371 */
15372 for_each_pipe(dev_priv, pipe) {
15373 struct drm_crtc *crtc =
15374 dev_priv->pipe_to_crtc_mapping[pipe];
15375
15376 intel_crtc_restore_mode(crtc);
15377 }
15378 } else {
15379 intel_modeset_update_staged_output_state(dev);
15380 }
15381
15382 intel_modeset_check_state(dev);
15383 }
15384
15385 void intel_modeset_gem_init(struct drm_device *dev)
15386 {
15387 struct drm_i915_private *dev_priv = dev->dev_private;
15388 struct drm_crtc *c;
15389 struct drm_i915_gem_object *obj;
15390 int ret;
15391
15392 mutex_lock(&dev->struct_mutex);
15393 intel_init_gt_powersave(dev);
15394 mutex_unlock(&dev->struct_mutex);
15395
15396 /*
15397 * There may be no VBT; and if the BIOS enabled SSC we can
15398 * just keep using it to avoid unnecessary flicker. Whereas if the
15399 * BIOS isn't using it, don't assume it will work even if the VBT
15400 * indicates as much.
15401 */
15402 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15403 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15404 DREF_SSC1_ENABLE);
15405
15406 intel_modeset_init_hw(dev);
15407
15408 intel_setup_overlay(dev);
15409
15410 /*
15411 * Make sure any fbs we allocated at startup are properly
15412 * pinned & fenced. When we do the allocation it's too early
15413 * for this.
15414 */
15415 for_each_crtc(dev, c) {
15416 obj = intel_fb_obj(c->primary->fb);
15417 if (obj == NULL)
15418 continue;
15419
15420 mutex_lock(&dev->struct_mutex);
15421 ret = intel_pin_and_fence_fb_obj(c->primary,
15422 c->primary->fb,
15423 c->primary->state,
15424 NULL);
15425 mutex_unlock(&dev->struct_mutex);
15426 if (ret) {
15427 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15428 to_intel_crtc(c)->pipe);
15429 drm_framebuffer_unreference(c->primary->fb);
15430 c->primary->fb = NULL;
15431 update_state_fb(c->primary);
15432 }
15433 }
15434
15435 intel_backlight_register(dev);
15436 }
15437
15438 void intel_connector_unregister(struct intel_connector *intel_connector)
15439 {
15440 struct drm_connector *connector = &intel_connector->base;
15441
15442 intel_panel_destroy_backlight(connector);
15443 drm_connector_unregister(connector);
15444 }
15445
15446 void intel_modeset_cleanup(struct drm_device *dev)
15447 {
15448 struct drm_i915_private *dev_priv = dev->dev_private;
15449 struct drm_connector *connector;
15450
15451 intel_disable_gt_powersave(dev);
15452
15453 intel_backlight_unregister(dev);
15454
15455 /*
15456 * Interrupts and polling as the first thing to avoid creating havoc.
15457 * Too much stuff here (turning of connectors, ...) would
15458 * experience fancy races otherwise.
15459 */
15460 intel_irq_uninstall(dev_priv);
15461
15462 /*
15463 * Due to the hpd irq storm handling the hotplug work can re-arm the
15464 * poll handlers. Hence disable polling after hpd handling is shut down.
15465 */
15466 drm_kms_helper_poll_fini(dev);
15467
15468 mutex_lock(&dev->struct_mutex);
15469
15470 intel_unregister_dsm_handler();
15471
15472 intel_fbc_disable(dev);
15473
15474 mutex_unlock(&dev->struct_mutex);
15475
15476 /* flush any delayed tasks or pending work */
15477 flush_scheduled_work();
15478
15479 /* destroy the backlight and sysfs files before encoders/connectors */
15480 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15481 struct intel_connector *intel_connector;
15482
15483 intel_connector = to_intel_connector(connector);
15484 intel_connector->unregister(intel_connector);
15485 }
15486
15487 drm_mode_config_cleanup(dev);
15488
15489 intel_cleanup_overlay(dev);
15490
15491 mutex_lock(&dev->struct_mutex);
15492 intel_cleanup_gt_powersave(dev);
15493 mutex_unlock(&dev->struct_mutex);
15494 }
15495
15496 /*
15497 * Return which encoder is currently attached for connector.
15498 */
15499 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15500 {
15501 return &intel_attached_encoder(connector)->base;
15502 }
15503
15504 void intel_connector_attach_encoder(struct intel_connector *connector,
15505 struct intel_encoder *encoder)
15506 {
15507 connector->encoder = encoder;
15508 drm_mode_connector_attach_encoder(&connector->base,
15509 &encoder->base);
15510 }
15511
15512 /*
15513 * set vga decode state - true == enable VGA decode
15514 */
15515 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15516 {
15517 struct drm_i915_private *dev_priv = dev->dev_private;
15518 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15519 u16 gmch_ctrl;
15520
15521 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15522 DRM_ERROR("failed to read control word\n");
15523 return -EIO;
15524 }
15525
15526 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15527 return 0;
15528
15529 if (state)
15530 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15531 else
15532 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15533
15534 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15535 DRM_ERROR("failed to write control word\n");
15536 return -EIO;
15537 }
15538
15539 return 0;
15540 }
15541
15542 struct intel_display_error_state {
15543
15544 u32 power_well_driver;
15545
15546 int num_transcoders;
15547
15548 struct intel_cursor_error_state {
15549 u32 control;
15550 u32 position;
15551 u32 base;
15552 u32 size;
15553 } cursor[I915_MAX_PIPES];
15554
15555 struct intel_pipe_error_state {
15556 bool power_domain_on;
15557 u32 source;
15558 u32 stat;
15559 } pipe[I915_MAX_PIPES];
15560
15561 struct intel_plane_error_state {
15562 u32 control;
15563 u32 stride;
15564 u32 size;
15565 u32 pos;
15566 u32 addr;
15567 u32 surface;
15568 u32 tile_offset;
15569 } plane[I915_MAX_PIPES];
15570
15571 struct intel_transcoder_error_state {
15572 bool power_domain_on;
15573 enum transcoder cpu_transcoder;
15574
15575 u32 conf;
15576
15577 u32 htotal;
15578 u32 hblank;
15579 u32 hsync;
15580 u32 vtotal;
15581 u32 vblank;
15582 u32 vsync;
15583 } transcoder[4];
15584 };
15585
15586 struct intel_display_error_state *
15587 intel_display_capture_error_state(struct drm_device *dev)
15588 {
15589 struct drm_i915_private *dev_priv = dev->dev_private;
15590 struct intel_display_error_state *error;
15591 int transcoders[] = {
15592 TRANSCODER_A,
15593 TRANSCODER_B,
15594 TRANSCODER_C,
15595 TRANSCODER_EDP,
15596 };
15597 int i;
15598
15599 if (INTEL_INFO(dev)->num_pipes == 0)
15600 return NULL;
15601
15602 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15603 if (error == NULL)
15604 return NULL;
15605
15606 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15607 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15608
15609 for_each_pipe(dev_priv, i) {
15610 error->pipe[i].power_domain_on =
15611 __intel_display_power_is_enabled(dev_priv,
15612 POWER_DOMAIN_PIPE(i));
15613 if (!error->pipe[i].power_domain_on)
15614 continue;
15615
15616 error->cursor[i].control = I915_READ(CURCNTR(i));
15617 error->cursor[i].position = I915_READ(CURPOS(i));
15618 error->cursor[i].base = I915_READ(CURBASE(i));
15619
15620 error->plane[i].control = I915_READ(DSPCNTR(i));
15621 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15622 if (INTEL_INFO(dev)->gen <= 3) {
15623 error->plane[i].size = I915_READ(DSPSIZE(i));
15624 error->plane[i].pos = I915_READ(DSPPOS(i));
15625 }
15626 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15627 error->plane[i].addr = I915_READ(DSPADDR(i));
15628 if (INTEL_INFO(dev)->gen >= 4) {
15629 error->plane[i].surface = I915_READ(DSPSURF(i));
15630 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15631 }
15632
15633 error->pipe[i].source = I915_READ(PIPESRC(i));
15634
15635 if (HAS_GMCH_DISPLAY(dev))
15636 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15637 }
15638
15639 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15640 if (HAS_DDI(dev_priv->dev))
15641 error->num_transcoders++; /* Account for eDP. */
15642
15643 for (i = 0; i < error->num_transcoders; i++) {
15644 enum transcoder cpu_transcoder = transcoders[i];
15645
15646 error->transcoder[i].power_domain_on =
15647 __intel_display_power_is_enabled(dev_priv,
15648 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15649 if (!error->transcoder[i].power_domain_on)
15650 continue;
15651
15652 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15653
15654 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15655 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15656 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15657 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15658 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15659 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15660 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15661 }
15662
15663 return error;
15664 }
15665
15666 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15667
15668 void
15669 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15670 struct drm_device *dev,
15671 struct intel_display_error_state *error)
15672 {
15673 struct drm_i915_private *dev_priv = dev->dev_private;
15674 int i;
15675
15676 if (!error)
15677 return;
15678
15679 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15680 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15681 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15682 error->power_well_driver);
15683 for_each_pipe(dev_priv, i) {
15684 err_printf(m, "Pipe [%d]:\n", i);
15685 err_printf(m, " Power: %s\n",
15686 error->pipe[i].power_domain_on ? "on" : "off");
15687 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15688 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15689
15690 err_printf(m, "Plane [%d]:\n", i);
15691 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15692 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15693 if (INTEL_INFO(dev)->gen <= 3) {
15694 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15695 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15696 }
15697 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15698 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15699 if (INTEL_INFO(dev)->gen >= 4) {
15700 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15701 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15702 }
15703
15704 err_printf(m, "Cursor [%d]:\n", i);
15705 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15706 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15707 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15708 }
15709
15710 for (i = 0; i < error->num_transcoders; i++) {
15711 err_printf(m, "CPU transcoder: %c\n",
15712 transcoder_name(error->transcoder[i].cpu_transcoder));
15713 err_printf(m, " Power: %s\n",
15714 error->transcoder[i].power_domain_on ? "on" : "off");
15715 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15716 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15717 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15718 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15719 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15720 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15721 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15722 }
15723 }
15724
15725 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15726 {
15727 struct intel_crtc *crtc;
15728
15729 for_each_intel_crtc(dev, crtc) {
15730 struct intel_unpin_work *work;
15731
15732 spin_lock_irq(&dev->event_lock);
15733
15734 work = crtc->unpin_work;
15735
15736 if (work && work->event &&
15737 work->event->base.file_priv == file) {
15738 kfree(work->event);
15739 work->event = NULL;
15740 }
15741
15742 spin_unlock_irq(&dev->event_lock);
15743 }
15744 }
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