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1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static void skylake_pfit_enable(struct intel_crtc *crtc);
114 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
115 static void ironlake_pfit_enable(struct intel_crtc *crtc);
116 static void intel_modeset_setup_hw_state(struct drm_device *dev);
117 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
118 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
119 static void intel_modeset_verify_crtc(struct drm_crtc *crtc,
120 struct drm_crtc_state *old_state,
121 struct drm_crtc_state *new_state);
122
123 struct intel_limit {
124 struct {
125 int min, max;
126 } dot, vco, n, m, m1, m2, p, p1;
127
128 struct {
129 int dot_limit;
130 int p2_slow, p2_fast;
131 } p2;
132 };
133
134 /* returns HPLL frequency in kHz */
135 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
136 {
137 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
138
139 /* Obtain SKU information */
140 mutex_lock(&dev_priv->sb_lock);
141 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
142 CCK_FUSE_HPLL_FREQ_MASK;
143 mutex_unlock(&dev_priv->sb_lock);
144
145 return vco_freq[hpll_freq] * 1000;
146 }
147
148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
149 const char *name, u32 reg, int ref_freq)
150 {
151 u32 val;
152 int divider;
153
154 mutex_lock(&dev_priv->sb_lock);
155 val = vlv_cck_read(dev_priv, reg);
156 mutex_unlock(&dev_priv->sb_lock);
157
158 divider = val & CCK_FREQUENCY_VALUES;
159
160 WARN((val & CCK_FREQUENCY_STATUS) !=
161 (divider << CCK_FREQUENCY_STATUS_SHIFT),
162 "%s change in progress\n", name);
163
164 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
165 }
166
167 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
168 const char *name, u32 reg)
169 {
170 if (dev_priv->hpll_freq == 0)
171 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
172
173 return vlv_get_cck_clock(dev_priv, name, reg,
174 dev_priv->hpll_freq);
175 }
176
177 static int
178 intel_pch_rawclk(struct drm_i915_private *dev_priv)
179 {
180 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
181 }
182
183 static int
184 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
185 {
186 /* RAWCLK_FREQ_VLV register updated from power well code */
187 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
188 CCK_DISPLAY_REF_CLOCK_CONTROL);
189 }
190
191 static int
192 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
193 {
194 uint32_t clkcfg;
195
196 /* hrawclock is 1/4 the FSB frequency */
197 clkcfg = I915_READ(CLKCFG);
198 switch (clkcfg & CLKCFG_FSB_MASK) {
199 case CLKCFG_FSB_400:
200 return 100000;
201 case CLKCFG_FSB_533:
202 return 133333;
203 case CLKCFG_FSB_667:
204 return 166667;
205 case CLKCFG_FSB_800:
206 return 200000;
207 case CLKCFG_FSB_1067:
208 return 266667;
209 case CLKCFG_FSB_1333:
210 return 333333;
211 /* these two are just a guess; one of them might be right */
212 case CLKCFG_FSB_1600:
213 case CLKCFG_FSB_1600_ALT:
214 return 400000;
215 default:
216 return 133333;
217 }
218 }
219
220 void intel_update_rawclk(struct drm_i915_private *dev_priv)
221 {
222 if (HAS_PCH_SPLIT(dev_priv))
223 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
224 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
225 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
226 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
227 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
228 else
229 return; /* no rawclk on other platforms, or no need to know it */
230
231 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
232 }
233
234 static void intel_update_czclk(struct drm_i915_private *dev_priv)
235 {
236 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 return;
238
239 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
240 CCK_CZ_CLOCK_CONTROL);
241
242 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
243 }
244
245 static inline u32 /* units of 100MHz */
246 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
247 const struct intel_crtc_state *pipe_config)
248 {
249 if (HAS_DDI(dev_priv))
250 return pipe_config->port_clock; /* SPLL */
251 else if (IS_GEN5(dev_priv))
252 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
253 else
254 return 270000;
255 }
256
257 static const struct intel_limit intel_limits_i8xx_dac = {
258 .dot = { .min = 25000, .max = 350000 },
259 .vco = { .min = 908000, .max = 1512000 },
260 .n = { .min = 2, .max = 16 },
261 .m = { .min = 96, .max = 140 },
262 .m1 = { .min = 18, .max = 26 },
263 .m2 = { .min = 6, .max = 16 },
264 .p = { .min = 4, .max = 128 },
265 .p1 = { .min = 2, .max = 33 },
266 .p2 = { .dot_limit = 165000,
267 .p2_slow = 4, .p2_fast = 2 },
268 };
269
270 static const struct intel_limit intel_limits_i8xx_dvo = {
271 .dot = { .min = 25000, .max = 350000 },
272 .vco = { .min = 908000, .max = 1512000 },
273 .n = { .min = 2, .max = 16 },
274 .m = { .min = 96, .max = 140 },
275 .m1 = { .min = 18, .max = 26 },
276 .m2 = { .min = 6, .max = 16 },
277 .p = { .min = 4, .max = 128 },
278 .p1 = { .min = 2, .max = 33 },
279 .p2 = { .dot_limit = 165000,
280 .p2_slow = 4, .p2_fast = 4 },
281 };
282
283 static const struct intel_limit intel_limits_i8xx_lvds = {
284 .dot = { .min = 25000, .max = 350000 },
285 .vco = { .min = 908000, .max = 1512000 },
286 .n = { .min = 2, .max = 16 },
287 .m = { .min = 96, .max = 140 },
288 .m1 = { .min = 18, .max = 26 },
289 .m2 = { .min = 6, .max = 16 },
290 .p = { .min = 4, .max = 128 },
291 .p1 = { .min = 1, .max = 6 },
292 .p2 = { .dot_limit = 165000,
293 .p2_slow = 14, .p2_fast = 7 },
294 };
295
296 static const struct intel_limit intel_limits_i9xx_sdvo = {
297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1400000, .max = 2800000 },
299 .n = { .min = 1, .max = 6 },
300 .m = { .min = 70, .max = 120 },
301 .m1 = { .min = 8, .max = 18 },
302 .m2 = { .min = 3, .max = 7 },
303 .p = { .min = 5, .max = 80 },
304 .p1 = { .min = 1, .max = 8 },
305 .p2 = { .dot_limit = 200000,
306 .p2_slow = 10, .p2_fast = 5 },
307 };
308
309 static const struct intel_limit intel_limits_i9xx_lvds = {
310 .dot = { .min = 20000, .max = 400000 },
311 .vco = { .min = 1400000, .max = 2800000 },
312 .n = { .min = 1, .max = 6 },
313 .m = { .min = 70, .max = 120 },
314 .m1 = { .min = 8, .max = 18 },
315 .m2 = { .min = 3, .max = 7 },
316 .p = { .min = 7, .max = 98 },
317 .p1 = { .min = 1, .max = 8 },
318 .p2 = { .dot_limit = 112000,
319 .p2_slow = 14, .p2_fast = 7 },
320 };
321
322
323 static const struct intel_limit intel_limits_g4x_sdvo = {
324 .dot = { .min = 25000, .max = 270000 },
325 .vco = { .min = 1750000, .max = 3500000},
326 .n = { .min = 1, .max = 4 },
327 .m = { .min = 104, .max = 138 },
328 .m1 = { .min = 17, .max = 23 },
329 .m2 = { .min = 5, .max = 11 },
330 .p = { .min = 10, .max = 30 },
331 .p1 = { .min = 1, .max = 3},
332 .p2 = { .dot_limit = 270000,
333 .p2_slow = 10,
334 .p2_fast = 10
335 },
336 };
337
338 static const struct intel_limit intel_limits_g4x_hdmi = {
339 .dot = { .min = 22000, .max = 400000 },
340 .vco = { .min = 1750000, .max = 3500000},
341 .n = { .min = 1, .max = 4 },
342 .m = { .min = 104, .max = 138 },
343 .m1 = { .min = 16, .max = 23 },
344 .m2 = { .min = 5, .max = 11 },
345 .p = { .min = 5, .max = 80 },
346 .p1 = { .min = 1, .max = 8},
347 .p2 = { .dot_limit = 165000,
348 .p2_slow = 10, .p2_fast = 5 },
349 };
350
351 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
352 .dot = { .min = 20000, .max = 115000 },
353 .vco = { .min = 1750000, .max = 3500000 },
354 .n = { .min = 1, .max = 3 },
355 .m = { .min = 104, .max = 138 },
356 .m1 = { .min = 17, .max = 23 },
357 .m2 = { .min = 5, .max = 11 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 0,
361 .p2_slow = 14, .p2_fast = 14
362 },
363 };
364
365 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
366 .dot = { .min = 80000, .max = 224000 },
367 .vco = { .min = 1750000, .max = 3500000 },
368 .n = { .min = 1, .max = 3 },
369 .m = { .min = 104, .max = 138 },
370 .m1 = { .min = 17, .max = 23 },
371 .m2 = { .min = 5, .max = 11 },
372 .p = { .min = 14, .max = 42 },
373 .p1 = { .min = 2, .max = 6 },
374 .p2 = { .dot_limit = 0,
375 .p2_slow = 7, .p2_fast = 7
376 },
377 };
378
379 static const struct intel_limit intel_limits_pineview_sdvo = {
380 .dot = { .min = 20000, .max = 400000},
381 .vco = { .min = 1700000, .max = 3500000 },
382 /* Pineview's Ncounter is a ring counter */
383 .n = { .min = 3, .max = 6 },
384 .m = { .min = 2, .max = 256 },
385 /* Pineview only has one combined m divider, which we treat as m2. */
386 .m1 = { .min = 0, .max = 0 },
387 .m2 = { .min = 0, .max = 254 },
388 .p = { .min = 5, .max = 80 },
389 .p1 = { .min = 1, .max = 8 },
390 .p2 = { .dot_limit = 200000,
391 .p2_slow = 10, .p2_fast = 5 },
392 };
393
394 static const struct intel_limit intel_limits_pineview_lvds = {
395 .dot = { .min = 20000, .max = 400000 },
396 .vco = { .min = 1700000, .max = 3500000 },
397 .n = { .min = 3, .max = 6 },
398 .m = { .min = 2, .max = 256 },
399 .m1 = { .min = 0, .max = 0 },
400 .m2 = { .min = 0, .max = 254 },
401 .p = { .min = 7, .max = 112 },
402 .p1 = { .min = 1, .max = 8 },
403 .p2 = { .dot_limit = 112000,
404 .p2_slow = 14, .p2_fast = 14 },
405 };
406
407 /* Ironlake / Sandybridge
408 *
409 * We calculate clock using (register_value + 2) for N/M1/M2, so here
410 * the range value for them is (actual_value - 2).
411 */
412 static const struct intel_limit intel_limits_ironlake_dac = {
413 .dot = { .min = 25000, .max = 350000 },
414 .vco = { .min = 1760000, .max = 3510000 },
415 .n = { .min = 1, .max = 5 },
416 .m = { .min = 79, .max = 127 },
417 .m1 = { .min = 12, .max = 22 },
418 .m2 = { .min = 5, .max = 9 },
419 .p = { .min = 5, .max = 80 },
420 .p1 = { .min = 1, .max = 8 },
421 .p2 = { .dot_limit = 225000,
422 .p2_slow = 10, .p2_fast = 5 },
423 };
424
425 static const struct intel_limit intel_limits_ironlake_single_lvds = {
426 .dot = { .min = 25000, .max = 350000 },
427 .vco = { .min = 1760000, .max = 3510000 },
428 .n = { .min = 1, .max = 3 },
429 .m = { .min = 79, .max = 118 },
430 .m1 = { .min = 12, .max = 22 },
431 .m2 = { .min = 5, .max = 9 },
432 .p = { .min = 28, .max = 112 },
433 .p1 = { .min = 2, .max = 8 },
434 .p2 = { .dot_limit = 225000,
435 .p2_slow = 14, .p2_fast = 14 },
436 };
437
438 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
439 .dot = { .min = 25000, .max = 350000 },
440 .vco = { .min = 1760000, .max = 3510000 },
441 .n = { .min = 1, .max = 3 },
442 .m = { .min = 79, .max = 127 },
443 .m1 = { .min = 12, .max = 22 },
444 .m2 = { .min = 5, .max = 9 },
445 .p = { .min = 14, .max = 56 },
446 .p1 = { .min = 2, .max = 8 },
447 .p2 = { .dot_limit = 225000,
448 .p2_slow = 7, .p2_fast = 7 },
449 };
450
451 /* LVDS 100mhz refclk limits. */
452 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
453 .dot = { .min = 25000, .max = 350000 },
454 .vco = { .min = 1760000, .max = 3510000 },
455 .n = { .min = 1, .max = 2 },
456 .m = { .min = 79, .max = 126 },
457 .m1 = { .min = 12, .max = 22 },
458 .m2 = { .min = 5, .max = 9 },
459 .p = { .min = 28, .max = 112 },
460 .p1 = { .min = 2, .max = 8 },
461 .p2 = { .dot_limit = 225000,
462 .p2_slow = 14, .p2_fast = 14 },
463 };
464
465 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
466 .dot = { .min = 25000, .max = 350000 },
467 .vco = { .min = 1760000, .max = 3510000 },
468 .n = { .min = 1, .max = 3 },
469 .m = { .min = 79, .max = 126 },
470 .m1 = { .min = 12, .max = 22 },
471 .m2 = { .min = 5, .max = 9 },
472 .p = { .min = 14, .max = 42 },
473 .p1 = { .min = 2, .max = 6 },
474 .p2 = { .dot_limit = 225000,
475 .p2_slow = 7, .p2_fast = 7 },
476 };
477
478 static const struct intel_limit intel_limits_vlv = {
479 /*
480 * These are the data rate limits (measured in fast clocks)
481 * since those are the strictest limits we have. The fast
482 * clock and actual rate limits are more relaxed, so checking
483 * them would make no difference.
484 */
485 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
486 .vco = { .min = 4000000, .max = 6000000 },
487 .n = { .min = 1, .max = 7 },
488 .m1 = { .min = 2, .max = 3 },
489 .m2 = { .min = 11, .max = 156 },
490 .p1 = { .min = 2, .max = 3 },
491 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
492 };
493
494 static const struct intel_limit intel_limits_chv = {
495 /*
496 * These are the data rate limits (measured in fast clocks)
497 * since those are the strictest limits we have. The fast
498 * clock and actual rate limits are more relaxed, so checking
499 * them would make no difference.
500 */
501 .dot = { .min = 25000 * 5, .max = 540000 * 5},
502 .vco = { .min = 4800000, .max = 6480000 },
503 .n = { .min = 1, .max = 1 },
504 .m1 = { .min = 2, .max = 2 },
505 .m2 = { .min = 24 << 22, .max = 175 << 22 },
506 .p1 = { .min = 2, .max = 4 },
507 .p2 = { .p2_slow = 1, .p2_fast = 14 },
508 };
509
510 static const struct intel_limit intel_limits_bxt = {
511 /* FIXME: find real dot limits */
512 .dot = { .min = 0, .max = INT_MAX },
513 .vco = { .min = 4800000, .max = 6700000 },
514 .n = { .min = 1, .max = 1 },
515 .m1 = { .min = 2, .max = 2 },
516 /* FIXME: find real m2 limits */
517 .m2 = { .min = 2 << 22, .max = 255 << 22 },
518 .p1 = { .min = 2, .max = 4 },
519 .p2 = { .p2_slow = 1, .p2_fast = 20 },
520 };
521
522 static bool
523 needs_modeset(struct drm_crtc_state *state)
524 {
525 return drm_atomic_crtc_needs_modeset(state);
526 }
527
528 /**
529 * Returns whether any output on the specified pipe is of the specified type
530 */
531 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
532 {
533 struct drm_device *dev = crtc->base.dev;
534 struct intel_encoder *encoder;
535
536 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
537 if (encoder->type == type)
538 return true;
539
540 return false;
541 }
542
543 /**
544 * Returns whether any output on the specified pipe will have the specified
545 * type after a staged modeset is complete, i.e., the same as
546 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
547 * encoder->crtc.
548 */
549 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
550 int type)
551 {
552 struct drm_atomic_state *state = crtc_state->base.state;
553 struct drm_connector *connector;
554 struct drm_connector_state *connector_state;
555 struct intel_encoder *encoder;
556 int i, num_connectors = 0;
557
558 for_each_connector_in_state(state, connector, connector_state, i) {
559 if (connector_state->crtc != crtc_state->base.crtc)
560 continue;
561
562 num_connectors++;
563
564 encoder = to_intel_encoder(connector_state->best_encoder);
565 if (encoder->type == type)
566 return true;
567 }
568
569 WARN_ON(num_connectors == 0);
570
571 return false;
572 }
573
574 /*
575 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
576 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
577 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
578 * The helpers' return value is the rate of the clock that is fed to the
579 * display engine's pipe which can be the above fast dot clock rate or a
580 * divided-down version of it.
581 */
582 /* m1 is reserved as 0 in Pineview, n is a ring counter */
583 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
584 {
585 clock->m = clock->m2 + 2;
586 clock->p = clock->p1 * clock->p2;
587 if (WARN_ON(clock->n == 0 || clock->p == 0))
588 return 0;
589 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
590 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
591
592 return clock->dot;
593 }
594
595 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
596 {
597 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
598 }
599
600 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
601 {
602 clock->m = i9xx_dpll_compute_m(clock);
603 clock->p = clock->p1 * clock->p2;
604 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
605 return 0;
606 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
607 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
608
609 return clock->dot;
610 }
611
612 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
613 {
614 clock->m = clock->m1 * clock->m2;
615 clock->p = clock->p1 * clock->p2;
616 if (WARN_ON(clock->n == 0 || clock->p == 0))
617 return 0;
618 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
619 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
620
621 return clock->dot / 5;
622 }
623
624 int chv_calc_dpll_params(int refclk, struct dpll *clock)
625 {
626 clock->m = clock->m1 * clock->m2;
627 clock->p = clock->p1 * clock->p2;
628 if (WARN_ON(clock->n == 0 || clock->p == 0))
629 return 0;
630 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
631 clock->n << 22);
632 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
633
634 return clock->dot / 5;
635 }
636
637 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
638 /**
639 * Returns whether the given set of divisors are valid for a given refclk with
640 * the given connectors.
641 */
642
643 static bool intel_PLL_is_valid(struct drm_device *dev,
644 const struct intel_limit *limit,
645 const struct dpll *clock)
646 {
647 if (clock->n < limit->n.min || limit->n.max < clock->n)
648 INTELPllInvalid("n out of range\n");
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
652 INTELPllInvalid("m2 out of range\n");
653 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
654 INTELPllInvalid("m1 out of range\n");
655
656 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
657 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
658 if (clock->m1 <= clock->m2)
659 INTELPllInvalid("m1 <= m2\n");
660
661 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
662 if (clock->p < limit->p.min || limit->p.max < clock->p)
663 INTELPllInvalid("p out of range\n");
664 if (clock->m < limit->m.min || limit->m.max < clock->m)
665 INTELPllInvalid("m out of range\n");
666 }
667
668 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
669 INTELPllInvalid("vco out of range\n");
670 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
671 * connector, etc., rather than just a single range.
672 */
673 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 INTELPllInvalid("dot out of range\n");
675
676 return true;
677 }
678
679 static int
680 i9xx_select_p2_div(const struct intel_limit *limit,
681 const struct intel_crtc_state *crtc_state,
682 int target)
683 {
684 struct drm_device *dev = crtc_state->base.crtc->dev;
685
686 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
687 /*
688 * For LVDS just rely on its current settings for dual-channel.
689 * We haven't figured out how to reliably set up different
690 * single/dual channel state, if we even can.
691 */
692 if (intel_is_dual_link_lvds(dev))
693 return limit->p2.p2_fast;
694 else
695 return limit->p2.p2_slow;
696 } else {
697 if (target < limit->p2.dot_limit)
698 return limit->p2.p2_slow;
699 else
700 return limit->p2.p2_fast;
701 }
702 }
703
704 /*
705 * Returns a set of divisors for the desired target clock with the given
706 * refclk, or FALSE. The returned values represent the clock equation:
707 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
708 *
709 * Target and reference clocks are specified in kHz.
710 *
711 * If match_clock is provided, then best_clock P divider must match the P
712 * divider from @match_clock used for LVDS downclocking.
713 */
714 static bool
715 i9xx_find_best_dpll(const struct intel_limit *limit,
716 struct intel_crtc_state *crtc_state,
717 int target, int refclk, struct dpll *match_clock,
718 struct dpll *best_clock)
719 {
720 struct drm_device *dev = crtc_state->base.crtc->dev;
721 struct dpll clock;
722 int err = target;
723
724 memset(best_clock, 0, sizeof(*best_clock));
725
726 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
727
728 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
729 clock.m1++) {
730 for (clock.m2 = limit->m2.min;
731 clock.m2 <= limit->m2.max; clock.m2++) {
732 if (clock.m2 >= clock.m1)
733 break;
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 i9xx_calc_dpll_params(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 /*
762 * Returns a set of divisors for the desired target clock with the given
763 * refclk, or FALSE. The returned values represent the clock equation:
764 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
765 *
766 * Target and reference clocks are specified in kHz.
767 *
768 * If match_clock is provided, then best_clock P divider must match the P
769 * divider from @match_clock used for LVDS downclocking.
770 */
771 static bool
772 pnv_find_best_dpll(const struct intel_limit *limit,
773 struct intel_crtc_state *crtc_state,
774 int target, int refclk, struct dpll *match_clock,
775 struct dpll *best_clock)
776 {
777 struct drm_device *dev = crtc_state->base.crtc->dev;
778 struct dpll clock;
779 int err = target;
780
781 memset(best_clock, 0, sizeof(*best_clock));
782
783 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
784
785 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
786 clock.m1++) {
787 for (clock.m2 = limit->m2.min;
788 clock.m2 <= limit->m2.max; clock.m2++) {
789 for (clock.n = limit->n.min;
790 clock.n <= limit->n.max; clock.n++) {
791 for (clock.p1 = limit->p1.min;
792 clock.p1 <= limit->p1.max; clock.p1++) {
793 int this_err;
794
795 pnv_calc_dpll_params(refclk, &clock);
796 if (!intel_PLL_is_valid(dev, limit,
797 &clock))
798 continue;
799 if (match_clock &&
800 clock.p != match_clock->p)
801 continue;
802
803 this_err = abs(clock.dot - target);
804 if (this_err < err) {
805 *best_clock = clock;
806 err = this_err;
807 }
808 }
809 }
810 }
811 }
812
813 return (err != target);
814 }
815
816 /*
817 * Returns a set of divisors for the desired target clock with the given
818 * refclk, or FALSE. The returned values represent the clock equation:
819 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
820 *
821 * Target and reference clocks are specified in kHz.
822 *
823 * If match_clock is provided, then best_clock P divider must match the P
824 * divider from @match_clock used for LVDS downclocking.
825 */
826 static bool
827 g4x_find_best_dpll(const struct intel_limit *limit,
828 struct intel_crtc_state *crtc_state,
829 int target, int refclk, struct dpll *match_clock,
830 struct dpll *best_clock)
831 {
832 struct drm_device *dev = crtc_state->base.crtc->dev;
833 struct dpll clock;
834 int max_n;
835 bool found = false;
836 /* approximately equals target * 0.00585 */
837 int err_most = (target >> 8) + (target >> 9);
838
839 memset(best_clock, 0, sizeof(*best_clock));
840
841 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
842
843 max_n = limit->n.max;
844 /* based on hardware requirement, prefer smaller n to precision */
845 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
846 /* based on hardware requirement, prefere larger m1,m2 */
847 for (clock.m1 = limit->m1.max;
848 clock.m1 >= limit->m1.min; clock.m1--) {
849 for (clock.m2 = limit->m2.max;
850 clock.m2 >= limit->m2.min; clock.m2--) {
851 for (clock.p1 = limit->p1.max;
852 clock.p1 >= limit->p1.min; clock.p1--) {
853 int this_err;
854
855 i9xx_calc_dpll_params(refclk, &clock);
856 if (!intel_PLL_is_valid(dev, limit,
857 &clock))
858 continue;
859
860 this_err = abs(clock.dot - target);
861 if (this_err < err_most) {
862 *best_clock = clock;
863 err_most = this_err;
864 max_n = clock.n;
865 found = true;
866 }
867 }
868 }
869 }
870 }
871 return found;
872 }
873
874 /*
875 * Check if the calculated PLL configuration is more optimal compared to the
876 * best configuration and error found so far. Return the calculated error.
877 */
878 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
879 const struct dpll *calculated_clock,
880 const struct dpll *best_clock,
881 unsigned int best_error_ppm,
882 unsigned int *error_ppm)
883 {
884 /*
885 * For CHV ignore the error and consider only the P value.
886 * Prefer a bigger P value based on HW requirements.
887 */
888 if (IS_CHERRYVIEW(dev)) {
889 *error_ppm = 0;
890
891 return calculated_clock->p > best_clock->p;
892 }
893
894 if (WARN_ON_ONCE(!target_freq))
895 return false;
896
897 *error_ppm = div_u64(1000000ULL *
898 abs(target_freq - calculated_clock->dot),
899 target_freq);
900 /*
901 * Prefer a better P value over a better (smaller) error if the error
902 * is small. Ensure this preference for future configurations too by
903 * setting the error to 0.
904 */
905 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
906 *error_ppm = 0;
907
908 return true;
909 }
910
911 return *error_ppm + 10 < best_error_ppm;
912 }
913
914 /*
915 * Returns a set of divisors for the desired target clock with the given
916 * refclk, or FALSE. The returned values represent the clock equation:
917 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
918 */
919 static bool
920 vlv_find_best_dpll(const struct intel_limit *limit,
921 struct intel_crtc_state *crtc_state,
922 int target, int refclk, struct dpll *match_clock,
923 struct dpll *best_clock)
924 {
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
926 struct drm_device *dev = crtc->base.dev;
927 struct dpll clock;
928 unsigned int bestppm = 1000000;
929 /* min update 19.2 MHz */
930 int max_n = min(limit->n.max, refclk / 19200);
931 bool found = false;
932
933 target *= 5; /* fast clock */
934
935 memset(best_clock, 0, sizeof(*best_clock));
936
937 /* based on hardware requirement, prefer smaller n to precision */
938 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
939 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
940 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
942 clock.p = clock.p1 * clock.p2;
943 /* based on hardware requirement, prefer bigger m1,m2 values */
944 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
945 unsigned int ppm;
946
947 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
948 refclk * clock.m1);
949
950 vlv_calc_dpll_params(refclk, &clock);
951
952 if (!intel_PLL_is_valid(dev, limit,
953 &clock))
954 continue;
955
956 if (!vlv_PLL_is_optimal(dev, target,
957 &clock,
958 best_clock,
959 bestppm, &ppm))
960 continue;
961
962 *best_clock = clock;
963 bestppm = ppm;
964 found = true;
965 }
966 }
967 }
968 }
969
970 return found;
971 }
972
973 /*
974 * Returns a set of divisors for the desired target clock with the given
975 * refclk, or FALSE. The returned values represent the clock equation:
976 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 */
978 static bool
979 chv_find_best_dpll(const struct intel_limit *limit,
980 struct intel_crtc_state *crtc_state,
981 int target, int refclk, struct dpll *match_clock,
982 struct dpll *best_clock)
983 {
984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
985 struct drm_device *dev = crtc->base.dev;
986 unsigned int best_error_ppm;
987 struct dpll clock;
988 uint64_t m2;
989 int found = false;
990
991 memset(best_clock, 0, sizeof(*best_clock));
992 best_error_ppm = 1000000;
993
994 /*
995 * Based on hardware doc, the n always set to 1, and m1 always
996 * set to 2. If requires to support 200Mhz refclk, we need to
997 * revisit this because n may not 1 anymore.
998 */
999 clock.n = 1, clock.m1 = 2;
1000 target *= 5; /* fast clock */
1001
1002 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1003 for (clock.p2 = limit->p2.p2_fast;
1004 clock.p2 >= limit->p2.p2_slow;
1005 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1006 unsigned int error_ppm;
1007
1008 clock.p = clock.p1 * clock.p2;
1009
1010 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1011 clock.n) << 22, refclk * clock.m1);
1012
1013 if (m2 > INT_MAX/clock.m1)
1014 continue;
1015
1016 clock.m2 = m2;
1017
1018 chv_calc_dpll_params(refclk, &clock);
1019
1020 if (!intel_PLL_is_valid(dev, limit, &clock))
1021 continue;
1022
1023 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1024 best_error_ppm, &error_ppm))
1025 continue;
1026
1027 *best_clock = clock;
1028 best_error_ppm = error_ppm;
1029 found = true;
1030 }
1031 }
1032
1033 return found;
1034 }
1035
1036 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1037 struct dpll *best_clock)
1038 {
1039 int refclk = 100000;
1040 const struct intel_limit *limit = &intel_limits_bxt;
1041
1042 return chv_find_best_dpll(limit, crtc_state,
1043 target_clock, refclk, NULL, best_clock);
1044 }
1045
1046 bool intel_crtc_active(struct drm_crtc *crtc)
1047 {
1048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1049
1050 /* Be paranoid as we can arrive here with only partial
1051 * state retrieved from the hardware during setup.
1052 *
1053 * We can ditch the adjusted_mode.crtc_clock check as soon
1054 * as Haswell has gained clock readout/fastboot support.
1055 *
1056 * We can ditch the crtc->primary->fb check as soon as we can
1057 * properly reconstruct framebuffers.
1058 *
1059 * FIXME: The intel_crtc->active here should be switched to
1060 * crtc->state->active once we have proper CRTC states wired up
1061 * for atomic.
1062 */
1063 return intel_crtc->active && crtc->primary->state->fb &&
1064 intel_crtc->config->base.adjusted_mode.crtc_clock;
1065 }
1066
1067 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1068 enum pipe pipe)
1069 {
1070 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072
1073 return intel_crtc->config->cpu_transcoder;
1074 }
1075
1076 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1077 {
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 i915_reg_t reg = PIPEDSL(pipe);
1080 u32 line1, line2;
1081 u32 line_mask;
1082
1083 if (IS_GEN2(dev))
1084 line_mask = DSL_LINEMASK_GEN2;
1085 else
1086 line_mask = DSL_LINEMASK_GEN3;
1087
1088 line1 = I915_READ(reg) & line_mask;
1089 msleep(5);
1090 line2 = I915_READ(reg) & line_mask;
1091
1092 return line1 == line2;
1093 }
1094
1095 /*
1096 * intel_wait_for_pipe_off - wait for pipe to turn off
1097 * @crtc: crtc whose pipe to wait for
1098 *
1099 * After disabling a pipe, we can't wait for vblank in the usual way,
1100 * spinning on the vblank interrupt status bit, since we won't actually
1101 * see an interrupt when the pipe is disabled.
1102 *
1103 * On Gen4 and above:
1104 * wait for the pipe register state bit to turn off
1105 *
1106 * Otherwise:
1107 * wait for the display line value to settle (it usually
1108 * ends up stopping at the start of the next frame).
1109 *
1110 */
1111 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1112 {
1113 struct drm_device *dev = crtc->base.dev;
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1116 enum pipe pipe = crtc->pipe;
1117
1118 if (INTEL_INFO(dev)->gen >= 4) {
1119 i915_reg_t reg = PIPECONF(cpu_transcoder);
1120
1121 /* Wait for the Pipe State to go off */
1122 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1123 100))
1124 WARN(1, "pipe_off wait timed out\n");
1125 } else {
1126 /* Wait for the display line to settle */
1127 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1128 WARN(1, "pipe_off wait timed out\n");
1129 }
1130 }
1131
1132 /* Only for pre-ILK configs */
1133 void assert_pll(struct drm_i915_private *dev_priv,
1134 enum pipe pipe, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 val = I915_READ(DPLL(pipe));
1140 cur_state = !!(val & DPLL_VCO_ENABLE);
1141 I915_STATE_WARN(cur_state != state,
1142 "PLL state assertion failure (expected %s, current %s)\n",
1143 onoff(state), onoff(cur_state));
1144 }
1145
1146 /* XXX: the dsi pll is shared between MIPI DSI ports */
1147 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1148 {
1149 u32 val;
1150 bool cur_state;
1151
1152 mutex_lock(&dev_priv->sb_lock);
1153 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1154 mutex_unlock(&dev_priv->sb_lock);
1155
1156 cur_state = val & DSI_PLL_VCO_EN;
1157 I915_STATE_WARN(cur_state != state,
1158 "DSI PLL state assertion failure (expected %s, current %s)\n",
1159 onoff(state), onoff(cur_state));
1160 }
1161
1162 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1163 enum pipe pipe, bool state)
1164 {
1165 bool cur_state;
1166 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1167 pipe);
1168
1169 if (HAS_DDI(dev_priv)) {
1170 /* DDI does not have a specific FDI_TX register */
1171 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1172 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1173 } else {
1174 u32 val = I915_READ(FDI_TX_CTL(pipe));
1175 cur_state = !!(val & FDI_TX_ENABLE);
1176 }
1177 I915_STATE_WARN(cur_state != state,
1178 "FDI TX state assertion failure (expected %s, current %s)\n",
1179 onoff(state), onoff(cur_state));
1180 }
1181 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1182 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1183
1184 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186 {
1187 u32 val;
1188 bool cur_state;
1189
1190 val = I915_READ(FDI_RX_CTL(pipe));
1191 cur_state = !!(val & FDI_RX_ENABLE);
1192 I915_STATE_WARN(cur_state != state,
1193 "FDI RX state assertion failure (expected %s, current %s)\n",
1194 onoff(state), onoff(cur_state));
1195 }
1196 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1197 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1198
1199 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe)
1201 {
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
1205 if (IS_GEN5(dev_priv))
1206 return;
1207
1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209 if (HAS_DDI(dev_priv))
1210 return;
1211
1212 val = I915_READ(FDI_TX_CTL(pipe));
1213 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1214 }
1215
1216 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218 {
1219 u32 val;
1220 bool cur_state;
1221
1222 val = I915_READ(FDI_RX_CTL(pipe));
1223 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1224 I915_STATE_WARN(cur_state != state,
1225 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1226 onoff(state), onoff(cur_state));
1227 }
1228
1229 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1230 enum pipe pipe)
1231 {
1232 struct drm_device *dev = dev_priv->dev;
1233 i915_reg_t pp_reg;
1234 u32 val;
1235 enum pipe panel_pipe = PIPE_A;
1236 bool locked = true;
1237
1238 if (WARN_ON(HAS_DDI(dev)))
1239 return;
1240
1241 if (HAS_PCH_SPLIT(dev)) {
1242 u32 port_sel;
1243
1244 pp_reg = PCH_PP_CONTROL;
1245 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1246
1247 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1248 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1249 panel_pipe = PIPE_B;
1250 /* XXX: else fix for eDP */
1251 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1252 /* presumably write lock depends on pipe, not port select */
1253 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1254 panel_pipe = pipe;
1255 } else {
1256 pp_reg = PP_CONTROL;
1257 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1258 panel_pipe = PIPE_B;
1259 }
1260
1261 val = I915_READ(pp_reg);
1262 if (!(val & PANEL_POWER_ON) ||
1263 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1264 locked = false;
1265
1266 I915_STATE_WARN(panel_pipe == pipe && locked,
1267 "panel assertion failure, pipe %c regs locked\n",
1268 pipe_name(pipe));
1269 }
1270
1271 static void assert_cursor(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 struct drm_device *dev = dev_priv->dev;
1275 bool cur_state;
1276
1277 if (IS_845G(dev) || IS_I865G(dev))
1278 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1279 else
1280 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1281
1282 I915_STATE_WARN(cur_state != state,
1283 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1284 pipe_name(pipe), onoff(state), onoff(cur_state));
1285 }
1286 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1287 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1288
1289 void assert_pipe(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, bool state)
1291 {
1292 bool cur_state;
1293 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1294 pipe);
1295 enum intel_display_power_domain power_domain;
1296
1297 /* if we need the pipe quirk it must be always on */
1298 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1299 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1300 state = true;
1301
1302 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1303 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1304 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1305 cur_state = !!(val & PIPECONF_ENABLE);
1306
1307 intel_display_power_put(dev_priv, power_domain);
1308 } else {
1309 cur_state = false;
1310 }
1311
1312 I915_STATE_WARN(cur_state != state,
1313 "pipe %c assertion failure (expected %s, current %s)\n",
1314 pipe_name(pipe), onoff(state), onoff(cur_state));
1315 }
1316
1317 static void assert_plane(struct drm_i915_private *dev_priv,
1318 enum plane plane, bool state)
1319 {
1320 u32 val;
1321 bool cur_state;
1322
1323 val = I915_READ(DSPCNTR(plane));
1324 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1325 I915_STATE_WARN(cur_state != state,
1326 "plane %c assertion failure (expected %s, current %s)\n",
1327 plane_name(plane), onoff(state), onoff(cur_state));
1328 }
1329
1330 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1331 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1332
1333 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1334 enum pipe pipe)
1335 {
1336 struct drm_device *dev = dev_priv->dev;
1337 int i;
1338
1339 /* Primary planes are fixed to pipes on gen4+ */
1340 if (INTEL_INFO(dev)->gen >= 4) {
1341 u32 val = I915_READ(DSPCNTR(pipe));
1342 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1343 "plane %c assertion failure, should be disabled but not\n",
1344 plane_name(pipe));
1345 return;
1346 }
1347
1348 /* Need to check both planes against the pipe */
1349 for_each_pipe(dev_priv, i) {
1350 u32 val = I915_READ(DSPCNTR(i));
1351 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1352 DISPPLANE_SEL_PIPE_SHIFT;
1353 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1354 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1355 plane_name(i), pipe_name(pipe));
1356 }
1357 }
1358
1359 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 struct drm_device *dev = dev_priv->dev;
1363 int sprite;
1364
1365 if (INTEL_INFO(dev)->gen >= 9) {
1366 for_each_sprite(dev_priv, pipe, sprite) {
1367 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1368 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1369 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1370 sprite, pipe_name(pipe));
1371 }
1372 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1373 for_each_sprite(dev_priv, pipe, sprite) {
1374 u32 val = I915_READ(SPCNTR(pipe, sprite));
1375 I915_STATE_WARN(val & SP_ENABLE,
1376 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1377 sprite_name(pipe, sprite), pipe_name(pipe));
1378 }
1379 } else if (INTEL_INFO(dev)->gen >= 7) {
1380 u32 val = I915_READ(SPRCTL(pipe));
1381 I915_STATE_WARN(val & SPRITE_ENABLE,
1382 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1383 plane_name(pipe), pipe_name(pipe));
1384 } else if (INTEL_INFO(dev)->gen >= 5) {
1385 u32 val = I915_READ(DVSCNTR(pipe));
1386 I915_STATE_WARN(val & DVS_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(pipe), pipe_name(pipe));
1389 }
1390 }
1391
1392 static void assert_vblank_disabled(struct drm_crtc *crtc)
1393 {
1394 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1395 drm_crtc_vblank_put(crtc);
1396 }
1397
1398 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400 {
1401 u32 val;
1402 bool enabled;
1403
1404 val = I915_READ(PCH_TRANSCONF(pipe));
1405 enabled = !!(val & TRANS_ENABLE);
1406 I915_STATE_WARN(enabled,
1407 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1408 pipe_name(pipe));
1409 }
1410
1411 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 port_sel, u32 val)
1413 {
1414 if ((val & DP_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420 return false;
1421 } else if (IS_CHERRYVIEW(dev_priv)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423 return false;
1424 } else {
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426 return false;
1427 }
1428 return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433 {
1434 if ((val & SDVO_ENABLE) == 0)
1435 return false;
1436
1437 if (HAS_PCH_CPT(dev_priv)) {
1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439 return false;
1440 } else if (IS_CHERRYVIEW(dev_priv)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442 return false;
1443 } else {
1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445 return false;
1446 }
1447 return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1452 {
1453 if ((val & LVDS_PORT_EN) == 0)
1454 return false;
1455
1456 if (HAS_PCH_CPT(dev_priv)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461 return false;
1462 }
1463 return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1468 {
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1470 return false;
1471 if (HAS_PCH_CPT(dev_priv)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473 return false;
1474 } else {
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476 return false;
1477 }
1478 return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, i915_reg_t reg,
1483 u32 port_sel)
1484 {
1485 u32 val = I915_READ(reg);
1486 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1487 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1488 i915_mmio_reg_offset(reg), pipe_name(pipe));
1489
1490 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1491 && (val & DP_PIPEB_SELECT),
1492 "IBX PCH dp port still using transcoder B\n");
1493 }
1494
1495 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, i915_reg_t reg)
1497 {
1498 u32 val = I915_READ(reg);
1499 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1500 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1501 i915_mmio_reg_offset(reg), pipe_name(pipe));
1502
1503 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1504 && (val & SDVO_PIPE_B_SELECT),
1505 "IBX PCH hdmi port still using transcoder B\n");
1506 }
1507
1508 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe)
1510 {
1511 u32 val;
1512
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517 val = I915_READ(PCH_ADPA);
1518 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1519 "PCH VGA enabled on transcoder %c, should be disabled\n",
1520 pipe_name(pipe));
1521
1522 val = I915_READ(PCH_LVDS);
1523 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1524 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1525 pipe_name(pipe));
1526
1527 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1528 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1530 }
1531
1532 static void _vlv_enable_pll(struct intel_crtc *crtc,
1533 const struct intel_crtc_state *pipe_config)
1534 {
1535 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536 enum pipe pipe = crtc->pipe;
1537
1538 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1539 POSTING_READ(DPLL(pipe));
1540 udelay(150);
1541
1542 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1543 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1544 }
1545
1546 static void vlv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_state *pipe_config)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 enum pipe pipe = crtc->pipe;
1551
1552 assert_pipe_disabled(dev_priv, pipe);
1553
1554 /* PLL is protected by panel, make sure we can write it */
1555 assert_panel_unlocked(dev_priv, pipe);
1556
1557 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1558 _vlv_enable_pll(crtc, pipe_config);
1559
1560 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1561 POSTING_READ(DPLL_MD(pipe));
1562 }
1563
1564
1565 static void _chv_enable_pll(struct intel_crtc *crtc,
1566 const struct intel_crtc_state *pipe_config)
1567 {
1568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1569 enum pipe pipe = crtc->pipe;
1570 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1571 u32 tmp;
1572
1573 mutex_lock(&dev_priv->sb_lock);
1574
1575 /* Enable back the 10bit clock to display controller */
1576 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1577 tmp |= DPIO_DCLKP_EN;
1578 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1579
1580 mutex_unlock(&dev_priv->sb_lock);
1581
1582 /*
1583 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1584 */
1585 udelay(1);
1586
1587 /* Enable PLL */
1588 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1589
1590 /* Check PLL is locked */
1591 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1592 DRM_ERROR("PLL %d failed to lock\n", pipe);
1593 }
1594
1595 static void chv_enable_pll(struct intel_crtc *crtc,
1596 const struct intel_crtc_state *pipe_config)
1597 {
1598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1599 enum pipe pipe = crtc->pipe;
1600
1601 assert_pipe_disabled(dev_priv, pipe);
1602
1603 /* PLL is protected by panel, make sure we can write it */
1604 assert_panel_unlocked(dev_priv, pipe);
1605
1606 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1607 _chv_enable_pll(crtc, pipe_config);
1608
1609 if (pipe != PIPE_A) {
1610 /*
1611 * WaPixelRepeatModeFixForC0:chv
1612 *
1613 * DPLLCMD is AWOL. Use chicken bits to propagate
1614 * the value from DPLLBMD to either pipe B or C.
1615 */
1616 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1617 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1618 I915_WRITE(CBR4_VLV, 0);
1619 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1620
1621 /*
1622 * DPLLB VGA mode also seems to cause problems.
1623 * We should always have it disabled.
1624 */
1625 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1626 } else {
1627 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1628 POSTING_READ(DPLL_MD(pipe));
1629 }
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634 struct intel_crtc *crtc;
1635 int count = 0;
1636
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->base.state->active &&
1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641 return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 i915_reg_t reg = DPLL(crtc->pipe);
1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651 assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653 /* PLL is protected by panel, make sure we can write it */
1654 if (IS_MOBILE(dev) && !IS_I830(dev))
1655 assert_panel_unlocked(dev_priv, crtc->pipe);
1656
1657 /* Enable DVO 2x clock on both PLLs if necessary */
1658 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1659 /*
1660 * It appears to be important that we don't enable this
1661 * for the current pipe before otherwise configuring the
1662 * PLL. No idea how this should be handled if multiple
1663 * DVO outputs are enabled simultaneosly.
1664 */
1665 dpll |= DPLL_DVO_2X_MODE;
1666 I915_WRITE(DPLL(!crtc->pipe),
1667 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1668 }
1669
1670 /*
1671 * Apparently we need to have VGA mode enabled prior to changing
1672 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1673 * dividers, even though the register value does change.
1674 */
1675 I915_WRITE(reg, 0);
1676
1677 I915_WRITE(reg, dpll);
1678
1679 /* Wait for the clocks to stabilize. */
1680 POSTING_READ(reg);
1681 udelay(150);
1682
1683 if (INTEL_INFO(dev)->gen >= 4) {
1684 I915_WRITE(DPLL_MD(crtc->pipe),
1685 crtc->config->dpll_hw_state.dpll_md);
1686 } else {
1687 /* The pixel multiplier can only be updated once the
1688 * DPLL is enabled and the clocks are stable.
1689 *
1690 * So write it again.
1691 */
1692 I915_WRITE(reg, dpll);
1693 }
1694
1695 /* We do this three times for luck */
1696 I915_WRITE(reg, dpll);
1697 POSTING_READ(reg);
1698 udelay(150); /* wait for warmup */
1699 I915_WRITE(reg, dpll);
1700 POSTING_READ(reg);
1701 udelay(150); /* wait for warmup */
1702 I915_WRITE(reg, dpll);
1703 POSTING_READ(reg);
1704 udelay(150); /* wait for warmup */
1705 }
1706
1707 /**
1708 * i9xx_disable_pll - disable a PLL
1709 * @dev_priv: i915 private structure
1710 * @pipe: pipe PLL to disable
1711 *
1712 * Disable the PLL for @pipe, making sure the pipe is off first.
1713 *
1714 * Note! This is for pre-ILK only.
1715 */
1716 static void i9xx_disable_pll(struct intel_crtc *crtc)
1717 {
1718 struct drm_device *dev = crtc->base.dev;
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720 enum pipe pipe = crtc->pipe;
1721
1722 /* Disable DVO 2x clock on both PLLs if necessary */
1723 if (IS_I830(dev) &&
1724 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1725 !intel_num_dvo_pipes(dev)) {
1726 I915_WRITE(DPLL(PIPE_B),
1727 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1728 I915_WRITE(DPLL(PIPE_A),
1729 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1730 }
1731
1732 /* Don't disable pipe or pipe PLLs if needed */
1733 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1734 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1735 return;
1736
1737 /* Make sure the pipe isn't still relying on us */
1738 assert_pipe_disabled(dev_priv, pipe);
1739
1740 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1741 POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746 u32 val;
1747
1748 /* Make sure the pipe isn't still relying on us */
1749 assert_pipe_disabled(dev_priv, pipe);
1750
1751 val = DPLL_INTEGRATED_REF_CLK_VLV |
1752 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1753 if (pipe != PIPE_A)
1754 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1755
1756 I915_WRITE(DPLL(pipe), val);
1757 POSTING_READ(DPLL(pipe));
1758 }
1759
1760 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1761 {
1762 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1763 u32 val;
1764
1765 /* Make sure the pipe isn't still relying on us */
1766 assert_pipe_disabled(dev_priv, pipe);
1767
1768 val = DPLL_SSC_REF_CLK_CHV |
1769 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1770 if (pipe != PIPE_A)
1771 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1772
1773 I915_WRITE(DPLL(pipe), val);
1774 POSTING_READ(DPLL(pipe));
1775
1776 mutex_lock(&dev_priv->sb_lock);
1777
1778 /* Disable 10bit clock to display controller */
1779 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1780 val &= ~DPIO_DCLKP_EN;
1781 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1782
1783 mutex_unlock(&dev_priv->sb_lock);
1784 }
1785
1786 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1787 struct intel_digital_port *dport,
1788 unsigned int expected_mask)
1789 {
1790 u32 port_mask;
1791 i915_reg_t dpll_reg;
1792
1793 switch (dport->port) {
1794 case PORT_B:
1795 port_mask = DPLL_PORTB_READY_MASK;
1796 dpll_reg = DPLL(0);
1797 break;
1798 case PORT_C:
1799 port_mask = DPLL_PORTC_READY_MASK;
1800 dpll_reg = DPLL(0);
1801 expected_mask <<= 4;
1802 break;
1803 case PORT_D:
1804 port_mask = DPLL_PORTD_READY_MASK;
1805 dpll_reg = DPIO_PHY_STATUS;
1806 break;
1807 default:
1808 BUG();
1809 }
1810
1811 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1812 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1813 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1814 }
1815
1816 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1817 enum pipe pipe)
1818 {
1819 struct drm_device *dev = dev_priv->dev;
1820 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1822 i915_reg_t reg;
1823 uint32_t val, pipeconf_val;
1824
1825 /* Make sure PCH DPLL is enabled */
1826 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1827
1828 /* FDI must be feeding us bits for PCH ports */
1829 assert_fdi_tx_enabled(dev_priv, pipe);
1830 assert_fdi_rx_enabled(dev_priv, pipe);
1831
1832 if (HAS_PCH_CPT(dev)) {
1833 /* Workaround: Set the timing override bit before enabling the
1834 * pch transcoder. */
1835 reg = TRANS_CHICKEN2(pipe);
1836 val = I915_READ(reg);
1837 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1838 I915_WRITE(reg, val);
1839 }
1840
1841 reg = PCH_TRANSCONF(pipe);
1842 val = I915_READ(reg);
1843 pipeconf_val = I915_READ(PIPECONF(pipe));
1844
1845 if (HAS_PCH_IBX(dev_priv)) {
1846 /*
1847 * Make the BPC in transcoder be consistent with
1848 * that in pipeconf reg. For HDMI we must use 8bpc
1849 * here for both 8bpc and 12bpc.
1850 */
1851 val &= ~PIPECONF_BPC_MASK;
1852 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1853 val |= PIPECONF_8BPC;
1854 else
1855 val |= pipeconf_val & PIPECONF_BPC_MASK;
1856 }
1857
1858 val &= ~TRANS_INTERLACE_MASK;
1859 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1860 if (HAS_PCH_IBX(dev_priv) &&
1861 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1862 val |= TRANS_LEGACY_INTERLACED_ILK;
1863 else
1864 val |= TRANS_INTERLACED;
1865 else
1866 val |= TRANS_PROGRESSIVE;
1867
1868 I915_WRITE(reg, val | TRANS_ENABLE);
1869 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1870 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1871 }
1872
1873 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1874 enum transcoder cpu_transcoder)
1875 {
1876 u32 val, pipeconf_val;
1877
1878 /* FDI must be feeding us bits for PCH ports */
1879 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1880 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1881
1882 /* Workaround: set timing override bit. */
1883 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1884 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1885 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1886
1887 val = TRANS_ENABLE;
1888 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1889
1890 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1891 PIPECONF_INTERLACED_ILK)
1892 val |= TRANS_INTERLACED;
1893 else
1894 val |= TRANS_PROGRESSIVE;
1895
1896 I915_WRITE(LPT_TRANSCONF, val);
1897 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1898 DRM_ERROR("Failed to enable PCH transcoder\n");
1899 }
1900
1901 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1902 enum pipe pipe)
1903 {
1904 struct drm_device *dev = dev_priv->dev;
1905 i915_reg_t reg;
1906 uint32_t val;
1907
1908 /* FDI relies on the transcoder */
1909 assert_fdi_tx_disabled(dev_priv, pipe);
1910 assert_fdi_rx_disabled(dev_priv, pipe);
1911
1912 /* Ports must be off as well */
1913 assert_pch_ports_disabled(dev_priv, pipe);
1914
1915 reg = PCH_TRANSCONF(pipe);
1916 val = I915_READ(reg);
1917 val &= ~TRANS_ENABLE;
1918 I915_WRITE(reg, val);
1919 /* wait for PCH transcoder off, transcoder state */
1920 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1921 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1922
1923 if (HAS_PCH_CPT(dev)) {
1924 /* Workaround: Clear the timing override chicken bit again. */
1925 reg = TRANS_CHICKEN2(pipe);
1926 val = I915_READ(reg);
1927 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1928 I915_WRITE(reg, val);
1929 }
1930 }
1931
1932 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1933 {
1934 u32 val;
1935
1936 val = I915_READ(LPT_TRANSCONF);
1937 val &= ~TRANS_ENABLE;
1938 I915_WRITE(LPT_TRANSCONF, val);
1939 /* wait for PCH transcoder off, transcoder state */
1940 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1941 DRM_ERROR("Failed to disable PCH transcoder\n");
1942
1943 /* Workaround: clear timing override bit. */
1944 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1945 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1946 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1947 }
1948
1949 /**
1950 * intel_enable_pipe - enable a pipe, asserting requirements
1951 * @crtc: crtc responsible for the pipe
1952 *
1953 * Enable @crtc's pipe, making sure that various hardware specific requirements
1954 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1955 */
1956 static void intel_enable_pipe(struct intel_crtc *crtc)
1957 {
1958 struct drm_device *dev = crtc->base.dev;
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 enum pipe pipe = crtc->pipe;
1961 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1962 enum pipe pch_transcoder;
1963 i915_reg_t reg;
1964 u32 val;
1965
1966 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1967
1968 assert_planes_disabled(dev_priv, pipe);
1969 assert_cursor_disabled(dev_priv, pipe);
1970 assert_sprites_disabled(dev_priv, pipe);
1971
1972 if (HAS_PCH_LPT(dev_priv))
1973 pch_transcoder = TRANSCODER_A;
1974 else
1975 pch_transcoder = pipe;
1976
1977 /*
1978 * A pipe without a PLL won't actually be able to drive bits from
1979 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1980 * need the check.
1981 */
1982 if (HAS_GMCH_DISPLAY(dev_priv))
1983 if (crtc->config->has_dsi_encoder)
1984 assert_dsi_pll_enabled(dev_priv);
1985 else
1986 assert_pll_enabled(dev_priv, pipe);
1987 else {
1988 if (crtc->config->has_pch_encoder) {
1989 /* if driving the PCH, we need FDI enabled */
1990 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1991 assert_fdi_tx_pll_enabled(dev_priv,
1992 (enum pipe) cpu_transcoder);
1993 }
1994 /* FIXME: assert CPU port conditions for SNB+ */
1995 }
1996
1997 reg = PIPECONF(cpu_transcoder);
1998 val = I915_READ(reg);
1999 if (val & PIPECONF_ENABLE) {
2000 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2001 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2002 return;
2003 }
2004
2005 I915_WRITE(reg, val | PIPECONF_ENABLE);
2006 POSTING_READ(reg);
2007
2008 /*
2009 * Until the pipe starts DSL will read as 0, which would cause
2010 * an apparent vblank timestamp jump, which messes up also the
2011 * frame count when it's derived from the timestamps. So let's
2012 * wait for the pipe to start properly before we call
2013 * drm_crtc_vblank_on()
2014 */
2015 if (dev->max_vblank_count == 0 &&
2016 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2017 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2018 }
2019
2020 /**
2021 * intel_disable_pipe - disable a pipe, asserting requirements
2022 * @crtc: crtc whose pipes is to be disabled
2023 *
2024 * Disable the pipe of @crtc, making sure that various hardware
2025 * specific requirements are met, if applicable, e.g. plane
2026 * disabled, panel fitter off, etc.
2027 *
2028 * Will wait until the pipe has shut down before returning.
2029 */
2030 static void intel_disable_pipe(struct intel_crtc *crtc)
2031 {
2032 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2033 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2034 enum pipe pipe = crtc->pipe;
2035 i915_reg_t reg;
2036 u32 val;
2037
2038 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2039
2040 /*
2041 * Make sure planes won't keep trying to pump pixels to us,
2042 * or we might hang the display.
2043 */
2044 assert_planes_disabled(dev_priv, pipe);
2045 assert_cursor_disabled(dev_priv, pipe);
2046 assert_sprites_disabled(dev_priv, pipe);
2047
2048 reg = PIPECONF(cpu_transcoder);
2049 val = I915_READ(reg);
2050 if ((val & PIPECONF_ENABLE) == 0)
2051 return;
2052
2053 /*
2054 * Double wide has implications for planes
2055 * so best keep it disabled when not needed.
2056 */
2057 if (crtc->config->double_wide)
2058 val &= ~PIPECONF_DOUBLE_WIDE;
2059
2060 /* Don't disable pipe or pipe PLLs if needed */
2061 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2062 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2063 val &= ~PIPECONF_ENABLE;
2064
2065 I915_WRITE(reg, val);
2066 if ((val & PIPECONF_ENABLE) == 0)
2067 intel_wait_for_pipe_off(crtc);
2068 }
2069
2070 static bool need_vtd_wa(struct drm_device *dev)
2071 {
2072 #ifdef CONFIG_INTEL_IOMMU
2073 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2074 return true;
2075 #endif
2076 return false;
2077 }
2078
2079 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2080 {
2081 return IS_GEN2(dev_priv) ? 2048 : 4096;
2082 }
2083
2084 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2085 uint64_t fb_modifier, unsigned int cpp)
2086 {
2087 switch (fb_modifier) {
2088 case DRM_FORMAT_MOD_NONE:
2089 return cpp;
2090 case I915_FORMAT_MOD_X_TILED:
2091 if (IS_GEN2(dev_priv))
2092 return 128;
2093 else
2094 return 512;
2095 case I915_FORMAT_MOD_Y_TILED:
2096 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2097 return 128;
2098 else
2099 return 512;
2100 case I915_FORMAT_MOD_Yf_TILED:
2101 switch (cpp) {
2102 case 1:
2103 return 64;
2104 case 2:
2105 case 4:
2106 return 128;
2107 case 8:
2108 case 16:
2109 return 256;
2110 default:
2111 MISSING_CASE(cpp);
2112 return cpp;
2113 }
2114 break;
2115 default:
2116 MISSING_CASE(fb_modifier);
2117 return cpp;
2118 }
2119 }
2120
2121 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2122 uint64_t fb_modifier, unsigned int cpp)
2123 {
2124 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2125 return 1;
2126 else
2127 return intel_tile_size(dev_priv) /
2128 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2129 }
2130
2131 /* Return the tile dimensions in pixel units */
2132 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2133 unsigned int *tile_width,
2134 unsigned int *tile_height,
2135 uint64_t fb_modifier,
2136 unsigned int cpp)
2137 {
2138 unsigned int tile_width_bytes =
2139 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2140
2141 *tile_width = tile_width_bytes / cpp;
2142 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2143 }
2144
2145 unsigned int
2146 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2147 uint32_t pixel_format, uint64_t fb_modifier)
2148 {
2149 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2150 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2151
2152 return ALIGN(height, tile_height);
2153 }
2154
2155 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2156 {
2157 unsigned int size = 0;
2158 int i;
2159
2160 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2161 size += rot_info->plane[i].width * rot_info->plane[i].height;
2162
2163 return size;
2164 }
2165
2166 static void
2167 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2168 const struct drm_framebuffer *fb,
2169 unsigned int rotation)
2170 {
2171 if (intel_rotation_90_or_270(rotation)) {
2172 *view = i915_ggtt_view_rotated;
2173 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2174 } else {
2175 *view = i915_ggtt_view_normal;
2176 }
2177 }
2178
2179 static void
2180 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2181 struct drm_framebuffer *fb)
2182 {
2183 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2184 unsigned int tile_size, tile_width, tile_height, cpp;
2185
2186 tile_size = intel_tile_size(dev_priv);
2187
2188 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2189 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2190 fb->modifier[0], cpp);
2191
2192 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2193 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2194
2195 if (info->pixel_format == DRM_FORMAT_NV12) {
2196 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2197 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2198 fb->modifier[1], cpp);
2199
2200 info->uv_offset = fb->offsets[1];
2201 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2202 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2203 }
2204 }
2205
2206 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2207 {
2208 if (INTEL_INFO(dev_priv)->gen >= 9)
2209 return 256 * 1024;
2210 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2211 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2212 return 128 * 1024;
2213 else if (INTEL_INFO(dev_priv)->gen >= 4)
2214 return 4 * 1024;
2215 else
2216 return 0;
2217 }
2218
2219 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2220 uint64_t fb_modifier)
2221 {
2222 switch (fb_modifier) {
2223 case DRM_FORMAT_MOD_NONE:
2224 return intel_linear_alignment(dev_priv);
2225 case I915_FORMAT_MOD_X_TILED:
2226 if (INTEL_INFO(dev_priv)->gen >= 9)
2227 return 256 * 1024;
2228 return 0;
2229 case I915_FORMAT_MOD_Y_TILED:
2230 case I915_FORMAT_MOD_Yf_TILED:
2231 return 1 * 1024 * 1024;
2232 default:
2233 MISSING_CASE(fb_modifier);
2234 return 0;
2235 }
2236 }
2237
2238 int
2239 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2240 unsigned int rotation)
2241 {
2242 struct drm_device *dev = fb->dev;
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2245 struct i915_ggtt_view view;
2246 u32 alignment;
2247 int ret;
2248
2249 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2250
2251 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2252
2253 intel_fill_fb_ggtt_view(&view, fb, rotation);
2254
2255 /* Note that the w/a also requires 64 PTE of padding following the
2256 * bo. We currently fill all unused PTE with the shadow page and so
2257 * we should always have valid PTE following the scanout preventing
2258 * the VT-d warning.
2259 */
2260 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2261 alignment = 256 * 1024;
2262
2263 /*
2264 * Global gtt pte registers are special registers which actually forward
2265 * writes to a chunk of system memory. Which means that there is no risk
2266 * that the register values disappear as soon as we call
2267 * intel_runtime_pm_put(), so it is correct to wrap only the
2268 * pin/unpin/fence and not more.
2269 */
2270 intel_runtime_pm_get(dev_priv);
2271
2272 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2273 &view);
2274 if (ret)
2275 goto err_pm;
2276
2277 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2278 * fence, whereas 965+ only requires a fence if using
2279 * framebuffer compression. For simplicity, we always install
2280 * a fence as the cost is not that onerous.
2281 */
2282 if (view.type == I915_GGTT_VIEW_NORMAL) {
2283 ret = i915_gem_object_get_fence(obj);
2284 if (ret == -EDEADLK) {
2285 /*
2286 * -EDEADLK means there are no free fences
2287 * no pending flips.
2288 *
2289 * This is propagated to atomic, but it uses
2290 * -EDEADLK to force a locking recovery, so
2291 * change the returned error to -EBUSY.
2292 */
2293 ret = -EBUSY;
2294 goto err_unpin;
2295 } else if (ret)
2296 goto err_unpin;
2297
2298 i915_gem_object_pin_fence(obj);
2299 }
2300
2301 intel_runtime_pm_put(dev_priv);
2302 return 0;
2303
2304 err_unpin:
2305 i915_gem_object_unpin_from_display_plane(obj, &view);
2306 err_pm:
2307 intel_runtime_pm_put(dev_priv);
2308 return ret;
2309 }
2310
2311 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2312 {
2313 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2314 struct i915_ggtt_view view;
2315
2316 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2317
2318 intel_fill_fb_ggtt_view(&view, fb, rotation);
2319
2320 if (view.type == I915_GGTT_VIEW_NORMAL)
2321 i915_gem_object_unpin_fence(obj);
2322
2323 i915_gem_object_unpin_from_display_plane(obj, &view);
2324 }
2325
2326 /*
2327 * Adjust the tile offset by moving the difference into
2328 * the x/y offsets.
2329 *
2330 * Input tile dimensions and pitch must already be
2331 * rotated to match x and y, and in pixel units.
2332 */
2333 static u32 intel_adjust_tile_offset(int *x, int *y,
2334 unsigned int tile_width,
2335 unsigned int tile_height,
2336 unsigned int tile_size,
2337 unsigned int pitch_tiles,
2338 u32 old_offset,
2339 u32 new_offset)
2340 {
2341 unsigned int tiles;
2342
2343 WARN_ON(old_offset & (tile_size - 1));
2344 WARN_ON(new_offset & (tile_size - 1));
2345 WARN_ON(new_offset > old_offset);
2346
2347 tiles = (old_offset - new_offset) / tile_size;
2348
2349 *y += tiles / pitch_tiles * tile_height;
2350 *x += tiles % pitch_tiles * tile_width;
2351
2352 return new_offset;
2353 }
2354
2355 /*
2356 * Computes the linear offset to the base tile and adjusts
2357 * x, y. bytes per pixel is assumed to be a power-of-two.
2358 *
2359 * In the 90/270 rotated case, x and y are assumed
2360 * to be already rotated to match the rotated GTT view, and
2361 * pitch is the tile_height aligned framebuffer height.
2362 */
2363 u32 intel_compute_tile_offset(int *x, int *y,
2364 const struct drm_framebuffer *fb, int plane,
2365 unsigned int pitch,
2366 unsigned int rotation)
2367 {
2368 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2369 uint64_t fb_modifier = fb->modifier[plane];
2370 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2371 u32 offset, offset_aligned, alignment;
2372
2373 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2374 if (alignment)
2375 alignment--;
2376
2377 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2378 unsigned int tile_size, tile_width, tile_height;
2379 unsigned int tile_rows, tiles, pitch_tiles;
2380
2381 tile_size = intel_tile_size(dev_priv);
2382 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2383 fb_modifier, cpp);
2384
2385 if (intel_rotation_90_or_270(rotation)) {
2386 pitch_tiles = pitch / tile_height;
2387 swap(tile_width, tile_height);
2388 } else {
2389 pitch_tiles = pitch / (tile_width * cpp);
2390 }
2391
2392 tile_rows = *y / tile_height;
2393 *y %= tile_height;
2394
2395 tiles = *x / tile_width;
2396 *x %= tile_width;
2397
2398 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2399 offset_aligned = offset & ~alignment;
2400
2401 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2402 tile_size, pitch_tiles,
2403 offset, offset_aligned);
2404 } else {
2405 offset = *y * pitch + *x * cpp;
2406 offset_aligned = offset & ~alignment;
2407
2408 *y = (offset & alignment) / pitch;
2409 *x = ((offset & alignment) - *y * pitch) / cpp;
2410 }
2411
2412 return offset_aligned;
2413 }
2414
2415 static int i9xx_format_to_fourcc(int format)
2416 {
2417 switch (format) {
2418 case DISPPLANE_8BPP:
2419 return DRM_FORMAT_C8;
2420 case DISPPLANE_BGRX555:
2421 return DRM_FORMAT_XRGB1555;
2422 case DISPPLANE_BGRX565:
2423 return DRM_FORMAT_RGB565;
2424 default:
2425 case DISPPLANE_BGRX888:
2426 return DRM_FORMAT_XRGB8888;
2427 case DISPPLANE_RGBX888:
2428 return DRM_FORMAT_XBGR8888;
2429 case DISPPLANE_BGRX101010:
2430 return DRM_FORMAT_XRGB2101010;
2431 case DISPPLANE_RGBX101010:
2432 return DRM_FORMAT_XBGR2101010;
2433 }
2434 }
2435
2436 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2437 {
2438 switch (format) {
2439 case PLANE_CTL_FORMAT_RGB_565:
2440 return DRM_FORMAT_RGB565;
2441 default:
2442 case PLANE_CTL_FORMAT_XRGB_8888:
2443 if (rgb_order) {
2444 if (alpha)
2445 return DRM_FORMAT_ABGR8888;
2446 else
2447 return DRM_FORMAT_XBGR8888;
2448 } else {
2449 if (alpha)
2450 return DRM_FORMAT_ARGB8888;
2451 else
2452 return DRM_FORMAT_XRGB8888;
2453 }
2454 case PLANE_CTL_FORMAT_XRGB_2101010:
2455 if (rgb_order)
2456 return DRM_FORMAT_XBGR2101010;
2457 else
2458 return DRM_FORMAT_XRGB2101010;
2459 }
2460 }
2461
2462 static bool
2463 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2464 struct intel_initial_plane_config *plane_config)
2465 {
2466 struct drm_device *dev = crtc->base.dev;
2467 struct drm_i915_private *dev_priv = to_i915(dev);
2468 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2469 struct drm_i915_gem_object *obj = NULL;
2470 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2471 struct drm_framebuffer *fb = &plane_config->fb->base;
2472 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2473 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2474 PAGE_SIZE);
2475
2476 size_aligned -= base_aligned;
2477
2478 if (plane_config->size == 0)
2479 return false;
2480
2481 /* If the FB is too big, just don't use it since fbdev is not very
2482 * important and we should probably use that space with FBC or other
2483 * features. */
2484 if (size_aligned * 2 > ggtt->stolen_usable_size)
2485 return false;
2486
2487 mutex_lock(&dev->struct_mutex);
2488
2489 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2490 base_aligned,
2491 base_aligned,
2492 size_aligned);
2493 if (!obj) {
2494 mutex_unlock(&dev->struct_mutex);
2495 return false;
2496 }
2497
2498 obj->tiling_mode = plane_config->tiling;
2499 if (obj->tiling_mode == I915_TILING_X)
2500 obj->stride = fb->pitches[0];
2501
2502 mode_cmd.pixel_format = fb->pixel_format;
2503 mode_cmd.width = fb->width;
2504 mode_cmd.height = fb->height;
2505 mode_cmd.pitches[0] = fb->pitches[0];
2506 mode_cmd.modifier[0] = fb->modifier[0];
2507 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2508
2509 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2510 &mode_cmd, obj)) {
2511 DRM_DEBUG_KMS("intel fb init failed\n");
2512 goto out_unref_obj;
2513 }
2514
2515 mutex_unlock(&dev->struct_mutex);
2516
2517 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2518 return true;
2519
2520 out_unref_obj:
2521 drm_gem_object_unreference(&obj->base);
2522 mutex_unlock(&dev->struct_mutex);
2523 return false;
2524 }
2525
2526 static void
2527 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2528 struct intel_initial_plane_config *plane_config)
2529 {
2530 struct drm_device *dev = intel_crtc->base.dev;
2531 struct drm_i915_private *dev_priv = dev->dev_private;
2532 struct drm_crtc *c;
2533 struct intel_crtc *i;
2534 struct drm_i915_gem_object *obj;
2535 struct drm_plane *primary = intel_crtc->base.primary;
2536 struct drm_plane_state *plane_state = primary->state;
2537 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2538 struct intel_plane *intel_plane = to_intel_plane(primary);
2539 struct intel_plane_state *intel_state =
2540 to_intel_plane_state(plane_state);
2541 struct drm_framebuffer *fb;
2542
2543 if (!plane_config->fb)
2544 return;
2545
2546 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2547 fb = &plane_config->fb->base;
2548 goto valid_fb;
2549 }
2550
2551 kfree(plane_config->fb);
2552
2553 /*
2554 * Failed to alloc the obj, check to see if we should share
2555 * an fb with another CRTC instead
2556 */
2557 for_each_crtc(dev, c) {
2558 i = to_intel_crtc(c);
2559
2560 if (c == &intel_crtc->base)
2561 continue;
2562
2563 if (!i->active)
2564 continue;
2565
2566 fb = c->primary->fb;
2567 if (!fb)
2568 continue;
2569
2570 obj = intel_fb_obj(fb);
2571 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2572 drm_framebuffer_reference(fb);
2573 goto valid_fb;
2574 }
2575 }
2576
2577 /*
2578 * We've failed to reconstruct the BIOS FB. Current display state
2579 * indicates that the primary plane is visible, but has a NULL FB,
2580 * which will lead to problems later if we don't fix it up. The
2581 * simplest solution is to just disable the primary plane now and
2582 * pretend the BIOS never had it enabled.
2583 */
2584 to_intel_plane_state(plane_state)->visible = false;
2585 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2586 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2587 intel_plane->disable_plane(primary, &intel_crtc->base);
2588
2589 return;
2590
2591 valid_fb:
2592 plane_state->src_x = 0;
2593 plane_state->src_y = 0;
2594 plane_state->src_w = fb->width << 16;
2595 plane_state->src_h = fb->height << 16;
2596
2597 plane_state->crtc_x = 0;
2598 plane_state->crtc_y = 0;
2599 plane_state->crtc_w = fb->width;
2600 plane_state->crtc_h = fb->height;
2601
2602 intel_state->src.x1 = plane_state->src_x;
2603 intel_state->src.y1 = plane_state->src_y;
2604 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2605 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2606 intel_state->dst.x1 = plane_state->crtc_x;
2607 intel_state->dst.y1 = plane_state->crtc_y;
2608 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2609 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2610
2611 obj = intel_fb_obj(fb);
2612 if (obj->tiling_mode != I915_TILING_NONE)
2613 dev_priv->preserve_bios_swizzle = true;
2614
2615 drm_framebuffer_reference(fb);
2616 primary->fb = primary->state->fb = fb;
2617 primary->crtc = primary->state->crtc = &intel_crtc->base;
2618 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2619 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2620 }
2621
2622 static void i9xx_update_primary_plane(struct drm_plane *primary,
2623 const struct intel_crtc_state *crtc_state,
2624 const struct intel_plane_state *plane_state)
2625 {
2626 struct drm_device *dev = primary->dev;
2627 struct drm_i915_private *dev_priv = dev->dev_private;
2628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2629 struct drm_framebuffer *fb = plane_state->base.fb;
2630 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2631 int plane = intel_crtc->plane;
2632 u32 linear_offset;
2633 u32 dspcntr;
2634 i915_reg_t reg = DSPCNTR(plane);
2635 unsigned int rotation = plane_state->base.rotation;
2636 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2637 int x = plane_state->src.x1 >> 16;
2638 int y = plane_state->src.y1 >> 16;
2639
2640 dspcntr = DISPPLANE_GAMMA_ENABLE;
2641
2642 dspcntr |= DISPLAY_PLANE_ENABLE;
2643
2644 if (INTEL_INFO(dev)->gen < 4) {
2645 if (intel_crtc->pipe == PIPE_B)
2646 dspcntr |= DISPPLANE_SEL_PIPE_B;
2647
2648 /* pipesrc and dspsize control the size that is scaled from,
2649 * which should always be the user's requested size.
2650 */
2651 I915_WRITE(DSPSIZE(plane),
2652 ((crtc_state->pipe_src_h - 1) << 16) |
2653 (crtc_state->pipe_src_w - 1));
2654 I915_WRITE(DSPPOS(plane), 0);
2655 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2656 I915_WRITE(PRIMSIZE(plane),
2657 ((crtc_state->pipe_src_h - 1) << 16) |
2658 (crtc_state->pipe_src_w - 1));
2659 I915_WRITE(PRIMPOS(plane), 0);
2660 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2661 }
2662
2663 switch (fb->pixel_format) {
2664 case DRM_FORMAT_C8:
2665 dspcntr |= DISPPLANE_8BPP;
2666 break;
2667 case DRM_FORMAT_XRGB1555:
2668 dspcntr |= DISPPLANE_BGRX555;
2669 break;
2670 case DRM_FORMAT_RGB565:
2671 dspcntr |= DISPPLANE_BGRX565;
2672 break;
2673 case DRM_FORMAT_XRGB8888:
2674 dspcntr |= DISPPLANE_BGRX888;
2675 break;
2676 case DRM_FORMAT_XBGR8888:
2677 dspcntr |= DISPPLANE_RGBX888;
2678 break;
2679 case DRM_FORMAT_XRGB2101010:
2680 dspcntr |= DISPPLANE_BGRX101010;
2681 break;
2682 case DRM_FORMAT_XBGR2101010:
2683 dspcntr |= DISPPLANE_RGBX101010;
2684 break;
2685 default:
2686 BUG();
2687 }
2688
2689 if (INTEL_INFO(dev)->gen >= 4 &&
2690 obj->tiling_mode != I915_TILING_NONE)
2691 dspcntr |= DISPPLANE_TILED;
2692
2693 if (IS_G4X(dev))
2694 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2695
2696 linear_offset = y * fb->pitches[0] + x * cpp;
2697
2698 if (INTEL_INFO(dev)->gen >= 4) {
2699 intel_crtc->dspaddr_offset =
2700 intel_compute_tile_offset(&x, &y, fb, 0,
2701 fb->pitches[0], rotation);
2702 linear_offset -= intel_crtc->dspaddr_offset;
2703 } else {
2704 intel_crtc->dspaddr_offset = linear_offset;
2705 }
2706
2707 if (rotation == BIT(DRM_ROTATE_180)) {
2708 dspcntr |= DISPPLANE_ROTATE_180;
2709
2710 x += (crtc_state->pipe_src_w - 1);
2711 y += (crtc_state->pipe_src_h - 1);
2712
2713 /* Finding the last pixel of the last line of the display
2714 data and adding to linear_offset*/
2715 linear_offset +=
2716 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2717 (crtc_state->pipe_src_w - 1) * cpp;
2718 }
2719
2720 intel_crtc->adjusted_x = x;
2721 intel_crtc->adjusted_y = y;
2722
2723 I915_WRITE(reg, dspcntr);
2724
2725 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2726 if (INTEL_INFO(dev)->gen >= 4) {
2727 I915_WRITE(DSPSURF(plane),
2728 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2729 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2730 I915_WRITE(DSPLINOFF(plane), linear_offset);
2731 } else
2732 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2733 POSTING_READ(reg);
2734 }
2735
2736 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2737 struct drm_crtc *crtc)
2738 {
2739 struct drm_device *dev = crtc->dev;
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742 int plane = intel_crtc->plane;
2743
2744 I915_WRITE(DSPCNTR(plane), 0);
2745 if (INTEL_INFO(dev_priv)->gen >= 4)
2746 I915_WRITE(DSPSURF(plane), 0);
2747 else
2748 I915_WRITE(DSPADDR(plane), 0);
2749 POSTING_READ(DSPCNTR(plane));
2750 }
2751
2752 static void ironlake_update_primary_plane(struct drm_plane *primary,
2753 const struct intel_crtc_state *crtc_state,
2754 const struct intel_plane_state *plane_state)
2755 {
2756 struct drm_device *dev = primary->dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2759 struct drm_framebuffer *fb = plane_state->base.fb;
2760 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2761 int plane = intel_crtc->plane;
2762 u32 linear_offset;
2763 u32 dspcntr;
2764 i915_reg_t reg = DSPCNTR(plane);
2765 unsigned int rotation = plane_state->base.rotation;
2766 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2767 int x = plane_state->src.x1 >> 16;
2768 int y = plane_state->src.y1 >> 16;
2769
2770 dspcntr = DISPPLANE_GAMMA_ENABLE;
2771 dspcntr |= DISPLAY_PLANE_ENABLE;
2772
2773 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2774 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2775
2776 switch (fb->pixel_format) {
2777 case DRM_FORMAT_C8:
2778 dspcntr |= DISPPLANE_8BPP;
2779 break;
2780 case DRM_FORMAT_RGB565:
2781 dspcntr |= DISPPLANE_BGRX565;
2782 break;
2783 case DRM_FORMAT_XRGB8888:
2784 dspcntr |= DISPPLANE_BGRX888;
2785 break;
2786 case DRM_FORMAT_XBGR8888:
2787 dspcntr |= DISPPLANE_RGBX888;
2788 break;
2789 case DRM_FORMAT_XRGB2101010:
2790 dspcntr |= DISPPLANE_BGRX101010;
2791 break;
2792 case DRM_FORMAT_XBGR2101010:
2793 dspcntr |= DISPPLANE_RGBX101010;
2794 break;
2795 default:
2796 BUG();
2797 }
2798
2799 if (obj->tiling_mode != I915_TILING_NONE)
2800 dspcntr |= DISPPLANE_TILED;
2801
2802 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2803 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2804
2805 linear_offset = y * fb->pitches[0] + x * cpp;
2806 intel_crtc->dspaddr_offset =
2807 intel_compute_tile_offset(&x, &y, fb, 0,
2808 fb->pitches[0], rotation);
2809 linear_offset -= intel_crtc->dspaddr_offset;
2810 if (rotation == BIT(DRM_ROTATE_180)) {
2811 dspcntr |= DISPPLANE_ROTATE_180;
2812
2813 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2814 x += (crtc_state->pipe_src_w - 1);
2815 y += (crtc_state->pipe_src_h - 1);
2816
2817 /* Finding the last pixel of the last line of the display
2818 data and adding to linear_offset*/
2819 linear_offset +=
2820 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2821 (crtc_state->pipe_src_w - 1) * cpp;
2822 }
2823 }
2824
2825 intel_crtc->adjusted_x = x;
2826 intel_crtc->adjusted_y = y;
2827
2828 I915_WRITE(reg, dspcntr);
2829
2830 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2831 I915_WRITE(DSPSURF(plane),
2832 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2833 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2834 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2835 } else {
2836 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2837 I915_WRITE(DSPLINOFF(plane), linear_offset);
2838 }
2839 POSTING_READ(reg);
2840 }
2841
2842 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2843 uint64_t fb_modifier, uint32_t pixel_format)
2844 {
2845 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2846 return 64;
2847 } else {
2848 int cpp = drm_format_plane_cpp(pixel_format, 0);
2849
2850 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2851 }
2852 }
2853
2854 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2855 struct drm_i915_gem_object *obj,
2856 unsigned int plane)
2857 {
2858 struct i915_ggtt_view view;
2859 struct i915_vma *vma;
2860 u64 offset;
2861
2862 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2863 intel_plane->base.state->rotation);
2864
2865 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2866 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2867 view.type))
2868 return -1;
2869
2870 offset = vma->node.start;
2871
2872 if (plane == 1) {
2873 offset += vma->ggtt_view.params.rotated.uv_start_page *
2874 PAGE_SIZE;
2875 }
2876
2877 WARN_ON(upper_32_bits(offset));
2878
2879 return lower_32_bits(offset);
2880 }
2881
2882 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2883 {
2884 struct drm_device *dev = intel_crtc->base.dev;
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886
2887 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2888 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2889 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2890 }
2891
2892 /*
2893 * This function detaches (aka. unbinds) unused scalers in hardware
2894 */
2895 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2896 {
2897 struct intel_crtc_scaler_state *scaler_state;
2898 int i;
2899
2900 scaler_state = &intel_crtc->config->scaler_state;
2901
2902 /* loop through and disable scalers that aren't in use */
2903 for (i = 0; i < intel_crtc->num_scalers; i++) {
2904 if (!scaler_state->scalers[i].in_use)
2905 skl_detach_scaler(intel_crtc, i);
2906 }
2907 }
2908
2909 u32 skl_plane_ctl_format(uint32_t pixel_format)
2910 {
2911 switch (pixel_format) {
2912 case DRM_FORMAT_C8:
2913 return PLANE_CTL_FORMAT_INDEXED;
2914 case DRM_FORMAT_RGB565:
2915 return PLANE_CTL_FORMAT_RGB_565;
2916 case DRM_FORMAT_XBGR8888:
2917 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2918 case DRM_FORMAT_XRGB8888:
2919 return PLANE_CTL_FORMAT_XRGB_8888;
2920 /*
2921 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2922 * to be already pre-multiplied. We need to add a knob (or a different
2923 * DRM_FORMAT) for user-space to configure that.
2924 */
2925 case DRM_FORMAT_ABGR8888:
2926 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2927 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2928 case DRM_FORMAT_ARGB8888:
2929 return PLANE_CTL_FORMAT_XRGB_8888 |
2930 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2931 case DRM_FORMAT_XRGB2101010:
2932 return PLANE_CTL_FORMAT_XRGB_2101010;
2933 case DRM_FORMAT_XBGR2101010:
2934 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2935 case DRM_FORMAT_YUYV:
2936 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2937 case DRM_FORMAT_YVYU:
2938 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2939 case DRM_FORMAT_UYVY:
2940 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2941 case DRM_FORMAT_VYUY:
2942 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2943 default:
2944 MISSING_CASE(pixel_format);
2945 }
2946
2947 return 0;
2948 }
2949
2950 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2951 {
2952 switch (fb_modifier) {
2953 case DRM_FORMAT_MOD_NONE:
2954 break;
2955 case I915_FORMAT_MOD_X_TILED:
2956 return PLANE_CTL_TILED_X;
2957 case I915_FORMAT_MOD_Y_TILED:
2958 return PLANE_CTL_TILED_Y;
2959 case I915_FORMAT_MOD_Yf_TILED:
2960 return PLANE_CTL_TILED_YF;
2961 default:
2962 MISSING_CASE(fb_modifier);
2963 }
2964
2965 return 0;
2966 }
2967
2968 u32 skl_plane_ctl_rotation(unsigned int rotation)
2969 {
2970 switch (rotation) {
2971 case BIT(DRM_ROTATE_0):
2972 break;
2973 /*
2974 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2975 * while i915 HW rotation is clockwise, thats why this swapping.
2976 */
2977 case BIT(DRM_ROTATE_90):
2978 return PLANE_CTL_ROTATE_270;
2979 case BIT(DRM_ROTATE_180):
2980 return PLANE_CTL_ROTATE_180;
2981 case BIT(DRM_ROTATE_270):
2982 return PLANE_CTL_ROTATE_90;
2983 default:
2984 MISSING_CASE(rotation);
2985 }
2986
2987 return 0;
2988 }
2989
2990 static void skylake_update_primary_plane(struct drm_plane *plane,
2991 const struct intel_crtc_state *crtc_state,
2992 const struct intel_plane_state *plane_state)
2993 {
2994 struct drm_device *dev = plane->dev;
2995 struct drm_i915_private *dev_priv = dev->dev_private;
2996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2997 struct drm_framebuffer *fb = plane_state->base.fb;
2998 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2999 int pipe = intel_crtc->pipe;
3000 u32 plane_ctl, stride_div, stride;
3001 u32 tile_height, plane_offset, plane_size;
3002 unsigned int rotation = plane_state->base.rotation;
3003 int x_offset, y_offset;
3004 u32 surf_addr;
3005 int scaler_id = plane_state->scaler_id;
3006 int src_x = plane_state->src.x1 >> 16;
3007 int src_y = plane_state->src.y1 >> 16;
3008 int src_w = drm_rect_width(&plane_state->src) >> 16;
3009 int src_h = drm_rect_height(&plane_state->src) >> 16;
3010 int dst_x = plane_state->dst.x1;
3011 int dst_y = plane_state->dst.y1;
3012 int dst_w = drm_rect_width(&plane_state->dst);
3013 int dst_h = drm_rect_height(&plane_state->dst);
3014
3015 plane_ctl = PLANE_CTL_ENABLE |
3016 PLANE_CTL_PIPE_GAMMA_ENABLE |
3017 PLANE_CTL_PIPE_CSC_ENABLE;
3018
3019 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3020 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3021 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3022 plane_ctl |= skl_plane_ctl_rotation(rotation);
3023
3024 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3025 fb->pixel_format);
3026 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3027
3028 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3029
3030 if (intel_rotation_90_or_270(rotation)) {
3031 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3032
3033 /* stride = Surface height in tiles */
3034 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3035 stride = DIV_ROUND_UP(fb->height, tile_height);
3036 x_offset = stride * tile_height - src_y - src_h;
3037 y_offset = src_x;
3038 plane_size = (src_w - 1) << 16 | (src_h - 1);
3039 } else {
3040 stride = fb->pitches[0] / stride_div;
3041 x_offset = src_x;
3042 y_offset = src_y;
3043 plane_size = (src_h - 1) << 16 | (src_w - 1);
3044 }
3045 plane_offset = y_offset << 16 | x_offset;
3046
3047 intel_crtc->adjusted_x = x_offset;
3048 intel_crtc->adjusted_y = y_offset;
3049
3050 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3051 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3052 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3053 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3054
3055 if (scaler_id >= 0) {
3056 uint32_t ps_ctrl = 0;
3057
3058 WARN_ON(!dst_w || !dst_h);
3059 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3060 crtc_state->scaler_state.scalers[scaler_id].mode;
3061 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3062 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3063 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3064 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3065 I915_WRITE(PLANE_POS(pipe, 0), 0);
3066 } else {
3067 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3068 }
3069
3070 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3071
3072 POSTING_READ(PLANE_SURF(pipe, 0));
3073 }
3074
3075 static void skylake_disable_primary_plane(struct drm_plane *primary,
3076 struct drm_crtc *crtc)
3077 {
3078 struct drm_device *dev = crtc->dev;
3079 struct drm_i915_private *dev_priv = dev->dev_private;
3080 int pipe = to_intel_crtc(crtc)->pipe;
3081
3082 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3083 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3084 POSTING_READ(PLANE_SURF(pipe, 0));
3085 }
3086
3087 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3088 static int
3089 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3090 int x, int y, enum mode_set_atomic state)
3091 {
3092 /* Support for kgdboc is disabled, this needs a major rework. */
3093 DRM_ERROR("legacy panic handler not supported any more.\n");
3094
3095 return -ENODEV;
3096 }
3097
3098 static void intel_update_primary_planes(struct drm_device *dev)
3099 {
3100 struct drm_crtc *crtc;
3101
3102 for_each_crtc(dev, crtc) {
3103 struct intel_plane *plane = to_intel_plane(crtc->primary);
3104 struct intel_plane_state *plane_state;
3105
3106 drm_modeset_lock_crtc(crtc, &plane->base);
3107 plane_state = to_intel_plane_state(plane->base.state);
3108
3109 if (plane_state->visible)
3110 plane->update_plane(&plane->base,
3111 to_intel_crtc_state(crtc->state),
3112 plane_state);
3113
3114 drm_modeset_unlock_crtc(crtc);
3115 }
3116 }
3117
3118 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3119 {
3120 /* no reset support for gen2 */
3121 if (IS_GEN2(dev_priv))
3122 return;
3123
3124 /* reset doesn't touch the display */
3125 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3126 return;
3127
3128 drm_modeset_lock_all(dev_priv->dev);
3129 /*
3130 * Disabling the crtcs gracefully seems nicer. Also the
3131 * g33 docs say we should at least disable all the planes.
3132 */
3133 intel_display_suspend(dev_priv->dev);
3134 }
3135
3136 void intel_finish_reset(struct drm_i915_private *dev_priv)
3137 {
3138 /* no reset support for gen2 */
3139 if (IS_GEN2(dev_priv))
3140 return;
3141
3142 /* reset doesn't touch the display */
3143 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3144 /*
3145 * Flips in the rings have been nuked by the reset,
3146 * so update the base address of all primary
3147 * planes to the the last fb to make sure we're
3148 * showing the correct fb after a reset.
3149 *
3150 * FIXME: Atomic will make this obsolete since we won't schedule
3151 * CS-based flips (which might get lost in gpu resets) any more.
3152 */
3153 intel_update_primary_planes(dev_priv->dev);
3154 return;
3155 }
3156
3157 /*
3158 * The display has been reset as well,
3159 * so need a full re-initialization.
3160 */
3161 intel_runtime_pm_disable_interrupts(dev_priv);
3162 intel_runtime_pm_enable_interrupts(dev_priv);
3163
3164 intel_modeset_init_hw(dev_priv->dev);
3165
3166 spin_lock_irq(&dev_priv->irq_lock);
3167 if (dev_priv->display.hpd_irq_setup)
3168 dev_priv->display.hpd_irq_setup(dev_priv);
3169 spin_unlock_irq(&dev_priv->irq_lock);
3170
3171 intel_display_resume(dev_priv->dev);
3172
3173 intel_hpd_init(dev_priv);
3174
3175 drm_modeset_unlock_all(dev_priv->dev);
3176 }
3177
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180 return !list_empty_careful(&to_intel_crtc(crtc)->flip_work);
3181 }
3182
3183 static void intel_update_pipe_config(struct intel_crtc *crtc,
3184 struct intel_crtc_state *old_crtc_state)
3185 {
3186 struct drm_device *dev = crtc->base.dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc_state *pipe_config =
3189 to_intel_crtc_state(crtc->base.state);
3190
3191 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3192 crtc->base.mode = crtc->base.state->mode;
3193
3194 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3195 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3196 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3197
3198 /*
3199 * Update pipe size and adjust fitter if needed: the reason for this is
3200 * that in compute_mode_changes we check the native mode (not the pfit
3201 * mode) to see if we can flip rather than do a full mode set. In the
3202 * fastboot case, we'll flip, but if we don't update the pipesrc and
3203 * pfit state, we'll end up with a big fb scanned out into the wrong
3204 * sized surface.
3205 */
3206
3207 I915_WRITE(PIPESRC(crtc->pipe),
3208 ((pipe_config->pipe_src_w - 1) << 16) |
3209 (pipe_config->pipe_src_h - 1));
3210
3211 /* on skylake this is done by detaching scalers */
3212 if (INTEL_INFO(dev)->gen >= 9) {
3213 skl_detach_scalers(crtc);
3214
3215 if (pipe_config->pch_pfit.enabled)
3216 skylake_pfit_enable(crtc);
3217 } else if (HAS_PCH_SPLIT(dev)) {
3218 if (pipe_config->pch_pfit.enabled)
3219 ironlake_pfit_enable(crtc);
3220 else if (old_crtc_state->pch_pfit.enabled)
3221 ironlake_pfit_disable(crtc, true);
3222 }
3223 }
3224
3225 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3226 {
3227 struct drm_device *dev = crtc->dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3230 int pipe = intel_crtc->pipe;
3231 i915_reg_t reg;
3232 u32 temp;
3233
3234 /* enable normal train */
3235 reg = FDI_TX_CTL(pipe);
3236 temp = I915_READ(reg);
3237 if (IS_IVYBRIDGE(dev)) {
3238 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3239 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3240 } else {
3241 temp &= ~FDI_LINK_TRAIN_NONE;
3242 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3243 }
3244 I915_WRITE(reg, temp);
3245
3246 reg = FDI_RX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 if (HAS_PCH_CPT(dev)) {
3249 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3250 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3251 } else {
3252 temp &= ~FDI_LINK_TRAIN_NONE;
3253 temp |= FDI_LINK_TRAIN_NONE;
3254 }
3255 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3256
3257 /* wait one idle pattern time */
3258 POSTING_READ(reg);
3259 udelay(1000);
3260
3261 /* IVB wants error correction enabled */
3262 if (IS_IVYBRIDGE(dev))
3263 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3264 FDI_FE_ERRC_ENABLE);
3265 }
3266
3267 /* The FDI link training functions for ILK/Ibexpeak. */
3268 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3269 {
3270 struct drm_device *dev = crtc->dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273 int pipe = intel_crtc->pipe;
3274 i915_reg_t reg;
3275 u32 temp, tries;
3276
3277 /* FDI needs bits from pipe first */
3278 assert_pipe_enabled(dev_priv, pipe);
3279
3280 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3281 for train result */
3282 reg = FDI_RX_IMR(pipe);
3283 temp = I915_READ(reg);
3284 temp &= ~FDI_RX_SYMBOL_LOCK;
3285 temp &= ~FDI_RX_BIT_LOCK;
3286 I915_WRITE(reg, temp);
3287 I915_READ(reg);
3288 udelay(150);
3289
3290 /* enable CPU FDI TX and PCH FDI RX */
3291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3294 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3295 temp &= ~FDI_LINK_TRAIN_NONE;
3296 temp |= FDI_LINK_TRAIN_PATTERN_1;
3297 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3298
3299 reg = FDI_RX_CTL(pipe);
3300 temp = I915_READ(reg);
3301 temp &= ~FDI_LINK_TRAIN_NONE;
3302 temp |= FDI_LINK_TRAIN_PATTERN_1;
3303 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3304
3305 POSTING_READ(reg);
3306 udelay(150);
3307
3308 /* Ironlake workaround, enable clock pointer after FDI enable*/
3309 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3310 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3311 FDI_RX_PHASE_SYNC_POINTER_EN);
3312
3313 reg = FDI_RX_IIR(pipe);
3314 for (tries = 0; tries < 5; tries++) {
3315 temp = I915_READ(reg);
3316 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3317
3318 if ((temp & FDI_RX_BIT_LOCK)) {
3319 DRM_DEBUG_KMS("FDI train 1 done.\n");
3320 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3321 break;
3322 }
3323 }
3324 if (tries == 5)
3325 DRM_ERROR("FDI train 1 fail!\n");
3326
3327 /* Train 2 */
3328 reg = FDI_TX_CTL(pipe);
3329 temp = I915_READ(reg);
3330 temp &= ~FDI_LINK_TRAIN_NONE;
3331 temp |= FDI_LINK_TRAIN_PATTERN_2;
3332 I915_WRITE(reg, temp);
3333
3334 reg = FDI_RX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_PATTERN_2;
3338 I915_WRITE(reg, temp);
3339
3340 POSTING_READ(reg);
3341 udelay(150);
3342
3343 reg = FDI_RX_IIR(pipe);
3344 for (tries = 0; tries < 5; tries++) {
3345 temp = I915_READ(reg);
3346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3347
3348 if (temp & FDI_RX_SYMBOL_LOCK) {
3349 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3350 DRM_DEBUG_KMS("FDI train 2 done.\n");
3351 break;
3352 }
3353 }
3354 if (tries == 5)
3355 DRM_ERROR("FDI train 2 fail!\n");
3356
3357 DRM_DEBUG_KMS("FDI train done\n");
3358
3359 }
3360
3361 static const int snb_b_fdi_train_param[] = {
3362 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3363 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3364 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3365 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3366 };
3367
3368 /* The FDI link training functions for SNB/Cougarpoint. */
3369 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3370 {
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374 int pipe = intel_crtc->pipe;
3375 i915_reg_t reg;
3376 u32 temp, i, retry;
3377
3378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3379 for train result */
3380 reg = FDI_RX_IMR(pipe);
3381 temp = I915_READ(reg);
3382 temp &= ~FDI_RX_SYMBOL_LOCK;
3383 temp &= ~FDI_RX_BIT_LOCK;
3384 I915_WRITE(reg, temp);
3385
3386 POSTING_READ(reg);
3387 udelay(150);
3388
3389 /* enable CPU FDI TX and PCH FDI RX */
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3393 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3394 temp &= ~FDI_LINK_TRAIN_NONE;
3395 temp |= FDI_LINK_TRAIN_PATTERN_1;
3396 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3397 /* SNB-B */
3398 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3399 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3400
3401 I915_WRITE(FDI_RX_MISC(pipe),
3402 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3403
3404 reg = FDI_RX_CTL(pipe);
3405 temp = I915_READ(reg);
3406 if (HAS_PCH_CPT(dev)) {
3407 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3408 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3409 } else {
3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
3412 }
3413 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3414
3415 POSTING_READ(reg);
3416 udelay(150);
3417
3418 for (i = 0; i < 4; i++) {
3419 reg = FDI_TX_CTL(pipe);
3420 temp = I915_READ(reg);
3421 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3422 temp |= snb_b_fdi_train_param[i];
3423 I915_WRITE(reg, temp);
3424
3425 POSTING_READ(reg);
3426 udelay(500);
3427
3428 for (retry = 0; retry < 5; retry++) {
3429 reg = FDI_RX_IIR(pipe);
3430 temp = I915_READ(reg);
3431 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3432 if (temp & FDI_RX_BIT_LOCK) {
3433 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3434 DRM_DEBUG_KMS("FDI train 1 done.\n");
3435 break;
3436 }
3437 udelay(50);
3438 }
3439 if (retry < 5)
3440 break;
3441 }
3442 if (i == 4)
3443 DRM_ERROR("FDI train 1 fail!\n");
3444
3445 /* Train 2 */
3446 reg = FDI_TX_CTL(pipe);
3447 temp = I915_READ(reg);
3448 temp &= ~FDI_LINK_TRAIN_NONE;
3449 temp |= FDI_LINK_TRAIN_PATTERN_2;
3450 if (IS_GEN6(dev)) {
3451 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3452 /* SNB-B */
3453 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3454 }
3455 I915_WRITE(reg, temp);
3456
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 if (HAS_PCH_CPT(dev)) {
3460 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3461 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3462 } else {
3463 temp &= ~FDI_LINK_TRAIN_NONE;
3464 temp |= FDI_LINK_TRAIN_PATTERN_2;
3465 }
3466 I915_WRITE(reg, temp);
3467
3468 POSTING_READ(reg);
3469 udelay(150);
3470
3471 for (i = 0; i < 4; i++) {
3472 reg = FDI_TX_CTL(pipe);
3473 temp = I915_READ(reg);
3474 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3475 temp |= snb_b_fdi_train_param[i];
3476 I915_WRITE(reg, temp);
3477
3478 POSTING_READ(reg);
3479 udelay(500);
3480
3481 for (retry = 0; retry < 5; retry++) {
3482 reg = FDI_RX_IIR(pipe);
3483 temp = I915_READ(reg);
3484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
3490 udelay(50);
3491 }
3492 if (retry < 5)
3493 break;
3494 }
3495 if (i == 4)
3496 DRM_ERROR("FDI train 2 fail!\n");
3497
3498 DRM_DEBUG_KMS("FDI train done.\n");
3499 }
3500
3501 /* Manual link training for Ivy Bridge A0 parts */
3502 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3503 {
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507 int pipe = intel_crtc->pipe;
3508 i915_reg_t reg;
3509 u32 temp, i, j;
3510
3511 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3512 for train result */
3513 reg = FDI_RX_IMR(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_RX_SYMBOL_LOCK;
3516 temp &= ~FDI_RX_BIT_LOCK;
3517 I915_WRITE(reg, temp);
3518
3519 POSTING_READ(reg);
3520 udelay(150);
3521
3522 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3523 I915_READ(FDI_RX_IIR(pipe)));
3524
3525 /* Try each vswing and preemphasis setting twice before moving on */
3526 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3527 /* disable first in case we need to retry */
3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3531 temp &= ~FDI_TX_ENABLE;
3532 I915_WRITE(reg, temp);
3533
3534 reg = FDI_RX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~FDI_LINK_TRAIN_AUTO;
3537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3538 temp &= ~FDI_RX_ENABLE;
3539 I915_WRITE(reg, temp);
3540
3541 /* enable CPU FDI TX and PCH FDI RX */
3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3545 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3546 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548 temp |= snb_b_fdi_train_param[j/2];
3549 temp |= FDI_COMPOSITE_SYNC;
3550 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3551
3552 I915_WRITE(FDI_RX_MISC(pipe),
3553 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3554
3555 reg = FDI_RX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3558 temp |= FDI_COMPOSITE_SYNC;
3559 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3560
3561 POSTING_READ(reg);
3562 udelay(1); /* should be 0.5us */
3563
3564 for (i = 0; i < 4; i++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568
3569 if (temp & FDI_RX_BIT_LOCK ||
3570 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3571 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3572 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3573 i);
3574 break;
3575 }
3576 udelay(1); /* should be 0.5us */
3577 }
3578 if (i == 4) {
3579 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3580 continue;
3581 }
3582
3583 /* Train 2 */
3584 reg = FDI_TX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3587 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3588 I915_WRITE(reg, temp);
3589
3590 reg = FDI_RX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3593 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
3597 udelay(2); /* should be 1.5us */
3598
3599 for (i = 0; i < 4; i++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603
3604 if (temp & FDI_RX_SYMBOL_LOCK ||
3605 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3606 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3607 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3608 i);
3609 goto train_done;
3610 }
3611 udelay(2); /* should be 1.5us */
3612 }
3613 if (i == 4)
3614 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3615 }
3616
3617 train_done:
3618 DRM_DEBUG_KMS("FDI train done.\n");
3619 }
3620
3621 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3622 {
3623 struct drm_device *dev = intel_crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 int pipe = intel_crtc->pipe;
3626 i915_reg_t reg;
3627 u32 temp;
3628
3629 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3630 reg = FDI_RX_CTL(pipe);
3631 temp = I915_READ(reg);
3632 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3633 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3634 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3635 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3636
3637 POSTING_READ(reg);
3638 udelay(200);
3639
3640 /* Switch from Rawclk to PCDclk */
3641 temp = I915_READ(reg);
3642 I915_WRITE(reg, temp | FDI_PCDCLK);
3643
3644 POSTING_READ(reg);
3645 udelay(200);
3646
3647 /* Enable CPU FDI TX PLL, always on for Ironlake */
3648 reg = FDI_TX_CTL(pipe);
3649 temp = I915_READ(reg);
3650 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3651 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3652
3653 POSTING_READ(reg);
3654 udelay(100);
3655 }
3656 }
3657
3658 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3659 {
3660 struct drm_device *dev = intel_crtc->base.dev;
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 int pipe = intel_crtc->pipe;
3663 i915_reg_t reg;
3664 u32 temp;
3665
3666 /* Switch from PCDclk to Rawclk */
3667 reg = FDI_RX_CTL(pipe);
3668 temp = I915_READ(reg);
3669 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3670
3671 /* Disable CPU FDI TX PLL */
3672 reg = FDI_TX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3675
3676 POSTING_READ(reg);
3677 udelay(100);
3678
3679 reg = FDI_RX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3682
3683 /* Wait for the clocks to turn off. */
3684 POSTING_READ(reg);
3685 udelay(100);
3686 }
3687
3688 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3689 {
3690 struct drm_device *dev = crtc->dev;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693 int pipe = intel_crtc->pipe;
3694 i915_reg_t reg;
3695 u32 temp;
3696
3697 /* disable CPU FDI tx and PCH FDI rx */
3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3701 POSTING_READ(reg);
3702
3703 reg = FDI_RX_CTL(pipe);
3704 temp = I915_READ(reg);
3705 temp &= ~(0x7 << 16);
3706 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3707 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3708
3709 POSTING_READ(reg);
3710 udelay(100);
3711
3712 /* Ironlake workaround, disable clock pointer after downing FDI */
3713 if (HAS_PCH_IBX(dev))
3714 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3715
3716 /* still set train pattern 1 */
3717 reg = FDI_TX_CTL(pipe);
3718 temp = I915_READ(reg);
3719 temp &= ~FDI_LINK_TRAIN_NONE;
3720 temp |= FDI_LINK_TRAIN_PATTERN_1;
3721 I915_WRITE(reg, temp);
3722
3723 reg = FDI_RX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 if (HAS_PCH_CPT(dev)) {
3726 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3727 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728 } else {
3729 temp &= ~FDI_LINK_TRAIN_NONE;
3730 temp |= FDI_LINK_TRAIN_PATTERN_1;
3731 }
3732 /* BPC in FDI rx is consistent with that in PIPECONF */
3733 temp &= ~(0x07 << 16);
3734 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3735 I915_WRITE(reg, temp);
3736
3737 POSTING_READ(reg);
3738 udelay(100);
3739 }
3740
3741 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3742 {
3743 struct intel_crtc *crtc;
3744
3745 /* Note that we don't need to be called with mode_config.lock here
3746 * as our list of CRTC objects is static for the lifetime of the
3747 * device and so cannot disappear as we iterate. Similarly, we can
3748 * happily treat the predicates as racy, atomic checks as userspace
3749 * cannot claim and pin a new fb without at least acquring the
3750 * struct_mutex and so serialising with us.
3751 */
3752 for_each_intel_crtc(dev, crtc) {
3753 if (atomic_read(&crtc->unpin_work_count) == 0)
3754 continue;
3755
3756 if (!list_empty_careful(&crtc->flip_work))
3757 intel_wait_for_vblank(dev, crtc->pipe);
3758
3759 return true;
3760 }
3761
3762 return false;
3763 }
3764
3765 static void page_flip_completed(struct intel_crtc *intel_crtc, struct intel_flip_work *work)
3766 {
3767 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3768 struct drm_plane_state *new_plane_state;
3769 struct drm_plane *primary = intel_crtc->base.primary;
3770
3771 if (work->event)
3772 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3773
3774 drm_crtc_vblank_put(&intel_crtc->base);
3775
3776 new_plane_state = &work->old_plane_state[0]->base;
3777 if (work->num_planes >= 1 &&
3778 new_plane_state->plane == primary &&
3779 new_plane_state->fb)
3780 trace_i915_flip_complete(intel_crtc->plane,
3781 intel_fb_obj(new_plane_state->fb));
3782
3783 if (work->can_async_unpin) {
3784 list_del_init(&work->head);
3785 wake_up_all(&dev_priv->pending_flip_queue);
3786 }
3787
3788 queue_work(dev_priv->wq, &work->unpin_work);
3789 }
3790
3791 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3792 {
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 long ret;
3796
3797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3798
3799 ret = wait_event_interruptible_timeout(
3800 dev_priv->pending_flip_queue,
3801 !intel_crtc_has_pending_flip(crtc),
3802 60*HZ);
3803
3804 if (ret < 0)
3805 return ret;
3806
3807 WARN(ret == 0, "Stuck page flip\n");
3808
3809 return 0;
3810 }
3811
3812 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3813 {
3814 u32 temp;
3815
3816 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3817
3818 mutex_lock(&dev_priv->sb_lock);
3819
3820 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3821 temp |= SBI_SSCCTL_DISABLE;
3822 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3823
3824 mutex_unlock(&dev_priv->sb_lock);
3825 }
3826
3827 /* Program iCLKIP clock to the desired frequency */
3828 static void lpt_program_iclkip(struct drm_crtc *crtc)
3829 {
3830 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3831 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3832 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3833 u32 temp;
3834
3835 lpt_disable_iclkip(dev_priv);
3836
3837 /* The iCLK virtual clock root frequency is in MHz,
3838 * but the adjusted_mode->crtc_clock in in KHz. To get the
3839 * divisors, it is necessary to divide one by another, so we
3840 * convert the virtual clock precision to KHz here for higher
3841 * precision.
3842 */
3843 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3844 u32 iclk_virtual_root_freq = 172800 * 1000;
3845 u32 iclk_pi_range = 64;
3846 u32 desired_divisor;
3847
3848 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3849 clock << auxdiv);
3850 divsel = (desired_divisor / iclk_pi_range) - 2;
3851 phaseinc = desired_divisor % iclk_pi_range;
3852
3853 /*
3854 * Near 20MHz is a corner case which is
3855 * out of range for the 7-bit divisor
3856 */
3857 if (divsel <= 0x7f)
3858 break;
3859 }
3860
3861 /* This should not happen with any sane values */
3862 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3863 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3864 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3865 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3866
3867 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3868 clock,
3869 auxdiv,
3870 divsel,
3871 phasedir,
3872 phaseinc);
3873
3874 mutex_lock(&dev_priv->sb_lock);
3875
3876 /* Program SSCDIVINTPHASE6 */
3877 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3878 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3879 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3880 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3881 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3882 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3883 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3884 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3885
3886 /* Program SSCAUXDIV */
3887 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3888 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3889 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3890 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3891
3892 /* Enable modulator and associated divider */
3893 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3894 temp &= ~SBI_SSCCTL_DISABLE;
3895 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3896
3897 mutex_unlock(&dev_priv->sb_lock);
3898
3899 /* Wait for initialization time */
3900 udelay(24);
3901
3902 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3903 }
3904
3905 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3906 {
3907 u32 divsel, phaseinc, auxdiv;
3908 u32 iclk_virtual_root_freq = 172800 * 1000;
3909 u32 iclk_pi_range = 64;
3910 u32 desired_divisor;
3911 u32 temp;
3912
3913 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3914 return 0;
3915
3916 mutex_lock(&dev_priv->sb_lock);
3917
3918 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3919 if (temp & SBI_SSCCTL_DISABLE) {
3920 mutex_unlock(&dev_priv->sb_lock);
3921 return 0;
3922 }
3923
3924 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3925 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3926 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3927 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3928 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3929
3930 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3931 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3932 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3933
3934 mutex_unlock(&dev_priv->sb_lock);
3935
3936 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3937
3938 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3939 desired_divisor << auxdiv);
3940 }
3941
3942 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3943 enum pipe pch_transcoder)
3944 {
3945 struct drm_device *dev = crtc->base.dev;
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3948
3949 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3950 I915_READ(HTOTAL(cpu_transcoder)));
3951 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3952 I915_READ(HBLANK(cpu_transcoder)));
3953 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3954 I915_READ(HSYNC(cpu_transcoder)));
3955
3956 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3957 I915_READ(VTOTAL(cpu_transcoder)));
3958 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3959 I915_READ(VBLANK(cpu_transcoder)));
3960 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3961 I915_READ(VSYNC(cpu_transcoder)));
3962 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3963 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3964 }
3965
3966 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3967 {
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 uint32_t temp;
3970
3971 temp = I915_READ(SOUTH_CHICKEN1);
3972 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3973 return;
3974
3975 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3976 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3977
3978 temp &= ~FDI_BC_BIFURCATION_SELECT;
3979 if (enable)
3980 temp |= FDI_BC_BIFURCATION_SELECT;
3981
3982 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3983 I915_WRITE(SOUTH_CHICKEN1, temp);
3984 POSTING_READ(SOUTH_CHICKEN1);
3985 }
3986
3987 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3988 {
3989 struct drm_device *dev = intel_crtc->base.dev;
3990
3991 switch (intel_crtc->pipe) {
3992 case PIPE_A:
3993 break;
3994 case PIPE_B:
3995 if (intel_crtc->config->fdi_lanes > 2)
3996 cpt_set_fdi_bc_bifurcation(dev, false);
3997 else
3998 cpt_set_fdi_bc_bifurcation(dev, true);
3999
4000 break;
4001 case PIPE_C:
4002 cpt_set_fdi_bc_bifurcation(dev, true);
4003
4004 break;
4005 default:
4006 BUG();
4007 }
4008 }
4009
4010 /* Return which DP Port should be selected for Transcoder DP control */
4011 static enum port
4012 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4013 {
4014 struct drm_device *dev = crtc->dev;
4015 struct intel_encoder *encoder;
4016
4017 for_each_encoder_on_crtc(dev, crtc, encoder) {
4018 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4019 encoder->type == INTEL_OUTPUT_EDP)
4020 return enc_to_dig_port(&encoder->base)->port;
4021 }
4022
4023 return -1;
4024 }
4025
4026 /*
4027 * Enable PCH resources required for PCH ports:
4028 * - PCH PLLs
4029 * - FDI training & RX/TX
4030 * - update transcoder timings
4031 * - DP transcoding bits
4032 * - transcoder
4033 */
4034 static void ironlake_pch_enable(struct drm_crtc *crtc)
4035 {
4036 struct drm_device *dev = crtc->dev;
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039 int pipe = intel_crtc->pipe;
4040 u32 temp;
4041
4042 assert_pch_transcoder_disabled(dev_priv, pipe);
4043
4044 if (IS_IVYBRIDGE(dev))
4045 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4046
4047 /* Write the TU size bits before fdi link training, so that error
4048 * detection works. */
4049 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4050 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4051
4052 /* For PCH output, training FDI link */
4053 dev_priv->display.fdi_link_train(crtc);
4054
4055 /* We need to program the right clock selection before writing the pixel
4056 * mutliplier into the DPLL. */
4057 if (HAS_PCH_CPT(dev)) {
4058 u32 sel;
4059
4060 temp = I915_READ(PCH_DPLL_SEL);
4061 temp |= TRANS_DPLL_ENABLE(pipe);
4062 sel = TRANS_DPLLB_SEL(pipe);
4063 if (intel_crtc->config->shared_dpll ==
4064 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4065 temp |= sel;
4066 else
4067 temp &= ~sel;
4068 I915_WRITE(PCH_DPLL_SEL, temp);
4069 }
4070
4071 /* XXX: pch pll's can be enabled any time before we enable the PCH
4072 * transcoder, and we actually should do this to not upset any PCH
4073 * transcoder that already use the clock when we share it.
4074 *
4075 * Note that enable_shared_dpll tries to do the right thing, but
4076 * get_shared_dpll unconditionally resets the pll - we need that to have
4077 * the right LVDS enable sequence. */
4078 intel_enable_shared_dpll(intel_crtc);
4079
4080 /* set transcoder timing, panel must allow it */
4081 assert_panel_unlocked(dev_priv, pipe);
4082 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4083
4084 intel_fdi_normal_train(crtc);
4085
4086 /* For PCH DP, enable TRANS_DP_CTL */
4087 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4088 const struct drm_display_mode *adjusted_mode =
4089 &intel_crtc->config->base.adjusted_mode;
4090 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4091 i915_reg_t reg = TRANS_DP_CTL(pipe);
4092 temp = I915_READ(reg);
4093 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4094 TRANS_DP_SYNC_MASK |
4095 TRANS_DP_BPC_MASK);
4096 temp |= TRANS_DP_OUTPUT_ENABLE;
4097 temp |= bpc << 9; /* same format but at 11:9 */
4098
4099 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4100 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4101 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4102 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4103
4104 switch (intel_trans_dp_port_sel(crtc)) {
4105 case PORT_B:
4106 temp |= TRANS_DP_PORT_SEL_B;
4107 break;
4108 case PORT_C:
4109 temp |= TRANS_DP_PORT_SEL_C;
4110 break;
4111 case PORT_D:
4112 temp |= TRANS_DP_PORT_SEL_D;
4113 break;
4114 default:
4115 BUG();
4116 }
4117
4118 I915_WRITE(reg, temp);
4119 }
4120
4121 ironlake_enable_pch_transcoder(dev_priv, pipe);
4122 }
4123
4124 static void lpt_pch_enable(struct drm_crtc *crtc)
4125 {
4126 struct drm_device *dev = crtc->dev;
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4130
4131 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4132
4133 lpt_program_iclkip(crtc);
4134
4135 /* Set transcoder timing. */
4136 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4137
4138 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4139 }
4140
4141 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4142 {
4143 struct drm_i915_private *dev_priv = dev->dev_private;
4144 i915_reg_t dslreg = PIPEDSL(pipe);
4145 u32 temp;
4146
4147 temp = I915_READ(dslreg);
4148 udelay(500);
4149 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4150 if (wait_for(I915_READ(dslreg) != temp, 5))
4151 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4152 }
4153 }
4154
4155 static int
4156 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4157 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4158 int src_w, int src_h, int dst_w, int dst_h)
4159 {
4160 struct intel_crtc_scaler_state *scaler_state =
4161 &crtc_state->scaler_state;
4162 struct intel_crtc *intel_crtc =
4163 to_intel_crtc(crtc_state->base.crtc);
4164 int need_scaling;
4165
4166 need_scaling = intel_rotation_90_or_270(rotation) ?
4167 (src_h != dst_w || src_w != dst_h):
4168 (src_w != dst_w || src_h != dst_h);
4169
4170 /*
4171 * if plane is being disabled or scaler is no more required or force detach
4172 * - free scaler binded to this plane/crtc
4173 * - in order to do this, update crtc->scaler_usage
4174 *
4175 * Here scaler state in crtc_state is set free so that
4176 * scaler can be assigned to other user. Actual register
4177 * update to free the scaler is done in plane/panel-fit programming.
4178 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4179 */
4180 if (force_detach || !need_scaling) {
4181 if (*scaler_id >= 0) {
4182 scaler_state->scaler_users &= ~(1 << scaler_user);
4183 scaler_state->scalers[*scaler_id].in_use = 0;
4184
4185 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4186 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4187 intel_crtc->pipe, scaler_user, *scaler_id,
4188 scaler_state->scaler_users);
4189 *scaler_id = -1;
4190 }
4191 return 0;
4192 }
4193
4194 /* range checks */
4195 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4196 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4197
4198 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4199 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4200 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4201 "size is out of scaler range\n",
4202 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4203 return -EINVAL;
4204 }
4205
4206 /* mark this plane as a scaler user in crtc_state */
4207 scaler_state->scaler_users |= (1 << scaler_user);
4208 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4209 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4210 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4211 scaler_state->scaler_users);
4212
4213 return 0;
4214 }
4215
4216 /**
4217 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4218 *
4219 * @state: crtc's scaler state
4220 *
4221 * Return
4222 * 0 - scaler_usage updated successfully
4223 * error - requested scaling cannot be supported or other error condition
4224 */
4225 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4226 {
4227 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4228 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4229
4230 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4231 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4232
4233 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4234 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4235 state->pipe_src_w, state->pipe_src_h,
4236 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4237 }
4238
4239 /**
4240 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4241 *
4242 * @state: crtc's scaler state
4243 * @plane_state: atomic plane state to update
4244 *
4245 * Return
4246 * 0 - scaler_usage updated successfully
4247 * error - requested scaling cannot be supported or other error condition
4248 */
4249 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4250 struct intel_plane_state *plane_state)
4251 {
4252
4253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4254 struct intel_plane *intel_plane =
4255 to_intel_plane(plane_state->base.plane);
4256 struct drm_framebuffer *fb = plane_state->base.fb;
4257 int ret;
4258
4259 bool force_detach = !fb || !plane_state->visible;
4260
4261 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4262 intel_plane->base.base.id, intel_crtc->pipe,
4263 drm_plane_index(&intel_plane->base));
4264
4265 ret = skl_update_scaler(crtc_state, force_detach,
4266 drm_plane_index(&intel_plane->base),
4267 &plane_state->scaler_id,
4268 plane_state->base.rotation,
4269 drm_rect_width(&plane_state->src) >> 16,
4270 drm_rect_height(&plane_state->src) >> 16,
4271 drm_rect_width(&plane_state->dst),
4272 drm_rect_height(&plane_state->dst));
4273
4274 if (ret || plane_state->scaler_id < 0)
4275 return ret;
4276
4277 /* check colorkey */
4278 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4279 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4280 intel_plane->base.base.id);
4281 return -EINVAL;
4282 }
4283
4284 /* Check src format */
4285 switch (fb->pixel_format) {
4286 case DRM_FORMAT_RGB565:
4287 case DRM_FORMAT_XBGR8888:
4288 case DRM_FORMAT_XRGB8888:
4289 case DRM_FORMAT_ABGR8888:
4290 case DRM_FORMAT_ARGB8888:
4291 case DRM_FORMAT_XRGB2101010:
4292 case DRM_FORMAT_XBGR2101010:
4293 case DRM_FORMAT_YUYV:
4294 case DRM_FORMAT_YVYU:
4295 case DRM_FORMAT_UYVY:
4296 case DRM_FORMAT_VYUY:
4297 break;
4298 default:
4299 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4300 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4301 return -EINVAL;
4302 }
4303
4304 return 0;
4305 }
4306
4307 static void skylake_scaler_disable(struct intel_crtc *crtc)
4308 {
4309 int i;
4310
4311 for (i = 0; i < crtc->num_scalers; i++)
4312 skl_detach_scaler(crtc, i);
4313 }
4314
4315 static void skylake_pfit_enable(struct intel_crtc *crtc)
4316 {
4317 struct drm_device *dev = crtc->base.dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 int pipe = crtc->pipe;
4320 struct intel_crtc_scaler_state *scaler_state =
4321 &crtc->config->scaler_state;
4322
4323 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4324
4325 if (crtc->config->pch_pfit.enabled) {
4326 int id;
4327
4328 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4329 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4330 return;
4331 }
4332
4333 id = scaler_state->scaler_id;
4334 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4335 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4336 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4337 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4338
4339 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4340 }
4341 }
4342
4343 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4344 {
4345 struct drm_device *dev = crtc->base.dev;
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347 int pipe = crtc->pipe;
4348
4349 if (crtc->config->pch_pfit.enabled) {
4350 /* Force use of hard-coded filter coefficients
4351 * as some pre-programmed values are broken,
4352 * e.g. x201.
4353 */
4354 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4355 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4356 PF_PIPE_SEL_IVB(pipe));
4357 else
4358 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4359 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4360 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4361 }
4362 }
4363
4364 void hsw_enable_ips(struct intel_crtc *crtc)
4365 {
4366 struct drm_device *dev = crtc->base.dev;
4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368
4369 if (!crtc->config->ips_enabled)
4370 return;
4371
4372 /*
4373 * We can only enable IPS after we enable a plane and wait for a vblank
4374 * This function is called from post_plane_update, which is run after
4375 * a vblank wait.
4376 */
4377
4378 assert_plane_enabled(dev_priv, crtc->plane);
4379 if (IS_BROADWELL(dev)) {
4380 mutex_lock(&dev_priv->rps.hw_lock);
4381 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4382 mutex_unlock(&dev_priv->rps.hw_lock);
4383 /* Quoting Art Runyan: "its not safe to expect any particular
4384 * value in IPS_CTL bit 31 after enabling IPS through the
4385 * mailbox." Moreover, the mailbox may return a bogus state,
4386 * so we need to just enable it and continue on.
4387 */
4388 } else {
4389 I915_WRITE(IPS_CTL, IPS_ENABLE);
4390 /* The bit only becomes 1 in the next vblank, so this wait here
4391 * is essentially intel_wait_for_vblank. If we don't have this
4392 * and don't wait for vblanks until the end of crtc_enable, then
4393 * the HW state readout code will complain that the expected
4394 * IPS_CTL value is not the one we read. */
4395 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4396 DRM_ERROR("Timed out waiting for IPS enable\n");
4397 }
4398 }
4399
4400 void hsw_disable_ips(struct intel_crtc *crtc)
4401 {
4402 struct drm_device *dev = crtc->base.dev;
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404
4405 if (!crtc->config->ips_enabled)
4406 return;
4407
4408 assert_plane_enabled(dev_priv, crtc->plane);
4409 if (IS_BROADWELL(dev)) {
4410 mutex_lock(&dev_priv->rps.hw_lock);
4411 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4412 mutex_unlock(&dev_priv->rps.hw_lock);
4413 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4414 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4415 DRM_ERROR("Timed out waiting for IPS disable\n");
4416 } else {
4417 I915_WRITE(IPS_CTL, 0);
4418 POSTING_READ(IPS_CTL);
4419 }
4420
4421 /* We need to wait for a vblank before we can disable the plane. */
4422 intel_wait_for_vblank(dev, crtc->pipe);
4423 }
4424
4425 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4426 {
4427 if (intel_crtc->overlay) {
4428 struct drm_device *dev = intel_crtc->base.dev;
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430
4431 mutex_lock(&dev->struct_mutex);
4432 dev_priv->mm.interruptible = false;
4433 (void) intel_overlay_switch_off(intel_crtc->overlay);
4434 dev_priv->mm.interruptible = true;
4435 mutex_unlock(&dev->struct_mutex);
4436 }
4437
4438 /* Let userspace switch the overlay on again. In most cases userspace
4439 * has to recompute where to put it anyway.
4440 */
4441 }
4442
4443 /**
4444 * intel_post_enable_primary - Perform operations after enabling primary plane
4445 * @crtc: the CRTC whose primary plane was just enabled
4446 *
4447 * Performs potentially sleeping operations that must be done after the primary
4448 * plane is enabled, such as updating FBC and IPS. Note that this may be
4449 * called due to an explicit primary plane update, or due to an implicit
4450 * re-enable that is caused when a sprite plane is updated to no longer
4451 * completely hide the primary plane.
4452 */
4453 static void
4454 intel_post_enable_primary(struct drm_crtc *crtc)
4455 {
4456 struct drm_device *dev = crtc->dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4459 int pipe = intel_crtc->pipe;
4460
4461 /*
4462 * FIXME IPS should be fine as long as one plane is
4463 * enabled, but in practice it seems to have problems
4464 * when going from primary only to sprite only and vice
4465 * versa.
4466 */
4467 hsw_enable_ips(intel_crtc);
4468
4469 /*
4470 * Gen2 reports pipe underruns whenever all planes are disabled.
4471 * So don't enable underrun reporting before at least some planes
4472 * are enabled.
4473 * FIXME: Need to fix the logic to work when we turn off all planes
4474 * but leave the pipe running.
4475 */
4476 if (IS_GEN2(dev))
4477 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4478
4479 /* Underruns don't always raise interrupts, so check manually. */
4480 intel_check_cpu_fifo_underruns(dev_priv);
4481 intel_check_pch_fifo_underruns(dev_priv);
4482 }
4483
4484 /* FIXME move all this to pre_plane_update() with proper state tracking */
4485 static void
4486 intel_pre_disable_primary(struct drm_crtc *crtc)
4487 {
4488 struct drm_device *dev = crtc->dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4491 int pipe = intel_crtc->pipe;
4492
4493 /*
4494 * Gen2 reports pipe underruns whenever all planes are disabled.
4495 * So diasble underrun reporting before all the planes get disabled.
4496 * FIXME: Need to fix the logic to work when we turn off all planes
4497 * but leave the pipe running.
4498 */
4499 if (IS_GEN2(dev))
4500 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4501
4502 /*
4503 * FIXME IPS should be fine as long as one plane is
4504 * enabled, but in practice it seems to have problems
4505 * when going from primary only to sprite only and vice
4506 * versa.
4507 */
4508 hsw_disable_ips(intel_crtc);
4509 }
4510
4511 /* FIXME get rid of this and use pre_plane_update */
4512 static void
4513 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4514 {
4515 struct drm_device *dev = crtc->dev;
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518 int pipe = intel_crtc->pipe;
4519
4520 intel_pre_disable_primary(crtc);
4521
4522 /*
4523 * Vblank time updates from the shadow to live plane control register
4524 * are blocked if the memory self-refresh mode is active at that
4525 * moment. So to make sure the plane gets truly disabled, disable
4526 * first the self-refresh mode. The self-refresh enable bit in turn
4527 * will be checked/applied by the HW only at the next frame start
4528 * event which is after the vblank start event, so we need to have a
4529 * wait-for-vblank between disabling the plane and the pipe.
4530 */
4531 if (HAS_GMCH_DISPLAY(dev)) {
4532 intel_set_memory_cxsr(dev_priv, false);
4533 dev_priv->wm.vlv.cxsr = false;
4534 intel_wait_for_vblank(dev, pipe);
4535 }
4536 }
4537
4538 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4539 {
4540 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4541 struct drm_device *dev = crtc->base.dev;
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 struct intel_crtc_state *pipe_config =
4544 to_intel_crtc_state(crtc->base.state);
4545 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4546 struct drm_plane *primary = crtc->base.primary;
4547 struct drm_plane_state *old_pri_state =
4548 drm_atomic_get_existing_plane_state(old_state, primary);
4549 bool modeset = needs_modeset(&pipe_config->base);
4550
4551 if (old_pri_state) {
4552 struct intel_plane_state *primary_state =
4553 to_intel_plane_state(primary->state);
4554 struct intel_plane_state *old_primary_state =
4555 to_intel_plane_state(old_pri_state);
4556
4557 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4558
4559 if (old_primary_state->visible &&
4560 (modeset || !primary_state->visible))
4561 intel_pre_disable_primary(&crtc->base);
4562 }
4563
4564 if (pipe_config->disable_cxsr) {
4565 crtc->wm.cxsr_allowed = false;
4566
4567 /*
4568 * Vblank time updates from the shadow to live plane control register
4569 * are blocked if the memory self-refresh mode is active at that
4570 * moment. So to make sure the plane gets truly disabled, disable
4571 * first the self-refresh mode. The self-refresh enable bit in turn
4572 * will be checked/applied by the HW only at the next frame start
4573 * event which is after the vblank start event, so we need to have a
4574 * wait-for-vblank between disabling the plane and the pipe.
4575 */
4576 if (old_crtc_state->base.active) {
4577 intel_set_memory_cxsr(dev_priv, false);
4578 dev_priv->wm.vlv.cxsr = false;
4579 intel_wait_for_vblank(dev, crtc->pipe);
4580 }
4581 }
4582
4583 /*
4584 * IVB workaround: must disable low power watermarks for at least
4585 * one frame before enabling scaling. LP watermarks can be re-enabled
4586 * when scaling is disabled.
4587 *
4588 * WaCxSRDisabledForSpriteScaling:ivb
4589 */
4590 if (pipe_config->disable_lp_wm) {
4591 ilk_disable_lp_wm(dev);
4592 intel_wait_for_vblank(dev, crtc->pipe);
4593 }
4594
4595 /*
4596 * If we're doing a modeset, we're done. No need to do any pre-vblank
4597 * watermark programming here.
4598 */
4599 if (needs_modeset(&pipe_config->base))
4600 return;
4601
4602 /*
4603 * For platforms that support atomic watermarks, program the
4604 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4605 * will be the intermediate values that are safe for both pre- and
4606 * post- vblank; when vblank happens, the 'active' values will be set
4607 * to the final 'target' values and we'll do this again to get the
4608 * optimal watermarks. For gen9+ platforms, the values we program here
4609 * will be the final target values which will get automatically latched
4610 * at vblank time; no further programming will be necessary.
4611 *
4612 * If a platform hasn't been transitioned to atomic watermarks yet,
4613 * we'll continue to update watermarks the old way, if flags tell
4614 * us to.
4615 */
4616 if (dev_priv->display.initial_watermarks != NULL)
4617 dev_priv->display.initial_watermarks(pipe_config);
4618 else if (pipe_config->update_wm_pre)
4619 intel_update_watermarks(&crtc->base);
4620 }
4621
4622 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4623 {
4624 struct drm_device *dev = crtc->dev;
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 struct drm_plane *p;
4627 int pipe = intel_crtc->pipe;
4628
4629 intel_crtc_dpms_overlay_disable(intel_crtc);
4630
4631 drm_for_each_plane_mask(p, dev, plane_mask)
4632 to_intel_plane(p)->disable_plane(p, crtc);
4633
4634 /*
4635 * FIXME: Once we grow proper nuclear flip support out of this we need
4636 * to compute the mask of flip planes precisely. For the time being
4637 * consider this a flip to a NULL plane.
4638 */
4639 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4640 }
4641
4642 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4643 {
4644 struct drm_device *dev = crtc->dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647 struct intel_encoder *encoder;
4648 int pipe = intel_crtc->pipe;
4649 struct intel_crtc_state *pipe_config =
4650 to_intel_crtc_state(crtc->state);
4651
4652 if (WARN_ON(intel_crtc->active))
4653 return;
4654
4655 /*
4656 * Sometimes spurious CPU pipe underruns happen during FDI
4657 * training, at least with VGA+HDMI cloning. Suppress them.
4658 *
4659 * On ILK we get an occasional spurious CPU pipe underruns
4660 * between eDP port A enable and vdd enable. Also PCH port
4661 * enable seems to result in the occasional CPU pipe underrun.
4662 *
4663 * Spurious PCH underruns also occur during PCH enabling.
4664 */
4665 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4666 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4667 if (intel_crtc->config->has_pch_encoder)
4668 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4669
4670 if (intel_crtc->config->has_pch_encoder)
4671 intel_prepare_shared_dpll(intel_crtc);
4672
4673 if (intel_crtc->config->has_dp_encoder)
4674 intel_dp_set_m_n(intel_crtc, M1_N1);
4675
4676 intel_set_pipe_timings(intel_crtc);
4677 intel_set_pipe_src_size(intel_crtc);
4678
4679 if (intel_crtc->config->has_pch_encoder) {
4680 intel_cpu_transcoder_set_m_n(intel_crtc,
4681 &intel_crtc->config->fdi_m_n, NULL);
4682 }
4683
4684 ironlake_set_pipeconf(crtc);
4685
4686 intel_crtc->active = true;
4687
4688 for_each_encoder_on_crtc(dev, crtc, encoder)
4689 if (encoder->pre_enable)
4690 encoder->pre_enable(encoder);
4691
4692 if (intel_crtc->config->has_pch_encoder) {
4693 /* Note: FDI PLL enabling _must_ be done before we enable the
4694 * cpu pipes, hence this is separate from all the other fdi/pch
4695 * enabling. */
4696 ironlake_fdi_pll_enable(intel_crtc);
4697 } else {
4698 assert_fdi_tx_disabled(dev_priv, pipe);
4699 assert_fdi_rx_disabled(dev_priv, pipe);
4700 }
4701
4702 ironlake_pfit_enable(intel_crtc);
4703
4704 /*
4705 * On ILK+ LUT must be loaded before the pipe is running but with
4706 * clocks enabled
4707 */
4708 intel_color_load_luts(&pipe_config->base);
4709
4710 if (dev_priv->display.initial_watermarks != NULL)
4711 dev_priv->display.initial_watermarks(intel_crtc->config);
4712 intel_enable_pipe(intel_crtc);
4713
4714 if (intel_crtc->config->has_pch_encoder)
4715 ironlake_pch_enable(crtc);
4716
4717 assert_vblank_disabled(crtc);
4718 drm_crtc_vblank_on(crtc);
4719
4720 for_each_encoder_on_crtc(dev, crtc, encoder)
4721 encoder->enable(encoder);
4722
4723 if (HAS_PCH_CPT(dev))
4724 cpt_verify_modeset(dev, intel_crtc->pipe);
4725
4726 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4727 if (intel_crtc->config->has_pch_encoder)
4728 intel_wait_for_vblank(dev, pipe);
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4730 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4731 }
4732
4733 /* IPS only exists on ULT machines and is tied to pipe A. */
4734 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4735 {
4736 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4737 }
4738
4739 static void haswell_crtc_enable(struct drm_crtc *crtc)
4740 {
4741 struct drm_device *dev = crtc->dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4744 struct intel_encoder *encoder;
4745 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4746 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4747 struct intel_crtc_state *pipe_config =
4748 to_intel_crtc_state(crtc->state);
4749
4750 if (WARN_ON(intel_crtc->active))
4751 return;
4752
4753 if (intel_crtc->config->has_pch_encoder)
4754 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4755 false);
4756
4757 if (intel_crtc->config->shared_dpll)
4758 intel_enable_shared_dpll(intel_crtc);
4759
4760 if (intel_crtc->config->has_dp_encoder)
4761 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763 if (!intel_crtc->config->has_dsi_encoder)
4764 intel_set_pipe_timings(intel_crtc);
4765
4766 intel_set_pipe_src_size(intel_crtc);
4767
4768 if (cpu_transcoder != TRANSCODER_EDP &&
4769 !transcoder_is_dsi(cpu_transcoder)) {
4770 I915_WRITE(PIPE_MULT(cpu_transcoder),
4771 intel_crtc->config->pixel_multiplier - 1);
4772 }
4773
4774 if (intel_crtc->config->has_pch_encoder) {
4775 intel_cpu_transcoder_set_m_n(intel_crtc,
4776 &intel_crtc->config->fdi_m_n, NULL);
4777 }
4778
4779 if (!intel_crtc->config->has_dsi_encoder)
4780 haswell_set_pipeconf(crtc);
4781
4782 haswell_set_pipemisc(crtc);
4783
4784 intel_color_set_csc(&pipe_config->base);
4785
4786 intel_crtc->active = true;
4787
4788 if (intel_crtc->config->has_pch_encoder)
4789 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4790 else
4791 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4792
4793 for_each_encoder_on_crtc(dev, crtc, encoder) {
4794 if (encoder->pre_enable)
4795 encoder->pre_enable(encoder);
4796 }
4797
4798 if (intel_crtc->config->has_pch_encoder)
4799 dev_priv->display.fdi_link_train(crtc);
4800
4801 if (!intel_crtc->config->has_dsi_encoder)
4802 intel_ddi_enable_pipe_clock(intel_crtc);
4803
4804 if (INTEL_INFO(dev)->gen >= 9)
4805 skylake_pfit_enable(intel_crtc);
4806 else
4807 ironlake_pfit_enable(intel_crtc);
4808
4809 /*
4810 * On ILK+ LUT must be loaded before the pipe is running but with
4811 * clocks enabled
4812 */
4813 intel_color_load_luts(&pipe_config->base);
4814
4815 intel_ddi_set_pipe_settings(crtc);
4816 if (!intel_crtc->config->has_dsi_encoder)
4817 intel_ddi_enable_transcoder_func(crtc);
4818
4819 if (dev_priv->display.initial_watermarks != NULL)
4820 dev_priv->display.initial_watermarks(pipe_config);
4821 else
4822 intel_update_watermarks(crtc);
4823
4824 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4825 if (!intel_crtc->config->has_dsi_encoder)
4826 intel_enable_pipe(intel_crtc);
4827
4828 if (intel_crtc->config->has_pch_encoder)
4829 lpt_pch_enable(crtc);
4830
4831 if (intel_crtc->config->dp_encoder_is_mst)
4832 intel_ddi_set_vc_payload_alloc(crtc, true);
4833
4834 assert_vblank_disabled(crtc);
4835 drm_crtc_vblank_on(crtc);
4836
4837 for_each_encoder_on_crtc(dev, crtc, encoder) {
4838 encoder->enable(encoder);
4839 intel_opregion_notify_encoder(encoder, true);
4840 }
4841
4842 if (intel_crtc->config->has_pch_encoder) {
4843 intel_wait_for_vblank(dev, pipe);
4844 intel_wait_for_vblank(dev, pipe);
4845 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4846 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4847 true);
4848 }
4849
4850 /* If we change the relative order between pipe/planes enabling, we need
4851 * to change the workaround. */
4852 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4853 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4854 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4855 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4856 }
4857 }
4858
4859 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4860 {
4861 struct drm_device *dev = crtc->base.dev;
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863 int pipe = crtc->pipe;
4864
4865 /* To avoid upsetting the power well on haswell only disable the pfit if
4866 * it's in use. The hw state code will make sure we get this right. */
4867 if (force || crtc->config->pch_pfit.enabled) {
4868 I915_WRITE(PF_CTL(pipe), 0);
4869 I915_WRITE(PF_WIN_POS(pipe), 0);
4870 I915_WRITE(PF_WIN_SZ(pipe), 0);
4871 }
4872 }
4873
4874 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4875 {
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 struct intel_encoder *encoder;
4880 int pipe = intel_crtc->pipe;
4881
4882 /*
4883 * Sometimes spurious CPU pipe underruns happen when the
4884 * pipe is already disabled, but FDI RX/TX is still enabled.
4885 * Happens at least with VGA+HDMI cloning. Suppress them.
4886 */
4887 if (intel_crtc->config->has_pch_encoder) {
4888 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4889 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4890 }
4891
4892 for_each_encoder_on_crtc(dev, crtc, encoder)
4893 encoder->disable(encoder);
4894
4895 drm_crtc_vblank_off(crtc);
4896 assert_vblank_disabled(crtc);
4897
4898 intel_disable_pipe(intel_crtc);
4899
4900 ironlake_pfit_disable(intel_crtc, false);
4901
4902 if (intel_crtc->config->has_pch_encoder)
4903 ironlake_fdi_disable(crtc);
4904
4905 for_each_encoder_on_crtc(dev, crtc, encoder)
4906 if (encoder->post_disable)
4907 encoder->post_disable(encoder);
4908
4909 if (intel_crtc->config->has_pch_encoder) {
4910 ironlake_disable_pch_transcoder(dev_priv, pipe);
4911
4912 if (HAS_PCH_CPT(dev)) {
4913 i915_reg_t reg;
4914 u32 temp;
4915
4916 /* disable TRANS_DP_CTL */
4917 reg = TRANS_DP_CTL(pipe);
4918 temp = I915_READ(reg);
4919 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4920 TRANS_DP_PORT_SEL_MASK);
4921 temp |= TRANS_DP_PORT_SEL_NONE;
4922 I915_WRITE(reg, temp);
4923
4924 /* disable DPLL_SEL */
4925 temp = I915_READ(PCH_DPLL_SEL);
4926 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4927 I915_WRITE(PCH_DPLL_SEL, temp);
4928 }
4929
4930 ironlake_fdi_pll_disable(intel_crtc);
4931 }
4932
4933 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4935 }
4936
4937 static void haswell_crtc_disable(struct drm_crtc *crtc)
4938 {
4939 struct drm_device *dev = crtc->dev;
4940 struct drm_i915_private *dev_priv = dev->dev_private;
4941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942 struct intel_encoder *encoder;
4943 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4944
4945 if (intel_crtc->config->has_pch_encoder)
4946 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4947 false);
4948
4949 for_each_encoder_on_crtc(dev, crtc, encoder) {
4950 intel_opregion_notify_encoder(encoder, false);
4951 encoder->disable(encoder);
4952 }
4953
4954 drm_crtc_vblank_off(crtc);
4955 assert_vblank_disabled(crtc);
4956
4957 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4958 if (!intel_crtc->config->has_dsi_encoder)
4959 intel_disable_pipe(intel_crtc);
4960
4961 if (intel_crtc->config->dp_encoder_is_mst)
4962 intel_ddi_set_vc_payload_alloc(crtc, false);
4963
4964 if (!intel_crtc->config->has_dsi_encoder)
4965 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4966
4967 if (INTEL_INFO(dev)->gen >= 9)
4968 skylake_scaler_disable(intel_crtc);
4969 else
4970 ironlake_pfit_disable(intel_crtc, false);
4971
4972 if (!intel_crtc->config->has_dsi_encoder)
4973 intel_ddi_disable_pipe_clock(intel_crtc);
4974
4975 for_each_encoder_on_crtc(dev, crtc, encoder)
4976 if (encoder->post_disable)
4977 encoder->post_disable(encoder);
4978
4979 if (intel_crtc->config->has_pch_encoder) {
4980 lpt_disable_pch_transcoder(dev_priv);
4981 lpt_disable_iclkip(dev_priv);
4982 intel_ddi_fdi_disable(crtc);
4983
4984 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4985 true);
4986 }
4987 }
4988
4989 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4990 {
4991 struct drm_device *dev = crtc->base.dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_crtc_state *pipe_config = crtc->config;
4994
4995 if (!pipe_config->gmch_pfit.control)
4996 return;
4997
4998 /*
4999 * The panel fitter should only be adjusted whilst the pipe is disabled,
5000 * according to register description and PRM.
5001 */
5002 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5003 assert_pipe_disabled(dev_priv, crtc->pipe);
5004
5005 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5006 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5007
5008 /* Border color in case we don't scale up to the full screen. Black by
5009 * default, change to something else for debugging. */
5010 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5011 }
5012
5013 static enum intel_display_power_domain port_to_power_domain(enum port port)
5014 {
5015 switch (port) {
5016 case PORT_A:
5017 return POWER_DOMAIN_PORT_DDI_A_LANES;
5018 case PORT_B:
5019 return POWER_DOMAIN_PORT_DDI_B_LANES;
5020 case PORT_C:
5021 return POWER_DOMAIN_PORT_DDI_C_LANES;
5022 case PORT_D:
5023 return POWER_DOMAIN_PORT_DDI_D_LANES;
5024 case PORT_E:
5025 return POWER_DOMAIN_PORT_DDI_E_LANES;
5026 default:
5027 MISSING_CASE(port);
5028 return POWER_DOMAIN_PORT_OTHER;
5029 }
5030 }
5031
5032 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5033 {
5034 switch (port) {
5035 case PORT_A:
5036 return POWER_DOMAIN_AUX_A;
5037 case PORT_B:
5038 return POWER_DOMAIN_AUX_B;
5039 case PORT_C:
5040 return POWER_DOMAIN_AUX_C;
5041 case PORT_D:
5042 return POWER_DOMAIN_AUX_D;
5043 case PORT_E:
5044 /* FIXME: Check VBT for actual wiring of PORT E */
5045 return POWER_DOMAIN_AUX_D;
5046 default:
5047 MISSING_CASE(port);
5048 return POWER_DOMAIN_AUX_A;
5049 }
5050 }
5051
5052 enum intel_display_power_domain
5053 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5054 {
5055 struct drm_device *dev = intel_encoder->base.dev;
5056 struct intel_digital_port *intel_dig_port;
5057
5058 switch (intel_encoder->type) {
5059 case INTEL_OUTPUT_UNKNOWN:
5060 /* Only DDI platforms should ever use this output type */
5061 WARN_ON_ONCE(!HAS_DDI(dev));
5062 case INTEL_OUTPUT_DISPLAYPORT:
5063 case INTEL_OUTPUT_HDMI:
5064 case INTEL_OUTPUT_EDP:
5065 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5066 return port_to_power_domain(intel_dig_port->port);
5067 case INTEL_OUTPUT_DP_MST:
5068 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5069 return port_to_power_domain(intel_dig_port->port);
5070 case INTEL_OUTPUT_ANALOG:
5071 return POWER_DOMAIN_PORT_CRT;
5072 case INTEL_OUTPUT_DSI:
5073 return POWER_DOMAIN_PORT_DSI;
5074 default:
5075 return POWER_DOMAIN_PORT_OTHER;
5076 }
5077 }
5078
5079 enum intel_display_power_domain
5080 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5081 {
5082 struct drm_device *dev = intel_encoder->base.dev;
5083 struct intel_digital_port *intel_dig_port;
5084
5085 switch (intel_encoder->type) {
5086 case INTEL_OUTPUT_UNKNOWN:
5087 case INTEL_OUTPUT_HDMI:
5088 /*
5089 * Only DDI platforms should ever use these output types.
5090 * We can get here after the HDMI detect code has already set
5091 * the type of the shared encoder. Since we can't be sure
5092 * what's the status of the given connectors, play safe and
5093 * run the DP detection too.
5094 */
5095 WARN_ON_ONCE(!HAS_DDI(dev));
5096 case INTEL_OUTPUT_DISPLAYPORT:
5097 case INTEL_OUTPUT_EDP:
5098 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5099 return port_to_aux_power_domain(intel_dig_port->port);
5100 case INTEL_OUTPUT_DP_MST:
5101 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5102 return port_to_aux_power_domain(intel_dig_port->port);
5103 default:
5104 MISSING_CASE(intel_encoder->type);
5105 return POWER_DOMAIN_AUX_A;
5106 }
5107 }
5108
5109 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5110 struct intel_crtc_state *crtc_state)
5111 {
5112 struct drm_device *dev = crtc->dev;
5113 struct drm_encoder *encoder;
5114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115 enum pipe pipe = intel_crtc->pipe;
5116 unsigned long mask;
5117 enum transcoder transcoder = crtc_state->cpu_transcoder;
5118
5119 if (!crtc_state->base.active)
5120 return 0;
5121
5122 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5123 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5124 if (crtc_state->pch_pfit.enabled ||
5125 crtc_state->pch_pfit.force_thru)
5126 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5127
5128 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5129 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5130
5131 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5132 }
5133
5134 if (crtc_state->shared_dpll)
5135 mask |= BIT(POWER_DOMAIN_PLLS);
5136
5137 return mask;
5138 }
5139
5140 static unsigned long
5141 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5142 struct intel_crtc_state *crtc_state)
5143 {
5144 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5146 enum intel_display_power_domain domain;
5147 unsigned long domains, new_domains, old_domains, ms_domain = 0;
5148
5149 old_domains = intel_crtc->enabled_power_domains;
5150 intel_crtc->enabled_power_domains = new_domains =
5151 get_crtc_power_domains(crtc, crtc_state);
5152
5153 if (needs_modeset(&crtc_state->base))
5154 ms_domain = BIT(POWER_DOMAIN_MODESET);
5155
5156 domains = (new_domains & ~old_domains) | ms_domain;
5157
5158 for_each_power_domain(domain, domains)
5159 intel_display_power_get(dev_priv, domain);
5160
5161 return (old_domains & ~new_domains) | ms_domain;
5162 }
5163
5164 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5165 unsigned long domains)
5166 {
5167 enum intel_display_power_domain domain;
5168
5169 for_each_power_domain(domain, domains)
5170 intel_display_power_put(dev_priv, domain);
5171 }
5172
5173 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5174 {
5175 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5176
5177 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5178 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5179 return max_cdclk_freq;
5180 else if (IS_CHERRYVIEW(dev_priv))
5181 return max_cdclk_freq*95/100;
5182 else if (INTEL_INFO(dev_priv)->gen < 4)
5183 return 2*max_cdclk_freq*90/100;
5184 else
5185 return max_cdclk_freq*90/100;
5186 }
5187
5188 static void intel_update_max_cdclk(struct drm_device *dev)
5189 {
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191
5192 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5193 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5194
5195 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5196 dev_priv->max_cdclk_freq = 675000;
5197 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5198 dev_priv->max_cdclk_freq = 540000;
5199 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5200 dev_priv->max_cdclk_freq = 450000;
5201 else
5202 dev_priv->max_cdclk_freq = 337500;
5203 } else if (IS_BROXTON(dev)) {
5204 dev_priv->max_cdclk_freq = 624000;
5205 } else if (IS_BROADWELL(dev)) {
5206 /*
5207 * FIXME with extra cooling we can allow
5208 * 540 MHz for ULX and 675 Mhz for ULT.
5209 * How can we know if extra cooling is
5210 * available? PCI ID, VTB, something else?
5211 */
5212 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5213 dev_priv->max_cdclk_freq = 450000;
5214 else if (IS_BDW_ULX(dev))
5215 dev_priv->max_cdclk_freq = 450000;
5216 else if (IS_BDW_ULT(dev))
5217 dev_priv->max_cdclk_freq = 540000;
5218 else
5219 dev_priv->max_cdclk_freq = 675000;
5220 } else if (IS_CHERRYVIEW(dev)) {
5221 dev_priv->max_cdclk_freq = 320000;
5222 } else if (IS_VALLEYVIEW(dev)) {
5223 dev_priv->max_cdclk_freq = 400000;
5224 } else {
5225 /* otherwise assume cdclk is fixed */
5226 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5227 }
5228
5229 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5230
5231 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5232 dev_priv->max_cdclk_freq);
5233
5234 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5235 dev_priv->max_dotclk_freq);
5236 }
5237
5238 static void intel_update_cdclk(struct drm_device *dev)
5239 {
5240 struct drm_i915_private *dev_priv = dev->dev_private;
5241
5242 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5243 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5244 dev_priv->cdclk_freq);
5245
5246 /*
5247 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5248 * Programmng [sic] note: bit[9:2] should be programmed to the number
5249 * of cdclk that generates 4MHz reference clock freq which is used to
5250 * generate GMBus clock. This will vary with the cdclk freq.
5251 */
5252 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5253 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5254
5255 if (dev_priv->max_cdclk_freq == 0)
5256 intel_update_max_cdclk(dev);
5257 }
5258
5259 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5260 static int skl_cdclk_decimal(int cdclk)
5261 {
5262 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5263 }
5264
5265 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5266 {
5267 uint32_t divider;
5268 uint32_t ratio;
5269 uint32_t current_cdclk;
5270 int ret;
5271
5272 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5273 switch (cdclk) {
5274 case 144000:
5275 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5276 ratio = BXT_DE_PLL_RATIO(60);
5277 break;
5278 case 288000:
5279 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5280 ratio = BXT_DE_PLL_RATIO(60);
5281 break;
5282 case 384000:
5283 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5284 ratio = BXT_DE_PLL_RATIO(60);
5285 break;
5286 case 576000:
5287 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5288 ratio = BXT_DE_PLL_RATIO(60);
5289 break;
5290 case 624000:
5291 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5292 ratio = BXT_DE_PLL_RATIO(65);
5293 break;
5294 case 19200:
5295 /*
5296 * Bypass frequency with DE PLL disabled. Init ratio, divider
5297 * to suppress GCC warning.
5298 */
5299 ratio = 0;
5300 divider = 0;
5301 break;
5302 default:
5303 DRM_ERROR("unsupported CDCLK freq %d", cdclk);
5304
5305 return;
5306 }
5307
5308 mutex_lock(&dev_priv->rps.hw_lock);
5309 /* Inform power controller of upcoming frequency change */
5310 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5311 0x80000000);
5312 mutex_unlock(&dev_priv->rps.hw_lock);
5313
5314 if (ret) {
5315 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5316 ret, cdclk);
5317 return;
5318 }
5319
5320 current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5321 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5322 current_cdclk = current_cdclk * 500 + 1000;
5323
5324 /*
5325 * DE PLL has to be disabled when
5326 * - setting to 19.2MHz (bypass, PLL isn't used)
5327 * - before setting to 624MHz (PLL needs toggling)
5328 * - before setting to any frequency from 624MHz (PLL needs toggling)
5329 */
5330 if (cdclk == 19200 || cdclk == 624000 ||
5331 current_cdclk == 624000) {
5332 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5333 /* Timeout 200us */
5334 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5335 1))
5336 DRM_ERROR("timout waiting for DE PLL unlock\n");
5337 }
5338
5339 if (cdclk != 19200) {
5340 uint32_t val;
5341
5342 val = I915_READ(BXT_DE_PLL_CTL);
5343 val &= ~BXT_DE_PLL_RATIO_MASK;
5344 val |= ratio;
5345 I915_WRITE(BXT_DE_PLL_CTL, val);
5346
5347 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5348 /* Timeout 200us */
5349 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5350 DRM_ERROR("timeout waiting for DE PLL lock\n");
5351
5352 val = divider | skl_cdclk_decimal(cdclk);
5353 /*
5354 * FIXME if only the cd2x divider needs changing, it could be done
5355 * without shutting off the pipe (if only one pipe is active).
5356 */
5357 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5358 /*
5359 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5360 * enable otherwise.
5361 */
5362 if (cdclk >= 500000)
5363 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5364 I915_WRITE(CDCLK_CTL, val);
5365 }
5366
5367 mutex_lock(&dev_priv->rps.hw_lock);
5368 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5369 DIV_ROUND_UP(cdclk, 25000));
5370 mutex_unlock(&dev_priv->rps.hw_lock);
5371
5372 if (ret) {
5373 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5374 ret, cdclk);
5375 return;
5376 }
5377
5378 intel_update_cdclk(dev_priv->dev);
5379 }
5380
5381 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5382 {
5383 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5384 return false;
5385
5386 /* TODO: Check for a valid CDCLK rate */
5387
5388 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5389 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5390
5391 return false;
5392 }
5393
5394 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5395 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5396
5397 return false;
5398 }
5399
5400 return true;
5401 }
5402
5403 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5404 {
5405 return broxton_cdclk_is_enabled(dev_priv);
5406 }
5407
5408 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5409 {
5410 /* check if cd clock is enabled */
5411 if (broxton_cdclk_is_enabled(dev_priv)) {
5412 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5413 return;
5414 }
5415
5416 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5417
5418 /*
5419 * FIXME:
5420 * - The initial CDCLK needs to be read from VBT.
5421 * Need to make this change after VBT has changes for BXT.
5422 * - check if setting the max (or any) cdclk freq is really necessary
5423 * here, it belongs to modeset time
5424 */
5425 broxton_set_cdclk(dev_priv, 624000);
5426
5427 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5428 POSTING_READ(DBUF_CTL);
5429
5430 udelay(10);
5431
5432 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5433 DRM_ERROR("DBuf power enable timeout!\n");
5434 }
5435
5436 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5437 {
5438 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5439 POSTING_READ(DBUF_CTL);
5440
5441 udelay(10);
5442
5443 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5444 DRM_ERROR("DBuf power disable timeout!\n");
5445
5446 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5447 broxton_set_cdclk(dev_priv, 19200);
5448 }
5449
5450 static const struct skl_cdclk_entry {
5451 unsigned int freq;
5452 unsigned int vco;
5453 } skl_cdclk_frequencies[] = {
5454 { .freq = 308570, .vco = 8640 },
5455 { .freq = 337500, .vco = 8100 },
5456 { .freq = 432000, .vco = 8640 },
5457 { .freq = 450000, .vco = 8100 },
5458 { .freq = 540000, .vco = 8100 },
5459 { .freq = 617140, .vco = 8640 },
5460 { .freq = 675000, .vco = 8100 },
5461 };
5462
5463 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5464 {
5465 unsigned int i;
5466
5467 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5468 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5469
5470 if (e->freq == freq)
5471 return e->vco;
5472 }
5473
5474 return 8100;
5475 }
5476
5477 static void
5478 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5479 {
5480 int min_cdclk;
5481 u32 val;
5482
5483 /* select the minimum CDCLK before enabling DPLL 0 */
5484 if (vco == 8640)
5485 min_cdclk = 308570;
5486 else
5487 min_cdclk = 337500;
5488
5489 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5490 I915_WRITE(CDCLK_CTL, val);
5491 POSTING_READ(CDCLK_CTL);
5492
5493 /*
5494 * We always enable DPLL0 with the lowest link rate possible, but still
5495 * taking into account the VCO required to operate the eDP panel at the
5496 * desired frequency. The usual DP link rates operate with a VCO of
5497 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5498 * The modeset code is responsible for the selection of the exact link
5499 * rate later on, with the constraint of choosing a frequency that
5500 * works with required_vco.
5501 */
5502 val = I915_READ(DPLL_CTRL1);
5503
5504 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5505 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5506 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5507 if (vco == 8640)
5508 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5509 SKL_DPLL0);
5510 else
5511 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5512 SKL_DPLL0);
5513
5514 I915_WRITE(DPLL_CTRL1, val);
5515 POSTING_READ(DPLL_CTRL1);
5516
5517 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5518
5519 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5520 DRM_ERROR("DPLL0 not locked\n");
5521 }
5522
5523 static void
5524 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5525 {
5526 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5527 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5528 DRM_ERROR("Couldn't disable DPLL0\n");
5529 }
5530
5531 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5532 {
5533 int ret;
5534 u32 val;
5535
5536 /* inform PCU we want to change CDCLK */
5537 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5538 mutex_lock(&dev_priv->rps.hw_lock);
5539 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5540 mutex_unlock(&dev_priv->rps.hw_lock);
5541
5542 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5543 }
5544
5545 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5546 {
5547 unsigned int i;
5548
5549 for (i = 0; i < 15; i++) {
5550 if (skl_cdclk_pcu_ready(dev_priv))
5551 return true;
5552 udelay(10);
5553 }
5554
5555 return false;
5556 }
5557
5558 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5559 {
5560 struct drm_device *dev = dev_priv->dev;
5561 u32 freq_select, pcu_ack;
5562
5563 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk);
5564
5565 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5566 DRM_ERROR("failed to inform PCU about cdclk change\n");
5567 return;
5568 }
5569
5570 /* set CDCLK_CTL */
5571 switch (cdclk) {
5572 case 450000:
5573 case 432000:
5574 freq_select = CDCLK_FREQ_450_432;
5575 pcu_ack = 1;
5576 break;
5577 case 540000:
5578 freq_select = CDCLK_FREQ_540;
5579 pcu_ack = 2;
5580 break;
5581 case 308570:
5582 case 337500:
5583 default:
5584 freq_select = CDCLK_FREQ_337_308;
5585 pcu_ack = 0;
5586 break;
5587 case 617140:
5588 case 675000:
5589 freq_select = CDCLK_FREQ_675_617;
5590 pcu_ack = 3;
5591 break;
5592 }
5593
5594 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5595 POSTING_READ(CDCLK_CTL);
5596
5597 /* inform PCU of the change */
5598 mutex_lock(&dev_priv->rps.hw_lock);
5599 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5600 mutex_unlock(&dev_priv->rps.hw_lock);
5601
5602 intel_update_cdclk(dev);
5603 }
5604
5605 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5606 {
5607 /* disable DBUF power */
5608 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5609 POSTING_READ(DBUF_CTL);
5610
5611 udelay(10);
5612
5613 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5614 DRM_ERROR("DBuf power disable timeout\n");
5615
5616 skl_dpll0_disable(dev_priv);
5617 }
5618
5619 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5620 {
5621 unsigned int vco;
5622
5623 /* DPLL0 not enabled (happens on early BIOS versions) */
5624 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5625 /* enable DPLL0 */
5626 vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5627 skl_dpll0_enable(dev_priv, vco);
5628 }
5629
5630 /* set CDCLK to the frequency the BIOS chose */
5631 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5632
5633 /* enable DBUF power */
5634 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5635 POSTING_READ(DBUF_CTL);
5636
5637 udelay(10);
5638
5639 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5640 DRM_ERROR("DBuf power enable timeout\n");
5641 }
5642
5643 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5644 {
5645 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5646 uint32_t cdctl = I915_READ(CDCLK_CTL);
5647 int freq = dev_priv->skl_boot_cdclk;
5648
5649 /*
5650 * check if the pre-os intialized the display
5651 * There is SWF18 scratchpad register defined which is set by the
5652 * pre-os which can be used by the OS drivers to check the status
5653 */
5654 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5655 goto sanitize;
5656
5657 /* Is PLL enabled and locked ? */
5658 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5659 goto sanitize;
5660
5661 /* DPLL okay; verify the cdclock
5662 *
5663 * Noticed in some instances that the freq selection is correct but
5664 * decimal part is programmed wrong from BIOS where pre-os does not
5665 * enable display. Verify the same as well.
5666 */
5667 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5668 /* All well; nothing to sanitize */
5669 return false;
5670 sanitize:
5671 /*
5672 * As of now initialize with max cdclk till
5673 * we get dynamic cdclk support
5674 * */
5675 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5676 skl_init_cdclk(dev_priv);
5677
5678 /* we did have to sanitize */
5679 return true;
5680 }
5681
5682 /* Adjust CDclk dividers to allow high res or save power if possible */
5683 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5684 {
5685 struct drm_i915_private *dev_priv = dev->dev_private;
5686 u32 val, cmd;
5687
5688 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5689 != dev_priv->cdclk_freq);
5690
5691 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5692 cmd = 2;
5693 else if (cdclk == 266667)
5694 cmd = 1;
5695 else
5696 cmd = 0;
5697
5698 mutex_lock(&dev_priv->rps.hw_lock);
5699 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5700 val &= ~DSPFREQGUAR_MASK;
5701 val |= (cmd << DSPFREQGUAR_SHIFT);
5702 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5703 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5704 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5705 50)) {
5706 DRM_ERROR("timed out waiting for CDclk change\n");
5707 }
5708 mutex_unlock(&dev_priv->rps.hw_lock);
5709
5710 mutex_lock(&dev_priv->sb_lock);
5711
5712 if (cdclk == 400000) {
5713 u32 divider;
5714
5715 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5716
5717 /* adjust cdclk divider */
5718 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5719 val &= ~CCK_FREQUENCY_VALUES;
5720 val |= divider;
5721 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5722
5723 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5724 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5725 50))
5726 DRM_ERROR("timed out waiting for CDclk change\n");
5727 }
5728
5729 /* adjust self-refresh exit latency value */
5730 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5731 val &= ~0x7f;
5732
5733 /*
5734 * For high bandwidth configs, we set a higher latency in the bunit
5735 * so that the core display fetch happens in time to avoid underruns.
5736 */
5737 if (cdclk == 400000)
5738 val |= 4500 / 250; /* 4.5 usec */
5739 else
5740 val |= 3000 / 250; /* 3.0 usec */
5741 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5742
5743 mutex_unlock(&dev_priv->sb_lock);
5744
5745 intel_update_cdclk(dev);
5746 }
5747
5748 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5749 {
5750 struct drm_i915_private *dev_priv = dev->dev_private;
5751 u32 val, cmd;
5752
5753 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5754 != dev_priv->cdclk_freq);
5755
5756 switch (cdclk) {
5757 case 333333:
5758 case 320000:
5759 case 266667:
5760 case 200000:
5761 break;
5762 default:
5763 MISSING_CASE(cdclk);
5764 return;
5765 }
5766
5767 /*
5768 * Specs are full of misinformation, but testing on actual
5769 * hardware has shown that we just need to write the desired
5770 * CCK divider into the Punit register.
5771 */
5772 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5773
5774 mutex_lock(&dev_priv->rps.hw_lock);
5775 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5776 val &= ~DSPFREQGUAR_MASK_CHV;
5777 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5778 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5779 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5780 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5781 50)) {
5782 DRM_ERROR("timed out waiting for CDclk change\n");
5783 }
5784 mutex_unlock(&dev_priv->rps.hw_lock);
5785
5786 intel_update_cdclk(dev);
5787 }
5788
5789 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5790 int max_pixclk)
5791 {
5792 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5793 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5794
5795 /*
5796 * Really only a few cases to deal with, as only 4 CDclks are supported:
5797 * 200MHz
5798 * 267MHz
5799 * 320/333MHz (depends on HPLL freq)
5800 * 400MHz (VLV only)
5801 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5802 * of the lower bin and adjust if needed.
5803 *
5804 * We seem to get an unstable or solid color picture at 200MHz.
5805 * Not sure what's wrong. For now use 200MHz only when all pipes
5806 * are off.
5807 */
5808 if (!IS_CHERRYVIEW(dev_priv) &&
5809 max_pixclk > freq_320*limit/100)
5810 return 400000;
5811 else if (max_pixclk > 266667*limit/100)
5812 return freq_320;
5813 else if (max_pixclk > 0)
5814 return 266667;
5815 else
5816 return 200000;
5817 }
5818
5819 static int broxton_calc_cdclk(int max_pixclk)
5820 {
5821 /*
5822 * FIXME:
5823 * - set 19.2MHz bypass frequency if there are no active pipes
5824 */
5825 if (max_pixclk > 576000)
5826 return 624000;
5827 else if (max_pixclk > 384000)
5828 return 576000;
5829 else if (max_pixclk > 288000)
5830 return 384000;
5831 else if (max_pixclk > 144000)
5832 return 288000;
5833 else
5834 return 144000;
5835 }
5836
5837 /* Compute the max pixel clock for new configuration. */
5838 static int intel_mode_max_pixclk(struct drm_device *dev,
5839 struct drm_atomic_state *state)
5840 {
5841 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5842 struct drm_i915_private *dev_priv = dev->dev_private;
5843 struct drm_crtc *crtc;
5844 struct drm_crtc_state *crtc_state;
5845 unsigned max_pixclk = 0, i;
5846 enum pipe pipe;
5847
5848 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5849 sizeof(intel_state->min_pixclk));
5850
5851 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5852 int pixclk = 0;
5853
5854 if (crtc_state->enable)
5855 pixclk = crtc_state->adjusted_mode.crtc_clock;
5856
5857 intel_state->min_pixclk[i] = pixclk;
5858 }
5859
5860 for_each_pipe(dev_priv, pipe)
5861 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5862
5863 return max_pixclk;
5864 }
5865
5866 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5867 {
5868 struct drm_device *dev = state->dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 int max_pixclk = intel_mode_max_pixclk(dev, state);
5871 struct intel_atomic_state *intel_state =
5872 to_intel_atomic_state(state);
5873
5874 intel_state->cdclk = intel_state->dev_cdclk =
5875 valleyview_calc_cdclk(dev_priv, max_pixclk);
5876
5877 if (!intel_state->active_crtcs)
5878 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5879
5880 return 0;
5881 }
5882
5883 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5884 {
5885 int max_pixclk = ilk_max_pixel_rate(state);
5886 struct intel_atomic_state *intel_state =
5887 to_intel_atomic_state(state);
5888
5889 intel_state->cdclk = intel_state->dev_cdclk =
5890 broxton_calc_cdclk(max_pixclk);
5891
5892 if (!intel_state->active_crtcs)
5893 intel_state->dev_cdclk = broxton_calc_cdclk(0);
5894
5895 return 0;
5896 }
5897
5898 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5899 {
5900 unsigned int credits, default_credits;
5901
5902 if (IS_CHERRYVIEW(dev_priv))
5903 default_credits = PFI_CREDIT(12);
5904 else
5905 default_credits = PFI_CREDIT(8);
5906
5907 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5908 /* CHV suggested value is 31 or 63 */
5909 if (IS_CHERRYVIEW(dev_priv))
5910 credits = PFI_CREDIT_63;
5911 else
5912 credits = PFI_CREDIT(15);
5913 } else {
5914 credits = default_credits;
5915 }
5916
5917 /*
5918 * WA - write default credits before re-programming
5919 * FIXME: should we also set the resend bit here?
5920 */
5921 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5922 default_credits);
5923
5924 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5925 credits | PFI_CREDIT_RESEND);
5926
5927 /*
5928 * FIXME is this guaranteed to clear
5929 * immediately or should we poll for it?
5930 */
5931 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5932 }
5933
5934 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5935 {
5936 struct drm_device *dev = old_state->dev;
5937 struct drm_i915_private *dev_priv = dev->dev_private;
5938 struct intel_atomic_state *old_intel_state =
5939 to_intel_atomic_state(old_state);
5940 unsigned req_cdclk = old_intel_state->dev_cdclk;
5941
5942 /*
5943 * FIXME: We can end up here with all power domains off, yet
5944 * with a CDCLK frequency other than the minimum. To account
5945 * for this take the PIPE-A power domain, which covers the HW
5946 * blocks needed for the following programming. This can be
5947 * removed once it's guaranteed that we get here either with
5948 * the minimum CDCLK set, or the required power domains
5949 * enabled.
5950 */
5951 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5952
5953 if (IS_CHERRYVIEW(dev))
5954 cherryview_set_cdclk(dev, req_cdclk);
5955 else
5956 valleyview_set_cdclk(dev, req_cdclk);
5957
5958 vlv_program_pfi_credits(dev_priv);
5959
5960 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5961 }
5962
5963 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5964 {
5965 struct drm_device *dev = crtc->dev;
5966 struct drm_i915_private *dev_priv = to_i915(dev);
5967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5968 struct intel_encoder *encoder;
5969 struct intel_crtc_state *pipe_config =
5970 to_intel_crtc_state(crtc->state);
5971 int pipe = intel_crtc->pipe;
5972
5973 if (WARN_ON(intel_crtc->active))
5974 return;
5975
5976 if (intel_crtc->config->has_dp_encoder)
5977 intel_dp_set_m_n(intel_crtc, M1_N1);
5978
5979 intel_set_pipe_timings(intel_crtc);
5980 intel_set_pipe_src_size(intel_crtc);
5981
5982 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5983 struct drm_i915_private *dev_priv = dev->dev_private;
5984
5985 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5986 I915_WRITE(CHV_CANVAS(pipe), 0);
5987 }
5988
5989 i9xx_set_pipeconf(intel_crtc);
5990
5991 intel_crtc->active = true;
5992
5993 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5994
5995 for_each_encoder_on_crtc(dev, crtc, encoder)
5996 if (encoder->pre_pll_enable)
5997 encoder->pre_pll_enable(encoder);
5998
5999 if (IS_CHERRYVIEW(dev)) {
6000 chv_prepare_pll(intel_crtc, intel_crtc->config);
6001 chv_enable_pll(intel_crtc, intel_crtc->config);
6002 } else {
6003 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6004 vlv_enable_pll(intel_crtc, intel_crtc->config);
6005 }
6006
6007 for_each_encoder_on_crtc(dev, crtc, encoder)
6008 if (encoder->pre_enable)
6009 encoder->pre_enable(encoder);
6010
6011 i9xx_pfit_enable(intel_crtc);
6012
6013 intel_color_load_luts(&pipe_config->base);
6014
6015 intel_update_watermarks(crtc);
6016 intel_enable_pipe(intel_crtc);
6017
6018 assert_vblank_disabled(crtc);
6019 drm_crtc_vblank_on(crtc);
6020
6021 for_each_encoder_on_crtc(dev, crtc, encoder)
6022 encoder->enable(encoder);
6023 }
6024
6025 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6026 {
6027 struct drm_device *dev = crtc->base.dev;
6028 struct drm_i915_private *dev_priv = dev->dev_private;
6029
6030 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6031 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6032 }
6033
6034 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6035 {
6036 struct drm_device *dev = crtc->dev;
6037 struct drm_i915_private *dev_priv = to_i915(dev);
6038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6039 struct intel_encoder *encoder;
6040 struct intel_crtc_state *pipe_config =
6041 to_intel_crtc_state(crtc->state);
6042 enum pipe pipe = intel_crtc->pipe;
6043
6044 if (WARN_ON(intel_crtc->active))
6045 return;
6046
6047 i9xx_set_pll_dividers(intel_crtc);
6048
6049 if (intel_crtc->config->has_dp_encoder)
6050 intel_dp_set_m_n(intel_crtc, M1_N1);
6051
6052 intel_set_pipe_timings(intel_crtc);
6053 intel_set_pipe_src_size(intel_crtc);
6054
6055 i9xx_set_pipeconf(intel_crtc);
6056
6057 intel_crtc->active = true;
6058
6059 if (!IS_GEN2(dev))
6060 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6061
6062 for_each_encoder_on_crtc(dev, crtc, encoder)
6063 if (encoder->pre_enable)
6064 encoder->pre_enable(encoder);
6065
6066 i9xx_enable_pll(intel_crtc);
6067
6068 i9xx_pfit_enable(intel_crtc);
6069
6070 intel_color_load_luts(&pipe_config->base);
6071
6072 intel_update_watermarks(crtc);
6073 intel_enable_pipe(intel_crtc);
6074
6075 assert_vblank_disabled(crtc);
6076 drm_crtc_vblank_on(crtc);
6077
6078 for_each_encoder_on_crtc(dev, crtc, encoder)
6079 encoder->enable(encoder);
6080 }
6081
6082 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6083 {
6084 struct drm_device *dev = crtc->base.dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086
6087 if (!crtc->config->gmch_pfit.control)
6088 return;
6089
6090 assert_pipe_disabled(dev_priv, crtc->pipe);
6091
6092 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6093 I915_READ(PFIT_CONTROL));
6094 I915_WRITE(PFIT_CONTROL, 0);
6095 }
6096
6097 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6098 {
6099 struct drm_device *dev = crtc->dev;
6100 struct drm_i915_private *dev_priv = dev->dev_private;
6101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102 struct intel_encoder *encoder;
6103 int pipe = intel_crtc->pipe;
6104
6105 /*
6106 * On gen2 planes are double buffered but the pipe isn't, so we must
6107 * wait for planes to fully turn off before disabling the pipe.
6108 */
6109 if (IS_GEN2(dev))
6110 intel_wait_for_vblank(dev, pipe);
6111
6112 for_each_encoder_on_crtc(dev, crtc, encoder)
6113 encoder->disable(encoder);
6114
6115 drm_crtc_vblank_off(crtc);
6116 assert_vblank_disabled(crtc);
6117
6118 intel_disable_pipe(intel_crtc);
6119
6120 i9xx_pfit_disable(intel_crtc);
6121
6122 for_each_encoder_on_crtc(dev, crtc, encoder)
6123 if (encoder->post_disable)
6124 encoder->post_disable(encoder);
6125
6126 if (!intel_crtc->config->has_dsi_encoder) {
6127 if (IS_CHERRYVIEW(dev))
6128 chv_disable_pll(dev_priv, pipe);
6129 else if (IS_VALLEYVIEW(dev))
6130 vlv_disable_pll(dev_priv, pipe);
6131 else
6132 i9xx_disable_pll(intel_crtc);
6133 }
6134
6135 for_each_encoder_on_crtc(dev, crtc, encoder)
6136 if (encoder->post_pll_disable)
6137 encoder->post_pll_disable(encoder);
6138
6139 if (!IS_GEN2(dev))
6140 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6141 }
6142
6143 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6144 {
6145 struct intel_encoder *encoder;
6146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6147 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6148 enum intel_display_power_domain domain;
6149 unsigned long domains;
6150
6151 if (!intel_crtc->active)
6152 return;
6153
6154 if (to_intel_plane_state(crtc->primary->state)->visible) {
6155 WARN_ON(list_empty(&intel_crtc->flip_work));
6156
6157 intel_pre_disable_primary_noatomic(crtc);
6158
6159 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6160 to_intel_plane_state(crtc->primary->state)->visible = false;
6161 }
6162
6163 dev_priv->display.crtc_disable(crtc);
6164
6165 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6166 crtc->base.id);
6167
6168 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6169 crtc->state->active = false;
6170 intel_crtc->active = false;
6171 crtc->enabled = false;
6172 crtc->state->connector_mask = 0;
6173 crtc->state->encoder_mask = 0;
6174
6175 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6176 encoder->base.crtc = NULL;
6177
6178 intel_fbc_disable(intel_crtc);
6179 intel_update_watermarks(crtc);
6180 intel_disable_shared_dpll(intel_crtc);
6181
6182 domains = intel_crtc->enabled_power_domains;
6183 for_each_power_domain(domain, domains)
6184 intel_display_power_put(dev_priv, domain);
6185 intel_crtc->enabled_power_domains = 0;
6186
6187 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6188 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6189 }
6190
6191 /*
6192 * turn all crtc's off, but do not adjust state
6193 * This has to be paired with a call to intel_modeset_setup_hw_state.
6194 */
6195 int intel_display_suspend(struct drm_device *dev)
6196 {
6197 struct drm_i915_private *dev_priv = to_i915(dev);
6198 struct drm_atomic_state *state;
6199 int ret;
6200
6201 state = drm_atomic_helper_suspend(dev);
6202 ret = PTR_ERR_OR_ZERO(state);
6203 if (ret)
6204 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6205 else
6206 dev_priv->modeset_restore_state = state;
6207
6208 /*
6209 * Make sure all unpin_work completes before returning.
6210 */
6211 flush_workqueue(dev_priv->wq);
6212
6213 return ret;
6214 }
6215
6216 void intel_encoder_destroy(struct drm_encoder *encoder)
6217 {
6218 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6219
6220 drm_encoder_cleanup(encoder);
6221 kfree(intel_encoder);
6222 }
6223
6224 /* Cross check the actual hw state with our own modeset state tracking (and it's
6225 * internal consistency). */
6226 static void intel_connector_verify_state(struct intel_connector *connector,
6227 struct drm_connector_state *conn_state)
6228 {
6229 struct drm_crtc *crtc = conn_state->crtc;
6230
6231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6232 connector->base.base.id,
6233 connector->base.name);
6234
6235 if (connector->get_hw_state(connector)) {
6236 struct intel_encoder *encoder = connector->encoder;
6237
6238 I915_STATE_WARN(!crtc,
6239 "connector enabled without attached crtc\n");
6240
6241 if (!crtc)
6242 return;
6243
6244 I915_STATE_WARN(!crtc->state->active,
6245 "connector is active, but attached crtc isn't\n");
6246
6247 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6248 return;
6249
6250 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6251 "atomic encoder doesn't match attached encoder\n");
6252
6253 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6254 "attached encoder crtc differs from connector crtc\n");
6255 } else {
6256 I915_STATE_WARN(crtc && crtc->state->active,
6257 "attached crtc is active, but connector isn't\n");
6258 I915_STATE_WARN(!crtc && conn_state->best_encoder,
6259 "best encoder set without crtc!\n");
6260 }
6261 }
6262
6263 int intel_connector_init(struct intel_connector *connector)
6264 {
6265 drm_atomic_helper_connector_reset(&connector->base);
6266
6267 if (!connector->base.state)
6268 return -ENOMEM;
6269
6270 return 0;
6271 }
6272
6273 struct intel_connector *intel_connector_alloc(void)
6274 {
6275 struct intel_connector *connector;
6276
6277 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6278 if (!connector)
6279 return NULL;
6280
6281 if (intel_connector_init(connector) < 0) {
6282 kfree(connector);
6283 return NULL;
6284 }
6285
6286 return connector;
6287 }
6288
6289 /* Simple connector->get_hw_state implementation for encoders that support only
6290 * one connector and no cloning and hence the encoder state determines the state
6291 * of the connector. */
6292 bool intel_connector_get_hw_state(struct intel_connector *connector)
6293 {
6294 enum pipe pipe = 0;
6295 struct intel_encoder *encoder = connector->encoder;
6296
6297 return encoder->get_hw_state(encoder, &pipe);
6298 }
6299
6300 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6301 {
6302 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6303 return crtc_state->fdi_lanes;
6304
6305 return 0;
6306 }
6307
6308 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6309 struct intel_crtc_state *pipe_config)
6310 {
6311 struct drm_atomic_state *state = pipe_config->base.state;
6312 struct intel_crtc *other_crtc;
6313 struct intel_crtc_state *other_crtc_state;
6314
6315 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6316 pipe_name(pipe), pipe_config->fdi_lanes);
6317 if (pipe_config->fdi_lanes > 4) {
6318 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6319 pipe_name(pipe), pipe_config->fdi_lanes);
6320 return -EINVAL;
6321 }
6322
6323 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6324 if (pipe_config->fdi_lanes > 2) {
6325 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6326 pipe_config->fdi_lanes);
6327 return -EINVAL;
6328 } else {
6329 return 0;
6330 }
6331 }
6332
6333 if (INTEL_INFO(dev)->num_pipes == 2)
6334 return 0;
6335
6336 /* Ivybridge 3 pipe is really complicated */
6337 switch (pipe) {
6338 case PIPE_A:
6339 return 0;
6340 case PIPE_B:
6341 if (pipe_config->fdi_lanes <= 2)
6342 return 0;
6343
6344 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6345 other_crtc_state =
6346 intel_atomic_get_crtc_state(state, other_crtc);
6347 if (IS_ERR(other_crtc_state))
6348 return PTR_ERR(other_crtc_state);
6349
6350 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6351 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6352 pipe_name(pipe), pipe_config->fdi_lanes);
6353 return -EINVAL;
6354 }
6355 return 0;
6356 case PIPE_C:
6357 if (pipe_config->fdi_lanes > 2) {
6358 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6359 pipe_name(pipe), pipe_config->fdi_lanes);
6360 return -EINVAL;
6361 }
6362
6363 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6364 other_crtc_state =
6365 intel_atomic_get_crtc_state(state, other_crtc);
6366 if (IS_ERR(other_crtc_state))
6367 return PTR_ERR(other_crtc_state);
6368
6369 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6370 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6371 return -EINVAL;
6372 }
6373 return 0;
6374 default:
6375 BUG();
6376 }
6377 }
6378
6379 #define RETRY 1
6380 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6381 struct intel_crtc_state *pipe_config)
6382 {
6383 struct drm_device *dev = intel_crtc->base.dev;
6384 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6385 int lane, link_bw, fdi_dotclock, ret;
6386 bool needs_recompute = false;
6387
6388 retry:
6389 /* FDI is a binary signal running at ~2.7GHz, encoding
6390 * each output octet as 10 bits. The actual frequency
6391 * is stored as a divider into a 100MHz clock, and the
6392 * mode pixel clock is stored in units of 1KHz.
6393 * Hence the bw of each lane in terms of the mode signal
6394 * is:
6395 */
6396 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6397
6398 fdi_dotclock = adjusted_mode->crtc_clock;
6399
6400 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6401 pipe_config->pipe_bpp);
6402
6403 pipe_config->fdi_lanes = lane;
6404
6405 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6406 link_bw, &pipe_config->fdi_m_n);
6407
6408 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6409 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6410 pipe_config->pipe_bpp -= 2*3;
6411 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6412 pipe_config->pipe_bpp);
6413 needs_recompute = true;
6414 pipe_config->bw_constrained = true;
6415
6416 goto retry;
6417 }
6418
6419 if (needs_recompute)
6420 return RETRY;
6421
6422 return ret;
6423 }
6424
6425 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6426 struct intel_crtc_state *pipe_config)
6427 {
6428 if (pipe_config->pipe_bpp > 24)
6429 return false;
6430
6431 /* HSW can handle pixel rate up to cdclk? */
6432 if (IS_HASWELL(dev_priv))
6433 return true;
6434
6435 /*
6436 * We compare against max which means we must take
6437 * the increased cdclk requirement into account when
6438 * calculating the new cdclk.
6439 *
6440 * Should measure whether using a lower cdclk w/o IPS
6441 */
6442 return ilk_pipe_pixel_rate(pipe_config) <=
6443 dev_priv->max_cdclk_freq * 95 / 100;
6444 }
6445
6446 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6447 struct intel_crtc_state *pipe_config)
6448 {
6449 struct drm_device *dev = crtc->base.dev;
6450 struct drm_i915_private *dev_priv = dev->dev_private;
6451
6452 pipe_config->ips_enabled = i915.enable_ips &&
6453 hsw_crtc_supports_ips(crtc) &&
6454 pipe_config_supports_ips(dev_priv, pipe_config);
6455 }
6456
6457 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6458 {
6459 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6460
6461 /* GDG double wide on either pipe, otherwise pipe A only */
6462 return INTEL_INFO(dev_priv)->gen < 4 &&
6463 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6464 }
6465
6466 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6467 struct intel_crtc_state *pipe_config)
6468 {
6469 struct drm_device *dev = crtc->base.dev;
6470 struct drm_i915_private *dev_priv = dev->dev_private;
6471 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6472
6473 /* FIXME should check pixel clock limits on all platforms */
6474 if (INTEL_INFO(dev)->gen < 4) {
6475 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6476
6477 /*
6478 * Enable double wide mode when the dot clock
6479 * is > 90% of the (display) core speed.
6480 */
6481 if (intel_crtc_supports_double_wide(crtc) &&
6482 adjusted_mode->crtc_clock > clock_limit) {
6483 clock_limit *= 2;
6484 pipe_config->double_wide = true;
6485 }
6486
6487 if (adjusted_mode->crtc_clock > clock_limit) {
6488 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6489 adjusted_mode->crtc_clock, clock_limit,
6490 yesno(pipe_config->double_wide));
6491 return -EINVAL;
6492 }
6493 }
6494
6495 /*
6496 * Pipe horizontal size must be even in:
6497 * - DVO ganged mode
6498 * - LVDS dual channel mode
6499 * - Double wide pipe
6500 */
6501 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6502 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6503 pipe_config->pipe_src_w &= ~1;
6504
6505 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6506 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6507 */
6508 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6509 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6510 return -EINVAL;
6511
6512 if (HAS_IPS(dev))
6513 hsw_compute_ips_config(crtc, pipe_config);
6514
6515 if (pipe_config->has_pch_encoder)
6516 return ironlake_fdi_compute_config(crtc, pipe_config);
6517
6518 return 0;
6519 }
6520
6521 static int skylake_get_display_clock_speed(struct drm_device *dev)
6522 {
6523 struct drm_i915_private *dev_priv = to_i915(dev);
6524 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6525 uint32_t cdctl = I915_READ(CDCLK_CTL);
6526 uint32_t linkrate;
6527
6528 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6529 return 24000; /* 24MHz is the cd freq with NSSC ref */
6530
6531 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6532 return 540000;
6533
6534 linkrate = (I915_READ(DPLL_CTRL1) &
6535 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6536
6537 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6538 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6539 /* vco 8640 */
6540 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6541 case CDCLK_FREQ_450_432:
6542 return 432000;
6543 case CDCLK_FREQ_337_308:
6544 return 308570;
6545 case CDCLK_FREQ_675_617:
6546 return 617140;
6547 default:
6548 WARN(1, "Unknown cd freq selection\n");
6549 }
6550 } else {
6551 /* vco 8100 */
6552 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6553 case CDCLK_FREQ_450_432:
6554 return 450000;
6555 case CDCLK_FREQ_337_308:
6556 return 337500;
6557 case CDCLK_FREQ_675_617:
6558 return 675000;
6559 default:
6560 WARN(1, "Unknown cd freq selection\n");
6561 }
6562 }
6563
6564 /* error case, do as if DPLL0 isn't enabled */
6565 return 24000;
6566 }
6567
6568 static int broxton_get_display_clock_speed(struct drm_device *dev)
6569 {
6570 struct drm_i915_private *dev_priv = to_i915(dev);
6571 uint32_t cdctl = I915_READ(CDCLK_CTL);
6572 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6573 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6574 int cdclk;
6575
6576 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6577 return 19200;
6578
6579 cdclk = 19200 * pll_ratio / 2;
6580
6581 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6582 case BXT_CDCLK_CD2X_DIV_SEL_1:
6583 return cdclk; /* 576MHz or 624MHz */
6584 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6585 return cdclk * 2 / 3; /* 384MHz */
6586 case BXT_CDCLK_CD2X_DIV_SEL_2:
6587 return cdclk / 2; /* 288MHz */
6588 case BXT_CDCLK_CD2X_DIV_SEL_4:
6589 return cdclk / 4; /* 144MHz */
6590 }
6591
6592 /* error case, do as if DE PLL isn't enabled */
6593 return 19200;
6594 }
6595
6596 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6597 {
6598 struct drm_i915_private *dev_priv = dev->dev_private;
6599 uint32_t lcpll = I915_READ(LCPLL_CTL);
6600 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6601
6602 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6603 return 800000;
6604 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6605 return 450000;
6606 else if (freq == LCPLL_CLK_FREQ_450)
6607 return 450000;
6608 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6609 return 540000;
6610 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6611 return 337500;
6612 else
6613 return 675000;
6614 }
6615
6616 static int haswell_get_display_clock_speed(struct drm_device *dev)
6617 {
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619 uint32_t lcpll = I915_READ(LCPLL_CTL);
6620 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6621
6622 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6623 return 800000;
6624 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6625 return 450000;
6626 else if (freq == LCPLL_CLK_FREQ_450)
6627 return 450000;
6628 else if (IS_HSW_ULT(dev))
6629 return 337500;
6630 else
6631 return 540000;
6632 }
6633
6634 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6635 {
6636 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6637 CCK_DISPLAY_CLOCK_CONTROL);
6638 }
6639
6640 static int ilk_get_display_clock_speed(struct drm_device *dev)
6641 {
6642 return 450000;
6643 }
6644
6645 static int i945_get_display_clock_speed(struct drm_device *dev)
6646 {
6647 return 400000;
6648 }
6649
6650 static int i915_get_display_clock_speed(struct drm_device *dev)
6651 {
6652 return 333333;
6653 }
6654
6655 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6656 {
6657 return 200000;
6658 }
6659
6660 static int pnv_get_display_clock_speed(struct drm_device *dev)
6661 {
6662 u16 gcfgc = 0;
6663
6664 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6665
6666 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6667 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6668 return 266667;
6669 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6670 return 333333;
6671 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6672 return 444444;
6673 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6674 return 200000;
6675 default:
6676 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6677 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6678 return 133333;
6679 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6680 return 166667;
6681 }
6682 }
6683
6684 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6685 {
6686 u16 gcfgc = 0;
6687
6688 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6689
6690 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6691 return 133333;
6692 else {
6693 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6694 case GC_DISPLAY_CLOCK_333_MHZ:
6695 return 333333;
6696 default:
6697 case GC_DISPLAY_CLOCK_190_200_MHZ:
6698 return 190000;
6699 }
6700 }
6701 }
6702
6703 static int i865_get_display_clock_speed(struct drm_device *dev)
6704 {
6705 return 266667;
6706 }
6707
6708 static int i85x_get_display_clock_speed(struct drm_device *dev)
6709 {
6710 u16 hpllcc = 0;
6711
6712 /*
6713 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6714 * encoding is different :(
6715 * FIXME is this the right way to detect 852GM/852GMV?
6716 */
6717 if (dev->pdev->revision == 0x1)
6718 return 133333;
6719
6720 pci_bus_read_config_word(dev->pdev->bus,
6721 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6722
6723 /* Assume that the hardware is in the high speed state. This
6724 * should be the default.
6725 */
6726 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6727 case GC_CLOCK_133_200:
6728 case GC_CLOCK_133_200_2:
6729 case GC_CLOCK_100_200:
6730 return 200000;
6731 case GC_CLOCK_166_250:
6732 return 250000;
6733 case GC_CLOCK_100_133:
6734 return 133333;
6735 case GC_CLOCK_133_266:
6736 case GC_CLOCK_133_266_2:
6737 case GC_CLOCK_166_266:
6738 return 266667;
6739 }
6740
6741 /* Shouldn't happen */
6742 return 0;
6743 }
6744
6745 static int i830_get_display_clock_speed(struct drm_device *dev)
6746 {
6747 return 133333;
6748 }
6749
6750 static unsigned int intel_hpll_vco(struct drm_device *dev)
6751 {
6752 struct drm_i915_private *dev_priv = dev->dev_private;
6753 static const unsigned int blb_vco[8] = {
6754 [0] = 3200000,
6755 [1] = 4000000,
6756 [2] = 5333333,
6757 [3] = 4800000,
6758 [4] = 6400000,
6759 };
6760 static const unsigned int pnv_vco[8] = {
6761 [0] = 3200000,
6762 [1] = 4000000,
6763 [2] = 5333333,
6764 [3] = 4800000,
6765 [4] = 2666667,
6766 };
6767 static const unsigned int cl_vco[8] = {
6768 [0] = 3200000,
6769 [1] = 4000000,
6770 [2] = 5333333,
6771 [3] = 6400000,
6772 [4] = 3333333,
6773 [5] = 3566667,
6774 [6] = 4266667,
6775 };
6776 static const unsigned int elk_vco[8] = {
6777 [0] = 3200000,
6778 [1] = 4000000,
6779 [2] = 5333333,
6780 [3] = 4800000,
6781 };
6782 static const unsigned int ctg_vco[8] = {
6783 [0] = 3200000,
6784 [1] = 4000000,
6785 [2] = 5333333,
6786 [3] = 6400000,
6787 [4] = 2666667,
6788 [5] = 4266667,
6789 };
6790 const unsigned int *vco_table;
6791 unsigned int vco;
6792 uint8_t tmp = 0;
6793
6794 /* FIXME other chipsets? */
6795 if (IS_GM45(dev))
6796 vco_table = ctg_vco;
6797 else if (IS_G4X(dev))
6798 vco_table = elk_vco;
6799 else if (IS_CRESTLINE(dev))
6800 vco_table = cl_vco;
6801 else if (IS_PINEVIEW(dev))
6802 vco_table = pnv_vco;
6803 else if (IS_G33(dev))
6804 vco_table = blb_vco;
6805 else
6806 return 0;
6807
6808 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6809
6810 vco = vco_table[tmp & 0x7];
6811 if (vco == 0)
6812 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6813 else
6814 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6815
6816 return vco;
6817 }
6818
6819 static int gm45_get_display_clock_speed(struct drm_device *dev)
6820 {
6821 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6822 uint16_t tmp = 0;
6823
6824 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6825
6826 cdclk_sel = (tmp >> 12) & 0x1;
6827
6828 switch (vco) {
6829 case 2666667:
6830 case 4000000:
6831 case 5333333:
6832 return cdclk_sel ? 333333 : 222222;
6833 case 3200000:
6834 return cdclk_sel ? 320000 : 228571;
6835 default:
6836 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6837 return 222222;
6838 }
6839 }
6840
6841 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6842 {
6843 static const uint8_t div_3200[] = { 16, 10, 8 };
6844 static const uint8_t div_4000[] = { 20, 12, 10 };
6845 static const uint8_t div_5333[] = { 24, 16, 14 };
6846 const uint8_t *div_table;
6847 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6848 uint16_t tmp = 0;
6849
6850 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6851
6852 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6853
6854 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6855 goto fail;
6856
6857 switch (vco) {
6858 case 3200000:
6859 div_table = div_3200;
6860 break;
6861 case 4000000:
6862 div_table = div_4000;
6863 break;
6864 case 5333333:
6865 div_table = div_5333;
6866 break;
6867 default:
6868 goto fail;
6869 }
6870
6871 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6872
6873 fail:
6874 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6875 return 200000;
6876 }
6877
6878 static int g33_get_display_clock_speed(struct drm_device *dev)
6879 {
6880 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6881 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6882 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6883 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6884 const uint8_t *div_table;
6885 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6886 uint16_t tmp = 0;
6887
6888 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6889
6890 cdclk_sel = (tmp >> 4) & 0x7;
6891
6892 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6893 goto fail;
6894
6895 switch (vco) {
6896 case 3200000:
6897 div_table = div_3200;
6898 break;
6899 case 4000000:
6900 div_table = div_4000;
6901 break;
6902 case 4800000:
6903 div_table = div_4800;
6904 break;
6905 case 5333333:
6906 div_table = div_5333;
6907 break;
6908 default:
6909 goto fail;
6910 }
6911
6912 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6913
6914 fail:
6915 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6916 return 190476;
6917 }
6918
6919 static void
6920 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6921 {
6922 while (*num > DATA_LINK_M_N_MASK ||
6923 *den > DATA_LINK_M_N_MASK) {
6924 *num >>= 1;
6925 *den >>= 1;
6926 }
6927 }
6928
6929 static void compute_m_n(unsigned int m, unsigned int n,
6930 uint32_t *ret_m, uint32_t *ret_n)
6931 {
6932 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6933 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6934 intel_reduce_m_n_ratio(ret_m, ret_n);
6935 }
6936
6937 void
6938 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6939 int pixel_clock, int link_clock,
6940 struct intel_link_m_n *m_n)
6941 {
6942 m_n->tu = 64;
6943
6944 compute_m_n(bits_per_pixel * pixel_clock,
6945 link_clock * nlanes * 8,
6946 &m_n->gmch_m, &m_n->gmch_n);
6947
6948 compute_m_n(pixel_clock, link_clock,
6949 &m_n->link_m, &m_n->link_n);
6950 }
6951
6952 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6953 {
6954 if (i915.panel_use_ssc >= 0)
6955 return i915.panel_use_ssc != 0;
6956 return dev_priv->vbt.lvds_use_ssc
6957 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6958 }
6959
6960 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6961 {
6962 return (1 << dpll->n) << 16 | dpll->m2;
6963 }
6964
6965 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6966 {
6967 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6968 }
6969
6970 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6971 struct intel_crtc_state *crtc_state,
6972 struct dpll *reduced_clock)
6973 {
6974 struct drm_device *dev = crtc->base.dev;
6975 u32 fp, fp2 = 0;
6976
6977 if (IS_PINEVIEW(dev)) {
6978 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6979 if (reduced_clock)
6980 fp2 = pnv_dpll_compute_fp(reduced_clock);
6981 } else {
6982 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6983 if (reduced_clock)
6984 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6985 }
6986
6987 crtc_state->dpll_hw_state.fp0 = fp;
6988
6989 crtc->lowfreq_avail = false;
6990 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6991 reduced_clock) {
6992 crtc_state->dpll_hw_state.fp1 = fp2;
6993 crtc->lowfreq_avail = true;
6994 } else {
6995 crtc_state->dpll_hw_state.fp1 = fp;
6996 }
6997 }
6998
6999 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7000 pipe)
7001 {
7002 u32 reg_val;
7003
7004 /*
7005 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7006 * and set it to a reasonable value instead.
7007 */
7008 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7009 reg_val &= 0xffffff00;
7010 reg_val |= 0x00000030;
7011 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7012
7013 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7014 reg_val &= 0x8cffffff;
7015 reg_val = 0x8c000000;
7016 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7017
7018 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7019 reg_val &= 0xffffff00;
7020 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7021
7022 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7023 reg_val &= 0x00ffffff;
7024 reg_val |= 0xb0000000;
7025 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7026 }
7027
7028 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7029 struct intel_link_m_n *m_n)
7030 {
7031 struct drm_device *dev = crtc->base.dev;
7032 struct drm_i915_private *dev_priv = dev->dev_private;
7033 int pipe = crtc->pipe;
7034
7035 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7036 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7037 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7038 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7039 }
7040
7041 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7042 struct intel_link_m_n *m_n,
7043 struct intel_link_m_n *m2_n2)
7044 {
7045 struct drm_device *dev = crtc->base.dev;
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 int pipe = crtc->pipe;
7048 enum transcoder transcoder = crtc->config->cpu_transcoder;
7049
7050 if (INTEL_INFO(dev)->gen >= 5) {
7051 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7052 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7053 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7054 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7055 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7056 * for gen < 8) and if DRRS is supported (to make sure the
7057 * registers are not unnecessarily accessed).
7058 */
7059 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7060 crtc->config->has_drrs) {
7061 I915_WRITE(PIPE_DATA_M2(transcoder),
7062 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7063 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7064 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7065 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7066 }
7067 } else {
7068 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7069 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7070 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7071 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7072 }
7073 }
7074
7075 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7076 {
7077 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7078
7079 if (m_n == M1_N1) {
7080 dp_m_n = &crtc->config->dp_m_n;
7081 dp_m2_n2 = &crtc->config->dp_m2_n2;
7082 } else if (m_n == M2_N2) {
7083
7084 /*
7085 * M2_N2 registers are not supported. Hence m2_n2 divider value
7086 * needs to be programmed into M1_N1.
7087 */
7088 dp_m_n = &crtc->config->dp_m2_n2;
7089 } else {
7090 DRM_ERROR("Unsupported divider value\n");
7091 return;
7092 }
7093
7094 if (crtc->config->has_pch_encoder)
7095 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7096 else
7097 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7098 }
7099
7100 static void vlv_compute_dpll(struct intel_crtc *crtc,
7101 struct intel_crtc_state *pipe_config)
7102 {
7103 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7104 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7105 if (crtc->pipe != PIPE_A)
7106 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7107
7108 /* DPLL not used with DSI, but still need the rest set up */
7109 if (!pipe_config->has_dsi_encoder)
7110 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7111 DPLL_EXT_BUFFER_ENABLE_VLV;
7112
7113 pipe_config->dpll_hw_state.dpll_md =
7114 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7115 }
7116
7117 static void chv_compute_dpll(struct intel_crtc *crtc,
7118 struct intel_crtc_state *pipe_config)
7119 {
7120 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7121 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7122 if (crtc->pipe != PIPE_A)
7123 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7124
7125 /* DPLL not used with DSI, but still need the rest set up */
7126 if (!pipe_config->has_dsi_encoder)
7127 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7128
7129 pipe_config->dpll_hw_state.dpll_md =
7130 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7131 }
7132
7133 static void vlv_prepare_pll(struct intel_crtc *crtc,
7134 const struct intel_crtc_state *pipe_config)
7135 {
7136 struct drm_device *dev = crtc->base.dev;
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 enum pipe pipe = crtc->pipe;
7139 u32 mdiv;
7140 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7141 u32 coreclk, reg_val;
7142
7143 /* Enable Refclk */
7144 I915_WRITE(DPLL(pipe),
7145 pipe_config->dpll_hw_state.dpll &
7146 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7147
7148 /* No need to actually set up the DPLL with DSI */
7149 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7150 return;
7151
7152 mutex_lock(&dev_priv->sb_lock);
7153
7154 bestn = pipe_config->dpll.n;
7155 bestm1 = pipe_config->dpll.m1;
7156 bestm2 = pipe_config->dpll.m2;
7157 bestp1 = pipe_config->dpll.p1;
7158 bestp2 = pipe_config->dpll.p2;
7159
7160 /* See eDP HDMI DPIO driver vbios notes doc */
7161
7162 /* PLL B needs special handling */
7163 if (pipe == PIPE_B)
7164 vlv_pllb_recal_opamp(dev_priv, pipe);
7165
7166 /* Set up Tx target for periodic Rcomp update */
7167 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7168
7169 /* Disable target IRef on PLL */
7170 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7171 reg_val &= 0x00ffffff;
7172 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7173
7174 /* Disable fast lock */
7175 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7176
7177 /* Set idtafcrecal before PLL is enabled */
7178 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7179 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7180 mdiv |= ((bestn << DPIO_N_SHIFT));
7181 mdiv |= (1 << DPIO_K_SHIFT);
7182
7183 /*
7184 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7185 * but we don't support that).
7186 * Note: don't use the DAC post divider as it seems unstable.
7187 */
7188 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7189 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7190
7191 mdiv |= DPIO_ENABLE_CALIBRATION;
7192 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7193
7194 /* Set HBR and RBR LPF coefficients */
7195 if (pipe_config->port_clock == 162000 ||
7196 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7197 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7198 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7199 0x009f0003);
7200 else
7201 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7202 0x00d0000f);
7203
7204 if (pipe_config->has_dp_encoder) {
7205 /* Use SSC source */
7206 if (pipe == PIPE_A)
7207 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7208 0x0df40000);
7209 else
7210 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7211 0x0df70000);
7212 } else { /* HDMI or VGA */
7213 /* Use bend source */
7214 if (pipe == PIPE_A)
7215 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7216 0x0df70000);
7217 else
7218 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7219 0x0df40000);
7220 }
7221
7222 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7223 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7224 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7225 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7226 coreclk |= 0x01000000;
7227 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7228
7229 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7230 mutex_unlock(&dev_priv->sb_lock);
7231 }
7232
7233 static void chv_prepare_pll(struct intel_crtc *crtc,
7234 const struct intel_crtc_state *pipe_config)
7235 {
7236 struct drm_device *dev = crtc->base.dev;
7237 struct drm_i915_private *dev_priv = dev->dev_private;
7238 enum pipe pipe = crtc->pipe;
7239 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7240 u32 loopfilter, tribuf_calcntr;
7241 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7242 u32 dpio_val;
7243 int vco;
7244
7245 /* Enable Refclk and SSC */
7246 I915_WRITE(DPLL(pipe),
7247 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7248
7249 /* No need to actually set up the DPLL with DSI */
7250 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7251 return;
7252
7253 bestn = pipe_config->dpll.n;
7254 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7255 bestm1 = pipe_config->dpll.m1;
7256 bestm2 = pipe_config->dpll.m2 >> 22;
7257 bestp1 = pipe_config->dpll.p1;
7258 bestp2 = pipe_config->dpll.p2;
7259 vco = pipe_config->dpll.vco;
7260 dpio_val = 0;
7261 loopfilter = 0;
7262
7263 mutex_lock(&dev_priv->sb_lock);
7264
7265 /* p1 and p2 divider */
7266 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7267 5 << DPIO_CHV_S1_DIV_SHIFT |
7268 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7269 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7270 1 << DPIO_CHV_K_DIV_SHIFT);
7271
7272 /* Feedback post-divider - m2 */
7273 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7274
7275 /* Feedback refclk divider - n and m1 */
7276 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7277 DPIO_CHV_M1_DIV_BY_2 |
7278 1 << DPIO_CHV_N_DIV_SHIFT);
7279
7280 /* M2 fraction division */
7281 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7282
7283 /* M2 fraction division enable */
7284 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7285 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7286 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7287 if (bestm2_frac)
7288 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7289 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7290
7291 /* Program digital lock detect threshold */
7292 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7293 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7294 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7295 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7296 if (!bestm2_frac)
7297 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7298 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7299
7300 /* Loop filter */
7301 if (vco == 5400000) {
7302 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7303 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7304 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7305 tribuf_calcntr = 0x9;
7306 } else if (vco <= 6200000) {
7307 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7308 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7309 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7310 tribuf_calcntr = 0x9;
7311 } else if (vco <= 6480000) {
7312 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7313 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7314 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7315 tribuf_calcntr = 0x8;
7316 } else {
7317 /* Not supported. Apply the same limits as in the max case */
7318 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7319 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7320 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7321 tribuf_calcntr = 0;
7322 }
7323 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7324
7325 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7326 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7327 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7328 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7329
7330 /* AFC Recal */
7331 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7332 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7333 DPIO_AFC_RECAL);
7334
7335 mutex_unlock(&dev_priv->sb_lock);
7336 }
7337
7338 /**
7339 * vlv_force_pll_on - forcibly enable just the PLL
7340 * @dev_priv: i915 private structure
7341 * @pipe: pipe PLL to enable
7342 * @dpll: PLL configuration
7343 *
7344 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7345 * in cases where we need the PLL enabled even when @pipe is not going to
7346 * be enabled.
7347 */
7348 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7349 const struct dpll *dpll)
7350 {
7351 struct intel_crtc *crtc =
7352 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7353 struct intel_crtc_state *pipe_config;
7354
7355 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7356 if (!pipe_config)
7357 return -ENOMEM;
7358
7359 pipe_config->base.crtc = &crtc->base;
7360 pipe_config->pixel_multiplier = 1;
7361 pipe_config->dpll = *dpll;
7362
7363 if (IS_CHERRYVIEW(dev)) {
7364 chv_compute_dpll(crtc, pipe_config);
7365 chv_prepare_pll(crtc, pipe_config);
7366 chv_enable_pll(crtc, pipe_config);
7367 } else {
7368 vlv_compute_dpll(crtc, pipe_config);
7369 vlv_prepare_pll(crtc, pipe_config);
7370 vlv_enable_pll(crtc, pipe_config);
7371 }
7372
7373 kfree(pipe_config);
7374
7375 return 0;
7376 }
7377
7378 /**
7379 * vlv_force_pll_off - forcibly disable just the PLL
7380 * @dev_priv: i915 private structure
7381 * @pipe: pipe PLL to disable
7382 *
7383 * Disable the PLL for @pipe. To be used in cases where we need
7384 * the PLL enabled even when @pipe is not going to be enabled.
7385 */
7386 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7387 {
7388 if (IS_CHERRYVIEW(dev))
7389 chv_disable_pll(to_i915(dev), pipe);
7390 else
7391 vlv_disable_pll(to_i915(dev), pipe);
7392 }
7393
7394 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7395 struct intel_crtc_state *crtc_state,
7396 struct dpll *reduced_clock)
7397 {
7398 struct drm_device *dev = crtc->base.dev;
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400 u32 dpll;
7401 bool is_sdvo;
7402 struct dpll *clock = &crtc_state->dpll;
7403
7404 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7405
7406 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7407 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7408
7409 dpll = DPLL_VGA_MODE_DIS;
7410
7411 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7412 dpll |= DPLLB_MODE_LVDS;
7413 else
7414 dpll |= DPLLB_MODE_DAC_SERIAL;
7415
7416 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7417 dpll |= (crtc_state->pixel_multiplier - 1)
7418 << SDVO_MULTIPLIER_SHIFT_HIRES;
7419 }
7420
7421 if (is_sdvo)
7422 dpll |= DPLL_SDVO_HIGH_SPEED;
7423
7424 if (crtc_state->has_dp_encoder)
7425 dpll |= DPLL_SDVO_HIGH_SPEED;
7426
7427 /* compute bitmask from p1 value */
7428 if (IS_PINEVIEW(dev))
7429 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7430 else {
7431 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7432 if (IS_G4X(dev) && reduced_clock)
7433 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7434 }
7435 switch (clock->p2) {
7436 case 5:
7437 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7438 break;
7439 case 7:
7440 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7441 break;
7442 case 10:
7443 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7444 break;
7445 case 14:
7446 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7447 break;
7448 }
7449 if (INTEL_INFO(dev)->gen >= 4)
7450 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7451
7452 if (crtc_state->sdvo_tv_clock)
7453 dpll |= PLL_REF_INPUT_TVCLKINBC;
7454 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7455 intel_panel_use_ssc(dev_priv))
7456 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7457 else
7458 dpll |= PLL_REF_INPUT_DREFCLK;
7459
7460 dpll |= DPLL_VCO_ENABLE;
7461 crtc_state->dpll_hw_state.dpll = dpll;
7462
7463 if (INTEL_INFO(dev)->gen >= 4) {
7464 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7465 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7466 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7467 }
7468 }
7469
7470 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7471 struct intel_crtc_state *crtc_state,
7472 struct dpll *reduced_clock)
7473 {
7474 struct drm_device *dev = crtc->base.dev;
7475 struct drm_i915_private *dev_priv = dev->dev_private;
7476 u32 dpll;
7477 struct dpll *clock = &crtc_state->dpll;
7478
7479 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7480
7481 dpll = DPLL_VGA_MODE_DIS;
7482
7483 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7484 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7485 } else {
7486 if (clock->p1 == 2)
7487 dpll |= PLL_P1_DIVIDE_BY_TWO;
7488 else
7489 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7490 if (clock->p2 == 4)
7491 dpll |= PLL_P2_DIVIDE_BY_4;
7492 }
7493
7494 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7495 dpll |= DPLL_DVO_2X_MODE;
7496
7497 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7498 intel_panel_use_ssc(dev_priv))
7499 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7500 else
7501 dpll |= PLL_REF_INPUT_DREFCLK;
7502
7503 dpll |= DPLL_VCO_ENABLE;
7504 crtc_state->dpll_hw_state.dpll = dpll;
7505 }
7506
7507 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7508 {
7509 struct drm_device *dev = intel_crtc->base.dev;
7510 struct drm_i915_private *dev_priv = dev->dev_private;
7511 enum pipe pipe = intel_crtc->pipe;
7512 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7513 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7514 uint32_t crtc_vtotal, crtc_vblank_end;
7515 int vsyncshift = 0;
7516
7517 /* We need to be careful not to changed the adjusted mode, for otherwise
7518 * the hw state checker will get angry at the mismatch. */
7519 crtc_vtotal = adjusted_mode->crtc_vtotal;
7520 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7521
7522 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7523 /* the chip adds 2 halflines automatically */
7524 crtc_vtotal -= 1;
7525 crtc_vblank_end -= 1;
7526
7527 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7528 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7529 else
7530 vsyncshift = adjusted_mode->crtc_hsync_start -
7531 adjusted_mode->crtc_htotal / 2;
7532 if (vsyncshift < 0)
7533 vsyncshift += adjusted_mode->crtc_htotal;
7534 }
7535
7536 if (INTEL_INFO(dev)->gen > 3)
7537 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7538
7539 I915_WRITE(HTOTAL(cpu_transcoder),
7540 (adjusted_mode->crtc_hdisplay - 1) |
7541 ((adjusted_mode->crtc_htotal - 1) << 16));
7542 I915_WRITE(HBLANK(cpu_transcoder),
7543 (adjusted_mode->crtc_hblank_start - 1) |
7544 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7545 I915_WRITE(HSYNC(cpu_transcoder),
7546 (adjusted_mode->crtc_hsync_start - 1) |
7547 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7548
7549 I915_WRITE(VTOTAL(cpu_transcoder),
7550 (adjusted_mode->crtc_vdisplay - 1) |
7551 ((crtc_vtotal - 1) << 16));
7552 I915_WRITE(VBLANK(cpu_transcoder),
7553 (adjusted_mode->crtc_vblank_start - 1) |
7554 ((crtc_vblank_end - 1) << 16));
7555 I915_WRITE(VSYNC(cpu_transcoder),
7556 (adjusted_mode->crtc_vsync_start - 1) |
7557 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7558
7559 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7560 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7561 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7562 * bits. */
7563 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7564 (pipe == PIPE_B || pipe == PIPE_C))
7565 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7566
7567 }
7568
7569 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7570 {
7571 struct drm_device *dev = intel_crtc->base.dev;
7572 struct drm_i915_private *dev_priv = dev->dev_private;
7573 enum pipe pipe = intel_crtc->pipe;
7574
7575 /* pipesrc controls the size that is scaled from, which should
7576 * always be the user's requested size.
7577 */
7578 I915_WRITE(PIPESRC(pipe),
7579 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7580 (intel_crtc->config->pipe_src_h - 1));
7581 }
7582
7583 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7584 struct intel_crtc_state *pipe_config)
7585 {
7586 struct drm_device *dev = crtc->base.dev;
7587 struct drm_i915_private *dev_priv = dev->dev_private;
7588 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7589 uint32_t tmp;
7590
7591 tmp = I915_READ(HTOTAL(cpu_transcoder));
7592 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7593 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7594 tmp = I915_READ(HBLANK(cpu_transcoder));
7595 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7596 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7597 tmp = I915_READ(HSYNC(cpu_transcoder));
7598 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7599 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7600
7601 tmp = I915_READ(VTOTAL(cpu_transcoder));
7602 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7603 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7604 tmp = I915_READ(VBLANK(cpu_transcoder));
7605 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7606 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7607 tmp = I915_READ(VSYNC(cpu_transcoder));
7608 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7609 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7610
7611 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7612 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7613 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7614 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7615 }
7616 }
7617
7618 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7619 struct intel_crtc_state *pipe_config)
7620 {
7621 struct drm_device *dev = crtc->base.dev;
7622 struct drm_i915_private *dev_priv = dev->dev_private;
7623 u32 tmp;
7624
7625 tmp = I915_READ(PIPESRC(crtc->pipe));
7626 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7627 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7628
7629 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7630 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7631 }
7632
7633 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7634 struct intel_crtc_state *pipe_config)
7635 {
7636 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7637 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7638 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7639 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7640
7641 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7642 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7643 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7644 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7645
7646 mode->flags = pipe_config->base.adjusted_mode.flags;
7647 mode->type = DRM_MODE_TYPE_DRIVER;
7648
7649 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7650 mode->flags |= pipe_config->base.adjusted_mode.flags;
7651
7652 mode->hsync = drm_mode_hsync(mode);
7653 mode->vrefresh = drm_mode_vrefresh(mode);
7654 drm_mode_set_name(mode);
7655 }
7656
7657 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7658 {
7659 struct drm_device *dev = intel_crtc->base.dev;
7660 struct drm_i915_private *dev_priv = dev->dev_private;
7661 uint32_t pipeconf;
7662
7663 pipeconf = 0;
7664
7665 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7666 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7667 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7668
7669 if (intel_crtc->config->double_wide)
7670 pipeconf |= PIPECONF_DOUBLE_WIDE;
7671
7672 /* only g4x and later have fancy bpc/dither controls */
7673 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7674 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7675 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7676 pipeconf |= PIPECONF_DITHER_EN |
7677 PIPECONF_DITHER_TYPE_SP;
7678
7679 switch (intel_crtc->config->pipe_bpp) {
7680 case 18:
7681 pipeconf |= PIPECONF_6BPC;
7682 break;
7683 case 24:
7684 pipeconf |= PIPECONF_8BPC;
7685 break;
7686 case 30:
7687 pipeconf |= PIPECONF_10BPC;
7688 break;
7689 default:
7690 /* Case prevented by intel_choose_pipe_bpp_dither. */
7691 BUG();
7692 }
7693 }
7694
7695 if (HAS_PIPE_CXSR(dev)) {
7696 if (intel_crtc->lowfreq_avail) {
7697 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7698 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7699 } else {
7700 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7701 }
7702 }
7703
7704 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7705 if (INTEL_INFO(dev)->gen < 4 ||
7706 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7707 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7708 else
7709 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7710 } else
7711 pipeconf |= PIPECONF_PROGRESSIVE;
7712
7713 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7714 intel_crtc->config->limited_color_range)
7715 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7716
7717 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7718 POSTING_READ(PIPECONF(intel_crtc->pipe));
7719 }
7720
7721 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7722 struct intel_crtc_state *crtc_state)
7723 {
7724 struct drm_device *dev = crtc->base.dev;
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726 const struct intel_limit *limit;
7727 int refclk = 48000;
7728
7729 memset(&crtc_state->dpll_hw_state, 0,
7730 sizeof(crtc_state->dpll_hw_state));
7731
7732 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7733 if (intel_panel_use_ssc(dev_priv)) {
7734 refclk = dev_priv->vbt.lvds_ssc_freq;
7735 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7736 }
7737
7738 limit = &intel_limits_i8xx_lvds;
7739 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7740 limit = &intel_limits_i8xx_dvo;
7741 } else {
7742 limit = &intel_limits_i8xx_dac;
7743 }
7744
7745 if (!crtc_state->clock_set &&
7746 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7747 refclk, NULL, &crtc_state->dpll)) {
7748 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7749 return -EINVAL;
7750 }
7751
7752 i8xx_compute_dpll(crtc, crtc_state, NULL);
7753
7754 return 0;
7755 }
7756
7757 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7758 struct intel_crtc_state *crtc_state)
7759 {
7760 struct drm_device *dev = crtc->base.dev;
7761 struct drm_i915_private *dev_priv = dev->dev_private;
7762 const struct intel_limit *limit;
7763 int refclk = 96000;
7764
7765 memset(&crtc_state->dpll_hw_state, 0,
7766 sizeof(crtc_state->dpll_hw_state));
7767
7768 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7769 if (intel_panel_use_ssc(dev_priv)) {
7770 refclk = dev_priv->vbt.lvds_ssc_freq;
7771 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7772 }
7773
7774 if (intel_is_dual_link_lvds(dev))
7775 limit = &intel_limits_g4x_dual_channel_lvds;
7776 else
7777 limit = &intel_limits_g4x_single_channel_lvds;
7778 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7779 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7780 limit = &intel_limits_g4x_hdmi;
7781 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7782 limit = &intel_limits_g4x_sdvo;
7783 } else {
7784 /* The option is for other outputs */
7785 limit = &intel_limits_i9xx_sdvo;
7786 }
7787
7788 if (!crtc_state->clock_set &&
7789 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7790 refclk, NULL, &crtc_state->dpll)) {
7791 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7792 return -EINVAL;
7793 }
7794
7795 i9xx_compute_dpll(crtc, crtc_state, NULL);
7796
7797 return 0;
7798 }
7799
7800 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7801 struct intel_crtc_state *crtc_state)
7802 {
7803 struct drm_device *dev = crtc->base.dev;
7804 struct drm_i915_private *dev_priv = dev->dev_private;
7805 const struct intel_limit *limit;
7806 int refclk = 96000;
7807
7808 memset(&crtc_state->dpll_hw_state, 0,
7809 sizeof(crtc_state->dpll_hw_state));
7810
7811 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7812 if (intel_panel_use_ssc(dev_priv)) {
7813 refclk = dev_priv->vbt.lvds_ssc_freq;
7814 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7815 }
7816
7817 limit = &intel_limits_pineview_lvds;
7818 } else {
7819 limit = &intel_limits_pineview_sdvo;
7820 }
7821
7822 if (!crtc_state->clock_set &&
7823 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7824 refclk, NULL, &crtc_state->dpll)) {
7825 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7826 return -EINVAL;
7827 }
7828
7829 i9xx_compute_dpll(crtc, crtc_state, NULL);
7830
7831 return 0;
7832 }
7833
7834 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7835 struct intel_crtc_state *crtc_state)
7836 {
7837 struct drm_device *dev = crtc->base.dev;
7838 struct drm_i915_private *dev_priv = dev->dev_private;
7839 const struct intel_limit *limit;
7840 int refclk = 96000;
7841
7842 memset(&crtc_state->dpll_hw_state, 0,
7843 sizeof(crtc_state->dpll_hw_state));
7844
7845 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7846 if (intel_panel_use_ssc(dev_priv)) {
7847 refclk = dev_priv->vbt.lvds_ssc_freq;
7848 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7849 }
7850
7851 limit = &intel_limits_i9xx_lvds;
7852 } else {
7853 limit = &intel_limits_i9xx_sdvo;
7854 }
7855
7856 if (!crtc_state->clock_set &&
7857 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7858 refclk, NULL, &crtc_state->dpll)) {
7859 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7860 return -EINVAL;
7861 }
7862
7863 i9xx_compute_dpll(crtc, crtc_state, NULL);
7864
7865 return 0;
7866 }
7867
7868 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7869 struct intel_crtc_state *crtc_state)
7870 {
7871 int refclk = 100000;
7872 const struct intel_limit *limit = &intel_limits_chv;
7873
7874 memset(&crtc_state->dpll_hw_state, 0,
7875 sizeof(crtc_state->dpll_hw_state));
7876
7877 if (!crtc_state->clock_set &&
7878 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7879 refclk, NULL, &crtc_state->dpll)) {
7880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7881 return -EINVAL;
7882 }
7883
7884 chv_compute_dpll(crtc, crtc_state);
7885
7886 return 0;
7887 }
7888
7889 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7890 struct intel_crtc_state *crtc_state)
7891 {
7892 int refclk = 100000;
7893 const struct intel_limit *limit = &intel_limits_vlv;
7894
7895 memset(&crtc_state->dpll_hw_state, 0,
7896 sizeof(crtc_state->dpll_hw_state));
7897
7898 if (!crtc_state->clock_set &&
7899 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7900 refclk, NULL, &crtc_state->dpll)) {
7901 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7902 return -EINVAL;
7903 }
7904
7905 vlv_compute_dpll(crtc, crtc_state);
7906
7907 return 0;
7908 }
7909
7910 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7911 struct intel_crtc_state *pipe_config)
7912 {
7913 struct drm_device *dev = crtc->base.dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 uint32_t tmp;
7916
7917 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7918 return;
7919
7920 tmp = I915_READ(PFIT_CONTROL);
7921 if (!(tmp & PFIT_ENABLE))
7922 return;
7923
7924 /* Check whether the pfit is attached to our pipe. */
7925 if (INTEL_INFO(dev)->gen < 4) {
7926 if (crtc->pipe != PIPE_B)
7927 return;
7928 } else {
7929 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7930 return;
7931 }
7932
7933 pipe_config->gmch_pfit.control = tmp;
7934 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7935 }
7936
7937 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7938 struct intel_crtc_state *pipe_config)
7939 {
7940 struct drm_device *dev = crtc->base.dev;
7941 struct drm_i915_private *dev_priv = dev->dev_private;
7942 int pipe = pipe_config->cpu_transcoder;
7943 struct dpll clock;
7944 u32 mdiv;
7945 int refclk = 100000;
7946
7947 /* In case of DSI, DPLL will not be used */
7948 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7949 return;
7950
7951 mutex_lock(&dev_priv->sb_lock);
7952 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7953 mutex_unlock(&dev_priv->sb_lock);
7954
7955 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7956 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7957 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7958 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7959 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7960
7961 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7962 }
7963
7964 static void
7965 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7966 struct intel_initial_plane_config *plane_config)
7967 {
7968 struct drm_device *dev = crtc->base.dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970 u32 val, base, offset;
7971 int pipe = crtc->pipe, plane = crtc->plane;
7972 int fourcc, pixel_format;
7973 unsigned int aligned_height;
7974 struct drm_framebuffer *fb;
7975 struct intel_framebuffer *intel_fb;
7976
7977 val = I915_READ(DSPCNTR(plane));
7978 if (!(val & DISPLAY_PLANE_ENABLE))
7979 return;
7980
7981 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7982 if (!intel_fb) {
7983 DRM_DEBUG_KMS("failed to alloc fb\n");
7984 return;
7985 }
7986
7987 fb = &intel_fb->base;
7988
7989 if (INTEL_INFO(dev)->gen >= 4) {
7990 if (val & DISPPLANE_TILED) {
7991 plane_config->tiling = I915_TILING_X;
7992 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7993 }
7994 }
7995
7996 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7997 fourcc = i9xx_format_to_fourcc(pixel_format);
7998 fb->pixel_format = fourcc;
7999 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8000
8001 if (INTEL_INFO(dev)->gen >= 4) {
8002 if (plane_config->tiling)
8003 offset = I915_READ(DSPTILEOFF(plane));
8004 else
8005 offset = I915_READ(DSPLINOFF(plane));
8006 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8007 } else {
8008 base = I915_READ(DSPADDR(plane));
8009 }
8010 plane_config->base = base;
8011
8012 val = I915_READ(PIPESRC(pipe));
8013 fb->width = ((val >> 16) & 0xfff) + 1;
8014 fb->height = ((val >> 0) & 0xfff) + 1;
8015
8016 val = I915_READ(DSPSTRIDE(pipe));
8017 fb->pitches[0] = val & 0xffffffc0;
8018
8019 aligned_height = intel_fb_align_height(dev, fb->height,
8020 fb->pixel_format,
8021 fb->modifier[0]);
8022
8023 plane_config->size = fb->pitches[0] * aligned_height;
8024
8025 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8026 pipe_name(pipe), plane, fb->width, fb->height,
8027 fb->bits_per_pixel, base, fb->pitches[0],
8028 plane_config->size);
8029
8030 plane_config->fb = intel_fb;
8031 }
8032
8033 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8034 struct intel_crtc_state *pipe_config)
8035 {
8036 struct drm_device *dev = crtc->base.dev;
8037 struct drm_i915_private *dev_priv = dev->dev_private;
8038 int pipe = pipe_config->cpu_transcoder;
8039 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8040 struct dpll clock;
8041 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8042 int refclk = 100000;
8043
8044 /* In case of DSI, DPLL will not be used */
8045 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8046 return;
8047
8048 mutex_lock(&dev_priv->sb_lock);
8049 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8050 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8051 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8052 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8053 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8054 mutex_unlock(&dev_priv->sb_lock);
8055
8056 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8057 clock.m2 = (pll_dw0 & 0xff) << 22;
8058 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8059 clock.m2 |= pll_dw2 & 0x3fffff;
8060 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8061 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8062 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8063
8064 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8065 }
8066
8067 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8068 struct intel_crtc_state *pipe_config)
8069 {
8070 struct drm_device *dev = crtc->base.dev;
8071 struct drm_i915_private *dev_priv = dev->dev_private;
8072 enum intel_display_power_domain power_domain;
8073 uint32_t tmp;
8074 bool ret;
8075
8076 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8077 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8078 return false;
8079
8080 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8081 pipe_config->shared_dpll = NULL;
8082
8083 ret = false;
8084
8085 tmp = I915_READ(PIPECONF(crtc->pipe));
8086 if (!(tmp & PIPECONF_ENABLE))
8087 goto out;
8088
8089 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8090 switch (tmp & PIPECONF_BPC_MASK) {
8091 case PIPECONF_6BPC:
8092 pipe_config->pipe_bpp = 18;
8093 break;
8094 case PIPECONF_8BPC:
8095 pipe_config->pipe_bpp = 24;
8096 break;
8097 case PIPECONF_10BPC:
8098 pipe_config->pipe_bpp = 30;
8099 break;
8100 default:
8101 break;
8102 }
8103 }
8104
8105 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8106 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8107 pipe_config->limited_color_range = true;
8108
8109 if (INTEL_INFO(dev)->gen < 4)
8110 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8111
8112 intel_get_pipe_timings(crtc, pipe_config);
8113 intel_get_pipe_src_size(crtc, pipe_config);
8114
8115 i9xx_get_pfit_config(crtc, pipe_config);
8116
8117 if (INTEL_INFO(dev)->gen >= 4) {
8118 /* No way to read it out on pipes B and C */
8119 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8120 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8121 else
8122 tmp = I915_READ(DPLL_MD(crtc->pipe));
8123 pipe_config->pixel_multiplier =
8124 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8125 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8126 pipe_config->dpll_hw_state.dpll_md = tmp;
8127 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8128 tmp = I915_READ(DPLL(crtc->pipe));
8129 pipe_config->pixel_multiplier =
8130 ((tmp & SDVO_MULTIPLIER_MASK)
8131 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8132 } else {
8133 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8134 * port and will be fixed up in the encoder->get_config
8135 * function. */
8136 pipe_config->pixel_multiplier = 1;
8137 }
8138 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8139 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8140 /*
8141 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8142 * on 830. Filter it out here so that we don't
8143 * report errors due to that.
8144 */
8145 if (IS_I830(dev))
8146 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8147
8148 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8149 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8150 } else {
8151 /* Mask out read-only status bits. */
8152 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8153 DPLL_PORTC_READY_MASK |
8154 DPLL_PORTB_READY_MASK);
8155 }
8156
8157 if (IS_CHERRYVIEW(dev))
8158 chv_crtc_clock_get(crtc, pipe_config);
8159 else if (IS_VALLEYVIEW(dev))
8160 vlv_crtc_clock_get(crtc, pipe_config);
8161 else
8162 i9xx_crtc_clock_get(crtc, pipe_config);
8163
8164 /*
8165 * Normally the dotclock is filled in by the encoder .get_config()
8166 * but in case the pipe is enabled w/o any ports we need a sane
8167 * default.
8168 */
8169 pipe_config->base.adjusted_mode.crtc_clock =
8170 pipe_config->port_clock / pipe_config->pixel_multiplier;
8171
8172 ret = true;
8173
8174 out:
8175 intel_display_power_put(dev_priv, power_domain);
8176
8177 return ret;
8178 }
8179
8180 static void ironlake_init_pch_refclk(struct drm_device *dev)
8181 {
8182 struct drm_i915_private *dev_priv = dev->dev_private;
8183 struct intel_encoder *encoder;
8184 u32 val, final;
8185 bool has_lvds = false;
8186 bool has_cpu_edp = false;
8187 bool has_panel = false;
8188 bool has_ck505 = false;
8189 bool can_ssc = false;
8190
8191 /* We need to take the global config into account */
8192 for_each_intel_encoder(dev, encoder) {
8193 switch (encoder->type) {
8194 case INTEL_OUTPUT_LVDS:
8195 has_panel = true;
8196 has_lvds = true;
8197 break;
8198 case INTEL_OUTPUT_EDP:
8199 has_panel = true;
8200 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8201 has_cpu_edp = true;
8202 break;
8203 default:
8204 break;
8205 }
8206 }
8207
8208 if (HAS_PCH_IBX(dev)) {
8209 has_ck505 = dev_priv->vbt.display_clock_mode;
8210 can_ssc = has_ck505;
8211 } else {
8212 has_ck505 = false;
8213 can_ssc = true;
8214 }
8215
8216 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8217 has_panel, has_lvds, has_ck505);
8218
8219 /* Ironlake: try to setup display ref clock before DPLL
8220 * enabling. This is only under driver's control after
8221 * PCH B stepping, previous chipset stepping should be
8222 * ignoring this setting.
8223 */
8224 val = I915_READ(PCH_DREF_CONTROL);
8225
8226 /* As we must carefully and slowly disable/enable each source in turn,
8227 * compute the final state we want first and check if we need to
8228 * make any changes at all.
8229 */
8230 final = val;
8231 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8232 if (has_ck505)
8233 final |= DREF_NONSPREAD_CK505_ENABLE;
8234 else
8235 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8236
8237 final &= ~DREF_SSC_SOURCE_MASK;
8238 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8239 final &= ~DREF_SSC1_ENABLE;
8240
8241 if (has_panel) {
8242 final |= DREF_SSC_SOURCE_ENABLE;
8243
8244 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8245 final |= DREF_SSC1_ENABLE;
8246
8247 if (has_cpu_edp) {
8248 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8249 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8250 else
8251 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8252 } else
8253 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8254 } else {
8255 final |= DREF_SSC_SOURCE_DISABLE;
8256 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8257 }
8258
8259 if (final == val)
8260 return;
8261
8262 /* Always enable nonspread source */
8263 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8264
8265 if (has_ck505)
8266 val |= DREF_NONSPREAD_CK505_ENABLE;
8267 else
8268 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8269
8270 if (has_panel) {
8271 val &= ~DREF_SSC_SOURCE_MASK;
8272 val |= DREF_SSC_SOURCE_ENABLE;
8273
8274 /* SSC must be turned on before enabling the CPU output */
8275 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8276 DRM_DEBUG_KMS("Using SSC on panel\n");
8277 val |= DREF_SSC1_ENABLE;
8278 } else
8279 val &= ~DREF_SSC1_ENABLE;
8280
8281 /* Get SSC going before enabling the outputs */
8282 I915_WRITE(PCH_DREF_CONTROL, val);
8283 POSTING_READ(PCH_DREF_CONTROL);
8284 udelay(200);
8285
8286 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8287
8288 /* Enable CPU source on CPU attached eDP */
8289 if (has_cpu_edp) {
8290 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8291 DRM_DEBUG_KMS("Using SSC on eDP\n");
8292 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8293 } else
8294 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8295 } else
8296 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8297
8298 I915_WRITE(PCH_DREF_CONTROL, val);
8299 POSTING_READ(PCH_DREF_CONTROL);
8300 udelay(200);
8301 } else {
8302 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8303
8304 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8305
8306 /* Turn off CPU output */
8307 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8308
8309 I915_WRITE(PCH_DREF_CONTROL, val);
8310 POSTING_READ(PCH_DREF_CONTROL);
8311 udelay(200);
8312
8313 /* Turn off the SSC source */
8314 val &= ~DREF_SSC_SOURCE_MASK;
8315 val |= DREF_SSC_SOURCE_DISABLE;
8316
8317 /* Turn off SSC1 */
8318 val &= ~DREF_SSC1_ENABLE;
8319
8320 I915_WRITE(PCH_DREF_CONTROL, val);
8321 POSTING_READ(PCH_DREF_CONTROL);
8322 udelay(200);
8323 }
8324
8325 BUG_ON(val != final);
8326 }
8327
8328 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8329 {
8330 uint32_t tmp;
8331
8332 tmp = I915_READ(SOUTH_CHICKEN2);
8333 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8334 I915_WRITE(SOUTH_CHICKEN2, tmp);
8335
8336 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8337 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8338 DRM_ERROR("FDI mPHY reset assert timeout\n");
8339
8340 tmp = I915_READ(SOUTH_CHICKEN2);
8341 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8342 I915_WRITE(SOUTH_CHICKEN2, tmp);
8343
8344 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8345 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8346 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8347 }
8348
8349 /* WaMPhyProgramming:hsw */
8350 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8351 {
8352 uint32_t tmp;
8353
8354 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8355 tmp &= ~(0xFF << 24);
8356 tmp |= (0x12 << 24);
8357 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8358
8359 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8360 tmp |= (1 << 11);
8361 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8362
8363 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8364 tmp |= (1 << 11);
8365 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8366
8367 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8368 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8369 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8370
8371 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8372 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8373 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8374
8375 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8376 tmp &= ~(7 << 13);
8377 tmp |= (5 << 13);
8378 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8379
8380 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8381 tmp &= ~(7 << 13);
8382 tmp |= (5 << 13);
8383 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8384
8385 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8386 tmp &= ~0xFF;
8387 tmp |= 0x1C;
8388 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8389
8390 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8391 tmp &= ~0xFF;
8392 tmp |= 0x1C;
8393 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8394
8395 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8396 tmp &= ~(0xFF << 16);
8397 tmp |= (0x1C << 16);
8398 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8399
8400 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8401 tmp &= ~(0xFF << 16);
8402 tmp |= (0x1C << 16);
8403 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8404
8405 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8406 tmp |= (1 << 27);
8407 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8408
8409 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8410 tmp |= (1 << 27);
8411 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8412
8413 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8414 tmp &= ~(0xF << 28);
8415 tmp |= (4 << 28);
8416 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8417
8418 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8419 tmp &= ~(0xF << 28);
8420 tmp |= (4 << 28);
8421 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8422 }
8423
8424 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8425 * Programming" based on the parameters passed:
8426 * - Sequence to enable CLKOUT_DP
8427 * - Sequence to enable CLKOUT_DP without spread
8428 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8429 */
8430 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8431 bool with_fdi)
8432 {
8433 struct drm_i915_private *dev_priv = dev->dev_private;
8434 uint32_t reg, tmp;
8435
8436 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8437 with_spread = true;
8438 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8439 with_fdi = false;
8440
8441 mutex_lock(&dev_priv->sb_lock);
8442
8443 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8444 tmp &= ~SBI_SSCCTL_DISABLE;
8445 tmp |= SBI_SSCCTL_PATHALT;
8446 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8447
8448 udelay(24);
8449
8450 if (with_spread) {
8451 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8452 tmp &= ~SBI_SSCCTL_PATHALT;
8453 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8454
8455 if (with_fdi) {
8456 lpt_reset_fdi_mphy(dev_priv);
8457 lpt_program_fdi_mphy(dev_priv);
8458 }
8459 }
8460
8461 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8462 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8463 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8464 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8465
8466 mutex_unlock(&dev_priv->sb_lock);
8467 }
8468
8469 /* Sequence to disable CLKOUT_DP */
8470 static void lpt_disable_clkout_dp(struct drm_device *dev)
8471 {
8472 struct drm_i915_private *dev_priv = dev->dev_private;
8473 uint32_t reg, tmp;
8474
8475 mutex_lock(&dev_priv->sb_lock);
8476
8477 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8478 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8479 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8480 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8481
8482 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8483 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8484 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8485 tmp |= SBI_SSCCTL_PATHALT;
8486 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8487 udelay(32);
8488 }
8489 tmp |= SBI_SSCCTL_DISABLE;
8490 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8491 }
8492
8493 mutex_unlock(&dev_priv->sb_lock);
8494 }
8495
8496 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8497
8498 static const uint16_t sscdivintphase[] = {
8499 [BEND_IDX( 50)] = 0x3B23,
8500 [BEND_IDX( 45)] = 0x3B23,
8501 [BEND_IDX( 40)] = 0x3C23,
8502 [BEND_IDX( 35)] = 0x3C23,
8503 [BEND_IDX( 30)] = 0x3D23,
8504 [BEND_IDX( 25)] = 0x3D23,
8505 [BEND_IDX( 20)] = 0x3E23,
8506 [BEND_IDX( 15)] = 0x3E23,
8507 [BEND_IDX( 10)] = 0x3F23,
8508 [BEND_IDX( 5)] = 0x3F23,
8509 [BEND_IDX( 0)] = 0x0025,
8510 [BEND_IDX( -5)] = 0x0025,
8511 [BEND_IDX(-10)] = 0x0125,
8512 [BEND_IDX(-15)] = 0x0125,
8513 [BEND_IDX(-20)] = 0x0225,
8514 [BEND_IDX(-25)] = 0x0225,
8515 [BEND_IDX(-30)] = 0x0325,
8516 [BEND_IDX(-35)] = 0x0325,
8517 [BEND_IDX(-40)] = 0x0425,
8518 [BEND_IDX(-45)] = 0x0425,
8519 [BEND_IDX(-50)] = 0x0525,
8520 };
8521
8522 /*
8523 * Bend CLKOUT_DP
8524 * steps -50 to 50 inclusive, in steps of 5
8525 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8526 * change in clock period = -(steps / 10) * 5.787 ps
8527 */
8528 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8529 {
8530 uint32_t tmp;
8531 int idx = BEND_IDX(steps);
8532
8533 if (WARN_ON(steps % 5 != 0))
8534 return;
8535
8536 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8537 return;
8538
8539 mutex_lock(&dev_priv->sb_lock);
8540
8541 if (steps % 10 != 0)
8542 tmp = 0xAAAAAAAB;
8543 else
8544 tmp = 0x00000000;
8545 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8546
8547 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8548 tmp &= 0xffff0000;
8549 tmp |= sscdivintphase[idx];
8550 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8551
8552 mutex_unlock(&dev_priv->sb_lock);
8553 }
8554
8555 #undef BEND_IDX
8556
8557 static void lpt_init_pch_refclk(struct drm_device *dev)
8558 {
8559 struct intel_encoder *encoder;
8560 bool has_vga = false;
8561
8562 for_each_intel_encoder(dev, encoder) {
8563 switch (encoder->type) {
8564 case INTEL_OUTPUT_ANALOG:
8565 has_vga = true;
8566 break;
8567 default:
8568 break;
8569 }
8570 }
8571
8572 if (has_vga) {
8573 lpt_bend_clkout_dp(to_i915(dev), 0);
8574 lpt_enable_clkout_dp(dev, true, true);
8575 } else {
8576 lpt_disable_clkout_dp(dev);
8577 }
8578 }
8579
8580 /*
8581 * Initialize reference clocks when the driver loads
8582 */
8583 void intel_init_pch_refclk(struct drm_device *dev)
8584 {
8585 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8586 ironlake_init_pch_refclk(dev);
8587 else if (HAS_PCH_LPT(dev))
8588 lpt_init_pch_refclk(dev);
8589 }
8590
8591 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8592 {
8593 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8595 int pipe = intel_crtc->pipe;
8596 uint32_t val;
8597
8598 val = 0;
8599
8600 switch (intel_crtc->config->pipe_bpp) {
8601 case 18:
8602 val |= PIPECONF_6BPC;
8603 break;
8604 case 24:
8605 val |= PIPECONF_8BPC;
8606 break;
8607 case 30:
8608 val |= PIPECONF_10BPC;
8609 break;
8610 case 36:
8611 val |= PIPECONF_12BPC;
8612 break;
8613 default:
8614 /* Case prevented by intel_choose_pipe_bpp_dither. */
8615 BUG();
8616 }
8617
8618 if (intel_crtc->config->dither)
8619 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8620
8621 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8622 val |= PIPECONF_INTERLACED_ILK;
8623 else
8624 val |= PIPECONF_PROGRESSIVE;
8625
8626 if (intel_crtc->config->limited_color_range)
8627 val |= PIPECONF_COLOR_RANGE_SELECT;
8628
8629 I915_WRITE(PIPECONF(pipe), val);
8630 POSTING_READ(PIPECONF(pipe));
8631 }
8632
8633 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8634 {
8635 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8637 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8638 u32 val = 0;
8639
8640 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8641 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8642
8643 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8644 val |= PIPECONF_INTERLACED_ILK;
8645 else
8646 val |= PIPECONF_PROGRESSIVE;
8647
8648 I915_WRITE(PIPECONF(cpu_transcoder), val);
8649 POSTING_READ(PIPECONF(cpu_transcoder));
8650 }
8651
8652 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8653 {
8654 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8656
8657 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8658 u32 val = 0;
8659
8660 switch (intel_crtc->config->pipe_bpp) {
8661 case 18:
8662 val |= PIPEMISC_DITHER_6_BPC;
8663 break;
8664 case 24:
8665 val |= PIPEMISC_DITHER_8_BPC;
8666 break;
8667 case 30:
8668 val |= PIPEMISC_DITHER_10_BPC;
8669 break;
8670 case 36:
8671 val |= PIPEMISC_DITHER_12_BPC;
8672 break;
8673 default:
8674 /* Case prevented by pipe_config_set_bpp. */
8675 BUG();
8676 }
8677
8678 if (intel_crtc->config->dither)
8679 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8680
8681 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8682 }
8683 }
8684
8685 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8686 {
8687 /*
8688 * Account for spread spectrum to avoid
8689 * oversubscribing the link. Max center spread
8690 * is 2.5%; use 5% for safety's sake.
8691 */
8692 u32 bps = target_clock * bpp * 21 / 20;
8693 return DIV_ROUND_UP(bps, link_bw * 8);
8694 }
8695
8696 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8697 {
8698 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8699 }
8700
8701 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8702 struct intel_crtc_state *crtc_state,
8703 struct dpll *reduced_clock)
8704 {
8705 struct drm_crtc *crtc = &intel_crtc->base;
8706 struct drm_device *dev = crtc->dev;
8707 struct drm_i915_private *dev_priv = dev->dev_private;
8708 struct drm_atomic_state *state = crtc_state->base.state;
8709 struct drm_connector *connector;
8710 struct drm_connector_state *connector_state;
8711 struct intel_encoder *encoder;
8712 u32 dpll, fp, fp2;
8713 int factor, i;
8714 bool is_lvds = false, is_sdvo = false;
8715
8716 for_each_connector_in_state(state, connector, connector_state, i) {
8717 if (connector_state->crtc != crtc_state->base.crtc)
8718 continue;
8719
8720 encoder = to_intel_encoder(connector_state->best_encoder);
8721
8722 switch (encoder->type) {
8723 case INTEL_OUTPUT_LVDS:
8724 is_lvds = true;
8725 break;
8726 case INTEL_OUTPUT_SDVO:
8727 case INTEL_OUTPUT_HDMI:
8728 is_sdvo = true;
8729 break;
8730 default:
8731 break;
8732 }
8733 }
8734
8735 /* Enable autotuning of the PLL clock (if permissible) */
8736 factor = 21;
8737 if (is_lvds) {
8738 if ((intel_panel_use_ssc(dev_priv) &&
8739 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8740 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8741 factor = 25;
8742 } else if (crtc_state->sdvo_tv_clock)
8743 factor = 20;
8744
8745 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8746
8747 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8748 fp |= FP_CB_TUNE;
8749
8750 if (reduced_clock) {
8751 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8752
8753 if (reduced_clock->m < factor * reduced_clock->n)
8754 fp2 |= FP_CB_TUNE;
8755 } else {
8756 fp2 = fp;
8757 }
8758
8759 dpll = 0;
8760
8761 if (is_lvds)
8762 dpll |= DPLLB_MODE_LVDS;
8763 else
8764 dpll |= DPLLB_MODE_DAC_SERIAL;
8765
8766 dpll |= (crtc_state->pixel_multiplier - 1)
8767 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8768
8769 if (is_sdvo)
8770 dpll |= DPLL_SDVO_HIGH_SPEED;
8771 if (crtc_state->has_dp_encoder)
8772 dpll |= DPLL_SDVO_HIGH_SPEED;
8773
8774 /* compute bitmask from p1 value */
8775 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8776 /* also FPA1 */
8777 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8778
8779 switch (crtc_state->dpll.p2) {
8780 case 5:
8781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8782 break;
8783 case 7:
8784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8785 break;
8786 case 10:
8787 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8788 break;
8789 case 14:
8790 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8791 break;
8792 }
8793
8794 if (is_lvds && intel_panel_use_ssc(dev_priv))
8795 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8796 else
8797 dpll |= PLL_REF_INPUT_DREFCLK;
8798
8799 dpll |= DPLL_VCO_ENABLE;
8800
8801 crtc_state->dpll_hw_state.dpll = dpll;
8802 crtc_state->dpll_hw_state.fp0 = fp;
8803 crtc_state->dpll_hw_state.fp1 = fp2;
8804 }
8805
8806 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8807 struct intel_crtc_state *crtc_state)
8808 {
8809 struct drm_device *dev = crtc->base.dev;
8810 struct drm_i915_private *dev_priv = dev->dev_private;
8811 struct dpll reduced_clock;
8812 bool has_reduced_clock = false;
8813 struct intel_shared_dpll *pll;
8814 const struct intel_limit *limit;
8815 int refclk = 120000;
8816
8817 memset(&crtc_state->dpll_hw_state, 0,
8818 sizeof(crtc_state->dpll_hw_state));
8819
8820 crtc->lowfreq_avail = false;
8821
8822 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8823 if (!crtc_state->has_pch_encoder)
8824 return 0;
8825
8826 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8827 if (intel_panel_use_ssc(dev_priv)) {
8828 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8829 dev_priv->vbt.lvds_ssc_freq);
8830 refclk = dev_priv->vbt.lvds_ssc_freq;
8831 }
8832
8833 if (intel_is_dual_link_lvds(dev)) {
8834 if (refclk == 100000)
8835 limit = &intel_limits_ironlake_dual_lvds_100m;
8836 else
8837 limit = &intel_limits_ironlake_dual_lvds;
8838 } else {
8839 if (refclk == 100000)
8840 limit = &intel_limits_ironlake_single_lvds_100m;
8841 else
8842 limit = &intel_limits_ironlake_single_lvds;
8843 }
8844 } else {
8845 limit = &intel_limits_ironlake_dac;
8846 }
8847
8848 if (!crtc_state->clock_set &&
8849 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8850 refclk, NULL, &crtc_state->dpll)) {
8851 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8852 return -EINVAL;
8853 }
8854
8855 ironlake_compute_dpll(crtc, crtc_state,
8856 has_reduced_clock ? &reduced_clock : NULL);
8857
8858 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8859 if (pll == NULL) {
8860 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8861 pipe_name(crtc->pipe));
8862 return -EINVAL;
8863 }
8864
8865 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8866 has_reduced_clock)
8867 crtc->lowfreq_avail = true;
8868
8869 return 0;
8870 }
8871
8872 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8873 struct intel_link_m_n *m_n)
8874 {
8875 struct drm_device *dev = crtc->base.dev;
8876 struct drm_i915_private *dev_priv = dev->dev_private;
8877 enum pipe pipe = crtc->pipe;
8878
8879 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8880 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8881 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8882 & ~TU_SIZE_MASK;
8883 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8884 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8885 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8886 }
8887
8888 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8889 enum transcoder transcoder,
8890 struct intel_link_m_n *m_n,
8891 struct intel_link_m_n *m2_n2)
8892 {
8893 struct drm_device *dev = crtc->base.dev;
8894 struct drm_i915_private *dev_priv = dev->dev_private;
8895 enum pipe pipe = crtc->pipe;
8896
8897 if (INTEL_INFO(dev)->gen >= 5) {
8898 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8899 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8900 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8901 & ~TU_SIZE_MASK;
8902 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8903 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8904 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8905 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8906 * gen < 8) and if DRRS is supported (to make sure the
8907 * registers are not unnecessarily read).
8908 */
8909 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8910 crtc->config->has_drrs) {
8911 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8912 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8913 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8914 & ~TU_SIZE_MASK;
8915 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8916 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8917 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8918 }
8919 } else {
8920 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8921 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8922 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8923 & ~TU_SIZE_MASK;
8924 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8925 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8926 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8927 }
8928 }
8929
8930 void intel_dp_get_m_n(struct intel_crtc *crtc,
8931 struct intel_crtc_state *pipe_config)
8932 {
8933 if (pipe_config->has_pch_encoder)
8934 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8935 else
8936 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8937 &pipe_config->dp_m_n,
8938 &pipe_config->dp_m2_n2);
8939 }
8940
8941 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8942 struct intel_crtc_state *pipe_config)
8943 {
8944 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8945 &pipe_config->fdi_m_n, NULL);
8946 }
8947
8948 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8949 struct intel_crtc_state *pipe_config)
8950 {
8951 struct drm_device *dev = crtc->base.dev;
8952 struct drm_i915_private *dev_priv = dev->dev_private;
8953 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8954 uint32_t ps_ctrl = 0;
8955 int id = -1;
8956 int i;
8957
8958 /* find scaler attached to this pipe */
8959 for (i = 0; i < crtc->num_scalers; i++) {
8960 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8961 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8962 id = i;
8963 pipe_config->pch_pfit.enabled = true;
8964 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8965 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8966 break;
8967 }
8968 }
8969
8970 scaler_state->scaler_id = id;
8971 if (id >= 0) {
8972 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8973 } else {
8974 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8975 }
8976 }
8977
8978 static void
8979 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8980 struct intel_initial_plane_config *plane_config)
8981 {
8982 struct drm_device *dev = crtc->base.dev;
8983 struct drm_i915_private *dev_priv = dev->dev_private;
8984 u32 val, base, offset, stride_mult, tiling;
8985 int pipe = crtc->pipe;
8986 int fourcc, pixel_format;
8987 unsigned int aligned_height;
8988 struct drm_framebuffer *fb;
8989 struct intel_framebuffer *intel_fb;
8990
8991 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8992 if (!intel_fb) {
8993 DRM_DEBUG_KMS("failed to alloc fb\n");
8994 return;
8995 }
8996
8997 fb = &intel_fb->base;
8998
8999 val = I915_READ(PLANE_CTL(pipe, 0));
9000 if (!(val & PLANE_CTL_ENABLE))
9001 goto error;
9002
9003 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9004 fourcc = skl_format_to_fourcc(pixel_format,
9005 val & PLANE_CTL_ORDER_RGBX,
9006 val & PLANE_CTL_ALPHA_MASK);
9007 fb->pixel_format = fourcc;
9008 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9009
9010 tiling = val & PLANE_CTL_TILED_MASK;
9011 switch (tiling) {
9012 case PLANE_CTL_TILED_LINEAR:
9013 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9014 break;
9015 case PLANE_CTL_TILED_X:
9016 plane_config->tiling = I915_TILING_X;
9017 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9018 break;
9019 case PLANE_CTL_TILED_Y:
9020 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9021 break;
9022 case PLANE_CTL_TILED_YF:
9023 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9024 break;
9025 default:
9026 MISSING_CASE(tiling);
9027 goto error;
9028 }
9029
9030 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9031 plane_config->base = base;
9032
9033 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9034
9035 val = I915_READ(PLANE_SIZE(pipe, 0));
9036 fb->height = ((val >> 16) & 0xfff) + 1;
9037 fb->width = ((val >> 0) & 0x1fff) + 1;
9038
9039 val = I915_READ(PLANE_STRIDE(pipe, 0));
9040 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9041 fb->pixel_format);
9042 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9043
9044 aligned_height = intel_fb_align_height(dev, fb->height,
9045 fb->pixel_format,
9046 fb->modifier[0]);
9047
9048 plane_config->size = fb->pitches[0] * aligned_height;
9049
9050 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9051 pipe_name(pipe), fb->width, fb->height,
9052 fb->bits_per_pixel, base, fb->pitches[0],
9053 plane_config->size);
9054
9055 plane_config->fb = intel_fb;
9056 return;
9057
9058 error:
9059 kfree(fb);
9060 }
9061
9062 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9063 struct intel_crtc_state *pipe_config)
9064 {
9065 struct drm_device *dev = crtc->base.dev;
9066 struct drm_i915_private *dev_priv = dev->dev_private;
9067 uint32_t tmp;
9068
9069 tmp = I915_READ(PF_CTL(crtc->pipe));
9070
9071 if (tmp & PF_ENABLE) {
9072 pipe_config->pch_pfit.enabled = true;
9073 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9074 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9075
9076 /* We currently do not free assignements of panel fitters on
9077 * ivb/hsw (since we don't use the higher upscaling modes which
9078 * differentiates them) so just WARN about this case for now. */
9079 if (IS_GEN7(dev)) {
9080 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9081 PF_PIPE_SEL_IVB(crtc->pipe));
9082 }
9083 }
9084 }
9085
9086 static void
9087 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9088 struct intel_initial_plane_config *plane_config)
9089 {
9090 struct drm_device *dev = crtc->base.dev;
9091 struct drm_i915_private *dev_priv = dev->dev_private;
9092 u32 val, base, offset;
9093 int pipe = crtc->pipe;
9094 int fourcc, pixel_format;
9095 unsigned int aligned_height;
9096 struct drm_framebuffer *fb;
9097 struct intel_framebuffer *intel_fb;
9098
9099 val = I915_READ(DSPCNTR(pipe));
9100 if (!(val & DISPLAY_PLANE_ENABLE))
9101 return;
9102
9103 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9104 if (!intel_fb) {
9105 DRM_DEBUG_KMS("failed to alloc fb\n");
9106 return;
9107 }
9108
9109 fb = &intel_fb->base;
9110
9111 if (INTEL_INFO(dev)->gen >= 4) {
9112 if (val & DISPPLANE_TILED) {
9113 plane_config->tiling = I915_TILING_X;
9114 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9115 }
9116 }
9117
9118 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9119 fourcc = i9xx_format_to_fourcc(pixel_format);
9120 fb->pixel_format = fourcc;
9121 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9122
9123 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9124 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9125 offset = I915_READ(DSPOFFSET(pipe));
9126 } else {
9127 if (plane_config->tiling)
9128 offset = I915_READ(DSPTILEOFF(pipe));
9129 else
9130 offset = I915_READ(DSPLINOFF(pipe));
9131 }
9132 plane_config->base = base;
9133
9134 val = I915_READ(PIPESRC(pipe));
9135 fb->width = ((val >> 16) & 0xfff) + 1;
9136 fb->height = ((val >> 0) & 0xfff) + 1;
9137
9138 val = I915_READ(DSPSTRIDE(pipe));
9139 fb->pitches[0] = val & 0xffffffc0;
9140
9141 aligned_height = intel_fb_align_height(dev, fb->height,
9142 fb->pixel_format,
9143 fb->modifier[0]);
9144
9145 plane_config->size = fb->pitches[0] * aligned_height;
9146
9147 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9148 pipe_name(pipe), fb->width, fb->height,
9149 fb->bits_per_pixel, base, fb->pitches[0],
9150 plane_config->size);
9151
9152 plane_config->fb = intel_fb;
9153 }
9154
9155 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9156 struct intel_crtc_state *pipe_config)
9157 {
9158 struct drm_device *dev = crtc->base.dev;
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 enum intel_display_power_domain power_domain;
9161 uint32_t tmp;
9162 bool ret;
9163
9164 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9165 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9166 return false;
9167
9168 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9169 pipe_config->shared_dpll = NULL;
9170
9171 ret = false;
9172 tmp = I915_READ(PIPECONF(crtc->pipe));
9173 if (!(tmp & PIPECONF_ENABLE))
9174 goto out;
9175
9176 switch (tmp & PIPECONF_BPC_MASK) {
9177 case PIPECONF_6BPC:
9178 pipe_config->pipe_bpp = 18;
9179 break;
9180 case PIPECONF_8BPC:
9181 pipe_config->pipe_bpp = 24;
9182 break;
9183 case PIPECONF_10BPC:
9184 pipe_config->pipe_bpp = 30;
9185 break;
9186 case PIPECONF_12BPC:
9187 pipe_config->pipe_bpp = 36;
9188 break;
9189 default:
9190 break;
9191 }
9192
9193 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9194 pipe_config->limited_color_range = true;
9195
9196 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9197 struct intel_shared_dpll *pll;
9198 enum intel_dpll_id pll_id;
9199
9200 pipe_config->has_pch_encoder = true;
9201
9202 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9203 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9204 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9205
9206 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9207
9208 if (HAS_PCH_IBX(dev_priv)) {
9209 /*
9210 * The pipe->pch transcoder and pch transcoder->pll
9211 * mapping is fixed.
9212 */
9213 pll_id = (enum intel_dpll_id) crtc->pipe;
9214 } else {
9215 tmp = I915_READ(PCH_DPLL_SEL);
9216 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9217 pll_id = DPLL_ID_PCH_PLL_B;
9218 else
9219 pll_id= DPLL_ID_PCH_PLL_A;
9220 }
9221
9222 pipe_config->shared_dpll =
9223 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9224 pll = pipe_config->shared_dpll;
9225
9226 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9227 &pipe_config->dpll_hw_state));
9228
9229 tmp = pipe_config->dpll_hw_state.dpll;
9230 pipe_config->pixel_multiplier =
9231 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9232 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9233
9234 ironlake_pch_clock_get(crtc, pipe_config);
9235 } else {
9236 pipe_config->pixel_multiplier = 1;
9237 }
9238
9239 intel_get_pipe_timings(crtc, pipe_config);
9240 intel_get_pipe_src_size(crtc, pipe_config);
9241
9242 ironlake_get_pfit_config(crtc, pipe_config);
9243
9244 ret = true;
9245
9246 out:
9247 intel_display_power_put(dev_priv, power_domain);
9248
9249 return ret;
9250 }
9251
9252 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9253 {
9254 struct drm_device *dev = dev_priv->dev;
9255 struct intel_crtc *crtc;
9256
9257 for_each_intel_crtc(dev, crtc)
9258 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9259 pipe_name(crtc->pipe));
9260
9261 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9262 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9263 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9264 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9265 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9266 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9267 "CPU PWM1 enabled\n");
9268 if (IS_HASWELL(dev))
9269 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9270 "CPU PWM2 enabled\n");
9271 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9272 "PCH PWM1 enabled\n");
9273 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9274 "Utility pin enabled\n");
9275 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9276
9277 /*
9278 * In theory we can still leave IRQs enabled, as long as only the HPD
9279 * interrupts remain enabled. We used to check for that, but since it's
9280 * gen-specific and since we only disable LCPLL after we fully disable
9281 * the interrupts, the check below should be enough.
9282 */
9283 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9284 }
9285
9286 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9287 {
9288 struct drm_device *dev = dev_priv->dev;
9289
9290 if (IS_HASWELL(dev))
9291 return I915_READ(D_COMP_HSW);
9292 else
9293 return I915_READ(D_COMP_BDW);
9294 }
9295
9296 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9297 {
9298 struct drm_device *dev = dev_priv->dev;
9299
9300 if (IS_HASWELL(dev)) {
9301 mutex_lock(&dev_priv->rps.hw_lock);
9302 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9303 val))
9304 DRM_ERROR("Failed to write to D_COMP\n");
9305 mutex_unlock(&dev_priv->rps.hw_lock);
9306 } else {
9307 I915_WRITE(D_COMP_BDW, val);
9308 POSTING_READ(D_COMP_BDW);
9309 }
9310 }
9311
9312 /*
9313 * This function implements pieces of two sequences from BSpec:
9314 * - Sequence for display software to disable LCPLL
9315 * - Sequence for display software to allow package C8+
9316 * The steps implemented here are just the steps that actually touch the LCPLL
9317 * register. Callers should take care of disabling all the display engine
9318 * functions, doing the mode unset, fixing interrupts, etc.
9319 */
9320 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9321 bool switch_to_fclk, bool allow_power_down)
9322 {
9323 uint32_t val;
9324
9325 assert_can_disable_lcpll(dev_priv);
9326
9327 val = I915_READ(LCPLL_CTL);
9328
9329 if (switch_to_fclk) {
9330 val |= LCPLL_CD_SOURCE_FCLK;
9331 I915_WRITE(LCPLL_CTL, val);
9332
9333 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9334 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9335 DRM_ERROR("Switching to FCLK failed\n");
9336
9337 val = I915_READ(LCPLL_CTL);
9338 }
9339
9340 val |= LCPLL_PLL_DISABLE;
9341 I915_WRITE(LCPLL_CTL, val);
9342 POSTING_READ(LCPLL_CTL);
9343
9344 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9345 DRM_ERROR("LCPLL still locked\n");
9346
9347 val = hsw_read_dcomp(dev_priv);
9348 val |= D_COMP_COMP_DISABLE;
9349 hsw_write_dcomp(dev_priv, val);
9350 ndelay(100);
9351
9352 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9353 1))
9354 DRM_ERROR("D_COMP RCOMP still in progress\n");
9355
9356 if (allow_power_down) {
9357 val = I915_READ(LCPLL_CTL);
9358 val |= LCPLL_POWER_DOWN_ALLOW;
9359 I915_WRITE(LCPLL_CTL, val);
9360 POSTING_READ(LCPLL_CTL);
9361 }
9362 }
9363
9364 /*
9365 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9366 * source.
9367 */
9368 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9369 {
9370 uint32_t val;
9371
9372 val = I915_READ(LCPLL_CTL);
9373
9374 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9375 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9376 return;
9377
9378 /*
9379 * Make sure we're not on PC8 state before disabling PC8, otherwise
9380 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9381 */
9382 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9383
9384 if (val & LCPLL_POWER_DOWN_ALLOW) {
9385 val &= ~LCPLL_POWER_DOWN_ALLOW;
9386 I915_WRITE(LCPLL_CTL, val);
9387 POSTING_READ(LCPLL_CTL);
9388 }
9389
9390 val = hsw_read_dcomp(dev_priv);
9391 val |= D_COMP_COMP_FORCE;
9392 val &= ~D_COMP_COMP_DISABLE;
9393 hsw_write_dcomp(dev_priv, val);
9394
9395 val = I915_READ(LCPLL_CTL);
9396 val &= ~LCPLL_PLL_DISABLE;
9397 I915_WRITE(LCPLL_CTL, val);
9398
9399 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9400 DRM_ERROR("LCPLL not locked yet\n");
9401
9402 if (val & LCPLL_CD_SOURCE_FCLK) {
9403 val = I915_READ(LCPLL_CTL);
9404 val &= ~LCPLL_CD_SOURCE_FCLK;
9405 I915_WRITE(LCPLL_CTL, val);
9406
9407 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9408 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9409 DRM_ERROR("Switching back to LCPLL failed\n");
9410 }
9411
9412 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9413 intel_update_cdclk(dev_priv->dev);
9414 }
9415
9416 /*
9417 * Package states C8 and deeper are really deep PC states that can only be
9418 * reached when all the devices on the system allow it, so even if the graphics
9419 * device allows PC8+, it doesn't mean the system will actually get to these
9420 * states. Our driver only allows PC8+ when going into runtime PM.
9421 *
9422 * The requirements for PC8+ are that all the outputs are disabled, the power
9423 * well is disabled and most interrupts are disabled, and these are also
9424 * requirements for runtime PM. When these conditions are met, we manually do
9425 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9426 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9427 * hang the machine.
9428 *
9429 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9430 * the state of some registers, so when we come back from PC8+ we need to
9431 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9432 * need to take care of the registers kept by RC6. Notice that this happens even
9433 * if we don't put the device in PCI D3 state (which is what currently happens
9434 * because of the runtime PM support).
9435 *
9436 * For more, read "Display Sequences for Package C8" on the hardware
9437 * documentation.
9438 */
9439 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9440 {
9441 struct drm_device *dev = dev_priv->dev;
9442 uint32_t val;
9443
9444 DRM_DEBUG_KMS("Enabling package C8+\n");
9445
9446 if (HAS_PCH_LPT_LP(dev)) {
9447 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9448 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9449 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9450 }
9451
9452 lpt_disable_clkout_dp(dev);
9453 hsw_disable_lcpll(dev_priv, true, true);
9454 }
9455
9456 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9457 {
9458 struct drm_device *dev = dev_priv->dev;
9459 uint32_t val;
9460
9461 DRM_DEBUG_KMS("Disabling package C8+\n");
9462
9463 hsw_restore_lcpll(dev_priv);
9464 lpt_init_pch_refclk(dev);
9465
9466 if (HAS_PCH_LPT_LP(dev)) {
9467 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9468 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9469 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9470 }
9471 }
9472
9473 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9474 {
9475 struct drm_device *dev = old_state->dev;
9476 struct intel_atomic_state *old_intel_state =
9477 to_intel_atomic_state(old_state);
9478 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9479
9480 broxton_set_cdclk(to_i915(dev), req_cdclk);
9481 }
9482
9483 /* compute the max rate for new configuration */
9484 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9485 {
9486 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9487 struct drm_i915_private *dev_priv = state->dev->dev_private;
9488 struct drm_crtc *crtc;
9489 struct drm_crtc_state *cstate;
9490 struct intel_crtc_state *crtc_state;
9491 unsigned max_pixel_rate = 0, i;
9492 enum pipe pipe;
9493
9494 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9495 sizeof(intel_state->min_pixclk));
9496
9497 for_each_crtc_in_state(state, crtc, cstate, i) {
9498 int pixel_rate;
9499
9500 crtc_state = to_intel_crtc_state(cstate);
9501 if (!crtc_state->base.enable) {
9502 intel_state->min_pixclk[i] = 0;
9503 continue;
9504 }
9505
9506 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9507
9508 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9509 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9510 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9511
9512 intel_state->min_pixclk[i] = pixel_rate;
9513 }
9514
9515 for_each_pipe(dev_priv, pipe)
9516 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9517
9518 return max_pixel_rate;
9519 }
9520
9521 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9522 {
9523 struct drm_i915_private *dev_priv = dev->dev_private;
9524 uint32_t val, data;
9525 int ret;
9526
9527 if (WARN((I915_READ(LCPLL_CTL) &
9528 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9529 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9530 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9531 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9532 "trying to change cdclk frequency with cdclk not enabled\n"))
9533 return;
9534
9535 mutex_lock(&dev_priv->rps.hw_lock);
9536 ret = sandybridge_pcode_write(dev_priv,
9537 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9538 mutex_unlock(&dev_priv->rps.hw_lock);
9539 if (ret) {
9540 DRM_ERROR("failed to inform pcode about cdclk change\n");
9541 return;
9542 }
9543
9544 val = I915_READ(LCPLL_CTL);
9545 val |= LCPLL_CD_SOURCE_FCLK;
9546 I915_WRITE(LCPLL_CTL, val);
9547
9548 if (wait_for_us(I915_READ(LCPLL_CTL) &
9549 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9550 DRM_ERROR("Switching to FCLK failed\n");
9551
9552 val = I915_READ(LCPLL_CTL);
9553 val &= ~LCPLL_CLK_FREQ_MASK;
9554
9555 switch (cdclk) {
9556 case 450000:
9557 val |= LCPLL_CLK_FREQ_450;
9558 data = 0;
9559 break;
9560 case 540000:
9561 val |= LCPLL_CLK_FREQ_54O_BDW;
9562 data = 1;
9563 break;
9564 case 337500:
9565 val |= LCPLL_CLK_FREQ_337_5_BDW;
9566 data = 2;
9567 break;
9568 case 675000:
9569 val |= LCPLL_CLK_FREQ_675_BDW;
9570 data = 3;
9571 break;
9572 default:
9573 WARN(1, "invalid cdclk frequency\n");
9574 return;
9575 }
9576
9577 I915_WRITE(LCPLL_CTL, val);
9578
9579 val = I915_READ(LCPLL_CTL);
9580 val &= ~LCPLL_CD_SOURCE_FCLK;
9581 I915_WRITE(LCPLL_CTL, val);
9582
9583 if (wait_for_us((I915_READ(LCPLL_CTL) &
9584 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9585 DRM_ERROR("Switching back to LCPLL failed\n");
9586
9587 mutex_lock(&dev_priv->rps.hw_lock);
9588 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9589 mutex_unlock(&dev_priv->rps.hw_lock);
9590
9591 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9592
9593 intel_update_cdclk(dev);
9594
9595 WARN(cdclk != dev_priv->cdclk_freq,
9596 "cdclk requested %d kHz but got %d kHz\n",
9597 cdclk, dev_priv->cdclk_freq);
9598 }
9599
9600 static int broadwell_calc_cdclk(int max_pixclk)
9601 {
9602 if (max_pixclk > 540000)
9603 return 675000;
9604 else if (max_pixclk > 450000)
9605 return 540000;
9606 else if (max_pixclk > 337500)
9607 return 450000;
9608 else
9609 return 337500;
9610 }
9611
9612 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9613 {
9614 struct drm_i915_private *dev_priv = to_i915(state->dev);
9615 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9616 int max_pixclk = ilk_max_pixel_rate(state);
9617 int cdclk;
9618
9619 /*
9620 * FIXME should also account for plane ratio
9621 * once 64bpp pixel formats are supported.
9622 */
9623 cdclk = broadwell_calc_cdclk(max_pixclk);
9624
9625 if (cdclk > dev_priv->max_cdclk_freq) {
9626 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9627 cdclk, dev_priv->max_cdclk_freq);
9628 return -EINVAL;
9629 }
9630
9631 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9632 if (!intel_state->active_crtcs)
9633 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9634
9635 return 0;
9636 }
9637
9638 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9639 {
9640 struct drm_device *dev = old_state->dev;
9641 struct intel_atomic_state *old_intel_state =
9642 to_intel_atomic_state(old_state);
9643 unsigned req_cdclk = old_intel_state->dev_cdclk;
9644
9645 broadwell_set_cdclk(dev, req_cdclk);
9646 }
9647
9648 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9649 struct intel_crtc_state *crtc_state)
9650 {
9651 struct intel_encoder *intel_encoder =
9652 intel_ddi_get_crtc_new_encoder(crtc_state);
9653
9654 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9655 if (!intel_ddi_pll_select(crtc, crtc_state))
9656 return -EINVAL;
9657 }
9658
9659 crtc->lowfreq_avail = false;
9660
9661 return 0;
9662 }
9663
9664 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9665 enum port port,
9666 struct intel_crtc_state *pipe_config)
9667 {
9668 enum intel_dpll_id id;
9669
9670 switch (port) {
9671 case PORT_A:
9672 pipe_config->ddi_pll_sel = SKL_DPLL0;
9673 id = DPLL_ID_SKL_DPLL0;
9674 break;
9675 case PORT_B:
9676 pipe_config->ddi_pll_sel = SKL_DPLL1;
9677 id = DPLL_ID_SKL_DPLL1;
9678 break;
9679 case PORT_C:
9680 pipe_config->ddi_pll_sel = SKL_DPLL2;
9681 id = DPLL_ID_SKL_DPLL2;
9682 break;
9683 default:
9684 DRM_ERROR("Incorrect port type\n");
9685 return;
9686 }
9687
9688 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9689 }
9690
9691 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9692 enum port port,
9693 struct intel_crtc_state *pipe_config)
9694 {
9695 enum intel_dpll_id id;
9696 u32 temp;
9697
9698 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9699 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9700
9701 switch (pipe_config->ddi_pll_sel) {
9702 case SKL_DPLL0:
9703 id = DPLL_ID_SKL_DPLL0;
9704 break;
9705 case SKL_DPLL1:
9706 id = DPLL_ID_SKL_DPLL1;
9707 break;
9708 case SKL_DPLL2:
9709 id = DPLL_ID_SKL_DPLL2;
9710 break;
9711 case SKL_DPLL3:
9712 id = DPLL_ID_SKL_DPLL3;
9713 break;
9714 default:
9715 MISSING_CASE(pipe_config->ddi_pll_sel);
9716 return;
9717 }
9718
9719 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9720 }
9721
9722 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9723 enum port port,
9724 struct intel_crtc_state *pipe_config)
9725 {
9726 enum intel_dpll_id id;
9727
9728 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9729
9730 switch (pipe_config->ddi_pll_sel) {
9731 case PORT_CLK_SEL_WRPLL1:
9732 id = DPLL_ID_WRPLL1;
9733 break;
9734 case PORT_CLK_SEL_WRPLL2:
9735 id = DPLL_ID_WRPLL2;
9736 break;
9737 case PORT_CLK_SEL_SPLL:
9738 id = DPLL_ID_SPLL;
9739 break;
9740 case PORT_CLK_SEL_LCPLL_810:
9741 id = DPLL_ID_LCPLL_810;
9742 break;
9743 case PORT_CLK_SEL_LCPLL_1350:
9744 id = DPLL_ID_LCPLL_1350;
9745 break;
9746 case PORT_CLK_SEL_LCPLL_2700:
9747 id = DPLL_ID_LCPLL_2700;
9748 break;
9749 default:
9750 MISSING_CASE(pipe_config->ddi_pll_sel);
9751 /* fall through */
9752 case PORT_CLK_SEL_NONE:
9753 return;
9754 }
9755
9756 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9757 }
9758
9759 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9760 struct intel_crtc_state *pipe_config,
9761 unsigned long *power_domain_mask)
9762 {
9763 struct drm_device *dev = crtc->base.dev;
9764 struct drm_i915_private *dev_priv = dev->dev_private;
9765 enum intel_display_power_domain power_domain;
9766 u32 tmp;
9767
9768 /*
9769 * The pipe->transcoder mapping is fixed with the exception of the eDP
9770 * transcoder handled below.
9771 */
9772 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9773
9774 /*
9775 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9776 * consistency and less surprising code; it's in always on power).
9777 */
9778 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9779 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9780 enum pipe trans_edp_pipe;
9781 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9782 default:
9783 WARN(1, "unknown pipe linked to edp transcoder\n");
9784 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9785 case TRANS_DDI_EDP_INPUT_A_ON:
9786 trans_edp_pipe = PIPE_A;
9787 break;
9788 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9789 trans_edp_pipe = PIPE_B;
9790 break;
9791 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9792 trans_edp_pipe = PIPE_C;
9793 break;
9794 }
9795
9796 if (trans_edp_pipe == crtc->pipe)
9797 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9798 }
9799
9800 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9801 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9802 return false;
9803 *power_domain_mask |= BIT(power_domain);
9804
9805 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9806
9807 return tmp & PIPECONF_ENABLE;
9808 }
9809
9810 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9811 struct intel_crtc_state *pipe_config,
9812 unsigned long *power_domain_mask)
9813 {
9814 struct drm_device *dev = crtc->base.dev;
9815 struct drm_i915_private *dev_priv = dev->dev_private;
9816 enum intel_display_power_domain power_domain;
9817 enum port port;
9818 enum transcoder cpu_transcoder;
9819 u32 tmp;
9820
9821 pipe_config->has_dsi_encoder = false;
9822
9823 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9824 if (port == PORT_A)
9825 cpu_transcoder = TRANSCODER_DSI_A;
9826 else
9827 cpu_transcoder = TRANSCODER_DSI_C;
9828
9829 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9830 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9831 continue;
9832 *power_domain_mask |= BIT(power_domain);
9833
9834 /*
9835 * The PLL needs to be enabled with a valid divider
9836 * configuration, otherwise accessing DSI registers will hang
9837 * the machine. See BSpec North Display Engine
9838 * registers/MIPI[BXT]. We can break out here early, since we
9839 * need the same DSI PLL to be enabled for both DSI ports.
9840 */
9841 if (!intel_dsi_pll_is_enabled(dev_priv))
9842 break;
9843
9844 /* XXX: this works for video mode only */
9845 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9846 if (!(tmp & DPI_ENABLE))
9847 continue;
9848
9849 tmp = I915_READ(MIPI_CTRL(port));
9850 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9851 continue;
9852
9853 pipe_config->cpu_transcoder = cpu_transcoder;
9854 pipe_config->has_dsi_encoder = true;
9855 break;
9856 }
9857
9858 return pipe_config->has_dsi_encoder;
9859 }
9860
9861 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9862 struct intel_crtc_state *pipe_config)
9863 {
9864 struct drm_device *dev = crtc->base.dev;
9865 struct drm_i915_private *dev_priv = dev->dev_private;
9866 struct intel_shared_dpll *pll;
9867 enum port port;
9868 uint32_t tmp;
9869
9870 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9871
9872 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9873
9874 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9875 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9876 else if (IS_BROXTON(dev))
9877 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9878 else
9879 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9880
9881 pll = pipe_config->shared_dpll;
9882 if (pll) {
9883 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9884 &pipe_config->dpll_hw_state));
9885 }
9886
9887 /*
9888 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9889 * DDI E. So just check whether this pipe is wired to DDI E and whether
9890 * the PCH transcoder is on.
9891 */
9892 if (INTEL_INFO(dev)->gen < 9 &&
9893 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9894 pipe_config->has_pch_encoder = true;
9895
9896 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9897 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9898 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9899
9900 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9901 }
9902 }
9903
9904 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9905 struct intel_crtc_state *pipe_config)
9906 {
9907 struct drm_device *dev = crtc->base.dev;
9908 struct drm_i915_private *dev_priv = dev->dev_private;
9909 enum intel_display_power_domain power_domain;
9910 unsigned long power_domain_mask;
9911 bool active;
9912
9913 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9914 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9915 return false;
9916 power_domain_mask = BIT(power_domain);
9917
9918 pipe_config->shared_dpll = NULL;
9919
9920 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9921
9922 if (IS_BROXTON(dev_priv)) {
9923 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9924 &power_domain_mask);
9925 WARN_ON(active && pipe_config->has_dsi_encoder);
9926 if (pipe_config->has_dsi_encoder)
9927 active = true;
9928 }
9929
9930 if (!active)
9931 goto out;
9932
9933 if (!pipe_config->has_dsi_encoder) {
9934 haswell_get_ddi_port_state(crtc, pipe_config);
9935 intel_get_pipe_timings(crtc, pipe_config);
9936 }
9937
9938 intel_get_pipe_src_size(crtc, pipe_config);
9939
9940 pipe_config->gamma_mode =
9941 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9942
9943 if (INTEL_INFO(dev)->gen >= 9) {
9944 skl_init_scalers(dev, crtc, pipe_config);
9945 }
9946
9947 if (INTEL_INFO(dev)->gen >= 9) {
9948 pipe_config->scaler_state.scaler_id = -1;
9949 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9950 }
9951
9952 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9953 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9954 power_domain_mask |= BIT(power_domain);
9955 if (INTEL_INFO(dev)->gen >= 9)
9956 skylake_get_pfit_config(crtc, pipe_config);
9957 else
9958 ironlake_get_pfit_config(crtc, pipe_config);
9959 }
9960
9961 if (IS_HASWELL(dev))
9962 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9963 (I915_READ(IPS_CTL) & IPS_ENABLE);
9964
9965 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9966 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9967 pipe_config->pixel_multiplier =
9968 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9969 } else {
9970 pipe_config->pixel_multiplier = 1;
9971 }
9972
9973 out:
9974 for_each_power_domain(power_domain, power_domain_mask)
9975 intel_display_power_put(dev_priv, power_domain);
9976
9977 return active;
9978 }
9979
9980 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9981 const struct intel_plane_state *plane_state)
9982 {
9983 struct drm_device *dev = crtc->dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9986 uint32_t cntl = 0, size = 0;
9987
9988 if (plane_state && plane_state->visible) {
9989 unsigned int width = plane_state->base.crtc_w;
9990 unsigned int height = plane_state->base.crtc_h;
9991 unsigned int stride = roundup_pow_of_two(width) * 4;
9992
9993 switch (stride) {
9994 default:
9995 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9996 width, stride);
9997 stride = 256;
9998 /* fallthrough */
9999 case 256:
10000 case 512:
10001 case 1024:
10002 case 2048:
10003 break;
10004 }
10005
10006 cntl |= CURSOR_ENABLE |
10007 CURSOR_GAMMA_ENABLE |
10008 CURSOR_FORMAT_ARGB |
10009 CURSOR_STRIDE(stride);
10010
10011 size = (height << 12) | width;
10012 }
10013
10014 if (intel_crtc->cursor_cntl != 0 &&
10015 (intel_crtc->cursor_base != base ||
10016 intel_crtc->cursor_size != size ||
10017 intel_crtc->cursor_cntl != cntl)) {
10018 /* On these chipsets we can only modify the base/size/stride
10019 * whilst the cursor is disabled.
10020 */
10021 I915_WRITE(CURCNTR(PIPE_A), 0);
10022 POSTING_READ(CURCNTR(PIPE_A));
10023 intel_crtc->cursor_cntl = 0;
10024 }
10025
10026 if (intel_crtc->cursor_base != base) {
10027 I915_WRITE(CURBASE(PIPE_A), base);
10028 intel_crtc->cursor_base = base;
10029 }
10030
10031 if (intel_crtc->cursor_size != size) {
10032 I915_WRITE(CURSIZE, size);
10033 intel_crtc->cursor_size = size;
10034 }
10035
10036 if (intel_crtc->cursor_cntl != cntl) {
10037 I915_WRITE(CURCNTR(PIPE_A), cntl);
10038 POSTING_READ(CURCNTR(PIPE_A));
10039 intel_crtc->cursor_cntl = cntl;
10040 }
10041 }
10042
10043 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10044 const struct intel_plane_state *plane_state)
10045 {
10046 struct drm_device *dev = crtc->dev;
10047 struct drm_i915_private *dev_priv = dev->dev_private;
10048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10049 int pipe = intel_crtc->pipe;
10050 uint32_t cntl = 0;
10051
10052 if (plane_state && plane_state->visible) {
10053 cntl = MCURSOR_GAMMA_ENABLE;
10054 switch (plane_state->base.crtc_w) {
10055 case 64:
10056 cntl |= CURSOR_MODE_64_ARGB_AX;
10057 break;
10058 case 128:
10059 cntl |= CURSOR_MODE_128_ARGB_AX;
10060 break;
10061 case 256:
10062 cntl |= CURSOR_MODE_256_ARGB_AX;
10063 break;
10064 default:
10065 MISSING_CASE(plane_state->base.crtc_w);
10066 return;
10067 }
10068 cntl |= pipe << 28; /* Connect to correct pipe */
10069
10070 if (HAS_DDI(dev))
10071 cntl |= CURSOR_PIPE_CSC_ENABLE;
10072
10073 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10074 cntl |= CURSOR_ROTATE_180;
10075 }
10076
10077 if (intel_crtc->cursor_cntl != cntl) {
10078 I915_WRITE(CURCNTR(pipe), cntl);
10079 POSTING_READ(CURCNTR(pipe));
10080 intel_crtc->cursor_cntl = cntl;
10081 }
10082
10083 /* and commit changes on next vblank */
10084 I915_WRITE(CURBASE(pipe), base);
10085 POSTING_READ(CURBASE(pipe));
10086
10087 intel_crtc->cursor_base = base;
10088 }
10089
10090 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10091 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10092 const struct intel_plane_state *plane_state)
10093 {
10094 struct drm_device *dev = crtc->dev;
10095 struct drm_i915_private *dev_priv = dev->dev_private;
10096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10097 int pipe = intel_crtc->pipe;
10098 u32 base = intel_crtc->cursor_addr;
10099 u32 pos = 0;
10100
10101 if (plane_state) {
10102 int x = plane_state->base.crtc_x;
10103 int y = plane_state->base.crtc_y;
10104
10105 if (x < 0) {
10106 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10107 x = -x;
10108 }
10109 pos |= x << CURSOR_X_SHIFT;
10110
10111 if (y < 0) {
10112 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10113 y = -y;
10114 }
10115 pos |= y << CURSOR_Y_SHIFT;
10116
10117 /* ILK+ do this automagically */
10118 if (HAS_GMCH_DISPLAY(dev) &&
10119 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10120 base += (plane_state->base.crtc_h *
10121 plane_state->base.crtc_w - 1) * 4;
10122 }
10123 }
10124
10125 I915_WRITE(CURPOS(pipe), pos);
10126
10127 if (IS_845G(dev) || IS_I865G(dev))
10128 i845_update_cursor(crtc, base, plane_state);
10129 else
10130 i9xx_update_cursor(crtc, base, plane_state);
10131 }
10132
10133 static bool cursor_size_ok(struct drm_device *dev,
10134 uint32_t width, uint32_t height)
10135 {
10136 if (width == 0 || height == 0)
10137 return false;
10138
10139 /*
10140 * 845g/865g are special in that they are only limited by
10141 * the width of their cursors, the height is arbitrary up to
10142 * the precision of the register. Everything else requires
10143 * square cursors, limited to a few power-of-two sizes.
10144 */
10145 if (IS_845G(dev) || IS_I865G(dev)) {
10146 if ((width & 63) != 0)
10147 return false;
10148
10149 if (width > (IS_845G(dev) ? 64 : 512))
10150 return false;
10151
10152 if (height > 1023)
10153 return false;
10154 } else {
10155 switch (width | height) {
10156 case 256:
10157 case 128:
10158 if (IS_GEN2(dev))
10159 return false;
10160 case 64:
10161 break;
10162 default:
10163 return false;
10164 }
10165 }
10166
10167 return true;
10168 }
10169
10170 /* VESA 640x480x72Hz mode to set on the pipe */
10171 static struct drm_display_mode load_detect_mode = {
10172 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10173 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10174 };
10175
10176 struct drm_framebuffer *
10177 __intel_framebuffer_create(struct drm_device *dev,
10178 struct drm_mode_fb_cmd2 *mode_cmd,
10179 struct drm_i915_gem_object *obj)
10180 {
10181 struct intel_framebuffer *intel_fb;
10182 int ret;
10183
10184 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10185 if (!intel_fb)
10186 return ERR_PTR(-ENOMEM);
10187
10188 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10189 if (ret)
10190 goto err;
10191
10192 return &intel_fb->base;
10193
10194 err:
10195 kfree(intel_fb);
10196 return ERR_PTR(ret);
10197 }
10198
10199 static struct drm_framebuffer *
10200 intel_framebuffer_create(struct drm_device *dev,
10201 struct drm_mode_fb_cmd2 *mode_cmd,
10202 struct drm_i915_gem_object *obj)
10203 {
10204 struct drm_framebuffer *fb;
10205 int ret;
10206
10207 ret = i915_mutex_lock_interruptible(dev);
10208 if (ret)
10209 return ERR_PTR(ret);
10210 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10211 mutex_unlock(&dev->struct_mutex);
10212
10213 return fb;
10214 }
10215
10216 static u32
10217 intel_framebuffer_pitch_for_width(int width, int bpp)
10218 {
10219 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10220 return ALIGN(pitch, 64);
10221 }
10222
10223 static u32
10224 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10225 {
10226 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10227 return PAGE_ALIGN(pitch * mode->vdisplay);
10228 }
10229
10230 static struct drm_framebuffer *
10231 intel_framebuffer_create_for_mode(struct drm_device *dev,
10232 struct drm_display_mode *mode,
10233 int depth, int bpp)
10234 {
10235 struct drm_framebuffer *fb;
10236 struct drm_i915_gem_object *obj;
10237 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10238
10239 obj = i915_gem_object_create(dev,
10240 intel_framebuffer_size_for_mode(mode, bpp));
10241 if (IS_ERR(obj))
10242 return ERR_CAST(obj);
10243
10244 mode_cmd.width = mode->hdisplay;
10245 mode_cmd.height = mode->vdisplay;
10246 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10247 bpp);
10248 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10249
10250 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10251 if (IS_ERR(fb))
10252 drm_gem_object_unreference_unlocked(&obj->base);
10253
10254 return fb;
10255 }
10256
10257 static struct drm_framebuffer *
10258 mode_fits_in_fbdev(struct drm_device *dev,
10259 struct drm_display_mode *mode)
10260 {
10261 #ifdef CONFIG_DRM_FBDEV_EMULATION
10262 struct drm_i915_private *dev_priv = dev->dev_private;
10263 struct drm_i915_gem_object *obj;
10264 struct drm_framebuffer *fb;
10265
10266 if (!dev_priv->fbdev)
10267 return NULL;
10268
10269 if (!dev_priv->fbdev->fb)
10270 return NULL;
10271
10272 obj = dev_priv->fbdev->fb->obj;
10273 BUG_ON(!obj);
10274
10275 fb = &dev_priv->fbdev->fb->base;
10276 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10277 fb->bits_per_pixel))
10278 return NULL;
10279
10280 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10281 return NULL;
10282
10283 drm_framebuffer_reference(fb);
10284 return fb;
10285 #else
10286 return NULL;
10287 #endif
10288 }
10289
10290 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10291 struct drm_crtc *crtc,
10292 struct drm_display_mode *mode,
10293 struct drm_framebuffer *fb,
10294 int x, int y)
10295 {
10296 struct drm_plane_state *plane_state;
10297 int hdisplay, vdisplay;
10298 int ret;
10299
10300 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10301 if (IS_ERR(plane_state))
10302 return PTR_ERR(plane_state);
10303
10304 if (mode)
10305 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10306 else
10307 hdisplay = vdisplay = 0;
10308
10309 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10310 if (ret)
10311 return ret;
10312 drm_atomic_set_fb_for_plane(plane_state, fb);
10313 plane_state->crtc_x = 0;
10314 plane_state->crtc_y = 0;
10315 plane_state->crtc_w = hdisplay;
10316 plane_state->crtc_h = vdisplay;
10317 plane_state->src_x = x << 16;
10318 plane_state->src_y = y << 16;
10319 plane_state->src_w = hdisplay << 16;
10320 plane_state->src_h = vdisplay << 16;
10321
10322 return 0;
10323 }
10324
10325 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10326 struct drm_display_mode *mode,
10327 struct intel_load_detect_pipe *old,
10328 struct drm_modeset_acquire_ctx *ctx)
10329 {
10330 struct intel_crtc *intel_crtc;
10331 struct intel_encoder *intel_encoder =
10332 intel_attached_encoder(connector);
10333 struct drm_crtc *possible_crtc;
10334 struct drm_encoder *encoder = &intel_encoder->base;
10335 struct drm_crtc *crtc = NULL;
10336 struct drm_device *dev = encoder->dev;
10337 struct drm_framebuffer *fb;
10338 struct drm_mode_config *config = &dev->mode_config;
10339 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10340 struct drm_connector_state *connector_state;
10341 struct intel_crtc_state *crtc_state;
10342 int ret, i = -1;
10343
10344 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10345 connector->base.id, connector->name,
10346 encoder->base.id, encoder->name);
10347
10348 old->restore_state = NULL;
10349
10350 retry:
10351 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10352 if (ret)
10353 goto fail;
10354
10355 /*
10356 * Algorithm gets a little messy:
10357 *
10358 * - if the connector already has an assigned crtc, use it (but make
10359 * sure it's on first)
10360 *
10361 * - try to find the first unused crtc that can drive this connector,
10362 * and use that if we find one
10363 */
10364
10365 /* See if we already have a CRTC for this connector */
10366 if (connector->state->crtc) {
10367 crtc = connector->state->crtc;
10368
10369 ret = drm_modeset_lock(&crtc->mutex, ctx);
10370 if (ret)
10371 goto fail;
10372
10373 /* Make sure the crtc and connector are running */
10374 goto found;
10375 }
10376
10377 /* Find an unused one (if possible) */
10378 for_each_crtc(dev, possible_crtc) {
10379 i++;
10380 if (!(encoder->possible_crtcs & (1 << i)))
10381 continue;
10382
10383 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10384 if (ret)
10385 goto fail;
10386
10387 if (possible_crtc->state->enable) {
10388 drm_modeset_unlock(&possible_crtc->mutex);
10389 continue;
10390 }
10391
10392 crtc = possible_crtc;
10393 break;
10394 }
10395
10396 /*
10397 * If we didn't find an unused CRTC, don't use any.
10398 */
10399 if (!crtc) {
10400 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10401 goto fail;
10402 }
10403
10404 found:
10405 intel_crtc = to_intel_crtc(crtc);
10406
10407 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10408 if (ret)
10409 goto fail;
10410
10411 state = drm_atomic_state_alloc(dev);
10412 restore_state = drm_atomic_state_alloc(dev);
10413 if (!state || !restore_state) {
10414 ret = -ENOMEM;
10415 goto fail;
10416 }
10417
10418 state->acquire_ctx = ctx;
10419 restore_state->acquire_ctx = ctx;
10420
10421 connector_state = drm_atomic_get_connector_state(state, connector);
10422 if (IS_ERR(connector_state)) {
10423 ret = PTR_ERR(connector_state);
10424 goto fail;
10425 }
10426
10427 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10428 if (ret)
10429 goto fail;
10430
10431 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10432 if (IS_ERR(crtc_state)) {
10433 ret = PTR_ERR(crtc_state);
10434 goto fail;
10435 }
10436
10437 crtc_state->base.active = crtc_state->base.enable = true;
10438
10439 if (!mode)
10440 mode = &load_detect_mode;
10441
10442 /* We need a framebuffer large enough to accommodate all accesses
10443 * that the plane may generate whilst we perform load detection.
10444 * We can not rely on the fbcon either being present (we get called
10445 * during its initialisation to detect all boot displays, or it may
10446 * not even exist) or that it is large enough to satisfy the
10447 * requested mode.
10448 */
10449 fb = mode_fits_in_fbdev(dev, mode);
10450 if (fb == NULL) {
10451 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10452 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10453 } else
10454 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10455 if (IS_ERR(fb)) {
10456 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10457 goto fail;
10458 }
10459
10460 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10461 if (ret)
10462 goto fail;
10463
10464 drm_framebuffer_unreference(fb);
10465
10466 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10467 if (ret)
10468 goto fail;
10469
10470 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10471 if (!ret)
10472 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10473 if (!ret)
10474 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10475 if (ret) {
10476 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10477 goto fail;
10478 }
10479
10480 ret = drm_atomic_commit(state);
10481 if (ret) {
10482 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10483 goto fail;
10484 }
10485
10486 old->restore_state = restore_state;
10487
10488 /* let the connector get through one full cycle before testing */
10489 intel_wait_for_vblank(dev, intel_crtc->pipe);
10490 return true;
10491
10492 fail:
10493 drm_atomic_state_free(state);
10494 drm_atomic_state_free(restore_state);
10495 restore_state = state = NULL;
10496
10497 if (ret == -EDEADLK) {
10498 drm_modeset_backoff(ctx);
10499 goto retry;
10500 }
10501
10502 return false;
10503 }
10504
10505 void intel_release_load_detect_pipe(struct drm_connector *connector,
10506 struct intel_load_detect_pipe *old,
10507 struct drm_modeset_acquire_ctx *ctx)
10508 {
10509 struct intel_encoder *intel_encoder =
10510 intel_attached_encoder(connector);
10511 struct drm_encoder *encoder = &intel_encoder->base;
10512 struct drm_atomic_state *state = old->restore_state;
10513 int ret;
10514
10515 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10516 connector->base.id, connector->name,
10517 encoder->base.id, encoder->name);
10518
10519 if (!state)
10520 return;
10521
10522 ret = drm_atomic_commit(state);
10523 if (ret) {
10524 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10525 drm_atomic_state_free(state);
10526 }
10527 }
10528
10529 static int i9xx_pll_refclk(struct drm_device *dev,
10530 const struct intel_crtc_state *pipe_config)
10531 {
10532 struct drm_i915_private *dev_priv = dev->dev_private;
10533 u32 dpll = pipe_config->dpll_hw_state.dpll;
10534
10535 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10536 return dev_priv->vbt.lvds_ssc_freq;
10537 else if (HAS_PCH_SPLIT(dev))
10538 return 120000;
10539 else if (!IS_GEN2(dev))
10540 return 96000;
10541 else
10542 return 48000;
10543 }
10544
10545 /* Returns the clock of the currently programmed mode of the given pipe. */
10546 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10547 struct intel_crtc_state *pipe_config)
10548 {
10549 struct drm_device *dev = crtc->base.dev;
10550 struct drm_i915_private *dev_priv = dev->dev_private;
10551 int pipe = pipe_config->cpu_transcoder;
10552 u32 dpll = pipe_config->dpll_hw_state.dpll;
10553 u32 fp;
10554 struct dpll clock;
10555 int port_clock;
10556 int refclk = i9xx_pll_refclk(dev, pipe_config);
10557
10558 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10559 fp = pipe_config->dpll_hw_state.fp0;
10560 else
10561 fp = pipe_config->dpll_hw_state.fp1;
10562
10563 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10564 if (IS_PINEVIEW(dev)) {
10565 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10566 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10567 } else {
10568 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10569 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10570 }
10571
10572 if (!IS_GEN2(dev)) {
10573 if (IS_PINEVIEW(dev))
10574 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10575 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10576 else
10577 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10578 DPLL_FPA01_P1_POST_DIV_SHIFT);
10579
10580 switch (dpll & DPLL_MODE_MASK) {
10581 case DPLLB_MODE_DAC_SERIAL:
10582 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10583 5 : 10;
10584 break;
10585 case DPLLB_MODE_LVDS:
10586 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10587 7 : 14;
10588 break;
10589 default:
10590 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10591 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10592 return;
10593 }
10594
10595 if (IS_PINEVIEW(dev))
10596 port_clock = pnv_calc_dpll_params(refclk, &clock);
10597 else
10598 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10599 } else {
10600 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10601 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10602
10603 if (is_lvds) {
10604 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10605 DPLL_FPA01_P1_POST_DIV_SHIFT);
10606
10607 if (lvds & LVDS_CLKB_POWER_UP)
10608 clock.p2 = 7;
10609 else
10610 clock.p2 = 14;
10611 } else {
10612 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10613 clock.p1 = 2;
10614 else {
10615 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10616 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10617 }
10618 if (dpll & PLL_P2_DIVIDE_BY_4)
10619 clock.p2 = 4;
10620 else
10621 clock.p2 = 2;
10622 }
10623
10624 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10625 }
10626
10627 /*
10628 * This value includes pixel_multiplier. We will use
10629 * port_clock to compute adjusted_mode.crtc_clock in the
10630 * encoder's get_config() function.
10631 */
10632 pipe_config->port_clock = port_clock;
10633 }
10634
10635 int intel_dotclock_calculate(int link_freq,
10636 const struct intel_link_m_n *m_n)
10637 {
10638 /*
10639 * The calculation for the data clock is:
10640 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10641 * But we want to avoid losing precison if possible, so:
10642 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10643 *
10644 * and the link clock is simpler:
10645 * link_clock = (m * link_clock) / n
10646 */
10647
10648 if (!m_n->link_n)
10649 return 0;
10650
10651 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10652 }
10653
10654 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10655 struct intel_crtc_state *pipe_config)
10656 {
10657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10658
10659 /* read out port_clock from the DPLL */
10660 i9xx_crtc_clock_get(crtc, pipe_config);
10661
10662 /*
10663 * In case there is an active pipe without active ports,
10664 * we may need some idea for the dotclock anyway.
10665 * Calculate one based on the FDI configuration.
10666 */
10667 pipe_config->base.adjusted_mode.crtc_clock =
10668 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10669 &pipe_config->fdi_m_n);
10670 }
10671
10672 /** Returns the currently programmed mode of the given pipe. */
10673 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10674 struct drm_crtc *crtc)
10675 {
10676 struct drm_i915_private *dev_priv = dev->dev_private;
10677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10678 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10679 struct drm_display_mode *mode;
10680 struct intel_crtc_state *pipe_config;
10681 int htot = I915_READ(HTOTAL(cpu_transcoder));
10682 int hsync = I915_READ(HSYNC(cpu_transcoder));
10683 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10684 int vsync = I915_READ(VSYNC(cpu_transcoder));
10685 enum pipe pipe = intel_crtc->pipe;
10686
10687 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10688 if (!mode)
10689 return NULL;
10690
10691 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10692 if (!pipe_config) {
10693 kfree(mode);
10694 return NULL;
10695 }
10696
10697 /*
10698 * Construct a pipe_config sufficient for getting the clock info
10699 * back out of crtc_clock_get.
10700 *
10701 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10702 * to use a real value here instead.
10703 */
10704 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10705 pipe_config->pixel_multiplier = 1;
10706 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10707 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10708 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10709 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10710
10711 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10712 mode->hdisplay = (htot & 0xffff) + 1;
10713 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10714 mode->hsync_start = (hsync & 0xffff) + 1;
10715 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10716 mode->vdisplay = (vtot & 0xffff) + 1;
10717 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10718 mode->vsync_start = (vsync & 0xffff) + 1;
10719 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10720
10721 drm_mode_set_name(mode);
10722
10723 kfree(pipe_config);
10724
10725 return mode;
10726 }
10727
10728 void intel_mark_busy(struct drm_i915_private *dev_priv)
10729 {
10730 if (dev_priv->mm.busy)
10731 return;
10732
10733 intel_runtime_pm_get(dev_priv);
10734 i915_update_gfx_val(dev_priv);
10735 if (INTEL_GEN(dev_priv) >= 6)
10736 gen6_rps_busy(dev_priv);
10737 dev_priv->mm.busy = true;
10738 }
10739
10740 void intel_mark_idle(struct drm_i915_private *dev_priv)
10741 {
10742 if (!dev_priv->mm.busy)
10743 return;
10744
10745 dev_priv->mm.busy = false;
10746
10747 if (INTEL_GEN(dev_priv) >= 6)
10748 gen6_rps_idle(dev_priv);
10749
10750 intel_runtime_pm_put(dev_priv);
10751 }
10752
10753 void intel_free_flip_work(struct intel_flip_work *work)
10754 {
10755 kfree(work->old_connector_state);
10756 kfree(work->new_connector_state);
10757 kfree(work);
10758 }
10759
10760 static void intel_crtc_destroy(struct drm_crtc *crtc)
10761 {
10762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10763 struct drm_device *dev = crtc->dev;
10764 struct intel_flip_work *work;
10765
10766 spin_lock_irq(&dev->event_lock);
10767 while (!list_empty(&intel_crtc->flip_work)) {
10768 work = list_first_entry(&intel_crtc->flip_work,
10769 struct intel_flip_work, head);
10770 list_del_init(&work->head);
10771 spin_unlock_irq(&dev->event_lock);
10772
10773 cancel_work_sync(&work->mmio_work);
10774 cancel_work_sync(&work->unpin_work);
10775 intel_free_flip_work(work);
10776
10777 spin_lock_irq(&dev->event_lock);
10778 }
10779 spin_unlock_irq(&dev->event_lock);
10780
10781 drm_crtc_cleanup(crtc);
10782
10783 kfree(intel_crtc);
10784 }
10785
10786 static void intel_crtc_post_flip_update(struct intel_flip_work *work,
10787 struct drm_crtc *crtc)
10788 {
10789 struct intel_crtc_state *crtc_state = work->new_crtc_state;
10790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10791
10792 if (crtc_state->disable_cxsr)
10793 intel_crtc->wm.cxsr_allowed = true;
10794
10795 if (crtc_state->update_wm_post && crtc_state->base.active)
10796 intel_update_watermarks(crtc);
10797
10798 if (work->num_planes > 0 &&
10799 work->old_plane_state[0]->base.plane == crtc->primary) {
10800 struct intel_plane_state *plane_state =
10801 work->new_plane_state[0];
10802
10803 if (plane_state->visible &&
10804 (needs_modeset(&crtc_state->base) ||
10805 !work->old_plane_state[0]->visible))
10806 intel_post_enable_primary(crtc);
10807 }
10808 }
10809
10810 static void intel_unpin_work_fn(struct work_struct *__work)
10811 {
10812 struct intel_flip_work *work =
10813 container_of(__work, struct intel_flip_work, unpin_work);
10814 struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
10815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10816 struct drm_device *dev = crtc->dev;
10817 struct drm_i915_private *dev_priv = dev->dev_private;
10818 int i;
10819
10820 if (work->fb_bits)
10821 intel_frontbuffer_flip_complete(dev, work->fb_bits);
10822
10823 /*
10824 * Unless work->can_async_unpin is false, there's no way to ensure
10825 * that work->new_crtc_state contains valid memory during unpin
10826 * because intel_atomic_commit may free it before this runs.
10827 */
10828 if (!work->can_async_unpin) {
10829 intel_crtc_post_flip_update(work, crtc);
10830
10831 if (dev_priv->display.optimize_watermarks)
10832 dev_priv->display.optimize_watermarks(work->new_crtc_state);
10833 }
10834
10835 if (work->fb_bits & to_intel_plane(crtc->primary)->frontbuffer_bit)
10836 intel_fbc_post_update(intel_crtc);
10837
10838 if (work->put_power_domains)
10839 modeset_put_power_domains(dev_priv, work->put_power_domains);
10840
10841 /* Make sure mmio work is completely finished before freeing all state here. */
10842 flush_work(&work->mmio_work);
10843
10844 if (!work->can_async_unpin &&
10845 (work->new_crtc_state->update_pipe ||
10846 needs_modeset(&work->new_crtc_state->base))) {
10847 /* This must be called before work is unpinned for serialization. */
10848 intel_modeset_verify_crtc(crtc, &work->old_crtc_state->base,
10849 &work->new_crtc_state->base);
10850
10851 for (i = 0; i < work->num_new_connectors; i++) {
10852 struct drm_connector_state *conn_state =
10853 work->new_connector_state[i];
10854 struct drm_connector *con = conn_state->connector;
10855
10856 WARN_ON(!con);
10857
10858 intel_connector_verify_state(to_intel_connector(con),
10859 conn_state);
10860 }
10861 }
10862
10863 for (i = 0; i < work->num_old_connectors; i++) {
10864 struct drm_connector_state *old_con_state =
10865 work->old_connector_state[i];
10866 struct drm_connector *con =
10867 old_con_state->connector;
10868
10869 con->funcs->atomic_destroy_state(con, old_con_state);
10870 }
10871
10872 if (!work->can_async_unpin || !list_empty(&work->head)) {
10873 spin_lock_irq(&dev->event_lock);
10874 WARN(list_empty(&work->head) != work->can_async_unpin,
10875 "[CRTC:%i] Pin work %p async %i with %i planes, active %i -> %i ms %i\n",
10876 crtc->base.id, work, work->can_async_unpin, work->num_planes,
10877 work->old_crtc_state->base.active, work->new_crtc_state->base.active,
10878 needs_modeset(&work->new_crtc_state->base));
10879
10880 if (!list_empty(&work->head))
10881 list_del(&work->head);
10882
10883 wake_up_all(&dev_priv->pending_flip_queue);
10884 spin_unlock_irq(&dev->event_lock);
10885 }
10886
10887 /* New crtc_state freed? */
10888 if (work->free_new_crtc_state)
10889 intel_crtc_destroy_state(crtc, &work->new_crtc_state->base);
10890
10891 intel_crtc_destroy_state(crtc, &work->old_crtc_state->base);
10892
10893 for (i = 0; i < work->num_planes; i++) {
10894 struct intel_plane_state *old_plane_state =
10895 work->old_plane_state[i];
10896 struct drm_framebuffer *old_fb = old_plane_state->base.fb;
10897 struct drm_plane *plane = old_plane_state->base.plane;
10898 struct drm_i915_gem_request *req;
10899
10900 req = old_plane_state->wait_req;
10901 old_plane_state->wait_req = NULL;
10902 if (req)
10903 i915_gem_request_unreference(req);
10904
10905 fence_put(old_plane_state->base.fence);
10906 old_plane_state->base.fence = NULL;
10907
10908 if (old_fb &&
10909 (plane->type != DRM_PLANE_TYPE_CURSOR ||
10910 !INTEL_INFO(dev_priv)->cursor_needs_physical)) {
10911 mutex_lock(&dev->struct_mutex);
10912 intel_unpin_fb_obj(old_fb, old_plane_state->base.rotation);
10913 mutex_unlock(&dev->struct_mutex);
10914 }
10915
10916 intel_plane_destroy_state(plane, &old_plane_state->base);
10917 }
10918
10919 if (!WARN_ON(atomic_read(&intel_crtc->unpin_work_count) == 0))
10920 atomic_dec(&intel_crtc->unpin_work_count);
10921
10922 intel_free_flip_work(work);
10923 }
10924
10925
10926 static bool pageflip_finished(struct intel_crtc *crtc,
10927 struct intel_flip_work *work)
10928 {
10929 if (!atomic_read(&work->pending))
10930 return false;
10931
10932 smp_rmb();
10933
10934 /*
10935 * MMIO work completes when vblank is different from
10936 * flip_queued_vblank.
10937 */
10938 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10939 }
10940
10941 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10942 {
10943 struct drm_device *dev = dev_priv->dev;
10944 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10946 struct intel_flip_work *work;
10947 unsigned long flags;
10948
10949 /* Ignore early vblank irqs */
10950 if (!crtc)
10951 return;
10952
10953 /*
10954 * This is called both by irq handlers and the reset code (to complete
10955 * lost pageflips) so needs the full irqsave spinlocks.
10956 */
10957 spin_lock_irqsave(&dev->event_lock, flags);
10958 while (!list_empty(&intel_crtc->flip_work)) {
10959 work = list_first_entry(&intel_crtc->flip_work,
10960 struct intel_flip_work,
10961 head);
10962
10963 if (!pageflip_finished(intel_crtc, work) ||
10964 work_busy(&work->unpin_work))
10965 break;
10966
10967 page_flip_completed(intel_crtc, work);
10968 }
10969 spin_unlock_irqrestore(&dev->event_lock, flags);
10970 }
10971
10972 static void intel_mmio_flip_work_func(struct work_struct *w)
10973 {
10974 struct intel_flip_work *work =
10975 container_of(w, struct intel_flip_work, mmio_work);
10976 struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
10977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10978 struct intel_crtc_state *crtc_state = work->new_crtc_state;
10979 struct drm_device *dev = crtc->dev;
10980 struct drm_i915_private *dev_priv = dev->dev_private;
10981 struct drm_i915_gem_request *req;
10982 int i, ret;
10983
10984 if (!needs_modeset(&crtc_state->base) && crtc_state->update_pipe) {
10985 work->put_power_domains =
10986 modeset_get_crtc_power_domains(crtc, crtc_state);
10987 }
10988
10989 for (i = 0; i < work->num_planes; i++) {
10990 struct intel_plane_state *old_plane_state = work->old_plane_state[i];
10991
10992 /* For framebuffer backed by dmabuf, wait for fence */
10993 if (old_plane_state->base.fence)
10994 WARN_ON(fence_wait(old_plane_state->base.fence, false) < 0);
10995
10996 req = old_plane_state->wait_req;
10997 if (!req)
10998 continue;
10999
11000 WARN_ON(__i915_wait_request(req, false, NULL,
11001 &dev_priv->rps.mmioflips));
11002 }
11003
11004 ret = drm_crtc_vblank_get(crtc);
11005 I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
11006
11007 if (work->num_planes &&
11008 work->old_plane_state[0]->base.plane == crtc->primary)
11009 intel_fbc_enable(intel_crtc, work->new_crtc_state, work->new_plane_state[0]);
11010
11011 intel_frontbuffer_flip_prepare(dev, work->fb_bits);
11012
11013 intel_pipe_update_start(intel_crtc);
11014 if (!needs_modeset(&crtc_state->base)) {
11015 if (crtc_state->base.color_mgmt_changed || crtc_state->update_pipe) {
11016 intel_color_set_csc(&crtc_state->base);
11017 intel_color_load_luts(&crtc_state->base);
11018 }
11019
11020 if (crtc_state->update_pipe)
11021 intel_update_pipe_config(intel_crtc, work->old_crtc_state);
11022 else if (INTEL_INFO(dev)->gen >= 9)
11023 skl_detach_scalers(intel_crtc);
11024 }
11025
11026 for (i = 0; i < work->num_planes; i++) {
11027 struct intel_plane_state *new_plane_state = work->new_plane_state[i];
11028 struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
11029
11030 if (new_plane_state->visible)
11031 plane->update_plane(&plane->base, crtc_state, new_plane_state);
11032 else
11033 plane->disable_plane(&plane->base, crtc);
11034 }
11035
11036 intel_pipe_update_end(intel_crtc, work);
11037 }
11038
11039 /**
11040 * intel_wm_need_update - Check whether watermarks need updating
11041 * @plane: drm plane
11042 * @state: new plane state
11043 *
11044 * Check current plane state versus the new one to determine whether
11045 * watermarks need to be recalculated.
11046 *
11047 * Returns true or false.
11048 */
11049 static bool intel_wm_need_update(struct drm_plane *plane,
11050 struct drm_plane_state *state)
11051 {
11052 struct intel_plane_state *new = to_intel_plane_state(state);
11053 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11054
11055 /* Update watermarks on tiling or size changes. */
11056 if (new->visible != cur->visible)
11057 return true;
11058
11059 if (!cur->base.fb || !new->base.fb)
11060 return false;
11061
11062 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11063 cur->base.rotation != new->base.rotation ||
11064 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11065 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11066 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11067 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11068 return true;
11069
11070 return false;
11071 }
11072
11073 static bool needs_scaling(struct intel_plane_state *state)
11074 {
11075 int src_w = drm_rect_width(&state->src) >> 16;
11076 int src_h = drm_rect_height(&state->src) >> 16;
11077 int dst_w = drm_rect_width(&state->dst);
11078 int dst_h = drm_rect_height(&state->dst);
11079
11080 return (src_w != dst_w || src_h != dst_h);
11081 }
11082
11083 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11084 struct drm_plane_state *plane_state)
11085 {
11086 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11087 struct drm_crtc *crtc = crtc_state->crtc;
11088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11089 struct drm_plane *plane = plane_state->plane;
11090 struct drm_device *dev = crtc->dev;
11091 struct drm_i915_private *dev_priv = to_i915(dev);
11092 struct intel_plane_state *old_plane_state =
11093 to_intel_plane_state(plane->state);
11094 int idx = intel_crtc->base.base.id, ret;
11095 bool mode_changed = needs_modeset(crtc_state);
11096 bool was_crtc_enabled = crtc->state->active;
11097 bool is_crtc_enabled = crtc_state->active;
11098 bool turn_off, turn_on, visible, was_visible;
11099 struct drm_framebuffer *fb = plane_state->fb;
11100
11101 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11102 plane->type != DRM_PLANE_TYPE_CURSOR) {
11103 ret = skl_update_scaler_plane(
11104 to_intel_crtc_state(crtc_state),
11105 to_intel_plane_state(plane_state));
11106 if (ret)
11107 return ret;
11108 }
11109
11110 was_visible = old_plane_state->visible;
11111 visible = to_intel_plane_state(plane_state)->visible;
11112
11113 if (!was_crtc_enabled && WARN_ON(was_visible))
11114 was_visible = false;
11115
11116 /*
11117 * Visibility is calculated as if the crtc was on, but
11118 * after scaler setup everything depends on it being off
11119 * when the crtc isn't active.
11120 *
11121 * FIXME this is wrong for watermarks. Watermarks should also
11122 * be computed as if the pipe would be active. Perhaps move
11123 * per-plane wm computation to the .check_plane() hook, and
11124 * only combine the results from all planes in the current place?
11125 */
11126 if (!is_crtc_enabled)
11127 to_intel_plane_state(plane_state)->visible = visible = false;
11128
11129 if (!was_visible && !visible)
11130 return 0;
11131
11132 if (fb != old_plane_state->base.fb)
11133 pipe_config->fb_changed = true;
11134
11135 turn_off = was_visible && (!visible || mode_changed);
11136 turn_on = visible && (!was_visible || mode_changed);
11137
11138 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11139 plane->base.id, fb ? fb->base.id : -1);
11140
11141 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11142 plane->base.id, was_visible, visible,
11143 turn_off, turn_on, mode_changed);
11144
11145 if (turn_on) {
11146 pipe_config->update_wm_pre = true;
11147
11148 /* must disable cxsr around plane enable/disable */
11149 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11150 pipe_config->disable_cxsr = true;
11151 } else if (turn_off) {
11152 pipe_config->update_wm_post = true;
11153
11154 /* must disable cxsr around plane enable/disable */
11155 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11156 pipe_config->disable_cxsr = true;
11157 } else if (intel_wm_need_update(plane, plane_state)) {
11158 /* FIXME bollocks */
11159 pipe_config->update_wm_pre = true;
11160 pipe_config->update_wm_post = true;
11161 }
11162
11163 /* Pre-gen9 platforms need two-step watermark updates */
11164 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11165 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11166 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11167
11168 if (visible || was_visible)
11169 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11170
11171 /*
11172 * WaCxSRDisabledForSpriteScaling:ivb
11173 *
11174 * cstate->update_wm was already set above, so this flag will
11175 * take effect when we commit and program watermarks.
11176 */
11177 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11178 needs_scaling(to_intel_plane_state(plane_state)) &&
11179 !needs_scaling(old_plane_state))
11180 pipe_config->disable_lp_wm = true;
11181
11182 return 0;
11183 }
11184
11185 static bool encoders_cloneable(const struct intel_encoder *a,
11186 const struct intel_encoder *b)
11187 {
11188 /* masks could be asymmetric, so check both ways */
11189 return a == b || (a->cloneable & (1 << b->type) &&
11190 b->cloneable & (1 << a->type));
11191 }
11192
11193 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11194 struct intel_crtc *crtc,
11195 struct intel_encoder *encoder)
11196 {
11197 struct intel_encoder *source_encoder;
11198 struct drm_connector *connector;
11199 struct drm_connector_state *connector_state;
11200 int i;
11201
11202 for_each_connector_in_state(state, connector, connector_state, i) {
11203 if (connector_state->crtc != &crtc->base)
11204 continue;
11205
11206 source_encoder =
11207 to_intel_encoder(connector_state->best_encoder);
11208 if (!encoders_cloneable(encoder, source_encoder))
11209 return false;
11210 }
11211
11212 return true;
11213 }
11214
11215 static bool check_encoder_cloning(struct drm_atomic_state *state,
11216 struct intel_crtc *crtc)
11217 {
11218 struct intel_encoder *encoder;
11219 struct drm_connector *connector;
11220 struct drm_connector_state *connector_state;
11221 int i;
11222
11223 for_each_connector_in_state(state, connector, connector_state, i) {
11224 if (connector_state->crtc != &crtc->base)
11225 continue;
11226
11227 encoder = to_intel_encoder(connector_state->best_encoder);
11228 if (!check_single_encoder_cloning(state, crtc, encoder))
11229 return false;
11230 }
11231
11232 return true;
11233 }
11234
11235 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11236 struct drm_crtc_state *crtc_state)
11237 {
11238 struct drm_device *dev = crtc->dev;
11239 struct drm_i915_private *dev_priv = dev->dev_private;
11240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11241 struct intel_crtc_state *pipe_config =
11242 to_intel_crtc_state(crtc_state);
11243 struct drm_atomic_state *state = crtc_state->state;
11244 int ret;
11245 bool mode_changed = needs_modeset(crtc_state);
11246
11247 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11248 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11249 return -EINVAL;
11250 }
11251
11252 if (mode_changed && !crtc_state->active)
11253 pipe_config->update_wm_post = true;
11254
11255 if (mode_changed && crtc_state->enable &&
11256 dev_priv->display.crtc_compute_clock &&
11257 !WARN_ON(pipe_config->shared_dpll)) {
11258 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11259 pipe_config);
11260 if (ret)
11261 return ret;
11262 }
11263
11264 if (crtc_state->color_mgmt_changed) {
11265 ret = intel_color_check(crtc, crtc_state);
11266 if (ret)
11267 return ret;
11268 }
11269
11270 ret = 0;
11271 if (dev_priv->display.compute_pipe_wm) {
11272 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11273 if (ret) {
11274 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11275 return ret;
11276 }
11277 }
11278
11279 if (dev_priv->display.compute_intermediate_wm &&
11280 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11281 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11282 return 0;
11283
11284 /*
11285 * Calculate 'intermediate' watermarks that satisfy both the
11286 * old state and the new state. We can program these
11287 * immediately.
11288 */
11289 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11290 intel_crtc,
11291 pipe_config);
11292 if (ret) {
11293 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11294 return ret;
11295 }
11296 } else if (dev_priv->display.compute_intermediate_wm) {
11297 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11298 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11299 }
11300
11301 if (INTEL_INFO(dev)->gen >= 9) {
11302 if (mode_changed)
11303 ret = skl_update_scaler_crtc(pipe_config);
11304
11305 if (!ret)
11306 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11307 pipe_config);
11308 }
11309
11310 return ret;
11311 }
11312
11313 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11314 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11315 .atomic_check = intel_crtc_atomic_check,
11316 };
11317
11318 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11319 {
11320 struct intel_connector *connector;
11321
11322 for_each_intel_connector(dev, connector) {
11323 if (connector->base.state->crtc)
11324 drm_connector_unreference(&connector->base);
11325
11326 if (connector->base.encoder) {
11327 connector->base.state->best_encoder =
11328 connector->base.encoder;
11329 connector->base.state->crtc =
11330 connector->base.encoder->crtc;
11331
11332 drm_connector_reference(&connector->base);
11333 } else {
11334 connector->base.state->best_encoder = NULL;
11335 connector->base.state->crtc = NULL;
11336 }
11337 }
11338 }
11339
11340 static void
11341 connected_sink_compute_bpp(struct intel_connector *connector,
11342 struct intel_crtc_state *pipe_config)
11343 {
11344 int bpp = pipe_config->pipe_bpp;
11345
11346 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11347 connector->base.base.id,
11348 connector->base.name);
11349
11350 /* Don't use an invalid EDID bpc value */
11351 if (connector->base.display_info.bpc &&
11352 connector->base.display_info.bpc * 3 < bpp) {
11353 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11354 bpp, connector->base.display_info.bpc*3);
11355 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11356 }
11357
11358 /* Clamp bpp to default limit on screens without EDID 1.4 */
11359 if (connector->base.display_info.bpc == 0) {
11360 int type = connector->base.connector_type;
11361 int clamp_bpp = 24;
11362
11363 /* Fall back to 18 bpp when DP sink capability is unknown. */
11364 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
11365 type == DRM_MODE_CONNECTOR_eDP)
11366 clamp_bpp = 18;
11367
11368 if (bpp > clamp_bpp) {
11369 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
11370 bpp, clamp_bpp);
11371 pipe_config->pipe_bpp = clamp_bpp;
11372 }
11373 }
11374 }
11375
11376 static int
11377 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11378 struct intel_crtc_state *pipe_config)
11379 {
11380 struct drm_device *dev = crtc->base.dev;
11381 struct drm_atomic_state *state;
11382 struct drm_connector *connector;
11383 struct drm_connector_state *connector_state;
11384 int bpp, i;
11385
11386 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
11387 bpp = 10*3;
11388 else if (INTEL_INFO(dev)->gen >= 5)
11389 bpp = 12*3;
11390 else
11391 bpp = 8*3;
11392
11393
11394 pipe_config->pipe_bpp = bpp;
11395
11396 state = pipe_config->base.state;
11397
11398 /* Clamp display bpp to EDID value */
11399 for_each_connector_in_state(state, connector, connector_state, i) {
11400 if (connector_state->crtc != &crtc->base)
11401 continue;
11402
11403 connected_sink_compute_bpp(to_intel_connector(connector),
11404 pipe_config);
11405 }
11406
11407 return bpp;
11408 }
11409
11410 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11411 {
11412 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11413 "type: 0x%x flags: 0x%x\n",
11414 mode->crtc_clock,
11415 mode->crtc_hdisplay, mode->crtc_hsync_start,
11416 mode->crtc_hsync_end, mode->crtc_htotal,
11417 mode->crtc_vdisplay, mode->crtc_vsync_start,
11418 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11419 }
11420
11421 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11422 struct intel_crtc_state *pipe_config,
11423 const char *context)
11424 {
11425 struct drm_device *dev = crtc->base.dev;
11426 struct drm_plane *plane;
11427 struct intel_plane *intel_plane;
11428 struct intel_plane_state *state;
11429 struct drm_framebuffer *fb;
11430
11431 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11432 context, pipe_config, pipe_name(crtc->pipe));
11433
11434 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
11435 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11436 pipe_config->pipe_bpp, pipe_config->dither);
11437 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11438 pipe_config->has_pch_encoder,
11439 pipe_config->fdi_lanes,
11440 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11441 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11442 pipe_config->fdi_m_n.tu);
11443 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11444 pipe_config->has_dp_encoder,
11445 pipe_config->lane_count,
11446 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11447 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11448 pipe_config->dp_m_n.tu);
11449
11450 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11451 pipe_config->has_dp_encoder,
11452 pipe_config->lane_count,
11453 pipe_config->dp_m2_n2.gmch_m,
11454 pipe_config->dp_m2_n2.gmch_n,
11455 pipe_config->dp_m2_n2.link_m,
11456 pipe_config->dp_m2_n2.link_n,
11457 pipe_config->dp_m2_n2.tu);
11458
11459 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11460 pipe_config->has_audio,
11461 pipe_config->has_infoframe);
11462
11463 DRM_DEBUG_KMS("requested mode:\n");
11464 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11465 DRM_DEBUG_KMS("adjusted mode:\n");
11466 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11467 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11468 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11469 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11470 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11471 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11472 crtc->num_scalers,
11473 pipe_config->scaler_state.scaler_users,
11474 pipe_config->scaler_state.scaler_id);
11475 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11476 pipe_config->gmch_pfit.control,
11477 pipe_config->gmch_pfit.pgm_ratios,
11478 pipe_config->gmch_pfit.lvds_border_bits);
11479 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11480 pipe_config->pch_pfit.pos,
11481 pipe_config->pch_pfit.size,
11482 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11483 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11484 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11485
11486 if (IS_BROXTON(dev)) {
11487 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11488 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11489 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11490 pipe_config->ddi_pll_sel,
11491 pipe_config->dpll_hw_state.ebb0,
11492 pipe_config->dpll_hw_state.ebb4,
11493 pipe_config->dpll_hw_state.pll0,
11494 pipe_config->dpll_hw_state.pll1,
11495 pipe_config->dpll_hw_state.pll2,
11496 pipe_config->dpll_hw_state.pll3,
11497 pipe_config->dpll_hw_state.pll6,
11498 pipe_config->dpll_hw_state.pll8,
11499 pipe_config->dpll_hw_state.pll9,
11500 pipe_config->dpll_hw_state.pll10,
11501 pipe_config->dpll_hw_state.pcsdw12);
11502 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
11503 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11504 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11505 pipe_config->ddi_pll_sel,
11506 pipe_config->dpll_hw_state.ctrl1,
11507 pipe_config->dpll_hw_state.cfgcr1,
11508 pipe_config->dpll_hw_state.cfgcr2);
11509 } else if (HAS_DDI(dev)) {
11510 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
11511 pipe_config->ddi_pll_sel,
11512 pipe_config->dpll_hw_state.wrpll,
11513 pipe_config->dpll_hw_state.spll);
11514 } else {
11515 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11516 "fp0: 0x%x, fp1: 0x%x\n",
11517 pipe_config->dpll_hw_state.dpll,
11518 pipe_config->dpll_hw_state.dpll_md,
11519 pipe_config->dpll_hw_state.fp0,
11520 pipe_config->dpll_hw_state.fp1);
11521 }
11522
11523 DRM_DEBUG_KMS("planes on this crtc\n");
11524 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11525 intel_plane = to_intel_plane(plane);
11526 if (intel_plane->pipe != crtc->pipe)
11527 continue;
11528
11529 state = to_intel_plane_state(plane->state);
11530 fb = state->base.fb;
11531 if (!fb) {
11532 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11533 "disabled, scaler_id = %d\n",
11534 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11535 plane->base.id, intel_plane->pipe,
11536 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11537 drm_plane_index(plane), state->scaler_id);
11538 continue;
11539 }
11540
11541 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11542 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11543 plane->base.id, intel_plane->pipe,
11544 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11545 drm_plane_index(plane));
11546 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11547 fb->base.id, fb->width, fb->height, fb->pixel_format);
11548 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11549 state->scaler_id,
11550 state->src.x1 >> 16, state->src.y1 >> 16,
11551 drm_rect_width(&state->src) >> 16,
11552 drm_rect_height(&state->src) >> 16,
11553 state->dst.x1, state->dst.y1,
11554 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11555 }
11556 }
11557
11558 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11559 {
11560 struct drm_device *dev = state->dev;
11561 struct drm_connector *connector;
11562 unsigned int used_ports = 0;
11563
11564 /*
11565 * Walk the connector list instead of the encoder
11566 * list to detect the problem on ddi platforms
11567 * where there's just one encoder per digital port.
11568 */
11569 drm_for_each_connector(connector, dev) {
11570 struct drm_connector_state *connector_state;
11571 struct intel_encoder *encoder;
11572
11573 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11574 if (!connector_state)
11575 connector_state = connector->state;
11576
11577 if (!connector_state->best_encoder)
11578 continue;
11579
11580 encoder = to_intel_encoder(connector_state->best_encoder);
11581
11582 WARN_ON(!connector_state->crtc);
11583
11584 switch (encoder->type) {
11585 unsigned int port_mask;
11586 case INTEL_OUTPUT_UNKNOWN:
11587 if (WARN_ON(!HAS_DDI(dev)))
11588 break;
11589 case INTEL_OUTPUT_DISPLAYPORT:
11590 case INTEL_OUTPUT_HDMI:
11591 case INTEL_OUTPUT_EDP:
11592 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11593
11594 /* the same port mustn't appear more than once */
11595 if (used_ports & port_mask)
11596 return false;
11597
11598 used_ports |= port_mask;
11599 default:
11600 break;
11601 }
11602 }
11603
11604 return true;
11605 }
11606
11607 static void
11608 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11609 {
11610 struct drm_crtc_state tmp_state;
11611 struct intel_crtc_scaler_state scaler_state;
11612 struct intel_dpll_hw_state dpll_hw_state;
11613 struct intel_shared_dpll *shared_dpll;
11614 uint32_t ddi_pll_sel;
11615 bool force_thru;
11616
11617 /* FIXME: before the switch to atomic started, a new pipe_config was
11618 * kzalloc'd. Code that depends on any field being zero should be
11619 * fixed, so that the crtc_state can be safely duplicated. For now,
11620 * only fields that are know to not cause problems are preserved. */
11621
11622 tmp_state = crtc_state->base;
11623 scaler_state = crtc_state->scaler_state;
11624 shared_dpll = crtc_state->shared_dpll;
11625 dpll_hw_state = crtc_state->dpll_hw_state;
11626 ddi_pll_sel = crtc_state->ddi_pll_sel;
11627 force_thru = crtc_state->pch_pfit.force_thru;
11628
11629 memset(crtc_state, 0, sizeof *crtc_state);
11630
11631 crtc_state->base = tmp_state;
11632 crtc_state->scaler_state = scaler_state;
11633 crtc_state->shared_dpll = shared_dpll;
11634 crtc_state->dpll_hw_state = dpll_hw_state;
11635 crtc_state->ddi_pll_sel = ddi_pll_sel;
11636 crtc_state->pch_pfit.force_thru = force_thru;
11637 }
11638
11639 static int
11640 intel_modeset_pipe_config(struct drm_crtc *crtc,
11641 struct intel_crtc_state *pipe_config)
11642 {
11643 struct drm_atomic_state *state = pipe_config->base.state;
11644 struct intel_encoder *encoder;
11645 struct drm_connector *connector;
11646 struct drm_connector_state *connector_state;
11647 int base_bpp, ret = -EINVAL;
11648 int i;
11649 bool retry = true;
11650
11651 clear_intel_crtc_state(pipe_config);
11652
11653 pipe_config->cpu_transcoder =
11654 (enum transcoder) to_intel_crtc(crtc)->pipe;
11655
11656 /*
11657 * Sanitize sync polarity flags based on requested ones. If neither
11658 * positive or negative polarity is requested, treat this as meaning
11659 * negative polarity.
11660 */
11661 if (!(pipe_config->base.adjusted_mode.flags &
11662 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11663 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11664
11665 if (!(pipe_config->base.adjusted_mode.flags &
11666 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11667 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11668
11669 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11670 pipe_config);
11671 if (base_bpp < 0)
11672 goto fail;
11673
11674 /*
11675 * Determine the real pipe dimensions. Note that stereo modes can
11676 * increase the actual pipe size due to the frame doubling and
11677 * insertion of additional space for blanks between the frame. This
11678 * is stored in the crtc timings. We use the requested mode to do this
11679 * computation to clearly distinguish it from the adjusted mode, which
11680 * can be changed by the connectors in the below retry loop.
11681 */
11682 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11683 &pipe_config->pipe_src_w,
11684 &pipe_config->pipe_src_h);
11685
11686 encoder_retry:
11687 /* Ensure the port clock defaults are reset when retrying. */
11688 pipe_config->port_clock = 0;
11689 pipe_config->pixel_multiplier = 1;
11690
11691 /* Fill in default crtc timings, allow encoders to overwrite them. */
11692 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11693 CRTC_STEREO_DOUBLE);
11694
11695 /* Pass our mode to the connectors and the CRTC to give them a chance to
11696 * adjust it according to limitations or connector properties, and also
11697 * a chance to reject the mode entirely.
11698 */
11699 for_each_connector_in_state(state, connector, connector_state, i) {
11700 if (connector_state->crtc != crtc)
11701 continue;
11702
11703 encoder = to_intel_encoder(connector_state->best_encoder);
11704
11705 if (!(encoder->compute_config(encoder, pipe_config))) {
11706 DRM_DEBUG_KMS("Encoder config failure\n");
11707 goto fail;
11708 }
11709 }
11710
11711 /* Set default port clock if not overwritten by the encoder. Needs to be
11712 * done afterwards in case the encoder adjusts the mode. */
11713 if (!pipe_config->port_clock)
11714 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11715 * pipe_config->pixel_multiplier;
11716
11717 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11718 if (ret < 0) {
11719 DRM_DEBUG_KMS("CRTC fixup failed\n");
11720 goto fail;
11721 }
11722
11723 if (ret == RETRY) {
11724 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11725 ret = -EINVAL;
11726 goto fail;
11727 }
11728
11729 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11730 retry = false;
11731 goto encoder_retry;
11732 }
11733
11734 /* Dithering seems to not pass-through bits correctly when it should, so
11735 * only enable it on 6bpc panels. */
11736 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
11737 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11738 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11739
11740 fail:
11741 return ret;
11742 }
11743
11744 static void
11745 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11746 {
11747 struct drm_crtc *crtc;
11748 struct drm_crtc_state *crtc_state;
11749 int i;
11750
11751 /* Double check state. */
11752 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11753 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11754
11755 /* Update hwmode for vblank functions */
11756 if (crtc->state->active)
11757 crtc->hwmode = crtc->state->adjusted_mode;
11758 else
11759 crtc->hwmode.crtc_clock = 0;
11760
11761 /*
11762 * Update legacy state to satisfy fbc code. This can
11763 * be removed when fbc uses the atomic state.
11764 */
11765 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11766 struct drm_plane_state *plane_state = crtc->primary->state;
11767
11768 crtc->primary->fb = plane_state->fb;
11769 crtc->x = plane_state->src_x >> 16;
11770 crtc->y = plane_state->src_y >> 16;
11771 }
11772 }
11773 }
11774
11775 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11776 {
11777 int diff;
11778
11779 if (clock1 == clock2)
11780 return true;
11781
11782 if (!clock1 || !clock2)
11783 return false;
11784
11785 diff = abs(clock1 - clock2);
11786
11787 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11788 return true;
11789
11790 return false;
11791 }
11792
11793 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11794 list_for_each_entry((intel_crtc), \
11795 &(dev)->mode_config.crtc_list, \
11796 base.head) \
11797 for_each_if (mask & (1 <<(intel_crtc)->pipe))
11798
11799 static bool
11800 intel_compare_m_n(unsigned int m, unsigned int n,
11801 unsigned int m2, unsigned int n2,
11802 bool exact)
11803 {
11804 if (m == m2 && n == n2)
11805 return true;
11806
11807 if (exact || !m || !n || !m2 || !n2)
11808 return false;
11809
11810 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11811
11812 if (n > n2) {
11813 while (n > n2) {
11814 m2 <<= 1;
11815 n2 <<= 1;
11816 }
11817 } else if (n < n2) {
11818 while (n < n2) {
11819 m <<= 1;
11820 n <<= 1;
11821 }
11822 }
11823
11824 if (n != n2)
11825 return false;
11826
11827 return intel_fuzzy_clock_check(m, m2);
11828 }
11829
11830 static bool
11831 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11832 struct intel_link_m_n *m2_n2,
11833 bool adjust)
11834 {
11835 if (m_n->tu == m2_n2->tu &&
11836 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11837 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11838 intel_compare_m_n(m_n->link_m, m_n->link_n,
11839 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11840 if (adjust)
11841 *m2_n2 = *m_n;
11842
11843 return true;
11844 }
11845
11846 return false;
11847 }
11848
11849 static bool
11850 intel_pipe_config_compare(struct drm_device *dev,
11851 struct intel_crtc_state *current_config,
11852 struct intel_crtc_state *pipe_config,
11853 bool adjust)
11854 {
11855 bool ret = true;
11856
11857 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
11858 do { \
11859 if (!adjust) \
11860 DRM_ERROR(fmt, ##__VA_ARGS__); \
11861 else \
11862 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
11863 } while (0)
11864
11865 #define PIPE_CONF_CHECK_X(name) \
11866 if (current_config->name != pipe_config->name) { \
11867 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11868 "(expected 0x%08x, found 0x%08x)\n", \
11869 current_config->name, \
11870 pipe_config->name); \
11871 ret = false; \
11872 }
11873
11874 #define PIPE_CONF_CHECK_I(name) \
11875 if (current_config->name != pipe_config->name) { \
11876 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11877 "(expected %i, found %i)\n", \
11878 current_config->name, \
11879 pipe_config->name); \
11880 ret = false; \
11881 }
11882
11883 #define PIPE_CONF_CHECK_P(name) \
11884 if (current_config->name != pipe_config->name) { \
11885 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11886 "(expected %p, found %p)\n", \
11887 current_config->name, \
11888 pipe_config->name); \
11889 ret = false; \
11890 }
11891
11892 #define PIPE_CONF_CHECK_M_N(name) \
11893 if (!intel_compare_link_m_n(&current_config->name, \
11894 &pipe_config->name,\
11895 adjust)) { \
11896 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11897 "(expected tu %i gmch %i/%i link %i/%i, " \
11898 "found tu %i, gmch %i/%i link %i/%i)\n", \
11899 current_config->name.tu, \
11900 current_config->name.gmch_m, \
11901 current_config->name.gmch_n, \
11902 current_config->name.link_m, \
11903 current_config->name.link_n, \
11904 pipe_config->name.tu, \
11905 pipe_config->name.gmch_m, \
11906 pipe_config->name.gmch_n, \
11907 pipe_config->name.link_m, \
11908 pipe_config->name.link_n); \
11909 ret = false; \
11910 }
11911
11912 /* This is required for BDW+ where there is only one set of registers for
11913 * switching between high and low RR.
11914 * This macro can be used whenever a comparison has to be made between one
11915 * hw state and multiple sw state variables.
11916 */
11917 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11918 if (!intel_compare_link_m_n(&current_config->name, \
11919 &pipe_config->name, adjust) && \
11920 !intel_compare_link_m_n(&current_config->alt_name, \
11921 &pipe_config->name, adjust)) { \
11922 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11923 "(expected tu %i gmch %i/%i link %i/%i, " \
11924 "or tu %i gmch %i/%i link %i/%i, " \
11925 "found tu %i, gmch %i/%i link %i/%i)\n", \
11926 current_config->name.tu, \
11927 current_config->name.gmch_m, \
11928 current_config->name.gmch_n, \
11929 current_config->name.link_m, \
11930 current_config->name.link_n, \
11931 current_config->alt_name.tu, \
11932 current_config->alt_name.gmch_m, \
11933 current_config->alt_name.gmch_n, \
11934 current_config->alt_name.link_m, \
11935 current_config->alt_name.link_n, \
11936 pipe_config->name.tu, \
11937 pipe_config->name.gmch_m, \
11938 pipe_config->name.gmch_n, \
11939 pipe_config->name.link_m, \
11940 pipe_config->name.link_n); \
11941 ret = false; \
11942 }
11943
11944 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11945 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11946 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
11947 "(expected %i, found %i)\n", \
11948 current_config->name & (mask), \
11949 pipe_config->name & (mask)); \
11950 ret = false; \
11951 }
11952
11953 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11954 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11955 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11956 "(expected %i, found %i)\n", \
11957 current_config->name, \
11958 pipe_config->name); \
11959 ret = false; \
11960 }
11961
11962 #define PIPE_CONF_QUIRK(quirk) \
11963 ((current_config->quirks | pipe_config->quirks) & (quirk))
11964
11965 PIPE_CONF_CHECK_I(cpu_transcoder);
11966
11967 PIPE_CONF_CHECK_I(has_pch_encoder);
11968 PIPE_CONF_CHECK_I(fdi_lanes);
11969 PIPE_CONF_CHECK_M_N(fdi_m_n);
11970
11971 PIPE_CONF_CHECK_I(has_dp_encoder);
11972 PIPE_CONF_CHECK_I(lane_count);
11973
11974 if (INTEL_INFO(dev)->gen < 8) {
11975 PIPE_CONF_CHECK_M_N(dp_m_n);
11976
11977 if (current_config->has_drrs)
11978 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11979 } else
11980 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11981
11982 PIPE_CONF_CHECK_I(has_dsi_encoder);
11983
11984 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11985 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11986 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11987 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11988 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11989 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11990
11991 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11992 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11993 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11994 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11995 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11996 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11997
11998 PIPE_CONF_CHECK_I(pixel_multiplier);
11999 PIPE_CONF_CHECK_I(has_hdmi_sink);
12000 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12001 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12002 PIPE_CONF_CHECK_I(limited_color_range);
12003 PIPE_CONF_CHECK_I(has_infoframe);
12004
12005 PIPE_CONF_CHECK_I(has_audio);
12006
12007 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12008 DRM_MODE_FLAG_INTERLACE);
12009
12010 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12011 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12012 DRM_MODE_FLAG_PHSYNC);
12013 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12014 DRM_MODE_FLAG_NHSYNC);
12015 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12016 DRM_MODE_FLAG_PVSYNC);
12017 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12018 DRM_MODE_FLAG_NVSYNC);
12019 }
12020
12021 PIPE_CONF_CHECK_X(gmch_pfit.control);
12022 /* pfit ratios are autocomputed by the hw on gen4+ */
12023 if (INTEL_INFO(dev)->gen < 4)
12024 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12025 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12026
12027 if (!adjust) {
12028 PIPE_CONF_CHECK_I(pipe_src_w);
12029 PIPE_CONF_CHECK_I(pipe_src_h);
12030
12031 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12032 if (current_config->pch_pfit.enabled) {
12033 PIPE_CONF_CHECK_X(pch_pfit.pos);
12034 PIPE_CONF_CHECK_X(pch_pfit.size);
12035 }
12036
12037 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12038 }
12039
12040 /* BDW+ don't expose a synchronous way to read the state */
12041 if (IS_HASWELL(dev))
12042 PIPE_CONF_CHECK_I(ips_enabled);
12043
12044 PIPE_CONF_CHECK_I(double_wide);
12045
12046 PIPE_CONF_CHECK_X(ddi_pll_sel);
12047
12048 PIPE_CONF_CHECK_P(shared_dpll);
12049 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12050 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12051 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12052 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12053 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12054 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12055 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12056 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12057 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12058
12059 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12060 PIPE_CONF_CHECK_X(dsi_pll.div);
12061
12062 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12063 PIPE_CONF_CHECK_I(pipe_bpp);
12064
12065 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12066 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12067
12068 #undef PIPE_CONF_CHECK_X
12069 #undef PIPE_CONF_CHECK_I
12070 #undef PIPE_CONF_CHECK_P
12071 #undef PIPE_CONF_CHECK_FLAGS
12072 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12073 #undef PIPE_CONF_QUIRK
12074 #undef INTEL_ERR_OR_DBG_KMS
12075
12076 return ret;
12077 }
12078
12079 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12080 const struct intel_crtc_state *pipe_config)
12081 {
12082 if (pipe_config->has_pch_encoder) {
12083 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12084 &pipe_config->fdi_m_n);
12085 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12086
12087 /*
12088 * FDI already provided one idea for the dotclock.
12089 * Yell if the encoder disagrees.
12090 */
12091 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12092 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12093 fdi_dotclock, dotclock);
12094 }
12095 }
12096
12097 static void verify_wm_state(struct drm_crtc *crtc,
12098 struct drm_crtc_state *new_state)
12099 {
12100 struct drm_device *dev = crtc->dev;
12101 struct drm_i915_private *dev_priv = dev->dev_private;
12102 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12103 struct skl_ddb_entry *hw_entry, *sw_entry;
12104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12105 const enum pipe pipe = intel_crtc->pipe;
12106 int plane;
12107
12108 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12109 return;
12110
12111 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12112 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12113
12114 /* planes */
12115 for_each_plane(dev_priv, pipe, plane) {
12116 hw_entry = &hw_ddb.plane[pipe][plane];
12117 sw_entry = &sw_ddb->plane[pipe][plane];
12118
12119 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12120 continue;
12121
12122 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12123 "(expected (%u,%u), found (%u,%u))\n",
12124 pipe_name(pipe), plane + 1,
12125 sw_entry->start, sw_entry->end,
12126 hw_entry->start, hw_entry->end);
12127 }
12128
12129 /* cursor */
12130 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12131 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12132
12133 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12134 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12135 "(expected (%u,%u), found (%u,%u))\n",
12136 pipe_name(pipe),
12137 sw_entry->start, sw_entry->end,
12138 hw_entry->start, hw_entry->end);
12139 }
12140 }
12141
12142 static void
12143 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12144 {
12145 struct drm_connector *connector;
12146
12147 drm_for_each_connector(connector, dev) {
12148 struct drm_encoder *encoder = connector->encoder;
12149 struct drm_connector_state *state = connector->state;
12150
12151 if (state->crtc != crtc)
12152 continue;
12153
12154 intel_connector_verify_state(to_intel_connector(connector),
12155 connector->state);
12156
12157 I915_STATE_WARN(state->best_encoder != encoder,
12158 "connector's atomic encoder doesn't match legacy encoder\n");
12159 }
12160 }
12161
12162 static void
12163 verify_encoder_state(struct drm_device *dev)
12164 {
12165 struct intel_encoder *encoder;
12166 struct intel_connector *connector;
12167
12168 for_each_intel_encoder(dev, encoder) {
12169 bool enabled = false;
12170 enum pipe pipe;
12171
12172 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12173 encoder->base.base.id,
12174 encoder->base.name);
12175
12176 for_each_intel_connector(dev, connector) {
12177 if (connector->base.state->best_encoder != &encoder->base)
12178 continue;
12179 enabled = true;
12180
12181 I915_STATE_WARN(connector->base.state->crtc !=
12182 encoder->base.crtc,
12183 "connector's crtc doesn't match encoder crtc\n");
12184 }
12185
12186 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12187 "encoder's enabled state mismatch "
12188 "(expected %i, found %i)\n",
12189 !!encoder->base.crtc, enabled);
12190
12191 if (!encoder->base.crtc) {
12192 bool active;
12193
12194 active = encoder->get_hw_state(encoder, &pipe);
12195 I915_STATE_WARN(active,
12196 "encoder detached but still enabled on pipe %c.\n",
12197 pipe_name(pipe));
12198 }
12199 }
12200 }
12201
12202 static void
12203 verify_crtc_state(struct drm_crtc *crtc,
12204 struct drm_crtc_state *old_crtc_state,
12205 struct drm_crtc_state *new_crtc_state)
12206 {
12207 struct drm_device *dev = crtc->dev;
12208 struct drm_i915_private *dev_priv = dev->dev_private;
12209 struct intel_encoder *encoder;
12210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12211 struct intel_crtc_state *pipe_config, *sw_config;
12212 struct drm_atomic_state *old_state;
12213 bool active;
12214
12215 old_state = old_crtc_state->state;
12216 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12217 pipe_config = to_intel_crtc_state(old_crtc_state);
12218 memset(pipe_config, 0, sizeof(*pipe_config));
12219 pipe_config->base.crtc = crtc;
12220 pipe_config->base.state = old_state;
12221
12222 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12223
12224 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12225
12226 /* hw state is inconsistent with the pipe quirk */
12227 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12228 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12229 active = new_crtc_state->active;
12230
12231 I915_STATE_WARN(new_crtc_state->active != active,
12232 "crtc active state doesn't match with hw state "
12233 "(expected %i, found %i)\n", new_crtc_state->active, active);
12234
12235 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12236 "transitional active state does not match atomic hw state "
12237 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12238
12239 for_each_encoder_on_crtc(dev, crtc, encoder) {
12240 enum pipe pipe;
12241
12242 active = encoder->get_hw_state(encoder, &pipe);
12243 I915_STATE_WARN(active != new_crtc_state->active,
12244 "[ENCODER:%i] active %i with crtc active %i\n",
12245 encoder->base.base.id, active, new_crtc_state->active);
12246
12247 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12248 "Encoder connected to wrong pipe %c\n",
12249 pipe_name(pipe));
12250
12251 if (active)
12252 encoder->get_config(encoder, pipe_config);
12253 }
12254
12255 if (!new_crtc_state->active)
12256 return;
12257
12258 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12259
12260 sw_config = to_intel_crtc_state(crtc->state);
12261 if (!intel_pipe_config_compare(dev, sw_config,
12262 pipe_config, false)) {
12263 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12264 intel_dump_pipe_config(intel_crtc, pipe_config,
12265 "[hw state]");
12266 intel_dump_pipe_config(intel_crtc, sw_config,
12267 "[sw state]");
12268 }
12269 }
12270
12271 static void
12272 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12273 struct intel_shared_dpll *pll,
12274 struct drm_crtc *crtc,
12275 struct drm_crtc_state *new_state)
12276 {
12277 struct intel_dpll_hw_state dpll_hw_state;
12278 unsigned crtc_mask;
12279 bool active;
12280
12281 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12282
12283 DRM_DEBUG_KMS("%s\n", pll->name);
12284
12285 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12286
12287 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12288 I915_STATE_WARN(!pll->on && pll->active_mask,
12289 "pll in active use but not on in sw tracking\n");
12290 I915_STATE_WARN(pll->on && !pll->active_mask,
12291 "pll is on but not used by any active crtc\n");
12292 I915_STATE_WARN(pll->on != active,
12293 "pll on state mismatch (expected %i, found %i)\n",
12294 pll->on, active);
12295 }
12296
12297 if (!crtc) {
12298 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12299 "more active pll users than references: %x vs %x\n",
12300 pll->active_mask, pll->config.crtc_mask);
12301
12302 return;
12303 }
12304
12305 crtc_mask = 1 << drm_crtc_index(crtc);
12306
12307 if (new_state->active)
12308 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12309 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12310 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12311 else
12312 I915_STATE_WARN(pll->active_mask & crtc_mask,
12313 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12314 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12315
12316 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12317 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12318 crtc_mask, pll->config.crtc_mask);
12319
12320 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12321 &dpll_hw_state,
12322 sizeof(dpll_hw_state)),
12323 "pll hw state mismatch\n");
12324 }
12325
12326 static void
12327 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12328 struct drm_crtc_state *old_crtc_state,
12329 struct drm_crtc_state *new_crtc_state)
12330 {
12331 struct drm_i915_private *dev_priv = dev->dev_private;
12332 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12333 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12334
12335 if (new_state->shared_dpll)
12336 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12337
12338 if (old_state->shared_dpll &&
12339 old_state->shared_dpll != new_state->shared_dpll) {
12340 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12341 struct intel_shared_dpll *pll = old_state->shared_dpll;
12342
12343 I915_STATE_WARN(pll->active_mask & crtc_mask,
12344 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12345 pipe_name(drm_crtc_index(crtc)));
12346 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
12347 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12348 pipe_name(drm_crtc_index(crtc)));
12349 }
12350 }
12351
12352 static void
12353 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12354 struct drm_crtc_state *old_state,
12355 struct drm_crtc_state *new_state)
12356 {
12357 verify_wm_state(crtc, new_state);
12358 verify_crtc_state(crtc, old_state, new_state);
12359 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12360 }
12361
12362 static void
12363 verify_disabled_dpll_state(struct drm_device *dev)
12364 {
12365 struct drm_i915_private *dev_priv = dev->dev_private;
12366 int i;
12367
12368 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12369 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12370 }
12371
12372 static void
12373 intel_modeset_verify_disabled(struct drm_device *dev)
12374 {
12375 verify_encoder_state(dev);
12376 verify_connector_state(dev, NULL);
12377 verify_disabled_dpll_state(dev);
12378 }
12379
12380 static void update_scanline_offset(struct intel_crtc *crtc)
12381 {
12382 struct drm_device *dev = crtc->base.dev;
12383
12384 /*
12385 * The scanline counter increments at the leading edge of hsync.
12386 *
12387 * On most platforms it starts counting from vtotal-1 on the
12388 * first active line. That means the scanline counter value is
12389 * always one less than what we would expect. Ie. just after
12390 * start of vblank, which also occurs at start of hsync (on the
12391 * last active line), the scanline counter will read vblank_start-1.
12392 *
12393 * On gen2 the scanline counter starts counting from 1 instead
12394 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12395 * to keep the value positive), instead of adding one.
12396 *
12397 * On HSW+ the behaviour of the scanline counter depends on the output
12398 * type. For DP ports it behaves like most other platforms, but on HDMI
12399 * there's an extra 1 line difference. So we need to add two instead of
12400 * one to the value.
12401 */
12402 if (IS_GEN2(dev)) {
12403 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12404 int vtotal;
12405
12406 vtotal = adjusted_mode->crtc_vtotal;
12407 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12408 vtotal /= 2;
12409
12410 crtc->scanline_offset = vtotal - 1;
12411 } else if (HAS_DDI(dev) &&
12412 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12413 crtc->scanline_offset = 2;
12414 } else
12415 crtc->scanline_offset = 1;
12416 }
12417
12418 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12419 {
12420 struct drm_device *dev = state->dev;
12421 struct drm_i915_private *dev_priv = to_i915(dev);
12422 struct intel_shared_dpll_config *shared_dpll = NULL;
12423 struct drm_crtc *crtc;
12424 struct drm_crtc_state *crtc_state;
12425 int i;
12426
12427 if (!dev_priv->display.crtc_compute_clock)
12428 return;
12429
12430 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12432 struct intel_shared_dpll *old_dpll =
12433 to_intel_crtc_state(crtc->state)->shared_dpll;
12434
12435 if (!needs_modeset(crtc_state))
12436 continue;
12437
12438 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12439
12440 if (!old_dpll)
12441 continue;
12442
12443 if (!shared_dpll)
12444 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12445
12446 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
12447 }
12448 }
12449
12450 /*
12451 * This implements the workaround described in the "notes" section of the mode
12452 * set sequence documentation. When going from no pipes or single pipe to
12453 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12454 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12455 */
12456 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12457 {
12458 struct drm_crtc_state *crtc_state;
12459 struct intel_crtc *intel_crtc;
12460 struct drm_crtc *crtc;
12461 struct intel_crtc_state *first_crtc_state = NULL;
12462 struct intel_crtc_state *other_crtc_state = NULL;
12463 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12464 int i;
12465
12466 /* look at all crtc's that are going to be enabled in during modeset */
12467 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12468 intel_crtc = to_intel_crtc(crtc);
12469
12470 if (!crtc_state->active || !needs_modeset(crtc_state))
12471 continue;
12472
12473 if (first_crtc_state) {
12474 other_crtc_state = to_intel_crtc_state(crtc_state);
12475 break;
12476 } else {
12477 first_crtc_state = to_intel_crtc_state(crtc_state);
12478 first_pipe = intel_crtc->pipe;
12479 }
12480 }
12481
12482 /* No workaround needed? */
12483 if (!first_crtc_state)
12484 return 0;
12485
12486 /* w/a possibly needed, check how many crtc's are already enabled. */
12487 for_each_intel_crtc(state->dev, intel_crtc) {
12488 struct intel_crtc_state *pipe_config;
12489
12490 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12491 if (IS_ERR(pipe_config))
12492 return PTR_ERR(pipe_config);
12493
12494 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12495
12496 if (!pipe_config->base.active ||
12497 needs_modeset(&pipe_config->base))
12498 continue;
12499
12500 /* 2 or more enabled crtcs means no need for w/a */
12501 if (enabled_pipe != INVALID_PIPE)
12502 return 0;
12503
12504 enabled_pipe = intel_crtc->pipe;
12505 }
12506
12507 if (enabled_pipe != INVALID_PIPE)
12508 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12509 else if (other_crtc_state)
12510 other_crtc_state->hsw_workaround_pipe = first_pipe;
12511
12512 return 0;
12513 }
12514
12515 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12516 {
12517 struct drm_crtc *crtc;
12518 struct drm_crtc_state *crtc_state;
12519 int ret = 0;
12520
12521 /* add all active pipes to the state */
12522 for_each_crtc(state->dev, crtc) {
12523 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12524 if (IS_ERR(crtc_state))
12525 return PTR_ERR(crtc_state);
12526
12527 if (!crtc_state->active || needs_modeset(crtc_state))
12528 continue;
12529
12530 crtc_state->mode_changed = true;
12531
12532 ret = drm_atomic_add_affected_connectors(state, crtc);
12533 if (ret)
12534 break;
12535
12536 ret = drm_atomic_add_affected_planes(state, crtc);
12537 if (ret)
12538 break;
12539 }
12540
12541 return ret;
12542 }
12543
12544 static int intel_modeset_checks(struct drm_atomic_state *state)
12545 {
12546 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12547 struct drm_i915_private *dev_priv = state->dev->dev_private;
12548 struct drm_crtc *crtc;
12549 struct drm_crtc_state *crtc_state;
12550 int ret = 0, i;
12551
12552 if (!check_digital_port_conflicts(state)) {
12553 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12554 return -EINVAL;
12555 }
12556
12557 intel_state->modeset = true;
12558 intel_state->active_crtcs = dev_priv->active_crtcs;
12559
12560 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12561 if (crtc_state->active)
12562 intel_state->active_crtcs |= 1 << i;
12563 else
12564 intel_state->active_crtcs &= ~(1 << i);
12565
12566 if (crtc_state->active != crtc->state->active)
12567 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12568 }
12569
12570 /*
12571 * See if the config requires any additional preparation, e.g.
12572 * to adjust global state with pipes off. We need to do this
12573 * here so we can get the modeset_pipe updated config for the new
12574 * mode set on this crtc. For other crtcs we need to use the
12575 * adjusted_mode bits in the crtc directly.
12576 */
12577 if (dev_priv->display.modeset_calc_cdclk) {
12578 ret = dev_priv->display.modeset_calc_cdclk(state);
12579
12580 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
12581 ret = intel_modeset_all_pipes(state);
12582
12583 if (ret < 0)
12584 return ret;
12585
12586 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
12587 intel_state->cdclk, intel_state->dev_cdclk);
12588 } else
12589 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
12590
12591 intel_modeset_clear_plls(state);
12592
12593 if (IS_HASWELL(dev_priv))
12594 return haswell_mode_set_planes_workaround(state);
12595
12596 return 0;
12597 }
12598
12599 /*
12600 * Handle calculation of various watermark data at the end of the atomic check
12601 * phase. The code here should be run after the per-crtc and per-plane 'check'
12602 * handlers to ensure that all derived state has been updated.
12603 */
12604 static int calc_watermark_data(struct drm_atomic_state *state)
12605 {
12606 struct drm_device *dev = state->dev;
12607 struct drm_i915_private *dev_priv = to_i915(dev);
12608
12609 /* Is there platform-specific watermark information to calculate? */
12610 if (dev_priv->display.compute_global_watermarks)
12611 return dev_priv->display.compute_global_watermarks(state);
12612
12613 return 0;
12614 }
12615
12616 /**
12617 * intel_atomic_check - validate state object
12618 * @dev: drm device
12619 * @state: state to validate
12620 */
12621 static int intel_atomic_check(struct drm_device *dev,
12622 struct drm_atomic_state *state)
12623 {
12624 struct drm_i915_private *dev_priv = to_i915(dev);
12625 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12626 struct drm_crtc *crtc;
12627 struct drm_crtc_state *crtc_state;
12628 int ret, i;
12629 bool any_ms = false;
12630
12631 ret = drm_atomic_helper_check_modeset(dev, state);
12632 if (ret)
12633 return ret;
12634
12635 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12636 struct intel_crtc_state *pipe_config =
12637 to_intel_crtc_state(crtc_state);
12638
12639 /* Catch I915_MODE_FLAG_INHERITED */
12640 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12641 crtc_state->mode_changed = true;
12642
12643 if (!needs_modeset(crtc_state))
12644 continue;
12645
12646 if (!crtc_state->enable) {
12647 any_ms = true;
12648 continue;
12649 }
12650
12651 /* FIXME: For only active_changed we shouldn't need to do any
12652 * state recomputation at all. */
12653
12654 ret = drm_atomic_add_affected_connectors(state, crtc);
12655 if (ret)
12656 return ret;
12657
12658 ret = intel_modeset_pipe_config(crtc, pipe_config);
12659 if (ret) {
12660 intel_dump_pipe_config(to_intel_crtc(crtc),
12661 pipe_config, "[failed]");
12662 return ret;
12663 }
12664
12665 if (i915.fastboot &&
12666 intel_pipe_config_compare(dev,
12667 to_intel_crtc_state(crtc->state),
12668 pipe_config, true)) {
12669 crtc_state->mode_changed = false;
12670 to_intel_crtc_state(crtc_state)->update_pipe = true;
12671 }
12672
12673 if (needs_modeset(crtc_state))
12674 any_ms = true;
12675
12676 ret = drm_atomic_add_affected_planes(state, crtc);
12677 if (ret)
12678 return ret;
12679
12680 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12681 needs_modeset(crtc_state) ?
12682 "[modeset]" : "[fastset]");
12683 }
12684
12685 if (any_ms) {
12686 ret = intel_modeset_checks(state);
12687
12688 if (ret)
12689 return ret;
12690 } else
12691 intel_state->cdclk = dev_priv->cdclk_freq;
12692
12693 ret = drm_atomic_helper_check_planes(dev, state);
12694 if (ret)
12695 return ret;
12696
12697 intel_fbc_choose_crtc(dev_priv, state);
12698 return calc_watermark_data(state);
12699 }
12700
12701 static bool needs_work(struct drm_crtc_state *crtc_state)
12702 {
12703 /* hw state checker needs to run */
12704 if (needs_modeset(crtc_state))
12705 return true;
12706
12707 /* unpin old fb's, possibly vblank update */
12708 if (crtc_state->planes_changed)
12709 return true;
12710
12711 /* pipe parameters need to be updated, and hw state checker */
12712 if (to_intel_crtc_state(crtc_state)->update_pipe)
12713 return true;
12714
12715 /* vblank event requested? */
12716 if (crtc_state->event)
12717 return true;
12718
12719 return false;
12720 }
12721
12722 static int intel_atomic_prepare_commit(struct drm_device *dev,
12723 struct drm_atomic_state *state,
12724 bool nonblock)
12725 {
12726 struct drm_i915_private *dev_priv = dev->dev_private;
12727 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12728 struct drm_plane_state *plane_state;
12729 struct drm_crtc_state *crtc_state;
12730 struct drm_plane *plane;
12731 struct drm_crtc *crtc;
12732 int i, ret;
12733
12734 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12736 struct intel_flip_work *work;
12737
12738 if (!state->legacy_cursor_update) {
12739 ret = intel_crtc_wait_for_pending_flips(crtc);
12740 if (ret)
12741 return ret;
12742
12743 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12744 flush_workqueue(dev_priv->wq);
12745 }
12746
12747 /* test if we need to update something */
12748 if (!needs_work(crtc_state))
12749 continue;
12750
12751 intel_state->work[i] = work =
12752 kzalloc(sizeof(**intel_state->work), GFP_KERNEL);
12753
12754 if (!work)
12755 return -ENOMEM;
12756
12757 if (needs_modeset(crtc_state) ||
12758 to_intel_crtc_state(crtc_state)->update_pipe) {
12759 work->num_old_connectors = hweight32(crtc->state->connector_mask);
12760
12761 work->old_connector_state = kcalloc(work->num_old_connectors,
12762 sizeof(*work->old_connector_state),
12763 GFP_KERNEL);
12764
12765 work->num_new_connectors = hweight32(crtc_state->connector_mask);
12766 work->new_connector_state = kcalloc(work->num_new_connectors,
12767 sizeof(*work->new_connector_state),
12768 GFP_KERNEL);
12769
12770 if (!work->old_connector_state || !work->new_connector_state)
12771 return -ENOMEM;
12772 }
12773 }
12774
12775 if (intel_state->modeset && nonblock) {
12776 DRM_DEBUG_ATOMIC("Nonblock modesets are not yet supported!\n");
12777 return -EINVAL;
12778 }
12779
12780 ret = mutex_lock_interruptible(&dev->struct_mutex);
12781 if (ret)
12782 return ret;
12783
12784 ret = drm_atomic_helper_prepare_planes(dev, state);
12785 mutex_unlock(&dev->struct_mutex);
12786
12787 if (!ret && !nonblock) {
12788 for_each_plane_in_state(state, plane, plane_state, i) {
12789 struct intel_plane_state *intel_plane_state =
12790 to_intel_plane_state(plane_state);
12791
12792 if (plane_state->fence) {
12793 long lret = fence_wait(plane_state->fence, true);
12794
12795 if (lret < 0) {
12796 ret = lret;
12797 break;
12798 }
12799 }
12800
12801 if (!intel_plane_state->wait_req)
12802 continue;
12803
12804 ret = __i915_wait_request(intel_plane_state->wait_req,
12805 true, NULL, NULL);
12806 if (ret) {
12807 /* Any hang should be swallowed by the wait */
12808 WARN_ON(ret == -EIO);
12809 mutex_lock(&dev->struct_mutex);
12810 drm_atomic_helper_cleanup_planes(dev, state);
12811 mutex_unlock(&dev->struct_mutex);
12812 break;
12813 }
12814 }
12815 }
12816
12817 return ret;
12818 }
12819
12820 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12821 {
12822 struct drm_device *dev = crtc->base.dev;
12823
12824 if (!dev->max_vblank_count)
12825 return drm_accurate_vblank_count(&crtc->base);
12826
12827 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12828 }
12829
12830 static void intel_prepare_work(struct drm_crtc *crtc,
12831 struct intel_flip_work *work,
12832 struct drm_atomic_state *state,
12833 struct drm_crtc_state *old_crtc_state)
12834 {
12835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12836 struct drm_plane_state *old_plane_state;
12837 struct drm_plane *plane;
12838 int i, j = 0;
12839
12840 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12841 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12842 atomic_inc(&intel_crtc->unpin_work_count);
12843
12844 for_each_plane_in_state(state, plane, old_plane_state, i) {
12845 struct intel_plane_state *old_state = to_intel_plane_state(old_plane_state);
12846 struct intel_plane_state *new_state = to_intel_plane_state(plane->state);
12847
12848 if (old_state->base.crtc != crtc &&
12849 new_state->base.crtc != crtc)
12850 continue;
12851
12852 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
12853 plane->fb = new_state->base.fb;
12854 crtc->x = new_state->base.src_x >> 16;
12855 crtc->y = new_state->base.src_y >> 16;
12856 }
12857
12858 old_state->wait_req = new_state->wait_req;
12859 new_state->wait_req = NULL;
12860
12861 old_state->base.fence = new_state->base.fence;
12862 new_state->base.fence = NULL;
12863
12864 /* remove plane state from the atomic state and move it to work */
12865 old_plane_state->state = NULL;
12866 state->planes[i] = NULL;
12867 state->plane_states[i] = NULL;
12868
12869 work->old_plane_state[j] = old_state;
12870 work->new_plane_state[j++] = new_state;
12871 }
12872
12873 old_crtc_state->state = NULL;
12874 state->crtcs[drm_crtc_index(crtc)] = NULL;
12875 state->crtc_states[drm_crtc_index(crtc)] = NULL;
12876
12877 work->old_crtc_state = to_intel_crtc_state(old_crtc_state);
12878 work->new_crtc_state = to_intel_crtc_state(crtc->state);
12879 work->num_planes = j;
12880
12881 work->event = crtc->state->event;
12882 crtc->state->event = NULL;
12883
12884 if (needs_modeset(crtc->state) || work->new_crtc_state->update_pipe) {
12885 struct drm_connector *conn;
12886 struct drm_connector_state *old_conn_state;
12887 int k = 0;
12888
12889 j = 0;
12890
12891 /*
12892 * intel_unpin_work_fn cannot depend on the connector list
12893 * because it may be freed from underneath it, so add
12894 * them all to the work struct while we're holding locks.
12895 */
12896 for_each_connector_in_state(state, conn, old_conn_state, i) {
12897 if (old_conn_state->crtc == crtc) {
12898 work->old_connector_state[j++] = old_conn_state;
12899
12900 state->connectors[i] = NULL;
12901 state->connector_states[i] = NULL;
12902 }
12903 }
12904
12905 /* If another crtc has stolen the connector from state,
12906 * then for_each_connector_in_state is no longer reliable,
12907 * so use drm_for_each_connector here.
12908 */
12909 drm_for_each_connector(conn, state->dev)
12910 if (conn->state->crtc == crtc)
12911 work->new_connector_state[k++] = conn->state;
12912
12913 WARN(j != work->num_old_connectors, "j = %i, expected %i\n", j, work->num_old_connectors);
12914 WARN(k != work->num_new_connectors, "k = %i, expected %i\n", k, work->num_new_connectors);
12915 } else if (!work->new_crtc_state->update_wm_post)
12916 work->can_async_unpin = true;
12917
12918 work->fb_bits = work->new_crtc_state->fb_bits;
12919 }
12920
12921 static void intel_schedule_unpin(struct drm_crtc *crtc,
12922 struct intel_atomic_state *state,
12923 struct intel_flip_work *work)
12924 {
12925 struct drm_device *dev = crtc->dev;
12926 struct drm_i915_private *dev_priv = dev->dev_private;
12927
12928 to_intel_crtc(crtc)->config = work->new_crtc_state;
12929
12930 queue_work(dev_priv->wq, &work->unpin_work);
12931 }
12932
12933 static void intel_schedule_flip(struct drm_crtc *crtc,
12934 struct intel_atomic_state *state,
12935 struct intel_flip_work *work,
12936 bool nonblock)
12937 {
12938 struct intel_crtc_state *crtc_state = work->new_crtc_state;
12939
12940 if (crtc_state->base.planes_changed ||
12941 needs_modeset(&crtc_state->base) ||
12942 crtc_state->update_pipe) {
12943 if (nonblock)
12944 schedule_work(&work->mmio_work);
12945 else
12946 intel_mmio_flip_work_func(&work->mmio_work);
12947 } else {
12948 int ret;
12949
12950 ret = drm_crtc_vblank_get(crtc);
12951 I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
12952
12953 work->flip_queued_vblank = intel_crtc_get_vblank_counter(to_intel_crtc(crtc));
12954 smp_mb__before_atomic();
12955 atomic_set(&work->pending, 1);
12956 }
12957 }
12958
12959 static void intel_schedule_update(struct drm_crtc *crtc,
12960 struct intel_atomic_state *state,
12961 struct intel_flip_work *work,
12962 bool nonblock)
12963 {
12964 struct drm_device *dev = crtc->dev;
12965 struct intel_crtc_state *pipe_config = work->new_crtc_state;
12966
12967 if (!pipe_config->base.active && work->can_async_unpin) {
12968 INIT_LIST_HEAD(&work->head);
12969 intel_schedule_unpin(crtc, state, work);
12970 return;
12971 }
12972
12973 spin_lock_irq(&dev->event_lock);
12974 list_add_tail(&work->head, &to_intel_crtc(crtc)->flip_work);
12975 spin_unlock_irq(&dev->event_lock);
12976
12977 if (!pipe_config->base.active)
12978 intel_schedule_unpin(crtc, state, work);
12979 else
12980 intel_schedule_flip(crtc, state, work, nonblock);
12981 }
12982
12983 /**
12984 * intel_atomic_commit - commit validated state object
12985 * @dev: DRM device
12986 * @state: the top-level driver state object
12987 * @nonblock: nonblocking commit
12988 *
12989 * This function commits a top-level state object that has been validated
12990 * with drm_atomic_helper_check().
12991 *
12992 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
12993 * we can only handle plane-related operations and do not yet support
12994 * nonblocking commit.
12995 *
12996 * RETURNS
12997 * Zero for success or -errno.
12998 */
12999 static int intel_atomic_commit(struct drm_device *dev,
13000 struct drm_atomic_state *state,
13001 bool nonblock)
13002 {
13003 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13004 struct drm_i915_private *dev_priv = dev->dev_private;
13005 struct drm_crtc_state *old_crtc_state;
13006 struct drm_crtc *crtc;
13007 int ret = 0, i;
13008
13009 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13010 if (ret) {
13011 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13012 return ret;
13013 }
13014
13015 drm_atomic_helper_swap_state(dev, state);
13016 dev_priv->wm.distrust_bios_wm = false;
13017 dev_priv->wm.skl_results = intel_state->wm_results;
13018 intel_shared_dpll_commit(state);
13019
13020 if (intel_state->modeset) {
13021 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13022 sizeof(intel_state->min_pixclk));
13023 dev_priv->active_crtcs = intel_state->active_crtcs;
13024 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13025 }
13026
13027 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13029
13030 if (!needs_modeset(crtc->state))
13031 continue;
13032
13033 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13034
13035 intel_state->work[i]->put_power_domains =
13036 modeset_get_crtc_power_domains(crtc,
13037 to_intel_crtc_state(crtc->state));
13038
13039 if (old_crtc_state->active) {
13040 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13041 dev_priv->display.crtc_disable(crtc);
13042 intel_crtc->active = false;
13043 intel_fbc_disable(intel_crtc);
13044 intel_disable_shared_dpll(intel_crtc);
13045
13046 /*
13047 * Underruns don't always raise
13048 * interrupts, so check manually.
13049 */
13050 intel_check_cpu_fifo_underruns(dev_priv);
13051 intel_check_pch_fifo_underruns(dev_priv);
13052
13053 if (!crtc->state->active)
13054 intel_update_watermarks(crtc);
13055 }
13056 }
13057
13058 /* Only after disabling all output pipelines that will be changed can we
13059 * update the the output configuration. */
13060 intel_modeset_update_crtc_state(state);
13061
13062 if (intel_state->modeset) {
13063 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13064
13065 if (dev_priv->display.modeset_commit_cdclk &&
13066 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13067 dev_priv->display.modeset_commit_cdclk(state);
13068
13069 intel_modeset_verify_disabled(dev);
13070 }
13071
13072 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13073 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13074 struct intel_flip_work *work = intel_state->work[i];
13075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13076 bool modeset = needs_modeset(crtc->state);
13077
13078 if (modeset && crtc->state->active) {
13079 update_scanline_offset(to_intel_crtc(crtc));
13080 dev_priv->display.crtc_enable(crtc);
13081 }
13082
13083 if (!modeset)
13084 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13085
13086 if (!work) {
13087 if (!list_empty_careful(&intel_crtc->flip_work)) {
13088 spin_lock_irq(&dev->event_lock);
13089 if (!list_empty(&intel_crtc->flip_work))
13090 work = list_last_entry(&intel_crtc->flip_work,
13091 struct intel_flip_work, head);
13092
13093 if (work && work->new_crtc_state == to_intel_crtc_state(old_crtc_state)) {
13094 work->free_new_crtc_state = true;
13095 state->crtc_states[i] = NULL;
13096 state->crtcs[i] = NULL;
13097 }
13098 spin_unlock_irq(&dev->event_lock);
13099 }
13100 continue;
13101 }
13102
13103 intel_state->work[i] = NULL;
13104 intel_prepare_work(crtc, work, state, old_crtc_state);
13105 intel_schedule_update(crtc, intel_state, work, nonblock);
13106 }
13107
13108 /* FIXME: add subpixel order */
13109
13110 drm_atomic_state_free(state);
13111
13112 /* As one of the primary mmio accessors, KMS has a high likelihood
13113 * of triggering bugs in unclaimed access. After we finish
13114 * modesetting, see if an error has been flagged, and if so
13115 * enable debugging for the next modeset - and hope we catch
13116 * the culprit.
13117 *
13118 * XXX note that we assume display power is on at this point.
13119 * This might hold true now but we need to add pm helper to check
13120 * unclaimed only when the hardware is on, as atomic commits
13121 * can happen also when the device is completely off.
13122 */
13123 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13124
13125 return 0;
13126 }
13127
13128 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13129 {
13130 struct drm_device *dev = crtc->dev;
13131 struct drm_atomic_state *state;
13132 struct drm_crtc_state *crtc_state;
13133 int ret;
13134
13135 state = drm_atomic_state_alloc(dev);
13136 if (!state) {
13137 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13138 crtc->base.id);
13139 return;
13140 }
13141
13142 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13143
13144 retry:
13145 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13146 ret = PTR_ERR_OR_ZERO(crtc_state);
13147 if (!ret) {
13148 if (!crtc_state->active)
13149 goto out;
13150
13151 crtc_state->mode_changed = true;
13152 ret = drm_atomic_commit(state);
13153 }
13154
13155 if (ret == -EDEADLK) {
13156 drm_atomic_state_clear(state);
13157 drm_modeset_backoff(state->acquire_ctx);
13158 goto retry;
13159 }
13160
13161 if (ret)
13162 out:
13163 drm_atomic_state_free(state);
13164 }
13165
13166 #undef for_each_intel_crtc_masked
13167
13168 static const struct drm_crtc_funcs intel_crtc_funcs = {
13169 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13170 .set_config = drm_atomic_helper_set_config,
13171 .set_property = drm_atomic_helper_crtc_set_property,
13172 .destroy = intel_crtc_destroy,
13173 .page_flip = drm_atomic_helper_page_flip,
13174 .atomic_duplicate_state = intel_crtc_duplicate_state,
13175 .atomic_destroy_state = intel_crtc_destroy_state,
13176 };
13177
13178 static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
13179 {
13180 struct reservation_object *resv;
13181
13182
13183 if (!obj->base.dma_buf)
13184 return NULL;
13185
13186 resv = obj->base.dma_buf->resv;
13187
13188 /* For framebuffer backed by dmabuf, wait for fence */
13189 while (1) {
13190 struct fence *fence_excl, *ret = NULL;
13191
13192 rcu_read_lock();
13193
13194 fence_excl = rcu_dereference(resv->fence_excl);
13195 if (fence_excl)
13196 ret = fence_get_rcu(fence_excl);
13197
13198 rcu_read_unlock();
13199
13200 if (ret == fence_excl)
13201 return ret;
13202 }
13203 }
13204
13205 /**
13206 * intel_prepare_plane_fb - Prepare fb for usage on plane
13207 * @plane: drm plane to prepare for
13208 * @fb: framebuffer to prepare for presentation
13209 *
13210 * Prepares a framebuffer for usage on a display plane. Generally this
13211 * involves pinning the underlying object and updating the frontbuffer tracking
13212 * bits. Some older platforms need special physical address handling for
13213 * cursor planes.
13214 *
13215 * Must be called with struct_mutex held.
13216 *
13217 * Returns 0 on success, negative error code on failure.
13218 */
13219 int
13220 intel_prepare_plane_fb(struct drm_plane *plane,
13221 const struct drm_plane_state *new_state)
13222 {
13223 struct drm_device *dev = plane->dev;
13224 struct drm_framebuffer *fb = new_state->fb;
13225 struct intel_plane *intel_plane = to_intel_plane(plane);
13226 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13227 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13228 struct drm_crtc *crtc = new_state->crtc ?: plane->state->crtc;
13229 int ret = 0;
13230
13231 if (!obj && !old_obj)
13232 return 0;
13233
13234 if (WARN_ON(!new_state->state) || WARN_ON(!crtc) ||
13235 WARN_ON(!to_intel_atomic_state(new_state->state)->work[to_intel_crtc(crtc)->pipe])) {
13236 if (WARN_ON(old_obj != obj))
13237 return -EINVAL;
13238
13239 return 0;
13240 }
13241
13242 if (old_obj) {
13243 struct drm_crtc_state *crtc_state =
13244 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13245
13246 /* Big Hammer, we also need to ensure that any pending
13247 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13248 * current scanout is retired before unpinning the old
13249 * framebuffer. Note that we rely on userspace rendering
13250 * into the buffer attached to the pipe they are waiting
13251 * on. If not, userspace generates a GPU hang with IPEHR
13252 * point to the MI_WAIT_FOR_EVENT.
13253 *
13254 * This should only fail upon a hung GPU, in which case we
13255 * can safely continue.
13256 */
13257 if (needs_modeset(crtc_state))
13258 ret = i915_gem_object_wait_rendering(old_obj, true);
13259 if (ret) {
13260 /* GPU hangs should have been swallowed by the wait */
13261 WARN_ON(ret == -EIO);
13262 return ret;
13263 }
13264 }
13265
13266 if (!obj) {
13267 ret = 0;
13268 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13269 INTEL_INFO(dev)->cursor_needs_physical) {
13270 int align = IS_I830(dev) ? 16 * 1024 : 256;
13271 ret = i915_gem_object_attach_phys(obj, align);
13272 if (ret)
13273 DRM_DEBUG_KMS("failed to attach phys object\n");
13274 } else {
13275 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13276 }
13277
13278 if (ret == 0) {
13279 if (obj) {
13280 struct intel_plane_state *plane_state =
13281 to_intel_plane_state(new_state);
13282
13283 i915_gem_request_assign(&plane_state->wait_req,
13284 obj->last_write_req);
13285
13286 plane_state->base.fence = intel_get_excl_fence(obj);
13287 }
13288
13289 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13290 }
13291
13292 return ret;
13293 }
13294
13295 /**
13296 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13297 * @plane: drm plane to clean up for
13298 * @fb: old framebuffer that was on plane
13299 *
13300 * Cleans up a framebuffer that has just been removed from a plane.
13301 *
13302 * Must be called with struct_mutex held.
13303 */
13304 void
13305 intel_cleanup_plane_fb(struct drm_plane *plane,
13306 const struct drm_plane_state *old_state)
13307 {
13308 struct drm_device *dev = plane->dev;
13309 struct intel_plane *intel_plane = to_intel_plane(plane);
13310 struct intel_plane_state *old_intel_state;
13311 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13312 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13313
13314 old_intel_state = to_intel_plane_state(old_state);
13315
13316 if (!obj && !old_obj)
13317 return;
13318
13319 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13320 !INTEL_INFO(dev)->cursor_needs_physical))
13321 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13322
13323 /* prepare_fb aborted? */
13324 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13325 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13326 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13327
13328 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13329
13330 fence_put(old_intel_state->base.fence);
13331 old_intel_state->base.fence = NULL;
13332 }
13333
13334 int
13335 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13336 {
13337 int max_scale;
13338 struct drm_device *dev;
13339 struct drm_i915_private *dev_priv;
13340 int crtc_clock, cdclk;
13341
13342 if (!intel_crtc || !crtc_state->base.enable)
13343 return DRM_PLANE_HELPER_NO_SCALING;
13344
13345 dev = intel_crtc->base.dev;
13346 dev_priv = dev->dev_private;
13347 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13348 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13349
13350 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13351 return DRM_PLANE_HELPER_NO_SCALING;
13352
13353 /*
13354 * skl max scale is lower of:
13355 * close to 3 but not 3, -1 is for that purpose
13356 * or
13357 * cdclk/crtc_clock
13358 */
13359 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13360
13361 return max_scale;
13362 }
13363
13364 static int
13365 intel_check_primary_plane(struct drm_plane *plane,
13366 struct intel_crtc_state *crtc_state,
13367 struct intel_plane_state *state)
13368 {
13369 struct drm_crtc *crtc = state->base.crtc;
13370 struct drm_framebuffer *fb = state->base.fb;
13371 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13372 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13373 bool can_position = false;
13374
13375 if (INTEL_INFO(plane->dev)->gen >= 9) {
13376 /* use scaler when colorkey is not required */
13377 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13378 min_scale = 1;
13379 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13380 }
13381 can_position = true;
13382 }
13383
13384 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13385 &state->dst, &state->clip,
13386 min_scale, max_scale,
13387 can_position, true,
13388 &state->visible);
13389 }
13390
13391 /**
13392 * intel_plane_destroy - destroy a plane
13393 * @plane: plane to destroy
13394 *
13395 * Common destruction function for all types of planes (primary, cursor,
13396 * sprite).
13397 */
13398 void intel_plane_destroy(struct drm_plane *plane)
13399 {
13400 struct intel_plane *intel_plane = to_intel_plane(plane);
13401 drm_plane_cleanup(plane);
13402 kfree(intel_plane);
13403 }
13404
13405 const struct drm_plane_funcs intel_plane_funcs = {
13406 .update_plane = drm_atomic_helper_update_plane,
13407 .disable_plane = drm_atomic_helper_disable_plane,
13408 .destroy = intel_plane_destroy,
13409 .set_property = drm_atomic_helper_plane_set_property,
13410 .atomic_get_property = intel_plane_atomic_get_property,
13411 .atomic_set_property = intel_plane_atomic_set_property,
13412 .atomic_duplicate_state = intel_plane_duplicate_state,
13413 .atomic_destroy_state = intel_plane_destroy_state,
13414
13415 };
13416
13417 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13418 int pipe)
13419 {
13420 struct intel_plane *primary = NULL;
13421 struct intel_plane_state *state = NULL;
13422 const uint32_t *intel_primary_formats;
13423 unsigned int num_formats;
13424 int ret;
13425
13426 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13427 if (!primary)
13428 goto fail;
13429
13430 state = intel_create_plane_state(&primary->base);
13431 if (!state)
13432 goto fail;
13433 primary->base.state = &state->base;
13434
13435 primary->can_scale = false;
13436 primary->max_downscale = 1;
13437 if (INTEL_INFO(dev)->gen >= 9) {
13438 primary->can_scale = true;
13439 state->scaler_id = -1;
13440 }
13441 primary->pipe = pipe;
13442 primary->plane = pipe;
13443 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13444 primary->check_plane = intel_check_primary_plane;
13445 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13446 primary->plane = !pipe;
13447
13448 if (INTEL_INFO(dev)->gen >= 9) {
13449 intel_primary_formats = skl_primary_formats;
13450 num_formats = ARRAY_SIZE(skl_primary_formats);
13451
13452 primary->update_plane = skylake_update_primary_plane;
13453 primary->disable_plane = skylake_disable_primary_plane;
13454 } else if (HAS_PCH_SPLIT(dev)) {
13455 intel_primary_formats = i965_primary_formats;
13456 num_formats = ARRAY_SIZE(i965_primary_formats);
13457
13458 primary->update_plane = ironlake_update_primary_plane;
13459 primary->disable_plane = i9xx_disable_primary_plane;
13460 } else if (INTEL_INFO(dev)->gen >= 4) {
13461 intel_primary_formats = i965_primary_formats;
13462 num_formats = ARRAY_SIZE(i965_primary_formats);
13463
13464 primary->update_plane = i9xx_update_primary_plane;
13465 primary->disable_plane = i9xx_disable_primary_plane;
13466 } else {
13467 intel_primary_formats = i8xx_primary_formats;
13468 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13469
13470 primary->update_plane = i9xx_update_primary_plane;
13471 primary->disable_plane = i9xx_disable_primary_plane;
13472 }
13473
13474 ret = drm_universal_plane_init(dev, &primary->base, 0,
13475 &intel_plane_funcs,
13476 intel_primary_formats, num_formats,
13477 DRM_PLANE_TYPE_PRIMARY, NULL);
13478 if (ret)
13479 goto fail;
13480
13481 if (INTEL_INFO(dev)->gen >= 4)
13482 intel_create_rotation_property(dev, primary);
13483
13484 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13485
13486 return &primary->base;
13487
13488 fail:
13489 kfree(state);
13490 kfree(primary);
13491
13492 return NULL;
13493 }
13494
13495 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13496 {
13497 if (!dev->mode_config.rotation_property) {
13498 unsigned long flags = BIT(DRM_ROTATE_0) |
13499 BIT(DRM_ROTATE_180);
13500
13501 if (INTEL_INFO(dev)->gen >= 9)
13502 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13503
13504 dev->mode_config.rotation_property =
13505 drm_mode_create_rotation_property(dev, flags);
13506 }
13507 if (dev->mode_config.rotation_property)
13508 drm_object_attach_property(&plane->base.base,
13509 dev->mode_config.rotation_property,
13510 plane->base.state->rotation);
13511 }
13512
13513 static int
13514 intel_check_cursor_plane(struct drm_plane *plane,
13515 struct intel_crtc_state *crtc_state,
13516 struct intel_plane_state *state)
13517 {
13518 struct drm_crtc *crtc = crtc_state->base.crtc;
13519 struct drm_framebuffer *fb = state->base.fb;
13520 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13521 enum pipe pipe = to_intel_plane(plane)->pipe;
13522 unsigned stride;
13523 int ret;
13524
13525 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13526 &state->dst, &state->clip,
13527 DRM_PLANE_HELPER_NO_SCALING,
13528 DRM_PLANE_HELPER_NO_SCALING,
13529 true, true, &state->visible);
13530 if (ret)
13531 return ret;
13532
13533 /* if we want to turn off the cursor ignore width and height */
13534 if (!obj)
13535 return 0;
13536
13537 /* Check for which cursor types we support */
13538 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13539 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13540 state->base.crtc_w, state->base.crtc_h);
13541 return -EINVAL;
13542 }
13543
13544 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13545 if (obj->base.size < stride * state->base.crtc_h) {
13546 DRM_DEBUG_KMS("buffer is too small\n");
13547 return -ENOMEM;
13548 }
13549
13550 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13551 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13552 return -EINVAL;
13553 }
13554
13555 /*
13556 * There's something wrong with the cursor on CHV pipe C.
13557 * If it straddles the left edge of the screen then
13558 * moving it away from the edge or disabling it often
13559 * results in a pipe underrun, and often that can lead to
13560 * dead pipe (constant underrun reported, and it scans
13561 * out just a solid color). To recover from that, the
13562 * display power well must be turned off and on again.
13563 * Refuse the put the cursor into that compromised position.
13564 */
13565 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
13566 state->visible && state->base.crtc_x < 0) {
13567 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13568 return -EINVAL;
13569 }
13570
13571 return 0;
13572 }
13573
13574 static void
13575 intel_disable_cursor_plane(struct drm_plane *plane,
13576 struct drm_crtc *crtc)
13577 {
13578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13579
13580 intel_crtc->cursor_addr = 0;
13581 intel_crtc_update_cursor(crtc, NULL);
13582 }
13583
13584 static void
13585 intel_update_cursor_plane(struct drm_plane *plane,
13586 const struct intel_crtc_state *crtc_state,
13587 const struct intel_plane_state *state)
13588 {
13589 struct drm_crtc *crtc = crtc_state->base.crtc;
13590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13591 struct drm_device *dev = plane->dev;
13592 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13593 uint32_t addr;
13594
13595 if (!obj)
13596 addr = 0;
13597 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13598 addr = i915_gem_obj_ggtt_offset(obj);
13599 else
13600 addr = obj->phys_handle->busaddr;
13601
13602 intel_crtc->cursor_addr = addr;
13603 intel_crtc_update_cursor(crtc, state);
13604 }
13605
13606 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13607 int pipe)
13608 {
13609 struct intel_plane *cursor = NULL;
13610 struct intel_plane_state *state = NULL;
13611 int ret;
13612
13613 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13614 if (!cursor)
13615 goto fail;
13616
13617 state = intel_create_plane_state(&cursor->base);
13618 if (!state)
13619 goto fail;
13620 cursor->base.state = &state->base;
13621
13622 cursor->can_scale = false;
13623 cursor->max_downscale = 1;
13624 cursor->pipe = pipe;
13625 cursor->plane = pipe;
13626 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13627 cursor->check_plane = intel_check_cursor_plane;
13628 cursor->update_plane = intel_update_cursor_plane;
13629 cursor->disable_plane = intel_disable_cursor_plane;
13630
13631 ret = drm_universal_plane_init(dev, &cursor->base, 0,
13632 &intel_plane_funcs,
13633 intel_cursor_formats,
13634 ARRAY_SIZE(intel_cursor_formats),
13635 DRM_PLANE_TYPE_CURSOR, NULL);
13636 if (ret)
13637 goto fail;
13638
13639 if (INTEL_INFO(dev)->gen >= 4) {
13640 if (!dev->mode_config.rotation_property)
13641 dev->mode_config.rotation_property =
13642 drm_mode_create_rotation_property(dev,
13643 BIT(DRM_ROTATE_0) |
13644 BIT(DRM_ROTATE_180));
13645 if (dev->mode_config.rotation_property)
13646 drm_object_attach_property(&cursor->base.base,
13647 dev->mode_config.rotation_property,
13648 state->base.rotation);
13649 }
13650
13651 if (INTEL_INFO(dev)->gen >=9)
13652 state->scaler_id = -1;
13653
13654 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13655
13656 return &cursor->base;
13657
13658 fail:
13659 kfree(state);
13660 kfree(cursor);
13661
13662 return NULL;
13663 }
13664
13665 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13666 struct intel_crtc_state *crtc_state)
13667 {
13668 int i;
13669 struct intel_scaler *intel_scaler;
13670 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13671
13672 for (i = 0; i < intel_crtc->num_scalers; i++) {
13673 intel_scaler = &scaler_state->scalers[i];
13674 intel_scaler->in_use = 0;
13675 intel_scaler->mode = PS_SCALER_MODE_DYN;
13676 }
13677
13678 scaler_state->scaler_id = -1;
13679 }
13680
13681 static void intel_crtc_init(struct drm_device *dev, int pipe)
13682 {
13683 struct drm_i915_private *dev_priv = dev->dev_private;
13684 struct intel_crtc *intel_crtc;
13685 struct intel_crtc_state *crtc_state = NULL;
13686 struct drm_plane *primary = NULL;
13687 struct drm_plane *cursor = NULL;
13688 int ret;
13689
13690 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13691 if (intel_crtc == NULL)
13692 return;
13693
13694 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13695 if (!crtc_state)
13696 goto fail;
13697 intel_crtc->config = crtc_state;
13698 intel_crtc->base.state = &crtc_state->base;
13699 crtc_state->base.crtc = &intel_crtc->base;
13700
13701 INIT_LIST_HEAD(&intel_crtc->flip_work);
13702
13703 /* initialize shared scalers */
13704 if (INTEL_INFO(dev)->gen >= 9) {
13705 if (pipe == PIPE_C)
13706 intel_crtc->num_scalers = 1;
13707 else
13708 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13709
13710 skl_init_scalers(dev, intel_crtc, crtc_state);
13711 }
13712
13713 primary = intel_primary_plane_create(dev, pipe);
13714 if (!primary)
13715 goto fail;
13716
13717 cursor = intel_cursor_plane_create(dev, pipe);
13718 if (!cursor)
13719 goto fail;
13720
13721 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13722 cursor, &intel_crtc_funcs, NULL);
13723 if (ret)
13724 goto fail;
13725
13726 /*
13727 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13728 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13729 */
13730 intel_crtc->pipe = pipe;
13731 intel_crtc->plane = pipe;
13732 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13733 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13734 intel_crtc->plane = !pipe;
13735 }
13736
13737 intel_crtc->cursor_base = ~0;
13738 intel_crtc->cursor_cntl = ~0;
13739 intel_crtc->cursor_size = ~0;
13740
13741 intel_crtc->wm.cxsr_allowed = true;
13742
13743 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13744 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13745 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13746 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13747
13748 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13749
13750 intel_color_init(&intel_crtc->base);
13751
13752 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13753 return;
13754
13755 fail:
13756 if (primary)
13757 drm_plane_cleanup(primary);
13758 if (cursor)
13759 drm_plane_cleanup(cursor);
13760 kfree(crtc_state);
13761 kfree(intel_crtc);
13762 }
13763
13764 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13765 {
13766 struct drm_encoder *encoder = connector->base.encoder;
13767 struct drm_device *dev = connector->base.dev;
13768
13769 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13770
13771 if (!encoder || WARN_ON(!encoder->crtc))
13772 return INVALID_PIPE;
13773
13774 return to_intel_crtc(encoder->crtc)->pipe;
13775 }
13776
13777 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13778 struct drm_file *file)
13779 {
13780 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13781 struct drm_crtc *drmmode_crtc;
13782 struct intel_crtc *crtc;
13783
13784 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13785
13786 if (!drmmode_crtc) {
13787 DRM_ERROR("no such CRTC id\n");
13788 return -ENOENT;
13789 }
13790
13791 crtc = to_intel_crtc(drmmode_crtc);
13792 pipe_from_crtc_id->pipe = crtc->pipe;
13793
13794 return 0;
13795 }
13796
13797 static int intel_encoder_clones(struct intel_encoder *encoder)
13798 {
13799 struct drm_device *dev = encoder->base.dev;
13800 struct intel_encoder *source_encoder;
13801 int index_mask = 0;
13802 int entry = 0;
13803
13804 for_each_intel_encoder(dev, source_encoder) {
13805 if (encoders_cloneable(encoder, source_encoder))
13806 index_mask |= (1 << entry);
13807
13808 entry++;
13809 }
13810
13811 return index_mask;
13812 }
13813
13814 static bool has_edp_a(struct drm_device *dev)
13815 {
13816 struct drm_i915_private *dev_priv = dev->dev_private;
13817
13818 if (!IS_MOBILE(dev))
13819 return false;
13820
13821 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13822 return false;
13823
13824 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13825 return false;
13826
13827 return true;
13828 }
13829
13830 static bool intel_crt_present(struct drm_device *dev)
13831 {
13832 struct drm_i915_private *dev_priv = dev->dev_private;
13833
13834 if (INTEL_INFO(dev)->gen >= 9)
13835 return false;
13836
13837 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13838 return false;
13839
13840 if (IS_CHERRYVIEW(dev))
13841 return false;
13842
13843 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13844 return false;
13845
13846 /* DDI E can't be used if DDI A requires 4 lanes */
13847 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13848 return false;
13849
13850 if (!dev_priv->vbt.int_crt_support)
13851 return false;
13852
13853 return true;
13854 }
13855
13856 static void intel_setup_outputs(struct drm_device *dev)
13857 {
13858 struct drm_i915_private *dev_priv = dev->dev_private;
13859 struct intel_encoder *encoder;
13860 bool dpd_is_edp = false;
13861
13862 intel_lvds_init(dev);
13863
13864 if (intel_crt_present(dev))
13865 intel_crt_init(dev);
13866
13867 if (IS_BROXTON(dev)) {
13868 /*
13869 * FIXME: Broxton doesn't support port detection via the
13870 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13871 * detect the ports.
13872 */
13873 intel_ddi_init(dev, PORT_A);
13874 intel_ddi_init(dev, PORT_B);
13875 intel_ddi_init(dev, PORT_C);
13876
13877 intel_dsi_init(dev);
13878 } else if (HAS_DDI(dev)) {
13879 int found;
13880
13881 /*
13882 * Haswell uses DDI functions to detect digital outputs.
13883 * On SKL pre-D0 the strap isn't connected, so we assume
13884 * it's there.
13885 */
13886 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13887 /* WaIgnoreDDIAStrap: skl */
13888 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
13889 intel_ddi_init(dev, PORT_A);
13890
13891 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13892 * register */
13893 found = I915_READ(SFUSE_STRAP);
13894
13895 if (found & SFUSE_STRAP_DDIB_DETECTED)
13896 intel_ddi_init(dev, PORT_B);
13897 if (found & SFUSE_STRAP_DDIC_DETECTED)
13898 intel_ddi_init(dev, PORT_C);
13899 if (found & SFUSE_STRAP_DDID_DETECTED)
13900 intel_ddi_init(dev, PORT_D);
13901 /*
13902 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13903 */
13904 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
13905 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13906 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13907 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13908 intel_ddi_init(dev, PORT_E);
13909
13910 } else if (HAS_PCH_SPLIT(dev)) {
13911 int found;
13912 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13913
13914 if (has_edp_a(dev))
13915 intel_dp_init(dev, DP_A, PORT_A);
13916
13917 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13918 /* PCH SDVOB multiplex with HDMIB */
13919 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
13920 if (!found)
13921 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13922 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13923 intel_dp_init(dev, PCH_DP_B, PORT_B);
13924 }
13925
13926 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13927 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13928
13929 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13930 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13931
13932 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13933 intel_dp_init(dev, PCH_DP_C, PORT_C);
13934
13935 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13936 intel_dp_init(dev, PCH_DP_D, PORT_D);
13937 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
13938 /*
13939 * The DP_DETECTED bit is the latched state of the DDC
13940 * SDA pin at boot. However since eDP doesn't require DDC
13941 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13942 * eDP ports may have been muxed to an alternate function.
13943 * Thus we can't rely on the DP_DETECTED bit alone to detect
13944 * eDP ports. Consult the VBT as well as DP_DETECTED to
13945 * detect eDP ports.
13946 */
13947 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
13948 !intel_dp_is_edp(dev, PORT_B))
13949 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
13950 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
13951 intel_dp_is_edp(dev, PORT_B))
13952 intel_dp_init(dev, VLV_DP_B, PORT_B);
13953
13954 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
13955 !intel_dp_is_edp(dev, PORT_C))
13956 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
13957 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
13958 intel_dp_is_edp(dev, PORT_C))
13959 intel_dp_init(dev, VLV_DP_C, PORT_C);
13960
13961 if (IS_CHERRYVIEW(dev)) {
13962 /* eDP not supported on port D, so don't check VBT */
13963 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
13964 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
13965 if (I915_READ(CHV_DP_D) & DP_DETECTED)
13966 intel_dp_init(dev, CHV_DP_D, PORT_D);
13967 }
13968
13969 intel_dsi_init(dev);
13970 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
13971 bool found = false;
13972
13973 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13974 DRM_DEBUG_KMS("probing SDVOB\n");
13975 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
13976 if (!found && IS_G4X(dev)) {
13977 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13978 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13979 }
13980
13981 if (!found && IS_G4X(dev))
13982 intel_dp_init(dev, DP_B, PORT_B);
13983 }
13984
13985 /* Before G4X SDVOC doesn't have its own detect register */
13986
13987 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13988 DRM_DEBUG_KMS("probing SDVOC\n");
13989 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
13990 }
13991
13992 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13993
13994 if (IS_G4X(dev)) {
13995 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13996 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13997 }
13998 if (IS_G4X(dev))
13999 intel_dp_init(dev, DP_C, PORT_C);
14000 }
14001
14002 if (IS_G4X(dev) &&
14003 (I915_READ(DP_D) & DP_DETECTED))
14004 intel_dp_init(dev, DP_D, PORT_D);
14005 } else if (IS_GEN2(dev))
14006 intel_dvo_init(dev);
14007
14008 if (SUPPORTS_TV(dev))
14009 intel_tv_init(dev);
14010
14011 intel_psr_init(dev);
14012
14013 for_each_intel_encoder(dev, encoder) {
14014 encoder->base.possible_crtcs = encoder->crtc_mask;
14015 encoder->base.possible_clones =
14016 intel_encoder_clones(encoder);
14017 }
14018
14019 intel_init_pch_refclk(dev);
14020
14021 drm_helper_move_panel_connectors_to_head(dev);
14022 }
14023
14024 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14025 {
14026 struct drm_device *dev = fb->dev;
14027 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14028
14029 drm_framebuffer_cleanup(fb);
14030 mutex_lock(&dev->struct_mutex);
14031 WARN_ON(!intel_fb->obj->framebuffer_references--);
14032 drm_gem_object_unreference(&intel_fb->obj->base);
14033 mutex_unlock(&dev->struct_mutex);
14034 kfree(intel_fb);
14035 }
14036
14037 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14038 struct drm_file *file,
14039 unsigned int *handle)
14040 {
14041 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14042 struct drm_i915_gem_object *obj = intel_fb->obj;
14043
14044 if (obj->userptr.mm) {
14045 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14046 return -EINVAL;
14047 }
14048
14049 return drm_gem_handle_create(file, &obj->base, handle);
14050 }
14051
14052 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14053 struct drm_file *file,
14054 unsigned flags, unsigned color,
14055 struct drm_clip_rect *clips,
14056 unsigned num_clips)
14057 {
14058 struct drm_device *dev = fb->dev;
14059 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14060 struct drm_i915_gem_object *obj = intel_fb->obj;
14061
14062 mutex_lock(&dev->struct_mutex);
14063 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14064 mutex_unlock(&dev->struct_mutex);
14065
14066 return 0;
14067 }
14068
14069 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14070 .destroy = intel_user_framebuffer_destroy,
14071 .create_handle = intel_user_framebuffer_create_handle,
14072 .dirty = intel_user_framebuffer_dirty,
14073 };
14074
14075 static
14076 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14077 uint32_t pixel_format)
14078 {
14079 u32 gen = INTEL_INFO(dev)->gen;
14080
14081 if (gen >= 9) {
14082 int cpp = drm_format_plane_cpp(pixel_format, 0);
14083
14084 /* "The stride in bytes must not exceed the of the size of 8K
14085 * pixels and 32K bytes."
14086 */
14087 return min(8192 * cpp, 32768);
14088 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14089 return 32*1024;
14090 } else if (gen >= 4) {
14091 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14092 return 16*1024;
14093 else
14094 return 32*1024;
14095 } else if (gen >= 3) {
14096 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14097 return 8*1024;
14098 else
14099 return 16*1024;
14100 } else {
14101 /* XXX DSPC is limited to 4k tiled */
14102 return 8*1024;
14103 }
14104 }
14105
14106 static int intel_framebuffer_init(struct drm_device *dev,
14107 struct intel_framebuffer *intel_fb,
14108 struct drm_mode_fb_cmd2 *mode_cmd,
14109 struct drm_i915_gem_object *obj)
14110 {
14111 struct drm_i915_private *dev_priv = to_i915(dev);
14112 unsigned int aligned_height;
14113 int ret;
14114 u32 pitch_limit, stride_alignment;
14115
14116 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14117
14118 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14119 /* Enforce that fb modifier and tiling mode match, but only for
14120 * X-tiled. This is needed for FBC. */
14121 if (!!(obj->tiling_mode == I915_TILING_X) !=
14122 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14123 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14124 return -EINVAL;
14125 }
14126 } else {
14127 if (obj->tiling_mode == I915_TILING_X)
14128 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14129 else if (obj->tiling_mode == I915_TILING_Y) {
14130 DRM_DEBUG("No Y tiling for legacy addfb\n");
14131 return -EINVAL;
14132 }
14133 }
14134
14135 /* Passed in modifier sanity checking. */
14136 switch (mode_cmd->modifier[0]) {
14137 case I915_FORMAT_MOD_Y_TILED:
14138 case I915_FORMAT_MOD_Yf_TILED:
14139 if (INTEL_INFO(dev)->gen < 9) {
14140 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14141 mode_cmd->modifier[0]);
14142 return -EINVAL;
14143 }
14144 case DRM_FORMAT_MOD_NONE:
14145 case I915_FORMAT_MOD_X_TILED:
14146 break;
14147 default:
14148 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14149 mode_cmd->modifier[0]);
14150 return -EINVAL;
14151 }
14152
14153 stride_alignment = intel_fb_stride_alignment(dev_priv,
14154 mode_cmd->modifier[0],
14155 mode_cmd->pixel_format);
14156 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14157 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14158 mode_cmd->pitches[0], stride_alignment);
14159 return -EINVAL;
14160 }
14161
14162 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14163 mode_cmd->pixel_format);
14164 if (mode_cmd->pitches[0] > pitch_limit) {
14165 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14166 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14167 "tiled" : "linear",
14168 mode_cmd->pitches[0], pitch_limit);
14169 return -EINVAL;
14170 }
14171
14172 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14173 mode_cmd->pitches[0] != obj->stride) {
14174 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14175 mode_cmd->pitches[0], obj->stride);
14176 return -EINVAL;
14177 }
14178
14179 /* Reject formats not supported by any plane early. */
14180 switch (mode_cmd->pixel_format) {
14181 case DRM_FORMAT_C8:
14182 case DRM_FORMAT_RGB565:
14183 case DRM_FORMAT_XRGB8888:
14184 case DRM_FORMAT_ARGB8888:
14185 break;
14186 case DRM_FORMAT_XRGB1555:
14187 if (INTEL_INFO(dev)->gen > 3) {
14188 DRM_DEBUG("unsupported pixel format: %s\n",
14189 drm_get_format_name(mode_cmd->pixel_format));
14190 return -EINVAL;
14191 }
14192 break;
14193 case DRM_FORMAT_ABGR8888:
14194 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14195 INTEL_INFO(dev)->gen < 9) {
14196 DRM_DEBUG("unsupported pixel format: %s\n",
14197 drm_get_format_name(mode_cmd->pixel_format));
14198 return -EINVAL;
14199 }
14200 break;
14201 case DRM_FORMAT_XBGR8888:
14202 case DRM_FORMAT_XRGB2101010:
14203 case DRM_FORMAT_XBGR2101010:
14204 if (INTEL_INFO(dev)->gen < 4) {
14205 DRM_DEBUG("unsupported pixel format: %s\n",
14206 drm_get_format_name(mode_cmd->pixel_format));
14207 return -EINVAL;
14208 }
14209 break;
14210 case DRM_FORMAT_ABGR2101010:
14211 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14212 DRM_DEBUG("unsupported pixel format: %s\n",
14213 drm_get_format_name(mode_cmd->pixel_format));
14214 return -EINVAL;
14215 }
14216 break;
14217 case DRM_FORMAT_YUYV:
14218 case DRM_FORMAT_UYVY:
14219 case DRM_FORMAT_YVYU:
14220 case DRM_FORMAT_VYUY:
14221 if (INTEL_INFO(dev)->gen < 5) {
14222 DRM_DEBUG("unsupported pixel format: %s\n",
14223 drm_get_format_name(mode_cmd->pixel_format));
14224 return -EINVAL;
14225 }
14226 break;
14227 default:
14228 DRM_DEBUG("unsupported pixel format: %s\n",
14229 drm_get_format_name(mode_cmd->pixel_format));
14230 return -EINVAL;
14231 }
14232
14233 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14234 if (mode_cmd->offsets[0] != 0)
14235 return -EINVAL;
14236
14237 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14238 mode_cmd->pixel_format,
14239 mode_cmd->modifier[0]);
14240 /* FIXME drm helper for size checks (especially planar formats)? */
14241 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14242 return -EINVAL;
14243
14244 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14245 intel_fb->obj = obj;
14246
14247 intel_fill_fb_info(dev_priv, &intel_fb->base);
14248
14249 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14250 if (ret) {
14251 DRM_ERROR("framebuffer init failed %d\n", ret);
14252 return ret;
14253 }
14254
14255 intel_fb->obj->framebuffer_references++;
14256
14257 return 0;
14258 }
14259
14260 static struct drm_framebuffer *
14261 intel_user_framebuffer_create(struct drm_device *dev,
14262 struct drm_file *filp,
14263 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14264 {
14265 struct drm_framebuffer *fb;
14266 struct drm_i915_gem_object *obj;
14267 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14268
14269 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14270 mode_cmd.handles[0]));
14271 if (&obj->base == NULL)
14272 return ERR_PTR(-ENOENT);
14273
14274 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14275 if (IS_ERR(fb))
14276 drm_gem_object_unreference_unlocked(&obj->base);
14277
14278 return fb;
14279 }
14280
14281 #ifndef CONFIG_DRM_FBDEV_EMULATION
14282 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14283 {
14284 }
14285 #endif
14286
14287 static const struct drm_mode_config_funcs intel_mode_funcs = {
14288 .fb_create = intel_user_framebuffer_create,
14289 .output_poll_changed = intel_fbdev_output_poll_changed,
14290 .atomic_check = intel_atomic_check,
14291 .atomic_commit = intel_atomic_commit,
14292 .atomic_state_alloc = intel_atomic_state_alloc,
14293 .atomic_state_clear = intel_atomic_state_clear,
14294 };
14295
14296 /**
14297 * intel_init_display_hooks - initialize the display modesetting hooks
14298 * @dev_priv: device private
14299 */
14300 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14301 {
14302 if (INTEL_INFO(dev_priv)->gen >= 9) {
14303 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14304 dev_priv->display.get_initial_plane_config =
14305 skylake_get_initial_plane_config;
14306 dev_priv->display.crtc_compute_clock =
14307 haswell_crtc_compute_clock;
14308 dev_priv->display.crtc_enable = haswell_crtc_enable;
14309 dev_priv->display.crtc_disable = haswell_crtc_disable;
14310 } else if (HAS_DDI(dev_priv)) {
14311 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14312 dev_priv->display.get_initial_plane_config =
14313 ironlake_get_initial_plane_config;
14314 dev_priv->display.crtc_compute_clock =
14315 haswell_crtc_compute_clock;
14316 dev_priv->display.crtc_enable = haswell_crtc_enable;
14317 dev_priv->display.crtc_disable = haswell_crtc_disable;
14318 } else if (HAS_PCH_SPLIT(dev_priv)) {
14319 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14320 dev_priv->display.get_initial_plane_config =
14321 ironlake_get_initial_plane_config;
14322 dev_priv->display.crtc_compute_clock =
14323 ironlake_crtc_compute_clock;
14324 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14325 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14326 } else if (IS_CHERRYVIEW(dev_priv)) {
14327 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14328 dev_priv->display.get_initial_plane_config =
14329 i9xx_get_initial_plane_config;
14330 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14331 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14332 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14333 } else if (IS_VALLEYVIEW(dev_priv)) {
14334 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14335 dev_priv->display.get_initial_plane_config =
14336 i9xx_get_initial_plane_config;
14337 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14338 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14339 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14340 } else if (IS_G4X(dev_priv)) {
14341 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14342 dev_priv->display.get_initial_plane_config =
14343 i9xx_get_initial_plane_config;
14344 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14345 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14346 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14347 } else if (IS_PINEVIEW(dev_priv)) {
14348 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14349 dev_priv->display.get_initial_plane_config =
14350 i9xx_get_initial_plane_config;
14351 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14352 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14353 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14354 } else if (!IS_GEN2(dev_priv)) {
14355 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14356 dev_priv->display.get_initial_plane_config =
14357 i9xx_get_initial_plane_config;
14358 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14359 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14360 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14361 } else {
14362 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14363 dev_priv->display.get_initial_plane_config =
14364 i9xx_get_initial_plane_config;
14365 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14366 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14367 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14368 }
14369
14370 /* Returns the core display clock speed */
14371 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14372 dev_priv->display.get_display_clock_speed =
14373 skylake_get_display_clock_speed;
14374 else if (IS_BROXTON(dev_priv))
14375 dev_priv->display.get_display_clock_speed =
14376 broxton_get_display_clock_speed;
14377 else if (IS_BROADWELL(dev_priv))
14378 dev_priv->display.get_display_clock_speed =
14379 broadwell_get_display_clock_speed;
14380 else if (IS_HASWELL(dev_priv))
14381 dev_priv->display.get_display_clock_speed =
14382 haswell_get_display_clock_speed;
14383 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14384 dev_priv->display.get_display_clock_speed =
14385 valleyview_get_display_clock_speed;
14386 else if (IS_GEN5(dev_priv))
14387 dev_priv->display.get_display_clock_speed =
14388 ilk_get_display_clock_speed;
14389 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14390 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14391 dev_priv->display.get_display_clock_speed =
14392 i945_get_display_clock_speed;
14393 else if (IS_GM45(dev_priv))
14394 dev_priv->display.get_display_clock_speed =
14395 gm45_get_display_clock_speed;
14396 else if (IS_CRESTLINE(dev_priv))
14397 dev_priv->display.get_display_clock_speed =
14398 i965gm_get_display_clock_speed;
14399 else if (IS_PINEVIEW(dev_priv))
14400 dev_priv->display.get_display_clock_speed =
14401 pnv_get_display_clock_speed;
14402 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14403 dev_priv->display.get_display_clock_speed =
14404 g33_get_display_clock_speed;
14405 else if (IS_I915G(dev_priv))
14406 dev_priv->display.get_display_clock_speed =
14407 i915_get_display_clock_speed;
14408 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14409 dev_priv->display.get_display_clock_speed =
14410 i9xx_misc_get_display_clock_speed;
14411 else if (IS_I915GM(dev_priv))
14412 dev_priv->display.get_display_clock_speed =
14413 i915gm_get_display_clock_speed;
14414 else if (IS_I865G(dev_priv))
14415 dev_priv->display.get_display_clock_speed =
14416 i865_get_display_clock_speed;
14417 else if (IS_I85X(dev_priv))
14418 dev_priv->display.get_display_clock_speed =
14419 i85x_get_display_clock_speed;
14420 else { /* 830 */
14421 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14422 dev_priv->display.get_display_clock_speed =
14423 i830_get_display_clock_speed;
14424 }
14425
14426 if (IS_GEN5(dev_priv)) {
14427 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14428 } else if (IS_GEN6(dev_priv)) {
14429 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14430 } else if (IS_IVYBRIDGE(dev_priv)) {
14431 /* FIXME: detect B0+ stepping and use auto training */
14432 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14433 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14434 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14435 }
14436
14437 if (IS_BROADWELL(dev_priv)) {
14438 dev_priv->display.modeset_commit_cdclk =
14439 broadwell_modeset_commit_cdclk;
14440 dev_priv->display.modeset_calc_cdclk =
14441 broadwell_modeset_calc_cdclk;
14442 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14443 dev_priv->display.modeset_commit_cdclk =
14444 valleyview_modeset_commit_cdclk;
14445 dev_priv->display.modeset_calc_cdclk =
14446 valleyview_modeset_calc_cdclk;
14447 } else if (IS_BROXTON(dev_priv)) {
14448 dev_priv->display.modeset_commit_cdclk =
14449 broxton_modeset_commit_cdclk;
14450 dev_priv->display.modeset_calc_cdclk =
14451 broxton_modeset_calc_cdclk;
14452 }
14453 }
14454
14455 /*
14456 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14457 * resume, or other times. This quirk makes sure that's the case for
14458 * affected systems.
14459 */
14460 static void quirk_pipea_force(struct drm_device *dev)
14461 {
14462 struct drm_i915_private *dev_priv = dev->dev_private;
14463
14464 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14465 DRM_INFO("applying pipe a force quirk\n");
14466 }
14467
14468 static void quirk_pipeb_force(struct drm_device *dev)
14469 {
14470 struct drm_i915_private *dev_priv = dev->dev_private;
14471
14472 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14473 DRM_INFO("applying pipe b force quirk\n");
14474 }
14475
14476 /*
14477 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14478 */
14479 static void quirk_ssc_force_disable(struct drm_device *dev)
14480 {
14481 struct drm_i915_private *dev_priv = dev->dev_private;
14482 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14483 DRM_INFO("applying lvds SSC disable quirk\n");
14484 }
14485
14486 /*
14487 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14488 * brightness value
14489 */
14490 static void quirk_invert_brightness(struct drm_device *dev)
14491 {
14492 struct drm_i915_private *dev_priv = dev->dev_private;
14493 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14494 DRM_INFO("applying inverted panel brightness quirk\n");
14495 }
14496
14497 /* Some VBT's incorrectly indicate no backlight is present */
14498 static void quirk_backlight_present(struct drm_device *dev)
14499 {
14500 struct drm_i915_private *dev_priv = dev->dev_private;
14501 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14502 DRM_INFO("applying backlight present quirk\n");
14503 }
14504
14505 struct intel_quirk {
14506 int device;
14507 int subsystem_vendor;
14508 int subsystem_device;
14509 void (*hook)(struct drm_device *dev);
14510 };
14511
14512 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14513 struct intel_dmi_quirk {
14514 void (*hook)(struct drm_device *dev);
14515 const struct dmi_system_id (*dmi_id_list)[];
14516 };
14517
14518 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14519 {
14520 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14521 return 1;
14522 }
14523
14524 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14525 {
14526 .dmi_id_list = &(const struct dmi_system_id[]) {
14527 {
14528 .callback = intel_dmi_reverse_brightness,
14529 .ident = "NCR Corporation",
14530 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14531 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14532 },
14533 },
14534 { } /* terminating entry */
14535 },
14536 .hook = quirk_invert_brightness,
14537 },
14538 };
14539
14540 static struct intel_quirk intel_quirks[] = {
14541 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14542 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14543
14544 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14545 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14546
14547 /* 830 needs to leave pipe A & dpll A up */
14548 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14549
14550 /* 830 needs to leave pipe B & dpll B up */
14551 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14552
14553 /* Lenovo U160 cannot use SSC on LVDS */
14554 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14555
14556 /* Sony Vaio Y cannot use SSC on LVDS */
14557 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14558
14559 /* Acer Aspire 5734Z must invert backlight brightness */
14560 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14561
14562 /* Acer/eMachines G725 */
14563 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14564
14565 /* Acer/eMachines e725 */
14566 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14567
14568 /* Acer/Packard Bell NCL20 */
14569 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14570
14571 /* Acer Aspire 4736Z */
14572 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14573
14574 /* Acer Aspire 5336 */
14575 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14576
14577 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14578 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14579
14580 /* Acer C720 Chromebook (Core i3 4005U) */
14581 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14582
14583 /* Apple Macbook 2,1 (Core 2 T7400) */
14584 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14585
14586 /* Apple Macbook 4,1 */
14587 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14588
14589 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14590 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14591
14592 /* HP Chromebook 14 (Celeron 2955U) */
14593 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14594
14595 /* Dell Chromebook 11 */
14596 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14597
14598 /* Dell Chromebook 11 (2015 version) */
14599 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14600 };
14601
14602 static void intel_init_quirks(struct drm_device *dev)
14603 {
14604 struct pci_dev *d = dev->pdev;
14605 int i;
14606
14607 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14608 struct intel_quirk *q = &intel_quirks[i];
14609
14610 if (d->device == q->device &&
14611 (d->subsystem_vendor == q->subsystem_vendor ||
14612 q->subsystem_vendor == PCI_ANY_ID) &&
14613 (d->subsystem_device == q->subsystem_device ||
14614 q->subsystem_device == PCI_ANY_ID))
14615 q->hook(dev);
14616 }
14617 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14618 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14619 intel_dmi_quirks[i].hook(dev);
14620 }
14621 }
14622
14623 /* Disable the VGA plane that we never use */
14624 static void i915_disable_vga(struct drm_device *dev)
14625 {
14626 struct drm_i915_private *dev_priv = dev->dev_private;
14627 u8 sr1;
14628 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
14629
14630 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14631 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14632 outb(SR01, VGA_SR_INDEX);
14633 sr1 = inb(VGA_SR_DATA);
14634 outb(sr1 | 1<<5, VGA_SR_DATA);
14635 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14636 udelay(300);
14637
14638 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14639 POSTING_READ(vga_reg);
14640 }
14641
14642 void intel_modeset_init_hw(struct drm_device *dev)
14643 {
14644 struct drm_i915_private *dev_priv = dev->dev_private;
14645
14646 intel_update_cdclk(dev);
14647
14648 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
14649
14650 intel_init_clock_gating(dev);
14651 intel_enable_gt_powersave(dev_priv);
14652 }
14653
14654 /*
14655 * Calculate what we think the watermarks should be for the state we've read
14656 * out of the hardware and then immediately program those watermarks so that
14657 * we ensure the hardware settings match our internal state.
14658 *
14659 * We can calculate what we think WM's should be by creating a duplicate of the
14660 * current state (which was constructed during hardware readout) and running it
14661 * through the atomic check code to calculate new watermark values in the
14662 * state object.
14663 */
14664 static void sanitize_watermarks(struct drm_device *dev)
14665 {
14666 struct drm_i915_private *dev_priv = to_i915(dev);
14667 struct drm_atomic_state *state;
14668 struct drm_crtc *crtc;
14669 struct drm_crtc_state *cstate;
14670 struct drm_modeset_acquire_ctx ctx;
14671 int ret;
14672 int i;
14673
14674 /* Only supported on platforms that use atomic watermark design */
14675 if (!dev_priv->display.optimize_watermarks)
14676 return;
14677
14678 /*
14679 * We need to hold connection_mutex before calling duplicate_state so
14680 * that the connector loop is protected.
14681 */
14682 drm_modeset_acquire_init(&ctx, 0);
14683 retry:
14684 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14685 if (ret == -EDEADLK) {
14686 drm_modeset_backoff(&ctx);
14687 goto retry;
14688 } else if (WARN_ON(ret)) {
14689 goto fail;
14690 }
14691
14692 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14693 if (WARN_ON(IS_ERR(state)))
14694 goto fail;
14695
14696 /*
14697 * Hardware readout is the only time we don't want to calculate
14698 * intermediate watermarks (since we don't trust the current
14699 * watermarks).
14700 */
14701 to_intel_atomic_state(state)->skip_intermediate_wm = true;
14702
14703 ret = intel_atomic_check(dev, state);
14704 if (ret) {
14705 /*
14706 * If we fail here, it means that the hardware appears to be
14707 * programmed in a way that shouldn't be possible, given our
14708 * understanding of watermark requirements. This might mean a
14709 * mistake in the hardware readout code or a mistake in the
14710 * watermark calculations for a given platform. Raise a WARN
14711 * so that this is noticeable.
14712 *
14713 * If this actually happens, we'll have to just leave the
14714 * BIOS-programmed watermarks untouched and hope for the best.
14715 */
14716 WARN(true, "Could not determine valid watermarks for inherited state\n");
14717 goto fail;
14718 }
14719
14720 /* Write calculated watermark values back */
14721 for_each_crtc_in_state(state, crtc, cstate, i) {
14722 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14723
14724 cs->wm.need_postvbl_update = true;
14725 dev_priv->display.optimize_watermarks(cs);
14726 }
14727
14728 drm_atomic_state_free(state);
14729 fail:
14730 drm_modeset_drop_locks(&ctx);
14731 drm_modeset_acquire_fini(&ctx);
14732 }
14733
14734 void intel_modeset_init(struct drm_device *dev)
14735 {
14736 struct drm_i915_private *dev_priv = to_i915(dev);
14737 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14738 int sprite, ret;
14739 enum pipe pipe;
14740 struct intel_crtc *crtc;
14741
14742 drm_mode_config_init(dev);
14743
14744 dev->mode_config.min_width = 0;
14745 dev->mode_config.min_height = 0;
14746
14747 dev->mode_config.preferred_depth = 24;
14748 dev->mode_config.prefer_shadow = 1;
14749
14750 dev->mode_config.allow_fb_modifiers = true;
14751
14752 dev->mode_config.funcs = &intel_mode_funcs;
14753
14754 intel_init_quirks(dev);
14755
14756 intel_init_pm(dev);
14757
14758 if (INTEL_INFO(dev)->num_pipes == 0)
14759 return;
14760
14761 /*
14762 * There may be no VBT; and if the BIOS enabled SSC we can
14763 * just keep using it to avoid unnecessary flicker. Whereas if the
14764 * BIOS isn't using it, don't assume it will work even if the VBT
14765 * indicates as much.
14766 */
14767 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14768 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14769 DREF_SSC1_ENABLE);
14770
14771 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14772 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14773 bios_lvds_use_ssc ? "en" : "dis",
14774 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14775 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14776 }
14777 }
14778
14779 if (IS_GEN2(dev)) {
14780 dev->mode_config.max_width = 2048;
14781 dev->mode_config.max_height = 2048;
14782 } else if (IS_GEN3(dev)) {
14783 dev->mode_config.max_width = 4096;
14784 dev->mode_config.max_height = 4096;
14785 } else {
14786 dev->mode_config.max_width = 8192;
14787 dev->mode_config.max_height = 8192;
14788 }
14789
14790 if (IS_845G(dev) || IS_I865G(dev)) {
14791 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14792 dev->mode_config.cursor_height = 1023;
14793 } else if (IS_GEN2(dev)) {
14794 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14795 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14796 } else {
14797 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14798 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14799 }
14800
14801 dev->mode_config.fb_base = ggtt->mappable_base;
14802
14803 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14804 INTEL_INFO(dev)->num_pipes,
14805 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14806
14807 for_each_pipe(dev_priv, pipe) {
14808 intel_crtc_init(dev, pipe);
14809 for_each_sprite(dev_priv, pipe, sprite) {
14810 ret = intel_plane_init(dev, pipe, sprite);
14811 if (ret)
14812 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14813 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14814 }
14815 }
14816
14817 intel_update_czclk(dev_priv);
14818 intel_update_cdclk(dev);
14819
14820 intel_shared_dpll_init(dev);
14821
14822 /* Just disable it once at startup */
14823 i915_disable_vga(dev);
14824 intel_setup_outputs(dev);
14825
14826 drm_modeset_lock_all(dev);
14827 intel_modeset_setup_hw_state(dev);
14828 drm_modeset_unlock_all(dev);
14829
14830 for_each_intel_crtc(dev, crtc) {
14831 struct intel_initial_plane_config plane_config = {};
14832
14833 if (!crtc->active)
14834 continue;
14835
14836 /*
14837 * Note that reserving the BIOS fb up front prevents us
14838 * from stuffing other stolen allocations like the ring
14839 * on top. This prevents some ugliness at boot time, and
14840 * can even allow for smooth boot transitions if the BIOS
14841 * fb is large enough for the active pipe configuration.
14842 */
14843 dev_priv->display.get_initial_plane_config(crtc,
14844 &plane_config);
14845
14846 /*
14847 * If the fb is shared between multiple heads, we'll
14848 * just get the first one.
14849 */
14850 intel_find_initial_plane_obj(crtc, &plane_config);
14851 }
14852
14853 /*
14854 * Make sure hardware watermarks really match the state we read out.
14855 * Note that we need to do this after reconstructing the BIOS fb's
14856 * since the watermark calculation done here will use pstate->fb.
14857 */
14858 sanitize_watermarks(dev);
14859 }
14860
14861 static void intel_enable_pipe_a(struct drm_device *dev)
14862 {
14863 struct intel_connector *connector;
14864 struct drm_connector *crt = NULL;
14865 struct intel_load_detect_pipe load_detect_temp;
14866 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14867
14868 /* We can't just switch on the pipe A, we need to set things up with a
14869 * proper mode and output configuration. As a gross hack, enable pipe A
14870 * by enabling the load detect pipe once. */
14871 for_each_intel_connector(dev, connector) {
14872 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14873 crt = &connector->base;
14874 break;
14875 }
14876 }
14877
14878 if (!crt)
14879 return;
14880
14881 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14882 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14883 }
14884
14885 static bool
14886 intel_check_plane_mapping(struct intel_crtc *crtc)
14887 {
14888 struct drm_device *dev = crtc->base.dev;
14889 struct drm_i915_private *dev_priv = dev->dev_private;
14890 u32 val;
14891
14892 if (INTEL_INFO(dev)->num_pipes == 1)
14893 return true;
14894
14895 val = I915_READ(DSPCNTR(!crtc->plane));
14896
14897 if ((val & DISPLAY_PLANE_ENABLE) &&
14898 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14899 return false;
14900
14901 return true;
14902 }
14903
14904 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14905 {
14906 struct drm_device *dev = crtc->base.dev;
14907 struct intel_encoder *encoder;
14908
14909 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14910 return true;
14911
14912 return false;
14913 }
14914
14915 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
14916 {
14917 struct drm_device *dev = encoder->base.dev;
14918 struct intel_connector *connector;
14919
14920 for_each_connector_on_encoder(dev, &encoder->base, connector)
14921 return true;
14922
14923 return false;
14924 }
14925
14926 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14927 {
14928 struct drm_device *dev = crtc->base.dev;
14929 struct drm_i915_private *dev_priv = dev->dev_private;
14930 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14931
14932 /* Clear any frame start delays used for debugging left by the BIOS */
14933 if (!transcoder_is_dsi(cpu_transcoder)) {
14934 i915_reg_t reg = PIPECONF(cpu_transcoder);
14935
14936 I915_WRITE(reg,
14937 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14938 }
14939
14940 /* restore vblank interrupts to correct state */
14941 drm_crtc_vblank_reset(&crtc->base);
14942 if (crtc->active) {
14943 struct intel_plane *plane;
14944
14945 drm_crtc_vblank_on(&crtc->base);
14946
14947 /* Disable everything but the primary plane */
14948 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14949 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14950 continue;
14951
14952 plane->disable_plane(&plane->base, &crtc->base);
14953 }
14954 }
14955
14956 /* We need to sanitize the plane -> pipe mapping first because this will
14957 * disable the crtc (and hence change the state) if it is wrong. Note
14958 * that gen4+ has a fixed plane -> pipe mapping. */
14959 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14960 bool plane;
14961
14962 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14963 crtc->base.base.id);
14964
14965 /* Pipe has the wrong plane attached and the plane is active.
14966 * Temporarily change the plane mapping and disable everything
14967 * ... */
14968 plane = crtc->plane;
14969 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14970 crtc->plane = !plane;
14971 intel_crtc_disable_noatomic(&crtc->base);
14972 crtc->plane = plane;
14973 }
14974
14975 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14976 crtc->pipe == PIPE_A && !crtc->active) {
14977 /* BIOS forgot to enable pipe A, this mostly happens after
14978 * resume. Force-enable the pipe to fix this, the update_dpms
14979 * call below we restore the pipe to the right state, but leave
14980 * the required bits on. */
14981 intel_enable_pipe_a(dev);
14982 }
14983
14984 /* Adjust the state of the output pipe according to whether we
14985 * have active connectors/encoders. */
14986 if (crtc->active && !intel_crtc_has_encoders(crtc))
14987 intel_crtc_disable_noatomic(&crtc->base);
14988
14989 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14990 /*
14991 * We start out with underrun reporting disabled to avoid races.
14992 * For correct bookkeeping mark this on active crtcs.
14993 *
14994 * Also on gmch platforms we dont have any hardware bits to
14995 * disable the underrun reporting. Which means we need to start
14996 * out with underrun reporting disabled also on inactive pipes,
14997 * since otherwise we'll complain about the garbage we read when
14998 * e.g. coming up after runtime pm.
14999 *
15000 * No protection against concurrent access is required - at
15001 * worst a fifo underrun happens which also sets this to false.
15002 */
15003 crtc->cpu_fifo_underrun_disabled = true;
15004 crtc->pch_fifo_underrun_disabled = true;
15005 }
15006 }
15007
15008 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15009 {
15010 struct intel_connector *connector;
15011 struct drm_device *dev = encoder->base.dev;
15012
15013 /* We need to check both for a crtc link (meaning that the
15014 * encoder is active and trying to read from a pipe) and the
15015 * pipe itself being active. */
15016 bool has_active_crtc = encoder->base.crtc &&
15017 to_intel_crtc(encoder->base.crtc)->active;
15018
15019 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15020 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15021 encoder->base.base.id,
15022 encoder->base.name);
15023
15024 /* Connector is active, but has no active pipe. This is
15025 * fallout from our resume register restoring. Disable
15026 * the encoder manually again. */
15027 if (encoder->base.crtc) {
15028 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15029 encoder->base.base.id,
15030 encoder->base.name);
15031 encoder->disable(encoder);
15032 if (encoder->post_disable)
15033 encoder->post_disable(encoder);
15034 }
15035 encoder->base.crtc = NULL;
15036
15037 /* Inconsistent output/port/pipe state happens presumably due to
15038 * a bug in one of the get_hw_state functions. Or someplace else
15039 * in our code, like the register restore mess on resume. Clamp
15040 * things to off as a safer default. */
15041 for_each_intel_connector(dev, connector) {
15042 if (connector->encoder != encoder)
15043 continue;
15044 connector->base.dpms = DRM_MODE_DPMS_OFF;
15045 connector->base.encoder = NULL;
15046 }
15047 }
15048 /* Enabled encoders without active connectors will be fixed in
15049 * the crtc fixup. */
15050 }
15051
15052 void i915_redisable_vga_power_on(struct drm_device *dev)
15053 {
15054 struct drm_i915_private *dev_priv = dev->dev_private;
15055 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15056
15057 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15058 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15059 i915_disable_vga(dev);
15060 }
15061 }
15062
15063 void i915_redisable_vga(struct drm_device *dev)
15064 {
15065 struct drm_i915_private *dev_priv = dev->dev_private;
15066
15067 /* This function can be called both from intel_modeset_setup_hw_state or
15068 * at a very early point in our resume sequence, where the power well
15069 * structures are not yet restored. Since this function is at a very
15070 * paranoid "someone might have enabled VGA while we were not looking"
15071 * level, just check if the power well is enabled instead of trying to
15072 * follow the "don't touch the power well if we don't need it" policy
15073 * the rest of the driver uses. */
15074 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15075 return;
15076
15077 i915_redisable_vga_power_on(dev);
15078
15079 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15080 }
15081
15082 static bool primary_get_hw_state(struct intel_plane *plane)
15083 {
15084 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15085
15086 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15087 }
15088
15089 /* FIXME read out full plane state for all planes */
15090 static void readout_plane_state(struct intel_crtc *crtc)
15091 {
15092 struct drm_plane *primary = crtc->base.primary;
15093 struct intel_plane_state *plane_state =
15094 to_intel_plane_state(primary->state);
15095
15096 plane_state->visible = crtc->active &&
15097 primary_get_hw_state(to_intel_plane(primary));
15098
15099 if (plane_state->visible)
15100 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15101 }
15102
15103 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15104 {
15105 struct drm_i915_private *dev_priv = dev->dev_private;
15106 enum pipe pipe;
15107 struct intel_crtc *crtc;
15108 struct intel_encoder *encoder;
15109 struct intel_connector *connector;
15110 int i;
15111
15112 dev_priv->active_crtcs = 0;
15113
15114 for_each_intel_crtc(dev, crtc) {
15115 struct intel_crtc_state *crtc_state = crtc->config;
15116 int pixclk = 0;
15117
15118 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15119 memset(crtc_state, 0, sizeof(*crtc_state));
15120 crtc_state->base.crtc = &crtc->base;
15121
15122 crtc_state->base.active = crtc_state->base.enable =
15123 dev_priv->display.get_pipe_config(crtc, crtc_state);
15124
15125 crtc->base.enabled = crtc_state->base.enable;
15126 crtc->active = crtc_state->base.active;
15127
15128 if (crtc_state->base.active) {
15129 dev_priv->active_crtcs |= 1 << crtc->pipe;
15130
15131 if (IS_BROADWELL(dev_priv)) {
15132 pixclk = ilk_pipe_pixel_rate(crtc_state);
15133
15134 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15135 if (crtc_state->ips_enabled)
15136 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15137 } else if (IS_VALLEYVIEW(dev_priv) ||
15138 IS_CHERRYVIEW(dev_priv) ||
15139 IS_BROXTON(dev_priv))
15140 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15141 else
15142 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15143 }
15144
15145 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15146
15147 readout_plane_state(crtc);
15148
15149 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15150 crtc->base.base.id,
15151 crtc->active ? "enabled" : "disabled");
15152 }
15153
15154 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15155 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15156
15157 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15158 &pll->config.hw_state);
15159 pll->config.crtc_mask = 0;
15160 for_each_intel_crtc(dev, crtc) {
15161 if (crtc->active && crtc->config->shared_dpll == pll)
15162 pll->config.crtc_mask |= 1 << crtc->pipe;
15163 }
15164 pll->active_mask = pll->config.crtc_mask;
15165
15166 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15167 pll->name, pll->config.crtc_mask, pll->on);
15168 }
15169
15170 for_each_intel_encoder(dev, encoder) {
15171 pipe = 0;
15172
15173 if (encoder->get_hw_state(encoder, &pipe)) {
15174 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15175 encoder->base.crtc = &crtc->base;
15176 encoder->get_config(encoder, crtc->config);
15177 } else {
15178 encoder->base.crtc = NULL;
15179 }
15180
15181 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15182 encoder->base.base.id,
15183 encoder->base.name,
15184 encoder->base.crtc ? "enabled" : "disabled",
15185 pipe_name(pipe));
15186 }
15187
15188 for_each_intel_connector(dev, connector) {
15189 if (connector->get_hw_state(connector)) {
15190 connector->base.dpms = DRM_MODE_DPMS_ON;
15191
15192 encoder = connector->encoder;
15193 connector->base.encoder = &encoder->base;
15194
15195 if (encoder->base.crtc &&
15196 encoder->base.crtc->state->active) {
15197 /*
15198 * This has to be done during hardware readout
15199 * because anything calling .crtc_disable may
15200 * rely on the connector_mask being accurate.
15201 */
15202 encoder->base.crtc->state->connector_mask |=
15203 1 << drm_connector_index(&connector->base);
15204 encoder->base.crtc->state->encoder_mask |=
15205 1 << drm_encoder_index(&encoder->base);
15206 }
15207
15208 } else {
15209 connector->base.dpms = DRM_MODE_DPMS_OFF;
15210 connector->base.encoder = NULL;
15211 }
15212 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15213 connector->base.base.id,
15214 connector->base.name,
15215 connector->base.encoder ? "enabled" : "disabled");
15216 }
15217
15218 for_each_intel_crtc(dev, crtc) {
15219 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15220
15221 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15222 if (crtc->base.state->active) {
15223 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15224 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15225 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15226
15227 /*
15228 * The initial mode needs to be set in order to keep
15229 * the atomic core happy. It wants a valid mode if the
15230 * crtc's enabled, so we do the above call.
15231 *
15232 * At this point some state updated by the connectors
15233 * in their ->detect() callback has not run yet, so
15234 * no recalculation can be done yet.
15235 *
15236 * Even if we could do a recalculation and modeset
15237 * right now it would cause a double modeset if
15238 * fbdev or userspace chooses a different initial mode.
15239 *
15240 * If that happens, someone indicated they wanted a
15241 * mode change, which means it's safe to do a full
15242 * recalculation.
15243 */
15244 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15245
15246 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15247 update_scanline_offset(crtc);
15248 }
15249
15250 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15251 }
15252 }
15253
15254 /* Scan out the current hw modeset state,
15255 * and sanitizes it to the current state
15256 */
15257 static void
15258 intel_modeset_setup_hw_state(struct drm_device *dev)
15259 {
15260 struct drm_i915_private *dev_priv = dev->dev_private;
15261 enum pipe pipe;
15262 struct intel_crtc *crtc;
15263 struct intel_encoder *encoder;
15264 int i;
15265
15266 intel_modeset_readout_hw_state(dev);
15267
15268 /* HW state is read out, now we need to sanitize this mess. */
15269 for_each_intel_encoder(dev, encoder) {
15270 intel_sanitize_encoder(encoder);
15271 }
15272
15273 for_each_pipe(dev_priv, pipe) {
15274 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15275 intel_sanitize_crtc(crtc);
15276 intel_dump_pipe_config(crtc, crtc->config,
15277 "[setup_hw_state]");
15278 }
15279
15280 intel_modeset_update_connector_atomic_state(dev);
15281
15282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15283 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15284
15285 if (!pll->on || pll->active_mask)
15286 continue;
15287
15288 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15289
15290 pll->funcs.disable(dev_priv, pll);
15291 pll->on = false;
15292 }
15293
15294 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15295 vlv_wm_get_hw_state(dev);
15296 else if (IS_GEN9(dev))
15297 skl_wm_get_hw_state(dev);
15298 else if (HAS_PCH_SPLIT(dev))
15299 ilk_wm_get_hw_state(dev);
15300
15301 for_each_intel_crtc(dev, crtc) {
15302 unsigned long put_domains;
15303
15304 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15305 if (WARN_ON(put_domains))
15306 modeset_put_power_domains(dev_priv, put_domains);
15307 }
15308 intel_display_set_init_power(dev_priv, false);
15309
15310 intel_fbc_init_pipe_state(dev_priv);
15311 }
15312
15313 void intel_display_resume(struct drm_device *dev)
15314 {
15315 struct drm_i915_private *dev_priv = to_i915(dev);
15316 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15317 struct drm_modeset_acquire_ctx ctx;
15318 int ret;
15319 bool setup = false;
15320
15321 dev_priv->modeset_restore_state = NULL;
15322
15323 /*
15324 * This is a cludge because with real atomic modeset mode_config.mutex
15325 * won't be taken. Unfortunately some probed state like
15326 * audio_codec_enable is still protected by mode_config.mutex, so lock
15327 * it here for now.
15328 */
15329 mutex_lock(&dev->mode_config.mutex);
15330 drm_modeset_acquire_init(&ctx, 0);
15331
15332 retry:
15333 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15334
15335 if (ret == 0 && !setup) {
15336 setup = true;
15337
15338 intel_modeset_setup_hw_state(dev);
15339 i915_redisable_vga(dev);
15340 }
15341
15342 if (ret == 0 && state) {
15343 struct drm_crtc_state *crtc_state;
15344 struct drm_crtc *crtc;
15345 int i;
15346
15347 state->acquire_ctx = &ctx;
15348
15349 /* ignore any reset values/BIOS leftovers in the WM registers */
15350 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15351
15352 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15353 /*
15354 * Force recalculation even if we restore
15355 * current state. With fast modeset this may not result
15356 * in a modeset when the state is compatible.
15357 */
15358 crtc_state->mode_changed = true;
15359 }
15360
15361 ret = drm_atomic_commit(state);
15362 }
15363
15364 if (ret == -EDEADLK) {
15365 drm_modeset_backoff(&ctx);
15366 goto retry;
15367 }
15368
15369 drm_modeset_drop_locks(&ctx);
15370 drm_modeset_acquire_fini(&ctx);
15371 mutex_unlock(&dev->mode_config.mutex);
15372
15373 if (ret) {
15374 DRM_ERROR("Restoring old state failed with %i\n", ret);
15375 drm_atomic_state_free(state);
15376 }
15377 }
15378
15379 void intel_modeset_gem_init(struct drm_device *dev)
15380 {
15381 struct drm_i915_private *dev_priv = to_i915(dev);
15382 struct drm_crtc *c;
15383 struct drm_i915_gem_object *obj;
15384 int ret;
15385
15386 intel_init_gt_powersave(dev_priv);
15387
15388 intel_modeset_init_hw(dev);
15389
15390 intel_setup_overlay(dev_priv);
15391
15392 /*
15393 * Make sure any fbs we allocated at startup are properly
15394 * pinned & fenced. When we do the allocation it's too early
15395 * for this.
15396 */
15397 for_each_crtc(dev, c) {
15398 obj = intel_fb_obj(c->primary->fb);
15399 if (obj == NULL)
15400 continue;
15401
15402 mutex_lock(&dev->struct_mutex);
15403 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15404 c->primary->state->rotation);
15405 mutex_unlock(&dev->struct_mutex);
15406 if (ret) {
15407 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15408 to_intel_crtc(c)->pipe);
15409 drm_framebuffer_unreference(c->primary->fb);
15410 drm_framebuffer_unreference(c->primary->state->fb);
15411 c->primary->fb = c->primary->state->fb = NULL;
15412 c->primary->crtc = c->primary->state->crtc = NULL;
15413 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15414 }
15415 }
15416
15417 intel_backlight_register(dev);
15418 }
15419
15420 void intel_connector_unregister(struct intel_connector *intel_connector)
15421 {
15422 struct drm_connector *connector = &intel_connector->base;
15423
15424 intel_panel_destroy_backlight(connector);
15425 drm_connector_unregister(connector);
15426 }
15427
15428 void intel_modeset_cleanup(struct drm_device *dev)
15429 {
15430 struct drm_i915_private *dev_priv = dev->dev_private;
15431 struct intel_connector *connector;
15432
15433 intel_disable_gt_powersave(dev_priv);
15434
15435 intel_backlight_unregister(dev);
15436
15437 /*
15438 * Interrupts and polling as the first thing to avoid creating havoc.
15439 * Too much stuff here (turning of connectors, ...) would
15440 * experience fancy races otherwise.
15441 */
15442 intel_irq_uninstall(dev_priv);
15443
15444 /*
15445 * Due to the hpd irq storm handling the hotplug work can re-arm the
15446 * poll handlers. Hence disable polling after hpd handling is shut down.
15447 */
15448 drm_kms_helper_poll_fini(dev);
15449
15450 intel_unregister_dsm_handler();
15451
15452 intel_fbc_global_disable(dev_priv);
15453
15454 /* flush any delayed tasks or pending work */
15455 flush_scheduled_work();
15456
15457 /* destroy the backlight and sysfs files before encoders/connectors */
15458 for_each_intel_connector(dev, connector)
15459 connector->unregister(connector);
15460
15461 drm_mode_config_cleanup(dev);
15462
15463 intel_cleanup_overlay(dev_priv);
15464
15465 intel_cleanup_gt_powersave(dev_priv);
15466
15467 intel_teardown_gmbus(dev);
15468 }
15469
15470 /*
15471 * Return which encoder is currently attached for connector.
15472 */
15473 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15474 {
15475 return &intel_attached_encoder(connector)->base;
15476 }
15477
15478 void intel_connector_attach_encoder(struct intel_connector *connector,
15479 struct intel_encoder *encoder)
15480 {
15481 connector->encoder = encoder;
15482 drm_mode_connector_attach_encoder(&connector->base,
15483 &encoder->base);
15484 }
15485
15486 /*
15487 * set vga decode state - true == enable VGA decode
15488 */
15489 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15490 {
15491 struct drm_i915_private *dev_priv = dev->dev_private;
15492 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15493 u16 gmch_ctrl;
15494
15495 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15496 DRM_ERROR("failed to read control word\n");
15497 return -EIO;
15498 }
15499
15500 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15501 return 0;
15502
15503 if (state)
15504 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15505 else
15506 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15507
15508 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15509 DRM_ERROR("failed to write control word\n");
15510 return -EIO;
15511 }
15512
15513 return 0;
15514 }
15515
15516 struct intel_display_error_state {
15517
15518 u32 power_well_driver;
15519
15520 int num_transcoders;
15521
15522 struct intel_cursor_error_state {
15523 u32 control;
15524 u32 position;
15525 u32 base;
15526 u32 size;
15527 } cursor[I915_MAX_PIPES];
15528
15529 struct intel_pipe_error_state {
15530 bool power_domain_on;
15531 u32 source;
15532 u32 stat;
15533 } pipe[I915_MAX_PIPES];
15534
15535 struct intel_plane_error_state {
15536 u32 control;
15537 u32 stride;
15538 u32 size;
15539 u32 pos;
15540 u32 addr;
15541 u32 surface;
15542 u32 tile_offset;
15543 } plane[I915_MAX_PIPES];
15544
15545 struct intel_transcoder_error_state {
15546 bool power_domain_on;
15547 enum transcoder cpu_transcoder;
15548
15549 u32 conf;
15550
15551 u32 htotal;
15552 u32 hblank;
15553 u32 hsync;
15554 u32 vtotal;
15555 u32 vblank;
15556 u32 vsync;
15557 } transcoder[4];
15558 };
15559
15560 struct intel_display_error_state *
15561 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15562 {
15563 struct intel_display_error_state *error;
15564 int transcoders[] = {
15565 TRANSCODER_A,
15566 TRANSCODER_B,
15567 TRANSCODER_C,
15568 TRANSCODER_EDP,
15569 };
15570 int i;
15571
15572 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15573 return NULL;
15574
15575 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15576 if (error == NULL)
15577 return NULL;
15578
15579 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15580 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15581
15582 for_each_pipe(dev_priv, i) {
15583 error->pipe[i].power_domain_on =
15584 __intel_display_power_is_enabled(dev_priv,
15585 POWER_DOMAIN_PIPE(i));
15586 if (!error->pipe[i].power_domain_on)
15587 continue;
15588
15589 error->cursor[i].control = I915_READ(CURCNTR(i));
15590 error->cursor[i].position = I915_READ(CURPOS(i));
15591 error->cursor[i].base = I915_READ(CURBASE(i));
15592
15593 error->plane[i].control = I915_READ(DSPCNTR(i));
15594 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15595 if (INTEL_GEN(dev_priv) <= 3) {
15596 error->plane[i].size = I915_READ(DSPSIZE(i));
15597 error->plane[i].pos = I915_READ(DSPPOS(i));
15598 }
15599 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15600 error->plane[i].addr = I915_READ(DSPADDR(i));
15601 if (INTEL_GEN(dev_priv) >= 4) {
15602 error->plane[i].surface = I915_READ(DSPSURF(i));
15603 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15604 }
15605
15606 error->pipe[i].source = I915_READ(PIPESRC(i));
15607
15608 if (HAS_GMCH_DISPLAY(dev_priv))
15609 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15610 }
15611
15612 /* Note: this does not include DSI transcoders. */
15613 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15614 if (HAS_DDI(dev_priv))
15615 error->num_transcoders++; /* Account for eDP. */
15616
15617 for (i = 0; i < error->num_transcoders; i++) {
15618 enum transcoder cpu_transcoder = transcoders[i];
15619
15620 error->transcoder[i].power_domain_on =
15621 __intel_display_power_is_enabled(dev_priv,
15622 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15623 if (!error->transcoder[i].power_domain_on)
15624 continue;
15625
15626 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15627
15628 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15629 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15630 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15631 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15632 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15633 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15634 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15635 }
15636
15637 return error;
15638 }
15639
15640 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15641
15642 void
15643 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15644 struct drm_device *dev,
15645 struct intel_display_error_state *error)
15646 {
15647 struct drm_i915_private *dev_priv = dev->dev_private;
15648 int i;
15649
15650 if (!error)
15651 return;
15652
15653 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15654 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15655 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15656 error->power_well_driver);
15657 for_each_pipe(dev_priv, i) {
15658 err_printf(m, "Pipe [%d]:\n", i);
15659 err_printf(m, " Power: %s\n",
15660 onoff(error->pipe[i].power_domain_on));
15661 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15662 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15663
15664 err_printf(m, "Plane [%d]:\n", i);
15665 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15666 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15667 if (INTEL_INFO(dev)->gen <= 3) {
15668 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15669 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15670 }
15671 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15672 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15673 if (INTEL_INFO(dev)->gen >= 4) {
15674 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15675 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15676 }
15677
15678 err_printf(m, "Cursor [%d]:\n", i);
15679 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15680 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15681 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15682 }
15683
15684 for (i = 0; i < error->num_transcoders; i++) {
15685 err_printf(m, "CPU transcoder: %s\n",
15686 transcoder_name(error->transcoder[i].cpu_transcoder));
15687 err_printf(m, " Power: %s\n",
15688 onoff(error->transcoder[i].power_domain_on));
15689 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15690 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15691 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15692 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15693 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15694 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15695 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15696 }
15697 }
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