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drm/i915: Ensure cache flushes prior to doing CS flips
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc,
86 struct drm_atomic_state *state);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
107 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
109 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
111
112 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113 {
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118 }
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 int
136 intel_pch_rawclk(struct drm_device *dev)
137 {
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143 }
144
145 static inline u32 /* units of 100MHz */
146 intel_fdi_link_freq(struct drm_device *dev)
147 {
148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
153 }
154
155 static const intel_limit_t intel_limits_i8xx_dac = {
156 .dot = { .min = 25000, .max = 350000 },
157 .vco = { .min = 908000, .max = 1512000 },
158 .n = { .min = 2, .max = 16 },
159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
166 };
167
168 static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
170 .vco = { .min = 908000, .max = 1512000 },
171 .n = { .min = 2, .max = 16 },
172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179 };
180
181 static const intel_limit_t intel_limits_i8xx_lvds = {
182 .dot = { .min = 25000, .max = 350000 },
183 .vco = { .min = 908000, .max = 1512000 },
184 .n = { .min = 2, .max = 16 },
185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
192 };
193
194 static const intel_limit_t intel_limits_i9xx_sdvo = {
195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
205 };
206
207 static const intel_limit_t intel_limits_i9xx_lvds = {
208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
218 };
219
220
221 static const intel_limit_t intel_limits_g4x_sdvo = {
222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
233 },
234 };
235
236 static const intel_limit_t intel_limits_g4x_hdmi = {
237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
247 };
248
249 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
260 },
261 };
262
263 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
274 },
275 };
276
277 static const intel_limit_t intel_limits_pineview_sdvo = {
278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
280 /* Pineview's Ncounter is a ring counter */
281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
283 /* Pineview only has one combined m divider, which we treat as m2. */
284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
290 };
291
292 static const intel_limit_t intel_limits_pineview_lvds = {
293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
303 };
304
305 /* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
310 static const intel_limit_t intel_limits_ironlake_dac = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
321 };
322
323 static const intel_limit_t intel_limits_ironlake_single_lvds = {
324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
334 };
335
336 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
347 };
348
349 /* LVDS 100mhz refclk limits. */
350 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
358 .p1 = { .min = 2, .max = 8 },
359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 };
375
376 static const intel_limit_t intel_limits_vlv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
384 .vco = { .min = 4000000, .max = 6000000 },
385 .n = { .min = 1, .max = 7 },
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p1 = { .min = 2, .max = 3 },
389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
390 };
391
392 static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
400 .vco = { .min = 4800000, .max = 6480000 },
401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406 };
407
408 static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418 };
419
420 static void vlv_clock(int refclk, intel_clock_t *clock)
421 {
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
428 }
429
430 /**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
433 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
439 if (encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 /**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
451 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
453 {
454 struct drm_atomic_state *state = crtc_state->base.state;
455 struct drm_connector *connector;
456 struct drm_connector_state *connector_state;
457 struct intel_encoder *encoder;
458 int i, num_connectors = 0;
459
460 for_each_connector_in_state(state, connector, connector_state, i) {
461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
465
466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
468 return true;
469 }
470
471 WARN_ON(num_connectors == 0);
472
473 return false;
474 }
475
476 static const intel_limit_t *
477 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
478 {
479 struct drm_device *dev = crtc_state->base.crtc->dev;
480 const intel_limit_t *limit;
481
482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
483 if (intel_is_dual_link_lvds(dev)) {
484 if (refclk == 100000)
485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
489 if (refclk == 100000)
490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
494 } else
495 limit = &intel_limits_ironlake_dac;
496
497 return limit;
498 }
499
500 static const intel_limit_t *
501 intel_g4x_limit(struct intel_crtc_state *crtc_state)
502 {
503 struct drm_device *dev = crtc_state->base.crtc->dev;
504 const intel_limit_t *limit;
505
506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
507 if (intel_is_dual_link_lvds(dev))
508 limit = &intel_limits_g4x_dual_channel_lvds;
509 else
510 limit = &intel_limits_g4x_single_channel_lvds;
511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
513 limit = &intel_limits_g4x_hdmi;
514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
515 limit = &intel_limits_g4x_sdvo;
516 } else /* The option is for other outputs */
517 limit = &intel_limits_i9xx_sdvo;
518
519 return limit;
520 }
521
522 static const intel_limit_t *
523 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
524 {
525 struct drm_device *dev = crtc_state->base.crtc->dev;
526 const intel_limit_t *limit;
527
528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
531 limit = intel_ironlake_limit(crtc_state, refclk);
532 else if (IS_G4X(dev)) {
533 limit = intel_g4x_limit(crtc_state);
534 } else if (IS_PINEVIEW(dev)) {
535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
536 limit = &intel_limits_pineview_lvds;
537 else
538 limit = &intel_limits_pineview_sdvo;
539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
541 } else if (IS_VALLEYVIEW(dev)) {
542 limit = &intel_limits_vlv;
543 } else if (!IS_GEN2(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
548 } else {
549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
550 limit = &intel_limits_i8xx_lvds;
551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
552 limit = &intel_limits_i8xx_dvo;
553 else
554 limit = &intel_limits_i8xx_dac;
555 }
556 return limit;
557 }
558
559 /* m1 is reserved as 0 in Pineview, n is a ring counter */
560 static void pineview_clock(int refclk, intel_clock_t *clock)
561 {
562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568 }
569
570 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 {
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573 }
574
575 static void i9xx_clock(int refclk, intel_clock_t *clock)
576 {
577 clock->m = i9xx_dpll_compute_m(clock);
578 clock->p = clock->p1 * clock->p2;
579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
583 }
584
585 static void chv_clock(int refclk, intel_clock_t *clock)
586 {
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 }
595
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
597 /**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
602 static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
605 {
606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
613 INTELPllInvalid("m1 out of range\n");
614
615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid("dot out of range\n");
633
634 return true;
635 }
636
637 static bool
638 i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642 {
643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
644 struct drm_device *dev = crtc->base.dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 if (clock.m2 >= clock.m1)
672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
677 int this_err;
678
679 i9xx_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698 }
699
700 static bool
701 pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
707 struct drm_device *dev = crtc->base.dev;
708 intel_clock_t clock;
709 int err = target;
710
711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
712 /*
713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
716 */
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 static bool
762 g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
766 {
767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
768 struct drm_device *dev = crtc->base.dev;
769 intel_clock_t clock;
770 int max_n;
771 bool found;
772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
774 found = false;
775
776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
777 if (intel_is_dual_link_lvds(dev))
778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
790 /* based on hardware requirement, prefer smaller n to precision */
791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
792 /* based on hardware requirement, prefere larger m1,m2 */
793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
801 i9xx_clock(refclk, &clock);
802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
804 continue;
805
806 this_err = abs(clock.dot - target);
807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
817 return found;
818 }
819
820 /*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829 {
830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858 }
859
860 static bool
861 vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
867 struct drm_device *dev = crtc->base.dev;
868 intel_clock_t clock;
869 unsigned int bestppm = 1000000;
870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
872 bool found = false;
873
874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
877
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
883 clock.p = clock.p1 * clock.p2;
884 /* based on hardware requirement, prefer bigger m1,m2 values */
885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
886 unsigned int ppm;
887
888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
890
891 vlv_clock(refclk, &clock);
892
893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
895 continue;
896
897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
902
903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
906 }
907 }
908 }
909 }
910
911 return found;
912 }
913
914 static bool
915 chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919 {
920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
921 struct drm_device *dev = crtc->base.dev;
922 unsigned int best_error_ppm;
923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
928 best_error_ppm = 1000000;
929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
942 unsigned int error_ppm;
943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
966 }
967 }
968
969 return found;
970 }
971
972 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974 {
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979 }
980
981 bool intel_crtc_active(struct drm_crtc *crtc)
982 {
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
988 * We can ditch the adjusted_mode.crtc_clock check as soon
989 * as Haswell has gained clock readout/fastboot support.
990 *
991 * We can ditch the crtc->primary->fb check as soon as we can
992 * properly reconstruct framebuffers.
993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
997 */
998 return intel_crtc->active && crtc->primary->state->fb &&
999 intel_crtc->config->base.adjusted_mode.crtc_clock;
1000 }
1001
1002 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004 {
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
1008 return intel_crtc->config->cpu_transcoder;
1009 }
1010
1011 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012 {
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028 }
1029
1030 /*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
1032 * @crtc: crtc whose pipe to wait for
1033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
1044 *
1045 */
1046 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1047 {
1048 struct drm_device *dev = crtc->base.dev;
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1051 enum pipe pipe = crtc->pipe;
1052
1053 if (INTEL_INFO(dev)->gen >= 4) {
1054 int reg = PIPECONF(cpu_transcoder);
1055
1056 /* Wait for the Pipe State to go off */
1057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
1059 WARN(1, "pipe_off wait timed out\n");
1060 } else {
1061 /* Wait for the display line to settle */
1062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 }
1065 }
1066
1067 /*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076 {
1077 u32 bit;
1078
1079 if (HAS_PCH_IBX(dev_priv->dev)) {
1080 switch (port->port) {
1081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
1094 switch (port->port) {
1095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114 return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
1128 I915_STATE_WARN(cur_state != state,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
1144 I915_STATE_WARN(cur_state != state,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156 if (crtc->config->shared_dpll < 0)
1157 return NULL;
1158
1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
1166 {
1167 bool cur_state;
1168 struct intel_dpll_hw_state hw_state;
1169
1170 if (WARN (!pll,
1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
1172 return;
1173
1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175 I915_STATE_WARN(cur_state != state,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
1188
1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208 {
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
1216 I915_STATE_WARN(cur_state != state,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225 {
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231 return;
1232
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv->dev))
1235 return;
1236
1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252 I915_STATE_WARN(cur_state != state,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259 {
1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
1264 bool locked = true;
1265
1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
1272 pp_reg = PCH_PP_CONTROL;
1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
1283 } else {
1284 pp_reg = PP_CONTROL;
1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292 locked = false;
1293
1294 I915_STATE_WARN(panel_pipe == pipe && locked,
1295 "panel assertion failure, pipe %c regs locked\n",
1296 pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
1305 if (IS_845G(dev) || IS_I865G(dev))
1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307 else
1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310 I915_STATE_WARN(cur_state != state,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
1319 {
1320 int reg;
1321 u32 val;
1322 bool cur_state;
1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
1325
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329 state = true;
1330
1331 if (!intel_display_power_is_enabled(dev_priv,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
1340 I915_STATE_WARN(cur_state != state,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
1347 {
1348 int reg;
1349 u32 val;
1350 bool cur_state;
1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355 I915_STATE_WARN(cur_state != state,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365 {
1366 struct drm_device *dev = dev_priv->dev;
1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
1378 return;
1379 }
1380
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv, i) {
1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395 {
1396 struct drm_device *dev = dev_priv->dev;
1397 int reg, sprite;
1398 u32 val;
1399
1400 if (INTEL_INFO(dev)->gen >= 9) {
1401 for_each_sprite(dev_priv, pipe, sprite) {
1402 val = I915_READ(PLANE_CTL(pipe, sprite));
1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 reg = SPCNTR(pipe, sprite);
1410 val = I915_READ(reg);
1411 I915_STATE_WARN(val & SP_ENABLE,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe, sprite), pipe_name(pipe));
1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
1424 I915_STATE_WARN(val & DVS_ENABLE,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
1427 }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438 u32 val;
1439 bool enabled;
1440
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
1451 {
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
1456 reg = PCH_TRANSCONF(pipe);
1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
1459 I915_STATE_WARN(enabled,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487 {
1488 if ((val & SDVO_ENABLE) == 0)
1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493 return false;
1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1497 } else {
1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499 return false;
1500 }
1501 return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506 {
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522 {
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, int reg, u32 port_sel)
1537 {
1538 u32 val = I915_READ(reg);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg, pipe_name(pipe));
1542
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544 && (val & DP_PIPEB_SELECT),
1545 "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550 {
1551 u32 val = I915_READ(reg);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg, pipe_name(pipe));
1555
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557 && (val & SDVO_PIPE_B_SELECT),
1558 "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563 {
1564 int reg;
1565 u32 val;
1566
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 pipe_name(pipe));
1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609 const struct intel_crtc_state *pipe_config)
1610 {
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv->dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635 /* We do this three times for luck */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648 const struct intel_crtc_state *pipe_config)
1649 {
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
1673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674
1675 /* Check PLL is locked */
1676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
1679 /* not sure when this should be written */
1680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1681 POSTING_READ(DPLL_MD(pipe));
1682
1683 mutex_unlock(&dev_priv->dpio_lock);
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695 return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705 assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
1733 crtc->config->dpll_hw_state.dpll_md);
1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
1742
1743 /* We do this three times for luck */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 I915_WRITE(reg, dpll);
1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756 * i9xx_disable_pll - disable a PLL
1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
1803 if (pipe == PIPE_B)
1804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
1807
1808 }
1809
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811 {
1812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 u32 val;
1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
1818 /* Set PLL en = 0 */
1819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
1843 mutex_unlock(&dev_priv->dpio_lock);
1844 }
1845
1846 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1847 struct intel_digital_port *dport,
1848 unsigned int expected_mask)
1849 {
1850 u32 port_mask;
1851 int dpll_reg;
1852
1853 switch (dport->port) {
1854 case PORT_B:
1855 port_mask = DPLL_PORTB_READY_MASK;
1856 dpll_reg = DPLL(0);
1857 break;
1858 case PORT_C:
1859 port_mask = DPLL_PORTC_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 expected_mask <<= 4;
1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
1866 break;
1867 default:
1868 BUG();
1869 }
1870
1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1872 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1874 }
1875
1876 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877 {
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
1882 if (WARN_ON(pll == NULL))
1883 return;
1884
1885 WARN_ON(!pll->config.crtc_mask);
1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893 }
1894
1895 /**
1896 * intel_enable_shared_dpll - enable PCH PLL
1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
1903 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1904 {
1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1908
1909 if (WARN_ON(pll == NULL))
1910 return;
1911
1912 if (WARN_ON(pll->config.crtc_mask == 0))
1913 return;
1914
1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1916 pll->name, pll->active, pll->on,
1917 crtc->base.base.id);
1918
1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
1921 assert_shared_dpll_enabled(dev_priv, pll);
1922 return;
1923 }
1924 WARN_ON(pll->on);
1925
1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1929 pll->enable(dev_priv, pll);
1930 pll->on = true;
1931 }
1932
1933 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1934 {
1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1938
1939 /* PCH only available on ILK+ */
1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
1941 if (WARN_ON(pll == NULL))
1942 return;
1943
1944 if (WARN_ON(pll->config.crtc_mask == 0))
1945 return;
1946
1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
1949 crtc->base.base.id);
1950
1951 if (WARN_ON(pll->active == 0)) {
1952 assert_shared_dpll_disabled(dev_priv, pll);
1953 return;
1954 }
1955
1956 assert_shared_dpll_enabled(dev_priv, pll);
1957 WARN_ON(!pll->on);
1958 if (--pll->active)
1959 return;
1960
1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1962 pll->disable(dev_priv, pll);
1963 pll->on = false;
1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1966 }
1967
1968 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
1970 {
1971 struct drm_device *dev = dev_priv->dev;
1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1974 uint32_t reg, val, pipeconf_val;
1975
1976 /* PCH only available on ILK+ */
1977 BUG_ON(!HAS_PCH_SPLIT(dev));
1978
1979 /* Make sure PCH DPLL is enabled */
1980 assert_shared_dpll_enabled(dev_priv,
1981 intel_crtc_to_shared_dpll(intel_crtc));
1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
1994 }
1995
1996 reg = PCH_TRANSCONF(pipe);
1997 val = I915_READ(reg);
1998 pipeconf_val = I915_READ(PIPECONF(pipe));
1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
2007 }
2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2011 if (HAS_PCH_IBX(dev_priv->dev) &&
2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2022 }
2023
2024 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2025 enum transcoder cpu_transcoder)
2026 {
2027 u32 val, pipeconf_val;
2028
2029 /* PCH only available on ILK+ */
2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2031
2032 /* FDI must be feeding us bits for PCH ports */
2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2035
2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
2041 val = TRANS_ENABLE;
2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2043
2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
2046 val |= TRANS_INTERLACED;
2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2052 DRM_ERROR("Failed to enable PCH transcoder\n");
2053 }
2054
2055 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
2057 {
2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
2068 reg = PCH_TRANSCONF(pipe);
2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
2083 }
2084
2085 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2086 {
2087 u32 val;
2088
2089 val = I915_READ(LPT_TRANSCONF);
2090 val &= ~TRANS_ENABLE;
2091 I915_WRITE(LPT_TRANSCONF, val);
2092 /* wait for PCH transcoder off, transcoder state */
2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2094 DRM_ERROR("Failed to disable PCH transcoder\n");
2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2099 I915_WRITE(_TRANSA_CHICKEN2, val);
2100 }
2101
2102 /**
2103 * intel_enable_pipe - enable a pipe, asserting requirements
2104 * @crtc: crtc responsible for the pipe
2105 *
2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2108 */
2109 static void intel_enable_pipe(struct intel_crtc *crtc)
2110 {
2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
2116 enum pipe pch_transcoder;
2117 int reg;
2118 u32 val;
2119
2120 assert_planes_disabled(dev_priv, pipe);
2121 assert_cursor_disabled(dev_priv, pipe);
2122 assert_sprites_disabled(dev_priv, pipe);
2123
2124 if (HAS_PCH_LPT(dev_priv->dev))
2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
2134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
2139 else {
2140 if (crtc->config->has_pch_encoder) {
2141 /* if driving the PCH, we need FDI enabled */
2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
2148
2149 reg = PIPECONF(cpu_transcoder);
2150 val = I915_READ(reg);
2151 if (val & PIPECONF_ENABLE) {
2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154 return;
2155 }
2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
2158 POSTING_READ(reg);
2159 }
2160
2161 /**
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2164 *
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175 enum pipe pipe = crtc->pipe;
2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
2184 assert_cursor_disabled(dev_priv, pipe);
2185 assert_sprites_disabled(dev_priv, pipe);
2186
2187 reg = PIPECONF(cpu_transcoder);
2188 val = I915_READ(reg);
2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
2196 if (crtc->config->double_wide)
2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 /*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
2213 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
2215 {
2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
2221 }
2222
2223 /**
2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
2227 *
2228 * Enable @plane on @crtc, making sure that the pipe is running first.
2229 */
2230 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
2232 {
2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2239 to_intel_plane_state(plane->state)->visible = true;
2240
2241 dev_priv->display.update_primary_plane(crtc, plane->fb,
2242 crtc->x, crtc->y);
2243 }
2244
2245 static bool need_vtd_wa(struct drm_device *dev)
2246 {
2247 #ifdef CONFIG_INTEL_IOMMU
2248 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2249 return true;
2250 #endif
2251 return false;
2252 }
2253
2254 unsigned int
2255 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2256 uint64_t fb_format_modifier)
2257 {
2258 unsigned int tile_height;
2259 uint32_t pixel_bytes;
2260
2261 switch (fb_format_modifier) {
2262 case DRM_FORMAT_MOD_NONE:
2263 tile_height = 1;
2264 break;
2265 case I915_FORMAT_MOD_X_TILED:
2266 tile_height = IS_GEN2(dev) ? 16 : 8;
2267 break;
2268 case I915_FORMAT_MOD_Y_TILED:
2269 tile_height = 32;
2270 break;
2271 case I915_FORMAT_MOD_Yf_TILED:
2272 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2273 switch (pixel_bytes) {
2274 default:
2275 case 1:
2276 tile_height = 64;
2277 break;
2278 case 2:
2279 case 4:
2280 tile_height = 32;
2281 break;
2282 case 8:
2283 tile_height = 16;
2284 break;
2285 case 16:
2286 WARN_ONCE(1,
2287 "128-bit pixels are not supported for display!");
2288 tile_height = 16;
2289 break;
2290 }
2291 break;
2292 default:
2293 MISSING_CASE(fb_format_modifier);
2294 tile_height = 1;
2295 break;
2296 }
2297
2298 return tile_height;
2299 }
2300
2301 unsigned int
2302 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2303 uint32_t pixel_format, uint64_t fb_format_modifier)
2304 {
2305 return ALIGN(height, intel_tile_height(dev, pixel_format,
2306 fb_format_modifier));
2307 }
2308
2309 static int
2310 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2311 const struct drm_plane_state *plane_state)
2312 {
2313 struct intel_rotation_info *info = &view->rotation_info;
2314
2315 *view = i915_ggtt_view_normal;
2316
2317 if (!plane_state)
2318 return 0;
2319
2320 if (!intel_rotation_90_or_270(plane_state->rotation))
2321 return 0;
2322
2323 *view = i915_ggtt_view_rotated;
2324
2325 info->height = fb->height;
2326 info->pixel_format = fb->pixel_format;
2327 info->pitch = fb->pitches[0];
2328 info->fb_modifier = fb->modifier[0];
2329
2330 return 0;
2331 }
2332
2333 int
2334 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
2336 const struct drm_plane_state *plane_state,
2337 struct intel_engine_cs *pipelined)
2338 {
2339 struct drm_device *dev = fb->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2342 struct i915_ggtt_view view;
2343 u32 alignment;
2344 int ret;
2345
2346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
2348 switch (fb->modifier[0]) {
2349 case DRM_FORMAT_MOD_NONE:
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2353 alignment = 128 * 1024;
2354 else if (INTEL_INFO(dev)->gen >= 4)
2355 alignment = 4 * 1024;
2356 else
2357 alignment = 64 * 1024;
2358 break;
2359 case I915_FORMAT_MOD_X_TILED:
2360 if (INTEL_INFO(dev)->gen >= 9)
2361 alignment = 256 * 1024;
2362 else {
2363 /* pin() will align the object as required by fence */
2364 alignment = 0;
2365 }
2366 break;
2367 case I915_FORMAT_MOD_Y_TILED:
2368 case I915_FORMAT_MOD_Yf_TILED:
2369 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370 "Y tiling bo slipped through, driver bug!\n"))
2371 return -EINVAL;
2372 alignment = 1 * 1024 * 1024;
2373 break;
2374 default:
2375 MISSING_CASE(fb->modifier[0]);
2376 return -EINVAL;
2377 }
2378
2379 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380 if (ret)
2381 return ret;
2382
2383 /* Note that the w/a also requires 64 PTE of padding following the
2384 * bo. We currently fill all unused PTE with the shadow page and so
2385 * we should always have valid PTE following the scanout preventing
2386 * the VT-d warning.
2387 */
2388 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389 alignment = 256 * 1024;
2390
2391 /*
2392 * Global gtt pte registers are special registers which actually forward
2393 * writes to a chunk of system memory. Which means that there is no risk
2394 * that the register values disappear as soon as we call
2395 * intel_runtime_pm_put(), so it is correct to wrap only the
2396 * pin/unpin/fence and not more.
2397 */
2398 intel_runtime_pm_get(dev_priv);
2399
2400 dev_priv->mm.interruptible = false;
2401 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2402 &view);
2403 if (ret)
2404 goto err_interruptible;
2405
2406 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407 * fence, whereas 965+ only requires a fence if using
2408 * framebuffer compression. For simplicity, we always install
2409 * a fence as the cost is not that onerous.
2410 */
2411 ret = i915_gem_object_get_fence(obj);
2412 if (ret)
2413 goto err_unpin;
2414
2415 i915_gem_object_pin_fence(obj);
2416
2417 dev_priv->mm.interruptible = true;
2418 intel_runtime_pm_put(dev_priv);
2419 return 0;
2420
2421 err_unpin:
2422 i915_gem_object_unpin_from_display_plane(obj, &view);
2423 err_interruptible:
2424 dev_priv->mm.interruptible = true;
2425 intel_runtime_pm_put(dev_priv);
2426 return ret;
2427 }
2428
2429 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2430 const struct drm_plane_state *plane_state)
2431 {
2432 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2433 struct i915_ggtt_view view;
2434 int ret;
2435
2436 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2437
2438 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2439 WARN_ONCE(ret, "Couldn't get view from plane state!");
2440
2441 i915_gem_object_unpin_fence(obj);
2442 i915_gem_object_unpin_from_display_plane(obj, &view);
2443 }
2444
2445 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446 * is assumed to be a power-of-two. */
2447 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
2451 {
2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
2454
2455 tile_rows = *y / 8;
2456 *y %= 8;
2457
2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
2463 unsigned int offset;
2464
2465 offset = *y * pitch + *x * cpp;
2466 *y = 0;
2467 *x = (offset & 4095) / cpp;
2468 return offset & -4096;
2469 }
2470 }
2471
2472 static int i9xx_format_to_fourcc(int format)
2473 {
2474 switch (format) {
2475 case DISPPLANE_8BPP:
2476 return DRM_FORMAT_C8;
2477 case DISPPLANE_BGRX555:
2478 return DRM_FORMAT_XRGB1555;
2479 case DISPPLANE_BGRX565:
2480 return DRM_FORMAT_RGB565;
2481 default:
2482 case DISPPLANE_BGRX888:
2483 return DRM_FORMAT_XRGB8888;
2484 case DISPPLANE_RGBX888:
2485 return DRM_FORMAT_XBGR8888;
2486 case DISPPLANE_BGRX101010:
2487 return DRM_FORMAT_XRGB2101010;
2488 case DISPPLANE_RGBX101010:
2489 return DRM_FORMAT_XBGR2101010;
2490 }
2491 }
2492
2493 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2494 {
2495 switch (format) {
2496 case PLANE_CTL_FORMAT_RGB_565:
2497 return DRM_FORMAT_RGB565;
2498 default:
2499 case PLANE_CTL_FORMAT_XRGB_8888:
2500 if (rgb_order) {
2501 if (alpha)
2502 return DRM_FORMAT_ABGR8888;
2503 else
2504 return DRM_FORMAT_XBGR8888;
2505 } else {
2506 if (alpha)
2507 return DRM_FORMAT_ARGB8888;
2508 else
2509 return DRM_FORMAT_XRGB8888;
2510 }
2511 case PLANE_CTL_FORMAT_XRGB_2101010:
2512 if (rgb_order)
2513 return DRM_FORMAT_XBGR2101010;
2514 else
2515 return DRM_FORMAT_XRGB2101010;
2516 }
2517 }
2518
2519 static bool
2520 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2521 struct intel_initial_plane_config *plane_config)
2522 {
2523 struct drm_device *dev = crtc->base.dev;
2524 struct drm_i915_gem_object *obj = NULL;
2525 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526 struct drm_framebuffer *fb = &plane_config->fb->base;
2527 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529 PAGE_SIZE);
2530
2531 size_aligned -= base_aligned;
2532
2533 if (plane_config->size == 0)
2534 return false;
2535
2536 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537 base_aligned,
2538 base_aligned,
2539 size_aligned);
2540 if (!obj)
2541 return false;
2542
2543 obj->tiling_mode = plane_config->tiling;
2544 if (obj->tiling_mode == I915_TILING_X)
2545 obj->stride = fb->pitches[0];
2546
2547 mode_cmd.pixel_format = fb->pixel_format;
2548 mode_cmd.width = fb->width;
2549 mode_cmd.height = fb->height;
2550 mode_cmd.pitches[0] = fb->pitches[0];
2551 mode_cmd.modifier[0] = fb->modifier[0];
2552 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2553
2554 mutex_lock(&dev->struct_mutex);
2555 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2556 &mode_cmd, obj)) {
2557 DRM_DEBUG_KMS("intel fb init failed\n");
2558 goto out_unref_obj;
2559 }
2560 mutex_unlock(&dev->struct_mutex);
2561
2562 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2563 return true;
2564
2565 out_unref_obj:
2566 drm_gem_object_unreference(&obj->base);
2567 mutex_unlock(&dev->struct_mutex);
2568 return false;
2569 }
2570
2571 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2572 static void
2573 update_state_fb(struct drm_plane *plane)
2574 {
2575 if (plane->fb == plane->state->fb)
2576 return;
2577
2578 if (plane->state->fb)
2579 drm_framebuffer_unreference(plane->state->fb);
2580 plane->state->fb = plane->fb;
2581 if (plane->state->fb)
2582 drm_framebuffer_reference(plane->state->fb);
2583 }
2584
2585 static void
2586 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2587 struct intel_initial_plane_config *plane_config)
2588 {
2589 struct drm_device *dev = intel_crtc->base.dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct drm_crtc *c;
2592 struct intel_crtc *i;
2593 struct drm_i915_gem_object *obj;
2594 struct drm_plane *primary = intel_crtc->base.primary;
2595 struct drm_framebuffer *fb;
2596
2597 if (!plane_config->fb)
2598 return;
2599
2600 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2601 fb = &plane_config->fb->base;
2602 goto valid_fb;
2603 }
2604
2605 kfree(plane_config->fb);
2606
2607 /*
2608 * Failed to alloc the obj, check to see if we should share
2609 * an fb with another CRTC instead
2610 */
2611 for_each_crtc(dev, c) {
2612 i = to_intel_crtc(c);
2613
2614 if (c == &intel_crtc->base)
2615 continue;
2616
2617 if (!i->active)
2618 continue;
2619
2620 fb = c->primary->fb;
2621 if (!fb)
2622 continue;
2623
2624 obj = intel_fb_obj(fb);
2625 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2626 drm_framebuffer_reference(fb);
2627 goto valid_fb;
2628 }
2629 }
2630
2631 return;
2632
2633 valid_fb:
2634 obj = intel_fb_obj(fb);
2635 if (obj->tiling_mode != I915_TILING_NONE)
2636 dev_priv->preserve_bios_swizzle = true;
2637
2638 primary->fb = fb;
2639 primary->state->crtc = &intel_crtc->base;
2640 primary->crtc = &intel_crtc->base;
2641 update_state_fb(primary);
2642 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2643 }
2644
2645 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646 struct drm_framebuffer *fb,
2647 int x, int y)
2648 {
2649 struct drm_device *dev = crtc->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2652 struct drm_plane *primary = crtc->primary;
2653 bool visible = to_intel_plane_state(primary->state)->visible;
2654 struct drm_i915_gem_object *obj;
2655 int plane = intel_crtc->plane;
2656 unsigned long linear_offset;
2657 u32 dspcntr;
2658 u32 reg = DSPCNTR(plane);
2659 int pixel_size;
2660
2661 if (!visible || !fb) {
2662 I915_WRITE(reg, 0);
2663 if (INTEL_INFO(dev)->gen >= 4)
2664 I915_WRITE(DSPSURF(plane), 0);
2665 else
2666 I915_WRITE(DSPADDR(plane), 0);
2667 POSTING_READ(reg);
2668 return;
2669 }
2670
2671 obj = intel_fb_obj(fb);
2672 if (WARN_ON(obj == NULL))
2673 return;
2674
2675 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
2677 dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
2679 dspcntr |= DISPLAY_PLANE_ENABLE;
2680
2681 if (INTEL_INFO(dev)->gen < 4) {
2682 if (intel_crtc->pipe == PIPE_B)
2683 dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685 /* pipesrc and dspsize control the size that is scaled from,
2686 * which should always be the user's requested size.
2687 */
2688 I915_WRITE(DSPSIZE(plane),
2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
2691 I915_WRITE(DSPPOS(plane), 0);
2692 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693 I915_WRITE(PRIMSIZE(plane),
2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
2696 I915_WRITE(PRIMPOS(plane), 0);
2697 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2698 }
2699
2700 switch (fb->pixel_format) {
2701 case DRM_FORMAT_C8:
2702 dspcntr |= DISPPLANE_8BPP;
2703 break;
2704 case DRM_FORMAT_XRGB1555:
2705 case DRM_FORMAT_ARGB1555:
2706 dspcntr |= DISPPLANE_BGRX555;
2707 break;
2708 case DRM_FORMAT_RGB565:
2709 dspcntr |= DISPPLANE_BGRX565;
2710 break;
2711 case DRM_FORMAT_XRGB8888:
2712 case DRM_FORMAT_ARGB8888:
2713 dspcntr |= DISPPLANE_BGRX888;
2714 break;
2715 case DRM_FORMAT_XBGR8888:
2716 case DRM_FORMAT_ABGR8888:
2717 dspcntr |= DISPPLANE_RGBX888;
2718 break;
2719 case DRM_FORMAT_XRGB2101010:
2720 case DRM_FORMAT_ARGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 case DRM_FORMAT_ABGR2101010:
2725 dspcntr |= DISPPLANE_RGBX101010;
2726 break;
2727 default:
2728 BUG();
2729 }
2730
2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
2734
2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
2739
2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
2742 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2743 pixel_size,
2744 fb->pitches[0]);
2745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
2747 intel_crtc->dspaddr_offset = linear_offset;
2748 }
2749
2750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2751 dspcntr |= DISPPLANE_ROTATE_180;
2752
2753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
2755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
2759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
2765 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2766 if (INTEL_INFO(dev)->gen >= 4) {
2767 I915_WRITE(DSPSURF(plane),
2768 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2769 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2770 I915_WRITE(DSPLINOFF(plane), linear_offset);
2771 } else
2772 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2773 POSTING_READ(reg);
2774 }
2775
2776 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2777 struct drm_framebuffer *fb,
2778 int x, int y)
2779 {
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783 struct drm_plane *primary = crtc->primary;
2784 bool visible = to_intel_plane_state(primary->state)->visible;
2785 struct drm_i915_gem_object *obj;
2786 int plane = intel_crtc->plane;
2787 unsigned long linear_offset;
2788 u32 dspcntr;
2789 u32 reg = DSPCNTR(plane);
2790 int pixel_size;
2791
2792 if (!visible || !fb) {
2793 I915_WRITE(reg, 0);
2794 I915_WRITE(DSPSURF(plane), 0);
2795 POSTING_READ(reg);
2796 return;
2797 }
2798
2799 obj = intel_fb_obj(fb);
2800 if (WARN_ON(obj == NULL))
2801 return;
2802
2803 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2804
2805 dspcntr = DISPPLANE_GAMMA_ENABLE;
2806
2807 dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812 switch (fb->pixel_format) {
2813 case DRM_FORMAT_C8:
2814 dspcntr |= DISPPLANE_8BPP;
2815 break;
2816 case DRM_FORMAT_RGB565:
2817 dspcntr |= DISPPLANE_BGRX565;
2818 break;
2819 case DRM_FORMAT_XRGB8888:
2820 case DRM_FORMAT_ARGB8888:
2821 dspcntr |= DISPPLANE_BGRX888;
2822 break;
2823 case DRM_FORMAT_XBGR8888:
2824 case DRM_FORMAT_ABGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 case DRM_FORMAT_ARGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 case DRM_FORMAT_ABGR2101010:
2833 dspcntr |= DISPPLANE_RGBX101010;
2834 break;
2835 default:
2836 BUG();
2837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
2841
2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2844
2845 linear_offset = y * fb->pitches[0] + x * pixel_size;
2846 intel_crtc->dspaddr_offset =
2847 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2848 pixel_size,
2849 fb->pitches[0]);
2850 linear_offset -= intel_crtc->dspaddr_offset;
2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
2867
2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
2877 POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882 {
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912 }
2913
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916 {
2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920 view = &i915_ggtt_view_rotated;
2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923 }
2924
2925 /*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929 {
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952 }
2953
2954 u32 skl_plane_ctl_format(uint32_t pixel_format)
2955 {
2956 u32 plane_ctl_format = 0;
2957 switch (pixel_format) {
2958 case DRM_FORMAT_RGB565:
2959 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
2960 break;
2961 case DRM_FORMAT_XBGR8888:
2962 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963 break;
2964 case DRM_FORMAT_XRGB8888:
2965 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
2966 break;
2967 /*
2968 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2969 * to be already pre-multiplied. We need to add a knob (or a different
2970 * DRM_FORMAT) for user-space to configure that.
2971 */
2972 case DRM_FORMAT_ABGR8888:
2973 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2974 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2975 break;
2976 case DRM_FORMAT_ARGB8888:
2977 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979 break;
2980 case DRM_FORMAT_XRGB2101010:
2981 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
2982 break;
2983 case DRM_FORMAT_XBGR2101010:
2984 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2985 break;
2986 case DRM_FORMAT_YUYV:
2987 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2988 break;
2989 case DRM_FORMAT_YVYU:
2990 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2991 break;
2992 case DRM_FORMAT_UYVY:
2993 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2994 break;
2995 case DRM_FORMAT_VYUY:
2996 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2997 break;
2998 default:
2999 BUG();
3000 }
3001 return plane_ctl_format;
3002 }
3003
3004 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3005 {
3006 u32 plane_ctl_tiling = 0;
3007 switch (fb_modifier) {
3008 case DRM_FORMAT_MOD_NONE:
3009 break;
3010 case I915_FORMAT_MOD_X_TILED:
3011 plane_ctl_tiling = PLANE_CTL_TILED_X;
3012 break;
3013 case I915_FORMAT_MOD_Y_TILED:
3014 plane_ctl_tiling = PLANE_CTL_TILED_Y;
3015 break;
3016 case I915_FORMAT_MOD_Yf_TILED:
3017 plane_ctl_tiling = PLANE_CTL_TILED_YF;
3018 break;
3019 default:
3020 MISSING_CASE(fb_modifier);
3021 }
3022 return plane_ctl_tiling;
3023 }
3024
3025 u32 skl_plane_ctl_rotation(unsigned int rotation)
3026 {
3027 u32 plane_ctl_rotation = 0;
3028 switch (rotation) {
3029 case BIT(DRM_ROTATE_0):
3030 break;
3031 case BIT(DRM_ROTATE_90):
3032 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3033 break;
3034 case BIT(DRM_ROTATE_180):
3035 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3036 break;
3037 case BIT(DRM_ROTATE_270):
3038 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3039 break;
3040 default:
3041 MISSING_CASE(rotation);
3042 }
3043
3044 return plane_ctl_rotation;
3045 }
3046
3047 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3048 struct drm_framebuffer *fb,
3049 int x, int y)
3050 {
3051 struct drm_device *dev = crtc->dev;
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 struct drm_plane *plane = crtc->primary;
3055 bool visible = to_intel_plane_state(plane->state)->visible;
3056 struct drm_i915_gem_object *obj;
3057 int pipe = intel_crtc->pipe;
3058 u32 plane_ctl, stride_div, stride;
3059 u32 tile_height, plane_offset, plane_size;
3060 unsigned int rotation;
3061 int x_offset, y_offset;
3062 unsigned long surf_addr;
3063 struct intel_crtc_state *crtc_state = intel_crtc->config;
3064 struct intel_plane_state *plane_state;
3065 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3066 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3067 int scaler_id = -1;
3068
3069 plane_state = to_intel_plane_state(plane->state);
3070
3071 if (!visible || !fb) {
3072 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3073 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3074 POSTING_READ(PLANE_CTL(pipe, 0));
3075 return;
3076 }
3077
3078 plane_ctl = PLANE_CTL_ENABLE |
3079 PLANE_CTL_PIPE_GAMMA_ENABLE |
3080 PLANE_CTL_PIPE_CSC_ENABLE;
3081
3082 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3083 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3084 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3085
3086 rotation = plane->state->rotation;
3087 plane_ctl |= skl_plane_ctl_rotation(rotation);
3088
3089 obj = intel_fb_obj(fb);
3090 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3091 fb->pixel_format);
3092 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3093
3094 /*
3095 * FIXME: intel_plane_state->src, dst aren't set when transitional
3096 * update_plane helpers are called from legacy paths.
3097 * Once full atomic crtc is available, below check can be avoided.
3098 */
3099 if (drm_rect_width(&plane_state->src)) {
3100 scaler_id = plane_state->scaler_id;
3101 src_x = plane_state->src.x1 >> 16;
3102 src_y = plane_state->src.y1 >> 16;
3103 src_w = drm_rect_width(&plane_state->src) >> 16;
3104 src_h = drm_rect_height(&plane_state->src) >> 16;
3105 dst_x = plane_state->dst.x1;
3106 dst_y = plane_state->dst.y1;
3107 dst_w = drm_rect_width(&plane_state->dst);
3108 dst_h = drm_rect_height(&plane_state->dst);
3109
3110 WARN_ON(x != src_x || y != src_y);
3111 } else {
3112 src_w = intel_crtc->config->pipe_src_w;
3113 src_h = intel_crtc->config->pipe_src_h;
3114 }
3115
3116 if (intel_rotation_90_or_270(rotation)) {
3117 /* stride = Surface height in tiles */
3118 tile_height = intel_tile_height(dev, fb->pixel_format,
3119 fb->modifier[0]);
3120 stride = DIV_ROUND_UP(fb->height, tile_height);
3121 x_offset = stride * tile_height - y - src_h;
3122 y_offset = x;
3123 plane_size = (src_w - 1) << 16 | (src_h - 1);
3124 } else {
3125 stride = fb->pitches[0] / stride_div;
3126 x_offset = x;
3127 y_offset = y;
3128 plane_size = (src_h - 1) << 16 | (src_w - 1);
3129 }
3130 plane_offset = y_offset << 16 | x_offset;
3131
3132 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3133 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3134 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3135 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3136
3137 if (scaler_id >= 0) {
3138 uint32_t ps_ctrl = 0;
3139
3140 WARN_ON(!dst_w || !dst_h);
3141 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3142 crtc_state->scaler_state.scalers[scaler_id].mode;
3143 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3144 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3145 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3146 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3147 I915_WRITE(PLANE_POS(pipe, 0), 0);
3148 } else {
3149 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3150 }
3151
3152 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3153
3154 POSTING_READ(PLANE_SURF(pipe, 0));
3155 }
3156
3157 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3158 static int
3159 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3160 int x, int y, enum mode_set_atomic state)
3161 {
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164
3165 if (dev_priv->display.disable_fbc)
3166 dev_priv->display.disable_fbc(dev);
3167
3168 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3169
3170 return 0;
3171 }
3172
3173 static void intel_complete_page_flips(struct drm_device *dev)
3174 {
3175 struct drm_crtc *crtc;
3176
3177 for_each_crtc(dev, crtc) {
3178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179 enum plane plane = intel_crtc->plane;
3180
3181 intel_prepare_page_flip(dev, plane);
3182 intel_finish_page_flip_plane(dev, plane);
3183 }
3184 }
3185
3186 static void intel_update_primary_planes(struct drm_device *dev)
3187 {
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189 struct drm_crtc *crtc;
3190
3191 for_each_crtc(dev, crtc) {
3192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193
3194 drm_modeset_lock(&crtc->mutex, NULL);
3195 /*
3196 * FIXME: Once we have proper support for primary planes (and
3197 * disabling them without disabling the entire crtc) allow again
3198 * a NULL crtc->primary->fb.
3199 */
3200 if (intel_crtc->active && crtc->primary->fb)
3201 dev_priv->display.update_primary_plane(crtc,
3202 crtc->primary->fb,
3203 crtc->x,
3204 crtc->y);
3205 drm_modeset_unlock(&crtc->mutex);
3206 }
3207 }
3208
3209 void intel_crtc_reset(struct intel_crtc *crtc)
3210 {
3211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3212
3213 if (!crtc->active)
3214 return;
3215
3216 intel_crtc_disable_planes(&crtc->base);
3217 dev_priv->display.crtc_disable(&crtc->base);
3218 dev_priv->display.crtc_enable(&crtc->base);
3219 intel_crtc_enable_planes(&crtc->base);
3220 }
3221
3222 void intel_prepare_reset(struct drm_device *dev)
3223 {
3224 struct drm_i915_private *dev_priv = to_i915(dev);
3225 struct intel_crtc *crtc;
3226
3227 /* no reset support for gen2 */
3228 if (IS_GEN2(dev))
3229 return;
3230
3231 /* reset doesn't touch the display */
3232 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3233 return;
3234
3235 drm_modeset_lock_all(dev);
3236
3237 /*
3238 * Disabling the crtcs gracefully seems nicer. Also the
3239 * g33 docs say we should at least disable all the planes.
3240 */
3241 for_each_intel_crtc(dev, crtc) {
3242 if (!crtc->active)
3243 continue;
3244
3245 intel_crtc_disable_planes(&crtc->base);
3246 dev_priv->display.crtc_disable(&crtc->base);
3247 }
3248 }
3249
3250 void intel_finish_reset(struct drm_device *dev)
3251 {
3252 struct drm_i915_private *dev_priv = to_i915(dev);
3253
3254 /*
3255 * Flips in the rings will be nuked by the reset,
3256 * so complete all pending flips so that user space
3257 * will get its events and not get stuck.
3258 */
3259 intel_complete_page_flips(dev);
3260
3261 /* no reset support for gen2 */
3262 if (IS_GEN2(dev))
3263 return;
3264
3265 /* reset doesn't touch the display */
3266 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3267 /*
3268 * Flips in the rings have been nuked by the reset,
3269 * so update the base address of all primary
3270 * planes to the the last fb to make sure we're
3271 * showing the correct fb after a reset.
3272 */
3273 intel_update_primary_planes(dev);
3274 return;
3275 }
3276
3277 /*
3278 * The display has been reset as well,
3279 * so need a full re-initialization.
3280 */
3281 intel_runtime_pm_disable_interrupts(dev_priv);
3282 intel_runtime_pm_enable_interrupts(dev_priv);
3283
3284 intel_modeset_init_hw(dev);
3285
3286 spin_lock_irq(&dev_priv->irq_lock);
3287 if (dev_priv->display.hpd_irq_setup)
3288 dev_priv->display.hpd_irq_setup(dev);
3289 spin_unlock_irq(&dev_priv->irq_lock);
3290
3291 intel_modeset_setup_hw_state(dev, true);
3292
3293 intel_hpd_init(dev_priv);
3294
3295 drm_modeset_unlock_all(dev);
3296 }
3297
3298 static void
3299 intel_finish_fb(struct drm_framebuffer *old_fb)
3300 {
3301 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3302 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3303 bool was_interruptible = dev_priv->mm.interruptible;
3304 int ret;
3305
3306 /* Big Hammer, we also need to ensure that any pending
3307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3308 * current scanout is retired before unpinning the old
3309 * framebuffer. Note that we rely on userspace rendering
3310 * into the buffer attached to the pipe they are waiting
3311 * on. If not, userspace generates a GPU hang with IPEHR
3312 * point to the MI_WAIT_FOR_EVENT.
3313 *
3314 * This should only fail upon a hung GPU, in which case we
3315 * can safely continue.
3316 */
3317 dev_priv->mm.interruptible = false;
3318 ret = i915_gem_object_wait_rendering(obj, true);
3319 dev_priv->mm.interruptible = was_interruptible;
3320
3321 WARN_ON(ret);
3322 }
3323
3324 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3325 {
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329 bool pending;
3330
3331 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3332 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3333 return false;
3334
3335 spin_lock_irq(&dev->event_lock);
3336 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3337 spin_unlock_irq(&dev->event_lock);
3338
3339 return pending;
3340 }
3341
3342 static void intel_update_pipe_size(struct intel_crtc *crtc)
3343 {
3344 struct drm_device *dev = crtc->base.dev;
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3346 const struct drm_display_mode *adjusted_mode;
3347
3348 if (!i915.fastboot)
3349 return;
3350
3351 /*
3352 * Update pipe size and adjust fitter if needed: the reason for this is
3353 * that in compute_mode_changes we check the native mode (not the pfit
3354 * mode) to see if we can flip rather than do a full mode set. In the
3355 * fastboot case, we'll flip, but if we don't update the pipesrc and
3356 * pfit state, we'll end up with a big fb scanned out into the wrong
3357 * sized surface.
3358 *
3359 * To fix this properly, we need to hoist the checks up into
3360 * compute_mode_changes (or above), check the actual pfit state and
3361 * whether the platform allows pfit disable with pipe active, and only
3362 * then update the pipesrc and pfit state, even on the flip path.
3363 */
3364
3365 adjusted_mode = &crtc->config->base.adjusted_mode;
3366
3367 I915_WRITE(PIPESRC(crtc->pipe),
3368 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3369 (adjusted_mode->crtc_vdisplay - 1));
3370 if (!crtc->config->pch_pfit.enabled &&
3371 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3372 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3373 I915_WRITE(PF_CTL(crtc->pipe), 0);
3374 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3375 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3376 }
3377 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3378 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3379 }
3380
3381 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3382 {
3383 struct drm_device *dev = crtc->dev;
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386 int pipe = intel_crtc->pipe;
3387 u32 reg, temp;
3388
3389 /* enable normal train */
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 if (IS_IVYBRIDGE(dev)) {
3393 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3394 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3395 } else {
3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3398 }
3399 I915_WRITE(reg, temp);
3400
3401 reg = FDI_RX_CTL(pipe);
3402 temp = I915_READ(reg);
3403 if (HAS_PCH_CPT(dev)) {
3404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3405 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3406 } else {
3407 temp &= ~FDI_LINK_TRAIN_NONE;
3408 temp |= FDI_LINK_TRAIN_NONE;
3409 }
3410 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3411
3412 /* wait one idle pattern time */
3413 POSTING_READ(reg);
3414 udelay(1000);
3415
3416 /* IVB wants error correction enabled */
3417 if (IS_IVYBRIDGE(dev))
3418 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3419 FDI_FE_ERRC_ENABLE);
3420 }
3421
3422 /* The FDI link training functions for ILK/Ibexpeak. */
3423 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3424 {
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428 int pipe = intel_crtc->pipe;
3429 u32 reg, temp, tries;
3430
3431 /* FDI needs bits from pipe first */
3432 assert_pipe_enabled(dev_priv, pipe);
3433
3434 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3435 for train result */
3436 reg = FDI_RX_IMR(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~FDI_RX_SYMBOL_LOCK;
3439 temp &= ~FDI_RX_BIT_LOCK;
3440 I915_WRITE(reg, temp);
3441 I915_READ(reg);
3442 udelay(150);
3443
3444 /* enable CPU FDI TX and PCH FDI RX */
3445 reg = FDI_TX_CTL(pipe);
3446 temp = I915_READ(reg);
3447 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3448 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3449 temp &= ~FDI_LINK_TRAIN_NONE;
3450 temp |= FDI_LINK_TRAIN_PATTERN_1;
3451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3452
3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_1;
3457 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3458
3459 POSTING_READ(reg);
3460 udelay(150);
3461
3462 /* Ironlake workaround, enable clock pointer after FDI enable*/
3463 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3464 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3465 FDI_RX_PHASE_SYNC_POINTER_EN);
3466
3467 reg = FDI_RX_IIR(pipe);
3468 for (tries = 0; tries < 5; tries++) {
3469 temp = I915_READ(reg);
3470 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3471
3472 if ((temp & FDI_RX_BIT_LOCK)) {
3473 DRM_DEBUG_KMS("FDI train 1 done.\n");
3474 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3475 break;
3476 }
3477 }
3478 if (tries == 5)
3479 DRM_ERROR("FDI train 1 fail!\n");
3480
3481 /* Train 2 */
3482 reg = FDI_TX_CTL(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~FDI_LINK_TRAIN_NONE;
3485 temp |= FDI_LINK_TRAIN_PATTERN_2;
3486 I915_WRITE(reg, temp);
3487
3488 reg = FDI_RX_CTL(pipe);
3489 temp = I915_READ(reg);
3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_2;
3492 I915_WRITE(reg, temp);
3493
3494 POSTING_READ(reg);
3495 udelay(150);
3496
3497 reg = FDI_RX_IIR(pipe);
3498 for (tries = 0; tries < 5; tries++) {
3499 temp = I915_READ(reg);
3500 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3501
3502 if (temp & FDI_RX_SYMBOL_LOCK) {
3503 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3504 DRM_DEBUG_KMS("FDI train 2 done.\n");
3505 break;
3506 }
3507 }
3508 if (tries == 5)
3509 DRM_ERROR("FDI train 2 fail!\n");
3510
3511 DRM_DEBUG_KMS("FDI train done\n");
3512
3513 }
3514
3515 static const int snb_b_fdi_train_param[] = {
3516 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3517 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3518 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3519 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3520 };
3521
3522 /* The FDI link training functions for SNB/Cougarpoint. */
3523 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3524 {
3525 struct drm_device *dev = crtc->dev;
3526 struct drm_i915_private *dev_priv = dev->dev_private;
3527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3528 int pipe = intel_crtc->pipe;
3529 u32 reg, temp, i, retry;
3530
3531 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3532 for train result */
3533 reg = FDI_RX_IMR(pipe);
3534 temp = I915_READ(reg);
3535 temp &= ~FDI_RX_SYMBOL_LOCK;
3536 temp &= ~FDI_RX_BIT_LOCK;
3537 I915_WRITE(reg, temp);
3538
3539 POSTING_READ(reg);
3540 udelay(150);
3541
3542 /* enable CPU FDI TX and PCH FDI RX */
3543 reg = FDI_TX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3547 temp &= ~FDI_LINK_TRAIN_NONE;
3548 temp |= FDI_LINK_TRAIN_PATTERN_1;
3549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3550 /* SNB-B */
3551 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3553
3554 I915_WRITE(FDI_RX_MISC(pipe),
3555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3556
3557 reg = FDI_RX_CTL(pipe);
3558 temp = I915_READ(reg);
3559 if (HAS_PCH_CPT(dev)) {
3560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3562 } else {
3563 temp &= ~FDI_LINK_TRAIN_NONE;
3564 temp |= FDI_LINK_TRAIN_PATTERN_1;
3565 }
3566 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3567
3568 POSTING_READ(reg);
3569 udelay(150);
3570
3571 for (i = 0; i < 4; i++) {
3572 reg = FDI_TX_CTL(pipe);
3573 temp = I915_READ(reg);
3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575 temp |= snb_b_fdi_train_param[i];
3576 I915_WRITE(reg, temp);
3577
3578 POSTING_READ(reg);
3579 udelay(500);
3580
3581 for (retry = 0; retry < 5; retry++) {
3582 reg = FDI_RX_IIR(pipe);
3583 temp = I915_READ(reg);
3584 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3585 if (temp & FDI_RX_BIT_LOCK) {
3586 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3587 DRM_DEBUG_KMS("FDI train 1 done.\n");
3588 break;
3589 }
3590 udelay(50);
3591 }
3592 if (retry < 5)
3593 break;
3594 }
3595 if (i == 4)
3596 DRM_ERROR("FDI train 1 fail!\n");
3597
3598 /* Train 2 */
3599 reg = FDI_TX_CTL(pipe);
3600 temp = I915_READ(reg);
3601 temp &= ~FDI_LINK_TRAIN_NONE;
3602 temp |= FDI_LINK_TRAIN_PATTERN_2;
3603 if (IS_GEN6(dev)) {
3604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3605 /* SNB-B */
3606 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3607 }
3608 I915_WRITE(reg, temp);
3609
3610 reg = FDI_RX_CTL(pipe);
3611 temp = I915_READ(reg);
3612 if (HAS_PCH_CPT(dev)) {
3613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3614 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3615 } else {
3616 temp &= ~FDI_LINK_TRAIN_NONE;
3617 temp |= FDI_LINK_TRAIN_PATTERN_2;
3618 }
3619 I915_WRITE(reg, temp);
3620
3621 POSTING_READ(reg);
3622 udelay(150);
3623
3624 for (i = 0; i < 4; i++) {
3625 reg = FDI_TX_CTL(pipe);
3626 temp = I915_READ(reg);
3627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3628 temp |= snb_b_fdi_train_param[i];
3629 I915_WRITE(reg, temp);
3630
3631 POSTING_READ(reg);
3632 udelay(500);
3633
3634 for (retry = 0; retry < 5; retry++) {
3635 reg = FDI_RX_IIR(pipe);
3636 temp = I915_READ(reg);
3637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3638 if (temp & FDI_RX_SYMBOL_LOCK) {
3639 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640 DRM_DEBUG_KMS("FDI train 2 done.\n");
3641 break;
3642 }
3643 udelay(50);
3644 }
3645 if (retry < 5)
3646 break;
3647 }
3648 if (i == 4)
3649 DRM_ERROR("FDI train 2 fail!\n");
3650
3651 DRM_DEBUG_KMS("FDI train done.\n");
3652 }
3653
3654 /* Manual link training for Ivy Bridge A0 parts */
3655 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3656 {
3657 struct drm_device *dev = crtc->dev;
3658 struct drm_i915_private *dev_priv = dev->dev_private;
3659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 int pipe = intel_crtc->pipe;
3661 u32 reg, temp, i, j;
3662
3663 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3664 for train result */
3665 reg = FDI_RX_IMR(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_RX_SYMBOL_LOCK;
3668 temp &= ~FDI_RX_BIT_LOCK;
3669 I915_WRITE(reg, temp);
3670
3671 POSTING_READ(reg);
3672 udelay(150);
3673
3674 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3675 I915_READ(FDI_RX_IIR(pipe)));
3676
3677 /* Try each vswing and preemphasis setting twice before moving on */
3678 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3679 /* disable first in case we need to retry */
3680 reg = FDI_TX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3683 temp &= ~FDI_TX_ENABLE;
3684 I915_WRITE(reg, temp);
3685
3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
3688 temp &= ~FDI_LINK_TRAIN_AUTO;
3689 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690 temp &= ~FDI_RX_ENABLE;
3691 I915_WRITE(reg, temp);
3692
3693 /* enable CPU FDI TX and PCH FDI RX */
3694 reg = FDI_TX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3697 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3698 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3699 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3700 temp |= snb_b_fdi_train_param[j/2];
3701 temp |= FDI_COMPOSITE_SYNC;
3702 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3703
3704 I915_WRITE(FDI_RX_MISC(pipe),
3705 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3710 temp |= FDI_COMPOSITE_SYNC;
3711 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3712
3713 POSTING_READ(reg);
3714 udelay(1); /* should be 0.5us */
3715
3716 for (i = 0; i < 4; i++) {
3717 reg = FDI_RX_IIR(pipe);
3718 temp = I915_READ(reg);
3719 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3720
3721 if (temp & FDI_RX_BIT_LOCK ||
3722 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3723 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3724 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3725 i);
3726 break;
3727 }
3728 udelay(1); /* should be 0.5us */
3729 }
3730 if (i == 4) {
3731 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3732 continue;
3733 }
3734
3735 /* Train 2 */
3736 reg = FDI_TX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3739 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3740 I915_WRITE(reg, temp);
3741
3742 reg = FDI_RX_CTL(pipe);
3743 temp = I915_READ(reg);
3744 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3745 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3746 I915_WRITE(reg, temp);
3747
3748 POSTING_READ(reg);
3749 udelay(2); /* should be 1.5us */
3750
3751 for (i = 0; i < 4; i++) {
3752 reg = FDI_RX_IIR(pipe);
3753 temp = I915_READ(reg);
3754 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3755
3756 if (temp & FDI_RX_SYMBOL_LOCK ||
3757 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3758 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3759 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3760 i);
3761 goto train_done;
3762 }
3763 udelay(2); /* should be 1.5us */
3764 }
3765 if (i == 4)
3766 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3767 }
3768
3769 train_done:
3770 DRM_DEBUG_KMS("FDI train done.\n");
3771 }
3772
3773 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3774 {
3775 struct drm_device *dev = intel_crtc->base.dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 int pipe = intel_crtc->pipe;
3778 u32 reg, temp;
3779
3780
3781 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3785 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3786 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3787 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3788
3789 POSTING_READ(reg);
3790 udelay(200);
3791
3792 /* Switch from Rawclk to PCDclk */
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp | FDI_PCDCLK);
3795
3796 POSTING_READ(reg);
3797 udelay(200);
3798
3799 /* Enable CPU FDI TX PLL, always on for Ironlake */
3800 reg = FDI_TX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3803 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3804
3805 POSTING_READ(reg);
3806 udelay(100);
3807 }
3808 }
3809
3810 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3811 {
3812 struct drm_device *dev = intel_crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 int pipe = intel_crtc->pipe;
3815 u32 reg, temp;
3816
3817 /* Switch from PCDclk to Rawclk */
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3821
3822 /* Disable CPU FDI TX PLL */
3823 reg = FDI_TX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3826
3827 POSTING_READ(reg);
3828 udelay(100);
3829
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3833
3834 /* Wait for the clocks to turn off. */
3835 POSTING_READ(reg);
3836 udelay(100);
3837 }
3838
3839 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3840 {
3841 struct drm_device *dev = crtc->dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3844 int pipe = intel_crtc->pipe;
3845 u32 reg, temp;
3846
3847 /* disable CPU FDI tx and PCH FDI rx */
3848 reg = FDI_TX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3851 POSTING_READ(reg);
3852
3853 reg = FDI_RX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 temp &= ~(0x7 << 16);
3856 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3857 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3858
3859 POSTING_READ(reg);
3860 udelay(100);
3861
3862 /* Ironlake workaround, disable clock pointer after downing FDI */
3863 if (HAS_PCH_IBX(dev))
3864 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3865
3866 /* still set train pattern 1 */
3867 reg = FDI_TX_CTL(pipe);
3868 temp = I915_READ(reg);
3869 temp &= ~FDI_LINK_TRAIN_NONE;
3870 temp |= FDI_LINK_TRAIN_PATTERN_1;
3871 I915_WRITE(reg, temp);
3872
3873 reg = FDI_RX_CTL(pipe);
3874 temp = I915_READ(reg);
3875 if (HAS_PCH_CPT(dev)) {
3876 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3877 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3878 } else {
3879 temp &= ~FDI_LINK_TRAIN_NONE;
3880 temp |= FDI_LINK_TRAIN_PATTERN_1;
3881 }
3882 /* BPC in FDI rx is consistent with that in PIPECONF */
3883 temp &= ~(0x07 << 16);
3884 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3885 I915_WRITE(reg, temp);
3886
3887 POSTING_READ(reg);
3888 udelay(100);
3889 }
3890
3891 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3892 {
3893 struct intel_crtc *crtc;
3894
3895 /* Note that we don't need to be called with mode_config.lock here
3896 * as our list of CRTC objects is static for the lifetime of the
3897 * device and so cannot disappear as we iterate. Similarly, we can
3898 * happily treat the predicates as racy, atomic checks as userspace
3899 * cannot claim and pin a new fb without at least acquring the
3900 * struct_mutex and so serialising with us.
3901 */
3902 for_each_intel_crtc(dev, crtc) {
3903 if (atomic_read(&crtc->unpin_work_count) == 0)
3904 continue;
3905
3906 if (crtc->unpin_work)
3907 intel_wait_for_vblank(dev, crtc->pipe);
3908
3909 return true;
3910 }
3911
3912 return false;
3913 }
3914
3915 static void page_flip_completed(struct intel_crtc *intel_crtc)
3916 {
3917 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3918 struct intel_unpin_work *work = intel_crtc->unpin_work;
3919
3920 /* ensure that the unpin work is consistent wrt ->pending. */
3921 smp_rmb();
3922 intel_crtc->unpin_work = NULL;
3923
3924 if (work->event)
3925 drm_send_vblank_event(intel_crtc->base.dev,
3926 intel_crtc->pipe,
3927 work->event);
3928
3929 drm_crtc_vblank_put(&intel_crtc->base);
3930
3931 wake_up_all(&dev_priv->pending_flip_queue);
3932 queue_work(dev_priv->wq, &work->work);
3933
3934 trace_i915_flip_complete(intel_crtc->plane,
3935 work->pending_flip_obj);
3936 }
3937
3938 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3939 {
3940 struct drm_device *dev = crtc->dev;
3941 struct drm_i915_private *dev_priv = dev->dev_private;
3942
3943 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3944 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3945 !intel_crtc_has_pending_flip(crtc),
3946 60*HZ) == 0)) {
3947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3948
3949 spin_lock_irq(&dev->event_lock);
3950 if (intel_crtc->unpin_work) {
3951 WARN_ONCE(1, "Removing stuck page flip\n");
3952 page_flip_completed(intel_crtc);
3953 }
3954 spin_unlock_irq(&dev->event_lock);
3955 }
3956
3957 if (crtc->primary->fb) {
3958 mutex_lock(&dev->struct_mutex);
3959 intel_finish_fb(crtc->primary->fb);
3960 mutex_unlock(&dev->struct_mutex);
3961 }
3962 }
3963
3964 /* Program iCLKIP clock to the desired frequency */
3965 static void lpt_program_iclkip(struct drm_crtc *crtc)
3966 {
3967 struct drm_device *dev = crtc->dev;
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3970 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3971 u32 temp;
3972
3973 mutex_lock(&dev_priv->dpio_lock);
3974
3975 /* It is necessary to ungate the pixclk gate prior to programming
3976 * the divisors, and gate it back when it is done.
3977 */
3978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3979
3980 /* Disable SSCCTL */
3981 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3982 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3983 SBI_SSCCTL_DISABLE,
3984 SBI_ICLK);
3985
3986 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3987 if (clock == 20000) {
3988 auxdiv = 1;
3989 divsel = 0x41;
3990 phaseinc = 0x20;
3991 } else {
3992 /* The iCLK virtual clock root frequency is in MHz,
3993 * but the adjusted_mode->crtc_clock in in KHz. To get the
3994 * divisors, it is necessary to divide one by another, so we
3995 * convert the virtual clock precision to KHz here for higher
3996 * precision.
3997 */
3998 u32 iclk_virtual_root_freq = 172800 * 1000;
3999 u32 iclk_pi_range = 64;
4000 u32 desired_divisor, msb_divisor_value, pi_value;
4001
4002 desired_divisor = (iclk_virtual_root_freq / clock);
4003 msb_divisor_value = desired_divisor / iclk_pi_range;
4004 pi_value = desired_divisor % iclk_pi_range;
4005
4006 auxdiv = 0;
4007 divsel = msb_divisor_value - 2;
4008 phaseinc = pi_value;
4009 }
4010
4011 /* This should not happen with any sane values */
4012 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4013 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4014 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4015 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4016
4017 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4018 clock,
4019 auxdiv,
4020 divsel,
4021 phasedir,
4022 phaseinc);
4023
4024 /* Program SSCDIVINTPHASE6 */
4025 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4026 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4027 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4028 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4029 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4030 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4031 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4032 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4033
4034 /* Program SSCAUXDIV */
4035 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4036 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4037 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4038 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4039
4040 /* Enable modulator and associated divider */
4041 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4042 temp &= ~SBI_SSCCTL_DISABLE;
4043 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4044
4045 /* Wait for initialization time */
4046 udelay(24);
4047
4048 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4049
4050 mutex_unlock(&dev_priv->dpio_lock);
4051 }
4052
4053 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4054 enum pipe pch_transcoder)
4055 {
4056 struct drm_device *dev = crtc->base.dev;
4057 struct drm_i915_private *dev_priv = dev->dev_private;
4058 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4059
4060 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4061 I915_READ(HTOTAL(cpu_transcoder)));
4062 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4063 I915_READ(HBLANK(cpu_transcoder)));
4064 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4065 I915_READ(HSYNC(cpu_transcoder)));
4066
4067 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4068 I915_READ(VTOTAL(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4070 I915_READ(VBLANK(cpu_transcoder)));
4071 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4072 I915_READ(VSYNC(cpu_transcoder)));
4073 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4074 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4075 }
4076
4077 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4078 {
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4080 uint32_t temp;
4081
4082 temp = I915_READ(SOUTH_CHICKEN1);
4083 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4084 return;
4085
4086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4088
4089 temp &= ~FDI_BC_BIFURCATION_SELECT;
4090 if (enable)
4091 temp |= FDI_BC_BIFURCATION_SELECT;
4092
4093 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4094 I915_WRITE(SOUTH_CHICKEN1, temp);
4095 POSTING_READ(SOUTH_CHICKEN1);
4096 }
4097
4098 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4099 {
4100 struct drm_device *dev = intel_crtc->base.dev;
4101
4102 switch (intel_crtc->pipe) {
4103 case PIPE_A:
4104 break;
4105 case PIPE_B:
4106 if (intel_crtc->config->fdi_lanes > 2)
4107 cpt_set_fdi_bc_bifurcation(dev, false);
4108 else
4109 cpt_set_fdi_bc_bifurcation(dev, true);
4110
4111 break;
4112 case PIPE_C:
4113 cpt_set_fdi_bc_bifurcation(dev, true);
4114
4115 break;
4116 default:
4117 BUG();
4118 }
4119 }
4120
4121 /*
4122 * Enable PCH resources required for PCH ports:
4123 * - PCH PLLs
4124 * - FDI training & RX/TX
4125 * - update transcoder timings
4126 * - DP transcoding bits
4127 * - transcoder
4128 */
4129 static void ironlake_pch_enable(struct drm_crtc *crtc)
4130 {
4131 struct drm_device *dev = crtc->dev;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4134 int pipe = intel_crtc->pipe;
4135 u32 reg, temp;
4136
4137 assert_pch_transcoder_disabled(dev_priv, pipe);
4138
4139 if (IS_IVYBRIDGE(dev))
4140 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4141
4142 /* Write the TU size bits before fdi link training, so that error
4143 * detection works. */
4144 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4145 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4146
4147 /* For PCH output, training FDI link */
4148 dev_priv->display.fdi_link_train(crtc);
4149
4150 /* We need to program the right clock selection before writing the pixel
4151 * mutliplier into the DPLL. */
4152 if (HAS_PCH_CPT(dev)) {
4153 u32 sel;
4154
4155 temp = I915_READ(PCH_DPLL_SEL);
4156 temp |= TRANS_DPLL_ENABLE(pipe);
4157 sel = TRANS_DPLLB_SEL(pipe);
4158 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4159 temp |= sel;
4160 else
4161 temp &= ~sel;
4162 I915_WRITE(PCH_DPLL_SEL, temp);
4163 }
4164
4165 /* XXX: pch pll's can be enabled any time before we enable the PCH
4166 * transcoder, and we actually should do this to not upset any PCH
4167 * transcoder that already use the clock when we share it.
4168 *
4169 * Note that enable_shared_dpll tries to do the right thing, but
4170 * get_shared_dpll unconditionally resets the pll - we need that to have
4171 * the right LVDS enable sequence. */
4172 intel_enable_shared_dpll(intel_crtc);
4173
4174 /* set transcoder timing, panel must allow it */
4175 assert_panel_unlocked(dev_priv, pipe);
4176 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4177
4178 intel_fdi_normal_train(crtc);
4179
4180 /* For PCH DP, enable TRANS_DP_CTL */
4181 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4182 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4183 reg = TRANS_DP_CTL(pipe);
4184 temp = I915_READ(reg);
4185 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4186 TRANS_DP_SYNC_MASK |
4187 TRANS_DP_BPC_MASK);
4188 temp |= (TRANS_DP_OUTPUT_ENABLE |
4189 TRANS_DP_ENH_FRAMING);
4190 temp |= bpc << 9; /* same format but at 11:9 */
4191
4192 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4193 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4194 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4195 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4196
4197 switch (intel_trans_dp_port_sel(crtc)) {
4198 case PCH_DP_B:
4199 temp |= TRANS_DP_PORT_SEL_B;
4200 break;
4201 case PCH_DP_C:
4202 temp |= TRANS_DP_PORT_SEL_C;
4203 break;
4204 case PCH_DP_D:
4205 temp |= TRANS_DP_PORT_SEL_D;
4206 break;
4207 default:
4208 BUG();
4209 }
4210
4211 I915_WRITE(reg, temp);
4212 }
4213
4214 ironlake_enable_pch_transcoder(dev_priv, pipe);
4215 }
4216
4217 static void lpt_pch_enable(struct drm_crtc *crtc)
4218 {
4219 struct drm_device *dev = crtc->dev;
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4222 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4223
4224 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4225
4226 lpt_program_iclkip(crtc);
4227
4228 /* Set transcoder timing. */
4229 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4230
4231 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4232 }
4233
4234 void intel_put_shared_dpll(struct intel_crtc *crtc)
4235 {
4236 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4237
4238 if (pll == NULL)
4239 return;
4240
4241 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4242 WARN(1, "bad %s crtc mask\n", pll->name);
4243 return;
4244 }
4245
4246 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4247 if (pll->config.crtc_mask == 0) {
4248 WARN_ON(pll->on);
4249 WARN_ON(pll->active);
4250 }
4251
4252 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4253 }
4254
4255 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4256 struct intel_crtc_state *crtc_state)
4257 {
4258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4259 struct intel_shared_dpll *pll;
4260 enum intel_dpll_id i;
4261
4262 if (HAS_PCH_IBX(dev_priv->dev)) {
4263 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4264 i = (enum intel_dpll_id) crtc->pipe;
4265 pll = &dev_priv->shared_dplls[i];
4266
4267 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4268 crtc->base.base.id, pll->name);
4269
4270 WARN_ON(pll->new_config->crtc_mask);
4271
4272 goto found;
4273 }
4274
4275 if (IS_BROXTON(dev_priv->dev)) {
4276 /* PLL is attached to port in bxt */
4277 struct intel_encoder *encoder;
4278 struct intel_digital_port *intel_dig_port;
4279
4280 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4281 if (WARN_ON(!encoder))
4282 return NULL;
4283
4284 intel_dig_port = enc_to_dig_port(&encoder->base);
4285 /* 1:1 mapping between ports and PLLs */
4286 i = (enum intel_dpll_id)intel_dig_port->port;
4287 pll = &dev_priv->shared_dplls[i];
4288 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4289 crtc->base.base.id, pll->name);
4290 WARN_ON(pll->new_config->crtc_mask);
4291
4292 goto found;
4293 }
4294
4295 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4296 pll = &dev_priv->shared_dplls[i];
4297
4298 /* Only want to check enabled timings first */
4299 if (pll->new_config->crtc_mask == 0)
4300 continue;
4301
4302 if (memcmp(&crtc_state->dpll_hw_state,
4303 &pll->new_config->hw_state,
4304 sizeof(pll->new_config->hw_state)) == 0) {
4305 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4306 crtc->base.base.id, pll->name,
4307 pll->new_config->crtc_mask,
4308 pll->active);
4309 goto found;
4310 }
4311 }
4312
4313 /* Ok no matching timings, maybe there's a free one? */
4314 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4315 pll = &dev_priv->shared_dplls[i];
4316 if (pll->new_config->crtc_mask == 0) {
4317 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4318 crtc->base.base.id, pll->name);
4319 goto found;
4320 }
4321 }
4322
4323 return NULL;
4324
4325 found:
4326 if (pll->new_config->crtc_mask == 0)
4327 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4328
4329 crtc_state->shared_dpll = i;
4330 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4331 pipe_name(crtc->pipe));
4332
4333 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4334
4335 return pll;
4336 }
4337
4338 /**
4339 * intel_shared_dpll_start_config - start a new PLL staged config
4340 * @dev_priv: DRM device
4341 * @clear_pipes: mask of pipes that will have their PLLs freed
4342 *
4343 * Starts a new PLL staged config, copying the current config but
4344 * releasing the references of pipes specified in clear_pipes.
4345 */
4346 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4347 unsigned clear_pipes)
4348 {
4349 struct intel_shared_dpll *pll;
4350 enum intel_dpll_id i;
4351
4352 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4353 pll = &dev_priv->shared_dplls[i];
4354
4355 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4356 GFP_KERNEL);
4357 if (!pll->new_config)
4358 goto cleanup;
4359
4360 pll->new_config->crtc_mask &= ~clear_pipes;
4361 }
4362
4363 return 0;
4364
4365 cleanup:
4366 while (--i >= 0) {
4367 pll = &dev_priv->shared_dplls[i];
4368 kfree(pll->new_config);
4369 pll->new_config = NULL;
4370 }
4371
4372 return -ENOMEM;
4373 }
4374
4375 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4376 {
4377 struct intel_shared_dpll *pll;
4378 enum intel_dpll_id i;
4379
4380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4381 pll = &dev_priv->shared_dplls[i];
4382
4383 WARN_ON(pll->new_config == &pll->config);
4384
4385 pll->config = *pll->new_config;
4386 kfree(pll->new_config);
4387 pll->new_config = NULL;
4388 }
4389 }
4390
4391 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4392 {
4393 struct intel_shared_dpll *pll;
4394 enum intel_dpll_id i;
4395
4396 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4397 pll = &dev_priv->shared_dplls[i];
4398
4399 WARN_ON(pll->new_config == &pll->config);
4400
4401 kfree(pll->new_config);
4402 pll->new_config = NULL;
4403 }
4404 }
4405
4406 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4407 {
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409 int dslreg = PIPEDSL(pipe);
4410 u32 temp;
4411
4412 temp = I915_READ(dslreg);
4413 udelay(500);
4414 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4415 if (wait_for(I915_READ(dslreg) != temp, 5))
4416 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4417 }
4418 }
4419
4420 /**
4421 * skl_update_scaler_users - Stages update to crtc's scaler state
4422 * @intel_crtc: crtc
4423 * @crtc_state: crtc_state
4424 * @plane: plane (NULL indicates crtc is requesting update)
4425 * @plane_state: plane's state
4426 * @force_detach: request unconditional detachment of scaler
4427 *
4428 * This function updates scaler state for requested plane or crtc.
4429 * To request scaler usage update for a plane, caller shall pass plane pointer.
4430 * To request scaler usage update for crtc, caller shall pass plane pointer
4431 * as NULL.
4432 *
4433 * Return
4434 * 0 - scaler_usage updated successfully
4435 * error - requested scaling cannot be supported or other error condition
4436 */
4437 int
4438 skl_update_scaler_users(
4439 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4440 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4441 int force_detach)
4442 {
4443 int need_scaling;
4444 int idx;
4445 int src_w, src_h, dst_w, dst_h;
4446 int *scaler_id;
4447 struct drm_framebuffer *fb;
4448 struct intel_crtc_scaler_state *scaler_state;
4449 unsigned int rotation;
4450
4451 if (!intel_crtc || !crtc_state)
4452 return 0;
4453
4454 scaler_state = &crtc_state->scaler_state;
4455
4456 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4457 fb = intel_plane ? plane_state->base.fb : NULL;
4458
4459 if (intel_plane) {
4460 src_w = drm_rect_width(&plane_state->src) >> 16;
4461 src_h = drm_rect_height(&plane_state->src) >> 16;
4462 dst_w = drm_rect_width(&plane_state->dst);
4463 dst_h = drm_rect_height(&plane_state->dst);
4464 scaler_id = &plane_state->scaler_id;
4465 rotation = plane_state->base.rotation;
4466 } else {
4467 struct drm_display_mode *adjusted_mode =
4468 &crtc_state->base.adjusted_mode;
4469 src_w = crtc_state->pipe_src_w;
4470 src_h = crtc_state->pipe_src_h;
4471 dst_w = adjusted_mode->hdisplay;
4472 dst_h = adjusted_mode->vdisplay;
4473 scaler_id = &scaler_state->scaler_id;
4474 rotation = DRM_ROTATE_0;
4475 }
4476
4477 need_scaling = intel_rotation_90_or_270(rotation) ?
4478 (src_h != dst_w || src_w != dst_h):
4479 (src_w != dst_w || src_h != dst_h);
4480
4481 /*
4482 * if plane is being disabled or scaler is no more required or force detach
4483 * - free scaler binded to this plane/crtc
4484 * - in order to do this, update crtc->scaler_usage
4485 *
4486 * Here scaler state in crtc_state is set free so that
4487 * scaler can be assigned to other user. Actual register
4488 * update to free the scaler is done in plane/panel-fit programming.
4489 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4490 */
4491 if (force_detach || !need_scaling || (intel_plane &&
4492 (!fb || !plane_state->visible))) {
4493 if (*scaler_id >= 0) {
4494 scaler_state->scaler_users &= ~(1 << idx);
4495 scaler_state->scalers[*scaler_id].in_use = 0;
4496
4497 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4498 "crtc_state = %p scaler_users = 0x%x\n",
4499 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4500 intel_plane ? intel_plane->base.base.id :
4501 intel_crtc->base.base.id, crtc_state,
4502 scaler_state->scaler_users);
4503 *scaler_id = -1;
4504 }
4505 return 0;
4506 }
4507
4508 /* range checks */
4509 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4510 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4511
4512 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4513 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4514 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4515 "size is out of scaler range\n",
4516 intel_plane ? "PLANE" : "CRTC",
4517 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4518 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4519 return -EINVAL;
4520 }
4521
4522 /* check colorkey */
4523 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4524 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4525 intel_plane->base.base.id);
4526 return -EINVAL;
4527 }
4528
4529 /* Check src format */
4530 if (intel_plane) {
4531 switch (fb->pixel_format) {
4532 case DRM_FORMAT_RGB565:
4533 case DRM_FORMAT_XBGR8888:
4534 case DRM_FORMAT_XRGB8888:
4535 case DRM_FORMAT_ABGR8888:
4536 case DRM_FORMAT_ARGB8888:
4537 case DRM_FORMAT_XRGB2101010:
4538 case DRM_FORMAT_ARGB2101010:
4539 case DRM_FORMAT_XBGR2101010:
4540 case DRM_FORMAT_ABGR2101010:
4541 case DRM_FORMAT_YUYV:
4542 case DRM_FORMAT_YVYU:
4543 case DRM_FORMAT_UYVY:
4544 case DRM_FORMAT_VYUY:
4545 break;
4546 default:
4547 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4548 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4549 return -EINVAL;
4550 }
4551 }
4552
4553 /* mark this plane as a scaler user in crtc_state */
4554 scaler_state->scaler_users |= (1 << idx);
4555 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4556 "crtc_state = %p scaler_users = 0x%x\n",
4557 intel_plane ? "PLANE" : "CRTC",
4558 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4559 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4560 return 0;
4561 }
4562
4563 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4564 {
4565 struct drm_device *dev = crtc->base.dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 int pipe = crtc->pipe;
4568 struct intel_crtc_scaler_state *scaler_state =
4569 &crtc->config->scaler_state;
4570
4571 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4572
4573 /* To update pfit, first update scaler state */
4574 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4575 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4576 skl_detach_scalers(crtc);
4577 if (!enable)
4578 return;
4579
4580 if (crtc->config->pch_pfit.enabled) {
4581 int id;
4582
4583 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4584 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4585 return;
4586 }
4587
4588 id = scaler_state->scaler_id;
4589 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4590 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4591 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4592 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4593
4594 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4595 }
4596 }
4597
4598 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4599 {
4600 struct drm_device *dev = crtc->base.dev;
4601 struct drm_i915_private *dev_priv = dev->dev_private;
4602 int pipe = crtc->pipe;
4603
4604 if (crtc->config->pch_pfit.enabled) {
4605 /* Force use of hard-coded filter coefficients
4606 * as some pre-programmed values are broken,
4607 * e.g. x201.
4608 */
4609 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4610 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4611 PF_PIPE_SEL_IVB(pipe));
4612 else
4613 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4614 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4615 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4616 }
4617 }
4618
4619 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4620 {
4621 struct drm_device *dev = crtc->dev;
4622 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4623 struct drm_plane *plane;
4624 struct intel_plane *intel_plane;
4625
4626 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4627 intel_plane = to_intel_plane(plane);
4628 if (intel_plane->pipe == pipe)
4629 intel_plane_restore(&intel_plane->base);
4630 }
4631 }
4632
4633 void hsw_enable_ips(struct intel_crtc *crtc)
4634 {
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
4638 if (!crtc->config->ips_enabled)
4639 return;
4640
4641 /* We can only enable IPS after we enable a plane and wait for a vblank */
4642 intel_wait_for_vblank(dev, crtc->pipe);
4643
4644 assert_plane_enabled(dev_priv, crtc->plane);
4645 if (IS_BROADWELL(dev)) {
4646 mutex_lock(&dev_priv->rps.hw_lock);
4647 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4648 mutex_unlock(&dev_priv->rps.hw_lock);
4649 /* Quoting Art Runyan: "its not safe to expect any particular
4650 * value in IPS_CTL bit 31 after enabling IPS through the
4651 * mailbox." Moreover, the mailbox may return a bogus state,
4652 * so we need to just enable it and continue on.
4653 */
4654 } else {
4655 I915_WRITE(IPS_CTL, IPS_ENABLE);
4656 /* The bit only becomes 1 in the next vblank, so this wait here
4657 * is essentially intel_wait_for_vblank. If we don't have this
4658 * and don't wait for vblanks until the end of crtc_enable, then
4659 * the HW state readout code will complain that the expected
4660 * IPS_CTL value is not the one we read. */
4661 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4662 DRM_ERROR("Timed out waiting for IPS enable\n");
4663 }
4664 }
4665
4666 void hsw_disable_ips(struct intel_crtc *crtc)
4667 {
4668 struct drm_device *dev = crtc->base.dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 if (!crtc->config->ips_enabled)
4672 return;
4673
4674 assert_plane_enabled(dev_priv, crtc->plane);
4675 if (IS_BROADWELL(dev)) {
4676 mutex_lock(&dev_priv->rps.hw_lock);
4677 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4678 mutex_unlock(&dev_priv->rps.hw_lock);
4679 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4680 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4681 DRM_ERROR("Timed out waiting for IPS disable\n");
4682 } else {
4683 I915_WRITE(IPS_CTL, 0);
4684 POSTING_READ(IPS_CTL);
4685 }
4686
4687 /* We need to wait for a vblank before we can disable the plane. */
4688 intel_wait_for_vblank(dev, crtc->pipe);
4689 }
4690
4691 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4692 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4693 {
4694 struct drm_device *dev = crtc->dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4697 enum pipe pipe = intel_crtc->pipe;
4698 int palreg = PALETTE(pipe);
4699 int i;
4700 bool reenable_ips = false;
4701
4702 /* The clocks have to be on to load the palette. */
4703 if (!crtc->state->enable || !intel_crtc->active)
4704 return;
4705
4706 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4707 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4708 assert_dsi_pll_enabled(dev_priv);
4709 else
4710 assert_pll_enabled(dev_priv, pipe);
4711 }
4712
4713 /* use legacy palette for Ironlake */
4714 if (!HAS_GMCH_DISPLAY(dev))
4715 palreg = LGC_PALETTE(pipe);
4716
4717 /* Workaround : Do not read or write the pipe palette/gamma data while
4718 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4719 */
4720 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4721 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4722 GAMMA_MODE_MODE_SPLIT)) {
4723 hsw_disable_ips(intel_crtc);
4724 reenable_ips = true;
4725 }
4726
4727 for (i = 0; i < 256; i++) {
4728 I915_WRITE(palreg + 4 * i,
4729 (intel_crtc->lut_r[i] << 16) |
4730 (intel_crtc->lut_g[i] << 8) |
4731 intel_crtc->lut_b[i]);
4732 }
4733
4734 if (reenable_ips)
4735 hsw_enable_ips(intel_crtc);
4736 }
4737
4738 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4739 {
4740 if (intel_crtc->overlay) {
4741 struct drm_device *dev = intel_crtc->base.dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743
4744 mutex_lock(&dev->struct_mutex);
4745 dev_priv->mm.interruptible = false;
4746 (void) intel_overlay_switch_off(intel_crtc->overlay);
4747 dev_priv->mm.interruptible = true;
4748 mutex_unlock(&dev->struct_mutex);
4749 }
4750
4751 /* Let userspace switch the overlay on again. In most cases userspace
4752 * has to recompute where to put it anyway.
4753 */
4754 }
4755
4756 /**
4757 * intel_post_enable_primary - Perform operations after enabling primary plane
4758 * @crtc: the CRTC whose primary plane was just enabled
4759 *
4760 * Performs potentially sleeping operations that must be done after the primary
4761 * plane is enabled, such as updating FBC and IPS. Note that this may be
4762 * called due to an explicit primary plane update, or due to an implicit
4763 * re-enable that is caused when a sprite plane is updated to no longer
4764 * completely hide the primary plane.
4765 */
4766 static void
4767 intel_post_enable_primary(struct drm_crtc *crtc)
4768 {
4769 struct drm_device *dev = crtc->dev;
4770 struct drm_i915_private *dev_priv = dev->dev_private;
4771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4772 int pipe = intel_crtc->pipe;
4773
4774 /*
4775 * BDW signals flip done immediately if the plane
4776 * is disabled, even if the plane enable is already
4777 * armed to occur at the next vblank :(
4778 */
4779 if (IS_BROADWELL(dev))
4780 intel_wait_for_vblank(dev, pipe);
4781
4782 /*
4783 * FIXME IPS should be fine as long as one plane is
4784 * enabled, but in practice it seems to have problems
4785 * when going from primary only to sprite only and vice
4786 * versa.
4787 */
4788 hsw_enable_ips(intel_crtc);
4789
4790 mutex_lock(&dev->struct_mutex);
4791 intel_fbc_update(dev);
4792 mutex_unlock(&dev->struct_mutex);
4793
4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So don't enable underrun reporting before at least some planes
4797 * are enabled.
4798 * FIXME: Need to fix the logic to work when we turn off all planes
4799 * but leave the pipe running.
4800 */
4801 if (IS_GEN2(dev))
4802 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4803
4804 /* Underruns don't raise interrupts, so check manually. */
4805 if (HAS_GMCH_DISPLAY(dev))
4806 i9xx_check_fifo_underruns(dev_priv);
4807 }
4808
4809 /**
4810 * intel_pre_disable_primary - Perform operations before disabling primary plane
4811 * @crtc: the CRTC whose primary plane is to be disabled
4812 *
4813 * Performs potentially sleeping operations that must be done before the
4814 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4815 * be called due to an explicit primary plane update, or due to an implicit
4816 * disable that is caused when a sprite plane completely hides the primary
4817 * plane.
4818 */
4819 static void
4820 intel_pre_disable_primary(struct drm_crtc *crtc)
4821 {
4822 struct drm_device *dev = crtc->dev;
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4825 int pipe = intel_crtc->pipe;
4826
4827 /*
4828 * Gen2 reports pipe underruns whenever all planes are disabled.
4829 * So diasble underrun reporting before all the planes get disabled.
4830 * FIXME: Need to fix the logic to work when we turn off all planes
4831 * but leave the pipe running.
4832 */
4833 if (IS_GEN2(dev))
4834 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4835
4836 /*
4837 * Vblank time updates from the shadow to live plane control register
4838 * are blocked if the memory self-refresh mode is active at that
4839 * moment. So to make sure the plane gets truly disabled, disable
4840 * first the self-refresh mode. The self-refresh enable bit in turn
4841 * will be checked/applied by the HW only at the next frame start
4842 * event which is after the vblank start event, so we need to have a
4843 * wait-for-vblank between disabling the plane and the pipe.
4844 */
4845 if (HAS_GMCH_DISPLAY(dev))
4846 intel_set_memory_cxsr(dev_priv, false);
4847
4848 mutex_lock(&dev->struct_mutex);
4849 if (dev_priv->fbc.crtc == intel_crtc)
4850 intel_fbc_disable(dev);
4851 mutex_unlock(&dev->struct_mutex);
4852
4853 /*
4854 * FIXME IPS should be fine as long as one plane is
4855 * enabled, but in practice it seems to have problems
4856 * when going from primary only to sprite only and vice
4857 * versa.
4858 */
4859 hsw_disable_ips(intel_crtc);
4860 }
4861
4862 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4863 {
4864 intel_enable_primary_hw_plane(crtc->primary, crtc);
4865 intel_enable_sprite_planes(crtc);
4866 intel_crtc_update_cursor(crtc, true);
4867
4868 intel_post_enable_primary(crtc);
4869 }
4870
4871 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4872 {
4873 struct drm_device *dev = crtc->dev;
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875 struct intel_plane *intel_plane;
4876 int pipe = intel_crtc->pipe;
4877
4878 intel_crtc_wait_for_pending_flips(crtc);
4879
4880 intel_pre_disable_primary(crtc);
4881
4882 intel_crtc_dpms_overlay_disable(intel_crtc);
4883 for_each_intel_plane(dev, intel_plane) {
4884 if (intel_plane->pipe == pipe) {
4885 struct drm_crtc *from = intel_plane->base.crtc;
4886
4887 intel_plane->disable_plane(&intel_plane->base,
4888 from ?: crtc, true);
4889 }
4890 }
4891
4892 /*
4893 * FIXME: Once we grow proper nuclear flip support out of this we need
4894 * to compute the mask of flip planes precisely. For the time being
4895 * consider this a flip to a NULL plane.
4896 */
4897 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4898 }
4899
4900 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4901 {
4902 struct drm_device *dev = crtc->dev;
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905 struct intel_encoder *encoder;
4906 int pipe = intel_crtc->pipe;
4907
4908 WARN_ON(!crtc->state->enable);
4909
4910 if (intel_crtc->active)
4911 return;
4912
4913 if (intel_crtc->config->has_pch_encoder)
4914 intel_prepare_shared_dpll(intel_crtc);
4915
4916 if (intel_crtc->config->has_dp_encoder)
4917 intel_dp_set_m_n(intel_crtc, M1_N1);
4918
4919 intel_set_pipe_timings(intel_crtc);
4920
4921 if (intel_crtc->config->has_pch_encoder) {
4922 intel_cpu_transcoder_set_m_n(intel_crtc,
4923 &intel_crtc->config->fdi_m_n, NULL);
4924 }
4925
4926 ironlake_set_pipeconf(crtc);
4927
4928 intel_crtc->active = true;
4929
4930 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4931 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4932
4933 for_each_encoder_on_crtc(dev, crtc, encoder)
4934 if (encoder->pre_enable)
4935 encoder->pre_enable(encoder);
4936
4937 if (intel_crtc->config->has_pch_encoder) {
4938 /* Note: FDI PLL enabling _must_ be done before we enable the
4939 * cpu pipes, hence this is separate from all the other fdi/pch
4940 * enabling. */
4941 ironlake_fdi_pll_enable(intel_crtc);
4942 } else {
4943 assert_fdi_tx_disabled(dev_priv, pipe);
4944 assert_fdi_rx_disabled(dev_priv, pipe);
4945 }
4946
4947 ironlake_pfit_enable(intel_crtc);
4948
4949 /*
4950 * On ILK+ LUT must be loaded before the pipe is running but with
4951 * clocks enabled
4952 */
4953 intel_crtc_load_lut(crtc);
4954
4955 intel_update_watermarks(crtc);
4956 intel_enable_pipe(intel_crtc);
4957
4958 if (intel_crtc->config->has_pch_encoder)
4959 ironlake_pch_enable(crtc);
4960
4961 assert_vblank_disabled(crtc);
4962 drm_crtc_vblank_on(crtc);
4963
4964 for_each_encoder_on_crtc(dev, crtc, encoder)
4965 encoder->enable(encoder);
4966
4967 if (HAS_PCH_CPT(dev))
4968 cpt_verify_modeset(dev, intel_crtc->pipe);
4969 }
4970
4971 /* IPS only exists on ULT machines and is tied to pipe A. */
4972 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4973 {
4974 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4975 }
4976
4977 /*
4978 * This implements the workaround described in the "notes" section of the mode
4979 * set sequence documentation. When going from no pipes or single pipe to
4980 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4981 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4982 */
4983 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4984 {
4985 struct drm_device *dev = crtc->base.dev;
4986 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4987
4988 /* We want to get the other_active_crtc only if there's only 1 other
4989 * active crtc. */
4990 for_each_intel_crtc(dev, crtc_it) {
4991 if (!crtc_it->active || crtc_it == crtc)
4992 continue;
4993
4994 if (other_active_crtc)
4995 return;
4996
4997 other_active_crtc = crtc_it;
4998 }
4999 if (!other_active_crtc)
5000 return;
5001
5002 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5003 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5004 }
5005
5006 static void haswell_crtc_enable(struct drm_crtc *crtc)
5007 {
5008 struct drm_device *dev = crtc->dev;
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5011 struct intel_encoder *encoder;
5012 int pipe = intel_crtc->pipe;
5013
5014 WARN_ON(!crtc->state->enable);
5015
5016 if (intel_crtc->active)
5017 return;
5018
5019 if (intel_crtc_to_shared_dpll(intel_crtc))
5020 intel_enable_shared_dpll(intel_crtc);
5021
5022 if (intel_crtc->config->has_dp_encoder)
5023 intel_dp_set_m_n(intel_crtc, M1_N1);
5024
5025 intel_set_pipe_timings(intel_crtc);
5026
5027 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5028 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5029 intel_crtc->config->pixel_multiplier - 1);
5030 }
5031
5032 if (intel_crtc->config->has_pch_encoder) {
5033 intel_cpu_transcoder_set_m_n(intel_crtc,
5034 &intel_crtc->config->fdi_m_n, NULL);
5035 }
5036
5037 haswell_set_pipeconf(crtc);
5038
5039 intel_set_pipe_csc(crtc);
5040
5041 intel_crtc->active = true;
5042
5043 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5044 for_each_encoder_on_crtc(dev, crtc, encoder)
5045 if (encoder->pre_enable)
5046 encoder->pre_enable(encoder);
5047
5048 if (intel_crtc->config->has_pch_encoder) {
5049 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5050 true);
5051 dev_priv->display.fdi_link_train(crtc);
5052 }
5053
5054 intel_ddi_enable_pipe_clock(intel_crtc);
5055
5056 if (INTEL_INFO(dev)->gen == 9)
5057 skylake_pfit_update(intel_crtc, 1);
5058 else if (INTEL_INFO(dev)->gen < 9)
5059 ironlake_pfit_enable(intel_crtc);
5060 else
5061 MISSING_CASE(INTEL_INFO(dev)->gen);
5062
5063 /*
5064 * On ILK+ LUT must be loaded before the pipe is running but with
5065 * clocks enabled
5066 */
5067 intel_crtc_load_lut(crtc);
5068
5069 intel_ddi_set_pipe_settings(crtc);
5070 intel_ddi_enable_transcoder_func(crtc);
5071
5072 intel_update_watermarks(crtc);
5073 intel_enable_pipe(intel_crtc);
5074
5075 if (intel_crtc->config->has_pch_encoder)
5076 lpt_pch_enable(crtc);
5077
5078 if (intel_crtc->config->dp_encoder_is_mst)
5079 intel_ddi_set_vc_payload_alloc(crtc, true);
5080
5081 assert_vblank_disabled(crtc);
5082 drm_crtc_vblank_on(crtc);
5083
5084 for_each_encoder_on_crtc(dev, crtc, encoder) {
5085 encoder->enable(encoder);
5086 intel_opregion_notify_encoder(encoder, true);
5087 }
5088
5089 /* If we change the relative order between pipe/planes enabling, we need
5090 * to change the workaround. */
5091 haswell_mode_set_planes_workaround(intel_crtc);
5092 }
5093
5094 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5095 {
5096 struct drm_device *dev = crtc->base.dev;
5097 struct drm_i915_private *dev_priv = dev->dev_private;
5098 int pipe = crtc->pipe;
5099
5100 /* To avoid upsetting the power well on haswell only disable the pfit if
5101 * it's in use. The hw state code will make sure we get this right. */
5102 if (crtc->config->pch_pfit.enabled) {
5103 I915_WRITE(PF_CTL(pipe), 0);
5104 I915_WRITE(PF_WIN_POS(pipe), 0);
5105 I915_WRITE(PF_WIN_SZ(pipe), 0);
5106 }
5107 }
5108
5109 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5110 {
5111 struct drm_device *dev = crtc->dev;
5112 struct drm_i915_private *dev_priv = dev->dev_private;
5113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5114 struct intel_encoder *encoder;
5115 int pipe = intel_crtc->pipe;
5116 u32 reg, temp;
5117
5118 if (!intel_crtc->active)
5119 return;
5120
5121 for_each_encoder_on_crtc(dev, crtc, encoder)
5122 encoder->disable(encoder);
5123
5124 drm_crtc_vblank_off(crtc);
5125 assert_vblank_disabled(crtc);
5126
5127 if (intel_crtc->config->has_pch_encoder)
5128 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5129
5130 intel_disable_pipe(intel_crtc);
5131
5132 ironlake_pfit_disable(intel_crtc);
5133
5134 for_each_encoder_on_crtc(dev, crtc, encoder)
5135 if (encoder->post_disable)
5136 encoder->post_disable(encoder);
5137
5138 if (intel_crtc->config->has_pch_encoder) {
5139 ironlake_fdi_disable(crtc);
5140
5141 ironlake_disable_pch_transcoder(dev_priv, pipe);
5142
5143 if (HAS_PCH_CPT(dev)) {
5144 /* disable TRANS_DP_CTL */
5145 reg = TRANS_DP_CTL(pipe);
5146 temp = I915_READ(reg);
5147 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5148 TRANS_DP_PORT_SEL_MASK);
5149 temp |= TRANS_DP_PORT_SEL_NONE;
5150 I915_WRITE(reg, temp);
5151
5152 /* disable DPLL_SEL */
5153 temp = I915_READ(PCH_DPLL_SEL);
5154 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5155 I915_WRITE(PCH_DPLL_SEL, temp);
5156 }
5157
5158 /* disable PCH DPLL */
5159 intel_disable_shared_dpll(intel_crtc);
5160
5161 ironlake_fdi_pll_disable(intel_crtc);
5162 }
5163
5164 intel_crtc->active = false;
5165 intel_update_watermarks(crtc);
5166
5167 mutex_lock(&dev->struct_mutex);
5168 intel_fbc_update(dev);
5169 mutex_unlock(&dev->struct_mutex);
5170 }
5171
5172 static void haswell_crtc_disable(struct drm_crtc *crtc)
5173 {
5174 struct drm_device *dev = crtc->dev;
5175 struct drm_i915_private *dev_priv = dev->dev_private;
5176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5177 struct intel_encoder *encoder;
5178 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5179
5180 if (!intel_crtc->active)
5181 return;
5182
5183 for_each_encoder_on_crtc(dev, crtc, encoder) {
5184 intel_opregion_notify_encoder(encoder, false);
5185 encoder->disable(encoder);
5186 }
5187
5188 drm_crtc_vblank_off(crtc);
5189 assert_vblank_disabled(crtc);
5190
5191 if (intel_crtc->config->has_pch_encoder)
5192 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5193 false);
5194 intel_disable_pipe(intel_crtc);
5195
5196 if (intel_crtc->config->dp_encoder_is_mst)
5197 intel_ddi_set_vc_payload_alloc(crtc, false);
5198
5199 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5200
5201 if (INTEL_INFO(dev)->gen == 9)
5202 skylake_pfit_update(intel_crtc, 0);
5203 else if (INTEL_INFO(dev)->gen < 9)
5204 ironlake_pfit_disable(intel_crtc);
5205 else
5206 MISSING_CASE(INTEL_INFO(dev)->gen);
5207
5208 intel_ddi_disable_pipe_clock(intel_crtc);
5209
5210 if (intel_crtc->config->has_pch_encoder) {
5211 lpt_disable_pch_transcoder(dev_priv);
5212 intel_ddi_fdi_disable(crtc);
5213 }
5214
5215 for_each_encoder_on_crtc(dev, crtc, encoder)
5216 if (encoder->post_disable)
5217 encoder->post_disable(encoder);
5218
5219 intel_crtc->active = false;
5220 intel_update_watermarks(crtc);
5221
5222 mutex_lock(&dev->struct_mutex);
5223 intel_fbc_update(dev);
5224 mutex_unlock(&dev->struct_mutex);
5225
5226 if (intel_crtc_to_shared_dpll(intel_crtc))
5227 intel_disable_shared_dpll(intel_crtc);
5228 }
5229
5230 static void ironlake_crtc_off(struct drm_crtc *crtc)
5231 {
5232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5233 intel_put_shared_dpll(intel_crtc);
5234 }
5235
5236
5237 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5238 {
5239 struct drm_device *dev = crtc->base.dev;
5240 struct drm_i915_private *dev_priv = dev->dev_private;
5241 struct intel_crtc_state *pipe_config = crtc->config;
5242
5243 if (!pipe_config->gmch_pfit.control)
5244 return;
5245
5246 /*
5247 * The panel fitter should only be adjusted whilst the pipe is disabled,
5248 * according to register description and PRM.
5249 */
5250 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5251 assert_pipe_disabled(dev_priv, crtc->pipe);
5252
5253 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5254 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5255
5256 /* Border color in case we don't scale up to the full screen. Black by
5257 * default, change to something else for debugging. */
5258 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5259 }
5260
5261 static enum intel_display_power_domain port_to_power_domain(enum port port)
5262 {
5263 switch (port) {
5264 case PORT_A:
5265 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5266 case PORT_B:
5267 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5268 case PORT_C:
5269 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5270 case PORT_D:
5271 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5272 default:
5273 WARN_ON_ONCE(1);
5274 return POWER_DOMAIN_PORT_OTHER;
5275 }
5276 }
5277
5278 #define for_each_power_domain(domain, mask) \
5279 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5280 if ((1 << (domain)) & (mask))
5281
5282 enum intel_display_power_domain
5283 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5284 {
5285 struct drm_device *dev = intel_encoder->base.dev;
5286 struct intel_digital_port *intel_dig_port;
5287
5288 switch (intel_encoder->type) {
5289 case INTEL_OUTPUT_UNKNOWN:
5290 /* Only DDI platforms should ever use this output type */
5291 WARN_ON_ONCE(!HAS_DDI(dev));
5292 case INTEL_OUTPUT_DISPLAYPORT:
5293 case INTEL_OUTPUT_HDMI:
5294 case INTEL_OUTPUT_EDP:
5295 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5296 return port_to_power_domain(intel_dig_port->port);
5297 case INTEL_OUTPUT_DP_MST:
5298 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5299 return port_to_power_domain(intel_dig_port->port);
5300 case INTEL_OUTPUT_ANALOG:
5301 return POWER_DOMAIN_PORT_CRT;
5302 case INTEL_OUTPUT_DSI:
5303 return POWER_DOMAIN_PORT_DSI;
5304 default:
5305 return POWER_DOMAIN_PORT_OTHER;
5306 }
5307 }
5308
5309 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5310 {
5311 struct drm_device *dev = crtc->dev;
5312 struct intel_encoder *intel_encoder;
5313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5314 enum pipe pipe = intel_crtc->pipe;
5315 unsigned long mask;
5316 enum transcoder transcoder;
5317
5318 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5319
5320 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5321 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5322 if (intel_crtc->config->pch_pfit.enabled ||
5323 intel_crtc->config->pch_pfit.force_thru)
5324 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5325
5326 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5327 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5328
5329 return mask;
5330 }
5331
5332 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5333 {
5334 struct drm_device *dev = state->dev;
5335 struct drm_i915_private *dev_priv = dev->dev_private;
5336 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5337 struct intel_crtc *crtc;
5338
5339 /*
5340 * First get all needed power domains, then put all unneeded, to avoid
5341 * any unnecessary toggling of the power wells.
5342 */
5343 for_each_intel_crtc(dev, crtc) {
5344 enum intel_display_power_domain domain;
5345
5346 if (!crtc->base.state->enable)
5347 continue;
5348
5349 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5350
5351 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5352 intel_display_power_get(dev_priv, domain);
5353 }
5354
5355 if (dev_priv->display.modeset_global_resources)
5356 dev_priv->display.modeset_global_resources(state);
5357
5358 for_each_intel_crtc(dev, crtc) {
5359 enum intel_display_power_domain domain;
5360
5361 for_each_power_domain(domain, crtc->enabled_power_domains)
5362 intel_display_power_put(dev_priv, domain);
5363
5364 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5365 }
5366
5367 intel_display_set_init_power(dev_priv, false);
5368 }
5369
5370 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5371 {
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 uint32_t divider;
5374 uint32_t ratio;
5375 uint32_t current_freq;
5376 int ret;
5377
5378 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5379 switch (frequency) {
5380 case 144000:
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5382 ratio = BXT_DE_PLL_RATIO(60);
5383 break;
5384 case 288000:
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5386 ratio = BXT_DE_PLL_RATIO(60);
5387 break;
5388 case 384000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 576000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394 ratio = BXT_DE_PLL_RATIO(60);
5395 break;
5396 case 624000:
5397 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5398 ratio = BXT_DE_PLL_RATIO(65);
5399 break;
5400 case 19200:
5401 /*
5402 * Bypass frequency with DE PLL disabled. Init ratio, divider
5403 * to suppress GCC warning.
5404 */
5405 ratio = 0;
5406 divider = 0;
5407 break;
5408 default:
5409 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5410
5411 return;
5412 }
5413
5414 mutex_lock(&dev_priv->rps.hw_lock);
5415 /* Inform power controller of upcoming frequency change */
5416 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5417 0x80000000);
5418 mutex_unlock(&dev_priv->rps.hw_lock);
5419
5420 if (ret) {
5421 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5422 ret, frequency);
5423 return;
5424 }
5425
5426 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5427 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5428 current_freq = current_freq * 500 + 1000;
5429
5430 /*
5431 * DE PLL has to be disabled when
5432 * - setting to 19.2MHz (bypass, PLL isn't used)
5433 * - before setting to 624MHz (PLL needs toggling)
5434 * - before setting to any frequency from 624MHz (PLL needs toggling)
5435 */
5436 if (frequency == 19200 || frequency == 624000 ||
5437 current_freq == 624000) {
5438 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5439 /* Timeout 200us */
5440 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5441 1))
5442 DRM_ERROR("timout waiting for DE PLL unlock\n");
5443 }
5444
5445 if (frequency != 19200) {
5446 uint32_t val;
5447
5448 val = I915_READ(BXT_DE_PLL_CTL);
5449 val &= ~BXT_DE_PLL_RATIO_MASK;
5450 val |= ratio;
5451 I915_WRITE(BXT_DE_PLL_CTL, val);
5452
5453 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5454 /* Timeout 200us */
5455 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5456 DRM_ERROR("timeout waiting for DE PLL lock\n");
5457
5458 val = I915_READ(CDCLK_CTL);
5459 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5460 val |= divider;
5461 /*
5462 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5463 * enable otherwise.
5464 */
5465 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5466 if (frequency >= 500000)
5467 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5468
5469 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5470 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5471 val |= (frequency - 1000) / 500;
5472 I915_WRITE(CDCLK_CTL, val);
5473 }
5474
5475 mutex_lock(&dev_priv->rps.hw_lock);
5476 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5477 DIV_ROUND_UP(frequency, 25000));
5478 mutex_unlock(&dev_priv->rps.hw_lock);
5479
5480 if (ret) {
5481 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5482 ret, frequency);
5483 return;
5484 }
5485
5486 dev_priv->cdclk_freq = frequency;
5487 }
5488
5489 void broxton_init_cdclk(struct drm_device *dev)
5490 {
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492 uint32_t val;
5493
5494 /*
5495 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5496 * or else the reset will hang because there is no PCH to respond.
5497 * Move the handshake programming to initialization sequence.
5498 * Previously was left up to BIOS.
5499 */
5500 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5501 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5502 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5503
5504 /* Enable PG1 for cdclk */
5505 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5506
5507 /* check if cd clock is enabled */
5508 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5509 DRM_DEBUG_KMS("Display already initialized\n");
5510 return;
5511 }
5512
5513 /*
5514 * FIXME:
5515 * - The initial CDCLK needs to be read from VBT.
5516 * Need to make this change after VBT has changes for BXT.
5517 * - check if setting the max (or any) cdclk freq is really necessary
5518 * here, it belongs to modeset time
5519 */
5520 broxton_set_cdclk(dev, 624000);
5521
5522 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5523 POSTING_READ(DBUF_CTL);
5524
5525 udelay(10);
5526
5527 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5528 DRM_ERROR("DBuf power enable timeout!\n");
5529 }
5530
5531 void broxton_uninit_cdclk(struct drm_device *dev)
5532 {
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534
5535 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5536 POSTING_READ(DBUF_CTL);
5537
5538 udelay(10);
5539
5540 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5541 DRM_ERROR("DBuf power disable timeout!\n");
5542
5543 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5544 broxton_set_cdclk(dev, 19200);
5545
5546 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5547 }
5548
5549 /* returns HPLL frequency in kHz */
5550 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5551 {
5552 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5553
5554 /* Obtain SKU information */
5555 mutex_lock(&dev_priv->dpio_lock);
5556 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5557 CCK_FUSE_HPLL_FREQ_MASK;
5558 mutex_unlock(&dev_priv->dpio_lock);
5559
5560 return vco_freq[hpll_freq] * 1000;
5561 }
5562
5563 static void vlv_update_cdclk(struct drm_device *dev)
5564 {
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566
5567 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5568 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5569 dev_priv->cdclk_freq);
5570
5571 /*
5572 * Program the gmbus_freq based on the cdclk frequency.
5573 * BSpec erroneously claims we should aim for 4MHz, but
5574 * in fact 1MHz is the correct frequency.
5575 */
5576 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5577 }
5578
5579 /* Adjust CDclk dividers to allow high res or save power if possible */
5580 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5581 {
5582 struct drm_i915_private *dev_priv = dev->dev_private;
5583 u32 val, cmd;
5584
5585 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5586 != dev_priv->cdclk_freq);
5587
5588 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5589 cmd = 2;
5590 else if (cdclk == 266667)
5591 cmd = 1;
5592 else
5593 cmd = 0;
5594
5595 mutex_lock(&dev_priv->rps.hw_lock);
5596 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5597 val &= ~DSPFREQGUAR_MASK;
5598 val |= (cmd << DSPFREQGUAR_SHIFT);
5599 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5600 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5601 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5602 50)) {
5603 DRM_ERROR("timed out waiting for CDclk change\n");
5604 }
5605 mutex_unlock(&dev_priv->rps.hw_lock);
5606
5607 if (cdclk == 400000) {
5608 u32 divider;
5609
5610 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5611
5612 mutex_lock(&dev_priv->dpio_lock);
5613 /* adjust cdclk divider */
5614 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5615 val &= ~DISPLAY_FREQUENCY_VALUES;
5616 val |= divider;
5617 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5618
5619 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5620 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5621 50))
5622 DRM_ERROR("timed out waiting for CDclk change\n");
5623 mutex_unlock(&dev_priv->dpio_lock);
5624 }
5625
5626 mutex_lock(&dev_priv->dpio_lock);
5627 /* adjust self-refresh exit latency value */
5628 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5629 val &= ~0x7f;
5630
5631 /*
5632 * For high bandwidth configs, we set a higher latency in the bunit
5633 * so that the core display fetch happens in time to avoid underruns.
5634 */
5635 if (cdclk == 400000)
5636 val |= 4500 / 250; /* 4.5 usec */
5637 else
5638 val |= 3000 / 250; /* 3.0 usec */
5639 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5640 mutex_unlock(&dev_priv->dpio_lock);
5641
5642 vlv_update_cdclk(dev);
5643 }
5644
5645 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5646 {
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5648 u32 val, cmd;
5649
5650 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5651 != dev_priv->cdclk_freq);
5652
5653 switch (cdclk) {
5654 case 333333:
5655 case 320000:
5656 case 266667:
5657 case 200000:
5658 break;
5659 default:
5660 MISSING_CASE(cdclk);
5661 return;
5662 }
5663
5664 /*
5665 * Specs are full of misinformation, but testing on actual
5666 * hardware has shown that we just need to write the desired
5667 * CCK divider into the Punit register.
5668 */
5669 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5670
5671 mutex_lock(&dev_priv->rps.hw_lock);
5672 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5673 val &= ~DSPFREQGUAR_MASK_CHV;
5674 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5675 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5676 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5677 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5678 50)) {
5679 DRM_ERROR("timed out waiting for CDclk change\n");
5680 }
5681 mutex_unlock(&dev_priv->rps.hw_lock);
5682
5683 vlv_update_cdclk(dev);
5684 }
5685
5686 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5687 int max_pixclk)
5688 {
5689 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5690 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5691
5692 /*
5693 * Really only a few cases to deal with, as only 4 CDclks are supported:
5694 * 200MHz
5695 * 267MHz
5696 * 320/333MHz (depends on HPLL freq)
5697 * 400MHz (VLV only)
5698 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5699 * of the lower bin and adjust if needed.
5700 *
5701 * We seem to get an unstable or solid color picture at 200MHz.
5702 * Not sure what's wrong. For now use 200MHz only when all pipes
5703 * are off.
5704 */
5705 if (!IS_CHERRYVIEW(dev_priv) &&
5706 max_pixclk > freq_320*limit/100)
5707 return 400000;
5708 else if (max_pixclk > 266667*limit/100)
5709 return freq_320;
5710 else if (max_pixclk > 0)
5711 return 266667;
5712 else
5713 return 200000;
5714 }
5715
5716 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5717 int max_pixclk)
5718 {
5719 /*
5720 * FIXME:
5721 * - remove the guardband, it's not needed on BXT
5722 * - set 19.2MHz bypass frequency if there are no active pipes
5723 */
5724 if (max_pixclk > 576000*9/10)
5725 return 624000;
5726 else if (max_pixclk > 384000*9/10)
5727 return 576000;
5728 else if (max_pixclk > 288000*9/10)
5729 return 384000;
5730 else if (max_pixclk > 144000*9/10)
5731 return 288000;
5732 else
5733 return 144000;
5734 }
5735
5736 /* Compute the max pixel clock for new configuration. Uses atomic state if
5737 * that's non-NULL, look at current state otherwise. */
5738 static int intel_mode_max_pixclk(struct drm_device *dev,
5739 struct drm_atomic_state *state)
5740 {
5741 struct intel_crtc *intel_crtc;
5742 struct intel_crtc_state *crtc_state;
5743 int max_pixclk = 0;
5744
5745 for_each_intel_crtc(dev, intel_crtc) {
5746 if (state)
5747 crtc_state =
5748 intel_atomic_get_crtc_state(state, intel_crtc);
5749 else
5750 crtc_state = intel_crtc->config;
5751 if (IS_ERR(crtc_state))
5752 return PTR_ERR(crtc_state);
5753
5754 if (!crtc_state->base.enable)
5755 continue;
5756
5757 max_pixclk = max(max_pixclk,
5758 crtc_state->base.adjusted_mode.crtc_clock);
5759 }
5760
5761 return max_pixclk;
5762 }
5763
5764 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5765 {
5766 struct drm_i915_private *dev_priv = to_i915(state->dev);
5767 struct drm_crtc *crtc;
5768 struct drm_crtc_state *crtc_state;
5769 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5770 int cdclk, i;
5771
5772 if (max_pixclk < 0)
5773 return max_pixclk;
5774
5775 if (IS_VALLEYVIEW(dev_priv))
5776 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5777 else
5778 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5779
5780 if (cdclk == dev_priv->cdclk_freq)
5781 return 0;
5782
5783 /* add all active pipes to the state */
5784 for_each_crtc(state->dev, crtc) {
5785 if (!crtc->state->enable)
5786 continue;
5787
5788 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5789 if (IS_ERR(crtc_state))
5790 return PTR_ERR(crtc_state);
5791 }
5792
5793 /* disable/enable all currently active pipes while we change cdclk */
5794 for_each_crtc_in_state(state, crtc, crtc_state, i)
5795 if (crtc_state->enable)
5796 crtc_state->mode_changed = true;
5797
5798 return 0;
5799 }
5800
5801 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5802 {
5803 unsigned int credits, default_credits;
5804
5805 if (IS_CHERRYVIEW(dev_priv))
5806 default_credits = PFI_CREDIT(12);
5807 else
5808 default_credits = PFI_CREDIT(8);
5809
5810 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5811 /* CHV suggested value is 31 or 63 */
5812 if (IS_CHERRYVIEW(dev_priv))
5813 credits = PFI_CREDIT_31;
5814 else
5815 credits = PFI_CREDIT(15);
5816 } else {
5817 credits = default_credits;
5818 }
5819
5820 /*
5821 * WA - write default credits before re-programming
5822 * FIXME: should we also set the resend bit here?
5823 */
5824 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5825 default_credits);
5826
5827 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5828 credits | PFI_CREDIT_RESEND);
5829
5830 /*
5831 * FIXME is this guaranteed to clear
5832 * immediately or should we poll for it?
5833 */
5834 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5835 }
5836
5837 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5838 {
5839 struct drm_device *dev = old_state->dev;
5840 struct drm_i915_private *dev_priv = dev->dev_private;
5841 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5842 int req_cdclk;
5843
5844 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5845 * never fail. */
5846 if (WARN_ON(max_pixclk < 0))
5847 return;
5848
5849 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5850
5851 if (req_cdclk != dev_priv->cdclk_freq) {
5852 /*
5853 * FIXME: We can end up here with all power domains off, yet
5854 * with a CDCLK frequency other than the minimum. To account
5855 * for this take the PIPE-A power domain, which covers the HW
5856 * blocks needed for the following programming. This can be
5857 * removed once it's guaranteed that we get here either with
5858 * the minimum CDCLK set, or the required power domains
5859 * enabled.
5860 */
5861 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5862
5863 if (IS_CHERRYVIEW(dev))
5864 cherryview_set_cdclk(dev, req_cdclk);
5865 else
5866 valleyview_set_cdclk(dev, req_cdclk);
5867
5868 vlv_program_pfi_credits(dev_priv);
5869
5870 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5871 }
5872 }
5873
5874 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5875 {
5876 struct drm_device *dev = crtc->dev;
5877 struct drm_i915_private *dev_priv = to_i915(dev);
5878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5879 struct intel_encoder *encoder;
5880 int pipe = intel_crtc->pipe;
5881 bool is_dsi;
5882
5883 WARN_ON(!crtc->state->enable);
5884
5885 if (intel_crtc->active)
5886 return;
5887
5888 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5889
5890 if (!is_dsi) {
5891 if (IS_CHERRYVIEW(dev))
5892 chv_prepare_pll(intel_crtc, intel_crtc->config);
5893 else
5894 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5895 }
5896
5897 if (intel_crtc->config->has_dp_encoder)
5898 intel_dp_set_m_n(intel_crtc, M1_N1);
5899
5900 intel_set_pipe_timings(intel_crtc);
5901
5902 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5903 struct drm_i915_private *dev_priv = dev->dev_private;
5904
5905 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5906 I915_WRITE(CHV_CANVAS(pipe), 0);
5907 }
5908
5909 i9xx_set_pipeconf(intel_crtc);
5910
5911 intel_crtc->active = true;
5912
5913 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5914
5915 for_each_encoder_on_crtc(dev, crtc, encoder)
5916 if (encoder->pre_pll_enable)
5917 encoder->pre_pll_enable(encoder);
5918
5919 if (!is_dsi) {
5920 if (IS_CHERRYVIEW(dev))
5921 chv_enable_pll(intel_crtc, intel_crtc->config);
5922 else
5923 vlv_enable_pll(intel_crtc, intel_crtc->config);
5924 }
5925
5926 for_each_encoder_on_crtc(dev, crtc, encoder)
5927 if (encoder->pre_enable)
5928 encoder->pre_enable(encoder);
5929
5930 i9xx_pfit_enable(intel_crtc);
5931
5932 intel_crtc_load_lut(crtc);
5933
5934 intel_update_watermarks(crtc);
5935 intel_enable_pipe(intel_crtc);
5936
5937 assert_vblank_disabled(crtc);
5938 drm_crtc_vblank_on(crtc);
5939
5940 for_each_encoder_on_crtc(dev, crtc, encoder)
5941 encoder->enable(encoder);
5942 }
5943
5944 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5945 {
5946 struct drm_device *dev = crtc->base.dev;
5947 struct drm_i915_private *dev_priv = dev->dev_private;
5948
5949 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5950 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5951 }
5952
5953 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5954 {
5955 struct drm_device *dev = crtc->dev;
5956 struct drm_i915_private *dev_priv = to_i915(dev);
5957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5958 struct intel_encoder *encoder;
5959 int pipe = intel_crtc->pipe;
5960
5961 WARN_ON(!crtc->state->enable);
5962
5963 if (intel_crtc->active)
5964 return;
5965
5966 i9xx_set_pll_dividers(intel_crtc);
5967
5968 if (intel_crtc->config->has_dp_encoder)
5969 intel_dp_set_m_n(intel_crtc, M1_N1);
5970
5971 intel_set_pipe_timings(intel_crtc);
5972
5973 i9xx_set_pipeconf(intel_crtc);
5974
5975 intel_crtc->active = true;
5976
5977 if (!IS_GEN2(dev))
5978 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5979
5980 for_each_encoder_on_crtc(dev, crtc, encoder)
5981 if (encoder->pre_enable)
5982 encoder->pre_enable(encoder);
5983
5984 i9xx_enable_pll(intel_crtc);
5985
5986 i9xx_pfit_enable(intel_crtc);
5987
5988 intel_crtc_load_lut(crtc);
5989
5990 intel_update_watermarks(crtc);
5991 intel_enable_pipe(intel_crtc);
5992
5993 assert_vblank_disabled(crtc);
5994 drm_crtc_vblank_on(crtc);
5995
5996 for_each_encoder_on_crtc(dev, crtc, encoder)
5997 encoder->enable(encoder);
5998 }
5999
6000 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6001 {
6002 struct drm_device *dev = crtc->base.dev;
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004
6005 if (!crtc->config->gmch_pfit.control)
6006 return;
6007
6008 assert_pipe_disabled(dev_priv, crtc->pipe);
6009
6010 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6011 I915_READ(PFIT_CONTROL));
6012 I915_WRITE(PFIT_CONTROL, 0);
6013 }
6014
6015 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6016 {
6017 struct drm_device *dev = crtc->dev;
6018 struct drm_i915_private *dev_priv = dev->dev_private;
6019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6020 struct intel_encoder *encoder;
6021 int pipe = intel_crtc->pipe;
6022
6023 if (!intel_crtc->active)
6024 return;
6025
6026 /*
6027 * On gen2 planes are double buffered but the pipe isn't, so we must
6028 * wait for planes to fully turn off before disabling the pipe.
6029 * We also need to wait on all gmch platforms because of the
6030 * self-refresh mode constraint explained above.
6031 */
6032 intel_wait_for_vblank(dev, pipe);
6033
6034 for_each_encoder_on_crtc(dev, crtc, encoder)
6035 encoder->disable(encoder);
6036
6037 drm_crtc_vblank_off(crtc);
6038 assert_vblank_disabled(crtc);
6039
6040 intel_disable_pipe(intel_crtc);
6041
6042 i9xx_pfit_disable(intel_crtc);
6043
6044 for_each_encoder_on_crtc(dev, crtc, encoder)
6045 if (encoder->post_disable)
6046 encoder->post_disable(encoder);
6047
6048 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6049 if (IS_CHERRYVIEW(dev))
6050 chv_disable_pll(dev_priv, pipe);
6051 else if (IS_VALLEYVIEW(dev))
6052 vlv_disable_pll(dev_priv, pipe);
6053 else
6054 i9xx_disable_pll(intel_crtc);
6055 }
6056
6057 if (!IS_GEN2(dev))
6058 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6059
6060 intel_crtc->active = false;
6061 intel_update_watermarks(crtc);
6062
6063 mutex_lock(&dev->struct_mutex);
6064 intel_fbc_update(dev);
6065 mutex_unlock(&dev->struct_mutex);
6066 }
6067
6068 static void i9xx_crtc_off(struct drm_crtc *crtc)
6069 {
6070 }
6071
6072 /* Master function to enable/disable CRTC and corresponding power wells */
6073 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6074 {
6075 struct drm_device *dev = crtc->dev;
6076 struct drm_i915_private *dev_priv = dev->dev_private;
6077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6078 enum intel_display_power_domain domain;
6079 unsigned long domains;
6080
6081 if (enable) {
6082 if (!intel_crtc->active) {
6083 domains = get_crtc_power_domains(crtc);
6084 for_each_power_domain(domain, domains)
6085 intel_display_power_get(dev_priv, domain);
6086 intel_crtc->enabled_power_domains = domains;
6087
6088 dev_priv->display.crtc_enable(crtc);
6089 intel_crtc_enable_planes(crtc);
6090 }
6091 } else {
6092 if (intel_crtc->active) {
6093 intel_crtc_disable_planes(crtc);
6094 dev_priv->display.crtc_disable(crtc);
6095
6096 domains = intel_crtc->enabled_power_domains;
6097 for_each_power_domain(domain, domains)
6098 intel_display_power_put(dev_priv, domain);
6099 intel_crtc->enabled_power_domains = 0;
6100 }
6101 }
6102 }
6103
6104 /**
6105 * Sets the power management mode of the pipe and plane.
6106 */
6107 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6108 {
6109 struct drm_device *dev = crtc->dev;
6110 struct intel_encoder *intel_encoder;
6111 bool enable = false;
6112
6113 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6114 enable |= intel_encoder->connectors_active;
6115
6116 intel_crtc_control(crtc, enable);
6117
6118 crtc->state->active = enable;
6119 }
6120
6121 static void intel_crtc_disable(struct drm_crtc *crtc)
6122 {
6123 struct drm_device *dev = crtc->dev;
6124 struct drm_connector *connector;
6125 struct drm_i915_private *dev_priv = dev->dev_private;
6126
6127 /* crtc should still be enabled when we disable it. */
6128 WARN_ON(!crtc->state->enable);
6129
6130 intel_crtc_disable_planes(crtc);
6131 dev_priv->display.crtc_disable(crtc);
6132 dev_priv->display.off(crtc);
6133
6134 drm_plane_helper_disable(crtc->primary);
6135
6136 /* Update computed state. */
6137 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6138 if (!connector->encoder || !connector->encoder->crtc)
6139 continue;
6140
6141 if (connector->encoder->crtc != crtc)
6142 continue;
6143
6144 connector->dpms = DRM_MODE_DPMS_OFF;
6145 to_intel_encoder(connector->encoder)->connectors_active = false;
6146 }
6147 }
6148
6149 void intel_encoder_destroy(struct drm_encoder *encoder)
6150 {
6151 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6152
6153 drm_encoder_cleanup(encoder);
6154 kfree(intel_encoder);
6155 }
6156
6157 /* Simple dpms helper for encoders with just one connector, no cloning and only
6158 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6159 * state of the entire output pipe. */
6160 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6161 {
6162 if (mode == DRM_MODE_DPMS_ON) {
6163 encoder->connectors_active = true;
6164
6165 intel_crtc_update_dpms(encoder->base.crtc);
6166 } else {
6167 encoder->connectors_active = false;
6168
6169 intel_crtc_update_dpms(encoder->base.crtc);
6170 }
6171 }
6172
6173 /* Cross check the actual hw state with our own modeset state tracking (and it's
6174 * internal consistency). */
6175 static void intel_connector_check_state(struct intel_connector *connector)
6176 {
6177 if (connector->get_hw_state(connector)) {
6178 struct intel_encoder *encoder = connector->encoder;
6179 struct drm_crtc *crtc;
6180 bool encoder_enabled;
6181 enum pipe pipe;
6182
6183 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6184 connector->base.base.id,
6185 connector->base.name);
6186
6187 /* there is no real hw state for MST connectors */
6188 if (connector->mst_port)
6189 return;
6190
6191 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6192 "wrong connector dpms state\n");
6193 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6194 "active connector not linked to encoder\n");
6195
6196 if (encoder) {
6197 I915_STATE_WARN(!encoder->connectors_active,
6198 "encoder->connectors_active not set\n");
6199
6200 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6201 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6202 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6203 return;
6204
6205 crtc = encoder->base.crtc;
6206
6207 I915_STATE_WARN(!crtc->state->enable,
6208 "crtc not enabled\n");
6209 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6210 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6211 "encoder active on the wrong pipe\n");
6212 }
6213 }
6214 }
6215
6216 int intel_connector_init(struct intel_connector *connector)
6217 {
6218 struct drm_connector_state *connector_state;
6219
6220 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6221 if (!connector_state)
6222 return -ENOMEM;
6223
6224 connector->base.state = connector_state;
6225 return 0;
6226 }
6227
6228 struct intel_connector *intel_connector_alloc(void)
6229 {
6230 struct intel_connector *connector;
6231
6232 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6233 if (!connector)
6234 return NULL;
6235
6236 if (intel_connector_init(connector) < 0) {
6237 kfree(connector);
6238 return NULL;
6239 }
6240
6241 return connector;
6242 }
6243
6244 /* Even simpler default implementation, if there's really no special case to
6245 * consider. */
6246 void intel_connector_dpms(struct drm_connector *connector, int mode)
6247 {
6248 /* All the simple cases only support two dpms states. */
6249 if (mode != DRM_MODE_DPMS_ON)
6250 mode = DRM_MODE_DPMS_OFF;
6251
6252 if (mode == connector->dpms)
6253 return;
6254
6255 connector->dpms = mode;
6256
6257 /* Only need to change hw state when actually enabled */
6258 if (connector->encoder)
6259 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6260
6261 intel_modeset_check_state(connector->dev);
6262 }
6263
6264 /* Simple connector->get_hw_state implementation for encoders that support only
6265 * one connector and no cloning and hence the encoder state determines the state
6266 * of the connector. */
6267 bool intel_connector_get_hw_state(struct intel_connector *connector)
6268 {
6269 enum pipe pipe = 0;
6270 struct intel_encoder *encoder = connector->encoder;
6271
6272 return encoder->get_hw_state(encoder, &pipe);
6273 }
6274
6275 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6276 {
6277 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6278 return crtc_state->fdi_lanes;
6279
6280 return 0;
6281 }
6282
6283 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6284 struct intel_crtc_state *pipe_config)
6285 {
6286 struct drm_atomic_state *state = pipe_config->base.state;
6287 struct intel_crtc *other_crtc;
6288 struct intel_crtc_state *other_crtc_state;
6289
6290 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6291 pipe_name(pipe), pipe_config->fdi_lanes);
6292 if (pipe_config->fdi_lanes > 4) {
6293 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6294 pipe_name(pipe), pipe_config->fdi_lanes);
6295 return -EINVAL;
6296 }
6297
6298 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6299 if (pipe_config->fdi_lanes > 2) {
6300 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6301 pipe_config->fdi_lanes);
6302 return -EINVAL;
6303 } else {
6304 return 0;
6305 }
6306 }
6307
6308 if (INTEL_INFO(dev)->num_pipes == 2)
6309 return 0;
6310
6311 /* Ivybridge 3 pipe is really complicated */
6312 switch (pipe) {
6313 case PIPE_A:
6314 return 0;
6315 case PIPE_B:
6316 if (pipe_config->fdi_lanes <= 2)
6317 return 0;
6318
6319 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6320 other_crtc_state =
6321 intel_atomic_get_crtc_state(state, other_crtc);
6322 if (IS_ERR(other_crtc_state))
6323 return PTR_ERR(other_crtc_state);
6324
6325 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6326 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6327 pipe_name(pipe), pipe_config->fdi_lanes);
6328 return -EINVAL;
6329 }
6330 return 0;
6331 case PIPE_C:
6332 if (pipe_config->fdi_lanes > 2) {
6333 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6334 pipe_name(pipe), pipe_config->fdi_lanes);
6335 return -EINVAL;
6336 }
6337
6338 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6339 other_crtc_state =
6340 intel_atomic_get_crtc_state(state, other_crtc);
6341 if (IS_ERR(other_crtc_state))
6342 return PTR_ERR(other_crtc_state);
6343
6344 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6345 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6346 return -EINVAL;
6347 }
6348 return 0;
6349 default:
6350 BUG();
6351 }
6352 }
6353
6354 #define RETRY 1
6355 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6356 struct intel_crtc_state *pipe_config)
6357 {
6358 struct drm_device *dev = intel_crtc->base.dev;
6359 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6360 int lane, link_bw, fdi_dotclock, ret;
6361 bool needs_recompute = false;
6362
6363 retry:
6364 /* FDI is a binary signal running at ~2.7GHz, encoding
6365 * each output octet as 10 bits. The actual frequency
6366 * is stored as a divider into a 100MHz clock, and the
6367 * mode pixel clock is stored in units of 1KHz.
6368 * Hence the bw of each lane in terms of the mode signal
6369 * is:
6370 */
6371 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6372
6373 fdi_dotclock = adjusted_mode->crtc_clock;
6374
6375 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6376 pipe_config->pipe_bpp);
6377
6378 pipe_config->fdi_lanes = lane;
6379
6380 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6381 link_bw, &pipe_config->fdi_m_n);
6382
6383 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6384 intel_crtc->pipe, pipe_config);
6385 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6386 pipe_config->pipe_bpp -= 2*3;
6387 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6388 pipe_config->pipe_bpp);
6389 needs_recompute = true;
6390 pipe_config->bw_constrained = true;
6391
6392 goto retry;
6393 }
6394
6395 if (needs_recompute)
6396 return RETRY;
6397
6398 return ret;
6399 }
6400
6401 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6402 struct intel_crtc_state *pipe_config)
6403 {
6404 pipe_config->ips_enabled = i915.enable_ips &&
6405 hsw_crtc_supports_ips(crtc) &&
6406 pipe_config->pipe_bpp <= 24;
6407 }
6408
6409 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6410 struct intel_crtc_state *pipe_config)
6411 {
6412 struct drm_device *dev = crtc->base.dev;
6413 struct drm_i915_private *dev_priv = dev->dev_private;
6414 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6415 int ret;
6416
6417 /* FIXME should check pixel clock limits on all platforms */
6418 if (INTEL_INFO(dev)->gen < 4) {
6419 int clock_limit =
6420 dev_priv->display.get_display_clock_speed(dev);
6421
6422 /*
6423 * Enable pixel doubling when the dot clock
6424 * is > 90% of the (display) core speed.
6425 *
6426 * GDG double wide on either pipe,
6427 * otherwise pipe A only.
6428 */
6429 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6430 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6431 clock_limit *= 2;
6432 pipe_config->double_wide = true;
6433 }
6434
6435 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6436 return -EINVAL;
6437 }
6438
6439 /*
6440 * Pipe horizontal size must be even in:
6441 * - DVO ganged mode
6442 * - LVDS dual channel mode
6443 * - Double wide pipe
6444 */
6445 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6446 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6447 pipe_config->pipe_src_w &= ~1;
6448
6449 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6450 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6451 */
6452 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6453 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6454 return -EINVAL;
6455
6456 if (HAS_IPS(dev))
6457 hsw_compute_ips_config(crtc, pipe_config);
6458
6459 if (pipe_config->has_pch_encoder)
6460 return ironlake_fdi_compute_config(crtc, pipe_config);
6461
6462 /* FIXME: remove below call once atomic mode set is place and all crtc
6463 * related checks called from atomic_crtc_check function */
6464 ret = 0;
6465 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6466 crtc, pipe_config->base.state);
6467 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6468
6469 return ret;
6470 }
6471
6472 static int skylake_get_display_clock_speed(struct drm_device *dev)
6473 {
6474 struct drm_i915_private *dev_priv = to_i915(dev);
6475 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6476 uint32_t cdctl = I915_READ(CDCLK_CTL);
6477 uint32_t linkrate;
6478
6479 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6480 WARN(1, "LCPLL1 not enabled\n");
6481 return 24000; /* 24MHz is the cd freq with NSSC ref */
6482 }
6483
6484 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6485 return 540000;
6486
6487 linkrate = (I915_READ(DPLL_CTRL1) &
6488 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6489
6490 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6491 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6492 /* vco 8640 */
6493 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6494 case CDCLK_FREQ_450_432:
6495 return 432000;
6496 case CDCLK_FREQ_337_308:
6497 return 308570;
6498 case CDCLK_FREQ_675_617:
6499 return 617140;
6500 default:
6501 WARN(1, "Unknown cd freq selection\n");
6502 }
6503 } else {
6504 /* vco 8100 */
6505 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6506 case CDCLK_FREQ_450_432:
6507 return 450000;
6508 case CDCLK_FREQ_337_308:
6509 return 337500;
6510 case CDCLK_FREQ_675_617:
6511 return 675000;
6512 default:
6513 WARN(1, "Unknown cd freq selection\n");
6514 }
6515 }
6516
6517 /* error case, do as if DPLL0 isn't enabled */
6518 return 24000;
6519 }
6520
6521 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6522 {
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524 uint32_t lcpll = I915_READ(LCPLL_CTL);
6525 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6526
6527 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6528 return 800000;
6529 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6530 return 450000;
6531 else if (freq == LCPLL_CLK_FREQ_450)
6532 return 450000;
6533 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6534 return 540000;
6535 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6536 return 337500;
6537 else
6538 return 675000;
6539 }
6540
6541 static int haswell_get_display_clock_speed(struct drm_device *dev)
6542 {
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544 uint32_t lcpll = I915_READ(LCPLL_CTL);
6545 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6546
6547 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6548 return 800000;
6549 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6550 return 450000;
6551 else if (freq == LCPLL_CLK_FREQ_450)
6552 return 450000;
6553 else if (IS_HSW_ULT(dev))
6554 return 337500;
6555 else
6556 return 540000;
6557 }
6558
6559 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6560 {
6561 struct drm_i915_private *dev_priv = dev->dev_private;
6562 u32 val;
6563 int divider;
6564
6565 if (dev_priv->hpll_freq == 0)
6566 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6567
6568 mutex_lock(&dev_priv->dpio_lock);
6569 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6570 mutex_unlock(&dev_priv->dpio_lock);
6571
6572 divider = val & DISPLAY_FREQUENCY_VALUES;
6573
6574 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6575 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6576 "cdclk change in progress\n");
6577
6578 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6579 }
6580
6581 static int ilk_get_display_clock_speed(struct drm_device *dev)
6582 {
6583 return 450000;
6584 }
6585
6586 static int i945_get_display_clock_speed(struct drm_device *dev)
6587 {
6588 return 400000;
6589 }
6590
6591 static int i915_get_display_clock_speed(struct drm_device *dev)
6592 {
6593 return 333333;
6594 }
6595
6596 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6597 {
6598 return 200000;
6599 }
6600
6601 static int pnv_get_display_clock_speed(struct drm_device *dev)
6602 {
6603 u16 gcfgc = 0;
6604
6605 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6606
6607 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6608 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6609 return 266667;
6610 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6611 return 333333;
6612 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6613 return 444444;
6614 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6615 return 200000;
6616 default:
6617 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6618 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6619 return 133333;
6620 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6621 return 166667;
6622 }
6623 }
6624
6625 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6626 {
6627 u16 gcfgc = 0;
6628
6629 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6630
6631 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6632 return 133333;
6633 else {
6634 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6635 case GC_DISPLAY_CLOCK_333_MHZ:
6636 return 333333;
6637 default:
6638 case GC_DISPLAY_CLOCK_190_200_MHZ:
6639 return 190000;
6640 }
6641 }
6642 }
6643
6644 static int i865_get_display_clock_speed(struct drm_device *dev)
6645 {
6646 return 266667;
6647 }
6648
6649 static int i855_get_display_clock_speed(struct drm_device *dev)
6650 {
6651 u16 hpllcc = 0;
6652 /* Assume that the hardware is in the high speed state. This
6653 * should be the default.
6654 */
6655 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6656 case GC_CLOCK_133_200:
6657 case GC_CLOCK_100_200:
6658 return 200000;
6659 case GC_CLOCK_166_250:
6660 return 250000;
6661 case GC_CLOCK_100_133:
6662 return 133333;
6663 }
6664
6665 /* Shouldn't happen */
6666 return 0;
6667 }
6668
6669 static int i830_get_display_clock_speed(struct drm_device *dev)
6670 {
6671 return 133333;
6672 }
6673
6674 static void
6675 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6676 {
6677 while (*num > DATA_LINK_M_N_MASK ||
6678 *den > DATA_LINK_M_N_MASK) {
6679 *num >>= 1;
6680 *den >>= 1;
6681 }
6682 }
6683
6684 static void compute_m_n(unsigned int m, unsigned int n,
6685 uint32_t *ret_m, uint32_t *ret_n)
6686 {
6687 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6688 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6689 intel_reduce_m_n_ratio(ret_m, ret_n);
6690 }
6691
6692 void
6693 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6694 int pixel_clock, int link_clock,
6695 struct intel_link_m_n *m_n)
6696 {
6697 m_n->tu = 64;
6698
6699 compute_m_n(bits_per_pixel * pixel_clock,
6700 link_clock * nlanes * 8,
6701 &m_n->gmch_m, &m_n->gmch_n);
6702
6703 compute_m_n(pixel_clock, link_clock,
6704 &m_n->link_m, &m_n->link_n);
6705 }
6706
6707 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6708 {
6709 if (i915.panel_use_ssc >= 0)
6710 return i915.panel_use_ssc != 0;
6711 return dev_priv->vbt.lvds_use_ssc
6712 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6713 }
6714
6715 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6716 int num_connectors)
6717 {
6718 struct drm_device *dev = crtc_state->base.crtc->dev;
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 int refclk;
6721
6722 WARN_ON(!crtc_state->base.state);
6723
6724 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6725 refclk = 100000;
6726 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6727 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6728 refclk = dev_priv->vbt.lvds_ssc_freq;
6729 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6730 } else if (!IS_GEN2(dev)) {
6731 refclk = 96000;
6732 } else {
6733 refclk = 48000;
6734 }
6735
6736 return refclk;
6737 }
6738
6739 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6740 {
6741 return (1 << dpll->n) << 16 | dpll->m2;
6742 }
6743
6744 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6745 {
6746 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6747 }
6748
6749 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6750 struct intel_crtc_state *crtc_state,
6751 intel_clock_t *reduced_clock)
6752 {
6753 struct drm_device *dev = crtc->base.dev;
6754 u32 fp, fp2 = 0;
6755
6756 if (IS_PINEVIEW(dev)) {
6757 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6758 if (reduced_clock)
6759 fp2 = pnv_dpll_compute_fp(reduced_clock);
6760 } else {
6761 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6762 if (reduced_clock)
6763 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6764 }
6765
6766 crtc_state->dpll_hw_state.fp0 = fp;
6767
6768 crtc->lowfreq_avail = false;
6769 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6770 reduced_clock) {
6771 crtc_state->dpll_hw_state.fp1 = fp2;
6772 crtc->lowfreq_avail = true;
6773 } else {
6774 crtc_state->dpll_hw_state.fp1 = fp;
6775 }
6776 }
6777
6778 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6779 pipe)
6780 {
6781 u32 reg_val;
6782
6783 /*
6784 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6785 * and set it to a reasonable value instead.
6786 */
6787 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6788 reg_val &= 0xffffff00;
6789 reg_val |= 0x00000030;
6790 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6791
6792 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6793 reg_val &= 0x8cffffff;
6794 reg_val = 0x8c000000;
6795 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6796
6797 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6798 reg_val &= 0xffffff00;
6799 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6800
6801 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6802 reg_val &= 0x00ffffff;
6803 reg_val |= 0xb0000000;
6804 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6805 }
6806
6807 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6808 struct intel_link_m_n *m_n)
6809 {
6810 struct drm_device *dev = crtc->base.dev;
6811 struct drm_i915_private *dev_priv = dev->dev_private;
6812 int pipe = crtc->pipe;
6813
6814 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6815 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6816 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6817 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6818 }
6819
6820 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6821 struct intel_link_m_n *m_n,
6822 struct intel_link_m_n *m2_n2)
6823 {
6824 struct drm_device *dev = crtc->base.dev;
6825 struct drm_i915_private *dev_priv = dev->dev_private;
6826 int pipe = crtc->pipe;
6827 enum transcoder transcoder = crtc->config->cpu_transcoder;
6828
6829 if (INTEL_INFO(dev)->gen >= 5) {
6830 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6831 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6832 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6833 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6834 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6835 * for gen < 8) and if DRRS is supported (to make sure the
6836 * registers are not unnecessarily accessed).
6837 */
6838 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6839 crtc->config->has_drrs) {
6840 I915_WRITE(PIPE_DATA_M2(transcoder),
6841 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6842 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6843 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6844 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6845 }
6846 } else {
6847 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6848 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6849 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6850 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6851 }
6852 }
6853
6854 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6855 {
6856 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6857
6858 if (m_n == M1_N1) {
6859 dp_m_n = &crtc->config->dp_m_n;
6860 dp_m2_n2 = &crtc->config->dp_m2_n2;
6861 } else if (m_n == M2_N2) {
6862
6863 /*
6864 * M2_N2 registers are not supported. Hence m2_n2 divider value
6865 * needs to be programmed into M1_N1.
6866 */
6867 dp_m_n = &crtc->config->dp_m2_n2;
6868 } else {
6869 DRM_ERROR("Unsupported divider value\n");
6870 return;
6871 }
6872
6873 if (crtc->config->has_pch_encoder)
6874 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6875 else
6876 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6877 }
6878
6879 static void vlv_update_pll(struct intel_crtc *crtc,
6880 struct intel_crtc_state *pipe_config)
6881 {
6882 u32 dpll, dpll_md;
6883
6884 /*
6885 * Enable DPIO clock input. We should never disable the reference
6886 * clock for pipe B, since VGA hotplug / manual detection depends
6887 * on it.
6888 */
6889 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6890 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6891 /* We should never disable this, set it here for state tracking */
6892 if (crtc->pipe == PIPE_B)
6893 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6894 dpll |= DPLL_VCO_ENABLE;
6895 pipe_config->dpll_hw_state.dpll = dpll;
6896
6897 dpll_md = (pipe_config->pixel_multiplier - 1)
6898 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6899 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6900 }
6901
6902 static void vlv_prepare_pll(struct intel_crtc *crtc,
6903 const struct intel_crtc_state *pipe_config)
6904 {
6905 struct drm_device *dev = crtc->base.dev;
6906 struct drm_i915_private *dev_priv = dev->dev_private;
6907 int pipe = crtc->pipe;
6908 u32 mdiv;
6909 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6910 u32 coreclk, reg_val;
6911
6912 mutex_lock(&dev_priv->dpio_lock);
6913
6914 bestn = pipe_config->dpll.n;
6915 bestm1 = pipe_config->dpll.m1;
6916 bestm2 = pipe_config->dpll.m2;
6917 bestp1 = pipe_config->dpll.p1;
6918 bestp2 = pipe_config->dpll.p2;
6919
6920 /* See eDP HDMI DPIO driver vbios notes doc */
6921
6922 /* PLL B needs special handling */
6923 if (pipe == PIPE_B)
6924 vlv_pllb_recal_opamp(dev_priv, pipe);
6925
6926 /* Set up Tx target for periodic Rcomp update */
6927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6928
6929 /* Disable target IRef on PLL */
6930 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6931 reg_val &= 0x00ffffff;
6932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6933
6934 /* Disable fast lock */
6935 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6936
6937 /* Set idtafcrecal before PLL is enabled */
6938 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6939 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6940 mdiv |= ((bestn << DPIO_N_SHIFT));
6941 mdiv |= (1 << DPIO_K_SHIFT);
6942
6943 /*
6944 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6945 * but we don't support that).
6946 * Note: don't use the DAC post divider as it seems unstable.
6947 */
6948 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6950
6951 mdiv |= DPIO_ENABLE_CALIBRATION;
6952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6953
6954 /* Set HBR and RBR LPF coefficients */
6955 if (pipe_config->port_clock == 162000 ||
6956 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6957 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6959 0x009f0003);
6960 else
6961 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6962 0x00d0000f);
6963
6964 if (pipe_config->has_dp_encoder) {
6965 /* Use SSC source */
6966 if (pipe == PIPE_A)
6967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6968 0x0df40000);
6969 else
6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6971 0x0df70000);
6972 } else { /* HDMI or VGA */
6973 /* Use bend source */
6974 if (pipe == PIPE_A)
6975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6976 0x0df70000);
6977 else
6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6979 0x0df40000);
6980 }
6981
6982 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6983 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6984 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6985 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6986 coreclk |= 0x01000000;
6987 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6988
6989 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6990 mutex_unlock(&dev_priv->dpio_lock);
6991 }
6992
6993 static void chv_update_pll(struct intel_crtc *crtc,
6994 struct intel_crtc_state *pipe_config)
6995 {
6996 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6997 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6998 DPLL_VCO_ENABLE;
6999 if (crtc->pipe != PIPE_A)
7000 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7001
7002 pipe_config->dpll_hw_state.dpll_md =
7003 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7004 }
7005
7006 static void chv_prepare_pll(struct intel_crtc *crtc,
7007 const struct intel_crtc_state *pipe_config)
7008 {
7009 struct drm_device *dev = crtc->base.dev;
7010 struct drm_i915_private *dev_priv = dev->dev_private;
7011 int pipe = crtc->pipe;
7012 int dpll_reg = DPLL(crtc->pipe);
7013 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7014 u32 loopfilter, tribuf_calcntr;
7015 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7016 u32 dpio_val;
7017 int vco;
7018
7019 bestn = pipe_config->dpll.n;
7020 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7021 bestm1 = pipe_config->dpll.m1;
7022 bestm2 = pipe_config->dpll.m2 >> 22;
7023 bestp1 = pipe_config->dpll.p1;
7024 bestp2 = pipe_config->dpll.p2;
7025 vco = pipe_config->dpll.vco;
7026 dpio_val = 0;
7027 loopfilter = 0;
7028
7029 /*
7030 * Enable Refclk and SSC
7031 */
7032 I915_WRITE(dpll_reg,
7033 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7034
7035 mutex_lock(&dev_priv->dpio_lock);
7036
7037 /* p1 and p2 divider */
7038 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7039 5 << DPIO_CHV_S1_DIV_SHIFT |
7040 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7041 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7042 1 << DPIO_CHV_K_DIV_SHIFT);
7043
7044 /* Feedback post-divider - m2 */
7045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7046
7047 /* Feedback refclk divider - n and m1 */
7048 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7049 DPIO_CHV_M1_DIV_BY_2 |
7050 1 << DPIO_CHV_N_DIV_SHIFT);
7051
7052 /* M2 fraction division */
7053 if (bestm2_frac)
7054 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7055
7056 /* M2 fraction division enable */
7057 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7058 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7059 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7060 if (bestm2_frac)
7061 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7062 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7063
7064 /* Program digital lock detect threshold */
7065 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7066 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7067 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7068 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7069 if (!bestm2_frac)
7070 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7071 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7072
7073 /* Loop filter */
7074 if (vco == 5400000) {
7075 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7076 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7077 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7078 tribuf_calcntr = 0x9;
7079 } else if (vco <= 6200000) {
7080 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7081 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7082 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7083 tribuf_calcntr = 0x9;
7084 } else if (vco <= 6480000) {
7085 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7086 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7087 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7088 tribuf_calcntr = 0x8;
7089 } else {
7090 /* Not supported. Apply the same limits as in the max case */
7091 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7092 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7093 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7094 tribuf_calcntr = 0;
7095 }
7096 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7097
7098 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7099 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7100 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7101 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7102
7103 /* AFC Recal */
7104 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7105 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7106 DPIO_AFC_RECAL);
7107
7108 mutex_unlock(&dev_priv->dpio_lock);
7109 }
7110
7111 /**
7112 * vlv_force_pll_on - forcibly enable just the PLL
7113 * @dev_priv: i915 private structure
7114 * @pipe: pipe PLL to enable
7115 * @dpll: PLL configuration
7116 *
7117 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7118 * in cases where we need the PLL enabled even when @pipe is not going to
7119 * be enabled.
7120 */
7121 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7122 const struct dpll *dpll)
7123 {
7124 struct intel_crtc *crtc =
7125 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7126 struct intel_crtc_state pipe_config = {
7127 .base.crtc = &crtc->base,
7128 .pixel_multiplier = 1,
7129 .dpll = *dpll,
7130 };
7131
7132 if (IS_CHERRYVIEW(dev)) {
7133 chv_update_pll(crtc, &pipe_config);
7134 chv_prepare_pll(crtc, &pipe_config);
7135 chv_enable_pll(crtc, &pipe_config);
7136 } else {
7137 vlv_update_pll(crtc, &pipe_config);
7138 vlv_prepare_pll(crtc, &pipe_config);
7139 vlv_enable_pll(crtc, &pipe_config);
7140 }
7141 }
7142
7143 /**
7144 * vlv_force_pll_off - forcibly disable just the PLL
7145 * @dev_priv: i915 private structure
7146 * @pipe: pipe PLL to disable
7147 *
7148 * Disable the PLL for @pipe. To be used in cases where we need
7149 * the PLL enabled even when @pipe is not going to be enabled.
7150 */
7151 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7152 {
7153 if (IS_CHERRYVIEW(dev))
7154 chv_disable_pll(to_i915(dev), pipe);
7155 else
7156 vlv_disable_pll(to_i915(dev), pipe);
7157 }
7158
7159 static void i9xx_update_pll(struct intel_crtc *crtc,
7160 struct intel_crtc_state *crtc_state,
7161 intel_clock_t *reduced_clock,
7162 int num_connectors)
7163 {
7164 struct drm_device *dev = crtc->base.dev;
7165 struct drm_i915_private *dev_priv = dev->dev_private;
7166 u32 dpll;
7167 bool is_sdvo;
7168 struct dpll *clock = &crtc_state->dpll;
7169
7170 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7171
7172 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7173 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7174
7175 dpll = DPLL_VGA_MODE_DIS;
7176
7177 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7178 dpll |= DPLLB_MODE_LVDS;
7179 else
7180 dpll |= DPLLB_MODE_DAC_SERIAL;
7181
7182 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7183 dpll |= (crtc_state->pixel_multiplier - 1)
7184 << SDVO_MULTIPLIER_SHIFT_HIRES;
7185 }
7186
7187 if (is_sdvo)
7188 dpll |= DPLL_SDVO_HIGH_SPEED;
7189
7190 if (crtc_state->has_dp_encoder)
7191 dpll |= DPLL_SDVO_HIGH_SPEED;
7192
7193 /* compute bitmask from p1 value */
7194 if (IS_PINEVIEW(dev))
7195 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7196 else {
7197 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7198 if (IS_G4X(dev) && reduced_clock)
7199 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7200 }
7201 switch (clock->p2) {
7202 case 5:
7203 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7204 break;
7205 case 7:
7206 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7207 break;
7208 case 10:
7209 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7210 break;
7211 case 14:
7212 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7213 break;
7214 }
7215 if (INTEL_INFO(dev)->gen >= 4)
7216 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7217
7218 if (crtc_state->sdvo_tv_clock)
7219 dpll |= PLL_REF_INPUT_TVCLKINBC;
7220 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7221 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7222 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7223 else
7224 dpll |= PLL_REF_INPUT_DREFCLK;
7225
7226 dpll |= DPLL_VCO_ENABLE;
7227 crtc_state->dpll_hw_state.dpll = dpll;
7228
7229 if (INTEL_INFO(dev)->gen >= 4) {
7230 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7231 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7232 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7233 }
7234 }
7235
7236 static void i8xx_update_pll(struct intel_crtc *crtc,
7237 struct intel_crtc_state *crtc_state,
7238 intel_clock_t *reduced_clock,
7239 int num_connectors)
7240 {
7241 struct drm_device *dev = crtc->base.dev;
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 u32 dpll;
7244 struct dpll *clock = &crtc_state->dpll;
7245
7246 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7247
7248 dpll = DPLL_VGA_MODE_DIS;
7249
7250 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7251 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7252 } else {
7253 if (clock->p1 == 2)
7254 dpll |= PLL_P1_DIVIDE_BY_TWO;
7255 else
7256 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7257 if (clock->p2 == 4)
7258 dpll |= PLL_P2_DIVIDE_BY_4;
7259 }
7260
7261 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7262 dpll |= DPLL_DVO_2X_MODE;
7263
7264 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7265 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7266 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7267 else
7268 dpll |= PLL_REF_INPUT_DREFCLK;
7269
7270 dpll |= DPLL_VCO_ENABLE;
7271 crtc_state->dpll_hw_state.dpll = dpll;
7272 }
7273
7274 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7275 {
7276 struct drm_device *dev = intel_crtc->base.dev;
7277 struct drm_i915_private *dev_priv = dev->dev_private;
7278 enum pipe pipe = intel_crtc->pipe;
7279 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7280 struct drm_display_mode *adjusted_mode =
7281 &intel_crtc->config->base.adjusted_mode;
7282 uint32_t crtc_vtotal, crtc_vblank_end;
7283 int vsyncshift = 0;
7284
7285 /* We need to be careful not to changed the adjusted mode, for otherwise
7286 * the hw state checker will get angry at the mismatch. */
7287 crtc_vtotal = adjusted_mode->crtc_vtotal;
7288 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7289
7290 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7291 /* the chip adds 2 halflines automatically */
7292 crtc_vtotal -= 1;
7293 crtc_vblank_end -= 1;
7294
7295 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7296 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7297 else
7298 vsyncshift = adjusted_mode->crtc_hsync_start -
7299 adjusted_mode->crtc_htotal / 2;
7300 if (vsyncshift < 0)
7301 vsyncshift += adjusted_mode->crtc_htotal;
7302 }
7303
7304 if (INTEL_INFO(dev)->gen > 3)
7305 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7306
7307 I915_WRITE(HTOTAL(cpu_transcoder),
7308 (adjusted_mode->crtc_hdisplay - 1) |
7309 ((adjusted_mode->crtc_htotal - 1) << 16));
7310 I915_WRITE(HBLANK(cpu_transcoder),
7311 (adjusted_mode->crtc_hblank_start - 1) |
7312 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7313 I915_WRITE(HSYNC(cpu_transcoder),
7314 (adjusted_mode->crtc_hsync_start - 1) |
7315 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7316
7317 I915_WRITE(VTOTAL(cpu_transcoder),
7318 (adjusted_mode->crtc_vdisplay - 1) |
7319 ((crtc_vtotal - 1) << 16));
7320 I915_WRITE(VBLANK(cpu_transcoder),
7321 (adjusted_mode->crtc_vblank_start - 1) |
7322 ((crtc_vblank_end - 1) << 16));
7323 I915_WRITE(VSYNC(cpu_transcoder),
7324 (adjusted_mode->crtc_vsync_start - 1) |
7325 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7326
7327 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7328 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7329 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7330 * bits. */
7331 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7332 (pipe == PIPE_B || pipe == PIPE_C))
7333 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7334
7335 /* pipesrc controls the size that is scaled from, which should
7336 * always be the user's requested size.
7337 */
7338 I915_WRITE(PIPESRC(pipe),
7339 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7340 (intel_crtc->config->pipe_src_h - 1));
7341 }
7342
7343 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7344 struct intel_crtc_state *pipe_config)
7345 {
7346 struct drm_device *dev = crtc->base.dev;
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7349 uint32_t tmp;
7350
7351 tmp = I915_READ(HTOTAL(cpu_transcoder));
7352 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7353 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7354 tmp = I915_READ(HBLANK(cpu_transcoder));
7355 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7356 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7357 tmp = I915_READ(HSYNC(cpu_transcoder));
7358 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7359 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7360
7361 tmp = I915_READ(VTOTAL(cpu_transcoder));
7362 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7363 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7364 tmp = I915_READ(VBLANK(cpu_transcoder));
7365 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7366 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7367 tmp = I915_READ(VSYNC(cpu_transcoder));
7368 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7369 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7370
7371 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7372 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7373 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7374 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7375 }
7376
7377 tmp = I915_READ(PIPESRC(crtc->pipe));
7378 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7379 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7380
7381 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7382 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7383 }
7384
7385 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7386 struct intel_crtc_state *pipe_config)
7387 {
7388 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7389 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7390 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7391 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7392
7393 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7394 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7395 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7396 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7397
7398 mode->flags = pipe_config->base.adjusted_mode.flags;
7399
7400 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7401 mode->flags |= pipe_config->base.adjusted_mode.flags;
7402 }
7403
7404 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7405 {
7406 struct drm_device *dev = intel_crtc->base.dev;
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 uint32_t pipeconf;
7409
7410 pipeconf = 0;
7411
7412 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7413 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7414 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7415
7416 if (intel_crtc->config->double_wide)
7417 pipeconf |= PIPECONF_DOUBLE_WIDE;
7418
7419 /* only g4x and later have fancy bpc/dither controls */
7420 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7421 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7422 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7423 pipeconf |= PIPECONF_DITHER_EN |
7424 PIPECONF_DITHER_TYPE_SP;
7425
7426 switch (intel_crtc->config->pipe_bpp) {
7427 case 18:
7428 pipeconf |= PIPECONF_6BPC;
7429 break;
7430 case 24:
7431 pipeconf |= PIPECONF_8BPC;
7432 break;
7433 case 30:
7434 pipeconf |= PIPECONF_10BPC;
7435 break;
7436 default:
7437 /* Case prevented by intel_choose_pipe_bpp_dither. */
7438 BUG();
7439 }
7440 }
7441
7442 if (HAS_PIPE_CXSR(dev)) {
7443 if (intel_crtc->lowfreq_avail) {
7444 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7445 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7446 } else {
7447 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7448 }
7449 }
7450
7451 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7452 if (INTEL_INFO(dev)->gen < 4 ||
7453 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7454 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7455 else
7456 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7457 } else
7458 pipeconf |= PIPECONF_PROGRESSIVE;
7459
7460 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7461 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7462
7463 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7464 POSTING_READ(PIPECONF(intel_crtc->pipe));
7465 }
7466
7467 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7468 struct intel_crtc_state *crtc_state)
7469 {
7470 struct drm_device *dev = crtc->base.dev;
7471 struct drm_i915_private *dev_priv = dev->dev_private;
7472 int refclk, num_connectors = 0;
7473 intel_clock_t clock, reduced_clock;
7474 bool ok, has_reduced_clock = false;
7475 bool is_lvds = false, is_dsi = false;
7476 struct intel_encoder *encoder;
7477 const intel_limit_t *limit;
7478 struct drm_atomic_state *state = crtc_state->base.state;
7479 struct drm_connector *connector;
7480 struct drm_connector_state *connector_state;
7481 int i;
7482
7483 for_each_connector_in_state(state, connector, connector_state, i) {
7484 if (connector_state->crtc != &crtc->base)
7485 continue;
7486
7487 encoder = to_intel_encoder(connector_state->best_encoder);
7488
7489 switch (encoder->type) {
7490 case INTEL_OUTPUT_LVDS:
7491 is_lvds = true;
7492 break;
7493 case INTEL_OUTPUT_DSI:
7494 is_dsi = true;
7495 break;
7496 default:
7497 break;
7498 }
7499
7500 num_connectors++;
7501 }
7502
7503 if (is_dsi)
7504 return 0;
7505
7506 if (!crtc_state->clock_set) {
7507 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7508
7509 /*
7510 * Returns a set of divisors for the desired target clock with
7511 * the given refclk, or FALSE. The returned values represent
7512 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7513 * 2) / p1 / p2.
7514 */
7515 limit = intel_limit(crtc_state, refclk);
7516 ok = dev_priv->display.find_dpll(limit, crtc_state,
7517 crtc_state->port_clock,
7518 refclk, NULL, &clock);
7519 if (!ok) {
7520 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7521 return -EINVAL;
7522 }
7523
7524 if (is_lvds && dev_priv->lvds_downclock_avail) {
7525 /*
7526 * Ensure we match the reduced clock's P to the target
7527 * clock. If the clocks don't match, we can't switch
7528 * the display clock by using the FP0/FP1. In such case
7529 * we will disable the LVDS downclock feature.
7530 */
7531 has_reduced_clock =
7532 dev_priv->display.find_dpll(limit, crtc_state,
7533 dev_priv->lvds_downclock,
7534 refclk, &clock,
7535 &reduced_clock);
7536 }
7537 /* Compat-code for transition, will disappear. */
7538 crtc_state->dpll.n = clock.n;
7539 crtc_state->dpll.m1 = clock.m1;
7540 crtc_state->dpll.m2 = clock.m2;
7541 crtc_state->dpll.p1 = clock.p1;
7542 crtc_state->dpll.p2 = clock.p2;
7543 }
7544
7545 if (IS_GEN2(dev)) {
7546 i8xx_update_pll(crtc, crtc_state,
7547 has_reduced_clock ? &reduced_clock : NULL,
7548 num_connectors);
7549 } else if (IS_CHERRYVIEW(dev)) {
7550 chv_update_pll(crtc, crtc_state);
7551 } else if (IS_VALLEYVIEW(dev)) {
7552 vlv_update_pll(crtc, crtc_state);
7553 } else {
7554 i9xx_update_pll(crtc, crtc_state,
7555 has_reduced_clock ? &reduced_clock : NULL,
7556 num_connectors);
7557 }
7558
7559 return 0;
7560 }
7561
7562 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7563 struct intel_crtc_state *pipe_config)
7564 {
7565 struct drm_device *dev = crtc->base.dev;
7566 struct drm_i915_private *dev_priv = dev->dev_private;
7567 uint32_t tmp;
7568
7569 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7570 return;
7571
7572 tmp = I915_READ(PFIT_CONTROL);
7573 if (!(tmp & PFIT_ENABLE))
7574 return;
7575
7576 /* Check whether the pfit is attached to our pipe. */
7577 if (INTEL_INFO(dev)->gen < 4) {
7578 if (crtc->pipe != PIPE_B)
7579 return;
7580 } else {
7581 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7582 return;
7583 }
7584
7585 pipe_config->gmch_pfit.control = tmp;
7586 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7587 if (INTEL_INFO(dev)->gen < 5)
7588 pipe_config->gmch_pfit.lvds_border_bits =
7589 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7590 }
7591
7592 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7593 struct intel_crtc_state *pipe_config)
7594 {
7595 struct drm_device *dev = crtc->base.dev;
7596 struct drm_i915_private *dev_priv = dev->dev_private;
7597 int pipe = pipe_config->cpu_transcoder;
7598 intel_clock_t clock;
7599 u32 mdiv;
7600 int refclk = 100000;
7601
7602 /* In case of MIPI DPLL will not even be used */
7603 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7604 return;
7605
7606 mutex_lock(&dev_priv->dpio_lock);
7607 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7608 mutex_unlock(&dev_priv->dpio_lock);
7609
7610 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7611 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7612 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7613 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7614 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7615
7616 vlv_clock(refclk, &clock);
7617
7618 /* clock.dot is the fast clock */
7619 pipe_config->port_clock = clock.dot / 5;
7620 }
7621
7622 static void
7623 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7624 struct intel_initial_plane_config *plane_config)
7625 {
7626 struct drm_device *dev = crtc->base.dev;
7627 struct drm_i915_private *dev_priv = dev->dev_private;
7628 u32 val, base, offset;
7629 int pipe = crtc->pipe, plane = crtc->plane;
7630 int fourcc, pixel_format;
7631 unsigned int aligned_height;
7632 struct drm_framebuffer *fb;
7633 struct intel_framebuffer *intel_fb;
7634
7635 val = I915_READ(DSPCNTR(plane));
7636 if (!(val & DISPLAY_PLANE_ENABLE))
7637 return;
7638
7639 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7640 if (!intel_fb) {
7641 DRM_DEBUG_KMS("failed to alloc fb\n");
7642 return;
7643 }
7644
7645 fb = &intel_fb->base;
7646
7647 if (INTEL_INFO(dev)->gen >= 4) {
7648 if (val & DISPPLANE_TILED) {
7649 plane_config->tiling = I915_TILING_X;
7650 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7651 }
7652 }
7653
7654 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7655 fourcc = i9xx_format_to_fourcc(pixel_format);
7656 fb->pixel_format = fourcc;
7657 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7658
7659 if (INTEL_INFO(dev)->gen >= 4) {
7660 if (plane_config->tiling)
7661 offset = I915_READ(DSPTILEOFF(plane));
7662 else
7663 offset = I915_READ(DSPLINOFF(plane));
7664 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7665 } else {
7666 base = I915_READ(DSPADDR(plane));
7667 }
7668 plane_config->base = base;
7669
7670 val = I915_READ(PIPESRC(pipe));
7671 fb->width = ((val >> 16) & 0xfff) + 1;
7672 fb->height = ((val >> 0) & 0xfff) + 1;
7673
7674 val = I915_READ(DSPSTRIDE(pipe));
7675 fb->pitches[0] = val & 0xffffffc0;
7676
7677 aligned_height = intel_fb_align_height(dev, fb->height,
7678 fb->pixel_format,
7679 fb->modifier[0]);
7680
7681 plane_config->size = fb->pitches[0] * aligned_height;
7682
7683 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7684 pipe_name(pipe), plane, fb->width, fb->height,
7685 fb->bits_per_pixel, base, fb->pitches[0],
7686 plane_config->size);
7687
7688 plane_config->fb = intel_fb;
7689 }
7690
7691 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7692 struct intel_crtc_state *pipe_config)
7693 {
7694 struct drm_device *dev = crtc->base.dev;
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 int pipe = pipe_config->cpu_transcoder;
7697 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7698 intel_clock_t clock;
7699 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7700 int refclk = 100000;
7701
7702 mutex_lock(&dev_priv->dpio_lock);
7703 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7704 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7705 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7706 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7707 mutex_unlock(&dev_priv->dpio_lock);
7708
7709 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7710 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7711 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7712 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7713 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7714
7715 chv_clock(refclk, &clock);
7716
7717 /* clock.dot is the fast clock */
7718 pipe_config->port_clock = clock.dot / 5;
7719 }
7720
7721 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7722 struct intel_crtc_state *pipe_config)
7723 {
7724 struct drm_device *dev = crtc->base.dev;
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726 uint32_t tmp;
7727
7728 if (!intel_display_power_is_enabled(dev_priv,
7729 POWER_DOMAIN_PIPE(crtc->pipe)))
7730 return false;
7731
7732 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7733 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7734
7735 tmp = I915_READ(PIPECONF(crtc->pipe));
7736 if (!(tmp & PIPECONF_ENABLE))
7737 return false;
7738
7739 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7740 switch (tmp & PIPECONF_BPC_MASK) {
7741 case PIPECONF_6BPC:
7742 pipe_config->pipe_bpp = 18;
7743 break;
7744 case PIPECONF_8BPC:
7745 pipe_config->pipe_bpp = 24;
7746 break;
7747 case PIPECONF_10BPC:
7748 pipe_config->pipe_bpp = 30;
7749 break;
7750 default:
7751 break;
7752 }
7753 }
7754
7755 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7756 pipe_config->limited_color_range = true;
7757
7758 if (INTEL_INFO(dev)->gen < 4)
7759 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7760
7761 intel_get_pipe_timings(crtc, pipe_config);
7762
7763 i9xx_get_pfit_config(crtc, pipe_config);
7764
7765 if (INTEL_INFO(dev)->gen >= 4) {
7766 tmp = I915_READ(DPLL_MD(crtc->pipe));
7767 pipe_config->pixel_multiplier =
7768 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7769 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7770 pipe_config->dpll_hw_state.dpll_md = tmp;
7771 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7772 tmp = I915_READ(DPLL(crtc->pipe));
7773 pipe_config->pixel_multiplier =
7774 ((tmp & SDVO_MULTIPLIER_MASK)
7775 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7776 } else {
7777 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7778 * port and will be fixed up in the encoder->get_config
7779 * function. */
7780 pipe_config->pixel_multiplier = 1;
7781 }
7782 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7783 if (!IS_VALLEYVIEW(dev)) {
7784 /*
7785 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7786 * on 830. Filter it out here so that we don't
7787 * report errors due to that.
7788 */
7789 if (IS_I830(dev))
7790 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7791
7792 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7793 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7794 } else {
7795 /* Mask out read-only status bits. */
7796 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7797 DPLL_PORTC_READY_MASK |
7798 DPLL_PORTB_READY_MASK);
7799 }
7800
7801 if (IS_CHERRYVIEW(dev))
7802 chv_crtc_clock_get(crtc, pipe_config);
7803 else if (IS_VALLEYVIEW(dev))
7804 vlv_crtc_clock_get(crtc, pipe_config);
7805 else
7806 i9xx_crtc_clock_get(crtc, pipe_config);
7807
7808 return true;
7809 }
7810
7811 static void ironlake_init_pch_refclk(struct drm_device *dev)
7812 {
7813 struct drm_i915_private *dev_priv = dev->dev_private;
7814 struct intel_encoder *encoder;
7815 u32 val, final;
7816 bool has_lvds = false;
7817 bool has_cpu_edp = false;
7818 bool has_panel = false;
7819 bool has_ck505 = false;
7820 bool can_ssc = false;
7821
7822 /* We need to take the global config into account */
7823 for_each_intel_encoder(dev, encoder) {
7824 switch (encoder->type) {
7825 case INTEL_OUTPUT_LVDS:
7826 has_panel = true;
7827 has_lvds = true;
7828 break;
7829 case INTEL_OUTPUT_EDP:
7830 has_panel = true;
7831 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7832 has_cpu_edp = true;
7833 break;
7834 default:
7835 break;
7836 }
7837 }
7838
7839 if (HAS_PCH_IBX(dev)) {
7840 has_ck505 = dev_priv->vbt.display_clock_mode;
7841 can_ssc = has_ck505;
7842 } else {
7843 has_ck505 = false;
7844 can_ssc = true;
7845 }
7846
7847 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7848 has_panel, has_lvds, has_ck505);
7849
7850 /* Ironlake: try to setup display ref clock before DPLL
7851 * enabling. This is only under driver's control after
7852 * PCH B stepping, previous chipset stepping should be
7853 * ignoring this setting.
7854 */
7855 val = I915_READ(PCH_DREF_CONTROL);
7856
7857 /* As we must carefully and slowly disable/enable each source in turn,
7858 * compute the final state we want first and check if we need to
7859 * make any changes at all.
7860 */
7861 final = val;
7862 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7863 if (has_ck505)
7864 final |= DREF_NONSPREAD_CK505_ENABLE;
7865 else
7866 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7867
7868 final &= ~DREF_SSC_SOURCE_MASK;
7869 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7870 final &= ~DREF_SSC1_ENABLE;
7871
7872 if (has_panel) {
7873 final |= DREF_SSC_SOURCE_ENABLE;
7874
7875 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7876 final |= DREF_SSC1_ENABLE;
7877
7878 if (has_cpu_edp) {
7879 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7880 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7881 else
7882 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7883 } else
7884 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7885 } else {
7886 final |= DREF_SSC_SOURCE_DISABLE;
7887 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7888 }
7889
7890 if (final == val)
7891 return;
7892
7893 /* Always enable nonspread source */
7894 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7895
7896 if (has_ck505)
7897 val |= DREF_NONSPREAD_CK505_ENABLE;
7898 else
7899 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7900
7901 if (has_panel) {
7902 val &= ~DREF_SSC_SOURCE_MASK;
7903 val |= DREF_SSC_SOURCE_ENABLE;
7904
7905 /* SSC must be turned on before enabling the CPU output */
7906 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7907 DRM_DEBUG_KMS("Using SSC on panel\n");
7908 val |= DREF_SSC1_ENABLE;
7909 } else
7910 val &= ~DREF_SSC1_ENABLE;
7911
7912 /* Get SSC going before enabling the outputs */
7913 I915_WRITE(PCH_DREF_CONTROL, val);
7914 POSTING_READ(PCH_DREF_CONTROL);
7915 udelay(200);
7916
7917 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7918
7919 /* Enable CPU source on CPU attached eDP */
7920 if (has_cpu_edp) {
7921 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7922 DRM_DEBUG_KMS("Using SSC on eDP\n");
7923 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7924 } else
7925 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7926 } else
7927 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7928
7929 I915_WRITE(PCH_DREF_CONTROL, val);
7930 POSTING_READ(PCH_DREF_CONTROL);
7931 udelay(200);
7932 } else {
7933 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7934
7935 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7936
7937 /* Turn off CPU output */
7938 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7939
7940 I915_WRITE(PCH_DREF_CONTROL, val);
7941 POSTING_READ(PCH_DREF_CONTROL);
7942 udelay(200);
7943
7944 /* Turn off the SSC source */
7945 val &= ~DREF_SSC_SOURCE_MASK;
7946 val |= DREF_SSC_SOURCE_DISABLE;
7947
7948 /* Turn off SSC1 */
7949 val &= ~DREF_SSC1_ENABLE;
7950
7951 I915_WRITE(PCH_DREF_CONTROL, val);
7952 POSTING_READ(PCH_DREF_CONTROL);
7953 udelay(200);
7954 }
7955
7956 BUG_ON(val != final);
7957 }
7958
7959 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7960 {
7961 uint32_t tmp;
7962
7963 tmp = I915_READ(SOUTH_CHICKEN2);
7964 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7965 I915_WRITE(SOUTH_CHICKEN2, tmp);
7966
7967 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7968 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7969 DRM_ERROR("FDI mPHY reset assert timeout\n");
7970
7971 tmp = I915_READ(SOUTH_CHICKEN2);
7972 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7973 I915_WRITE(SOUTH_CHICKEN2, tmp);
7974
7975 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7976 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7977 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7978 }
7979
7980 /* WaMPhyProgramming:hsw */
7981 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7982 {
7983 uint32_t tmp;
7984
7985 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7986 tmp &= ~(0xFF << 24);
7987 tmp |= (0x12 << 24);
7988 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7989
7990 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7991 tmp |= (1 << 11);
7992 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7993
7994 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7995 tmp |= (1 << 11);
7996 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7997
7998 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7999 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8000 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8001
8002 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8003 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8004 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8005
8006 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8007 tmp &= ~(7 << 13);
8008 tmp |= (5 << 13);
8009 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8010
8011 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8012 tmp &= ~(7 << 13);
8013 tmp |= (5 << 13);
8014 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8015
8016 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8017 tmp &= ~0xFF;
8018 tmp |= 0x1C;
8019 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8020
8021 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8022 tmp &= ~0xFF;
8023 tmp |= 0x1C;
8024 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8025
8026 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8027 tmp &= ~(0xFF << 16);
8028 tmp |= (0x1C << 16);
8029 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8030
8031 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8032 tmp &= ~(0xFF << 16);
8033 tmp |= (0x1C << 16);
8034 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8035
8036 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8037 tmp |= (1 << 27);
8038 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8039
8040 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8041 tmp |= (1 << 27);
8042 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8043
8044 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8045 tmp &= ~(0xF << 28);
8046 tmp |= (4 << 28);
8047 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8048
8049 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8050 tmp &= ~(0xF << 28);
8051 tmp |= (4 << 28);
8052 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8053 }
8054
8055 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8056 * Programming" based on the parameters passed:
8057 * - Sequence to enable CLKOUT_DP
8058 * - Sequence to enable CLKOUT_DP without spread
8059 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8060 */
8061 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8062 bool with_fdi)
8063 {
8064 struct drm_i915_private *dev_priv = dev->dev_private;
8065 uint32_t reg, tmp;
8066
8067 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8068 with_spread = true;
8069 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8070 with_fdi, "LP PCH doesn't have FDI\n"))
8071 with_fdi = false;
8072
8073 mutex_lock(&dev_priv->dpio_lock);
8074
8075 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8076 tmp &= ~SBI_SSCCTL_DISABLE;
8077 tmp |= SBI_SSCCTL_PATHALT;
8078 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8079
8080 udelay(24);
8081
8082 if (with_spread) {
8083 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8084 tmp &= ~SBI_SSCCTL_PATHALT;
8085 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8086
8087 if (with_fdi) {
8088 lpt_reset_fdi_mphy(dev_priv);
8089 lpt_program_fdi_mphy(dev_priv);
8090 }
8091 }
8092
8093 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8094 SBI_GEN0 : SBI_DBUFF0;
8095 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8096 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8097 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8098
8099 mutex_unlock(&dev_priv->dpio_lock);
8100 }
8101
8102 /* Sequence to disable CLKOUT_DP */
8103 static void lpt_disable_clkout_dp(struct drm_device *dev)
8104 {
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8106 uint32_t reg, tmp;
8107
8108 mutex_lock(&dev_priv->dpio_lock);
8109
8110 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8111 SBI_GEN0 : SBI_DBUFF0;
8112 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8113 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8114 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8115
8116 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8117 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8118 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8119 tmp |= SBI_SSCCTL_PATHALT;
8120 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8121 udelay(32);
8122 }
8123 tmp |= SBI_SSCCTL_DISABLE;
8124 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8125 }
8126
8127 mutex_unlock(&dev_priv->dpio_lock);
8128 }
8129
8130 static void lpt_init_pch_refclk(struct drm_device *dev)
8131 {
8132 struct intel_encoder *encoder;
8133 bool has_vga = false;
8134
8135 for_each_intel_encoder(dev, encoder) {
8136 switch (encoder->type) {
8137 case INTEL_OUTPUT_ANALOG:
8138 has_vga = true;
8139 break;
8140 default:
8141 break;
8142 }
8143 }
8144
8145 if (has_vga)
8146 lpt_enable_clkout_dp(dev, true, true);
8147 else
8148 lpt_disable_clkout_dp(dev);
8149 }
8150
8151 /*
8152 * Initialize reference clocks when the driver loads
8153 */
8154 void intel_init_pch_refclk(struct drm_device *dev)
8155 {
8156 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8157 ironlake_init_pch_refclk(dev);
8158 else if (HAS_PCH_LPT(dev))
8159 lpt_init_pch_refclk(dev);
8160 }
8161
8162 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8163 {
8164 struct drm_device *dev = crtc_state->base.crtc->dev;
8165 struct drm_i915_private *dev_priv = dev->dev_private;
8166 struct drm_atomic_state *state = crtc_state->base.state;
8167 struct drm_connector *connector;
8168 struct drm_connector_state *connector_state;
8169 struct intel_encoder *encoder;
8170 int num_connectors = 0, i;
8171 bool is_lvds = false;
8172
8173 for_each_connector_in_state(state, connector, connector_state, i) {
8174 if (connector_state->crtc != crtc_state->base.crtc)
8175 continue;
8176
8177 encoder = to_intel_encoder(connector_state->best_encoder);
8178
8179 switch (encoder->type) {
8180 case INTEL_OUTPUT_LVDS:
8181 is_lvds = true;
8182 break;
8183 default:
8184 break;
8185 }
8186 num_connectors++;
8187 }
8188
8189 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8190 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8191 dev_priv->vbt.lvds_ssc_freq);
8192 return dev_priv->vbt.lvds_ssc_freq;
8193 }
8194
8195 return 120000;
8196 }
8197
8198 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8199 {
8200 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8202 int pipe = intel_crtc->pipe;
8203 uint32_t val;
8204
8205 val = 0;
8206
8207 switch (intel_crtc->config->pipe_bpp) {
8208 case 18:
8209 val |= PIPECONF_6BPC;
8210 break;
8211 case 24:
8212 val |= PIPECONF_8BPC;
8213 break;
8214 case 30:
8215 val |= PIPECONF_10BPC;
8216 break;
8217 case 36:
8218 val |= PIPECONF_12BPC;
8219 break;
8220 default:
8221 /* Case prevented by intel_choose_pipe_bpp_dither. */
8222 BUG();
8223 }
8224
8225 if (intel_crtc->config->dither)
8226 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8227
8228 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8229 val |= PIPECONF_INTERLACED_ILK;
8230 else
8231 val |= PIPECONF_PROGRESSIVE;
8232
8233 if (intel_crtc->config->limited_color_range)
8234 val |= PIPECONF_COLOR_RANGE_SELECT;
8235
8236 I915_WRITE(PIPECONF(pipe), val);
8237 POSTING_READ(PIPECONF(pipe));
8238 }
8239
8240 /*
8241 * Set up the pipe CSC unit.
8242 *
8243 * Currently only full range RGB to limited range RGB conversion
8244 * is supported, but eventually this should handle various
8245 * RGB<->YCbCr scenarios as well.
8246 */
8247 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8248 {
8249 struct drm_device *dev = crtc->dev;
8250 struct drm_i915_private *dev_priv = dev->dev_private;
8251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8252 int pipe = intel_crtc->pipe;
8253 uint16_t coeff = 0x7800; /* 1.0 */
8254
8255 /*
8256 * TODO: Check what kind of values actually come out of the pipe
8257 * with these coeff/postoff values and adjust to get the best
8258 * accuracy. Perhaps we even need to take the bpc value into
8259 * consideration.
8260 */
8261
8262 if (intel_crtc->config->limited_color_range)
8263 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8264
8265 /*
8266 * GY/GU and RY/RU should be the other way around according
8267 * to BSpec, but reality doesn't agree. Just set them up in
8268 * a way that results in the correct picture.
8269 */
8270 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8271 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8272
8273 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8274 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8275
8276 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8277 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8278
8279 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8280 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8281 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8282
8283 if (INTEL_INFO(dev)->gen > 6) {
8284 uint16_t postoff = 0;
8285
8286 if (intel_crtc->config->limited_color_range)
8287 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8288
8289 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8290 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8291 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8292
8293 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8294 } else {
8295 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8296
8297 if (intel_crtc->config->limited_color_range)
8298 mode |= CSC_BLACK_SCREEN_OFFSET;
8299
8300 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8301 }
8302 }
8303
8304 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8305 {
8306 struct drm_device *dev = crtc->dev;
8307 struct drm_i915_private *dev_priv = dev->dev_private;
8308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8309 enum pipe pipe = intel_crtc->pipe;
8310 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8311 uint32_t val;
8312
8313 val = 0;
8314
8315 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8316 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8317
8318 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8319 val |= PIPECONF_INTERLACED_ILK;
8320 else
8321 val |= PIPECONF_PROGRESSIVE;
8322
8323 I915_WRITE(PIPECONF(cpu_transcoder), val);
8324 POSTING_READ(PIPECONF(cpu_transcoder));
8325
8326 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8327 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8328
8329 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8330 val = 0;
8331
8332 switch (intel_crtc->config->pipe_bpp) {
8333 case 18:
8334 val |= PIPEMISC_DITHER_6_BPC;
8335 break;
8336 case 24:
8337 val |= PIPEMISC_DITHER_8_BPC;
8338 break;
8339 case 30:
8340 val |= PIPEMISC_DITHER_10_BPC;
8341 break;
8342 case 36:
8343 val |= PIPEMISC_DITHER_12_BPC;
8344 break;
8345 default:
8346 /* Case prevented by pipe_config_set_bpp. */
8347 BUG();
8348 }
8349
8350 if (intel_crtc->config->dither)
8351 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8352
8353 I915_WRITE(PIPEMISC(pipe), val);
8354 }
8355 }
8356
8357 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8358 struct intel_crtc_state *crtc_state,
8359 intel_clock_t *clock,
8360 bool *has_reduced_clock,
8361 intel_clock_t *reduced_clock)
8362 {
8363 struct drm_device *dev = crtc->dev;
8364 struct drm_i915_private *dev_priv = dev->dev_private;
8365 int refclk;
8366 const intel_limit_t *limit;
8367 bool ret, is_lvds = false;
8368
8369 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8370
8371 refclk = ironlake_get_refclk(crtc_state);
8372
8373 /*
8374 * Returns a set of divisors for the desired target clock with the given
8375 * refclk, or FALSE. The returned values represent the clock equation:
8376 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8377 */
8378 limit = intel_limit(crtc_state, refclk);
8379 ret = dev_priv->display.find_dpll(limit, crtc_state,
8380 crtc_state->port_clock,
8381 refclk, NULL, clock);
8382 if (!ret)
8383 return false;
8384
8385 if (is_lvds && dev_priv->lvds_downclock_avail) {
8386 /*
8387 * Ensure we match the reduced clock's P to the target clock.
8388 * If the clocks don't match, we can't switch the display clock
8389 * by using the FP0/FP1. In such case we will disable the LVDS
8390 * downclock feature.
8391 */
8392 *has_reduced_clock =
8393 dev_priv->display.find_dpll(limit, crtc_state,
8394 dev_priv->lvds_downclock,
8395 refclk, clock,
8396 reduced_clock);
8397 }
8398
8399 return true;
8400 }
8401
8402 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8403 {
8404 /*
8405 * Account for spread spectrum to avoid
8406 * oversubscribing the link. Max center spread
8407 * is 2.5%; use 5% for safety's sake.
8408 */
8409 u32 bps = target_clock * bpp * 21 / 20;
8410 return DIV_ROUND_UP(bps, link_bw * 8);
8411 }
8412
8413 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8414 {
8415 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8416 }
8417
8418 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8419 struct intel_crtc_state *crtc_state,
8420 u32 *fp,
8421 intel_clock_t *reduced_clock, u32 *fp2)
8422 {
8423 struct drm_crtc *crtc = &intel_crtc->base;
8424 struct drm_device *dev = crtc->dev;
8425 struct drm_i915_private *dev_priv = dev->dev_private;
8426 struct drm_atomic_state *state = crtc_state->base.state;
8427 struct drm_connector *connector;
8428 struct drm_connector_state *connector_state;
8429 struct intel_encoder *encoder;
8430 uint32_t dpll;
8431 int factor, num_connectors = 0, i;
8432 bool is_lvds = false, is_sdvo = false;
8433
8434 for_each_connector_in_state(state, connector, connector_state, i) {
8435 if (connector_state->crtc != crtc_state->base.crtc)
8436 continue;
8437
8438 encoder = to_intel_encoder(connector_state->best_encoder);
8439
8440 switch (encoder->type) {
8441 case INTEL_OUTPUT_LVDS:
8442 is_lvds = true;
8443 break;
8444 case INTEL_OUTPUT_SDVO:
8445 case INTEL_OUTPUT_HDMI:
8446 is_sdvo = true;
8447 break;
8448 default:
8449 break;
8450 }
8451
8452 num_connectors++;
8453 }
8454
8455 /* Enable autotuning of the PLL clock (if permissible) */
8456 factor = 21;
8457 if (is_lvds) {
8458 if ((intel_panel_use_ssc(dev_priv) &&
8459 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8460 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8461 factor = 25;
8462 } else if (crtc_state->sdvo_tv_clock)
8463 factor = 20;
8464
8465 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8466 *fp |= FP_CB_TUNE;
8467
8468 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8469 *fp2 |= FP_CB_TUNE;
8470
8471 dpll = 0;
8472
8473 if (is_lvds)
8474 dpll |= DPLLB_MODE_LVDS;
8475 else
8476 dpll |= DPLLB_MODE_DAC_SERIAL;
8477
8478 dpll |= (crtc_state->pixel_multiplier - 1)
8479 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8480
8481 if (is_sdvo)
8482 dpll |= DPLL_SDVO_HIGH_SPEED;
8483 if (crtc_state->has_dp_encoder)
8484 dpll |= DPLL_SDVO_HIGH_SPEED;
8485
8486 /* compute bitmask from p1 value */
8487 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8488 /* also FPA1 */
8489 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8490
8491 switch (crtc_state->dpll.p2) {
8492 case 5:
8493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8494 break;
8495 case 7:
8496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8497 break;
8498 case 10:
8499 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8500 break;
8501 case 14:
8502 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8503 break;
8504 }
8505
8506 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8507 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8508 else
8509 dpll |= PLL_REF_INPUT_DREFCLK;
8510
8511 return dpll | DPLL_VCO_ENABLE;
8512 }
8513
8514 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8515 struct intel_crtc_state *crtc_state)
8516 {
8517 struct drm_device *dev = crtc->base.dev;
8518 intel_clock_t clock, reduced_clock;
8519 u32 dpll = 0, fp = 0, fp2 = 0;
8520 bool ok, has_reduced_clock = false;
8521 bool is_lvds = false;
8522 struct intel_shared_dpll *pll;
8523
8524 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8525
8526 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8527 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8528
8529 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8530 &has_reduced_clock, &reduced_clock);
8531 if (!ok && !crtc_state->clock_set) {
8532 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8533 return -EINVAL;
8534 }
8535 /* Compat-code for transition, will disappear. */
8536 if (!crtc_state->clock_set) {
8537 crtc_state->dpll.n = clock.n;
8538 crtc_state->dpll.m1 = clock.m1;
8539 crtc_state->dpll.m2 = clock.m2;
8540 crtc_state->dpll.p1 = clock.p1;
8541 crtc_state->dpll.p2 = clock.p2;
8542 }
8543
8544 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8545 if (crtc_state->has_pch_encoder) {
8546 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8547 if (has_reduced_clock)
8548 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8549
8550 dpll = ironlake_compute_dpll(crtc, crtc_state,
8551 &fp, &reduced_clock,
8552 has_reduced_clock ? &fp2 : NULL);
8553
8554 crtc_state->dpll_hw_state.dpll = dpll;
8555 crtc_state->dpll_hw_state.fp0 = fp;
8556 if (has_reduced_clock)
8557 crtc_state->dpll_hw_state.fp1 = fp2;
8558 else
8559 crtc_state->dpll_hw_state.fp1 = fp;
8560
8561 pll = intel_get_shared_dpll(crtc, crtc_state);
8562 if (pll == NULL) {
8563 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8564 pipe_name(crtc->pipe));
8565 return -EINVAL;
8566 }
8567 }
8568
8569 if (is_lvds && has_reduced_clock)
8570 crtc->lowfreq_avail = true;
8571 else
8572 crtc->lowfreq_avail = false;
8573
8574 return 0;
8575 }
8576
8577 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8578 struct intel_link_m_n *m_n)
8579 {
8580 struct drm_device *dev = crtc->base.dev;
8581 struct drm_i915_private *dev_priv = dev->dev_private;
8582 enum pipe pipe = crtc->pipe;
8583
8584 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8585 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8586 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8587 & ~TU_SIZE_MASK;
8588 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8589 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8590 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8591 }
8592
8593 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8594 enum transcoder transcoder,
8595 struct intel_link_m_n *m_n,
8596 struct intel_link_m_n *m2_n2)
8597 {
8598 struct drm_device *dev = crtc->base.dev;
8599 struct drm_i915_private *dev_priv = dev->dev_private;
8600 enum pipe pipe = crtc->pipe;
8601
8602 if (INTEL_INFO(dev)->gen >= 5) {
8603 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8604 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8605 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8606 & ~TU_SIZE_MASK;
8607 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8608 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8609 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8610 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8611 * gen < 8) and if DRRS is supported (to make sure the
8612 * registers are not unnecessarily read).
8613 */
8614 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8615 crtc->config->has_drrs) {
8616 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8617 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8618 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8619 & ~TU_SIZE_MASK;
8620 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8621 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8622 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8623 }
8624 } else {
8625 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8626 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8627 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8628 & ~TU_SIZE_MASK;
8629 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8630 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8631 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8632 }
8633 }
8634
8635 void intel_dp_get_m_n(struct intel_crtc *crtc,
8636 struct intel_crtc_state *pipe_config)
8637 {
8638 if (pipe_config->has_pch_encoder)
8639 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8640 else
8641 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8642 &pipe_config->dp_m_n,
8643 &pipe_config->dp_m2_n2);
8644 }
8645
8646 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8647 struct intel_crtc_state *pipe_config)
8648 {
8649 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8650 &pipe_config->fdi_m_n, NULL);
8651 }
8652
8653 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8654 struct intel_crtc_state *pipe_config)
8655 {
8656 struct drm_device *dev = crtc->base.dev;
8657 struct drm_i915_private *dev_priv = dev->dev_private;
8658 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8659 uint32_t ps_ctrl = 0;
8660 int id = -1;
8661 int i;
8662
8663 /* find scaler attached to this pipe */
8664 for (i = 0; i < crtc->num_scalers; i++) {
8665 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8666 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8667 id = i;
8668 pipe_config->pch_pfit.enabled = true;
8669 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8670 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8671 break;
8672 }
8673 }
8674
8675 scaler_state->scaler_id = id;
8676 if (id >= 0) {
8677 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8678 } else {
8679 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8680 }
8681 }
8682
8683 static void
8684 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8685 struct intel_initial_plane_config *plane_config)
8686 {
8687 struct drm_device *dev = crtc->base.dev;
8688 struct drm_i915_private *dev_priv = dev->dev_private;
8689 u32 val, base, offset, stride_mult, tiling;
8690 int pipe = crtc->pipe;
8691 int fourcc, pixel_format;
8692 unsigned int aligned_height;
8693 struct drm_framebuffer *fb;
8694 struct intel_framebuffer *intel_fb;
8695
8696 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8697 if (!intel_fb) {
8698 DRM_DEBUG_KMS("failed to alloc fb\n");
8699 return;
8700 }
8701
8702 fb = &intel_fb->base;
8703
8704 val = I915_READ(PLANE_CTL(pipe, 0));
8705 if (!(val & PLANE_CTL_ENABLE))
8706 goto error;
8707
8708 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8709 fourcc = skl_format_to_fourcc(pixel_format,
8710 val & PLANE_CTL_ORDER_RGBX,
8711 val & PLANE_CTL_ALPHA_MASK);
8712 fb->pixel_format = fourcc;
8713 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8714
8715 tiling = val & PLANE_CTL_TILED_MASK;
8716 switch (tiling) {
8717 case PLANE_CTL_TILED_LINEAR:
8718 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8719 break;
8720 case PLANE_CTL_TILED_X:
8721 plane_config->tiling = I915_TILING_X;
8722 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8723 break;
8724 case PLANE_CTL_TILED_Y:
8725 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8726 break;
8727 case PLANE_CTL_TILED_YF:
8728 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8729 break;
8730 default:
8731 MISSING_CASE(tiling);
8732 goto error;
8733 }
8734
8735 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8736 plane_config->base = base;
8737
8738 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8739
8740 val = I915_READ(PLANE_SIZE(pipe, 0));
8741 fb->height = ((val >> 16) & 0xfff) + 1;
8742 fb->width = ((val >> 0) & 0x1fff) + 1;
8743
8744 val = I915_READ(PLANE_STRIDE(pipe, 0));
8745 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8746 fb->pixel_format);
8747 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8748
8749 aligned_height = intel_fb_align_height(dev, fb->height,
8750 fb->pixel_format,
8751 fb->modifier[0]);
8752
8753 plane_config->size = fb->pitches[0] * aligned_height;
8754
8755 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8756 pipe_name(pipe), fb->width, fb->height,
8757 fb->bits_per_pixel, base, fb->pitches[0],
8758 plane_config->size);
8759
8760 plane_config->fb = intel_fb;
8761 return;
8762
8763 error:
8764 kfree(fb);
8765 }
8766
8767 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8768 struct intel_crtc_state *pipe_config)
8769 {
8770 struct drm_device *dev = crtc->base.dev;
8771 struct drm_i915_private *dev_priv = dev->dev_private;
8772 uint32_t tmp;
8773
8774 tmp = I915_READ(PF_CTL(crtc->pipe));
8775
8776 if (tmp & PF_ENABLE) {
8777 pipe_config->pch_pfit.enabled = true;
8778 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8779 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8780
8781 /* We currently do not free assignements of panel fitters on
8782 * ivb/hsw (since we don't use the higher upscaling modes which
8783 * differentiates them) so just WARN about this case for now. */
8784 if (IS_GEN7(dev)) {
8785 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8786 PF_PIPE_SEL_IVB(crtc->pipe));
8787 }
8788 }
8789 }
8790
8791 static void
8792 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8793 struct intel_initial_plane_config *plane_config)
8794 {
8795 struct drm_device *dev = crtc->base.dev;
8796 struct drm_i915_private *dev_priv = dev->dev_private;
8797 u32 val, base, offset;
8798 int pipe = crtc->pipe;
8799 int fourcc, pixel_format;
8800 unsigned int aligned_height;
8801 struct drm_framebuffer *fb;
8802 struct intel_framebuffer *intel_fb;
8803
8804 val = I915_READ(DSPCNTR(pipe));
8805 if (!(val & DISPLAY_PLANE_ENABLE))
8806 return;
8807
8808 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8809 if (!intel_fb) {
8810 DRM_DEBUG_KMS("failed to alloc fb\n");
8811 return;
8812 }
8813
8814 fb = &intel_fb->base;
8815
8816 if (INTEL_INFO(dev)->gen >= 4) {
8817 if (val & DISPPLANE_TILED) {
8818 plane_config->tiling = I915_TILING_X;
8819 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8820 }
8821 }
8822
8823 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8824 fourcc = i9xx_format_to_fourcc(pixel_format);
8825 fb->pixel_format = fourcc;
8826 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8827
8828 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8829 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8830 offset = I915_READ(DSPOFFSET(pipe));
8831 } else {
8832 if (plane_config->tiling)
8833 offset = I915_READ(DSPTILEOFF(pipe));
8834 else
8835 offset = I915_READ(DSPLINOFF(pipe));
8836 }
8837 plane_config->base = base;
8838
8839 val = I915_READ(PIPESRC(pipe));
8840 fb->width = ((val >> 16) & 0xfff) + 1;
8841 fb->height = ((val >> 0) & 0xfff) + 1;
8842
8843 val = I915_READ(DSPSTRIDE(pipe));
8844 fb->pitches[0] = val & 0xffffffc0;
8845
8846 aligned_height = intel_fb_align_height(dev, fb->height,
8847 fb->pixel_format,
8848 fb->modifier[0]);
8849
8850 plane_config->size = fb->pitches[0] * aligned_height;
8851
8852 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8853 pipe_name(pipe), fb->width, fb->height,
8854 fb->bits_per_pixel, base, fb->pitches[0],
8855 plane_config->size);
8856
8857 plane_config->fb = intel_fb;
8858 }
8859
8860 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8861 struct intel_crtc_state *pipe_config)
8862 {
8863 struct drm_device *dev = crtc->base.dev;
8864 struct drm_i915_private *dev_priv = dev->dev_private;
8865 uint32_t tmp;
8866
8867 if (!intel_display_power_is_enabled(dev_priv,
8868 POWER_DOMAIN_PIPE(crtc->pipe)))
8869 return false;
8870
8871 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8872 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8873
8874 tmp = I915_READ(PIPECONF(crtc->pipe));
8875 if (!(tmp & PIPECONF_ENABLE))
8876 return false;
8877
8878 switch (tmp & PIPECONF_BPC_MASK) {
8879 case PIPECONF_6BPC:
8880 pipe_config->pipe_bpp = 18;
8881 break;
8882 case PIPECONF_8BPC:
8883 pipe_config->pipe_bpp = 24;
8884 break;
8885 case PIPECONF_10BPC:
8886 pipe_config->pipe_bpp = 30;
8887 break;
8888 case PIPECONF_12BPC:
8889 pipe_config->pipe_bpp = 36;
8890 break;
8891 default:
8892 break;
8893 }
8894
8895 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8896 pipe_config->limited_color_range = true;
8897
8898 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8899 struct intel_shared_dpll *pll;
8900
8901 pipe_config->has_pch_encoder = true;
8902
8903 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8904 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8905 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8906
8907 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8908
8909 if (HAS_PCH_IBX(dev_priv->dev)) {
8910 pipe_config->shared_dpll =
8911 (enum intel_dpll_id) crtc->pipe;
8912 } else {
8913 tmp = I915_READ(PCH_DPLL_SEL);
8914 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8915 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8916 else
8917 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8918 }
8919
8920 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8921
8922 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8923 &pipe_config->dpll_hw_state));
8924
8925 tmp = pipe_config->dpll_hw_state.dpll;
8926 pipe_config->pixel_multiplier =
8927 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8928 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8929
8930 ironlake_pch_clock_get(crtc, pipe_config);
8931 } else {
8932 pipe_config->pixel_multiplier = 1;
8933 }
8934
8935 intel_get_pipe_timings(crtc, pipe_config);
8936
8937 ironlake_get_pfit_config(crtc, pipe_config);
8938
8939 return true;
8940 }
8941
8942 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8943 {
8944 struct drm_device *dev = dev_priv->dev;
8945 struct intel_crtc *crtc;
8946
8947 for_each_intel_crtc(dev, crtc)
8948 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8949 pipe_name(crtc->pipe));
8950
8951 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8952 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8953 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8954 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8955 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8956 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8957 "CPU PWM1 enabled\n");
8958 if (IS_HASWELL(dev))
8959 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8960 "CPU PWM2 enabled\n");
8961 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8962 "PCH PWM1 enabled\n");
8963 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8964 "Utility pin enabled\n");
8965 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8966
8967 /*
8968 * In theory we can still leave IRQs enabled, as long as only the HPD
8969 * interrupts remain enabled. We used to check for that, but since it's
8970 * gen-specific and since we only disable LCPLL after we fully disable
8971 * the interrupts, the check below should be enough.
8972 */
8973 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8974 }
8975
8976 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8977 {
8978 struct drm_device *dev = dev_priv->dev;
8979
8980 if (IS_HASWELL(dev))
8981 return I915_READ(D_COMP_HSW);
8982 else
8983 return I915_READ(D_COMP_BDW);
8984 }
8985
8986 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8987 {
8988 struct drm_device *dev = dev_priv->dev;
8989
8990 if (IS_HASWELL(dev)) {
8991 mutex_lock(&dev_priv->rps.hw_lock);
8992 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8993 val))
8994 DRM_ERROR("Failed to write to D_COMP\n");
8995 mutex_unlock(&dev_priv->rps.hw_lock);
8996 } else {
8997 I915_WRITE(D_COMP_BDW, val);
8998 POSTING_READ(D_COMP_BDW);
8999 }
9000 }
9001
9002 /*
9003 * This function implements pieces of two sequences from BSpec:
9004 * - Sequence for display software to disable LCPLL
9005 * - Sequence for display software to allow package C8+
9006 * The steps implemented here are just the steps that actually touch the LCPLL
9007 * register. Callers should take care of disabling all the display engine
9008 * functions, doing the mode unset, fixing interrupts, etc.
9009 */
9010 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9011 bool switch_to_fclk, bool allow_power_down)
9012 {
9013 uint32_t val;
9014
9015 assert_can_disable_lcpll(dev_priv);
9016
9017 val = I915_READ(LCPLL_CTL);
9018
9019 if (switch_to_fclk) {
9020 val |= LCPLL_CD_SOURCE_FCLK;
9021 I915_WRITE(LCPLL_CTL, val);
9022
9023 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9024 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9025 DRM_ERROR("Switching to FCLK failed\n");
9026
9027 val = I915_READ(LCPLL_CTL);
9028 }
9029
9030 val |= LCPLL_PLL_DISABLE;
9031 I915_WRITE(LCPLL_CTL, val);
9032 POSTING_READ(LCPLL_CTL);
9033
9034 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9035 DRM_ERROR("LCPLL still locked\n");
9036
9037 val = hsw_read_dcomp(dev_priv);
9038 val |= D_COMP_COMP_DISABLE;
9039 hsw_write_dcomp(dev_priv, val);
9040 ndelay(100);
9041
9042 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9043 1))
9044 DRM_ERROR("D_COMP RCOMP still in progress\n");
9045
9046 if (allow_power_down) {
9047 val = I915_READ(LCPLL_CTL);
9048 val |= LCPLL_POWER_DOWN_ALLOW;
9049 I915_WRITE(LCPLL_CTL, val);
9050 POSTING_READ(LCPLL_CTL);
9051 }
9052 }
9053
9054 /*
9055 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9056 * source.
9057 */
9058 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9059 {
9060 uint32_t val;
9061
9062 val = I915_READ(LCPLL_CTL);
9063
9064 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9065 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9066 return;
9067
9068 /*
9069 * Make sure we're not on PC8 state before disabling PC8, otherwise
9070 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9071 */
9072 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9073
9074 if (val & LCPLL_POWER_DOWN_ALLOW) {
9075 val &= ~LCPLL_POWER_DOWN_ALLOW;
9076 I915_WRITE(LCPLL_CTL, val);
9077 POSTING_READ(LCPLL_CTL);
9078 }
9079
9080 val = hsw_read_dcomp(dev_priv);
9081 val |= D_COMP_COMP_FORCE;
9082 val &= ~D_COMP_COMP_DISABLE;
9083 hsw_write_dcomp(dev_priv, val);
9084
9085 val = I915_READ(LCPLL_CTL);
9086 val &= ~LCPLL_PLL_DISABLE;
9087 I915_WRITE(LCPLL_CTL, val);
9088
9089 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9090 DRM_ERROR("LCPLL not locked yet\n");
9091
9092 if (val & LCPLL_CD_SOURCE_FCLK) {
9093 val = I915_READ(LCPLL_CTL);
9094 val &= ~LCPLL_CD_SOURCE_FCLK;
9095 I915_WRITE(LCPLL_CTL, val);
9096
9097 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9098 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9099 DRM_ERROR("Switching back to LCPLL failed\n");
9100 }
9101
9102 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9103 }
9104
9105 /*
9106 * Package states C8 and deeper are really deep PC states that can only be
9107 * reached when all the devices on the system allow it, so even if the graphics
9108 * device allows PC8+, it doesn't mean the system will actually get to these
9109 * states. Our driver only allows PC8+ when going into runtime PM.
9110 *
9111 * The requirements for PC8+ are that all the outputs are disabled, the power
9112 * well is disabled and most interrupts are disabled, and these are also
9113 * requirements for runtime PM. When these conditions are met, we manually do
9114 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9115 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9116 * hang the machine.
9117 *
9118 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9119 * the state of some registers, so when we come back from PC8+ we need to
9120 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9121 * need to take care of the registers kept by RC6. Notice that this happens even
9122 * if we don't put the device in PCI D3 state (which is what currently happens
9123 * because of the runtime PM support).
9124 *
9125 * For more, read "Display Sequences for Package C8" on the hardware
9126 * documentation.
9127 */
9128 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9129 {
9130 struct drm_device *dev = dev_priv->dev;
9131 uint32_t val;
9132
9133 DRM_DEBUG_KMS("Enabling package C8+\n");
9134
9135 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9136 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9137 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9138 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9139 }
9140
9141 lpt_disable_clkout_dp(dev);
9142 hsw_disable_lcpll(dev_priv, true, true);
9143 }
9144
9145 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9146 {
9147 struct drm_device *dev = dev_priv->dev;
9148 uint32_t val;
9149
9150 DRM_DEBUG_KMS("Disabling package C8+\n");
9151
9152 hsw_restore_lcpll(dev_priv);
9153 lpt_init_pch_refclk(dev);
9154
9155 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9156 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9157 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9158 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9159 }
9160
9161 intel_prepare_ddi(dev);
9162 }
9163
9164 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9165 {
9166 struct drm_device *dev = old_state->dev;
9167 struct drm_i915_private *dev_priv = dev->dev_private;
9168 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9169 int req_cdclk;
9170
9171 /* see the comment in valleyview_modeset_global_resources */
9172 if (WARN_ON(max_pixclk < 0))
9173 return;
9174
9175 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9176
9177 if (req_cdclk != dev_priv->cdclk_freq)
9178 broxton_set_cdclk(dev, req_cdclk);
9179 }
9180
9181 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9182 struct intel_crtc_state *crtc_state)
9183 {
9184 if (!intel_ddi_pll_select(crtc, crtc_state))
9185 return -EINVAL;
9186
9187 crtc->lowfreq_avail = false;
9188
9189 return 0;
9190 }
9191
9192 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9193 enum port port,
9194 struct intel_crtc_state *pipe_config)
9195 {
9196 switch (port) {
9197 case PORT_A:
9198 pipe_config->ddi_pll_sel = SKL_DPLL0;
9199 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9200 break;
9201 case PORT_B:
9202 pipe_config->ddi_pll_sel = SKL_DPLL1;
9203 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9204 break;
9205 case PORT_C:
9206 pipe_config->ddi_pll_sel = SKL_DPLL2;
9207 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9208 break;
9209 default:
9210 DRM_ERROR("Incorrect port type\n");
9211 }
9212 }
9213
9214 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9215 enum port port,
9216 struct intel_crtc_state *pipe_config)
9217 {
9218 u32 temp, dpll_ctl1;
9219
9220 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9221 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9222
9223 switch (pipe_config->ddi_pll_sel) {
9224 case SKL_DPLL0:
9225 /*
9226 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9227 * of the shared DPLL framework and thus needs to be read out
9228 * separately
9229 */
9230 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9231 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9232 break;
9233 case SKL_DPLL1:
9234 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9235 break;
9236 case SKL_DPLL2:
9237 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9238 break;
9239 case SKL_DPLL3:
9240 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9241 break;
9242 }
9243 }
9244
9245 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9246 enum port port,
9247 struct intel_crtc_state *pipe_config)
9248 {
9249 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9250
9251 switch (pipe_config->ddi_pll_sel) {
9252 case PORT_CLK_SEL_WRPLL1:
9253 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9254 break;
9255 case PORT_CLK_SEL_WRPLL2:
9256 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9257 break;
9258 }
9259 }
9260
9261 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9262 struct intel_crtc_state *pipe_config)
9263 {
9264 struct drm_device *dev = crtc->base.dev;
9265 struct drm_i915_private *dev_priv = dev->dev_private;
9266 struct intel_shared_dpll *pll;
9267 enum port port;
9268 uint32_t tmp;
9269
9270 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9271
9272 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9273
9274 if (IS_SKYLAKE(dev))
9275 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9276 else if (IS_BROXTON(dev))
9277 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9278 else
9279 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9280
9281 if (pipe_config->shared_dpll >= 0) {
9282 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9283
9284 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9285 &pipe_config->dpll_hw_state));
9286 }
9287
9288 /*
9289 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9290 * DDI E. So just check whether this pipe is wired to DDI E and whether
9291 * the PCH transcoder is on.
9292 */
9293 if (INTEL_INFO(dev)->gen < 9 &&
9294 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9295 pipe_config->has_pch_encoder = true;
9296
9297 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9298 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9299 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9300
9301 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9302 }
9303 }
9304
9305 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9306 struct intel_crtc_state *pipe_config)
9307 {
9308 struct drm_device *dev = crtc->base.dev;
9309 struct drm_i915_private *dev_priv = dev->dev_private;
9310 enum intel_display_power_domain pfit_domain;
9311 uint32_t tmp;
9312
9313 if (!intel_display_power_is_enabled(dev_priv,
9314 POWER_DOMAIN_PIPE(crtc->pipe)))
9315 return false;
9316
9317 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9318 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9319
9320 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9321 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9322 enum pipe trans_edp_pipe;
9323 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9324 default:
9325 WARN(1, "unknown pipe linked to edp transcoder\n");
9326 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9327 case TRANS_DDI_EDP_INPUT_A_ON:
9328 trans_edp_pipe = PIPE_A;
9329 break;
9330 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9331 trans_edp_pipe = PIPE_B;
9332 break;
9333 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9334 trans_edp_pipe = PIPE_C;
9335 break;
9336 }
9337
9338 if (trans_edp_pipe == crtc->pipe)
9339 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9340 }
9341
9342 if (!intel_display_power_is_enabled(dev_priv,
9343 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9344 return false;
9345
9346 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9347 if (!(tmp & PIPECONF_ENABLE))
9348 return false;
9349
9350 haswell_get_ddi_port_state(crtc, pipe_config);
9351
9352 intel_get_pipe_timings(crtc, pipe_config);
9353
9354 if (INTEL_INFO(dev)->gen >= 9) {
9355 skl_init_scalers(dev, crtc, pipe_config);
9356 }
9357
9358 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9359 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9360 if (INTEL_INFO(dev)->gen == 9)
9361 skylake_get_pfit_config(crtc, pipe_config);
9362 else if (INTEL_INFO(dev)->gen < 9)
9363 ironlake_get_pfit_config(crtc, pipe_config);
9364 else
9365 MISSING_CASE(INTEL_INFO(dev)->gen);
9366
9367 } else {
9368 pipe_config->scaler_state.scaler_id = -1;
9369 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9370 }
9371
9372 if (IS_HASWELL(dev))
9373 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9374 (I915_READ(IPS_CTL) & IPS_ENABLE);
9375
9376 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9377 pipe_config->pixel_multiplier =
9378 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9379 } else {
9380 pipe_config->pixel_multiplier = 1;
9381 }
9382
9383 return true;
9384 }
9385
9386 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9387 {
9388 struct drm_device *dev = crtc->dev;
9389 struct drm_i915_private *dev_priv = dev->dev_private;
9390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9391 uint32_t cntl = 0, size = 0;
9392
9393 if (base) {
9394 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9395 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9396 unsigned int stride = roundup_pow_of_two(width) * 4;
9397
9398 switch (stride) {
9399 default:
9400 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9401 width, stride);
9402 stride = 256;
9403 /* fallthrough */
9404 case 256:
9405 case 512:
9406 case 1024:
9407 case 2048:
9408 break;
9409 }
9410
9411 cntl |= CURSOR_ENABLE |
9412 CURSOR_GAMMA_ENABLE |
9413 CURSOR_FORMAT_ARGB |
9414 CURSOR_STRIDE(stride);
9415
9416 size = (height << 12) | width;
9417 }
9418
9419 if (intel_crtc->cursor_cntl != 0 &&
9420 (intel_crtc->cursor_base != base ||
9421 intel_crtc->cursor_size != size ||
9422 intel_crtc->cursor_cntl != cntl)) {
9423 /* On these chipsets we can only modify the base/size/stride
9424 * whilst the cursor is disabled.
9425 */
9426 I915_WRITE(_CURACNTR, 0);
9427 POSTING_READ(_CURACNTR);
9428 intel_crtc->cursor_cntl = 0;
9429 }
9430
9431 if (intel_crtc->cursor_base != base) {
9432 I915_WRITE(_CURABASE, base);
9433 intel_crtc->cursor_base = base;
9434 }
9435
9436 if (intel_crtc->cursor_size != size) {
9437 I915_WRITE(CURSIZE, size);
9438 intel_crtc->cursor_size = size;
9439 }
9440
9441 if (intel_crtc->cursor_cntl != cntl) {
9442 I915_WRITE(_CURACNTR, cntl);
9443 POSTING_READ(_CURACNTR);
9444 intel_crtc->cursor_cntl = cntl;
9445 }
9446 }
9447
9448 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9449 {
9450 struct drm_device *dev = crtc->dev;
9451 struct drm_i915_private *dev_priv = dev->dev_private;
9452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9453 int pipe = intel_crtc->pipe;
9454 uint32_t cntl;
9455
9456 cntl = 0;
9457 if (base) {
9458 cntl = MCURSOR_GAMMA_ENABLE;
9459 switch (intel_crtc->base.cursor->state->crtc_w) {
9460 case 64:
9461 cntl |= CURSOR_MODE_64_ARGB_AX;
9462 break;
9463 case 128:
9464 cntl |= CURSOR_MODE_128_ARGB_AX;
9465 break;
9466 case 256:
9467 cntl |= CURSOR_MODE_256_ARGB_AX;
9468 break;
9469 default:
9470 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9471 return;
9472 }
9473 cntl |= pipe << 28; /* Connect to correct pipe */
9474
9475 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9476 cntl |= CURSOR_PIPE_CSC_ENABLE;
9477 }
9478
9479 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9480 cntl |= CURSOR_ROTATE_180;
9481
9482 if (intel_crtc->cursor_cntl != cntl) {
9483 I915_WRITE(CURCNTR(pipe), cntl);
9484 POSTING_READ(CURCNTR(pipe));
9485 intel_crtc->cursor_cntl = cntl;
9486 }
9487
9488 /* and commit changes on next vblank */
9489 I915_WRITE(CURBASE(pipe), base);
9490 POSTING_READ(CURBASE(pipe));
9491
9492 intel_crtc->cursor_base = base;
9493 }
9494
9495 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9496 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9497 bool on)
9498 {
9499 struct drm_device *dev = crtc->dev;
9500 struct drm_i915_private *dev_priv = dev->dev_private;
9501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9502 int pipe = intel_crtc->pipe;
9503 int x = crtc->cursor_x;
9504 int y = crtc->cursor_y;
9505 u32 base = 0, pos = 0;
9506
9507 if (on)
9508 base = intel_crtc->cursor_addr;
9509
9510 if (x >= intel_crtc->config->pipe_src_w)
9511 base = 0;
9512
9513 if (y >= intel_crtc->config->pipe_src_h)
9514 base = 0;
9515
9516 if (x < 0) {
9517 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9518 base = 0;
9519
9520 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9521 x = -x;
9522 }
9523 pos |= x << CURSOR_X_SHIFT;
9524
9525 if (y < 0) {
9526 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9527 base = 0;
9528
9529 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9530 y = -y;
9531 }
9532 pos |= y << CURSOR_Y_SHIFT;
9533
9534 if (base == 0 && intel_crtc->cursor_base == 0)
9535 return;
9536
9537 I915_WRITE(CURPOS(pipe), pos);
9538
9539 /* ILK+ do this automagically */
9540 if (HAS_GMCH_DISPLAY(dev) &&
9541 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9542 base += (intel_crtc->base.cursor->state->crtc_h *
9543 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9544 }
9545
9546 if (IS_845G(dev) || IS_I865G(dev))
9547 i845_update_cursor(crtc, base);
9548 else
9549 i9xx_update_cursor(crtc, base);
9550 }
9551
9552 static bool cursor_size_ok(struct drm_device *dev,
9553 uint32_t width, uint32_t height)
9554 {
9555 if (width == 0 || height == 0)
9556 return false;
9557
9558 /*
9559 * 845g/865g are special in that they are only limited by
9560 * the width of their cursors, the height is arbitrary up to
9561 * the precision of the register. Everything else requires
9562 * square cursors, limited to a few power-of-two sizes.
9563 */
9564 if (IS_845G(dev) || IS_I865G(dev)) {
9565 if ((width & 63) != 0)
9566 return false;
9567
9568 if (width > (IS_845G(dev) ? 64 : 512))
9569 return false;
9570
9571 if (height > 1023)
9572 return false;
9573 } else {
9574 switch (width | height) {
9575 case 256:
9576 case 128:
9577 if (IS_GEN2(dev))
9578 return false;
9579 case 64:
9580 break;
9581 default:
9582 return false;
9583 }
9584 }
9585
9586 return true;
9587 }
9588
9589 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9590 u16 *blue, uint32_t start, uint32_t size)
9591 {
9592 int end = (start + size > 256) ? 256 : start + size, i;
9593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9594
9595 for (i = start; i < end; i++) {
9596 intel_crtc->lut_r[i] = red[i] >> 8;
9597 intel_crtc->lut_g[i] = green[i] >> 8;
9598 intel_crtc->lut_b[i] = blue[i] >> 8;
9599 }
9600
9601 intel_crtc_load_lut(crtc);
9602 }
9603
9604 /* VESA 640x480x72Hz mode to set on the pipe */
9605 static struct drm_display_mode load_detect_mode = {
9606 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9607 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9608 };
9609
9610 struct drm_framebuffer *
9611 __intel_framebuffer_create(struct drm_device *dev,
9612 struct drm_mode_fb_cmd2 *mode_cmd,
9613 struct drm_i915_gem_object *obj)
9614 {
9615 struct intel_framebuffer *intel_fb;
9616 int ret;
9617
9618 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9619 if (!intel_fb) {
9620 drm_gem_object_unreference(&obj->base);
9621 return ERR_PTR(-ENOMEM);
9622 }
9623
9624 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9625 if (ret)
9626 goto err;
9627
9628 return &intel_fb->base;
9629 err:
9630 drm_gem_object_unreference(&obj->base);
9631 kfree(intel_fb);
9632
9633 return ERR_PTR(ret);
9634 }
9635
9636 static struct drm_framebuffer *
9637 intel_framebuffer_create(struct drm_device *dev,
9638 struct drm_mode_fb_cmd2 *mode_cmd,
9639 struct drm_i915_gem_object *obj)
9640 {
9641 struct drm_framebuffer *fb;
9642 int ret;
9643
9644 ret = i915_mutex_lock_interruptible(dev);
9645 if (ret)
9646 return ERR_PTR(ret);
9647 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9648 mutex_unlock(&dev->struct_mutex);
9649
9650 return fb;
9651 }
9652
9653 static u32
9654 intel_framebuffer_pitch_for_width(int width, int bpp)
9655 {
9656 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9657 return ALIGN(pitch, 64);
9658 }
9659
9660 static u32
9661 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9662 {
9663 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9664 return PAGE_ALIGN(pitch * mode->vdisplay);
9665 }
9666
9667 static struct drm_framebuffer *
9668 intel_framebuffer_create_for_mode(struct drm_device *dev,
9669 struct drm_display_mode *mode,
9670 int depth, int bpp)
9671 {
9672 struct drm_i915_gem_object *obj;
9673 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9674
9675 obj = i915_gem_alloc_object(dev,
9676 intel_framebuffer_size_for_mode(mode, bpp));
9677 if (obj == NULL)
9678 return ERR_PTR(-ENOMEM);
9679
9680 mode_cmd.width = mode->hdisplay;
9681 mode_cmd.height = mode->vdisplay;
9682 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9683 bpp);
9684 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9685
9686 return intel_framebuffer_create(dev, &mode_cmd, obj);
9687 }
9688
9689 static struct drm_framebuffer *
9690 mode_fits_in_fbdev(struct drm_device *dev,
9691 struct drm_display_mode *mode)
9692 {
9693 #ifdef CONFIG_DRM_I915_FBDEV
9694 struct drm_i915_private *dev_priv = dev->dev_private;
9695 struct drm_i915_gem_object *obj;
9696 struct drm_framebuffer *fb;
9697
9698 if (!dev_priv->fbdev)
9699 return NULL;
9700
9701 if (!dev_priv->fbdev->fb)
9702 return NULL;
9703
9704 obj = dev_priv->fbdev->fb->obj;
9705 BUG_ON(!obj);
9706
9707 fb = &dev_priv->fbdev->fb->base;
9708 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9709 fb->bits_per_pixel))
9710 return NULL;
9711
9712 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9713 return NULL;
9714
9715 return fb;
9716 #else
9717 return NULL;
9718 #endif
9719 }
9720
9721 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9722 struct drm_crtc *crtc,
9723 struct drm_display_mode *mode,
9724 struct drm_framebuffer *fb,
9725 int x, int y)
9726 {
9727 struct drm_plane_state *plane_state;
9728 int hdisplay, vdisplay;
9729 int ret;
9730
9731 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9732 if (IS_ERR(plane_state))
9733 return PTR_ERR(plane_state);
9734
9735 if (mode)
9736 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9737 else
9738 hdisplay = vdisplay = 0;
9739
9740 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9741 if (ret)
9742 return ret;
9743 drm_atomic_set_fb_for_plane(plane_state, fb);
9744 plane_state->crtc_x = 0;
9745 plane_state->crtc_y = 0;
9746 plane_state->crtc_w = hdisplay;
9747 plane_state->crtc_h = vdisplay;
9748 plane_state->src_x = x << 16;
9749 plane_state->src_y = y << 16;
9750 plane_state->src_w = hdisplay << 16;
9751 plane_state->src_h = vdisplay << 16;
9752
9753 return 0;
9754 }
9755
9756 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9757 struct drm_display_mode *mode,
9758 struct intel_load_detect_pipe *old,
9759 struct drm_modeset_acquire_ctx *ctx)
9760 {
9761 struct intel_crtc *intel_crtc;
9762 struct intel_encoder *intel_encoder =
9763 intel_attached_encoder(connector);
9764 struct drm_crtc *possible_crtc;
9765 struct drm_encoder *encoder = &intel_encoder->base;
9766 struct drm_crtc *crtc = NULL;
9767 struct drm_device *dev = encoder->dev;
9768 struct drm_framebuffer *fb;
9769 struct drm_mode_config *config = &dev->mode_config;
9770 struct drm_atomic_state *state = NULL;
9771 struct drm_connector_state *connector_state;
9772 struct intel_crtc_state *crtc_state;
9773 int ret, i = -1;
9774
9775 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9776 connector->base.id, connector->name,
9777 encoder->base.id, encoder->name);
9778
9779 retry:
9780 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9781 if (ret)
9782 goto fail_unlock;
9783
9784 /*
9785 * Algorithm gets a little messy:
9786 *
9787 * - if the connector already has an assigned crtc, use it (but make
9788 * sure it's on first)
9789 *
9790 * - try to find the first unused crtc that can drive this connector,
9791 * and use that if we find one
9792 */
9793
9794 /* See if we already have a CRTC for this connector */
9795 if (encoder->crtc) {
9796 crtc = encoder->crtc;
9797
9798 ret = drm_modeset_lock(&crtc->mutex, ctx);
9799 if (ret)
9800 goto fail_unlock;
9801 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9802 if (ret)
9803 goto fail_unlock;
9804
9805 old->dpms_mode = connector->dpms;
9806 old->load_detect_temp = false;
9807
9808 /* Make sure the crtc and connector are running */
9809 if (connector->dpms != DRM_MODE_DPMS_ON)
9810 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9811
9812 return true;
9813 }
9814
9815 /* Find an unused one (if possible) */
9816 for_each_crtc(dev, possible_crtc) {
9817 i++;
9818 if (!(encoder->possible_crtcs & (1 << i)))
9819 continue;
9820 if (possible_crtc->state->enable)
9821 continue;
9822 /* This can occur when applying the pipe A quirk on resume. */
9823 if (to_intel_crtc(possible_crtc)->new_enabled)
9824 continue;
9825
9826 crtc = possible_crtc;
9827 break;
9828 }
9829
9830 /*
9831 * If we didn't find an unused CRTC, don't use any.
9832 */
9833 if (!crtc) {
9834 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9835 goto fail_unlock;
9836 }
9837
9838 ret = drm_modeset_lock(&crtc->mutex, ctx);
9839 if (ret)
9840 goto fail_unlock;
9841 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9842 if (ret)
9843 goto fail_unlock;
9844 intel_encoder->new_crtc = to_intel_crtc(crtc);
9845 to_intel_connector(connector)->new_encoder = intel_encoder;
9846
9847 intel_crtc = to_intel_crtc(crtc);
9848 intel_crtc->new_enabled = true;
9849 old->dpms_mode = connector->dpms;
9850 old->load_detect_temp = true;
9851 old->release_fb = NULL;
9852
9853 state = drm_atomic_state_alloc(dev);
9854 if (!state)
9855 return false;
9856
9857 state->acquire_ctx = ctx;
9858
9859 connector_state = drm_atomic_get_connector_state(state, connector);
9860 if (IS_ERR(connector_state)) {
9861 ret = PTR_ERR(connector_state);
9862 goto fail;
9863 }
9864
9865 connector_state->crtc = crtc;
9866 connector_state->best_encoder = &intel_encoder->base;
9867
9868 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9869 if (IS_ERR(crtc_state)) {
9870 ret = PTR_ERR(crtc_state);
9871 goto fail;
9872 }
9873
9874 crtc_state->base.active = crtc_state->base.enable = true;
9875
9876 if (!mode)
9877 mode = &load_detect_mode;
9878
9879 /* We need a framebuffer large enough to accommodate all accesses
9880 * that the plane may generate whilst we perform load detection.
9881 * We can not rely on the fbcon either being present (we get called
9882 * during its initialisation to detect all boot displays, or it may
9883 * not even exist) or that it is large enough to satisfy the
9884 * requested mode.
9885 */
9886 fb = mode_fits_in_fbdev(dev, mode);
9887 if (fb == NULL) {
9888 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9889 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9890 old->release_fb = fb;
9891 } else
9892 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9893 if (IS_ERR(fb)) {
9894 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9895 goto fail;
9896 }
9897
9898 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9899 if (ret)
9900 goto fail;
9901
9902 drm_mode_copy(&crtc_state->base.mode, mode);
9903
9904 if (intel_set_mode(crtc, state)) {
9905 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9906 if (old->release_fb)
9907 old->release_fb->funcs->destroy(old->release_fb);
9908 goto fail;
9909 }
9910 crtc->primary->crtc = crtc;
9911
9912 /* let the connector get through one full cycle before testing */
9913 intel_wait_for_vblank(dev, intel_crtc->pipe);
9914 return true;
9915
9916 fail:
9917 intel_crtc->new_enabled = crtc->state->enable;
9918 fail_unlock:
9919 drm_atomic_state_free(state);
9920 state = NULL;
9921
9922 if (ret == -EDEADLK) {
9923 drm_modeset_backoff(ctx);
9924 goto retry;
9925 }
9926
9927 return false;
9928 }
9929
9930 void intel_release_load_detect_pipe(struct drm_connector *connector,
9931 struct intel_load_detect_pipe *old,
9932 struct drm_modeset_acquire_ctx *ctx)
9933 {
9934 struct drm_device *dev = connector->dev;
9935 struct intel_encoder *intel_encoder =
9936 intel_attached_encoder(connector);
9937 struct drm_encoder *encoder = &intel_encoder->base;
9938 struct drm_crtc *crtc = encoder->crtc;
9939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9940 struct drm_atomic_state *state;
9941 struct drm_connector_state *connector_state;
9942 struct intel_crtc_state *crtc_state;
9943 int ret;
9944
9945 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9946 connector->base.id, connector->name,
9947 encoder->base.id, encoder->name);
9948
9949 if (old->load_detect_temp) {
9950 state = drm_atomic_state_alloc(dev);
9951 if (!state)
9952 goto fail;
9953
9954 state->acquire_ctx = ctx;
9955
9956 connector_state = drm_atomic_get_connector_state(state, connector);
9957 if (IS_ERR(connector_state))
9958 goto fail;
9959
9960 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9961 if (IS_ERR(crtc_state))
9962 goto fail;
9963
9964 to_intel_connector(connector)->new_encoder = NULL;
9965 intel_encoder->new_crtc = NULL;
9966 intel_crtc->new_enabled = false;
9967
9968 connector_state->best_encoder = NULL;
9969 connector_state->crtc = NULL;
9970
9971 crtc_state->base.enable = crtc_state->base.active = false;
9972
9973 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9974 0, 0);
9975 if (ret)
9976 goto fail;
9977
9978 ret = intel_set_mode(crtc, state);
9979 if (ret)
9980 goto fail;
9981
9982 if (old->release_fb) {
9983 drm_framebuffer_unregister_private(old->release_fb);
9984 drm_framebuffer_unreference(old->release_fb);
9985 }
9986
9987 return;
9988 }
9989
9990 /* Switch crtc and encoder back off if necessary */
9991 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9992 connector->funcs->dpms(connector, old->dpms_mode);
9993
9994 return;
9995 fail:
9996 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9997 drm_atomic_state_free(state);
9998 }
9999
10000 static int i9xx_pll_refclk(struct drm_device *dev,
10001 const struct intel_crtc_state *pipe_config)
10002 {
10003 struct drm_i915_private *dev_priv = dev->dev_private;
10004 u32 dpll = pipe_config->dpll_hw_state.dpll;
10005
10006 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10007 return dev_priv->vbt.lvds_ssc_freq;
10008 else if (HAS_PCH_SPLIT(dev))
10009 return 120000;
10010 else if (!IS_GEN2(dev))
10011 return 96000;
10012 else
10013 return 48000;
10014 }
10015
10016 /* Returns the clock of the currently programmed mode of the given pipe. */
10017 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10018 struct intel_crtc_state *pipe_config)
10019 {
10020 struct drm_device *dev = crtc->base.dev;
10021 struct drm_i915_private *dev_priv = dev->dev_private;
10022 int pipe = pipe_config->cpu_transcoder;
10023 u32 dpll = pipe_config->dpll_hw_state.dpll;
10024 u32 fp;
10025 intel_clock_t clock;
10026 int refclk = i9xx_pll_refclk(dev, pipe_config);
10027
10028 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10029 fp = pipe_config->dpll_hw_state.fp0;
10030 else
10031 fp = pipe_config->dpll_hw_state.fp1;
10032
10033 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10034 if (IS_PINEVIEW(dev)) {
10035 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10036 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10037 } else {
10038 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10039 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10040 }
10041
10042 if (!IS_GEN2(dev)) {
10043 if (IS_PINEVIEW(dev))
10044 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10045 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10046 else
10047 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10048 DPLL_FPA01_P1_POST_DIV_SHIFT);
10049
10050 switch (dpll & DPLL_MODE_MASK) {
10051 case DPLLB_MODE_DAC_SERIAL:
10052 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10053 5 : 10;
10054 break;
10055 case DPLLB_MODE_LVDS:
10056 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10057 7 : 14;
10058 break;
10059 default:
10060 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10061 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10062 return;
10063 }
10064
10065 if (IS_PINEVIEW(dev))
10066 pineview_clock(refclk, &clock);
10067 else
10068 i9xx_clock(refclk, &clock);
10069 } else {
10070 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10071 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10072
10073 if (is_lvds) {
10074 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10075 DPLL_FPA01_P1_POST_DIV_SHIFT);
10076
10077 if (lvds & LVDS_CLKB_POWER_UP)
10078 clock.p2 = 7;
10079 else
10080 clock.p2 = 14;
10081 } else {
10082 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10083 clock.p1 = 2;
10084 else {
10085 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10086 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10087 }
10088 if (dpll & PLL_P2_DIVIDE_BY_4)
10089 clock.p2 = 4;
10090 else
10091 clock.p2 = 2;
10092 }
10093
10094 i9xx_clock(refclk, &clock);
10095 }
10096
10097 /*
10098 * This value includes pixel_multiplier. We will use
10099 * port_clock to compute adjusted_mode.crtc_clock in the
10100 * encoder's get_config() function.
10101 */
10102 pipe_config->port_clock = clock.dot;
10103 }
10104
10105 int intel_dotclock_calculate(int link_freq,
10106 const struct intel_link_m_n *m_n)
10107 {
10108 /*
10109 * The calculation for the data clock is:
10110 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10111 * But we want to avoid losing precison if possible, so:
10112 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10113 *
10114 * and the link clock is simpler:
10115 * link_clock = (m * link_clock) / n
10116 */
10117
10118 if (!m_n->link_n)
10119 return 0;
10120
10121 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10122 }
10123
10124 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10125 struct intel_crtc_state *pipe_config)
10126 {
10127 struct drm_device *dev = crtc->base.dev;
10128
10129 /* read out port_clock from the DPLL */
10130 i9xx_crtc_clock_get(crtc, pipe_config);
10131
10132 /*
10133 * This value does not include pixel_multiplier.
10134 * We will check that port_clock and adjusted_mode.crtc_clock
10135 * agree once we know their relationship in the encoder's
10136 * get_config() function.
10137 */
10138 pipe_config->base.adjusted_mode.crtc_clock =
10139 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10140 &pipe_config->fdi_m_n);
10141 }
10142
10143 /** Returns the currently programmed mode of the given pipe. */
10144 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10145 struct drm_crtc *crtc)
10146 {
10147 struct drm_i915_private *dev_priv = dev->dev_private;
10148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10149 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10150 struct drm_display_mode *mode;
10151 struct intel_crtc_state pipe_config;
10152 int htot = I915_READ(HTOTAL(cpu_transcoder));
10153 int hsync = I915_READ(HSYNC(cpu_transcoder));
10154 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10155 int vsync = I915_READ(VSYNC(cpu_transcoder));
10156 enum pipe pipe = intel_crtc->pipe;
10157
10158 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10159 if (!mode)
10160 return NULL;
10161
10162 /*
10163 * Construct a pipe_config sufficient for getting the clock info
10164 * back out of crtc_clock_get.
10165 *
10166 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10167 * to use a real value here instead.
10168 */
10169 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10170 pipe_config.pixel_multiplier = 1;
10171 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10172 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10173 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10174 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10175
10176 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10177 mode->hdisplay = (htot & 0xffff) + 1;
10178 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10179 mode->hsync_start = (hsync & 0xffff) + 1;
10180 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10181 mode->vdisplay = (vtot & 0xffff) + 1;
10182 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10183 mode->vsync_start = (vsync & 0xffff) + 1;
10184 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10185
10186 drm_mode_set_name(mode);
10187
10188 return mode;
10189 }
10190
10191 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10192 {
10193 struct drm_device *dev = crtc->dev;
10194 struct drm_i915_private *dev_priv = dev->dev_private;
10195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10196
10197 if (!HAS_GMCH_DISPLAY(dev))
10198 return;
10199
10200 if (!dev_priv->lvds_downclock_avail)
10201 return;
10202
10203 /*
10204 * Since this is called by a timer, we should never get here in
10205 * the manual case.
10206 */
10207 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10208 int pipe = intel_crtc->pipe;
10209 int dpll_reg = DPLL(pipe);
10210 int dpll;
10211
10212 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10213
10214 assert_panel_unlocked(dev_priv, pipe);
10215
10216 dpll = I915_READ(dpll_reg);
10217 dpll |= DISPLAY_RATE_SELECT_FPA1;
10218 I915_WRITE(dpll_reg, dpll);
10219 intel_wait_for_vblank(dev, pipe);
10220 dpll = I915_READ(dpll_reg);
10221 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10222 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10223 }
10224
10225 }
10226
10227 void intel_mark_busy(struct drm_device *dev)
10228 {
10229 struct drm_i915_private *dev_priv = dev->dev_private;
10230
10231 if (dev_priv->mm.busy)
10232 return;
10233
10234 intel_runtime_pm_get(dev_priv);
10235 i915_update_gfx_val(dev_priv);
10236 if (INTEL_INFO(dev)->gen >= 6)
10237 gen6_rps_busy(dev_priv);
10238 dev_priv->mm.busy = true;
10239 }
10240
10241 void intel_mark_idle(struct drm_device *dev)
10242 {
10243 struct drm_i915_private *dev_priv = dev->dev_private;
10244 struct drm_crtc *crtc;
10245
10246 if (!dev_priv->mm.busy)
10247 return;
10248
10249 dev_priv->mm.busy = false;
10250
10251 for_each_crtc(dev, crtc) {
10252 if (!crtc->primary->fb)
10253 continue;
10254
10255 intel_decrease_pllclock(crtc);
10256 }
10257
10258 if (INTEL_INFO(dev)->gen >= 6)
10259 gen6_rps_idle(dev->dev_private);
10260
10261 intel_runtime_pm_put(dev_priv);
10262 }
10263
10264 static void intel_crtc_destroy(struct drm_crtc *crtc)
10265 {
10266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10267 struct drm_device *dev = crtc->dev;
10268 struct intel_unpin_work *work;
10269
10270 spin_lock_irq(&dev->event_lock);
10271 work = intel_crtc->unpin_work;
10272 intel_crtc->unpin_work = NULL;
10273 spin_unlock_irq(&dev->event_lock);
10274
10275 if (work) {
10276 cancel_work_sync(&work->work);
10277 kfree(work);
10278 }
10279
10280 drm_crtc_cleanup(crtc);
10281
10282 kfree(intel_crtc);
10283 }
10284
10285 static void intel_unpin_work_fn(struct work_struct *__work)
10286 {
10287 struct intel_unpin_work *work =
10288 container_of(__work, struct intel_unpin_work, work);
10289 struct drm_device *dev = work->crtc->dev;
10290 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10291
10292 mutex_lock(&dev->struct_mutex);
10293 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10294 drm_gem_object_unreference(&work->pending_flip_obj->base);
10295
10296 intel_fbc_update(dev);
10297
10298 if (work->flip_queued_req)
10299 i915_gem_request_assign(&work->flip_queued_req, NULL);
10300 mutex_unlock(&dev->struct_mutex);
10301
10302 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10303 drm_framebuffer_unreference(work->old_fb);
10304
10305 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10306 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10307
10308 kfree(work);
10309 }
10310
10311 static void do_intel_finish_page_flip(struct drm_device *dev,
10312 struct drm_crtc *crtc)
10313 {
10314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10315 struct intel_unpin_work *work;
10316 unsigned long flags;
10317
10318 /* Ignore early vblank irqs */
10319 if (intel_crtc == NULL)
10320 return;
10321
10322 /*
10323 * This is called both by irq handlers and the reset code (to complete
10324 * lost pageflips) so needs the full irqsave spinlocks.
10325 */
10326 spin_lock_irqsave(&dev->event_lock, flags);
10327 work = intel_crtc->unpin_work;
10328
10329 /* Ensure we don't miss a work->pending update ... */
10330 smp_rmb();
10331
10332 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10333 spin_unlock_irqrestore(&dev->event_lock, flags);
10334 return;
10335 }
10336
10337 page_flip_completed(intel_crtc);
10338
10339 spin_unlock_irqrestore(&dev->event_lock, flags);
10340 }
10341
10342 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10343 {
10344 struct drm_i915_private *dev_priv = dev->dev_private;
10345 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10346
10347 do_intel_finish_page_flip(dev, crtc);
10348 }
10349
10350 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10351 {
10352 struct drm_i915_private *dev_priv = dev->dev_private;
10353 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10354
10355 do_intel_finish_page_flip(dev, crtc);
10356 }
10357
10358 /* Is 'a' after or equal to 'b'? */
10359 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10360 {
10361 return !((a - b) & 0x80000000);
10362 }
10363
10364 static bool page_flip_finished(struct intel_crtc *crtc)
10365 {
10366 struct drm_device *dev = crtc->base.dev;
10367 struct drm_i915_private *dev_priv = dev->dev_private;
10368
10369 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10370 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10371 return true;
10372
10373 /*
10374 * The relevant registers doen't exist on pre-ctg.
10375 * As the flip done interrupt doesn't trigger for mmio
10376 * flips on gmch platforms, a flip count check isn't
10377 * really needed there. But since ctg has the registers,
10378 * include it in the check anyway.
10379 */
10380 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10381 return true;
10382
10383 /*
10384 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10385 * used the same base address. In that case the mmio flip might
10386 * have completed, but the CS hasn't even executed the flip yet.
10387 *
10388 * A flip count check isn't enough as the CS might have updated
10389 * the base address just after start of vblank, but before we
10390 * managed to process the interrupt. This means we'd complete the
10391 * CS flip too soon.
10392 *
10393 * Combining both checks should get us a good enough result. It may
10394 * still happen that the CS flip has been executed, but has not
10395 * yet actually completed. But in case the base address is the same
10396 * anyway, we don't really care.
10397 */
10398 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10399 crtc->unpin_work->gtt_offset &&
10400 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10401 crtc->unpin_work->flip_count);
10402 }
10403
10404 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10405 {
10406 struct drm_i915_private *dev_priv = dev->dev_private;
10407 struct intel_crtc *intel_crtc =
10408 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10409 unsigned long flags;
10410
10411
10412 /*
10413 * This is called both by irq handlers and the reset code (to complete
10414 * lost pageflips) so needs the full irqsave spinlocks.
10415 *
10416 * NB: An MMIO update of the plane base pointer will also
10417 * generate a page-flip completion irq, i.e. every modeset
10418 * is also accompanied by a spurious intel_prepare_page_flip().
10419 */
10420 spin_lock_irqsave(&dev->event_lock, flags);
10421 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10422 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10423 spin_unlock_irqrestore(&dev->event_lock, flags);
10424 }
10425
10426 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10427 {
10428 /* Ensure that the work item is consistent when activating it ... */
10429 smp_wmb();
10430 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10431 /* and that it is marked active as soon as the irq could fire. */
10432 smp_wmb();
10433 }
10434
10435 static int intel_gen2_queue_flip(struct drm_device *dev,
10436 struct drm_crtc *crtc,
10437 struct drm_framebuffer *fb,
10438 struct drm_i915_gem_object *obj,
10439 struct intel_engine_cs *ring,
10440 uint32_t flags)
10441 {
10442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10443 u32 flip_mask;
10444 int ret;
10445
10446 ret = intel_ring_begin(ring, 6);
10447 if (ret)
10448 return ret;
10449
10450 /* Can't queue multiple flips, so wait for the previous
10451 * one to finish before executing the next.
10452 */
10453 if (intel_crtc->plane)
10454 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10455 else
10456 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10457 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10458 intel_ring_emit(ring, MI_NOOP);
10459 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10460 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10461 intel_ring_emit(ring, fb->pitches[0]);
10462 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10463 intel_ring_emit(ring, 0); /* aux display base address, unused */
10464
10465 intel_mark_page_flip_active(intel_crtc);
10466 __intel_ring_advance(ring);
10467 return 0;
10468 }
10469
10470 static int intel_gen3_queue_flip(struct drm_device *dev,
10471 struct drm_crtc *crtc,
10472 struct drm_framebuffer *fb,
10473 struct drm_i915_gem_object *obj,
10474 struct intel_engine_cs *ring,
10475 uint32_t flags)
10476 {
10477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10478 u32 flip_mask;
10479 int ret;
10480
10481 ret = intel_ring_begin(ring, 6);
10482 if (ret)
10483 return ret;
10484
10485 if (intel_crtc->plane)
10486 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10487 else
10488 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10489 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10490 intel_ring_emit(ring, MI_NOOP);
10491 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10492 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10493 intel_ring_emit(ring, fb->pitches[0]);
10494 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10495 intel_ring_emit(ring, MI_NOOP);
10496
10497 intel_mark_page_flip_active(intel_crtc);
10498 __intel_ring_advance(ring);
10499 return 0;
10500 }
10501
10502 static int intel_gen4_queue_flip(struct drm_device *dev,
10503 struct drm_crtc *crtc,
10504 struct drm_framebuffer *fb,
10505 struct drm_i915_gem_object *obj,
10506 struct intel_engine_cs *ring,
10507 uint32_t flags)
10508 {
10509 struct drm_i915_private *dev_priv = dev->dev_private;
10510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10511 uint32_t pf, pipesrc;
10512 int ret;
10513
10514 ret = intel_ring_begin(ring, 4);
10515 if (ret)
10516 return ret;
10517
10518 /* i965+ uses the linear or tiled offsets from the
10519 * Display Registers (which do not change across a page-flip)
10520 * so we need only reprogram the base address.
10521 */
10522 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10523 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10524 intel_ring_emit(ring, fb->pitches[0]);
10525 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10526 obj->tiling_mode);
10527
10528 /* XXX Enabling the panel-fitter across page-flip is so far
10529 * untested on non-native modes, so ignore it for now.
10530 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10531 */
10532 pf = 0;
10533 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10534 intel_ring_emit(ring, pf | pipesrc);
10535
10536 intel_mark_page_flip_active(intel_crtc);
10537 __intel_ring_advance(ring);
10538 return 0;
10539 }
10540
10541 static int intel_gen6_queue_flip(struct drm_device *dev,
10542 struct drm_crtc *crtc,
10543 struct drm_framebuffer *fb,
10544 struct drm_i915_gem_object *obj,
10545 struct intel_engine_cs *ring,
10546 uint32_t flags)
10547 {
10548 struct drm_i915_private *dev_priv = dev->dev_private;
10549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10550 uint32_t pf, pipesrc;
10551 int ret;
10552
10553 ret = intel_ring_begin(ring, 4);
10554 if (ret)
10555 return ret;
10556
10557 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10558 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10559 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10560 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10561
10562 /* Contrary to the suggestions in the documentation,
10563 * "Enable Panel Fitter" does not seem to be required when page
10564 * flipping with a non-native mode, and worse causes a normal
10565 * modeset to fail.
10566 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10567 */
10568 pf = 0;
10569 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10570 intel_ring_emit(ring, pf | pipesrc);
10571
10572 intel_mark_page_flip_active(intel_crtc);
10573 __intel_ring_advance(ring);
10574 return 0;
10575 }
10576
10577 static int intel_gen7_queue_flip(struct drm_device *dev,
10578 struct drm_crtc *crtc,
10579 struct drm_framebuffer *fb,
10580 struct drm_i915_gem_object *obj,
10581 struct intel_engine_cs *ring,
10582 uint32_t flags)
10583 {
10584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10585 uint32_t plane_bit = 0;
10586 int len, ret;
10587
10588 switch (intel_crtc->plane) {
10589 case PLANE_A:
10590 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10591 break;
10592 case PLANE_B:
10593 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10594 break;
10595 case PLANE_C:
10596 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10597 break;
10598 default:
10599 WARN_ONCE(1, "unknown plane in flip command\n");
10600 return -ENODEV;
10601 }
10602
10603 len = 4;
10604 if (ring->id == RCS) {
10605 len += 6;
10606 /*
10607 * On Gen 8, SRM is now taking an extra dword to accommodate
10608 * 48bits addresses, and we need a NOOP for the batch size to
10609 * stay even.
10610 */
10611 if (IS_GEN8(dev))
10612 len += 2;
10613 }
10614
10615 /*
10616 * BSpec MI_DISPLAY_FLIP for IVB:
10617 * "The full packet must be contained within the same cache line."
10618 *
10619 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10620 * cacheline, if we ever start emitting more commands before
10621 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10622 * then do the cacheline alignment, and finally emit the
10623 * MI_DISPLAY_FLIP.
10624 */
10625 ret = intel_ring_cacheline_align(ring);
10626 if (ret)
10627 return ret;
10628
10629 ret = intel_ring_begin(ring, len);
10630 if (ret)
10631 return ret;
10632
10633 /* Unmask the flip-done completion message. Note that the bspec says that
10634 * we should do this for both the BCS and RCS, and that we must not unmask
10635 * more than one flip event at any time (or ensure that one flip message
10636 * can be sent by waiting for flip-done prior to queueing new flips).
10637 * Experimentation says that BCS works despite DERRMR masking all
10638 * flip-done completion events and that unmasking all planes at once
10639 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10640 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10641 */
10642 if (ring->id == RCS) {
10643 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10644 intel_ring_emit(ring, DERRMR);
10645 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10646 DERRMR_PIPEB_PRI_FLIP_DONE |
10647 DERRMR_PIPEC_PRI_FLIP_DONE));
10648 if (IS_GEN8(dev))
10649 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10650 MI_SRM_LRM_GLOBAL_GTT);
10651 else
10652 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10653 MI_SRM_LRM_GLOBAL_GTT);
10654 intel_ring_emit(ring, DERRMR);
10655 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10656 if (IS_GEN8(dev)) {
10657 intel_ring_emit(ring, 0);
10658 intel_ring_emit(ring, MI_NOOP);
10659 }
10660 }
10661
10662 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10663 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10664 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10665 intel_ring_emit(ring, (MI_NOOP));
10666
10667 intel_mark_page_flip_active(intel_crtc);
10668 __intel_ring_advance(ring);
10669 return 0;
10670 }
10671
10672 static bool use_mmio_flip(struct intel_engine_cs *ring,
10673 struct drm_i915_gem_object *obj)
10674 {
10675 /*
10676 * This is not being used for older platforms, because
10677 * non-availability of flip done interrupt forces us to use
10678 * CS flips. Older platforms derive flip done using some clever
10679 * tricks involving the flip_pending status bits and vblank irqs.
10680 * So using MMIO flips there would disrupt this mechanism.
10681 */
10682
10683 if (ring == NULL)
10684 return true;
10685
10686 if (INTEL_INFO(ring->dev)->gen < 5)
10687 return false;
10688
10689 if (i915.use_mmio_flip < 0)
10690 return false;
10691 else if (i915.use_mmio_flip > 0)
10692 return true;
10693 else if (i915.enable_execlists)
10694 return true;
10695 else
10696 return ring != i915_gem_request_get_ring(obj->last_read_req);
10697 }
10698
10699 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10700 {
10701 struct drm_device *dev = intel_crtc->base.dev;
10702 struct drm_i915_private *dev_priv = dev->dev_private;
10703 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10704 const enum pipe pipe = intel_crtc->pipe;
10705 u32 ctl, stride;
10706
10707 ctl = I915_READ(PLANE_CTL(pipe, 0));
10708 ctl &= ~PLANE_CTL_TILED_MASK;
10709 switch (fb->modifier[0]) {
10710 case DRM_FORMAT_MOD_NONE:
10711 break;
10712 case I915_FORMAT_MOD_X_TILED:
10713 ctl |= PLANE_CTL_TILED_X;
10714 break;
10715 case I915_FORMAT_MOD_Y_TILED:
10716 ctl |= PLANE_CTL_TILED_Y;
10717 break;
10718 case I915_FORMAT_MOD_Yf_TILED:
10719 ctl |= PLANE_CTL_TILED_YF;
10720 break;
10721 default:
10722 MISSING_CASE(fb->modifier[0]);
10723 }
10724
10725 /*
10726 * The stride is either expressed as a multiple of 64 bytes chunks for
10727 * linear buffers or in number of tiles for tiled buffers.
10728 */
10729 stride = fb->pitches[0] /
10730 intel_fb_stride_alignment(dev, fb->modifier[0],
10731 fb->pixel_format);
10732
10733 /*
10734 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10735 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10736 */
10737 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10738 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10739
10740 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10741 POSTING_READ(PLANE_SURF(pipe, 0));
10742 }
10743
10744 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10745 {
10746 struct drm_device *dev = intel_crtc->base.dev;
10747 struct drm_i915_private *dev_priv = dev->dev_private;
10748 struct intel_framebuffer *intel_fb =
10749 to_intel_framebuffer(intel_crtc->base.primary->fb);
10750 struct drm_i915_gem_object *obj = intel_fb->obj;
10751 u32 dspcntr;
10752 u32 reg;
10753
10754 reg = DSPCNTR(intel_crtc->plane);
10755 dspcntr = I915_READ(reg);
10756
10757 if (obj->tiling_mode != I915_TILING_NONE)
10758 dspcntr |= DISPPLANE_TILED;
10759 else
10760 dspcntr &= ~DISPPLANE_TILED;
10761
10762 I915_WRITE(reg, dspcntr);
10763
10764 I915_WRITE(DSPSURF(intel_crtc->plane),
10765 intel_crtc->unpin_work->gtt_offset);
10766 POSTING_READ(DSPSURF(intel_crtc->plane));
10767
10768 }
10769
10770 /*
10771 * XXX: This is the temporary way to update the plane registers until we get
10772 * around to using the usual plane update functions for MMIO flips
10773 */
10774 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10775 {
10776 struct drm_device *dev = intel_crtc->base.dev;
10777 bool atomic_update;
10778 u32 start_vbl_count;
10779
10780 intel_mark_page_flip_active(intel_crtc);
10781
10782 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10783
10784 if (INTEL_INFO(dev)->gen >= 9)
10785 skl_do_mmio_flip(intel_crtc);
10786 else
10787 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10788 ilk_do_mmio_flip(intel_crtc);
10789
10790 if (atomic_update)
10791 intel_pipe_update_end(intel_crtc, start_vbl_count);
10792 }
10793
10794 static void intel_mmio_flip_work_func(struct work_struct *work)
10795 {
10796 struct intel_crtc *crtc =
10797 container_of(work, struct intel_crtc, mmio_flip.work);
10798 struct intel_mmio_flip *mmio_flip;
10799
10800 mmio_flip = &crtc->mmio_flip;
10801 if (mmio_flip->req)
10802 WARN_ON(__i915_wait_request(mmio_flip->req,
10803 crtc->reset_counter,
10804 false, NULL, NULL) != 0);
10805
10806 intel_do_mmio_flip(crtc);
10807 if (mmio_flip->req) {
10808 mutex_lock(&crtc->base.dev->struct_mutex);
10809 i915_gem_request_assign(&mmio_flip->req, NULL);
10810 mutex_unlock(&crtc->base.dev->struct_mutex);
10811 }
10812 }
10813
10814 static int intel_queue_mmio_flip(struct drm_device *dev,
10815 struct drm_crtc *crtc,
10816 struct drm_framebuffer *fb,
10817 struct drm_i915_gem_object *obj,
10818 struct intel_engine_cs *ring,
10819 uint32_t flags)
10820 {
10821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10822
10823 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10824 obj->last_write_req);
10825
10826 schedule_work(&intel_crtc->mmio_flip.work);
10827
10828 return 0;
10829 }
10830
10831 static int intel_default_queue_flip(struct drm_device *dev,
10832 struct drm_crtc *crtc,
10833 struct drm_framebuffer *fb,
10834 struct drm_i915_gem_object *obj,
10835 struct intel_engine_cs *ring,
10836 uint32_t flags)
10837 {
10838 return -ENODEV;
10839 }
10840
10841 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10842 struct drm_crtc *crtc)
10843 {
10844 struct drm_i915_private *dev_priv = dev->dev_private;
10845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10846 struct intel_unpin_work *work = intel_crtc->unpin_work;
10847 u32 addr;
10848
10849 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10850 return true;
10851
10852 if (!work->enable_stall_check)
10853 return false;
10854
10855 if (work->flip_ready_vblank == 0) {
10856 if (work->flip_queued_req &&
10857 !i915_gem_request_completed(work->flip_queued_req, true))
10858 return false;
10859
10860 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10861 }
10862
10863 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10864 return false;
10865
10866 /* Potential stall - if we see that the flip has happened,
10867 * assume a missed interrupt. */
10868 if (INTEL_INFO(dev)->gen >= 4)
10869 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10870 else
10871 addr = I915_READ(DSPADDR(intel_crtc->plane));
10872
10873 /* There is a potential issue here with a false positive after a flip
10874 * to the same address. We could address this by checking for a
10875 * non-incrementing frame counter.
10876 */
10877 return addr == work->gtt_offset;
10878 }
10879
10880 void intel_check_page_flip(struct drm_device *dev, int pipe)
10881 {
10882 struct drm_i915_private *dev_priv = dev->dev_private;
10883 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10885 struct intel_unpin_work *work;
10886
10887 WARN_ON(!in_interrupt());
10888
10889 if (crtc == NULL)
10890 return;
10891
10892 spin_lock(&dev->event_lock);
10893 work = intel_crtc->unpin_work;
10894 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10895 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10896 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10897 page_flip_completed(intel_crtc);
10898 work = NULL;
10899 }
10900 if (work != NULL &&
10901 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10902 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10903 spin_unlock(&dev->event_lock);
10904 }
10905
10906 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10907 struct drm_framebuffer *fb,
10908 struct drm_pending_vblank_event *event,
10909 uint32_t page_flip_flags)
10910 {
10911 struct drm_device *dev = crtc->dev;
10912 struct drm_i915_private *dev_priv = dev->dev_private;
10913 struct drm_framebuffer *old_fb = crtc->primary->fb;
10914 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10916 struct drm_plane *primary = crtc->primary;
10917 enum pipe pipe = intel_crtc->pipe;
10918 struct intel_unpin_work *work;
10919 struct intel_engine_cs *ring;
10920 bool mmio_flip;
10921 int ret;
10922
10923 /*
10924 * drm_mode_page_flip_ioctl() should already catch this, but double
10925 * check to be safe. In the future we may enable pageflipping from
10926 * a disabled primary plane.
10927 */
10928 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10929 return -EBUSY;
10930
10931 /* Can't change pixel format via MI display flips. */
10932 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10933 return -EINVAL;
10934
10935 /*
10936 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10937 * Note that pitch changes could also affect these register.
10938 */
10939 if (INTEL_INFO(dev)->gen > 3 &&
10940 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10941 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10942 return -EINVAL;
10943
10944 if (i915_terminally_wedged(&dev_priv->gpu_error))
10945 goto out_hang;
10946
10947 work = kzalloc(sizeof(*work), GFP_KERNEL);
10948 if (work == NULL)
10949 return -ENOMEM;
10950
10951 work->event = event;
10952 work->crtc = crtc;
10953 work->old_fb = old_fb;
10954 INIT_WORK(&work->work, intel_unpin_work_fn);
10955
10956 ret = drm_crtc_vblank_get(crtc);
10957 if (ret)
10958 goto free_work;
10959
10960 /* We borrow the event spin lock for protecting unpin_work */
10961 spin_lock_irq(&dev->event_lock);
10962 if (intel_crtc->unpin_work) {
10963 /* Before declaring the flip queue wedged, check if
10964 * the hardware completed the operation behind our backs.
10965 */
10966 if (__intel_pageflip_stall_check(dev, crtc)) {
10967 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10968 page_flip_completed(intel_crtc);
10969 } else {
10970 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10971 spin_unlock_irq(&dev->event_lock);
10972
10973 drm_crtc_vblank_put(crtc);
10974 kfree(work);
10975 return -EBUSY;
10976 }
10977 }
10978 intel_crtc->unpin_work = work;
10979 spin_unlock_irq(&dev->event_lock);
10980
10981 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10982 flush_workqueue(dev_priv->wq);
10983
10984 /* Reference the objects for the scheduled work. */
10985 drm_framebuffer_reference(work->old_fb);
10986 drm_gem_object_reference(&obj->base);
10987
10988 crtc->primary->fb = fb;
10989 update_state_fb(crtc->primary);
10990
10991 work->pending_flip_obj = obj;
10992
10993 ret = i915_mutex_lock_interruptible(dev);
10994 if (ret)
10995 goto cleanup;
10996
10997 atomic_inc(&intel_crtc->unpin_work_count);
10998 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10999
11000 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11001 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11002
11003 if (IS_VALLEYVIEW(dev)) {
11004 ring = &dev_priv->ring[BCS];
11005 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11006 /* vlv: DISPLAY_FLIP fails to change tiling */
11007 ring = NULL;
11008 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11009 ring = &dev_priv->ring[BCS];
11010 } else if (INTEL_INFO(dev)->gen >= 7) {
11011 ring = i915_gem_request_get_ring(obj->last_read_req);
11012 if (ring == NULL || ring->id != RCS)
11013 ring = &dev_priv->ring[BCS];
11014 } else {
11015 ring = &dev_priv->ring[RCS];
11016 }
11017
11018 mmio_flip = use_mmio_flip(ring, obj);
11019
11020 /* When using CS flips, we want to emit semaphores between rings.
11021 * However, when using mmio flips we will create a task to do the
11022 * synchronisation, so all we want here is to pin the framebuffer
11023 * into the display plane and skip any waits.
11024 */
11025 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11026 crtc->primary->state,
11027 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11028 if (ret)
11029 goto cleanup_pending;
11030
11031 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11032 + intel_crtc->dspaddr_offset;
11033
11034 if (mmio_flip) {
11035 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11036 page_flip_flags);
11037 if (ret)
11038 goto cleanup_unpin;
11039
11040 i915_gem_request_assign(&work->flip_queued_req,
11041 obj->last_write_req);
11042 } else {
11043 if (obj->last_write_req) {
11044 ret = i915_gem_check_olr(obj->last_write_req);
11045 if (ret)
11046 goto cleanup_unpin;
11047 }
11048
11049 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11050 page_flip_flags);
11051 if (ret)
11052 goto cleanup_unpin;
11053
11054 i915_gem_request_assign(&work->flip_queued_req,
11055 intel_ring_get_request(ring));
11056 }
11057
11058 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11059 work->enable_stall_check = true;
11060
11061 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11062 INTEL_FRONTBUFFER_PRIMARY(pipe));
11063
11064 intel_fbc_disable(dev);
11065 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11066 mutex_unlock(&dev->struct_mutex);
11067
11068 trace_i915_flip_request(intel_crtc->plane, obj);
11069
11070 return 0;
11071
11072 cleanup_unpin:
11073 intel_unpin_fb_obj(fb, crtc->primary->state);
11074 cleanup_pending:
11075 atomic_dec(&intel_crtc->unpin_work_count);
11076 mutex_unlock(&dev->struct_mutex);
11077 cleanup:
11078 crtc->primary->fb = old_fb;
11079 update_state_fb(crtc->primary);
11080
11081 drm_gem_object_unreference_unlocked(&obj->base);
11082 drm_framebuffer_unreference(work->old_fb);
11083
11084 spin_lock_irq(&dev->event_lock);
11085 intel_crtc->unpin_work = NULL;
11086 spin_unlock_irq(&dev->event_lock);
11087
11088 drm_crtc_vblank_put(crtc);
11089 free_work:
11090 kfree(work);
11091
11092 if (ret == -EIO) {
11093 out_hang:
11094 ret = intel_plane_restore(primary);
11095 if (ret == 0 && event) {
11096 spin_lock_irq(&dev->event_lock);
11097 drm_send_vblank_event(dev, pipe, event);
11098 spin_unlock_irq(&dev->event_lock);
11099 }
11100 }
11101 return ret;
11102 }
11103
11104 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11105 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11106 .load_lut = intel_crtc_load_lut,
11107 .atomic_begin = intel_begin_crtc_commit,
11108 .atomic_flush = intel_finish_crtc_commit,
11109 };
11110
11111 /**
11112 * intel_modeset_update_staged_output_state
11113 *
11114 * Updates the staged output configuration state, e.g. after we've read out the
11115 * current hw state.
11116 */
11117 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11118 {
11119 struct intel_crtc *crtc;
11120 struct intel_encoder *encoder;
11121 struct intel_connector *connector;
11122
11123 for_each_intel_connector(dev, connector) {
11124 connector->new_encoder =
11125 to_intel_encoder(connector->base.encoder);
11126 }
11127
11128 for_each_intel_encoder(dev, encoder) {
11129 encoder->new_crtc =
11130 to_intel_crtc(encoder->base.crtc);
11131 }
11132
11133 for_each_intel_crtc(dev, crtc) {
11134 crtc->new_enabled = crtc->base.state->enable;
11135 }
11136 }
11137
11138 /* Transitional helper to copy current connector/encoder state to
11139 * connector->state. This is needed so that code that is partially
11140 * converted to atomic does the right thing.
11141 */
11142 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11143 {
11144 struct intel_connector *connector;
11145
11146 for_each_intel_connector(dev, connector) {
11147 if (connector->base.encoder) {
11148 connector->base.state->best_encoder =
11149 connector->base.encoder;
11150 connector->base.state->crtc =
11151 connector->base.encoder->crtc;
11152 } else {
11153 connector->base.state->best_encoder = NULL;
11154 connector->base.state->crtc = NULL;
11155 }
11156 }
11157 }
11158
11159 /* Fixup legacy state after an atomic state swap.
11160 */
11161 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11162 {
11163 struct intel_crtc *crtc;
11164 struct intel_encoder *encoder;
11165 struct intel_connector *connector;
11166
11167 for_each_intel_connector(state->dev, connector) {
11168 connector->base.encoder = connector->base.state->best_encoder;
11169 if (connector->base.encoder)
11170 connector->base.encoder->crtc =
11171 connector->base.state->crtc;
11172 }
11173
11174 /* Update crtc of disabled encoders */
11175 for_each_intel_encoder(state->dev, encoder) {
11176 int num_connectors = 0;
11177
11178 for_each_intel_connector(state->dev, connector)
11179 if (connector->base.encoder == &encoder->base)
11180 num_connectors++;
11181
11182 if (num_connectors == 0)
11183 encoder->base.crtc = NULL;
11184 }
11185
11186 for_each_intel_crtc(state->dev, crtc) {
11187 crtc->base.enabled = crtc->base.state->enable;
11188 crtc->config = to_intel_crtc_state(crtc->base.state);
11189 }
11190
11191 /* Copy the new configuration to the staged state, to keep the few
11192 * pieces of code that haven't been converted yet happy */
11193 intel_modeset_update_staged_output_state(state->dev);
11194 }
11195
11196 static void
11197 connected_sink_compute_bpp(struct intel_connector *connector,
11198 struct intel_crtc_state *pipe_config)
11199 {
11200 int bpp = pipe_config->pipe_bpp;
11201
11202 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11203 connector->base.base.id,
11204 connector->base.name);
11205
11206 /* Don't use an invalid EDID bpc value */
11207 if (connector->base.display_info.bpc &&
11208 connector->base.display_info.bpc * 3 < bpp) {
11209 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11210 bpp, connector->base.display_info.bpc*3);
11211 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11212 }
11213
11214 /* Clamp bpp to 8 on screens without EDID 1.4 */
11215 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11216 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11217 bpp);
11218 pipe_config->pipe_bpp = 24;
11219 }
11220 }
11221
11222 static int
11223 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11224 struct intel_crtc_state *pipe_config)
11225 {
11226 struct drm_device *dev = crtc->base.dev;
11227 struct drm_atomic_state *state;
11228 struct drm_connector *connector;
11229 struct drm_connector_state *connector_state;
11230 int bpp, i;
11231
11232 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11233 bpp = 10*3;
11234 else if (INTEL_INFO(dev)->gen >= 5)
11235 bpp = 12*3;
11236 else
11237 bpp = 8*3;
11238
11239
11240 pipe_config->pipe_bpp = bpp;
11241
11242 state = pipe_config->base.state;
11243
11244 /* Clamp display bpp to EDID value */
11245 for_each_connector_in_state(state, connector, connector_state, i) {
11246 if (connector_state->crtc != &crtc->base)
11247 continue;
11248
11249 connected_sink_compute_bpp(to_intel_connector(connector),
11250 pipe_config);
11251 }
11252
11253 return bpp;
11254 }
11255
11256 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11257 {
11258 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11259 "type: 0x%x flags: 0x%x\n",
11260 mode->crtc_clock,
11261 mode->crtc_hdisplay, mode->crtc_hsync_start,
11262 mode->crtc_hsync_end, mode->crtc_htotal,
11263 mode->crtc_vdisplay, mode->crtc_vsync_start,
11264 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11265 }
11266
11267 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11268 struct intel_crtc_state *pipe_config,
11269 const char *context)
11270 {
11271 struct drm_device *dev = crtc->base.dev;
11272 struct drm_plane *plane;
11273 struct intel_plane *intel_plane;
11274 struct intel_plane_state *state;
11275 struct drm_framebuffer *fb;
11276
11277 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11278 context, pipe_config, pipe_name(crtc->pipe));
11279
11280 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11281 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11282 pipe_config->pipe_bpp, pipe_config->dither);
11283 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11284 pipe_config->has_pch_encoder,
11285 pipe_config->fdi_lanes,
11286 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11287 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11288 pipe_config->fdi_m_n.tu);
11289 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11290 pipe_config->has_dp_encoder,
11291 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11292 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11293 pipe_config->dp_m_n.tu);
11294
11295 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11296 pipe_config->has_dp_encoder,
11297 pipe_config->dp_m2_n2.gmch_m,
11298 pipe_config->dp_m2_n2.gmch_n,
11299 pipe_config->dp_m2_n2.link_m,
11300 pipe_config->dp_m2_n2.link_n,
11301 pipe_config->dp_m2_n2.tu);
11302
11303 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11304 pipe_config->has_audio,
11305 pipe_config->has_infoframe);
11306
11307 DRM_DEBUG_KMS("requested mode:\n");
11308 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11309 DRM_DEBUG_KMS("adjusted mode:\n");
11310 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11311 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11312 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11313 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11314 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11315 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11316 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11317 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
11318 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11319 pipe_config->gmch_pfit.control,
11320 pipe_config->gmch_pfit.pgm_ratios,
11321 pipe_config->gmch_pfit.lvds_border_bits);
11322 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11323 pipe_config->pch_pfit.pos,
11324 pipe_config->pch_pfit.size,
11325 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11326 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11327 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11328
11329 DRM_DEBUG_KMS("planes on this crtc\n");
11330 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11331 intel_plane = to_intel_plane(plane);
11332 if (intel_plane->pipe != crtc->pipe)
11333 continue;
11334
11335 state = to_intel_plane_state(plane->state);
11336 fb = state->base.fb;
11337 if (!fb) {
11338 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11339 "disabled, scaler_id = %d\n",
11340 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11341 plane->base.id, intel_plane->pipe,
11342 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11343 drm_plane_index(plane), state->scaler_id);
11344 continue;
11345 }
11346
11347 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11348 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11349 plane->base.id, intel_plane->pipe,
11350 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11351 drm_plane_index(plane));
11352 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11353 fb->base.id, fb->width, fb->height, fb->pixel_format);
11354 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11355 state->scaler_id,
11356 state->src.x1 >> 16, state->src.y1 >> 16,
11357 drm_rect_width(&state->src) >> 16,
11358 drm_rect_height(&state->src) >> 16,
11359 state->dst.x1, state->dst.y1,
11360 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11361 }
11362 }
11363
11364 static bool encoders_cloneable(const struct intel_encoder *a,
11365 const struct intel_encoder *b)
11366 {
11367 /* masks could be asymmetric, so check both ways */
11368 return a == b || (a->cloneable & (1 << b->type) &&
11369 b->cloneable & (1 << a->type));
11370 }
11371
11372 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11373 struct intel_crtc *crtc,
11374 struct intel_encoder *encoder)
11375 {
11376 struct intel_encoder *source_encoder;
11377 struct drm_connector *connector;
11378 struct drm_connector_state *connector_state;
11379 int i;
11380
11381 for_each_connector_in_state(state, connector, connector_state, i) {
11382 if (connector_state->crtc != &crtc->base)
11383 continue;
11384
11385 source_encoder =
11386 to_intel_encoder(connector_state->best_encoder);
11387 if (!encoders_cloneable(encoder, source_encoder))
11388 return false;
11389 }
11390
11391 return true;
11392 }
11393
11394 static bool check_encoder_cloning(struct drm_atomic_state *state,
11395 struct intel_crtc *crtc)
11396 {
11397 struct intel_encoder *encoder;
11398 struct drm_connector *connector;
11399 struct drm_connector_state *connector_state;
11400 int i;
11401
11402 for_each_connector_in_state(state, connector, connector_state, i) {
11403 if (connector_state->crtc != &crtc->base)
11404 continue;
11405
11406 encoder = to_intel_encoder(connector_state->best_encoder);
11407 if (!check_single_encoder_cloning(state, crtc, encoder))
11408 return false;
11409 }
11410
11411 return true;
11412 }
11413
11414 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11415 {
11416 struct drm_device *dev = state->dev;
11417 struct intel_encoder *encoder;
11418 struct drm_connector *connector;
11419 struct drm_connector_state *connector_state;
11420 unsigned int used_ports = 0;
11421 int i;
11422
11423 /*
11424 * Walk the connector list instead of the encoder
11425 * list to detect the problem on ddi platforms
11426 * where there's just one encoder per digital port.
11427 */
11428 for_each_connector_in_state(state, connector, connector_state, i) {
11429 if (!connector_state->best_encoder)
11430 continue;
11431
11432 encoder = to_intel_encoder(connector_state->best_encoder);
11433
11434 WARN_ON(!connector_state->crtc);
11435
11436 switch (encoder->type) {
11437 unsigned int port_mask;
11438 case INTEL_OUTPUT_UNKNOWN:
11439 if (WARN_ON(!HAS_DDI(dev)))
11440 break;
11441 case INTEL_OUTPUT_DISPLAYPORT:
11442 case INTEL_OUTPUT_HDMI:
11443 case INTEL_OUTPUT_EDP:
11444 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11445
11446 /* the same port mustn't appear more than once */
11447 if (used_ports & port_mask)
11448 return false;
11449
11450 used_ports |= port_mask;
11451 default:
11452 break;
11453 }
11454 }
11455
11456 return true;
11457 }
11458
11459 static void
11460 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11461 {
11462 struct drm_crtc_state tmp_state;
11463 struct intel_crtc_scaler_state scaler_state;
11464 struct intel_dpll_hw_state dpll_hw_state;
11465 enum intel_dpll_id shared_dpll;
11466
11467 /* Clear only the intel specific part of the crtc state excluding scalers */
11468 tmp_state = crtc_state->base;
11469 scaler_state = crtc_state->scaler_state;
11470 shared_dpll = crtc_state->shared_dpll;
11471 dpll_hw_state = crtc_state->dpll_hw_state;
11472
11473 memset(crtc_state, 0, sizeof *crtc_state);
11474
11475 crtc_state->base = tmp_state;
11476 crtc_state->scaler_state = scaler_state;
11477 crtc_state->shared_dpll = shared_dpll;
11478 crtc_state->dpll_hw_state = dpll_hw_state;
11479 }
11480
11481 static int
11482 intel_modeset_pipe_config(struct drm_crtc *crtc,
11483 struct drm_atomic_state *state,
11484 struct intel_crtc_state *pipe_config)
11485 {
11486 struct intel_encoder *encoder;
11487 struct drm_connector *connector;
11488 struct drm_connector_state *connector_state;
11489 int base_bpp, ret = -EINVAL;
11490 int i;
11491 bool retry = true;
11492
11493 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11494 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11495 return -EINVAL;
11496 }
11497
11498 if (!check_digital_port_conflicts(state)) {
11499 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11500 return -EINVAL;
11501 }
11502
11503 clear_intel_crtc_state(pipe_config);
11504
11505 pipe_config->cpu_transcoder =
11506 (enum transcoder) to_intel_crtc(crtc)->pipe;
11507
11508 /*
11509 * Sanitize sync polarity flags based on requested ones. If neither
11510 * positive or negative polarity is requested, treat this as meaning
11511 * negative polarity.
11512 */
11513 if (!(pipe_config->base.adjusted_mode.flags &
11514 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11515 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11516
11517 if (!(pipe_config->base.adjusted_mode.flags &
11518 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11519 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11520
11521 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11522 * plane pixel format and any sink constraints into account. Returns the
11523 * source plane bpp so that dithering can be selected on mismatches
11524 * after encoders and crtc also have had their say. */
11525 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11526 pipe_config);
11527 if (base_bpp < 0)
11528 goto fail;
11529
11530 /*
11531 * Determine the real pipe dimensions. Note that stereo modes can
11532 * increase the actual pipe size due to the frame doubling and
11533 * insertion of additional space for blanks between the frame. This
11534 * is stored in the crtc timings. We use the requested mode to do this
11535 * computation to clearly distinguish it from the adjusted mode, which
11536 * can be changed by the connectors in the below retry loop.
11537 */
11538 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11539 &pipe_config->pipe_src_w,
11540 &pipe_config->pipe_src_h);
11541
11542 encoder_retry:
11543 /* Ensure the port clock defaults are reset when retrying. */
11544 pipe_config->port_clock = 0;
11545 pipe_config->pixel_multiplier = 1;
11546
11547 /* Fill in default crtc timings, allow encoders to overwrite them. */
11548 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11549 CRTC_STEREO_DOUBLE);
11550
11551 /* Pass our mode to the connectors and the CRTC to give them a chance to
11552 * adjust it according to limitations or connector properties, and also
11553 * a chance to reject the mode entirely.
11554 */
11555 for_each_connector_in_state(state, connector, connector_state, i) {
11556 if (connector_state->crtc != crtc)
11557 continue;
11558
11559 encoder = to_intel_encoder(connector_state->best_encoder);
11560
11561 if (!(encoder->compute_config(encoder, pipe_config))) {
11562 DRM_DEBUG_KMS("Encoder config failure\n");
11563 goto fail;
11564 }
11565 }
11566
11567 /* Set default port clock if not overwritten by the encoder. Needs to be
11568 * done afterwards in case the encoder adjusts the mode. */
11569 if (!pipe_config->port_clock)
11570 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11571 * pipe_config->pixel_multiplier;
11572
11573 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11574 if (ret < 0) {
11575 DRM_DEBUG_KMS("CRTC fixup failed\n");
11576 goto fail;
11577 }
11578
11579 if (ret == RETRY) {
11580 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11581 ret = -EINVAL;
11582 goto fail;
11583 }
11584
11585 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11586 retry = false;
11587 goto encoder_retry;
11588 }
11589
11590 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11591 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11592 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11593
11594 return 0;
11595 fail:
11596 return ret;
11597 }
11598
11599 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11600 {
11601 struct drm_encoder *encoder;
11602 struct drm_device *dev = crtc->dev;
11603
11604 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11605 if (encoder->crtc == crtc)
11606 return true;
11607
11608 return false;
11609 }
11610
11611 static bool
11612 needs_modeset(struct drm_crtc_state *state)
11613 {
11614 return state->mode_changed || state->active_changed;
11615 }
11616
11617 static void
11618 intel_modeset_update_state(struct drm_atomic_state *state)
11619 {
11620 struct drm_device *dev = state->dev;
11621 struct drm_i915_private *dev_priv = dev->dev_private;
11622 struct intel_encoder *intel_encoder;
11623 struct drm_crtc *crtc;
11624 struct drm_crtc_state *crtc_state;
11625 struct drm_connector *connector;
11626 int i;
11627
11628 intel_shared_dpll_commit(dev_priv);
11629
11630 for_each_intel_encoder(dev, intel_encoder) {
11631 if (!intel_encoder->base.crtc)
11632 continue;
11633
11634 for_each_crtc_in_state(state, crtc, crtc_state, i)
11635 if (crtc == intel_encoder->base.crtc)
11636 break;
11637
11638 if (crtc != intel_encoder->base.crtc)
11639 continue;
11640
11641 if (crtc_state->enable && needs_modeset(crtc_state))
11642 intel_encoder->connectors_active = false;
11643 }
11644
11645 drm_atomic_helper_swap_state(state->dev, state);
11646 intel_modeset_fixup_state(state);
11647
11648 /* Double check state. */
11649 for_each_crtc(dev, crtc) {
11650 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11651 }
11652
11653 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11654 if (!connector->encoder || !connector->encoder->crtc)
11655 continue;
11656
11657 for_each_crtc_in_state(state, crtc, crtc_state, i)
11658 if (crtc == connector->encoder->crtc)
11659 break;
11660
11661 if (crtc != connector->encoder->crtc)
11662 continue;
11663
11664 if (crtc->state->enable && needs_modeset(crtc->state)) {
11665 struct drm_property *dpms_property =
11666 dev->mode_config.dpms_property;
11667
11668 connector->dpms = DRM_MODE_DPMS_ON;
11669 drm_object_property_set_value(&connector->base,
11670 dpms_property,
11671 DRM_MODE_DPMS_ON);
11672
11673 intel_encoder = to_intel_encoder(connector->encoder);
11674 intel_encoder->connectors_active = true;
11675 }
11676 }
11677
11678 }
11679
11680 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11681 {
11682 int diff;
11683
11684 if (clock1 == clock2)
11685 return true;
11686
11687 if (!clock1 || !clock2)
11688 return false;
11689
11690 diff = abs(clock1 - clock2);
11691
11692 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11693 return true;
11694
11695 return false;
11696 }
11697
11698 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11699 list_for_each_entry((intel_crtc), \
11700 &(dev)->mode_config.crtc_list, \
11701 base.head) \
11702 if (mask & (1 <<(intel_crtc)->pipe))
11703
11704 static bool
11705 intel_pipe_config_compare(struct drm_device *dev,
11706 struct intel_crtc_state *current_config,
11707 struct intel_crtc_state *pipe_config)
11708 {
11709 #define PIPE_CONF_CHECK_X(name) \
11710 if (current_config->name != pipe_config->name) { \
11711 DRM_ERROR("mismatch in " #name " " \
11712 "(expected 0x%08x, found 0x%08x)\n", \
11713 current_config->name, \
11714 pipe_config->name); \
11715 return false; \
11716 }
11717
11718 #define PIPE_CONF_CHECK_I(name) \
11719 if (current_config->name != pipe_config->name) { \
11720 DRM_ERROR("mismatch in " #name " " \
11721 "(expected %i, found %i)\n", \
11722 current_config->name, \
11723 pipe_config->name); \
11724 return false; \
11725 }
11726
11727 /* This is required for BDW+ where there is only one set of registers for
11728 * switching between high and low RR.
11729 * This macro can be used whenever a comparison has to be made between one
11730 * hw state and multiple sw state variables.
11731 */
11732 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11733 if ((current_config->name != pipe_config->name) && \
11734 (current_config->alt_name != pipe_config->name)) { \
11735 DRM_ERROR("mismatch in " #name " " \
11736 "(expected %i or %i, found %i)\n", \
11737 current_config->name, \
11738 current_config->alt_name, \
11739 pipe_config->name); \
11740 return false; \
11741 }
11742
11743 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11744 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11745 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11746 "(expected %i, found %i)\n", \
11747 current_config->name & (mask), \
11748 pipe_config->name & (mask)); \
11749 return false; \
11750 }
11751
11752 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11753 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11754 DRM_ERROR("mismatch in " #name " " \
11755 "(expected %i, found %i)\n", \
11756 current_config->name, \
11757 pipe_config->name); \
11758 return false; \
11759 }
11760
11761 #define PIPE_CONF_QUIRK(quirk) \
11762 ((current_config->quirks | pipe_config->quirks) & (quirk))
11763
11764 PIPE_CONF_CHECK_I(cpu_transcoder);
11765
11766 PIPE_CONF_CHECK_I(has_pch_encoder);
11767 PIPE_CONF_CHECK_I(fdi_lanes);
11768 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11769 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11770 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11771 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11772 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11773
11774 PIPE_CONF_CHECK_I(has_dp_encoder);
11775
11776 if (INTEL_INFO(dev)->gen < 8) {
11777 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11778 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11779 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11780 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11781 PIPE_CONF_CHECK_I(dp_m_n.tu);
11782
11783 if (current_config->has_drrs) {
11784 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11785 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11786 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11787 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11788 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11789 }
11790 } else {
11791 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11792 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11793 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11794 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11795 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11796 }
11797
11798 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11799 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11800 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11801 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11802 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11803 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11804
11805 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11806 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11807 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11808 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11809 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11810 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11811
11812 PIPE_CONF_CHECK_I(pixel_multiplier);
11813 PIPE_CONF_CHECK_I(has_hdmi_sink);
11814 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11815 IS_VALLEYVIEW(dev))
11816 PIPE_CONF_CHECK_I(limited_color_range);
11817 PIPE_CONF_CHECK_I(has_infoframe);
11818
11819 PIPE_CONF_CHECK_I(has_audio);
11820
11821 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11822 DRM_MODE_FLAG_INTERLACE);
11823
11824 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11825 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11826 DRM_MODE_FLAG_PHSYNC);
11827 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11828 DRM_MODE_FLAG_NHSYNC);
11829 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11830 DRM_MODE_FLAG_PVSYNC);
11831 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11832 DRM_MODE_FLAG_NVSYNC);
11833 }
11834
11835 PIPE_CONF_CHECK_I(pipe_src_w);
11836 PIPE_CONF_CHECK_I(pipe_src_h);
11837
11838 /*
11839 * FIXME: BIOS likes to set up a cloned config with lvds+external
11840 * screen. Since we don't yet re-compute the pipe config when moving
11841 * just the lvds port away to another pipe the sw tracking won't match.
11842 *
11843 * Proper atomic modesets with recomputed global state will fix this.
11844 * Until then just don't check gmch state for inherited modes.
11845 */
11846 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11847 PIPE_CONF_CHECK_I(gmch_pfit.control);
11848 /* pfit ratios are autocomputed by the hw on gen4+ */
11849 if (INTEL_INFO(dev)->gen < 4)
11850 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11851 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11852 }
11853
11854 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11855 if (current_config->pch_pfit.enabled) {
11856 PIPE_CONF_CHECK_I(pch_pfit.pos);
11857 PIPE_CONF_CHECK_I(pch_pfit.size);
11858 }
11859
11860 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11861
11862 /* BDW+ don't expose a synchronous way to read the state */
11863 if (IS_HASWELL(dev))
11864 PIPE_CONF_CHECK_I(ips_enabled);
11865
11866 PIPE_CONF_CHECK_I(double_wide);
11867
11868 PIPE_CONF_CHECK_X(ddi_pll_sel);
11869
11870 PIPE_CONF_CHECK_I(shared_dpll);
11871 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11872 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11873 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11874 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11875 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11876 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11877 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11878 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11879
11880 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11881 PIPE_CONF_CHECK_I(pipe_bpp);
11882
11883 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11884 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11885
11886 #undef PIPE_CONF_CHECK_X
11887 #undef PIPE_CONF_CHECK_I
11888 #undef PIPE_CONF_CHECK_I_ALT
11889 #undef PIPE_CONF_CHECK_FLAGS
11890 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11891 #undef PIPE_CONF_QUIRK
11892
11893 return true;
11894 }
11895
11896 static void check_wm_state(struct drm_device *dev)
11897 {
11898 struct drm_i915_private *dev_priv = dev->dev_private;
11899 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11900 struct intel_crtc *intel_crtc;
11901 int plane;
11902
11903 if (INTEL_INFO(dev)->gen < 9)
11904 return;
11905
11906 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11907 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11908
11909 for_each_intel_crtc(dev, intel_crtc) {
11910 struct skl_ddb_entry *hw_entry, *sw_entry;
11911 const enum pipe pipe = intel_crtc->pipe;
11912
11913 if (!intel_crtc->active)
11914 continue;
11915
11916 /* planes */
11917 for_each_plane(dev_priv, pipe, plane) {
11918 hw_entry = &hw_ddb.plane[pipe][plane];
11919 sw_entry = &sw_ddb->plane[pipe][plane];
11920
11921 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11922 continue;
11923
11924 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11925 "(expected (%u,%u), found (%u,%u))\n",
11926 pipe_name(pipe), plane + 1,
11927 sw_entry->start, sw_entry->end,
11928 hw_entry->start, hw_entry->end);
11929 }
11930
11931 /* cursor */
11932 hw_entry = &hw_ddb.cursor[pipe];
11933 sw_entry = &sw_ddb->cursor[pipe];
11934
11935 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11936 continue;
11937
11938 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11939 "(expected (%u,%u), found (%u,%u))\n",
11940 pipe_name(pipe),
11941 sw_entry->start, sw_entry->end,
11942 hw_entry->start, hw_entry->end);
11943 }
11944 }
11945
11946 static void
11947 check_connector_state(struct drm_device *dev)
11948 {
11949 struct intel_connector *connector;
11950
11951 for_each_intel_connector(dev, connector) {
11952 /* This also checks the encoder/connector hw state with the
11953 * ->get_hw_state callbacks. */
11954 intel_connector_check_state(connector);
11955
11956 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11957 "connector's staged encoder doesn't match current encoder\n");
11958 }
11959 }
11960
11961 static void
11962 check_encoder_state(struct drm_device *dev)
11963 {
11964 struct intel_encoder *encoder;
11965 struct intel_connector *connector;
11966
11967 for_each_intel_encoder(dev, encoder) {
11968 bool enabled = false;
11969 bool active = false;
11970 enum pipe pipe, tracked_pipe;
11971
11972 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11973 encoder->base.base.id,
11974 encoder->base.name);
11975
11976 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11977 "encoder's stage crtc doesn't match current crtc\n");
11978 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11979 "encoder's active_connectors set, but no crtc\n");
11980
11981 for_each_intel_connector(dev, connector) {
11982 if (connector->base.encoder != &encoder->base)
11983 continue;
11984 enabled = true;
11985 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11986 active = true;
11987 }
11988 /*
11989 * for MST connectors if we unplug the connector is gone
11990 * away but the encoder is still connected to a crtc
11991 * until a modeset happens in response to the hotplug.
11992 */
11993 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11994 continue;
11995
11996 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11997 "encoder's enabled state mismatch "
11998 "(expected %i, found %i)\n",
11999 !!encoder->base.crtc, enabled);
12000 I915_STATE_WARN(active && !encoder->base.crtc,
12001 "active encoder with no crtc\n");
12002
12003 I915_STATE_WARN(encoder->connectors_active != active,
12004 "encoder's computed active state doesn't match tracked active state "
12005 "(expected %i, found %i)\n", active, encoder->connectors_active);
12006
12007 active = encoder->get_hw_state(encoder, &pipe);
12008 I915_STATE_WARN(active != encoder->connectors_active,
12009 "encoder's hw state doesn't match sw tracking "
12010 "(expected %i, found %i)\n",
12011 encoder->connectors_active, active);
12012
12013 if (!encoder->base.crtc)
12014 continue;
12015
12016 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12017 I915_STATE_WARN(active && pipe != tracked_pipe,
12018 "active encoder's pipe doesn't match"
12019 "(expected %i, found %i)\n",
12020 tracked_pipe, pipe);
12021
12022 }
12023 }
12024
12025 static void
12026 check_crtc_state(struct drm_device *dev)
12027 {
12028 struct drm_i915_private *dev_priv = dev->dev_private;
12029 struct intel_crtc *crtc;
12030 struct intel_encoder *encoder;
12031 struct intel_crtc_state pipe_config;
12032
12033 for_each_intel_crtc(dev, crtc) {
12034 bool enabled = false;
12035 bool active = false;
12036
12037 memset(&pipe_config, 0, sizeof(pipe_config));
12038
12039 DRM_DEBUG_KMS("[CRTC:%d]\n",
12040 crtc->base.base.id);
12041
12042 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12043 "active crtc, but not enabled in sw tracking\n");
12044
12045 for_each_intel_encoder(dev, encoder) {
12046 if (encoder->base.crtc != &crtc->base)
12047 continue;
12048 enabled = true;
12049 if (encoder->connectors_active)
12050 active = true;
12051 }
12052
12053 I915_STATE_WARN(active != crtc->active,
12054 "crtc's computed active state doesn't match tracked active state "
12055 "(expected %i, found %i)\n", active, crtc->active);
12056 I915_STATE_WARN(enabled != crtc->base.state->enable,
12057 "crtc's computed enabled state doesn't match tracked enabled state "
12058 "(expected %i, found %i)\n", enabled,
12059 crtc->base.state->enable);
12060
12061 active = dev_priv->display.get_pipe_config(crtc,
12062 &pipe_config);
12063
12064 /* hw state is inconsistent with the pipe quirk */
12065 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12066 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12067 active = crtc->active;
12068
12069 for_each_intel_encoder(dev, encoder) {
12070 enum pipe pipe;
12071 if (encoder->base.crtc != &crtc->base)
12072 continue;
12073 if (encoder->get_hw_state(encoder, &pipe))
12074 encoder->get_config(encoder, &pipe_config);
12075 }
12076
12077 I915_STATE_WARN(crtc->active != active,
12078 "crtc active state doesn't match with hw state "
12079 "(expected %i, found %i)\n", crtc->active, active);
12080
12081 if (active &&
12082 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12083 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12084 intel_dump_pipe_config(crtc, &pipe_config,
12085 "[hw state]");
12086 intel_dump_pipe_config(crtc, crtc->config,
12087 "[sw state]");
12088 }
12089 }
12090 }
12091
12092 static void
12093 check_shared_dpll_state(struct drm_device *dev)
12094 {
12095 struct drm_i915_private *dev_priv = dev->dev_private;
12096 struct intel_crtc *crtc;
12097 struct intel_dpll_hw_state dpll_hw_state;
12098 int i;
12099
12100 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12101 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12102 int enabled_crtcs = 0, active_crtcs = 0;
12103 bool active;
12104
12105 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12106
12107 DRM_DEBUG_KMS("%s\n", pll->name);
12108
12109 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12110
12111 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12112 "more active pll users than references: %i vs %i\n",
12113 pll->active, hweight32(pll->config.crtc_mask));
12114 I915_STATE_WARN(pll->active && !pll->on,
12115 "pll in active use but not on in sw tracking\n");
12116 I915_STATE_WARN(pll->on && !pll->active,
12117 "pll in on but not on in use in sw tracking\n");
12118 I915_STATE_WARN(pll->on != active,
12119 "pll on state mismatch (expected %i, found %i)\n",
12120 pll->on, active);
12121
12122 for_each_intel_crtc(dev, crtc) {
12123 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12124 enabled_crtcs++;
12125 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12126 active_crtcs++;
12127 }
12128 I915_STATE_WARN(pll->active != active_crtcs,
12129 "pll active crtcs mismatch (expected %i, found %i)\n",
12130 pll->active, active_crtcs);
12131 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12132 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12133 hweight32(pll->config.crtc_mask), enabled_crtcs);
12134
12135 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12136 sizeof(dpll_hw_state)),
12137 "pll hw state mismatch\n");
12138 }
12139 }
12140
12141 void
12142 intel_modeset_check_state(struct drm_device *dev)
12143 {
12144 check_wm_state(dev);
12145 check_connector_state(dev);
12146 check_encoder_state(dev);
12147 check_crtc_state(dev);
12148 check_shared_dpll_state(dev);
12149 }
12150
12151 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12152 int dotclock)
12153 {
12154 /*
12155 * FDI already provided one idea for the dotclock.
12156 * Yell if the encoder disagrees.
12157 */
12158 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12159 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12160 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12161 }
12162
12163 static void update_scanline_offset(struct intel_crtc *crtc)
12164 {
12165 struct drm_device *dev = crtc->base.dev;
12166
12167 /*
12168 * The scanline counter increments at the leading edge of hsync.
12169 *
12170 * On most platforms it starts counting from vtotal-1 on the
12171 * first active line. That means the scanline counter value is
12172 * always one less than what we would expect. Ie. just after
12173 * start of vblank, which also occurs at start of hsync (on the
12174 * last active line), the scanline counter will read vblank_start-1.
12175 *
12176 * On gen2 the scanline counter starts counting from 1 instead
12177 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12178 * to keep the value positive), instead of adding one.
12179 *
12180 * On HSW+ the behaviour of the scanline counter depends on the output
12181 * type. For DP ports it behaves like most other platforms, but on HDMI
12182 * there's an extra 1 line difference. So we need to add two instead of
12183 * one to the value.
12184 */
12185 if (IS_GEN2(dev)) {
12186 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12187 int vtotal;
12188
12189 vtotal = mode->crtc_vtotal;
12190 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12191 vtotal /= 2;
12192
12193 crtc->scanline_offset = vtotal - 1;
12194 } else if (HAS_DDI(dev) &&
12195 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12196 crtc->scanline_offset = 2;
12197 } else
12198 crtc->scanline_offset = 1;
12199 }
12200
12201 static struct intel_crtc_state *
12202 intel_modeset_compute_config(struct drm_crtc *crtc,
12203 struct drm_atomic_state *state)
12204 {
12205 struct intel_crtc_state *pipe_config;
12206 int ret = 0;
12207
12208 ret = drm_atomic_add_affected_connectors(state, crtc);
12209 if (ret)
12210 return ERR_PTR(ret);
12211
12212 ret = drm_atomic_helper_check_modeset(state->dev, state);
12213 if (ret)
12214 return ERR_PTR(ret);
12215
12216 /*
12217 * Note this needs changes when we start tracking multiple modes
12218 * and crtcs. At that point we'll need to compute the whole config
12219 * (i.e. one pipe_config for each crtc) rather than just the one
12220 * for this crtc.
12221 */
12222 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12223 if (IS_ERR(pipe_config))
12224 return pipe_config;
12225
12226 if (!pipe_config->base.enable)
12227 return pipe_config;
12228
12229 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12230 if (ret)
12231 return ERR_PTR(ret);
12232
12233 /* Check things that can only be changed through modeset */
12234 if (pipe_config->has_audio !=
12235 to_intel_crtc(crtc)->config->has_audio)
12236 pipe_config->base.mode_changed = true;
12237
12238 /*
12239 * Note we have an issue here with infoframes: current code
12240 * only updates them on the full mode set path per hw
12241 * requirements. So here we should be checking for any
12242 * required changes and forcing a mode set.
12243 */
12244
12245 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12246
12247 ret = drm_atomic_helper_check_planes(state->dev, state);
12248 if (ret)
12249 return ERR_PTR(ret);
12250
12251 return pipe_config;
12252 }
12253
12254 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12255 {
12256 struct drm_device *dev = state->dev;
12257 struct drm_i915_private *dev_priv = to_i915(dev);
12258 unsigned clear_pipes = 0;
12259 struct intel_crtc *intel_crtc;
12260 struct intel_crtc_state *intel_crtc_state;
12261 struct drm_crtc *crtc;
12262 struct drm_crtc_state *crtc_state;
12263 int ret = 0;
12264 int i;
12265
12266 if (!dev_priv->display.crtc_compute_clock)
12267 return 0;
12268
12269 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12270 intel_crtc = to_intel_crtc(crtc);
12271 intel_crtc_state = to_intel_crtc_state(crtc_state);
12272
12273 if (needs_modeset(crtc_state)) {
12274 clear_pipes |= 1 << intel_crtc->pipe;
12275 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12276 memset(&intel_crtc_state->dpll_hw_state, 0,
12277 sizeof(intel_crtc_state->dpll_hw_state));
12278 }
12279 }
12280
12281 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12282 if (ret)
12283 goto done;
12284
12285 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12286 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12287 continue;
12288
12289 intel_crtc = to_intel_crtc(crtc);
12290 intel_crtc_state = to_intel_crtc_state(crtc_state);
12291
12292 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12293 intel_crtc_state);
12294 if (ret) {
12295 intel_shared_dpll_abort_config(dev_priv);
12296 goto done;
12297 }
12298 }
12299
12300 done:
12301 return ret;
12302 }
12303
12304 /* Code that should eventually be part of atomic_check() */
12305 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12306 {
12307 struct drm_device *dev = state->dev;
12308 int ret;
12309
12310 /*
12311 * See if the config requires any additional preparation, e.g.
12312 * to adjust global state with pipes off. We need to do this
12313 * here so we can get the modeset_pipe updated config for the new
12314 * mode set on this crtc. For other crtcs we need to use the
12315 * adjusted_mode bits in the crtc directly.
12316 */
12317 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12318 ret = valleyview_modeset_global_pipes(state);
12319 if (ret)
12320 return ret;
12321 }
12322
12323 ret = __intel_set_mode_setup_plls(state);
12324 if (ret)
12325 return ret;
12326
12327 return 0;
12328 }
12329
12330 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12331 struct intel_crtc_state *pipe_config)
12332 {
12333 struct drm_device *dev = modeset_crtc->dev;
12334 struct drm_i915_private *dev_priv = dev->dev_private;
12335 struct drm_atomic_state *state = pipe_config->base.state;
12336 struct drm_crtc *crtc;
12337 struct drm_crtc_state *crtc_state;
12338 int ret = 0;
12339 int i;
12340
12341 ret = __intel_set_mode_checks(state);
12342 if (ret < 0)
12343 return ret;
12344
12345 ret = drm_atomic_helper_prepare_planes(dev, state);
12346 if (ret)
12347 return ret;
12348
12349 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12350 if (!needs_modeset(crtc_state))
12351 continue;
12352
12353 if (!crtc_state->enable) {
12354 intel_crtc_disable(crtc);
12355 } else if (crtc->state->enable) {
12356 intel_crtc_disable_planes(crtc);
12357 dev_priv->display.crtc_disable(crtc);
12358 }
12359 }
12360
12361 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12362 * to set it here already despite that we pass it down the callchain.
12363 *
12364 * Note we'll need to fix this up when we start tracking multiple
12365 * pipes; here we assume a single modeset_pipe and only track the
12366 * single crtc and mode.
12367 */
12368 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12369 modeset_crtc->mode = pipe_config->base.mode;
12370
12371 /*
12372 * Calculate and store various constants which
12373 * are later needed by vblank and swap-completion
12374 * timestamping. They are derived from true hwmode.
12375 */
12376 drm_calc_timestamping_constants(modeset_crtc,
12377 &pipe_config->base.adjusted_mode);
12378 }
12379
12380 /* Only after disabling all output pipelines that will be changed can we
12381 * update the the output configuration. */
12382 intel_modeset_update_state(state);
12383
12384 /* The state has been swaped above, so state actually contains the
12385 * old state now. */
12386
12387 modeset_update_crtc_power_domains(state);
12388
12389 drm_atomic_helper_commit_planes(dev, state);
12390
12391 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12392 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12393 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12394 continue;
12395
12396 update_scanline_offset(to_intel_crtc(crtc));
12397
12398 dev_priv->display.crtc_enable(crtc);
12399 intel_crtc_enable_planes(crtc);
12400 }
12401
12402 /* FIXME: add subpixel order */
12403
12404 drm_atomic_helper_cleanup_planes(dev, state);
12405
12406 drm_atomic_state_free(state);
12407
12408 return 0;
12409 }
12410
12411 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12412 struct intel_crtc_state *pipe_config)
12413 {
12414 int ret;
12415
12416 ret = __intel_set_mode(crtc, pipe_config);
12417
12418 if (ret == 0)
12419 intel_modeset_check_state(crtc->dev);
12420
12421 return ret;
12422 }
12423
12424 static int intel_set_mode(struct drm_crtc *crtc,
12425 struct drm_atomic_state *state)
12426 {
12427 struct intel_crtc_state *pipe_config;
12428 int ret = 0;
12429
12430 pipe_config = intel_modeset_compute_config(crtc, state);
12431 if (IS_ERR(pipe_config)) {
12432 ret = PTR_ERR(pipe_config);
12433 goto out;
12434 }
12435
12436 ret = intel_set_mode_with_config(crtc, pipe_config);
12437 if (ret)
12438 goto out;
12439
12440 out:
12441 return ret;
12442 }
12443
12444 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12445 {
12446 struct drm_device *dev = crtc->dev;
12447 struct drm_atomic_state *state;
12448 struct intel_crtc *intel_crtc;
12449 struct intel_encoder *encoder;
12450 struct intel_connector *connector;
12451 struct drm_connector_state *connector_state;
12452 struct intel_crtc_state *crtc_state;
12453 int ret;
12454
12455 state = drm_atomic_state_alloc(dev);
12456 if (!state) {
12457 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12458 crtc->base.id);
12459 return;
12460 }
12461
12462 state->acquire_ctx = dev->mode_config.acquire_ctx;
12463
12464 /* The force restore path in the HW readout code relies on the staged
12465 * config still keeping the user requested config while the actual
12466 * state has been overwritten by the configuration read from HW. We
12467 * need to copy the staged config to the atomic state, otherwise the
12468 * mode set will just reapply the state the HW is already in. */
12469 for_each_intel_encoder(dev, encoder) {
12470 if (&encoder->new_crtc->base != crtc)
12471 continue;
12472
12473 for_each_intel_connector(dev, connector) {
12474 if (connector->new_encoder != encoder)
12475 continue;
12476
12477 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12478 if (IS_ERR(connector_state)) {
12479 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12480 connector->base.base.id,
12481 connector->base.name,
12482 PTR_ERR(connector_state));
12483 continue;
12484 }
12485
12486 connector_state->crtc = crtc;
12487 connector_state->best_encoder = &encoder->base;
12488 }
12489 }
12490
12491 for_each_intel_crtc(dev, intel_crtc) {
12492 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12493 continue;
12494
12495 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12496 if (IS_ERR(crtc_state)) {
12497 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12498 intel_crtc->base.base.id,
12499 PTR_ERR(crtc_state));
12500 continue;
12501 }
12502
12503 crtc_state->base.active = crtc_state->base.enable =
12504 intel_crtc->new_enabled;
12505
12506 if (&intel_crtc->base == crtc)
12507 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12508 }
12509
12510 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12511 crtc->primary->fb, crtc->x, crtc->y);
12512
12513 ret = intel_set_mode(crtc, state);
12514 if (ret)
12515 drm_atomic_state_free(state);
12516 }
12517
12518 #undef for_each_intel_crtc_masked
12519
12520 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12521 struct drm_mode_set *set)
12522 {
12523 int ro;
12524
12525 for (ro = 0; ro < set->num_connectors; ro++)
12526 if (set->connectors[ro] == &connector->base)
12527 return true;
12528
12529 return false;
12530 }
12531
12532 static int
12533 intel_modeset_stage_output_state(struct drm_device *dev,
12534 struct drm_mode_set *set,
12535 struct drm_atomic_state *state)
12536 {
12537 struct intel_connector *connector;
12538 struct drm_connector *drm_connector;
12539 struct drm_connector_state *connector_state;
12540 struct drm_crtc *crtc;
12541 struct drm_crtc_state *crtc_state;
12542 int i, ret;
12543
12544 /* The upper layers ensure that we either disable a crtc or have a list
12545 * of connectors. For paranoia, double-check this. */
12546 WARN_ON(!set->fb && (set->num_connectors != 0));
12547 WARN_ON(set->fb && (set->num_connectors == 0));
12548
12549 for_each_intel_connector(dev, connector) {
12550 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12551
12552 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12553 continue;
12554
12555 connector_state =
12556 drm_atomic_get_connector_state(state, &connector->base);
12557 if (IS_ERR(connector_state))
12558 return PTR_ERR(connector_state);
12559
12560 if (in_mode_set) {
12561 int pipe = to_intel_crtc(set->crtc)->pipe;
12562 connector_state->best_encoder =
12563 &intel_find_encoder(connector, pipe)->base;
12564 }
12565
12566 if (connector->base.state->crtc != set->crtc)
12567 continue;
12568
12569 /* If we disable the crtc, disable all its connectors. Also, if
12570 * the connector is on the changing crtc but not on the new
12571 * connector list, disable it. */
12572 if (!set->fb || !in_mode_set) {
12573 connector_state->best_encoder = NULL;
12574
12575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12576 connector->base.base.id,
12577 connector->base.name);
12578 }
12579 }
12580 /* connector->new_encoder is now updated for all connectors. */
12581
12582 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12583 connector = to_intel_connector(drm_connector);
12584
12585 if (!connector_state->best_encoder) {
12586 ret = drm_atomic_set_crtc_for_connector(connector_state,
12587 NULL);
12588 if (ret)
12589 return ret;
12590
12591 continue;
12592 }
12593
12594 if (intel_connector_in_mode_set(connector, set)) {
12595 struct drm_crtc *crtc = connector->base.state->crtc;
12596
12597 /* If this connector was in a previous crtc, add it
12598 * to the state. We might need to disable it. */
12599 if (crtc) {
12600 crtc_state =
12601 drm_atomic_get_crtc_state(state, crtc);
12602 if (IS_ERR(crtc_state))
12603 return PTR_ERR(crtc_state);
12604 }
12605
12606 ret = drm_atomic_set_crtc_for_connector(connector_state,
12607 set->crtc);
12608 if (ret)
12609 return ret;
12610 }
12611
12612 /* Make sure the new CRTC will work with the encoder */
12613 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12614 connector_state->crtc)) {
12615 return -EINVAL;
12616 }
12617
12618 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12619 connector->base.base.id,
12620 connector->base.name,
12621 connector_state->crtc->base.id);
12622
12623 if (connector_state->best_encoder != &connector->encoder->base)
12624 connector->encoder =
12625 to_intel_encoder(connector_state->best_encoder);
12626 }
12627
12628 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12629 bool has_connectors;
12630
12631 ret = drm_atomic_add_affected_connectors(state, crtc);
12632 if (ret)
12633 return ret;
12634
12635 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12636 if (has_connectors != crtc_state->enable)
12637 crtc_state->enable =
12638 crtc_state->active = has_connectors;
12639 }
12640
12641 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12642 set->fb, set->x, set->y);
12643 if (ret)
12644 return ret;
12645
12646 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12647 if (IS_ERR(crtc_state))
12648 return PTR_ERR(crtc_state);
12649
12650 if (set->mode)
12651 drm_mode_copy(&crtc_state->mode, set->mode);
12652
12653 if (set->num_connectors)
12654 crtc_state->active = true;
12655
12656 return 0;
12657 }
12658
12659 static bool primary_plane_visible(struct drm_crtc *crtc)
12660 {
12661 struct intel_plane_state *plane_state =
12662 to_intel_plane_state(crtc->primary->state);
12663
12664 return plane_state->visible;
12665 }
12666
12667 static int intel_crtc_set_config(struct drm_mode_set *set)
12668 {
12669 struct drm_device *dev;
12670 struct drm_atomic_state *state = NULL;
12671 struct intel_crtc_state *pipe_config;
12672 bool primary_plane_was_visible;
12673 int ret;
12674
12675 BUG_ON(!set);
12676 BUG_ON(!set->crtc);
12677 BUG_ON(!set->crtc->helper_private);
12678
12679 /* Enforce sane interface api - has been abused by the fb helper. */
12680 BUG_ON(!set->mode && set->fb);
12681 BUG_ON(set->fb && set->num_connectors == 0);
12682
12683 if (set->fb) {
12684 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12685 set->crtc->base.id, set->fb->base.id,
12686 (int)set->num_connectors, set->x, set->y);
12687 } else {
12688 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12689 }
12690
12691 dev = set->crtc->dev;
12692
12693 state = drm_atomic_state_alloc(dev);
12694 if (!state)
12695 return -ENOMEM;
12696
12697 state->acquire_ctx = dev->mode_config.acquire_ctx;
12698
12699 ret = intel_modeset_stage_output_state(dev, set, state);
12700 if (ret)
12701 goto out;
12702
12703 pipe_config = intel_modeset_compute_config(set->crtc, state);
12704 if (IS_ERR(pipe_config)) {
12705 ret = PTR_ERR(pipe_config);
12706 goto out;
12707 }
12708
12709 intel_update_pipe_size(to_intel_crtc(set->crtc));
12710
12711 primary_plane_was_visible = primary_plane_visible(set->crtc);
12712
12713 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12714
12715 if (ret == 0 &&
12716 pipe_config->base.enable &&
12717 pipe_config->base.planes_changed &&
12718 !needs_modeset(&pipe_config->base)) {
12719 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12720
12721 /*
12722 * We need to make sure the primary plane is re-enabled if it
12723 * has previously been turned off.
12724 */
12725 if (ret == 0 && !primary_plane_was_visible &&
12726 primary_plane_visible(set->crtc)) {
12727 WARN_ON(!intel_crtc->active);
12728 intel_post_enable_primary(set->crtc);
12729 }
12730
12731 /*
12732 * In the fastboot case this may be our only check of the
12733 * state after boot. It would be better to only do it on
12734 * the first update, but we don't have a nice way of doing that
12735 * (and really, set_config isn't used much for high freq page
12736 * flipping, so increasing its cost here shouldn't be a big
12737 * deal).
12738 */
12739 if (i915.fastboot && ret == 0)
12740 intel_modeset_check_state(set->crtc->dev);
12741 }
12742
12743 if (ret) {
12744 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12745 set->crtc->base.id, ret);
12746 }
12747
12748 out:
12749 if (ret)
12750 drm_atomic_state_free(state);
12751 return ret;
12752 }
12753
12754 static const struct drm_crtc_funcs intel_crtc_funcs = {
12755 .gamma_set = intel_crtc_gamma_set,
12756 .set_config = intel_crtc_set_config,
12757 .destroy = intel_crtc_destroy,
12758 .page_flip = intel_crtc_page_flip,
12759 .atomic_duplicate_state = intel_crtc_duplicate_state,
12760 .atomic_destroy_state = intel_crtc_destroy_state,
12761 };
12762
12763 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12764 struct intel_shared_dpll *pll,
12765 struct intel_dpll_hw_state *hw_state)
12766 {
12767 uint32_t val;
12768
12769 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12770 return false;
12771
12772 val = I915_READ(PCH_DPLL(pll->id));
12773 hw_state->dpll = val;
12774 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12775 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12776
12777 return val & DPLL_VCO_ENABLE;
12778 }
12779
12780 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12781 struct intel_shared_dpll *pll)
12782 {
12783 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12784 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12785 }
12786
12787 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12788 struct intel_shared_dpll *pll)
12789 {
12790 /* PCH refclock must be enabled first */
12791 ibx_assert_pch_refclk_enabled(dev_priv);
12792
12793 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12794
12795 /* Wait for the clocks to stabilize. */
12796 POSTING_READ(PCH_DPLL(pll->id));
12797 udelay(150);
12798
12799 /* The pixel multiplier can only be updated once the
12800 * DPLL is enabled and the clocks are stable.
12801 *
12802 * So write it again.
12803 */
12804 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12805 POSTING_READ(PCH_DPLL(pll->id));
12806 udelay(200);
12807 }
12808
12809 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12810 struct intel_shared_dpll *pll)
12811 {
12812 struct drm_device *dev = dev_priv->dev;
12813 struct intel_crtc *crtc;
12814
12815 /* Make sure no transcoder isn't still depending on us. */
12816 for_each_intel_crtc(dev, crtc) {
12817 if (intel_crtc_to_shared_dpll(crtc) == pll)
12818 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12819 }
12820
12821 I915_WRITE(PCH_DPLL(pll->id), 0);
12822 POSTING_READ(PCH_DPLL(pll->id));
12823 udelay(200);
12824 }
12825
12826 static char *ibx_pch_dpll_names[] = {
12827 "PCH DPLL A",
12828 "PCH DPLL B",
12829 };
12830
12831 static void ibx_pch_dpll_init(struct drm_device *dev)
12832 {
12833 struct drm_i915_private *dev_priv = dev->dev_private;
12834 int i;
12835
12836 dev_priv->num_shared_dpll = 2;
12837
12838 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12839 dev_priv->shared_dplls[i].id = i;
12840 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12841 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12842 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12843 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12844 dev_priv->shared_dplls[i].get_hw_state =
12845 ibx_pch_dpll_get_hw_state;
12846 }
12847 }
12848
12849 static void intel_shared_dpll_init(struct drm_device *dev)
12850 {
12851 struct drm_i915_private *dev_priv = dev->dev_private;
12852
12853 if (HAS_DDI(dev))
12854 intel_ddi_pll_init(dev);
12855 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12856 ibx_pch_dpll_init(dev);
12857 else
12858 dev_priv->num_shared_dpll = 0;
12859
12860 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12861 }
12862
12863 /**
12864 * intel_wm_need_update - Check whether watermarks need updating
12865 * @plane: drm plane
12866 * @state: new plane state
12867 *
12868 * Check current plane state versus the new one to determine whether
12869 * watermarks need to be recalculated.
12870 *
12871 * Returns true or false.
12872 */
12873 bool intel_wm_need_update(struct drm_plane *plane,
12874 struct drm_plane_state *state)
12875 {
12876 /* Update watermarks on tiling changes. */
12877 if (!plane->state->fb || !state->fb ||
12878 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12879 plane->state->rotation != state->rotation)
12880 return true;
12881
12882 return false;
12883 }
12884
12885 /**
12886 * intel_prepare_plane_fb - Prepare fb for usage on plane
12887 * @plane: drm plane to prepare for
12888 * @fb: framebuffer to prepare for presentation
12889 *
12890 * Prepares a framebuffer for usage on a display plane. Generally this
12891 * involves pinning the underlying object and updating the frontbuffer tracking
12892 * bits. Some older platforms need special physical address handling for
12893 * cursor planes.
12894 *
12895 * Returns 0 on success, negative error code on failure.
12896 */
12897 int
12898 intel_prepare_plane_fb(struct drm_plane *plane,
12899 struct drm_framebuffer *fb,
12900 const struct drm_plane_state *new_state)
12901 {
12902 struct drm_device *dev = plane->dev;
12903 struct intel_plane *intel_plane = to_intel_plane(plane);
12904 enum pipe pipe = intel_plane->pipe;
12905 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12906 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12907 unsigned frontbuffer_bits = 0;
12908 int ret = 0;
12909
12910 if (!obj)
12911 return 0;
12912
12913 switch (plane->type) {
12914 case DRM_PLANE_TYPE_PRIMARY:
12915 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12916 break;
12917 case DRM_PLANE_TYPE_CURSOR:
12918 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12919 break;
12920 case DRM_PLANE_TYPE_OVERLAY:
12921 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12922 break;
12923 }
12924
12925 mutex_lock(&dev->struct_mutex);
12926
12927 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12928 INTEL_INFO(dev)->cursor_needs_physical) {
12929 int align = IS_I830(dev) ? 16 * 1024 : 256;
12930 ret = i915_gem_object_attach_phys(obj, align);
12931 if (ret)
12932 DRM_DEBUG_KMS("failed to attach phys object\n");
12933 } else {
12934 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12935 }
12936
12937 if (ret == 0)
12938 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12939
12940 mutex_unlock(&dev->struct_mutex);
12941
12942 return ret;
12943 }
12944
12945 /**
12946 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12947 * @plane: drm plane to clean up for
12948 * @fb: old framebuffer that was on plane
12949 *
12950 * Cleans up a framebuffer that has just been removed from a plane.
12951 */
12952 void
12953 intel_cleanup_plane_fb(struct drm_plane *plane,
12954 struct drm_framebuffer *fb,
12955 const struct drm_plane_state *old_state)
12956 {
12957 struct drm_device *dev = plane->dev;
12958 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12959
12960 if (WARN_ON(!obj))
12961 return;
12962
12963 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12964 !INTEL_INFO(dev)->cursor_needs_physical) {
12965 mutex_lock(&dev->struct_mutex);
12966 intel_unpin_fb_obj(fb, old_state);
12967 mutex_unlock(&dev->struct_mutex);
12968 }
12969 }
12970
12971 int
12972 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12973 {
12974 int max_scale;
12975 struct drm_device *dev;
12976 struct drm_i915_private *dev_priv;
12977 int crtc_clock, cdclk;
12978
12979 if (!intel_crtc || !crtc_state)
12980 return DRM_PLANE_HELPER_NO_SCALING;
12981
12982 dev = intel_crtc->base.dev;
12983 dev_priv = dev->dev_private;
12984 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12985 cdclk = dev_priv->display.get_display_clock_speed(dev);
12986
12987 if (!crtc_clock || !cdclk)
12988 return DRM_PLANE_HELPER_NO_SCALING;
12989
12990 /*
12991 * skl max scale is lower of:
12992 * close to 3 but not 3, -1 is for that purpose
12993 * or
12994 * cdclk/crtc_clock
12995 */
12996 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
12997
12998 return max_scale;
12999 }
13000
13001 static int
13002 intel_check_primary_plane(struct drm_plane *plane,
13003 struct intel_plane_state *state)
13004 {
13005 struct drm_device *dev = plane->dev;
13006 struct drm_i915_private *dev_priv = dev->dev_private;
13007 struct drm_crtc *crtc = state->base.crtc;
13008 struct intel_crtc *intel_crtc;
13009 struct intel_crtc_state *crtc_state;
13010 struct drm_framebuffer *fb = state->base.fb;
13011 struct drm_rect *dest = &state->dst;
13012 struct drm_rect *src = &state->src;
13013 const struct drm_rect *clip = &state->clip;
13014 bool can_position = false;
13015 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13016 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13017 int ret;
13018
13019 crtc = crtc ? crtc : plane->crtc;
13020 intel_crtc = to_intel_crtc(crtc);
13021 crtc_state = state->base.state ?
13022 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13023
13024 if (INTEL_INFO(dev)->gen >= 9) {
13025 min_scale = 1;
13026 max_scale = skl_max_scale(intel_crtc, crtc_state);
13027 can_position = true;
13028 }
13029
13030 ret = drm_plane_helper_check_update(plane, crtc, fb,
13031 src, dest, clip,
13032 min_scale,
13033 max_scale,
13034 can_position, true,
13035 &state->visible);
13036 if (ret)
13037 return ret;
13038
13039 if (intel_crtc->active) {
13040 struct intel_plane_state *old_state =
13041 to_intel_plane_state(plane->state);
13042
13043 intel_crtc->atomic.wait_for_flips = true;
13044
13045 /*
13046 * FBC does not work on some platforms for rotated
13047 * planes, so disable it when rotation is not 0 and
13048 * update it when rotation is set back to 0.
13049 *
13050 * FIXME: This is redundant with the fbc update done in
13051 * the primary plane enable function except that that
13052 * one is done too late. We eventually need to unify
13053 * this.
13054 */
13055 if (state->visible &&
13056 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13057 dev_priv->fbc.crtc == intel_crtc &&
13058 state->base.rotation != BIT(DRM_ROTATE_0)) {
13059 intel_crtc->atomic.disable_fbc = true;
13060 }
13061
13062 if (state->visible && !old_state->visible) {
13063 /*
13064 * BDW signals flip done immediately if the plane
13065 * is disabled, even if the plane enable is already
13066 * armed to occur at the next vblank :(
13067 */
13068 if (IS_BROADWELL(dev))
13069 intel_crtc->atomic.wait_vblank = true;
13070 }
13071
13072 intel_crtc->atomic.fb_bits |=
13073 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13074
13075 intel_crtc->atomic.update_fbc = true;
13076
13077 if (intel_wm_need_update(plane, &state->base))
13078 intel_crtc->atomic.update_wm = true;
13079 }
13080
13081 if (INTEL_INFO(dev)->gen >= 9) {
13082 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13083 to_intel_plane(plane), state, 0);
13084 if (ret)
13085 return ret;
13086 }
13087
13088 return 0;
13089 }
13090
13091 static void
13092 intel_commit_primary_plane(struct drm_plane *plane,
13093 struct intel_plane_state *state)
13094 {
13095 struct drm_crtc *crtc = state->base.crtc;
13096 struct drm_framebuffer *fb = state->base.fb;
13097 struct drm_device *dev = plane->dev;
13098 struct drm_i915_private *dev_priv = dev->dev_private;
13099 struct intel_crtc *intel_crtc;
13100 struct drm_rect *src = &state->src;
13101
13102 crtc = crtc ? crtc : plane->crtc;
13103 intel_crtc = to_intel_crtc(crtc);
13104
13105 plane->fb = fb;
13106 crtc->x = src->x1 >> 16;
13107 crtc->y = src->y1 >> 16;
13108
13109 if (intel_crtc->active) {
13110 if (state->visible)
13111 /* FIXME: kill this fastboot hack */
13112 intel_update_pipe_size(intel_crtc);
13113
13114 dev_priv->display.update_primary_plane(crtc, plane->fb,
13115 crtc->x, crtc->y);
13116 }
13117 }
13118
13119 static void
13120 intel_disable_primary_plane(struct drm_plane *plane,
13121 struct drm_crtc *crtc,
13122 bool force)
13123 {
13124 struct drm_device *dev = plane->dev;
13125 struct drm_i915_private *dev_priv = dev->dev_private;
13126
13127 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13128 }
13129
13130 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13131 {
13132 struct drm_device *dev = crtc->dev;
13133 struct drm_i915_private *dev_priv = dev->dev_private;
13134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13135 struct intel_plane *intel_plane;
13136 struct drm_plane *p;
13137 unsigned fb_bits = 0;
13138
13139 /* Track fb's for any planes being disabled */
13140 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13141 intel_plane = to_intel_plane(p);
13142
13143 if (intel_crtc->atomic.disabled_planes &
13144 (1 << drm_plane_index(p))) {
13145 switch (p->type) {
13146 case DRM_PLANE_TYPE_PRIMARY:
13147 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13148 break;
13149 case DRM_PLANE_TYPE_CURSOR:
13150 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13151 break;
13152 case DRM_PLANE_TYPE_OVERLAY:
13153 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13154 break;
13155 }
13156
13157 mutex_lock(&dev->struct_mutex);
13158 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13159 mutex_unlock(&dev->struct_mutex);
13160 }
13161 }
13162
13163 if (intel_crtc->atomic.wait_for_flips)
13164 intel_crtc_wait_for_pending_flips(crtc);
13165
13166 if (intel_crtc->atomic.disable_fbc)
13167 intel_fbc_disable(dev);
13168
13169 if (intel_crtc->atomic.pre_disable_primary)
13170 intel_pre_disable_primary(crtc);
13171
13172 if (intel_crtc->atomic.update_wm)
13173 intel_update_watermarks(crtc);
13174
13175 intel_runtime_pm_get(dev_priv);
13176
13177 /* Perform vblank evasion around commit operation */
13178 if (intel_crtc->active)
13179 intel_crtc->atomic.evade =
13180 intel_pipe_update_start(intel_crtc,
13181 &intel_crtc->atomic.start_vbl_count);
13182 }
13183
13184 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13185 {
13186 struct drm_device *dev = crtc->dev;
13187 struct drm_i915_private *dev_priv = dev->dev_private;
13188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13189 struct drm_plane *p;
13190
13191 if (intel_crtc->atomic.evade)
13192 intel_pipe_update_end(intel_crtc,
13193 intel_crtc->atomic.start_vbl_count);
13194
13195 intel_runtime_pm_put(dev_priv);
13196
13197 if (intel_crtc->atomic.wait_vblank)
13198 intel_wait_for_vblank(dev, intel_crtc->pipe);
13199
13200 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13201
13202 if (intel_crtc->atomic.update_fbc) {
13203 mutex_lock(&dev->struct_mutex);
13204 intel_fbc_update(dev);
13205 mutex_unlock(&dev->struct_mutex);
13206 }
13207
13208 if (intel_crtc->atomic.post_enable_primary)
13209 intel_post_enable_primary(crtc);
13210
13211 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13212 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13213 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13214 false, false);
13215
13216 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13217 }
13218
13219 /**
13220 * intel_plane_destroy - destroy a plane
13221 * @plane: plane to destroy
13222 *
13223 * Common destruction function for all types of planes (primary, cursor,
13224 * sprite).
13225 */
13226 void intel_plane_destroy(struct drm_plane *plane)
13227 {
13228 struct intel_plane *intel_plane = to_intel_plane(plane);
13229 drm_plane_cleanup(plane);
13230 kfree(intel_plane);
13231 }
13232
13233 const struct drm_plane_funcs intel_plane_funcs = {
13234 .update_plane = drm_atomic_helper_update_plane,
13235 .disable_plane = drm_atomic_helper_disable_plane,
13236 .destroy = intel_plane_destroy,
13237 .set_property = drm_atomic_helper_plane_set_property,
13238 .atomic_get_property = intel_plane_atomic_get_property,
13239 .atomic_set_property = intel_plane_atomic_set_property,
13240 .atomic_duplicate_state = intel_plane_duplicate_state,
13241 .atomic_destroy_state = intel_plane_destroy_state,
13242
13243 };
13244
13245 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13246 int pipe)
13247 {
13248 struct intel_plane *primary;
13249 struct intel_plane_state *state;
13250 const uint32_t *intel_primary_formats;
13251 int num_formats;
13252
13253 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13254 if (primary == NULL)
13255 return NULL;
13256
13257 state = intel_create_plane_state(&primary->base);
13258 if (!state) {
13259 kfree(primary);
13260 return NULL;
13261 }
13262 primary->base.state = &state->base;
13263
13264 primary->can_scale = false;
13265 primary->max_downscale = 1;
13266 if (INTEL_INFO(dev)->gen >= 9) {
13267 primary->can_scale = true;
13268 }
13269 state->scaler_id = -1;
13270 primary->pipe = pipe;
13271 primary->plane = pipe;
13272 primary->check_plane = intel_check_primary_plane;
13273 primary->commit_plane = intel_commit_primary_plane;
13274 primary->disable_plane = intel_disable_primary_plane;
13275 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13276 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13277 primary->plane = !pipe;
13278
13279 if (INTEL_INFO(dev)->gen <= 3) {
13280 intel_primary_formats = intel_primary_formats_gen2;
13281 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13282 } else {
13283 intel_primary_formats = intel_primary_formats_gen4;
13284 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13285 }
13286
13287 drm_universal_plane_init(dev, &primary->base, 0,
13288 &intel_plane_funcs,
13289 intel_primary_formats, num_formats,
13290 DRM_PLANE_TYPE_PRIMARY);
13291
13292 if (INTEL_INFO(dev)->gen >= 4)
13293 intel_create_rotation_property(dev, primary);
13294
13295 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13296
13297 return &primary->base;
13298 }
13299
13300 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13301 {
13302 if (!dev->mode_config.rotation_property) {
13303 unsigned long flags = BIT(DRM_ROTATE_0) |
13304 BIT(DRM_ROTATE_180);
13305
13306 if (INTEL_INFO(dev)->gen >= 9)
13307 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13308
13309 dev->mode_config.rotation_property =
13310 drm_mode_create_rotation_property(dev, flags);
13311 }
13312 if (dev->mode_config.rotation_property)
13313 drm_object_attach_property(&plane->base.base,
13314 dev->mode_config.rotation_property,
13315 plane->base.state->rotation);
13316 }
13317
13318 static int
13319 intel_check_cursor_plane(struct drm_plane *plane,
13320 struct intel_plane_state *state)
13321 {
13322 struct drm_crtc *crtc = state->base.crtc;
13323 struct drm_device *dev = plane->dev;
13324 struct drm_framebuffer *fb = state->base.fb;
13325 struct drm_rect *dest = &state->dst;
13326 struct drm_rect *src = &state->src;
13327 const struct drm_rect *clip = &state->clip;
13328 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13329 struct intel_crtc *intel_crtc;
13330 unsigned stride;
13331 int ret;
13332
13333 crtc = crtc ? crtc : plane->crtc;
13334 intel_crtc = to_intel_crtc(crtc);
13335
13336 ret = drm_plane_helper_check_update(plane, crtc, fb,
13337 src, dest, clip,
13338 DRM_PLANE_HELPER_NO_SCALING,
13339 DRM_PLANE_HELPER_NO_SCALING,
13340 true, true, &state->visible);
13341 if (ret)
13342 return ret;
13343
13344
13345 /* if we want to turn off the cursor ignore width and height */
13346 if (!obj)
13347 goto finish;
13348
13349 /* Check for which cursor types we support */
13350 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13351 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13352 state->base.crtc_w, state->base.crtc_h);
13353 return -EINVAL;
13354 }
13355
13356 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13357 if (obj->base.size < stride * state->base.crtc_h) {
13358 DRM_DEBUG_KMS("buffer is too small\n");
13359 return -ENOMEM;
13360 }
13361
13362 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13363 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13364 ret = -EINVAL;
13365 }
13366
13367 finish:
13368 if (intel_crtc->active) {
13369 if (plane->state->crtc_w != state->base.crtc_w)
13370 intel_crtc->atomic.update_wm = true;
13371
13372 intel_crtc->atomic.fb_bits |=
13373 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13374 }
13375
13376 return ret;
13377 }
13378
13379 static void
13380 intel_disable_cursor_plane(struct drm_plane *plane,
13381 struct drm_crtc *crtc,
13382 bool force)
13383 {
13384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13385
13386 if (!force) {
13387 plane->fb = NULL;
13388 intel_crtc->cursor_bo = NULL;
13389 intel_crtc->cursor_addr = 0;
13390 }
13391
13392 intel_crtc_update_cursor(crtc, false);
13393 }
13394
13395 static void
13396 intel_commit_cursor_plane(struct drm_plane *plane,
13397 struct intel_plane_state *state)
13398 {
13399 struct drm_crtc *crtc = state->base.crtc;
13400 struct drm_device *dev = plane->dev;
13401 struct intel_crtc *intel_crtc;
13402 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13403 uint32_t addr;
13404
13405 crtc = crtc ? crtc : plane->crtc;
13406 intel_crtc = to_intel_crtc(crtc);
13407
13408 plane->fb = state->base.fb;
13409 crtc->cursor_x = state->base.crtc_x;
13410 crtc->cursor_y = state->base.crtc_y;
13411
13412 if (intel_crtc->cursor_bo == obj)
13413 goto update;
13414
13415 if (!obj)
13416 addr = 0;
13417 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13418 addr = i915_gem_obj_ggtt_offset(obj);
13419 else
13420 addr = obj->phys_handle->busaddr;
13421
13422 intel_crtc->cursor_addr = addr;
13423 intel_crtc->cursor_bo = obj;
13424 update:
13425
13426 if (intel_crtc->active)
13427 intel_crtc_update_cursor(crtc, state->visible);
13428 }
13429
13430 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13431 int pipe)
13432 {
13433 struct intel_plane *cursor;
13434 struct intel_plane_state *state;
13435
13436 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13437 if (cursor == NULL)
13438 return NULL;
13439
13440 state = intel_create_plane_state(&cursor->base);
13441 if (!state) {
13442 kfree(cursor);
13443 return NULL;
13444 }
13445 cursor->base.state = &state->base;
13446
13447 cursor->can_scale = false;
13448 cursor->max_downscale = 1;
13449 cursor->pipe = pipe;
13450 cursor->plane = pipe;
13451 state->scaler_id = -1;
13452 cursor->check_plane = intel_check_cursor_plane;
13453 cursor->commit_plane = intel_commit_cursor_plane;
13454 cursor->disable_plane = intel_disable_cursor_plane;
13455
13456 drm_universal_plane_init(dev, &cursor->base, 0,
13457 &intel_plane_funcs,
13458 intel_cursor_formats,
13459 ARRAY_SIZE(intel_cursor_formats),
13460 DRM_PLANE_TYPE_CURSOR);
13461
13462 if (INTEL_INFO(dev)->gen >= 4) {
13463 if (!dev->mode_config.rotation_property)
13464 dev->mode_config.rotation_property =
13465 drm_mode_create_rotation_property(dev,
13466 BIT(DRM_ROTATE_0) |
13467 BIT(DRM_ROTATE_180));
13468 if (dev->mode_config.rotation_property)
13469 drm_object_attach_property(&cursor->base.base,
13470 dev->mode_config.rotation_property,
13471 state->base.rotation);
13472 }
13473
13474 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13475
13476 return &cursor->base;
13477 }
13478
13479 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13480 struct intel_crtc_state *crtc_state)
13481 {
13482 int i;
13483 struct intel_scaler *intel_scaler;
13484 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13485
13486 for (i = 0; i < intel_crtc->num_scalers; i++) {
13487 intel_scaler = &scaler_state->scalers[i];
13488 intel_scaler->in_use = 0;
13489 intel_scaler->id = i;
13490
13491 intel_scaler->mode = PS_SCALER_MODE_DYN;
13492 }
13493
13494 scaler_state->scaler_id = -1;
13495 }
13496
13497 static void intel_crtc_init(struct drm_device *dev, int pipe)
13498 {
13499 struct drm_i915_private *dev_priv = dev->dev_private;
13500 struct intel_crtc *intel_crtc;
13501 struct intel_crtc_state *crtc_state = NULL;
13502 struct drm_plane *primary = NULL;
13503 struct drm_plane *cursor = NULL;
13504 int i, ret;
13505
13506 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13507 if (intel_crtc == NULL)
13508 return;
13509
13510 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13511 if (!crtc_state)
13512 goto fail;
13513 intel_crtc->config = crtc_state;
13514 intel_crtc->base.state = &crtc_state->base;
13515 crtc_state->base.crtc = &intel_crtc->base;
13516
13517 /* initialize shared scalers */
13518 if (INTEL_INFO(dev)->gen >= 9) {
13519 if (pipe == PIPE_C)
13520 intel_crtc->num_scalers = 1;
13521 else
13522 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13523
13524 skl_init_scalers(dev, intel_crtc, crtc_state);
13525 }
13526
13527 primary = intel_primary_plane_create(dev, pipe);
13528 if (!primary)
13529 goto fail;
13530
13531 cursor = intel_cursor_plane_create(dev, pipe);
13532 if (!cursor)
13533 goto fail;
13534
13535 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13536 cursor, &intel_crtc_funcs);
13537 if (ret)
13538 goto fail;
13539
13540 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13541 for (i = 0; i < 256; i++) {
13542 intel_crtc->lut_r[i] = i;
13543 intel_crtc->lut_g[i] = i;
13544 intel_crtc->lut_b[i] = i;
13545 }
13546
13547 /*
13548 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13549 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13550 */
13551 intel_crtc->pipe = pipe;
13552 intel_crtc->plane = pipe;
13553 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13554 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13555 intel_crtc->plane = !pipe;
13556 }
13557
13558 intel_crtc->cursor_base = ~0;
13559 intel_crtc->cursor_cntl = ~0;
13560 intel_crtc->cursor_size = ~0;
13561
13562 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13563 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13564 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13565 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13566
13567 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13568
13569 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13570
13571 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13572 return;
13573
13574 fail:
13575 if (primary)
13576 drm_plane_cleanup(primary);
13577 if (cursor)
13578 drm_plane_cleanup(cursor);
13579 kfree(crtc_state);
13580 kfree(intel_crtc);
13581 }
13582
13583 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13584 {
13585 struct drm_encoder *encoder = connector->base.encoder;
13586 struct drm_device *dev = connector->base.dev;
13587
13588 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13589
13590 if (!encoder || WARN_ON(!encoder->crtc))
13591 return INVALID_PIPE;
13592
13593 return to_intel_crtc(encoder->crtc)->pipe;
13594 }
13595
13596 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13597 struct drm_file *file)
13598 {
13599 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13600 struct drm_crtc *drmmode_crtc;
13601 struct intel_crtc *crtc;
13602
13603 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13604
13605 if (!drmmode_crtc) {
13606 DRM_ERROR("no such CRTC id\n");
13607 return -ENOENT;
13608 }
13609
13610 crtc = to_intel_crtc(drmmode_crtc);
13611 pipe_from_crtc_id->pipe = crtc->pipe;
13612
13613 return 0;
13614 }
13615
13616 static int intel_encoder_clones(struct intel_encoder *encoder)
13617 {
13618 struct drm_device *dev = encoder->base.dev;
13619 struct intel_encoder *source_encoder;
13620 int index_mask = 0;
13621 int entry = 0;
13622
13623 for_each_intel_encoder(dev, source_encoder) {
13624 if (encoders_cloneable(encoder, source_encoder))
13625 index_mask |= (1 << entry);
13626
13627 entry++;
13628 }
13629
13630 return index_mask;
13631 }
13632
13633 static bool has_edp_a(struct drm_device *dev)
13634 {
13635 struct drm_i915_private *dev_priv = dev->dev_private;
13636
13637 if (!IS_MOBILE(dev))
13638 return false;
13639
13640 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13641 return false;
13642
13643 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13644 return false;
13645
13646 return true;
13647 }
13648
13649 static bool intel_crt_present(struct drm_device *dev)
13650 {
13651 struct drm_i915_private *dev_priv = dev->dev_private;
13652
13653 if (INTEL_INFO(dev)->gen >= 9)
13654 return false;
13655
13656 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13657 return false;
13658
13659 if (IS_CHERRYVIEW(dev))
13660 return false;
13661
13662 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13663 return false;
13664
13665 return true;
13666 }
13667
13668 static void intel_setup_outputs(struct drm_device *dev)
13669 {
13670 struct drm_i915_private *dev_priv = dev->dev_private;
13671 struct intel_encoder *encoder;
13672 bool dpd_is_edp = false;
13673
13674 intel_lvds_init(dev);
13675
13676 if (intel_crt_present(dev))
13677 intel_crt_init(dev);
13678
13679 if (IS_BROXTON(dev)) {
13680 /*
13681 * FIXME: Broxton doesn't support port detection via the
13682 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13683 * detect the ports.
13684 */
13685 intel_ddi_init(dev, PORT_A);
13686 intel_ddi_init(dev, PORT_B);
13687 intel_ddi_init(dev, PORT_C);
13688 } else if (HAS_DDI(dev)) {
13689 int found;
13690
13691 /*
13692 * Haswell uses DDI functions to detect digital outputs.
13693 * On SKL pre-D0 the strap isn't connected, so we assume
13694 * it's there.
13695 */
13696 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13697 /* WaIgnoreDDIAStrap: skl */
13698 if (found ||
13699 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13700 intel_ddi_init(dev, PORT_A);
13701
13702 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13703 * register */
13704 found = I915_READ(SFUSE_STRAP);
13705
13706 if (found & SFUSE_STRAP_DDIB_DETECTED)
13707 intel_ddi_init(dev, PORT_B);
13708 if (found & SFUSE_STRAP_DDIC_DETECTED)
13709 intel_ddi_init(dev, PORT_C);
13710 if (found & SFUSE_STRAP_DDID_DETECTED)
13711 intel_ddi_init(dev, PORT_D);
13712 } else if (HAS_PCH_SPLIT(dev)) {
13713 int found;
13714 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13715
13716 if (has_edp_a(dev))
13717 intel_dp_init(dev, DP_A, PORT_A);
13718
13719 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13720 /* PCH SDVOB multiplex with HDMIB */
13721 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13722 if (!found)
13723 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13724 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13725 intel_dp_init(dev, PCH_DP_B, PORT_B);
13726 }
13727
13728 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13729 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13730
13731 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13732 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13733
13734 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13735 intel_dp_init(dev, PCH_DP_C, PORT_C);
13736
13737 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13738 intel_dp_init(dev, PCH_DP_D, PORT_D);
13739 } else if (IS_VALLEYVIEW(dev)) {
13740 /*
13741 * The DP_DETECTED bit is the latched state of the DDC
13742 * SDA pin at boot. However since eDP doesn't require DDC
13743 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13744 * eDP ports may have been muxed to an alternate function.
13745 * Thus we can't rely on the DP_DETECTED bit alone to detect
13746 * eDP ports. Consult the VBT as well as DP_DETECTED to
13747 * detect eDP ports.
13748 */
13749 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13750 !intel_dp_is_edp(dev, PORT_B))
13751 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13752 PORT_B);
13753 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13754 intel_dp_is_edp(dev, PORT_B))
13755 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13756
13757 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13758 !intel_dp_is_edp(dev, PORT_C))
13759 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13760 PORT_C);
13761 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13762 intel_dp_is_edp(dev, PORT_C))
13763 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13764
13765 if (IS_CHERRYVIEW(dev)) {
13766 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13767 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13768 PORT_D);
13769 /* eDP not supported on port D, so don't check VBT */
13770 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13771 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13772 }
13773
13774 intel_dsi_init(dev);
13775 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13776 bool found = false;
13777
13778 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13779 DRM_DEBUG_KMS("probing SDVOB\n");
13780 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13781 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13782 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13783 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13784 }
13785
13786 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13787 intel_dp_init(dev, DP_B, PORT_B);
13788 }
13789
13790 /* Before G4X SDVOC doesn't have its own detect register */
13791
13792 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13793 DRM_DEBUG_KMS("probing SDVOC\n");
13794 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13795 }
13796
13797 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13798
13799 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13800 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13801 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13802 }
13803 if (SUPPORTS_INTEGRATED_DP(dev))
13804 intel_dp_init(dev, DP_C, PORT_C);
13805 }
13806
13807 if (SUPPORTS_INTEGRATED_DP(dev) &&
13808 (I915_READ(DP_D) & DP_DETECTED))
13809 intel_dp_init(dev, DP_D, PORT_D);
13810 } else if (IS_GEN2(dev))
13811 intel_dvo_init(dev);
13812
13813 if (SUPPORTS_TV(dev))
13814 intel_tv_init(dev);
13815
13816 intel_psr_init(dev);
13817
13818 for_each_intel_encoder(dev, encoder) {
13819 encoder->base.possible_crtcs = encoder->crtc_mask;
13820 encoder->base.possible_clones =
13821 intel_encoder_clones(encoder);
13822 }
13823
13824 intel_init_pch_refclk(dev);
13825
13826 drm_helper_move_panel_connectors_to_head(dev);
13827 }
13828
13829 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13830 {
13831 struct drm_device *dev = fb->dev;
13832 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13833
13834 drm_framebuffer_cleanup(fb);
13835 mutex_lock(&dev->struct_mutex);
13836 WARN_ON(!intel_fb->obj->framebuffer_references--);
13837 drm_gem_object_unreference(&intel_fb->obj->base);
13838 mutex_unlock(&dev->struct_mutex);
13839 kfree(intel_fb);
13840 }
13841
13842 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13843 struct drm_file *file,
13844 unsigned int *handle)
13845 {
13846 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13847 struct drm_i915_gem_object *obj = intel_fb->obj;
13848
13849 return drm_gem_handle_create(file, &obj->base, handle);
13850 }
13851
13852 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13853 .destroy = intel_user_framebuffer_destroy,
13854 .create_handle = intel_user_framebuffer_create_handle,
13855 };
13856
13857 static
13858 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13859 uint32_t pixel_format)
13860 {
13861 u32 gen = INTEL_INFO(dev)->gen;
13862
13863 if (gen >= 9) {
13864 /* "The stride in bytes must not exceed the of the size of 8K
13865 * pixels and 32K bytes."
13866 */
13867 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13868 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13869 return 32*1024;
13870 } else if (gen >= 4) {
13871 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13872 return 16*1024;
13873 else
13874 return 32*1024;
13875 } else if (gen >= 3) {
13876 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13877 return 8*1024;
13878 else
13879 return 16*1024;
13880 } else {
13881 /* XXX DSPC is limited to 4k tiled */
13882 return 8*1024;
13883 }
13884 }
13885
13886 static int intel_framebuffer_init(struct drm_device *dev,
13887 struct intel_framebuffer *intel_fb,
13888 struct drm_mode_fb_cmd2 *mode_cmd,
13889 struct drm_i915_gem_object *obj)
13890 {
13891 unsigned int aligned_height;
13892 int ret;
13893 u32 pitch_limit, stride_alignment;
13894
13895 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13896
13897 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13898 /* Enforce that fb modifier and tiling mode match, but only for
13899 * X-tiled. This is needed for FBC. */
13900 if (!!(obj->tiling_mode == I915_TILING_X) !=
13901 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13902 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13903 return -EINVAL;
13904 }
13905 } else {
13906 if (obj->tiling_mode == I915_TILING_X)
13907 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13908 else if (obj->tiling_mode == I915_TILING_Y) {
13909 DRM_DEBUG("No Y tiling for legacy addfb\n");
13910 return -EINVAL;
13911 }
13912 }
13913
13914 /* Passed in modifier sanity checking. */
13915 switch (mode_cmd->modifier[0]) {
13916 case I915_FORMAT_MOD_Y_TILED:
13917 case I915_FORMAT_MOD_Yf_TILED:
13918 if (INTEL_INFO(dev)->gen < 9) {
13919 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13920 mode_cmd->modifier[0]);
13921 return -EINVAL;
13922 }
13923 case DRM_FORMAT_MOD_NONE:
13924 case I915_FORMAT_MOD_X_TILED:
13925 break;
13926 default:
13927 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13928 mode_cmd->modifier[0]);
13929 return -EINVAL;
13930 }
13931
13932 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13933 mode_cmd->pixel_format);
13934 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13935 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13936 mode_cmd->pitches[0], stride_alignment);
13937 return -EINVAL;
13938 }
13939
13940 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13941 mode_cmd->pixel_format);
13942 if (mode_cmd->pitches[0] > pitch_limit) {
13943 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13944 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13945 "tiled" : "linear",
13946 mode_cmd->pitches[0], pitch_limit);
13947 return -EINVAL;
13948 }
13949
13950 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13951 mode_cmd->pitches[0] != obj->stride) {
13952 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13953 mode_cmd->pitches[0], obj->stride);
13954 return -EINVAL;
13955 }
13956
13957 /* Reject formats not supported by any plane early. */
13958 switch (mode_cmd->pixel_format) {
13959 case DRM_FORMAT_C8:
13960 case DRM_FORMAT_RGB565:
13961 case DRM_FORMAT_XRGB8888:
13962 case DRM_FORMAT_ARGB8888:
13963 break;
13964 case DRM_FORMAT_XRGB1555:
13965 case DRM_FORMAT_ARGB1555:
13966 if (INTEL_INFO(dev)->gen > 3) {
13967 DRM_DEBUG("unsupported pixel format: %s\n",
13968 drm_get_format_name(mode_cmd->pixel_format));
13969 return -EINVAL;
13970 }
13971 break;
13972 case DRM_FORMAT_XBGR8888:
13973 case DRM_FORMAT_ABGR8888:
13974 case DRM_FORMAT_XRGB2101010:
13975 case DRM_FORMAT_ARGB2101010:
13976 case DRM_FORMAT_XBGR2101010:
13977 case DRM_FORMAT_ABGR2101010:
13978 if (INTEL_INFO(dev)->gen < 4) {
13979 DRM_DEBUG("unsupported pixel format: %s\n",
13980 drm_get_format_name(mode_cmd->pixel_format));
13981 return -EINVAL;
13982 }
13983 break;
13984 case DRM_FORMAT_YUYV:
13985 case DRM_FORMAT_UYVY:
13986 case DRM_FORMAT_YVYU:
13987 case DRM_FORMAT_VYUY:
13988 if (INTEL_INFO(dev)->gen < 5) {
13989 DRM_DEBUG("unsupported pixel format: %s\n",
13990 drm_get_format_name(mode_cmd->pixel_format));
13991 return -EINVAL;
13992 }
13993 break;
13994 default:
13995 DRM_DEBUG("unsupported pixel format: %s\n",
13996 drm_get_format_name(mode_cmd->pixel_format));
13997 return -EINVAL;
13998 }
13999
14000 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14001 if (mode_cmd->offsets[0] != 0)
14002 return -EINVAL;
14003
14004 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14005 mode_cmd->pixel_format,
14006 mode_cmd->modifier[0]);
14007 /* FIXME drm helper for size checks (especially planar formats)? */
14008 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14009 return -EINVAL;
14010
14011 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14012 intel_fb->obj = obj;
14013 intel_fb->obj->framebuffer_references++;
14014
14015 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14016 if (ret) {
14017 DRM_ERROR("framebuffer init failed %d\n", ret);
14018 return ret;
14019 }
14020
14021 return 0;
14022 }
14023
14024 static struct drm_framebuffer *
14025 intel_user_framebuffer_create(struct drm_device *dev,
14026 struct drm_file *filp,
14027 struct drm_mode_fb_cmd2 *mode_cmd)
14028 {
14029 struct drm_i915_gem_object *obj;
14030
14031 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14032 mode_cmd->handles[0]));
14033 if (&obj->base == NULL)
14034 return ERR_PTR(-ENOENT);
14035
14036 return intel_framebuffer_create(dev, mode_cmd, obj);
14037 }
14038
14039 #ifndef CONFIG_DRM_I915_FBDEV
14040 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14041 {
14042 }
14043 #endif
14044
14045 static const struct drm_mode_config_funcs intel_mode_funcs = {
14046 .fb_create = intel_user_framebuffer_create,
14047 .output_poll_changed = intel_fbdev_output_poll_changed,
14048 .atomic_check = intel_atomic_check,
14049 .atomic_commit = intel_atomic_commit,
14050 };
14051
14052 /* Set up chip specific display functions */
14053 static void intel_init_display(struct drm_device *dev)
14054 {
14055 struct drm_i915_private *dev_priv = dev->dev_private;
14056
14057 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14058 dev_priv->display.find_dpll = g4x_find_best_dpll;
14059 else if (IS_CHERRYVIEW(dev))
14060 dev_priv->display.find_dpll = chv_find_best_dpll;
14061 else if (IS_VALLEYVIEW(dev))
14062 dev_priv->display.find_dpll = vlv_find_best_dpll;
14063 else if (IS_PINEVIEW(dev))
14064 dev_priv->display.find_dpll = pnv_find_best_dpll;
14065 else
14066 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14067
14068 if (INTEL_INFO(dev)->gen >= 9) {
14069 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14070 dev_priv->display.get_initial_plane_config =
14071 skylake_get_initial_plane_config;
14072 dev_priv->display.crtc_compute_clock =
14073 haswell_crtc_compute_clock;
14074 dev_priv->display.crtc_enable = haswell_crtc_enable;
14075 dev_priv->display.crtc_disable = haswell_crtc_disable;
14076 dev_priv->display.off = ironlake_crtc_off;
14077 dev_priv->display.update_primary_plane =
14078 skylake_update_primary_plane;
14079 } else if (HAS_DDI(dev)) {
14080 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14081 dev_priv->display.get_initial_plane_config =
14082 ironlake_get_initial_plane_config;
14083 dev_priv->display.crtc_compute_clock =
14084 haswell_crtc_compute_clock;
14085 dev_priv->display.crtc_enable = haswell_crtc_enable;
14086 dev_priv->display.crtc_disable = haswell_crtc_disable;
14087 dev_priv->display.off = ironlake_crtc_off;
14088 dev_priv->display.update_primary_plane =
14089 ironlake_update_primary_plane;
14090 } else if (HAS_PCH_SPLIT(dev)) {
14091 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14092 dev_priv->display.get_initial_plane_config =
14093 ironlake_get_initial_plane_config;
14094 dev_priv->display.crtc_compute_clock =
14095 ironlake_crtc_compute_clock;
14096 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14097 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14098 dev_priv->display.off = ironlake_crtc_off;
14099 dev_priv->display.update_primary_plane =
14100 ironlake_update_primary_plane;
14101 } else if (IS_VALLEYVIEW(dev)) {
14102 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14103 dev_priv->display.get_initial_plane_config =
14104 i9xx_get_initial_plane_config;
14105 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14106 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14107 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14108 dev_priv->display.off = i9xx_crtc_off;
14109 dev_priv->display.update_primary_plane =
14110 i9xx_update_primary_plane;
14111 } else {
14112 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14113 dev_priv->display.get_initial_plane_config =
14114 i9xx_get_initial_plane_config;
14115 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14116 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14117 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14118 dev_priv->display.off = i9xx_crtc_off;
14119 dev_priv->display.update_primary_plane =
14120 i9xx_update_primary_plane;
14121 }
14122
14123 /* Returns the core display clock speed */
14124 if (IS_SKYLAKE(dev))
14125 dev_priv->display.get_display_clock_speed =
14126 skylake_get_display_clock_speed;
14127 else if (IS_BROADWELL(dev))
14128 dev_priv->display.get_display_clock_speed =
14129 broadwell_get_display_clock_speed;
14130 else if (IS_HASWELL(dev))
14131 dev_priv->display.get_display_clock_speed =
14132 haswell_get_display_clock_speed;
14133 else if (IS_VALLEYVIEW(dev))
14134 dev_priv->display.get_display_clock_speed =
14135 valleyview_get_display_clock_speed;
14136 else if (IS_GEN5(dev))
14137 dev_priv->display.get_display_clock_speed =
14138 ilk_get_display_clock_speed;
14139 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14140 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14141 dev_priv->display.get_display_clock_speed =
14142 i945_get_display_clock_speed;
14143 else if (IS_I915G(dev))
14144 dev_priv->display.get_display_clock_speed =
14145 i915_get_display_clock_speed;
14146 else if (IS_I945GM(dev) || IS_845G(dev))
14147 dev_priv->display.get_display_clock_speed =
14148 i9xx_misc_get_display_clock_speed;
14149 else if (IS_PINEVIEW(dev))
14150 dev_priv->display.get_display_clock_speed =
14151 pnv_get_display_clock_speed;
14152 else if (IS_I915GM(dev))
14153 dev_priv->display.get_display_clock_speed =
14154 i915gm_get_display_clock_speed;
14155 else if (IS_I865G(dev))
14156 dev_priv->display.get_display_clock_speed =
14157 i865_get_display_clock_speed;
14158 else if (IS_I85X(dev))
14159 dev_priv->display.get_display_clock_speed =
14160 i855_get_display_clock_speed;
14161 else /* 852, 830 */
14162 dev_priv->display.get_display_clock_speed =
14163 i830_get_display_clock_speed;
14164
14165 if (IS_GEN5(dev)) {
14166 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14167 } else if (IS_GEN6(dev)) {
14168 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14169 } else if (IS_IVYBRIDGE(dev)) {
14170 /* FIXME: detect B0+ stepping and use auto training */
14171 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14172 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14173 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14174 } else if (IS_VALLEYVIEW(dev)) {
14175 dev_priv->display.modeset_global_resources =
14176 valleyview_modeset_global_resources;
14177 } else if (IS_BROXTON(dev)) {
14178 dev_priv->display.modeset_global_resources =
14179 broxton_modeset_global_resources;
14180 }
14181
14182 switch (INTEL_INFO(dev)->gen) {
14183 case 2:
14184 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14185 break;
14186
14187 case 3:
14188 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14189 break;
14190
14191 case 4:
14192 case 5:
14193 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14194 break;
14195
14196 case 6:
14197 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14198 break;
14199 case 7:
14200 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14201 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14202 break;
14203 case 9:
14204 /* Drop through - unsupported since execlist only. */
14205 default:
14206 /* Default just returns -ENODEV to indicate unsupported */
14207 dev_priv->display.queue_flip = intel_default_queue_flip;
14208 }
14209
14210 intel_panel_init_backlight_funcs(dev);
14211
14212 mutex_init(&dev_priv->pps_mutex);
14213 }
14214
14215 /*
14216 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14217 * resume, or other times. This quirk makes sure that's the case for
14218 * affected systems.
14219 */
14220 static void quirk_pipea_force(struct drm_device *dev)
14221 {
14222 struct drm_i915_private *dev_priv = dev->dev_private;
14223
14224 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14225 DRM_INFO("applying pipe a force quirk\n");
14226 }
14227
14228 static void quirk_pipeb_force(struct drm_device *dev)
14229 {
14230 struct drm_i915_private *dev_priv = dev->dev_private;
14231
14232 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14233 DRM_INFO("applying pipe b force quirk\n");
14234 }
14235
14236 /*
14237 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14238 */
14239 static void quirk_ssc_force_disable(struct drm_device *dev)
14240 {
14241 struct drm_i915_private *dev_priv = dev->dev_private;
14242 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14243 DRM_INFO("applying lvds SSC disable quirk\n");
14244 }
14245
14246 /*
14247 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14248 * brightness value
14249 */
14250 static void quirk_invert_brightness(struct drm_device *dev)
14251 {
14252 struct drm_i915_private *dev_priv = dev->dev_private;
14253 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14254 DRM_INFO("applying inverted panel brightness quirk\n");
14255 }
14256
14257 /* Some VBT's incorrectly indicate no backlight is present */
14258 static void quirk_backlight_present(struct drm_device *dev)
14259 {
14260 struct drm_i915_private *dev_priv = dev->dev_private;
14261 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14262 DRM_INFO("applying backlight present quirk\n");
14263 }
14264
14265 struct intel_quirk {
14266 int device;
14267 int subsystem_vendor;
14268 int subsystem_device;
14269 void (*hook)(struct drm_device *dev);
14270 };
14271
14272 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14273 struct intel_dmi_quirk {
14274 void (*hook)(struct drm_device *dev);
14275 const struct dmi_system_id (*dmi_id_list)[];
14276 };
14277
14278 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14279 {
14280 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14281 return 1;
14282 }
14283
14284 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14285 {
14286 .dmi_id_list = &(const struct dmi_system_id[]) {
14287 {
14288 .callback = intel_dmi_reverse_brightness,
14289 .ident = "NCR Corporation",
14290 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14291 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14292 },
14293 },
14294 { } /* terminating entry */
14295 },
14296 .hook = quirk_invert_brightness,
14297 },
14298 };
14299
14300 static struct intel_quirk intel_quirks[] = {
14301 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14302 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14303
14304 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14305 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14306
14307 /* 830 needs to leave pipe A & dpll A up */
14308 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14309
14310 /* 830 needs to leave pipe B & dpll B up */
14311 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14312
14313 /* Lenovo U160 cannot use SSC on LVDS */
14314 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14315
14316 /* Sony Vaio Y cannot use SSC on LVDS */
14317 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14318
14319 /* Acer Aspire 5734Z must invert backlight brightness */
14320 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14321
14322 /* Acer/eMachines G725 */
14323 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14324
14325 /* Acer/eMachines e725 */
14326 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14327
14328 /* Acer/Packard Bell NCL20 */
14329 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14330
14331 /* Acer Aspire 4736Z */
14332 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14333
14334 /* Acer Aspire 5336 */
14335 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14336
14337 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14338 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14339
14340 /* Acer C720 Chromebook (Core i3 4005U) */
14341 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14342
14343 /* Apple Macbook 2,1 (Core 2 T7400) */
14344 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14345
14346 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14347 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14348
14349 /* HP Chromebook 14 (Celeron 2955U) */
14350 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14351
14352 /* Dell Chromebook 11 */
14353 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14354 };
14355
14356 static void intel_init_quirks(struct drm_device *dev)
14357 {
14358 struct pci_dev *d = dev->pdev;
14359 int i;
14360
14361 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14362 struct intel_quirk *q = &intel_quirks[i];
14363
14364 if (d->device == q->device &&
14365 (d->subsystem_vendor == q->subsystem_vendor ||
14366 q->subsystem_vendor == PCI_ANY_ID) &&
14367 (d->subsystem_device == q->subsystem_device ||
14368 q->subsystem_device == PCI_ANY_ID))
14369 q->hook(dev);
14370 }
14371 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14372 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14373 intel_dmi_quirks[i].hook(dev);
14374 }
14375 }
14376
14377 /* Disable the VGA plane that we never use */
14378 static void i915_disable_vga(struct drm_device *dev)
14379 {
14380 struct drm_i915_private *dev_priv = dev->dev_private;
14381 u8 sr1;
14382 u32 vga_reg = i915_vgacntrl_reg(dev);
14383
14384 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14385 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14386 outb(SR01, VGA_SR_INDEX);
14387 sr1 = inb(VGA_SR_DATA);
14388 outb(sr1 | 1<<5, VGA_SR_DATA);
14389 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14390 udelay(300);
14391
14392 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14393 POSTING_READ(vga_reg);
14394 }
14395
14396 void intel_modeset_init_hw(struct drm_device *dev)
14397 {
14398 intel_prepare_ddi(dev);
14399
14400 if (IS_VALLEYVIEW(dev))
14401 vlv_update_cdclk(dev);
14402
14403 intel_init_clock_gating(dev);
14404
14405 intel_enable_gt_powersave(dev);
14406 }
14407
14408 void intel_modeset_init(struct drm_device *dev)
14409 {
14410 struct drm_i915_private *dev_priv = dev->dev_private;
14411 int sprite, ret;
14412 enum pipe pipe;
14413 struct intel_crtc *crtc;
14414
14415 drm_mode_config_init(dev);
14416
14417 dev->mode_config.min_width = 0;
14418 dev->mode_config.min_height = 0;
14419
14420 dev->mode_config.preferred_depth = 24;
14421 dev->mode_config.prefer_shadow = 1;
14422
14423 dev->mode_config.allow_fb_modifiers = true;
14424
14425 dev->mode_config.funcs = &intel_mode_funcs;
14426
14427 intel_init_quirks(dev);
14428
14429 intel_init_pm(dev);
14430
14431 if (INTEL_INFO(dev)->num_pipes == 0)
14432 return;
14433
14434 intel_init_display(dev);
14435 intel_init_audio(dev);
14436
14437 if (IS_GEN2(dev)) {
14438 dev->mode_config.max_width = 2048;
14439 dev->mode_config.max_height = 2048;
14440 } else if (IS_GEN3(dev)) {
14441 dev->mode_config.max_width = 4096;
14442 dev->mode_config.max_height = 4096;
14443 } else {
14444 dev->mode_config.max_width = 8192;
14445 dev->mode_config.max_height = 8192;
14446 }
14447
14448 if (IS_845G(dev) || IS_I865G(dev)) {
14449 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14450 dev->mode_config.cursor_height = 1023;
14451 } else if (IS_GEN2(dev)) {
14452 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14453 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14454 } else {
14455 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14456 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14457 }
14458
14459 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14460
14461 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14462 INTEL_INFO(dev)->num_pipes,
14463 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14464
14465 for_each_pipe(dev_priv, pipe) {
14466 intel_crtc_init(dev, pipe);
14467 for_each_sprite(dev_priv, pipe, sprite) {
14468 ret = intel_plane_init(dev, pipe, sprite);
14469 if (ret)
14470 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14471 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14472 }
14473 }
14474
14475 intel_init_dpio(dev);
14476
14477 intel_shared_dpll_init(dev);
14478
14479 /* Just disable it once at startup */
14480 i915_disable_vga(dev);
14481 intel_setup_outputs(dev);
14482
14483 /* Just in case the BIOS is doing something questionable. */
14484 intel_fbc_disable(dev);
14485
14486 drm_modeset_lock_all(dev);
14487 intel_modeset_setup_hw_state(dev, false);
14488 drm_modeset_unlock_all(dev);
14489
14490 for_each_intel_crtc(dev, crtc) {
14491 if (!crtc->active)
14492 continue;
14493
14494 /*
14495 * Note that reserving the BIOS fb up front prevents us
14496 * from stuffing other stolen allocations like the ring
14497 * on top. This prevents some ugliness at boot time, and
14498 * can even allow for smooth boot transitions if the BIOS
14499 * fb is large enough for the active pipe configuration.
14500 */
14501 if (dev_priv->display.get_initial_plane_config) {
14502 dev_priv->display.get_initial_plane_config(crtc,
14503 &crtc->plane_config);
14504 /*
14505 * If the fb is shared between multiple heads, we'll
14506 * just get the first one.
14507 */
14508 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14509 }
14510 }
14511 }
14512
14513 static void intel_enable_pipe_a(struct drm_device *dev)
14514 {
14515 struct intel_connector *connector;
14516 struct drm_connector *crt = NULL;
14517 struct intel_load_detect_pipe load_detect_temp;
14518 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14519
14520 /* We can't just switch on the pipe A, we need to set things up with a
14521 * proper mode and output configuration. As a gross hack, enable pipe A
14522 * by enabling the load detect pipe once. */
14523 for_each_intel_connector(dev, connector) {
14524 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14525 crt = &connector->base;
14526 break;
14527 }
14528 }
14529
14530 if (!crt)
14531 return;
14532
14533 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14534 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14535 }
14536
14537 static bool
14538 intel_check_plane_mapping(struct intel_crtc *crtc)
14539 {
14540 struct drm_device *dev = crtc->base.dev;
14541 struct drm_i915_private *dev_priv = dev->dev_private;
14542 u32 reg, val;
14543
14544 if (INTEL_INFO(dev)->num_pipes == 1)
14545 return true;
14546
14547 reg = DSPCNTR(!crtc->plane);
14548 val = I915_READ(reg);
14549
14550 if ((val & DISPLAY_PLANE_ENABLE) &&
14551 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14552 return false;
14553
14554 return true;
14555 }
14556
14557 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14558 {
14559 struct drm_device *dev = crtc->base.dev;
14560 struct drm_i915_private *dev_priv = dev->dev_private;
14561 u32 reg;
14562
14563 /* Clear any frame start delays used for debugging left by the BIOS */
14564 reg = PIPECONF(crtc->config->cpu_transcoder);
14565 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14566
14567 /* restore vblank interrupts to correct state */
14568 drm_crtc_vblank_reset(&crtc->base);
14569 if (crtc->active) {
14570 update_scanline_offset(crtc);
14571 drm_crtc_vblank_on(&crtc->base);
14572 }
14573
14574 /* We need to sanitize the plane -> pipe mapping first because this will
14575 * disable the crtc (and hence change the state) if it is wrong. Note
14576 * that gen4+ has a fixed plane -> pipe mapping. */
14577 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14578 struct intel_connector *connector;
14579 bool plane;
14580
14581 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14582 crtc->base.base.id);
14583
14584 /* Pipe has the wrong plane attached and the plane is active.
14585 * Temporarily change the plane mapping and disable everything
14586 * ... */
14587 plane = crtc->plane;
14588 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14589 crtc->plane = !plane;
14590 intel_crtc_disable_planes(&crtc->base);
14591 dev_priv->display.crtc_disable(&crtc->base);
14592 crtc->plane = plane;
14593
14594 /* ... and break all links. */
14595 for_each_intel_connector(dev, connector) {
14596 if (connector->encoder->base.crtc != &crtc->base)
14597 continue;
14598
14599 connector->base.dpms = DRM_MODE_DPMS_OFF;
14600 connector->base.encoder = NULL;
14601 }
14602 /* multiple connectors may have the same encoder:
14603 * handle them and break crtc link separately */
14604 for_each_intel_connector(dev, connector)
14605 if (connector->encoder->base.crtc == &crtc->base) {
14606 connector->encoder->base.crtc = NULL;
14607 connector->encoder->connectors_active = false;
14608 }
14609
14610 WARN_ON(crtc->active);
14611 crtc->base.state->enable = false;
14612 crtc->base.state->active = false;
14613 crtc->base.enabled = false;
14614 }
14615
14616 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14617 crtc->pipe == PIPE_A && !crtc->active) {
14618 /* BIOS forgot to enable pipe A, this mostly happens after
14619 * resume. Force-enable the pipe to fix this, the update_dpms
14620 * call below we restore the pipe to the right state, but leave
14621 * the required bits on. */
14622 intel_enable_pipe_a(dev);
14623 }
14624
14625 /* Adjust the state of the output pipe according to whether we
14626 * have active connectors/encoders. */
14627 intel_crtc_update_dpms(&crtc->base);
14628
14629 if (crtc->active != crtc->base.state->enable) {
14630 struct intel_encoder *encoder;
14631
14632 /* This can happen either due to bugs in the get_hw_state
14633 * functions or because the pipe is force-enabled due to the
14634 * pipe A quirk. */
14635 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14636 crtc->base.base.id,
14637 crtc->base.state->enable ? "enabled" : "disabled",
14638 crtc->active ? "enabled" : "disabled");
14639
14640 crtc->base.state->enable = crtc->active;
14641 crtc->base.state->active = crtc->active;
14642 crtc->base.enabled = crtc->active;
14643
14644 /* Because we only establish the connector -> encoder ->
14645 * crtc links if something is active, this means the
14646 * crtc is now deactivated. Break the links. connector
14647 * -> encoder links are only establish when things are
14648 * actually up, hence no need to break them. */
14649 WARN_ON(crtc->active);
14650
14651 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14652 WARN_ON(encoder->connectors_active);
14653 encoder->base.crtc = NULL;
14654 }
14655 }
14656
14657 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14658 /*
14659 * We start out with underrun reporting disabled to avoid races.
14660 * For correct bookkeeping mark this on active crtcs.
14661 *
14662 * Also on gmch platforms we dont have any hardware bits to
14663 * disable the underrun reporting. Which means we need to start
14664 * out with underrun reporting disabled also on inactive pipes,
14665 * since otherwise we'll complain about the garbage we read when
14666 * e.g. coming up after runtime pm.
14667 *
14668 * No protection against concurrent access is required - at
14669 * worst a fifo underrun happens which also sets this to false.
14670 */
14671 crtc->cpu_fifo_underrun_disabled = true;
14672 crtc->pch_fifo_underrun_disabled = true;
14673 }
14674 }
14675
14676 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14677 {
14678 struct intel_connector *connector;
14679 struct drm_device *dev = encoder->base.dev;
14680
14681 /* We need to check both for a crtc link (meaning that the
14682 * encoder is active and trying to read from a pipe) and the
14683 * pipe itself being active. */
14684 bool has_active_crtc = encoder->base.crtc &&
14685 to_intel_crtc(encoder->base.crtc)->active;
14686
14687 if (encoder->connectors_active && !has_active_crtc) {
14688 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14689 encoder->base.base.id,
14690 encoder->base.name);
14691
14692 /* Connector is active, but has no active pipe. This is
14693 * fallout from our resume register restoring. Disable
14694 * the encoder manually again. */
14695 if (encoder->base.crtc) {
14696 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14697 encoder->base.base.id,
14698 encoder->base.name);
14699 encoder->disable(encoder);
14700 if (encoder->post_disable)
14701 encoder->post_disable(encoder);
14702 }
14703 encoder->base.crtc = NULL;
14704 encoder->connectors_active = false;
14705
14706 /* Inconsistent output/port/pipe state happens presumably due to
14707 * a bug in one of the get_hw_state functions. Or someplace else
14708 * in our code, like the register restore mess on resume. Clamp
14709 * things to off as a safer default. */
14710 for_each_intel_connector(dev, connector) {
14711 if (connector->encoder != encoder)
14712 continue;
14713 connector->base.dpms = DRM_MODE_DPMS_OFF;
14714 connector->base.encoder = NULL;
14715 }
14716 }
14717 /* Enabled encoders without active connectors will be fixed in
14718 * the crtc fixup. */
14719 }
14720
14721 void i915_redisable_vga_power_on(struct drm_device *dev)
14722 {
14723 struct drm_i915_private *dev_priv = dev->dev_private;
14724 u32 vga_reg = i915_vgacntrl_reg(dev);
14725
14726 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14727 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14728 i915_disable_vga(dev);
14729 }
14730 }
14731
14732 void i915_redisable_vga(struct drm_device *dev)
14733 {
14734 struct drm_i915_private *dev_priv = dev->dev_private;
14735
14736 /* This function can be called both from intel_modeset_setup_hw_state or
14737 * at a very early point in our resume sequence, where the power well
14738 * structures are not yet restored. Since this function is at a very
14739 * paranoid "someone might have enabled VGA while we were not looking"
14740 * level, just check if the power well is enabled instead of trying to
14741 * follow the "don't touch the power well if we don't need it" policy
14742 * the rest of the driver uses. */
14743 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14744 return;
14745
14746 i915_redisable_vga_power_on(dev);
14747 }
14748
14749 static bool primary_get_hw_state(struct intel_crtc *crtc)
14750 {
14751 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14752
14753 if (!crtc->active)
14754 return false;
14755
14756 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14757 }
14758
14759 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14760 {
14761 struct drm_i915_private *dev_priv = dev->dev_private;
14762 enum pipe pipe;
14763 struct intel_crtc *crtc;
14764 struct intel_encoder *encoder;
14765 struct intel_connector *connector;
14766 int i;
14767
14768 for_each_intel_crtc(dev, crtc) {
14769 struct drm_plane *primary = crtc->base.primary;
14770 struct intel_plane_state *plane_state;
14771
14772 memset(crtc->config, 0, sizeof(*crtc->config));
14773
14774 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14775
14776 crtc->active = dev_priv->display.get_pipe_config(crtc,
14777 crtc->config);
14778
14779 crtc->base.state->enable = crtc->active;
14780 crtc->base.state->active = crtc->active;
14781 crtc->base.enabled = crtc->active;
14782
14783 plane_state = to_intel_plane_state(primary->state);
14784 plane_state->visible = primary_get_hw_state(crtc);
14785
14786 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14787 crtc->base.base.id,
14788 crtc->active ? "enabled" : "disabled");
14789 }
14790
14791 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14792 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14793
14794 pll->on = pll->get_hw_state(dev_priv, pll,
14795 &pll->config.hw_state);
14796 pll->active = 0;
14797 pll->config.crtc_mask = 0;
14798 for_each_intel_crtc(dev, crtc) {
14799 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14800 pll->active++;
14801 pll->config.crtc_mask |= 1 << crtc->pipe;
14802 }
14803 }
14804
14805 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14806 pll->name, pll->config.crtc_mask, pll->on);
14807
14808 if (pll->config.crtc_mask)
14809 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14810 }
14811
14812 for_each_intel_encoder(dev, encoder) {
14813 pipe = 0;
14814
14815 if (encoder->get_hw_state(encoder, &pipe)) {
14816 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14817 encoder->base.crtc = &crtc->base;
14818 encoder->get_config(encoder, crtc->config);
14819 } else {
14820 encoder->base.crtc = NULL;
14821 }
14822
14823 encoder->connectors_active = false;
14824 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14825 encoder->base.base.id,
14826 encoder->base.name,
14827 encoder->base.crtc ? "enabled" : "disabled",
14828 pipe_name(pipe));
14829 }
14830
14831 for_each_intel_connector(dev, connector) {
14832 if (connector->get_hw_state(connector)) {
14833 connector->base.dpms = DRM_MODE_DPMS_ON;
14834 connector->encoder->connectors_active = true;
14835 connector->base.encoder = &connector->encoder->base;
14836 } else {
14837 connector->base.dpms = DRM_MODE_DPMS_OFF;
14838 connector->base.encoder = NULL;
14839 }
14840 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14841 connector->base.base.id,
14842 connector->base.name,
14843 connector->base.encoder ? "enabled" : "disabled");
14844 }
14845 }
14846
14847 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14848 * and i915 state tracking structures. */
14849 void intel_modeset_setup_hw_state(struct drm_device *dev,
14850 bool force_restore)
14851 {
14852 struct drm_i915_private *dev_priv = dev->dev_private;
14853 enum pipe pipe;
14854 struct intel_crtc *crtc;
14855 struct intel_encoder *encoder;
14856 int i;
14857
14858 intel_modeset_readout_hw_state(dev);
14859
14860 /*
14861 * Now that we have the config, copy it to each CRTC struct
14862 * Note that this could go away if we move to using crtc_config
14863 * checking everywhere.
14864 */
14865 for_each_intel_crtc(dev, crtc) {
14866 if (crtc->active && i915.fastboot) {
14867 intel_mode_from_pipe_config(&crtc->base.mode,
14868 crtc->config);
14869 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14870 crtc->base.base.id);
14871 drm_mode_debug_printmodeline(&crtc->base.mode);
14872 }
14873 }
14874
14875 /* HW state is read out, now we need to sanitize this mess. */
14876 for_each_intel_encoder(dev, encoder) {
14877 intel_sanitize_encoder(encoder);
14878 }
14879
14880 for_each_pipe(dev_priv, pipe) {
14881 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14882 intel_sanitize_crtc(crtc);
14883 intel_dump_pipe_config(crtc, crtc->config,
14884 "[setup_hw_state]");
14885 }
14886
14887 intel_modeset_update_connector_atomic_state(dev);
14888
14889 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14890 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14891
14892 if (!pll->on || pll->active)
14893 continue;
14894
14895 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14896
14897 pll->disable(dev_priv, pll);
14898 pll->on = false;
14899 }
14900
14901 if (IS_GEN9(dev))
14902 skl_wm_get_hw_state(dev);
14903 else if (HAS_PCH_SPLIT(dev))
14904 ilk_wm_get_hw_state(dev);
14905
14906 if (force_restore) {
14907 i915_redisable_vga(dev);
14908
14909 /*
14910 * We need to use raw interfaces for restoring state to avoid
14911 * checking (bogus) intermediate states.
14912 */
14913 for_each_pipe(dev_priv, pipe) {
14914 struct drm_crtc *crtc =
14915 dev_priv->pipe_to_crtc_mapping[pipe];
14916
14917 intel_crtc_restore_mode(crtc);
14918 }
14919 } else {
14920 intel_modeset_update_staged_output_state(dev);
14921 }
14922
14923 intel_modeset_check_state(dev);
14924 }
14925
14926 void intel_modeset_gem_init(struct drm_device *dev)
14927 {
14928 struct drm_i915_private *dev_priv = dev->dev_private;
14929 struct drm_crtc *c;
14930 struct drm_i915_gem_object *obj;
14931 int ret;
14932
14933 mutex_lock(&dev->struct_mutex);
14934 intel_init_gt_powersave(dev);
14935 mutex_unlock(&dev->struct_mutex);
14936
14937 /*
14938 * There may be no VBT; and if the BIOS enabled SSC we can
14939 * just keep using it to avoid unnecessary flicker. Whereas if the
14940 * BIOS isn't using it, don't assume it will work even if the VBT
14941 * indicates as much.
14942 */
14943 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14944 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14945 DREF_SSC1_ENABLE);
14946
14947 intel_modeset_init_hw(dev);
14948
14949 intel_setup_overlay(dev);
14950
14951 /*
14952 * Make sure any fbs we allocated at startup are properly
14953 * pinned & fenced. When we do the allocation it's too early
14954 * for this.
14955 */
14956 for_each_crtc(dev, c) {
14957 obj = intel_fb_obj(c->primary->fb);
14958 if (obj == NULL)
14959 continue;
14960
14961 mutex_lock(&dev->struct_mutex);
14962 ret = intel_pin_and_fence_fb_obj(c->primary,
14963 c->primary->fb,
14964 c->primary->state,
14965 NULL);
14966 mutex_unlock(&dev->struct_mutex);
14967 if (ret) {
14968 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14969 to_intel_crtc(c)->pipe);
14970 drm_framebuffer_unreference(c->primary->fb);
14971 c->primary->fb = NULL;
14972 update_state_fb(c->primary);
14973 }
14974 }
14975
14976 intel_backlight_register(dev);
14977 }
14978
14979 void intel_connector_unregister(struct intel_connector *intel_connector)
14980 {
14981 struct drm_connector *connector = &intel_connector->base;
14982
14983 intel_panel_destroy_backlight(connector);
14984 drm_connector_unregister(connector);
14985 }
14986
14987 void intel_modeset_cleanup(struct drm_device *dev)
14988 {
14989 struct drm_i915_private *dev_priv = dev->dev_private;
14990 struct drm_connector *connector;
14991
14992 intel_disable_gt_powersave(dev);
14993
14994 intel_backlight_unregister(dev);
14995
14996 /*
14997 * Interrupts and polling as the first thing to avoid creating havoc.
14998 * Too much stuff here (turning of connectors, ...) would
14999 * experience fancy races otherwise.
15000 */
15001 intel_irq_uninstall(dev_priv);
15002
15003 /*
15004 * Due to the hpd irq storm handling the hotplug work can re-arm the
15005 * poll handlers. Hence disable polling after hpd handling is shut down.
15006 */
15007 drm_kms_helper_poll_fini(dev);
15008
15009 mutex_lock(&dev->struct_mutex);
15010
15011 intel_unregister_dsm_handler();
15012
15013 intel_fbc_disable(dev);
15014
15015 mutex_unlock(&dev->struct_mutex);
15016
15017 /* flush any delayed tasks or pending work */
15018 flush_scheduled_work();
15019
15020 /* destroy the backlight and sysfs files before encoders/connectors */
15021 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15022 struct intel_connector *intel_connector;
15023
15024 intel_connector = to_intel_connector(connector);
15025 intel_connector->unregister(intel_connector);
15026 }
15027
15028 drm_mode_config_cleanup(dev);
15029
15030 intel_cleanup_overlay(dev);
15031
15032 mutex_lock(&dev->struct_mutex);
15033 intel_cleanup_gt_powersave(dev);
15034 mutex_unlock(&dev->struct_mutex);
15035 }
15036
15037 /*
15038 * Return which encoder is currently attached for connector.
15039 */
15040 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15041 {
15042 return &intel_attached_encoder(connector)->base;
15043 }
15044
15045 void intel_connector_attach_encoder(struct intel_connector *connector,
15046 struct intel_encoder *encoder)
15047 {
15048 connector->encoder = encoder;
15049 drm_mode_connector_attach_encoder(&connector->base,
15050 &encoder->base);
15051 }
15052
15053 /*
15054 * set vga decode state - true == enable VGA decode
15055 */
15056 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15057 {
15058 struct drm_i915_private *dev_priv = dev->dev_private;
15059 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15060 u16 gmch_ctrl;
15061
15062 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15063 DRM_ERROR("failed to read control word\n");
15064 return -EIO;
15065 }
15066
15067 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15068 return 0;
15069
15070 if (state)
15071 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15072 else
15073 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15074
15075 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15076 DRM_ERROR("failed to write control word\n");
15077 return -EIO;
15078 }
15079
15080 return 0;
15081 }
15082
15083 struct intel_display_error_state {
15084
15085 u32 power_well_driver;
15086
15087 int num_transcoders;
15088
15089 struct intel_cursor_error_state {
15090 u32 control;
15091 u32 position;
15092 u32 base;
15093 u32 size;
15094 } cursor[I915_MAX_PIPES];
15095
15096 struct intel_pipe_error_state {
15097 bool power_domain_on;
15098 u32 source;
15099 u32 stat;
15100 } pipe[I915_MAX_PIPES];
15101
15102 struct intel_plane_error_state {
15103 u32 control;
15104 u32 stride;
15105 u32 size;
15106 u32 pos;
15107 u32 addr;
15108 u32 surface;
15109 u32 tile_offset;
15110 } plane[I915_MAX_PIPES];
15111
15112 struct intel_transcoder_error_state {
15113 bool power_domain_on;
15114 enum transcoder cpu_transcoder;
15115
15116 u32 conf;
15117
15118 u32 htotal;
15119 u32 hblank;
15120 u32 hsync;
15121 u32 vtotal;
15122 u32 vblank;
15123 u32 vsync;
15124 } transcoder[4];
15125 };
15126
15127 struct intel_display_error_state *
15128 intel_display_capture_error_state(struct drm_device *dev)
15129 {
15130 struct drm_i915_private *dev_priv = dev->dev_private;
15131 struct intel_display_error_state *error;
15132 int transcoders[] = {
15133 TRANSCODER_A,
15134 TRANSCODER_B,
15135 TRANSCODER_C,
15136 TRANSCODER_EDP,
15137 };
15138 int i;
15139
15140 if (INTEL_INFO(dev)->num_pipes == 0)
15141 return NULL;
15142
15143 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15144 if (error == NULL)
15145 return NULL;
15146
15147 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15148 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15149
15150 for_each_pipe(dev_priv, i) {
15151 error->pipe[i].power_domain_on =
15152 __intel_display_power_is_enabled(dev_priv,
15153 POWER_DOMAIN_PIPE(i));
15154 if (!error->pipe[i].power_domain_on)
15155 continue;
15156
15157 error->cursor[i].control = I915_READ(CURCNTR(i));
15158 error->cursor[i].position = I915_READ(CURPOS(i));
15159 error->cursor[i].base = I915_READ(CURBASE(i));
15160
15161 error->plane[i].control = I915_READ(DSPCNTR(i));
15162 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15163 if (INTEL_INFO(dev)->gen <= 3) {
15164 error->plane[i].size = I915_READ(DSPSIZE(i));
15165 error->plane[i].pos = I915_READ(DSPPOS(i));
15166 }
15167 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15168 error->plane[i].addr = I915_READ(DSPADDR(i));
15169 if (INTEL_INFO(dev)->gen >= 4) {
15170 error->plane[i].surface = I915_READ(DSPSURF(i));
15171 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15172 }
15173
15174 error->pipe[i].source = I915_READ(PIPESRC(i));
15175
15176 if (HAS_GMCH_DISPLAY(dev))
15177 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15178 }
15179
15180 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15181 if (HAS_DDI(dev_priv->dev))
15182 error->num_transcoders++; /* Account for eDP. */
15183
15184 for (i = 0; i < error->num_transcoders; i++) {
15185 enum transcoder cpu_transcoder = transcoders[i];
15186
15187 error->transcoder[i].power_domain_on =
15188 __intel_display_power_is_enabled(dev_priv,
15189 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15190 if (!error->transcoder[i].power_domain_on)
15191 continue;
15192
15193 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15194
15195 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15196 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15197 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15198 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15199 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15200 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15201 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15202 }
15203
15204 return error;
15205 }
15206
15207 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15208
15209 void
15210 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15211 struct drm_device *dev,
15212 struct intel_display_error_state *error)
15213 {
15214 struct drm_i915_private *dev_priv = dev->dev_private;
15215 int i;
15216
15217 if (!error)
15218 return;
15219
15220 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15221 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15222 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15223 error->power_well_driver);
15224 for_each_pipe(dev_priv, i) {
15225 err_printf(m, "Pipe [%d]:\n", i);
15226 err_printf(m, " Power: %s\n",
15227 error->pipe[i].power_domain_on ? "on" : "off");
15228 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15229 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15230
15231 err_printf(m, "Plane [%d]:\n", i);
15232 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15233 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15234 if (INTEL_INFO(dev)->gen <= 3) {
15235 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15236 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15237 }
15238 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15239 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15240 if (INTEL_INFO(dev)->gen >= 4) {
15241 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15242 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15243 }
15244
15245 err_printf(m, "Cursor [%d]:\n", i);
15246 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15247 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15248 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15249 }
15250
15251 for (i = 0; i < error->num_transcoders; i++) {
15252 err_printf(m, "CPU transcoder: %c\n",
15253 transcoder_name(error->transcoder[i].cpu_transcoder));
15254 err_printf(m, " Power: %s\n",
15255 error->transcoder[i].power_domain_on ? "on" : "off");
15256 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15257 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15258 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15259 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15260 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15261 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15262 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15263 }
15264 }
15265
15266 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15267 {
15268 struct intel_crtc *crtc;
15269
15270 for_each_intel_crtc(dev, crtc) {
15271 struct intel_unpin_work *work;
15272
15273 spin_lock_irq(&dev->event_lock);
15274
15275 work = crtc->unpin_work;
15276
15277 if (work && work->event &&
15278 work->event->base.file_priv == file) {
15279 kfree(work->event);
15280 work->event = NULL;
15281 }
15282
15283 spin_unlock_irq(&dev->event_lock);
15284 }
15285 }
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