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Merge branch 'drm-next-3.14-wip' of git://people.freedesktop.org/~agd5f/linux into...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
46
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
51
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
56 typedef struct {
57 int min, max;
58 } intel_range_t;
59
60 typedef struct {
61 int dot_limit;
62 int p2_slow, p2_fast;
63 } intel_p2_t;
64
65 typedef struct intel_limit intel_limit_t;
66 struct intel_limit {
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
69 };
70
71 int
72 intel_pch_rawclk(struct drm_device *dev)
73 {
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79 }
80
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
83 {
84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
89 }
90
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 908000, .max = 1512000 },
94 .n = { .min = 2, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
102 };
103
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 908000, .max = 1512000 },
107 .n = { .min = 2, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115 };
116
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 908000, .max = 1512000 },
120 .n = { .min = 2, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
128 };
129
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
141 };
142
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
154 };
155
156
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
169 },
170 };
171
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
183 };
184
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
196 },
197 };
198
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
210 },
211 };
212
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
226 };
227
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
239 };
240
241 /* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
257 };
258
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
270 };
271
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
283 };
284
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 };
311
312 static const intel_limit_t intel_limits_vlv = {
313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
326 };
327
328 static void vlv_clock(int refclk, intel_clock_t *clock)
329 {
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 if (WARN_ON(clock->n == 0 || clock->p == 0))
333 return;
334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
336 }
337
338 /**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342 {
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351 }
352
353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
355 {
356 struct drm_device *dev = crtc->dev;
357 const intel_limit_t *limit;
358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
360 if (intel_is_dual_link_lvds(dev)) {
361 if (refclk == 100000)
362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
366 if (refclk == 100000)
367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
371 } else
372 limit = &intel_limits_ironlake_dac;
373
374 return limit;
375 }
376
377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378 {
379 struct drm_device *dev = crtc->dev;
380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
383 if (intel_is_dual_link_lvds(dev))
384 limit = &intel_limits_g4x_dual_channel_lvds;
385 else
386 limit = &intel_limits_g4x_single_channel_lvds;
387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
389 limit = &intel_limits_g4x_hdmi;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
391 limit = &intel_limits_g4x_sdvo;
392 } else /* The option is for other outputs */
393 limit = &intel_limits_i9xx_sdvo;
394
395 return limit;
396 }
397
398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
399 {
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
403 if (HAS_PCH_SPLIT(dev))
404 limit = intel_ironlake_limit(crtc, refclk);
405 else if (IS_G4X(dev)) {
406 limit = intel_g4x_limit(crtc);
407 } else if (IS_PINEVIEW(dev)) {
408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
409 limit = &intel_limits_pineview_lvds;
410 else
411 limit = &intel_limits_pineview_sdvo;
412 } else if (IS_VALLEYVIEW(dev)) {
413 limit = &intel_limits_vlv;
414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
417 else
418 limit = &intel_limits_i9xx_sdvo;
419 } else {
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
421 limit = &intel_limits_i8xx_lvds;
422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
423 limit = &intel_limits_i8xx_dvo;
424 else
425 limit = &intel_limits_i8xx_dac;
426 }
427 return limit;
428 }
429
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk, intel_clock_t *clock)
432 {
433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
435 if (WARN_ON(clock->n == 0 || clock->p == 0))
436 return;
437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
439 }
440
441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
442 {
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
444 }
445
446 static void i9xx_clock(int refclk, intel_clock_t *clock)
447 {
448 clock->m = i9xx_dpll_compute_m(clock);
449 clock->p = clock->p1 * clock->p2;
450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
451 return;
452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
454 }
455
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 /**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
465 {
466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
474
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
478
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
484 }
485
486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
490 */
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
492 INTELPllInvalid("dot out of range\n");
493
494 return true;
495 }
496
497 static bool
498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
501 {
502 struct drm_device *dev = crtc->dev;
503 intel_clock_t clock;
504 int err = target;
505
506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
507 /*
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
511 */
512 if (intel_is_dual_link_lvds(dev))
513 clock.p2 = limit->p2.p2_fast;
514 else
515 clock.p2 = limit->p2.p2_slow;
516 } else {
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
519 else
520 clock.p2 = limit->p2.p2_fast;
521 }
522
523 memset(best_clock, 0, sizeof(*best_clock));
524
525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
526 clock.m1++) {
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
529 if (clock.m2 >= clock.m1)
530 break;
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
535 int this_err;
536
537 i9xx_clock(refclk, &clock);
538 if (!intel_PLL_is_valid(dev, limit,
539 &clock))
540 continue;
541 if (match_clock &&
542 clock.p != match_clock->p)
543 continue;
544
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
547 *best_clock = clock;
548 err = this_err;
549 }
550 }
551 }
552 }
553 }
554
555 return (err != target);
556 }
557
558 static bool
559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
562 {
563 struct drm_device *dev = crtc->dev;
564 intel_clock_t clock;
565 int err = target;
566
567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
568 /*
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
572 */
573 if (intel_is_dual_link_lvds(dev))
574 clock.p2 = limit->p2.p2_fast;
575 else
576 clock.p2 = limit->p2.p2_slow;
577 } else {
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
580 else
581 clock.p2 = limit->p2.p2_fast;
582 }
583
584 memset(best_clock, 0, sizeof(*best_clock));
585
586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
587 clock.m1++) {
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
594 int this_err;
595
596 pineview_clock(refclk, &clock);
597 if (!intel_PLL_is_valid(dev, limit,
598 &clock))
599 continue;
600 if (match_clock &&
601 clock.p != match_clock->p)
602 continue;
603
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
606 *best_clock = clock;
607 err = this_err;
608 }
609 }
610 }
611 }
612 }
613
614 return (err != target);
615 }
616
617 static bool
618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
621 {
622 struct drm_device *dev = crtc->dev;
623 intel_clock_t clock;
624 int max_n;
625 bool found;
626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
628 found = false;
629
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
631 if (intel_is_dual_link_lvds(dev))
632 clock.p2 = limit->p2.p2_fast;
633 else
634 clock.p2 = limit->p2.p2_slow;
635 } else {
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
638 else
639 clock.p2 = limit->p2.p2_fast;
640 }
641
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
653 int this_err;
654
655 i9xx_clock(refclk, &clock);
656 if (!intel_PLL_is_valid(dev, limit,
657 &clock))
658 continue;
659
660 this_err = abs(clock.dot - target);
661 if (this_err < err_most) {
662 *best_clock = clock;
663 err_most = this_err;
664 max_n = clock.n;
665 found = true;
666 }
667 }
668 }
669 }
670 }
671 return found;
672 }
673
674 static bool
675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678 {
679 struct drm_device *dev = crtc->dev;
680 intel_clock_t clock;
681 unsigned int bestppm = 1000000;
682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
684 bool found = false;
685
686 target *= 5; /* fast clock */
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
695 clock.p = clock.p1 * clock.p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
698 unsigned int ppm, diff;
699
700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
701 refclk * clock.m1);
702
703 vlv_clock(refclk, &clock);
704
705 if (!intel_PLL_is_valid(dev, limit,
706 &clock))
707 continue;
708
709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
711
712 if (ppm < 100 && clock.p > best_clock->p) {
713 bestppm = 0;
714 *best_clock = clock;
715 found = true;
716 }
717
718 if (bestppm >= 10 && ppm < bestppm - 10) {
719 bestppm = ppm;
720 *best_clock = clock;
721 found = true;
722 }
723 }
724 }
725 }
726 }
727
728 return found;
729 }
730
731 bool intel_crtc_active(struct drm_crtc *crtc)
732 {
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
737 *
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
740 *
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
743 */
744 return intel_crtc->active && crtc->fb &&
745 intel_crtc->config.adjusted_mode.crtc_clock;
746 }
747
748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
749 enum pipe pipe)
750 {
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
753
754 return intel_crtc->config.cpu_transcoder;
755 }
756
757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
758 {
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
761
762 frame = I915_READ(frame_reg);
763
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
766 }
767
768 /**
769 * intel_wait_for_vblank - wait for vblank on a given pipe
770 * @dev: drm device
771 * @pipe: pipe to wait for
772 *
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
774 * mode setting code.
775 */
776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
777 {
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 int pipestat_reg = PIPESTAT(pipe);
780
781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
783 return;
784 }
785
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
788 *
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
795 * vblanks...
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
798 */
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
801
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
805 50))
806 DRM_DEBUG_KMS("vblank wait timed out\n");
807 }
808
809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
810 {
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
813 u32 line1, line2;
814 u32 line_mask;
815
816 if (IS_GEN2(dev))
817 line_mask = DSL_LINEMASK_GEN2;
818 else
819 line_mask = DSL_LINEMASK_GEN3;
820
821 line1 = I915_READ(reg) & line_mask;
822 mdelay(5);
823 line2 = I915_READ(reg) & line_mask;
824
825 return line1 == line2;
826 }
827
828 /*
829 * intel_wait_for_pipe_off - wait for pipe to turn off
830 * @dev: drm device
831 * @pipe: pipe to wait for
832 *
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
836 *
837 * On Gen4 and above:
838 * wait for the pipe register state bit to turn off
839 *
840 * Otherwise:
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
843 *
844 */
845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
846 {
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
849 pipe);
850
851 if (INTEL_INFO(dev)->gen >= 4) {
852 int reg = PIPECONF(cpu_transcoder);
853
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
856 100))
857 WARN(1, "pipe_off wait timed out\n");
858 } else {
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
861 WARN(1, "pipe_off wait timed out\n");
862 }
863 }
864
865 /*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874 {
875 u32 bit;
876
877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
905 }
906
907 return I915_READ(SDEISR) & bit;
908 }
909
910 static const char *state_string(bool enabled)
911 {
912 return enabled ? "on" : "off";
913 }
914
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
918 {
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929 }
930
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933 {
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945 }
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951 {
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
954 if (crtc->config.shared_dpll < 0)
955 return NULL;
956
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
958 }
959
960 /* For ILK+ */
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
964 {
965 bool cur_state;
966 struct intel_dpll_hw_state hw_state;
967
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
973 if (WARN (!pll,
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
975 return;
976
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
981 }
982
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985 {
986 int reg;
987 u32 val;
988 bool cur_state;
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
991
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011 {
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028 {
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1038 return;
1039
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062 {
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
1066 bool locked = true;
1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1086 pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091 {
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1111 {
1112 int reg;
1113 u32 val;
1114 bool cur_state;
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
1117
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1138 {
1139 int reg;
1140 u32 val;
1141 bool cur_state;
1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156 {
1157 struct drm_device *dev = dev_priv->dev;
1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
1169 return;
1170 }
1171
1172 /* Need to check both planes against the pipe */
1173 for_each_pipe(i) {
1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1181 }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186 {
1187 struct drm_device *dev = dev_priv->dev;
1188 int reg, i;
1189 u32 val;
1190
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1211 }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216 u32 val;
1217 bool enabled;
1218
1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265 {
1266 if ((val & SDVO_ENABLE) == 0)
1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271 return false;
1272 } else {
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274 return false;
1275 }
1276 return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281 {
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297 {
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1312 {
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1317
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325 {
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1330
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338 {
1339 int reg;
1340 u32 val;
1341
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 pipe_name(pipe));
1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356 pipe_name(pipe));
1357
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 if (!IS_VALLEYVIEW(dev))
1368 return;
1369
1370 /* Enable the CRI clock source so we can get at the display */
1371 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1372 DPLL_INTEGRATED_CRI_CLK_VLV);
1373
1374 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1375 /*
1376 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1377 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1378 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1379 * b. The other bits such as sfr settings / modesel may all be set
1380 * to 0.
1381 *
1382 * This should only be done on init and resume from S3 with both
1383 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1384 */
1385 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1386 }
1387
1388 static void vlv_enable_pll(struct intel_crtc *crtc)
1389 {
1390 struct drm_device *dev = crtc->base.dev;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 int reg = DPLL(crtc->pipe);
1393 u32 dpll = crtc->config.dpll_hw_state.dpll;
1394
1395 assert_pipe_disabled(dev_priv, crtc->pipe);
1396
1397 /* No really, not for ILK+ */
1398 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1399
1400 /* PLL is protected by panel, make sure we can write it */
1401 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1402 assert_panel_unlocked(dev_priv, crtc->pipe);
1403
1404 I915_WRITE(reg, dpll);
1405 POSTING_READ(reg);
1406 udelay(150);
1407
1408 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1409 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1410
1411 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1412 POSTING_READ(DPLL_MD(crtc->pipe));
1413
1414 /* We do this three times for luck */
1415 I915_WRITE(reg, dpll);
1416 POSTING_READ(reg);
1417 udelay(150); /* wait for warmup */
1418 I915_WRITE(reg, dpll);
1419 POSTING_READ(reg);
1420 udelay(150); /* wait for warmup */
1421 I915_WRITE(reg, dpll);
1422 POSTING_READ(reg);
1423 udelay(150); /* wait for warmup */
1424 }
1425
1426 static void i9xx_enable_pll(struct intel_crtc *crtc)
1427 {
1428 struct drm_device *dev = crtc->base.dev;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 int reg = DPLL(crtc->pipe);
1431 u32 dpll = crtc->config.dpll_hw_state.dpll;
1432
1433 assert_pipe_disabled(dev_priv, crtc->pipe);
1434
1435 /* No really, not for ILK+ */
1436 BUG_ON(dev_priv->info->gen >= 5);
1437
1438 /* PLL is protected by panel, make sure we can write it */
1439 if (IS_MOBILE(dev) && !IS_I830(dev))
1440 assert_panel_unlocked(dev_priv, crtc->pipe);
1441
1442 I915_WRITE(reg, dpll);
1443
1444 /* Wait for the clocks to stabilize. */
1445 POSTING_READ(reg);
1446 udelay(150);
1447
1448 if (INTEL_INFO(dev)->gen >= 4) {
1449 I915_WRITE(DPLL_MD(crtc->pipe),
1450 crtc->config.dpll_hw_state.dpll_md);
1451 } else {
1452 /* The pixel multiplier can only be updated once the
1453 * DPLL is enabled and the clocks are stable.
1454 *
1455 * So write it again.
1456 */
1457 I915_WRITE(reg, dpll);
1458 }
1459
1460 /* We do this three times for luck */
1461 I915_WRITE(reg, dpll);
1462 POSTING_READ(reg);
1463 udelay(150); /* wait for warmup */
1464 I915_WRITE(reg, dpll);
1465 POSTING_READ(reg);
1466 udelay(150); /* wait for warmup */
1467 I915_WRITE(reg, dpll);
1468 POSTING_READ(reg);
1469 udelay(150); /* wait for warmup */
1470 }
1471
1472 /**
1473 * i9xx_disable_pll - disable a PLL
1474 * @dev_priv: i915 private structure
1475 * @pipe: pipe PLL to disable
1476 *
1477 * Disable the PLL for @pipe, making sure the pipe is off first.
1478 *
1479 * Note! This is for pre-ILK only.
1480 */
1481 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1482 {
1483 /* Don't disable pipe A or pipe A PLLs if needed */
1484 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1485 return;
1486
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1489
1490 I915_WRITE(DPLL(pipe), 0);
1491 POSTING_READ(DPLL(pipe));
1492 }
1493
1494 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496 u32 val = 0;
1497
1498 /* Make sure the pipe isn't still relying on us */
1499 assert_pipe_disabled(dev_priv, pipe);
1500
1501 /* Leave integrated clock source enabled */
1502 if (pipe == PIPE_B)
1503 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1504 I915_WRITE(DPLL(pipe), val);
1505 POSTING_READ(DPLL(pipe));
1506 }
1507
1508 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1509 struct intel_digital_port *dport)
1510 {
1511 u32 port_mask;
1512
1513 switch (dport->port) {
1514 case PORT_B:
1515 port_mask = DPLL_PORTB_READY_MASK;
1516 break;
1517 case PORT_C:
1518 port_mask = DPLL_PORTC_READY_MASK;
1519 break;
1520 default:
1521 BUG();
1522 }
1523
1524 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1525 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1526 port_name(dport->port), I915_READ(DPLL(0)));
1527 }
1528
1529 /**
1530 * ironlake_enable_shared_dpll - enable PCH PLL
1531 * @dev_priv: i915 private structure
1532 * @pipe: pipe PLL to enable
1533 *
1534 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1535 * drives the transcoder clock.
1536 */
1537 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1538 {
1539 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1540 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1541
1542 /* PCH PLLs only available on ILK, SNB and IVB */
1543 BUG_ON(dev_priv->info->gen < 5);
1544 if (WARN_ON(pll == NULL))
1545 return;
1546
1547 if (WARN_ON(pll->refcount == 0))
1548 return;
1549
1550 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1551 pll->name, pll->active, pll->on,
1552 crtc->base.base.id);
1553
1554 if (pll->active++) {
1555 WARN_ON(!pll->on);
1556 assert_shared_dpll_enabled(dev_priv, pll);
1557 return;
1558 }
1559 WARN_ON(pll->on);
1560
1561 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1562 pll->enable(dev_priv, pll);
1563 pll->on = true;
1564 }
1565
1566 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1567 {
1568 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1569 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1570
1571 /* PCH only available on ILK+ */
1572 BUG_ON(dev_priv->info->gen < 5);
1573 if (WARN_ON(pll == NULL))
1574 return;
1575
1576 if (WARN_ON(pll->refcount == 0))
1577 return;
1578
1579 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1580 pll->name, pll->active, pll->on,
1581 crtc->base.base.id);
1582
1583 if (WARN_ON(pll->active == 0)) {
1584 assert_shared_dpll_disabled(dev_priv, pll);
1585 return;
1586 }
1587
1588 assert_shared_dpll_enabled(dev_priv, pll);
1589 WARN_ON(!pll->on);
1590 if (--pll->active)
1591 return;
1592
1593 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1594 pll->disable(dev_priv, pll);
1595 pll->on = false;
1596 }
1597
1598 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1599 enum pipe pipe)
1600 {
1601 struct drm_device *dev = dev_priv->dev;
1602 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1604 uint32_t reg, val, pipeconf_val;
1605
1606 /* PCH only available on ILK+ */
1607 BUG_ON(dev_priv->info->gen < 5);
1608
1609 /* Make sure PCH DPLL is enabled */
1610 assert_shared_dpll_enabled(dev_priv,
1611 intel_crtc_to_shared_dpll(intel_crtc));
1612
1613 /* FDI must be feeding us bits for PCH ports */
1614 assert_fdi_tx_enabled(dev_priv, pipe);
1615 assert_fdi_rx_enabled(dev_priv, pipe);
1616
1617 if (HAS_PCH_CPT(dev)) {
1618 /* Workaround: Set the timing override bit before enabling the
1619 * pch transcoder. */
1620 reg = TRANS_CHICKEN2(pipe);
1621 val = I915_READ(reg);
1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623 I915_WRITE(reg, val);
1624 }
1625
1626 reg = PCH_TRANSCONF(pipe);
1627 val = I915_READ(reg);
1628 pipeconf_val = I915_READ(PIPECONF(pipe));
1629
1630 if (HAS_PCH_IBX(dev_priv->dev)) {
1631 /*
1632 * make the BPC in transcoder be consistent with
1633 * that in pipeconf reg.
1634 */
1635 val &= ~PIPECONF_BPC_MASK;
1636 val |= pipeconf_val & PIPECONF_BPC_MASK;
1637 }
1638
1639 val &= ~TRANS_INTERLACE_MASK;
1640 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1641 if (HAS_PCH_IBX(dev_priv->dev) &&
1642 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1643 val |= TRANS_LEGACY_INTERLACED_ILK;
1644 else
1645 val |= TRANS_INTERLACED;
1646 else
1647 val |= TRANS_PROGRESSIVE;
1648
1649 I915_WRITE(reg, val | TRANS_ENABLE);
1650 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1651 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1652 }
1653
1654 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1655 enum transcoder cpu_transcoder)
1656 {
1657 u32 val, pipeconf_val;
1658
1659 /* PCH only available on ILK+ */
1660 BUG_ON(dev_priv->info->gen < 5);
1661
1662 /* FDI must be feeding us bits for PCH ports */
1663 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1664 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1665
1666 /* Workaround: set timing override bit. */
1667 val = I915_READ(_TRANSA_CHICKEN2);
1668 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1669 I915_WRITE(_TRANSA_CHICKEN2, val);
1670
1671 val = TRANS_ENABLE;
1672 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1673
1674 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1675 PIPECONF_INTERLACED_ILK)
1676 val |= TRANS_INTERLACED;
1677 else
1678 val |= TRANS_PROGRESSIVE;
1679
1680 I915_WRITE(LPT_TRANSCONF, val);
1681 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1682 DRM_ERROR("Failed to enable PCH transcoder\n");
1683 }
1684
1685 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1686 enum pipe pipe)
1687 {
1688 struct drm_device *dev = dev_priv->dev;
1689 uint32_t reg, val;
1690
1691 /* FDI relies on the transcoder */
1692 assert_fdi_tx_disabled(dev_priv, pipe);
1693 assert_fdi_rx_disabled(dev_priv, pipe);
1694
1695 /* Ports must be off as well */
1696 assert_pch_ports_disabled(dev_priv, pipe);
1697
1698 reg = PCH_TRANSCONF(pipe);
1699 val = I915_READ(reg);
1700 val &= ~TRANS_ENABLE;
1701 I915_WRITE(reg, val);
1702 /* wait for PCH transcoder off, transcoder state */
1703 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1704 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1705
1706 if (!HAS_PCH_IBX(dev)) {
1707 /* Workaround: Clear the timing override chicken bit again. */
1708 reg = TRANS_CHICKEN2(pipe);
1709 val = I915_READ(reg);
1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711 I915_WRITE(reg, val);
1712 }
1713 }
1714
1715 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1716 {
1717 u32 val;
1718
1719 val = I915_READ(LPT_TRANSCONF);
1720 val &= ~TRANS_ENABLE;
1721 I915_WRITE(LPT_TRANSCONF, val);
1722 /* wait for PCH transcoder off, transcoder state */
1723 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1724 DRM_ERROR("Failed to disable PCH transcoder\n");
1725
1726 /* Workaround: clear timing override bit. */
1727 val = I915_READ(_TRANSA_CHICKEN2);
1728 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 I915_WRITE(_TRANSA_CHICKEN2, val);
1730 }
1731
1732 /**
1733 * intel_enable_pipe - enable a pipe, asserting requirements
1734 * @dev_priv: i915 private structure
1735 * @pipe: pipe to enable
1736 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1737 *
1738 * Enable @pipe, making sure that various hardware specific requirements
1739 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1740 *
1741 * @pipe should be %PIPE_A or %PIPE_B.
1742 *
1743 * Will wait until the pipe is actually running (i.e. first vblank) before
1744 * returning.
1745 */
1746 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1747 bool pch_port, bool dsi)
1748 {
1749 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1750 pipe);
1751 enum pipe pch_transcoder;
1752 int reg;
1753 u32 val;
1754
1755 assert_planes_disabled(dev_priv, pipe);
1756 assert_cursor_disabled(dev_priv, pipe);
1757 assert_sprites_disabled(dev_priv, pipe);
1758
1759 if (HAS_PCH_LPT(dev_priv->dev))
1760 pch_transcoder = TRANSCODER_A;
1761 else
1762 pch_transcoder = pipe;
1763
1764 /*
1765 * A pipe without a PLL won't actually be able to drive bits from
1766 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1767 * need the check.
1768 */
1769 if (!HAS_PCH_SPLIT(dev_priv->dev))
1770 if (dsi)
1771 assert_dsi_pll_enabled(dev_priv);
1772 else
1773 assert_pll_enabled(dev_priv, pipe);
1774 else {
1775 if (pch_port) {
1776 /* if driving the PCH, we need FDI enabled */
1777 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1778 assert_fdi_tx_pll_enabled(dev_priv,
1779 (enum pipe) cpu_transcoder);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
1783
1784 reg = PIPECONF(cpu_transcoder);
1785 val = I915_READ(reg);
1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794 * intel_disable_pipe - disable a pipe, asserting requirements
1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807 {
1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818 assert_cursor_disabled(dev_priv, pipe);
1819 assert_sprites_disabled(dev_priv, pipe);
1820
1821 /* Don't disable pipe A or pipe A PLLs if needed */
1822 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1823 return;
1824
1825 reg = PIPECONF(cpu_transcoder);
1826 val = I915_READ(reg);
1827 if ((val & PIPECONF_ENABLE) == 0)
1828 return;
1829
1830 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1831 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1832 }
1833
1834 /*
1835 * Plane regs are double buffered, going from enabled->disabled needs a
1836 * trigger in order to latch. The display address reg provides this.
1837 */
1838 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1839 enum plane plane)
1840 {
1841 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1842
1843 I915_WRITE(reg, I915_READ(reg));
1844 POSTING_READ(reg);
1845 }
1846
1847 /**
1848 * intel_enable_primary_plane - enable the primary plane on a given pipe
1849 * @dev_priv: i915 private structure
1850 * @plane: plane to enable
1851 * @pipe: pipe being fed
1852 *
1853 * Enable @plane on @pipe, making sure that @pipe is running first.
1854 */
1855 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1856 enum plane plane, enum pipe pipe)
1857 {
1858 struct intel_crtc *intel_crtc =
1859 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1860 int reg;
1861 u32 val;
1862
1863 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1864 assert_pipe_enabled(dev_priv, pipe);
1865
1866 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1867
1868 intel_crtc->primary_enabled = true;
1869
1870 reg = DSPCNTR(plane);
1871 val = I915_READ(reg);
1872 if (val & DISPLAY_PLANE_ENABLE)
1873 return;
1874
1875 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1876 intel_flush_primary_plane(dev_priv, plane);
1877 intel_wait_for_vblank(dev_priv->dev, pipe);
1878 }
1879
1880 /**
1881 * intel_disable_primary_plane - disable the primary plane
1882 * @dev_priv: i915 private structure
1883 * @plane: plane to disable
1884 * @pipe: pipe consuming the data
1885 *
1886 * Disable @plane; should be an independent operation.
1887 */
1888 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1889 enum plane plane, enum pipe pipe)
1890 {
1891 struct intel_crtc *intel_crtc =
1892 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1893 int reg;
1894 u32 val;
1895
1896 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1897
1898 intel_crtc->primary_enabled = false;
1899
1900 reg = DSPCNTR(plane);
1901 val = I915_READ(reg);
1902 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1906 intel_flush_primary_plane(dev_priv, plane);
1907 intel_wait_for_vblank(dev_priv->dev, pipe);
1908 }
1909
1910 static bool need_vtd_wa(struct drm_device *dev)
1911 {
1912 #ifdef CONFIG_INTEL_IOMMU
1913 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1914 return true;
1915 #endif
1916 return false;
1917 }
1918
1919 int
1920 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1921 struct drm_i915_gem_object *obj,
1922 struct intel_ring_buffer *pipelined)
1923 {
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 u32 alignment;
1926 int ret;
1927
1928 switch (obj->tiling_mode) {
1929 case I915_TILING_NONE:
1930 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1931 alignment = 128 * 1024;
1932 else if (INTEL_INFO(dev)->gen >= 4)
1933 alignment = 4 * 1024;
1934 else
1935 alignment = 64 * 1024;
1936 break;
1937 case I915_TILING_X:
1938 /* pin() will align the object as required by fence */
1939 alignment = 0;
1940 break;
1941 case I915_TILING_Y:
1942 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1943 return -EINVAL;
1944 default:
1945 BUG();
1946 }
1947
1948 /* Note that the w/a also requires 64 PTE of padding following the
1949 * bo. We currently fill all unused PTE with the shadow page and so
1950 * we should always have valid PTE following the scanout preventing
1951 * the VT-d warning.
1952 */
1953 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1954 alignment = 256 * 1024;
1955
1956 dev_priv->mm.interruptible = false;
1957 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1958 if (ret)
1959 goto err_interruptible;
1960
1961 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1962 * fence, whereas 965+ only requires a fence if using
1963 * framebuffer compression. For simplicity, we always install
1964 * a fence as the cost is not that onerous.
1965 */
1966 ret = i915_gem_object_get_fence(obj);
1967 if (ret)
1968 goto err_unpin;
1969
1970 i915_gem_object_pin_fence(obj);
1971
1972 dev_priv->mm.interruptible = true;
1973 return 0;
1974
1975 err_unpin:
1976 i915_gem_object_unpin_from_display_plane(obj);
1977 err_interruptible:
1978 dev_priv->mm.interruptible = true;
1979 return ret;
1980 }
1981
1982 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1983 {
1984 i915_gem_object_unpin_fence(obj);
1985 i915_gem_object_unpin_from_display_plane(obj);
1986 }
1987
1988 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1989 * is assumed to be a power-of-two. */
1990 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1991 unsigned int tiling_mode,
1992 unsigned int cpp,
1993 unsigned int pitch)
1994 {
1995 if (tiling_mode != I915_TILING_NONE) {
1996 unsigned int tile_rows, tiles;
1997
1998 tile_rows = *y / 8;
1999 *y %= 8;
2000
2001 tiles = *x / (512/cpp);
2002 *x %= 512/cpp;
2003
2004 return tile_rows * pitch * 8 + tiles * 4096;
2005 } else {
2006 unsigned int offset;
2007
2008 offset = *y * pitch + *x * cpp;
2009 *y = 0;
2010 *x = (offset & 4095) / cpp;
2011 return offset & -4096;
2012 }
2013 }
2014
2015 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2016 int x, int y)
2017 {
2018 struct drm_device *dev = crtc->dev;
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2021 struct intel_framebuffer *intel_fb;
2022 struct drm_i915_gem_object *obj;
2023 int plane = intel_crtc->plane;
2024 unsigned long linear_offset;
2025 u32 dspcntr;
2026 u32 reg;
2027
2028 switch (plane) {
2029 case 0:
2030 case 1:
2031 break;
2032 default:
2033 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2034 return -EINVAL;
2035 }
2036
2037 intel_fb = to_intel_framebuffer(fb);
2038 obj = intel_fb->obj;
2039
2040 reg = DSPCNTR(plane);
2041 dspcntr = I915_READ(reg);
2042 /* Mask out pixel format bits in case we change it */
2043 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2044 switch (fb->pixel_format) {
2045 case DRM_FORMAT_C8:
2046 dspcntr |= DISPPLANE_8BPP;
2047 break;
2048 case DRM_FORMAT_XRGB1555:
2049 case DRM_FORMAT_ARGB1555:
2050 dspcntr |= DISPPLANE_BGRX555;
2051 break;
2052 case DRM_FORMAT_RGB565:
2053 dspcntr |= DISPPLANE_BGRX565;
2054 break;
2055 case DRM_FORMAT_XRGB8888:
2056 case DRM_FORMAT_ARGB8888:
2057 dspcntr |= DISPPLANE_BGRX888;
2058 break;
2059 case DRM_FORMAT_XBGR8888:
2060 case DRM_FORMAT_ABGR8888:
2061 dspcntr |= DISPPLANE_RGBX888;
2062 break;
2063 case DRM_FORMAT_XRGB2101010:
2064 case DRM_FORMAT_ARGB2101010:
2065 dspcntr |= DISPPLANE_BGRX101010;
2066 break;
2067 case DRM_FORMAT_XBGR2101010:
2068 case DRM_FORMAT_ABGR2101010:
2069 dspcntr |= DISPPLANE_RGBX101010;
2070 break;
2071 default:
2072 BUG();
2073 }
2074
2075 if (INTEL_INFO(dev)->gen >= 4) {
2076 if (obj->tiling_mode != I915_TILING_NONE)
2077 dspcntr |= DISPPLANE_TILED;
2078 else
2079 dspcntr &= ~DISPPLANE_TILED;
2080 }
2081
2082 if (IS_G4X(dev))
2083 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2084
2085 I915_WRITE(reg, dspcntr);
2086
2087 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2088
2089 if (INTEL_INFO(dev)->gen >= 4) {
2090 intel_crtc->dspaddr_offset =
2091 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2092 fb->bits_per_pixel / 8,
2093 fb->pitches[0]);
2094 linear_offset -= intel_crtc->dspaddr_offset;
2095 } else {
2096 intel_crtc->dspaddr_offset = linear_offset;
2097 }
2098
2099 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2100 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2101 fb->pitches[0]);
2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103 if (INTEL_INFO(dev)->gen >= 4) {
2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
2108 } else
2109 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2110 POSTING_READ(reg);
2111
2112 return 0;
2113 }
2114
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117 {
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
2124 unsigned long linear_offset;
2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
2131 case 2:
2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
2151 break;
2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
2167 break;
2168 default:
2169 BUG();
2170 }
2171
2172 if (obj->tiling_mode != I915_TILING_NONE)
2173 dspcntr |= DISPPLANE_TILED;
2174 else
2175 dspcntr &= ~DISPPLANE_TILED;
2176
2177 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2178 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2179 else
2180 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2181
2182 I915_WRITE(reg, dspcntr);
2183
2184 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2185 intel_crtc->dspaddr_offset =
2186 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2187 fb->bits_per_pixel / 8,
2188 fb->pitches[0]);
2189 linear_offset -= intel_crtc->dspaddr_offset;
2190
2191 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2192 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2193 fb->pitches[0]);
2194 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2195 I915_MODIFY_DISPBASE(DSPSURF(plane),
2196 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2197 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2198 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2199 } else {
2200 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2201 I915_WRITE(DSPLINOFF(plane), linear_offset);
2202 }
2203 POSTING_READ(reg);
2204
2205 return 0;
2206 }
2207
2208 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2209 static int
2210 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2211 int x, int y, enum mode_set_atomic state)
2212 {
2213 struct drm_device *dev = crtc->dev;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215
2216 if (dev_priv->display.disable_fbc)
2217 dev_priv->display.disable_fbc(dev);
2218 intel_increase_pllclock(crtc);
2219
2220 return dev_priv->display.update_plane(crtc, fb, x, y);
2221 }
2222
2223 void intel_display_handle_reset(struct drm_device *dev)
2224 {
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 struct drm_crtc *crtc;
2227
2228 /*
2229 * Flips in the rings have been nuked by the reset,
2230 * so complete all pending flips so that user space
2231 * will get its events and not get stuck.
2232 *
2233 * Also update the base address of all primary
2234 * planes to the the last fb to make sure we're
2235 * showing the correct fb after a reset.
2236 *
2237 * Need to make two loops over the crtcs so that we
2238 * don't try to grab a crtc mutex before the
2239 * pending_flip_queue really got woken up.
2240 */
2241
2242 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244 enum plane plane = intel_crtc->plane;
2245
2246 intel_prepare_page_flip(dev, plane);
2247 intel_finish_page_flip_plane(dev, plane);
2248 }
2249
2250 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2252
2253 mutex_lock(&crtc->mutex);
2254 /*
2255 * FIXME: Once we have proper support for primary planes (and
2256 * disabling them without disabling the entire crtc) allow again
2257 * a NULL crtc->fb.
2258 */
2259 if (intel_crtc->active && crtc->fb)
2260 dev_priv->display.update_plane(crtc, crtc->fb,
2261 crtc->x, crtc->y);
2262 mutex_unlock(&crtc->mutex);
2263 }
2264 }
2265
2266 static int
2267 intel_finish_fb(struct drm_framebuffer *old_fb)
2268 {
2269 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2270 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2271 bool was_interruptible = dev_priv->mm.interruptible;
2272 int ret;
2273
2274 /* Big Hammer, we also need to ensure that any pending
2275 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2276 * current scanout is retired before unpinning the old
2277 * framebuffer.
2278 *
2279 * This should only fail upon a hung GPU, in which case we
2280 * can safely continue.
2281 */
2282 dev_priv->mm.interruptible = false;
2283 ret = i915_gem_object_finish_gpu(obj);
2284 dev_priv->mm.interruptible = was_interruptible;
2285
2286 return ret;
2287 }
2288
2289 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2290 {
2291 struct drm_device *dev = crtc->dev;
2292 struct drm_i915_master_private *master_priv;
2293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294
2295 if (!dev->primary->master)
2296 return;
2297
2298 master_priv = dev->primary->master->driver_priv;
2299 if (!master_priv->sarea_priv)
2300 return;
2301
2302 switch (intel_crtc->pipe) {
2303 case 0:
2304 master_priv->sarea_priv->pipeA_x = x;
2305 master_priv->sarea_priv->pipeA_y = y;
2306 break;
2307 case 1:
2308 master_priv->sarea_priv->pipeB_x = x;
2309 master_priv->sarea_priv->pipeB_y = y;
2310 break;
2311 default:
2312 break;
2313 }
2314 }
2315
2316 static int
2317 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2318 struct drm_framebuffer *fb)
2319 {
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 struct drm_framebuffer *old_fb;
2324 int ret;
2325
2326 /* no fb bound */
2327 if (!fb) {
2328 DRM_ERROR("No FB bound\n");
2329 return 0;
2330 }
2331
2332 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2333 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2334 plane_name(intel_crtc->plane),
2335 INTEL_INFO(dev)->num_pipes);
2336 return -EINVAL;
2337 }
2338
2339 mutex_lock(&dev->struct_mutex);
2340 ret = intel_pin_and_fence_fb_obj(dev,
2341 to_intel_framebuffer(fb)->obj,
2342 NULL);
2343 if (ret != 0) {
2344 mutex_unlock(&dev->struct_mutex);
2345 DRM_ERROR("pin & fence failed\n");
2346 return ret;
2347 }
2348
2349 /*
2350 * Update pipe size and adjust fitter if needed: the reason for this is
2351 * that in compute_mode_changes we check the native mode (not the pfit
2352 * mode) to see if we can flip rather than do a full mode set. In the
2353 * fastboot case, we'll flip, but if we don't update the pipesrc and
2354 * pfit state, we'll end up with a big fb scanned out into the wrong
2355 * sized surface.
2356 *
2357 * To fix this properly, we need to hoist the checks up into
2358 * compute_mode_changes (or above), check the actual pfit state and
2359 * whether the platform allows pfit disable with pipe active, and only
2360 * then update the pipesrc and pfit state, even on the flip path.
2361 */
2362 if (i915_fastboot) {
2363 const struct drm_display_mode *adjusted_mode =
2364 &intel_crtc->config.adjusted_mode;
2365
2366 I915_WRITE(PIPESRC(intel_crtc->pipe),
2367 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2368 (adjusted_mode->crtc_vdisplay - 1));
2369 if (!intel_crtc->config.pch_pfit.enabled &&
2370 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2371 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2372 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2373 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2374 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2375 }
2376 }
2377
2378 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2379 if (ret) {
2380 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2381 mutex_unlock(&dev->struct_mutex);
2382 DRM_ERROR("failed to update base address\n");
2383 return ret;
2384 }
2385
2386 old_fb = crtc->fb;
2387 crtc->fb = fb;
2388 crtc->x = x;
2389 crtc->y = y;
2390
2391 if (old_fb) {
2392 if (intel_crtc->active && old_fb != fb)
2393 intel_wait_for_vblank(dev, intel_crtc->pipe);
2394 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2395 }
2396
2397 intel_update_fbc(dev);
2398 intel_edp_psr_update(dev);
2399 mutex_unlock(&dev->struct_mutex);
2400
2401 intel_crtc_update_sarea_pos(crtc, x, y);
2402
2403 return 0;
2404 }
2405
2406 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2407 {
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 int pipe = intel_crtc->pipe;
2412 u32 reg, temp;
2413
2414 /* enable normal train */
2415 reg = FDI_TX_CTL(pipe);
2416 temp = I915_READ(reg);
2417 if (IS_IVYBRIDGE(dev)) {
2418 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2419 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2420 } else {
2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2423 }
2424 I915_WRITE(reg, temp);
2425
2426 reg = FDI_RX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 if (HAS_PCH_CPT(dev)) {
2429 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2430 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2431 } else {
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_NONE;
2434 }
2435 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2436
2437 /* wait one idle pattern time */
2438 POSTING_READ(reg);
2439 udelay(1000);
2440
2441 /* IVB wants error correction enabled */
2442 if (IS_IVYBRIDGE(dev))
2443 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2444 FDI_FE_ERRC_ENABLE);
2445 }
2446
2447 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2448 {
2449 return crtc->base.enabled && crtc->active &&
2450 crtc->config.has_pch_encoder;
2451 }
2452
2453 static void ivb_modeset_global_resources(struct drm_device *dev)
2454 {
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *pipe_B_crtc =
2457 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2458 struct intel_crtc *pipe_C_crtc =
2459 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2460 uint32_t temp;
2461
2462 /*
2463 * When everything is off disable fdi C so that we could enable fdi B
2464 * with all lanes. Note that we don't care about enabled pipes without
2465 * an enabled pch encoder.
2466 */
2467 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2468 !pipe_has_enabled_pch(pipe_C_crtc)) {
2469 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2470 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2471
2472 temp = I915_READ(SOUTH_CHICKEN1);
2473 temp &= ~FDI_BC_BIFURCATION_SELECT;
2474 DRM_DEBUG_KMS("disabling fdi C rx\n");
2475 I915_WRITE(SOUTH_CHICKEN1, temp);
2476 }
2477 }
2478
2479 /* The FDI link training functions for ILK/Ibexpeak. */
2480 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2481 {
2482 struct drm_device *dev = crtc->dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2485 int pipe = intel_crtc->pipe;
2486 int plane = intel_crtc->plane;
2487 u32 reg, temp, tries;
2488
2489 /* FDI needs bits from pipe & plane first */
2490 assert_pipe_enabled(dev_priv, pipe);
2491 assert_plane_enabled(dev_priv, plane);
2492
2493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2494 for train result */
2495 reg = FDI_RX_IMR(pipe);
2496 temp = I915_READ(reg);
2497 temp &= ~FDI_RX_SYMBOL_LOCK;
2498 temp &= ~FDI_RX_BIT_LOCK;
2499 I915_WRITE(reg, temp);
2500 I915_READ(reg);
2501 udelay(150);
2502
2503 /* enable CPU FDI TX and PCH FDI RX */
2504 reg = FDI_TX_CTL(pipe);
2505 temp = I915_READ(reg);
2506 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2507 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2511
2512 reg = FDI_RX_CTL(pipe);
2513 temp = I915_READ(reg);
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_1;
2516 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518 POSTING_READ(reg);
2519 udelay(150);
2520
2521 /* Ironlake workaround, enable clock pointer after FDI enable*/
2522 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2523 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2524 FDI_RX_PHASE_SYNC_POINTER_EN);
2525
2526 reg = FDI_RX_IIR(pipe);
2527 for (tries = 0; tries < 5; tries++) {
2528 temp = I915_READ(reg);
2529 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2530
2531 if ((temp & FDI_RX_BIT_LOCK)) {
2532 DRM_DEBUG_KMS("FDI train 1 done.\n");
2533 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2534 break;
2535 }
2536 }
2537 if (tries == 5)
2538 DRM_ERROR("FDI train 1 fail!\n");
2539
2540 /* Train 2 */
2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
2545 I915_WRITE(reg, temp);
2546
2547 reg = FDI_RX_CTL(pipe);
2548 temp = I915_READ(reg);
2549 temp &= ~FDI_LINK_TRAIN_NONE;
2550 temp |= FDI_LINK_TRAIN_PATTERN_2;
2551 I915_WRITE(reg, temp);
2552
2553 POSTING_READ(reg);
2554 udelay(150);
2555
2556 reg = FDI_RX_IIR(pipe);
2557 for (tries = 0; tries < 5; tries++) {
2558 temp = I915_READ(reg);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2560
2561 if (temp & FDI_RX_SYMBOL_LOCK) {
2562 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2563 DRM_DEBUG_KMS("FDI train 2 done.\n");
2564 break;
2565 }
2566 }
2567 if (tries == 5)
2568 DRM_ERROR("FDI train 2 fail!\n");
2569
2570 DRM_DEBUG_KMS("FDI train done\n");
2571
2572 }
2573
2574 static const int snb_b_fdi_train_param[] = {
2575 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2576 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2577 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2578 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2579 };
2580
2581 /* The FDI link training functions for SNB/Cougarpoint. */
2582 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2583 {
2584 struct drm_device *dev = crtc->dev;
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2587 int pipe = intel_crtc->pipe;
2588 u32 reg, temp, i, retry;
2589
2590 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2591 for train result */
2592 reg = FDI_RX_IMR(pipe);
2593 temp = I915_READ(reg);
2594 temp &= ~FDI_RX_SYMBOL_LOCK;
2595 temp &= ~FDI_RX_BIT_LOCK;
2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
2601 /* enable CPU FDI TX and PCH FDI RX */
2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2605 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2606 temp &= ~FDI_LINK_TRAIN_NONE;
2607 temp |= FDI_LINK_TRAIN_PATTERN_1;
2608 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2609 /* SNB-B */
2610 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2611 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2612
2613 I915_WRITE(FDI_RX_MISC(pipe),
2614 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2615
2616 reg = FDI_RX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 if (HAS_PCH_CPT(dev)) {
2619 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2620 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2621 } else {
2622 temp &= ~FDI_LINK_TRAIN_NONE;
2623 temp |= FDI_LINK_TRAIN_PATTERN_1;
2624 }
2625 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2626
2627 POSTING_READ(reg);
2628 udelay(150);
2629
2630 for (i = 0; i < 4; i++) {
2631 reg = FDI_TX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2634 temp |= snb_b_fdi_train_param[i];
2635 I915_WRITE(reg, temp);
2636
2637 POSTING_READ(reg);
2638 udelay(500);
2639
2640 for (retry = 0; retry < 5; retry++) {
2641 reg = FDI_RX_IIR(pipe);
2642 temp = I915_READ(reg);
2643 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2644 if (temp & FDI_RX_BIT_LOCK) {
2645 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2646 DRM_DEBUG_KMS("FDI train 1 done.\n");
2647 break;
2648 }
2649 udelay(50);
2650 }
2651 if (retry < 5)
2652 break;
2653 }
2654 if (i == 4)
2655 DRM_ERROR("FDI train 1 fail!\n");
2656
2657 /* Train 2 */
2658 reg = FDI_TX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 temp &= ~FDI_LINK_TRAIN_NONE;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2;
2662 if (IS_GEN6(dev)) {
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 /* SNB-B */
2665 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2666 }
2667 I915_WRITE(reg, temp);
2668
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 if (HAS_PCH_CPT(dev)) {
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2674 } else {
2675 temp &= ~FDI_LINK_TRAIN_NONE;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2;
2677 }
2678 I915_WRITE(reg, temp);
2679
2680 POSTING_READ(reg);
2681 udelay(150);
2682
2683 for (i = 0; i < 4; i++) {
2684 reg = FDI_TX_CTL(pipe);
2685 temp = I915_READ(reg);
2686 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2687 temp |= snb_b_fdi_train_param[i];
2688 I915_WRITE(reg, temp);
2689
2690 POSTING_READ(reg);
2691 udelay(500);
2692
2693 for (retry = 0; retry < 5; retry++) {
2694 reg = FDI_RX_IIR(pipe);
2695 temp = I915_READ(reg);
2696 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2697 if (temp & FDI_RX_SYMBOL_LOCK) {
2698 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2699 DRM_DEBUG_KMS("FDI train 2 done.\n");
2700 break;
2701 }
2702 udelay(50);
2703 }
2704 if (retry < 5)
2705 break;
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 2 fail!\n");
2709
2710 DRM_DEBUG_KMS("FDI train done.\n");
2711 }
2712
2713 /* Manual link training for Ivy Bridge A0 parts */
2714 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2715 {
2716 struct drm_device *dev = crtc->dev;
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2719 int pipe = intel_crtc->pipe;
2720 u32 reg, temp, i, j;
2721
2722 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2723 for train result */
2724 reg = FDI_RX_IMR(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~FDI_RX_SYMBOL_LOCK;
2727 temp &= ~FDI_RX_BIT_LOCK;
2728 I915_WRITE(reg, temp);
2729
2730 POSTING_READ(reg);
2731 udelay(150);
2732
2733 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2734 I915_READ(FDI_RX_IIR(pipe)));
2735
2736 /* Try each vswing and preemphasis setting twice before moving on */
2737 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2738 /* disable first in case we need to retry */
2739 reg = FDI_TX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2742 temp &= ~FDI_TX_ENABLE;
2743 I915_WRITE(reg, temp);
2744
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_LINK_TRAIN_AUTO;
2748 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749 temp &= ~FDI_RX_ENABLE;
2750 I915_WRITE(reg, temp);
2751
2752 /* enable CPU FDI TX and PCH FDI RX */
2753 reg = FDI_TX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2757 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2758 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2759 temp |= snb_b_fdi_train_param[j/2];
2760 temp |= FDI_COMPOSITE_SYNC;
2761 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2762
2763 I915_WRITE(FDI_RX_MISC(pipe),
2764 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2765
2766 reg = FDI_RX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2769 temp |= FDI_COMPOSITE_SYNC;
2770 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2771
2772 POSTING_READ(reg);
2773 udelay(1); /* should be 0.5us */
2774
2775 for (i = 0; i < 4; i++) {
2776 reg = FDI_RX_IIR(pipe);
2777 temp = I915_READ(reg);
2778 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2779
2780 if (temp & FDI_RX_BIT_LOCK ||
2781 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2782 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2783 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2784 i);
2785 break;
2786 }
2787 udelay(1); /* should be 0.5us */
2788 }
2789 if (i == 4) {
2790 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2791 continue;
2792 }
2793
2794 /* Train 2 */
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2798 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2799 I915_WRITE(reg, temp);
2800
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2804 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2805 I915_WRITE(reg, temp);
2806
2807 POSTING_READ(reg);
2808 udelay(2); /* should be 1.5us */
2809
2810 for (i = 0; i < 4; i++) {
2811 reg = FDI_RX_IIR(pipe);
2812 temp = I915_READ(reg);
2813 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2814
2815 if (temp & FDI_RX_SYMBOL_LOCK ||
2816 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2817 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2818 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2819 i);
2820 goto train_done;
2821 }
2822 udelay(2); /* should be 1.5us */
2823 }
2824 if (i == 4)
2825 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2826 }
2827
2828 train_done:
2829 DRM_DEBUG_KMS("FDI train done.\n");
2830 }
2831
2832 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2833 {
2834 struct drm_device *dev = intel_crtc->base.dev;
2835 struct drm_i915_private *dev_priv = dev->dev_private;
2836 int pipe = intel_crtc->pipe;
2837 u32 reg, temp;
2838
2839
2840 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2841 reg = FDI_RX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2844 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2845 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2846 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2847
2848 POSTING_READ(reg);
2849 udelay(200);
2850
2851 /* Switch from Rawclk to PCDclk */
2852 temp = I915_READ(reg);
2853 I915_WRITE(reg, temp | FDI_PCDCLK);
2854
2855 POSTING_READ(reg);
2856 udelay(200);
2857
2858 /* Enable CPU FDI TX PLL, always on for Ironlake */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2862 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2863
2864 POSTING_READ(reg);
2865 udelay(100);
2866 }
2867 }
2868
2869 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2870 {
2871 struct drm_device *dev = intel_crtc->base.dev;
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 int pipe = intel_crtc->pipe;
2874 u32 reg, temp;
2875
2876 /* Switch from PCDclk to Rawclk */
2877 reg = FDI_RX_CTL(pipe);
2878 temp = I915_READ(reg);
2879 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2880
2881 /* Disable CPU FDI TX PLL */
2882 reg = FDI_TX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2885
2886 POSTING_READ(reg);
2887 udelay(100);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2892
2893 /* Wait for the clocks to turn off. */
2894 POSTING_READ(reg);
2895 udelay(100);
2896 }
2897
2898 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2899 {
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 int pipe = intel_crtc->pipe;
2904 u32 reg, temp;
2905
2906 /* disable CPU FDI tx and PCH FDI rx */
2907 reg = FDI_TX_CTL(pipe);
2908 temp = I915_READ(reg);
2909 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2910 POSTING_READ(reg);
2911
2912 reg = FDI_RX_CTL(pipe);
2913 temp = I915_READ(reg);
2914 temp &= ~(0x7 << 16);
2915 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2916 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2917
2918 POSTING_READ(reg);
2919 udelay(100);
2920
2921 /* Ironlake workaround, disable clock pointer after downing FDI */
2922 if (HAS_PCH_IBX(dev)) {
2923 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2924 }
2925
2926 /* still set train pattern 1 */
2927 reg = FDI_TX_CTL(pipe);
2928 temp = I915_READ(reg);
2929 temp &= ~FDI_LINK_TRAIN_NONE;
2930 temp |= FDI_LINK_TRAIN_PATTERN_1;
2931 I915_WRITE(reg, temp);
2932
2933 reg = FDI_RX_CTL(pipe);
2934 temp = I915_READ(reg);
2935 if (HAS_PCH_CPT(dev)) {
2936 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2937 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2938 } else {
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 }
2942 /* BPC in FDI rx is consistent with that in PIPECONF */
2943 temp &= ~(0x07 << 16);
2944 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2945 I915_WRITE(reg, temp);
2946
2947 POSTING_READ(reg);
2948 udelay(100);
2949 }
2950
2951 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2952 {
2953 struct drm_device *dev = crtc->dev;
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956 unsigned long flags;
2957 bool pending;
2958
2959 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2960 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2961 return false;
2962
2963 spin_lock_irqsave(&dev->event_lock, flags);
2964 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965 spin_unlock_irqrestore(&dev->event_lock, flags);
2966
2967 return pending;
2968 }
2969
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2971 {
2972 struct drm_device *dev = crtc->dev;
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2974
2975 if (crtc->fb == NULL)
2976 return;
2977
2978 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2979
2980 wait_event(dev_priv->pending_flip_queue,
2981 !intel_crtc_has_pending_flip(crtc));
2982
2983 mutex_lock(&dev->struct_mutex);
2984 intel_finish_fb(crtc->fb);
2985 mutex_unlock(&dev->struct_mutex);
2986 }
2987
2988 /* Program iCLKIP clock to the desired frequency */
2989 static void lpt_program_iclkip(struct drm_crtc *crtc)
2990 {
2991 struct drm_device *dev = crtc->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2994 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2995 u32 temp;
2996
2997 mutex_lock(&dev_priv->dpio_lock);
2998
2999 /* It is necessary to ungate the pixclk gate prior to programming
3000 * the divisors, and gate it back when it is done.
3001 */
3002 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3003
3004 /* Disable SSCCTL */
3005 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3006 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3007 SBI_SSCCTL_DISABLE,
3008 SBI_ICLK);
3009
3010 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3011 if (clock == 20000) {
3012 auxdiv = 1;
3013 divsel = 0x41;
3014 phaseinc = 0x20;
3015 } else {
3016 /* The iCLK virtual clock root frequency is in MHz,
3017 * but the adjusted_mode->crtc_clock in in KHz. To get the
3018 * divisors, it is necessary to divide one by another, so we
3019 * convert the virtual clock precision to KHz here for higher
3020 * precision.
3021 */
3022 u32 iclk_virtual_root_freq = 172800 * 1000;
3023 u32 iclk_pi_range = 64;
3024 u32 desired_divisor, msb_divisor_value, pi_value;
3025
3026 desired_divisor = (iclk_virtual_root_freq / clock);
3027 msb_divisor_value = desired_divisor / iclk_pi_range;
3028 pi_value = desired_divisor % iclk_pi_range;
3029
3030 auxdiv = 0;
3031 divsel = msb_divisor_value - 2;
3032 phaseinc = pi_value;
3033 }
3034
3035 /* This should not happen with any sane values */
3036 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3037 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3038 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3039 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3040
3041 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3042 clock,
3043 auxdiv,
3044 divsel,
3045 phasedir,
3046 phaseinc);
3047
3048 /* Program SSCDIVINTPHASE6 */
3049 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3050 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3051 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3052 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3053 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3054 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3055 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3056 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3057
3058 /* Program SSCAUXDIV */
3059 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3060 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3061 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3062 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3063
3064 /* Enable modulator and associated divider */
3065 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3066 temp &= ~SBI_SSCCTL_DISABLE;
3067 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3068
3069 /* Wait for initialization time */
3070 udelay(24);
3071
3072 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3073
3074 mutex_unlock(&dev_priv->dpio_lock);
3075 }
3076
3077 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3078 enum pipe pch_transcoder)
3079 {
3080 struct drm_device *dev = crtc->base.dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3083
3084 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3085 I915_READ(HTOTAL(cpu_transcoder)));
3086 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3087 I915_READ(HBLANK(cpu_transcoder)));
3088 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3089 I915_READ(HSYNC(cpu_transcoder)));
3090
3091 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3092 I915_READ(VTOTAL(cpu_transcoder)));
3093 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3094 I915_READ(VBLANK(cpu_transcoder)));
3095 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3096 I915_READ(VSYNC(cpu_transcoder)));
3097 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3098 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3099 }
3100
3101 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3102 {
3103 struct drm_i915_private *dev_priv = dev->dev_private;
3104 uint32_t temp;
3105
3106 temp = I915_READ(SOUTH_CHICKEN1);
3107 if (temp & FDI_BC_BIFURCATION_SELECT)
3108 return;
3109
3110 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3111 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3112
3113 temp |= FDI_BC_BIFURCATION_SELECT;
3114 DRM_DEBUG_KMS("enabling fdi C rx\n");
3115 I915_WRITE(SOUTH_CHICKEN1, temp);
3116 POSTING_READ(SOUTH_CHICKEN1);
3117 }
3118
3119 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3120 {
3121 struct drm_device *dev = intel_crtc->base.dev;
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3123
3124 switch (intel_crtc->pipe) {
3125 case PIPE_A:
3126 break;
3127 case PIPE_B:
3128 if (intel_crtc->config.fdi_lanes > 2)
3129 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3130 else
3131 cpt_enable_fdi_bc_bifurcation(dev);
3132
3133 break;
3134 case PIPE_C:
3135 cpt_enable_fdi_bc_bifurcation(dev);
3136
3137 break;
3138 default:
3139 BUG();
3140 }
3141 }
3142
3143 /*
3144 * Enable PCH resources required for PCH ports:
3145 * - PCH PLLs
3146 * - FDI training & RX/TX
3147 * - update transcoder timings
3148 * - DP transcoding bits
3149 * - transcoder
3150 */
3151 static void ironlake_pch_enable(struct drm_crtc *crtc)
3152 {
3153 struct drm_device *dev = crtc->dev;
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3156 int pipe = intel_crtc->pipe;
3157 u32 reg, temp;
3158
3159 assert_pch_transcoder_disabled(dev_priv, pipe);
3160
3161 if (IS_IVYBRIDGE(dev))
3162 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3163
3164 /* Write the TU size bits before fdi link training, so that error
3165 * detection works. */
3166 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3167 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3168
3169 /* For PCH output, training FDI link */
3170 dev_priv->display.fdi_link_train(crtc);
3171
3172 /* We need to program the right clock selection before writing the pixel
3173 * mutliplier into the DPLL. */
3174 if (HAS_PCH_CPT(dev)) {
3175 u32 sel;
3176
3177 temp = I915_READ(PCH_DPLL_SEL);
3178 temp |= TRANS_DPLL_ENABLE(pipe);
3179 sel = TRANS_DPLLB_SEL(pipe);
3180 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3181 temp |= sel;
3182 else
3183 temp &= ~sel;
3184 I915_WRITE(PCH_DPLL_SEL, temp);
3185 }
3186
3187 /* XXX: pch pll's can be enabled any time before we enable the PCH
3188 * transcoder, and we actually should do this to not upset any PCH
3189 * transcoder that already use the clock when we share it.
3190 *
3191 * Note that enable_shared_dpll tries to do the right thing, but
3192 * get_shared_dpll unconditionally resets the pll - we need that to have
3193 * the right LVDS enable sequence. */
3194 ironlake_enable_shared_dpll(intel_crtc);
3195
3196 /* set transcoder timing, panel must allow it */
3197 assert_panel_unlocked(dev_priv, pipe);
3198 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3199
3200 intel_fdi_normal_train(crtc);
3201
3202 /* For PCH DP, enable TRANS_DP_CTL */
3203 if (HAS_PCH_CPT(dev) &&
3204 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3205 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3206 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3207 reg = TRANS_DP_CTL(pipe);
3208 temp = I915_READ(reg);
3209 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3210 TRANS_DP_SYNC_MASK |
3211 TRANS_DP_BPC_MASK);
3212 temp |= (TRANS_DP_OUTPUT_ENABLE |
3213 TRANS_DP_ENH_FRAMING);
3214 temp |= bpc << 9; /* same format but at 11:9 */
3215
3216 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3217 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3218 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3219 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3220
3221 switch (intel_trans_dp_port_sel(crtc)) {
3222 case PCH_DP_B:
3223 temp |= TRANS_DP_PORT_SEL_B;
3224 break;
3225 case PCH_DP_C:
3226 temp |= TRANS_DP_PORT_SEL_C;
3227 break;
3228 case PCH_DP_D:
3229 temp |= TRANS_DP_PORT_SEL_D;
3230 break;
3231 default:
3232 BUG();
3233 }
3234
3235 I915_WRITE(reg, temp);
3236 }
3237
3238 ironlake_enable_pch_transcoder(dev_priv, pipe);
3239 }
3240
3241 static void lpt_pch_enable(struct drm_crtc *crtc)
3242 {
3243 struct drm_device *dev = crtc->dev;
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3246 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3247
3248 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3249
3250 lpt_program_iclkip(crtc);
3251
3252 /* Set transcoder timing. */
3253 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3254
3255 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3256 }
3257
3258 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3259 {
3260 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3261
3262 if (pll == NULL)
3263 return;
3264
3265 if (pll->refcount == 0) {
3266 WARN(1, "bad %s refcount\n", pll->name);
3267 return;
3268 }
3269
3270 if (--pll->refcount == 0) {
3271 WARN_ON(pll->on);
3272 WARN_ON(pll->active);
3273 }
3274
3275 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3276 }
3277
3278 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3279 {
3280 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3281 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3282 enum intel_dpll_id i;
3283
3284 if (pll) {
3285 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3286 crtc->base.base.id, pll->name);
3287 intel_put_shared_dpll(crtc);
3288 }
3289
3290 if (HAS_PCH_IBX(dev_priv->dev)) {
3291 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3292 i = (enum intel_dpll_id) crtc->pipe;
3293 pll = &dev_priv->shared_dplls[i];
3294
3295 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3296 crtc->base.base.id, pll->name);
3297
3298 goto found;
3299 }
3300
3301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3302 pll = &dev_priv->shared_dplls[i];
3303
3304 /* Only want to check enabled timings first */
3305 if (pll->refcount == 0)
3306 continue;
3307
3308 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3309 sizeof(pll->hw_state)) == 0) {
3310 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3311 crtc->base.base.id,
3312 pll->name, pll->refcount, pll->active);
3313
3314 goto found;
3315 }
3316 }
3317
3318 /* Ok no matching timings, maybe there's a free one? */
3319 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3320 pll = &dev_priv->shared_dplls[i];
3321 if (pll->refcount == 0) {
3322 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3323 crtc->base.base.id, pll->name);
3324 goto found;
3325 }
3326 }
3327
3328 return NULL;
3329
3330 found:
3331 crtc->config.shared_dpll = i;
3332 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3333 pipe_name(crtc->pipe));
3334
3335 if (pll->active == 0) {
3336 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3337 sizeof(pll->hw_state));
3338
3339 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3340 WARN_ON(pll->on);
3341 assert_shared_dpll_disabled(dev_priv, pll);
3342
3343 pll->mode_set(dev_priv, pll);
3344 }
3345 pll->refcount++;
3346
3347 return pll;
3348 }
3349
3350 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3351 {
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 int dslreg = PIPEDSL(pipe);
3354 u32 temp;
3355
3356 temp = I915_READ(dslreg);
3357 udelay(500);
3358 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3359 if (wait_for(I915_READ(dslreg) != temp, 5))
3360 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3361 }
3362 }
3363
3364 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3365 {
3366 struct drm_device *dev = crtc->base.dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 int pipe = crtc->pipe;
3369
3370 if (crtc->config.pch_pfit.enabled) {
3371 /* Force use of hard-coded filter coefficients
3372 * as some pre-programmed values are broken,
3373 * e.g. x201.
3374 */
3375 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3376 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3377 PF_PIPE_SEL_IVB(pipe));
3378 else
3379 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3380 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3381 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3382 }
3383 }
3384
3385 static void intel_enable_planes(struct drm_crtc *crtc)
3386 {
3387 struct drm_device *dev = crtc->dev;
3388 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3389 struct intel_plane *intel_plane;
3390
3391 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3392 if (intel_plane->pipe == pipe)
3393 intel_plane_restore(&intel_plane->base);
3394 }
3395
3396 static void intel_disable_planes(struct drm_crtc *crtc)
3397 {
3398 struct drm_device *dev = crtc->dev;
3399 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3400 struct intel_plane *intel_plane;
3401
3402 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3403 if (intel_plane->pipe == pipe)
3404 intel_plane_disable(&intel_plane->base);
3405 }
3406
3407 void hsw_enable_ips(struct intel_crtc *crtc)
3408 {
3409 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3410
3411 if (!crtc->config.ips_enabled)
3412 return;
3413
3414 /* We can only enable IPS after we enable a plane and wait for a vblank.
3415 * We guarantee that the plane is enabled by calling intel_enable_ips
3416 * only after intel_enable_plane. And intel_enable_plane already waits
3417 * for a vblank, so all we need to do here is to enable the IPS bit. */
3418 assert_plane_enabled(dev_priv, crtc->plane);
3419 if (IS_BROADWELL(crtc->base.dev)) {
3420 mutex_lock(&dev_priv->rps.hw_lock);
3421 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3422 mutex_unlock(&dev_priv->rps.hw_lock);
3423 /* Quoting Art Runyan: "its not safe to expect any particular
3424 * value in IPS_CTL bit 31 after enabling IPS through the
3425 * mailbox." Therefore we need to defer waiting on the state
3426 * change.
3427 * TODO: need to fix this for state checker
3428 */
3429 } else {
3430 I915_WRITE(IPS_CTL, IPS_ENABLE);
3431 /* The bit only becomes 1 in the next vblank, so this wait here
3432 * is essentially intel_wait_for_vblank. If we don't have this
3433 * and don't wait for vblanks until the end of crtc_enable, then
3434 * the HW state readout code will complain that the expected
3435 * IPS_CTL value is not the one we read. */
3436 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3437 DRM_ERROR("Timed out waiting for IPS enable\n");
3438 }
3439 }
3440
3441 void hsw_disable_ips(struct intel_crtc *crtc)
3442 {
3443 struct drm_device *dev = crtc->base.dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445
3446 if (!crtc->config.ips_enabled)
3447 return;
3448
3449 assert_plane_enabled(dev_priv, crtc->plane);
3450 if (IS_BROADWELL(crtc->base.dev)) {
3451 mutex_lock(&dev_priv->rps.hw_lock);
3452 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3453 mutex_unlock(&dev_priv->rps.hw_lock);
3454 } else
3455 I915_WRITE(IPS_CTL, 0);
3456 POSTING_READ(IPS_CTL);
3457
3458 /* We need to wait for a vblank before we can disable the plane. */
3459 intel_wait_for_vblank(dev, crtc->pipe);
3460 }
3461
3462 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3463 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3464 {
3465 struct drm_device *dev = crtc->dev;
3466 struct drm_i915_private *dev_priv = dev->dev_private;
3467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3468 enum pipe pipe = intel_crtc->pipe;
3469 int palreg = PALETTE(pipe);
3470 int i;
3471 bool reenable_ips = false;
3472
3473 /* The clocks have to be on to load the palette. */
3474 if (!crtc->enabled || !intel_crtc->active)
3475 return;
3476
3477 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3479 assert_dsi_pll_enabled(dev_priv);
3480 else
3481 assert_pll_enabled(dev_priv, pipe);
3482 }
3483
3484 /* use legacy palette for Ironlake */
3485 if (HAS_PCH_SPLIT(dev))
3486 palreg = LGC_PALETTE(pipe);
3487
3488 /* Workaround : Do not read or write the pipe palette/gamma data while
3489 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3490 */
3491 if (intel_crtc->config.ips_enabled &&
3492 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3493 GAMMA_MODE_MODE_SPLIT)) {
3494 hsw_disable_ips(intel_crtc);
3495 reenable_ips = true;
3496 }
3497
3498 for (i = 0; i < 256; i++) {
3499 I915_WRITE(palreg + 4 * i,
3500 (intel_crtc->lut_r[i] << 16) |
3501 (intel_crtc->lut_g[i] << 8) |
3502 intel_crtc->lut_b[i]);
3503 }
3504
3505 if (reenable_ips)
3506 hsw_enable_ips(intel_crtc);
3507 }
3508
3509 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3510 {
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3517
3518 WARN_ON(!crtc->enabled);
3519
3520 if (intel_crtc->active)
3521 return;
3522
3523 intel_crtc->active = true;
3524
3525 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3526 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3527
3528 for_each_encoder_on_crtc(dev, crtc, encoder)
3529 if (encoder->pre_enable)
3530 encoder->pre_enable(encoder);
3531
3532 if (intel_crtc->config.has_pch_encoder) {
3533 /* Note: FDI PLL enabling _must_ be done before we enable the
3534 * cpu pipes, hence this is separate from all the other fdi/pch
3535 * enabling. */
3536 ironlake_fdi_pll_enable(intel_crtc);
3537 } else {
3538 assert_fdi_tx_disabled(dev_priv, pipe);
3539 assert_fdi_rx_disabled(dev_priv, pipe);
3540 }
3541
3542 ironlake_pfit_enable(intel_crtc);
3543
3544 /*
3545 * On ILK+ LUT must be loaded before the pipe is running but with
3546 * clocks enabled
3547 */
3548 intel_crtc_load_lut(crtc);
3549
3550 intel_update_watermarks(crtc);
3551 intel_enable_pipe(dev_priv, pipe,
3552 intel_crtc->config.has_pch_encoder, false);
3553 intel_enable_primary_plane(dev_priv, plane, pipe);
3554 intel_enable_planes(crtc);
3555 intel_crtc_update_cursor(crtc, true);
3556
3557 if (intel_crtc->config.has_pch_encoder)
3558 ironlake_pch_enable(crtc);
3559
3560 mutex_lock(&dev->struct_mutex);
3561 intel_update_fbc(dev);
3562 mutex_unlock(&dev->struct_mutex);
3563
3564 for_each_encoder_on_crtc(dev, crtc, encoder)
3565 encoder->enable(encoder);
3566
3567 if (HAS_PCH_CPT(dev))
3568 cpt_verify_modeset(dev, intel_crtc->pipe);
3569
3570 /*
3571 * There seems to be a race in PCH platform hw (at least on some
3572 * outputs) where an enabled pipe still completes any pageflip right
3573 * away (as if the pipe is off) instead of waiting for vblank. As soon
3574 * as the first vblank happend, everything works as expected. Hence just
3575 * wait for one vblank before returning to avoid strange things
3576 * happening.
3577 */
3578 intel_wait_for_vblank(dev, intel_crtc->pipe);
3579 }
3580
3581 /* IPS only exists on ULT machines and is tied to pipe A. */
3582 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3583 {
3584 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3585 }
3586
3587 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3588 {
3589 struct drm_device *dev = crtc->dev;
3590 struct drm_i915_private *dev_priv = dev->dev_private;
3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592 int pipe = intel_crtc->pipe;
3593 int plane = intel_crtc->plane;
3594
3595 intel_enable_primary_plane(dev_priv, plane, pipe);
3596 intel_enable_planes(crtc);
3597 intel_crtc_update_cursor(crtc, true);
3598
3599 hsw_enable_ips(intel_crtc);
3600
3601 mutex_lock(&dev->struct_mutex);
3602 intel_update_fbc(dev);
3603 mutex_unlock(&dev->struct_mutex);
3604 }
3605
3606 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3607 {
3608 struct drm_device *dev = crtc->dev;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611 int pipe = intel_crtc->pipe;
3612 int plane = intel_crtc->plane;
3613
3614 intel_crtc_wait_for_pending_flips(crtc);
3615 drm_vblank_off(dev, pipe);
3616
3617 /* FBC must be disabled before disabling the plane on HSW. */
3618 if (dev_priv->fbc.plane == plane)
3619 intel_disable_fbc(dev);
3620
3621 hsw_disable_ips(intel_crtc);
3622
3623 intel_crtc_update_cursor(crtc, false);
3624 intel_disable_planes(crtc);
3625 intel_disable_primary_plane(dev_priv, plane, pipe);
3626 }
3627
3628 /*
3629 * This implements the workaround described in the "notes" section of the mode
3630 * set sequence documentation. When going from no pipes or single pipe to
3631 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3632 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3633 */
3634 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3635 {
3636 struct drm_device *dev = crtc->base.dev;
3637 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3638
3639 /* We want to get the other_active_crtc only if there's only 1 other
3640 * active crtc. */
3641 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3642 if (!crtc_it->active || crtc_it == crtc)
3643 continue;
3644
3645 if (other_active_crtc)
3646 return;
3647
3648 other_active_crtc = crtc_it;
3649 }
3650 if (!other_active_crtc)
3651 return;
3652
3653 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3654 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3655 }
3656
3657 static void haswell_crtc_enable(struct drm_crtc *crtc)
3658 {
3659 struct drm_device *dev = crtc->dev;
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662 struct intel_encoder *encoder;
3663 int pipe = intel_crtc->pipe;
3664
3665 WARN_ON(!crtc->enabled);
3666
3667 if (intel_crtc->active)
3668 return;
3669
3670 intel_crtc->active = true;
3671
3672 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3673 if (intel_crtc->config.has_pch_encoder)
3674 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3675
3676 if (intel_crtc->config.has_pch_encoder)
3677 dev_priv->display.fdi_link_train(crtc);
3678
3679 for_each_encoder_on_crtc(dev, crtc, encoder)
3680 if (encoder->pre_enable)
3681 encoder->pre_enable(encoder);
3682
3683 intel_ddi_enable_pipe_clock(intel_crtc);
3684
3685 ironlake_pfit_enable(intel_crtc);
3686
3687 /*
3688 * On ILK+ LUT must be loaded before the pipe is running but with
3689 * clocks enabled
3690 */
3691 intel_crtc_load_lut(crtc);
3692
3693 intel_ddi_set_pipe_settings(crtc);
3694 intel_ddi_enable_transcoder_func(crtc);
3695
3696 intel_update_watermarks(crtc);
3697 intel_enable_pipe(dev_priv, pipe,
3698 intel_crtc->config.has_pch_encoder, false);
3699
3700 if (intel_crtc->config.has_pch_encoder)
3701 lpt_pch_enable(crtc);
3702
3703 for_each_encoder_on_crtc(dev, crtc, encoder) {
3704 encoder->enable(encoder);
3705 intel_opregion_notify_encoder(encoder, true);
3706 }
3707
3708 /* If we change the relative order between pipe/planes enabling, we need
3709 * to change the workaround. */
3710 haswell_mode_set_planes_workaround(intel_crtc);
3711 haswell_crtc_enable_planes(crtc);
3712
3713 /*
3714 * There seems to be a race in PCH platform hw (at least on some
3715 * outputs) where an enabled pipe still completes any pageflip right
3716 * away (as if the pipe is off) instead of waiting for vblank. As soon
3717 * as the first vblank happend, everything works as expected. Hence just
3718 * wait for one vblank before returning to avoid strange things
3719 * happening.
3720 */
3721 intel_wait_for_vblank(dev, intel_crtc->pipe);
3722 }
3723
3724 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3725 {
3726 struct drm_device *dev = crtc->base.dev;
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728 int pipe = crtc->pipe;
3729
3730 /* To avoid upsetting the power well on haswell only disable the pfit if
3731 * it's in use. The hw state code will make sure we get this right. */
3732 if (crtc->config.pch_pfit.enabled) {
3733 I915_WRITE(PF_CTL(pipe), 0);
3734 I915_WRITE(PF_WIN_POS(pipe), 0);
3735 I915_WRITE(PF_WIN_SZ(pipe), 0);
3736 }
3737 }
3738
3739 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3740 {
3741 struct drm_device *dev = crtc->dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744 struct intel_encoder *encoder;
3745 int pipe = intel_crtc->pipe;
3746 int plane = intel_crtc->plane;
3747 u32 reg, temp;
3748
3749
3750 if (!intel_crtc->active)
3751 return;
3752
3753 for_each_encoder_on_crtc(dev, crtc, encoder)
3754 encoder->disable(encoder);
3755
3756 intel_crtc_wait_for_pending_flips(crtc);
3757 drm_vblank_off(dev, pipe);
3758
3759 if (dev_priv->fbc.plane == plane)
3760 intel_disable_fbc(dev);
3761
3762 intel_crtc_update_cursor(crtc, false);
3763 intel_disable_planes(crtc);
3764 intel_disable_primary_plane(dev_priv, plane, pipe);
3765
3766 if (intel_crtc->config.has_pch_encoder)
3767 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3768
3769 intel_disable_pipe(dev_priv, pipe);
3770
3771 ironlake_pfit_disable(intel_crtc);
3772
3773 for_each_encoder_on_crtc(dev, crtc, encoder)
3774 if (encoder->post_disable)
3775 encoder->post_disable(encoder);
3776
3777 if (intel_crtc->config.has_pch_encoder) {
3778 ironlake_fdi_disable(crtc);
3779
3780 ironlake_disable_pch_transcoder(dev_priv, pipe);
3781 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3782
3783 if (HAS_PCH_CPT(dev)) {
3784 /* disable TRANS_DP_CTL */
3785 reg = TRANS_DP_CTL(pipe);
3786 temp = I915_READ(reg);
3787 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3788 TRANS_DP_PORT_SEL_MASK);
3789 temp |= TRANS_DP_PORT_SEL_NONE;
3790 I915_WRITE(reg, temp);
3791
3792 /* disable DPLL_SEL */
3793 temp = I915_READ(PCH_DPLL_SEL);
3794 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3795 I915_WRITE(PCH_DPLL_SEL, temp);
3796 }
3797
3798 /* disable PCH DPLL */
3799 intel_disable_shared_dpll(intel_crtc);
3800
3801 ironlake_fdi_pll_disable(intel_crtc);
3802 }
3803
3804 intel_crtc->active = false;
3805 intel_update_watermarks(crtc);
3806
3807 mutex_lock(&dev->struct_mutex);
3808 intel_update_fbc(dev);
3809 mutex_unlock(&dev->struct_mutex);
3810 }
3811
3812 static void haswell_crtc_disable(struct drm_crtc *crtc)
3813 {
3814 struct drm_device *dev = crtc->dev;
3815 struct drm_i915_private *dev_priv = dev->dev_private;
3816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3817 struct intel_encoder *encoder;
3818 int pipe = intel_crtc->pipe;
3819 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3820
3821 if (!intel_crtc->active)
3822 return;
3823
3824 haswell_crtc_disable_planes(crtc);
3825
3826 for_each_encoder_on_crtc(dev, crtc, encoder) {
3827 intel_opregion_notify_encoder(encoder, false);
3828 encoder->disable(encoder);
3829 }
3830
3831 if (intel_crtc->config.has_pch_encoder)
3832 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3833 intel_disable_pipe(dev_priv, pipe);
3834
3835 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3836
3837 ironlake_pfit_disable(intel_crtc);
3838
3839 intel_ddi_disable_pipe_clock(intel_crtc);
3840
3841 for_each_encoder_on_crtc(dev, crtc, encoder)
3842 if (encoder->post_disable)
3843 encoder->post_disable(encoder);
3844
3845 if (intel_crtc->config.has_pch_encoder) {
3846 lpt_disable_pch_transcoder(dev_priv);
3847 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3848 intel_ddi_fdi_disable(crtc);
3849 }
3850
3851 intel_crtc->active = false;
3852 intel_update_watermarks(crtc);
3853
3854 mutex_lock(&dev->struct_mutex);
3855 intel_update_fbc(dev);
3856 mutex_unlock(&dev->struct_mutex);
3857 }
3858
3859 static void ironlake_crtc_off(struct drm_crtc *crtc)
3860 {
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 intel_put_shared_dpll(intel_crtc);
3863 }
3864
3865 static void haswell_crtc_off(struct drm_crtc *crtc)
3866 {
3867 intel_ddi_put_crtc_pll(crtc);
3868 }
3869
3870 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3871 {
3872 if (!enable && intel_crtc->overlay) {
3873 struct drm_device *dev = intel_crtc->base.dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875
3876 mutex_lock(&dev->struct_mutex);
3877 dev_priv->mm.interruptible = false;
3878 (void) intel_overlay_switch_off(intel_crtc->overlay);
3879 dev_priv->mm.interruptible = true;
3880 mutex_unlock(&dev->struct_mutex);
3881 }
3882
3883 /* Let userspace switch the overlay on again. In most cases userspace
3884 * has to recompute where to put it anyway.
3885 */
3886 }
3887
3888 /**
3889 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3890 * cursor plane briefly if not already running after enabling the display
3891 * plane.
3892 * This workaround avoids occasional blank screens when self refresh is
3893 * enabled.
3894 */
3895 static void
3896 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3897 {
3898 u32 cntl = I915_READ(CURCNTR(pipe));
3899
3900 if ((cntl & CURSOR_MODE) == 0) {
3901 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3902
3903 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3904 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3905 intel_wait_for_vblank(dev_priv->dev, pipe);
3906 I915_WRITE(CURCNTR(pipe), cntl);
3907 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3908 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3909 }
3910 }
3911
3912 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3913 {
3914 struct drm_device *dev = crtc->base.dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916 struct intel_crtc_config *pipe_config = &crtc->config;
3917
3918 if (!crtc->config.gmch_pfit.control)
3919 return;
3920
3921 /*
3922 * The panel fitter should only be adjusted whilst the pipe is disabled,
3923 * according to register description and PRM.
3924 */
3925 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3926 assert_pipe_disabled(dev_priv, crtc->pipe);
3927
3928 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3929 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3930
3931 /* Border color in case we don't scale up to the full screen. Black by
3932 * default, change to something else for debugging. */
3933 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3934 }
3935
3936 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3937 {
3938 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3939
3940 /* Obtain SKU information */
3941 mutex_lock(&dev_priv->dpio_lock);
3942 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3943 CCK_FUSE_HPLL_FREQ_MASK;
3944 mutex_unlock(&dev_priv->dpio_lock);
3945
3946 return vco_freq[hpll_freq];
3947 }
3948
3949 /* Adjust CDclk dividers to allow high res or save power if possible */
3950 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3951 {
3952 struct drm_i915_private *dev_priv = dev->dev_private;
3953 u32 val, cmd;
3954
3955 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3956 cmd = 2;
3957 else if (cdclk == 266)
3958 cmd = 1;
3959 else
3960 cmd = 0;
3961
3962 mutex_lock(&dev_priv->rps.hw_lock);
3963 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3964 val &= ~DSPFREQGUAR_MASK;
3965 val |= (cmd << DSPFREQGUAR_SHIFT);
3966 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3967 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3968 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3969 50)) {
3970 DRM_ERROR("timed out waiting for CDclk change\n");
3971 }
3972 mutex_unlock(&dev_priv->rps.hw_lock);
3973
3974 if (cdclk == 400) {
3975 u32 divider, vco;
3976
3977 vco = valleyview_get_vco(dev_priv);
3978 divider = ((vco << 1) / cdclk) - 1;
3979
3980 mutex_lock(&dev_priv->dpio_lock);
3981 /* adjust cdclk divider */
3982 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3983 val &= ~0xf;
3984 val |= divider;
3985 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3986 mutex_unlock(&dev_priv->dpio_lock);
3987 }
3988
3989 mutex_lock(&dev_priv->dpio_lock);
3990 /* adjust self-refresh exit latency value */
3991 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
3992 val &= ~0x7f;
3993
3994 /*
3995 * For high bandwidth configs, we set a higher latency in the bunit
3996 * so that the core display fetch happens in time to avoid underruns.
3997 */
3998 if (cdclk == 400)
3999 val |= 4500 / 250; /* 4.5 usec */
4000 else
4001 val |= 3000 / 250; /* 3.0 usec */
4002 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4003 mutex_unlock(&dev_priv->dpio_lock);
4004
4005 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4006 intel_i2c_reset(dev);
4007 }
4008
4009 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4010 {
4011 int cur_cdclk, vco;
4012 int divider;
4013
4014 vco = valleyview_get_vco(dev_priv);
4015
4016 mutex_lock(&dev_priv->dpio_lock);
4017 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4018 mutex_unlock(&dev_priv->dpio_lock);
4019
4020 divider &= 0xf;
4021
4022 cur_cdclk = (vco << 1) / (divider + 1);
4023
4024 return cur_cdclk;
4025 }
4026
4027 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4028 int max_pixclk)
4029 {
4030 int cur_cdclk;
4031
4032 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4033
4034 /*
4035 * Really only a few cases to deal with, as only 4 CDclks are supported:
4036 * 200MHz
4037 * 267MHz
4038 * 320MHz
4039 * 400MHz
4040 * So we check to see whether we're above 90% of the lower bin and
4041 * adjust if needed.
4042 */
4043 if (max_pixclk > 288000) {
4044 return 400;
4045 } else if (max_pixclk > 240000) {
4046 return 320;
4047 } else
4048 return 266;
4049 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4050 }
4051
4052 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4053 unsigned modeset_pipes,
4054 struct intel_crtc_config *pipe_config)
4055 {
4056 struct drm_device *dev = dev_priv->dev;
4057 struct intel_crtc *intel_crtc;
4058 int max_pixclk = 0;
4059
4060 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4061 base.head) {
4062 if (modeset_pipes & (1 << intel_crtc->pipe))
4063 max_pixclk = max(max_pixclk,
4064 pipe_config->adjusted_mode.crtc_clock);
4065 else if (intel_crtc->base.enabled)
4066 max_pixclk = max(max_pixclk,
4067 intel_crtc->config.adjusted_mode.crtc_clock);
4068 }
4069
4070 return max_pixclk;
4071 }
4072
4073 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4074 unsigned *prepare_pipes,
4075 unsigned modeset_pipes,
4076 struct intel_crtc_config *pipe_config)
4077 {
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 struct intel_crtc *intel_crtc;
4080 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4081 pipe_config);
4082 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4083
4084 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4085 return;
4086
4087 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4088 base.head)
4089 if (intel_crtc->base.enabled)
4090 *prepare_pipes |= (1 << intel_crtc->pipe);
4091 }
4092
4093 static void valleyview_modeset_global_resources(struct drm_device *dev)
4094 {
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4097 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4098 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4099
4100 if (req_cdclk != cur_cdclk)
4101 valleyview_set_cdclk(dev, req_cdclk);
4102 }
4103
4104 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109 struct intel_encoder *encoder;
4110 int pipe = intel_crtc->pipe;
4111 int plane = intel_crtc->plane;
4112 bool is_dsi;
4113
4114 WARN_ON(!crtc->enabled);
4115
4116 if (intel_crtc->active)
4117 return;
4118
4119 intel_crtc->active = true;
4120
4121 for_each_encoder_on_crtc(dev, crtc, encoder)
4122 if (encoder->pre_pll_enable)
4123 encoder->pre_pll_enable(encoder);
4124
4125 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4126
4127 if (!is_dsi)
4128 vlv_enable_pll(intel_crtc);
4129
4130 for_each_encoder_on_crtc(dev, crtc, encoder)
4131 if (encoder->pre_enable)
4132 encoder->pre_enable(encoder);
4133
4134 i9xx_pfit_enable(intel_crtc);
4135
4136 intel_crtc_load_lut(crtc);
4137
4138 intel_update_watermarks(crtc);
4139 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4140 intel_enable_primary_plane(dev_priv, plane, pipe);
4141 intel_enable_planes(crtc);
4142 intel_crtc_update_cursor(crtc, true);
4143
4144 intel_update_fbc(dev);
4145
4146 for_each_encoder_on_crtc(dev, crtc, encoder)
4147 encoder->enable(encoder);
4148 }
4149
4150 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4151 {
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4155 struct intel_encoder *encoder;
4156 int pipe = intel_crtc->pipe;
4157 int plane = intel_crtc->plane;
4158
4159 WARN_ON(!crtc->enabled);
4160
4161 if (intel_crtc->active)
4162 return;
4163
4164 intel_crtc->active = true;
4165
4166 for_each_encoder_on_crtc(dev, crtc, encoder)
4167 if (encoder->pre_enable)
4168 encoder->pre_enable(encoder);
4169
4170 i9xx_enable_pll(intel_crtc);
4171
4172 i9xx_pfit_enable(intel_crtc);
4173
4174 intel_crtc_load_lut(crtc);
4175
4176 intel_update_watermarks(crtc);
4177 intel_enable_pipe(dev_priv, pipe, false, false);
4178 intel_enable_primary_plane(dev_priv, plane, pipe);
4179 intel_enable_planes(crtc);
4180 /* The fixup needs to happen before cursor is enabled */
4181 if (IS_G4X(dev))
4182 g4x_fixup_plane(dev_priv, pipe);
4183 intel_crtc_update_cursor(crtc, true);
4184
4185 /* Give the overlay scaler a chance to enable if it's on this pipe */
4186 intel_crtc_dpms_overlay(intel_crtc, true);
4187
4188 intel_update_fbc(dev);
4189
4190 for_each_encoder_on_crtc(dev, crtc, encoder)
4191 encoder->enable(encoder);
4192 }
4193
4194 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4195 {
4196 struct drm_device *dev = crtc->base.dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198
4199 if (!crtc->config.gmch_pfit.control)
4200 return;
4201
4202 assert_pipe_disabled(dev_priv, crtc->pipe);
4203
4204 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4205 I915_READ(PFIT_CONTROL));
4206 I915_WRITE(PFIT_CONTROL, 0);
4207 }
4208
4209 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4210 {
4211 struct drm_device *dev = crtc->dev;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
4213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4214 struct intel_encoder *encoder;
4215 int pipe = intel_crtc->pipe;
4216 int plane = intel_crtc->plane;
4217
4218 if (!intel_crtc->active)
4219 return;
4220
4221 for_each_encoder_on_crtc(dev, crtc, encoder)
4222 encoder->disable(encoder);
4223
4224 /* Give the overlay scaler a chance to disable if it's on this pipe */
4225 intel_crtc_wait_for_pending_flips(crtc);
4226 drm_vblank_off(dev, pipe);
4227
4228 if (dev_priv->fbc.plane == plane)
4229 intel_disable_fbc(dev);
4230
4231 intel_crtc_dpms_overlay(intel_crtc, false);
4232 intel_crtc_update_cursor(crtc, false);
4233 intel_disable_planes(crtc);
4234 intel_disable_primary_plane(dev_priv, plane, pipe);
4235
4236 intel_disable_pipe(dev_priv, pipe);
4237
4238 i9xx_pfit_disable(intel_crtc);
4239
4240 for_each_encoder_on_crtc(dev, crtc, encoder)
4241 if (encoder->post_disable)
4242 encoder->post_disable(encoder);
4243
4244 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4245 vlv_disable_pll(dev_priv, pipe);
4246 else if (!IS_VALLEYVIEW(dev))
4247 i9xx_disable_pll(dev_priv, pipe);
4248
4249 intel_crtc->active = false;
4250 intel_update_watermarks(crtc);
4251
4252 intel_update_fbc(dev);
4253 }
4254
4255 static void i9xx_crtc_off(struct drm_crtc *crtc)
4256 {
4257 }
4258
4259 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4260 bool enabled)
4261 {
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_master_private *master_priv;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 int pipe = intel_crtc->pipe;
4266
4267 if (!dev->primary->master)
4268 return;
4269
4270 master_priv = dev->primary->master->driver_priv;
4271 if (!master_priv->sarea_priv)
4272 return;
4273
4274 switch (pipe) {
4275 case 0:
4276 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4277 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4278 break;
4279 case 1:
4280 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4281 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4282 break;
4283 default:
4284 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4285 break;
4286 }
4287 }
4288
4289 /**
4290 * Sets the power management mode of the pipe and plane.
4291 */
4292 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4293 {
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_encoder *intel_encoder;
4297 bool enable = false;
4298
4299 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4300 enable |= intel_encoder->connectors_active;
4301
4302 if (enable)
4303 dev_priv->display.crtc_enable(crtc);
4304 else
4305 dev_priv->display.crtc_disable(crtc);
4306
4307 intel_crtc_update_sarea(crtc, enable);
4308 }
4309
4310 static void intel_crtc_disable(struct drm_crtc *crtc)
4311 {
4312 struct drm_device *dev = crtc->dev;
4313 struct drm_connector *connector;
4314 struct drm_i915_private *dev_priv = dev->dev_private;
4315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4316
4317 /* crtc should still be enabled when we disable it. */
4318 WARN_ON(!crtc->enabled);
4319
4320 dev_priv->display.crtc_disable(crtc);
4321 intel_crtc->eld_vld = false;
4322 intel_crtc_update_sarea(crtc, false);
4323 dev_priv->display.off(crtc);
4324
4325 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4326 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4327 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4328
4329 if (crtc->fb) {
4330 mutex_lock(&dev->struct_mutex);
4331 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4332 mutex_unlock(&dev->struct_mutex);
4333 crtc->fb = NULL;
4334 }
4335
4336 /* Update computed state. */
4337 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4338 if (!connector->encoder || !connector->encoder->crtc)
4339 continue;
4340
4341 if (connector->encoder->crtc != crtc)
4342 continue;
4343
4344 connector->dpms = DRM_MODE_DPMS_OFF;
4345 to_intel_encoder(connector->encoder)->connectors_active = false;
4346 }
4347 }
4348
4349 void intel_encoder_destroy(struct drm_encoder *encoder)
4350 {
4351 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4352
4353 drm_encoder_cleanup(encoder);
4354 kfree(intel_encoder);
4355 }
4356
4357 /* Simple dpms helper for encoders with just one connector, no cloning and only
4358 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4359 * state of the entire output pipe. */
4360 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4361 {
4362 if (mode == DRM_MODE_DPMS_ON) {
4363 encoder->connectors_active = true;
4364
4365 intel_crtc_update_dpms(encoder->base.crtc);
4366 } else {
4367 encoder->connectors_active = false;
4368
4369 intel_crtc_update_dpms(encoder->base.crtc);
4370 }
4371 }
4372
4373 /* Cross check the actual hw state with our own modeset state tracking (and it's
4374 * internal consistency). */
4375 static void intel_connector_check_state(struct intel_connector *connector)
4376 {
4377 if (connector->get_hw_state(connector)) {
4378 struct intel_encoder *encoder = connector->encoder;
4379 struct drm_crtc *crtc;
4380 bool encoder_enabled;
4381 enum pipe pipe;
4382
4383 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4384 connector->base.base.id,
4385 drm_get_connector_name(&connector->base));
4386
4387 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4388 "wrong connector dpms state\n");
4389 WARN(connector->base.encoder != &encoder->base,
4390 "active connector not linked to encoder\n");
4391 WARN(!encoder->connectors_active,
4392 "encoder->connectors_active not set\n");
4393
4394 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4395 WARN(!encoder_enabled, "encoder not enabled\n");
4396 if (WARN_ON(!encoder->base.crtc))
4397 return;
4398
4399 crtc = encoder->base.crtc;
4400
4401 WARN(!crtc->enabled, "crtc not enabled\n");
4402 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4403 WARN(pipe != to_intel_crtc(crtc)->pipe,
4404 "encoder active on the wrong pipe\n");
4405 }
4406 }
4407
4408 /* Even simpler default implementation, if there's really no special case to
4409 * consider. */
4410 void intel_connector_dpms(struct drm_connector *connector, int mode)
4411 {
4412 /* All the simple cases only support two dpms states. */
4413 if (mode != DRM_MODE_DPMS_ON)
4414 mode = DRM_MODE_DPMS_OFF;
4415
4416 if (mode == connector->dpms)
4417 return;
4418
4419 connector->dpms = mode;
4420
4421 /* Only need to change hw state when actually enabled */
4422 if (connector->encoder)
4423 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4424
4425 intel_modeset_check_state(connector->dev);
4426 }
4427
4428 /* Simple connector->get_hw_state implementation for encoders that support only
4429 * one connector and no cloning and hence the encoder state determines the state
4430 * of the connector. */
4431 bool intel_connector_get_hw_state(struct intel_connector *connector)
4432 {
4433 enum pipe pipe = 0;
4434 struct intel_encoder *encoder = connector->encoder;
4435
4436 return encoder->get_hw_state(encoder, &pipe);
4437 }
4438
4439 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4440 struct intel_crtc_config *pipe_config)
4441 {
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 struct intel_crtc *pipe_B_crtc =
4444 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4445
4446 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4447 pipe_name(pipe), pipe_config->fdi_lanes);
4448 if (pipe_config->fdi_lanes > 4) {
4449 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4450 pipe_name(pipe), pipe_config->fdi_lanes);
4451 return false;
4452 }
4453
4454 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4455 if (pipe_config->fdi_lanes > 2) {
4456 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4457 pipe_config->fdi_lanes);
4458 return false;
4459 } else {
4460 return true;
4461 }
4462 }
4463
4464 if (INTEL_INFO(dev)->num_pipes == 2)
4465 return true;
4466
4467 /* Ivybridge 3 pipe is really complicated */
4468 switch (pipe) {
4469 case PIPE_A:
4470 return true;
4471 case PIPE_B:
4472 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4473 pipe_config->fdi_lanes > 2) {
4474 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4475 pipe_name(pipe), pipe_config->fdi_lanes);
4476 return false;
4477 }
4478 return true;
4479 case PIPE_C:
4480 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4481 pipe_B_crtc->config.fdi_lanes <= 2) {
4482 if (pipe_config->fdi_lanes > 2) {
4483 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4484 pipe_name(pipe), pipe_config->fdi_lanes);
4485 return false;
4486 }
4487 } else {
4488 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4489 return false;
4490 }
4491 return true;
4492 default:
4493 BUG();
4494 }
4495 }
4496
4497 #define RETRY 1
4498 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4499 struct intel_crtc_config *pipe_config)
4500 {
4501 struct drm_device *dev = intel_crtc->base.dev;
4502 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4503 int lane, link_bw, fdi_dotclock;
4504 bool setup_ok, needs_recompute = false;
4505
4506 retry:
4507 /* FDI is a binary signal running at ~2.7GHz, encoding
4508 * each output octet as 10 bits. The actual frequency
4509 * is stored as a divider into a 100MHz clock, and the
4510 * mode pixel clock is stored in units of 1KHz.
4511 * Hence the bw of each lane in terms of the mode signal
4512 * is:
4513 */
4514 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4515
4516 fdi_dotclock = adjusted_mode->crtc_clock;
4517
4518 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4519 pipe_config->pipe_bpp);
4520
4521 pipe_config->fdi_lanes = lane;
4522
4523 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4524 link_bw, &pipe_config->fdi_m_n);
4525
4526 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4527 intel_crtc->pipe, pipe_config);
4528 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4529 pipe_config->pipe_bpp -= 2*3;
4530 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4531 pipe_config->pipe_bpp);
4532 needs_recompute = true;
4533 pipe_config->bw_constrained = true;
4534
4535 goto retry;
4536 }
4537
4538 if (needs_recompute)
4539 return RETRY;
4540
4541 return setup_ok ? 0 : -EINVAL;
4542 }
4543
4544 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4545 struct intel_crtc_config *pipe_config)
4546 {
4547 pipe_config->ips_enabled = i915_enable_ips &&
4548 hsw_crtc_supports_ips(crtc) &&
4549 pipe_config->pipe_bpp <= 24;
4550 }
4551
4552 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4553 struct intel_crtc_config *pipe_config)
4554 {
4555 struct drm_device *dev = crtc->base.dev;
4556 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4557
4558 /* FIXME should check pixel clock limits on all platforms */
4559 if (INTEL_INFO(dev)->gen < 4) {
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 int clock_limit =
4562 dev_priv->display.get_display_clock_speed(dev);
4563
4564 /*
4565 * Enable pixel doubling when the dot clock
4566 * is > 90% of the (display) core speed.
4567 *
4568 * GDG double wide on either pipe,
4569 * otherwise pipe A only.
4570 */
4571 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4572 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4573 clock_limit *= 2;
4574 pipe_config->double_wide = true;
4575 }
4576
4577 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4578 return -EINVAL;
4579 }
4580
4581 /*
4582 * Pipe horizontal size must be even in:
4583 * - DVO ganged mode
4584 * - LVDS dual channel mode
4585 * - Double wide pipe
4586 */
4587 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4588 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4589 pipe_config->pipe_src_w &= ~1;
4590
4591 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4592 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4593 */
4594 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4595 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4596 return -EINVAL;
4597
4598 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4599 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4600 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4601 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4602 * for lvds. */
4603 pipe_config->pipe_bpp = 8*3;
4604 }
4605
4606 if (HAS_IPS(dev))
4607 hsw_compute_ips_config(crtc, pipe_config);
4608
4609 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4610 * clock survives for now. */
4611 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4612 pipe_config->shared_dpll = crtc->config.shared_dpll;
4613
4614 if (pipe_config->has_pch_encoder)
4615 return ironlake_fdi_compute_config(crtc, pipe_config);
4616
4617 return 0;
4618 }
4619
4620 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4621 {
4622 return 400000; /* FIXME */
4623 }
4624
4625 static int i945_get_display_clock_speed(struct drm_device *dev)
4626 {
4627 return 400000;
4628 }
4629
4630 static int i915_get_display_clock_speed(struct drm_device *dev)
4631 {
4632 return 333000;
4633 }
4634
4635 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4636 {
4637 return 200000;
4638 }
4639
4640 static int pnv_get_display_clock_speed(struct drm_device *dev)
4641 {
4642 u16 gcfgc = 0;
4643
4644 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4645
4646 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4647 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4648 return 267000;
4649 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4650 return 333000;
4651 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4652 return 444000;
4653 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4654 return 200000;
4655 default:
4656 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4657 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4658 return 133000;
4659 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4660 return 167000;
4661 }
4662 }
4663
4664 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4665 {
4666 u16 gcfgc = 0;
4667
4668 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4669
4670 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4671 return 133000;
4672 else {
4673 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4674 case GC_DISPLAY_CLOCK_333_MHZ:
4675 return 333000;
4676 default:
4677 case GC_DISPLAY_CLOCK_190_200_MHZ:
4678 return 190000;
4679 }
4680 }
4681 }
4682
4683 static int i865_get_display_clock_speed(struct drm_device *dev)
4684 {
4685 return 266000;
4686 }
4687
4688 static int i855_get_display_clock_speed(struct drm_device *dev)
4689 {
4690 u16 hpllcc = 0;
4691 /* Assume that the hardware is in the high speed state. This
4692 * should be the default.
4693 */
4694 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4695 case GC_CLOCK_133_200:
4696 case GC_CLOCK_100_200:
4697 return 200000;
4698 case GC_CLOCK_166_250:
4699 return 250000;
4700 case GC_CLOCK_100_133:
4701 return 133000;
4702 }
4703
4704 /* Shouldn't happen */
4705 return 0;
4706 }
4707
4708 static int i830_get_display_clock_speed(struct drm_device *dev)
4709 {
4710 return 133000;
4711 }
4712
4713 static void
4714 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4715 {
4716 while (*num > DATA_LINK_M_N_MASK ||
4717 *den > DATA_LINK_M_N_MASK) {
4718 *num >>= 1;
4719 *den >>= 1;
4720 }
4721 }
4722
4723 static void compute_m_n(unsigned int m, unsigned int n,
4724 uint32_t *ret_m, uint32_t *ret_n)
4725 {
4726 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4727 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4728 intel_reduce_m_n_ratio(ret_m, ret_n);
4729 }
4730
4731 void
4732 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4733 int pixel_clock, int link_clock,
4734 struct intel_link_m_n *m_n)
4735 {
4736 m_n->tu = 64;
4737
4738 compute_m_n(bits_per_pixel * pixel_clock,
4739 link_clock * nlanes * 8,
4740 &m_n->gmch_m, &m_n->gmch_n);
4741
4742 compute_m_n(pixel_clock, link_clock,
4743 &m_n->link_m, &m_n->link_n);
4744 }
4745
4746 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4747 {
4748 if (i915_panel_use_ssc >= 0)
4749 return i915_panel_use_ssc != 0;
4750 return dev_priv->vbt.lvds_use_ssc
4751 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4752 }
4753
4754 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4755 {
4756 struct drm_device *dev = crtc->dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 int refclk;
4759
4760 if (IS_VALLEYVIEW(dev)) {
4761 refclk = 100000;
4762 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4763 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4764 refclk = dev_priv->vbt.lvds_ssc_freq;
4765 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4766 } else if (!IS_GEN2(dev)) {
4767 refclk = 96000;
4768 } else {
4769 refclk = 48000;
4770 }
4771
4772 return refclk;
4773 }
4774
4775 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4776 {
4777 return (1 << dpll->n) << 16 | dpll->m2;
4778 }
4779
4780 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4781 {
4782 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4783 }
4784
4785 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4786 intel_clock_t *reduced_clock)
4787 {
4788 struct drm_device *dev = crtc->base.dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 int pipe = crtc->pipe;
4791 u32 fp, fp2 = 0;
4792
4793 if (IS_PINEVIEW(dev)) {
4794 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4795 if (reduced_clock)
4796 fp2 = pnv_dpll_compute_fp(reduced_clock);
4797 } else {
4798 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4799 if (reduced_clock)
4800 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4801 }
4802
4803 I915_WRITE(FP0(pipe), fp);
4804 crtc->config.dpll_hw_state.fp0 = fp;
4805
4806 crtc->lowfreq_avail = false;
4807 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4808 reduced_clock && i915_powersave) {
4809 I915_WRITE(FP1(pipe), fp2);
4810 crtc->config.dpll_hw_state.fp1 = fp2;
4811 crtc->lowfreq_avail = true;
4812 } else {
4813 I915_WRITE(FP1(pipe), fp);
4814 crtc->config.dpll_hw_state.fp1 = fp;
4815 }
4816 }
4817
4818 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4819 pipe)
4820 {
4821 u32 reg_val;
4822
4823 /*
4824 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4825 * and set it to a reasonable value instead.
4826 */
4827 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4828 reg_val &= 0xffffff00;
4829 reg_val |= 0x00000030;
4830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4831
4832 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4833 reg_val &= 0x8cffffff;
4834 reg_val = 0x8c000000;
4835 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4836
4837 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4838 reg_val &= 0xffffff00;
4839 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4840
4841 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4842 reg_val &= 0x00ffffff;
4843 reg_val |= 0xb0000000;
4844 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4845 }
4846
4847 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4848 struct intel_link_m_n *m_n)
4849 {
4850 struct drm_device *dev = crtc->base.dev;
4851 struct drm_i915_private *dev_priv = dev->dev_private;
4852 int pipe = crtc->pipe;
4853
4854 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4855 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4856 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4857 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4858 }
4859
4860 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4861 struct intel_link_m_n *m_n)
4862 {
4863 struct drm_device *dev = crtc->base.dev;
4864 struct drm_i915_private *dev_priv = dev->dev_private;
4865 int pipe = crtc->pipe;
4866 enum transcoder transcoder = crtc->config.cpu_transcoder;
4867
4868 if (INTEL_INFO(dev)->gen >= 5) {
4869 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4870 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4871 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4872 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4873 } else {
4874 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4875 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4876 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4877 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4878 }
4879 }
4880
4881 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4882 {
4883 if (crtc->config.has_pch_encoder)
4884 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4885 else
4886 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4887 }
4888
4889 static void vlv_update_pll(struct intel_crtc *crtc)
4890 {
4891 struct drm_device *dev = crtc->base.dev;
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 int pipe = crtc->pipe;
4894 u32 dpll, mdiv;
4895 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4896 u32 coreclk, reg_val, dpll_md;
4897
4898 mutex_lock(&dev_priv->dpio_lock);
4899
4900 bestn = crtc->config.dpll.n;
4901 bestm1 = crtc->config.dpll.m1;
4902 bestm2 = crtc->config.dpll.m2;
4903 bestp1 = crtc->config.dpll.p1;
4904 bestp2 = crtc->config.dpll.p2;
4905
4906 /* See eDP HDMI DPIO driver vbios notes doc */
4907
4908 /* PLL B needs special handling */
4909 if (pipe)
4910 vlv_pllb_recal_opamp(dev_priv, pipe);
4911
4912 /* Set up Tx target for periodic Rcomp update */
4913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4914
4915 /* Disable target IRef on PLL */
4916 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4917 reg_val &= 0x00ffffff;
4918 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4919
4920 /* Disable fast lock */
4921 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4922
4923 /* Set idtafcrecal before PLL is enabled */
4924 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4925 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4926 mdiv |= ((bestn << DPIO_N_SHIFT));
4927 mdiv |= (1 << DPIO_K_SHIFT);
4928
4929 /*
4930 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4931 * but we don't support that).
4932 * Note: don't use the DAC post divider as it seems unstable.
4933 */
4934 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4936
4937 mdiv |= DPIO_ENABLE_CALIBRATION;
4938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4939
4940 /* Set HBR and RBR LPF coefficients */
4941 if (crtc->config.port_clock == 162000 ||
4942 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4943 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4945 0x009f0003);
4946 else
4947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4948 0x00d0000f);
4949
4950 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4951 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4952 /* Use SSC source */
4953 if (!pipe)
4954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4955 0x0df40000);
4956 else
4957 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4958 0x0df70000);
4959 } else { /* HDMI or VGA */
4960 /* Use bend source */
4961 if (!pipe)
4962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4963 0x0df70000);
4964 else
4965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4966 0x0df40000);
4967 }
4968
4969 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4970 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4971 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4972 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4973 coreclk |= 0x01000000;
4974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4975
4976 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4977
4978 /* Enable DPIO clock input */
4979 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4980 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4981 /* We should never disable this, set it here for state tracking */
4982 if (pipe == PIPE_B)
4983 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4984 dpll |= DPLL_VCO_ENABLE;
4985 crtc->config.dpll_hw_state.dpll = dpll;
4986
4987 dpll_md = (crtc->config.pixel_multiplier - 1)
4988 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4989 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4990
4991 if (crtc->config.has_dp_encoder)
4992 intel_dp_set_m_n(crtc);
4993
4994 mutex_unlock(&dev_priv->dpio_lock);
4995 }
4996
4997 static void i9xx_update_pll(struct intel_crtc *crtc,
4998 intel_clock_t *reduced_clock,
4999 int num_connectors)
5000 {
5001 struct drm_device *dev = crtc->base.dev;
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 u32 dpll;
5004 bool is_sdvo;
5005 struct dpll *clock = &crtc->config.dpll;
5006
5007 i9xx_update_pll_dividers(crtc, reduced_clock);
5008
5009 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5010 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5011
5012 dpll = DPLL_VGA_MODE_DIS;
5013
5014 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5015 dpll |= DPLLB_MODE_LVDS;
5016 else
5017 dpll |= DPLLB_MODE_DAC_SERIAL;
5018
5019 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5020 dpll |= (crtc->config.pixel_multiplier - 1)
5021 << SDVO_MULTIPLIER_SHIFT_HIRES;
5022 }
5023
5024 if (is_sdvo)
5025 dpll |= DPLL_SDVO_HIGH_SPEED;
5026
5027 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5028 dpll |= DPLL_SDVO_HIGH_SPEED;
5029
5030 /* compute bitmask from p1 value */
5031 if (IS_PINEVIEW(dev))
5032 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5033 else {
5034 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5035 if (IS_G4X(dev) && reduced_clock)
5036 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5037 }
5038 switch (clock->p2) {
5039 case 5:
5040 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5041 break;
5042 case 7:
5043 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5044 break;
5045 case 10:
5046 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5047 break;
5048 case 14:
5049 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5050 break;
5051 }
5052 if (INTEL_INFO(dev)->gen >= 4)
5053 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5054
5055 if (crtc->config.sdvo_tv_clock)
5056 dpll |= PLL_REF_INPUT_TVCLKINBC;
5057 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5058 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5059 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5060 else
5061 dpll |= PLL_REF_INPUT_DREFCLK;
5062
5063 dpll |= DPLL_VCO_ENABLE;
5064 crtc->config.dpll_hw_state.dpll = dpll;
5065
5066 if (INTEL_INFO(dev)->gen >= 4) {
5067 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5068 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5069 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5070 }
5071
5072 if (crtc->config.has_dp_encoder)
5073 intel_dp_set_m_n(crtc);
5074 }
5075
5076 static void i8xx_update_pll(struct intel_crtc *crtc,
5077 intel_clock_t *reduced_clock,
5078 int num_connectors)
5079 {
5080 struct drm_device *dev = crtc->base.dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 u32 dpll;
5083 struct dpll *clock = &crtc->config.dpll;
5084
5085 i9xx_update_pll_dividers(crtc, reduced_clock);
5086
5087 dpll = DPLL_VGA_MODE_DIS;
5088
5089 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5090 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5091 } else {
5092 if (clock->p1 == 2)
5093 dpll |= PLL_P1_DIVIDE_BY_TWO;
5094 else
5095 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5096 if (clock->p2 == 4)
5097 dpll |= PLL_P2_DIVIDE_BY_4;
5098 }
5099
5100 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5101 dpll |= DPLL_DVO_2X_MODE;
5102
5103 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5104 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5105 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5106 else
5107 dpll |= PLL_REF_INPUT_DREFCLK;
5108
5109 dpll |= DPLL_VCO_ENABLE;
5110 crtc->config.dpll_hw_state.dpll = dpll;
5111 }
5112
5113 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5114 {
5115 struct drm_device *dev = intel_crtc->base.dev;
5116 struct drm_i915_private *dev_priv = dev->dev_private;
5117 enum pipe pipe = intel_crtc->pipe;
5118 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5119 struct drm_display_mode *adjusted_mode =
5120 &intel_crtc->config.adjusted_mode;
5121 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5122
5123 /* We need to be careful not to changed the adjusted mode, for otherwise
5124 * the hw state checker will get angry at the mismatch. */
5125 crtc_vtotal = adjusted_mode->crtc_vtotal;
5126 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5127
5128 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5129 /* the chip adds 2 halflines automatically */
5130 crtc_vtotal -= 1;
5131 crtc_vblank_end -= 1;
5132 vsyncshift = adjusted_mode->crtc_hsync_start
5133 - adjusted_mode->crtc_htotal / 2;
5134 } else {
5135 vsyncshift = 0;
5136 }
5137
5138 if (INTEL_INFO(dev)->gen > 3)
5139 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5140
5141 I915_WRITE(HTOTAL(cpu_transcoder),
5142 (adjusted_mode->crtc_hdisplay - 1) |
5143 ((adjusted_mode->crtc_htotal - 1) << 16));
5144 I915_WRITE(HBLANK(cpu_transcoder),
5145 (adjusted_mode->crtc_hblank_start - 1) |
5146 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5147 I915_WRITE(HSYNC(cpu_transcoder),
5148 (adjusted_mode->crtc_hsync_start - 1) |
5149 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5150
5151 I915_WRITE(VTOTAL(cpu_transcoder),
5152 (adjusted_mode->crtc_vdisplay - 1) |
5153 ((crtc_vtotal - 1) << 16));
5154 I915_WRITE(VBLANK(cpu_transcoder),
5155 (adjusted_mode->crtc_vblank_start - 1) |
5156 ((crtc_vblank_end - 1) << 16));
5157 I915_WRITE(VSYNC(cpu_transcoder),
5158 (adjusted_mode->crtc_vsync_start - 1) |
5159 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5160
5161 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5162 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5163 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5164 * bits. */
5165 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5166 (pipe == PIPE_B || pipe == PIPE_C))
5167 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5168
5169 /* pipesrc controls the size that is scaled from, which should
5170 * always be the user's requested size.
5171 */
5172 I915_WRITE(PIPESRC(pipe),
5173 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5174 (intel_crtc->config.pipe_src_h - 1));
5175 }
5176
5177 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5178 struct intel_crtc_config *pipe_config)
5179 {
5180 struct drm_device *dev = crtc->base.dev;
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5183 uint32_t tmp;
5184
5185 tmp = I915_READ(HTOTAL(cpu_transcoder));
5186 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5187 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5188 tmp = I915_READ(HBLANK(cpu_transcoder));
5189 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5190 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5191 tmp = I915_READ(HSYNC(cpu_transcoder));
5192 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5193 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5194
5195 tmp = I915_READ(VTOTAL(cpu_transcoder));
5196 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5197 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5198 tmp = I915_READ(VBLANK(cpu_transcoder));
5199 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5200 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5201 tmp = I915_READ(VSYNC(cpu_transcoder));
5202 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5203 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5204
5205 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5206 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5207 pipe_config->adjusted_mode.crtc_vtotal += 1;
5208 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5209 }
5210
5211 tmp = I915_READ(PIPESRC(crtc->pipe));
5212 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5213 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5214
5215 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5216 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5217 }
5218
5219 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5220 struct intel_crtc_config *pipe_config)
5221 {
5222 struct drm_crtc *crtc = &intel_crtc->base;
5223
5224 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5225 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5226 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5227 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5228
5229 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5230 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5231 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5232 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5233
5234 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5235
5236 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5237 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5238 }
5239
5240 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5241 {
5242 struct drm_device *dev = intel_crtc->base.dev;
5243 struct drm_i915_private *dev_priv = dev->dev_private;
5244 uint32_t pipeconf;
5245
5246 pipeconf = 0;
5247
5248 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5249 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5250 pipeconf |= PIPECONF_ENABLE;
5251
5252 if (intel_crtc->config.double_wide)
5253 pipeconf |= PIPECONF_DOUBLE_WIDE;
5254
5255 /* only g4x and later have fancy bpc/dither controls */
5256 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5257 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5258 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5259 pipeconf |= PIPECONF_DITHER_EN |
5260 PIPECONF_DITHER_TYPE_SP;
5261
5262 switch (intel_crtc->config.pipe_bpp) {
5263 case 18:
5264 pipeconf |= PIPECONF_6BPC;
5265 break;
5266 case 24:
5267 pipeconf |= PIPECONF_8BPC;
5268 break;
5269 case 30:
5270 pipeconf |= PIPECONF_10BPC;
5271 break;
5272 default:
5273 /* Case prevented by intel_choose_pipe_bpp_dither. */
5274 BUG();
5275 }
5276 }
5277
5278 if (HAS_PIPE_CXSR(dev)) {
5279 if (intel_crtc->lowfreq_avail) {
5280 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5281 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5282 } else {
5283 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5284 }
5285 }
5286
5287 if (!IS_GEN2(dev) &&
5288 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5289 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5290 else
5291 pipeconf |= PIPECONF_PROGRESSIVE;
5292
5293 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5294 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5295
5296 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5297 POSTING_READ(PIPECONF(intel_crtc->pipe));
5298 }
5299
5300 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5301 int x, int y,
5302 struct drm_framebuffer *fb)
5303 {
5304 struct drm_device *dev = crtc->dev;
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5307 int pipe = intel_crtc->pipe;
5308 int plane = intel_crtc->plane;
5309 int refclk, num_connectors = 0;
5310 intel_clock_t clock, reduced_clock;
5311 u32 dspcntr;
5312 bool ok, has_reduced_clock = false;
5313 bool is_lvds = false, is_dsi = false;
5314 struct intel_encoder *encoder;
5315 const intel_limit_t *limit;
5316 int ret;
5317
5318 for_each_encoder_on_crtc(dev, crtc, encoder) {
5319 switch (encoder->type) {
5320 case INTEL_OUTPUT_LVDS:
5321 is_lvds = true;
5322 break;
5323 case INTEL_OUTPUT_DSI:
5324 is_dsi = true;
5325 break;
5326 }
5327
5328 num_connectors++;
5329 }
5330
5331 if (is_dsi)
5332 goto skip_dpll;
5333
5334 if (!intel_crtc->config.clock_set) {
5335 refclk = i9xx_get_refclk(crtc, num_connectors);
5336
5337 /*
5338 * Returns a set of divisors for the desired target clock with
5339 * the given refclk, or FALSE. The returned values represent
5340 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5341 * 2) / p1 / p2.
5342 */
5343 limit = intel_limit(crtc, refclk);
5344 ok = dev_priv->display.find_dpll(limit, crtc,
5345 intel_crtc->config.port_clock,
5346 refclk, NULL, &clock);
5347 if (!ok) {
5348 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5349 return -EINVAL;
5350 }
5351
5352 if (is_lvds && dev_priv->lvds_downclock_avail) {
5353 /*
5354 * Ensure we match the reduced clock's P to the target
5355 * clock. If the clocks don't match, we can't switch
5356 * the display clock by using the FP0/FP1. In such case
5357 * we will disable the LVDS downclock feature.
5358 */
5359 has_reduced_clock =
5360 dev_priv->display.find_dpll(limit, crtc,
5361 dev_priv->lvds_downclock,
5362 refclk, &clock,
5363 &reduced_clock);
5364 }
5365 /* Compat-code for transition, will disappear. */
5366 intel_crtc->config.dpll.n = clock.n;
5367 intel_crtc->config.dpll.m1 = clock.m1;
5368 intel_crtc->config.dpll.m2 = clock.m2;
5369 intel_crtc->config.dpll.p1 = clock.p1;
5370 intel_crtc->config.dpll.p2 = clock.p2;
5371 }
5372
5373 if (IS_GEN2(dev)) {
5374 i8xx_update_pll(intel_crtc,
5375 has_reduced_clock ? &reduced_clock : NULL,
5376 num_connectors);
5377 } else if (IS_VALLEYVIEW(dev)) {
5378 vlv_update_pll(intel_crtc);
5379 } else {
5380 i9xx_update_pll(intel_crtc,
5381 has_reduced_clock ? &reduced_clock : NULL,
5382 num_connectors);
5383 }
5384
5385 skip_dpll:
5386 /* Set up the display plane register */
5387 dspcntr = DISPPLANE_GAMMA_ENABLE;
5388
5389 if (!IS_VALLEYVIEW(dev)) {
5390 if (pipe == 0)
5391 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5392 else
5393 dspcntr |= DISPPLANE_SEL_PIPE_B;
5394 }
5395
5396 intel_set_pipe_timings(intel_crtc);
5397
5398 /* pipesrc and dspsize control the size that is scaled from,
5399 * which should always be the user's requested size.
5400 */
5401 I915_WRITE(DSPSIZE(plane),
5402 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5403 (intel_crtc->config.pipe_src_w - 1));
5404 I915_WRITE(DSPPOS(plane), 0);
5405
5406 i9xx_set_pipeconf(intel_crtc);
5407
5408 I915_WRITE(DSPCNTR(plane), dspcntr);
5409 POSTING_READ(DSPCNTR(plane));
5410
5411 ret = intel_pipe_set_base(crtc, x, y, fb);
5412
5413 return ret;
5414 }
5415
5416 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5417 struct intel_crtc_config *pipe_config)
5418 {
5419 struct drm_device *dev = crtc->base.dev;
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 uint32_t tmp;
5422
5423 tmp = I915_READ(PFIT_CONTROL);
5424 if (!(tmp & PFIT_ENABLE))
5425 return;
5426
5427 /* Check whether the pfit is attached to our pipe. */
5428 if (INTEL_INFO(dev)->gen < 4) {
5429 if (crtc->pipe != PIPE_B)
5430 return;
5431 } else {
5432 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5433 return;
5434 }
5435
5436 pipe_config->gmch_pfit.control = tmp;
5437 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5438 if (INTEL_INFO(dev)->gen < 5)
5439 pipe_config->gmch_pfit.lvds_border_bits =
5440 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5441 }
5442
5443 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5444 struct intel_crtc_config *pipe_config)
5445 {
5446 struct drm_device *dev = crtc->base.dev;
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448 int pipe = pipe_config->cpu_transcoder;
5449 intel_clock_t clock;
5450 u32 mdiv;
5451 int refclk = 100000;
5452
5453 mutex_lock(&dev_priv->dpio_lock);
5454 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5455 mutex_unlock(&dev_priv->dpio_lock);
5456
5457 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5458 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5459 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5460 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5461 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5462
5463 vlv_clock(refclk, &clock);
5464
5465 /* clock.dot is the fast clock */
5466 pipe_config->port_clock = clock.dot / 5;
5467 }
5468
5469 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5470 struct intel_crtc_config *pipe_config)
5471 {
5472 struct drm_device *dev = crtc->base.dev;
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 uint32_t tmp;
5475
5476 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5477 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5478
5479 tmp = I915_READ(PIPECONF(crtc->pipe));
5480 if (!(tmp & PIPECONF_ENABLE))
5481 return false;
5482
5483 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5484 switch (tmp & PIPECONF_BPC_MASK) {
5485 case PIPECONF_6BPC:
5486 pipe_config->pipe_bpp = 18;
5487 break;
5488 case PIPECONF_8BPC:
5489 pipe_config->pipe_bpp = 24;
5490 break;
5491 case PIPECONF_10BPC:
5492 pipe_config->pipe_bpp = 30;
5493 break;
5494 default:
5495 break;
5496 }
5497 }
5498
5499 if (INTEL_INFO(dev)->gen < 4)
5500 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5501
5502 intel_get_pipe_timings(crtc, pipe_config);
5503
5504 i9xx_get_pfit_config(crtc, pipe_config);
5505
5506 if (INTEL_INFO(dev)->gen >= 4) {
5507 tmp = I915_READ(DPLL_MD(crtc->pipe));
5508 pipe_config->pixel_multiplier =
5509 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5510 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5511 pipe_config->dpll_hw_state.dpll_md = tmp;
5512 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5513 tmp = I915_READ(DPLL(crtc->pipe));
5514 pipe_config->pixel_multiplier =
5515 ((tmp & SDVO_MULTIPLIER_MASK)
5516 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5517 } else {
5518 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5519 * port and will be fixed up in the encoder->get_config
5520 * function. */
5521 pipe_config->pixel_multiplier = 1;
5522 }
5523 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5524 if (!IS_VALLEYVIEW(dev)) {
5525 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5526 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5527 } else {
5528 /* Mask out read-only status bits. */
5529 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5530 DPLL_PORTC_READY_MASK |
5531 DPLL_PORTB_READY_MASK);
5532 }
5533
5534 if (IS_VALLEYVIEW(dev))
5535 vlv_crtc_clock_get(crtc, pipe_config);
5536 else
5537 i9xx_crtc_clock_get(crtc, pipe_config);
5538
5539 return true;
5540 }
5541
5542 static void ironlake_init_pch_refclk(struct drm_device *dev)
5543 {
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5545 struct drm_mode_config *mode_config = &dev->mode_config;
5546 struct intel_encoder *encoder;
5547 u32 val, final;
5548 bool has_lvds = false;
5549 bool has_cpu_edp = false;
5550 bool has_panel = false;
5551 bool has_ck505 = false;
5552 bool can_ssc = false;
5553
5554 /* We need to take the global config into account */
5555 list_for_each_entry(encoder, &mode_config->encoder_list,
5556 base.head) {
5557 switch (encoder->type) {
5558 case INTEL_OUTPUT_LVDS:
5559 has_panel = true;
5560 has_lvds = true;
5561 break;
5562 case INTEL_OUTPUT_EDP:
5563 has_panel = true;
5564 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5565 has_cpu_edp = true;
5566 break;
5567 }
5568 }
5569
5570 if (HAS_PCH_IBX(dev)) {
5571 has_ck505 = dev_priv->vbt.display_clock_mode;
5572 can_ssc = has_ck505;
5573 } else {
5574 has_ck505 = false;
5575 can_ssc = true;
5576 }
5577
5578 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5579 has_panel, has_lvds, has_ck505);
5580
5581 /* Ironlake: try to setup display ref clock before DPLL
5582 * enabling. This is only under driver's control after
5583 * PCH B stepping, previous chipset stepping should be
5584 * ignoring this setting.
5585 */
5586 val = I915_READ(PCH_DREF_CONTROL);
5587
5588 /* As we must carefully and slowly disable/enable each source in turn,
5589 * compute the final state we want first and check if we need to
5590 * make any changes at all.
5591 */
5592 final = val;
5593 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5594 if (has_ck505)
5595 final |= DREF_NONSPREAD_CK505_ENABLE;
5596 else
5597 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5598
5599 final &= ~DREF_SSC_SOURCE_MASK;
5600 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5601 final &= ~DREF_SSC1_ENABLE;
5602
5603 if (has_panel) {
5604 final |= DREF_SSC_SOURCE_ENABLE;
5605
5606 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5607 final |= DREF_SSC1_ENABLE;
5608
5609 if (has_cpu_edp) {
5610 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5611 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5612 else
5613 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5614 } else
5615 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5616 } else {
5617 final |= DREF_SSC_SOURCE_DISABLE;
5618 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5619 }
5620
5621 if (final == val)
5622 return;
5623
5624 /* Always enable nonspread source */
5625 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5626
5627 if (has_ck505)
5628 val |= DREF_NONSPREAD_CK505_ENABLE;
5629 else
5630 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5631
5632 if (has_panel) {
5633 val &= ~DREF_SSC_SOURCE_MASK;
5634 val |= DREF_SSC_SOURCE_ENABLE;
5635
5636 /* SSC must be turned on before enabling the CPU output */
5637 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5638 DRM_DEBUG_KMS("Using SSC on panel\n");
5639 val |= DREF_SSC1_ENABLE;
5640 } else
5641 val &= ~DREF_SSC1_ENABLE;
5642
5643 /* Get SSC going before enabling the outputs */
5644 I915_WRITE(PCH_DREF_CONTROL, val);
5645 POSTING_READ(PCH_DREF_CONTROL);
5646 udelay(200);
5647
5648 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5649
5650 /* Enable CPU source on CPU attached eDP */
5651 if (has_cpu_edp) {
5652 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5653 DRM_DEBUG_KMS("Using SSC on eDP\n");
5654 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5655 }
5656 else
5657 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5658 } else
5659 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5660
5661 I915_WRITE(PCH_DREF_CONTROL, val);
5662 POSTING_READ(PCH_DREF_CONTROL);
5663 udelay(200);
5664 } else {
5665 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5666
5667 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5668
5669 /* Turn off CPU output */
5670 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5671
5672 I915_WRITE(PCH_DREF_CONTROL, val);
5673 POSTING_READ(PCH_DREF_CONTROL);
5674 udelay(200);
5675
5676 /* Turn off the SSC source */
5677 val &= ~DREF_SSC_SOURCE_MASK;
5678 val |= DREF_SSC_SOURCE_DISABLE;
5679
5680 /* Turn off SSC1 */
5681 val &= ~DREF_SSC1_ENABLE;
5682
5683 I915_WRITE(PCH_DREF_CONTROL, val);
5684 POSTING_READ(PCH_DREF_CONTROL);
5685 udelay(200);
5686 }
5687
5688 BUG_ON(val != final);
5689 }
5690
5691 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5692 {
5693 uint32_t tmp;
5694
5695 tmp = I915_READ(SOUTH_CHICKEN2);
5696 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5697 I915_WRITE(SOUTH_CHICKEN2, tmp);
5698
5699 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5700 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5701 DRM_ERROR("FDI mPHY reset assert timeout\n");
5702
5703 tmp = I915_READ(SOUTH_CHICKEN2);
5704 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5705 I915_WRITE(SOUTH_CHICKEN2, tmp);
5706
5707 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5708 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5709 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5710 }
5711
5712 /* WaMPhyProgramming:hsw */
5713 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5714 {
5715 uint32_t tmp;
5716
5717 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5718 tmp &= ~(0xFF << 24);
5719 tmp |= (0x12 << 24);
5720 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5721
5722 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5723 tmp |= (1 << 11);
5724 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5725
5726 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5727 tmp |= (1 << 11);
5728 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5729
5730 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5731 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5732 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5733
5734 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5735 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5736 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5737
5738 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5739 tmp &= ~(7 << 13);
5740 tmp |= (5 << 13);
5741 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5742
5743 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5744 tmp &= ~(7 << 13);
5745 tmp |= (5 << 13);
5746 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5747
5748 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5749 tmp &= ~0xFF;
5750 tmp |= 0x1C;
5751 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5752
5753 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5754 tmp &= ~0xFF;
5755 tmp |= 0x1C;
5756 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5757
5758 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5759 tmp &= ~(0xFF << 16);
5760 tmp |= (0x1C << 16);
5761 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5762
5763 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5764 tmp &= ~(0xFF << 16);
5765 tmp |= (0x1C << 16);
5766 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5767
5768 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5769 tmp |= (1 << 27);
5770 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5771
5772 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5773 tmp |= (1 << 27);
5774 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5775
5776 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5777 tmp &= ~(0xF << 28);
5778 tmp |= (4 << 28);
5779 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5780
5781 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5782 tmp &= ~(0xF << 28);
5783 tmp |= (4 << 28);
5784 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5785 }
5786
5787 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5788 * Programming" based on the parameters passed:
5789 * - Sequence to enable CLKOUT_DP
5790 * - Sequence to enable CLKOUT_DP without spread
5791 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5792 */
5793 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5794 bool with_fdi)
5795 {
5796 struct drm_i915_private *dev_priv = dev->dev_private;
5797 uint32_t reg, tmp;
5798
5799 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5800 with_spread = true;
5801 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5802 with_fdi, "LP PCH doesn't have FDI\n"))
5803 with_fdi = false;
5804
5805 mutex_lock(&dev_priv->dpio_lock);
5806
5807 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5808 tmp &= ~SBI_SSCCTL_DISABLE;
5809 tmp |= SBI_SSCCTL_PATHALT;
5810 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5811
5812 udelay(24);
5813
5814 if (with_spread) {
5815 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5816 tmp &= ~SBI_SSCCTL_PATHALT;
5817 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5818
5819 if (with_fdi) {
5820 lpt_reset_fdi_mphy(dev_priv);
5821 lpt_program_fdi_mphy(dev_priv);
5822 }
5823 }
5824
5825 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5826 SBI_GEN0 : SBI_DBUFF0;
5827 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5828 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5829 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5830
5831 mutex_unlock(&dev_priv->dpio_lock);
5832 }
5833
5834 /* Sequence to disable CLKOUT_DP */
5835 static void lpt_disable_clkout_dp(struct drm_device *dev)
5836 {
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 uint32_t reg, tmp;
5839
5840 mutex_lock(&dev_priv->dpio_lock);
5841
5842 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5843 SBI_GEN0 : SBI_DBUFF0;
5844 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5845 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5846 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5847
5848 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5849 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5850 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5851 tmp |= SBI_SSCCTL_PATHALT;
5852 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5853 udelay(32);
5854 }
5855 tmp |= SBI_SSCCTL_DISABLE;
5856 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5857 }
5858
5859 mutex_unlock(&dev_priv->dpio_lock);
5860 }
5861
5862 static void lpt_init_pch_refclk(struct drm_device *dev)
5863 {
5864 struct drm_mode_config *mode_config = &dev->mode_config;
5865 struct intel_encoder *encoder;
5866 bool has_vga = false;
5867
5868 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5869 switch (encoder->type) {
5870 case INTEL_OUTPUT_ANALOG:
5871 has_vga = true;
5872 break;
5873 }
5874 }
5875
5876 if (has_vga)
5877 lpt_enable_clkout_dp(dev, true, true);
5878 else
5879 lpt_disable_clkout_dp(dev);
5880 }
5881
5882 /*
5883 * Initialize reference clocks when the driver loads
5884 */
5885 void intel_init_pch_refclk(struct drm_device *dev)
5886 {
5887 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5888 ironlake_init_pch_refclk(dev);
5889 else if (HAS_PCH_LPT(dev))
5890 lpt_init_pch_refclk(dev);
5891 }
5892
5893 static int ironlake_get_refclk(struct drm_crtc *crtc)
5894 {
5895 struct drm_device *dev = crtc->dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 struct intel_encoder *encoder;
5898 int num_connectors = 0;
5899 bool is_lvds = false;
5900
5901 for_each_encoder_on_crtc(dev, crtc, encoder) {
5902 switch (encoder->type) {
5903 case INTEL_OUTPUT_LVDS:
5904 is_lvds = true;
5905 break;
5906 }
5907 num_connectors++;
5908 }
5909
5910 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5911 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5912 dev_priv->vbt.lvds_ssc_freq);
5913 return dev_priv->vbt.lvds_ssc_freq;
5914 }
5915
5916 return 120000;
5917 }
5918
5919 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5920 {
5921 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5923 int pipe = intel_crtc->pipe;
5924 uint32_t val;
5925
5926 val = 0;
5927
5928 switch (intel_crtc->config.pipe_bpp) {
5929 case 18:
5930 val |= PIPECONF_6BPC;
5931 break;
5932 case 24:
5933 val |= PIPECONF_8BPC;
5934 break;
5935 case 30:
5936 val |= PIPECONF_10BPC;
5937 break;
5938 case 36:
5939 val |= PIPECONF_12BPC;
5940 break;
5941 default:
5942 /* Case prevented by intel_choose_pipe_bpp_dither. */
5943 BUG();
5944 }
5945
5946 if (intel_crtc->config.dither)
5947 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5948
5949 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5950 val |= PIPECONF_INTERLACED_ILK;
5951 else
5952 val |= PIPECONF_PROGRESSIVE;
5953
5954 if (intel_crtc->config.limited_color_range)
5955 val |= PIPECONF_COLOR_RANGE_SELECT;
5956
5957 I915_WRITE(PIPECONF(pipe), val);
5958 POSTING_READ(PIPECONF(pipe));
5959 }
5960
5961 /*
5962 * Set up the pipe CSC unit.
5963 *
5964 * Currently only full range RGB to limited range RGB conversion
5965 * is supported, but eventually this should handle various
5966 * RGB<->YCbCr scenarios as well.
5967 */
5968 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5969 {
5970 struct drm_device *dev = crtc->dev;
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5973 int pipe = intel_crtc->pipe;
5974 uint16_t coeff = 0x7800; /* 1.0 */
5975
5976 /*
5977 * TODO: Check what kind of values actually come out of the pipe
5978 * with these coeff/postoff values and adjust to get the best
5979 * accuracy. Perhaps we even need to take the bpc value into
5980 * consideration.
5981 */
5982
5983 if (intel_crtc->config.limited_color_range)
5984 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5985
5986 /*
5987 * GY/GU and RY/RU should be the other way around according
5988 * to BSpec, but reality doesn't agree. Just set them up in
5989 * a way that results in the correct picture.
5990 */
5991 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5992 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5993
5994 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5995 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5996
5997 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5998 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5999
6000 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6001 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6002 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6003
6004 if (INTEL_INFO(dev)->gen > 6) {
6005 uint16_t postoff = 0;
6006
6007 if (intel_crtc->config.limited_color_range)
6008 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6009
6010 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6011 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6012 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6013
6014 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6015 } else {
6016 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6017
6018 if (intel_crtc->config.limited_color_range)
6019 mode |= CSC_BLACK_SCREEN_OFFSET;
6020
6021 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6022 }
6023 }
6024
6025 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6026 {
6027 struct drm_device *dev = crtc->dev;
6028 struct drm_i915_private *dev_priv = dev->dev_private;
6029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6030 enum pipe pipe = intel_crtc->pipe;
6031 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6032 uint32_t val;
6033
6034 val = 0;
6035
6036 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6037 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6038
6039 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6040 val |= PIPECONF_INTERLACED_ILK;
6041 else
6042 val |= PIPECONF_PROGRESSIVE;
6043
6044 I915_WRITE(PIPECONF(cpu_transcoder), val);
6045 POSTING_READ(PIPECONF(cpu_transcoder));
6046
6047 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6048 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6049
6050 if (IS_BROADWELL(dev)) {
6051 val = 0;
6052
6053 switch (intel_crtc->config.pipe_bpp) {
6054 case 18:
6055 val |= PIPEMISC_DITHER_6_BPC;
6056 break;
6057 case 24:
6058 val |= PIPEMISC_DITHER_8_BPC;
6059 break;
6060 case 30:
6061 val |= PIPEMISC_DITHER_10_BPC;
6062 break;
6063 case 36:
6064 val |= PIPEMISC_DITHER_12_BPC;
6065 break;
6066 default:
6067 /* Case prevented by pipe_config_set_bpp. */
6068 BUG();
6069 }
6070
6071 if (intel_crtc->config.dither)
6072 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6073
6074 I915_WRITE(PIPEMISC(pipe), val);
6075 }
6076 }
6077
6078 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6079 intel_clock_t *clock,
6080 bool *has_reduced_clock,
6081 intel_clock_t *reduced_clock)
6082 {
6083 struct drm_device *dev = crtc->dev;
6084 struct drm_i915_private *dev_priv = dev->dev_private;
6085 struct intel_encoder *intel_encoder;
6086 int refclk;
6087 const intel_limit_t *limit;
6088 bool ret, is_lvds = false;
6089
6090 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6091 switch (intel_encoder->type) {
6092 case INTEL_OUTPUT_LVDS:
6093 is_lvds = true;
6094 break;
6095 }
6096 }
6097
6098 refclk = ironlake_get_refclk(crtc);
6099
6100 /*
6101 * Returns a set of divisors for the desired target clock with the given
6102 * refclk, or FALSE. The returned values represent the clock equation:
6103 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6104 */
6105 limit = intel_limit(crtc, refclk);
6106 ret = dev_priv->display.find_dpll(limit, crtc,
6107 to_intel_crtc(crtc)->config.port_clock,
6108 refclk, NULL, clock);
6109 if (!ret)
6110 return false;
6111
6112 if (is_lvds && dev_priv->lvds_downclock_avail) {
6113 /*
6114 * Ensure we match the reduced clock's P to the target clock.
6115 * If the clocks don't match, we can't switch the display clock
6116 * by using the FP0/FP1. In such case we will disable the LVDS
6117 * downclock feature.
6118 */
6119 *has_reduced_clock =
6120 dev_priv->display.find_dpll(limit, crtc,
6121 dev_priv->lvds_downclock,
6122 refclk, clock,
6123 reduced_clock);
6124 }
6125
6126 return true;
6127 }
6128
6129 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6130 {
6131 /*
6132 * Account for spread spectrum to avoid
6133 * oversubscribing the link. Max center spread
6134 * is 2.5%; use 5% for safety's sake.
6135 */
6136 u32 bps = target_clock * bpp * 21 / 20;
6137 return bps / (link_bw * 8) + 1;
6138 }
6139
6140 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6141 {
6142 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6143 }
6144
6145 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6146 u32 *fp,
6147 intel_clock_t *reduced_clock, u32 *fp2)
6148 {
6149 struct drm_crtc *crtc = &intel_crtc->base;
6150 struct drm_device *dev = crtc->dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152 struct intel_encoder *intel_encoder;
6153 uint32_t dpll;
6154 int factor, num_connectors = 0;
6155 bool is_lvds = false, is_sdvo = false;
6156
6157 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6158 switch (intel_encoder->type) {
6159 case INTEL_OUTPUT_LVDS:
6160 is_lvds = true;
6161 break;
6162 case INTEL_OUTPUT_SDVO:
6163 case INTEL_OUTPUT_HDMI:
6164 is_sdvo = true;
6165 break;
6166 }
6167
6168 num_connectors++;
6169 }
6170
6171 /* Enable autotuning of the PLL clock (if permissible) */
6172 factor = 21;
6173 if (is_lvds) {
6174 if ((intel_panel_use_ssc(dev_priv) &&
6175 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6176 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6177 factor = 25;
6178 } else if (intel_crtc->config.sdvo_tv_clock)
6179 factor = 20;
6180
6181 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6182 *fp |= FP_CB_TUNE;
6183
6184 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6185 *fp2 |= FP_CB_TUNE;
6186
6187 dpll = 0;
6188
6189 if (is_lvds)
6190 dpll |= DPLLB_MODE_LVDS;
6191 else
6192 dpll |= DPLLB_MODE_DAC_SERIAL;
6193
6194 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6195 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6196
6197 if (is_sdvo)
6198 dpll |= DPLL_SDVO_HIGH_SPEED;
6199 if (intel_crtc->config.has_dp_encoder)
6200 dpll |= DPLL_SDVO_HIGH_SPEED;
6201
6202 /* compute bitmask from p1 value */
6203 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6204 /* also FPA1 */
6205 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6206
6207 switch (intel_crtc->config.dpll.p2) {
6208 case 5:
6209 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6210 break;
6211 case 7:
6212 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6213 break;
6214 case 10:
6215 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6216 break;
6217 case 14:
6218 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6219 break;
6220 }
6221
6222 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6223 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6224 else
6225 dpll |= PLL_REF_INPUT_DREFCLK;
6226
6227 return dpll | DPLL_VCO_ENABLE;
6228 }
6229
6230 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6231 int x, int y,
6232 struct drm_framebuffer *fb)
6233 {
6234 struct drm_device *dev = crtc->dev;
6235 struct drm_i915_private *dev_priv = dev->dev_private;
6236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237 int pipe = intel_crtc->pipe;
6238 int plane = intel_crtc->plane;
6239 int num_connectors = 0;
6240 intel_clock_t clock, reduced_clock;
6241 u32 dpll = 0, fp = 0, fp2 = 0;
6242 bool ok, has_reduced_clock = false;
6243 bool is_lvds = false;
6244 struct intel_encoder *encoder;
6245 struct intel_shared_dpll *pll;
6246 int ret;
6247
6248 for_each_encoder_on_crtc(dev, crtc, encoder) {
6249 switch (encoder->type) {
6250 case INTEL_OUTPUT_LVDS:
6251 is_lvds = true;
6252 break;
6253 }
6254
6255 num_connectors++;
6256 }
6257
6258 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6259 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6260
6261 ok = ironlake_compute_clocks(crtc, &clock,
6262 &has_reduced_clock, &reduced_clock);
6263 if (!ok && !intel_crtc->config.clock_set) {
6264 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6265 return -EINVAL;
6266 }
6267 /* Compat-code for transition, will disappear. */
6268 if (!intel_crtc->config.clock_set) {
6269 intel_crtc->config.dpll.n = clock.n;
6270 intel_crtc->config.dpll.m1 = clock.m1;
6271 intel_crtc->config.dpll.m2 = clock.m2;
6272 intel_crtc->config.dpll.p1 = clock.p1;
6273 intel_crtc->config.dpll.p2 = clock.p2;
6274 }
6275
6276 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6277 if (intel_crtc->config.has_pch_encoder) {
6278 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6279 if (has_reduced_clock)
6280 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6281
6282 dpll = ironlake_compute_dpll(intel_crtc,
6283 &fp, &reduced_clock,
6284 has_reduced_clock ? &fp2 : NULL);
6285
6286 intel_crtc->config.dpll_hw_state.dpll = dpll;
6287 intel_crtc->config.dpll_hw_state.fp0 = fp;
6288 if (has_reduced_clock)
6289 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6290 else
6291 intel_crtc->config.dpll_hw_state.fp1 = fp;
6292
6293 pll = intel_get_shared_dpll(intel_crtc);
6294 if (pll == NULL) {
6295 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6296 pipe_name(pipe));
6297 return -EINVAL;
6298 }
6299 } else
6300 intel_put_shared_dpll(intel_crtc);
6301
6302 if (intel_crtc->config.has_dp_encoder)
6303 intel_dp_set_m_n(intel_crtc);
6304
6305 if (is_lvds && has_reduced_clock && i915_powersave)
6306 intel_crtc->lowfreq_avail = true;
6307 else
6308 intel_crtc->lowfreq_avail = false;
6309
6310 intel_set_pipe_timings(intel_crtc);
6311
6312 if (intel_crtc->config.has_pch_encoder) {
6313 intel_cpu_transcoder_set_m_n(intel_crtc,
6314 &intel_crtc->config.fdi_m_n);
6315 }
6316
6317 ironlake_set_pipeconf(crtc);
6318
6319 /* Set up the display plane register */
6320 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6321 POSTING_READ(DSPCNTR(plane));
6322
6323 ret = intel_pipe_set_base(crtc, x, y, fb);
6324
6325 return ret;
6326 }
6327
6328 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6329 struct intel_link_m_n *m_n)
6330 {
6331 struct drm_device *dev = crtc->base.dev;
6332 struct drm_i915_private *dev_priv = dev->dev_private;
6333 enum pipe pipe = crtc->pipe;
6334
6335 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6336 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6337 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6338 & ~TU_SIZE_MASK;
6339 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6340 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6341 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6342 }
6343
6344 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6345 enum transcoder transcoder,
6346 struct intel_link_m_n *m_n)
6347 {
6348 struct drm_device *dev = crtc->base.dev;
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 enum pipe pipe = crtc->pipe;
6351
6352 if (INTEL_INFO(dev)->gen >= 5) {
6353 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6354 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6355 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6356 & ~TU_SIZE_MASK;
6357 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6358 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6359 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6360 } else {
6361 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6362 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6363 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6364 & ~TU_SIZE_MASK;
6365 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6366 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6367 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6368 }
6369 }
6370
6371 void intel_dp_get_m_n(struct intel_crtc *crtc,
6372 struct intel_crtc_config *pipe_config)
6373 {
6374 if (crtc->config.has_pch_encoder)
6375 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6376 else
6377 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6378 &pipe_config->dp_m_n);
6379 }
6380
6381 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6382 struct intel_crtc_config *pipe_config)
6383 {
6384 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6385 &pipe_config->fdi_m_n);
6386 }
6387
6388 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6389 struct intel_crtc_config *pipe_config)
6390 {
6391 struct drm_device *dev = crtc->base.dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 uint32_t tmp;
6394
6395 tmp = I915_READ(PF_CTL(crtc->pipe));
6396
6397 if (tmp & PF_ENABLE) {
6398 pipe_config->pch_pfit.enabled = true;
6399 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6400 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6401
6402 /* We currently do not free assignements of panel fitters on
6403 * ivb/hsw (since we don't use the higher upscaling modes which
6404 * differentiates them) so just WARN about this case for now. */
6405 if (IS_GEN7(dev)) {
6406 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6407 PF_PIPE_SEL_IVB(crtc->pipe));
6408 }
6409 }
6410 }
6411
6412 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6413 struct intel_crtc_config *pipe_config)
6414 {
6415 struct drm_device *dev = crtc->base.dev;
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 uint32_t tmp;
6418
6419 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6420 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6421
6422 tmp = I915_READ(PIPECONF(crtc->pipe));
6423 if (!(tmp & PIPECONF_ENABLE))
6424 return false;
6425
6426 switch (tmp & PIPECONF_BPC_MASK) {
6427 case PIPECONF_6BPC:
6428 pipe_config->pipe_bpp = 18;
6429 break;
6430 case PIPECONF_8BPC:
6431 pipe_config->pipe_bpp = 24;
6432 break;
6433 case PIPECONF_10BPC:
6434 pipe_config->pipe_bpp = 30;
6435 break;
6436 case PIPECONF_12BPC:
6437 pipe_config->pipe_bpp = 36;
6438 break;
6439 default:
6440 break;
6441 }
6442
6443 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6444 struct intel_shared_dpll *pll;
6445
6446 pipe_config->has_pch_encoder = true;
6447
6448 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6449 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6450 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6451
6452 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6453
6454 if (HAS_PCH_IBX(dev_priv->dev)) {
6455 pipe_config->shared_dpll =
6456 (enum intel_dpll_id) crtc->pipe;
6457 } else {
6458 tmp = I915_READ(PCH_DPLL_SEL);
6459 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6460 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6461 else
6462 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6463 }
6464
6465 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6466
6467 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6468 &pipe_config->dpll_hw_state));
6469
6470 tmp = pipe_config->dpll_hw_state.dpll;
6471 pipe_config->pixel_multiplier =
6472 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6473 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6474
6475 ironlake_pch_clock_get(crtc, pipe_config);
6476 } else {
6477 pipe_config->pixel_multiplier = 1;
6478 }
6479
6480 intel_get_pipe_timings(crtc, pipe_config);
6481
6482 ironlake_get_pfit_config(crtc, pipe_config);
6483
6484 return true;
6485 }
6486
6487 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6488 {
6489 struct drm_device *dev = dev_priv->dev;
6490 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6491 struct intel_crtc *crtc;
6492 unsigned long irqflags;
6493 uint32_t val;
6494
6495 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6496 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6497 pipe_name(crtc->pipe));
6498
6499 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6500 WARN(plls->spll_refcount, "SPLL enabled\n");
6501 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6502 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6503 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6504 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6505 "CPU PWM1 enabled\n");
6506 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6507 "CPU PWM2 enabled\n");
6508 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6509 "PCH PWM1 enabled\n");
6510 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6511 "Utility pin enabled\n");
6512 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6513
6514 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6515 val = I915_READ(DEIMR);
6516 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6517 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6518 val = I915_READ(SDEIMR);
6519 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6520 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6521 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6522 }
6523
6524 /*
6525 * This function implements pieces of two sequences from BSpec:
6526 * - Sequence for display software to disable LCPLL
6527 * - Sequence for display software to allow package C8+
6528 * The steps implemented here are just the steps that actually touch the LCPLL
6529 * register. Callers should take care of disabling all the display engine
6530 * functions, doing the mode unset, fixing interrupts, etc.
6531 */
6532 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6533 bool switch_to_fclk, bool allow_power_down)
6534 {
6535 uint32_t val;
6536
6537 assert_can_disable_lcpll(dev_priv);
6538
6539 val = I915_READ(LCPLL_CTL);
6540
6541 if (switch_to_fclk) {
6542 val |= LCPLL_CD_SOURCE_FCLK;
6543 I915_WRITE(LCPLL_CTL, val);
6544
6545 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6546 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6547 DRM_ERROR("Switching to FCLK failed\n");
6548
6549 val = I915_READ(LCPLL_CTL);
6550 }
6551
6552 val |= LCPLL_PLL_DISABLE;
6553 I915_WRITE(LCPLL_CTL, val);
6554 POSTING_READ(LCPLL_CTL);
6555
6556 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6557 DRM_ERROR("LCPLL still locked\n");
6558
6559 val = I915_READ(D_COMP);
6560 val |= D_COMP_COMP_DISABLE;
6561 mutex_lock(&dev_priv->rps.hw_lock);
6562 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6563 DRM_ERROR("Failed to disable D_COMP\n");
6564 mutex_unlock(&dev_priv->rps.hw_lock);
6565 POSTING_READ(D_COMP);
6566 ndelay(100);
6567
6568 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6569 DRM_ERROR("D_COMP RCOMP still in progress\n");
6570
6571 if (allow_power_down) {
6572 val = I915_READ(LCPLL_CTL);
6573 val |= LCPLL_POWER_DOWN_ALLOW;
6574 I915_WRITE(LCPLL_CTL, val);
6575 POSTING_READ(LCPLL_CTL);
6576 }
6577 }
6578
6579 /*
6580 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6581 * source.
6582 */
6583 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6584 {
6585 uint32_t val;
6586
6587 val = I915_READ(LCPLL_CTL);
6588
6589 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6590 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6591 return;
6592
6593 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6594 * we'll hang the machine! */
6595 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6596
6597 if (val & LCPLL_POWER_DOWN_ALLOW) {
6598 val &= ~LCPLL_POWER_DOWN_ALLOW;
6599 I915_WRITE(LCPLL_CTL, val);
6600 POSTING_READ(LCPLL_CTL);
6601 }
6602
6603 val = I915_READ(D_COMP);
6604 val |= D_COMP_COMP_FORCE;
6605 val &= ~D_COMP_COMP_DISABLE;
6606 mutex_lock(&dev_priv->rps.hw_lock);
6607 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6608 DRM_ERROR("Failed to enable D_COMP\n");
6609 mutex_unlock(&dev_priv->rps.hw_lock);
6610 POSTING_READ(D_COMP);
6611
6612 val = I915_READ(LCPLL_CTL);
6613 val &= ~LCPLL_PLL_DISABLE;
6614 I915_WRITE(LCPLL_CTL, val);
6615
6616 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6617 DRM_ERROR("LCPLL not locked yet\n");
6618
6619 if (val & LCPLL_CD_SOURCE_FCLK) {
6620 val = I915_READ(LCPLL_CTL);
6621 val &= ~LCPLL_CD_SOURCE_FCLK;
6622 I915_WRITE(LCPLL_CTL, val);
6623
6624 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6625 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6626 DRM_ERROR("Switching back to LCPLL failed\n");
6627 }
6628
6629 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6630 }
6631
6632 void hsw_enable_pc8_work(struct work_struct *__work)
6633 {
6634 struct drm_i915_private *dev_priv =
6635 container_of(to_delayed_work(__work), struct drm_i915_private,
6636 pc8.enable_work);
6637 struct drm_device *dev = dev_priv->dev;
6638 uint32_t val;
6639
6640 WARN_ON(!HAS_PC8(dev));
6641
6642 if (dev_priv->pc8.enabled)
6643 return;
6644
6645 DRM_DEBUG_KMS("Enabling package C8+\n");
6646
6647 dev_priv->pc8.enabled = true;
6648
6649 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6650 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6651 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6652 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6653 }
6654
6655 lpt_disable_clkout_dp(dev);
6656 hsw_pc8_disable_interrupts(dev);
6657 hsw_disable_lcpll(dev_priv, true, true);
6658
6659 intel_runtime_pm_put(dev_priv);
6660 }
6661
6662 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6663 {
6664 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6665 WARN(dev_priv->pc8.disable_count < 1,
6666 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6667
6668 dev_priv->pc8.disable_count--;
6669 if (dev_priv->pc8.disable_count != 0)
6670 return;
6671
6672 schedule_delayed_work(&dev_priv->pc8.enable_work,
6673 msecs_to_jiffies(i915_pc8_timeout));
6674 }
6675
6676 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6677 {
6678 struct drm_device *dev = dev_priv->dev;
6679 uint32_t val;
6680
6681 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6682 WARN(dev_priv->pc8.disable_count < 0,
6683 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6684
6685 dev_priv->pc8.disable_count++;
6686 if (dev_priv->pc8.disable_count != 1)
6687 return;
6688
6689 WARN_ON(!HAS_PC8(dev));
6690
6691 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6692 if (!dev_priv->pc8.enabled)
6693 return;
6694
6695 DRM_DEBUG_KMS("Disabling package C8+\n");
6696
6697 intel_runtime_pm_get(dev_priv);
6698
6699 hsw_restore_lcpll(dev_priv);
6700 hsw_pc8_restore_interrupts(dev);
6701 lpt_init_pch_refclk(dev);
6702
6703 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6704 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6705 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6706 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6707 }
6708
6709 intel_prepare_ddi(dev);
6710 i915_gem_init_swizzling(dev);
6711 mutex_lock(&dev_priv->rps.hw_lock);
6712 gen6_update_ring_freq(dev);
6713 mutex_unlock(&dev_priv->rps.hw_lock);
6714 dev_priv->pc8.enabled = false;
6715 }
6716
6717 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6718 {
6719 if (!HAS_PC8(dev_priv->dev))
6720 return;
6721
6722 mutex_lock(&dev_priv->pc8.lock);
6723 __hsw_enable_package_c8(dev_priv);
6724 mutex_unlock(&dev_priv->pc8.lock);
6725 }
6726
6727 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6728 {
6729 if (!HAS_PC8(dev_priv->dev))
6730 return;
6731
6732 mutex_lock(&dev_priv->pc8.lock);
6733 __hsw_disable_package_c8(dev_priv);
6734 mutex_unlock(&dev_priv->pc8.lock);
6735 }
6736
6737 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6738 {
6739 struct drm_device *dev = dev_priv->dev;
6740 struct intel_crtc *crtc;
6741 uint32_t val;
6742
6743 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6744 if (crtc->base.enabled)
6745 return false;
6746
6747 /* This case is still possible since we have the i915.disable_power_well
6748 * parameter and also the KVMr or something else might be requesting the
6749 * power well. */
6750 val = I915_READ(HSW_PWR_WELL_DRIVER);
6751 if (val != 0) {
6752 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6753 return false;
6754 }
6755
6756 return true;
6757 }
6758
6759 /* Since we're called from modeset_global_resources there's no way to
6760 * symmetrically increase and decrease the refcount, so we use
6761 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6762 * or not.
6763 */
6764 static void hsw_update_package_c8(struct drm_device *dev)
6765 {
6766 struct drm_i915_private *dev_priv = dev->dev_private;
6767 bool allow;
6768
6769 if (!HAS_PC8(dev_priv->dev))
6770 return;
6771
6772 if (!i915_enable_pc8)
6773 return;
6774
6775 mutex_lock(&dev_priv->pc8.lock);
6776
6777 allow = hsw_can_enable_package_c8(dev_priv);
6778
6779 if (allow == dev_priv->pc8.requirements_met)
6780 goto done;
6781
6782 dev_priv->pc8.requirements_met = allow;
6783
6784 if (allow)
6785 __hsw_enable_package_c8(dev_priv);
6786 else
6787 __hsw_disable_package_c8(dev_priv);
6788
6789 done:
6790 mutex_unlock(&dev_priv->pc8.lock);
6791 }
6792
6793 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6794 {
6795 if (!HAS_PC8(dev_priv->dev))
6796 return;
6797
6798 mutex_lock(&dev_priv->pc8.lock);
6799 if (!dev_priv->pc8.gpu_idle) {
6800 dev_priv->pc8.gpu_idle = true;
6801 __hsw_enable_package_c8(dev_priv);
6802 }
6803 mutex_unlock(&dev_priv->pc8.lock);
6804 }
6805
6806 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6807 {
6808 if (!HAS_PC8(dev_priv->dev))
6809 return;
6810
6811 mutex_lock(&dev_priv->pc8.lock);
6812 if (dev_priv->pc8.gpu_idle) {
6813 dev_priv->pc8.gpu_idle = false;
6814 __hsw_disable_package_c8(dev_priv);
6815 }
6816 mutex_unlock(&dev_priv->pc8.lock);
6817 }
6818
6819 #define for_each_power_domain(domain, mask) \
6820 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6821 if ((1 << (domain)) & (mask))
6822
6823 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6824 enum pipe pipe, bool pfit_enabled)
6825 {
6826 unsigned long mask;
6827 enum transcoder transcoder;
6828
6829 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6830
6831 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6832 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6833 if (pfit_enabled)
6834 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6835
6836 return mask;
6837 }
6838
6839 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6840 {
6841 struct drm_i915_private *dev_priv = dev->dev_private;
6842
6843 if (dev_priv->power_domains.init_power_on == enable)
6844 return;
6845
6846 if (enable)
6847 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6848 else
6849 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6850
6851 dev_priv->power_domains.init_power_on = enable;
6852 }
6853
6854 static void modeset_update_power_wells(struct drm_device *dev)
6855 {
6856 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6857 struct intel_crtc *crtc;
6858
6859 /*
6860 * First get all needed power domains, then put all unneeded, to avoid
6861 * any unnecessary toggling of the power wells.
6862 */
6863 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6864 enum intel_display_power_domain domain;
6865
6866 if (!crtc->base.enabled)
6867 continue;
6868
6869 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6870 crtc->pipe,
6871 crtc->config.pch_pfit.enabled);
6872
6873 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6874 intel_display_power_get(dev, domain);
6875 }
6876
6877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6878 enum intel_display_power_domain domain;
6879
6880 for_each_power_domain(domain, crtc->enabled_power_domains)
6881 intel_display_power_put(dev, domain);
6882
6883 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6884 }
6885
6886 intel_display_set_init_power(dev, false);
6887 }
6888
6889 static void haswell_modeset_global_resources(struct drm_device *dev)
6890 {
6891 modeset_update_power_wells(dev);
6892 hsw_update_package_c8(dev);
6893 }
6894
6895 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6896 int x, int y,
6897 struct drm_framebuffer *fb)
6898 {
6899 struct drm_device *dev = crtc->dev;
6900 struct drm_i915_private *dev_priv = dev->dev_private;
6901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6902 int plane = intel_crtc->plane;
6903 int ret;
6904
6905 if (!intel_ddi_pll_select(intel_crtc))
6906 return -EINVAL;
6907 intel_ddi_pll_enable(intel_crtc);
6908
6909 if (intel_crtc->config.has_dp_encoder)
6910 intel_dp_set_m_n(intel_crtc);
6911
6912 intel_crtc->lowfreq_avail = false;
6913
6914 intel_set_pipe_timings(intel_crtc);
6915
6916 if (intel_crtc->config.has_pch_encoder) {
6917 intel_cpu_transcoder_set_m_n(intel_crtc,
6918 &intel_crtc->config.fdi_m_n);
6919 }
6920
6921 haswell_set_pipeconf(crtc);
6922
6923 intel_set_pipe_csc(crtc);
6924
6925 /* Set up the display plane register */
6926 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6927 POSTING_READ(DSPCNTR(plane));
6928
6929 ret = intel_pipe_set_base(crtc, x, y, fb);
6930
6931 return ret;
6932 }
6933
6934 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6935 struct intel_crtc_config *pipe_config)
6936 {
6937 struct drm_device *dev = crtc->base.dev;
6938 struct drm_i915_private *dev_priv = dev->dev_private;
6939 enum intel_display_power_domain pfit_domain;
6940 uint32_t tmp;
6941
6942 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6943 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6944
6945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6946 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6947 enum pipe trans_edp_pipe;
6948 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6949 default:
6950 WARN(1, "unknown pipe linked to edp transcoder\n");
6951 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6952 case TRANS_DDI_EDP_INPUT_A_ON:
6953 trans_edp_pipe = PIPE_A;
6954 break;
6955 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6956 trans_edp_pipe = PIPE_B;
6957 break;
6958 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6959 trans_edp_pipe = PIPE_C;
6960 break;
6961 }
6962
6963 if (trans_edp_pipe == crtc->pipe)
6964 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6965 }
6966
6967 if (!intel_display_power_enabled(dev,
6968 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6969 return false;
6970
6971 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6972 if (!(tmp & PIPECONF_ENABLE))
6973 return false;
6974
6975 /*
6976 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6977 * DDI E. So just check whether this pipe is wired to DDI E and whether
6978 * the PCH transcoder is on.
6979 */
6980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6981 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6982 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6983 pipe_config->has_pch_encoder = true;
6984
6985 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6986 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6987 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6988
6989 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6990 }
6991
6992 intel_get_pipe_timings(crtc, pipe_config);
6993
6994 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6995 if (intel_display_power_enabled(dev, pfit_domain))
6996 ironlake_get_pfit_config(crtc, pipe_config);
6997
6998 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6999 (I915_READ(IPS_CTL) & IPS_ENABLE);
7000
7001 pipe_config->pixel_multiplier = 1;
7002
7003 return true;
7004 }
7005
7006 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7007 int x, int y,
7008 struct drm_framebuffer *fb)
7009 {
7010 struct drm_device *dev = crtc->dev;
7011 struct drm_i915_private *dev_priv = dev->dev_private;
7012 struct intel_encoder *encoder;
7013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7014 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7015 int pipe = intel_crtc->pipe;
7016 int ret;
7017
7018 drm_vblank_pre_modeset(dev, pipe);
7019
7020 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7021
7022 drm_vblank_post_modeset(dev, pipe);
7023
7024 if (ret != 0)
7025 return ret;
7026
7027 for_each_encoder_on_crtc(dev, crtc, encoder) {
7028 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7029 encoder->base.base.id,
7030 drm_get_encoder_name(&encoder->base),
7031 mode->base.id, mode->name);
7032 encoder->mode_set(encoder);
7033 }
7034
7035 return 0;
7036 }
7037
7038 static struct {
7039 int clock;
7040 u32 config;
7041 } hdmi_audio_clock[] = {
7042 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7043 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7044 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7045 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7046 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7047 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7048 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7049 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7050 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7051 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7052 };
7053
7054 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7055 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7056 {
7057 int i;
7058
7059 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7060 if (mode->clock == hdmi_audio_clock[i].clock)
7061 break;
7062 }
7063
7064 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7065 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7066 i = 1;
7067 }
7068
7069 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7070 hdmi_audio_clock[i].clock,
7071 hdmi_audio_clock[i].config);
7072
7073 return hdmi_audio_clock[i].config;
7074 }
7075
7076 static bool intel_eld_uptodate(struct drm_connector *connector,
7077 int reg_eldv, uint32_t bits_eldv,
7078 int reg_elda, uint32_t bits_elda,
7079 int reg_edid)
7080 {
7081 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7082 uint8_t *eld = connector->eld;
7083 uint32_t i;
7084
7085 i = I915_READ(reg_eldv);
7086 i &= bits_eldv;
7087
7088 if (!eld[0])
7089 return !i;
7090
7091 if (!i)
7092 return false;
7093
7094 i = I915_READ(reg_elda);
7095 i &= ~bits_elda;
7096 I915_WRITE(reg_elda, i);
7097
7098 for (i = 0; i < eld[2]; i++)
7099 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7100 return false;
7101
7102 return true;
7103 }
7104
7105 static void g4x_write_eld(struct drm_connector *connector,
7106 struct drm_crtc *crtc,
7107 struct drm_display_mode *mode)
7108 {
7109 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7110 uint8_t *eld = connector->eld;
7111 uint32_t eldv;
7112 uint32_t len;
7113 uint32_t i;
7114
7115 i = I915_READ(G4X_AUD_VID_DID);
7116
7117 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7118 eldv = G4X_ELDV_DEVCL_DEVBLC;
7119 else
7120 eldv = G4X_ELDV_DEVCTG;
7121
7122 if (intel_eld_uptodate(connector,
7123 G4X_AUD_CNTL_ST, eldv,
7124 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7125 G4X_HDMIW_HDMIEDID))
7126 return;
7127
7128 i = I915_READ(G4X_AUD_CNTL_ST);
7129 i &= ~(eldv | G4X_ELD_ADDR);
7130 len = (i >> 9) & 0x1f; /* ELD buffer size */
7131 I915_WRITE(G4X_AUD_CNTL_ST, i);
7132
7133 if (!eld[0])
7134 return;
7135
7136 len = min_t(uint8_t, eld[2], len);
7137 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7138 for (i = 0; i < len; i++)
7139 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7140
7141 i = I915_READ(G4X_AUD_CNTL_ST);
7142 i |= eldv;
7143 I915_WRITE(G4X_AUD_CNTL_ST, i);
7144 }
7145
7146 static void haswell_write_eld(struct drm_connector *connector,
7147 struct drm_crtc *crtc,
7148 struct drm_display_mode *mode)
7149 {
7150 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7151 uint8_t *eld = connector->eld;
7152 struct drm_device *dev = crtc->dev;
7153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7154 uint32_t eldv;
7155 uint32_t i;
7156 int len;
7157 int pipe = to_intel_crtc(crtc)->pipe;
7158 int tmp;
7159
7160 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7161 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7162 int aud_config = HSW_AUD_CFG(pipe);
7163 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7164
7165
7166 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7167
7168 /* Audio output enable */
7169 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7170 tmp = I915_READ(aud_cntrl_st2);
7171 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7172 I915_WRITE(aud_cntrl_st2, tmp);
7173
7174 /* Wait for 1 vertical blank */
7175 intel_wait_for_vblank(dev, pipe);
7176
7177 /* Set ELD valid state */
7178 tmp = I915_READ(aud_cntrl_st2);
7179 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7180 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7181 I915_WRITE(aud_cntrl_st2, tmp);
7182 tmp = I915_READ(aud_cntrl_st2);
7183 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7184
7185 /* Enable HDMI mode */
7186 tmp = I915_READ(aud_config);
7187 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7188 /* clear N_programing_enable and N_value_index */
7189 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7190 I915_WRITE(aud_config, tmp);
7191
7192 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7193
7194 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7195 intel_crtc->eld_vld = true;
7196
7197 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7198 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7199 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7200 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7201 } else {
7202 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7203 }
7204
7205 if (intel_eld_uptodate(connector,
7206 aud_cntrl_st2, eldv,
7207 aud_cntl_st, IBX_ELD_ADDRESS,
7208 hdmiw_hdmiedid))
7209 return;
7210
7211 i = I915_READ(aud_cntrl_st2);
7212 i &= ~eldv;
7213 I915_WRITE(aud_cntrl_st2, i);
7214
7215 if (!eld[0])
7216 return;
7217
7218 i = I915_READ(aud_cntl_st);
7219 i &= ~IBX_ELD_ADDRESS;
7220 I915_WRITE(aud_cntl_st, i);
7221 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7222 DRM_DEBUG_DRIVER("port num:%d\n", i);
7223
7224 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7225 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7226 for (i = 0; i < len; i++)
7227 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7228
7229 i = I915_READ(aud_cntrl_st2);
7230 i |= eldv;
7231 I915_WRITE(aud_cntrl_st2, i);
7232
7233 }
7234
7235 static void ironlake_write_eld(struct drm_connector *connector,
7236 struct drm_crtc *crtc,
7237 struct drm_display_mode *mode)
7238 {
7239 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7240 uint8_t *eld = connector->eld;
7241 uint32_t eldv;
7242 uint32_t i;
7243 int len;
7244 int hdmiw_hdmiedid;
7245 int aud_config;
7246 int aud_cntl_st;
7247 int aud_cntrl_st2;
7248 int pipe = to_intel_crtc(crtc)->pipe;
7249
7250 if (HAS_PCH_IBX(connector->dev)) {
7251 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7252 aud_config = IBX_AUD_CFG(pipe);
7253 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7254 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7255 } else if (IS_VALLEYVIEW(connector->dev)) {
7256 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7257 aud_config = VLV_AUD_CFG(pipe);
7258 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7259 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7260 } else {
7261 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7262 aud_config = CPT_AUD_CFG(pipe);
7263 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7264 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7265 }
7266
7267 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7268
7269 if (IS_VALLEYVIEW(connector->dev)) {
7270 struct intel_encoder *intel_encoder;
7271 struct intel_digital_port *intel_dig_port;
7272
7273 intel_encoder = intel_attached_encoder(connector);
7274 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7275 i = intel_dig_port->port;
7276 } else {
7277 i = I915_READ(aud_cntl_st);
7278 i = (i >> 29) & DIP_PORT_SEL_MASK;
7279 /* DIP_Port_Select, 0x1 = PortB */
7280 }
7281
7282 if (!i) {
7283 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7284 /* operate blindly on all ports */
7285 eldv = IBX_ELD_VALIDB;
7286 eldv |= IBX_ELD_VALIDB << 4;
7287 eldv |= IBX_ELD_VALIDB << 8;
7288 } else {
7289 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7290 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7291 }
7292
7293 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7294 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7295 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7296 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7297 } else {
7298 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7299 }
7300
7301 if (intel_eld_uptodate(connector,
7302 aud_cntrl_st2, eldv,
7303 aud_cntl_st, IBX_ELD_ADDRESS,
7304 hdmiw_hdmiedid))
7305 return;
7306
7307 i = I915_READ(aud_cntrl_st2);
7308 i &= ~eldv;
7309 I915_WRITE(aud_cntrl_st2, i);
7310
7311 if (!eld[0])
7312 return;
7313
7314 i = I915_READ(aud_cntl_st);
7315 i &= ~IBX_ELD_ADDRESS;
7316 I915_WRITE(aud_cntl_st, i);
7317
7318 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7319 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7320 for (i = 0; i < len; i++)
7321 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7322
7323 i = I915_READ(aud_cntrl_st2);
7324 i |= eldv;
7325 I915_WRITE(aud_cntrl_st2, i);
7326 }
7327
7328 void intel_write_eld(struct drm_encoder *encoder,
7329 struct drm_display_mode *mode)
7330 {
7331 struct drm_crtc *crtc = encoder->crtc;
7332 struct drm_connector *connector;
7333 struct drm_device *dev = encoder->dev;
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335
7336 connector = drm_select_eld(encoder, mode);
7337 if (!connector)
7338 return;
7339
7340 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7341 connector->base.id,
7342 drm_get_connector_name(connector),
7343 connector->encoder->base.id,
7344 drm_get_encoder_name(connector->encoder));
7345
7346 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7347
7348 if (dev_priv->display.write_eld)
7349 dev_priv->display.write_eld(connector, crtc, mode);
7350 }
7351
7352 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7353 {
7354 struct drm_device *dev = crtc->dev;
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357 bool visible = base != 0;
7358 u32 cntl;
7359
7360 if (intel_crtc->cursor_visible == visible)
7361 return;
7362
7363 cntl = I915_READ(_CURACNTR);
7364 if (visible) {
7365 /* On these chipsets we can only modify the base whilst
7366 * the cursor is disabled.
7367 */
7368 I915_WRITE(_CURABASE, base);
7369
7370 cntl &= ~(CURSOR_FORMAT_MASK);
7371 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7372 cntl |= CURSOR_ENABLE |
7373 CURSOR_GAMMA_ENABLE |
7374 CURSOR_FORMAT_ARGB;
7375 } else
7376 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7377 I915_WRITE(_CURACNTR, cntl);
7378
7379 intel_crtc->cursor_visible = visible;
7380 }
7381
7382 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7383 {
7384 struct drm_device *dev = crtc->dev;
7385 struct drm_i915_private *dev_priv = dev->dev_private;
7386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7387 int pipe = intel_crtc->pipe;
7388 bool visible = base != 0;
7389
7390 if (intel_crtc->cursor_visible != visible) {
7391 uint32_t cntl = I915_READ(CURCNTR(pipe));
7392 if (base) {
7393 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7394 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7395 cntl |= pipe << 28; /* Connect to correct pipe */
7396 } else {
7397 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7398 cntl |= CURSOR_MODE_DISABLE;
7399 }
7400 I915_WRITE(CURCNTR(pipe), cntl);
7401
7402 intel_crtc->cursor_visible = visible;
7403 }
7404 /* and commit changes on next vblank */
7405 POSTING_READ(CURCNTR(pipe));
7406 I915_WRITE(CURBASE(pipe), base);
7407 POSTING_READ(CURBASE(pipe));
7408 }
7409
7410 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7411 {
7412 struct drm_device *dev = crtc->dev;
7413 struct drm_i915_private *dev_priv = dev->dev_private;
7414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415 int pipe = intel_crtc->pipe;
7416 bool visible = base != 0;
7417
7418 if (intel_crtc->cursor_visible != visible) {
7419 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7420 if (base) {
7421 cntl &= ~CURSOR_MODE;
7422 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7423 } else {
7424 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7425 cntl |= CURSOR_MODE_DISABLE;
7426 }
7427 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7428 cntl |= CURSOR_PIPE_CSC_ENABLE;
7429 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7430 }
7431 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7432
7433 intel_crtc->cursor_visible = visible;
7434 }
7435 /* and commit changes on next vblank */
7436 POSTING_READ(CURCNTR_IVB(pipe));
7437 I915_WRITE(CURBASE_IVB(pipe), base);
7438 POSTING_READ(CURBASE_IVB(pipe));
7439 }
7440
7441 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7442 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7443 bool on)
7444 {
7445 struct drm_device *dev = crtc->dev;
7446 struct drm_i915_private *dev_priv = dev->dev_private;
7447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7448 int pipe = intel_crtc->pipe;
7449 int x = intel_crtc->cursor_x;
7450 int y = intel_crtc->cursor_y;
7451 u32 base = 0, pos = 0;
7452 bool visible;
7453
7454 if (on)
7455 base = intel_crtc->cursor_addr;
7456
7457 if (x >= intel_crtc->config.pipe_src_w)
7458 base = 0;
7459
7460 if (y >= intel_crtc->config.pipe_src_h)
7461 base = 0;
7462
7463 if (x < 0) {
7464 if (x + intel_crtc->cursor_width <= 0)
7465 base = 0;
7466
7467 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7468 x = -x;
7469 }
7470 pos |= x << CURSOR_X_SHIFT;
7471
7472 if (y < 0) {
7473 if (y + intel_crtc->cursor_height <= 0)
7474 base = 0;
7475
7476 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7477 y = -y;
7478 }
7479 pos |= y << CURSOR_Y_SHIFT;
7480
7481 visible = base != 0;
7482 if (!visible && !intel_crtc->cursor_visible)
7483 return;
7484
7485 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7486 I915_WRITE(CURPOS_IVB(pipe), pos);
7487 ivb_update_cursor(crtc, base);
7488 } else {
7489 I915_WRITE(CURPOS(pipe), pos);
7490 if (IS_845G(dev) || IS_I865G(dev))
7491 i845_update_cursor(crtc, base);
7492 else
7493 i9xx_update_cursor(crtc, base);
7494 }
7495 }
7496
7497 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7498 struct drm_file *file,
7499 uint32_t handle,
7500 uint32_t width, uint32_t height)
7501 {
7502 struct drm_device *dev = crtc->dev;
7503 struct drm_i915_private *dev_priv = dev->dev_private;
7504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7505 struct drm_i915_gem_object *obj;
7506 uint32_t addr;
7507 int ret;
7508
7509 /* if we want to turn off the cursor ignore width and height */
7510 if (!handle) {
7511 DRM_DEBUG_KMS("cursor off\n");
7512 addr = 0;
7513 obj = NULL;
7514 mutex_lock(&dev->struct_mutex);
7515 goto finish;
7516 }
7517
7518 /* Currently we only support 64x64 cursors */
7519 if (width != 64 || height != 64) {
7520 DRM_ERROR("we currently only support 64x64 cursors\n");
7521 return -EINVAL;
7522 }
7523
7524 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7525 if (&obj->base == NULL)
7526 return -ENOENT;
7527
7528 if (obj->base.size < width * height * 4) {
7529 DRM_ERROR("buffer is to small\n");
7530 ret = -ENOMEM;
7531 goto fail;
7532 }
7533
7534 /* we only need to pin inside GTT if cursor is non-phy */
7535 mutex_lock(&dev->struct_mutex);
7536 if (!dev_priv->info->cursor_needs_physical) {
7537 unsigned alignment;
7538
7539 if (obj->tiling_mode) {
7540 DRM_ERROR("cursor cannot be tiled\n");
7541 ret = -EINVAL;
7542 goto fail_locked;
7543 }
7544
7545 /* Note that the w/a also requires 2 PTE of padding following
7546 * the bo. We currently fill all unused PTE with the shadow
7547 * page and so we should always have valid PTE following the
7548 * cursor preventing the VT-d warning.
7549 */
7550 alignment = 0;
7551 if (need_vtd_wa(dev))
7552 alignment = 64*1024;
7553
7554 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7555 if (ret) {
7556 DRM_ERROR("failed to move cursor bo into the GTT\n");
7557 goto fail_locked;
7558 }
7559
7560 ret = i915_gem_object_put_fence(obj);
7561 if (ret) {
7562 DRM_ERROR("failed to release fence for cursor");
7563 goto fail_unpin;
7564 }
7565
7566 addr = i915_gem_obj_ggtt_offset(obj);
7567 } else {
7568 int align = IS_I830(dev) ? 16 * 1024 : 256;
7569 ret = i915_gem_attach_phys_object(dev, obj,
7570 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7571 align);
7572 if (ret) {
7573 DRM_ERROR("failed to attach phys object\n");
7574 goto fail_locked;
7575 }
7576 addr = obj->phys_obj->handle->busaddr;
7577 }
7578
7579 if (IS_GEN2(dev))
7580 I915_WRITE(CURSIZE, (height << 12) | width);
7581
7582 finish:
7583 if (intel_crtc->cursor_bo) {
7584 if (dev_priv->info->cursor_needs_physical) {
7585 if (intel_crtc->cursor_bo != obj)
7586 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7587 } else
7588 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7589 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7590 }
7591
7592 mutex_unlock(&dev->struct_mutex);
7593
7594 intel_crtc->cursor_addr = addr;
7595 intel_crtc->cursor_bo = obj;
7596 intel_crtc->cursor_width = width;
7597 intel_crtc->cursor_height = height;
7598
7599 if (intel_crtc->active)
7600 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7601
7602 return 0;
7603 fail_unpin:
7604 i915_gem_object_unpin_from_display_plane(obj);
7605 fail_locked:
7606 mutex_unlock(&dev->struct_mutex);
7607 fail:
7608 drm_gem_object_unreference_unlocked(&obj->base);
7609 return ret;
7610 }
7611
7612 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7613 {
7614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7615
7616 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7617 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7618
7619 if (intel_crtc->active)
7620 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7621
7622 return 0;
7623 }
7624
7625 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7626 u16 *blue, uint32_t start, uint32_t size)
7627 {
7628 int end = (start + size > 256) ? 256 : start + size, i;
7629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7630
7631 for (i = start; i < end; i++) {
7632 intel_crtc->lut_r[i] = red[i] >> 8;
7633 intel_crtc->lut_g[i] = green[i] >> 8;
7634 intel_crtc->lut_b[i] = blue[i] >> 8;
7635 }
7636
7637 intel_crtc_load_lut(crtc);
7638 }
7639
7640 /* VESA 640x480x72Hz mode to set on the pipe */
7641 static struct drm_display_mode load_detect_mode = {
7642 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7643 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7644 };
7645
7646 static struct drm_framebuffer *
7647 intel_framebuffer_create(struct drm_device *dev,
7648 struct drm_mode_fb_cmd2 *mode_cmd,
7649 struct drm_i915_gem_object *obj)
7650 {
7651 struct intel_framebuffer *intel_fb;
7652 int ret;
7653
7654 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7655 if (!intel_fb) {
7656 drm_gem_object_unreference_unlocked(&obj->base);
7657 return ERR_PTR(-ENOMEM);
7658 }
7659
7660 ret = i915_mutex_lock_interruptible(dev);
7661 if (ret)
7662 goto err;
7663
7664 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7665 mutex_unlock(&dev->struct_mutex);
7666 if (ret)
7667 goto err;
7668
7669 return &intel_fb->base;
7670 err:
7671 drm_gem_object_unreference_unlocked(&obj->base);
7672 kfree(intel_fb);
7673
7674 return ERR_PTR(ret);
7675 }
7676
7677 static u32
7678 intel_framebuffer_pitch_for_width(int width, int bpp)
7679 {
7680 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7681 return ALIGN(pitch, 64);
7682 }
7683
7684 static u32
7685 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7686 {
7687 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7688 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7689 }
7690
7691 static struct drm_framebuffer *
7692 intel_framebuffer_create_for_mode(struct drm_device *dev,
7693 struct drm_display_mode *mode,
7694 int depth, int bpp)
7695 {
7696 struct drm_i915_gem_object *obj;
7697 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7698
7699 obj = i915_gem_alloc_object(dev,
7700 intel_framebuffer_size_for_mode(mode, bpp));
7701 if (obj == NULL)
7702 return ERR_PTR(-ENOMEM);
7703
7704 mode_cmd.width = mode->hdisplay;
7705 mode_cmd.height = mode->vdisplay;
7706 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7707 bpp);
7708 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7709
7710 return intel_framebuffer_create(dev, &mode_cmd, obj);
7711 }
7712
7713 static struct drm_framebuffer *
7714 mode_fits_in_fbdev(struct drm_device *dev,
7715 struct drm_display_mode *mode)
7716 {
7717 #ifdef CONFIG_DRM_I915_FBDEV
7718 struct drm_i915_private *dev_priv = dev->dev_private;
7719 struct drm_i915_gem_object *obj;
7720 struct drm_framebuffer *fb;
7721
7722 if (dev_priv->fbdev == NULL)
7723 return NULL;
7724
7725 obj = dev_priv->fbdev->ifb.obj;
7726 if (obj == NULL)
7727 return NULL;
7728
7729 fb = &dev_priv->fbdev->ifb.base;
7730 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7731 fb->bits_per_pixel))
7732 return NULL;
7733
7734 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7735 return NULL;
7736
7737 return fb;
7738 #else
7739 return NULL;
7740 #endif
7741 }
7742
7743 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7744 struct drm_display_mode *mode,
7745 struct intel_load_detect_pipe *old)
7746 {
7747 struct intel_crtc *intel_crtc;
7748 struct intel_encoder *intel_encoder =
7749 intel_attached_encoder(connector);
7750 struct drm_crtc *possible_crtc;
7751 struct drm_encoder *encoder = &intel_encoder->base;
7752 struct drm_crtc *crtc = NULL;
7753 struct drm_device *dev = encoder->dev;
7754 struct drm_framebuffer *fb;
7755 int i = -1;
7756
7757 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7758 connector->base.id, drm_get_connector_name(connector),
7759 encoder->base.id, drm_get_encoder_name(encoder));
7760
7761 /*
7762 * Algorithm gets a little messy:
7763 *
7764 * - if the connector already has an assigned crtc, use it (but make
7765 * sure it's on first)
7766 *
7767 * - try to find the first unused crtc that can drive this connector,
7768 * and use that if we find one
7769 */
7770
7771 /* See if we already have a CRTC for this connector */
7772 if (encoder->crtc) {
7773 crtc = encoder->crtc;
7774
7775 mutex_lock(&crtc->mutex);
7776
7777 old->dpms_mode = connector->dpms;
7778 old->load_detect_temp = false;
7779
7780 /* Make sure the crtc and connector are running */
7781 if (connector->dpms != DRM_MODE_DPMS_ON)
7782 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7783
7784 return true;
7785 }
7786
7787 /* Find an unused one (if possible) */
7788 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7789 i++;
7790 if (!(encoder->possible_crtcs & (1 << i)))
7791 continue;
7792 if (!possible_crtc->enabled) {
7793 crtc = possible_crtc;
7794 break;
7795 }
7796 }
7797
7798 /*
7799 * If we didn't find an unused CRTC, don't use any.
7800 */
7801 if (!crtc) {
7802 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7803 return false;
7804 }
7805
7806 mutex_lock(&crtc->mutex);
7807 intel_encoder->new_crtc = to_intel_crtc(crtc);
7808 to_intel_connector(connector)->new_encoder = intel_encoder;
7809
7810 intel_crtc = to_intel_crtc(crtc);
7811 old->dpms_mode = connector->dpms;
7812 old->load_detect_temp = true;
7813 old->release_fb = NULL;
7814
7815 if (!mode)
7816 mode = &load_detect_mode;
7817
7818 /* We need a framebuffer large enough to accommodate all accesses
7819 * that the plane may generate whilst we perform load detection.
7820 * We can not rely on the fbcon either being present (we get called
7821 * during its initialisation to detect all boot displays, or it may
7822 * not even exist) or that it is large enough to satisfy the
7823 * requested mode.
7824 */
7825 fb = mode_fits_in_fbdev(dev, mode);
7826 if (fb == NULL) {
7827 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7828 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7829 old->release_fb = fb;
7830 } else
7831 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7832 if (IS_ERR(fb)) {
7833 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7834 mutex_unlock(&crtc->mutex);
7835 return false;
7836 }
7837
7838 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7839 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7840 if (old->release_fb)
7841 old->release_fb->funcs->destroy(old->release_fb);
7842 mutex_unlock(&crtc->mutex);
7843 return false;
7844 }
7845
7846 /* let the connector get through one full cycle before testing */
7847 intel_wait_for_vblank(dev, intel_crtc->pipe);
7848 return true;
7849 }
7850
7851 void intel_release_load_detect_pipe(struct drm_connector *connector,
7852 struct intel_load_detect_pipe *old)
7853 {
7854 struct intel_encoder *intel_encoder =
7855 intel_attached_encoder(connector);
7856 struct drm_encoder *encoder = &intel_encoder->base;
7857 struct drm_crtc *crtc = encoder->crtc;
7858
7859 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7860 connector->base.id, drm_get_connector_name(connector),
7861 encoder->base.id, drm_get_encoder_name(encoder));
7862
7863 if (old->load_detect_temp) {
7864 to_intel_connector(connector)->new_encoder = NULL;
7865 intel_encoder->new_crtc = NULL;
7866 intel_set_mode(crtc, NULL, 0, 0, NULL);
7867
7868 if (old->release_fb) {
7869 drm_framebuffer_unregister_private(old->release_fb);
7870 drm_framebuffer_unreference(old->release_fb);
7871 }
7872
7873 mutex_unlock(&crtc->mutex);
7874 return;
7875 }
7876
7877 /* Switch crtc and encoder back off if necessary */
7878 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7879 connector->funcs->dpms(connector, old->dpms_mode);
7880
7881 mutex_unlock(&crtc->mutex);
7882 }
7883
7884 static int i9xx_pll_refclk(struct drm_device *dev,
7885 const struct intel_crtc_config *pipe_config)
7886 {
7887 struct drm_i915_private *dev_priv = dev->dev_private;
7888 u32 dpll = pipe_config->dpll_hw_state.dpll;
7889
7890 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7891 return dev_priv->vbt.lvds_ssc_freq;
7892 else if (HAS_PCH_SPLIT(dev))
7893 return 120000;
7894 else if (!IS_GEN2(dev))
7895 return 96000;
7896 else
7897 return 48000;
7898 }
7899
7900 /* Returns the clock of the currently programmed mode of the given pipe. */
7901 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7902 struct intel_crtc_config *pipe_config)
7903 {
7904 struct drm_device *dev = crtc->base.dev;
7905 struct drm_i915_private *dev_priv = dev->dev_private;
7906 int pipe = pipe_config->cpu_transcoder;
7907 u32 dpll = pipe_config->dpll_hw_state.dpll;
7908 u32 fp;
7909 intel_clock_t clock;
7910 int refclk = i9xx_pll_refclk(dev, pipe_config);
7911
7912 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7913 fp = pipe_config->dpll_hw_state.fp0;
7914 else
7915 fp = pipe_config->dpll_hw_state.fp1;
7916
7917 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7918 if (IS_PINEVIEW(dev)) {
7919 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7920 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7921 } else {
7922 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7923 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7924 }
7925
7926 if (!IS_GEN2(dev)) {
7927 if (IS_PINEVIEW(dev))
7928 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7929 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7930 else
7931 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7932 DPLL_FPA01_P1_POST_DIV_SHIFT);
7933
7934 switch (dpll & DPLL_MODE_MASK) {
7935 case DPLLB_MODE_DAC_SERIAL:
7936 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7937 5 : 10;
7938 break;
7939 case DPLLB_MODE_LVDS:
7940 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7941 7 : 14;
7942 break;
7943 default:
7944 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7945 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7946 return;
7947 }
7948
7949 if (IS_PINEVIEW(dev))
7950 pineview_clock(refclk, &clock);
7951 else
7952 i9xx_clock(refclk, &clock);
7953 } else {
7954 u32 lvds = I915_READ(LVDS);
7955 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7956
7957 if (is_lvds) {
7958 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7959 DPLL_FPA01_P1_POST_DIV_SHIFT);
7960
7961 if (lvds & LVDS_CLKB_POWER_UP)
7962 clock.p2 = 7;
7963 else
7964 clock.p2 = 14;
7965 } else {
7966 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7967 clock.p1 = 2;
7968 else {
7969 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7970 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7971 }
7972 if (dpll & PLL_P2_DIVIDE_BY_4)
7973 clock.p2 = 4;
7974 else
7975 clock.p2 = 2;
7976 }
7977
7978 i9xx_clock(refclk, &clock);
7979 }
7980
7981 /*
7982 * This value includes pixel_multiplier. We will use
7983 * port_clock to compute adjusted_mode.crtc_clock in the
7984 * encoder's get_config() function.
7985 */
7986 pipe_config->port_clock = clock.dot;
7987 }
7988
7989 int intel_dotclock_calculate(int link_freq,
7990 const struct intel_link_m_n *m_n)
7991 {
7992 /*
7993 * The calculation for the data clock is:
7994 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7995 * But we want to avoid losing precison if possible, so:
7996 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7997 *
7998 * and the link clock is simpler:
7999 * link_clock = (m * link_clock) / n
8000 */
8001
8002 if (!m_n->link_n)
8003 return 0;
8004
8005 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8006 }
8007
8008 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8009 struct intel_crtc_config *pipe_config)
8010 {
8011 struct drm_device *dev = crtc->base.dev;
8012
8013 /* read out port_clock from the DPLL */
8014 i9xx_crtc_clock_get(crtc, pipe_config);
8015
8016 /*
8017 * This value does not include pixel_multiplier.
8018 * We will check that port_clock and adjusted_mode.crtc_clock
8019 * agree once we know their relationship in the encoder's
8020 * get_config() function.
8021 */
8022 pipe_config->adjusted_mode.crtc_clock =
8023 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8024 &pipe_config->fdi_m_n);
8025 }
8026
8027 /** Returns the currently programmed mode of the given pipe. */
8028 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8029 struct drm_crtc *crtc)
8030 {
8031 struct drm_i915_private *dev_priv = dev->dev_private;
8032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8033 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8034 struct drm_display_mode *mode;
8035 struct intel_crtc_config pipe_config;
8036 int htot = I915_READ(HTOTAL(cpu_transcoder));
8037 int hsync = I915_READ(HSYNC(cpu_transcoder));
8038 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8039 int vsync = I915_READ(VSYNC(cpu_transcoder));
8040 enum pipe pipe = intel_crtc->pipe;
8041
8042 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8043 if (!mode)
8044 return NULL;
8045
8046 /*
8047 * Construct a pipe_config sufficient for getting the clock info
8048 * back out of crtc_clock_get.
8049 *
8050 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8051 * to use a real value here instead.
8052 */
8053 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8054 pipe_config.pixel_multiplier = 1;
8055 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8056 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8057 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8058 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8059
8060 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8061 mode->hdisplay = (htot & 0xffff) + 1;
8062 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8063 mode->hsync_start = (hsync & 0xffff) + 1;
8064 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8065 mode->vdisplay = (vtot & 0xffff) + 1;
8066 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8067 mode->vsync_start = (vsync & 0xffff) + 1;
8068 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8069
8070 drm_mode_set_name(mode);
8071
8072 return mode;
8073 }
8074
8075 static void intel_increase_pllclock(struct drm_crtc *crtc)
8076 {
8077 struct drm_device *dev = crtc->dev;
8078 drm_i915_private_t *dev_priv = dev->dev_private;
8079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8080 int pipe = intel_crtc->pipe;
8081 int dpll_reg = DPLL(pipe);
8082 int dpll;
8083
8084 if (HAS_PCH_SPLIT(dev))
8085 return;
8086
8087 if (!dev_priv->lvds_downclock_avail)
8088 return;
8089
8090 dpll = I915_READ(dpll_reg);
8091 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8092 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8093
8094 assert_panel_unlocked(dev_priv, pipe);
8095
8096 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8097 I915_WRITE(dpll_reg, dpll);
8098 intel_wait_for_vblank(dev, pipe);
8099
8100 dpll = I915_READ(dpll_reg);
8101 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8102 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8103 }
8104 }
8105
8106 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8107 {
8108 struct drm_device *dev = crtc->dev;
8109 drm_i915_private_t *dev_priv = dev->dev_private;
8110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8111
8112 if (HAS_PCH_SPLIT(dev))
8113 return;
8114
8115 if (!dev_priv->lvds_downclock_avail)
8116 return;
8117
8118 /*
8119 * Since this is called by a timer, we should never get here in
8120 * the manual case.
8121 */
8122 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8123 int pipe = intel_crtc->pipe;
8124 int dpll_reg = DPLL(pipe);
8125 int dpll;
8126
8127 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8128
8129 assert_panel_unlocked(dev_priv, pipe);
8130
8131 dpll = I915_READ(dpll_reg);
8132 dpll |= DISPLAY_RATE_SELECT_FPA1;
8133 I915_WRITE(dpll_reg, dpll);
8134 intel_wait_for_vblank(dev, pipe);
8135 dpll = I915_READ(dpll_reg);
8136 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8137 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8138 }
8139
8140 }
8141
8142 void intel_mark_busy(struct drm_device *dev)
8143 {
8144 struct drm_i915_private *dev_priv = dev->dev_private;
8145
8146 hsw_package_c8_gpu_busy(dev_priv);
8147 i915_update_gfx_val(dev_priv);
8148 }
8149
8150 void intel_mark_idle(struct drm_device *dev)
8151 {
8152 struct drm_i915_private *dev_priv = dev->dev_private;
8153 struct drm_crtc *crtc;
8154
8155 hsw_package_c8_gpu_idle(dev_priv);
8156
8157 if (!i915_powersave)
8158 return;
8159
8160 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8161 if (!crtc->fb)
8162 continue;
8163
8164 intel_decrease_pllclock(crtc);
8165 }
8166
8167 if (dev_priv->info->gen >= 6)
8168 gen6_rps_idle(dev->dev_private);
8169 }
8170
8171 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8172 struct intel_ring_buffer *ring)
8173 {
8174 struct drm_device *dev = obj->base.dev;
8175 struct drm_crtc *crtc;
8176
8177 if (!i915_powersave)
8178 return;
8179
8180 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8181 if (!crtc->fb)
8182 continue;
8183
8184 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8185 continue;
8186
8187 intel_increase_pllclock(crtc);
8188 if (ring && intel_fbc_enabled(dev))
8189 ring->fbc_dirty = true;
8190 }
8191 }
8192
8193 static void intel_crtc_destroy(struct drm_crtc *crtc)
8194 {
8195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8196 struct drm_device *dev = crtc->dev;
8197 struct intel_unpin_work *work;
8198 unsigned long flags;
8199
8200 spin_lock_irqsave(&dev->event_lock, flags);
8201 work = intel_crtc->unpin_work;
8202 intel_crtc->unpin_work = NULL;
8203 spin_unlock_irqrestore(&dev->event_lock, flags);
8204
8205 if (work) {
8206 cancel_work_sync(&work->work);
8207 kfree(work);
8208 }
8209
8210 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8211
8212 drm_crtc_cleanup(crtc);
8213
8214 kfree(intel_crtc);
8215 }
8216
8217 static void intel_unpin_work_fn(struct work_struct *__work)
8218 {
8219 struct intel_unpin_work *work =
8220 container_of(__work, struct intel_unpin_work, work);
8221 struct drm_device *dev = work->crtc->dev;
8222
8223 mutex_lock(&dev->struct_mutex);
8224 intel_unpin_fb_obj(work->old_fb_obj);
8225 drm_gem_object_unreference(&work->pending_flip_obj->base);
8226 drm_gem_object_unreference(&work->old_fb_obj->base);
8227
8228 intel_update_fbc(dev);
8229 mutex_unlock(&dev->struct_mutex);
8230
8231 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8232 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8233
8234 kfree(work);
8235 }
8236
8237 static void do_intel_finish_page_flip(struct drm_device *dev,
8238 struct drm_crtc *crtc)
8239 {
8240 drm_i915_private_t *dev_priv = dev->dev_private;
8241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8242 struct intel_unpin_work *work;
8243 unsigned long flags;
8244
8245 /* Ignore early vblank irqs */
8246 if (intel_crtc == NULL)
8247 return;
8248
8249 spin_lock_irqsave(&dev->event_lock, flags);
8250 work = intel_crtc->unpin_work;
8251
8252 /* Ensure we don't miss a work->pending update ... */
8253 smp_rmb();
8254
8255 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8256 spin_unlock_irqrestore(&dev->event_lock, flags);
8257 return;
8258 }
8259
8260 /* and that the unpin work is consistent wrt ->pending. */
8261 smp_rmb();
8262
8263 intel_crtc->unpin_work = NULL;
8264
8265 if (work->event)
8266 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8267
8268 drm_vblank_put(dev, intel_crtc->pipe);
8269
8270 spin_unlock_irqrestore(&dev->event_lock, flags);
8271
8272 wake_up_all(&dev_priv->pending_flip_queue);
8273
8274 queue_work(dev_priv->wq, &work->work);
8275
8276 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8277 }
8278
8279 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8280 {
8281 drm_i915_private_t *dev_priv = dev->dev_private;
8282 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8283
8284 do_intel_finish_page_flip(dev, crtc);
8285 }
8286
8287 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8288 {
8289 drm_i915_private_t *dev_priv = dev->dev_private;
8290 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8291
8292 do_intel_finish_page_flip(dev, crtc);
8293 }
8294
8295 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8296 {
8297 drm_i915_private_t *dev_priv = dev->dev_private;
8298 struct intel_crtc *intel_crtc =
8299 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8300 unsigned long flags;
8301
8302 /* NB: An MMIO update of the plane base pointer will also
8303 * generate a page-flip completion irq, i.e. every modeset
8304 * is also accompanied by a spurious intel_prepare_page_flip().
8305 */
8306 spin_lock_irqsave(&dev->event_lock, flags);
8307 if (intel_crtc->unpin_work)
8308 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8309 spin_unlock_irqrestore(&dev->event_lock, flags);
8310 }
8311
8312 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8313 {
8314 /* Ensure that the work item is consistent when activating it ... */
8315 smp_wmb();
8316 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8317 /* and that it is marked active as soon as the irq could fire. */
8318 smp_wmb();
8319 }
8320
8321 static int intel_gen2_queue_flip(struct drm_device *dev,
8322 struct drm_crtc *crtc,
8323 struct drm_framebuffer *fb,
8324 struct drm_i915_gem_object *obj,
8325 uint32_t flags)
8326 {
8327 struct drm_i915_private *dev_priv = dev->dev_private;
8328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8329 u32 flip_mask;
8330 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8331 int ret;
8332
8333 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8334 if (ret)
8335 goto err;
8336
8337 ret = intel_ring_begin(ring, 6);
8338 if (ret)
8339 goto err_unpin;
8340
8341 /* Can't queue multiple flips, so wait for the previous
8342 * one to finish before executing the next.
8343 */
8344 if (intel_crtc->plane)
8345 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8346 else
8347 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8348 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8349 intel_ring_emit(ring, MI_NOOP);
8350 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8351 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8352 intel_ring_emit(ring, fb->pitches[0]);
8353 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8354 intel_ring_emit(ring, 0); /* aux display base address, unused */
8355
8356 intel_mark_page_flip_active(intel_crtc);
8357 __intel_ring_advance(ring);
8358 return 0;
8359
8360 err_unpin:
8361 intel_unpin_fb_obj(obj);
8362 err:
8363 return ret;
8364 }
8365
8366 static int intel_gen3_queue_flip(struct drm_device *dev,
8367 struct drm_crtc *crtc,
8368 struct drm_framebuffer *fb,
8369 struct drm_i915_gem_object *obj,
8370 uint32_t flags)
8371 {
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8374 u32 flip_mask;
8375 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8376 int ret;
8377
8378 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8379 if (ret)
8380 goto err;
8381
8382 ret = intel_ring_begin(ring, 6);
8383 if (ret)
8384 goto err_unpin;
8385
8386 if (intel_crtc->plane)
8387 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8388 else
8389 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8390 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8391 intel_ring_emit(ring, MI_NOOP);
8392 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8393 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8394 intel_ring_emit(ring, fb->pitches[0]);
8395 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8396 intel_ring_emit(ring, MI_NOOP);
8397
8398 intel_mark_page_flip_active(intel_crtc);
8399 __intel_ring_advance(ring);
8400 return 0;
8401
8402 err_unpin:
8403 intel_unpin_fb_obj(obj);
8404 err:
8405 return ret;
8406 }
8407
8408 static int intel_gen4_queue_flip(struct drm_device *dev,
8409 struct drm_crtc *crtc,
8410 struct drm_framebuffer *fb,
8411 struct drm_i915_gem_object *obj,
8412 uint32_t flags)
8413 {
8414 struct drm_i915_private *dev_priv = dev->dev_private;
8415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8416 uint32_t pf, pipesrc;
8417 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8418 int ret;
8419
8420 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8421 if (ret)
8422 goto err;
8423
8424 ret = intel_ring_begin(ring, 4);
8425 if (ret)
8426 goto err_unpin;
8427
8428 /* i965+ uses the linear or tiled offsets from the
8429 * Display Registers (which do not change across a page-flip)
8430 * so we need only reprogram the base address.
8431 */
8432 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8433 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8434 intel_ring_emit(ring, fb->pitches[0]);
8435 intel_ring_emit(ring,
8436 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8437 obj->tiling_mode);
8438
8439 /* XXX Enabling the panel-fitter across page-flip is so far
8440 * untested on non-native modes, so ignore it for now.
8441 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8442 */
8443 pf = 0;
8444 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8445 intel_ring_emit(ring, pf | pipesrc);
8446
8447 intel_mark_page_flip_active(intel_crtc);
8448 __intel_ring_advance(ring);
8449 return 0;
8450
8451 err_unpin:
8452 intel_unpin_fb_obj(obj);
8453 err:
8454 return ret;
8455 }
8456
8457 static int intel_gen6_queue_flip(struct drm_device *dev,
8458 struct drm_crtc *crtc,
8459 struct drm_framebuffer *fb,
8460 struct drm_i915_gem_object *obj,
8461 uint32_t flags)
8462 {
8463 struct drm_i915_private *dev_priv = dev->dev_private;
8464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8465 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8466 uint32_t pf, pipesrc;
8467 int ret;
8468
8469 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8470 if (ret)
8471 goto err;
8472
8473 ret = intel_ring_begin(ring, 4);
8474 if (ret)
8475 goto err_unpin;
8476
8477 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8478 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8479 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8480 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8481
8482 /* Contrary to the suggestions in the documentation,
8483 * "Enable Panel Fitter" does not seem to be required when page
8484 * flipping with a non-native mode, and worse causes a normal
8485 * modeset to fail.
8486 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8487 */
8488 pf = 0;
8489 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8490 intel_ring_emit(ring, pf | pipesrc);
8491
8492 intel_mark_page_flip_active(intel_crtc);
8493 __intel_ring_advance(ring);
8494 return 0;
8495
8496 err_unpin:
8497 intel_unpin_fb_obj(obj);
8498 err:
8499 return ret;
8500 }
8501
8502 static int intel_gen7_queue_flip(struct drm_device *dev,
8503 struct drm_crtc *crtc,
8504 struct drm_framebuffer *fb,
8505 struct drm_i915_gem_object *obj,
8506 uint32_t flags)
8507 {
8508 struct drm_i915_private *dev_priv = dev->dev_private;
8509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8510 struct intel_ring_buffer *ring;
8511 uint32_t plane_bit = 0;
8512 int len, ret;
8513
8514 ring = obj->ring;
8515 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8516 ring = &dev_priv->ring[BCS];
8517
8518 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8519 if (ret)
8520 goto err;
8521
8522 switch(intel_crtc->plane) {
8523 case PLANE_A:
8524 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8525 break;
8526 case PLANE_B:
8527 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8528 break;
8529 case PLANE_C:
8530 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8531 break;
8532 default:
8533 WARN_ONCE(1, "unknown plane in flip command\n");
8534 ret = -ENODEV;
8535 goto err_unpin;
8536 }
8537
8538 len = 4;
8539 if (ring->id == RCS)
8540 len += 6;
8541
8542 ret = intel_ring_begin(ring, len);
8543 if (ret)
8544 goto err_unpin;
8545
8546 /* Unmask the flip-done completion message. Note that the bspec says that
8547 * we should do this for both the BCS and RCS, and that we must not unmask
8548 * more than one flip event at any time (or ensure that one flip message
8549 * can be sent by waiting for flip-done prior to queueing new flips).
8550 * Experimentation says that BCS works despite DERRMR masking all
8551 * flip-done completion events and that unmasking all planes at once
8552 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8553 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8554 */
8555 if (ring->id == RCS) {
8556 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8557 intel_ring_emit(ring, DERRMR);
8558 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8559 DERRMR_PIPEB_PRI_FLIP_DONE |
8560 DERRMR_PIPEC_PRI_FLIP_DONE));
8561 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8562 MI_SRM_LRM_GLOBAL_GTT);
8563 intel_ring_emit(ring, DERRMR);
8564 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8565 }
8566
8567 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8568 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8569 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8570 intel_ring_emit(ring, (MI_NOOP));
8571
8572 intel_mark_page_flip_active(intel_crtc);
8573 __intel_ring_advance(ring);
8574 return 0;
8575
8576 err_unpin:
8577 intel_unpin_fb_obj(obj);
8578 err:
8579 return ret;
8580 }
8581
8582 static int intel_default_queue_flip(struct drm_device *dev,
8583 struct drm_crtc *crtc,
8584 struct drm_framebuffer *fb,
8585 struct drm_i915_gem_object *obj,
8586 uint32_t flags)
8587 {
8588 return -ENODEV;
8589 }
8590
8591 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8592 struct drm_framebuffer *fb,
8593 struct drm_pending_vblank_event *event,
8594 uint32_t page_flip_flags)
8595 {
8596 struct drm_device *dev = crtc->dev;
8597 struct drm_i915_private *dev_priv = dev->dev_private;
8598 struct drm_framebuffer *old_fb = crtc->fb;
8599 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8601 struct intel_unpin_work *work;
8602 unsigned long flags;
8603 int ret;
8604
8605 /* Can't change pixel format via MI display flips. */
8606 if (fb->pixel_format != crtc->fb->pixel_format)
8607 return -EINVAL;
8608
8609 /*
8610 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8611 * Note that pitch changes could also affect these register.
8612 */
8613 if (INTEL_INFO(dev)->gen > 3 &&
8614 (fb->offsets[0] != crtc->fb->offsets[0] ||
8615 fb->pitches[0] != crtc->fb->pitches[0]))
8616 return -EINVAL;
8617
8618 work = kzalloc(sizeof(*work), GFP_KERNEL);
8619 if (work == NULL)
8620 return -ENOMEM;
8621
8622 work->event = event;
8623 work->crtc = crtc;
8624 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8625 INIT_WORK(&work->work, intel_unpin_work_fn);
8626
8627 ret = drm_vblank_get(dev, intel_crtc->pipe);
8628 if (ret)
8629 goto free_work;
8630
8631 /* We borrow the event spin lock for protecting unpin_work */
8632 spin_lock_irqsave(&dev->event_lock, flags);
8633 if (intel_crtc->unpin_work) {
8634 spin_unlock_irqrestore(&dev->event_lock, flags);
8635 kfree(work);
8636 drm_vblank_put(dev, intel_crtc->pipe);
8637
8638 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8639 return -EBUSY;
8640 }
8641 intel_crtc->unpin_work = work;
8642 spin_unlock_irqrestore(&dev->event_lock, flags);
8643
8644 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8645 flush_workqueue(dev_priv->wq);
8646
8647 ret = i915_mutex_lock_interruptible(dev);
8648 if (ret)
8649 goto cleanup;
8650
8651 /* Reference the objects for the scheduled work. */
8652 drm_gem_object_reference(&work->old_fb_obj->base);
8653 drm_gem_object_reference(&obj->base);
8654
8655 crtc->fb = fb;
8656
8657 work->pending_flip_obj = obj;
8658
8659 work->enable_stall_check = true;
8660
8661 atomic_inc(&intel_crtc->unpin_work_count);
8662 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8663
8664 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8665 if (ret)
8666 goto cleanup_pending;
8667
8668 intel_disable_fbc(dev);
8669 intel_mark_fb_busy(obj, NULL);
8670 mutex_unlock(&dev->struct_mutex);
8671
8672 trace_i915_flip_request(intel_crtc->plane, obj);
8673
8674 return 0;
8675
8676 cleanup_pending:
8677 atomic_dec(&intel_crtc->unpin_work_count);
8678 crtc->fb = old_fb;
8679 drm_gem_object_unreference(&work->old_fb_obj->base);
8680 drm_gem_object_unreference(&obj->base);
8681 mutex_unlock(&dev->struct_mutex);
8682
8683 cleanup:
8684 spin_lock_irqsave(&dev->event_lock, flags);
8685 intel_crtc->unpin_work = NULL;
8686 spin_unlock_irqrestore(&dev->event_lock, flags);
8687
8688 drm_vblank_put(dev, intel_crtc->pipe);
8689 free_work:
8690 kfree(work);
8691
8692 return ret;
8693 }
8694
8695 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8696 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8697 .load_lut = intel_crtc_load_lut,
8698 };
8699
8700 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8701 struct drm_crtc *crtc)
8702 {
8703 struct drm_device *dev;
8704 struct drm_crtc *tmp;
8705 int crtc_mask = 1;
8706
8707 WARN(!crtc, "checking null crtc?\n");
8708
8709 dev = crtc->dev;
8710
8711 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8712 if (tmp == crtc)
8713 break;
8714 crtc_mask <<= 1;
8715 }
8716
8717 if (encoder->possible_crtcs & crtc_mask)
8718 return true;
8719 return false;
8720 }
8721
8722 /**
8723 * intel_modeset_update_staged_output_state
8724 *
8725 * Updates the staged output configuration state, e.g. after we've read out the
8726 * current hw state.
8727 */
8728 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8729 {
8730 struct intel_encoder *encoder;
8731 struct intel_connector *connector;
8732
8733 list_for_each_entry(connector, &dev->mode_config.connector_list,
8734 base.head) {
8735 connector->new_encoder =
8736 to_intel_encoder(connector->base.encoder);
8737 }
8738
8739 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8740 base.head) {
8741 encoder->new_crtc =
8742 to_intel_crtc(encoder->base.crtc);
8743 }
8744 }
8745
8746 /**
8747 * intel_modeset_commit_output_state
8748 *
8749 * This function copies the stage display pipe configuration to the real one.
8750 */
8751 static void intel_modeset_commit_output_state(struct drm_device *dev)
8752 {
8753 struct intel_encoder *encoder;
8754 struct intel_connector *connector;
8755
8756 list_for_each_entry(connector, &dev->mode_config.connector_list,
8757 base.head) {
8758 connector->base.encoder = &connector->new_encoder->base;
8759 }
8760
8761 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8762 base.head) {
8763 encoder->base.crtc = &encoder->new_crtc->base;
8764 }
8765 }
8766
8767 static void
8768 connected_sink_compute_bpp(struct intel_connector * connector,
8769 struct intel_crtc_config *pipe_config)
8770 {
8771 int bpp = pipe_config->pipe_bpp;
8772
8773 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8774 connector->base.base.id,
8775 drm_get_connector_name(&connector->base));
8776
8777 /* Don't use an invalid EDID bpc value */
8778 if (connector->base.display_info.bpc &&
8779 connector->base.display_info.bpc * 3 < bpp) {
8780 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8781 bpp, connector->base.display_info.bpc*3);
8782 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8783 }
8784
8785 /* Clamp bpp to 8 on screens without EDID 1.4 */
8786 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8787 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8788 bpp);
8789 pipe_config->pipe_bpp = 24;
8790 }
8791 }
8792
8793 static int
8794 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8795 struct drm_framebuffer *fb,
8796 struct intel_crtc_config *pipe_config)
8797 {
8798 struct drm_device *dev = crtc->base.dev;
8799 struct intel_connector *connector;
8800 int bpp;
8801
8802 switch (fb->pixel_format) {
8803 case DRM_FORMAT_C8:
8804 bpp = 8*3; /* since we go through a colormap */
8805 break;
8806 case DRM_FORMAT_XRGB1555:
8807 case DRM_FORMAT_ARGB1555:
8808 /* checked in intel_framebuffer_init already */
8809 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8810 return -EINVAL;
8811 case DRM_FORMAT_RGB565:
8812 bpp = 6*3; /* min is 18bpp */
8813 break;
8814 case DRM_FORMAT_XBGR8888:
8815 case DRM_FORMAT_ABGR8888:
8816 /* checked in intel_framebuffer_init already */
8817 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8818 return -EINVAL;
8819 case DRM_FORMAT_XRGB8888:
8820 case DRM_FORMAT_ARGB8888:
8821 bpp = 8*3;
8822 break;
8823 case DRM_FORMAT_XRGB2101010:
8824 case DRM_FORMAT_ARGB2101010:
8825 case DRM_FORMAT_XBGR2101010:
8826 case DRM_FORMAT_ABGR2101010:
8827 /* checked in intel_framebuffer_init already */
8828 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8829 return -EINVAL;
8830 bpp = 10*3;
8831 break;
8832 /* TODO: gen4+ supports 16 bpc floating point, too. */
8833 default:
8834 DRM_DEBUG_KMS("unsupported depth\n");
8835 return -EINVAL;
8836 }
8837
8838 pipe_config->pipe_bpp = bpp;
8839
8840 /* Clamp display bpp to EDID value */
8841 list_for_each_entry(connector, &dev->mode_config.connector_list,
8842 base.head) {
8843 if (!connector->new_encoder ||
8844 connector->new_encoder->new_crtc != crtc)
8845 continue;
8846
8847 connected_sink_compute_bpp(connector, pipe_config);
8848 }
8849
8850 return bpp;
8851 }
8852
8853 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8854 {
8855 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8856 "type: 0x%x flags: 0x%x\n",
8857 mode->crtc_clock,
8858 mode->crtc_hdisplay, mode->crtc_hsync_start,
8859 mode->crtc_hsync_end, mode->crtc_htotal,
8860 mode->crtc_vdisplay, mode->crtc_vsync_start,
8861 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8862 }
8863
8864 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8865 struct intel_crtc_config *pipe_config,
8866 const char *context)
8867 {
8868 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8869 context, pipe_name(crtc->pipe));
8870
8871 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8872 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8873 pipe_config->pipe_bpp, pipe_config->dither);
8874 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8875 pipe_config->has_pch_encoder,
8876 pipe_config->fdi_lanes,
8877 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8878 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8879 pipe_config->fdi_m_n.tu);
8880 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8881 pipe_config->has_dp_encoder,
8882 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8883 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8884 pipe_config->dp_m_n.tu);
8885 DRM_DEBUG_KMS("requested mode:\n");
8886 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8887 DRM_DEBUG_KMS("adjusted mode:\n");
8888 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8889 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8890 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8891 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8892 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8893 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8894 pipe_config->gmch_pfit.control,
8895 pipe_config->gmch_pfit.pgm_ratios,
8896 pipe_config->gmch_pfit.lvds_border_bits);
8897 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8898 pipe_config->pch_pfit.pos,
8899 pipe_config->pch_pfit.size,
8900 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8901 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8902 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8903 }
8904
8905 static bool check_encoder_cloning(struct drm_crtc *crtc)
8906 {
8907 int num_encoders = 0;
8908 bool uncloneable_encoders = false;
8909 struct intel_encoder *encoder;
8910
8911 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8912 base.head) {
8913 if (&encoder->new_crtc->base != crtc)
8914 continue;
8915
8916 num_encoders++;
8917 if (!encoder->cloneable)
8918 uncloneable_encoders = true;
8919 }
8920
8921 return !(num_encoders > 1 && uncloneable_encoders);
8922 }
8923
8924 static struct intel_crtc_config *
8925 intel_modeset_pipe_config(struct drm_crtc *crtc,
8926 struct drm_framebuffer *fb,
8927 struct drm_display_mode *mode)
8928 {
8929 struct drm_device *dev = crtc->dev;
8930 struct intel_encoder *encoder;
8931 struct intel_crtc_config *pipe_config;
8932 int plane_bpp, ret = -EINVAL;
8933 bool retry = true;
8934
8935 if (!check_encoder_cloning(crtc)) {
8936 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8937 return ERR_PTR(-EINVAL);
8938 }
8939
8940 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8941 if (!pipe_config)
8942 return ERR_PTR(-ENOMEM);
8943
8944 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8945 drm_mode_copy(&pipe_config->requested_mode, mode);
8946
8947 pipe_config->cpu_transcoder =
8948 (enum transcoder) to_intel_crtc(crtc)->pipe;
8949 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8950
8951 /*
8952 * Sanitize sync polarity flags based on requested ones. If neither
8953 * positive or negative polarity is requested, treat this as meaning
8954 * negative polarity.
8955 */
8956 if (!(pipe_config->adjusted_mode.flags &
8957 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8958 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8959
8960 if (!(pipe_config->adjusted_mode.flags &
8961 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8962 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8963
8964 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8965 * plane pixel format and any sink constraints into account. Returns the
8966 * source plane bpp so that dithering can be selected on mismatches
8967 * after encoders and crtc also have had their say. */
8968 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8969 fb, pipe_config);
8970 if (plane_bpp < 0)
8971 goto fail;
8972
8973 /*
8974 * Determine the real pipe dimensions. Note that stereo modes can
8975 * increase the actual pipe size due to the frame doubling and
8976 * insertion of additional space for blanks between the frame. This
8977 * is stored in the crtc timings. We use the requested mode to do this
8978 * computation to clearly distinguish it from the adjusted mode, which
8979 * can be changed by the connectors in the below retry loop.
8980 */
8981 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8982 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8983 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8984
8985 encoder_retry:
8986 /* Ensure the port clock defaults are reset when retrying. */
8987 pipe_config->port_clock = 0;
8988 pipe_config->pixel_multiplier = 1;
8989
8990 /* Fill in default crtc timings, allow encoders to overwrite them. */
8991 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8992
8993 /* Pass our mode to the connectors and the CRTC to give them a chance to
8994 * adjust it according to limitations or connector properties, and also
8995 * a chance to reject the mode entirely.
8996 */
8997 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8998 base.head) {
8999
9000 if (&encoder->new_crtc->base != crtc)
9001 continue;
9002
9003 if (!(encoder->compute_config(encoder, pipe_config))) {
9004 DRM_DEBUG_KMS("Encoder config failure\n");
9005 goto fail;
9006 }
9007 }
9008
9009 /* Set default port clock if not overwritten by the encoder. Needs to be
9010 * done afterwards in case the encoder adjusts the mode. */
9011 if (!pipe_config->port_clock)
9012 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9013 * pipe_config->pixel_multiplier;
9014
9015 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9016 if (ret < 0) {
9017 DRM_DEBUG_KMS("CRTC fixup failed\n");
9018 goto fail;
9019 }
9020
9021 if (ret == RETRY) {
9022 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9023 ret = -EINVAL;
9024 goto fail;
9025 }
9026
9027 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9028 retry = false;
9029 goto encoder_retry;
9030 }
9031
9032 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9033 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9034 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9035
9036 return pipe_config;
9037 fail:
9038 kfree(pipe_config);
9039 return ERR_PTR(ret);
9040 }
9041
9042 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9043 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9044 static void
9045 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9046 unsigned *prepare_pipes, unsigned *disable_pipes)
9047 {
9048 struct intel_crtc *intel_crtc;
9049 struct drm_device *dev = crtc->dev;
9050 struct intel_encoder *encoder;
9051 struct intel_connector *connector;
9052 struct drm_crtc *tmp_crtc;
9053
9054 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9055
9056 /* Check which crtcs have changed outputs connected to them, these need
9057 * to be part of the prepare_pipes mask. We don't (yet) support global
9058 * modeset across multiple crtcs, so modeset_pipes will only have one
9059 * bit set at most. */
9060 list_for_each_entry(connector, &dev->mode_config.connector_list,
9061 base.head) {
9062 if (connector->base.encoder == &connector->new_encoder->base)
9063 continue;
9064
9065 if (connector->base.encoder) {
9066 tmp_crtc = connector->base.encoder->crtc;
9067
9068 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9069 }
9070
9071 if (connector->new_encoder)
9072 *prepare_pipes |=
9073 1 << connector->new_encoder->new_crtc->pipe;
9074 }
9075
9076 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9077 base.head) {
9078 if (encoder->base.crtc == &encoder->new_crtc->base)
9079 continue;
9080
9081 if (encoder->base.crtc) {
9082 tmp_crtc = encoder->base.crtc;
9083
9084 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9085 }
9086
9087 if (encoder->new_crtc)
9088 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9089 }
9090
9091 /* Check for any pipes that will be fully disabled ... */
9092 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9093 base.head) {
9094 bool used = false;
9095
9096 /* Don't try to disable disabled crtcs. */
9097 if (!intel_crtc->base.enabled)
9098 continue;
9099
9100 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9101 base.head) {
9102 if (encoder->new_crtc == intel_crtc)
9103 used = true;
9104 }
9105
9106 if (!used)
9107 *disable_pipes |= 1 << intel_crtc->pipe;
9108 }
9109
9110
9111 /* set_mode is also used to update properties on life display pipes. */
9112 intel_crtc = to_intel_crtc(crtc);
9113 if (crtc->enabled)
9114 *prepare_pipes |= 1 << intel_crtc->pipe;
9115
9116 /*
9117 * For simplicity do a full modeset on any pipe where the output routing
9118 * changed. We could be more clever, but that would require us to be
9119 * more careful with calling the relevant encoder->mode_set functions.
9120 */
9121 if (*prepare_pipes)
9122 *modeset_pipes = *prepare_pipes;
9123
9124 /* ... and mask these out. */
9125 *modeset_pipes &= ~(*disable_pipes);
9126 *prepare_pipes &= ~(*disable_pipes);
9127
9128 /*
9129 * HACK: We don't (yet) fully support global modesets. intel_set_config
9130 * obies this rule, but the modeset restore mode of
9131 * intel_modeset_setup_hw_state does not.
9132 */
9133 *modeset_pipes &= 1 << intel_crtc->pipe;
9134 *prepare_pipes &= 1 << intel_crtc->pipe;
9135
9136 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9137 *modeset_pipes, *prepare_pipes, *disable_pipes);
9138 }
9139
9140 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9141 {
9142 struct drm_encoder *encoder;
9143 struct drm_device *dev = crtc->dev;
9144
9145 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9146 if (encoder->crtc == crtc)
9147 return true;
9148
9149 return false;
9150 }
9151
9152 static void
9153 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9154 {
9155 struct intel_encoder *intel_encoder;
9156 struct intel_crtc *intel_crtc;
9157 struct drm_connector *connector;
9158
9159 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9160 base.head) {
9161 if (!intel_encoder->base.crtc)
9162 continue;
9163
9164 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9165
9166 if (prepare_pipes & (1 << intel_crtc->pipe))
9167 intel_encoder->connectors_active = false;
9168 }
9169
9170 intel_modeset_commit_output_state(dev);
9171
9172 /* Update computed state. */
9173 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9174 base.head) {
9175 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9176 }
9177
9178 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9179 if (!connector->encoder || !connector->encoder->crtc)
9180 continue;
9181
9182 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9183
9184 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9185 struct drm_property *dpms_property =
9186 dev->mode_config.dpms_property;
9187
9188 connector->dpms = DRM_MODE_DPMS_ON;
9189 drm_object_property_set_value(&connector->base,
9190 dpms_property,
9191 DRM_MODE_DPMS_ON);
9192
9193 intel_encoder = to_intel_encoder(connector->encoder);
9194 intel_encoder->connectors_active = true;
9195 }
9196 }
9197
9198 }
9199
9200 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9201 {
9202 int diff;
9203
9204 if (clock1 == clock2)
9205 return true;
9206
9207 if (!clock1 || !clock2)
9208 return false;
9209
9210 diff = abs(clock1 - clock2);
9211
9212 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9213 return true;
9214
9215 return false;
9216 }
9217
9218 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9219 list_for_each_entry((intel_crtc), \
9220 &(dev)->mode_config.crtc_list, \
9221 base.head) \
9222 if (mask & (1 <<(intel_crtc)->pipe))
9223
9224 static bool
9225 intel_pipe_config_compare(struct drm_device *dev,
9226 struct intel_crtc_config *current_config,
9227 struct intel_crtc_config *pipe_config)
9228 {
9229 #define PIPE_CONF_CHECK_X(name) \
9230 if (current_config->name != pipe_config->name) { \
9231 DRM_ERROR("mismatch in " #name " " \
9232 "(expected 0x%08x, found 0x%08x)\n", \
9233 current_config->name, \
9234 pipe_config->name); \
9235 return false; \
9236 }
9237
9238 #define PIPE_CONF_CHECK_I(name) \
9239 if (current_config->name != pipe_config->name) { \
9240 DRM_ERROR("mismatch in " #name " " \
9241 "(expected %i, found %i)\n", \
9242 current_config->name, \
9243 pipe_config->name); \
9244 return false; \
9245 }
9246
9247 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9248 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9249 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9250 "(expected %i, found %i)\n", \
9251 current_config->name & (mask), \
9252 pipe_config->name & (mask)); \
9253 return false; \
9254 }
9255
9256 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9257 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9258 DRM_ERROR("mismatch in " #name " " \
9259 "(expected %i, found %i)\n", \
9260 current_config->name, \
9261 pipe_config->name); \
9262 return false; \
9263 }
9264
9265 #define PIPE_CONF_QUIRK(quirk) \
9266 ((current_config->quirks | pipe_config->quirks) & (quirk))
9267
9268 PIPE_CONF_CHECK_I(cpu_transcoder);
9269
9270 PIPE_CONF_CHECK_I(has_pch_encoder);
9271 PIPE_CONF_CHECK_I(fdi_lanes);
9272 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9273 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9274 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9275 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9276 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9277
9278 PIPE_CONF_CHECK_I(has_dp_encoder);
9279 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9280 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9281 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9282 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9283 PIPE_CONF_CHECK_I(dp_m_n.tu);
9284
9285 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9286 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9287 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9288 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9289 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9290 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9291
9292 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9293 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9294 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9295 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9296 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9297 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9298
9299 PIPE_CONF_CHECK_I(pixel_multiplier);
9300
9301 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9302 DRM_MODE_FLAG_INTERLACE);
9303
9304 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9305 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9306 DRM_MODE_FLAG_PHSYNC);
9307 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9308 DRM_MODE_FLAG_NHSYNC);
9309 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9310 DRM_MODE_FLAG_PVSYNC);
9311 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9312 DRM_MODE_FLAG_NVSYNC);
9313 }
9314
9315 PIPE_CONF_CHECK_I(pipe_src_w);
9316 PIPE_CONF_CHECK_I(pipe_src_h);
9317
9318 PIPE_CONF_CHECK_I(gmch_pfit.control);
9319 /* pfit ratios are autocomputed by the hw on gen4+ */
9320 if (INTEL_INFO(dev)->gen < 4)
9321 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9322 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9323 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9324 if (current_config->pch_pfit.enabled) {
9325 PIPE_CONF_CHECK_I(pch_pfit.pos);
9326 PIPE_CONF_CHECK_I(pch_pfit.size);
9327 }
9328
9329 PIPE_CONF_CHECK_I(ips_enabled);
9330
9331 PIPE_CONF_CHECK_I(double_wide);
9332
9333 PIPE_CONF_CHECK_I(shared_dpll);
9334 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9335 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9336 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9337 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9338
9339 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9340 PIPE_CONF_CHECK_I(pipe_bpp);
9341
9342 if (!IS_HASWELL(dev)) {
9343 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9344 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9345 }
9346
9347 #undef PIPE_CONF_CHECK_X
9348 #undef PIPE_CONF_CHECK_I
9349 #undef PIPE_CONF_CHECK_FLAGS
9350 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9351 #undef PIPE_CONF_QUIRK
9352
9353 return true;
9354 }
9355
9356 static void
9357 check_connector_state(struct drm_device *dev)
9358 {
9359 struct intel_connector *connector;
9360
9361 list_for_each_entry(connector, &dev->mode_config.connector_list,
9362 base.head) {
9363 /* This also checks the encoder/connector hw state with the
9364 * ->get_hw_state callbacks. */
9365 intel_connector_check_state(connector);
9366
9367 WARN(&connector->new_encoder->base != connector->base.encoder,
9368 "connector's staged encoder doesn't match current encoder\n");
9369 }
9370 }
9371
9372 static void
9373 check_encoder_state(struct drm_device *dev)
9374 {
9375 struct intel_encoder *encoder;
9376 struct intel_connector *connector;
9377
9378 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9379 base.head) {
9380 bool enabled = false;
9381 bool active = false;
9382 enum pipe pipe, tracked_pipe;
9383
9384 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9385 encoder->base.base.id,
9386 drm_get_encoder_name(&encoder->base));
9387
9388 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9389 "encoder's stage crtc doesn't match current crtc\n");
9390 WARN(encoder->connectors_active && !encoder->base.crtc,
9391 "encoder's active_connectors set, but no crtc\n");
9392
9393 list_for_each_entry(connector, &dev->mode_config.connector_list,
9394 base.head) {
9395 if (connector->base.encoder != &encoder->base)
9396 continue;
9397 enabled = true;
9398 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9399 active = true;
9400 }
9401 WARN(!!encoder->base.crtc != enabled,
9402 "encoder's enabled state mismatch "
9403 "(expected %i, found %i)\n",
9404 !!encoder->base.crtc, enabled);
9405 WARN(active && !encoder->base.crtc,
9406 "active encoder with no crtc\n");
9407
9408 WARN(encoder->connectors_active != active,
9409 "encoder's computed active state doesn't match tracked active state "
9410 "(expected %i, found %i)\n", active, encoder->connectors_active);
9411
9412 active = encoder->get_hw_state(encoder, &pipe);
9413 WARN(active != encoder->connectors_active,
9414 "encoder's hw state doesn't match sw tracking "
9415 "(expected %i, found %i)\n",
9416 encoder->connectors_active, active);
9417
9418 if (!encoder->base.crtc)
9419 continue;
9420
9421 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9422 WARN(active && pipe != tracked_pipe,
9423 "active encoder's pipe doesn't match"
9424 "(expected %i, found %i)\n",
9425 tracked_pipe, pipe);
9426
9427 }
9428 }
9429
9430 static void
9431 check_crtc_state(struct drm_device *dev)
9432 {
9433 drm_i915_private_t *dev_priv = dev->dev_private;
9434 struct intel_crtc *crtc;
9435 struct intel_encoder *encoder;
9436 struct intel_crtc_config pipe_config;
9437
9438 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9439 base.head) {
9440 bool enabled = false;
9441 bool active = false;
9442
9443 memset(&pipe_config, 0, sizeof(pipe_config));
9444
9445 DRM_DEBUG_KMS("[CRTC:%d]\n",
9446 crtc->base.base.id);
9447
9448 WARN(crtc->active && !crtc->base.enabled,
9449 "active crtc, but not enabled in sw tracking\n");
9450
9451 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9452 base.head) {
9453 if (encoder->base.crtc != &crtc->base)
9454 continue;
9455 enabled = true;
9456 if (encoder->connectors_active)
9457 active = true;
9458 }
9459
9460 WARN(active != crtc->active,
9461 "crtc's computed active state doesn't match tracked active state "
9462 "(expected %i, found %i)\n", active, crtc->active);
9463 WARN(enabled != crtc->base.enabled,
9464 "crtc's computed enabled state doesn't match tracked enabled state "
9465 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9466
9467 active = dev_priv->display.get_pipe_config(crtc,
9468 &pipe_config);
9469
9470 /* hw state is inconsistent with the pipe A quirk */
9471 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9472 active = crtc->active;
9473
9474 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9475 base.head) {
9476 enum pipe pipe;
9477 if (encoder->base.crtc != &crtc->base)
9478 continue;
9479 if (encoder->get_hw_state(encoder, &pipe))
9480 encoder->get_config(encoder, &pipe_config);
9481 }
9482
9483 WARN(crtc->active != active,
9484 "crtc active state doesn't match with hw state "
9485 "(expected %i, found %i)\n", crtc->active, active);
9486
9487 if (active &&
9488 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9489 WARN(1, "pipe state doesn't match!\n");
9490 intel_dump_pipe_config(crtc, &pipe_config,
9491 "[hw state]");
9492 intel_dump_pipe_config(crtc, &crtc->config,
9493 "[sw state]");
9494 }
9495 }
9496 }
9497
9498 static void
9499 check_shared_dpll_state(struct drm_device *dev)
9500 {
9501 drm_i915_private_t *dev_priv = dev->dev_private;
9502 struct intel_crtc *crtc;
9503 struct intel_dpll_hw_state dpll_hw_state;
9504 int i;
9505
9506 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9507 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9508 int enabled_crtcs = 0, active_crtcs = 0;
9509 bool active;
9510
9511 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9512
9513 DRM_DEBUG_KMS("%s\n", pll->name);
9514
9515 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9516
9517 WARN(pll->active > pll->refcount,
9518 "more active pll users than references: %i vs %i\n",
9519 pll->active, pll->refcount);
9520 WARN(pll->active && !pll->on,
9521 "pll in active use but not on in sw tracking\n");
9522 WARN(pll->on && !pll->active,
9523 "pll in on but not on in use in sw tracking\n");
9524 WARN(pll->on != active,
9525 "pll on state mismatch (expected %i, found %i)\n",
9526 pll->on, active);
9527
9528 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9529 base.head) {
9530 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9531 enabled_crtcs++;
9532 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9533 active_crtcs++;
9534 }
9535 WARN(pll->active != active_crtcs,
9536 "pll active crtcs mismatch (expected %i, found %i)\n",
9537 pll->active, active_crtcs);
9538 WARN(pll->refcount != enabled_crtcs,
9539 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9540 pll->refcount, enabled_crtcs);
9541
9542 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9543 sizeof(dpll_hw_state)),
9544 "pll hw state mismatch\n");
9545 }
9546 }
9547
9548 void
9549 intel_modeset_check_state(struct drm_device *dev)
9550 {
9551 check_connector_state(dev);
9552 check_encoder_state(dev);
9553 check_crtc_state(dev);
9554 check_shared_dpll_state(dev);
9555 }
9556
9557 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9558 int dotclock)
9559 {
9560 /*
9561 * FDI already provided one idea for the dotclock.
9562 * Yell if the encoder disagrees.
9563 */
9564 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9565 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9566 pipe_config->adjusted_mode.crtc_clock, dotclock);
9567 }
9568
9569 static int __intel_set_mode(struct drm_crtc *crtc,
9570 struct drm_display_mode *mode,
9571 int x, int y, struct drm_framebuffer *fb)
9572 {
9573 struct drm_device *dev = crtc->dev;
9574 drm_i915_private_t *dev_priv = dev->dev_private;
9575 struct drm_display_mode *saved_mode, *saved_hwmode;
9576 struct intel_crtc_config *pipe_config = NULL;
9577 struct intel_crtc *intel_crtc;
9578 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9579 int ret = 0;
9580
9581 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9582 if (!saved_mode)
9583 return -ENOMEM;
9584 saved_hwmode = saved_mode + 1;
9585
9586 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9587 &prepare_pipes, &disable_pipes);
9588
9589 *saved_hwmode = crtc->hwmode;
9590 *saved_mode = crtc->mode;
9591
9592 /* Hack: Because we don't (yet) support global modeset on multiple
9593 * crtcs, we don't keep track of the new mode for more than one crtc.
9594 * Hence simply check whether any bit is set in modeset_pipes in all the
9595 * pieces of code that are not yet converted to deal with mutliple crtcs
9596 * changing their mode at the same time. */
9597 if (modeset_pipes) {
9598 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9599 if (IS_ERR(pipe_config)) {
9600 ret = PTR_ERR(pipe_config);
9601 pipe_config = NULL;
9602
9603 goto out;
9604 }
9605 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9606 "[modeset]");
9607 }
9608
9609 /*
9610 * See if the config requires any additional preparation, e.g.
9611 * to adjust global state with pipes off. We need to do this
9612 * here so we can get the modeset_pipe updated config for the new
9613 * mode set on this crtc. For other crtcs we need to use the
9614 * adjusted_mode bits in the crtc directly.
9615 */
9616 if (IS_VALLEYVIEW(dev)) {
9617 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9618 modeset_pipes, pipe_config);
9619
9620 /* may have added more to prepare_pipes than we should */
9621 prepare_pipes &= ~disable_pipes;
9622 }
9623
9624 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9625 intel_crtc_disable(&intel_crtc->base);
9626
9627 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9628 if (intel_crtc->base.enabled)
9629 dev_priv->display.crtc_disable(&intel_crtc->base);
9630 }
9631
9632 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9633 * to set it here already despite that we pass it down the callchain.
9634 */
9635 if (modeset_pipes) {
9636 crtc->mode = *mode;
9637 /* mode_set/enable/disable functions rely on a correct pipe
9638 * config. */
9639 to_intel_crtc(crtc)->config = *pipe_config;
9640 }
9641
9642 /* Only after disabling all output pipelines that will be changed can we
9643 * update the the output configuration. */
9644 intel_modeset_update_state(dev, prepare_pipes);
9645
9646 if (dev_priv->display.modeset_global_resources)
9647 dev_priv->display.modeset_global_resources(dev);
9648
9649 /* Set up the DPLL and any encoders state that needs to adjust or depend
9650 * on the DPLL.
9651 */
9652 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9653 ret = intel_crtc_mode_set(&intel_crtc->base,
9654 x, y, fb);
9655 if (ret)
9656 goto done;
9657 }
9658
9659 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9660 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9661 dev_priv->display.crtc_enable(&intel_crtc->base);
9662
9663 if (modeset_pipes) {
9664 /* Store real post-adjustment hardware mode. */
9665 crtc->hwmode = pipe_config->adjusted_mode;
9666
9667 /* Calculate and store various constants which
9668 * are later needed by vblank and swap-completion
9669 * timestamping. They are derived from true hwmode.
9670 */
9671 drm_calc_timestamping_constants(crtc);
9672 }
9673
9674 /* FIXME: add subpixel order */
9675 done:
9676 if (ret && crtc->enabled) {
9677 crtc->hwmode = *saved_hwmode;
9678 crtc->mode = *saved_mode;
9679 }
9680
9681 out:
9682 kfree(pipe_config);
9683 kfree(saved_mode);
9684 return ret;
9685 }
9686
9687 static int intel_set_mode(struct drm_crtc *crtc,
9688 struct drm_display_mode *mode,
9689 int x, int y, struct drm_framebuffer *fb)
9690 {
9691 int ret;
9692
9693 ret = __intel_set_mode(crtc, mode, x, y, fb);
9694
9695 if (ret == 0)
9696 intel_modeset_check_state(crtc->dev);
9697
9698 return ret;
9699 }
9700
9701 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9702 {
9703 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9704 }
9705
9706 #undef for_each_intel_crtc_masked
9707
9708 static void intel_set_config_free(struct intel_set_config *config)
9709 {
9710 if (!config)
9711 return;
9712
9713 kfree(config->save_connector_encoders);
9714 kfree(config->save_encoder_crtcs);
9715 kfree(config);
9716 }
9717
9718 static int intel_set_config_save_state(struct drm_device *dev,
9719 struct intel_set_config *config)
9720 {
9721 struct drm_encoder *encoder;
9722 struct drm_connector *connector;
9723 int count;
9724
9725 config->save_encoder_crtcs =
9726 kcalloc(dev->mode_config.num_encoder,
9727 sizeof(struct drm_crtc *), GFP_KERNEL);
9728 if (!config->save_encoder_crtcs)
9729 return -ENOMEM;
9730
9731 config->save_connector_encoders =
9732 kcalloc(dev->mode_config.num_connector,
9733 sizeof(struct drm_encoder *), GFP_KERNEL);
9734 if (!config->save_connector_encoders)
9735 return -ENOMEM;
9736
9737 /* Copy data. Note that driver private data is not affected.
9738 * Should anything bad happen only the expected state is
9739 * restored, not the drivers personal bookkeeping.
9740 */
9741 count = 0;
9742 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9743 config->save_encoder_crtcs[count++] = encoder->crtc;
9744 }
9745
9746 count = 0;
9747 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9748 config->save_connector_encoders[count++] = connector->encoder;
9749 }
9750
9751 return 0;
9752 }
9753
9754 static void intel_set_config_restore_state(struct drm_device *dev,
9755 struct intel_set_config *config)
9756 {
9757 struct intel_encoder *encoder;
9758 struct intel_connector *connector;
9759 int count;
9760
9761 count = 0;
9762 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9763 encoder->new_crtc =
9764 to_intel_crtc(config->save_encoder_crtcs[count++]);
9765 }
9766
9767 count = 0;
9768 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9769 connector->new_encoder =
9770 to_intel_encoder(config->save_connector_encoders[count++]);
9771 }
9772 }
9773
9774 static bool
9775 is_crtc_connector_off(struct drm_mode_set *set)
9776 {
9777 int i;
9778
9779 if (set->num_connectors == 0)
9780 return false;
9781
9782 if (WARN_ON(set->connectors == NULL))
9783 return false;
9784
9785 for (i = 0; i < set->num_connectors; i++)
9786 if (set->connectors[i]->encoder &&
9787 set->connectors[i]->encoder->crtc == set->crtc &&
9788 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9789 return true;
9790
9791 return false;
9792 }
9793
9794 static void
9795 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9796 struct intel_set_config *config)
9797 {
9798
9799 /* We should be able to check here if the fb has the same properties
9800 * and then just flip_or_move it */
9801 if (is_crtc_connector_off(set)) {
9802 config->mode_changed = true;
9803 } else if (set->crtc->fb != set->fb) {
9804 /* If we have no fb then treat it as a full mode set */
9805 if (set->crtc->fb == NULL) {
9806 struct intel_crtc *intel_crtc =
9807 to_intel_crtc(set->crtc);
9808
9809 if (intel_crtc->active && i915_fastboot) {
9810 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9811 config->fb_changed = true;
9812 } else {
9813 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9814 config->mode_changed = true;
9815 }
9816 } else if (set->fb == NULL) {
9817 config->mode_changed = true;
9818 } else if (set->fb->pixel_format !=
9819 set->crtc->fb->pixel_format) {
9820 config->mode_changed = true;
9821 } else {
9822 config->fb_changed = true;
9823 }
9824 }
9825
9826 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9827 config->fb_changed = true;
9828
9829 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9830 DRM_DEBUG_KMS("modes are different, full mode set\n");
9831 drm_mode_debug_printmodeline(&set->crtc->mode);
9832 drm_mode_debug_printmodeline(set->mode);
9833 config->mode_changed = true;
9834 }
9835
9836 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9837 set->crtc->base.id, config->mode_changed, config->fb_changed);
9838 }
9839
9840 static int
9841 intel_modeset_stage_output_state(struct drm_device *dev,
9842 struct drm_mode_set *set,
9843 struct intel_set_config *config)
9844 {
9845 struct drm_crtc *new_crtc;
9846 struct intel_connector *connector;
9847 struct intel_encoder *encoder;
9848 int ro;
9849
9850 /* The upper layers ensure that we either disable a crtc or have a list
9851 * of connectors. For paranoia, double-check this. */
9852 WARN_ON(!set->fb && (set->num_connectors != 0));
9853 WARN_ON(set->fb && (set->num_connectors == 0));
9854
9855 list_for_each_entry(connector, &dev->mode_config.connector_list,
9856 base.head) {
9857 /* Otherwise traverse passed in connector list and get encoders
9858 * for them. */
9859 for (ro = 0; ro < set->num_connectors; ro++) {
9860 if (set->connectors[ro] == &connector->base) {
9861 connector->new_encoder = connector->encoder;
9862 break;
9863 }
9864 }
9865
9866 /* If we disable the crtc, disable all its connectors. Also, if
9867 * the connector is on the changing crtc but not on the new
9868 * connector list, disable it. */
9869 if ((!set->fb || ro == set->num_connectors) &&
9870 connector->base.encoder &&
9871 connector->base.encoder->crtc == set->crtc) {
9872 connector->new_encoder = NULL;
9873
9874 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9875 connector->base.base.id,
9876 drm_get_connector_name(&connector->base));
9877 }
9878
9879
9880 if (&connector->new_encoder->base != connector->base.encoder) {
9881 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9882 config->mode_changed = true;
9883 }
9884 }
9885 /* connector->new_encoder is now updated for all connectors. */
9886
9887 /* Update crtc of enabled connectors. */
9888 list_for_each_entry(connector, &dev->mode_config.connector_list,
9889 base.head) {
9890 if (!connector->new_encoder)
9891 continue;
9892
9893 new_crtc = connector->new_encoder->base.crtc;
9894
9895 for (ro = 0; ro < set->num_connectors; ro++) {
9896 if (set->connectors[ro] == &connector->base)
9897 new_crtc = set->crtc;
9898 }
9899
9900 /* Make sure the new CRTC will work with the encoder */
9901 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9902 new_crtc)) {
9903 return -EINVAL;
9904 }
9905 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9906
9907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9908 connector->base.base.id,
9909 drm_get_connector_name(&connector->base),
9910 new_crtc->base.id);
9911 }
9912
9913 /* Check for any encoders that needs to be disabled. */
9914 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9915 base.head) {
9916 list_for_each_entry(connector,
9917 &dev->mode_config.connector_list,
9918 base.head) {
9919 if (connector->new_encoder == encoder) {
9920 WARN_ON(!connector->new_encoder->new_crtc);
9921
9922 goto next_encoder;
9923 }
9924 }
9925 encoder->new_crtc = NULL;
9926 next_encoder:
9927 /* Only now check for crtc changes so we don't miss encoders
9928 * that will be disabled. */
9929 if (&encoder->new_crtc->base != encoder->base.crtc) {
9930 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9931 config->mode_changed = true;
9932 }
9933 }
9934 /* Now we've also updated encoder->new_crtc for all encoders. */
9935
9936 return 0;
9937 }
9938
9939 static int intel_crtc_set_config(struct drm_mode_set *set)
9940 {
9941 struct drm_device *dev;
9942 struct drm_mode_set save_set;
9943 struct intel_set_config *config;
9944 int ret;
9945
9946 BUG_ON(!set);
9947 BUG_ON(!set->crtc);
9948 BUG_ON(!set->crtc->helper_private);
9949
9950 /* Enforce sane interface api - has been abused by the fb helper. */
9951 BUG_ON(!set->mode && set->fb);
9952 BUG_ON(set->fb && set->num_connectors == 0);
9953
9954 if (set->fb) {
9955 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9956 set->crtc->base.id, set->fb->base.id,
9957 (int)set->num_connectors, set->x, set->y);
9958 } else {
9959 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9960 }
9961
9962 dev = set->crtc->dev;
9963
9964 ret = -ENOMEM;
9965 config = kzalloc(sizeof(*config), GFP_KERNEL);
9966 if (!config)
9967 goto out_config;
9968
9969 ret = intel_set_config_save_state(dev, config);
9970 if (ret)
9971 goto out_config;
9972
9973 save_set.crtc = set->crtc;
9974 save_set.mode = &set->crtc->mode;
9975 save_set.x = set->crtc->x;
9976 save_set.y = set->crtc->y;
9977 save_set.fb = set->crtc->fb;
9978
9979 /* Compute whether we need a full modeset, only an fb base update or no
9980 * change at all. In the future we might also check whether only the
9981 * mode changed, e.g. for LVDS where we only change the panel fitter in
9982 * such cases. */
9983 intel_set_config_compute_mode_changes(set, config);
9984
9985 ret = intel_modeset_stage_output_state(dev, set, config);
9986 if (ret)
9987 goto fail;
9988
9989 if (config->mode_changed) {
9990 ret = intel_set_mode(set->crtc, set->mode,
9991 set->x, set->y, set->fb);
9992 } else if (config->fb_changed) {
9993 intel_crtc_wait_for_pending_flips(set->crtc);
9994
9995 ret = intel_pipe_set_base(set->crtc,
9996 set->x, set->y, set->fb);
9997 }
9998
9999 if (ret) {
10000 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10001 set->crtc->base.id, ret);
10002 fail:
10003 intel_set_config_restore_state(dev, config);
10004
10005 /* Try to restore the config */
10006 if (config->mode_changed &&
10007 intel_set_mode(save_set.crtc, save_set.mode,
10008 save_set.x, save_set.y, save_set.fb))
10009 DRM_ERROR("failed to restore config after modeset failure\n");
10010 }
10011
10012 out_config:
10013 intel_set_config_free(config);
10014 return ret;
10015 }
10016
10017 static const struct drm_crtc_funcs intel_crtc_funcs = {
10018 .cursor_set = intel_crtc_cursor_set,
10019 .cursor_move = intel_crtc_cursor_move,
10020 .gamma_set = intel_crtc_gamma_set,
10021 .set_config = intel_crtc_set_config,
10022 .destroy = intel_crtc_destroy,
10023 .page_flip = intel_crtc_page_flip,
10024 };
10025
10026 static void intel_cpu_pll_init(struct drm_device *dev)
10027 {
10028 if (HAS_DDI(dev))
10029 intel_ddi_pll_init(dev);
10030 }
10031
10032 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10033 struct intel_shared_dpll *pll,
10034 struct intel_dpll_hw_state *hw_state)
10035 {
10036 uint32_t val;
10037
10038 val = I915_READ(PCH_DPLL(pll->id));
10039 hw_state->dpll = val;
10040 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10041 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10042
10043 return val & DPLL_VCO_ENABLE;
10044 }
10045
10046 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10047 struct intel_shared_dpll *pll)
10048 {
10049 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10050 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10051 }
10052
10053 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10054 struct intel_shared_dpll *pll)
10055 {
10056 /* PCH refclock must be enabled first */
10057 assert_pch_refclk_enabled(dev_priv);
10058
10059 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10060
10061 /* Wait for the clocks to stabilize. */
10062 POSTING_READ(PCH_DPLL(pll->id));
10063 udelay(150);
10064
10065 /* The pixel multiplier can only be updated once the
10066 * DPLL is enabled and the clocks are stable.
10067 *
10068 * So write it again.
10069 */
10070 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10071 POSTING_READ(PCH_DPLL(pll->id));
10072 udelay(200);
10073 }
10074
10075 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10076 struct intel_shared_dpll *pll)
10077 {
10078 struct drm_device *dev = dev_priv->dev;
10079 struct intel_crtc *crtc;
10080
10081 /* Make sure no transcoder isn't still depending on us. */
10082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10083 if (intel_crtc_to_shared_dpll(crtc) == pll)
10084 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10085 }
10086
10087 I915_WRITE(PCH_DPLL(pll->id), 0);
10088 POSTING_READ(PCH_DPLL(pll->id));
10089 udelay(200);
10090 }
10091
10092 static char *ibx_pch_dpll_names[] = {
10093 "PCH DPLL A",
10094 "PCH DPLL B",
10095 };
10096
10097 static void ibx_pch_dpll_init(struct drm_device *dev)
10098 {
10099 struct drm_i915_private *dev_priv = dev->dev_private;
10100 int i;
10101
10102 dev_priv->num_shared_dpll = 2;
10103
10104 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10105 dev_priv->shared_dplls[i].id = i;
10106 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10107 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10108 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10109 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10110 dev_priv->shared_dplls[i].get_hw_state =
10111 ibx_pch_dpll_get_hw_state;
10112 }
10113 }
10114
10115 static void intel_shared_dpll_init(struct drm_device *dev)
10116 {
10117 struct drm_i915_private *dev_priv = dev->dev_private;
10118
10119 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10120 ibx_pch_dpll_init(dev);
10121 else
10122 dev_priv->num_shared_dpll = 0;
10123
10124 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10125 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10126 dev_priv->num_shared_dpll);
10127 }
10128
10129 static void intel_crtc_init(struct drm_device *dev, int pipe)
10130 {
10131 drm_i915_private_t *dev_priv = dev->dev_private;
10132 struct intel_crtc *intel_crtc;
10133 int i;
10134
10135 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10136 if (intel_crtc == NULL)
10137 return;
10138
10139 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10140
10141 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10142 for (i = 0; i < 256; i++) {
10143 intel_crtc->lut_r[i] = i;
10144 intel_crtc->lut_g[i] = i;
10145 intel_crtc->lut_b[i] = i;
10146 }
10147
10148 /*
10149 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10150 * is hooked to plane B. Hence we want plane A feeding pipe B.
10151 */
10152 intel_crtc->pipe = pipe;
10153 intel_crtc->plane = pipe;
10154 if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
10155 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10156 intel_crtc->plane = !pipe;
10157 }
10158
10159 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10160 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10161 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10162 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10163
10164 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10165 }
10166
10167 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10168 {
10169 struct drm_encoder *encoder = connector->base.encoder;
10170
10171 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10172
10173 if (!encoder)
10174 return INVALID_PIPE;
10175
10176 return to_intel_crtc(encoder->crtc)->pipe;
10177 }
10178
10179 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10180 struct drm_file *file)
10181 {
10182 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10183 struct drm_mode_object *drmmode_obj;
10184 struct intel_crtc *crtc;
10185
10186 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10187 return -ENODEV;
10188
10189 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10190 DRM_MODE_OBJECT_CRTC);
10191
10192 if (!drmmode_obj) {
10193 DRM_ERROR("no such CRTC id\n");
10194 return -ENOENT;
10195 }
10196
10197 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10198 pipe_from_crtc_id->pipe = crtc->pipe;
10199
10200 return 0;
10201 }
10202
10203 static int intel_encoder_clones(struct intel_encoder *encoder)
10204 {
10205 struct drm_device *dev = encoder->base.dev;
10206 struct intel_encoder *source_encoder;
10207 int index_mask = 0;
10208 int entry = 0;
10209
10210 list_for_each_entry(source_encoder,
10211 &dev->mode_config.encoder_list, base.head) {
10212
10213 if (encoder == source_encoder)
10214 index_mask |= (1 << entry);
10215
10216 /* Intel hw has only one MUX where enocoders could be cloned. */
10217 if (encoder->cloneable && source_encoder->cloneable)
10218 index_mask |= (1 << entry);
10219
10220 entry++;
10221 }
10222
10223 return index_mask;
10224 }
10225
10226 static bool has_edp_a(struct drm_device *dev)
10227 {
10228 struct drm_i915_private *dev_priv = dev->dev_private;
10229
10230 if (!IS_MOBILE(dev))
10231 return false;
10232
10233 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10234 return false;
10235
10236 if (IS_GEN5(dev) &&
10237 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10238 return false;
10239
10240 return true;
10241 }
10242
10243 static void intel_setup_outputs(struct drm_device *dev)
10244 {
10245 struct drm_i915_private *dev_priv = dev->dev_private;
10246 struct intel_encoder *encoder;
10247 bool dpd_is_edp = false;
10248
10249 intel_lvds_init(dev);
10250
10251 if (!IS_ULT(dev))
10252 intel_crt_init(dev);
10253
10254 if (HAS_DDI(dev)) {
10255 int found;
10256
10257 /* Haswell uses DDI functions to detect digital outputs */
10258 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10259 /* DDI A only supports eDP */
10260 if (found)
10261 intel_ddi_init(dev, PORT_A);
10262
10263 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10264 * register */
10265 found = I915_READ(SFUSE_STRAP);
10266
10267 if (found & SFUSE_STRAP_DDIB_DETECTED)
10268 intel_ddi_init(dev, PORT_B);
10269 if (found & SFUSE_STRAP_DDIC_DETECTED)
10270 intel_ddi_init(dev, PORT_C);
10271 if (found & SFUSE_STRAP_DDID_DETECTED)
10272 intel_ddi_init(dev, PORT_D);
10273 } else if (HAS_PCH_SPLIT(dev)) {
10274 int found;
10275 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10276
10277 if (has_edp_a(dev))
10278 intel_dp_init(dev, DP_A, PORT_A);
10279
10280 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10281 /* PCH SDVOB multiplex with HDMIB */
10282 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10283 if (!found)
10284 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10285 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10286 intel_dp_init(dev, PCH_DP_B, PORT_B);
10287 }
10288
10289 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10290 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10291
10292 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10293 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10294
10295 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10296 intel_dp_init(dev, PCH_DP_C, PORT_C);
10297
10298 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10299 intel_dp_init(dev, PCH_DP_D, PORT_D);
10300 } else if (IS_VALLEYVIEW(dev)) {
10301 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10302 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10303 PORT_B);
10304 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10305 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10306 }
10307
10308 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10309 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10310 PORT_C);
10311 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10312 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10313 }
10314
10315 intel_dsi_init(dev);
10316 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10317 bool found = false;
10318
10319 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10320 DRM_DEBUG_KMS("probing SDVOB\n");
10321 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10322 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10323 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10324 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10325 }
10326
10327 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10328 intel_dp_init(dev, DP_B, PORT_B);
10329 }
10330
10331 /* Before G4X SDVOC doesn't have its own detect register */
10332
10333 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10334 DRM_DEBUG_KMS("probing SDVOC\n");
10335 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10336 }
10337
10338 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10339
10340 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10341 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10342 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10343 }
10344 if (SUPPORTS_INTEGRATED_DP(dev))
10345 intel_dp_init(dev, DP_C, PORT_C);
10346 }
10347
10348 if (SUPPORTS_INTEGRATED_DP(dev) &&
10349 (I915_READ(DP_D) & DP_DETECTED))
10350 intel_dp_init(dev, DP_D, PORT_D);
10351 } else if (IS_GEN2(dev))
10352 intel_dvo_init(dev);
10353
10354 if (SUPPORTS_TV(dev))
10355 intel_tv_init(dev);
10356
10357 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10358 encoder->base.possible_crtcs = encoder->crtc_mask;
10359 encoder->base.possible_clones =
10360 intel_encoder_clones(encoder);
10361 }
10362
10363 intel_init_pch_refclk(dev);
10364
10365 drm_helper_move_panel_connectors_to_head(dev);
10366 }
10367
10368 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10369 {
10370 drm_framebuffer_cleanup(&fb->base);
10371 WARN_ON(!fb->obj->framebuffer_references--);
10372 drm_gem_object_unreference_unlocked(&fb->obj->base);
10373 }
10374
10375 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10376 {
10377 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10378
10379 intel_framebuffer_fini(intel_fb);
10380 kfree(intel_fb);
10381 }
10382
10383 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10384 struct drm_file *file,
10385 unsigned int *handle)
10386 {
10387 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10388 struct drm_i915_gem_object *obj = intel_fb->obj;
10389
10390 return drm_gem_handle_create(file, &obj->base, handle);
10391 }
10392
10393 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10394 .destroy = intel_user_framebuffer_destroy,
10395 .create_handle = intel_user_framebuffer_create_handle,
10396 };
10397
10398 int intel_framebuffer_init(struct drm_device *dev,
10399 struct intel_framebuffer *intel_fb,
10400 struct drm_mode_fb_cmd2 *mode_cmd,
10401 struct drm_i915_gem_object *obj)
10402 {
10403 int aligned_height, tile_height;
10404 int pitch_limit;
10405 int ret;
10406
10407 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10408
10409 if (obj->tiling_mode == I915_TILING_Y) {
10410 DRM_DEBUG("hardware does not support tiling Y\n");
10411 return -EINVAL;
10412 }
10413
10414 if (mode_cmd->pitches[0] & 63) {
10415 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10416 mode_cmd->pitches[0]);
10417 return -EINVAL;
10418 }
10419
10420 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10421 pitch_limit = 32*1024;
10422 } else if (INTEL_INFO(dev)->gen >= 4) {
10423 if (obj->tiling_mode)
10424 pitch_limit = 16*1024;
10425 else
10426 pitch_limit = 32*1024;
10427 } else if (INTEL_INFO(dev)->gen >= 3) {
10428 if (obj->tiling_mode)
10429 pitch_limit = 8*1024;
10430 else
10431 pitch_limit = 16*1024;
10432 } else
10433 /* XXX DSPC is limited to 4k tiled */
10434 pitch_limit = 8*1024;
10435
10436 if (mode_cmd->pitches[0] > pitch_limit) {
10437 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10438 obj->tiling_mode ? "tiled" : "linear",
10439 mode_cmd->pitches[0], pitch_limit);
10440 return -EINVAL;
10441 }
10442
10443 if (obj->tiling_mode != I915_TILING_NONE &&
10444 mode_cmd->pitches[0] != obj->stride) {
10445 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10446 mode_cmd->pitches[0], obj->stride);
10447 return -EINVAL;
10448 }
10449
10450 /* Reject formats not supported by any plane early. */
10451 switch (mode_cmd->pixel_format) {
10452 case DRM_FORMAT_C8:
10453 case DRM_FORMAT_RGB565:
10454 case DRM_FORMAT_XRGB8888:
10455 case DRM_FORMAT_ARGB8888:
10456 break;
10457 case DRM_FORMAT_XRGB1555:
10458 case DRM_FORMAT_ARGB1555:
10459 if (INTEL_INFO(dev)->gen > 3) {
10460 DRM_DEBUG("unsupported pixel format: %s\n",
10461 drm_get_format_name(mode_cmd->pixel_format));
10462 return -EINVAL;
10463 }
10464 break;
10465 case DRM_FORMAT_XBGR8888:
10466 case DRM_FORMAT_ABGR8888:
10467 case DRM_FORMAT_XRGB2101010:
10468 case DRM_FORMAT_ARGB2101010:
10469 case DRM_FORMAT_XBGR2101010:
10470 case DRM_FORMAT_ABGR2101010:
10471 if (INTEL_INFO(dev)->gen < 4) {
10472 DRM_DEBUG("unsupported pixel format: %s\n",
10473 drm_get_format_name(mode_cmd->pixel_format));
10474 return -EINVAL;
10475 }
10476 break;
10477 case DRM_FORMAT_YUYV:
10478 case DRM_FORMAT_UYVY:
10479 case DRM_FORMAT_YVYU:
10480 case DRM_FORMAT_VYUY:
10481 if (INTEL_INFO(dev)->gen < 5) {
10482 DRM_DEBUG("unsupported pixel format: %s\n",
10483 drm_get_format_name(mode_cmd->pixel_format));
10484 return -EINVAL;
10485 }
10486 break;
10487 default:
10488 DRM_DEBUG("unsupported pixel format: %s\n",
10489 drm_get_format_name(mode_cmd->pixel_format));
10490 return -EINVAL;
10491 }
10492
10493 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10494 if (mode_cmd->offsets[0] != 0)
10495 return -EINVAL;
10496
10497 tile_height = IS_GEN2(dev) ? 16 : 8;
10498 aligned_height = ALIGN(mode_cmd->height,
10499 obj->tiling_mode ? tile_height : 1);
10500 /* FIXME drm helper for size checks (especially planar formats)? */
10501 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10502 return -EINVAL;
10503
10504 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10505 intel_fb->obj = obj;
10506 intel_fb->obj->framebuffer_references++;
10507
10508 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10509 if (ret) {
10510 DRM_ERROR("framebuffer init failed %d\n", ret);
10511 return ret;
10512 }
10513
10514 return 0;
10515 }
10516
10517 static struct drm_framebuffer *
10518 intel_user_framebuffer_create(struct drm_device *dev,
10519 struct drm_file *filp,
10520 struct drm_mode_fb_cmd2 *mode_cmd)
10521 {
10522 struct drm_i915_gem_object *obj;
10523
10524 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10525 mode_cmd->handles[0]));
10526 if (&obj->base == NULL)
10527 return ERR_PTR(-ENOENT);
10528
10529 return intel_framebuffer_create(dev, mode_cmd, obj);
10530 }
10531
10532 #ifndef CONFIG_DRM_I915_FBDEV
10533 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10534 {
10535 }
10536 #endif
10537
10538 static const struct drm_mode_config_funcs intel_mode_funcs = {
10539 .fb_create = intel_user_framebuffer_create,
10540 .output_poll_changed = intel_fbdev_output_poll_changed,
10541 };
10542
10543 /* Set up chip specific display functions */
10544 static void intel_init_display(struct drm_device *dev)
10545 {
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547
10548 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10549 dev_priv->display.find_dpll = g4x_find_best_dpll;
10550 else if (IS_VALLEYVIEW(dev))
10551 dev_priv->display.find_dpll = vlv_find_best_dpll;
10552 else if (IS_PINEVIEW(dev))
10553 dev_priv->display.find_dpll = pnv_find_best_dpll;
10554 else
10555 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10556
10557 if (HAS_DDI(dev)) {
10558 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10559 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10560 dev_priv->display.crtc_enable = haswell_crtc_enable;
10561 dev_priv->display.crtc_disable = haswell_crtc_disable;
10562 dev_priv->display.off = haswell_crtc_off;
10563 dev_priv->display.update_plane = ironlake_update_plane;
10564 } else if (HAS_PCH_SPLIT(dev)) {
10565 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10566 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10567 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10568 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10569 dev_priv->display.off = ironlake_crtc_off;
10570 dev_priv->display.update_plane = ironlake_update_plane;
10571 } else if (IS_VALLEYVIEW(dev)) {
10572 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10573 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10574 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10575 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10576 dev_priv->display.off = i9xx_crtc_off;
10577 dev_priv->display.update_plane = i9xx_update_plane;
10578 } else {
10579 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10580 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10581 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10582 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10583 dev_priv->display.off = i9xx_crtc_off;
10584 dev_priv->display.update_plane = i9xx_update_plane;
10585 }
10586
10587 /* Returns the core display clock speed */
10588 if (IS_VALLEYVIEW(dev))
10589 dev_priv->display.get_display_clock_speed =
10590 valleyview_get_display_clock_speed;
10591 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10592 dev_priv->display.get_display_clock_speed =
10593 i945_get_display_clock_speed;
10594 else if (IS_I915G(dev))
10595 dev_priv->display.get_display_clock_speed =
10596 i915_get_display_clock_speed;
10597 else if (IS_I945GM(dev) || IS_845G(dev))
10598 dev_priv->display.get_display_clock_speed =
10599 i9xx_misc_get_display_clock_speed;
10600 else if (IS_PINEVIEW(dev))
10601 dev_priv->display.get_display_clock_speed =
10602 pnv_get_display_clock_speed;
10603 else if (IS_I915GM(dev))
10604 dev_priv->display.get_display_clock_speed =
10605 i915gm_get_display_clock_speed;
10606 else if (IS_I865G(dev))
10607 dev_priv->display.get_display_clock_speed =
10608 i865_get_display_clock_speed;
10609 else if (IS_I85X(dev))
10610 dev_priv->display.get_display_clock_speed =
10611 i855_get_display_clock_speed;
10612 else /* 852, 830 */
10613 dev_priv->display.get_display_clock_speed =
10614 i830_get_display_clock_speed;
10615
10616 if (HAS_PCH_SPLIT(dev)) {
10617 if (IS_GEN5(dev)) {
10618 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10619 dev_priv->display.write_eld = ironlake_write_eld;
10620 } else if (IS_GEN6(dev)) {
10621 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10622 dev_priv->display.write_eld = ironlake_write_eld;
10623 } else if (IS_IVYBRIDGE(dev)) {
10624 /* FIXME: detect B0+ stepping and use auto training */
10625 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10626 dev_priv->display.write_eld = ironlake_write_eld;
10627 dev_priv->display.modeset_global_resources =
10628 ivb_modeset_global_resources;
10629 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10630 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10631 dev_priv->display.write_eld = haswell_write_eld;
10632 dev_priv->display.modeset_global_resources =
10633 haswell_modeset_global_resources;
10634 }
10635 } else if (IS_G4X(dev)) {
10636 dev_priv->display.write_eld = g4x_write_eld;
10637 } else if (IS_VALLEYVIEW(dev)) {
10638 dev_priv->display.modeset_global_resources =
10639 valleyview_modeset_global_resources;
10640 dev_priv->display.write_eld = ironlake_write_eld;
10641 }
10642
10643 /* Default just returns -ENODEV to indicate unsupported */
10644 dev_priv->display.queue_flip = intel_default_queue_flip;
10645
10646 switch (INTEL_INFO(dev)->gen) {
10647 case 2:
10648 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10649 break;
10650
10651 case 3:
10652 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10653 break;
10654
10655 case 4:
10656 case 5:
10657 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10658 break;
10659
10660 case 6:
10661 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10662 break;
10663 case 7:
10664 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10665 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10666 break;
10667 }
10668
10669 intel_panel_init_backlight_funcs(dev);
10670 }
10671
10672 /*
10673 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10674 * resume, or other times. This quirk makes sure that's the case for
10675 * affected systems.
10676 */
10677 static void quirk_pipea_force(struct drm_device *dev)
10678 {
10679 struct drm_i915_private *dev_priv = dev->dev_private;
10680
10681 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10682 DRM_INFO("applying pipe a force quirk\n");
10683 }
10684
10685 /*
10686 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10687 */
10688 static void quirk_ssc_force_disable(struct drm_device *dev)
10689 {
10690 struct drm_i915_private *dev_priv = dev->dev_private;
10691 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10692 DRM_INFO("applying lvds SSC disable quirk\n");
10693 }
10694
10695 /*
10696 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10697 * brightness value
10698 */
10699 static void quirk_invert_brightness(struct drm_device *dev)
10700 {
10701 struct drm_i915_private *dev_priv = dev->dev_private;
10702 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10703 DRM_INFO("applying inverted panel brightness quirk\n");
10704 }
10705
10706 struct intel_quirk {
10707 int device;
10708 int subsystem_vendor;
10709 int subsystem_device;
10710 void (*hook)(struct drm_device *dev);
10711 };
10712
10713 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10714 struct intel_dmi_quirk {
10715 void (*hook)(struct drm_device *dev);
10716 const struct dmi_system_id (*dmi_id_list)[];
10717 };
10718
10719 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10720 {
10721 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10722 return 1;
10723 }
10724
10725 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10726 {
10727 .dmi_id_list = &(const struct dmi_system_id[]) {
10728 {
10729 .callback = intel_dmi_reverse_brightness,
10730 .ident = "NCR Corporation",
10731 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10732 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10733 },
10734 },
10735 { } /* terminating entry */
10736 },
10737 .hook = quirk_invert_brightness,
10738 },
10739 };
10740
10741 static struct intel_quirk intel_quirks[] = {
10742 /* HP Mini needs pipe A force quirk (LP: #322104) */
10743 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10744
10745 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10746 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10747
10748 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10749 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10750
10751 /* 830 needs to leave pipe A & dpll A up */
10752 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10753
10754 /* Lenovo U160 cannot use SSC on LVDS */
10755 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10756
10757 /* Sony Vaio Y cannot use SSC on LVDS */
10758 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10759
10760 /*
10761 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10762 * seem to use inverted backlight PWM.
10763 */
10764 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10765 };
10766
10767 static void intel_init_quirks(struct drm_device *dev)
10768 {
10769 struct pci_dev *d = dev->pdev;
10770 int i;
10771
10772 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10773 struct intel_quirk *q = &intel_quirks[i];
10774
10775 if (d->device == q->device &&
10776 (d->subsystem_vendor == q->subsystem_vendor ||
10777 q->subsystem_vendor == PCI_ANY_ID) &&
10778 (d->subsystem_device == q->subsystem_device ||
10779 q->subsystem_device == PCI_ANY_ID))
10780 q->hook(dev);
10781 }
10782 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10783 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10784 intel_dmi_quirks[i].hook(dev);
10785 }
10786 }
10787
10788 /* Disable the VGA plane that we never use */
10789 static void i915_disable_vga(struct drm_device *dev)
10790 {
10791 struct drm_i915_private *dev_priv = dev->dev_private;
10792 u8 sr1;
10793 u32 vga_reg = i915_vgacntrl_reg(dev);
10794
10795 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10796 outb(SR01, VGA_SR_INDEX);
10797 sr1 = inb(VGA_SR_DATA);
10798 outb(sr1 | 1<<5, VGA_SR_DATA);
10799 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10800 udelay(300);
10801
10802 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10803 POSTING_READ(vga_reg);
10804 }
10805
10806 void intel_modeset_init_hw(struct drm_device *dev)
10807 {
10808 intel_prepare_ddi(dev);
10809
10810 intel_init_clock_gating(dev);
10811
10812 intel_init_dpio(dev);
10813
10814 mutex_lock(&dev->struct_mutex);
10815 intel_enable_gt_powersave(dev);
10816 mutex_unlock(&dev->struct_mutex);
10817 }
10818
10819 void intel_modeset_suspend_hw(struct drm_device *dev)
10820 {
10821 intel_suspend_hw(dev);
10822 }
10823
10824 void intel_modeset_init(struct drm_device *dev)
10825 {
10826 struct drm_i915_private *dev_priv = dev->dev_private;
10827 int i, j, ret;
10828
10829 drm_mode_config_init(dev);
10830
10831 dev->mode_config.min_width = 0;
10832 dev->mode_config.min_height = 0;
10833
10834 dev->mode_config.preferred_depth = 24;
10835 dev->mode_config.prefer_shadow = 1;
10836
10837 dev->mode_config.funcs = &intel_mode_funcs;
10838
10839 intel_init_quirks(dev);
10840
10841 intel_init_pm(dev);
10842
10843 if (INTEL_INFO(dev)->num_pipes == 0)
10844 return;
10845
10846 intel_init_display(dev);
10847
10848 if (IS_GEN2(dev)) {
10849 dev->mode_config.max_width = 2048;
10850 dev->mode_config.max_height = 2048;
10851 } else if (IS_GEN3(dev)) {
10852 dev->mode_config.max_width = 4096;
10853 dev->mode_config.max_height = 4096;
10854 } else {
10855 dev->mode_config.max_width = 8192;
10856 dev->mode_config.max_height = 8192;
10857 }
10858 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10859
10860 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10861 INTEL_INFO(dev)->num_pipes,
10862 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10863
10864 for_each_pipe(i) {
10865 intel_crtc_init(dev, i);
10866 for (j = 0; j < dev_priv->num_plane; j++) {
10867 ret = intel_plane_init(dev, i, j);
10868 if (ret)
10869 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10870 pipe_name(i), sprite_name(i, j), ret);
10871 }
10872 }
10873
10874 intel_cpu_pll_init(dev);
10875 intel_shared_dpll_init(dev);
10876
10877 /* Just disable it once at startup */
10878 i915_disable_vga(dev);
10879 intel_setup_outputs(dev);
10880
10881 /* Just in case the BIOS is doing something questionable. */
10882 intel_disable_fbc(dev);
10883 }
10884
10885 static void
10886 intel_connector_break_all_links(struct intel_connector *connector)
10887 {
10888 connector->base.dpms = DRM_MODE_DPMS_OFF;
10889 connector->base.encoder = NULL;
10890 connector->encoder->connectors_active = false;
10891 connector->encoder->base.crtc = NULL;
10892 }
10893
10894 static void intel_enable_pipe_a(struct drm_device *dev)
10895 {
10896 struct intel_connector *connector;
10897 struct drm_connector *crt = NULL;
10898 struct intel_load_detect_pipe load_detect_temp;
10899
10900 /* We can't just switch on the pipe A, we need to set things up with a
10901 * proper mode and output configuration. As a gross hack, enable pipe A
10902 * by enabling the load detect pipe once. */
10903 list_for_each_entry(connector,
10904 &dev->mode_config.connector_list,
10905 base.head) {
10906 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10907 crt = &connector->base;
10908 break;
10909 }
10910 }
10911
10912 if (!crt)
10913 return;
10914
10915 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10916 intel_release_load_detect_pipe(crt, &load_detect_temp);
10917
10918
10919 }
10920
10921 static bool
10922 intel_check_plane_mapping(struct intel_crtc *crtc)
10923 {
10924 struct drm_device *dev = crtc->base.dev;
10925 struct drm_i915_private *dev_priv = dev->dev_private;
10926 u32 reg, val;
10927
10928 if (INTEL_INFO(dev)->num_pipes == 1)
10929 return true;
10930
10931 reg = DSPCNTR(!crtc->plane);
10932 val = I915_READ(reg);
10933
10934 if ((val & DISPLAY_PLANE_ENABLE) &&
10935 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10936 return false;
10937
10938 return true;
10939 }
10940
10941 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10942 {
10943 struct drm_device *dev = crtc->base.dev;
10944 struct drm_i915_private *dev_priv = dev->dev_private;
10945 u32 reg;
10946
10947 /* Clear any frame start delays used for debugging left by the BIOS */
10948 reg = PIPECONF(crtc->config.cpu_transcoder);
10949 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10950
10951 /* We need to sanitize the plane -> pipe mapping first because this will
10952 * disable the crtc (and hence change the state) if it is wrong. Note
10953 * that gen4+ has a fixed plane -> pipe mapping. */
10954 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10955 struct intel_connector *connector;
10956 bool plane;
10957
10958 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10959 crtc->base.base.id);
10960
10961 /* Pipe has the wrong plane attached and the plane is active.
10962 * Temporarily change the plane mapping and disable everything
10963 * ... */
10964 plane = crtc->plane;
10965 crtc->plane = !plane;
10966 dev_priv->display.crtc_disable(&crtc->base);
10967 crtc->plane = plane;
10968
10969 /* ... and break all links. */
10970 list_for_each_entry(connector, &dev->mode_config.connector_list,
10971 base.head) {
10972 if (connector->encoder->base.crtc != &crtc->base)
10973 continue;
10974
10975 intel_connector_break_all_links(connector);
10976 }
10977
10978 WARN_ON(crtc->active);
10979 crtc->base.enabled = false;
10980 }
10981
10982 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10983 crtc->pipe == PIPE_A && !crtc->active) {
10984 /* BIOS forgot to enable pipe A, this mostly happens after
10985 * resume. Force-enable the pipe to fix this, the update_dpms
10986 * call below we restore the pipe to the right state, but leave
10987 * the required bits on. */
10988 intel_enable_pipe_a(dev);
10989 }
10990
10991 /* Adjust the state of the output pipe according to whether we
10992 * have active connectors/encoders. */
10993 intel_crtc_update_dpms(&crtc->base);
10994
10995 if (crtc->active != crtc->base.enabled) {
10996 struct intel_encoder *encoder;
10997
10998 /* This can happen either due to bugs in the get_hw_state
10999 * functions or because the pipe is force-enabled due to the
11000 * pipe A quirk. */
11001 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11002 crtc->base.base.id,
11003 crtc->base.enabled ? "enabled" : "disabled",
11004 crtc->active ? "enabled" : "disabled");
11005
11006 crtc->base.enabled = crtc->active;
11007
11008 /* Because we only establish the connector -> encoder ->
11009 * crtc links if something is active, this means the
11010 * crtc is now deactivated. Break the links. connector
11011 * -> encoder links are only establish when things are
11012 * actually up, hence no need to break them. */
11013 WARN_ON(crtc->active);
11014
11015 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11016 WARN_ON(encoder->connectors_active);
11017 encoder->base.crtc = NULL;
11018 }
11019 }
11020 }
11021
11022 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11023 {
11024 struct intel_connector *connector;
11025 struct drm_device *dev = encoder->base.dev;
11026
11027 /* We need to check both for a crtc link (meaning that the
11028 * encoder is active and trying to read from a pipe) and the
11029 * pipe itself being active. */
11030 bool has_active_crtc = encoder->base.crtc &&
11031 to_intel_crtc(encoder->base.crtc)->active;
11032
11033 if (encoder->connectors_active && !has_active_crtc) {
11034 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11035 encoder->base.base.id,
11036 drm_get_encoder_name(&encoder->base));
11037
11038 /* Connector is active, but has no active pipe. This is
11039 * fallout from our resume register restoring. Disable
11040 * the encoder manually again. */
11041 if (encoder->base.crtc) {
11042 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11043 encoder->base.base.id,
11044 drm_get_encoder_name(&encoder->base));
11045 encoder->disable(encoder);
11046 }
11047
11048 /* Inconsistent output/port/pipe state happens presumably due to
11049 * a bug in one of the get_hw_state functions. Or someplace else
11050 * in our code, like the register restore mess on resume. Clamp
11051 * things to off as a safer default. */
11052 list_for_each_entry(connector,
11053 &dev->mode_config.connector_list,
11054 base.head) {
11055 if (connector->encoder != encoder)
11056 continue;
11057
11058 intel_connector_break_all_links(connector);
11059 }
11060 }
11061 /* Enabled encoders without active connectors will be fixed in
11062 * the crtc fixup. */
11063 }
11064
11065 void i915_redisable_vga(struct drm_device *dev)
11066 {
11067 struct drm_i915_private *dev_priv = dev->dev_private;
11068 u32 vga_reg = i915_vgacntrl_reg(dev);
11069
11070 /* This function can be called both from intel_modeset_setup_hw_state or
11071 * at a very early point in our resume sequence, where the power well
11072 * structures are not yet restored. Since this function is at a very
11073 * paranoid "someone might have enabled VGA while we were not looking"
11074 * level, just check if the power well is enabled instead of trying to
11075 * follow the "don't touch the power well if we don't need it" policy
11076 * the rest of the driver uses. */
11077 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11078 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11079 return;
11080
11081 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11082 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11083 i915_disable_vga(dev);
11084 }
11085 }
11086
11087 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11088 {
11089 struct drm_i915_private *dev_priv = dev->dev_private;
11090 enum pipe pipe;
11091 struct intel_crtc *crtc;
11092 struct intel_encoder *encoder;
11093 struct intel_connector *connector;
11094 int i;
11095
11096 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11097 base.head) {
11098 memset(&crtc->config, 0, sizeof(crtc->config));
11099
11100 crtc->active = dev_priv->display.get_pipe_config(crtc,
11101 &crtc->config);
11102
11103 crtc->base.enabled = crtc->active;
11104 crtc->primary_enabled = crtc->active;
11105
11106 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11107 crtc->base.base.id,
11108 crtc->active ? "enabled" : "disabled");
11109 }
11110
11111 /* FIXME: Smash this into the new shared dpll infrastructure. */
11112 if (HAS_DDI(dev))
11113 intel_ddi_setup_hw_pll_state(dev);
11114
11115 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11116 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11117
11118 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11119 pll->active = 0;
11120 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11121 base.head) {
11122 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11123 pll->active++;
11124 }
11125 pll->refcount = pll->active;
11126
11127 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11128 pll->name, pll->refcount, pll->on);
11129 }
11130
11131 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11132 base.head) {
11133 pipe = 0;
11134
11135 if (encoder->get_hw_state(encoder, &pipe)) {
11136 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11137 encoder->base.crtc = &crtc->base;
11138 encoder->get_config(encoder, &crtc->config);
11139 } else {
11140 encoder->base.crtc = NULL;
11141 }
11142
11143 encoder->connectors_active = false;
11144 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11145 encoder->base.base.id,
11146 drm_get_encoder_name(&encoder->base),
11147 encoder->base.crtc ? "enabled" : "disabled",
11148 pipe_name(pipe));
11149 }
11150
11151 list_for_each_entry(connector, &dev->mode_config.connector_list,
11152 base.head) {
11153 if (connector->get_hw_state(connector)) {
11154 connector->base.dpms = DRM_MODE_DPMS_ON;
11155 connector->encoder->connectors_active = true;
11156 connector->base.encoder = &connector->encoder->base;
11157 } else {
11158 connector->base.dpms = DRM_MODE_DPMS_OFF;
11159 connector->base.encoder = NULL;
11160 }
11161 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11162 connector->base.base.id,
11163 drm_get_connector_name(&connector->base),
11164 connector->base.encoder ? "enabled" : "disabled");
11165 }
11166 }
11167
11168 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11169 * and i915 state tracking structures. */
11170 void intel_modeset_setup_hw_state(struct drm_device *dev,
11171 bool force_restore)
11172 {
11173 struct drm_i915_private *dev_priv = dev->dev_private;
11174 enum pipe pipe;
11175 struct intel_crtc *crtc;
11176 struct intel_encoder *encoder;
11177 int i;
11178
11179 intel_modeset_readout_hw_state(dev);
11180
11181 /*
11182 * Now that we have the config, copy it to each CRTC struct
11183 * Note that this could go away if we move to using crtc_config
11184 * checking everywhere.
11185 */
11186 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11187 base.head) {
11188 if (crtc->active && i915_fastboot) {
11189 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11190
11191 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11192 crtc->base.base.id);
11193 drm_mode_debug_printmodeline(&crtc->base.mode);
11194 }
11195 }
11196
11197 /* HW state is read out, now we need to sanitize this mess. */
11198 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11199 base.head) {
11200 intel_sanitize_encoder(encoder);
11201 }
11202
11203 for_each_pipe(pipe) {
11204 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11205 intel_sanitize_crtc(crtc);
11206 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11207 }
11208
11209 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11210 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11211
11212 if (!pll->on || pll->active)
11213 continue;
11214
11215 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11216
11217 pll->disable(dev_priv, pll);
11218 pll->on = false;
11219 }
11220
11221 if (IS_HASWELL(dev))
11222 ilk_wm_get_hw_state(dev);
11223
11224 if (force_restore) {
11225 i915_redisable_vga(dev);
11226
11227 /*
11228 * We need to use raw interfaces for restoring state to avoid
11229 * checking (bogus) intermediate states.
11230 */
11231 for_each_pipe(pipe) {
11232 struct drm_crtc *crtc =
11233 dev_priv->pipe_to_crtc_mapping[pipe];
11234
11235 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11236 crtc->fb);
11237 }
11238 } else {
11239 intel_modeset_update_staged_output_state(dev);
11240 }
11241
11242 intel_modeset_check_state(dev);
11243
11244 drm_mode_config_reset(dev);
11245 }
11246
11247 void intel_modeset_gem_init(struct drm_device *dev)
11248 {
11249 intel_modeset_init_hw(dev);
11250
11251 intel_setup_overlay(dev);
11252
11253 intel_modeset_setup_hw_state(dev, false);
11254 }
11255
11256 void intel_modeset_cleanup(struct drm_device *dev)
11257 {
11258 struct drm_i915_private *dev_priv = dev->dev_private;
11259 struct drm_crtc *crtc;
11260 struct drm_connector *connector;
11261
11262 /*
11263 * Interrupts and polling as the first thing to avoid creating havoc.
11264 * Too much stuff here (turning of rps, connectors, ...) would
11265 * experience fancy races otherwise.
11266 */
11267 drm_irq_uninstall(dev);
11268 cancel_work_sync(&dev_priv->hotplug_work);
11269 /*
11270 * Due to the hpd irq storm handling the hotplug work can re-arm the
11271 * poll handlers. Hence disable polling after hpd handling is shut down.
11272 */
11273 drm_kms_helper_poll_fini(dev);
11274
11275 mutex_lock(&dev->struct_mutex);
11276
11277 intel_unregister_dsm_handler();
11278
11279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11280 /* Skip inactive CRTCs */
11281 if (!crtc->fb)
11282 continue;
11283
11284 intel_increase_pllclock(crtc);
11285 }
11286
11287 intel_disable_fbc(dev);
11288
11289 intel_disable_gt_powersave(dev);
11290
11291 ironlake_teardown_rc6(dev);
11292
11293 mutex_unlock(&dev->struct_mutex);
11294
11295 /* flush any delayed tasks or pending work */
11296 flush_scheduled_work();
11297
11298 /* destroy the backlight and sysfs files before encoders/connectors */
11299 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11300 intel_panel_destroy_backlight(connector);
11301 drm_sysfs_connector_remove(connector);
11302 }
11303
11304 drm_mode_config_cleanup(dev);
11305
11306 intel_cleanup_overlay(dev);
11307 }
11308
11309 /*
11310 * Return which encoder is currently attached for connector.
11311 */
11312 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11313 {
11314 return &intel_attached_encoder(connector)->base;
11315 }
11316
11317 void intel_connector_attach_encoder(struct intel_connector *connector,
11318 struct intel_encoder *encoder)
11319 {
11320 connector->encoder = encoder;
11321 drm_mode_connector_attach_encoder(&connector->base,
11322 &encoder->base);
11323 }
11324
11325 /*
11326 * set vga decode state - true == enable VGA decode
11327 */
11328 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11329 {
11330 struct drm_i915_private *dev_priv = dev->dev_private;
11331 u16 gmch_ctrl;
11332
11333 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11334 if (state)
11335 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11336 else
11337 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11338 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11339 return 0;
11340 }
11341
11342 struct intel_display_error_state {
11343
11344 u32 power_well_driver;
11345
11346 int num_transcoders;
11347
11348 struct intel_cursor_error_state {
11349 u32 control;
11350 u32 position;
11351 u32 base;
11352 u32 size;
11353 } cursor[I915_MAX_PIPES];
11354
11355 struct intel_pipe_error_state {
11356 bool power_domain_on;
11357 u32 source;
11358 } pipe[I915_MAX_PIPES];
11359
11360 struct intel_plane_error_state {
11361 u32 control;
11362 u32 stride;
11363 u32 size;
11364 u32 pos;
11365 u32 addr;
11366 u32 surface;
11367 u32 tile_offset;
11368 } plane[I915_MAX_PIPES];
11369
11370 struct intel_transcoder_error_state {
11371 bool power_domain_on;
11372 enum transcoder cpu_transcoder;
11373
11374 u32 conf;
11375
11376 u32 htotal;
11377 u32 hblank;
11378 u32 hsync;
11379 u32 vtotal;
11380 u32 vblank;
11381 u32 vsync;
11382 } transcoder[4];
11383 };
11384
11385 struct intel_display_error_state *
11386 intel_display_capture_error_state(struct drm_device *dev)
11387 {
11388 drm_i915_private_t *dev_priv = dev->dev_private;
11389 struct intel_display_error_state *error;
11390 int transcoders[] = {
11391 TRANSCODER_A,
11392 TRANSCODER_B,
11393 TRANSCODER_C,
11394 TRANSCODER_EDP,
11395 };
11396 int i;
11397
11398 if (INTEL_INFO(dev)->num_pipes == 0)
11399 return NULL;
11400
11401 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11402 if (error == NULL)
11403 return NULL;
11404
11405 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11406 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11407
11408 for_each_pipe(i) {
11409 error->pipe[i].power_domain_on =
11410 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11411 if (!error->pipe[i].power_domain_on)
11412 continue;
11413
11414 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11415 error->cursor[i].control = I915_READ(CURCNTR(i));
11416 error->cursor[i].position = I915_READ(CURPOS(i));
11417 error->cursor[i].base = I915_READ(CURBASE(i));
11418 } else {
11419 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11420 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11421 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11422 }
11423
11424 error->plane[i].control = I915_READ(DSPCNTR(i));
11425 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11426 if (INTEL_INFO(dev)->gen <= 3) {
11427 error->plane[i].size = I915_READ(DSPSIZE(i));
11428 error->plane[i].pos = I915_READ(DSPPOS(i));
11429 }
11430 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11431 error->plane[i].addr = I915_READ(DSPADDR(i));
11432 if (INTEL_INFO(dev)->gen >= 4) {
11433 error->plane[i].surface = I915_READ(DSPSURF(i));
11434 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11435 }
11436
11437 error->pipe[i].source = I915_READ(PIPESRC(i));
11438 }
11439
11440 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11441 if (HAS_DDI(dev_priv->dev))
11442 error->num_transcoders++; /* Account for eDP. */
11443
11444 for (i = 0; i < error->num_transcoders; i++) {
11445 enum transcoder cpu_transcoder = transcoders[i];
11446
11447 error->transcoder[i].power_domain_on =
11448 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11449 if (!error->transcoder[i].power_domain_on)
11450 continue;
11451
11452 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11453
11454 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11455 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11456 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11457 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11458 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11459 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11460 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11461 }
11462
11463 return error;
11464 }
11465
11466 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11467
11468 void
11469 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11470 struct drm_device *dev,
11471 struct intel_display_error_state *error)
11472 {
11473 int i;
11474
11475 if (!error)
11476 return;
11477
11478 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11479 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11480 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11481 error->power_well_driver);
11482 for_each_pipe(i) {
11483 err_printf(m, "Pipe [%d]:\n", i);
11484 err_printf(m, " Power: %s\n",
11485 error->pipe[i].power_domain_on ? "on" : "off");
11486 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11487
11488 err_printf(m, "Plane [%d]:\n", i);
11489 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11490 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11491 if (INTEL_INFO(dev)->gen <= 3) {
11492 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11493 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11494 }
11495 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11496 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11497 if (INTEL_INFO(dev)->gen >= 4) {
11498 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11499 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11500 }
11501
11502 err_printf(m, "Cursor [%d]:\n", i);
11503 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11504 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11505 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11506 }
11507
11508 for (i = 0; i < error->num_transcoders; i++) {
11509 err_printf(m, "CPU transcoder: %c\n",
11510 transcoder_name(error->transcoder[i].cpu_transcoder));
11511 err_printf(m, " Power: %s\n",
11512 error->transcoder[i].power_domain_on ? "on" : "off");
11513 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11514 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11515 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11516 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11517 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11518 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11519 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11520 }
11521 }
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