]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-hirsute-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'v3.9-rc5' into drm-intel-next-queued
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92 };
93
94 /* FDI */
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
97 int
98 intel_pch_rawclk(struct drm_device *dev)
99 {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105 }
106
107 static bool
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
111 static bool
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
116 static bool
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
120 static bool
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
124
125 static bool
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
132 {
133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
138 }
139
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
180 };
181
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
194 };
195
196
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
225 };
226
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
238 },
239 .find_pll = intel_g4x_find_best_PLL,
240 };
241
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
253 },
254 .find_pll = intel_g4x_find_best_PLL,
255 };
256
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
299 };
300
301 /* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
375 };
376
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
389 };
390
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403 };
404
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
407 .vco = { .min = 4000000, .max = 5994000},
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417 };
418
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431 };
432
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434 {
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
436
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
439 return 0;
440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
447 return 0;
448 }
449
450 return I915_READ(DPIO_DATA);
451 }
452
453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455 {
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
457
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
460 return;
461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
469 }
470
471 static void vlv_init_dpio(struct drm_device *dev)
472 {
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480 }
481
482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
484 {
485 struct drm_device *dev = crtc->dev;
486 const intel_limit_t *limit;
487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
489 if (intel_is_dual_link_lvds(dev)) {
490 if (refclk == 100000)
491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
495 if (refclk == 100000)
496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
502 limit = &intel_limits_ironlake_display_port;
503 else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510 {
511 struct drm_device *dev = crtc->dev;
512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
515 if (intel_is_dual_link_lvds(dev))
516 limit = &intel_limits_g4x_dual_channel_lvds;
517 else
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
528
529 return limit;
530 }
531
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
533 {
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
537 if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
544 else
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
560 limit = &intel_limits_i8xx_lvds;
561 else
562 limit = &intel_limits_i8xx_dvo;
563 }
564 return limit;
565 }
566
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk, intel_clock_t *clock)
569 {
570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574 }
575
576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577 {
578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
580 return;
581 }
582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586 }
587
588 /**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
592 {
593 struct drm_device *dev = crtc->dev;
594 struct intel_encoder *encoder;
595
596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
598 return true;
599
600 return false;
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604 /**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
612 {
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->p < limit->p.min || limit->p.max < clock->p)
616 INTELPllInvalid("p out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 if (clock->n < limit->n.min || limit->n.max < clock->n)
626 INTELPllInvalid("n out of range\n");
627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633 INTELPllInvalid("dot out of range\n");
634
635 return true;
636 }
637
638 static bool
639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642
643 {
644 struct drm_device *dev = crtc->dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err;
679
680 intel_clock(dev, refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
683 continue;
684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699 }
700
701 static bool
702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct drm_device *dev = crtc->dev;
707 intel_clock_t clock;
708 int max_n;
709 bool found;
710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
715 int lvds_reg;
716
717 if (HAS_PCH_SPLIT(dev))
718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
745 intel_clock(dev, refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
764 return found;
765 }
766
767 static bool
768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
774
775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791 }
792
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
794 static bool
795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
798 {
799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
819 }
820 static bool
821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824 {
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
831 flag = 0;
832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887 }
888
889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891 {
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896 }
897
898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899 {
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907 }
908
909 /**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 int pipestat_reg = PIPESTAT(pipe);
921
922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
947 DRM_DEBUG_KMS("vblank wait timed out\n");
948 }
949
950 /*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
965 *
966 */
967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
968 {
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
972
973 if (INTEL_INFO(dev)->gen >= 4) {
974 int reg = PIPECONF(cpu_transcoder);
975
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
979 WARN(1, "pipe_off wait timed out\n");
980 } else {
981 u32 last_line, line_mask;
982 int reg = PIPEDSL(pipe);
983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 /* Wait for the display line to settle */
991 do {
992 last_line = I915_READ(reg) & line_mask;
993 mdelay(5);
994 } while (((I915_READ(reg) & line_mask) != last_line) &&
995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
997 WARN(1, "pipe_off wait timed out\n");
998 }
999 }
1000
1001 /*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010 {
1011 u32 bit;
1012
1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044 }
1045
1046 static const char *state_string(bool enabled)
1047 {
1048 return enabled ? "on" : "off";
1049 }
1050
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054 {
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065 }
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
1069 /* For ILK+ */
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085 return;
1086
1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
1110 }
1111 }
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
1123
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1170 return;
1171
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179 {
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
1194 bool locked = true;
1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1214 pipe_name(pipe));
1215 }
1216
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 int reg;
1221 u32 val;
1222 bool cur_state;
1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
1225
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
1276 return;
1277 }
1278
1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
1288 }
1289 }
1290
1291 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308 }
1309
1310 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311 {
1312 u32 val;
1313 bool enabled;
1314
1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324 }
1325
1326 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328 {
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
1339 }
1340
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
1343 {
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357 }
1358
1359 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361 {
1362 if ((val & SDVO_ENABLE) == 0)
1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1367 return false;
1368 } else {
1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1370 return false;
1371 }
1372 return true;
1373 }
1374
1375 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377 {
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389 }
1390
1391 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393 {
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, int reg, u32 port_sel)
1408 {
1409 u32 val = I915_READ(reg);
1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412 reg, pipe_name(pipe));
1413
1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
1416 "IBX PCH dp port still using transcoder B\n");
1417 }
1418
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421 {
1422 u32 val = I915_READ(reg);
1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425 reg, pipe_name(pipe));
1426
1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1428 && (val & SDVO_PIPE_B_SELECT),
1429 "IBX PCH hdmi port still using transcoder B\n");
1430 }
1431
1432 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434 {
1435 int reg;
1436 u32 val;
1437
1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
1446 pipe_name(pipe));
1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1452 pipe_name(pipe));
1453
1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1457 }
1458
1459 /**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1471 */
1472 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498 }
1499
1500 /**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510 {
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526 }
1527
1528 /* SBI access */
1529 static void
1530 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
1532 {
1533 u32 tmp;
1534
1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1536
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540 return;
1541 }
1542
1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1551
1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1555 return;
1556 }
1557 }
1558
1559 static u32
1560 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
1562 {
1563 u32 value = 0;
1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1565
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
1569 return 0;
1570 }
1571
1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1579
1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1583 return 0;
1584 }
1585
1586 return I915_READ(SBI_DATA);
1587 }
1588
1589 /**
1590 * ironlake_enable_pch_pll - enable PCH PLL
1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
1597 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1598 {
1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1600 struct intel_pch_pll *pll;
1601 int reg;
1602 u32 val;
1603
1604 /* PCH PLLs only available on ILK, SNB and IVB */
1605 BUG_ON(dev_priv->info->gen < 5);
1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
1620 if (pll->active++ && pll->on) {
1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
1633
1634 pll->on = true;
1635 }
1636
1637 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1638 {
1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1641 int reg;
1642 u32 val;
1643
1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
1646 if (pll == NULL)
1647 return;
1648
1649 if (WARN_ON(pll->refcount == 0))
1650 return;
1651
1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
1655
1656 if (WARN_ON(pll->active == 0)) {
1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
1658 return;
1659 }
1660
1661 if (--pll->active) {
1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
1663 return;
1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1670
1671 reg = pll->pll_reg;
1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
1677
1678 pll->on = false;
1679 }
1680
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
1683 {
1684 struct drm_device *dev = dev_priv->dev;
1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1686 uint32_t reg, val, pipeconf_val;
1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
1707 }
1708
1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
1711 pipeconf_val = I915_READ(PIPECONF(pipe));
1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
1720 }
1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735 }
1736
1737 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1738 enum transcoder cpu_transcoder)
1739 {
1740 u32 val, pipeconf_val;
1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
1745 /* FDI must be feeding us bits for PCH ports */
1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1748
1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
1754 val = TRANS_ENABLE;
1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1756
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
1759 val |= TRANS_INTERLACED;
1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
1766 }
1767
1768 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
1770 {
1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
1796 }
1797
1798 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1799 {
1800 u32 val;
1801
1802 val = I915_READ(_TRANSACONF);
1803 val &= ~TRANS_ENABLE;
1804 I915_WRITE(_TRANSACONF, val);
1805 /* wait for PCH transcoder off, transcoder state */
1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1812 I915_WRITE(_TRANSA_CHICKEN2, val);
1813 }
1814
1815 /**
1816 * intel_enable_pipe - enable a pipe, asserting requirements
1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
1829 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
1831 {
1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1834 enum pipe pch_transcoder;
1835 int reg;
1836 u32 val;
1837
1838 if (HAS_PCH_LPT(dev_priv->dev))
1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
1859
1860 reg = PIPECONF(cpu_transcoder);
1861 val = I915_READ(reg);
1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 /**
1870 * intel_disable_pipe - disable a pipe, asserting requirements
1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883 {
1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
1894 assert_sprites_disabled(dev_priv, pipe);
1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
1900 reg = PIPECONF(cpu_transcoder);
1901 val = I915_READ(reg);
1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907 }
1908
1909 /*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
1913 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane)
1915 {
1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1920 }
1921
1922 /**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932 {
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1945 intel_flush_display_plane(dev_priv, plane);
1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947 }
1948
1949 /**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959 {
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971 }
1972
1973 static bool need_vtd_wa(struct drm_device *dev)
1974 {
1975 #ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978 #endif
1979 return false;
1980 }
1981
1982 int
1983 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1984 struct drm_i915_gem_object *obj,
1985 struct intel_ring_buffer *pipelined)
1986 {
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 u32 alignment;
1989 int ret;
1990
1991 switch (obj->tiling_mode) {
1992 case I915_TILING_NONE:
1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
1995 else if (INTEL_INFO(dev)->gen >= 4)
1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
2005 /* FIXME: Is this true? */
2006 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007 return -EINVAL;
2008 default:
2009 BUG();
2010 }
2011
2012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2015 * the VT-d warning.
2016 */
2017 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018 alignment = 256 * 1024;
2019
2020 dev_priv->mm.interruptible = false;
2021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2022 if (ret)
2023 goto err_interruptible;
2024
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2029 */
2030 ret = i915_gem_object_get_fence(obj);
2031 if (ret)
2032 goto err_unpin;
2033
2034 i915_gem_object_pin_fence(obj);
2035
2036 dev_priv->mm.interruptible = true;
2037 return 0;
2038
2039 err_unpin:
2040 i915_gem_object_unpin(obj);
2041 err_interruptible:
2042 dev_priv->mm.interruptible = true;
2043 return ret;
2044 }
2045
2046 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2047 {
2048 i915_gem_object_unpin_fence(obj);
2049 i915_gem_object_unpin(obj);
2050 }
2051
2052 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053 * is assumed to be a power-of-two. */
2054 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2055 unsigned int tiling_mode,
2056 unsigned int cpp,
2057 unsigned int pitch)
2058 {
2059 if (tiling_mode != I915_TILING_NONE) {
2060 unsigned int tile_rows, tiles;
2061
2062 tile_rows = *y / 8;
2063 *y %= 8;
2064
2065 tiles = *x / (512/cpp);
2066 *x %= 512/cpp;
2067
2068 return tile_rows * pitch * 8 + tiles * 4096;
2069 } else {
2070 unsigned int offset;
2071
2072 offset = *y * pitch + *x * cpp;
2073 *y = 0;
2074 *x = (offset & 4095) / cpp;
2075 return offset & -4096;
2076 }
2077 }
2078
2079 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
2081 {
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long linear_offset;
2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
2103
2104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2108 switch (fb->pixel_format) {
2109 case DRM_FORMAT_C8:
2110 dspcntr |= DISPPLANE_8BPP;
2111 break;
2112 case DRM_FORMAT_XRGB1555:
2113 case DRM_FORMAT_ARGB1555:
2114 dspcntr |= DISPPLANE_BGRX555;
2115 break;
2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
2118 break;
2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
2134 break;
2135 default:
2136 BUG();
2137 }
2138
2139 if (INTEL_INFO(dev)->gen >= 4) {
2140 if (obj->tiling_mode != I915_TILING_NONE)
2141 dspcntr |= DISPPLANE_TILED;
2142 else
2143 dspcntr &= ~DISPPLANE_TILED;
2144 }
2145
2146 I915_WRITE(reg, dspcntr);
2147
2148 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2149
2150 if (INTEL_INFO(dev)->gen >= 4) {
2151 intel_crtc->dspaddr_offset =
2152 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2153 fb->bits_per_pixel / 8,
2154 fb->pitches[0]);
2155 linear_offset -= intel_crtc->dspaddr_offset;
2156 } else {
2157 intel_crtc->dspaddr_offset = linear_offset;
2158 }
2159
2160 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2162 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2163 if (INTEL_INFO(dev)->gen >= 4) {
2164 I915_MODIFY_DISPBASE(DSPSURF(plane),
2165 obj->gtt_offset + intel_crtc->dspaddr_offset);
2166 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2167 I915_WRITE(DSPLINOFF(plane), linear_offset);
2168 } else
2169 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2170 POSTING_READ(reg);
2171
2172 return 0;
2173 }
2174
2175 static int ironlake_update_plane(struct drm_crtc *crtc,
2176 struct drm_framebuffer *fb, int x, int y)
2177 {
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 struct intel_framebuffer *intel_fb;
2182 struct drm_i915_gem_object *obj;
2183 int plane = intel_crtc->plane;
2184 unsigned long linear_offset;
2185 u32 dspcntr;
2186 u32 reg;
2187
2188 switch (plane) {
2189 case 0:
2190 case 1:
2191 case 2:
2192 break;
2193 default:
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 return -EINVAL;
2196 }
2197
2198 intel_fb = to_intel_framebuffer(fb);
2199 obj = intel_fb->obj;
2200
2201 reg = DSPCNTR(plane);
2202 dspcntr = I915_READ(reg);
2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2205 switch (fb->pixel_format) {
2206 case DRM_FORMAT_C8:
2207 dspcntr |= DISPPLANE_8BPP;
2208 break;
2209 case DRM_FORMAT_RGB565:
2210 dspcntr |= DISPPLANE_BGRX565;
2211 break;
2212 case DRM_FORMAT_XRGB8888:
2213 case DRM_FORMAT_ARGB8888:
2214 dspcntr |= DISPPLANE_BGRX888;
2215 break;
2216 case DRM_FORMAT_XBGR8888:
2217 case DRM_FORMAT_ABGR8888:
2218 dspcntr |= DISPPLANE_RGBX888;
2219 break;
2220 case DRM_FORMAT_XRGB2101010:
2221 case DRM_FORMAT_ARGB2101010:
2222 dspcntr |= DISPPLANE_BGRX101010;
2223 break;
2224 case DRM_FORMAT_XBGR2101010:
2225 case DRM_FORMAT_ABGR2101010:
2226 dspcntr |= DISPPLANE_RGBX101010;
2227 break;
2228 default:
2229 BUG();
2230 }
2231
2232 if (obj->tiling_mode != I915_TILING_NONE)
2233 dspcntr |= DISPPLANE_TILED;
2234 else
2235 dspcntr &= ~DISPPLANE_TILED;
2236
2237 /* must disable */
2238 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2239
2240 I915_WRITE(reg, dspcntr);
2241
2242 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2243 intel_crtc->dspaddr_offset =
2244 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2245 fb->bits_per_pixel / 8,
2246 fb->pitches[0]);
2247 linear_offset -= intel_crtc->dspaddr_offset;
2248
2249 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2251 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2252 I915_MODIFY_DISPBASE(DSPSURF(plane),
2253 obj->gtt_offset + intel_crtc->dspaddr_offset);
2254 if (IS_HASWELL(dev)) {
2255 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2256 } else {
2257 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2258 I915_WRITE(DSPLINOFF(plane), linear_offset);
2259 }
2260 POSTING_READ(reg);
2261
2262 return 0;
2263 }
2264
2265 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2266 static int
2267 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2268 int x, int y, enum mode_set_atomic state)
2269 {
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273 if (dev_priv->display.disable_fbc)
2274 dev_priv->display.disable_fbc(dev);
2275 intel_increase_pllclock(crtc);
2276
2277 return dev_priv->display.update_plane(crtc, fb, x, y);
2278 }
2279
2280 void intel_display_handle_reset(struct drm_device *dev)
2281 {
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_crtc *crtc;
2284
2285 /*
2286 * Flips in the rings have been nuked by the reset,
2287 * so complete all pending flips so that user space
2288 * will get its events and not get stuck.
2289 *
2290 * Also update the base address of all primary
2291 * planes to the the last fb to make sure we're
2292 * showing the correct fb after a reset.
2293 *
2294 * Need to make two loops over the crtcs so that we
2295 * don't try to grab a crtc mutex before the
2296 * pending_flip_queue really got woken up.
2297 */
2298
2299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 enum plane plane = intel_crtc->plane;
2302
2303 intel_prepare_page_flip(dev, plane);
2304 intel_finish_page_flip_plane(dev, plane);
2305 }
2306
2307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
2310 mutex_lock(&crtc->mutex);
2311 if (intel_crtc->active)
2312 dev_priv->display.update_plane(crtc, crtc->fb,
2313 crtc->x, crtc->y);
2314 mutex_unlock(&crtc->mutex);
2315 }
2316 }
2317
2318 static int
2319 intel_finish_fb(struct drm_framebuffer *old_fb)
2320 {
2321 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323 bool was_interruptible = dev_priv->mm.interruptible;
2324 int ret;
2325
2326 /* Big Hammer, we also need to ensure that any pending
2327 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328 * current scanout is retired before unpinning the old
2329 * framebuffer.
2330 *
2331 * This should only fail upon a hung GPU, in which case we
2332 * can safely continue.
2333 */
2334 dev_priv->mm.interruptible = false;
2335 ret = i915_gem_object_finish_gpu(obj);
2336 dev_priv->mm.interruptible = was_interruptible;
2337
2338 return ret;
2339 }
2340
2341 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2342 {
2343 struct drm_device *dev = crtc->dev;
2344 struct drm_i915_master_private *master_priv;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346
2347 if (!dev->primary->master)
2348 return;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return;
2353
2354 switch (intel_crtc->pipe) {
2355 case 0:
2356 master_priv->sarea_priv->pipeA_x = x;
2357 master_priv->sarea_priv->pipeA_y = y;
2358 break;
2359 case 1:
2360 master_priv->sarea_priv->pipeB_x = x;
2361 master_priv->sarea_priv->pipeB_y = y;
2362 break;
2363 default:
2364 break;
2365 }
2366 }
2367
2368 static int
2369 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2370 struct drm_framebuffer *fb)
2371 {
2372 struct drm_device *dev = crtc->dev;
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375 struct drm_framebuffer *old_fb;
2376 int ret;
2377
2378 /* no fb bound */
2379 if (!fb) {
2380 DRM_ERROR("No FB bound\n");
2381 return 0;
2382 }
2383
2384 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2385 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2386 intel_crtc->plane,
2387 INTEL_INFO(dev)->num_pipes);
2388 return -EINVAL;
2389 }
2390
2391 mutex_lock(&dev->struct_mutex);
2392 ret = intel_pin_and_fence_fb_obj(dev,
2393 to_intel_framebuffer(fb)->obj,
2394 NULL);
2395 if (ret != 0) {
2396 mutex_unlock(&dev->struct_mutex);
2397 DRM_ERROR("pin & fence failed\n");
2398 return ret;
2399 }
2400
2401 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2402 if (ret) {
2403 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2404 mutex_unlock(&dev->struct_mutex);
2405 DRM_ERROR("failed to update base address\n");
2406 return ret;
2407 }
2408
2409 old_fb = crtc->fb;
2410 crtc->fb = fb;
2411 crtc->x = x;
2412 crtc->y = y;
2413
2414 if (old_fb) {
2415 intel_wait_for_vblank(dev, intel_crtc->pipe);
2416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2417 }
2418
2419 intel_update_fbc(dev);
2420 mutex_unlock(&dev->struct_mutex);
2421
2422 intel_crtc_update_sarea_pos(crtc, x, y);
2423
2424 return 0;
2425 }
2426
2427 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2428 {
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 int pipe = intel_crtc->pipe;
2433 u32 reg, temp;
2434
2435 /* enable normal train */
2436 reg = FDI_TX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 if (IS_IVYBRIDGE(dev)) {
2439 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2440 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2441 } else {
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2444 }
2445 I915_WRITE(reg, temp);
2446
2447 reg = FDI_RX_CTL(pipe);
2448 temp = I915_READ(reg);
2449 if (HAS_PCH_CPT(dev)) {
2450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2452 } else {
2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_NONE;
2455 }
2456 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2457
2458 /* wait one idle pattern time */
2459 POSTING_READ(reg);
2460 udelay(1000);
2461
2462 /* IVB wants error correction enabled */
2463 if (IS_IVYBRIDGE(dev))
2464 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2465 FDI_FE_ERRC_ENABLE);
2466 }
2467
2468 static void ivb_modeset_global_resources(struct drm_device *dev)
2469 {
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
2477 /* When everything is off disable fdi C so that we could enable fdi B
2478 * with all lanes. XXX: This misses the case where a pipe is not using
2479 * any pch resources and so doesn't need any fdi lanes. */
2480 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2482 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2483
2484 temp = I915_READ(SOUTH_CHICKEN1);
2485 temp &= ~FDI_BC_BIFURCATION_SELECT;
2486 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487 I915_WRITE(SOUTH_CHICKEN1, temp);
2488 }
2489 }
2490
2491 /* The FDI link training functions for ILK/Ibexpeak. */
2492 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2493 {
2494 struct drm_device *dev = crtc->dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497 int pipe = intel_crtc->pipe;
2498 int plane = intel_crtc->plane;
2499 u32 reg, temp, tries;
2500
2501 /* FDI needs bits from pipe & plane first */
2502 assert_pipe_enabled(dev_priv, pipe);
2503 assert_plane_enabled(dev_priv, plane);
2504
2505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506 for train result */
2507 reg = FDI_RX_IMR(pipe);
2508 temp = I915_READ(reg);
2509 temp &= ~FDI_RX_SYMBOL_LOCK;
2510 temp &= ~FDI_RX_BIT_LOCK;
2511 I915_WRITE(reg, temp);
2512 I915_READ(reg);
2513 udelay(150);
2514
2515 /* enable CPU FDI TX and PCH FDI RX */
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~(7 << 19);
2519 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1;
2522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2523
2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1;
2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
2531 udelay(150);
2532
2533 /* Ironlake workaround, enable clock pointer after FDI enable*/
2534 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2535 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2536 FDI_RX_PHASE_SYNC_POINTER_EN);
2537
2538 reg = FDI_RX_IIR(pipe);
2539 for (tries = 0; tries < 5; tries++) {
2540 temp = I915_READ(reg);
2541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2542
2543 if ((temp & FDI_RX_BIT_LOCK)) {
2544 DRM_DEBUG_KMS("FDI train 1 done.\n");
2545 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2546 break;
2547 }
2548 }
2549 if (tries == 5)
2550 DRM_ERROR("FDI train 1 fail!\n");
2551
2552 /* Train 2 */
2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
2557 I915_WRITE(reg, temp);
2558
2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
2561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 reg = FDI_RX_IIR(pipe);
2569 for (tries = 0; tries < 5; tries++) {
2570 temp = I915_READ(reg);
2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
2574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2576 break;
2577 }
2578 }
2579 if (tries == 5)
2580 DRM_ERROR("FDI train 2 fail!\n");
2581
2582 DRM_DEBUG_KMS("FDI train done\n");
2583
2584 }
2585
2586 static const int snb_b_fdi_train_param[] = {
2587 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2588 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2589 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2590 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2591 };
2592
2593 /* The FDI link training functions for SNB/Cougarpoint. */
2594 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2595 {
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
2600 u32 reg, temp, i, retry;
2601
2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603 for train result */
2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
2611 udelay(150);
2612
2613 /* enable CPU FDI TX and PCH FDI RX */
2614 reg = FDI_TX_CTL(pipe);
2615 temp = I915_READ(reg);
2616 temp &= ~(7 << 19);
2617 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_1;
2620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621 /* SNB-B */
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624
2625 I915_WRITE(FDI_RX_MISC(pipe),
2626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 if (HAS_PCH_CPT(dev)) {
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633 } else {
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1;
2636 }
2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
2640 udelay(150);
2641
2642 for (i = 0; i < 4; i++) {
2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(500);
2651
2652 for (retry = 0; retry < 5; retry++) {
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656 if (temp & FDI_RX_BIT_LOCK) {
2657 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2659 break;
2660 }
2661 udelay(50);
2662 }
2663 if (retry < 5)
2664 break;
2665 }
2666 if (i == 4)
2667 DRM_ERROR("FDI train 1 fail!\n");
2668
2669 /* Train 2 */
2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_NONE;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2;
2674 if (IS_GEN6(dev)) {
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 /* SNB-B */
2677 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678 }
2679 I915_WRITE(reg, temp);
2680
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 if (HAS_PCH_CPT(dev)) {
2684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2686 } else {
2687 temp &= ~FDI_LINK_TRAIN_NONE;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2;
2689 }
2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
2693 udelay(150);
2694
2695 for (i = 0; i < 4; i++) {
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
2700 I915_WRITE(reg, temp);
2701
2702 POSTING_READ(reg);
2703 udelay(500);
2704
2705 for (retry = 0; retry < 5; retry++) {
2706 reg = FDI_RX_IIR(pipe);
2707 temp = I915_READ(reg);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712 break;
2713 }
2714 udelay(50);
2715 }
2716 if (retry < 5)
2717 break;
2718 }
2719 if (i == 4)
2720 DRM_ERROR("FDI train 2 fail!\n");
2721
2722 DRM_DEBUG_KMS("FDI train done.\n");
2723 }
2724
2725 /* Manual link training for Ivy Bridge A0 parts */
2726 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2727 {
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp, i;
2733
2734 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2735 for train result */
2736 reg = FDI_RX_IMR(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_RX_SYMBOL_LOCK;
2739 temp &= ~FDI_RX_BIT_LOCK;
2740 I915_WRITE(reg, temp);
2741
2742 POSTING_READ(reg);
2743 udelay(150);
2744
2745 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746 I915_READ(FDI_RX_IIR(pipe)));
2747
2748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(7 << 19);
2752 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2753 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2754 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2757 temp |= FDI_COMPOSITE_SYNC;
2758 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759
2760 I915_WRITE(FDI_RX_MISC(pipe),
2761 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~FDI_LINK_TRAIN_AUTO;
2766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2768 temp |= FDI_COMPOSITE_SYNC;
2769 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(150);
2773
2774 for (i = 0; i < 4; i++) {
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778 temp |= snb_b_fdi_train_param[i];
2779 I915_WRITE(reg, temp);
2780
2781 POSTING_READ(reg);
2782 udelay(500);
2783
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788 if (temp & FDI_RX_BIT_LOCK ||
2789 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2792 break;
2793 }
2794 }
2795 if (i == 4)
2796 DRM_ERROR("FDI train 1 fail!\n");
2797
2798 /* Train 2 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2802 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2803 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2804 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2805 I915_WRITE(reg, temp);
2806
2807 reg = FDI_RX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2811 I915_WRITE(reg, temp);
2812
2813 POSTING_READ(reg);
2814 udelay(150);
2815
2816 for (i = 0; i < 4; i++) {
2817 reg = FDI_TX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2820 temp |= snb_b_fdi_train_param[i];
2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(500);
2825
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830 if (temp & FDI_RX_SYMBOL_LOCK) {
2831 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2832 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2833 break;
2834 }
2835 }
2836 if (i == 4)
2837 DRM_ERROR("FDI train 2 fail!\n");
2838
2839 DRM_DEBUG_KMS("FDI train done.\n");
2840 }
2841
2842 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2843 {
2844 struct drm_device *dev = intel_crtc->base.dev;
2845 struct drm_i915_private *dev_priv = dev->dev_private;
2846 int pipe = intel_crtc->pipe;
2847 u32 reg, temp;
2848
2849
2850 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~((0x7 << 19) | (0x7 << 16));
2854 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2856 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2857
2858 POSTING_READ(reg);
2859 udelay(200);
2860
2861 /* Switch from Rawclk to PCDclk */
2862 temp = I915_READ(reg);
2863 I915_WRITE(reg, temp | FDI_PCDCLK);
2864
2865 POSTING_READ(reg);
2866 udelay(200);
2867
2868 /* Enable CPU FDI TX PLL, always on for Ironlake */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2872 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2873
2874 POSTING_READ(reg);
2875 udelay(100);
2876 }
2877 }
2878
2879 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880 {
2881 struct drm_device *dev = intel_crtc->base.dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 int pipe = intel_crtc->pipe;
2884 u32 reg, temp;
2885
2886 /* Switch from PCDclk to Rawclk */
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890
2891 /* Disable CPU FDI TX PLL */
2892 reg = FDI_TX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2895
2896 POSTING_READ(reg);
2897 udelay(100);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902
2903 /* Wait for the clocks to turn off. */
2904 POSTING_READ(reg);
2905 udelay(100);
2906 }
2907
2908 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909 {
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913 int pipe = intel_crtc->pipe;
2914 u32 reg, temp;
2915
2916 /* disable CPU FDI tx and PCH FDI rx */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2920 POSTING_READ(reg);
2921
2922 reg = FDI_RX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~(0x7 << 16);
2925 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2926 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2927
2928 POSTING_READ(reg);
2929 udelay(100);
2930
2931 /* Ironlake workaround, disable clock pointer after downing FDI */
2932 if (HAS_PCH_IBX(dev)) {
2933 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2934 }
2935
2936 /* still set train pattern 1 */
2937 reg = FDI_TX_CTL(pipe);
2938 temp = I915_READ(reg);
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 I915_WRITE(reg, temp);
2942
2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 if (HAS_PCH_CPT(dev)) {
2946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 } else {
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 }
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp &= ~(0x07 << 16);
2954 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959 }
2960
2961 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962 {
2963 struct drm_device *dev = crtc->dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2966 unsigned long flags;
2967 bool pending;
2968
2969 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2970 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2971 return false;
2972
2973 spin_lock_irqsave(&dev->event_lock, flags);
2974 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2975 spin_unlock_irqrestore(&dev->event_lock, flags);
2976
2977 return pending;
2978 }
2979
2980 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981 {
2982 struct drm_device *dev = crtc->dev;
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984
2985 if (crtc->fb == NULL)
2986 return;
2987
2988 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989
2990 wait_event(dev_priv->pending_flip_queue,
2991 !intel_crtc_has_pending_flip(crtc));
2992
2993 mutex_lock(&dev->struct_mutex);
2994 intel_finish_fb(crtc->fb);
2995 mutex_unlock(&dev->struct_mutex);
2996 }
2997
2998 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999 {
3000 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001 }
3002
3003 /* Program iCLKIP clock to the desired frequency */
3004 static void lpt_program_iclkip(struct drm_crtc *crtc)
3005 {
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009 u32 temp;
3010
3011 mutex_lock(&dev_priv->dpio_lock);
3012
3013 /* It is necessary to ungate the pixclk gate prior to programming
3014 * the divisors, and gate it back when it is done.
3015 */
3016 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3017
3018 /* Disable SSCCTL */
3019 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3020 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3021 SBI_SSCCTL_DISABLE,
3022 SBI_ICLK);
3023
3024 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3025 if (crtc->mode.clock == 20000) {
3026 auxdiv = 1;
3027 divsel = 0x41;
3028 phaseinc = 0x20;
3029 } else {
3030 /* The iCLK virtual clock root frequency is in MHz,
3031 * but the crtc->mode.clock in in KHz. To get the divisors,
3032 * it is necessary to divide one by another, so we
3033 * convert the virtual clock precision to KHz here for higher
3034 * precision.
3035 */
3036 u32 iclk_virtual_root_freq = 172800 * 1000;
3037 u32 iclk_pi_range = 64;
3038 u32 desired_divisor, msb_divisor_value, pi_value;
3039
3040 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3041 msb_divisor_value = desired_divisor / iclk_pi_range;
3042 pi_value = desired_divisor % iclk_pi_range;
3043
3044 auxdiv = 0;
3045 divsel = msb_divisor_value - 2;
3046 phaseinc = pi_value;
3047 }
3048
3049 /* This should not happen with any sane values */
3050 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3051 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3052 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3053 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3054
3055 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3056 crtc->mode.clock,
3057 auxdiv,
3058 divsel,
3059 phasedir,
3060 phaseinc);
3061
3062 /* Program SSCDIVINTPHASE6 */
3063 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3064 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3065 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3066 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3067 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3068 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3069 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3070 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3071
3072 /* Program SSCAUXDIV */
3073 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3074 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3076 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3077
3078 /* Enable modulator and associated divider */
3079 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3080 temp &= ~SBI_SSCCTL_DISABLE;
3081 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3082
3083 /* Wait for initialization time */
3084 udelay(24);
3085
3086 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3087
3088 mutex_unlock(&dev_priv->dpio_lock);
3089 }
3090
3091 /*
3092 * Enable PCH resources required for PCH ports:
3093 * - PCH PLLs
3094 * - FDI training & RX/TX
3095 * - update transcoder timings
3096 * - DP transcoding bits
3097 * - transcoder
3098 */
3099 static void ironlake_pch_enable(struct drm_crtc *crtc)
3100 {
3101 struct drm_device *dev = crtc->dev;
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104 int pipe = intel_crtc->pipe;
3105 u32 reg, temp;
3106
3107 assert_transcoder_disabled(dev_priv, pipe);
3108
3109 /* Write the TU size bits before fdi link training, so that error
3110 * detection works. */
3111 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3112 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3113
3114 /* For PCH output, training FDI link */
3115 dev_priv->display.fdi_link_train(crtc);
3116
3117 /* XXX: pch pll's can be enabled any time before we enable the PCH
3118 * transcoder, and we actually should do this to not upset any PCH
3119 * transcoder that already use the clock when we share it.
3120 *
3121 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3122 * unconditionally resets the pll - we need that to have the right LVDS
3123 * enable sequence. */
3124 ironlake_enable_pch_pll(intel_crtc);
3125
3126 if (HAS_PCH_CPT(dev)) {
3127 u32 sel;
3128
3129 temp = I915_READ(PCH_DPLL_SEL);
3130 switch (pipe) {
3131 default:
3132 case 0:
3133 temp |= TRANSA_DPLL_ENABLE;
3134 sel = TRANSA_DPLLB_SEL;
3135 break;
3136 case 1:
3137 temp |= TRANSB_DPLL_ENABLE;
3138 sel = TRANSB_DPLLB_SEL;
3139 break;
3140 case 2:
3141 temp |= TRANSC_DPLL_ENABLE;
3142 sel = TRANSC_DPLLB_SEL;
3143 break;
3144 }
3145 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3146 temp |= sel;
3147 else
3148 temp &= ~sel;
3149 I915_WRITE(PCH_DPLL_SEL, temp);
3150 }
3151
3152 /* set transcoder timing, panel must allow it */
3153 assert_panel_unlocked(dev_priv, pipe);
3154 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3155 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3156 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3157
3158 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3159 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3160 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3161 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3162
3163 intel_fdi_normal_train(crtc);
3164
3165 /* For PCH DP, enable TRANS_DP_CTL */
3166 if (HAS_PCH_CPT(dev) &&
3167 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3168 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3169 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3170 reg = TRANS_DP_CTL(pipe);
3171 temp = I915_READ(reg);
3172 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3173 TRANS_DP_SYNC_MASK |
3174 TRANS_DP_BPC_MASK);
3175 temp |= (TRANS_DP_OUTPUT_ENABLE |
3176 TRANS_DP_ENH_FRAMING);
3177 temp |= bpc << 9; /* same format but at 11:9 */
3178
3179 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3180 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3181 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3182 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3183
3184 switch (intel_trans_dp_port_sel(crtc)) {
3185 case PCH_DP_B:
3186 temp |= TRANS_DP_PORT_SEL_B;
3187 break;
3188 case PCH_DP_C:
3189 temp |= TRANS_DP_PORT_SEL_C;
3190 break;
3191 case PCH_DP_D:
3192 temp |= TRANS_DP_PORT_SEL_D;
3193 break;
3194 default:
3195 BUG();
3196 }
3197
3198 I915_WRITE(reg, temp);
3199 }
3200
3201 ironlake_enable_pch_transcoder(dev_priv, pipe);
3202 }
3203
3204 static void lpt_pch_enable(struct drm_crtc *crtc)
3205 {
3206 struct drm_device *dev = crtc->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3209 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3210
3211 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3212
3213 lpt_program_iclkip(crtc);
3214
3215 /* Set transcoder timing. */
3216 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3217 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3218 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3219
3220 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3221 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3222 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3223 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3224
3225 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3226 }
3227
3228 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3229 {
3230 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3231
3232 if (pll == NULL)
3233 return;
3234
3235 if (pll->refcount == 0) {
3236 WARN(1, "bad PCH PLL refcount\n");
3237 return;
3238 }
3239
3240 --pll->refcount;
3241 intel_crtc->pch_pll = NULL;
3242 }
3243
3244 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3245 {
3246 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3247 struct intel_pch_pll *pll;
3248 int i;
3249
3250 pll = intel_crtc->pch_pll;
3251 if (pll) {
3252 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3253 intel_crtc->base.base.id, pll->pll_reg);
3254 goto prepare;
3255 }
3256
3257 if (HAS_PCH_IBX(dev_priv->dev)) {
3258 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3259 i = intel_crtc->pipe;
3260 pll = &dev_priv->pch_plls[i];
3261
3262 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3263 intel_crtc->base.base.id, pll->pll_reg);
3264
3265 goto found;
3266 }
3267
3268 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3269 pll = &dev_priv->pch_plls[i];
3270
3271 /* Only want to check enabled timings first */
3272 if (pll->refcount == 0)
3273 continue;
3274
3275 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3276 fp == I915_READ(pll->fp0_reg)) {
3277 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3278 intel_crtc->base.base.id,
3279 pll->pll_reg, pll->refcount, pll->active);
3280
3281 goto found;
3282 }
3283 }
3284
3285 /* Ok no matching timings, maybe there's a free one? */
3286 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3287 pll = &dev_priv->pch_plls[i];
3288 if (pll->refcount == 0) {
3289 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3290 intel_crtc->base.base.id, pll->pll_reg);
3291 goto found;
3292 }
3293 }
3294
3295 return NULL;
3296
3297 found:
3298 intel_crtc->pch_pll = pll;
3299 pll->refcount++;
3300 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3301 prepare: /* separate function? */
3302 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3303
3304 /* Wait for the clocks to stabilize before rewriting the regs */
3305 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3306 POSTING_READ(pll->pll_reg);
3307 udelay(150);
3308
3309 I915_WRITE(pll->fp0_reg, fp);
3310 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3311 pll->on = false;
3312 return pll;
3313 }
3314
3315 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3316 {
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 int dslreg = PIPEDSL(pipe);
3319 u32 temp;
3320
3321 temp = I915_READ(dslreg);
3322 udelay(500);
3323 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3324 if (wait_for(I915_READ(dslreg) != temp, 5))
3325 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3326 }
3327 }
3328
3329 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3330 {
3331 struct drm_device *dev = crtc->dev;
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3334 struct intel_encoder *encoder;
3335 int pipe = intel_crtc->pipe;
3336 int plane = intel_crtc->plane;
3337 u32 temp;
3338
3339 WARN_ON(!crtc->enabled);
3340
3341 if (intel_crtc->active)
3342 return;
3343
3344 intel_crtc->active = true;
3345 intel_update_watermarks(dev);
3346
3347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3348 temp = I915_READ(PCH_LVDS);
3349 if ((temp & LVDS_PORT_EN) == 0)
3350 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3351 }
3352
3353
3354 if (intel_crtc->config.has_pch_encoder) {
3355 /* Note: FDI PLL enabling _must_ be done before we enable the
3356 * cpu pipes, hence this is separate from all the other fdi/pch
3357 * enabling. */
3358 ironlake_fdi_pll_enable(intel_crtc);
3359 } else {
3360 assert_fdi_tx_disabled(dev_priv, pipe);
3361 assert_fdi_rx_disabled(dev_priv, pipe);
3362 }
3363
3364 for_each_encoder_on_crtc(dev, crtc, encoder)
3365 if (encoder->pre_enable)
3366 encoder->pre_enable(encoder);
3367
3368 /* Enable panel fitting for LVDS */
3369 if (dev_priv->pch_pf_size &&
3370 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3371 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3372 /* Force use of hard-coded filter coefficients
3373 * as some pre-programmed values are broken,
3374 * e.g. x201.
3375 */
3376 if (IS_IVYBRIDGE(dev))
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3378 PF_PIPE_SEL_IVB(pipe));
3379 else
3380 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3381 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3382 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3383 }
3384
3385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
3391 intel_enable_pipe(dev_priv, pipe,
3392 intel_crtc->config.has_pch_encoder);
3393 intel_enable_plane(dev_priv, plane, pipe);
3394
3395 if (intel_crtc->config.has_pch_encoder)
3396 ironlake_pch_enable(crtc);
3397
3398 mutex_lock(&dev->struct_mutex);
3399 intel_update_fbc(dev);
3400 mutex_unlock(&dev->struct_mutex);
3401
3402 intel_crtc_update_cursor(crtc, true);
3403
3404 for_each_encoder_on_crtc(dev, crtc, encoder)
3405 encoder->enable(encoder);
3406
3407 if (HAS_PCH_CPT(dev))
3408 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3409
3410 /*
3411 * There seems to be a race in PCH platform hw (at least on some
3412 * outputs) where an enabled pipe still completes any pageflip right
3413 * away (as if the pipe is off) instead of waiting for vblank. As soon
3414 * as the first vblank happend, everything works as expected. Hence just
3415 * wait for one vblank before returning to avoid strange things
3416 * happening.
3417 */
3418 intel_wait_for_vblank(dev, intel_crtc->pipe);
3419 }
3420
3421 static void haswell_crtc_enable(struct drm_crtc *crtc)
3422 {
3423 struct drm_device *dev = crtc->dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426 struct intel_encoder *encoder;
3427 int pipe = intel_crtc->pipe;
3428 int plane = intel_crtc->plane;
3429
3430 WARN_ON(!crtc->enabled);
3431
3432 if (intel_crtc->active)
3433 return;
3434
3435 intel_crtc->active = true;
3436 intel_update_watermarks(dev);
3437
3438 if (intel_crtc->config.has_pch_encoder)
3439 dev_priv->display.fdi_link_train(crtc);
3440
3441 for_each_encoder_on_crtc(dev, crtc, encoder)
3442 if (encoder->pre_enable)
3443 encoder->pre_enable(encoder);
3444
3445 intel_ddi_enable_pipe_clock(intel_crtc);
3446
3447 /* Enable panel fitting for eDP */
3448 if (dev_priv->pch_pf_size &&
3449 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3450 /* Force use of hard-coded filter coefficients
3451 * as some pre-programmed values are broken,
3452 * e.g. x201.
3453 */
3454 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3455 PF_PIPE_SEL_IVB(pipe));
3456 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3457 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3458 }
3459
3460 /*
3461 * On ILK+ LUT must be loaded before the pipe is running but with
3462 * clocks enabled
3463 */
3464 intel_crtc_load_lut(crtc);
3465
3466 intel_ddi_set_pipe_settings(crtc);
3467 intel_ddi_enable_transcoder_func(crtc);
3468
3469 intel_enable_pipe(dev_priv, pipe,
3470 intel_crtc->config.has_pch_encoder);
3471 intel_enable_plane(dev_priv, plane, pipe);
3472
3473 if (intel_crtc->config.has_pch_encoder)
3474 lpt_pch_enable(crtc);
3475
3476 mutex_lock(&dev->struct_mutex);
3477 intel_update_fbc(dev);
3478 mutex_unlock(&dev->struct_mutex);
3479
3480 intel_crtc_update_cursor(crtc, true);
3481
3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 encoder->enable(encoder);
3484
3485 /*
3486 * There seems to be a race in PCH platform hw (at least on some
3487 * outputs) where an enabled pipe still completes any pageflip right
3488 * away (as if the pipe is off) instead of waiting for vblank. As soon
3489 * as the first vblank happend, everything works as expected. Hence just
3490 * wait for one vblank before returning to avoid strange things
3491 * happening.
3492 */
3493 intel_wait_for_vblank(dev, intel_crtc->pipe);
3494 }
3495
3496 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3497 {
3498 struct drm_device *dev = crtc->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3501 struct intel_encoder *encoder;
3502 int pipe = intel_crtc->pipe;
3503 int plane = intel_crtc->plane;
3504 u32 reg, temp;
3505
3506
3507 if (!intel_crtc->active)
3508 return;
3509
3510 for_each_encoder_on_crtc(dev, crtc, encoder)
3511 encoder->disable(encoder);
3512
3513 intel_crtc_wait_for_pending_flips(crtc);
3514 drm_vblank_off(dev, pipe);
3515 intel_crtc_update_cursor(crtc, false);
3516
3517 intel_disable_plane(dev_priv, plane, pipe);
3518
3519 if (dev_priv->cfb_plane == plane)
3520 intel_disable_fbc(dev);
3521
3522 intel_disable_pipe(dev_priv, pipe);
3523
3524 /* Disable PF */
3525 I915_WRITE(PF_CTL(pipe), 0);
3526 I915_WRITE(PF_WIN_SZ(pipe), 0);
3527
3528 for_each_encoder_on_crtc(dev, crtc, encoder)
3529 if (encoder->post_disable)
3530 encoder->post_disable(encoder);
3531
3532 ironlake_fdi_disable(crtc);
3533
3534 ironlake_disable_pch_transcoder(dev_priv, pipe);
3535
3536 if (HAS_PCH_CPT(dev)) {
3537 /* disable TRANS_DP_CTL */
3538 reg = TRANS_DP_CTL(pipe);
3539 temp = I915_READ(reg);
3540 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3541 temp |= TRANS_DP_PORT_SEL_NONE;
3542 I915_WRITE(reg, temp);
3543
3544 /* disable DPLL_SEL */
3545 temp = I915_READ(PCH_DPLL_SEL);
3546 switch (pipe) {
3547 case 0:
3548 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3549 break;
3550 case 1:
3551 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3552 break;
3553 case 2:
3554 /* C shares PLL A or B */
3555 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3556 break;
3557 default:
3558 BUG(); /* wtf */
3559 }
3560 I915_WRITE(PCH_DPLL_SEL, temp);
3561 }
3562
3563 /* disable PCH DPLL */
3564 intel_disable_pch_pll(intel_crtc);
3565
3566 ironlake_fdi_pll_disable(intel_crtc);
3567
3568 intel_crtc->active = false;
3569 intel_update_watermarks(dev);
3570
3571 mutex_lock(&dev->struct_mutex);
3572 intel_update_fbc(dev);
3573 mutex_unlock(&dev->struct_mutex);
3574 }
3575
3576 static void haswell_crtc_disable(struct drm_crtc *crtc)
3577 {
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581 struct intel_encoder *encoder;
3582 int pipe = intel_crtc->pipe;
3583 int plane = intel_crtc->plane;
3584 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3585 bool is_pch_port;
3586
3587 if (!intel_crtc->active)
3588 return;
3589
3590 is_pch_port = haswell_crtc_driving_pch(crtc);
3591
3592 for_each_encoder_on_crtc(dev, crtc, encoder)
3593 encoder->disable(encoder);
3594
3595 intel_crtc_wait_for_pending_flips(crtc);
3596 drm_vblank_off(dev, pipe);
3597 intel_crtc_update_cursor(crtc, false);
3598
3599 intel_disable_plane(dev_priv, plane, pipe);
3600
3601 if (dev_priv->cfb_plane == plane)
3602 intel_disable_fbc(dev);
3603
3604 intel_disable_pipe(dev_priv, pipe);
3605
3606 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3607
3608 /* Disable PF */
3609 I915_WRITE(PF_CTL(pipe), 0);
3610 I915_WRITE(PF_WIN_SZ(pipe), 0);
3611
3612 intel_ddi_disable_pipe_clock(intel_crtc);
3613
3614 for_each_encoder_on_crtc(dev, crtc, encoder)
3615 if (encoder->post_disable)
3616 encoder->post_disable(encoder);
3617
3618 if (is_pch_port) {
3619 lpt_disable_pch_transcoder(dev_priv);
3620 intel_ddi_fdi_disable(crtc);
3621 }
3622
3623 intel_crtc->active = false;
3624 intel_update_watermarks(dev);
3625
3626 mutex_lock(&dev->struct_mutex);
3627 intel_update_fbc(dev);
3628 mutex_unlock(&dev->struct_mutex);
3629 }
3630
3631 static void ironlake_crtc_off(struct drm_crtc *crtc)
3632 {
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634 intel_put_pch_pll(intel_crtc);
3635 }
3636
3637 static void haswell_crtc_off(struct drm_crtc *crtc)
3638 {
3639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640
3641 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3642 * start using it. */
3643 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3644
3645 intel_ddi_put_crtc_pll(crtc);
3646 }
3647
3648 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3649 {
3650 if (!enable && intel_crtc->overlay) {
3651 struct drm_device *dev = intel_crtc->base.dev;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653
3654 mutex_lock(&dev->struct_mutex);
3655 dev_priv->mm.interruptible = false;
3656 (void) intel_overlay_switch_off(intel_crtc->overlay);
3657 dev_priv->mm.interruptible = true;
3658 mutex_unlock(&dev->struct_mutex);
3659 }
3660
3661 /* Let userspace switch the overlay on again. In most cases userspace
3662 * has to recompute where to put it anyway.
3663 */
3664 }
3665
3666 /**
3667 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3668 * cursor plane briefly if not already running after enabling the display
3669 * plane.
3670 * This workaround avoids occasional blank screens when self refresh is
3671 * enabled.
3672 */
3673 static void
3674 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3675 {
3676 u32 cntl = I915_READ(CURCNTR(pipe));
3677
3678 if ((cntl & CURSOR_MODE) == 0) {
3679 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3680
3681 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3682 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3683 intel_wait_for_vblank(dev_priv->dev, pipe);
3684 I915_WRITE(CURCNTR(pipe), cntl);
3685 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3686 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3687 }
3688 }
3689
3690 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3691 {
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
3698
3699 WARN_ON(!crtc->enabled);
3700
3701 if (intel_crtc->active)
3702 return;
3703
3704 intel_crtc->active = true;
3705 intel_update_watermarks(dev);
3706
3707 intel_enable_pll(dev_priv, pipe);
3708
3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 if (encoder->pre_enable)
3711 encoder->pre_enable(encoder);
3712
3713 intel_enable_pipe(dev_priv, pipe, false);
3714 intel_enable_plane(dev_priv, plane, pipe);
3715 if (IS_G4X(dev))
3716 g4x_fixup_plane(dev_priv, pipe);
3717
3718 intel_crtc_load_lut(crtc);
3719 intel_update_fbc(dev);
3720
3721 /* Give the overlay scaler a chance to enable if it's on this pipe */
3722 intel_crtc_dpms_overlay(intel_crtc, true);
3723 intel_crtc_update_cursor(crtc, true);
3724
3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
3727 }
3728
3729 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3730 {
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3734 struct intel_encoder *encoder;
3735 int pipe = intel_crtc->pipe;
3736 int plane = intel_crtc->plane;
3737 u32 pctl;
3738
3739
3740 if (!intel_crtc->active)
3741 return;
3742
3743 for_each_encoder_on_crtc(dev, crtc, encoder)
3744 encoder->disable(encoder);
3745
3746 /* Give the overlay scaler a chance to disable if it's on this pipe */
3747 intel_crtc_wait_for_pending_flips(crtc);
3748 drm_vblank_off(dev, pipe);
3749 intel_crtc_dpms_overlay(intel_crtc, false);
3750 intel_crtc_update_cursor(crtc, false);
3751
3752 if (dev_priv->cfb_plane == plane)
3753 intel_disable_fbc(dev);
3754
3755 intel_disable_plane(dev_priv, plane, pipe);
3756 intel_disable_pipe(dev_priv, pipe);
3757
3758 /* Disable pannel fitter if it is on this pipe. */
3759 pctl = I915_READ(PFIT_CONTROL);
3760 if ((pctl & PFIT_ENABLE) &&
3761 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3762 I915_WRITE(PFIT_CONTROL, 0);
3763
3764 intel_disable_pll(dev_priv, pipe);
3765
3766 intel_crtc->active = false;
3767 intel_update_fbc(dev);
3768 intel_update_watermarks(dev);
3769 }
3770
3771 static void i9xx_crtc_off(struct drm_crtc *crtc)
3772 {
3773 }
3774
3775 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3776 bool enabled)
3777 {
3778 struct drm_device *dev = crtc->dev;
3779 struct drm_i915_master_private *master_priv;
3780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781 int pipe = intel_crtc->pipe;
3782
3783 if (!dev->primary->master)
3784 return;
3785
3786 master_priv = dev->primary->master->driver_priv;
3787 if (!master_priv->sarea_priv)
3788 return;
3789
3790 switch (pipe) {
3791 case 0:
3792 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3793 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3794 break;
3795 case 1:
3796 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3797 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3798 break;
3799 default:
3800 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3801 break;
3802 }
3803 }
3804
3805 /**
3806 * Sets the power management mode of the pipe and plane.
3807 */
3808 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_encoder *intel_encoder;
3813 bool enable = false;
3814
3815 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3816 enable |= intel_encoder->connectors_active;
3817
3818 if (enable)
3819 dev_priv->display.crtc_enable(crtc);
3820 else
3821 dev_priv->display.crtc_disable(crtc);
3822
3823 intel_crtc_update_sarea(crtc, enable);
3824 }
3825
3826 static void intel_crtc_disable(struct drm_crtc *crtc)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_connector *connector;
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3832
3833 /* crtc should still be enabled when we disable it. */
3834 WARN_ON(!crtc->enabled);
3835
3836 intel_crtc->eld_vld = false;
3837 dev_priv->display.crtc_disable(crtc);
3838 intel_crtc_update_sarea(crtc, false);
3839 dev_priv->display.off(crtc);
3840
3841 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3842 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3843
3844 if (crtc->fb) {
3845 mutex_lock(&dev->struct_mutex);
3846 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3847 mutex_unlock(&dev->struct_mutex);
3848 crtc->fb = NULL;
3849 }
3850
3851 /* Update computed state. */
3852 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3853 if (!connector->encoder || !connector->encoder->crtc)
3854 continue;
3855
3856 if (connector->encoder->crtc != crtc)
3857 continue;
3858
3859 connector->dpms = DRM_MODE_DPMS_OFF;
3860 to_intel_encoder(connector->encoder)->connectors_active = false;
3861 }
3862 }
3863
3864 void intel_modeset_disable(struct drm_device *dev)
3865 {
3866 struct drm_crtc *crtc;
3867
3868 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3869 if (crtc->enabled)
3870 intel_crtc_disable(crtc);
3871 }
3872 }
3873
3874 void intel_encoder_destroy(struct drm_encoder *encoder)
3875 {
3876 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3877
3878 drm_encoder_cleanup(encoder);
3879 kfree(intel_encoder);
3880 }
3881
3882 /* Simple dpms helper for encodres with just one connector, no cloning and only
3883 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3884 * state of the entire output pipe. */
3885 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3886 {
3887 if (mode == DRM_MODE_DPMS_ON) {
3888 encoder->connectors_active = true;
3889
3890 intel_crtc_update_dpms(encoder->base.crtc);
3891 } else {
3892 encoder->connectors_active = false;
3893
3894 intel_crtc_update_dpms(encoder->base.crtc);
3895 }
3896 }
3897
3898 /* Cross check the actual hw state with our own modeset state tracking (and it's
3899 * internal consistency). */
3900 static void intel_connector_check_state(struct intel_connector *connector)
3901 {
3902 if (connector->get_hw_state(connector)) {
3903 struct intel_encoder *encoder = connector->encoder;
3904 struct drm_crtc *crtc;
3905 bool encoder_enabled;
3906 enum pipe pipe;
3907
3908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3909 connector->base.base.id,
3910 drm_get_connector_name(&connector->base));
3911
3912 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3913 "wrong connector dpms state\n");
3914 WARN(connector->base.encoder != &encoder->base,
3915 "active connector not linked to encoder\n");
3916 WARN(!encoder->connectors_active,
3917 "encoder->connectors_active not set\n");
3918
3919 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3920 WARN(!encoder_enabled, "encoder not enabled\n");
3921 if (WARN_ON(!encoder->base.crtc))
3922 return;
3923
3924 crtc = encoder->base.crtc;
3925
3926 WARN(!crtc->enabled, "crtc not enabled\n");
3927 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3928 WARN(pipe != to_intel_crtc(crtc)->pipe,
3929 "encoder active on the wrong pipe\n");
3930 }
3931 }
3932
3933 /* Even simpler default implementation, if there's really no special case to
3934 * consider. */
3935 void intel_connector_dpms(struct drm_connector *connector, int mode)
3936 {
3937 struct intel_encoder *encoder = intel_attached_encoder(connector);
3938
3939 /* All the simple cases only support two dpms states. */
3940 if (mode != DRM_MODE_DPMS_ON)
3941 mode = DRM_MODE_DPMS_OFF;
3942
3943 if (mode == connector->dpms)
3944 return;
3945
3946 connector->dpms = mode;
3947
3948 /* Only need to change hw state when actually enabled */
3949 if (encoder->base.crtc)
3950 intel_encoder_dpms(encoder, mode);
3951 else
3952 WARN_ON(encoder->connectors_active != false);
3953
3954 intel_modeset_check_state(connector->dev);
3955 }
3956
3957 /* Simple connector->get_hw_state implementation for encoders that support only
3958 * one connector and no cloning and hence the encoder state determines the state
3959 * of the connector. */
3960 bool intel_connector_get_hw_state(struct intel_connector *connector)
3961 {
3962 enum pipe pipe = 0;
3963 struct intel_encoder *encoder = connector->encoder;
3964
3965 return encoder->get_hw_state(encoder, &pipe);
3966 }
3967
3968 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3969 struct intel_crtc_config *pipe_config)
3970 {
3971 struct drm_device *dev = crtc->dev;
3972 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3973
3974 if (HAS_PCH_SPLIT(dev)) {
3975 /* FDI link clock is fixed at 2.7G */
3976 if (pipe_config->requested_mode.clock * 3
3977 > IRONLAKE_FDI_FREQ * 4)
3978 return false;
3979 }
3980
3981 /* All interlaced capable intel hw wants timings in frames. Note though
3982 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3983 * timings, so we need to be careful not to clobber these.*/
3984 if (!pipe_config->timings_set)
3985 drm_mode_set_crtcinfo(adjusted_mode, 0);
3986
3987 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3988 * with a hsync front porch of 0.
3989 */
3990 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3991 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3992 return false;
3993
3994 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3995 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3996 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3997 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3998 * for lvds. */
3999 pipe_config->pipe_bpp = 8*3;
4000 }
4001
4002 return true;
4003 }
4004
4005 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4006 {
4007 return 400000; /* FIXME */
4008 }
4009
4010 static int i945_get_display_clock_speed(struct drm_device *dev)
4011 {
4012 return 400000;
4013 }
4014
4015 static int i915_get_display_clock_speed(struct drm_device *dev)
4016 {
4017 return 333000;
4018 }
4019
4020 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4021 {
4022 return 200000;
4023 }
4024
4025 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4026 {
4027 u16 gcfgc = 0;
4028
4029 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4030
4031 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4032 return 133000;
4033 else {
4034 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4035 case GC_DISPLAY_CLOCK_333_MHZ:
4036 return 333000;
4037 default:
4038 case GC_DISPLAY_CLOCK_190_200_MHZ:
4039 return 190000;
4040 }
4041 }
4042 }
4043
4044 static int i865_get_display_clock_speed(struct drm_device *dev)
4045 {
4046 return 266000;
4047 }
4048
4049 static int i855_get_display_clock_speed(struct drm_device *dev)
4050 {
4051 u16 hpllcc = 0;
4052 /* Assume that the hardware is in the high speed state. This
4053 * should be the default.
4054 */
4055 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4056 case GC_CLOCK_133_200:
4057 case GC_CLOCK_100_200:
4058 return 200000;
4059 case GC_CLOCK_166_250:
4060 return 250000;
4061 case GC_CLOCK_100_133:
4062 return 133000;
4063 }
4064
4065 /* Shouldn't happen */
4066 return 0;
4067 }
4068
4069 static int i830_get_display_clock_speed(struct drm_device *dev)
4070 {
4071 return 133000;
4072 }
4073
4074 static void
4075 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4076 {
4077 while (*num > 0xffffff || *den > 0xffffff) {
4078 *num >>= 1;
4079 *den >>= 1;
4080 }
4081 }
4082
4083 void
4084 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4085 int pixel_clock, int link_clock,
4086 struct intel_link_m_n *m_n)
4087 {
4088 m_n->tu = 64;
4089 m_n->gmch_m = bits_per_pixel * pixel_clock;
4090 m_n->gmch_n = link_clock * nlanes * 8;
4091 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4092 m_n->link_m = pixel_clock;
4093 m_n->link_n = link_clock;
4094 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4095 }
4096
4097 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4098 {
4099 if (i915_panel_use_ssc >= 0)
4100 return i915_panel_use_ssc != 0;
4101 return dev_priv->lvds_use_ssc
4102 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4103 }
4104
4105 static int vlv_get_refclk(struct drm_crtc *crtc)
4106 {
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 int refclk = 27000; /* for DP & HDMI */
4110
4111 return 100000; /* only one validated so far */
4112
4113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4114 refclk = 96000;
4115 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4116 if (intel_panel_use_ssc(dev_priv))
4117 refclk = 100000;
4118 else
4119 refclk = 96000;
4120 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4121 refclk = 100000;
4122 }
4123
4124 return refclk;
4125 }
4126
4127 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4128 {
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 int refclk;
4132
4133 if (IS_VALLEYVIEW(dev)) {
4134 refclk = vlv_get_refclk(crtc);
4135 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4136 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4137 refclk = dev_priv->lvds_ssc_freq * 1000;
4138 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4139 refclk / 1000);
4140 } else if (!IS_GEN2(dev)) {
4141 refclk = 96000;
4142 } else {
4143 refclk = 48000;
4144 }
4145
4146 return refclk;
4147 }
4148
4149 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4150 intel_clock_t *clock)
4151 {
4152 /* SDVO TV has fixed PLL values depend on its clock range,
4153 this mirrors vbios setting. */
4154 if (adjusted_mode->clock >= 100000
4155 && adjusted_mode->clock < 140500) {
4156 clock->p1 = 2;
4157 clock->p2 = 10;
4158 clock->n = 3;
4159 clock->m1 = 16;
4160 clock->m2 = 8;
4161 } else if (adjusted_mode->clock >= 140500
4162 && adjusted_mode->clock <= 200000) {
4163 clock->p1 = 1;
4164 clock->p2 = 10;
4165 clock->n = 6;
4166 clock->m1 = 12;
4167 clock->m2 = 8;
4168 }
4169 }
4170
4171 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4172 intel_clock_t *clock,
4173 intel_clock_t *reduced_clock)
4174 {
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 int pipe = intel_crtc->pipe;
4179 u32 fp, fp2 = 0;
4180
4181 if (IS_PINEVIEW(dev)) {
4182 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4183 if (reduced_clock)
4184 fp2 = (1 << reduced_clock->n) << 16 |
4185 reduced_clock->m1 << 8 | reduced_clock->m2;
4186 } else {
4187 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4188 if (reduced_clock)
4189 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4190 reduced_clock->m2;
4191 }
4192
4193 I915_WRITE(FP0(pipe), fp);
4194
4195 intel_crtc->lowfreq_avail = false;
4196 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197 reduced_clock && i915_powersave) {
4198 I915_WRITE(FP1(pipe), fp2);
4199 intel_crtc->lowfreq_avail = true;
4200 } else {
4201 I915_WRITE(FP1(pipe), fp);
4202 }
4203 }
4204
4205 static void vlv_update_pll(struct drm_crtc *crtc,
4206 intel_clock_t *clock, intel_clock_t *reduced_clock,
4207 int num_connectors)
4208 {
4209 struct drm_device *dev = crtc->dev;
4210 struct drm_i915_private *dev_priv = dev->dev_private;
4211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4212 struct drm_display_mode *adjusted_mode =
4213 &intel_crtc->config.adjusted_mode;
4214 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4215 int pipe = intel_crtc->pipe;
4216 u32 dpll, mdiv, pdiv;
4217 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4218 bool is_sdvo;
4219 u32 temp;
4220
4221 mutex_lock(&dev_priv->dpio_lock);
4222
4223 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4224 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4225
4226 dpll = DPLL_VGA_MODE_DIS;
4227 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4228 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4229 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4230
4231 I915_WRITE(DPLL(pipe), dpll);
4232 POSTING_READ(DPLL(pipe));
4233
4234 bestn = clock->n;
4235 bestm1 = clock->m1;
4236 bestm2 = clock->m2;
4237 bestp1 = clock->p1;
4238 bestp2 = clock->p2;
4239
4240 /*
4241 * In Valleyview PLL and program lane counter registers are exposed
4242 * through DPIO interface
4243 */
4244 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4245 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4246 mdiv |= ((bestn << DPIO_N_SHIFT));
4247 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4248 mdiv |= (1 << DPIO_K_SHIFT);
4249 mdiv |= DPIO_ENABLE_CALIBRATION;
4250 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4251
4252 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4253
4254 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4255 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4256 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4257 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4258 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4259
4260 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4261
4262 dpll |= DPLL_VCO_ENABLE;
4263 I915_WRITE(DPLL(pipe), dpll);
4264 POSTING_READ(DPLL(pipe));
4265 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4266 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4267
4268 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4269
4270 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4271 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4272
4273 I915_WRITE(DPLL(pipe), dpll);
4274
4275 /* Wait for the clocks to stabilize. */
4276 POSTING_READ(DPLL(pipe));
4277 udelay(150);
4278
4279 temp = 0;
4280 if (is_sdvo) {
4281 temp = 0;
4282 if (intel_crtc->config.pixel_multiplier > 1) {
4283 temp = (intel_crtc->config.pixel_multiplier - 1)
4284 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4285 }
4286 }
4287 I915_WRITE(DPLL_MD(pipe), temp);
4288 POSTING_READ(DPLL_MD(pipe));
4289
4290 /* Now program lane control registers */
4291 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4292 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4293 {
4294 temp = 0x1000C4;
4295 if(pipe == 1)
4296 temp |= (1 << 21);
4297 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4298 }
4299 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4300 {
4301 temp = 0x1000C4;
4302 if(pipe == 1)
4303 temp |= (1 << 21);
4304 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4305 }
4306
4307 mutex_unlock(&dev_priv->dpio_lock);
4308 }
4309
4310 static void i9xx_update_pll(struct drm_crtc *crtc,
4311 intel_clock_t *clock, intel_clock_t *reduced_clock,
4312 int num_connectors)
4313 {
4314 struct drm_device *dev = crtc->dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 struct drm_display_mode *adjusted_mode =
4318 &intel_crtc->config.adjusted_mode;
4319 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4320 struct intel_encoder *encoder;
4321 int pipe = intel_crtc->pipe;
4322 u32 dpll;
4323 bool is_sdvo;
4324
4325 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4326
4327 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4328 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4329
4330 dpll = DPLL_VGA_MODE_DIS;
4331
4332 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4333 dpll |= DPLLB_MODE_LVDS;
4334 else
4335 dpll |= DPLLB_MODE_DAC_SERIAL;
4336
4337 if (is_sdvo) {
4338 if ((intel_crtc->config.pixel_multiplier > 1) &&
4339 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4340 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4341 << SDVO_MULTIPLIER_SHIFT_HIRES;
4342 }
4343 dpll |= DPLL_DVO_HIGH_SPEED;
4344 }
4345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4346 dpll |= DPLL_DVO_HIGH_SPEED;
4347
4348 /* compute bitmask from p1 value */
4349 if (IS_PINEVIEW(dev))
4350 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4351 else {
4352 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4353 if (IS_G4X(dev) && reduced_clock)
4354 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4355 }
4356 switch (clock->p2) {
4357 case 5:
4358 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4359 break;
4360 case 7:
4361 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4362 break;
4363 case 10:
4364 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4365 break;
4366 case 14:
4367 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4368 break;
4369 }
4370 if (INTEL_INFO(dev)->gen >= 4)
4371 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4372
4373 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4374 dpll |= PLL_REF_INPUT_TVCLKINBC;
4375 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4376 /* XXX: just matching BIOS for now */
4377 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4378 dpll |= 3;
4379 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4380 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4381 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4382 else
4383 dpll |= PLL_REF_INPUT_DREFCLK;
4384
4385 dpll |= DPLL_VCO_ENABLE;
4386 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4387 POSTING_READ(DPLL(pipe));
4388 udelay(150);
4389
4390 for_each_encoder_on_crtc(dev, crtc, encoder)
4391 if (encoder->pre_pll_enable)
4392 encoder->pre_pll_enable(encoder);
4393
4394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4395 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4396
4397 I915_WRITE(DPLL(pipe), dpll);
4398
4399 /* Wait for the clocks to stabilize. */
4400 POSTING_READ(DPLL(pipe));
4401 udelay(150);
4402
4403 if (INTEL_INFO(dev)->gen >= 4) {
4404 u32 temp = 0;
4405 if (is_sdvo) {
4406 temp = 0;
4407 if (intel_crtc->config.pixel_multiplier > 1) {
4408 temp = (intel_crtc->config.pixel_multiplier - 1)
4409 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4410 }
4411 }
4412 I915_WRITE(DPLL_MD(pipe), temp);
4413 } else {
4414 /* The pixel multiplier can only be updated once the
4415 * DPLL is enabled and the clocks are stable.
4416 *
4417 * So write it again.
4418 */
4419 I915_WRITE(DPLL(pipe), dpll);
4420 }
4421 }
4422
4423 static void i8xx_update_pll(struct drm_crtc *crtc,
4424 struct drm_display_mode *adjusted_mode,
4425 intel_clock_t *clock, intel_clock_t *reduced_clock,
4426 int num_connectors)
4427 {
4428 struct drm_device *dev = crtc->dev;
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4431 struct intel_encoder *encoder;
4432 int pipe = intel_crtc->pipe;
4433 u32 dpll;
4434
4435 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4436
4437 dpll = DPLL_VGA_MODE_DIS;
4438
4439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4440 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4441 } else {
4442 if (clock->p1 == 2)
4443 dpll |= PLL_P1_DIVIDE_BY_TWO;
4444 else
4445 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4446 if (clock->p2 == 4)
4447 dpll |= PLL_P2_DIVIDE_BY_4;
4448 }
4449
4450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4451 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4452 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4453 else
4454 dpll |= PLL_REF_INPUT_DREFCLK;
4455
4456 dpll |= DPLL_VCO_ENABLE;
4457 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4458 POSTING_READ(DPLL(pipe));
4459 udelay(150);
4460
4461 for_each_encoder_on_crtc(dev, crtc, encoder)
4462 if (encoder->pre_pll_enable)
4463 encoder->pre_pll_enable(encoder);
4464
4465 I915_WRITE(DPLL(pipe), dpll);
4466
4467 /* Wait for the clocks to stabilize. */
4468 POSTING_READ(DPLL(pipe));
4469 udelay(150);
4470
4471 /* The pixel multiplier can only be updated once the
4472 * DPLL is enabled and the clocks are stable.
4473 *
4474 * So write it again.
4475 */
4476 I915_WRITE(DPLL(pipe), dpll);
4477 }
4478
4479 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4480 struct drm_display_mode *mode,
4481 struct drm_display_mode *adjusted_mode)
4482 {
4483 struct drm_device *dev = intel_crtc->base.dev;
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4485 enum pipe pipe = intel_crtc->pipe;
4486 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4487 uint32_t vsyncshift;
4488
4489 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4490 /* the chip adds 2 halflines automatically */
4491 adjusted_mode->crtc_vtotal -= 1;
4492 adjusted_mode->crtc_vblank_end -= 1;
4493 vsyncshift = adjusted_mode->crtc_hsync_start
4494 - adjusted_mode->crtc_htotal / 2;
4495 } else {
4496 vsyncshift = 0;
4497 }
4498
4499 if (INTEL_INFO(dev)->gen > 3)
4500 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4501
4502 I915_WRITE(HTOTAL(cpu_transcoder),
4503 (adjusted_mode->crtc_hdisplay - 1) |
4504 ((adjusted_mode->crtc_htotal - 1) << 16));
4505 I915_WRITE(HBLANK(cpu_transcoder),
4506 (adjusted_mode->crtc_hblank_start - 1) |
4507 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4508 I915_WRITE(HSYNC(cpu_transcoder),
4509 (adjusted_mode->crtc_hsync_start - 1) |
4510 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4511
4512 I915_WRITE(VTOTAL(cpu_transcoder),
4513 (adjusted_mode->crtc_vdisplay - 1) |
4514 ((adjusted_mode->crtc_vtotal - 1) << 16));
4515 I915_WRITE(VBLANK(cpu_transcoder),
4516 (adjusted_mode->crtc_vblank_start - 1) |
4517 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4518 I915_WRITE(VSYNC(cpu_transcoder),
4519 (adjusted_mode->crtc_vsync_start - 1) |
4520 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4521
4522 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4523 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4524 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4525 * bits. */
4526 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4527 (pipe == PIPE_B || pipe == PIPE_C))
4528 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4529
4530 /* pipesrc controls the size that is scaled from, which should
4531 * always be the user's requested size.
4532 */
4533 I915_WRITE(PIPESRC(pipe),
4534 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4535 }
4536
4537 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4538 int x, int y,
4539 struct drm_framebuffer *fb)
4540 {
4541 struct drm_device *dev = crtc->dev;
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4544 struct drm_display_mode *adjusted_mode =
4545 &intel_crtc->config.adjusted_mode;
4546 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4547 int pipe = intel_crtc->pipe;
4548 int plane = intel_crtc->plane;
4549 int refclk, num_connectors = 0;
4550 intel_clock_t clock, reduced_clock;
4551 u32 dspcntr, pipeconf;
4552 bool ok, has_reduced_clock = false, is_sdvo = false;
4553 bool is_lvds = false, is_tv = false, is_dp = false;
4554 struct intel_encoder *encoder;
4555 const intel_limit_t *limit;
4556 int ret;
4557
4558 for_each_encoder_on_crtc(dev, crtc, encoder) {
4559 switch (encoder->type) {
4560 case INTEL_OUTPUT_LVDS:
4561 is_lvds = true;
4562 break;
4563 case INTEL_OUTPUT_SDVO:
4564 case INTEL_OUTPUT_HDMI:
4565 is_sdvo = true;
4566 if (encoder->needs_tv_clock)
4567 is_tv = true;
4568 break;
4569 case INTEL_OUTPUT_TVOUT:
4570 is_tv = true;
4571 break;
4572 case INTEL_OUTPUT_DISPLAYPORT:
4573 is_dp = true;
4574 break;
4575 }
4576
4577 num_connectors++;
4578 }
4579
4580 refclk = i9xx_get_refclk(crtc, num_connectors);
4581
4582 /*
4583 * Returns a set of divisors for the desired target clock with the given
4584 * refclk, or FALSE. The returned values represent the clock equation:
4585 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4586 */
4587 limit = intel_limit(crtc, refclk);
4588 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4589 &clock);
4590 if (!ok) {
4591 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4592 return -EINVAL;
4593 }
4594
4595 /* Ensure that the cursor is valid for the new mode before changing... */
4596 intel_crtc_update_cursor(crtc, true);
4597
4598 if (is_lvds && dev_priv->lvds_downclock_avail) {
4599 /*
4600 * Ensure we match the reduced clock's P to the target clock.
4601 * If the clocks don't match, we can't switch the display clock
4602 * by using the FP0/FP1. In such case we will disable the LVDS
4603 * downclock feature.
4604 */
4605 has_reduced_clock = limit->find_pll(limit, crtc,
4606 dev_priv->lvds_downclock,
4607 refclk,
4608 &clock,
4609 &reduced_clock);
4610 }
4611
4612 if (is_sdvo && is_tv)
4613 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4614
4615 if (IS_GEN2(dev))
4616 i8xx_update_pll(crtc, adjusted_mode, &clock,
4617 has_reduced_clock ? &reduced_clock : NULL,
4618 num_connectors);
4619 else if (IS_VALLEYVIEW(dev))
4620 vlv_update_pll(crtc, &clock,
4621 has_reduced_clock ? &reduced_clock : NULL,
4622 num_connectors);
4623 else
4624 i9xx_update_pll(crtc, &clock,
4625 has_reduced_clock ? &reduced_clock : NULL,
4626 num_connectors);
4627
4628 /* setup pipeconf */
4629 pipeconf = I915_READ(PIPECONF(pipe));
4630
4631 /* Set up the display plane register */
4632 dspcntr = DISPPLANE_GAMMA_ENABLE;
4633
4634 if (!IS_VALLEYVIEW(dev)) {
4635 if (pipe == 0)
4636 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4637 else
4638 dspcntr |= DISPPLANE_SEL_PIPE_B;
4639 }
4640
4641 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4642 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4643 * core speed.
4644 *
4645 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4646 * pipe == 0 check?
4647 */
4648 if (mode->clock >
4649 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4650 pipeconf |= PIPECONF_DOUBLE_WIDE;
4651 else
4652 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4653 }
4654
4655 /* default to 8bpc */
4656 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4657 if (is_dp) {
4658 if (intel_crtc->config.dither) {
4659 pipeconf |= PIPECONF_6BPC |
4660 PIPECONF_DITHER_EN |
4661 PIPECONF_DITHER_TYPE_SP;
4662 }
4663 }
4664
4665 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4666 if (intel_crtc->config.dither) {
4667 pipeconf |= PIPECONF_6BPC |
4668 PIPECONF_ENABLE |
4669 I965_PIPECONF_ACTIVE;
4670 }
4671 }
4672
4673 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4674 drm_mode_debug_printmodeline(mode);
4675
4676 if (HAS_PIPE_CXSR(dev)) {
4677 if (intel_crtc->lowfreq_avail) {
4678 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4679 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4680 } else {
4681 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4682 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4683 }
4684 }
4685
4686 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4687 if (!IS_GEN2(dev) &&
4688 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4689 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4690 else
4691 pipeconf |= PIPECONF_PROGRESSIVE;
4692
4693 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4694
4695 /* pipesrc and dspsize control the size that is scaled from,
4696 * which should always be the user's requested size.
4697 */
4698 I915_WRITE(DSPSIZE(plane),
4699 ((mode->vdisplay - 1) << 16) |
4700 (mode->hdisplay - 1));
4701 I915_WRITE(DSPPOS(plane), 0);
4702
4703 I915_WRITE(PIPECONF(pipe), pipeconf);
4704 POSTING_READ(PIPECONF(pipe));
4705 intel_enable_pipe(dev_priv, pipe, false);
4706
4707 intel_wait_for_vblank(dev, pipe);
4708
4709 I915_WRITE(DSPCNTR(plane), dspcntr);
4710 POSTING_READ(DSPCNTR(plane));
4711
4712 ret = intel_pipe_set_base(crtc, x, y, fb);
4713
4714 intel_update_watermarks(dev);
4715
4716 return ret;
4717 }
4718
4719 static void ironlake_init_pch_refclk(struct drm_device *dev)
4720 {
4721 struct drm_i915_private *dev_priv = dev->dev_private;
4722 struct drm_mode_config *mode_config = &dev->mode_config;
4723 struct intel_encoder *encoder;
4724 u32 val, final;
4725 bool has_lvds = false;
4726 bool has_cpu_edp = false;
4727 bool has_pch_edp = false;
4728 bool has_panel = false;
4729 bool has_ck505 = false;
4730 bool can_ssc = false;
4731
4732 /* We need to take the global config into account */
4733 list_for_each_entry(encoder, &mode_config->encoder_list,
4734 base.head) {
4735 switch (encoder->type) {
4736 case INTEL_OUTPUT_LVDS:
4737 has_panel = true;
4738 has_lvds = true;
4739 break;
4740 case INTEL_OUTPUT_EDP:
4741 has_panel = true;
4742 if (intel_encoder_is_pch_edp(&encoder->base))
4743 has_pch_edp = true;
4744 else
4745 has_cpu_edp = true;
4746 break;
4747 }
4748 }
4749
4750 if (HAS_PCH_IBX(dev)) {
4751 has_ck505 = dev_priv->display_clock_mode;
4752 can_ssc = has_ck505;
4753 } else {
4754 has_ck505 = false;
4755 can_ssc = true;
4756 }
4757
4758 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4759 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4760 has_ck505);
4761
4762 /* Ironlake: try to setup display ref clock before DPLL
4763 * enabling. This is only under driver's control after
4764 * PCH B stepping, previous chipset stepping should be
4765 * ignoring this setting.
4766 */
4767 val = I915_READ(PCH_DREF_CONTROL);
4768
4769 /* As we must carefully and slowly disable/enable each source in turn,
4770 * compute the final state we want first and check if we need to
4771 * make any changes at all.
4772 */
4773 final = val;
4774 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4775 if (has_ck505)
4776 final |= DREF_NONSPREAD_CK505_ENABLE;
4777 else
4778 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4779
4780 final &= ~DREF_SSC_SOURCE_MASK;
4781 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4782 final &= ~DREF_SSC1_ENABLE;
4783
4784 if (has_panel) {
4785 final |= DREF_SSC_SOURCE_ENABLE;
4786
4787 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4788 final |= DREF_SSC1_ENABLE;
4789
4790 if (has_cpu_edp) {
4791 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4792 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4793 else
4794 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4795 } else
4796 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4797 } else {
4798 final |= DREF_SSC_SOURCE_DISABLE;
4799 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4800 }
4801
4802 if (final == val)
4803 return;
4804
4805 /* Always enable nonspread source */
4806 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4807
4808 if (has_ck505)
4809 val |= DREF_NONSPREAD_CK505_ENABLE;
4810 else
4811 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4812
4813 if (has_panel) {
4814 val &= ~DREF_SSC_SOURCE_MASK;
4815 val |= DREF_SSC_SOURCE_ENABLE;
4816
4817 /* SSC must be turned on before enabling the CPU output */
4818 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4819 DRM_DEBUG_KMS("Using SSC on panel\n");
4820 val |= DREF_SSC1_ENABLE;
4821 } else
4822 val &= ~DREF_SSC1_ENABLE;
4823
4824 /* Get SSC going before enabling the outputs */
4825 I915_WRITE(PCH_DREF_CONTROL, val);
4826 POSTING_READ(PCH_DREF_CONTROL);
4827 udelay(200);
4828
4829 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4830
4831 /* Enable CPU source on CPU attached eDP */
4832 if (has_cpu_edp) {
4833 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4834 DRM_DEBUG_KMS("Using SSC on eDP\n");
4835 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4836 }
4837 else
4838 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4839 } else
4840 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4841
4842 I915_WRITE(PCH_DREF_CONTROL, val);
4843 POSTING_READ(PCH_DREF_CONTROL);
4844 udelay(200);
4845 } else {
4846 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4847
4848 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4849
4850 /* Turn off CPU output */
4851 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4852
4853 I915_WRITE(PCH_DREF_CONTROL, val);
4854 POSTING_READ(PCH_DREF_CONTROL);
4855 udelay(200);
4856
4857 /* Turn off the SSC source */
4858 val &= ~DREF_SSC_SOURCE_MASK;
4859 val |= DREF_SSC_SOURCE_DISABLE;
4860
4861 /* Turn off SSC1 */
4862 val &= ~DREF_SSC1_ENABLE;
4863
4864 I915_WRITE(PCH_DREF_CONTROL, val);
4865 POSTING_READ(PCH_DREF_CONTROL);
4866 udelay(200);
4867 }
4868
4869 BUG_ON(val != final);
4870 }
4871
4872 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4873 static void lpt_init_pch_refclk(struct drm_device *dev)
4874 {
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 struct drm_mode_config *mode_config = &dev->mode_config;
4877 struct intel_encoder *encoder;
4878 bool has_vga = false;
4879 bool is_sdv = false;
4880 u32 tmp;
4881
4882 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4883 switch (encoder->type) {
4884 case INTEL_OUTPUT_ANALOG:
4885 has_vga = true;
4886 break;
4887 }
4888 }
4889
4890 if (!has_vga)
4891 return;
4892
4893 mutex_lock(&dev_priv->dpio_lock);
4894
4895 /* XXX: Rip out SDV support once Haswell ships for real. */
4896 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4897 is_sdv = true;
4898
4899 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4900 tmp &= ~SBI_SSCCTL_DISABLE;
4901 tmp |= SBI_SSCCTL_PATHALT;
4902 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4903
4904 udelay(24);
4905
4906 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4907 tmp &= ~SBI_SSCCTL_PATHALT;
4908 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4909
4910 if (!is_sdv) {
4911 tmp = I915_READ(SOUTH_CHICKEN2);
4912 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4913 I915_WRITE(SOUTH_CHICKEN2, tmp);
4914
4915 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4916 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4917 DRM_ERROR("FDI mPHY reset assert timeout\n");
4918
4919 tmp = I915_READ(SOUTH_CHICKEN2);
4920 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4921 I915_WRITE(SOUTH_CHICKEN2, tmp);
4922
4923 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4924 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4925 100))
4926 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4927 }
4928
4929 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4930 tmp &= ~(0xFF << 24);
4931 tmp |= (0x12 << 24);
4932 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4933
4934 if (!is_sdv) {
4935 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4936 tmp &= ~(0x3 << 6);
4937 tmp |= (1 << 6) | (1 << 0);
4938 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4939 }
4940
4941 if (is_sdv) {
4942 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4943 tmp |= 0x7FFF;
4944 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4945 }
4946
4947 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4948 tmp |= (1 << 11);
4949 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4950
4951 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4952 tmp |= (1 << 11);
4953 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4954
4955 if (is_sdv) {
4956 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4957 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4958 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4959
4960 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4961 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4962 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4963
4964 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4965 tmp |= (0x3F << 8);
4966 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4967
4968 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4969 tmp |= (0x3F << 8);
4970 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4971 }
4972
4973 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4974 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4975 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4976
4977 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4978 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4979 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4980
4981 if (!is_sdv) {
4982 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4983 tmp &= ~(7 << 13);
4984 tmp |= (5 << 13);
4985 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4986
4987 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4988 tmp &= ~(7 << 13);
4989 tmp |= (5 << 13);
4990 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4991 }
4992
4993 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4994 tmp &= ~0xFF;
4995 tmp |= 0x1C;
4996 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4997
4998 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4999 tmp &= ~0xFF;
5000 tmp |= 0x1C;
5001 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5002
5003 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5004 tmp &= ~(0xFF << 16);
5005 tmp |= (0x1C << 16);
5006 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5007
5008 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5009 tmp &= ~(0xFF << 16);
5010 tmp |= (0x1C << 16);
5011 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5012
5013 if (!is_sdv) {
5014 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5015 tmp |= (1 << 27);
5016 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5017
5018 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5019 tmp |= (1 << 27);
5020 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5021
5022 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5023 tmp &= ~(0xF << 28);
5024 tmp |= (4 << 28);
5025 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5026
5027 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5028 tmp &= ~(0xF << 28);
5029 tmp |= (4 << 28);
5030 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5031 }
5032
5033 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5034 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5035 tmp |= SBI_DBUFF0_ENABLE;
5036 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5037
5038 mutex_unlock(&dev_priv->dpio_lock);
5039 }
5040
5041 /*
5042 * Initialize reference clocks when the driver loads
5043 */
5044 void intel_init_pch_refclk(struct drm_device *dev)
5045 {
5046 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5047 ironlake_init_pch_refclk(dev);
5048 else if (HAS_PCH_LPT(dev))
5049 lpt_init_pch_refclk(dev);
5050 }
5051
5052 static int ironlake_get_refclk(struct drm_crtc *crtc)
5053 {
5054 struct drm_device *dev = crtc->dev;
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5056 struct intel_encoder *encoder;
5057 struct intel_encoder *edp_encoder = NULL;
5058 int num_connectors = 0;
5059 bool is_lvds = false;
5060
5061 for_each_encoder_on_crtc(dev, crtc, encoder) {
5062 switch (encoder->type) {
5063 case INTEL_OUTPUT_LVDS:
5064 is_lvds = true;
5065 break;
5066 case INTEL_OUTPUT_EDP:
5067 edp_encoder = encoder;
5068 break;
5069 }
5070 num_connectors++;
5071 }
5072
5073 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5074 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5075 dev_priv->lvds_ssc_freq);
5076 return dev_priv->lvds_ssc_freq * 1000;
5077 }
5078
5079 return 120000;
5080 }
5081
5082 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5083 struct drm_display_mode *adjusted_mode,
5084 bool dither)
5085 {
5086 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5088 int pipe = intel_crtc->pipe;
5089 uint32_t val;
5090
5091 val = I915_READ(PIPECONF(pipe));
5092
5093 val &= ~PIPECONF_BPC_MASK;
5094 switch (intel_crtc->config.pipe_bpp) {
5095 case 18:
5096 val |= PIPECONF_6BPC;
5097 break;
5098 case 24:
5099 val |= PIPECONF_8BPC;
5100 break;
5101 case 30:
5102 val |= PIPECONF_10BPC;
5103 break;
5104 case 36:
5105 val |= PIPECONF_12BPC;
5106 break;
5107 default:
5108 /* Case prevented by intel_choose_pipe_bpp_dither. */
5109 BUG();
5110 }
5111
5112 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5113 if (dither)
5114 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5115
5116 val &= ~PIPECONF_INTERLACE_MASK;
5117 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5118 val |= PIPECONF_INTERLACED_ILK;
5119 else
5120 val |= PIPECONF_PROGRESSIVE;
5121
5122 if (intel_crtc->config.limited_color_range)
5123 val |= PIPECONF_COLOR_RANGE_SELECT;
5124 else
5125 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5126
5127 I915_WRITE(PIPECONF(pipe), val);
5128 POSTING_READ(PIPECONF(pipe));
5129 }
5130
5131 /*
5132 * Set up the pipe CSC unit.
5133 *
5134 * Currently only full range RGB to limited range RGB conversion
5135 * is supported, but eventually this should handle various
5136 * RGB<->YCbCr scenarios as well.
5137 */
5138 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5139 {
5140 struct drm_device *dev = crtc->dev;
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5143 int pipe = intel_crtc->pipe;
5144 uint16_t coeff = 0x7800; /* 1.0 */
5145
5146 /*
5147 * TODO: Check what kind of values actually come out of the pipe
5148 * with these coeff/postoff values and adjust to get the best
5149 * accuracy. Perhaps we even need to take the bpc value into
5150 * consideration.
5151 */
5152
5153 if (intel_crtc->config.limited_color_range)
5154 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5155
5156 /*
5157 * GY/GU and RY/RU should be the other way around according
5158 * to BSpec, but reality doesn't agree. Just set them up in
5159 * a way that results in the correct picture.
5160 */
5161 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5162 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5163
5164 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5165 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5166
5167 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5168 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5169
5170 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5171 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5172 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5173
5174 if (INTEL_INFO(dev)->gen > 6) {
5175 uint16_t postoff = 0;
5176
5177 if (intel_crtc->config.limited_color_range)
5178 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5179
5180 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5181 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5182 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5183
5184 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5185 } else {
5186 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5187
5188 if (intel_crtc->config.limited_color_range)
5189 mode |= CSC_BLACK_SCREEN_OFFSET;
5190
5191 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5192 }
5193 }
5194
5195 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5196 struct drm_display_mode *adjusted_mode,
5197 bool dither)
5198 {
5199 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5201 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5202 uint32_t val;
5203
5204 val = I915_READ(PIPECONF(cpu_transcoder));
5205
5206 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5207 if (dither)
5208 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5209
5210 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5211 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5212 val |= PIPECONF_INTERLACED_ILK;
5213 else
5214 val |= PIPECONF_PROGRESSIVE;
5215
5216 I915_WRITE(PIPECONF(cpu_transcoder), val);
5217 POSTING_READ(PIPECONF(cpu_transcoder));
5218 }
5219
5220 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5221 struct drm_display_mode *adjusted_mode,
5222 intel_clock_t *clock,
5223 bool *has_reduced_clock,
5224 intel_clock_t *reduced_clock)
5225 {
5226 struct drm_device *dev = crtc->dev;
5227 struct drm_i915_private *dev_priv = dev->dev_private;
5228 struct intel_encoder *intel_encoder;
5229 int refclk;
5230 const intel_limit_t *limit;
5231 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5232
5233 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5234 switch (intel_encoder->type) {
5235 case INTEL_OUTPUT_LVDS:
5236 is_lvds = true;
5237 break;
5238 case INTEL_OUTPUT_SDVO:
5239 case INTEL_OUTPUT_HDMI:
5240 is_sdvo = true;
5241 if (intel_encoder->needs_tv_clock)
5242 is_tv = true;
5243 break;
5244 case INTEL_OUTPUT_TVOUT:
5245 is_tv = true;
5246 break;
5247 }
5248 }
5249
5250 refclk = ironlake_get_refclk(crtc);
5251
5252 /*
5253 * Returns a set of divisors for the desired target clock with the given
5254 * refclk, or FALSE. The returned values represent the clock equation:
5255 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5256 */
5257 limit = intel_limit(crtc, refclk);
5258 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5259 clock);
5260 if (!ret)
5261 return false;
5262
5263 if (is_lvds && dev_priv->lvds_downclock_avail) {
5264 /*
5265 * Ensure we match the reduced clock's P to the target clock.
5266 * If the clocks don't match, we can't switch the display clock
5267 * by using the FP0/FP1. In such case we will disable the LVDS
5268 * downclock feature.
5269 */
5270 *has_reduced_clock = limit->find_pll(limit, crtc,
5271 dev_priv->lvds_downclock,
5272 refclk,
5273 clock,
5274 reduced_clock);
5275 }
5276
5277 if (is_sdvo && is_tv)
5278 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5279
5280 return true;
5281 }
5282
5283 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5284 {
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286 uint32_t temp;
5287
5288 temp = I915_READ(SOUTH_CHICKEN1);
5289 if (temp & FDI_BC_BIFURCATION_SELECT)
5290 return;
5291
5292 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5293 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5294
5295 temp |= FDI_BC_BIFURCATION_SELECT;
5296 DRM_DEBUG_KMS("enabling fdi C rx\n");
5297 I915_WRITE(SOUTH_CHICKEN1, temp);
5298 POSTING_READ(SOUTH_CHICKEN1);
5299 }
5300
5301 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5302 {
5303 struct drm_device *dev = intel_crtc->base.dev;
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305 struct intel_crtc *pipe_B_crtc =
5306 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5307
5308 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5309 intel_crtc->pipe, intel_crtc->fdi_lanes);
5310 if (intel_crtc->fdi_lanes > 4) {
5311 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5312 intel_crtc->pipe, intel_crtc->fdi_lanes);
5313 /* Clamp lanes to avoid programming the hw with bogus values. */
5314 intel_crtc->fdi_lanes = 4;
5315
5316 return false;
5317 }
5318
5319 if (INTEL_INFO(dev)->num_pipes == 2)
5320 return true;
5321
5322 switch (intel_crtc->pipe) {
5323 case PIPE_A:
5324 return true;
5325 case PIPE_B:
5326 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5327 intel_crtc->fdi_lanes > 2) {
5328 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5329 intel_crtc->pipe, intel_crtc->fdi_lanes);
5330 /* Clamp lanes to avoid programming the hw with bogus values. */
5331 intel_crtc->fdi_lanes = 2;
5332
5333 return false;
5334 }
5335
5336 if (intel_crtc->fdi_lanes > 2)
5337 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5338 else
5339 cpt_enable_fdi_bc_bifurcation(dev);
5340
5341 return true;
5342 case PIPE_C:
5343 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5344 if (intel_crtc->fdi_lanes > 2) {
5345 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5346 intel_crtc->pipe, intel_crtc->fdi_lanes);
5347 /* Clamp lanes to avoid programming the hw with bogus values. */
5348 intel_crtc->fdi_lanes = 2;
5349
5350 return false;
5351 }
5352 } else {
5353 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5354 return false;
5355 }
5356
5357 cpt_enable_fdi_bc_bifurcation(dev);
5358
5359 return true;
5360 default:
5361 BUG();
5362 }
5363 }
5364
5365 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5366 {
5367 /*
5368 * Account for spread spectrum to avoid
5369 * oversubscribing the link. Max center spread
5370 * is 2.5%; use 5% for safety's sake.
5371 */
5372 u32 bps = target_clock * bpp * 21 / 20;
5373 return bps / (link_bw * 8) + 1;
5374 }
5375
5376 static void ironlake_set_m_n(struct drm_crtc *crtc)
5377 {
5378 struct drm_device *dev = crtc->dev;
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5381 struct drm_display_mode *adjusted_mode =
5382 &intel_crtc->config.adjusted_mode;
5383 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5384 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5385 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5386 struct intel_link_m_n m_n = {0};
5387 int target_clock, lane, link_bw;
5388 bool is_dp = false, is_cpu_edp = false;
5389
5390 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5391 switch (intel_encoder->type) {
5392 case INTEL_OUTPUT_DISPLAYPORT:
5393 is_dp = true;
5394 break;
5395 case INTEL_OUTPUT_EDP:
5396 is_dp = true;
5397 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5398 is_cpu_edp = true;
5399 edp_encoder = intel_encoder;
5400 break;
5401 }
5402 }
5403
5404 /* FDI link */
5405 lane = 0;
5406 /* CPU eDP doesn't require FDI link, so just set DP M/N
5407 according to current link config */
5408 if (is_cpu_edp) {
5409 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5410 } else {
5411 /* FDI is a binary signal running at ~2.7GHz, encoding
5412 * each output octet as 10 bits. The actual frequency
5413 * is stored as a divider into a 100MHz clock, and the
5414 * mode pixel clock is stored in units of 1KHz.
5415 * Hence the bw of each lane in terms of the mode signal
5416 * is:
5417 */
5418 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5419 }
5420
5421 /* [e]DP over FDI requires target mode clock instead of link clock. */
5422 if (edp_encoder)
5423 target_clock = intel_edp_target_clock(edp_encoder, mode);
5424 else if (is_dp)
5425 target_clock = mode->clock;
5426 else
5427 target_clock = adjusted_mode->clock;
5428
5429 if (!lane)
5430 lane = ironlake_get_lanes_required(target_clock, link_bw,
5431 intel_crtc->config.pipe_bpp);
5432
5433 intel_crtc->fdi_lanes = lane;
5434
5435 if (intel_crtc->config.pixel_multiplier > 1)
5436 link_bw *= intel_crtc->config.pixel_multiplier;
5437 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5438 link_bw, &m_n);
5439
5440 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5441 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5442 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5443 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5444 }
5445
5446 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5447 intel_clock_t *clock, u32 fp)
5448 {
5449 struct drm_crtc *crtc = &intel_crtc->base;
5450 struct drm_device *dev = crtc->dev;
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 struct intel_encoder *intel_encoder;
5453 uint32_t dpll;
5454 int factor, num_connectors = 0;
5455 bool is_lvds = false, is_sdvo = false, is_tv = false;
5456 bool is_dp = false, is_cpu_edp = false;
5457
5458 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5459 switch (intel_encoder->type) {
5460 case INTEL_OUTPUT_LVDS:
5461 is_lvds = true;
5462 break;
5463 case INTEL_OUTPUT_SDVO:
5464 case INTEL_OUTPUT_HDMI:
5465 is_sdvo = true;
5466 if (intel_encoder->needs_tv_clock)
5467 is_tv = true;
5468 break;
5469 case INTEL_OUTPUT_TVOUT:
5470 is_tv = true;
5471 break;
5472 case INTEL_OUTPUT_DISPLAYPORT:
5473 is_dp = true;
5474 break;
5475 case INTEL_OUTPUT_EDP:
5476 is_dp = true;
5477 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5478 is_cpu_edp = true;
5479 break;
5480 }
5481
5482 num_connectors++;
5483 }
5484
5485 /* Enable autotuning of the PLL clock (if permissible) */
5486 factor = 21;
5487 if (is_lvds) {
5488 if ((intel_panel_use_ssc(dev_priv) &&
5489 dev_priv->lvds_ssc_freq == 100) ||
5490 intel_is_dual_link_lvds(dev))
5491 factor = 25;
5492 } else if (is_sdvo && is_tv)
5493 factor = 20;
5494
5495 if (clock->m < factor * clock->n)
5496 fp |= FP_CB_TUNE;
5497
5498 dpll = 0;
5499
5500 if (is_lvds)
5501 dpll |= DPLLB_MODE_LVDS;
5502 else
5503 dpll |= DPLLB_MODE_DAC_SERIAL;
5504 if (is_sdvo) {
5505 if (intel_crtc->config.pixel_multiplier > 1) {
5506 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5507 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5508 }
5509 dpll |= DPLL_DVO_HIGH_SPEED;
5510 }
5511 if (is_dp && !is_cpu_edp)
5512 dpll |= DPLL_DVO_HIGH_SPEED;
5513
5514 /* compute bitmask from p1 value */
5515 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5516 /* also FPA1 */
5517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5518
5519 switch (clock->p2) {
5520 case 5:
5521 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5522 break;
5523 case 7:
5524 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5525 break;
5526 case 10:
5527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5528 break;
5529 case 14:
5530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5531 break;
5532 }
5533
5534 if (is_sdvo && is_tv)
5535 dpll |= PLL_REF_INPUT_TVCLKINBC;
5536 else if (is_tv)
5537 /* XXX: just matching BIOS for now */
5538 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5539 dpll |= 3;
5540 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5541 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5542 else
5543 dpll |= PLL_REF_INPUT_DREFCLK;
5544
5545 return dpll;
5546 }
5547
5548 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5549 int x, int y,
5550 struct drm_framebuffer *fb)
5551 {
5552 struct drm_device *dev = crtc->dev;
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5555 struct drm_display_mode *adjusted_mode =
5556 &intel_crtc->config.adjusted_mode;
5557 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5558 int pipe = intel_crtc->pipe;
5559 int plane = intel_crtc->plane;
5560 int num_connectors = 0;
5561 intel_clock_t clock, reduced_clock;
5562 u32 dpll, fp = 0, fp2 = 0;
5563 bool ok, has_reduced_clock = false;
5564 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5565 struct intel_encoder *encoder;
5566 int ret;
5567 bool dither, fdi_config_ok;
5568
5569 for_each_encoder_on_crtc(dev, crtc, encoder) {
5570 switch (encoder->type) {
5571 case INTEL_OUTPUT_LVDS:
5572 is_lvds = true;
5573 break;
5574 case INTEL_OUTPUT_DISPLAYPORT:
5575 is_dp = true;
5576 break;
5577 case INTEL_OUTPUT_EDP:
5578 is_dp = true;
5579 if (!intel_encoder_is_pch_edp(&encoder->base))
5580 is_cpu_edp = true;
5581 break;
5582 }
5583
5584 num_connectors++;
5585 }
5586
5587 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5588 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5589
5590 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5591 &has_reduced_clock, &reduced_clock);
5592 if (!ok) {
5593 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5594 return -EINVAL;
5595 }
5596
5597 /* Ensure that the cursor is valid for the new mode before changing... */
5598 intel_crtc_update_cursor(crtc, true);
5599
5600 /* determine panel color depth */
5601 dither = intel_crtc->config.dither;
5602 if (is_lvds && dev_priv->lvds_dither)
5603 dither = true;
5604
5605 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5606 if (has_reduced_clock)
5607 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5608 reduced_clock.m2;
5609
5610 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
5611
5612 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5613 drm_mode_debug_printmodeline(mode);
5614
5615 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5616 if (!is_cpu_edp) {
5617 struct intel_pch_pll *pll;
5618
5619 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5620 if (pll == NULL) {
5621 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5622 pipe);
5623 return -EINVAL;
5624 }
5625 } else
5626 intel_put_pch_pll(intel_crtc);
5627
5628 if (is_dp && !is_cpu_edp)
5629 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5630
5631 for_each_encoder_on_crtc(dev, crtc, encoder)
5632 if (encoder->pre_pll_enable)
5633 encoder->pre_pll_enable(encoder);
5634
5635 if (intel_crtc->pch_pll) {
5636 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5637
5638 /* Wait for the clocks to stabilize. */
5639 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5640 udelay(150);
5641
5642 /* The pixel multiplier can only be updated once the
5643 * DPLL is enabled and the clocks are stable.
5644 *
5645 * So write it again.
5646 */
5647 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5648 }
5649
5650 intel_crtc->lowfreq_avail = false;
5651 if (intel_crtc->pch_pll) {
5652 if (is_lvds && has_reduced_clock && i915_powersave) {
5653 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5654 intel_crtc->lowfreq_avail = true;
5655 } else {
5656 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5657 }
5658 }
5659
5660 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5661
5662 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5663 * ironlake_check_fdi_lanes. */
5664 ironlake_set_m_n(crtc);
5665
5666 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5667
5668 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5669
5670 intel_wait_for_vblank(dev, pipe);
5671
5672 /* Set up the display plane register */
5673 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5674 POSTING_READ(DSPCNTR(plane));
5675
5676 ret = intel_pipe_set_base(crtc, x, y, fb);
5677
5678 intel_update_watermarks(dev);
5679
5680 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5681
5682 return fdi_config_ok ? ret : -EINVAL;
5683 }
5684
5685 static void haswell_modeset_global_resources(struct drm_device *dev)
5686 {
5687 struct drm_i915_private *dev_priv = dev->dev_private;
5688 bool enable = false;
5689 struct intel_crtc *crtc;
5690 struct intel_encoder *encoder;
5691
5692 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5693 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5694 enable = true;
5695 /* XXX: Should check for edp transcoder here, but thanks to init
5696 * sequence that's not yet available. Just in case desktop eDP
5697 * on PORT D is possible on haswell, too. */
5698 }
5699
5700 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5701 base.head) {
5702 if (encoder->type != INTEL_OUTPUT_EDP &&
5703 encoder->connectors_active)
5704 enable = true;
5705 }
5706
5707 /* Even the eDP panel fitter is outside the always-on well. */
5708 if (dev_priv->pch_pf_size)
5709 enable = true;
5710
5711 intel_set_power_well(dev, enable);
5712 }
5713
5714 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5715 int x, int y,
5716 struct drm_framebuffer *fb)
5717 {
5718 struct drm_device *dev = crtc->dev;
5719 struct drm_i915_private *dev_priv = dev->dev_private;
5720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5721 struct drm_display_mode *adjusted_mode =
5722 &intel_crtc->config.adjusted_mode;
5723 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5724 int pipe = intel_crtc->pipe;
5725 int plane = intel_crtc->plane;
5726 int num_connectors = 0;
5727 bool is_dp = false, is_cpu_edp = false;
5728 struct intel_encoder *encoder;
5729 int ret;
5730 bool dither;
5731
5732 for_each_encoder_on_crtc(dev, crtc, encoder) {
5733 switch (encoder->type) {
5734 case INTEL_OUTPUT_DISPLAYPORT:
5735 is_dp = true;
5736 break;
5737 case INTEL_OUTPUT_EDP:
5738 is_dp = true;
5739 if (!intel_encoder_is_pch_edp(&encoder->base))
5740 is_cpu_edp = true;
5741 break;
5742 }
5743
5744 num_connectors++;
5745 }
5746
5747 if (is_cpu_edp)
5748 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5749 else
5750 intel_crtc->cpu_transcoder = pipe;
5751
5752 /* We are not sure yet this won't happen. */
5753 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5754 INTEL_PCH_TYPE(dev));
5755
5756 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5757 num_connectors, pipe_name(pipe));
5758
5759 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5760 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5761
5762 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5763
5764 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5765 return -EINVAL;
5766
5767 /* Ensure that the cursor is valid for the new mode before changing... */
5768 intel_crtc_update_cursor(crtc, true);
5769
5770 /* determine panel color depth */
5771 dither = intel_crtc->config.dither;
5772
5773 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5774 drm_mode_debug_printmodeline(mode);
5775
5776 if (is_dp && !is_cpu_edp)
5777 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5778
5779 intel_crtc->lowfreq_avail = false;
5780
5781 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5782
5783 if (!is_dp || is_cpu_edp)
5784 ironlake_set_m_n(crtc);
5785
5786 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5787
5788 intel_set_pipe_csc(crtc);
5789
5790 /* Set up the display plane register */
5791 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5792 POSTING_READ(DSPCNTR(plane));
5793
5794 ret = intel_pipe_set_base(crtc, x, y, fb);
5795
5796 intel_update_watermarks(dev);
5797
5798 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5799
5800 return ret;
5801 }
5802
5803 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5804 int x, int y,
5805 struct drm_framebuffer *fb)
5806 {
5807 struct drm_device *dev = crtc->dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 struct drm_encoder_helper_funcs *encoder_funcs;
5810 struct intel_encoder *encoder;
5811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5812 struct drm_display_mode *adjusted_mode =
5813 &intel_crtc->config.adjusted_mode;
5814 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5815 int pipe = intel_crtc->pipe;
5816 int ret;
5817
5818 drm_vblank_pre_modeset(dev, pipe);
5819
5820 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5821
5822 drm_vblank_post_modeset(dev, pipe);
5823
5824 if (ret != 0)
5825 return ret;
5826
5827 for_each_encoder_on_crtc(dev, crtc, encoder) {
5828 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5829 encoder->base.base.id,
5830 drm_get_encoder_name(&encoder->base),
5831 mode->base.id, mode->name);
5832 if (encoder->mode_set) {
5833 encoder->mode_set(encoder);
5834 } else {
5835 encoder_funcs = encoder->base.helper_private;
5836 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5837 }
5838 }
5839
5840 return 0;
5841 }
5842
5843 static bool intel_eld_uptodate(struct drm_connector *connector,
5844 int reg_eldv, uint32_t bits_eldv,
5845 int reg_elda, uint32_t bits_elda,
5846 int reg_edid)
5847 {
5848 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5849 uint8_t *eld = connector->eld;
5850 uint32_t i;
5851
5852 i = I915_READ(reg_eldv);
5853 i &= bits_eldv;
5854
5855 if (!eld[0])
5856 return !i;
5857
5858 if (!i)
5859 return false;
5860
5861 i = I915_READ(reg_elda);
5862 i &= ~bits_elda;
5863 I915_WRITE(reg_elda, i);
5864
5865 for (i = 0; i < eld[2]; i++)
5866 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5867 return false;
5868
5869 return true;
5870 }
5871
5872 static void g4x_write_eld(struct drm_connector *connector,
5873 struct drm_crtc *crtc)
5874 {
5875 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5876 uint8_t *eld = connector->eld;
5877 uint32_t eldv;
5878 uint32_t len;
5879 uint32_t i;
5880
5881 i = I915_READ(G4X_AUD_VID_DID);
5882
5883 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5884 eldv = G4X_ELDV_DEVCL_DEVBLC;
5885 else
5886 eldv = G4X_ELDV_DEVCTG;
5887
5888 if (intel_eld_uptodate(connector,
5889 G4X_AUD_CNTL_ST, eldv,
5890 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5891 G4X_HDMIW_HDMIEDID))
5892 return;
5893
5894 i = I915_READ(G4X_AUD_CNTL_ST);
5895 i &= ~(eldv | G4X_ELD_ADDR);
5896 len = (i >> 9) & 0x1f; /* ELD buffer size */
5897 I915_WRITE(G4X_AUD_CNTL_ST, i);
5898
5899 if (!eld[0])
5900 return;
5901
5902 len = min_t(uint8_t, eld[2], len);
5903 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5904 for (i = 0; i < len; i++)
5905 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5906
5907 i = I915_READ(G4X_AUD_CNTL_ST);
5908 i |= eldv;
5909 I915_WRITE(G4X_AUD_CNTL_ST, i);
5910 }
5911
5912 static void haswell_write_eld(struct drm_connector *connector,
5913 struct drm_crtc *crtc)
5914 {
5915 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5916 uint8_t *eld = connector->eld;
5917 struct drm_device *dev = crtc->dev;
5918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5919 uint32_t eldv;
5920 uint32_t i;
5921 int len;
5922 int pipe = to_intel_crtc(crtc)->pipe;
5923 int tmp;
5924
5925 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5926 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5927 int aud_config = HSW_AUD_CFG(pipe);
5928 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5929
5930
5931 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5932
5933 /* Audio output enable */
5934 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5935 tmp = I915_READ(aud_cntrl_st2);
5936 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5937 I915_WRITE(aud_cntrl_st2, tmp);
5938
5939 /* Wait for 1 vertical blank */
5940 intel_wait_for_vblank(dev, pipe);
5941
5942 /* Set ELD valid state */
5943 tmp = I915_READ(aud_cntrl_st2);
5944 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5945 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5946 I915_WRITE(aud_cntrl_st2, tmp);
5947 tmp = I915_READ(aud_cntrl_st2);
5948 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5949
5950 /* Enable HDMI mode */
5951 tmp = I915_READ(aud_config);
5952 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5953 /* clear N_programing_enable and N_value_index */
5954 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5955 I915_WRITE(aud_config, tmp);
5956
5957 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5958
5959 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5960 intel_crtc->eld_vld = true;
5961
5962 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5963 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5964 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5965 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5966 } else
5967 I915_WRITE(aud_config, 0);
5968
5969 if (intel_eld_uptodate(connector,
5970 aud_cntrl_st2, eldv,
5971 aud_cntl_st, IBX_ELD_ADDRESS,
5972 hdmiw_hdmiedid))
5973 return;
5974
5975 i = I915_READ(aud_cntrl_st2);
5976 i &= ~eldv;
5977 I915_WRITE(aud_cntrl_st2, i);
5978
5979 if (!eld[0])
5980 return;
5981
5982 i = I915_READ(aud_cntl_st);
5983 i &= ~IBX_ELD_ADDRESS;
5984 I915_WRITE(aud_cntl_st, i);
5985 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5986 DRM_DEBUG_DRIVER("port num:%d\n", i);
5987
5988 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5989 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5990 for (i = 0; i < len; i++)
5991 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5992
5993 i = I915_READ(aud_cntrl_st2);
5994 i |= eldv;
5995 I915_WRITE(aud_cntrl_st2, i);
5996
5997 }
5998
5999 static void ironlake_write_eld(struct drm_connector *connector,
6000 struct drm_crtc *crtc)
6001 {
6002 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6003 uint8_t *eld = connector->eld;
6004 uint32_t eldv;
6005 uint32_t i;
6006 int len;
6007 int hdmiw_hdmiedid;
6008 int aud_config;
6009 int aud_cntl_st;
6010 int aud_cntrl_st2;
6011 int pipe = to_intel_crtc(crtc)->pipe;
6012
6013 if (HAS_PCH_IBX(connector->dev)) {
6014 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6015 aud_config = IBX_AUD_CFG(pipe);
6016 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6017 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6018 } else {
6019 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6020 aud_config = CPT_AUD_CFG(pipe);
6021 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6022 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6023 }
6024
6025 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6026
6027 i = I915_READ(aud_cntl_st);
6028 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6029 if (!i) {
6030 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6031 /* operate blindly on all ports */
6032 eldv = IBX_ELD_VALIDB;
6033 eldv |= IBX_ELD_VALIDB << 4;
6034 eldv |= IBX_ELD_VALIDB << 8;
6035 } else {
6036 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6037 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6038 }
6039
6040 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6041 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6042 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6043 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6044 } else
6045 I915_WRITE(aud_config, 0);
6046
6047 if (intel_eld_uptodate(connector,
6048 aud_cntrl_st2, eldv,
6049 aud_cntl_st, IBX_ELD_ADDRESS,
6050 hdmiw_hdmiedid))
6051 return;
6052
6053 i = I915_READ(aud_cntrl_st2);
6054 i &= ~eldv;
6055 I915_WRITE(aud_cntrl_st2, i);
6056
6057 if (!eld[0])
6058 return;
6059
6060 i = I915_READ(aud_cntl_st);
6061 i &= ~IBX_ELD_ADDRESS;
6062 I915_WRITE(aud_cntl_st, i);
6063
6064 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6065 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6066 for (i = 0; i < len; i++)
6067 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6068
6069 i = I915_READ(aud_cntrl_st2);
6070 i |= eldv;
6071 I915_WRITE(aud_cntrl_st2, i);
6072 }
6073
6074 void intel_write_eld(struct drm_encoder *encoder,
6075 struct drm_display_mode *mode)
6076 {
6077 struct drm_crtc *crtc = encoder->crtc;
6078 struct drm_connector *connector;
6079 struct drm_device *dev = encoder->dev;
6080 struct drm_i915_private *dev_priv = dev->dev_private;
6081
6082 connector = drm_select_eld(encoder, mode);
6083 if (!connector)
6084 return;
6085
6086 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6087 connector->base.id,
6088 drm_get_connector_name(connector),
6089 connector->encoder->base.id,
6090 drm_get_encoder_name(connector->encoder));
6091
6092 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6093
6094 if (dev_priv->display.write_eld)
6095 dev_priv->display.write_eld(connector, crtc);
6096 }
6097
6098 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6099 void intel_crtc_load_lut(struct drm_crtc *crtc)
6100 {
6101 struct drm_device *dev = crtc->dev;
6102 struct drm_i915_private *dev_priv = dev->dev_private;
6103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6104 int palreg = PALETTE(intel_crtc->pipe);
6105 int i;
6106
6107 /* The clocks have to be on to load the palette. */
6108 if (!crtc->enabled || !intel_crtc->active)
6109 return;
6110
6111 /* use legacy palette for Ironlake */
6112 if (HAS_PCH_SPLIT(dev))
6113 palreg = LGC_PALETTE(intel_crtc->pipe);
6114
6115 for (i = 0; i < 256; i++) {
6116 I915_WRITE(palreg + 4 * i,
6117 (intel_crtc->lut_r[i] << 16) |
6118 (intel_crtc->lut_g[i] << 8) |
6119 intel_crtc->lut_b[i]);
6120 }
6121 }
6122
6123 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6124 {
6125 struct drm_device *dev = crtc->dev;
6126 struct drm_i915_private *dev_priv = dev->dev_private;
6127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6128 bool visible = base != 0;
6129 u32 cntl;
6130
6131 if (intel_crtc->cursor_visible == visible)
6132 return;
6133
6134 cntl = I915_READ(_CURACNTR);
6135 if (visible) {
6136 /* On these chipsets we can only modify the base whilst
6137 * the cursor is disabled.
6138 */
6139 I915_WRITE(_CURABASE, base);
6140
6141 cntl &= ~(CURSOR_FORMAT_MASK);
6142 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6143 cntl |= CURSOR_ENABLE |
6144 CURSOR_GAMMA_ENABLE |
6145 CURSOR_FORMAT_ARGB;
6146 } else
6147 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6148 I915_WRITE(_CURACNTR, cntl);
6149
6150 intel_crtc->cursor_visible = visible;
6151 }
6152
6153 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6154 {
6155 struct drm_device *dev = crtc->dev;
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6158 int pipe = intel_crtc->pipe;
6159 bool visible = base != 0;
6160
6161 if (intel_crtc->cursor_visible != visible) {
6162 uint32_t cntl = I915_READ(CURCNTR(pipe));
6163 if (base) {
6164 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6165 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6166 cntl |= pipe << 28; /* Connect to correct pipe */
6167 } else {
6168 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6169 cntl |= CURSOR_MODE_DISABLE;
6170 }
6171 I915_WRITE(CURCNTR(pipe), cntl);
6172
6173 intel_crtc->cursor_visible = visible;
6174 }
6175 /* and commit changes on next vblank */
6176 I915_WRITE(CURBASE(pipe), base);
6177 }
6178
6179 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6180 {
6181 struct drm_device *dev = crtc->dev;
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6184 int pipe = intel_crtc->pipe;
6185 bool visible = base != 0;
6186
6187 if (intel_crtc->cursor_visible != visible) {
6188 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6189 if (base) {
6190 cntl &= ~CURSOR_MODE;
6191 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6192 } else {
6193 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6194 cntl |= CURSOR_MODE_DISABLE;
6195 }
6196 if (IS_HASWELL(dev))
6197 cntl |= CURSOR_PIPE_CSC_ENABLE;
6198 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6199
6200 intel_crtc->cursor_visible = visible;
6201 }
6202 /* and commit changes on next vblank */
6203 I915_WRITE(CURBASE_IVB(pipe), base);
6204 }
6205
6206 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6207 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6208 bool on)
6209 {
6210 struct drm_device *dev = crtc->dev;
6211 struct drm_i915_private *dev_priv = dev->dev_private;
6212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6213 int pipe = intel_crtc->pipe;
6214 int x = intel_crtc->cursor_x;
6215 int y = intel_crtc->cursor_y;
6216 u32 base, pos;
6217 bool visible;
6218
6219 pos = 0;
6220
6221 if (on && crtc->enabled && crtc->fb) {
6222 base = intel_crtc->cursor_addr;
6223 if (x > (int) crtc->fb->width)
6224 base = 0;
6225
6226 if (y > (int) crtc->fb->height)
6227 base = 0;
6228 } else
6229 base = 0;
6230
6231 if (x < 0) {
6232 if (x + intel_crtc->cursor_width < 0)
6233 base = 0;
6234
6235 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6236 x = -x;
6237 }
6238 pos |= x << CURSOR_X_SHIFT;
6239
6240 if (y < 0) {
6241 if (y + intel_crtc->cursor_height < 0)
6242 base = 0;
6243
6244 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6245 y = -y;
6246 }
6247 pos |= y << CURSOR_Y_SHIFT;
6248
6249 visible = base != 0;
6250 if (!visible && !intel_crtc->cursor_visible)
6251 return;
6252
6253 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6254 I915_WRITE(CURPOS_IVB(pipe), pos);
6255 ivb_update_cursor(crtc, base);
6256 } else {
6257 I915_WRITE(CURPOS(pipe), pos);
6258 if (IS_845G(dev) || IS_I865G(dev))
6259 i845_update_cursor(crtc, base);
6260 else
6261 i9xx_update_cursor(crtc, base);
6262 }
6263 }
6264
6265 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6266 struct drm_file *file,
6267 uint32_t handle,
6268 uint32_t width, uint32_t height)
6269 {
6270 struct drm_device *dev = crtc->dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273 struct drm_i915_gem_object *obj;
6274 uint32_t addr;
6275 int ret;
6276
6277 /* if we want to turn off the cursor ignore width and height */
6278 if (!handle) {
6279 DRM_DEBUG_KMS("cursor off\n");
6280 addr = 0;
6281 obj = NULL;
6282 mutex_lock(&dev->struct_mutex);
6283 goto finish;
6284 }
6285
6286 /* Currently we only support 64x64 cursors */
6287 if (width != 64 || height != 64) {
6288 DRM_ERROR("we currently only support 64x64 cursors\n");
6289 return -EINVAL;
6290 }
6291
6292 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6293 if (&obj->base == NULL)
6294 return -ENOENT;
6295
6296 if (obj->base.size < width * height * 4) {
6297 DRM_ERROR("buffer is to small\n");
6298 ret = -ENOMEM;
6299 goto fail;
6300 }
6301
6302 /* we only need to pin inside GTT if cursor is non-phy */
6303 mutex_lock(&dev->struct_mutex);
6304 if (!dev_priv->info->cursor_needs_physical) {
6305 unsigned alignment;
6306
6307 if (obj->tiling_mode) {
6308 DRM_ERROR("cursor cannot be tiled\n");
6309 ret = -EINVAL;
6310 goto fail_locked;
6311 }
6312
6313 /* Note that the w/a also requires 2 PTE of padding following
6314 * the bo. We currently fill all unused PTE with the shadow
6315 * page and so we should always have valid PTE following the
6316 * cursor preventing the VT-d warning.
6317 */
6318 alignment = 0;
6319 if (need_vtd_wa(dev))
6320 alignment = 64*1024;
6321
6322 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6323 if (ret) {
6324 DRM_ERROR("failed to move cursor bo into the GTT\n");
6325 goto fail_locked;
6326 }
6327
6328 ret = i915_gem_object_put_fence(obj);
6329 if (ret) {
6330 DRM_ERROR("failed to release fence for cursor");
6331 goto fail_unpin;
6332 }
6333
6334 addr = obj->gtt_offset;
6335 } else {
6336 int align = IS_I830(dev) ? 16 * 1024 : 256;
6337 ret = i915_gem_attach_phys_object(dev, obj,
6338 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6339 align);
6340 if (ret) {
6341 DRM_ERROR("failed to attach phys object\n");
6342 goto fail_locked;
6343 }
6344 addr = obj->phys_obj->handle->busaddr;
6345 }
6346
6347 if (IS_GEN2(dev))
6348 I915_WRITE(CURSIZE, (height << 12) | width);
6349
6350 finish:
6351 if (intel_crtc->cursor_bo) {
6352 if (dev_priv->info->cursor_needs_physical) {
6353 if (intel_crtc->cursor_bo != obj)
6354 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6355 } else
6356 i915_gem_object_unpin(intel_crtc->cursor_bo);
6357 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6358 }
6359
6360 mutex_unlock(&dev->struct_mutex);
6361
6362 intel_crtc->cursor_addr = addr;
6363 intel_crtc->cursor_bo = obj;
6364 intel_crtc->cursor_width = width;
6365 intel_crtc->cursor_height = height;
6366
6367 intel_crtc_update_cursor(crtc, true);
6368
6369 return 0;
6370 fail_unpin:
6371 i915_gem_object_unpin(obj);
6372 fail_locked:
6373 mutex_unlock(&dev->struct_mutex);
6374 fail:
6375 drm_gem_object_unreference_unlocked(&obj->base);
6376 return ret;
6377 }
6378
6379 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6380 {
6381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382
6383 intel_crtc->cursor_x = x;
6384 intel_crtc->cursor_y = y;
6385
6386 intel_crtc_update_cursor(crtc, true);
6387
6388 return 0;
6389 }
6390
6391 /** Sets the color ramps on behalf of RandR */
6392 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6393 u16 blue, int regno)
6394 {
6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396
6397 intel_crtc->lut_r[regno] = red >> 8;
6398 intel_crtc->lut_g[regno] = green >> 8;
6399 intel_crtc->lut_b[regno] = blue >> 8;
6400 }
6401
6402 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6403 u16 *blue, int regno)
6404 {
6405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406
6407 *red = intel_crtc->lut_r[regno] << 8;
6408 *green = intel_crtc->lut_g[regno] << 8;
6409 *blue = intel_crtc->lut_b[regno] << 8;
6410 }
6411
6412 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6413 u16 *blue, uint32_t start, uint32_t size)
6414 {
6415 int end = (start + size > 256) ? 256 : start + size, i;
6416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6417
6418 for (i = start; i < end; i++) {
6419 intel_crtc->lut_r[i] = red[i] >> 8;
6420 intel_crtc->lut_g[i] = green[i] >> 8;
6421 intel_crtc->lut_b[i] = blue[i] >> 8;
6422 }
6423
6424 intel_crtc_load_lut(crtc);
6425 }
6426
6427 /* VESA 640x480x72Hz mode to set on the pipe */
6428 static struct drm_display_mode load_detect_mode = {
6429 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6430 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6431 };
6432
6433 static struct drm_framebuffer *
6434 intel_framebuffer_create(struct drm_device *dev,
6435 struct drm_mode_fb_cmd2 *mode_cmd,
6436 struct drm_i915_gem_object *obj)
6437 {
6438 struct intel_framebuffer *intel_fb;
6439 int ret;
6440
6441 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6442 if (!intel_fb) {
6443 drm_gem_object_unreference_unlocked(&obj->base);
6444 return ERR_PTR(-ENOMEM);
6445 }
6446
6447 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6448 if (ret) {
6449 drm_gem_object_unreference_unlocked(&obj->base);
6450 kfree(intel_fb);
6451 return ERR_PTR(ret);
6452 }
6453
6454 return &intel_fb->base;
6455 }
6456
6457 static u32
6458 intel_framebuffer_pitch_for_width(int width, int bpp)
6459 {
6460 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6461 return ALIGN(pitch, 64);
6462 }
6463
6464 static u32
6465 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6466 {
6467 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6468 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6469 }
6470
6471 static struct drm_framebuffer *
6472 intel_framebuffer_create_for_mode(struct drm_device *dev,
6473 struct drm_display_mode *mode,
6474 int depth, int bpp)
6475 {
6476 struct drm_i915_gem_object *obj;
6477 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6478
6479 obj = i915_gem_alloc_object(dev,
6480 intel_framebuffer_size_for_mode(mode, bpp));
6481 if (obj == NULL)
6482 return ERR_PTR(-ENOMEM);
6483
6484 mode_cmd.width = mode->hdisplay;
6485 mode_cmd.height = mode->vdisplay;
6486 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6487 bpp);
6488 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6489
6490 return intel_framebuffer_create(dev, &mode_cmd, obj);
6491 }
6492
6493 static struct drm_framebuffer *
6494 mode_fits_in_fbdev(struct drm_device *dev,
6495 struct drm_display_mode *mode)
6496 {
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498 struct drm_i915_gem_object *obj;
6499 struct drm_framebuffer *fb;
6500
6501 if (dev_priv->fbdev == NULL)
6502 return NULL;
6503
6504 obj = dev_priv->fbdev->ifb.obj;
6505 if (obj == NULL)
6506 return NULL;
6507
6508 fb = &dev_priv->fbdev->ifb.base;
6509 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6510 fb->bits_per_pixel))
6511 return NULL;
6512
6513 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6514 return NULL;
6515
6516 return fb;
6517 }
6518
6519 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6520 struct drm_display_mode *mode,
6521 struct intel_load_detect_pipe *old)
6522 {
6523 struct intel_crtc *intel_crtc;
6524 struct intel_encoder *intel_encoder =
6525 intel_attached_encoder(connector);
6526 struct drm_crtc *possible_crtc;
6527 struct drm_encoder *encoder = &intel_encoder->base;
6528 struct drm_crtc *crtc = NULL;
6529 struct drm_device *dev = encoder->dev;
6530 struct drm_framebuffer *fb;
6531 int i = -1;
6532
6533 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6534 connector->base.id, drm_get_connector_name(connector),
6535 encoder->base.id, drm_get_encoder_name(encoder));
6536
6537 /*
6538 * Algorithm gets a little messy:
6539 *
6540 * - if the connector already has an assigned crtc, use it (but make
6541 * sure it's on first)
6542 *
6543 * - try to find the first unused crtc that can drive this connector,
6544 * and use that if we find one
6545 */
6546
6547 /* See if we already have a CRTC for this connector */
6548 if (encoder->crtc) {
6549 crtc = encoder->crtc;
6550
6551 mutex_lock(&crtc->mutex);
6552
6553 old->dpms_mode = connector->dpms;
6554 old->load_detect_temp = false;
6555
6556 /* Make sure the crtc and connector are running */
6557 if (connector->dpms != DRM_MODE_DPMS_ON)
6558 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6559
6560 return true;
6561 }
6562
6563 /* Find an unused one (if possible) */
6564 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6565 i++;
6566 if (!(encoder->possible_crtcs & (1 << i)))
6567 continue;
6568 if (!possible_crtc->enabled) {
6569 crtc = possible_crtc;
6570 break;
6571 }
6572 }
6573
6574 /*
6575 * If we didn't find an unused CRTC, don't use any.
6576 */
6577 if (!crtc) {
6578 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6579 return false;
6580 }
6581
6582 mutex_lock(&crtc->mutex);
6583 intel_encoder->new_crtc = to_intel_crtc(crtc);
6584 to_intel_connector(connector)->new_encoder = intel_encoder;
6585
6586 intel_crtc = to_intel_crtc(crtc);
6587 old->dpms_mode = connector->dpms;
6588 old->load_detect_temp = true;
6589 old->release_fb = NULL;
6590
6591 if (!mode)
6592 mode = &load_detect_mode;
6593
6594 /* We need a framebuffer large enough to accommodate all accesses
6595 * that the plane may generate whilst we perform load detection.
6596 * We can not rely on the fbcon either being present (we get called
6597 * during its initialisation to detect all boot displays, or it may
6598 * not even exist) or that it is large enough to satisfy the
6599 * requested mode.
6600 */
6601 fb = mode_fits_in_fbdev(dev, mode);
6602 if (fb == NULL) {
6603 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6604 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6605 old->release_fb = fb;
6606 } else
6607 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6608 if (IS_ERR(fb)) {
6609 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6610 mutex_unlock(&crtc->mutex);
6611 return false;
6612 }
6613
6614 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6615 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6616 if (old->release_fb)
6617 old->release_fb->funcs->destroy(old->release_fb);
6618 mutex_unlock(&crtc->mutex);
6619 return false;
6620 }
6621
6622 /* let the connector get through one full cycle before testing */
6623 intel_wait_for_vblank(dev, intel_crtc->pipe);
6624 return true;
6625 }
6626
6627 void intel_release_load_detect_pipe(struct drm_connector *connector,
6628 struct intel_load_detect_pipe *old)
6629 {
6630 struct intel_encoder *intel_encoder =
6631 intel_attached_encoder(connector);
6632 struct drm_encoder *encoder = &intel_encoder->base;
6633 struct drm_crtc *crtc = encoder->crtc;
6634
6635 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6636 connector->base.id, drm_get_connector_name(connector),
6637 encoder->base.id, drm_get_encoder_name(encoder));
6638
6639 if (old->load_detect_temp) {
6640 to_intel_connector(connector)->new_encoder = NULL;
6641 intel_encoder->new_crtc = NULL;
6642 intel_set_mode(crtc, NULL, 0, 0, NULL);
6643
6644 if (old->release_fb) {
6645 drm_framebuffer_unregister_private(old->release_fb);
6646 drm_framebuffer_unreference(old->release_fb);
6647 }
6648
6649 mutex_unlock(&crtc->mutex);
6650 return;
6651 }
6652
6653 /* Switch crtc and encoder back off if necessary */
6654 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6655 connector->funcs->dpms(connector, old->dpms_mode);
6656
6657 mutex_unlock(&crtc->mutex);
6658 }
6659
6660 /* Returns the clock of the currently programmed mode of the given pipe. */
6661 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6662 {
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665 int pipe = intel_crtc->pipe;
6666 u32 dpll = I915_READ(DPLL(pipe));
6667 u32 fp;
6668 intel_clock_t clock;
6669
6670 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6671 fp = I915_READ(FP0(pipe));
6672 else
6673 fp = I915_READ(FP1(pipe));
6674
6675 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6676 if (IS_PINEVIEW(dev)) {
6677 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6678 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6679 } else {
6680 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6681 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6682 }
6683
6684 if (!IS_GEN2(dev)) {
6685 if (IS_PINEVIEW(dev))
6686 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6687 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6688 else
6689 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6690 DPLL_FPA01_P1_POST_DIV_SHIFT);
6691
6692 switch (dpll & DPLL_MODE_MASK) {
6693 case DPLLB_MODE_DAC_SERIAL:
6694 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6695 5 : 10;
6696 break;
6697 case DPLLB_MODE_LVDS:
6698 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6699 7 : 14;
6700 break;
6701 default:
6702 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6703 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6704 return 0;
6705 }
6706
6707 /* XXX: Handle the 100Mhz refclk */
6708 intel_clock(dev, 96000, &clock);
6709 } else {
6710 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6711
6712 if (is_lvds) {
6713 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6714 DPLL_FPA01_P1_POST_DIV_SHIFT);
6715 clock.p2 = 14;
6716
6717 if ((dpll & PLL_REF_INPUT_MASK) ==
6718 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6719 /* XXX: might not be 66MHz */
6720 intel_clock(dev, 66000, &clock);
6721 } else
6722 intel_clock(dev, 48000, &clock);
6723 } else {
6724 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6725 clock.p1 = 2;
6726 else {
6727 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6728 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6729 }
6730 if (dpll & PLL_P2_DIVIDE_BY_4)
6731 clock.p2 = 4;
6732 else
6733 clock.p2 = 2;
6734
6735 intel_clock(dev, 48000, &clock);
6736 }
6737 }
6738
6739 /* XXX: It would be nice to validate the clocks, but we can't reuse
6740 * i830PllIsValid() because it relies on the xf86_config connector
6741 * configuration being accurate, which it isn't necessarily.
6742 */
6743
6744 return clock.dot;
6745 }
6746
6747 /** Returns the currently programmed mode of the given pipe. */
6748 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6749 struct drm_crtc *crtc)
6750 {
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6753 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6754 struct drm_display_mode *mode;
6755 int htot = I915_READ(HTOTAL(cpu_transcoder));
6756 int hsync = I915_READ(HSYNC(cpu_transcoder));
6757 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6758 int vsync = I915_READ(VSYNC(cpu_transcoder));
6759
6760 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6761 if (!mode)
6762 return NULL;
6763
6764 mode->clock = intel_crtc_clock_get(dev, crtc);
6765 mode->hdisplay = (htot & 0xffff) + 1;
6766 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6767 mode->hsync_start = (hsync & 0xffff) + 1;
6768 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6769 mode->vdisplay = (vtot & 0xffff) + 1;
6770 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6771 mode->vsync_start = (vsync & 0xffff) + 1;
6772 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6773
6774 drm_mode_set_name(mode);
6775
6776 return mode;
6777 }
6778
6779 static void intel_increase_pllclock(struct drm_crtc *crtc)
6780 {
6781 struct drm_device *dev = crtc->dev;
6782 drm_i915_private_t *dev_priv = dev->dev_private;
6783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784 int pipe = intel_crtc->pipe;
6785 int dpll_reg = DPLL(pipe);
6786 int dpll;
6787
6788 if (HAS_PCH_SPLIT(dev))
6789 return;
6790
6791 if (!dev_priv->lvds_downclock_avail)
6792 return;
6793
6794 dpll = I915_READ(dpll_reg);
6795 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6796 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6797
6798 assert_panel_unlocked(dev_priv, pipe);
6799
6800 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6801 I915_WRITE(dpll_reg, dpll);
6802 intel_wait_for_vblank(dev, pipe);
6803
6804 dpll = I915_READ(dpll_reg);
6805 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6806 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6807 }
6808 }
6809
6810 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6811 {
6812 struct drm_device *dev = crtc->dev;
6813 drm_i915_private_t *dev_priv = dev->dev_private;
6814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6815
6816 if (HAS_PCH_SPLIT(dev))
6817 return;
6818
6819 if (!dev_priv->lvds_downclock_avail)
6820 return;
6821
6822 /*
6823 * Since this is called by a timer, we should never get here in
6824 * the manual case.
6825 */
6826 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6827 int pipe = intel_crtc->pipe;
6828 int dpll_reg = DPLL(pipe);
6829 int dpll;
6830
6831 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6832
6833 assert_panel_unlocked(dev_priv, pipe);
6834
6835 dpll = I915_READ(dpll_reg);
6836 dpll |= DISPLAY_RATE_SELECT_FPA1;
6837 I915_WRITE(dpll_reg, dpll);
6838 intel_wait_for_vblank(dev, pipe);
6839 dpll = I915_READ(dpll_reg);
6840 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6841 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6842 }
6843
6844 }
6845
6846 void intel_mark_busy(struct drm_device *dev)
6847 {
6848 i915_update_gfx_val(dev->dev_private);
6849 }
6850
6851 void intel_mark_idle(struct drm_device *dev)
6852 {
6853 struct drm_crtc *crtc;
6854
6855 if (!i915_powersave)
6856 return;
6857
6858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6859 if (!crtc->fb)
6860 continue;
6861
6862 intel_decrease_pllclock(crtc);
6863 }
6864 }
6865
6866 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6867 {
6868 struct drm_device *dev = obj->base.dev;
6869 struct drm_crtc *crtc;
6870
6871 if (!i915_powersave)
6872 return;
6873
6874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6875 if (!crtc->fb)
6876 continue;
6877
6878 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6879 intel_increase_pllclock(crtc);
6880 }
6881 }
6882
6883 static void intel_crtc_destroy(struct drm_crtc *crtc)
6884 {
6885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6886 struct drm_device *dev = crtc->dev;
6887 struct intel_unpin_work *work;
6888 unsigned long flags;
6889
6890 spin_lock_irqsave(&dev->event_lock, flags);
6891 work = intel_crtc->unpin_work;
6892 intel_crtc->unpin_work = NULL;
6893 spin_unlock_irqrestore(&dev->event_lock, flags);
6894
6895 if (work) {
6896 cancel_work_sync(&work->work);
6897 kfree(work);
6898 }
6899
6900 drm_crtc_cleanup(crtc);
6901
6902 kfree(intel_crtc);
6903 }
6904
6905 static void intel_unpin_work_fn(struct work_struct *__work)
6906 {
6907 struct intel_unpin_work *work =
6908 container_of(__work, struct intel_unpin_work, work);
6909 struct drm_device *dev = work->crtc->dev;
6910
6911 mutex_lock(&dev->struct_mutex);
6912 intel_unpin_fb_obj(work->old_fb_obj);
6913 drm_gem_object_unreference(&work->pending_flip_obj->base);
6914 drm_gem_object_unreference(&work->old_fb_obj->base);
6915
6916 intel_update_fbc(dev);
6917 mutex_unlock(&dev->struct_mutex);
6918
6919 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6920 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6921
6922 kfree(work);
6923 }
6924
6925 static void do_intel_finish_page_flip(struct drm_device *dev,
6926 struct drm_crtc *crtc)
6927 {
6928 drm_i915_private_t *dev_priv = dev->dev_private;
6929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6930 struct intel_unpin_work *work;
6931 unsigned long flags;
6932
6933 /* Ignore early vblank irqs */
6934 if (intel_crtc == NULL)
6935 return;
6936
6937 spin_lock_irqsave(&dev->event_lock, flags);
6938 work = intel_crtc->unpin_work;
6939
6940 /* Ensure we don't miss a work->pending update ... */
6941 smp_rmb();
6942
6943 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6944 spin_unlock_irqrestore(&dev->event_lock, flags);
6945 return;
6946 }
6947
6948 /* and that the unpin work is consistent wrt ->pending. */
6949 smp_rmb();
6950
6951 intel_crtc->unpin_work = NULL;
6952
6953 if (work->event)
6954 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6955
6956 drm_vblank_put(dev, intel_crtc->pipe);
6957
6958 spin_unlock_irqrestore(&dev->event_lock, flags);
6959
6960 wake_up_all(&dev_priv->pending_flip_queue);
6961
6962 queue_work(dev_priv->wq, &work->work);
6963
6964 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6965 }
6966
6967 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6968 {
6969 drm_i915_private_t *dev_priv = dev->dev_private;
6970 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6971
6972 do_intel_finish_page_flip(dev, crtc);
6973 }
6974
6975 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6976 {
6977 drm_i915_private_t *dev_priv = dev->dev_private;
6978 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6979
6980 do_intel_finish_page_flip(dev, crtc);
6981 }
6982
6983 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6984 {
6985 drm_i915_private_t *dev_priv = dev->dev_private;
6986 struct intel_crtc *intel_crtc =
6987 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6988 unsigned long flags;
6989
6990 /* NB: An MMIO update of the plane base pointer will also
6991 * generate a page-flip completion irq, i.e. every modeset
6992 * is also accompanied by a spurious intel_prepare_page_flip().
6993 */
6994 spin_lock_irqsave(&dev->event_lock, flags);
6995 if (intel_crtc->unpin_work)
6996 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6997 spin_unlock_irqrestore(&dev->event_lock, flags);
6998 }
6999
7000 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7001 {
7002 /* Ensure that the work item is consistent when activating it ... */
7003 smp_wmb();
7004 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7005 /* and that it is marked active as soon as the irq could fire. */
7006 smp_wmb();
7007 }
7008
7009 static int intel_gen2_queue_flip(struct drm_device *dev,
7010 struct drm_crtc *crtc,
7011 struct drm_framebuffer *fb,
7012 struct drm_i915_gem_object *obj)
7013 {
7014 struct drm_i915_private *dev_priv = dev->dev_private;
7015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7016 u32 flip_mask;
7017 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7018 int ret;
7019
7020 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7021 if (ret)
7022 goto err;
7023
7024 ret = intel_ring_begin(ring, 6);
7025 if (ret)
7026 goto err_unpin;
7027
7028 /* Can't queue multiple flips, so wait for the previous
7029 * one to finish before executing the next.
7030 */
7031 if (intel_crtc->plane)
7032 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7033 else
7034 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7035 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7036 intel_ring_emit(ring, MI_NOOP);
7037 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7039 intel_ring_emit(ring, fb->pitches[0]);
7040 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7041 intel_ring_emit(ring, 0); /* aux display base address, unused */
7042
7043 intel_mark_page_flip_active(intel_crtc);
7044 intel_ring_advance(ring);
7045 return 0;
7046
7047 err_unpin:
7048 intel_unpin_fb_obj(obj);
7049 err:
7050 return ret;
7051 }
7052
7053 static int intel_gen3_queue_flip(struct drm_device *dev,
7054 struct drm_crtc *crtc,
7055 struct drm_framebuffer *fb,
7056 struct drm_i915_gem_object *obj)
7057 {
7058 struct drm_i915_private *dev_priv = dev->dev_private;
7059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7060 u32 flip_mask;
7061 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7062 int ret;
7063
7064 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7065 if (ret)
7066 goto err;
7067
7068 ret = intel_ring_begin(ring, 6);
7069 if (ret)
7070 goto err_unpin;
7071
7072 if (intel_crtc->plane)
7073 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7074 else
7075 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7076 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7077 intel_ring_emit(ring, MI_NOOP);
7078 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7079 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7080 intel_ring_emit(ring, fb->pitches[0]);
7081 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7082 intel_ring_emit(ring, MI_NOOP);
7083
7084 intel_mark_page_flip_active(intel_crtc);
7085 intel_ring_advance(ring);
7086 return 0;
7087
7088 err_unpin:
7089 intel_unpin_fb_obj(obj);
7090 err:
7091 return ret;
7092 }
7093
7094 static int intel_gen4_queue_flip(struct drm_device *dev,
7095 struct drm_crtc *crtc,
7096 struct drm_framebuffer *fb,
7097 struct drm_i915_gem_object *obj)
7098 {
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101 uint32_t pf, pipesrc;
7102 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7103 int ret;
7104
7105 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7106 if (ret)
7107 goto err;
7108
7109 ret = intel_ring_begin(ring, 4);
7110 if (ret)
7111 goto err_unpin;
7112
7113 /* i965+ uses the linear or tiled offsets from the
7114 * Display Registers (which do not change across a page-flip)
7115 * so we need only reprogram the base address.
7116 */
7117 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7118 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7119 intel_ring_emit(ring, fb->pitches[0]);
7120 intel_ring_emit(ring,
7121 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7122 obj->tiling_mode);
7123
7124 /* XXX Enabling the panel-fitter across page-flip is so far
7125 * untested on non-native modes, so ignore it for now.
7126 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7127 */
7128 pf = 0;
7129 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7130 intel_ring_emit(ring, pf | pipesrc);
7131
7132 intel_mark_page_flip_active(intel_crtc);
7133 intel_ring_advance(ring);
7134 return 0;
7135
7136 err_unpin:
7137 intel_unpin_fb_obj(obj);
7138 err:
7139 return ret;
7140 }
7141
7142 static int intel_gen6_queue_flip(struct drm_device *dev,
7143 struct drm_crtc *crtc,
7144 struct drm_framebuffer *fb,
7145 struct drm_i915_gem_object *obj)
7146 {
7147 struct drm_i915_private *dev_priv = dev->dev_private;
7148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7149 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7150 uint32_t pf, pipesrc;
7151 int ret;
7152
7153 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7154 if (ret)
7155 goto err;
7156
7157 ret = intel_ring_begin(ring, 4);
7158 if (ret)
7159 goto err_unpin;
7160
7161 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7162 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7163 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7164 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7165
7166 /* Contrary to the suggestions in the documentation,
7167 * "Enable Panel Fitter" does not seem to be required when page
7168 * flipping with a non-native mode, and worse causes a normal
7169 * modeset to fail.
7170 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7171 */
7172 pf = 0;
7173 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7174 intel_ring_emit(ring, pf | pipesrc);
7175
7176 intel_mark_page_flip_active(intel_crtc);
7177 intel_ring_advance(ring);
7178 return 0;
7179
7180 err_unpin:
7181 intel_unpin_fb_obj(obj);
7182 err:
7183 return ret;
7184 }
7185
7186 /*
7187 * On gen7 we currently use the blit ring because (in early silicon at least)
7188 * the render ring doesn't give us interrpts for page flip completion, which
7189 * means clients will hang after the first flip is queued. Fortunately the
7190 * blit ring generates interrupts properly, so use it instead.
7191 */
7192 static int intel_gen7_queue_flip(struct drm_device *dev,
7193 struct drm_crtc *crtc,
7194 struct drm_framebuffer *fb,
7195 struct drm_i915_gem_object *obj)
7196 {
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7200 uint32_t plane_bit = 0;
7201 int ret;
7202
7203 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7204 if (ret)
7205 goto err;
7206
7207 switch(intel_crtc->plane) {
7208 case PLANE_A:
7209 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7210 break;
7211 case PLANE_B:
7212 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7213 break;
7214 case PLANE_C:
7215 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7216 break;
7217 default:
7218 WARN_ONCE(1, "unknown plane in flip command\n");
7219 ret = -ENODEV;
7220 goto err_unpin;
7221 }
7222
7223 ret = intel_ring_begin(ring, 4);
7224 if (ret)
7225 goto err_unpin;
7226
7227 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7228 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7229 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7230 intel_ring_emit(ring, (MI_NOOP));
7231
7232 intel_mark_page_flip_active(intel_crtc);
7233 intel_ring_advance(ring);
7234 return 0;
7235
7236 err_unpin:
7237 intel_unpin_fb_obj(obj);
7238 err:
7239 return ret;
7240 }
7241
7242 static int intel_default_queue_flip(struct drm_device *dev,
7243 struct drm_crtc *crtc,
7244 struct drm_framebuffer *fb,
7245 struct drm_i915_gem_object *obj)
7246 {
7247 return -ENODEV;
7248 }
7249
7250 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7251 struct drm_framebuffer *fb,
7252 struct drm_pending_vblank_event *event)
7253 {
7254 struct drm_device *dev = crtc->dev;
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256 struct drm_framebuffer *old_fb = crtc->fb;
7257 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7259 struct intel_unpin_work *work;
7260 unsigned long flags;
7261 int ret;
7262
7263 /* Can't change pixel format via MI display flips. */
7264 if (fb->pixel_format != crtc->fb->pixel_format)
7265 return -EINVAL;
7266
7267 /*
7268 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7269 * Note that pitch changes could also affect these register.
7270 */
7271 if (INTEL_INFO(dev)->gen > 3 &&
7272 (fb->offsets[0] != crtc->fb->offsets[0] ||
7273 fb->pitches[0] != crtc->fb->pitches[0]))
7274 return -EINVAL;
7275
7276 work = kzalloc(sizeof *work, GFP_KERNEL);
7277 if (work == NULL)
7278 return -ENOMEM;
7279
7280 work->event = event;
7281 work->crtc = crtc;
7282 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7283 INIT_WORK(&work->work, intel_unpin_work_fn);
7284
7285 ret = drm_vblank_get(dev, intel_crtc->pipe);
7286 if (ret)
7287 goto free_work;
7288
7289 /* We borrow the event spin lock for protecting unpin_work */
7290 spin_lock_irqsave(&dev->event_lock, flags);
7291 if (intel_crtc->unpin_work) {
7292 spin_unlock_irqrestore(&dev->event_lock, flags);
7293 kfree(work);
7294 drm_vblank_put(dev, intel_crtc->pipe);
7295
7296 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7297 return -EBUSY;
7298 }
7299 intel_crtc->unpin_work = work;
7300 spin_unlock_irqrestore(&dev->event_lock, flags);
7301
7302 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7303 flush_workqueue(dev_priv->wq);
7304
7305 ret = i915_mutex_lock_interruptible(dev);
7306 if (ret)
7307 goto cleanup;
7308
7309 /* Reference the objects for the scheduled work. */
7310 drm_gem_object_reference(&work->old_fb_obj->base);
7311 drm_gem_object_reference(&obj->base);
7312
7313 crtc->fb = fb;
7314
7315 work->pending_flip_obj = obj;
7316
7317 work->enable_stall_check = true;
7318
7319 atomic_inc(&intel_crtc->unpin_work_count);
7320 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7321
7322 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7323 if (ret)
7324 goto cleanup_pending;
7325
7326 intel_disable_fbc(dev);
7327 intel_mark_fb_busy(obj);
7328 mutex_unlock(&dev->struct_mutex);
7329
7330 trace_i915_flip_request(intel_crtc->plane, obj);
7331
7332 return 0;
7333
7334 cleanup_pending:
7335 atomic_dec(&intel_crtc->unpin_work_count);
7336 crtc->fb = old_fb;
7337 drm_gem_object_unreference(&work->old_fb_obj->base);
7338 drm_gem_object_unreference(&obj->base);
7339 mutex_unlock(&dev->struct_mutex);
7340
7341 cleanup:
7342 spin_lock_irqsave(&dev->event_lock, flags);
7343 intel_crtc->unpin_work = NULL;
7344 spin_unlock_irqrestore(&dev->event_lock, flags);
7345
7346 drm_vblank_put(dev, intel_crtc->pipe);
7347 free_work:
7348 kfree(work);
7349
7350 return ret;
7351 }
7352
7353 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7354 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7355 .load_lut = intel_crtc_load_lut,
7356 };
7357
7358 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7359 {
7360 struct intel_encoder *other_encoder;
7361 struct drm_crtc *crtc = &encoder->new_crtc->base;
7362
7363 if (WARN_ON(!crtc))
7364 return false;
7365
7366 list_for_each_entry(other_encoder,
7367 &crtc->dev->mode_config.encoder_list,
7368 base.head) {
7369
7370 if (&other_encoder->new_crtc->base != crtc ||
7371 encoder == other_encoder)
7372 continue;
7373 else
7374 return true;
7375 }
7376
7377 return false;
7378 }
7379
7380 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7381 struct drm_crtc *crtc)
7382 {
7383 struct drm_device *dev;
7384 struct drm_crtc *tmp;
7385 int crtc_mask = 1;
7386
7387 WARN(!crtc, "checking null crtc?\n");
7388
7389 dev = crtc->dev;
7390
7391 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7392 if (tmp == crtc)
7393 break;
7394 crtc_mask <<= 1;
7395 }
7396
7397 if (encoder->possible_crtcs & crtc_mask)
7398 return true;
7399 return false;
7400 }
7401
7402 /**
7403 * intel_modeset_update_staged_output_state
7404 *
7405 * Updates the staged output configuration state, e.g. after we've read out the
7406 * current hw state.
7407 */
7408 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7409 {
7410 struct intel_encoder *encoder;
7411 struct intel_connector *connector;
7412
7413 list_for_each_entry(connector, &dev->mode_config.connector_list,
7414 base.head) {
7415 connector->new_encoder =
7416 to_intel_encoder(connector->base.encoder);
7417 }
7418
7419 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7420 base.head) {
7421 encoder->new_crtc =
7422 to_intel_crtc(encoder->base.crtc);
7423 }
7424 }
7425
7426 /**
7427 * intel_modeset_commit_output_state
7428 *
7429 * This function copies the stage display pipe configuration to the real one.
7430 */
7431 static void intel_modeset_commit_output_state(struct drm_device *dev)
7432 {
7433 struct intel_encoder *encoder;
7434 struct intel_connector *connector;
7435
7436 list_for_each_entry(connector, &dev->mode_config.connector_list,
7437 base.head) {
7438 connector->base.encoder = &connector->new_encoder->base;
7439 }
7440
7441 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7442 base.head) {
7443 encoder->base.crtc = &encoder->new_crtc->base;
7444 }
7445 }
7446
7447 static int
7448 pipe_config_set_bpp(struct drm_crtc *crtc,
7449 struct drm_framebuffer *fb,
7450 struct intel_crtc_config *pipe_config)
7451 {
7452 struct drm_device *dev = crtc->dev;
7453 struct drm_connector *connector;
7454 int bpp;
7455
7456 switch (fb->pixel_format) {
7457 case DRM_FORMAT_C8:
7458 bpp = 8*3; /* since we go through a colormap */
7459 break;
7460 case DRM_FORMAT_XRGB1555:
7461 case DRM_FORMAT_ARGB1555:
7462 /* checked in intel_framebuffer_init already */
7463 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7464 return -EINVAL;
7465 case DRM_FORMAT_RGB565:
7466 bpp = 6*3; /* min is 18bpp */
7467 break;
7468 case DRM_FORMAT_XBGR8888:
7469 case DRM_FORMAT_ABGR8888:
7470 /* checked in intel_framebuffer_init already */
7471 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7472 return -EINVAL;
7473 case DRM_FORMAT_XRGB8888:
7474 case DRM_FORMAT_ARGB8888:
7475 bpp = 8*3;
7476 break;
7477 case DRM_FORMAT_XRGB2101010:
7478 case DRM_FORMAT_ARGB2101010:
7479 case DRM_FORMAT_XBGR2101010:
7480 case DRM_FORMAT_ABGR2101010:
7481 /* checked in intel_framebuffer_init already */
7482 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7483 return -EINVAL;
7484 bpp = 10*3;
7485 break;
7486 /* TODO: gen4+ supports 16 bpc floating point, too. */
7487 default:
7488 DRM_DEBUG_KMS("unsupported depth\n");
7489 return -EINVAL;
7490 }
7491
7492 pipe_config->pipe_bpp = bpp;
7493
7494 /* Clamp display bpp to EDID value */
7495 list_for_each_entry(connector, &dev->mode_config.connector_list,
7496 head) {
7497 if (connector->encoder && connector->encoder->crtc != crtc)
7498 continue;
7499
7500 /* Don't use an invalid EDID bpc value */
7501 if (connector->display_info.bpc &&
7502 connector->display_info.bpc * 3 < bpp) {
7503 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7504 bpp, connector->display_info.bpc*3);
7505 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7506 }
7507 }
7508
7509 return bpp;
7510 }
7511
7512 static struct intel_crtc_config *
7513 intel_modeset_pipe_config(struct drm_crtc *crtc,
7514 struct drm_framebuffer *fb,
7515 struct drm_display_mode *mode)
7516 {
7517 struct drm_device *dev = crtc->dev;
7518 struct drm_encoder_helper_funcs *encoder_funcs;
7519 struct intel_encoder *encoder;
7520 struct intel_crtc_config *pipe_config;
7521 int plane_bpp;
7522
7523 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7524 if (!pipe_config)
7525 return ERR_PTR(-ENOMEM);
7526
7527 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7528 drm_mode_copy(&pipe_config->requested_mode, mode);
7529
7530 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7531 if (plane_bpp < 0)
7532 goto fail;
7533
7534 /* Pass our mode to the connectors and the CRTC to give them a chance to
7535 * adjust it according to limitations or connector properties, and also
7536 * a chance to reject the mode entirely.
7537 */
7538 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7539 base.head) {
7540
7541 if (&encoder->new_crtc->base != crtc)
7542 continue;
7543
7544 if (encoder->compute_config) {
7545 if (!(encoder->compute_config(encoder, pipe_config))) {
7546 DRM_DEBUG_KMS("Encoder config failure\n");
7547 goto fail;
7548 }
7549
7550 continue;
7551 }
7552
7553 encoder_funcs = encoder->base.helper_private;
7554 if (!(encoder_funcs->mode_fixup(&encoder->base,
7555 &pipe_config->requested_mode,
7556 &pipe_config->adjusted_mode))) {
7557 DRM_DEBUG_KMS("Encoder fixup failed\n");
7558 goto fail;
7559 }
7560 }
7561
7562 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7563 DRM_DEBUG_KMS("CRTC fixup failed\n");
7564 goto fail;
7565 }
7566 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7567
7568 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7569 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7570 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7571
7572 return pipe_config;
7573 fail:
7574 kfree(pipe_config);
7575 return ERR_PTR(-EINVAL);
7576 }
7577
7578 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7579 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7580 static void
7581 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7582 unsigned *prepare_pipes, unsigned *disable_pipes)
7583 {
7584 struct intel_crtc *intel_crtc;
7585 struct drm_device *dev = crtc->dev;
7586 struct intel_encoder *encoder;
7587 struct intel_connector *connector;
7588 struct drm_crtc *tmp_crtc;
7589
7590 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7591
7592 /* Check which crtcs have changed outputs connected to them, these need
7593 * to be part of the prepare_pipes mask. We don't (yet) support global
7594 * modeset across multiple crtcs, so modeset_pipes will only have one
7595 * bit set at most. */
7596 list_for_each_entry(connector, &dev->mode_config.connector_list,
7597 base.head) {
7598 if (connector->base.encoder == &connector->new_encoder->base)
7599 continue;
7600
7601 if (connector->base.encoder) {
7602 tmp_crtc = connector->base.encoder->crtc;
7603
7604 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7605 }
7606
7607 if (connector->new_encoder)
7608 *prepare_pipes |=
7609 1 << connector->new_encoder->new_crtc->pipe;
7610 }
7611
7612 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7613 base.head) {
7614 if (encoder->base.crtc == &encoder->new_crtc->base)
7615 continue;
7616
7617 if (encoder->base.crtc) {
7618 tmp_crtc = encoder->base.crtc;
7619
7620 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7621 }
7622
7623 if (encoder->new_crtc)
7624 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7625 }
7626
7627 /* Check for any pipes that will be fully disabled ... */
7628 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7629 base.head) {
7630 bool used = false;
7631
7632 /* Don't try to disable disabled crtcs. */
7633 if (!intel_crtc->base.enabled)
7634 continue;
7635
7636 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7637 base.head) {
7638 if (encoder->new_crtc == intel_crtc)
7639 used = true;
7640 }
7641
7642 if (!used)
7643 *disable_pipes |= 1 << intel_crtc->pipe;
7644 }
7645
7646
7647 /* set_mode is also used to update properties on life display pipes. */
7648 intel_crtc = to_intel_crtc(crtc);
7649 if (crtc->enabled)
7650 *prepare_pipes |= 1 << intel_crtc->pipe;
7651
7652 /* We only support modeset on one single crtc, hence we need to do that
7653 * only for the passed in crtc iff we change anything else than just
7654 * disable crtcs.
7655 *
7656 * This is actually not true, to be fully compatible with the old crtc
7657 * helper we automatically disable _any_ output (i.e. doesn't need to be
7658 * connected to the crtc we're modesetting on) if it's disconnected.
7659 * Which is a rather nutty api (since changed the output configuration
7660 * without userspace's explicit request can lead to confusion), but
7661 * alas. Hence we currently need to modeset on all pipes we prepare. */
7662 if (*prepare_pipes)
7663 *modeset_pipes = *prepare_pipes;
7664
7665 /* ... and mask these out. */
7666 *modeset_pipes &= ~(*disable_pipes);
7667 *prepare_pipes &= ~(*disable_pipes);
7668 }
7669
7670 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7671 {
7672 struct drm_encoder *encoder;
7673 struct drm_device *dev = crtc->dev;
7674
7675 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7676 if (encoder->crtc == crtc)
7677 return true;
7678
7679 return false;
7680 }
7681
7682 static void
7683 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7684 {
7685 struct intel_encoder *intel_encoder;
7686 struct intel_crtc *intel_crtc;
7687 struct drm_connector *connector;
7688
7689 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7690 base.head) {
7691 if (!intel_encoder->base.crtc)
7692 continue;
7693
7694 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7695
7696 if (prepare_pipes & (1 << intel_crtc->pipe))
7697 intel_encoder->connectors_active = false;
7698 }
7699
7700 intel_modeset_commit_output_state(dev);
7701
7702 /* Update computed state. */
7703 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7704 base.head) {
7705 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7706 }
7707
7708 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7709 if (!connector->encoder || !connector->encoder->crtc)
7710 continue;
7711
7712 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7713
7714 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7715 struct drm_property *dpms_property =
7716 dev->mode_config.dpms_property;
7717
7718 connector->dpms = DRM_MODE_DPMS_ON;
7719 drm_object_property_set_value(&connector->base,
7720 dpms_property,
7721 DRM_MODE_DPMS_ON);
7722
7723 intel_encoder = to_intel_encoder(connector->encoder);
7724 intel_encoder->connectors_active = true;
7725 }
7726 }
7727
7728 }
7729
7730 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7731 list_for_each_entry((intel_crtc), \
7732 &(dev)->mode_config.crtc_list, \
7733 base.head) \
7734 if (mask & (1 <<(intel_crtc)->pipe)) \
7735
7736 void
7737 intel_modeset_check_state(struct drm_device *dev)
7738 {
7739 struct intel_crtc *crtc;
7740 struct intel_encoder *encoder;
7741 struct intel_connector *connector;
7742
7743 list_for_each_entry(connector, &dev->mode_config.connector_list,
7744 base.head) {
7745 /* This also checks the encoder/connector hw state with the
7746 * ->get_hw_state callbacks. */
7747 intel_connector_check_state(connector);
7748
7749 WARN(&connector->new_encoder->base != connector->base.encoder,
7750 "connector's staged encoder doesn't match current encoder\n");
7751 }
7752
7753 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7754 base.head) {
7755 bool enabled = false;
7756 bool active = false;
7757 enum pipe pipe, tracked_pipe;
7758
7759 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7760 encoder->base.base.id,
7761 drm_get_encoder_name(&encoder->base));
7762
7763 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7764 "encoder's stage crtc doesn't match current crtc\n");
7765 WARN(encoder->connectors_active && !encoder->base.crtc,
7766 "encoder's active_connectors set, but no crtc\n");
7767
7768 list_for_each_entry(connector, &dev->mode_config.connector_list,
7769 base.head) {
7770 if (connector->base.encoder != &encoder->base)
7771 continue;
7772 enabled = true;
7773 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7774 active = true;
7775 }
7776 WARN(!!encoder->base.crtc != enabled,
7777 "encoder's enabled state mismatch "
7778 "(expected %i, found %i)\n",
7779 !!encoder->base.crtc, enabled);
7780 WARN(active && !encoder->base.crtc,
7781 "active encoder with no crtc\n");
7782
7783 WARN(encoder->connectors_active != active,
7784 "encoder's computed active state doesn't match tracked active state "
7785 "(expected %i, found %i)\n", active, encoder->connectors_active);
7786
7787 active = encoder->get_hw_state(encoder, &pipe);
7788 WARN(active != encoder->connectors_active,
7789 "encoder's hw state doesn't match sw tracking "
7790 "(expected %i, found %i)\n",
7791 encoder->connectors_active, active);
7792
7793 if (!encoder->base.crtc)
7794 continue;
7795
7796 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7797 WARN(active && pipe != tracked_pipe,
7798 "active encoder's pipe doesn't match"
7799 "(expected %i, found %i)\n",
7800 tracked_pipe, pipe);
7801
7802 }
7803
7804 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7805 base.head) {
7806 bool enabled = false;
7807 bool active = false;
7808
7809 DRM_DEBUG_KMS("[CRTC:%d]\n",
7810 crtc->base.base.id);
7811
7812 WARN(crtc->active && !crtc->base.enabled,
7813 "active crtc, but not enabled in sw tracking\n");
7814
7815 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7816 base.head) {
7817 if (encoder->base.crtc != &crtc->base)
7818 continue;
7819 enabled = true;
7820 if (encoder->connectors_active)
7821 active = true;
7822 }
7823 WARN(active != crtc->active,
7824 "crtc's computed active state doesn't match tracked active state "
7825 "(expected %i, found %i)\n", active, crtc->active);
7826 WARN(enabled != crtc->base.enabled,
7827 "crtc's computed enabled state doesn't match tracked enabled state "
7828 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7829
7830 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7831 }
7832 }
7833
7834 int intel_set_mode(struct drm_crtc *crtc,
7835 struct drm_display_mode *mode,
7836 int x, int y, struct drm_framebuffer *fb)
7837 {
7838 struct drm_device *dev = crtc->dev;
7839 drm_i915_private_t *dev_priv = dev->dev_private;
7840 struct drm_display_mode *saved_mode, *saved_hwmode;
7841 struct intel_crtc_config *pipe_config = NULL;
7842 struct intel_crtc *intel_crtc;
7843 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7844 int ret = 0;
7845
7846 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7847 if (!saved_mode)
7848 return -ENOMEM;
7849 saved_hwmode = saved_mode + 1;
7850
7851 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7852 &prepare_pipes, &disable_pipes);
7853
7854 *saved_hwmode = crtc->hwmode;
7855 *saved_mode = crtc->mode;
7856
7857 /* Hack: Because we don't (yet) support global modeset on multiple
7858 * crtcs, we don't keep track of the new mode for more than one crtc.
7859 * Hence simply check whether any bit is set in modeset_pipes in all the
7860 * pieces of code that are not yet converted to deal with mutliple crtcs
7861 * changing their mode at the same time. */
7862 if (modeset_pipes) {
7863 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7864 if (IS_ERR(pipe_config)) {
7865 ret = PTR_ERR(pipe_config);
7866 pipe_config = NULL;
7867
7868 goto out;
7869 }
7870 }
7871
7872 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7873 modeset_pipes, prepare_pipes, disable_pipes);
7874
7875 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7876 intel_crtc_disable(&intel_crtc->base);
7877
7878 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7879 if (intel_crtc->base.enabled)
7880 dev_priv->display.crtc_disable(&intel_crtc->base);
7881 }
7882
7883 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7884 * to set it here already despite that we pass it down the callchain.
7885 */
7886 if (modeset_pipes) {
7887 crtc->mode = *mode;
7888 /* mode_set/enable/disable functions rely on a correct pipe
7889 * config. */
7890 to_intel_crtc(crtc)->config = *pipe_config;
7891 }
7892
7893 /* Only after disabling all output pipelines that will be changed can we
7894 * update the the output configuration. */
7895 intel_modeset_update_state(dev, prepare_pipes);
7896
7897 if (dev_priv->display.modeset_global_resources)
7898 dev_priv->display.modeset_global_resources(dev);
7899
7900 /* Set up the DPLL and any encoders state that needs to adjust or depend
7901 * on the DPLL.
7902 */
7903 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7904 ret = intel_crtc_mode_set(&intel_crtc->base,
7905 x, y, fb);
7906 if (ret)
7907 goto done;
7908 }
7909
7910 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7911 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7912 dev_priv->display.crtc_enable(&intel_crtc->base);
7913
7914 if (modeset_pipes) {
7915 /* Store real post-adjustment hardware mode. */
7916 crtc->hwmode = pipe_config->adjusted_mode;
7917
7918 /* Calculate and store various constants which
7919 * are later needed by vblank and swap-completion
7920 * timestamping. They are derived from true hwmode.
7921 */
7922 drm_calc_timestamping_constants(crtc);
7923 }
7924
7925 /* FIXME: add subpixel order */
7926 done:
7927 if (ret && crtc->enabled) {
7928 crtc->hwmode = *saved_hwmode;
7929 crtc->mode = *saved_mode;
7930 } else {
7931 intel_modeset_check_state(dev);
7932 }
7933
7934 out:
7935 kfree(pipe_config);
7936 kfree(saved_mode);
7937 return ret;
7938 }
7939
7940 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7941 {
7942 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7943 }
7944
7945 #undef for_each_intel_crtc_masked
7946
7947 static void intel_set_config_free(struct intel_set_config *config)
7948 {
7949 if (!config)
7950 return;
7951
7952 kfree(config->save_connector_encoders);
7953 kfree(config->save_encoder_crtcs);
7954 kfree(config);
7955 }
7956
7957 static int intel_set_config_save_state(struct drm_device *dev,
7958 struct intel_set_config *config)
7959 {
7960 struct drm_encoder *encoder;
7961 struct drm_connector *connector;
7962 int count;
7963
7964 config->save_encoder_crtcs =
7965 kcalloc(dev->mode_config.num_encoder,
7966 sizeof(struct drm_crtc *), GFP_KERNEL);
7967 if (!config->save_encoder_crtcs)
7968 return -ENOMEM;
7969
7970 config->save_connector_encoders =
7971 kcalloc(dev->mode_config.num_connector,
7972 sizeof(struct drm_encoder *), GFP_KERNEL);
7973 if (!config->save_connector_encoders)
7974 return -ENOMEM;
7975
7976 /* Copy data. Note that driver private data is not affected.
7977 * Should anything bad happen only the expected state is
7978 * restored, not the drivers personal bookkeeping.
7979 */
7980 count = 0;
7981 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7982 config->save_encoder_crtcs[count++] = encoder->crtc;
7983 }
7984
7985 count = 0;
7986 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7987 config->save_connector_encoders[count++] = connector->encoder;
7988 }
7989
7990 return 0;
7991 }
7992
7993 static void intel_set_config_restore_state(struct drm_device *dev,
7994 struct intel_set_config *config)
7995 {
7996 struct intel_encoder *encoder;
7997 struct intel_connector *connector;
7998 int count;
7999
8000 count = 0;
8001 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8002 encoder->new_crtc =
8003 to_intel_crtc(config->save_encoder_crtcs[count++]);
8004 }
8005
8006 count = 0;
8007 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8008 connector->new_encoder =
8009 to_intel_encoder(config->save_connector_encoders[count++]);
8010 }
8011 }
8012
8013 static void
8014 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8015 struct intel_set_config *config)
8016 {
8017
8018 /* We should be able to check here if the fb has the same properties
8019 * and then just flip_or_move it */
8020 if (set->crtc->fb != set->fb) {
8021 /* If we have no fb then treat it as a full mode set */
8022 if (set->crtc->fb == NULL) {
8023 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8024 config->mode_changed = true;
8025 } else if (set->fb == NULL) {
8026 config->mode_changed = true;
8027 } else if (set->fb->pixel_format !=
8028 set->crtc->fb->pixel_format) {
8029 config->mode_changed = true;
8030 } else
8031 config->fb_changed = true;
8032 }
8033
8034 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8035 config->fb_changed = true;
8036
8037 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8038 DRM_DEBUG_KMS("modes are different, full mode set\n");
8039 drm_mode_debug_printmodeline(&set->crtc->mode);
8040 drm_mode_debug_printmodeline(set->mode);
8041 config->mode_changed = true;
8042 }
8043 }
8044
8045 static int
8046 intel_modeset_stage_output_state(struct drm_device *dev,
8047 struct drm_mode_set *set,
8048 struct intel_set_config *config)
8049 {
8050 struct drm_crtc *new_crtc;
8051 struct intel_connector *connector;
8052 struct intel_encoder *encoder;
8053 int count, ro;
8054
8055 /* The upper layers ensure that we either disable a crtc or have a list
8056 * of connectors. For paranoia, double-check this. */
8057 WARN_ON(!set->fb && (set->num_connectors != 0));
8058 WARN_ON(set->fb && (set->num_connectors == 0));
8059
8060 count = 0;
8061 list_for_each_entry(connector, &dev->mode_config.connector_list,
8062 base.head) {
8063 /* Otherwise traverse passed in connector list and get encoders
8064 * for them. */
8065 for (ro = 0; ro < set->num_connectors; ro++) {
8066 if (set->connectors[ro] == &connector->base) {
8067 connector->new_encoder = connector->encoder;
8068 break;
8069 }
8070 }
8071
8072 /* If we disable the crtc, disable all its connectors. Also, if
8073 * the connector is on the changing crtc but not on the new
8074 * connector list, disable it. */
8075 if ((!set->fb || ro == set->num_connectors) &&
8076 connector->base.encoder &&
8077 connector->base.encoder->crtc == set->crtc) {
8078 connector->new_encoder = NULL;
8079
8080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8081 connector->base.base.id,
8082 drm_get_connector_name(&connector->base));
8083 }
8084
8085
8086 if (&connector->new_encoder->base != connector->base.encoder) {
8087 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8088 config->mode_changed = true;
8089 }
8090 }
8091 /* connector->new_encoder is now updated for all connectors. */
8092
8093 /* Update crtc of enabled connectors. */
8094 count = 0;
8095 list_for_each_entry(connector, &dev->mode_config.connector_list,
8096 base.head) {
8097 if (!connector->new_encoder)
8098 continue;
8099
8100 new_crtc = connector->new_encoder->base.crtc;
8101
8102 for (ro = 0; ro < set->num_connectors; ro++) {
8103 if (set->connectors[ro] == &connector->base)
8104 new_crtc = set->crtc;
8105 }
8106
8107 /* Make sure the new CRTC will work with the encoder */
8108 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8109 new_crtc)) {
8110 return -EINVAL;
8111 }
8112 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8113
8114 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8115 connector->base.base.id,
8116 drm_get_connector_name(&connector->base),
8117 new_crtc->base.id);
8118 }
8119
8120 /* Check for any encoders that needs to be disabled. */
8121 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8122 base.head) {
8123 list_for_each_entry(connector,
8124 &dev->mode_config.connector_list,
8125 base.head) {
8126 if (connector->new_encoder == encoder) {
8127 WARN_ON(!connector->new_encoder->new_crtc);
8128
8129 goto next_encoder;
8130 }
8131 }
8132 encoder->new_crtc = NULL;
8133 next_encoder:
8134 /* Only now check for crtc changes so we don't miss encoders
8135 * that will be disabled. */
8136 if (&encoder->new_crtc->base != encoder->base.crtc) {
8137 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8138 config->mode_changed = true;
8139 }
8140 }
8141 /* Now we've also updated encoder->new_crtc for all encoders. */
8142
8143 return 0;
8144 }
8145
8146 static int intel_crtc_set_config(struct drm_mode_set *set)
8147 {
8148 struct drm_device *dev;
8149 struct drm_mode_set save_set;
8150 struct intel_set_config *config;
8151 int ret;
8152
8153 BUG_ON(!set);
8154 BUG_ON(!set->crtc);
8155 BUG_ON(!set->crtc->helper_private);
8156
8157 /* Enforce sane interface api - has been abused by the fb helper. */
8158 BUG_ON(!set->mode && set->fb);
8159 BUG_ON(set->fb && set->num_connectors == 0);
8160
8161 if (set->fb) {
8162 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8163 set->crtc->base.id, set->fb->base.id,
8164 (int)set->num_connectors, set->x, set->y);
8165 } else {
8166 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8167 }
8168
8169 dev = set->crtc->dev;
8170
8171 ret = -ENOMEM;
8172 config = kzalloc(sizeof(*config), GFP_KERNEL);
8173 if (!config)
8174 goto out_config;
8175
8176 ret = intel_set_config_save_state(dev, config);
8177 if (ret)
8178 goto out_config;
8179
8180 save_set.crtc = set->crtc;
8181 save_set.mode = &set->crtc->mode;
8182 save_set.x = set->crtc->x;
8183 save_set.y = set->crtc->y;
8184 save_set.fb = set->crtc->fb;
8185
8186 /* Compute whether we need a full modeset, only an fb base update or no
8187 * change at all. In the future we might also check whether only the
8188 * mode changed, e.g. for LVDS where we only change the panel fitter in
8189 * such cases. */
8190 intel_set_config_compute_mode_changes(set, config);
8191
8192 ret = intel_modeset_stage_output_state(dev, set, config);
8193 if (ret)
8194 goto fail;
8195
8196 if (config->mode_changed) {
8197 if (set->mode) {
8198 DRM_DEBUG_KMS("attempting to set mode from"
8199 " userspace\n");
8200 drm_mode_debug_printmodeline(set->mode);
8201 }
8202
8203 ret = intel_set_mode(set->crtc, set->mode,
8204 set->x, set->y, set->fb);
8205 if (ret) {
8206 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8207 set->crtc->base.id, ret);
8208 goto fail;
8209 }
8210 } else if (config->fb_changed) {
8211 intel_crtc_wait_for_pending_flips(set->crtc);
8212
8213 ret = intel_pipe_set_base(set->crtc,
8214 set->x, set->y, set->fb);
8215 }
8216
8217 intel_set_config_free(config);
8218
8219 return 0;
8220
8221 fail:
8222 intel_set_config_restore_state(dev, config);
8223
8224 /* Try to restore the config */
8225 if (config->mode_changed &&
8226 intel_set_mode(save_set.crtc, save_set.mode,
8227 save_set.x, save_set.y, save_set.fb))
8228 DRM_ERROR("failed to restore config after modeset failure\n");
8229
8230 out_config:
8231 intel_set_config_free(config);
8232 return ret;
8233 }
8234
8235 static const struct drm_crtc_funcs intel_crtc_funcs = {
8236 .cursor_set = intel_crtc_cursor_set,
8237 .cursor_move = intel_crtc_cursor_move,
8238 .gamma_set = intel_crtc_gamma_set,
8239 .set_config = intel_crtc_set_config,
8240 .destroy = intel_crtc_destroy,
8241 .page_flip = intel_crtc_page_flip,
8242 };
8243
8244 static void intel_cpu_pll_init(struct drm_device *dev)
8245 {
8246 if (HAS_DDI(dev))
8247 intel_ddi_pll_init(dev);
8248 }
8249
8250 static void intel_pch_pll_init(struct drm_device *dev)
8251 {
8252 drm_i915_private_t *dev_priv = dev->dev_private;
8253 int i;
8254
8255 if (dev_priv->num_pch_pll == 0) {
8256 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8257 return;
8258 }
8259
8260 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8261 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8262 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8263 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8264 }
8265 }
8266
8267 static void intel_crtc_init(struct drm_device *dev, int pipe)
8268 {
8269 drm_i915_private_t *dev_priv = dev->dev_private;
8270 struct intel_crtc *intel_crtc;
8271 int i;
8272
8273 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8274 if (intel_crtc == NULL)
8275 return;
8276
8277 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8278
8279 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8280 for (i = 0; i < 256; i++) {
8281 intel_crtc->lut_r[i] = i;
8282 intel_crtc->lut_g[i] = i;
8283 intel_crtc->lut_b[i] = i;
8284 }
8285
8286 /* Swap pipes & planes for FBC on pre-965 */
8287 intel_crtc->pipe = pipe;
8288 intel_crtc->plane = pipe;
8289 intel_crtc->cpu_transcoder = pipe;
8290 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8291 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8292 intel_crtc->plane = !pipe;
8293 }
8294
8295 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8296 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8297 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8298 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8299
8300 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8301 }
8302
8303 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8304 struct drm_file *file)
8305 {
8306 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8307 struct drm_mode_object *drmmode_obj;
8308 struct intel_crtc *crtc;
8309
8310 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8311 return -ENODEV;
8312
8313 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8314 DRM_MODE_OBJECT_CRTC);
8315
8316 if (!drmmode_obj) {
8317 DRM_ERROR("no such CRTC id\n");
8318 return -EINVAL;
8319 }
8320
8321 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8322 pipe_from_crtc_id->pipe = crtc->pipe;
8323
8324 return 0;
8325 }
8326
8327 static int intel_encoder_clones(struct intel_encoder *encoder)
8328 {
8329 struct drm_device *dev = encoder->base.dev;
8330 struct intel_encoder *source_encoder;
8331 int index_mask = 0;
8332 int entry = 0;
8333
8334 list_for_each_entry(source_encoder,
8335 &dev->mode_config.encoder_list, base.head) {
8336
8337 if (encoder == source_encoder)
8338 index_mask |= (1 << entry);
8339
8340 /* Intel hw has only one MUX where enocoders could be cloned. */
8341 if (encoder->cloneable && source_encoder->cloneable)
8342 index_mask |= (1 << entry);
8343
8344 entry++;
8345 }
8346
8347 return index_mask;
8348 }
8349
8350 static bool has_edp_a(struct drm_device *dev)
8351 {
8352 struct drm_i915_private *dev_priv = dev->dev_private;
8353
8354 if (!IS_MOBILE(dev))
8355 return false;
8356
8357 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8358 return false;
8359
8360 if (IS_GEN5(dev) &&
8361 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8362 return false;
8363
8364 return true;
8365 }
8366
8367 static void intel_setup_outputs(struct drm_device *dev)
8368 {
8369 struct drm_i915_private *dev_priv = dev->dev_private;
8370 struct intel_encoder *encoder;
8371 bool dpd_is_edp = false;
8372 bool has_lvds;
8373
8374 has_lvds = intel_lvds_init(dev);
8375 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8376 /* disable the panel fitter on everything but LVDS */
8377 I915_WRITE(PFIT_CONTROL, 0);
8378 }
8379
8380 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8381 intel_crt_init(dev);
8382
8383 if (HAS_DDI(dev)) {
8384 int found;
8385
8386 /* Haswell uses DDI functions to detect digital outputs */
8387 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8388 /* DDI A only supports eDP */
8389 if (found)
8390 intel_ddi_init(dev, PORT_A);
8391
8392 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8393 * register */
8394 found = I915_READ(SFUSE_STRAP);
8395
8396 if (found & SFUSE_STRAP_DDIB_DETECTED)
8397 intel_ddi_init(dev, PORT_B);
8398 if (found & SFUSE_STRAP_DDIC_DETECTED)
8399 intel_ddi_init(dev, PORT_C);
8400 if (found & SFUSE_STRAP_DDID_DETECTED)
8401 intel_ddi_init(dev, PORT_D);
8402 } else if (HAS_PCH_SPLIT(dev)) {
8403 int found;
8404 dpd_is_edp = intel_dpd_is_edp(dev);
8405
8406 if (has_edp_a(dev))
8407 intel_dp_init(dev, DP_A, PORT_A);
8408
8409 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8410 /* PCH SDVOB multiplex with HDMIB */
8411 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8412 if (!found)
8413 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8414 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8415 intel_dp_init(dev, PCH_DP_B, PORT_B);
8416 }
8417
8418 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8419 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8420
8421 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8422 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8423
8424 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8425 intel_dp_init(dev, PCH_DP_C, PORT_C);
8426
8427 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8428 intel_dp_init(dev, PCH_DP_D, PORT_D);
8429 } else if (IS_VALLEYVIEW(dev)) {
8430 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8431 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8432 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8433
8434 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8435 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8436 PORT_B);
8437 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8438 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8439 }
8440 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8441 bool found = false;
8442
8443 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8444 DRM_DEBUG_KMS("probing SDVOB\n");
8445 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8446 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8447 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8448 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8449 }
8450
8451 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8452 DRM_DEBUG_KMS("probing DP_B\n");
8453 intel_dp_init(dev, DP_B, PORT_B);
8454 }
8455 }
8456
8457 /* Before G4X SDVOC doesn't have its own detect register */
8458
8459 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8460 DRM_DEBUG_KMS("probing SDVOC\n");
8461 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8462 }
8463
8464 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8465
8466 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8467 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8468 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8469 }
8470 if (SUPPORTS_INTEGRATED_DP(dev)) {
8471 DRM_DEBUG_KMS("probing DP_C\n");
8472 intel_dp_init(dev, DP_C, PORT_C);
8473 }
8474 }
8475
8476 if (SUPPORTS_INTEGRATED_DP(dev) &&
8477 (I915_READ(DP_D) & DP_DETECTED)) {
8478 DRM_DEBUG_KMS("probing DP_D\n");
8479 intel_dp_init(dev, DP_D, PORT_D);
8480 }
8481 } else if (IS_GEN2(dev))
8482 intel_dvo_init(dev);
8483
8484 if (SUPPORTS_TV(dev))
8485 intel_tv_init(dev);
8486
8487 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8488 encoder->base.possible_crtcs = encoder->crtc_mask;
8489 encoder->base.possible_clones =
8490 intel_encoder_clones(encoder);
8491 }
8492
8493 intel_init_pch_refclk(dev);
8494
8495 drm_helper_move_panel_connectors_to_head(dev);
8496 }
8497
8498 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8499 {
8500 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8501
8502 drm_framebuffer_cleanup(fb);
8503 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8504
8505 kfree(intel_fb);
8506 }
8507
8508 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8509 struct drm_file *file,
8510 unsigned int *handle)
8511 {
8512 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8513 struct drm_i915_gem_object *obj = intel_fb->obj;
8514
8515 return drm_gem_handle_create(file, &obj->base, handle);
8516 }
8517
8518 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8519 .destroy = intel_user_framebuffer_destroy,
8520 .create_handle = intel_user_framebuffer_create_handle,
8521 };
8522
8523 int intel_framebuffer_init(struct drm_device *dev,
8524 struct intel_framebuffer *intel_fb,
8525 struct drm_mode_fb_cmd2 *mode_cmd,
8526 struct drm_i915_gem_object *obj)
8527 {
8528 int ret;
8529
8530 if (obj->tiling_mode == I915_TILING_Y) {
8531 DRM_DEBUG("hardware does not support tiling Y\n");
8532 return -EINVAL;
8533 }
8534
8535 if (mode_cmd->pitches[0] & 63) {
8536 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8537 mode_cmd->pitches[0]);
8538 return -EINVAL;
8539 }
8540
8541 /* FIXME <= Gen4 stride limits are bit unclear */
8542 if (mode_cmd->pitches[0] > 32768) {
8543 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8544 mode_cmd->pitches[0]);
8545 return -EINVAL;
8546 }
8547
8548 if (obj->tiling_mode != I915_TILING_NONE &&
8549 mode_cmd->pitches[0] != obj->stride) {
8550 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8551 mode_cmd->pitches[0], obj->stride);
8552 return -EINVAL;
8553 }
8554
8555 /* Reject formats not supported by any plane early. */
8556 switch (mode_cmd->pixel_format) {
8557 case DRM_FORMAT_C8:
8558 case DRM_FORMAT_RGB565:
8559 case DRM_FORMAT_XRGB8888:
8560 case DRM_FORMAT_ARGB8888:
8561 break;
8562 case DRM_FORMAT_XRGB1555:
8563 case DRM_FORMAT_ARGB1555:
8564 if (INTEL_INFO(dev)->gen > 3) {
8565 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8566 return -EINVAL;
8567 }
8568 break;
8569 case DRM_FORMAT_XBGR8888:
8570 case DRM_FORMAT_ABGR8888:
8571 case DRM_FORMAT_XRGB2101010:
8572 case DRM_FORMAT_ARGB2101010:
8573 case DRM_FORMAT_XBGR2101010:
8574 case DRM_FORMAT_ABGR2101010:
8575 if (INTEL_INFO(dev)->gen < 4) {
8576 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8577 return -EINVAL;
8578 }
8579 break;
8580 case DRM_FORMAT_YUYV:
8581 case DRM_FORMAT_UYVY:
8582 case DRM_FORMAT_YVYU:
8583 case DRM_FORMAT_VYUY:
8584 if (INTEL_INFO(dev)->gen < 5) {
8585 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8586 return -EINVAL;
8587 }
8588 break;
8589 default:
8590 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8591 return -EINVAL;
8592 }
8593
8594 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8595 if (mode_cmd->offsets[0] != 0)
8596 return -EINVAL;
8597
8598 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8599 intel_fb->obj = obj;
8600
8601 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8602 if (ret) {
8603 DRM_ERROR("framebuffer init failed %d\n", ret);
8604 return ret;
8605 }
8606
8607 return 0;
8608 }
8609
8610 static struct drm_framebuffer *
8611 intel_user_framebuffer_create(struct drm_device *dev,
8612 struct drm_file *filp,
8613 struct drm_mode_fb_cmd2 *mode_cmd)
8614 {
8615 struct drm_i915_gem_object *obj;
8616
8617 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8618 mode_cmd->handles[0]));
8619 if (&obj->base == NULL)
8620 return ERR_PTR(-ENOENT);
8621
8622 return intel_framebuffer_create(dev, mode_cmd, obj);
8623 }
8624
8625 static const struct drm_mode_config_funcs intel_mode_funcs = {
8626 .fb_create = intel_user_framebuffer_create,
8627 .output_poll_changed = intel_fb_output_poll_changed,
8628 };
8629
8630 /* Set up chip specific display functions */
8631 static void intel_init_display(struct drm_device *dev)
8632 {
8633 struct drm_i915_private *dev_priv = dev->dev_private;
8634
8635 if (HAS_DDI(dev)) {
8636 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8637 dev_priv->display.crtc_enable = haswell_crtc_enable;
8638 dev_priv->display.crtc_disable = haswell_crtc_disable;
8639 dev_priv->display.off = haswell_crtc_off;
8640 dev_priv->display.update_plane = ironlake_update_plane;
8641 } else if (HAS_PCH_SPLIT(dev)) {
8642 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8643 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8644 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8645 dev_priv->display.off = ironlake_crtc_off;
8646 dev_priv->display.update_plane = ironlake_update_plane;
8647 } else {
8648 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8649 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8650 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8651 dev_priv->display.off = i9xx_crtc_off;
8652 dev_priv->display.update_plane = i9xx_update_plane;
8653 }
8654
8655 /* Returns the core display clock speed */
8656 if (IS_VALLEYVIEW(dev))
8657 dev_priv->display.get_display_clock_speed =
8658 valleyview_get_display_clock_speed;
8659 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8660 dev_priv->display.get_display_clock_speed =
8661 i945_get_display_clock_speed;
8662 else if (IS_I915G(dev))
8663 dev_priv->display.get_display_clock_speed =
8664 i915_get_display_clock_speed;
8665 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8666 dev_priv->display.get_display_clock_speed =
8667 i9xx_misc_get_display_clock_speed;
8668 else if (IS_I915GM(dev))
8669 dev_priv->display.get_display_clock_speed =
8670 i915gm_get_display_clock_speed;
8671 else if (IS_I865G(dev))
8672 dev_priv->display.get_display_clock_speed =
8673 i865_get_display_clock_speed;
8674 else if (IS_I85X(dev))
8675 dev_priv->display.get_display_clock_speed =
8676 i855_get_display_clock_speed;
8677 else /* 852, 830 */
8678 dev_priv->display.get_display_clock_speed =
8679 i830_get_display_clock_speed;
8680
8681 if (HAS_PCH_SPLIT(dev)) {
8682 if (IS_GEN5(dev)) {
8683 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8684 dev_priv->display.write_eld = ironlake_write_eld;
8685 } else if (IS_GEN6(dev)) {
8686 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8687 dev_priv->display.write_eld = ironlake_write_eld;
8688 } else if (IS_IVYBRIDGE(dev)) {
8689 /* FIXME: detect B0+ stepping and use auto training */
8690 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8691 dev_priv->display.write_eld = ironlake_write_eld;
8692 dev_priv->display.modeset_global_resources =
8693 ivb_modeset_global_resources;
8694 } else if (IS_HASWELL(dev)) {
8695 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8696 dev_priv->display.write_eld = haswell_write_eld;
8697 dev_priv->display.modeset_global_resources =
8698 haswell_modeset_global_resources;
8699 }
8700 } else if (IS_G4X(dev)) {
8701 dev_priv->display.write_eld = g4x_write_eld;
8702 }
8703
8704 /* Default just returns -ENODEV to indicate unsupported */
8705 dev_priv->display.queue_flip = intel_default_queue_flip;
8706
8707 switch (INTEL_INFO(dev)->gen) {
8708 case 2:
8709 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8710 break;
8711
8712 case 3:
8713 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8714 break;
8715
8716 case 4:
8717 case 5:
8718 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8719 break;
8720
8721 case 6:
8722 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8723 break;
8724 case 7:
8725 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8726 break;
8727 }
8728 }
8729
8730 /*
8731 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8732 * resume, or other times. This quirk makes sure that's the case for
8733 * affected systems.
8734 */
8735 static void quirk_pipea_force(struct drm_device *dev)
8736 {
8737 struct drm_i915_private *dev_priv = dev->dev_private;
8738
8739 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8740 DRM_INFO("applying pipe a force quirk\n");
8741 }
8742
8743 /*
8744 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8745 */
8746 static void quirk_ssc_force_disable(struct drm_device *dev)
8747 {
8748 struct drm_i915_private *dev_priv = dev->dev_private;
8749 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8750 DRM_INFO("applying lvds SSC disable quirk\n");
8751 }
8752
8753 /*
8754 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8755 * brightness value
8756 */
8757 static void quirk_invert_brightness(struct drm_device *dev)
8758 {
8759 struct drm_i915_private *dev_priv = dev->dev_private;
8760 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8761 DRM_INFO("applying inverted panel brightness quirk\n");
8762 }
8763
8764 struct intel_quirk {
8765 int device;
8766 int subsystem_vendor;
8767 int subsystem_device;
8768 void (*hook)(struct drm_device *dev);
8769 };
8770
8771 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8772 struct intel_dmi_quirk {
8773 void (*hook)(struct drm_device *dev);
8774 const struct dmi_system_id (*dmi_id_list)[];
8775 };
8776
8777 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8778 {
8779 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8780 return 1;
8781 }
8782
8783 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8784 {
8785 .dmi_id_list = &(const struct dmi_system_id[]) {
8786 {
8787 .callback = intel_dmi_reverse_brightness,
8788 .ident = "NCR Corporation",
8789 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8790 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8791 },
8792 },
8793 { } /* terminating entry */
8794 },
8795 .hook = quirk_invert_brightness,
8796 },
8797 };
8798
8799 static struct intel_quirk intel_quirks[] = {
8800 /* HP Mini needs pipe A force quirk (LP: #322104) */
8801 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8802
8803 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8804 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8805
8806 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8807 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8808
8809 /* 830/845 need to leave pipe A & dpll A up */
8810 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8811 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8812
8813 /* Lenovo U160 cannot use SSC on LVDS */
8814 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8815
8816 /* Sony Vaio Y cannot use SSC on LVDS */
8817 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8818
8819 /* Acer Aspire 5734Z must invert backlight brightness */
8820 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8821
8822 /* Acer/eMachines G725 */
8823 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8824
8825 /* Acer/eMachines e725 */
8826 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8827
8828 /* Acer/Packard Bell NCL20 */
8829 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8830
8831 /* Acer Aspire 4736Z */
8832 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8833 };
8834
8835 static void intel_init_quirks(struct drm_device *dev)
8836 {
8837 struct pci_dev *d = dev->pdev;
8838 int i;
8839
8840 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8841 struct intel_quirk *q = &intel_quirks[i];
8842
8843 if (d->device == q->device &&
8844 (d->subsystem_vendor == q->subsystem_vendor ||
8845 q->subsystem_vendor == PCI_ANY_ID) &&
8846 (d->subsystem_device == q->subsystem_device ||
8847 q->subsystem_device == PCI_ANY_ID))
8848 q->hook(dev);
8849 }
8850 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8851 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8852 intel_dmi_quirks[i].hook(dev);
8853 }
8854 }
8855
8856 /* Disable the VGA plane that we never use */
8857 static void i915_disable_vga(struct drm_device *dev)
8858 {
8859 struct drm_i915_private *dev_priv = dev->dev_private;
8860 u8 sr1;
8861 u32 vga_reg = i915_vgacntrl_reg(dev);
8862
8863 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8864 outb(SR01, VGA_SR_INDEX);
8865 sr1 = inb(VGA_SR_DATA);
8866 outb(sr1 | 1<<5, VGA_SR_DATA);
8867 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8868 udelay(300);
8869
8870 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8871 POSTING_READ(vga_reg);
8872 }
8873
8874 void intel_modeset_init_hw(struct drm_device *dev)
8875 {
8876 intel_init_power_well(dev);
8877
8878 intel_prepare_ddi(dev);
8879
8880 intel_init_clock_gating(dev);
8881
8882 mutex_lock(&dev->struct_mutex);
8883 intel_enable_gt_powersave(dev);
8884 mutex_unlock(&dev->struct_mutex);
8885 }
8886
8887 void intel_modeset_init(struct drm_device *dev)
8888 {
8889 struct drm_i915_private *dev_priv = dev->dev_private;
8890 int i, j, ret;
8891
8892 drm_mode_config_init(dev);
8893
8894 dev->mode_config.min_width = 0;
8895 dev->mode_config.min_height = 0;
8896
8897 dev->mode_config.preferred_depth = 24;
8898 dev->mode_config.prefer_shadow = 1;
8899
8900 dev->mode_config.funcs = &intel_mode_funcs;
8901
8902 intel_init_quirks(dev);
8903
8904 intel_init_pm(dev);
8905
8906 intel_init_display(dev);
8907
8908 if (IS_GEN2(dev)) {
8909 dev->mode_config.max_width = 2048;
8910 dev->mode_config.max_height = 2048;
8911 } else if (IS_GEN3(dev)) {
8912 dev->mode_config.max_width = 4096;
8913 dev->mode_config.max_height = 4096;
8914 } else {
8915 dev->mode_config.max_width = 8192;
8916 dev->mode_config.max_height = 8192;
8917 }
8918 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8919
8920 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8921 INTEL_INFO(dev)->num_pipes,
8922 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
8923
8924 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
8925 intel_crtc_init(dev, i);
8926 for (j = 0; j < dev_priv->num_plane; j++) {
8927 ret = intel_plane_init(dev, i, j);
8928 if (ret)
8929 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
8930 i, j, ret);
8931 }
8932 }
8933
8934 intel_cpu_pll_init(dev);
8935 intel_pch_pll_init(dev);
8936
8937 /* Just disable it once at startup */
8938 i915_disable_vga(dev);
8939 intel_setup_outputs(dev);
8940
8941 /* Just in case the BIOS is doing something questionable. */
8942 intel_disable_fbc(dev);
8943 }
8944
8945 static void
8946 intel_connector_break_all_links(struct intel_connector *connector)
8947 {
8948 connector->base.dpms = DRM_MODE_DPMS_OFF;
8949 connector->base.encoder = NULL;
8950 connector->encoder->connectors_active = false;
8951 connector->encoder->base.crtc = NULL;
8952 }
8953
8954 static void intel_enable_pipe_a(struct drm_device *dev)
8955 {
8956 struct intel_connector *connector;
8957 struct drm_connector *crt = NULL;
8958 struct intel_load_detect_pipe load_detect_temp;
8959
8960 /* We can't just switch on the pipe A, we need to set things up with a
8961 * proper mode and output configuration. As a gross hack, enable pipe A
8962 * by enabling the load detect pipe once. */
8963 list_for_each_entry(connector,
8964 &dev->mode_config.connector_list,
8965 base.head) {
8966 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8967 crt = &connector->base;
8968 break;
8969 }
8970 }
8971
8972 if (!crt)
8973 return;
8974
8975 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8976 intel_release_load_detect_pipe(crt, &load_detect_temp);
8977
8978
8979 }
8980
8981 static bool
8982 intel_check_plane_mapping(struct intel_crtc *crtc)
8983 {
8984 struct drm_device *dev = crtc->base.dev;
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 u32 reg, val;
8987
8988 if (INTEL_INFO(dev)->num_pipes == 1)
8989 return true;
8990
8991 reg = DSPCNTR(!crtc->plane);
8992 val = I915_READ(reg);
8993
8994 if ((val & DISPLAY_PLANE_ENABLE) &&
8995 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8996 return false;
8997
8998 return true;
8999 }
9000
9001 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9002 {
9003 struct drm_device *dev = crtc->base.dev;
9004 struct drm_i915_private *dev_priv = dev->dev_private;
9005 u32 reg;
9006
9007 /* Clear any frame start delays used for debugging left by the BIOS */
9008 reg = PIPECONF(crtc->cpu_transcoder);
9009 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9010
9011 /* We need to sanitize the plane -> pipe mapping first because this will
9012 * disable the crtc (and hence change the state) if it is wrong. Note
9013 * that gen4+ has a fixed plane -> pipe mapping. */
9014 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9015 struct intel_connector *connector;
9016 bool plane;
9017
9018 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9019 crtc->base.base.id);
9020
9021 /* Pipe has the wrong plane attached and the plane is active.
9022 * Temporarily change the plane mapping and disable everything
9023 * ... */
9024 plane = crtc->plane;
9025 crtc->plane = !plane;
9026 dev_priv->display.crtc_disable(&crtc->base);
9027 crtc->plane = plane;
9028
9029 /* ... and break all links. */
9030 list_for_each_entry(connector, &dev->mode_config.connector_list,
9031 base.head) {
9032 if (connector->encoder->base.crtc != &crtc->base)
9033 continue;
9034
9035 intel_connector_break_all_links(connector);
9036 }
9037
9038 WARN_ON(crtc->active);
9039 crtc->base.enabled = false;
9040 }
9041
9042 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9043 crtc->pipe == PIPE_A && !crtc->active) {
9044 /* BIOS forgot to enable pipe A, this mostly happens after
9045 * resume. Force-enable the pipe to fix this, the update_dpms
9046 * call below we restore the pipe to the right state, but leave
9047 * the required bits on. */
9048 intel_enable_pipe_a(dev);
9049 }
9050
9051 /* Adjust the state of the output pipe according to whether we
9052 * have active connectors/encoders. */
9053 intel_crtc_update_dpms(&crtc->base);
9054
9055 if (crtc->active != crtc->base.enabled) {
9056 struct intel_encoder *encoder;
9057
9058 /* This can happen either due to bugs in the get_hw_state
9059 * functions or because the pipe is force-enabled due to the
9060 * pipe A quirk. */
9061 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9062 crtc->base.base.id,
9063 crtc->base.enabled ? "enabled" : "disabled",
9064 crtc->active ? "enabled" : "disabled");
9065
9066 crtc->base.enabled = crtc->active;
9067
9068 /* Because we only establish the connector -> encoder ->
9069 * crtc links if something is active, this means the
9070 * crtc is now deactivated. Break the links. connector
9071 * -> encoder links are only establish when things are
9072 * actually up, hence no need to break them. */
9073 WARN_ON(crtc->active);
9074
9075 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9076 WARN_ON(encoder->connectors_active);
9077 encoder->base.crtc = NULL;
9078 }
9079 }
9080 }
9081
9082 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9083 {
9084 struct intel_connector *connector;
9085 struct drm_device *dev = encoder->base.dev;
9086
9087 /* We need to check both for a crtc link (meaning that the
9088 * encoder is active and trying to read from a pipe) and the
9089 * pipe itself being active. */
9090 bool has_active_crtc = encoder->base.crtc &&
9091 to_intel_crtc(encoder->base.crtc)->active;
9092
9093 if (encoder->connectors_active && !has_active_crtc) {
9094 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9095 encoder->base.base.id,
9096 drm_get_encoder_name(&encoder->base));
9097
9098 /* Connector is active, but has no active pipe. This is
9099 * fallout from our resume register restoring. Disable
9100 * the encoder manually again. */
9101 if (encoder->base.crtc) {
9102 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9103 encoder->base.base.id,
9104 drm_get_encoder_name(&encoder->base));
9105 encoder->disable(encoder);
9106 }
9107
9108 /* Inconsistent output/port/pipe state happens presumably due to
9109 * a bug in one of the get_hw_state functions. Or someplace else
9110 * in our code, like the register restore mess on resume. Clamp
9111 * things to off as a safer default. */
9112 list_for_each_entry(connector,
9113 &dev->mode_config.connector_list,
9114 base.head) {
9115 if (connector->encoder != encoder)
9116 continue;
9117
9118 intel_connector_break_all_links(connector);
9119 }
9120 }
9121 /* Enabled encoders without active connectors will be fixed in
9122 * the crtc fixup. */
9123 }
9124
9125 void i915_redisable_vga(struct drm_device *dev)
9126 {
9127 struct drm_i915_private *dev_priv = dev->dev_private;
9128 u32 vga_reg = i915_vgacntrl_reg(dev);
9129
9130 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9131 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9132 i915_disable_vga(dev);
9133 }
9134 }
9135
9136 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9137 * and i915 state tracking structures. */
9138 void intel_modeset_setup_hw_state(struct drm_device *dev,
9139 bool force_restore)
9140 {
9141 struct drm_i915_private *dev_priv = dev->dev_private;
9142 enum pipe pipe;
9143 u32 tmp;
9144 struct drm_plane *plane;
9145 struct intel_crtc *crtc;
9146 struct intel_encoder *encoder;
9147 struct intel_connector *connector;
9148
9149 if (HAS_DDI(dev)) {
9150 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9151
9152 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9153 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9154 case TRANS_DDI_EDP_INPUT_A_ON:
9155 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9156 pipe = PIPE_A;
9157 break;
9158 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9159 pipe = PIPE_B;
9160 break;
9161 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9162 pipe = PIPE_C;
9163 break;
9164 default:
9165 /* A bogus value has been programmed, disable
9166 * the transcoder */
9167 WARN(1, "Bogus eDP source %08x\n", tmp);
9168 intel_ddi_disable_transcoder_func(dev_priv,
9169 TRANSCODER_EDP);
9170 goto setup_pipes;
9171 }
9172
9173 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9174 crtc->cpu_transcoder = TRANSCODER_EDP;
9175
9176 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9177 pipe_name(pipe));
9178 }
9179 }
9180
9181 setup_pipes:
9182 for_each_pipe(pipe) {
9183 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9184
9185 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9186 if (tmp & PIPECONF_ENABLE)
9187 crtc->active = true;
9188 else
9189 crtc->active = false;
9190
9191 crtc->base.enabled = crtc->active;
9192
9193 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9194 crtc->base.base.id,
9195 crtc->active ? "enabled" : "disabled");
9196 }
9197
9198 if (HAS_DDI(dev))
9199 intel_ddi_setup_hw_pll_state(dev);
9200
9201 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9202 base.head) {
9203 pipe = 0;
9204
9205 if (encoder->get_hw_state(encoder, &pipe)) {
9206 encoder->base.crtc =
9207 dev_priv->pipe_to_crtc_mapping[pipe];
9208 } else {
9209 encoder->base.crtc = NULL;
9210 }
9211
9212 encoder->connectors_active = false;
9213 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9214 encoder->base.base.id,
9215 drm_get_encoder_name(&encoder->base),
9216 encoder->base.crtc ? "enabled" : "disabled",
9217 pipe);
9218 }
9219
9220 list_for_each_entry(connector, &dev->mode_config.connector_list,
9221 base.head) {
9222 if (connector->get_hw_state(connector)) {
9223 connector->base.dpms = DRM_MODE_DPMS_ON;
9224 connector->encoder->connectors_active = true;
9225 connector->base.encoder = &connector->encoder->base;
9226 } else {
9227 connector->base.dpms = DRM_MODE_DPMS_OFF;
9228 connector->base.encoder = NULL;
9229 }
9230 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9231 connector->base.base.id,
9232 drm_get_connector_name(&connector->base),
9233 connector->base.encoder ? "enabled" : "disabled");
9234 }
9235
9236 /* HW state is read out, now we need to sanitize this mess. */
9237 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9238 base.head) {
9239 intel_sanitize_encoder(encoder);
9240 }
9241
9242 for_each_pipe(pipe) {
9243 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9244 intel_sanitize_crtc(crtc);
9245 }
9246
9247 if (force_restore) {
9248 for_each_pipe(pipe) {
9249 struct drm_crtc *crtc =
9250 dev_priv->pipe_to_crtc_mapping[pipe];
9251 intel_crtc_restore_mode(crtc);
9252 }
9253 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9254 intel_plane_restore(plane);
9255
9256 i915_redisable_vga(dev);
9257 } else {
9258 intel_modeset_update_staged_output_state(dev);
9259 }
9260
9261 intel_modeset_check_state(dev);
9262
9263 drm_mode_config_reset(dev);
9264 }
9265
9266 void intel_modeset_gem_init(struct drm_device *dev)
9267 {
9268 intel_modeset_init_hw(dev);
9269
9270 intel_setup_overlay(dev);
9271
9272 intel_modeset_setup_hw_state(dev, false);
9273 }
9274
9275 void intel_modeset_cleanup(struct drm_device *dev)
9276 {
9277 struct drm_i915_private *dev_priv = dev->dev_private;
9278 struct drm_crtc *crtc;
9279 struct intel_crtc *intel_crtc;
9280
9281 drm_kms_helper_poll_fini(dev);
9282 mutex_lock(&dev->struct_mutex);
9283
9284 intel_unregister_dsm_handler();
9285
9286
9287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9288 /* Skip inactive CRTCs */
9289 if (!crtc->fb)
9290 continue;
9291
9292 intel_crtc = to_intel_crtc(crtc);
9293 intel_increase_pllclock(crtc);
9294 }
9295
9296 intel_disable_fbc(dev);
9297
9298 intel_disable_gt_powersave(dev);
9299
9300 ironlake_teardown_rc6(dev);
9301
9302 if (IS_VALLEYVIEW(dev))
9303 vlv_init_dpio(dev);
9304
9305 mutex_unlock(&dev->struct_mutex);
9306
9307 /* Disable the irq before mode object teardown, for the irq might
9308 * enqueue unpin/hotplug work. */
9309 drm_irq_uninstall(dev);
9310 cancel_work_sync(&dev_priv->hotplug_work);
9311 cancel_work_sync(&dev_priv->rps.work);
9312
9313 /* flush any delayed tasks or pending work */
9314 flush_scheduled_work();
9315
9316 drm_mode_config_cleanup(dev);
9317
9318 intel_cleanup_overlay(dev);
9319 }
9320
9321 /*
9322 * Return which encoder is currently attached for connector.
9323 */
9324 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9325 {
9326 return &intel_attached_encoder(connector)->base;
9327 }
9328
9329 void intel_connector_attach_encoder(struct intel_connector *connector,
9330 struct intel_encoder *encoder)
9331 {
9332 connector->encoder = encoder;
9333 drm_mode_connector_attach_encoder(&connector->base,
9334 &encoder->base);
9335 }
9336
9337 /*
9338 * set vga decode state - true == enable VGA decode
9339 */
9340 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9341 {
9342 struct drm_i915_private *dev_priv = dev->dev_private;
9343 u16 gmch_ctrl;
9344
9345 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9346 if (state)
9347 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9348 else
9349 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9350 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9351 return 0;
9352 }
9353
9354 #ifdef CONFIG_DEBUG_FS
9355 #include <linux/seq_file.h>
9356
9357 struct intel_display_error_state {
9358 struct intel_cursor_error_state {
9359 u32 control;
9360 u32 position;
9361 u32 base;
9362 u32 size;
9363 } cursor[I915_MAX_PIPES];
9364
9365 struct intel_pipe_error_state {
9366 u32 conf;
9367 u32 source;
9368
9369 u32 htotal;
9370 u32 hblank;
9371 u32 hsync;
9372 u32 vtotal;
9373 u32 vblank;
9374 u32 vsync;
9375 } pipe[I915_MAX_PIPES];
9376
9377 struct intel_plane_error_state {
9378 u32 control;
9379 u32 stride;
9380 u32 size;
9381 u32 pos;
9382 u32 addr;
9383 u32 surface;
9384 u32 tile_offset;
9385 } plane[I915_MAX_PIPES];
9386 };
9387
9388 struct intel_display_error_state *
9389 intel_display_capture_error_state(struct drm_device *dev)
9390 {
9391 drm_i915_private_t *dev_priv = dev->dev_private;
9392 struct intel_display_error_state *error;
9393 enum transcoder cpu_transcoder;
9394 int i;
9395
9396 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9397 if (error == NULL)
9398 return NULL;
9399
9400 for_each_pipe(i) {
9401 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9402
9403 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9404 error->cursor[i].control = I915_READ(CURCNTR(i));
9405 error->cursor[i].position = I915_READ(CURPOS(i));
9406 error->cursor[i].base = I915_READ(CURBASE(i));
9407 } else {
9408 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9409 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9410 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9411 }
9412
9413 error->plane[i].control = I915_READ(DSPCNTR(i));
9414 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9415 if (INTEL_INFO(dev)->gen <= 3) {
9416 error->plane[i].size = I915_READ(DSPSIZE(i));
9417 error->plane[i].pos = I915_READ(DSPPOS(i));
9418 }
9419 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9420 error->plane[i].addr = I915_READ(DSPADDR(i));
9421 if (INTEL_INFO(dev)->gen >= 4) {
9422 error->plane[i].surface = I915_READ(DSPSURF(i));
9423 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9424 }
9425
9426 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9427 error->pipe[i].source = I915_READ(PIPESRC(i));
9428 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9429 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9430 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9431 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9432 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9433 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9434 }
9435
9436 return error;
9437 }
9438
9439 void
9440 intel_display_print_error_state(struct seq_file *m,
9441 struct drm_device *dev,
9442 struct intel_display_error_state *error)
9443 {
9444 int i;
9445
9446 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9447 for_each_pipe(i) {
9448 seq_printf(m, "Pipe [%d]:\n", i);
9449 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9450 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9451 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9452 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9453 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9454 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9455 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9456 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9457
9458 seq_printf(m, "Plane [%d]:\n", i);
9459 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9460 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9461 if (INTEL_INFO(dev)->gen <= 3) {
9462 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9463 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9464 }
9465 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9466 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9467 if (INTEL_INFO(dev)->gen >= 4) {
9468 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9469 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9470 }
9471
9472 seq_printf(m, "Cursor [%d]:\n", i);
9473 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9474 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9475 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9476 }
9477 }
9478 #endif
Ubuntu Hirsute Linux kernel mirror