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drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static void skylake_pfit_enable(struct intel_crtc *crtc);
114 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
115 static void ironlake_pfit_enable(struct intel_crtc *crtc);
116 static void intel_modeset_setup_hw_state(struct drm_device *dev);
117 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
118 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
119 static void intel_modeset_verify_crtc(struct drm_crtc *crtc,
120 struct drm_crtc_state *old_state,
121 struct drm_crtc_state *new_state);
122
123 struct intel_limit {
124 struct {
125 int min, max;
126 } dot, vco, n, m, m1, m2, p, p1;
127
128 struct {
129 int dot_limit;
130 int p2_slow, p2_fast;
131 } p2;
132 };
133
134 /* returns HPLL frequency in kHz */
135 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
136 {
137 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
138
139 /* Obtain SKU information */
140 mutex_lock(&dev_priv->sb_lock);
141 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
142 CCK_FUSE_HPLL_FREQ_MASK;
143 mutex_unlock(&dev_priv->sb_lock);
144
145 return vco_freq[hpll_freq] * 1000;
146 }
147
148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
149 const char *name, u32 reg, int ref_freq)
150 {
151 u32 val;
152 int divider;
153
154 mutex_lock(&dev_priv->sb_lock);
155 val = vlv_cck_read(dev_priv, reg);
156 mutex_unlock(&dev_priv->sb_lock);
157
158 divider = val & CCK_FREQUENCY_VALUES;
159
160 WARN((val & CCK_FREQUENCY_STATUS) !=
161 (divider << CCK_FREQUENCY_STATUS_SHIFT),
162 "%s change in progress\n", name);
163
164 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
165 }
166
167 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
168 const char *name, u32 reg)
169 {
170 if (dev_priv->hpll_freq == 0)
171 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
172
173 return vlv_get_cck_clock(dev_priv, name, reg,
174 dev_priv->hpll_freq);
175 }
176
177 static int
178 intel_pch_rawclk(struct drm_i915_private *dev_priv)
179 {
180 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
181 }
182
183 static int
184 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
185 {
186 /* RAWCLK_FREQ_VLV register updated from power well code */
187 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
188 CCK_DISPLAY_REF_CLOCK_CONTROL);
189 }
190
191 static int
192 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
193 {
194 uint32_t clkcfg;
195
196 /* hrawclock is 1/4 the FSB frequency */
197 clkcfg = I915_READ(CLKCFG);
198 switch (clkcfg & CLKCFG_FSB_MASK) {
199 case CLKCFG_FSB_400:
200 return 100000;
201 case CLKCFG_FSB_533:
202 return 133333;
203 case CLKCFG_FSB_667:
204 return 166667;
205 case CLKCFG_FSB_800:
206 return 200000;
207 case CLKCFG_FSB_1067:
208 return 266667;
209 case CLKCFG_FSB_1333:
210 return 333333;
211 /* these two are just a guess; one of them might be right */
212 case CLKCFG_FSB_1600:
213 case CLKCFG_FSB_1600_ALT:
214 return 400000;
215 default:
216 return 133333;
217 }
218 }
219
220 void intel_update_rawclk(struct drm_i915_private *dev_priv)
221 {
222 if (HAS_PCH_SPLIT(dev_priv))
223 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
224 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
225 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
226 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
227 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
228 else
229 return; /* no rawclk on other platforms, or no need to know it */
230
231 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
232 }
233
234 static void intel_update_czclk(struct drm_i915_private *dev_priv)
235 {
236 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 return;
238
239 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
240 CCK_CZ_CLOCK_CONTROL);
241
242 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
243 }
244
245 static inline u32 /* units of 100MHz */
246 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
247 const struct intel_crtc_state *pipe_config)
248 {
249 if (HAS_DDI(dev_priv))
250 return pipe_config->port_clock; /* SPLL */
251 else if (IS_GEN5(dev_priv))
252 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
253 else
254 return 270000;
255 }
256
257 static const struct intel_limit intel_limits_i8xx_dac = {
258 .dot = { .min = 25000, .max = 350000 },
259 .vco = { .min = 908000, .max = 1512000 },
260 .n = { .min = 2, .max = 16 },
261 .m = { .min = 96, .max = 140 },
262 .m1 = { .min = 18, .max = 26 },
263 .m2 = { .min = 6, .max = 16 },
264 .p = { .min = 4, .max = 128 },
265 .p1 = { .min = 2, .max = 33 },
266 .p2 = { .dot_limit = 165000,
267 .p2_slow = 4, .p2_fast = 2 },
268 };
269
270 static const struct intel_limit intel_limits_i8xx_dvo = {
271 .dot = { .min = 25000, .max = 350000 },
272 .vco = { .min = 908000, .max = 1512000 },
273 .n = { .min = 2, .max = 16 },
274 .m = { .min = 96, .max = 140 },
275 .m1 = { .min = 18, .max = 26 },
276 .m2 = { .min = 6, .max = 16 },
277 .p = { .min = 4, .max = 128 },
278 .p1 = { .min = 2, .max = 33 },
279 .p2 = { .dot_limit = 165000,
280 .p2_slow = 4, .p2_fast = 4 },
281 };
282
283 static const struct intel_limit intel_limits_i8xx_lvds = {
284 .dot = { .min = 25000, .max = 350000 },
285 .vco = { .min = 908000, .max = 1512000 },
286 .n = { .min = 2, .max = 16 },
287 .m = { .min = 96, .max = 140 },
288 .m1 = { .min = 18, .max = 26 },
289 .m2 = { .min = 6, .max = 16 },
290 .p = { .min = 4, .max = 128 },
291 .p1 = { .min = 1, .max = 6 },
292 .p2 = { .dot_limit = 165000,
293 .p2_slow = 14, .p2_fast = 7 },
294 };
295
296 static const struct intel_limit intel_limits_i9xx_sdvo = {
297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1400000, .max = 2800000 },
299 .n = { .min = 1, .max = 6 },
300 .m = { .min = 70, .max = 120 },
301 .m1 = { .min = 8, .max = 18 },
302 .m2 = { .min = 3, .max = 7 },
303 .p = { .min = 5, .max = 80 },
304 .p1 = { .min = 1, .max = 8 },
305 .p2 = { .dot_limit = 200000,
306 .p2_slow = 10, .p2_fast = 5 },
307 };
308
309 static const struct intel_limit intel_limits_i9xx_lvds = {
310 .dot = { .min = 20000, .max = 400000 },
311 .vco = { .min = 1400000, .max = 2800000 },
312 .n = { .min = 1, .max = 6 },
313 .m = { .min = 70, .max = 120 },
314 .m1 = { .min = 8, .max = 18 },
315 .m2 = { .min = 3, .max = 7 },
316 .p = { .min = 7, .max = 98 },
317 .p1 = { .min = 1, .max = 8 },
318 .p2 = { .dot_limit = 112000,
319 .p2_slow = 14, .p2_fast = 7 },
320 };
321
322
323 static const struct intel_limit intel_limits_g4x_sdvo = {
324 .dot = { .min = 25000, .max = 270000 },
325 .vco = { .min = 1750000, .max = 3500000},
326 .n = { .min = 1, .max = 4 },
327 .m = { .min = 104, .max = 138 },
328 .m1 = { .min = 17, .max = 23 },
329 .m2 = { .min = 5, .max = 11 },
330 .p = { .min = 10, .max = 30 },
331 .p1 = { .min = 1, .max = 3},
332 .p2 = { .dot_limit = 270000,
333 .p2_slow = 10,
334 .p2_fast = 10
335 },
336 };
337
338 static const struct intel_limit intel_limits_g4x_hdmi = {
339 .dot = { .min = 22000, .max = 400000 },
340 .vco = { .min = 1750000, .max = 3500000},
341 .n = { .min = 1, .max = 4 },
342 .m = { .min = 104, .max = 138 },
343 .m1 = { .min = 16, .max = 23 },
344 .m2 = { .min = 5, .max = 11 },
345 .p = { .min = 5, .max = 80 },
346 .p1 = { .min = 1, .max = 8},
347 .p2 = { .dot_limit = 165000,
348 .p2_slow = 10, .p2_fast = 5 },
349 };
350
351 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
352 .dot = { .min = 20000, .max = 115000 },
353 .vco = { .min = 1750000, .max = 3500000 },
354 .n = { .min = 1, .max = 3 },
355 .m = { .min = 104, .max = 138 },
356 .m1 = { .min = 17, .max = 23 },
357 .m2 = { .min = 5, .max = 11 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 0,
361 .p2_slow = 14, .p2_fast = 14
362 },
363 };
364
365 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
366 .dot = { .min = 80000, .max = 224000 },
367 .vco = { .min = 1750000, .max = 3500000 },
368 .n = { .min = 1, .max = 3 },
369 .m = { .min = 104, .max = 138 },
370 .m1 = { .min = 17, .max = 23 },
371 .m2 = { .min = 5, .max = 11 },
372 .p = { .min = 14, .max = 42 },
373 .p1 = { .min = 2, .max = 6 },
374 .p2 = { .dot_limit = 0,
375 .p2_slow = 7, .p2_fast = 7
376 },
377 };
378
379 static const struct intel_limit intel_limits_pineview_sdvo = {
380 .dot = { .min = 20000, .max = 400000},
381 .vco = { .min = 1700000, .max = 3500000 },
382 /* Pineview's Ncounter is a ring counter */
383 .n = { .min = 3, .max = 6 },
384 .m = { .min = 2, .max = 256 },
385 /* Pineview only has one combined m divider, which we treat as m2. */
386 .m1 = { .min = 0, .max = 0 },
387 .m2 = { .min = 0, .max = 254 },
388 .p = { .min = 5, .max = 80 },
389 .p1 = { .min = 1, .max = 8 },
390 .p2 = { .dot_limit = 200000,
391 .p2_slow = 10, .p2_fast = 5 },
392 };
393
394 static const struct intel_limit intel_limits_pineview_lvds = {
395 .dot = { .min = 20000, .max = 400000 },
396 .vco = { .min = 1700000, .max = 3500000 },
397 .n = { .min = 3, .max = 6 },
398 .m = { .min = 2, .max = 256 },
399 .m1 = { .min = 0, .max = 0 },
400 .m2 = { .min = 0, .max = 254 },
401 .p = { .min = 7, .max = 112 },
402 .p1 = { .min = 1, .max = 8 },
403 .p2 = { .dot_limit = 112000,
404 .p2_slow = 14, .p2_fast = 14 },
405 };
406
407 /* Ironlake / Sandybridge
408 *
409 * We calculate clock using (register_value + 2) for N/M1/M2, so here
410 * the range value for them is (actual_value - 2).
411 */
412 static const struct intel_limit intel_limits_ironlake_dac = {
413 .dot = { .min = 25000, .max = 350000 },
414 .vco = { .min = 1760000, .max = 3510000 },
415 .n = { .min = 1, .max = 5 },
416 .m = { .min = 79, .max = 127 },
417 .m1 = { .min = 12, .max = 22 },
418 .m2 = { .min = 5, .max = 9 },
419 .p = { .min = 5, .max = 80 },
420 .p1 = { .min = 1, .max = 8 },
421 .p2 = { .dot_limit = 225000,
422 .p2_slow = 10, .p2_fast = 5 },
423 };
424
425 static const struct intel_limit intel_limits_ironlake_single_lvds = {
426 .dot = { .min = 25000, .max = 350000 },
427 .vco = { .min = 1760000, .max = 3510000 },
428 .n = { .min = 1, .max = 3 },
429 .m = { .min = 79, .max = 118 },
430 .m1 = { .min = 12, .max = 22 },
431 .m2 = { .min = 5, .max = 9 },
432 .p = { .min = 28, .max = 112 },
433 .p1 = { .min = 2, .max = 8 },
434 .p2 = { .dot_limit = 225000,
435 .p2_slow = 14, .p2_fast = 14 },
436 };
437
438 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
439 .dot = { .min = 25000, .max = 350000 },
440 .vco = { .min = 1760000, .max = 3510000 },
441 .n = { .min = 1, .max = 3 },
442 .m = { .min = 79, .max = 127 },
443 .m1 = { .min = 12, .max = 22 },
444 .m2 = { .min = 5, .max = 9 },
445 .p = { .min = 14, .max = 56 },
446 .p1 = { .min = 2, .max = 8 },
447 .p2 = { .dot_limit = 225000,
448 .p2_slow = 7, .p2_fast = 7 },
449 };
450
451 /* LVDS 100mhz refclk limits. */
452 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
453 .dot = { .min = 25000, .max = 350000 },
454 .vco = { .min = 1760000, .max = 3510000 },
455 .n = { .min = 1, .max = 2 },
456 .m = { .min = 79, .max = 126 },
457 .m1 = { .min = 12, .max = 22 },
458 .m2 = { .min = 5, .max = 9 },
459 .p = { .min = 28, .max = 112 },
460 .p1 = { .min = 2, .max = 8 },
461 .p2 = { .dot_limit = 225000,
462 .p2_slow = 14, .p2_fast = 14 },
463 };
464
465 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
466 .dot = { .min = 25000, .max = 350000 },
467 .vco = { .min = 1760000, .max = 3510000 },
468 .n = { .min = 1, .max = 3 },
469 .m = { .min = 79, .max = 126 },
470 .m1 = { .min = 12, .max = 22 },
471 .m2 = { .min = 5, .max = 9 },
472 .p = { .min = 14, .max = 42 },
473 .p1 = { .min = 2, .max = 6 },
474 .p2 = { .dot_limit = 225000,
475 .p2_slow = 7, .p2_fast = 7 },
476 };
477
478 static const struct intel_limit intel_limits_vlv = {
479 /*
480 * These are the data rate limits (measured in fast clocks)
481 * since those are the strictest limits we have. The fast
482 * clock and actual rate limits are more relaxed, so checking
483 * them would make no difference.
484 */
485 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
486 .vco = { .min = 4000000, .max = 6000000 },
487 .n = { .min = 1, .max = 7 },
488 .m1 = { .min = 2, .max = 3 },
489 .m2 = { .min = 11, .max = 156 },
490 .p1 = { .min = 2, .max = 3 },
491 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
492 };
493
494 static const struct intel_limit intel_limits_chv = {
495 /*
496 * These are the data rate limits (measured in fast clocks)
497 * since those are the strictest limits we have. The fast
498 * clock and actual rate limits are more relaxed, so checking
499 * them would make no difference.
500 */
501 .dot = { .min = 25000 * 5, .max = 540000 * 5},
502 .vco = { .min = 4800000, .max = 6480000 },
503 .n = { .min = 1, .max = 1 },
504 .m1 = { .min = 2, .max = 2 },
505 .m2 = { .min = 24 << 22, .max = 175 << 22 },
506 .p1 = { .min = 2, .max = 4 },
507 .p2 = { .p2_slow = 1, .p2_fast = 14 },
508 };
509
510 static const struct intel_limit intel_limits_bxt = {
511 /* FIXME: find real dot limits */
512 .dot = { .min = 0, .max = INT_MAX },
513 .vco = { .min = 4800000, .max = 6700000 },
514 .n = { .min = 1, .max = 1 },
515 .m1 = { .min = 2, .max = 2 },
516 /* FIXME: find real m2 limits */
517 .m2 = { .min = 2 << 22, .max = 255 << 22 },
518 .p1 = { .min = 2, .max = 4 },
519 .p2 = { .p2_slow = 1, .p2_fast = 20 },
520 };
521
522 static bool
523 needs_modeset(struct drm_crtc_state *state)
524 {
525 return drm_atomic_crtc_needs_modeset(state);
526 }
527
528 /**
529 * Returns whether any output on the specified pipe is of the specified type
530 */
531 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
532 {
533 struct drm_device *dev = crtc->base.dev;
534 struct intel_encoder *encoder;
535
536 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
537 if (encoder->type == type)
538 return true;
539
540 return false;
541 }
542
543 /**
544 * Returns whether any output on the specified pipe will have the specified
545 * type after a staged modeset is complete, i.e., the same as
546 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
547 * encoder->crtc.
548 */
549 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
550 int type)
551 {
552 struct drm_atomic_state *state = crtc_state->base.state;
553 struct drm_connector *connector;
554 struct drm_connector_state *connector_state;
555 struct intel_encoder *encoder;
556 int i, num_connectors = 0;
557
558 for_each_connector_in_state(state, connector, connector_state, i) {
559 if (connector_state->crtc != crtc_state->base.crtc)
560 continue;
561
562 num_connectors++;
563
564 encoder = to_intel_encoder(connector_state->best_encoder);
565 if (encoder->type == type)
566 return true;
567 }
568
569 WARN_ON(num_connectors == 0);
570
571 return false;
572 }
573
574 /*
575 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
576 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
577 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
578 * The helpers' return value is the rate of the clock that is fed to the
579 * display engine's pipe which can be the above fast dot clock rate or a
580 * divided-down version of it.
581 */
582 /* m1 is reserved as 0 in Pineview, n is a ring counter */
583 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
584 {
585 clock->m = clock->m2 + 2;
586 clock->p = clock->p1 * clock->p2;
587 if (WARN_ON(clock->n == 0 || clock->p == 0))
588 return 0;
589 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
590 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
591
592 return clock->dot;
593 }
594
595 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
596 {
597 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
598 }
599
600 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
601 {
602 clock->m = i9xx_dpll_compute_m(clock);
603 clock->p = clock->p1 * clock->p2;
604 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
605 return 0;
606 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
607 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
608
609 return clock->dot;
610 }
611
612 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
613 {
614 clock->m = clock->m1 * clock->m2;
615 clock->p = clock->p1 * clock->p2;
616 if (WARN_ON(clock->n == 0 || clock->p == 0))
617 return 0;
618 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
619 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
620
621 return clock->dot / 5;
622 }
623
624 int chv_calc_dpll_params(int refclk, struct dpll *clock)
625 {
626 clock->m = clock->m1 * clock->m2;
627 clock->p = clock->p1 * clock->p2;
628 if (WARN_ON(clock->n == 0 || clock->p == 0))
629 return 0;
630 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
631 clock->n << 22);
632 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
633
634 return clock->dot / 5;
635 }
636
637 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
638 /**
639 * Returns whether the given set of divisors are valid for a given refclk with
640 * the given connectors.
641 */
642
643 static bool intel_PLL_is_valid(struct drm_device *dev,
644 const struct intel_limit *limit,
645 const struct dpll *clock)
646 {
647 if (clock->n < limit->n.min || limit->n.max < clock->n)
648 INTELPllInvalid("n out of range\n");
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
652 INTELPllInvalid("m2 out of range\n");
653 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
654 INTELPllInvalid("m1 out of range\n");
655
656 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
657 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
658 if (clock->m1 <= clock->m2)
659 INTELPllInvalid("m1 <= m2\n");
660
661 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
662 if (clock->p < limit->p.min || limit->p.max < clock->p)
663 INTELPllInvalid("p out of range\n");
664 if (clock->m < limit->m.min || limit->m.max < clock->m)
665 INTELPllInvalid("m out of range\n");
666 }
667
668 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
669 INTELPllInvalid("vco out of range\n");
670 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
671 * connector, etc., rather than just a single range.
672 */
673 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 INTELPllInvalid("dot out of range\n");
675
676 return true;
677 }
678
679 static int
680 i9xx_select_p2_div(const struct intel_limit *limit,
681 const struct intel_crtc_state *crtc_state,
682 int target)
683 {
684 struct drm_device *dev = crtc_state->base.crtc->dev;
685
686 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
687 /*
688 * For LVDS just rely on its current settings for dual-channel.
689 * We haven't figured out how to reliably set up different
690 * single/dual channel state, if we even can.
691 */
692 if (intel_is_dual_link_lvds(dev))
693 return limit->p2.p2_fast;
694 else
695 return limit->p2.p2_slow;
696 } else {
697 if (target < limit->p2.dot_limit)
698 return limit->p2.p2_slow;
699 else
700 return limit->p2.p2_fast;
701 }
702 }
703
704 /*
705 * Returns a set of divisors for the desired target clock with the given
706 * refclk, or FALSE. The returned values represent the clock equation:
707 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
708 *
709 * Target and reference clocks are specified in kHz.
710 *
711 * If match_clock is provided, then best_clock P divider must match the P
712 * divider from @match_clock used for LVDS downclocking.
713 */
714 static bool
715 i9xx_find_best_dpll(const struct intel_limit *limit,
716 struct intel_crtc_state *crtc_state,
717 int target, int refclk, struct dpll *match_clock,
718 struct dpll *best_clock)
719 {
720 struct drm_device *dev = crtc_state->base.crtc->dev;
721 struct dpll clock;
722 int err = target;
723
724 memset(best_clock, 0, sizeof(*best_clock));
725
726 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
727
728 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
729 clock.m1++) {
730 for (clock.m2 = limit->m2.min;
731 clock.m2 <= limit->m2.max; clock.m2++) {
732 if (clock.m2 >= clock.m1)
733 break;
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 i9xx_calc_dpll_params(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 /*
762 * Returns a set of divisors for the desired target clock with the given
763 * refclk, or FALSE. The returned values represent the clock equation:
764 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
765 *
766 * Target and reference clocks are specified in kHz.
767 *
768 * If match_clock is provided, then best_clock P divider must match the P
769 * divider from @match_clock used for LVDS downclocking.
770 */
771 static bool
772 pnv_find_best_dpll(const struct intel_limit *limit,
773 struct intel_crtc_state *crtc_state,
774 int target, int refclk, struct dpll *match_clock,
775 struct dpll *best_clock)
776 {
777 struct drm_device *dev = crtc_state->base.crtc->dev;
778 struct dpll clock;
779 int err = target;
780
781 memset(best_clock, 0, sizeof(*best_clock));
782
783 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
784
785 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
786 clock.m1++) {
787 for (clock.m2 = limit->m2.min;
788 clock.m2 <= limit->m2.max; clock.m2++) {
789 for (clock.n = limit->n.min;
790 clock.n <= limit->n.max; clock.n++) {
791 for (clock.p1 = limit->p1.min;
792 clock.p1 <= limit->p1.max; clock.p1++) {
793 int this_err;
794
795 pnv_calc_dpll_params(refclk, &clock);
796 if (!intel_PLL_is_valid(dev, limit,
797 &clock))
798 continue;
799 if (match_clock &&
800 clock.p != match_clock->p)
801 continue;
802
803 this_err = abs(clock.dot - target);
804 if (this_err < err) {
805 *best_clock = clock;
806 err = this_err;
807 }
808 }
809 }
810 }
811 }
812
813 return (err != target);
814 }
815
816 /*
817 * Returns a set of divisors for the desired target clock with the given
818 * refclk, or FALSE. The returned values represent the clock equation:
819 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
820 *
821 * Target and reference clocks are specified in kHz.
822 *
823 * If match_clock is provided, then best_clock P divider must match the P
824 * divider from @match_clock used for LVDS downclocking.
825 */
826 static bool
827 g4x_find_best_dpll(const struct intel_limit *limit,
828 struct intel_crtc_state *crtc_state,
829 int target, int refclk, struct dpll *match_clock,
830 struct dpll *best_clock)
831 {
832 struct drm_device *dev = crtc_state->base.crtc->dev;
833 struct dpll clock;
834 int max_n;
835 bool found = false;
836 /* approximately equals target * 0.00585 */
837 int err_most = (target >> 8) + (target >> 9);
838
839 memset(best_clock, 0, sizeof(*best_clock));
840
841 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
842
843 max_n = limit->n.max;
844 /* based on hardware requirement, prefer smaller n to precision */
845 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
846 /* based on hardware requirement, prefere larger m1,m2 */
847 for (clock.m1 = limit->m1.max;
848 clock.m1 >= limit->m1.min; clock.m1--) {
849 for (clock.m2 = limit->m2.max;
850 clock.m2 >= limit->m2.min; clock.m2--) {
851 for (clock.p1 = limit->p1.max;
852 clock.p1 >= limit->p1.min; clock.p1--) {
853 int this_err;
854
855 i9xx_calc_dpll_params(refclk, &clock);
856 if (!intel_PLL_is_valid(dev, limit,
857 &clock))
858 continue;
859
860 this_err = abs(clock.dot - target);
861 if (this_err < err_most) {
862 *best_clock = clock;
863 err_most = this_err;
864 max_n = clock.n;
865 found = true;
866 }
867 }
868 }
869 }
870 }
871 return found;
872 }
873
874 /*
875 * Check if the calculated PLL configuration is more optimal compared to the
876 * best configuration and error found so far. Return the calculated error.
877 */
878 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
879 const struct dpll *calculated_clock,
880 const struct dpll *best_clock,
881 unsigned int best_error_ppm,
882 unsigned int *error_ppm)
883 {
884 /*
885 * For CHV ignore the error and consider only the P value.
886 * Prefer a bigger P value based on HW requirements.
887 */
888 if (IS_CHERRYVIEW(dev)) {
889 *error_ppm = 0;
890
891 return calculated_clock->p > best_clock->p;
892 }
893
894 if (WARN_ON_ONCE(!target_freq))
895 return false;
896
897 *error_ppm = div_u64(1000000ULL *
898 abs(target_freq - calculated_clock->dot),
899 target_freq);
900 /*
901 * Prefer a better P value over a better (smaller) error if the error
902 * is small. Ensure this preference for future configurations too by
903 * setting the error to 0.
904 */
905 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
906 *error_ppm = 0;
907
908 return true;
909 }
910
911 return *error_ppm + 10 < best_error_ppm;
912 }
913
914 /*
915 * Returns a set of divisors for the desired target clock with the given
916 * refclk, or FALSE. The returned values represent the clock equation:
917 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
918 */
919 static bool
920 vlv_find_best_dpll(const struct intel_limit *limit,
921 struct intel_crtc_state *crtc_state,
922 int target, int refclk, struct dpll *match_clock,
923 struct dpll *best_clock)
924 {
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
926 struct drm_device *dev = crtc->base.dev;
927 struct dpll clock;
928 unsigned int bestppm = 1000000;
929 /* min update 19.2 MHz */
930 int max_n = min(limit->n.max, refclk / 19200);
931 bool found = false;
932
933 target *= 5; /* fast clock */
934
935 memset(best_clock, 0, sizeof(*best_clock));
936
937 /* based on hardware requirement, prefer smaller n to precision */
938 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
939 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
940 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
942 clock.p = clock.p1 * clock.p2;
943 /* based on hardware requirement, prefer bigger m1,m2 values */
944 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
945 unsigned int ppm;
946
947 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
948 refclk * clock.m1);
949
950 vlv_calc_dpll_params(refclk, &clock);
951
952 if (!intel_PLL_is_valid(dev, limit,
953 &clock))
954 continue;
955
956 if (!vlv_PLL_is_optimal(dev, target,
957 &clock,
958 best_clock,
959 bestppm, &ppm))
960 continue;
961
962 *best_clock = clock;
963 bestppm = ppm;
964 found = true;
965 }
966 }
967 }
968 }
969
970 return found;
971 }
972
973 /*
974 * Returns a set of divisors for the desired target clock with the given
975 * refclk, or FALSE. The returned values represent the clock equation:
976 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 */
978 static bool
979 chv_find_best_dpll(const struct intel_limit *limit,
980 struct intel_crtc_state *crtc_state,
981 int target, int refclk, struct dpll *match_clock,
982 struct dpll *best_clock)
983 {
984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
985 struct drm_device *dev = crtc->base.dev;
986 unsigned int best_error_ppm;
987 struct dpll clock;
988 uint64_t m2;
989 int found = false;
990
991 memset(best_clock, 0, sizeof(*best_clock));
992 best_error_ppm = 1000000;
993
994 /*
995 * Based on hardware doc, the n always set to 1, and m1 always
996 * set to 2. If requires to support 200Mhz refclk, we need to
997 * revisit this because n may not 1 anymore.
998 */
999 clock.n = 1, clock.m1 = 2;
1000 target *= 5; /* fast clock */
1001
1002 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1003 for (clock.p2 = limit->p2.p2_fast;
1004 clock.p2 >= limit->p2.p2_slow;
1005 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1006 unsigned int error_ppm;
1007
1008 clock.p = clock.p1 * clock.p2;
1009
1010 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1011 clock.n) << 22, refclk * clock.m1);
1012
1013 if (m2 > INT_MAX/clock.m1)
1014 continue;
1015
1016 clock.m2 = m2;
1017
1018 chv_calc_dpll_params(refclk, &clock);
1019
1020 if (!intel_PLL_is_valid(dev, limit, &clock))
1021 continue;
1022
1023 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1024 best_error_ppm, &error_ppm))
1025 continue;
1026
1027 *best_clock = clock;
1028 best_error_ppm = error_ppm;
1029 found = true;
1030 }
1031 }
1032
1033 return found;
1034 }
1035
1036 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1037 struct dpll *best_clock)
1038 {
1039 int refclk = 100000;
1040 const struct intel_limit *limit = &intel_limits_bxt;
1041
1042 return chv_find_best_dpll(limit, crtc_state,
1043 target_clock, refclk, NULL, best_clock);
1044 }
1045
1046 bool intel_crtc_active(struct drm_crtc *crtc)
1047 {
1048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1049
1050 /* Be paranoid as we can arrive here with only partial
1051 * state retrieved from the hardware during setup.
1052 *
1053 * We can ditch the adjusted_mode.crtc_clock check as soon
1054 * as Haswell has gained clock readout/fastboot support.
1055 *
1056 * We can ditch the crtc->primary->fb check as soon as we can
1057 * properly reconstruct framebuffers.
1058 *
1059 * FIXME: The intel_crtc->active here should be switched to
1060 * crtc->state->active once we have proper CRTC states wired up
1061 * for atomic.
1062 */
1063 return intel_crtc->active && crtc->primary->state->fb &&
1064 intel_crtc->config->base.adjusted_mode.crtc_clock;
1065 }
1066
1067 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1068 enum pipe pipe)
1069 {
1070 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072
1073 return intel_crtc->config->cpu_transcoder;
1074 }
1075
1076 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1077 {
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 i915_reg_t reg = PIPEDSL(pipe);
1080 u32 line1, line2;
1081 u32 line_mask;
1082
1083 if (IS_GEN2(dev))
1084 line_mask = DSL_LINEMASK_GEN2;
1085 else
1086 line_mask = DSL_LINEMASK_GEN3;
1087
1088 line1 = I915_READ(reg) & line_mask;
1089 msleep(5);
1090 line2 = I915_READ(reg) & line_mask;
1091
1092 return line1 == line2;
1093 }
1094
1095 /*
1096 * intel_wait_for_pipe_off - wait for pipe to turn off
1097 * @crtc: crtc whose pipe to wait for
1098 *
1099 * After disabling a pipe, we can't wait for vblank in the usual way,
1100 * spinning on the vblank interrupt status bit, since we won't actually
1101 * see an interrupt when the pipe is disabled.
1102 *
1103 * On Gen4 and above:
1104 * wait for the pipe register state bit to turn off
1105 *
1106 * Otherwise:
1107 * wait for the display line value to settle (it usually
1108 * ends up stopping at the start of the next frame).
1109 *
1110 */
1111 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1112 {
1113 struct drm_device *dev = crtc->base.dev;
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1116 enum pipe pipe = crtc->pipe;
1117
1118 if (INTEL_INFO(dev)->gen >= 4) {
1119 i915_reg_t reg = PIPECONF(cpu_transcoder);
1120
1121 /* Wait for the Pipe State to go off */
1122 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1123 100))
1124 WARN(1, "pipe_off wait timed out\n");
1125 } else {
1126 /* Wait for the display line to settle */
1127 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1128 WARN(1, "pipe_off wait timed out\n");
1129 }
1130 }
1131
1132 /* Only for pre-ILK configs */
1133 void assert_pll(struct drm_i915_private *dev_priv,
1134 enum pipe pipe, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 val = I915_READ(DPLL(pipe));
1140 cur_state = !!(val & DPLL_VCO_ENABLE);
1141 I915_STATE_WARN(cur_state != state,
1142 "PLL state assertion failure (expected %s, current %s)\n",
1143 onoff(state), onoff(cur_state));
1144 }
1145
1146 /* XXX: the dsi pll is shared between MIPI DSI ports */
1147 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1148 {
1149 u32 val;
1150 bool cur_state;
1151
1152 mutex_lock(&dev_priv->sb_lock);
1153 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1154 mutex_unlock(&dev_priv->sb_lock);
1155
1156 cur_state = val & DSI_PLL_VCO_EN;
1157 I915_STATE_WARN(cur_state != state,
1158 "DSI PLL state assertion failure (expected %s, current %s)\n",
1159 onoff(state), onoff(cur_state));
1160 }
1161
1162 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1163 enum pipe pipe, bool state)
1164 {
1165 bool cur_state;
1166 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1167 pipe);
1168
1169 if (HAS_DDI(dev_priv)) {
1170 /* DDI does not have a specific FDI_TX register */
1171 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1172 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1173 } else {
1174 u32 val = I915_READ(FDI_TX_CTL(pipe));
1175 cur_state = !!(val & FDI_TX_ENABLE);
1176 }
1177 I915_STATE_WARN(cur_state != state,
1178 "FDI TX state assertion failure (expected %s, current %s)\n",
1179 onoff(state), onoff(cur_state));
1180 }
1181 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1182 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1183
1184 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186 {
1187 u32 val;
1188 bool cur_state;
1189
1190 val = I915_READ(FDI_RX_CTL(pipe));
1191 cur_state = !!(val & FDI_RX_ENABLE);
1192 I915_STATE_WARN(cur_state != state,
1193 "FDI RX state assertion failure (expected %s, current %s)\n",
1194 onoff(state), onoff(cur_state));
1195 }
1196 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1197 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1198
1199 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe)
1201 {
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
1205 if (IS_GEN5(dev_priv))
1206 return;
1207
1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209 if (HAS_DDI(dev_priv))
1210 return;
1211
1212 val = I915_READ(FDI_TX_CTL(pipe));
1213 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1214 }
1215
1216 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218 {
1219 u32 val;
1220 bool cur_state;
1221
1222 val = I915_READ(FDI_RX_CTL(pipe));
1223 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1224 I915_STATE_WARN(cur_state != state,
1225 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1226 onoff(state), onoff(cur_state));
1227 }
1228
1229 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1230 enum pipe pipe)
1231 {
1232 struct drm_device *dev = dev_priv->dev;
1233 i915_reg_t pp_reg;
1234 u32 val;
1235 enum pipe panel_pipe = PIPE_A;
1236 bool locked = true;
1237
1238 if (WARN_ON(HAS_DDI(dev)))
1239 return;
1240
1241 if (HAS_PCH_SPLIT(dev)) {
1242 u32 port_sel;
1243
1244 pp_reg = PCH_PP_CONTROL;
1245 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1246
1247 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1248 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1249 panel_pipe = PIPE_B;
1250 /* XXX: else fix for eDP */
1251 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1252 /* presumably write lock depends on pipe, not port select */
1253 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1254 panel_pipe = pipe;
1255 } else {
1256 pp_reg = PP_CONTROL;
1257 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1258 panel_pipe = PIPE_B;
1259 }
1260
1261 val = I915_READ(pp_reg);
1262 if (!(val & PANEL_POWER_ON) ||
1263 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1264 locked = false;
1265
1266 I915_STATE_WARN(panel_pipe == pipe && locked,
1267 "panel assertion failure, pipe %c regs locked\n",
1268 pipe_name(pipe));
1269 }
1270
1271 static void assert_cursor(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 struct drm_device *dev = dev_priv->dev;
1275 bool cur_state;
1276
1277 if (IS_845G(dev) || IS_I865G(dev))
1278 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1279 else
1280 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1281
1282 I915_STATE_WARN(cur_state != state,
1283 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1284 pipe_name(pipe), onoff(state), onoff(cur_state));
1285 }
1286 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1287 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1288
1289 void assert_pipe(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, bool state)
1291 {
1292 bool cur_state;
1293 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1294 pipe);
1295 enum intel_display_power_domain power_domain;
1296
1297 /* if we need the pipe quirk it must be always on */
1298 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1299 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1300 state = true;
1301
1302 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1303 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1304 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1305 cur_state = !!(val & PIPECONF_ENABLE);
1306
1307 intel_display_power_put(dev_priv, power_domain);
1308 } else {
1309 cur_state = false;
1310 }
1311
1312 I915_STATE_WARN(cur_state != state,
1313 "pipe %c assertion failure (expected %s, current %s)\n",
1314 pipe_name(pipe), onoff(state), onoff(cur_state));
1315 }
1316
1317 static void assert_plane(struct drm_i915_private *dev_priv,
1318 enum plane plane, bool state)
1319 {
1320 u32 val;
1321 bool cur_state;
1322
1323 val = I915_READ(DSPCNTR(plane));
1324 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1325 I915_STATE_WARN(cur_state != state,
1326 "plane %c assertion failure (expected %s, current %s)\n",
1327 plane_name(plane), onoff(state), onoff(cur_state));
1328 }
1329
1330 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1331 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1332
1333 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1334 enum pipe pipe)
1335 {
1336 struct drm_device *dev = dev_priv->dev;
1337 int i;
1338
1339 /* Primary planes are fixed to pipes on gen4+ */
1340 if (INTEL_INFO(dev)->gen >= 4) {
1341 u32 val = I915_READ(DSPCNTR(pipe));
1342 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1343 "plane %c assertion failure, should be disabled but not\n",
1344 plane_name(pipe));
1345 return;
1346 }
1347
1348 /* Need to check both planes against the pipe */
1349 for_each_pipe(dev_priv, i) {
1350 u32 val = I915_READ(DSPCNTR(i));
1351 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1352 DISPPLANE_SEL_PIPE_SHIFT;
1353 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1354 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1355 plane_name(i), pipe_name(pipe));
1356 }
1357 }
1358
1359 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 struct drm_device *dev = dev_priv->dev;
1363 int sprite;
1364
1365 if (INTEL_INFO(dev)->gen >= 9) {
1366 for_each_sprite(dev_priv, pipe, sprite) {
1367 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1368 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1369 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1370 sprite, pipe_name(pipe));
1371 }
1372 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1373 for_each_sprite(dev_priv, pipe, sprite) {
1374 u32 val = I915_READ(SPCNTR(pipe, sprite));
1375 I915_STATE_WARN(val & SP_ENABLE,
1376 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1377 sprite_name(pipe, sprite), pipe_name(pipe));
1378 }
1379 } else if (INTEL_INFO(dev)->gen >= 7) {
1380 u32 val = I915_READ(SPRCTL(pipe));
1381 I915_STATE_WARN(val & SPRITE_ENABLE,
1382 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1383 plane_name(pipe), pipe_name(pipe));
1384 } else if (INTEL_INFO(dev)->gen >= 5) {
1385 u32 val = I915_READ(DVSCNTR(pipe));
1386 I915_STATE_WARN(val & DVS_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(pipe), pipe_name(pipe));
1389 }
1390 }
1391
1392 static void assert_vblank_disabled(struct drm_crtc *crtc)
1393 {
1394 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1395 drm_crtc_vblank_put(crtc);
1396 }
1397
1398 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400 {
1401 u32 val;
1402 bool enabled;
1403
1404 val = I915_READ(PCH_TRANSCONF(pipe));
1405 enabled = !!(val & TRANS_ENABLE);
1406 I915_STATE_WARN(enabled,
1407 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1408 pipe_name(pipe));
1409 }
1410
1411 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 port_sel, u32 val)
1413 {
1414 if ((val & DP_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420 return false;
1421 } else if (IS_CHERRYVIEW(dev_priv)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423 return false;
1424 } else {
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426 return false;
1427 }
1428 return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433 {
1434 if ((val & SDVO_ENABLE) == 0)
1435 return false;
1436
1437 if (HAS_PCH_CPT(dev_priv)) {
1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439 return false;
1440 } else if (IS_CHERRYVIEW(dev_priv)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442 return false;
1443 } else {
1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445 return false;
1446 }
1447 return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1452 {
1453 if ((val & LVDS_PORT_EN) == 0)
1454 return false;
1455
1456 if (HAS_PCH_CPT(dev_priv)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461 return false;
1462 }
1463 return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1468 {
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1470 return false;
1471 if (HAS_PCH_CPT(dev_priv)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473 return false;
1474 } else {
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476 return false;
1477 }
1478 return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, i915_reg_t reg,
1483 u32 port_sel)
1484 {
1485 u32 val = I915_READ(reg);
1486 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1487 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1488 i915_mmio_reg_offset(reg), pipe_name(pipe));
1489
1490 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1491 && (val & DP_PIPEB_SELECT),
1492 "IBX PCH dp port still using transcoder B\n");
1493 }
1494
1495 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, i915_reg_t reg)
1497 {
1498 u32 val = I915_READ(reg);
1499 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1500 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1501 i915_mmio_reg_offset(reg), pipe_name(pipe));
1502
1503 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1504 && (val & SDVO_PIPE_B_SELECT),
1505 "IBX PCH hdmi port still using transcoder B\n");
1506 }
1507
1508 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe)
1510 {
1511 u32 val;
1512
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517 val = I915_READ(PCH_ADPA);
1518 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1519 "PCH VGA enabled on transcoder %c, should be disabled\n",
1520 pipe_name(pipe));
1521
1522 val = I915_READ(PCH_LVDS);
1523 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1524 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1525 pipe_name(pipe));
1526
1527 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1528 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1530 }
1531
1532 static void _vlv_enable_pll(struct intel_crtc *crtc,
1533 const struct intel_crtc_state *pipe_config)
1534 {
1535 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536 enum pipe pipe = crtc->pipe;
1537
1538 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1539 POSTING_READ(DPLL(pipe));
1540 udelay(150);
1541
1542 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1543 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1544 }
1545
1546 static void vlv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_state *pipe_config)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 enum pipe pipe = crtc->pipe;
1551
1552 assert_pipe_disabled(dev_priv, pipe);
1553
1554 /* PLL is protected by panel, make sure we can write it */
1555 assert_panel_unlocked(dev_priv, pipe);
1556
1557 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1558 _vlv_enable_pll(crtc, pipe_config);
1559
1560 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1561 POSTING_READ(DPLL_MD(pipe));
1562 }
1563
1564
1565 static void _chv_enable_pll(struct intel_crtc *crtc,
1566 const struct intel_crtc_state *pipe_config)
1567 {
1568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1569 enum pipe pipe = crtc->pipe;
1570 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1571 u32 tmp;
1572
1573 mutex_lock(&dev_priv->sb_lock);
1574
1575 /* Enable back the 10bit clock to display controller */
1576 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1577 tmp |= DPIO_DCLKP_EN;
1578 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1579
1580 mutex_unlock(&dev_priv->sb_lock);
1581
1582 /*
1583 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1584 */
1585 udelay(1);
1586
1587 /* Enable PLL */
1588 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1589
1590 /* Check PLL is locked */
1591 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1592 DRM_ERROR("PLL %d failed to lock\n", pipe);
1593 }
1594
1595 static void chv_enable_pll(struct intel_crtc *crtc,
1596 const struct intel_crtc_state *pipe_config)
1597 {
1598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1599 enum pipe pipe = crtc->pipe;
1600
1601 assert_pipe_disabled(dev_priv, pipe);
1602
1603 /* PLL is protected by panel, make sure we can write it */
1604 assert_panel_unlocked(dev_priv, pipe);
1605
1606 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1607 _chv_enable_pll(crtc, pipe_config);
1608
1609 if (pipe != PIPE_A) {
1610 /*
1611 * WaPixelRepeatModeFixForC0:chv
1612 *
1613 * DPLLCMD is AWOL. Use chicken bits to propagate
1614 * the value from DPLLBMD to either pipe B or C.
1615 */
1616 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1617 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1618 I915_WRITE(CBR4_VLV, 0);
1619 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1620
1621 /*
1622 * DPLLB VGA mode also seems to cause problems.
1623 * We should always have it disabled.
1624 */
1625 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1626 } else {
1627 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1628 POSTING_READ(DPLL_MD(pipe));
1629 }
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634 struct intel_crtc *crtc;
1635 int count = 0;
1636
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->base.state->active &&
1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641 return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 i915_reg_t reg = DPLL(crtc->pipe);
1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651 assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653 /* PLL is protected by panel, make sure we can write it */
1654 if (IS_MOBILE(dev) && !IS_I830(dev))
1655 assert_panel_unlocked(dev_priv, crtc->pipe);
1656
1657 /* Enable DVO 2x clock on both PLLs if necessary */
1658 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1659 /*
1660 * It appears to be important that we don't enable this
1661 * for the current pipe before otherwise configuring the
1662 * PLL. No idea how this should be handled if multiple
1663 * DVO outputs are enabled simultaneosly.
1664 */
1665 dpll |= DPLL_DVO_2X_MODE;
1666 I915_WRITE(DPLL(!crtc->pipe),
1667 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1668 }
1669
1670 /*
1671 * Apparently we need to have VGA mode enabled prior to changing
1672 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1673 * dividers, even though the register value does change.
1674 */
1675 I915_WRITE(reg, 0);
1676
1677 I915_WRITE(reg, dpll);
1678
1679 /* Wait for the clocks to stabilize. */
1680 POSTING_READ(reg);
1681 udelay(150);
1682
1683 if (INTEL_INFO(dev)->gen >= 4) {
1684 I915_WRITE(DPLL_MD(crtc->pipe),
1685 crtc->config->dpll_hw_state.dpll_md);
1686 } else {
1687 /* The pixel multiplier can only be updated once the
1688 * DPLL is enabled and the clocks are stable.
1689 *
1690 * So write it again.
1691 */
1692 I915_WRITE(reg, dpll);
1693 }
1694
1695 /* We do this three times for luck */
1696 I915_WRITE(reg, dpll);
1697 POSTING_READ(reg);
1698 udelay(150); /* wait for warmup */
1699 I915_WRITE(reg, dpll);
1700 POSTING_READ(reg);
1701 udelay(150); /* wait for warmup */
1702 I915_WRITE(reg, dpll);
1703 POSTING_READ(reg);
1704 udelay(150); /* wait for warmup */
1705 }
1706
1707 /**
1708 * i9xx_disable_pll - disable a PLL
1709 * @dev_priv: i915 private structure
1710 * @pipe: pipe PLL to disable
1711 *
1712 * Disable the PLL for @pipe, making sure the pipe is off first.
1713 *
1714 * Note! This is for pre-ILK only.
1715 */
1716 static void i9xx_disable_pll(struct intel_crtc *crtc)
1717 {
1718 struct drm_device *dev = crtc->base.dev;
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720 enum pipe pipe = crtc->pipe;
1721
1722 /* Disable DVO 2x clock on both PLLs if necessary */
1723 if (IS_I830(dev) &&
1724 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1725 !intel_num_dvo_pipes(dev)) {
1726 I915_WRITE(DPLL(PIPE_B),
1727 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1728 I915_WRITE(DPLL(PIPE_A),
1729 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1730 }
1731
1732 /* Don't disable pipe or pipe PLLs if needed */
1733 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1734 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1735 return;
1736
1737 /* Make sure the pipe isn't still relying on us */
1738 assert_pipe_disabled(dev_priv, pipe);
1739
1740 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1741 POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746 u32 val;
1747
1748 /* Make sure the pipe isn't still relying on us */
1749 assert_pipe_disabled(dev_priv, pipe);
1750
1751 val = DPLL_INTEGRATED_REF_CLK_VLV |
1752 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1753 if (pipe != PIPE_A)
1754 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1755
1756 I915_WRITE(DPLL(pipe), val);
1757 POSTING_READ(DPLL(pipe));
1758 }
1759
1760 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1761 {
1762 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1763 u32 val;
1764
1765 /* Make sure the pipe isn't still relying on us */
1766 assert_pipe_disabled(dev_priv, pipe);
1767
1768 val = DPLL_SSC_REF_CLK_CHV |
1769 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1770 if (pipe != PIPE_A)
1771 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1772
1773 I915_WRITE(DPLL(pipe), val);
1774 POSTING_READ(DPLL(pipe));
1775
1776 mutex_lock(&dev_priv->sb_lock);
1777
1778 /* Disable 10bit clock to display controller */
1779 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1780 val &= ~DPIO_DCLKP_EN;
1781 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1782
1783 mutex_unlock(&dev_priv->sb_lock);
1784 }
1785
1786 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1787 struct intel_digital_port *dport,
1788 unsigned int expected_mask)
1789 {
1790 u32 port_mask;
1791 i915_reg_t dpll_reg;
1792
1793 switch (dport->port) {
1794 case PORT_B:
1795 port_mask = DPLL_PORTB_READY_MASK;
1796 dpll_reg = DPLL(0);
1797 break;
1798 case PORT_C:
1799 port_mask = DPLL_PORTC_READY_MASK;
1800 dpll_reg = DPLL(0);
1801 expected_mask <<= 4;
1802 break;
1803 case PORT_D:
1804 port_mask = DPLL_PORTD_READY_MASK;
1805 dpll_reg = DPIO_PHY_STATUS;
1806 break;
1807 default:
1808 BUG();
1809 }
1810
1811 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1812 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1813 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1814 }
1815
1816 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1817 enum pipe pipe)
1818 {
1819 struct drm_device *dev = dev_priv->dev;
1820 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1822 i915_reg_t reg;
1823 uint32_t val, pipeconf_val;
1824
1825 /* Make sure PCH DPLL is enabled */
1826 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1827
1828 /* FDI must be feeding us bits for PCH ports */
1829 assert_fdi_tx_enabled(dev_priv, pipe);
1830 assert_fdi_rx_enabled(dev_priv, pipe);
1831
1832 if (HAS_PCH_CPT(dev)) {
1833 /* Workaround: Set the timing override bit before enabling the
1834 * pch transcoder. */
1835 reg = TRANS_CHICKEN2(pipe);
1836 val = I915_READ(reg);
1837 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1838 I915_WRITE(reg, val);
1839 }
1840
1841 reg = PCH_TRANSCONF(pipe);
1842 val = I915_READ(reg);
1843 pipeconf_val = I915_READ(PIPECONF(pipe));
1844
1845 if (HAS_PCH_IBX(dev_priv)) {
1846 /*
1847 * Make the BPC in transcoder be consistent with
1848 * that in pipeconf reg. For HDMI we must use 8bpc
1849 * here for both 8bpc and 12bpc.
1850 */
1851 val &= ~PIPECONF_BPC_MASK;
1852 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1853 val |= PIPECONF_8BPC;
1854 else
1855 val |= pipeconf_val & PIPECONF_BPC_MASK;
1856 }
1857
1858 val &= ~TRANS_INTERLACE_MASK;
1859 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1860 if (HAS_PCH_IBX(dev_priv) &&
1861 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1862 val |= TRANS_LEGACY_INTERLACED_ILK;
1863 else
1864 val |= TRANS_INTERLACED;
1865 else
1866 val |= TRANS_PROGRESSIVE;
1867
1868 I915_WRITE(reg, val | TRANS_ENABLE);
1869 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1870 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1871 }
1872
1873 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1874 enum transcoder cpu_transcoder)
1875 {
1876 u32 val, pipeconf_val;
1877
1878 /* FDI must be feeding us bits for PCH ports */
1879 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1880 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1881
1882 /* Workaround: set timing override bit. */
1883 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1884 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1885 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1886
1887 val = TRANS_ENABLE;
1888 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1889
1890 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1891 PIPECONF_INTERLACED_ILK)
1892 val |= TRANS_INTERLACED;
1893 else
1894 val |= TRANS_PROGRESSIVE;
1895
1896 I915_WRITE(LPT_TRANSCONF, val);
1897 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1898 DRM_ERROR("Failed to enable PCH transcoder\n");
1899 }
1900
1901 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1902 enum pipe pipe)
1903 {
1904 struct drm_device *dev = dev_priv->dev;
1905 i915_reg_t reg;
1906 uint32_t val;
1907
1908 /* FDI relies on the transcoder */
1909 assert_fdi_tx_disabled(dev_priv, pipe);
1910 assert_fdi_rx_disabled(dev_priv, pipe);
1911
1912 /* Ports must be off as well */
1913 assert_pch_ports_disabled(dev_priv, pipe);
1914
1915 reg = PCH_TRANSCONF(pipe);
1916 val = I915_READ(reg);
1917 val &= ~TRANS_ENABLE;
1918 I915_WRITE(reg, val);
1919 /* wait for PCH transcoder off, transcoder state */
1920 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1921 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1922
1923 if (HAS_PCH_CPT(dev)) {
1924 /* Workaround: Clear the timing override chicken bit again. */
1925 reg = TRANS_CHICKEN2(pipe);
1926 val = I915_READ(reg);
1927 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1928 I915_WRITE(reg, val);
1929 }
1930 }
1931
1932 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1933 {
1934 u32 val;
1935
1936 val = I915_READ(LPT_TRANSCONF);
1937 val &= ~TRANS_ENABLE;
1938 I915_WRITE(LPT_TRANSCONF, val);
1939 /* wait for PCH transcoder off, transcoder state */
1940 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1941 DRM_ERROR("Failed to disable PCH transcoder\n");
1942
1943 /* Workaround: clear timing override bit. */
1944 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1945 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1946 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1947 }
1948
1949 /**
1950 * intel_enable_pipe - enable a pipe, asserting requirements
1951 * @crtc: crtc responsible for the pipe
1952 *
1953 * Enable @crtc's pipe, making sure that various hardware specific requirements
1954 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1955 */
1956 static void intel_enable_pipe(struct intel_crtc *crtc)
1957 {
1958 struct drm_device *dev = crtc->base.dev;
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 enum pipe pipe = crtc->pipe;
1961 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1962 enum pipe pch_transcoder;
1963 i915_reg_t reg;
1964 u32 val;
1965
1966 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1967
1968 assert_planes_disabled(dev_priv, pipe);
1969 assert_cursor_disabled(dev_priv, pipe);
1970 assert_sprites_disabled(dev_priv, pipe);
1971
1972 if (HAS_PCH_LPT(dev_priv))
1973 pch_transcoder = TRANSCODER_A;
1974 else
1975 pch_transcoder = pipe;
1976
1977 /*
1978 * A pipe without a PLL won't actually be able to drive bits from
1979 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1980 * need the check.
1981 */
1982 if (HAS_GMCH_DISPLAY(dev_priv))
1983 if (crtc->config->has_dsi_encoder)
1984 assert_dsi_pll_enabled(dev_priv);
1985 else
1986 assert_pll_enabled(dev_priv, pipe);
1987 else {
1988 if (crtc->config->has_pch_encoder) {
1989 /* if driving the PCH, we need FDI enabled */
1990 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1991 assert_fdi_tx_pll_enabled(dev_priv,
1992 (enum pipe) cpu_transcoder);
1993 }
1994 /* FIXME: assert CPU port conditions for SNB+ */
1995 }
1996
1997 reg = PIPECONF(cpu_transcoder);
1998 val = I915_READ(reg);
1999 if (val & PIPECONF_ENABLE) {
2000 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2001 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2002 return;
2003 }
2004
2005 I915_WRITE(reg, val | PIPECONF_ENABLE);
2006 POSTING_READ(reg);
2007
2008 /*
2009 * Until the pipe starts DSL will read as 0, which would cause
2010 * an apparent vblank timestamp jump, which messes up also the
2011 * frame count when it's derived from the timestamps. So let's
2012 * wait for the pipe to start properly before we call
2013 * drm_crtc_vblank_on()
2014 */
2015 if (dev->max_vblank_count == 0 &&
2016 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2017 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2018 }
2019
2020 /**
2021 * intel_disable_pipe - disable a pipe, asserting requirements
2022 * @crtc: crtc whose pipes is to be disabled
2023 *
2024 * Disable the pipe of @crtc, making sure that various hardware
2025 * specific requirements are met, if applicable, e.g. plane
2026 * disabled, panel fitter off, etc.
2027 *
2028 * Will wait until the pipe has shut down before returning.
2029 */
2030 static void intel_disable_pipe(struct intel_crtc *crtc)
2031 {
2032 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2033 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2034 enum pipe pipe = crtc->pipe;
2035 i915_reg_t reg;
2036 u32 val;
2037
2038 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2039
2040 /*
2041 * Make sure planes won't keep trying to pump pixels to us,
2042 * or we might hang the display.
2043 */
2044 assert_planes_disabled(dev_priv, pipe);
2045 assert_cursor_disabled(dev_priv, pipe);
2046 assert_sprites_disabled(dev_priv, pipe);
2047
2048 reg = PIPECONF(cpu_transcoder);
2049 val = I915_READ(reg);
2050 if ((val & PIPECONF_ENABLE) == 0)
2051 return;
2052
2053 /*
2054 * Double wide has implications for planes
2055 * so best keep it disabled when not needed.
2056 */
2057 if (crtc->config->double_wide)
2058 val &= ~PIPECONF_DOUBLE_WIDE;
2059
2060 /* Don't disable pipe or pipe PLLs if needed */
2061 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2062 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2063 val &= ~PIPECONF_ENABLE;
2064
2065 I915_WRITE(reg, val);
2066 if ((val & PIPECONF_ENABLE) == 0)
2067 intel_wait_for_pipe_off(crtc);
2068 }
2069
2070 static bool need_vtd_wa(struct drm_device *dev)
2071 {
2072 #ifdef CONFIG_INTEL_IOMMU
2073 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2074 return true;
2075 #endif
2076 return false;
2077 }
2078
2079 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2080 {
2081 return IS_GEN2(dev_priv) ? 2048 : 4096;
2082 }
2083
2084 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2085 uint64_t fb_modifier, unsigned int cpp)
2086 {
2087 switch (fb_modifier) {
2088 case DRM_FORMAT_MOD_NONE:
2089 return cpp;
2090 case I915_FORMAT_MOD_X_TILED:
2091 if (IS_GEN2(dev_priv))
2092 return 128;
2093 else
2094 return 512;
2095 case I915_FORMAT_MOD_Y_TILED:
2096 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2097 return 128;
2098 else
2099 return 512;
2100 case I915_FORMAT_MOD_Yf_TILED:
2101 switch (cpp) {
2102 case 1:
2103 return 64;
2104 case 2:
2105 case 4:
2106 return 128;
2107 case 8:
2108 case 16:
2109 return 256;
2110 default:
2111 MISSING_CASE(cpp);
2112 return cpp;
2113 }
2114 break;
2115 default:
2116 MISSING_CASE(fb_modifier);
2117 return cpp;
2118 }
2119 }
2120
2121 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2122 uint64_t fb_modifier, unsigned int cpp)
2123 {
2124 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2125 return 1;
2126 else
2127 return intel_tile_size(dev_priv) /
2128 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2129 }
2130
2131 /* Return the tile dimensions in pixel units */
2132 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2133 unsigned int *tile_width,
2134 unsigned int *tile_height,
2135 uint64_t fb_modifier,
2136 unsigned int cpp)
2137 {
2138 unsigned int tile_width_bytes =
2139 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2140
2141 *tile_width = tile_width_bytes / cpp;
2142 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2143 }
2144
2145 unsigned int
2146 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2147 uint32_t pixel_format, uint64_t fb_modifier)
2148 {
2149 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2150 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2151
2152 return ALIGN(height, tile_height);
2153 }
2154
2155 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2156 {
2157 unsigned int size = 0;
2158 int i;
2159
2160 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2161 size += rot_info->plane[i].width * rot_info->plane[i].height;
2162
2163 return size;
2164 }
2165
2166 static void
2167 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2168 const struct drm_framebuffer *fb,
2169 unsigned int rotation)
2170 {
2171 if (intel_rotation_90_or_270(rotation)) {
2172 *view = i915_ggtt_view_rotated;
2173 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2174 } else {
2175 *view = i915_ggtt_view_normal;
2176 }
2177 }
2178
2179 static void
2180 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2181 struct drm_framebuffer *fb)
2182 {
2183 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2184 unsigned int tile_size, tile_width, tile_height, cpp;
2185
2186 tile_size = intel_tile_size(dev_priv);
2187
2188 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2189 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2190 fb->modifier[0], cpp);
2191
2192 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2193 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2194
2195 if (info->pixel_format == DRM_FORMAT_NV12) {
2196 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2197 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2198 fb->modifier[1], cpp);
2199
2200 info->uv_offset = fb->offsets[1];
2201 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2202 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2203 }
2204 }
2205
2206 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2207 {
2208 if (INTEL_INFO(dev_priv)->gen >= 9)
2209 return 256 * 1024;
2210 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2211 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2212 return 128 * 1024;
2213 else if (INTEL_INFO(dev_priv)->gen >= 4)
2214 return 4 * 1024;
2215 else
2216 return 0;
2217 }
2218
2219 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2220 uint64_t fb_modifier)
2221 {
2222 switch (fb_modifier) {
2223 case DRM_FORMAT_MOD_NONE:
2224 return intel_linear_alignment(dev_priv);
2225 case I915_FORMAT_MOD_X_TILED:
2226 if (INTEL_INFO(dev_priv)->gen >= 9)
2227 return 256 * 1024;
2228 return 0;
2229 case I915_FORMAT_MOD_Y_TILED:
2230 case I915_FORMAT_MOD_Yf_TILED:
2231 return 1 * 1024 * 1024;
2232 default:
2233 MISSING_CASE(fb_modifier);
2234 return 0;
2235 }
2236 }
2237
2238 int
2239 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2240 unsigned int rotation)
2241 {
2242 struct drm_device *dev = fb->dev;
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2245 struct i915_ggtt_view view;
2246 u32 alignment;
2247 int ret;
2248
2249 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2250
2251 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2252
2253 intel_fill_fb_ggtt_view(&view, fb, rotation);
2254
2255 /* Note that the w/a also requires 64 PTE of padding following the
2256 * bo. We currently fill all unused PTE with the shadow page and so
2257 * we should always have valid PTE following the scanout preventing
2258 * the VT-d warning.
2259 */
2260 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2261 alignment = 256 * 1024;
2262
2263 /*
2264 * Global gtt pte registers are special registers which actually forward
2265 * writes to a chunk of system memory. Which means that there is no risk
2266 * that the register values disappear as soon as we call
2267 * intel_runtime_pm_put(), so it is correct to wrap only the
2268 * pin/unpin/fence and not more.
2269 */
2270 intel_runtime_pm_get(dev_priv);
2271
2272 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2273 &view);
2274 if (ret)
2275 goto err_pm;
2276
2277 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2278 * fence, whereas 965+ only requires a fence if using
2279 * framebuffer compression. For simplicity, we always install
2280 * a fence as the cost is not that onerous.
2281 */
2282 if (view.type == I915_GGTT_VIEW_NORMAL) {
2283 ret = i915_gem_object_get_fence(obj);
2284 if (ret == -EDEADLK) {
2285 /*
2286 * -EDEADLK means there are no free fences
2287 * no pending flips.
2288 *
2289 * This is propagated to atomic, but it uses
2290 * -EDEADLK to force a locking recovery, so
2291 * change the returned error to -EBUSY.
2292 */
2293 ret = -EBUSY;
2294 goto err_unpin;
2295 } else if (ret)
2296 goto err_unpin;
2297
2298 i915_gem_object_pin_fence(obj);
2299 }
2300
2301 intel_runtime_pm_put(dev_priv);
2302 return 0;
2303
2304 err_unpin:
2305 i915_gem_object_unpin_from_display_plane(obj, &view);
2306 err_pm:
2307 intel_runtime_pm_put(dev_priv);
2308 return ret;
2309 }
2310
2311 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2312 {
2313 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2314 struct i915_ggtt_view view;
2315
2316 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2317
2318 intel_fill_fb_ggtt_view(&view, fb, rotation);
2319
2320 if (view.type == I915_GGTT_VIEW_NORMAL)
2321 i915_gem_object_unpin_fence(obj);
2322
2323 i915_gem_object_unpin_from_display_plane(obj, &view);
2324 }
2325
2326 /*
2327 * Adjust the tile offset by moving the difference into
2328 * the x/y offsets.
2329 *
2330 * Input tile dimensions and pitch must already be
2331 * rotated to match x and y, and in pixel units.
2332 */
2333 static u32 intel_adjust_tile_offset(int *x, int *y,
2334 unsigned int tile_width,
2335 unsigned int tile_height,
2336 unsigned int tile_size,
2337 unsigned int pitch_tiles,
2338 u32 old_offset,
2339 u32 new_offset)
2340 {
2341 unsigned int tiles;
2342
2343 WARN_ON(old_offset & (tile_size - 1));
2344 WARN_ON(new_offset & (tile_size - 1));
2345 WARN_ON(new_offset > old_offset);
2346
2347 tiles = (old_offset - new_offset) / tile_size;
2348
2349 *y += tiles / pitch_tiles * tile_height;
2350 *x += tiles % pitch_tiles * tile_width;
2351
2352 return new_offset;
2353 }
2354
2355 /*
2356 * Computes the linear offset to the base tile and adjusts
2357 * x, y. bytes per pixel is assumed to be a power-of-two.
2358 *
2359 * In the 90/270 rotated case, x and y are assumed
2360 * to be already rotated to match the rotated GTT view, and
2361 * pitch is the tile_height aligned framebuffer height.
2362 */
2363 u32 intel_compute_tile_offset(int *x, int *y,
2364 const struct drm_framebuffer *fb, int plane,
2365 unsigned int pitch,
2366 unsigned int rotation)
2367 {
2368 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2369 uint64_t fb_modifier = fb->modifier[plane];
2370 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2371 u32 offset, offset_aligned, alignment;
2372
2373 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2374 if (alignment)
2375 alignment--;
2376
2377 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2378 unsigned int tile_size, tile_width, tile_height;
2379 unsigned int tile_rows, tiles, pitch_tiles;
2380
2381 tile_size = intel_tile_size(dev_priv);
2382 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2383 fb_modifier, cpp);
2384
2385 if (intel_rotation_90_or_270(rotation)) {
2386 pitch_tiles = pitch / tile_height;
2387 swap(tile_width, tile_height);
2388 } else {
2389 pitch_tiles = pitch / (tile_width * cpp);
2390 }
2391
2392 tile_rows = *y / tile_height;
2393 *y %= tile_height;
2394
2395 tiles = *x / tile_width;
2396 *x %= tile_width;
2397
2398 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2399 offset_aligned = offset & ~alignment;
2400
2401 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2402 tile_size, pitch_tiles,
2403 offset, offset_aligned);
2404 } else {
2405 offset = *y * pitch + *x * cpp;
2406 offset_aligned = offset & ~alignment;
2407
2408 *y = (offset & alignment) / pitch;
2409 *x = ((offset & alignment) - *y * pitch) / cpp;
2410 }
2411
2412 return offset_aligned;
2413 }
2414
2415 static int i9xx_format_to_fourcc(int format)
2416 {
2417 switch (format) {
2418 case DISPPLANE_8BPP:
2419 return DRM_FORMAT_C8;
2420 case DISPPLANE_BGRX555:
2421 return DRM_FORMAT_XRGB1555;
2422 case DISPPLANE_BGRX565:
2423 return DRM_FORMAT_RGB565;
2424 default:
2425 case DISPPLANE_BGRX888:
2426 return DRM_FORMAT_XRGB8888;
2427 case DISPPLANE_RGBX888:
2428 return DRM_FORMAT_XBGR8888;
2429 case DISPPLANE_BGRX101010:
2430 return DRM_FORMAT_XRGB2101010;
2431 case DISPPLANE_RGBX101010:
2432 return DRM_FORMAT_XBGR2101010;
2433 }
2434 }
2435
2436 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2437 {
2438 switch (format) {
2439 case PLANE_CTL_FORMAT_RGB_565:
2440 return DRM_FORMAT_RGB565;
2441 default:
2442 case PLANE_CTL_FORMAT_XRGB_8888:
2443 if (rgb_order) {
2444 if (alpha)
2445 return DRM_FORMAT_ABGR8888;
2446 else
2447 return DRM_FORMAT_XBGR8888;
2448 } else {
2449 if (alpha)
2450 return DRM_FORMAT_ARGB8888;
2451 else
2452 return DRM_FORMAT_XRGB8888;
2453 }
2454 case PLANE_CTL_FORMAT_XRGB_2101010:
2455 if (rgb_order)
2456 return DRM_FORMAT_XBGR2101010;
2457 else
2458 return DRM_FORMAT_XRGB2101010;
2459 }
2460 }
2461
2462 static bool
2463 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2464 struct intel_initial_plane_config *plane_config)
2465 {
2466 struct drm_device *dev = crtc->base.dev;
2467 struct drm_i915_private *dev_priv = to_i915(dev);
2468 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2469 struct drm_i915_gem_object *obj = NULL;
2470 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2471 struct drm_framebuffer *fb = &plane_config->fb->base;
2472 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2473 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2474 PAGE_SIZE);
2475
2476 size_aligned -= base_aligned;
2477
2478 if (plane_config->size == 0)
2479 return false;
2480
2481 /* If the FB is too big, just don't use it since fbdev is not very
2482 * important and we should probably use that space with FBC or other
2483 * features. */
2484 if (size_aligned * 2 > ggtt->stolen_usable_size)
2485 return false;
2486
2487 mutex_lock(&dev->struct_mutex);
2488
2489 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2490 base_aligned,
2491 base_aligned,
2492 size_aligned);
2493 if (!obj) {
2494 mutex_unlock(&dev->struct_mutex);
2495 return false;
2496 }
2497
2498 obj->tiling_mode = plane_config->tiling;
2499 if (obj->tiling_mode == I915_TILING_X)
2500 obj->stride = fb->pitches[0];
2501
2502 mode_cmd.pixel_format = fb->pixel_format;
2503 mode_cmd.width = fb->width;
2504 mode_cmd.height = fb->height;
2505 mode_cmd.pitches[0] = fb->pitches[0];
2506 mode_cmd.modifier[0] = fb->modifier[0];
2507 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2508
2509 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2510 &mode_cmd, obj)) {
2511 DRM_DEBUG_KMS("intel fb init failed\n");
2512 goto out_unref_obj;
2513 }
2514
2515 mutex_unlock(&dev->struct_mutex);
2516
2517 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2518 return true;
2519
2520 out_unref_obj:
2521 drm_gem_object_unreference(&obj->base);
2522 mutex_unlock(&dev->struct_mutex);
2523 return false;
2524 }
2525
2526 static void
2527 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2528 struct intel_initial_plane_config *plane_config)
2529 {
2530 struct drm_device *dev = intel_crtc->base.dev;
2531 struct drm_i915_private *dev_priv = dev->dev_private;
2532 struct drm_crtc *c;
2533 struct intel_crtc *i;
2534 struct drm_i915_gem_object *obj;
2535 struct drm_plane *primary = intel_crtc->base.primary;
2536 struct drm_plane_state *plane_state = primary->state;
2537 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2538 struct intel_plane *intel_plane = to_intel_plane(primary);
2539 struct intel_plane_state *intel_state =
2540 to_intel_plane_state(plane_state);
2541 struct drm_framebuffer *fb;
2542
2543 if (!plane_config->fb)
2544 return;
2545
2546 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2547 fb = &plane_config->fb->base;
2548 goto valid_fb;
2549 }
2550
2551 kfree(plane_config->fb);
2552
2553 /*
2554 * Failed to alloc the obj, check to see if we should share
2555 * an fb with another CRTC instead
2556 */
2557 for_each_crtc(dev, c) {
2558 i = to_intel_crtc(c);
2559
2560 if (c == &intel_crtc->base)
2561 continue;
2562
2563 if (!i->active)
2564 continue;
2565
2566 fb = c->primary->fb;
2567 if (!fb)
2568 continue;
2569
2570 obj = intel_fb_obj(fb);
2571 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2572 drm_framebuffer_reference(fb);
2573 goto valid_fb;
2574 }
2575 }
2576
2577 /*
2578 * We've failed to reconstruct the BIOS FB. Current display state
2579 * indicates that the primary plane is visible, but has a NULL FB,
2580 * which will lead to problems later if we don't fix it up. The
2581 * simplest solution is to just disable the primary plane now and
2582 * pretend the BIOS never had it enabled.
2583 */
2584 to_intel_plane_state(plane_state)->visible = false;
2585 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2586 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2587 intel_plane->disable_plane(primary, &intel_crtc->base);
2588
2589 return;
2590
2591 valid_fb:
2592 plane_state->src_x = 0;
2593 plane_state->src_y = 0;
2594 plane_state->src_w = fb->width << 16;
2595 plane_state->src_h = fb->height << 16;
2596
2597 plane_state->crtc_x = 0;
2598 plane_state->crtc_y = 0;
2599 plane_state->crtc_w = fb->width;
2600 plane_state->crtc_h = fb->height;
2601
2602 intel_state->src.x1 = plane_state->src_x;
2603 intel_state->src.y1 = plane_state->src_y;
2604 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2605 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2606 intel_state->dst.x1 = plane_state->crtc_x;
2607 intel_state->dst.y1 = plane_state->crtc_y;
2608 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2609 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2610
2611 obj = intel_fb_obj(fb);
2612 if (obj->tiling_mode != I915_TILING_NONE)
2613 dev_priv->preserve_bios_swizzle = true;
2614
2615 drm_framebuffer_reference(fb);
2616 primary->fb = primary->state->fb = fb;
2617 primary->crtc = primary->state->crtc = &intel_crtc->base;
2618 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2619 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2620 }
2621
2622 static void i9xx_update_primary_plane(struct drm_plane *primary,
2623 const struct intel_crtc_state *crtc_state,
2624 const struct intel_plane_state *plane_state)
2625 {
2626 struct drm_device *dev = primary->dev;
2627 struct drm_i915_private *dev_priv = dev->dev_private;
2628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2629 struct drm_framebuffer *fb = plane_state->base.fb;
2630 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2631 int plane = intel_crtc->plane;
2632 u32 linear_offset;
2633 u32 dspcntr;
2634 i915_reg_t reg = DSPCNTR(plane);
2635 unsigned int rotation = plane_state->base.rotation;
2636 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2637 int x = plane_state->src.x1 >> 16;
2638 int y = plane_state->src.y1 >> 16;
2639
2640 dspcntr = DISPPLANE_GAMMA_ENABLE;
2641
2642 dspcntr |= DISPLAY_PLANE_ENABLE;
2643
2644 if (INTEL_INFO(dev)->gen < 4) {
2645 if (intel_crtc->pipe == PIPE_B)
2646 dspcntr |= DISPPLANE_SEL_PIPE_B;
2647
2648 /* pipesrc and dspsize control the size that is scaled from,
2649 * which should always be the user's requested size.
2650 */
2651 I915_WRITE(DSPSIZE(plane),
2652 ((crtc_state->pipe_src_h - 1) << 16) |
2653 (crtc_state->pipe_src_w - 1));
2654 I915_WRITE(DSPPOS(plane), 0);
2655 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2656 I915_WRITE(PRIMSIZE(plane),
2657 ((crtc_state->pipe_src_h - 1) << 16) |
2658 (crtc_state->pipe_src_w - 1));
2659 I915_WRITE(PRIMPOS(plane), 0);
2660 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2661 }
2662
2663 switch (fb->pixel_format) {
2664 case DRM_FORMAT_C8:
2665 dspcntr |= DISPPLANE_8BPP;
2666 break;
2667 case DRM_FORMAT_XRGB1555:
2668 dspcntr |= DISPPLANE_BGRX555;
2669 break;
2670 case DRM_FORMAT_RGB565:
2671 dspcntr |= DISPPLANE_BGRX565;
2672 break;
2673 case DRM_FORMAT_XRGB8888:
2674 dspcntr |= DISPPLANE_BGRX888;
2675 break;
2676 case DRM_FORMAT_XBGR8888:
2677 dspcntr |= DISPPLANE_RGBX888;
2678 break;
2679 case DRM_FORMAT_XRGB2101010:
2680 dspcntr |= DISPPLANE_BGRX101010;
2681 break;
2682 case DRM_FORMAT_XBGR2101010:
2683 dspcntr |= DISPPLANE_RGBX101010;
2684 break;
2685 default:
2686 BUG();
2687 }
2688
2689 if (INTEL_INFO(dev)->gen >= 4 &&
2690 obj->tiling_mode != I915_TILING_NONE)
2691 dspcntr |= DISPPLANE_TILED;
2692
2693 if (IS_G4X(dev))
2694 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2695
2696 linear_offset = y * fb->pitches[0] + x * cpp;
2697
2698 if (INTEL_INFO(dev)->gen >= 4) {
2699 intel_crtc->dspaddr_offset =
2700 intel_compute_tile_offset(&x, &y, fb, 0,
2701 fb->pitches[0], rotation);
2702 linear_offset -= intel_crtc->dspaddr_offset;
2703 } else {
2704 intel_crtc->dspaddr_offset = linear_offset;
2705 }
2706
2707 if (rotation == BIT(DRM_ROTATE_180)) {
2708 dspcntr |= DISPPLANE_ROTATE_180;
2709
2710 x += (crtc_state->pipe_src_w - 1);
2711 y += (crtc_state->pipe_src_h - 1);
2712
2713 /* Finding the last pixel of the last line of the display
2714 data and adding to linear_offset*/
2715 linear_offset +=
2716 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2717 (crtc_state->pipe_src_w - 1) * cpp;
2718 }
2719
2720 intel_crtc->adjusted_x = x;
2721 intel_crtc->adjusted_y = y;
2722
2723 I915_WRITE(reg, dspcntr);
2724
2725 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2726 if (INTEL_INFO(dev)->gen >= 4) {
2727 I915_WRITE(DSPSURF(plane),
2728 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2729 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2730 I915_WRITE(DSPLINOFF(plane), linear_offset);
2731 } else
2732 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2733 POSTING_READ(reg);
2734 }
2735
2736 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2737 struct drm_crtc *crtc)
2738 {
2739 struct drm_device *dev = crtc->dev;
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742 int plane = intel_crtc->plane;
2743
2744 I915_WRITE(DSPCNTR(plane), 0);
2745 if (INTEL_INFO(dev_priv)->gen >= 4)
2746 I915_WRITE(DSPSURF(plane), 0);
2747 else
2748 I915_WRITE(DSPADDR(plane), 0);
2749 POSTING_READ(DSPCNTR(plane));
2750 }
2751
2752 static void ironlake_update_primary_plane(struct drm_plane *primary,
2753 const struct intel_crtc_state *crtc_state,
2754 const struct intel_plane_state *plane_state)
2755 {
2756 struct drm_device *dev = primary->dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2759 struct drm_framebuffer *fb = plane_state->base.fb;
2760 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2761 int plane = intel_crtc->plane;
2762 u32 linear_offset;
2763 u32 dspcntr;
2764 i915_reg_t reg = DSPCNTR(plane);
2765 unsigned int rotation = plane_state->base.rotation;
2766 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2767 int x = plane_state->src.x1 >> 16;
2768 int y = plane_state->src.y1 >> 16;
2769
2770 dspcntr = DISPPLANE_GAMMA_ENABLE;
2771 dspcntr |= DISPLAY_PLANE_ENABLE;
2772
2773 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2774 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2775
2776 switch (fb->pixel_format) {
2777 case DRM_FORMAT_C8:
2778 dspcntr |= DISPPLANE_8BPP;
2779 break;
2780 case DRM_FORMAT_RGB565:
2781 dspcntr |= DISPPLANE_BGRX565;
2782 break;
2783 case DRM_FORMAT_XRGB8888:
2784 dspcntr |= DISPPLANE_BGRX888;
2785 break;
2786 case DRM_FORMAT_XBGR8888:
2787 dspcntr |= DISPPLANE_RGBX888;
2788 break;
2789 case DRM_FORMAT_XRGB2101010:
2790 dspcntr |= DISPPLANE_BGRX101010;
2791 break;
2792 case DRM_FORMAT_XBGR2101010:
2793 dspcntr |= DISPPLANE_RGBX101010;
2794 break;
2795 default:
2796 BUG();
2797 }
2798
2799 if (obj->tiling_mode != I915_TILING_NONE)
2800 dspcntr |= DISPPLANE_TILED;
2801
2802 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2803 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2804
2805 linear_offset = y * fb->pitches[0] + x * cpp;
2806 intel_crtc->dspaddr_offset =
2807 intel_compute_tile_offset(&x, &y, fb, 0,
2808 fb->pitches[0], rotation);
2809 linear_offset -= intel_crtc->dspaddr_offset;
2810 if (rotation == BIT(DRM_ROTATE_180)) {
2811 dspcntr |= DISPPLANE_ROTATE_180;
2812
2813 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2814 x += (crtc_state->pipe_src_w - 1);
2815 y += (crtc_state->pipe_src_h - 1);
2816
2817 /* Finding the last pixel of the last line of the display
2818 data and adding to linear_offset*/
2819 linear_offset +=
2820 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2821 (crtc_state->pipe_src_w - 1) * cpp;
2822 }
2823 }
2824
2825 intel_crtc->adjusted_x = x;
2826 intel_crtc->adjusted_y = y;
2827
2828 I915_WRITE(reg, dspcntr);
2829
2830 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2831 I915_WRITE(DSPSURF(plane),
2832 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2833 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2834 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2835 } else {
2836 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2837 I915_WRITE(DSPLINOFF(plane), linear_offset);
2838 }
2839 POSTING_READ(reg);
2840 }
2841
2842 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2843 uint64_t fb_modifier, uint32_t pixel_format)
2844 {
2845 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2846 return 64;
2847 } else {
2848 int cpp = drm_format_plane_cpp(pixel_format, 0);
2849
2850 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2851 }
2852 }
2853
2854 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2855 struct drm_i915_gem_object *obj,
2856 unsigned int plane)
2857 {
2858 struct i915_ggtt_view view;
2859 struct i915_vma *vma;
2860 u64 offset;
2861
2862 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2863 intel_plane->base.state->rotation);
2864
2865 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2866 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2867 view.type))
2868 return -1;
2869
2870 offset = vma->node.start;
2871
2872 if (plane == 1) {
2873 offset += vma->ggtt_view.params.rotated.uv_start_page *
2874 PAGE_SIZE;
2875 }
2876
2877 WARN_ON(upper_32_bits(offset));
2878
2879 return lower_32_bits(offset);
2880 }
2881
2882 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2883 {
2884 struct drm_device *dev = intel_crtc->base.dev;
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886
2887 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2888 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2889 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2890 }
2891
2892 /*
2893 * This function detaches (aka. unbinds) unused scalers in hardware
2894 */
2895 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2896 {
2897 struct intel_crtc_scaler_state *scaler_state;
2898 int i;
2899
2900 scaler_state = &intel_crtc->config->scaler_state;
2901
2902 /* loop through and disable scalers that aren't in use */
2903 for (i = 0; i < intel_crtc->num_scalers; i++) {
2904 if (!scaler_state->scalers[i].in_use)
2905 skl_detach_scaler(intel_crtc, i);
2906 }
2907 }
2908
2909 u32 skl_plane_ctl_format(uint32_t pixel_format)
2910 {
2911 switch (pixel_format) {
2912 case DRM_FORMAT_C8:
2913 return PLANE_CTL_FORMAT_INDEXED;
2914 case DRM_FORMAT_RGB565:
2915 return PLANE_CTL_FORMAT_RGB_565;
2916 case DRM_FORMAT_XBGR8888:
2917 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2918 case DRM_FORMAT_XRGB8888:
2919 return PLANE_CTL_FORMAT_XRGB_8888;
2920 /*
2921 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2922 * to be already pre-multiplied. We need to add a knob (or a different
2923 * DRM_FORMAT) for user-space to configure that.
2924 */
2925 case DRM_FORMAT_ABGR8888:
2926 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2927 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2928 case DRM_FORMAT_ARGB8888:
2929 return PLANE_CTL_FORMAT_XRGB_8888 |
2930 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2931 case DRM_FORMAT_XRGB2101010:
2932 return PLANE_CTL_FORMAT_XRGB_2101010;
2933 case DRM_FORMAT_XBGR2101010:
2934 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2935 case DRM_FORMAT_YUYV:
2936 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2937 case DRM_FORMAT_YVYU:
2938 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2939 case DRM_FORMAT_UYVY:
2940 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2941 case DRM_FORMAT_VYUY:
2942 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2943 default:
2944 MISSING_CASE(pixel_format);
2945 }
2946
2947 return 0;
2948 }
2949
2950 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2951 {
2952 switch (fb_modifier) {
2953 case DRM_FORMAT_MOD_NONE:
2954 break;
2955 case I915_FORMAT_MOD_X_TILED:
2956 return PLANE_CTL_TILED_X;
2957 case I915_FORMAT_MOD_Y_TILED:
2958 return PLANE_CTL_TILED_Y;
2959 case I915_FORMAT_MOD_Yf_TILED:
2960 return PLANE_CTL_TILED_YF;
2961 default:
2962 MISSING_CASE(fb_modifier);
2963 }
2964
2965 return 0;
2966 }
2967
2968 u32 skl_plane_ctl_rotation(unsigned int rotation)
2969 {
2970 switch (rotation) {
2971 case BIT(DRM_ROTATE_0):
2972 break;
2973 /*
2974 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2975 * while i915 HW rotation is clockwise, thats why this swapping.
2976 */
2977 case BIT(DRM_ROTATE_90):
2978 return PLANE_CTL_ROTATE_270;
2979 case BIT(DRM_ROTATE_180):
2980 return PLANE_CTL_ROTATE_180;
2981 case BIT(DRM_ROTATE_270):
2982 return PLANE_CTL_ROTATE_90;
2983 default:
2984 MISSING_CASE(rotation);
2985 }
2986
2987 return 0;
2988 }
2989
2990 static void skylake_update_primary_plane(struct drm_plane *plane,
2991 const struct intel_crtc_state *crtc_state,
2992 const struct intel_plane_state *plane_state)
2993 {
2994 struct drm_device *dev = plane->dev;
2995 struct drm_i915_private *dev_priv = dev->dev_private;
2996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2997 struct drm_framebuffer *fb = plane_state->base.fb;
2998 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2999 int pipe = intel_crtc->pipe;
3000 u32 plane_ctl, stride_div, stride;
3001 u32 tile_height, plane_offset, plane_size;
3002 unsigned int rotation = plane_state->base.rotation;
3003 int x_offset, y_offset;
3004 u32 surf_addr;
3005 int scaler_id = plane_state->scaler_id;
3006 int src_x = plane_state->src.x1 >> 16;
3007 int src_y = plane_state->src.y1 >> 16;
3008 int src_w = drm_rect_width(&plane_state->src) >> 16;
3009 int src_h = drm_rect_height(&plane_state->src) >> 16;
3010 int dst_x = plane_state->dst.x1;
3011 int dst_y = plane_state->dst.y1;
3012 int dst_w = drm_rect_width(&plane_state->dst);
3013 int dst_h = drm_rect_height(&plane_state->dst);
3014
3015 plane_ctl = PLANE_CTL_ENABLE |
3016 PLANE_CTL_PIPE_GAMMA_ENABLE |
3017 PLANE_CTL_PIPE_CSC_ENABLE;
3018
3019 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3020 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3021 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3022 plane_ctl |= skl_plane_ctl_rotation(rotation);
3023
3024 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3025 fb->pixel_format);
3026 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3027
3028 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3029
3030 if (intel_rotation_90_or_270(rotation)) {
3031 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3032
3033 /* stride = Surface height in tiles */
3034 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3035 stride = DIV_ROUND_UP(fb->height, tile_height);
3036 x_offset = stride * tile_height - src_y - src_h;
3037 y_offset = src_x;
3038 plane_size = (src_w - 1) << 16 | (src_h - 1);
3039 } else {
3040 stride = fb->pitches[0] / stride_div;
3041 x_offset = src_x;
3042 y_offset = src_y;
3043 plane_size = (src_h - 1) << 16 | (src_w - 1);
3044 }
3045 plane_offset = y_offset << 16 | x_offset;
3046
3047 intel_crtc->adjusted_x = x_offset;
3048 intel_crtc->adjusted_y = y_offset;
3049
3050 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3051 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3052 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3053 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3054
3055 if (scaler_id >= 0) {
3056 uint32_t ps_ctrl = 0;
3057
3058 WARN_ON(!dst_w || !dst_h);
3059 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3060 crtc_state->scaler_state.scalers[scaler_id].mode;
3061 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3062 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3063 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3064 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3065 I915_WRITE(PLANE_POS(pipe, 0), 0);
3066 } else {
3067 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3068 }
3069
3070 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3071
3072 POSTING_READ(PLANE_SURF(pipe, 0));
3073 }
3074
3075 static void skylake_disable_primary_plane(struct drm_plane *primary,
3076 struct drm_crtc *crtc)
3077 {
3078 struct drm_device *dev = crtc->dev;
3079 struct drm_i915_private *dev_priv = dev->dev_private;
3080 int pipe = to_intel_crtc(crtc)->pipe;
3081
3082 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3083 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3084 POSTING_READ(PLANE_SURF(pipe, 0));
3085 }
3086
3087 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3088 static int
3089 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3090 int x, int y, enum mode_set_atomic state)
3091 {
3092 /* Support for kgdboc is disabled, this needs a major rework. */
3093 DRM_ERROR("legacy panic handler not supported any more.\n");
3094
3095 return -ENODEV;
3096 }
3097
3098 static void intel_update_primary_planes(struct drm_device *dev)
3099 {
3100 struct drm_crtc *crtc;
3101
3102 for_each_crtc(dev, crtc) {
3103 struct intel_plane *plane = to_intel_plane(crtc->primary);
3104 struct intel_plane_state *plane_state;
3105
3106 drm_modeset_lock_crtc(crtc, &plane->base);
3107 plane_state = to_intel_plane_state(plane->base.state);
3108
3109 if (plane_state->visible)
3110 plane->update_plane(&plane->base,
3111 to_intel_crtc_state(crtc->state),
3112 plane_state);
3113
3114 drm_modeset_unlock_crtc(crtc);
3115 }
3116 }
3117
3118 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3119 {
3120 /* no reset support for gen2 */
3121 if (IS_GEN2(dev_priv))
3122 return;
3123
3124 /* reset doesn't touch the display */
3125 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3126 return;
3127
3128 drm_modeset_lock_all(dev_priv->dev);
3129 /*
3130 * Disabling the crtcs gracefully seems nicer. Also the
3131 * g33 docs say we should at least disable all the planes.
3132 */
3133 intel_display_suspend(dev_priv->dev);
3134 }
3135
3136 void intel_finish_reset(struct drm_i915_private *dev_priv)
3137 {
3138 /* no reset support for gen2 */
3139 if (IS_GEN2(dev_priv))
3140 return;
3141
3142 /* reset doesn't touch the display */
3143 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3144 /*
3145 * Flips in the rings have been nuked by the reset,
3146 * so update the base address of all primary
3147 * planes to the the last fb to make sure we're
3148 * showing the correct fb after a reset.
3149 *
3150 * FIXME: Atomic will make this obsolete since we won't schedule
3151 * CS-based flips (which might get lost in gpu resets) any more.
3152 */
3153 intel_update_primary_planes(dev_priv->dev);
3154 return;
3155 }
3156
3157 /*
3158 * The display has been reset as well,
3159 * so need a full re-initialization.
3160 */
3161 intel_runtime_pm_disable_interrupts(dev_priv);
3162 intel_runtime_pm_enable_interrupts(dev_priv);
3163
3164 intel_modeset_init_hw(dev_priv->dev);
3165
3166 spin_lock_irq(&dev_priv->irq_lock);
3167 if (dev_priv->display.hpd_irq_setup)
3168 dev_priv->display.hpd_irq_setup(dev_priv);
3169 spin_unlock_irq(&dev_priv->irq_lock);
3170
3171 intel_display_resume(dev_priv->dev);
3172
3173 intel_hpd_init(dev_priv);
3174
3175 drm_modeset_unlock_all(dev_priv->dev);
3176 }
3177
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180 return !list_empty_careful(&to_intel_crtc(crtc)->flip_work);
3181 }
3182
3183 static void intel_update_pipe_config(struct intel_crtc *crtc,
3184 struct intel_crtc_state *old_crtc_state)
3185 {
3186 struct drm_device *dev = crtc->base.dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc_state *pipe_config =
3189 to_intel_crtc_state(crtc->base.state);
3190
3191 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3192 crtc->base.mode = crtc->base.state->mode;
3193
3194 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3195 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3196 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3197
3198 /*
3199 * Update pipe size and adjust fitter if needed: the reason for this is
3200 * that in compute_mode_changes we check the native mode (not the pfit
3201 * mode) to see if we can flip rather than do a full mode set. In the
3202 * fastboot case, we'll flip, but if we don't update the pipesrc and
3203 * pfit state, we'll end up with a big fb scanned out into the wrong
3204 * sized surface.
3205 */
3206
3207 I915_WRITE(PIPESRC(crtc->pipe),
3208 ((pipe_config->pipe_src_w - 1) << 16) |
3209 (pipe_config->pipe_src_h - 1));
3210
3211 /* on skylake this is done by detaching scalers */
3212 if (INTEL_INFO(dev)->gen >= 9) {
3213 skl_detach_scalers(crtc);
3214
3215 if (pipe_config->pch_pfit.enabled)
3216 skylake_pfit_enable(crtc);
3217 } else if (HAS_PCH_SPLIT(dev)) {
3218 if (pipe_config->pch_pfit.enabled)
3219 ironlake_pfit_enable(crtc);
3220 else if (old_crtc_state->pch_pfit.enabled)
3221 ironlake_pfit_disable(crtc, true);
3222 }
3223 }
3224
3225 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3226 {
3227 struct drm_device *dev = crtc->dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3230 int pipe = intel_crtc->pipe;
3231 i915_reg_t reg;
3232 u32 temp;
3233
3234 /* enable normal train */
3235 reg = FDI_TX_CTL(pipe);
3236 temp = I915_READ(reg);
3237 if (IS_IVYBRIDGE(dev)) {
3238 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3239 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3240 } else {
3241 temp &= ~FDI_LINK_TRAIN_NONE;
3242 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3243 }
3244 I915_WRITE(reg, temp);
3245
3246 reg = FDI_RX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 if (HAS_PCH_CPT(dev)) {
3249 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3250 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3251 } else {
3252 temp &= ~FDI_LINK_TRAIN_NONE;
3253 temp |= FDI_LINK_TRAIN_NONE;
3254 }
3255 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3256
3257 /* wait one idle pattern time */
3258 POSTING_READ(reg);
3259 udelay(1000);
3260
3261 /* IVB wants error correction enabled */
3262 if (IS_IVYBRIDGE(dev))
3263 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3264 FDI_FE_ERRC_ENABLE);
3265 }
3266
3267 /* The FDI link training functions for ILK/Ibexpeak. */
3268 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3269 {
3270 struct drm_device *dev = crtc->dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273 int pipe = intel_crtc->pipe;
3274 i915_reg_t reg;
3275 u32 temp, tries;
3276
3277 /* FDI needs bits from pipe first */
3278 assert_pipe_enabled(dev_priv, pipe);
3279
3280 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3281 for train result */
3282 reg = FDI_RX_IMR(pipe);
3283 temp = I915_READ(reg);
3284 temp &= ~FDI_RX_SYMBOL_LOCK;
3285 temp &= ~FDI_RX_BIT_LOCK;
3286 I915_WRITE(reg, temp);
3287 I915_READ(reg);
3288 udelay(150);
3289
3290 /* enable CPU FDI TX and PCH FDI RX */
3291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3294 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3295 temp &= ~FDI_LINK_TRAIN_NONE;
3296 temp |= FDI_LINK_TRAIN_PATTERN_1;
3297 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3298
3299 reg = FDI_RX_CTL(pipe);
3300 temp = I915_READ(reg);
3301 temp &= ~FDI_LINK_TRAIN_NONE;
3302 temp |= FDI_LINK_TRAIN_PATTERN_1;
3303 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3304
3305 POSTING_READ(reg);
3306 udelay(150);
3307
3308 /* Ironlake workaround, enable clock pointer after FDI enable*/
3309 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3310 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3311 FDI_RX_PHASE_SYNC_POINTER_EN);
3312
3313 reg = FDI_RX_IIR(pipe);
3314 for (tries = 0; tries < 5; tries++) {
3315 temp = I915_READ(reg);
3316 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3317
3318 if ((temp & FDI_RX_BIT_LOCK)) {
3319 DRM_DEBUG_KMS("FDI train 1 done.\n");
3320 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3321 break;
3322 }
3323 }
3324 if (tries == 5)
3325 DRM_ERROR("FDI train 1 fail!\n");
3326
3327 /* Train 2 */
3328 reg = FDI_TX_CTL(pipe);
3329 temp = I915_READ(reg);
3330 temp &= ~FDI_LINK_TRAIN_NONE;
3331 temp |= FDI_LINK_TRAIN_PATTERN_2;
3332 I915_WRITE(reg, temp);
3333
3334 reg = FDI_RX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_PATTERN_2;
3338 I915_WRITE(reg, temp);
3339
3340 POSTING_READ(reg);
3341 udelay(150);
3342
3343 reg = FDI_RX_IIR(pipe);
3344 for (tries = 0; tries < 5; tries++) {
3345 temp = I915_READ(reg);
3346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3347
3348 if (temp & FDI_RX_SYMBOL_LOCK) {
3349 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3350 DRM_DEBUG_KMS("FDI train 2 done.\n");
3351 break;
3352 }
3353 }
3354 if (tries == 5)
3355 DRM_ERROR("FDI train 2 fail!\n");
3356
3357 DRM_DEBUG_KMS("FDI train done\n");
3358
3359 }
3360
3361 static const int snb_b_fdi_train_param[] = {
3362 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3363 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3364 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3365 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3366 };
3367
3368 /* The FDI link training functions for SNB/Cougarpoint. */
3369 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3370 {
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374 int pipe = intel_crtc->pipe;
3375 i915_reg_t reg;
3376 u32 temp, i, retry;
3377
3378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3379 for train result */
3380 reg = FDI_RX_IMR(pipe);
3381 temp = I915_READ(reg);
3382 temp &= ~FDI_RX_SYMBOL_LOCK;
3383 temp &= ~FDI_RX_BIT_LOCK;
3384 I915_WRITE(reg, temp);
3385
3386 POSTING_READ(reg);
3387 udelay(150);
3388
3389 /* enable CPU FDI TX and PCH FDI RX */
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3393 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3394 temp &= ~FDI_LINK_TRAIN_NONE;
3395 temp |= FDI_LINK_TRAIN_PATTERN_1;
3396 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3397 /* SNB-B */
3398 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3399 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3400
3401 I915_WRITE(FDI_RX_MISC(pipe),
3402 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3403
3404 reg = FDI_RX_CTL(pipe);
3405 temp = I915_READ(reg);
3406 if (HAS_PCH_CPT(dev)) {
3407 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3408 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3409 } else {
3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
3412 }
3413 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3414
3415 POSTING_READ(reg);
3416 udelay(150);
3417
3418 for (i = 0; i < 4; i++) {
3419 reg = FDI_TX_CTL(pipe);
3420 temp = I915_READ(reg);
3421 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3422 temp |= snb_b_fdi_train_param[i];
3423 I915_WRITE(reg, temp);
3424
3425 POSTING_READ(reg);
3426 udelay(500);
3427
3428 for (retry = 0; retry < 5; retry++) {
3429 reg = FDI_RX_IIR(pipe);
3430 temp = I915_READ(reg);
3431 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3432 if (temp & FDI_RX_BIT_LOCK) {
3433 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3434 DRM_DEBUG_KMS("FDI train 1 done.\n");
3435 break;
3436 }
3437 udelay(50);
3438 }
3439 if (retry < 5)
3440 break;
3441 }
3442 if (i == 4)
3443 DRM_ERROR("FDI train 1 fail!\n");
3444
3445 /* Train 2 */
3446 reg = FDI_TX_CTL(pipe);
3447 temp = I915_READ(reg);
3448 temp &= ~FDI_LINK_TRAIN_NONE;
3449 temp |= FDI_LINK_TRAIN_PATTERN_2;
3450 if (IS_GEN6(dev)) {
3451 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3452 /* SNB-B */
3453 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3454 }
3455 I915_WRITE(reg, temp);
3456
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 if (HAS_PCH_CPT(dev)) {
3460 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3461 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3462 } else {
3463 temp &= ~FDI_LINK_TRAIN_NONE;
3464 temp |= FDI_LINK_TRAIN_PATTERN_2;
3465 }
3466 I915_WRITE(reg, temp);
3467
3468 POSTING_READ(reg);
3469 udelay(150);
3470
3471 for (i = 0; i < 4; i++) {
3472 reg = FDI_TX_CTL(pipe);
3473 temp = I915_READ(reg);
3474 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3475 temp |= snb_b_fdi_train_param[i];
3476 I915_WRITE(reg, temp);
3477
3478 POSTING_READ(reg);
3479 udelay(500);
3480
3481 for (retry = 0; retry < 5; retry++) {
3482 reg = FDI_RX_IIR(pipe);
3483 temp = I915_READ(reg);
3484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
3490 udelay(50);
3491 }
3492 if (retry < 5)
3493 break;
3494 }
3495 if (i == 4)
3496 DRM_ERROR("FDI train 2 fail!\n");
3497
3498 DRM_DEBUG_KMS("FDI train done.\n");
3499 }
3500
3501 /* Manual link training for Ivy Bridge A0 parts */
3502 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3503 {
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507 int pipe = intel_crtc->pipe;
3508 i915_reg_t reg;
3509 u32 temp, i, j;
3510
3511 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3512 for train result */
3513 reg = FDI_RX_IMR(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_RX_SYMBOL_LOCK;
3516 temp &= ~FDI_RX_BIT_LOCK;
3517 I915_WRITE(reg, temp);
3518
3519 POSTING_READ(reg);
3520 udelay(150);
3521
3522 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3523 I915_READ(FDI_RX_IIR(pipe)));
3524
3525 /* Try each vswing and preemphasis setting twice before moving on */
3526 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3527 /* disable first in case we need to retry */
3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3531 temp &= ~FDI_TX_ENABLE;
3532 I915_WRITE(reg, temp);
3533
3534 reg = FDI_RX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~FDI_LINK_TRAIN_AUTO;
3537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3538 temp &= ~FDI_RX_ENABLE;
3539 I915_WRITE(reg, temp);
3540
3541 /* enable CPU FDI TX and PCH FDI RX */
3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3545 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3546 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548 temp |= snb_b_fdi_train_param[j/2];
3549 temp |= FDI_COMPOSITE_SYNC;
3550 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3551
3552 I915_WRITE(FDI_RX_MISC(pipe),
3553 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3554
3555 reg = FDI_RX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3558 temp |= FDI_COMPOSITE_SYNC;
3559 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3560
3561 POSTING_READ(reg);
3562 udelay(1); /* should be 0.5us */
3563
3564 for (i = 0; i < 4; i++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568
3569 if (temp & FDI_RX_BIT_LOCK ||
3570 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3571 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3572 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3573 i);
3574 break;
3575 }
3576 udelay(1); /* should be 0.5us */
3577 }
3578 if (i == 4) {
3579 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3580 continue;
3581 }
3582
3583 /* Train 2 */
3584 reg = FDI_TX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3587 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3588 I915_WRITE(reg, temp);
3589
3590 reg = FDI_RX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3593 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
3597 udelay(2); /* should be 1.5us */
3598
3599 for (i = 0; i < 4; i++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603
3604 if (temp & FDI_RX_SYMBOL_LOCK ||
3605 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3606 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3607 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3608 i);
3609 goto train_done;
3610 }
3611 udelay(2); /* should be 1.5us */
3612 }
3613 if (i == 4)
3614 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3615 }
3616
3617 train_done:
3618 DRM_DEBUG_KMS("FDI train done.\n");
3619 }
3620
3621 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3622 {
3623 struct drm_device *dev = intel_crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 int pipe = intel_crtc->pipe;
3626 i915_reg_t reg;
3627 u32 temp;
3628
3629 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3630 reg = FDI_RX_CTL(pipe);
3631 temp = I915_READ(reg);
3632 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3633 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3634 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3635 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3636
3637 POSTING_READ(reg);
3638 udelay(200);
3639
3640 /* Switch from Rawclk to PCDclk */
3641 temp = I915_READ(reg);
3642 I915_WRITE(reg, temp | FDI_PCDCLK);
3643
3644 POSTING_READ(reg);
3645 udelay(200);
3646
3647 /* Enable CPU FDI TX PLL, always on for Ironlake */
3648 reg = FDI_TX_CTL(pipe);
3649 temp = I915_READ(reg);
3650 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3651 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3652
3653 POSTING_READ(reg);
3654 udelay(100);
3655 }
3656 }
3657
3658 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3659 {
3660 struct drm_device *dev = intel_crtc->base.dev;
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 int pipe = intel_crtc->pipe;
3663 i915_reg_t reg;
3664 u32 temp;
3665
3666 /* Switch from PCDclk to Rawclk */
3667 reg = FDI_RX_CTL(pipe);
3668 temp = I915_READ(reg);
3669 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3670
3671 /* Disable CPU FDI TX PLL */
3672 reg = FDI_TX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3675
3676 POSTING_READ(reg);
3677 udelay(100);
3678
3679 reg = FDI_RX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3682
3683 /* Wait for the clocks to turn off. */
3684 POSTING_READ(reg);
3685 udelay(100);
3686 }
3687
3688 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3689 {
3690 struct drm_device *dev = crtc->dev;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693 int pipe = intel_crtc->pipe;
3694 i915_reg_t reg;
3695 u32 temp;
3696
3697 /* disable CPU FDI tx and PCH FDI rx */
3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3701 POSTING_READ(reg);
3702
3703 reg = FDI_RX_CTL(pipe);
3704 temp = I915_READ(reg);
3705 temp &= ~(0x7 << 16);
3706 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3707 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3708
3709 POSTING_READ(reg);
3710 udelay(100);
3711
3712 /* Ironlake workaround, disable clock pointer after downing FDI */
3713 if (HAS_PCH_IBX(dev))
3714 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3715
3716 /* still set train pattern 1 */
3717 reg = FDI_TX_CTL(pipe);
3718 temp = I915_READ(reg);
3719 temp &= ~FDI_LINK_TRAIN_NONE;
3720 temp |= FDI_LINK_TRAIN_PATTERN_1;
3721 I915_WRITE(reg, temp);
3722
3723 reg = FDI_RX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 if (HAS_PCH_CPT(dev)) {
3726 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3727 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728 } else {
3729 temp &= ~FDI_LINK_TRAIN_NONE;
3730 temp |= FDI_LINK_TRAIN_PATTERN_1;
3731 }
3732 /* BPC in FDI rx is consistent with that in PIPECONF */
3733 temp &= ~(0x07 << 16);
3734 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3735 I915_WRITE(reg, temp);
3736
3737 POSTING_READ(reg);
3738 udelay(100);
3739 }
3740
3741 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3742 {
3743 struct intel_crtc *crtc;
3744
3745 /* Note that we don't need to be called with mode_config.lock here
3746 * as our list of CRTC objects is static for the lifetime of the
3747 * device and so cannot disappear as we iterate. Similarly, we can
3748 * happily treat the predicates as racy, atomic checks as userspace
3749 * cannot claim and pin a new fb without at least acquring the
3750 * struct_mutex and so serialising with us.
3751 */
3752 for_each_intel_crtc(dev, crtc) {
3753 if (atomic_read(&crtc->unpin_work_count) == 0)
3754 continue;
3755
3756 if (!list_empty_careful(&crtc->flip_work))
3757 intel_wait_for_vblank(dev, crtc->pipe);
3758
3759 return true;
3760 }
3761
3762 return false;
3763 }
3764
3765 static void page_flip_completed(struct intel_crtc *intel_crtc, struct intel_flip_work *work)
3766 {
3767 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3768 struct drm_plane_state *new_plane_state;
3769 struct drm_plane *primary = intel_crtc->base.primary;
3770
3771 if (work->event)
3772 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3773
3774 drm_crtc_vblank_put(&intel_crtc->base);
3775
3776 new_plane_state = &work->old_plane_state[0]->base;
3777 if (work->num_planes >= 1 &&
3778 new_plane_state->plane == primary &&
3779 new_plane_state->fb)
3780 trace_i915_flip_complete(intel_crtc->plane,
3781 intel_fb_obj(new_plane_state->fb));
3782
3783 if (work->can_async_unpin) {
3784 list_del_init(&work->head);
3785 wake_up_all(&dev_priv->pending_flip_queue);
3786 }
3787
3788 queue_work(dev_priv->wq, &work->unpin_work);
3789 }
3790
3791 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3792 {
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 long ret;
3796
3797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3798
3799 ret = wait_event_interruptible_timeout(
3800 dev_priv->pending_flip_queue,
3801 !intel_crtc_has_pending_flip(crtc),
3802 60*HZ);
3803
3804 if (ret < 0)
3805 return ret;
3806
3807 WARN(ret == 0, "Stuck page flip\n");
3808
3809 return 0;
3810 }
3811
3812 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3813 {
3814 u32 temp;
3815
3816 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3817
3818 mutex_lock(&dev_priv->sb_lock);
3819
3820 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3821 temp |= SBI_SSCCTL_DISABLE;
3822 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3823
3824 mutex_unlock(&dev_priv->sb_lock);
3825 }
3826
3827 /* Program iCLKIP clock to the desired frequency */
3828 static void lpt_program_iclkip(struct drm_crtc *crtc)
3829 {
3830 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3831 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3832 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3833 u32 temp;
3834
3835 lpt_disable_iclkip(dev_priv);
3836
3837 /* The iCLK virtual clock root frequency is in MHz,
3838 * but the adjusted_mode->crtc_clock in in KHz. To get the
3839 * divisors, it is necessary to divide one by another, so we
3840 * convert the virtual clock precision to KHz here for higher
3841 * precision.
3842 */
3843 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3844 u32 iclk_virtual_root_freq = 172800 * 1000;
3845 u32 iclk_pi_range = 64;
3846 u32 desired_divisor;
3847
3848 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3849 clock << auxdiv);
3850 divsel = (desired_divisor / iclk_pi_range) - 2;
3851 phaseinc = desired_divisor % iclk_pi_range;
3852
3853 /*
3854 * Near 20MHz is a corner case which is
3855 * out of range for the 7-bit divisor
3856 */
3857 if (divsel <= 0x7f)
3858 break;
3859 }
3860
3861 /* This should not happen with any sane values */
3862 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3863 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3864 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3865 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3866
3867 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3868 clock,
3869 auxdiv,
3870 divsel,
3871 phasedir,
3872 phaseinc);
3873
3874 mutex_lock(&dev_priv->sb_lock);
3875
3876 /* Program SSCDIVINTPHASE6 */
3877 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3878 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3879 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3880 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3881 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3882 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3883 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3884 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3885
3886 /* Program SSCAUXDIV */
3887 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3888 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3889 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3890 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3891
3892 /* Enable modulator and associated divider */
3893 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3894 temp &= ~SBI_SSCCTL_DISABLE;
3895 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3896
3897 mutex_unlock(&dev_priv->sb_lock);
3898
3899 /* Wait for initialization time */
3900 udelay(24);
3901
3902 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3903 }
3904
3905 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3906 {
3907 u32 divsel, phaseinc, auxdiv;
3908 u32 iclk_virtual_root_freq = 172800 * 1000;
3909 u32 iclk_pi_range = 64;
3910 u32 desired_divisor;
3911 u32 temp;
3912
3913 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3914 return 0;
3915
3916 mutex_lock(&dev_priv->sb_lock);
3917
3918 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3919 if (temp & SBI_SSCCTL_DISABLE) {
3920 mutex_unlock(&dev_priv->sb_lock);
3921 return 0;
3922 }
3923
3924 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3925 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3926 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3927 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3928 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3929
3930 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3931 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3932 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3933
3934 mutex_unlock(&dev_priv->sb_lock);
3935
3936 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3937
3938 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3939 desired_divisor << auxdiv);
3940 }
3941
3942 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3943 enum pipe pch_transcoder)
3944 {
3945 struct drm_device *dev = crtc->base.dev;
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3948
3949 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3950 I915_READ(HTOTAL(cpu_transcoder)));
3951 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3952 I915_READ(HBLANK(cpu_transcoder)));
3953 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3954 I915_READ(HSYNC(cpu_transcoder)));
3955
3956 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3957 I915_READ(VTOTAL(cpu_transcoder)));
3958 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3959 I915_READ(VBLANK(cpu_transcoder)));
3960 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3961 I915_READ(VSYNC(cpu_transcoder)));
3962 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3963 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3964 }
3965
3966 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3967 {
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 uint32_t temp;
3970
3971 temp = I915_READ(SOUTH_CHICKEN1);
3972 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3973 return;
3974
3975 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3976 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3977
3978 temp &= ~FDI_BC_BIFURCATION_SELECT;
3979 if (enable)
3980 temp |= FDI_BC_BIFURCATION_SELECT;
3981
3982 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3983 I915_WRITE(SOUTH_CHICKEN1, temp);
3984 POSTING_READ(SOUTH_CHICKEN1);
3985 }
3986
3987 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3988 {
3989 struct drm_device *dev = intel_crtc->base.dev;
3990
3991 switch (intel_crtc->pipe) {
3992 case PIPE_A:
3993 break;
3994 case PIPE_B:
3995 if (intel_crtc->config->fdi_lanes > 2)
3996 cpt_set_fdi_bc_bifurcation(dev, false);
3997 else
3998 cpt_set_fdi_bc_bifurcation(dev, true);
3999
4000 break;
4001 case PIPE_C:
4002 cpt_set_fdi_bc_bifurcation(dev, true);
4003
4004 break;
4005 default:
4006 BUG();
4007 }
4008 }
4009
4010 /* Return which DP Port should be selected for Transcoder DP control */
4011 static enum port
4012 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4013 {
4014 struct drm_device *dev = crtc->dev;
4015 struct intel_encoder *encoder;
4016
4017 for_each_encoder_on_crtc(dev, crtc, encoder) {
4018 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4019 encoder->type == INTEL_OUTPUT_EDP)
4020 return enc_to_dig_port(&encoder->base)->port;
4021 }
4022
4023 return -1;
4024 }
4025
4026 /*
4027 * Enable PCH resources required for PCH ports:
4028 * - PCH PLLs
4029 * - FDI training & RX/TX
4030 * - update transcoder timings
4031 * - DP transcoding bits
4032 * - transcoder
4033 */
4034 static void ironlake_pch_enable(struct drm_crtc *crtc)
4035 {
4036 struct drm_device *dev = crtc->dev;
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039 int pipe = intel_crtc->pipe;
4040 u32 temp;
4041
4042 assert_pch_transcoder_disabled(dev_priv, pipe);
4043
4044 if (IS_IVYBRIDGE(dev))
4045 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4046
4047 /* Write the TU size bits before fdi link training, so that error
4048 * detection works. */
4049 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4050 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4051
4052 /* For PCH output, training FDI link */
4053 dev_priv->display.fdi_link_train(crtc);
4054
4055 /* We need to program the right clock selection before writing the pixel
4056 * mutliplier into the DPLL. */
4057 if (HAS_PCH_CPT(dev)) {
4058 u32 sel;
4059
4060 temp = I915_READ(PCH_DPLL_SEL);
4061 temp |= TRANS_DPLL_ENABLE(pipe);
4062 sel = TRANS_DPLLB_SEL(pipe);
4063 if (intel_crtc->config->shared_dpll ==
4064 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4065 temp |= sel;
4066 else
4067 temp &= ~sel;
4068 I915_WRITE(PCH_DPLL_SEL, temp);
4069 }
4070
4071 /* XXX: pch pll's can be enabled any time before we enable the PCH
4072 * transcoder, and we actually should do this to not upset any PCH
4073 * transcoder that already use the clock when we share it.
4074 *
4075 * Note that enable_shared_dpll tries to do the right thing, but
4076 * get_shared_dpll unconditionally resets the pll - we need that to have
4077 * the right LVDS enable sequence. */
4078 intel_enable_shared_dpll(intel_crtc);
4079
4080 /* set transcoder timing, panel must allow it */
4081 assert_panel_unlocked(dev_priv, pipe);
4082 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4083
4084 intel_fdi_normal_train(crtc);
4085
4086 /* For PCH DP, enable TRANS_DP_CTL */
4087 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4088 const struct drm_display_mode *adjusted_mode =
4089 &intel_crtc->config->base.adjusted_mode;
4090 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4091 i915_reg_t reg = TRANS_DP_CTL(pipe);
4092 temp = I915_READ(reg);
4093 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4094 TRANS_DP_SYNC_MASK |
4095 TRANS_DP_BPC_MASK);
4096 temp |= TRANS_DP_OUTPUT_ENABLE;
4097 temp |= bpc << 9; /* same format but at 11:9 */
4098
4099 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4100 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4101 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4102 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4103
4104 switch (intel_trans_dp_port_sel(crtc)) {
4105 case PORT_B:
4106 temp |= TRANS_DP_PORT_SEL_B;
4107 break;
4108 case PORT_C:
4109 temp |= TRANS_DP_PORT_SEL_C;
4110 break;
4111 case PORT_D:
4112 temp |= TRANS_DP_PORT_SEL_D;
4113 break;
4114 default:
4115 BUG();
4116 }
4117
4118 I915_WRITE(reg, temp);
4119 }
4120
4121 ironlake_enable_pch_transcoder(dev_priv, pipe);
4122 }
4123
4124 static void lpt_pch_enable(struct drm_crtc *crtc)
4125 {
4126 struct drm_device *dev = crtc->dev;
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4130
4131 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4132
4133 lpt_program_iclkip(crtc);
4134
4135 /* Set transcoder timing. */
4136 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4137
4138 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4139 }
4140
4141 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4142 {
4143 struct drm_i915_private *dev_priv = dev->dev_private;
4144 i915_reg_t dslreg = PIPEDSL(pipe);
4145 u32 temp;
4146
4147 temp = I915_READ(dslreg);
4148 udelay(500);
4149 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4150 if (wait_for(I915_READ(dslreg) != temp, 5))
4151 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4152 }
4153 }
4154
4155 static int
4156 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4157 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4158 int src_w, int src_h, int dst_w, int dst_h)
4159 {
4160 struct intel_crtc_scaler_state *scaler_state =
4161 &crtc_state->scaler_state;
4162 struct intel_crtc *intel_crtc =
4163 to_intel_crtc(crtc_state->base.crtc);
4164 int need_scaling;
4165
4166 need_scaling = intel_rotation_90_or_270(rotation) ?
4167 (src_h != dst_w || src_w != dst_h):
4168 (src_w != dst_w || src_h != dst_h);
4169
4170 /*
4171 * if plane is being disabled or scaler is no more required or force detach
4172 * - free scaler binded to this plane/crtc
4173 * - in order to do this, update crtc->scaler_usage
4174 *
4175 * Here scaler state in crtc_state is set free so that
4176 * scaler can be assigned to other user. Actual register
4177 * update to free the scaler is done in plane/panel-fit programming.
4178 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4179 */
4180 if (force_detach || !need_scaling) {
4181 if (*scaler_id >= 0) {
4182 scaler_state->scaler_users &= ~(1 << scaler_user);
4183 scaler_state->scalers[*scaler_id].in_use = 0;
4184
4185 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4186 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4187 intel_crtc->pipe, scaler_user, *scaler_id,
4188 scaler_state->scaler_users);
4189 *scaler_id = -1;
4190 }
4191 return 0;
4192 }
4193
4194 /* range checks */
4195 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4196 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4197
4198 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4199 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4200 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4201 "size is out of scaler range\n",
4202 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4203 return -EINVAL;
4204 }
4205
4206 /* mark this plane as a scaler user in crtc_state */
4207 scaler_state->scaler_users |= (1 << scaler_user);
4208 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4209 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4210 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4211 scaler_state->scaler_users);
4212
4213 return 0;
4214 }
4215
4216 /**
4217 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4218 *
4219 * @state: crtc's scaler state
4220 *
4221 * Return
4222 * 0 - scaler_usage updated successfully
4223 * error - requested scaling cannot be supported or other error condition
4224 */
4225 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4226 {
4227 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4228 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4229
4230 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4231 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4232
4233 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4234 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4235 state->pipe_src_w, state->pipe_src_h,
4236 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4237 }
4238
4239 /**
4240 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4241 *
4242 * @state: crtc's scaler state
4243 * @plane_state: atomic plane state to update
4244 *
4245 * Return
4246 * 0 - scaler_usage updated successfully
4247 * error - requested scaling cannot be supported or other error condition
4248 */
4249 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4250 struct intel_plane_state *plane_state)
4251 {
4252
4253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4254 struct intel_plane *intel_plane =
4255 to_intel_plane(plane_state->base.plane);
4256 struct drm_framebuffer *fb = plane_state->base.fb;
4257 int ret;
4258
4259 bool force_detach = !fb || !plane_state->visible;
4260
4261 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4262 intel_plane->base.base.id, intel_crtc->pipe,
4263 drm_plane_index(&intel_plane->base));
4264
4265 ret = skl_update_scaler(crtc_state, force_detach,
4266 drm_plane_index(&intel_plane->base),
4267 &plane_state->scaler_id,
4268 plane_state->base.rotation,
4269 drm_rect_width(&plane_state->src) >> 16,
4270 drm_rect_height(&plane_state->src) >> 16,
4271 drm_rect_width(&plane_state->dst),
4272 drm_rect_height(&plane_state->dst));
4273
4274 if (ret || plane_state->scaler_id < 0)
4275 return ret;
4276
4277 /* check colorkey */
4278 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4279 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4280 intel_plane->base.base.id);
4281 return -EINVAL;
4282 }
4283
4284 /* Check src format */
4285 switch (fb->pixel_format) {
4286 case DRM_FORMAT_RGB565:
4287 case DRM_FORMAT_XBGR8888:
4288 case DRM_FORMAT_XRGB8888:
4289 case DRM_FORMAT_ABGR8888:
4290 case DRM_FORMAT_ARGB8888:
4291 case DRM_FORMAT_XRGB2101010:
4292 case DRM_FORMAT_XBGR2101010:
4293 case DRM_FORMAT_YUYV:
4294 case DRM_FORMAT_YVYU:
4295 case DRM_FORMAT_UYVY:
4296 case DRM_FORMAT_VYUY:
4297 break;
4298 default:
4299 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4300 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4301 return -EINVAL;
4302 }
4303
4304 return 0;
4305 }
4306
4307 static void skylake_scaler_disable(struct intel_crtc *crtc)
4308 {
4309 int i;
4310
4311 for (i = 0; i < crtc->num_scalers; i++)
4312 skl_detach_scaler(crtc, i);
4313 }
4314
4315 static void skylake_pfit_enable(struct intel_crtc *crtc)
4316 {
4317 struct drm_device *dev = crtc->base.dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 int pipe = crtc->pipe;
4320 struct intel_crtc_scaler_state *scaler_state =
4321 &crtc->config->scaler_state;
4322
4323 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4324
4325 if (crtc->config->pch_pfit.enabled) {
4326 int id;
4327
4328 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4329 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4330 return;
4331 }
4332
4333 id = scaler_state->scaler_id;
4334 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4335 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4336 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4337 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4338
4339 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4340 }
4341 }
4342
4343 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4344 {
4345 struct drm_device *dev = crtc->base.dev;
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347 int pipe = crtc->pipe;
4348
4349 if (crtc->config->pch_pfit.enabled) {
4350 /* Force use of hard-coded filter coefficients
4351 * as some pre-programmed values are broken,
4352 * e.g. x201.
4353 */
4354 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4355 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4356 PF_PIPE_SEL_IVB(pipe));
4357 else
4358 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4359 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4360 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4361 }
4362 }
4363
4364 void hsw_enable_ips(struct intel_crtc *crtc)
4365 {
4366 struct drm_device *dev = crtc->base.dev;
4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368
4369 if (!crtc->config->ips_enabled)
4370 return;
4371
4372 /*
4373 * We can only enable IPS after we enable a plane and wait for a vblank
4374 * This function is called from post_plane_update, which is run after
4375 * a vblank wait.
4376 */
4377
4378 assert_plane_enabled(dev_priv, crtc->plane);
4379 if (IS_BROADWELL(dev)) {
4380 mutex_lock(&dev_priv->rps.hw_lock);
4381 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4382 mutex_unlock(&dev_priv->rps.hw_lock);
4383 /* Quoting Art Runyan: "its not safe to expect any particular
4384 * value in IPS_CTL bit 31 after enabling IPS through the
4385 * mailbox." Moreover, the mailbox may return a bogus state,
4386 * so we need to just enable it and continue on.
4387 */
4388 } else {
4389 I915_WRITE(IPS_CTL, IPS_ENABLE);
4390 /* The bit only becomes 1 in the next vblank, so this wait here
4391 * is essentially intel_wait_for_vblank. If we don't have this
4392 * and don't wait for vblanks until the end of crtc_enable, then
4393 * the HW state readout code will complain that the expected
4394 * IPS_CTL value is not the one we read. */
4395 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4396 DRM_ERROR("Timed out waiting for IPS enable\n");
4397 }
4398 }
4399
4400 void hsw_disable_ips(struct intel_crtc *crtc)
4401 {
4402 struct drm_device *dev = crtc->base.dev;
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404
4405 if (!crtc->config->ips_enabled)
4406 return;
4407
4408 assert_plane_enabled(dev_priv, crtc->plane);
4409 if (IS_BROADWELL(dev)) {
4410 mutex_lock(&dev_priv->rps.hw_lock);
4411 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4412 mutex_unlock(&dev_priv->rps.hw_lock);
4413 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4414 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4415 DRM_ERROR("Timed out waiting for IPS disable\n");
4416 } else {
4417 I915_WRITE(IPS_CTL, 0);
4418 POSTING_READ(IPS_CTL);
4419 }
4420
4421 /* We need to wait for a vblank before we can disable the plane. */
4422 intel_wait_for_vblank(dev, crtc->pipe);
4423 }
4424
4425 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4426 {
4427 if (intel_crtc->overlay) {
4428 struct drm_device *dev = intel_crtc->base.dev;
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430
4431 mutex_lock(&dev->struct_mutex);
4432 dev_priv->mm.interruptible = false;
4433 (void) intel_overlay_switch_off(intel_crtc->overlay);
4434 dev_priv->mm.interruptible = true;
4435 mutex_unlock(&dev->struct_mutex);
4436 }
4437
4438 /* Let userspace switch the overlay on again. In most cases userspace
4439 * has to recompute where to put it anyway.
4440 */
4441 }
4442
4443 /**
4444 * intel_post_enable_primary - Perform operations after enabling primary plane
4445 * @crtc: the CRTC whose primary plane was just enabled
4446 *
4447 * Performs potentially sleeping operations that must be done after the primary
4448 * plane is enabled, such as updating FBC and IPS. Note that this may be
4449 * called due to an explicit primary plane update, or due to an implicit
4450 * re-enable that is caused when a sprite plane is updated to no longer
4451 * completely hide the primary plane.
4452 */
4453 static void
4454 intel_post_enable_primary(struct drm_crtc *crtc)
4455 {
4456 struct drm_device *dev = crtc->dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4459 int pipe = intel_crtc->pipe;
4460
4461 /*
4462 * FIXME IPS should be fine as long as one plane is
4463 * enabled, but in practice it seems to have problems
4464 * when going from primary only to sprite only and vice
4465 * versa.
4466 */
4467 hsw_enable_ips(intel_crtc);
4468
4469 /*
4470 * Gen2 reports pipe underruns whenever all planes are disabled.
4471 * So don't enable underrun reporting before at least some planes
4472 * are enabled.
4473 * FIXME: Need to fix the logic to work when we turn off all planes
4474 * but leave the pipe running.
4475 */
4476 if (IS_GEN2(dev))
4477 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4478
4479 /* Underruns don't always raise interrupts, so check manually. */
4480 intel_check_cpu_fifo_underruns(dev_priv);
4481 intel_check_pch_fifo_underruns(dev_priv);
4482 }
4483
4484 /* FIXME move all this to pre_plane_update() with proper state tracking */
4485 static void
4486 intel_pre_disable_primary(struct drm_crtc *crtc)
4487 {
4488 struct drm_device *dev = crtc->dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4491 int pipe = intel_crtc->pipe;
4492
4493 /*
4494 * Gen2 reports pipe underruns whenever all planes are disabled.
4495 * So diasble underrun reporting before all the planes get disabled.
4496 * FIXME: Need to fix the logic to work when we turn off all planes
4497 * but leave the pipe running.
4498 */
4499 if (IS_GEN2(dev))
4500 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4501
4502 /*
4503 * FIXME IPS should be fine as long as one plane is
4504 * enabled, but in practice it seems to have problems
4505 * when going from primary only to sprite only and vice
4506 * versa.
4507 */
4508 hsw_disable_ips(intel_crtc);
4509 }
4510
4511 /* FIXME get rid of this and use pre_plane_update */
4512 static void
4513 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4514 {
4515 struct drm_device *dev = crtc->dev;
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518 int pipe = intel_crtc->pipe;
4519
4520 intel_pre_disable_primary(crtc);
4521
4522 /*
4523 * Vblank time updates from the shadow to live plane control register
4524 * are blocked if the memory self-refresh mode is active at that
4525 * moment. So to make sure the plane gets truly disabled, disable
4526 * first the self-refresh mode. The self-refresh enable bit in turn
4527 * will be checked/applied by the HW only at the next frame start
4528 * event which is after the vblank start event, so we need to have a
4529 * wait-for-vblank between disabling the plane and the pipe.
4530 */
4531 if (HAS_GMCH_DISPLAY(dev)) {
4532 intel_set_memory_cxsr(dev_priv, false);
4533 dev_priv->wm.vlv.cxsr = false;
4534 intel_wait_for_vblank(dev, pipe);
4535 }
4536 }
4537
4538 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4539 {
4540 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4541 struct drm_device *dev = crtc->base.dev;
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 struct intel_crtc_state *pipe_config =
4544 to_intel_crtc_state(crtc->base.state);
4545 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4546 struct drm_plane *primary = crtc->base.primary;
4547 struct drm_plane_state *old_pri_state =
4548 drm_atomic_get_existing_plane_state(old_state, primary);
4549 bool modeset = needs_modeset(&pipe_config->base);
4550
4551 if (old_pri_state) {
4552 struct intel_plane_state *primary_state =
4553 to_intel_plane_state(primary->state);
4554 struct intel_plane_state *old_primary_state =
4555 to_intel_plane_state(old_pri_state);
4556
4557 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4558
4559 if (old_primary_state->visible &&
4560 (modeset || !primary_state->visible))
4561 intel_pre_disable_primary(&crtc->base);
4562 }
4563
4564 if (pipe_config->disable_cxsr) {
4565 crtc->wm.cxsr_allowed = false;
4566
4567 /*
4568 * Vblank time updates from the shadow to live plane control register
4569 * are blocked if the memory self-refresh mode is active at that
4570 * moment. So to make sure the plane gets truly disabled, disable
4571 * first the self-refresh mode. The self-refresh enable bit in turn
4572 * will be checked/applied by the HW only at the next frame start
4573 * event which is after the vblank start event, so we need to have a
4574 * wait-for-vblank between disabling the plane and the pipe.
4575 */
4576 if (old_crtc_state->base.active) {
4577 intel_set_memory_cxsr(dev_priv, false);
4578 dev_priv->wm.vlv.cxsr = false;
4579 intel_wait_for_vblank(dev, crtc->pipe);
4580 }
4581 }
4582
4583 /*
4584 * IVB workaround: must disable low power watermarks for at least
4585 * one frame before enabling scaling. LP watermarks can be re-enabled
4586 * when scaling is disabled.
4587 *
4588 * WaCxSRDisabledForSpriteScaling:ivb
4589 */
4590 if (pipe_config->disable_lp_wm) {
4591 ilk_disable_lp_wm(dev);
4592 intel_wait_for_vblank(dev, crtc->pipe);
4593 }
4594
4595 /*
4596 * If we're doing a modeset, we're done. No need to do any pre-vblank
4597 * watermark programming here.
4598 */
4599 if (needs_modeset(&pipe_config->base))
4600 return;
4601
4602 /*
4603 * For platforms that support atomic watermarks, program the
4604 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4605 * will be the intermediate values that are safe for both pre- and
4606 * post- vblank; when vblank happens, the 'active' values will be set
4607 * to the final 'target' values and we'll do this again to get the
4608 * optimal watermarks. For gen9+ platforms, the values we program here
4609 * will be the final target values which will get automatically latched
4610 * at vblank time; no further programming will be necessary.
4611 *
4612 * If a platform hasn't been transitioned to atomic watermarks yet,
4613 * we'll continue to update watermarks the old way, if flags tell
4614 * us to.
4615 */
4616 if (dev_priv->display.initial_watermarks != NULL)
4617 dev_priv->display.initial_watermarks(pipe_config);
4618 else if (pipe_config->update_wm_pre)
4619 intel_update_watermarks(&crtc->base);
4620 }
4621
4622 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4623 {
4624 struct drm_device *dev = crtc->dev;
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 struct drm_plane *p;
4627 int pipe = intel_crtc->pipe;
4628
4629 intel_crtc_dpms_overlay_disable(intel_crtc);
4630
4631 drm_for_each_plane_mask(p, dev, plane_mask)
4632 to_intel_plane(p)->disable_plane(p, crtc);
4633
4634 /*
4635 * FIXME: Once we grow proper nuclear flip support out of this we need
4636 * to compute the mask of flip planes precisely. For the time being
4637 * consider this a flip to a NULL plane.
4638 */
4639 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4640 }
4641
4642 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4643 {
4644 struct drm_device *dev = crtc->dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647 struct intel_encoder *encoder;
4648 int pipe = intel_crtc->pipe;
4649 struct intel_crtc_state *pipe_config =
4650 to_intel_crtc_state(crtc->state);
4651
4652 if (WARN_ON(intel_crtc->active))
4653 return;
4654
4655 /*
4656 * Sometimes spurious CPU pipe underruns happen during FDI
4657 * training, at least with VGA+HDMI cloning. Suppress them.
4658 *
4659 * On ILK we get an occasional spurious CPU pipe underruns
4660 * between eDP port A enable and vdd enable. Also PCH port
4661 * enable seems to result in the occasional CPU pipe underrun.
4662 *
4663 * Spurious PCH underruns also occur during PCH enabling.
4664 */
4665 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4666 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4667 if (intel_crtc->config->has_pch_encoder)
4668 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4669
4670 if (intel_crtc->config->has_pch_encoder)
4671 intel_prepare_shared_dpll(intel_crtc);
4672
4673 if (intel_crtc->config->has_dp_encoder)
4674 intel_dp_set_m_n(intel_crtc, M1_N1);
4675
4676 intel_set_pipe_timings(intel_crtc);
4677 intel_set_pipe_src_size(intel_crtc);
4678
4679 if (intel_crtc->config->has_pch_encoder) {
4680 intel_cpu_transcoder_set_m_n(intel_crtc,
4681 &intel_crtc->config->fdi_m_n, NULL);
4682 }
4683
4684 ironlake_set_pipeconf(crtc);
4685
4686 intel_crtc->active = true;
4687
4688 for_each_encoder_on_crtc(dev, crtc, encoder)
4689 if (encoder->pre_enable)
4690 encoder->pre_enable(encoder);
4691
4692 if (intel_crtc->config->has_pch_encoder) {
4693 /* Note: FDI PLL enabling _must_ be done before we enable the
4694 * cpu pipes, hence this is separate from all the other fdi/pch
4695 * enabling. */
4696 ironlake_fdi_pll_enable(intel_crtc);
4697 } else {
4698 assert_fdi_tx_disabled(dev_priv, pipe);
4699 assert_fdi_rx_disabled(dev_priv, pipe);
4700 }
4701
4702 ironlake_pfit_enable(intel_crtc);
4703
4704 /*
4705 * On ILK+ LUT must be loaded before the pipe is running but with
4706 * clocks enabled
4707 */
4708 intel_color_load_luts(&pipe_config->base);
4709
4710 if (dev_priv->display.initial_watermarks != NULL)
4711 dev_priv->display.initial_watermarks(intel_crtc->config);
4712 intel_enable_pipe(intel_crtc);
4713
4714 if (intel_crtc->config->has_pch_encoder)
4715 ironlake_pch_enable(crtc);
4716
4717 assert_vblank_disabled(crtc);
4718 drm_crtc_vblank_on(crtc);
4719
4720 for_each_encoder_on_crtc(dev, crtc, encoder)
4721 encoder->enable(encoder);
4722
4723 if (HAS_PCH_CPT(dev))
4724 cpt_verify_modeset(dev, intel_crtc->pipe);
4725
4726 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4727 if (intel_crtc->config->has_pch_encoder)
4728 intel_wait_for_vblank(dev, pipe);
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4730 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4731 }
4732
4733 /* IPS only exists on ULT machines and is tied to pipe A. */
4734 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4735 {
4736 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4737 }
4738
4739 static void haswell_crtc_enable(struct drm_crtc *crtc)
4740 {
4741 struct drm_device *dev = crtc->dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4744 struct intel_encoder *encoder;
4745 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4746 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4747 struct intel_crtc_state *pipe_config =
4748 to_intel_crtc_state(crtc->state);
4749
4750 if (WARN_ON(intel_crtc->active))
4751 return;
4752
4753 if (intel_crtc->config->has_pch_encoder)
4754 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4755 false);
4756
4757 if (intel_crtc->config->shared_dpll)
4758 intel_enable_shared_dpll(intel_crtc);
4759
4760 if (intel_crtc->config->has_dp_encoder)
4761 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763 if (!intel_crtc->config->has_dsi_encoder)
4764 intel_set_pipe_timings(intel_crtc);
4765
4766 intel_set_pipe_src_size(intel_crtc);
4767
4768 if (cpu_transcoder != TRANSCODER_EDP &&
4769 !transcoder_is_dsi(cpu_transcoder)) {
4770 I915_WRITE(PIPE_MULT(cpu_transcoder),
4771 intel_crtc->config->pixel_multiplier - 1);
4772 }
4773
4774 if (intel_crtc->config->has_pch_encoder) {
4775 intel_cpu_transcoder_set_m_n(intel_crtc,
4776 &intel_crtc->config->fdi_m_n, NULL);
4777 }
4778
4779 if (!intel_crtc->config->has_dsi_encoder)
4780 haswell_set_pipeconf(crtc);
4781
4782 haswell_set_pipemisc(crtc);
4783
4784 intel_color_set_csc(&pipe_config->base);
4785
4786 intel_crtc->active = true;
4787
4788 if (intel_crtc->config->has_pch_encoder)
4789 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4790 else
4791 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4792
4793 for_each_encoder_on_crtc(dev, crtc, encoder) {
4794 if (encoder->pre_enable)
4795 encoder->pre_enable(encoder);
4796 }
4797
4798 if (intel_crtc->config->has_pch_encoder)
4799 dev_priv->display.fdi_link_train(crtc);
4800
4801 if (!intel_crtc->config->has_dsi_encoder)
4802 intel_ddi_enable_pipe_clock(intel_crtc);
4803
4804 if (INTEL_INFO(dev)->gen >= 9)
4805 skylake_pfit_enable(intel_crtc);
4806 else
4807 ironlake_pfit_enable(intel_crtc);
4808
4809 /*
4810 * On ILK+ LUT must be loaded before the pipe is running but with
4811 * clocks enabled
4812 */
4813 intel_color_load_luts(&pipe_config->base);
4814
4815 intel_ddi_set_pipe_settings(crtc);
4816 if (!intel_crtc->config->has_dsi_encoder)
4817 intel_ddi_enable_transcoder_func(crtc);
4818
4819 if (dev_priv->display.initial_watermarks != NULL)
4820 dev_priv->display.initial_watermarks(pipe_config);
4821 else
4822 intel_update_watermarks(crtc);
4823
4824 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4825 if (!intel_crtc->config->has_dsi_encoder)
4826 intel_enable_pipe(intel_crtc);
4827
4828 if (intel_crtc->config->has_pch_encoder)
4829 lpt_pch_enable(crtc);
4830
4831 if (intel_crtc->config->dp_encoder_is_mst)
4832 intel_ddi_set_vc_payload_alloc(crtc, true);
4833
4834 assert_vblank_disabled(crtc);
4835 drm_crtc_vblank_on(crtc);
4836
4837 for_each_encoder_on_crtc(dev, crtc, encoder) {
4838 encoder->enable(encoder);
4839 intel_opregion_notify_encoder(encoder, true);
4840 }
4841
4842 if (intel_crtc->config->has_pch_encoder) {
4843 intel_wait_for_vblank(dev, pipe);
4844 intel_wait_for_vblank(dev, pipe);
4845 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4846 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4847 true);
4848 }
4849
4850 /* If we change the relative order between pipe/planes enabling, we need
4851 * to change the workaround. */
4852 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4853 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4854 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4855 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4856 }
4857 }
4858
4859 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4860 {
4861 struct drm_device *dev = crtc->base.dev;
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863 int pipe = crtc->pipe;
4864
4865 /* To avoid upsetting the power well on haswell only disable the pfit if
4866 * it's in use. The hw state code will make sure we get this right. */
4867 if (force || crtc->config->pch_pfit.enabled) {
4868 I915_WRITE(PF_CTL(pipe), 0);
4869 I915_WRITE(PF_WIN_POS(pipe), 0);
4870 I915_WRITE(PF_WIN_SZ(pipe), 0);
4871 }
4872 }
4873
4874 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4875 {
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 struct intel_encoder *encoder;
4880 int pipe = intel_crtc->pipe;
4881
4882 /*
4883 * Sometimes spurious CPU pipe underruns happen when the
4884 * pipe is already disabled, but FDI RX/TX is still enabled.
4885 * Happens at least with VGA+HDMI cloning. Suppress them.
4886 */
4887 if (intel_crtc->config->has_pch_encoder) {
4888 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4889 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4890 }
4891
4892 for_each_encoder_on_crtc(dev, crtc, encoder)
4893 encoder->disable(encoder);
4894
4895 drm_crtc_vblank_off(crtc);
4896 assert_vblank_disabled(crtc);
4897
4898 intel_disable_pipe(intel_crtc);
4899
4900 ironlake_pfit_disable(intel_crtc, false);
4901
4902 if (intel_crtc->config->has_pch_encoder)
4903 ironlake_fdi_disable(crtc);
4904
4905 for_each_encoder_on_crtc(dev, crtc, encoder)
4906 if (encoder->post_disable)
4907 encoder->post_disable(encoder);
4908
4909 if (intel_crtc->config->has_pch_encoder) {
4910 ironlake_disable_pch_transcoder(dev_priv, pipe);
4911
4912 if (HAS_PCH_CPT(dev)) {
4913 i915_reg_t reg;
4914 u32 temp;
4915
4916 /* disable TRANS_DP_CTL */
4917 reg = TRANS_DP_CTL(pipe);
4918 temp = I915_READ(reg);
4919 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4920 TRANS_DP_PORT_SEL_MASK);
4921 temp |= TRANS_DP_PORT_SEL_NONE;
4922 I915_WRITE(reg, temp);
4923
4924 /* disable DPLL_SEL */
4925 temp = I915_READ(PCH_DPLL_SEL);
4926 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4927 I915_WRITE(PCH_DPLL_SEL, temp);
4928 }
4929
4930 ironlake_fdi_pll_disable(intel_crtc);
4931 }
4932
4933 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4935 }
4936
4937 static void haswell_crtc_disable(struct drm_crtc *crtc)
4938 {
4939 struct drm_device *dev = crtc->dev;
4940 struct drm_i915_private *dev_priv = dev->dev_private;
4941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942 struct intel_encoder *encoder;
4943 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4944
4945 if (intel_crtc->config->has_pch_encoder)
4946 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4947 false);
4948
4949 for_each_encoder_on_crtc(dev, crtc, encoder) {
4950 intel_opregion_notify_encoder(encoder, false);
4951 encoder->disable(encoder);
4952 }
4953
4954 drm_crtc_vblank_off(crtc);
4955 assert_vblank_disabled(crtc);
4956
4957 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4958 if (!intel_crtc->config->has_dsi_encoder)
4959 intel_disable_pipe(intel_crtc);
4960
4961 if (intel_crtc->config->dp_encoder_is_mst)
4962 intel_ddi_set_vc_payload_alloc(crtc, false);
4963
4964 if (!intel_crtc->config->has_dsi_encoder)
4965 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4966
4967 if (INTEL_INFO(dev)->gen >= 9)
4968 skylake_scaler_disable(intel_crtc);
4969 else
4970 ironlake_pfit_disable(intel_crtc, false);
4971
4972 if (!intel_crtc->config->has_dsi_encoder)
4973 intel_ddi_disable_pipe_clock(intel_crtc);
4974
4975 for_each_encoder_on_crtc(dev, crtc, encoder)
4976 if (encoder->post_disable)
4977 encoder->post_disable(encoder);
4978
4979 if (intel_crtc->config->has_pch_encoder) {
4980 lpt_disable_pch_transcoder(dev_priv);
4981 lpt_disable_iclkip(dev_priv);
4982 intel_ddi_fdi_disable(crtc);
4983
4984 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4985 true);
4986 }
4987 }
4988
4989 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4990 {
4991 struct drm_device *dev = crtc->base.dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_crtc_state *pipe_config = crtc->config;
4994
4995 if (!pipe_config->gmch_pfit.control)
4996 return;
4997
4998 /*
4999 * The panel fitter should only be adjusted whilst the pipe is disabled,
5000 * according to register description and PRM.
5001 */
5002 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5003 assert_pipe_disabled(dev_priv, crtc->pipe);
5004
5005 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5006 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5007
5008 /* Border color in case we don't scale up to the full screen. Black by
5009 * default, change to something else for debugging. */
5010 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5011 }
5012
5013 static enum intel_display_power_domain port_to_power_domain(enum port port)
5014 {
5015 switch (port) {
5016 case PORT_A:
5017 return POWER_DOMAIN_PORT_DDI_A_LANES;
5018 case PORT_B:
5019 return POWER_DOMAIN_PORT_DDI_B_LANES;
5020 case PORT_C:
5021 return POWER_DOMAIN_PORT_DDI_C_LANES;
5022 case PORT_D:
5023 return POWER_DOMAIN_PORT_DDI_D_LANES;
5024 case PORT_E:
5025 return POWER_DOMAIN_PORT_DDI_E_LANES;
5026 default:
5027 MISSING_CASE(port);
5028 return POWER_DOMAIN_PORT_OTHER;
5029 }
5030 }
5031
5032 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5033 {
5034 switch (port) {
5035 case PORT_A:
5036 return POWER_DOMAIN_AUX_A;
5037 case PORT_B:
5038 return POWER_DOMAIN_AUX_B;
5039 case PORT_C:
5040 return POWER_DOMAIN_AUX_C;
5041 case PORT_D:
5042 return POWER_DOMAIN_AUX_D;
5043 case PORT_E:
5044 /* FIXME: Check VBT for actual wiring of PORT E */
5045 return POWER_DOMAIN_AUX_D;
5046 default:
5047 MISSING_CASE(port);
5048 return POWER_DOMAIN_AUX_A;
5049 }
5050 }
5051
5052 enum intel_display_power_domain
5053 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5054 {
5055 struct drm_device *dev = intel_encoder->base.dev;
5056 struct intel_digital_port *intel_dig_port;
5057
5058 switch (intel_encoder->type) {
5059 case INTEL_OUTPUT_UNKNOWN:
5060 /* Only DDI platforms should ever use this output type */
5061 WARN_ON_ONCE(!HAS_DDI(dev));
5062 case INTEL_OUTPUT_DISPLAYPORT:
5063 case INTEL_OUTPUT_HDMI:
5064 case INTEL_OUTPUT_EDP:
5065 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5066 return port_to_power_domain(intel_dig_port->port);
5067 case INTEL_OUTPUT_DP_MST:
5068 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5069 return port_to_power_domain(intel_dig_port->port);
5070 case INTEL_OUTPUT_ANALOG:
5071 return POWER_DOMAIN_PORT_CRT;
5072 case INTEL_OUTPUT_DSI:
5073 return POWER_DOMAIN_PORT_DSI;
5074 default:
5075 return POWER_DOMAIN_PORT_OTHER;
5076 }
5077 }
5078
5079 enum intel_display_power_domain
5080 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5081 {
5082 struct drm_device *dev = intel_encoder->base.dev;
5083 struct intel_digital_port *intel_dig_port;
5084
5085 switch (intel_encoder->type) {
5086 case INTEL_OUTPUT_UNKNOWN:
5087 case INTEL_OUTPUT_HDMI:
5088 /*
5089 * Only DDI platforms should ever use these output types.
5090 * We can get here after the HDMI detect code has already set
5091 * the type of the shared encoder. Since we can't be sure
5092 * what's the status of the given connectors, play safe and
5093 * run the DP detection too.
5094 */
5095 WARN_ON_ONCE(!HAS_DDI(dev));
5096 case INTEL_OUTPUT_DISPLAYPORT:
5097 case INTEL_OUTPUT_EDP:
5098 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5099 return port_to_aux_power_domain(intel_dig_port->port);
5100 case INTEL_OUTPUT_DP_MST:
5101 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5102 return port_to_aux_power_domain(intel_dig_port->port);
5103 default:
5104 MISSING_CASE(intel_encoder->type);
5105 return POWER_DOMAIN_AUX_A;
5106 }
5107 }
5108
5109 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5110 struct intel_crtc_state *crtc_state)
5111 {
5112 struct drm_device *dev = crtc->dev;
5113 struct drm_encoder *encoder;
5114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115 enum pipe pipe = intel_crtc->pipe;
5116 unsigned long mask;
5117 enum transcoder transcoder = crtc_state->cpu_transcoder;
5118
5119 if (!crtc_state->base.active)
5120 return 0;
5121
5122 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5123 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5124 if (crtc_state->pch_pfit.enabled ||
5125 crtc_state->pch_pfit.force_thru)
5126 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5127
5128 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5129 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5130
5131 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5132 }
5133
5134 if (crtc_state->shared_dpll)
5135 mask |= BIT(POWER_DOMAIN_PLLS);
5136
5137 return mask;
5138 }
5139
5140 static unsigned long
5141 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5142 struct intel_crtc_state *crtc_state)
5143 {
5144 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5146 enum intel_display_power_domain domain;
5147 unsigned long domains, new_domains, old_domains, ms_domain = 0;
5148
5149 old_domains = intel_crtc->enabled_power_domains;
5150 intel_crtc->enabled_power_domains = new_domains =
5151 get_crtc_power_domains(crtc, crtc_state);
5152
5153 if (needs_modeset(&crtc_state->base))
5154 ms_domain = BIT(POWER_DOMAIN_MODESET);
5155
5156 domains = (new_domains & ~old_domains) | ms_domain;
5157
5158 for_each_power_domain(domain, domains)
5159 intel_display_power_get(dev_priv, domain);
5160
5161 return (old_domains & ~new_domains) | ms_domain;
5162 }
5163
5164 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5165 unsigned long domains)
5166 {
5167 enum intel_display_power_domain domain;
5168
5169 for_each_power_domain(domain, domains)
5170 intel_display_power_put(dev_priv, domain);
5171 }
5172
5173 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5174 {
5175 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5176
5177 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5178 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5179 return max_cdclk_freq;
5180 else if (IS_CHERRYVIEW(dev_priv))
5181 return max_cdclk_freq*95/100;
5182 else if (INTEL_INFO(dev_priv)->gen < 4)
5183 return 2*max_cdclk_freq*90/100;
5184 else
5185 return max_cdclk_freq*90/100;
5186 }
5187
5188 static int skl_calc_cdclk(int max_pixclk, int vco);
5189
5190 static void intel_update_max_cdclk(struct drm_device *dev)
5191 {
5192 struct drm_i915_private *dev_priv = dev->dev_private;
5193
5194 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5195 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5196 int max_cdclk, vco;
5197
5198 vco = dev_priv->skl_preferred_vco_freq;
5199 WARN_ON(vco != 8100000 && vco != 8640000);
5200
5201 /*
5202 * Use the lower (vco 8640) cdclk values as a
5203 * first guess. skl_calc_cdclk() will correct it
5204 * if the preferred vco is 8100 instead.
5205 */
5206 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5207 max_cdclk = 617143;
5208 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5209 max_cdclk = 540000;
5210 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5211 max_cdclk = 432000;
5212 else
5213 max_cdclk = 308571;
5214
5215 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5216 } else if (IS_BROXTON(dev)) {
5217 dev_priv->max_cdclk_freq = 624000;
5218 } else if (IS_BROADWELL(dev)) {
5219 /*
5220 * FIXME with extra cooling we can allow
5221 * 540 MHz for ULX and 675 Mhz for ULT.
5222 * How can we know if extra cooling is
5223 * available? PCI ID, VTB, something else?
5224 */
5225 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5226 dev_priv->max_cdclk_freq = 450000;
5227 else if (IS_BDW_ULX(dev))
5228 dev_priv->max_cdclk_freq = 450000;
5229 else if (IS_BDW_ULT(dev))
5230 dev_priv->max_cdclk_freq = 540000;
5231 else
5232 dev_priv->max_cdclk_freq = 675000;
5233 } else if (IS_CHERRYVIEW(dev)) {
5234 dev_priv->max_cdclk_freq = 320000;
5235 } else if (IS_VALLEYVIEW(dev)) {
5236 dev_priv->max_cdclk_freq = 400000;
5237 } else {
5238 /* otherwise assume cdclk is fixed */
5239 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5240 }
5241
5242 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5243
5244 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5245 dev_priv->max_cdclk_freq);
5246
5247 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5248 dev_priv->max_dotclk_freq);
5249 }
5250
5251 static void intel_update_cdclk(struct drm_device *dev)
5252 {
5253 struct drm_i915_private *dev_priv = dev->dev_private;
5254
5255 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5256
5257 if (INTEL_GEN(dev_priv) >= 9)
5258 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5259 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5260 dev_priv->cdclk_pll.ref);
5261 else
5262 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5263 dev_priv->cdclk_freq);
5264
5265 /*
5266 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5267 * Programmng [sic] note: bit[9:2] should be programmed to the number
5268 * of cdclk that generates 4MHz reference clock freq which is used to
5269 * generate GMBus clock. This will vary with the cdclk freq.
5270 */
5271 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5272 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5273 }
5274
5275 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5276 static int skl_cdclk_decimal(int cdclk)
5277 {
5278 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5279 }
5280
5281 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5282 {
5283 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5284
5285 /* Timeout 200us */
5286 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5287 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5288
5289 dev_priv->cdclk_pll.vco = 0;
5290 }
5291
5292 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
5293 {
5294 u32 val;
5295
5296 val = I915_READ(BXT_DE_PLL_CTL);
5297 val &= ~BXT_DE_PLL_RATIO_MASK;
5298 val |= ratio;
5299 I915_WRITE(BXT_DE_PLL_CTL, val);
5300
5301 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5302
5303 /* Timeout 200us */
5304 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5305 DRM_ERROR("timeout waiting for DE PLL lock\n");
5306
5307 dev_priv->cdclk_pll.vco = ratio * dev_priv->cdclk_pll.ref;
5308 }
5309
5310 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5311 {
5312 uint32_t divider;
5313 uint32_t ratio;
5314 uint32_t current_cdclk;
5315 int ret;
5316
5317 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5318 switch (cdclk) {
5319 case 144000:
5320 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5321 ratio = BXT_DE_PLL_RATIO(60);
5322 break;
5323 case 288000:
5324 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5325 ratio = BXT_DE_PLL_RATIO(60);
5326 break;
5327 case 384000:
5328 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5329 ratio = BXT_DE_PLL_RATIO(60);
5330 break;
5331 case 576000:
5332 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5333 ratio = BXT_DE_PLL_RATIO(60);
5334 break;
5335 case 624000:
5336 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5337 ratio = BXT_DE_PLL_RATIO(65);
5338 break;
5339 case 19200:
5340 /*
5341 * Bypass frequency with DE PLL disabled. Init ratio, divider
5342 * to suppress GCC warning.
5343 */
5344 ratio = 0;
5345 divider = 0;
5346 break;
5347 default:
5348 DRM_ERROR("unsupported CDCLK freq %d", cdclk);
5349
5350 return;
5351 }
5352
5353 mutex_lock(&dev_priv->rps.hw_lock);
5354 /* Inform power controller of upcoming frequency change */
5355 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5356 0x80000000);
5357 mutex_unlock(&dev_priv->rps.hw_lock);
5358
5359 if (ret) {
5360 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5361 ret, cdclk);
5362 return;
5363 }
5364
5365 current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5366 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5367 current_cdclk = current_cdclk * 500 + 1000;
5368
5369 /*
5370 * DE PLL has to be disabled when
5371 * - setting to 19.2MHz (bypass, PLL isn't used)
5372 * - before setting to 624MHz (PLL needs toggling)
5373 * - before setting to any frequency from 624MHz (PLL needs toggling)
5374 */
5375 if (cdclk == 19200 || cdclk == 624000 ||
5376 current_cdclk == 624000) {
5377 bxt_de_pll_disable(dev_priv);
5378 }
5379
5380 if (cdclk != 19200) {
5381 uint32_t val;
5382
5383 bxt_de_pll_enable(dev_priv, ratio);
5384
5385 val = divider | skl_cdclk_decimal(cdclk);
5386 /*
5387 * FIXME if only the cd2x divider needs changing, it could be done
5388 * without shutting off the pipe (if only one pipe is active).
5389 */
5390 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5391 /*
5392 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5393 * enable otherwise.
5394 */
5395 if (cdclk >= 500000)
5396 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5397 I915_WRITE(CDCLK_CTL, val);
5398 }
5399
5400 mutex_lock(&dev_priv->rps.hw_lock);
5401 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5402 DIV_ROUND_UP(cdclk, 25000));
5403 mutex_unlock(&dev_priv->rps.hw_lock);
5404
5405 if (ret) {
5406 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5407 ret, cdclk);
5408 return;
5409 }
5410
5411 intel_update_cdclk(dev_priv->dev);
5412 }
5413
5414 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5415 {
5416 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5417 return false;
5418
5419 /* TODO: Check for a valid CDCLK rate */
5420
5421 return true;
5422 }
5423
5424 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5425 {
5426 return broxton_cdclk_is_enabled(dev_priv);
5427 }
5428
5429 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5430 {
5431 intel_update_cdclk(dev_priv->dev);
5432
5433 if (dev_priv->cdclk_pll.vco != 0)
5434 return;
5435
5436 /*
5437 * FIXME:
5438 * - The initial CDCLK needs to be read from VBT.
5439 * Need to make this change after VBT has changes for BXT.
5440 * - check if setting the max (or any) cdclk freq is really necessary
5441 * here, it belongs to modeset time
5442 */
5443 broxton_set_cdclk(dev_priv, 624000);
5444 }
5445
5446 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5447 {
5448 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5449 broxton_set_cdclk(dev_priv, 19200);
5450 }
5451
5452 static int skl_calc_cdclk(int max_pixclk, int vco)
5453 {
5454 if (vco == 8640000) {
5455 if (max_pixclk > 540000)
5456 return 617143;
5457 else if (max_pixclk > 432000)
5458 return 540000;
5459 else if (max_pixclk > 308571)
5460 return 432000;
5461 else
5462 return 308571;
5463 } else {
5464 if (max_pixclk > 540000)
5465 return 675000;
5466 else if (max_pixclk > 450000)
5467 return 540000;
5468 else if (max_pixclk > 337500)
5469 return 450000;
5470 else
5471 return 337500;
5472 }
5473 }
5474
5475 static void
5476 skl_dpll0_update(struct drm_i915_private *dev_priv)
5477 {
5478 u32 val;
5479
5480 dev_priv->cdclk_pll.ref = 24000;
5481
5482 val = I915_READ(LCPLL1_CTL);
5483 if ((val & LCPLL_PLL_ENABLE) == 0) {
5484 dev_priv->cdclk_pll.vco = 0;
5485 return;
5486 }
5487
5488 WARN_ON((val & LCPLL_PLL_LOCK) == 0);
5489
5490 val = I915_READ(DPLL_CTRL1);
5491
5492 WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5493 DPLL_CTRL1_SSC(SKL_DPLL0) |
5494 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5495 DPLL_CTRL1_OVERRIDE(SKL_DPLL0));
5496
5497 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5498 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5499 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5500 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5501 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5502 dev_priv->cdclk_pll.vco = 8100000;
5503 break;
5504 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5505 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5506 dev_priv->cdclk_pll.vco = 8640000;
5507 break;
5508 default:
5509 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5510 dev_priv->cdclk_pll.vco = 0;
5511 break;
5512 }
5513 }
5514
5515 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5516 {
5517 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5518
5519 dev_priv->skl_preferred_vco_freq = vco;
5520
5521 if (changed)
5522 intel_update_max_cdclk(dev_priv->dev);
5523 }
5524
5525 static void
5526 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5527 {
5528 int min_cdclk = skl_calc_cdclk(0, vco);
5529 u32 val;
5530
5531 WARN_ON(vco != 8100000 && vco != 8640000);
5532
5533 /* select the minimum CDCLK before enabling DPLL 0 */
5534 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5535 I915_WRITE(CDCLK_CTL, val);
5536 POSTING_READ(CDCLK_CTL);
5537
5538 /*
5539 * We always enable DPLL0 with the lowest link rate possible, but still
5540 * taking into account the VCO required to operate the eDP panel at the
5541 * desired frequency. The usual DP link rates operate with a VCO of
5542 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5543 * The modeset code is responsible for the selection of the exact link
5544 * rate later on, with the constraint of choosing a frequency that
5545 * works with vco.
5546 */
5547 val = I915_READ(DPLL_CTRL1);
5548
5549 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5550 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5551 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5552 if (vco == 8640000)
5553 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5554 SKL_DPLL0);
5555 else
5556 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5557 SKL_DPLL0);
5558
5559 I915_WRITE(DPLL_CTRL1, val);
5560 POSTING_READ(DPLL_CTRL1);
5561
5562 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5563
5564 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5565 DRM_ERROR("DPLL0 not locked\n");
5566
5567 dev_priv->cdclk_pll.vco = vco;
5568
5569 /* We'll want to keep using the current vco from now on. */
5570 skl_set_preferred_cdclk_vco(dev_priv, vco);
5571 }
5572
5573 static void
5574 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5575 {
5576 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5577 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5578 DRM_ERROR("Couldn't disable DPLL0\n");
5579
5580 dev_priv->cdclk_pll.vco = 0;
5581 }
5582
5583 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5584 {
5585 int ret;
5586 u32 val;
5587
5588 /* inform PCU we want to change CDCLK */
5589 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5590 mutex_lock(&dev_priv->rps.hw_lock);
5591 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5592 mutex_unlock(&dev_priv->rps.hw_lock);
5593
5594 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5595 }
5596
5597 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5598 {
5599 unsigned int i;
5600
5601 for (i = 0; i < 15; i++) {
5602 if (skl_cdclk_pcu_ready(dev_priv))
5603 return true;
5604 udelay(10);
5605 }
5606
5607 return false;
5608 }
5609
5610 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5611 {
5612 struct drm_device *dev = dev_priv->dev;
5613 u32 freq_select, pcu_ack;
5614
5615 WARN_ON((cdclk == 24000) != (vco == 0));
5616
5617 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5618
5619 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5620 DRM_ERROR("failed to inform PCU about cdclk change\n");
5621 return;
5622 }
5623
5624 /* set CDCLK_CTL */
5625 switch (cdclk) {
5626 case 450000:
5627 case 432000:
5628 freq_select = CDCLK_FREQ_450_432;
5629 pcu_ack = 1;
5630 break;
5631 case 540000:
5632 freq_select = CDCLK_FREQ_540;
5633 pcu_ack = 2;
5634 break;
5635 case 308571:
5636 case 337500:
5637 default:
5638 freq_select = CDCLK_FREQ_337_308;
5639 pcu_ack = 0;
5640 break;
5641 case 617143:
5642 case 675000:
5643 freq_select = CDCLK_FREQ_675_617;
5644 pcu_ack = 3;
5645 break;
5646 }
5647
5648 if (dev_priv->cdclk_pll.vco != 0 &&
5649 dev_priv->cdclk_pll.vco != vco)
5650 skl_dpll0_disable(dev_priv);
5651
5652 if (dev_priv->cdclk_pll.vco != vco)
5653 skl_dpll0_enable(dev_priv, vco);
5654
5655 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5656 POSTING_READ(CDCLK_CTL);
5657
5658 /* inform PCU of the change */
5659 mutex_lock(&dev_priv->rps.hw_lock);
5660 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5661 mutex_unlock(&dev_priv->rps.hw_lock);
5662
5663 intel_update_cdclk(dev);
5664 }
5665
5666 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5667
5668 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5669 {
5670 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5671 }
5672
5673 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5674 {
5675 int cdclk, vco;
5676
5677 skl_sanitize_cdclk(dev_priv);
5678
5679 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5680 /*
5681 * Use the current vco as our initial
5682 * guess as to what the preferred vco is.
5683 */
5684 if (dev_priv->skl_preferred_vco_freq == 0)
5685 skl_set_preferred_cdclk_vco(dev_priv,
5686 dev_priv->cdclk_pll.vco);
5687 return;
5688 }
5689
5690 vco = dev_priv->skl_preferred_vco_freq;
5691 if (vco == 0)
5692 vco = 8100000;
5693 cdclk = skl_calc_cdclk(0, vco);
5694
5695 skl_set_cdclk(dev_priv, cdclk, vco);
5696 }
5697
5698 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5699 {
5700 uint32_t cdctl, expected;
5701
5702 /*
5703 * check if the pre-os intialized the display
5704 * There is SWF18 scratchpad register defined which is set by the
5705 * pre-os which can be used by the OS drivers to check the status
5706 */
5707 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5708 goto sanitize;
5709
5710 /* Is PLL enabled and locked ? */
5711 if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) !=
5712 (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK))
5713 goto sanitize;
5714
5715 if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5716 DPLL_CTRL1_SSC(SKL_DPLL0) |
5717 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5718 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
5719 goto sanitize;
5720
5721 intel_update_cdclk(dev_priv->dev);
5722
5723 /* DPLL okay; verify the cdclock
5724 *
5725 * Noticed in some instances that the freq selection is correct but
5726 * decimal part is programmed wrong from BIOS where pre-os does not
5727 * enable display. Verify the same as well.
5728 */
5729 cdctl = I915_READ(CDCLK_CTL);
5730 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5731 skl_cdclk_decimal(dev_priv->cdclk_freq);
5732 if (cdctl == expected)
5733 /* All well; nothing to sanitize */
5734 return;
5735
5736 sanitize:
5737 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5738
5739 /* force cdclk programming */
5740 dev_priv->cdclk_freq = 0;
5741 /* force full PLL disable + enable */
5742 dev_priv->cdclk_pll.vco = -1;
5743 }
5744
5745 /* Adjust CDclk dividers to allow high res or save power if possible */
5746 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5747 {
5748 struct drm_i915_private *dev_priv = dev->dev_private;
5749 u32 val, cmd;
5750
5751 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5752 != dev_priv->cdclk_freq);
5753
5754 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5755 cmd = 2;
5756 else if (cdclk == 266667)
5757 cmd = 1;
5758 else
5759 cmd = 0;
5760
5761 mutex_lock(&dev_priv->rps.hw_lock);
5762 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5763 val &= ~DSPFREQGUAR_MASK;
5764 val |= (cmd << DSPFREQGUAR_SHIFT);
5765 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5766 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5767 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5768 50)) {
5769 DRM_ERROR("timed out waiting for CDclk change\n");
5770 }
5771 mutex_unlock(&dev_priv->rps.hw_lock);
5772
5773 mutex_lock(&dev_priv->sb_lock);
5774
5775 if (cdclk == 400000) {
5776 u32 divider;
5777
5778 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5779
5780 /* adjust cdclk divider */
5781 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5782 val &= ~CCK_FREQUENCY_VALUES;
5783 val |= divider;
5784 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5785
5786 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5787 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5788 50))
5789 DRM_ERROR("timed out waiting for CDclk change\n");
5790 }
5791
5792 /* adjust self-refresh exit latency value */
5793 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5794 val &= ~0x7f;
5795
5796 /*
5797 * For high bandwidth configs, we set a higher latency in the bunit
5798 * so that the core display fetch happens in time to avoid underruns.
5799 */
5800 if (cdclk == 400000)
5801 val |= 4500 / 250; /* 4.5 usec */
5802 else
5803 val |= 3000 / 250; /* 3.0 usec */
5804 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5805
5806 mutex_unlock(&dev_priv->sb_lock);
5807
5808 intel_update_cdclk(dev);
5809 }
5810
5811 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5812 {
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 u32 val, cmd;
5815
5816 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5817 != dev_priv->cdclk_freq);
5818
5819 switch (cdclk) {
5820 case 333333:
5821 case 320000:
5822 case 266667:
5823 case 200000:
5824 break;
5825 default:
5826 MISSING_CASE(cdclk);
5827 return;
5828 }
5829
5830 /*
5831 * Specs are full of misinformation, but testing on actual
5832 * hardware has shown that we just need to write the desired
5833 * CCK divider into the Punit register.
5834 */
5835 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5836
5837 mutex_lock(&dev_priv->rps.hw_lock);
5838 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5839 val &= ~DSPFREQGUAR_MASK_CHV;
5840 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5841 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5842 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5843 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5844 50)) {
5845 DRM_ERROR("timed out waiting for CDclk change\n");
5846 }
5847 mutex_unlock(&dev_priv->rps.hw_lock);
5848
5849 intel_update_cdclk(dev);
5850 }
5851
5852 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5853 int max_pixclk)
5854 {
5855 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5856 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5857
5858 /*
5859 * Really only a few cases to deal with, as only 4 CDclks are supported:
5860 * 200MHz
5861 * 267MHz
5862 * 320/333MHz (depends on HPLL freq)
5863 * 400MHz (VLV only)
5864 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5865 * of the lower bin and adjust if needed.
5866 *
5867 * We seem to get an unstable or solid color picture at 200MHz.
5868 * Not sure what's wrong. For now use 200MHz only when all pipes
5869 * are off.
5870 */
5871 if (!IS_CHERRYVIEW(dev_priv) &&
5872 max_pixclk > freq_320*limit/100)
5873 return 400000;
5874 else if (max_pixclk > 266667*limit/100)
5875 return freq_320;
5876 else if (max_pixclk > 0)
5877 return 266667;
5878 else
5879 return 200000;
5880 }
5881
5882 static int broxton_calc_cdclk(int max_pixclk)
5883 {
5884 /*
5885 * FIXME:
5886 * - set 19.2MHz bypass frequency if there are no active pipes
5887 */
5888 if (max_pixclk > 576000)
5889 return 624000;
5890 else if (max_pixclk > 384000)
5891 return 576000;
5892 else if (max_pixclk > 288000)
5893 return 384000;
5894 else if (max_pixclk > 144000)
5895 return 288000;
5896 else
5897 return 144000;
5898 }
5899
5900 /* Compute the max pixel clock for new configuration. */
5901 static int intel_mode_max_pixclk(struct drm_device *dev,
5902 struct drm_atomic_state *state)
5903 {
5904 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5905 struct drm_i915_private *dev_priv = dev->dev_private;
5906 struct drm_crtc *crtc;
5907 struct drm_crtc_state *crtc_state;
5908 unsigned max_pixclk = 0, i;
5909 enum pipe pipe;
5910
5911 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5912 sizeof(intel_state->min_pixclk));
5913
5914 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5915 int pixclk = 0;
5916
5917 if (crtc_state->enable)
5918 pixclk = crtc_state->adjusted_mode.crtc_clock;
5919
5920 intel_state->min_pixclk[i] = pixclk;
5921 }
5922
5923 for_each_pipe(dev_priv, pipe)
5924 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5925
5926 return max_pixclk;
5927 }
5928
5929 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5930 {
5931 struct drm_device *dev = state->dev;
5932 struct drm_i915_private *dev_priv = dev->dev_private;
5933 int max_pixclk = intel_mode_max_pixclk(dev, state);
5934 struct intel_atomic_state *intel_state =
5935 to_intel_atomic_state(state);
5936
5937 intel_state->cdclk = intel_state->dev_cdclk =
5938 valleyview_calc_cdclk(dev_priv, max_pixclk);
5939
5940 if (!intel_state->active_crtcs)
5941 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5942
5943 return 0;
5944 }
5945
5946 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5947 {
5948 int max_pixclk = ilk_max_pixel_rate(state);
5949 struct intel_atomic_state *intel_state =
5950 to_intel_atomic_state(state);
5951
5952 intel_state->cdclk = intel_state->dev_cdclk =
5953 broxton_calc_cdclk(max_pixclk);
5954
5955 if (!intel_state->active_crtcs)
5956 intel_state->dev_cdclk = broxton_calc_cdclk(0);
5957
5958 return 0;
5959 }
5960
5961 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5962 {
5963 unsigned int credits, default_credits;
5964
5965 if (IS_CHERRYVIEW(dev_priv))
5966 default_credits = PFI_CREDIT(12);
5967 else
5968 default_credits = PFI_CREDIT(8);
5969
5970 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5971 /* CHV suggested value is 31 or 63 */
5972 if (IS_CHERRYVIEW(dev_priv))
5973 credits = PFI_CREDIT_63;
5974 else
5975 credits = PFI_CREDIT(15);
5976 } else {
5977 credits = default_credits;
5978 }
5979
5980 /*
5981 * WA - write default credits before re-programming
5982 * FIXME: should we also set the resend bit here?
5983 */
5984 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5985 default_credits);
5986
5987 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5988 credits | PFI_CREDIT_RESEND);
5989
5990 /*
5991 * FIXME is this guaranteed to clear
5992 * immediately or should we poll for it?
5993 */
5994 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5995 }
5996
5997 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5998 {
5999 struct drm_device *dev = old_state->dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 struct intel_atomic_state *old_intel_state =
6002 to_intel_atomic_state(old_state);
6003 unsigned req_cdclk = old_intel_state->dev_cdclk;
6004
6005 /*
6006 * FIXME: We can end up here with all power domains off, yet
6007 * with a CDCLK frequency other than the minimum. To account
6008 * for this take the PIPE-A power domain, which covers the HW
6009 * blocks needed for the following programming. This can be
6010 * removed once it's guaranteed that we get here either with
6011 * the minimum CDCLK set, or the required power domains
6012 * enabled.
6013 */
6014 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6015
6016 if (IS_CHERRYVIEW(dev))
6017 cherryview_set_cdclk(dev, req_cdclk);
6018 else
6019 valleyview_set_cdclk(dev, req_cdclk);
6020
6021 vlv_program_pfi_credits(dev_priv);
6022
6023 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6024 }
6025
6026 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6027 {
6028 struct drm_device *dev = crtc->dev;
6029 struct drm_i915_private *dev_priv = to_i915(dev);
6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031 struct intel_encoder *encoder;
6032 struct intel_crtc_state *pipe_config =
6033 to_intel_crtc_state(crtc->state);
6034 int pipe = intel_crtc->pipe;
6035
6036 if (WARN_ON(intel_crtc->active))
6037 return;
6038
6039 if (intel_crtc->config->has_dp_encoder)
6040 intel_dp_set_m_n(intel_crtc, M1_N1);
6041
6042 intel_set_pipe_timings(intel_crtc);
6043 intel_set_pipe_src_size(intel_crtc);
6044
6045 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6046 struct drm_i915_private *dev_priv = dev->dev_private;
6047
6048 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6049 I915_WRITE(CHV_CANVAS(pipe), 0);
6050 }
6051
6052 i9xx_set_pipeconf(intel_crtc);
6053
6054 intel_crtc->active = true;
6055
6056 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6057
6058 for_each_encoder_on_crtc(dev, crtc, encoder)
6059 if (encoder->pre_pll_enable)
6060 encoder->pre_pll_enable(encoder);
6061
6062 if (IS_CHERRYVIEW(dev)) {
6063 chv_prepare_pll(intel_crtc, intel_crtc->config);
6064 chv_enable_pll(intel_crtc, intel_crtc->config);
6065 } else {
6066 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6067 vlv_enable_pll(intel_crtc, intel_crtc->config);
6068 }
6069
6070 for_each_encoder_on_crtc(dev, crtc, encoder)
6071 if (encoder->pre_enable)
6072 encoder->pre_enable(encoder);
6073
6074 i9xx_pfit_enable(intel_crtc);
6075
6076 intel_color_load_luts(&pipe_config->base);
6077
6078 intel_update_watermarks(crtc);
6079 intel_enable_pipe(intel_crtc);
6080
6081 assert_vblank_disabled(crtc);
6082 drm_crtc_vblank_on(crtc);
6083
6084 for_each_encoder_on_crtc(dev, crtc, encoder)
6085 encoder->enable(encoder);
6086 }
6087
6088 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6089 {
6090 struct drm_device *dev = crtc->base.dev;
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6092
6093 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6094 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6095 }
6096
6097 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6098 {
6099 struct drm_device *dev = crtc->dev;
6100 struct drm_i915_private *dev_priv = to_i915(dev);
6101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102 struct intel_encoder *encoder;
6103 struct intel_crtc_state *pipe_config =
6104 to_intel_crtc_state(crtc->state);
6105 enum pipe pipe = intel_crtc->pipe;
6106
6107 if (WARN_ON(intel_crtc->active))
6108 return;
6109
6110 i9xx_set_pll_dividers(intel_crtc);
6111
6112 if (intel_crtc->config->has_dp_encoder)
6113 intel_dp_set_m_n(intel_crtc, M1_N1);
6114
6115 intel_set_pipe_timings(intel_crtc);
6116 intel_set_pipe_src_size(intel_crtc);
6117
6118 i9xx_set_pipeconf(intel_crtc);
6119
6120 intel_crtc->active = true;
6121
6122 if (!IS_GEN2(dev))
6123 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6124
6125 for_each_encoder_on_crtc(dev, crtc, encoder)
6126 if (encoder->pre_enable)
6127 encoder->pre_enable(encoder);
6128
6129 i9xx_enable_pll(intel_crtc);
6130
6131 i9xx_pfit_enable(intel_crtc);
6132
6133 intel_color_load_luts(&pipe_config->base);
6134
6135 intel_update_watermarks(crtc);
6136 intel_enable_pipe(intel_crtc);
6137
6138 assert_vblank_disabled(crtc);
6139 drm_crtc_vblank_on(crtc);
6140
6141 for_each_encoder_on_crtc(dev, crtc, encoder)
6142 encoder->enable(encoder);
6143 }
6144
6145 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6146 {
6147 struct drm_device *dev = crtc->base.dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149
6150 if (!crtc->config->gmch_pfit.control)
6151 return;
6152
6153 assert_pipe_disabled(dev_priv, crtc->pipe);
6154
6155 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6156 I915_READ(PFIT_CONTROL));
6157 I915_WRITE(PFIT_CONTROL, 0);
6158 }
6159
6160 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6161 {
6162 struct drm_device *dev = crtc->dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165 struct intel_encoder *encoder;
6166 int pipe = intel_crtc->pipe;
6167
6168 /*
6169 * On gen2 planes are double buffered but the pipe isn't, so we must
6170 * wait for planes to fully turn off before disabling the pipe.
6171 */
6172 if (IS_GEN2(dev))
6173 intel_wait_for_vblank(dev, pipe);
6174
6175 for_each_encoder_on_crtc(dev, crtc, encoder)
6176 encoder->disable(encoder);
6177
6178 drm_crtc_vblank_off(crtc);
6179 assert_vblank_disabled(crtc);
6180
6181 intel_disable_pipe(intel_crtc);
6182
6183 i9xx_pfit_disable(intel_crtc);
6184
6185 for_each_encoder_on_crtc(dev, crtc, encoder)
6186 if (encoder->post_disable)
6187 encoder->post_disable(encoder);
6188
6189 if (!intel_crtc->config->has_dsi_encoder) {
6190 if (IS_CHERRYVIEW(dev))
6191 chv_disable_pll(dev_priv, pipe);
6192 else if (IS_VALLEYVIEW(dev))
6193 vlv_disable_pll(dev_priv, pipe);
6194 else
6195 i9xx_disable_pll(intel_crtc);
6196 }
6197
6198 for_each_encoder_on_crtc(dev, crtc, encoder)
6199 if (encoder->post_pll_disable)
6200 encoder->post_pll_disable(encoder);
6201
6202 if (!IS_GEN2(dev))
6203 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6204 }
6205
6206 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6207 {
6208 struct intel_encoder *encoder;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6211 enum intel_display_power_domain domain;
6212 unsigned long domains;
6213
6214 if (!intel_crtc->active)
6215 return;
6216
6217 if (to_intel_plane_state(crtc->primary->state)->visible) {
6218 WARN_ON(list_empty(&intel_crtc->flip_work));
6219
6220 intel_pre_disable_primary_noatomic(crtc);
6221
6222 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6223 to_intel_plane_state(crtc->primary->state)->visible = false;
6224 }
6225
6226 dev_priv->display.crtc_disable(crtc);
6227
6228 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6229 crtc->base.id);
6230
6231 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6232 crtc->state->active = false;
6233 intel_crtc->active = false;
6234 crtc->enabled = false;
6235 crtc->state->connector_mask = 0;
6236 crtc->state->encoder_mask = 0;
6237
6238 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6239 encoder->base.crtc = NULL;
6240
6241 intel_fbc_disable(intel_crtc);
6242 intel_update_watermarks(crtc);
6243 intel_disable_shared_dpll(intel_crtc);
6244
6245 domains = intel_crtc->enabled_power_domains;
6246 for_each_power_domain(domain, domains)
6247 intel_display_power_put(dev_priv, domain);
6248 intel_crtc->enabled_power_domains = 0;
6249
6250 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6251 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6252 }
6253
6254 /*
6255 * turn all crtc's off, but do not adjust state
6256 * This has to be paired with a call to intel_modeset_setup_hw_state.
6257 */
6258 int intel_display_suspend(struct drm_device *dev)
6259 {
6260 struct drm_i915_private *dev_priv = to_i915(dev);
6261 struct drm_atomic_state *state;
6262 int ret;
6263
6264 state = drm_atomic_helper_suspend(dev);
6265 ret = PTR_ERR_OR_ZERO(state);
6266 if (ret)
6267 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6268 else
6269 dev_priv->modeset_restore_state = state;
6270
6271 /*
6272 * Make sure all unpin_work completes before returning.
6273 */
6274 flush_workqueue(dev_priv->wq);
6275
6276 return ret;
6277 }
6278
6279 void intel_encoder_destroy(struct drm_encoder *encoder)
6280 {
6281 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6282
6283 drm_encoder_cleanup(encoder);
6284 kfree(intel_encoder);
6285 }
6286
6287 /* Cross check the actual hw state with our own modeset state tracking (and it's
6288 * internal consistency). */
6289 static void intel_connector_verify_state(struct intel_connector *connector,
6290 struct drm_connector_state *conn_state)
6291 {
6292 struct drm_crtc *crtc = conn_state->crtc;
6293
6294 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6295 connector->base.base.id,
6296 connector->base.name);
6297
6298 if (connector->get_hw_state(connector)) {
6299 struct intel_encoder *encoder = connector->encoder;
6300
6301 I915_STATE_WARN(!crtc,
6302 "connector enabled without attached crtc\n");
6303
6304 if (!crtc)
6305 return;
6306
6307 I915_STATE_WARN(!crtc->state->active,
6308 "connector is active, but attached crtc isn't\n");
6309
6310 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6311 return;
6312
6313 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6314 "atomic encoder doesn't match attached encoder\n");
6315
6316 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6317 "attached encoder crtc differs from connector crtc\n");
6318 } else {
6319 I915_STATE_WARN(crtc && crtc->state->active,
6320 "attached crtc is active, but connector isn't\n");
6321 I915_STATE_WARN(!crtc && conn_state->best_encoder,
6322 "best encoder set without crtc!\n");
6323 }
6324 }
6325
6326 int intel_connector_init(struct intel_connector *connector)
6327 {
6328 drm_atomic_helper_connector_reset(&connector->base);
6329
6330 if (!connector->base.state)
6331 return -ENOMEM;
6332
6333 return 0;
6334 }
6335
6336 struct intel_connector *intel_connector_alloc(void)
6337 {
6338 struct intel_connector *connector;
6339
6340 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6341 if (!connector)
6342 return NULL;
6343
6344 if (intel_connector_init(connector) < 0) {
6345 kfree(connector);
6346 return NULL;
6347 }
6348
6349 return connector;
6350 }
6351
6352 /* Simple connector->get_hw_state implementation for encoders that support only
6353 * one connector and no cloning and hence the encoder state determines the state
6354 * of the connector. */
6355 bool intel_connector_get_hw_state(struct intel_connector *connector)
6356 {
6357 enum pipe pipe = 0;
6358 struct intel_encoder *encoder = connector->encoder;
6359
6360 return encoder->get_hw_state(encoder, &pipe);
6361 }
6362
6363 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6364 {
6365 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6366 return crtc_state->fdi_lanes;
6367
6368 return 0;
6369 }
6370
6371 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6372 struct intel_crtc_state *pipe_config)
6373 {
6374 struct drm_atomic_state *state = pipe_config->base.state;
6375 struct intel_crtc *other_crtc;
6376 struct intel_crtc_state *other_crtc_state;
6377
6378 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6379 pipe_name(pipe), pipe_config->fdi_lanes);
6380 if (pipe_config->fdi_lanes > 4) {
6381 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6382 pipe_name(pipe), pipe_config->fdi_lanes);
6383 return -EINVAL;
6384 }
6385
6386 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6387 if (pipe_config->fdi_lanes > 2) {
6388 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6389 pipe_config->fdi_lanes);
6390 return -EINVAL;
6391 } else {
6392 return 0;
6393 }
6394 }
6395
6396 if (INTEL_INFO(dev)->num_pipes == 2)
6397 return 0;
6398
6399 /* Ivybridge 3 pipe is really complicated */
6400 switch (pipe) {
6401 case PIPE_A:
6402 return 0;
6403 case PIPE_B:
6404 if (pipe_config->fdi_lanes <= 2)
6405 return 0;
6406
6407 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6408 other_crtc_state =
6409 intel_atomic_get_crtc_state(state, other_crtc);
6410 if (IS_ERR(other_crtc_state))
6411 return PTR_ERR(other_crtc_state);
6412
6413 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6414 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6415 pipe_name(pipe), pipe_config->fdi_lanes);
6416 return -EINVAL;
6417 }
6418 return 0;
6419 case PIPE_C:
6420 if (pipe_config->fdi_lanes > 2) {
6421 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6422 pipe_name(pipe), pipe_config->fdi_lanes);
6423 return -EINVAL;
6424 }
6425
6426 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6427 other_crtc_state =
6428 intel_atomic_get_crtc_state(state, other_crtc);
6429 if (IS_ERR(other_crtc_state))
6430 return PTR_ERR(other_crtc_state);
6431
6432 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6433 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6434 return -EINVAL;
6435 }
6436 return 0;
6437 default:
6438 BUG();
6439 }
6440 }
6441
6442 #define RETRY 1
6443 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6444 struct intel_crtc_state *pipe_config)
6445 {
6446 struct drm_device *dev = intel_crtc->base.dev;
6447 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6448 int lane, link_bw, fdi_dotclock, ret;
6449 bool needs_recompute = false;
6450
6451 retry:
6452 /* FDI is a binary signal running at ~2.7GHz, encoding
6453 * each output octet as 10 bits. The actual frequency
6454 * is stored as a divider into a 100MHz clock, and the
6455 * mode pixel clock is stored in units of 1KHz.
6456 * Hence the bw of each lane in terms of the mode signal
6457 * is:
6458 */
6459 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6460
6461 fdi_dotclock = adjusted_mode->crtc_clock;
6462
6463 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6464 pipe_config->pipe_bpp);
6465
6466 pipe_config->fdi_lanes = lane;
6467
6468 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6469 link_bw, &pipe_config->fdi_m_n);
6470
6471 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6472 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6473 pipe_config->pipe_bpp -= 2*3;
6474 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6475 pipe_config->pipe_bpp);
6476 needs_recompute = true;
6477 pipe_config->bw_constrained = true;
6478
6479 goto retry;
6480 }
6481
6482 if (needs_recompute)
6483 return RETRY;
6484
6485 return ret;
6486 }
6487
6488 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6489 struct intel_crtc_state *pipe_config)
6490 {
6491 if (pipe_config->pipe_bpp > 24)
6492 return false;
6493
6494 /* HSW can handle pixel rate up to cdclk? */
6495 if (IS_HASWELL(dev_priv))
6496 return true;
6497
6498 /*
6499 * We compare against max which means we must take
6500 * the increased cdclk requirement into account when
6501 * calculating the new cdclk.
6502 *
6503 * Should measure whether using a lower cdclk w/o IPS
6504 */
6505 return ilk_pipe_pixel_rate(pipe_config) <=
6506 dev_priv->max_cdclk_freq * 95 / 100;
6507 }
6508
6509 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6510 struct intel_crtc_state *pipe_config)
6511 {
6512 struct drm_device *dev = crtc->base.dev;
6513 struct drm_i915_private *dev_priv = dev->dev_private;
6514
6515 pipe_config->ips_enabled = i915.enable_ips &&
6516 hsw_crtc_supports_ips(crtc) &&
6517 pipe_config_supports_ips(dev_priv, pipe_config);
6518 }
6519
6520 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6521 {
6522 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6523
6524 /* GDG double wide on either pipe, otherwise pipe A only */
6525 return INTEL_INFO(dev_priv)->gen < 4 &&
6526 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6527 }
6528
6529 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6530 struct intel_crtc_state *pipe_config)
6531 {
6532 struct drm_device *dev = crtc->base.dev;
6533 struct drm_i915_private *dev_priv = dev->dev_private;
6534 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6535
6536 /* FIXME should check pixel clock limits on all platforms */
6537 if (INTEL_INFO(dev)->gen < 4) {
6538 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6539
6540 /*
6541 * Enable double wide mode when the dot clock
6542 * is > 90% of the (display) core speed.
6543 */
6544 if (intel_crtc_supports_double_wide(crtc) &&
6545 adjusted_mode->crtc_clock > clock_limit) {
6546 clock_limit *= 2;
6547 pipe_config->double_wide = true;
6548 }
6549
6550 if (adjusted_mode->crtc_clock > clock_limit) {
6551 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6552 adjusted_mode->crtc_clock, clock_limit,
6553 yesno(pipe_config->double_wide));
6554 return -EINVAL;
6555 }
6556 }
6557
6558 /*
6559 * Pipe horizontal size must be even in:
6560 * - DVO ganged mode
6561 * - LVDS dual channel mode
6562 * - Double wide pipe
6563 */
6564 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6565 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6566 pipe_config->pipe_src_w &= ~1;
6567
6568 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6569 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6570 */
6571 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6572 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6573 return -EINVAL;
6574
6575 if (HAS_IPS(dev))
6576 hsw_compute_ips_config(crtc, pipe_config);
6577
6578 if (pipe_config->has_pch_encoder)
6579 return ironlake_fdi_compute_config(crtc, pipe_config);
6580
6581 return 0;
6582 }
6583
6584 static int skylake_get_display_clock_speed(struct drm_device *dev)
6585 {
6586 struct drm_i915_private *dev_priv = to_i915(dev);
6587 uint32_t cdctl;
6588
6589 skl_dpll0_update(dev_priv);
6590
6591 if (dev_priv->cdclk_pll.vco == 0)
6592 return dev_priv->cdclk_pll.ref;
6593
6594 cdctl = I915_READ(CDCLK_CTL);
6595
6596 if (dev_priv->cdclk_pll.vco == 8640000) {
6597 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6598 case CDCLK_FREQ_450_432:
6599 return 432000;
6600 case CDCLK_FREQ_337_308:
6601 return 308571;
6602 case CDCLK_FREQ_540:
6603 return 540000;
6604 case CDCLK_FREQ_675_617:
6605 return 617143;
6606 default:
6607 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6608 }
6609 } else {
6610 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6611 case CDCLK_FREQ_450_432:
6612 return 450000;
6613 case CDCLK_FREQ_337_308:
6614 return 337500;
6615 case CDCLK_FREQ_540:
6616 return 540000;
6617 case CDCLK_FREQ_675_617:
6618 return 675000;
6619 default:
6620 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6621 }
6622 }
6623
6624 return dev_priv->cdclk_pll.ref;
6625 }
6626
6627 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6628 {
6629 u32 val;
6630
6631 dev_priv->cdclk_pll.ref = 19200;
6632
6633 val = I915_READ(BXT_DE_PLL_ENABLE);
6634 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) {
6635 dev_priv->cdclk_pll.vco = 0;
6636 return;
6637 }
6638
6639 WARN_ON((val & BXT_DE_PLL_LOCK) == 0);
6640
6641 val = I915_READ(BXT_DE_PLL_CTL);
6642 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6643 dev_priv->cdclk_pll.ref;
6644 }
6645
6646 static int broxton_get_display_clock_speed(struct drm_device *dev)
6647 {
6648 struct drm_i915_private *dev_priv = to_i915(dev);
6649 u32 divider;
6650 int div, vco;
6651
6652 bxt_de_pll_update(dev_priv);
6653
6654 vco = dev_priv->cdclk_pll.vco;
6655 if (vco == 0)
6656 return dev_priv->cdclk_pll.ref;
6657
6658 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6659
6660 switch (divider) {
6661 case BXT_CDCLK_CD2X_DIV_SEL_1:
6662 div = 2;
6663 break;
6664 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6665 div = 3;
6666 break;
6667 case BXT_CDCLK_CD2X_DIV_SEL_2:
6668 div = 4;
6669 break;
6670 case BXT_CDCLK_CD2X_DIV_SEL_4:
6671 div = 8;
6672 break;
6673 default:
6674 MISSING_CASE(divider);
6675 return dev_priv->cdclk_pll.ref;
6676 }
6677
6678 return DIV_ROUND_CLOSEST(vco, div);
6679 }
6680
6681 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6682 {
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684 uint32_t lcpll = I915_READ(LCPLL_CTL);
6685 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6686
6687 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6688 return 800000;
6689 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6690 return 450000;
6691 else if (freq == LCPLL_CLK_FREQ_450)
6692 return 450000;
6693 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6694 return 540000;
6695 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6696 return 337500;
6697 else
6698 return 675000;
6699 }
6700
6701 static int haswell_get_display_clock_speed(struct drm_device *dev)
6702 {
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 uint32_t lcpll = I915_READ(LCPLL_CTL);
6705 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6706
6707 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6708 return 800000;
6709 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6710 return 450000;
6711 else if (freq == LCPLL_CLK_FREQ_450)
6712 return 450000;
6713 else if (IS_HSW_ULT(dev))
6714 return 337500;
6715 else
6716 return 540000;
6717 }
6718
6719 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6720 {
6721 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6722 CCK_DISPLAY_CLOCK_CONTROL);
6723 }
6724
6725 static int ilk_get_display_clock_speed(struct drm_device *dev)
6726 {
6727 return 450000;
6728 }
6729
6730 static int i945_get_display_clock_speed(struct drm_device *dev)
6731 {
6732 return 400000;
6733 }
6734
6735 static int i915_get_display_clock_speed(struct drm_device *dev)
6736 {
6737 return 333333;
6738 }
6739
6740 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6741 {
6742 return 200000;
6743 }
6744
6745 static int pnv_get_display_clock_speed(struct drm_device *dev)
6746 {
6747 u16 gcfgc = 0;
6748
6749 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6750
6751 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6752 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6753 return 266667;
6754 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6755 return 333333;
6756 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6757 return 444444;
6758 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6759 return 200000;
6760 default:
6761 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6762 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6763 return 133333;
6764 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6765 return 166667;
6766 }
6767 }
6768
6769 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6770 {
6771 u16 gcfgc = 0;
6772
6773 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6774
6775 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6776 return 133333;
6777 else {
6778 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6779 case GC_DISPLAY_CLOCK_333_MHZ:
6780 return 333333;
6781 default:
6782 case GC_DISPLAY_CLOCK_190_200_MHZ:
6783 return 190000;
6784 }
6785 }
6786 }
6787
6788 static int i865_get_display_clock_speed(struct drm_device *dev)
6789 {
6790 return 266667;
6791 }
6792
6793 static int i85x_get_display_clock_speed(struct drm_device *dev)
6794 {
6795 u16 hpllcc = 0;
6796
6797 /*
6798 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6799 * encoding is different :(
6800 * FIXME is this the right way to detect 852GM/852GMV?
6801 */
6802 if (dev->pdev->revision == 0x1)
6803 return 133333;
6804
6805 pci_bus_read_config_word(dev->pdev->bus,
6806 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6807
6808 /* Assume that the hardware is in the high speed state. This
6809 * should be the default.
6810 */
6811 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6812 case GC_CLOCK_133_200:
6813 case GC_CLOCK_133_200_2:
6814 case GC_CLOCK_100_200:
6815 return 200000;
6816 case GC_CLOCK_166_250:
6817 return 250000;
6818 case GC_CLOCK_100_133:
6819 return 133333;
6820 case GC_CLOCK_133_266:
6821 case GC_CLOCK_133_266_2:
6822 case GC_CLOCK_166_266:
6823 return 266667;
6824 }
6825
6826 /* Shouldn't happen */
6827 return 0;
6828 }
6829
6830 static int i830_get_display_clock_speed(struct drm_device *dev)
6831 {
6832 return 133333;
6833 }
6834
6835 static unsigned int intel_hpll_vco(struct drm_device *dev)
6836 {
6837 struct drm_i915_private *dev_priv = dev->dev_private;
6838 static const unsigned int blb_vco[8] = {
6839 [0] = 3200000,
6840 [1] = 4000000,
6841 [2] = 5333333,
6842 [3] = 4800000,
6843 [4] = 6400000,
6844 };
6845 static const unsigned int pnv_vco[8] = {
6846 [0] = 3200000,
6847 [1] = 4000000,
6848 [2] = 5333333,
6849 [3] = 4800000,
6850 [4] = 2666667,
6851 };
6852 static const unsigned int cl_vco[8] = {
6853 [0] = 3200000,
6854 [1] = 4000000,
6855 [2] = 5333333,
6856 [3] = 6400000,
6857 [4] = 3333333,
6858 [5] = 3566667,
6859 [6] = 4266667,
6860 };
6861 static const unsigned int elk_vco[8] = {
6862 [0] = 3200000,
6863 [1] = 4000000,
6864 [2] = 5333333,
6865 [3] = 4800000,
6866 };
6867 static const unsigned int ctg_vco[8] = {
6868 [0] = 3200000,
6869 [1] = 4000000,
6870 [2] = 5333333,
6871 [3] = 6400000,
6872 [4] = 2666667,
6873 [5] = 4266667,
6874 };
6875 const unsigned int *vco_table;
6876 unsigned int vco;
6877 uint8_t tmp = 0;
6878
6879 /* FIXME other chipsets? */
6880 if (IS_GM45(dev))
6881 vco_table = ctg_vco;
6882 else if (IS_G4X(dev))
6883 vco_table = elk_vco;
6884 else if (IS_CRESTLINE(dev))
6885 vco_table = cl_vco;
6886 else if (IS_PINEVIEW(dev))
6887 vco_table = pnv_vco;
6888 else if (IS_G33(dev))
6889 vco_table = blb_vco;
6890 else
6891 return 0;
6892
6893 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6894
6895 vco = vco_table[tmp & 0x7];
6896 if (vco == 0)
6897 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6898 else
6899 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6900
6901 return vco;
6902 }
6903
6904 static int gm45_get_display_clock_speed(struct drm_device *dev)
6905 {
6906 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6907 uint16_t tmp = 0;
6908
6909 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6910
6911 cdclk_sel = (tmp >> 12) & 0x1;
6912
6913 switch (vco) {
6914 case 2666667:
6915 case 4000000:
6916 case 5333333:
6917 return cdclk_sel ? 333333 : 222222;
6918 case 3200000:
6919 return cdclk_sel ? 320000 : 228571;
6920 default:
6921 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6922 return 222222;
6923 }
6924 }
6925
6926 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6927 {
6928 static const uint8_t div_3200[] = { 16, 10, 8 };
6929 static const uint8_t div_4000[] = { 20, 12, 10 };
6930 static const uint8_t div_5333[] = { 24, 16, 14 };
6931 const uint8_t *div_table;
6932 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6933 uint16_t tmp = 0;
6934
6935 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6936
6937 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6938
6939 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6940 goto fail;
6941
6942 switch (vco) {
6943 case 3200000:
6944 div_table = div_3200;
6945 break;
6946 case 4000000:
6947 div_table = div_4000;
6948 break;
6949 case 5333333:
6950 div_table = div_5333;
6951 break;
6952 default:
6953 goto fail;
6954 }
6955
6956 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6957
6958 fail:
6959 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6960 return 200000;
6961 }
6962
6963 static int g33_get_display_clock_speed(struct drm_device *dev)
6964 {
6965 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6966 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6967 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6968 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6969 const uint8_t *div_table;
6970 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6971 uint16_t tmp = 0;
6972
6973 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6974
6975 cdclk_sel = (tmp >> 4) & 0x7;
6976
6977 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6978 goto fail;
6979
6980 switch (vco) {
6981 case 3200000:
6982 div_table = div_3200;
6983 break;
6984 case 4000000:
6985 div_table = div_4000;
6986 break;
6987 case 4800000:
6988 div_table = div_4800;
6989 break;
6990 case 5333333:
6991 div_table = div_5333;
6992 break;
6993 default:
6994 goto fail;
6995 }
6996
6997 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6998
6999 fail:
7000 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7001 return 190476;
7002 }
7003
7004 static void
7005 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7006 {
7007 while (*num > DATA_LINK_M_N_MASK ||
7008 *den > DATA_LINK_M_N_MASK) {
7009 *num >>= 1;
7010 *den >>= 1;
7011 }
7012 }
7013
7014 static void compute_m_n(unsigned int m, unsigned int n,
7015 uint32_t *ret_m, uint32_t *ret_n)
7016 {
7017 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7018 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7019 intel_reduce_m_n_ratio(ret_m, ret_n);
7020 }
7021
7022 void
7023 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7024 int pixel_clock, int link_clock,
7025 struct intel_link_m_n *m_n)
7026 {
7027 m_n->tu = 64;
7028
7029 compute_m_n(bits_per_pixel * pixel_clock,
7030 link_clock * nlanes * 8,
7031 &m_n->gmch_m, &m_n->gmch_n);
7032
7033 compute_m_n(pixel_clock, link_clock,
7034 &m_n->link_m, &m_n->link_n);
7035 }
7036
7037 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7038 {
7039 if (i915.panel_use_ssc >= 0)
7040 return i915.panel_use_ssc != 0;
7041 return dev_priv->vbt.lvds_use_ssc
7042 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7043 }
7044
7045 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7046 {
7047 return (1 << dpll->n) << 16 | dpll->m2;
7048 }
7049
7050 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7051 {
7052 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7053 }
7054
7055 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7056 struct intel_crtc_state *crtc_state,
7057 struct dpll *reduced_clock)
7058 {
7059 struct drm_device *dev = crtc->base.dev;
7060 u32 fp, fp2 = 0;
7061
7062 if (IS_PINEVIEW(dev)) {
7063 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7064 if (reduced_clock)
7065 fp2 = pnv_dpll_compute_fp(reduced_clock);
7066 } else {
7067 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7068 if (reduced_clock)
7069 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7070 }
7071
7072 crtc_state->dpll_hw_state.fp0 = fp;
7073
7074 crtc->lowfreq_avail = false;
7075 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7076 reduced_clock) {
7077 crtc_state->dpll_hw_state.fp1 = fp2;
7078 crtc->lowfreq_avail = true;
7079 } else {
7080 crtc_state->dpll_hw_state.fp1 = fp;
7081 }
7082 }
7083
7084 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7085 pipe)
7086 {
7087 u32 reg_val;
7088
7089 /*
7090 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7091 * and set it to a reasonable value instead.
7092 */
7093 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7094 reg_val &= 0xffffff00;
7095 reg_val |= 0x00000030;
7096 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7097
7098 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7099 reg_val &= 0x8cffffff;
7100 reg_val = 0x8c000000;
7101 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7102
7103 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7104 reg_val &= 0xffffff00;
7105 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7106
7107 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7108 reg_val &= 0x00ffffff;
7109 reg_val |= 0xb0000000;
7110 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7111 }
7112
7113 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7114 struct intel_link_m_n *m_n)
7115 {
7116 struct drm_device *dev = crtc->base.dev;
7117 struct drm_i915_private *dev_priv = dev->dev_private;
7118 int pipe = crtc->pipe;
7119
7120 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7121 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7122 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7123 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7124 }
7125
7126 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7127 struct intel_link_m_n *m_n,
7128 struct intel_link_m_n *m2_n2)
7129 {
7130 struct drm_device *dev = crtc->base.dev;
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 int pipe = crtc->pipe;
7133 enum transcoder transcoder = crtc->config->cpu_transcoder;
7134
7135 if (INTEL_INFO(dev)->gen >= 5) {
7136 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7137 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7138 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7139 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7140 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7141 * for gen < 8) and if DRRS is supported (to make sure the
7142 * registers are not unnecessarily accessed).
7143 */
7144 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7145 crtc->config->has_drrs) {
7146 I915_WRITE(PIPE_DATA_M2(transcoder),
7147 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7148 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7149 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7150 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7151 }
7152 } else {
7153 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7154 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7155 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7156 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7157 }
7158 }
7159
7160 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7161 {
7162 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7163
7164 if (m_n == M1_N1) {
7165 dp_m_n = &crtc->config->dp_m_n;
7166 dp_m2_n2 = &crtc->config->dp_m2_n2;
7167 } else if (m_n == M2_N2) {
7168
7169 /*
7170 * M2_N2 registers are not supported. Hence m2_n2 divider value
7171 * needs to be programmed into M1_N1.
7172 */
7173 dp_m_n = &crtc->config->dp_m2_n2;
7174 } else {
7175 DRM_ERROR("Unsupported divider value\n");
7176 return;
7177 }
7178
7179 if (crtc->config->has_pch_encoder)
7180 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7181 else
7182 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7183 }
7184
7185 static void vlv_compute_dpll(struct intel_crtc *crtc,
7186 struct intel_crtc_state *pipe_config)
7187 {
7188 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7189 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7190 if (crtc->pipe != PIPE_A)
7191 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7192
7193 /* DPLL not used with DSI, but still need the rest set up */
7194 if (!pipe_config->has_dsi_encoder)
7195 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7196 DPLL_EXT_BUFFER_ENABLE_VLV;
7197
7198 pipe_config->dpll_hw_state.dpll_md =
7199 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7200 }
7201
7202 static void chv_compute_dpll(struct intel_crtc *crtc,
7203 struct intel_crtc_state *pipe_config)
7204 {
7205 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7206 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7207 if (crtc->pipe != PIPE_A)
7208 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7209
7210 /* DPLL not used with DSI, but still need the rest set up */
7211 if (!pipe_config->has_dsi_encoder)
7212 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7213
7214 pipe_config->dpll_hw_state.dpll_md =
7215 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7216 }
7217
7218 static void vlv_prepare_pll(struct intel_crtc *crtc,
7219 const struct intel_crtc_state *pipe_config)
7220 {
7221 struct drm_device *dev = crtc->base.dev;
7222 struct drm_i915_private *dev_priv = dev->dev_private;
7223 enum pipe pipe = crtc->pipe;
7224 u32 mdiv;
7225 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7226 u32 coreclk, reg_val;
7227
7228 /* Enable Refclk */
7229 I915_WRITE(DPLL(pipe),
7230 pipe_config->dpll_hw_state.dpll &
7231 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7232
7233 /* No need to actually set up the DPLL with DSI */
7234 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7235 return;
7236
7237 mutex_lock(&dev_priv->sb_lock);
7238
7239 bestn = pipe_config->dpll.n;
7240 bestm1 = pipe_config->dpll.m1;
7241 bestm2 = pipe_config->dpll.m2;
7242 bestp1 = pipe_config->dpll.p1;
7243 bestp2 = pipe_config->dpll.p2;
7244
7245 /* See eDP HDMI DPIO driver vbios notes doc */
7246
7247 /* PLL B needs special handling */
7248 if (pipe == PIPE_B)
7249 vlv_pllb_recal_opamp(dev_priv, pipe);
7250
7251 /* Set up Tx target for periodic Rcomp update */
7252 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7253
7254 /* Disable target IRef on PLL */
7255 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7256 reg_val &= 0x00ffffff;
7257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7258
7259 /* Disable fast lock */
7260 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7261
7262 /* Set idtafcrecal before PLL is enabled */
7263 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7264 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7265 mdiv |= ((bestn << DPIO_N_SHIFT));
7266 mdiv |= (1 << DPIO_K_SHIFT);
7267
7268 /*
7269 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7270 * but we don't support that).
7271 * Note: don't use the DAC post divider as it seems unstable.
7272 */
7273 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7275
7276 mdiv |= DPIO_ENABLE_CALIBRATION;
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7278
7279 /* Set HBR and RBR LPF coefficients */
7280 if (pipe_config->port_clock == 162000 ||
7281 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7282 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7284 0x009f0003);
7285 else
7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7287 0x00d0000f);
7288
7289 if (pipe_config->has_dp_encoder) {
7290 /* Use SSC source */
7291 if (pipe == PIPE_A)
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7293 0x0df40000);
7294 else
7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7296 0x0df70000);
7297 } else { /* HDMI or VGA */
7298 /* Use bend source */
7299 if (pipe == PIPE_A)
7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7301 0x0df70000);
7302 else
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7304 0x0df40000);
7305 }
7306
7307 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7308 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7309 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7311 coreclk |= 0x01000000;
7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7313
7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7315 mutex_unlock(&dev_priv->sb_lock);
7316 }
7317
7318 static void chv_prepare_pll(struct intel_crtc *crtc,
7319 const struct intel_crtc_state *pipe_config)
7320 {
7321 struct drm_device *dev = crtc->base.dev;
7322 struct drm_i915_private *dev_priv = dev->dev_private;
7323 enum pipe pipe = crtc->pipe;
7324 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7325 u32 loopfilter, tribuf_calcntr;
7326 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7327 u32 dpio_val;
7328 int vco;
7329
7330 /* Enable Refclk and SSC */
7331 I915_WRITE(DPLL(pipe),
7332 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7333
7334 /* No need to actually set up the DPLL with DSI */
7335 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7336 return;
7337
7338 bestn = pipe_config->dpll.n;
7339 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7340 bestm1 = pipe_config->dpll.m1;
7341 bestm2 = pipe_config->dpll.m2 >> 22;
7342 bestp1 = pipe_config->dpll.p1;
7343 bestp2 = pipe_config->dpll.p2;
7344 vco = pipe_config->dpll.vco;
7345 dpio_val = 0;
7346 loopfilter = 0;
7347
7348 mutex_lock(&dev_priv->sb_lock);
7349
7350 /* p1 and p2 divider */
7351 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7352 5 << DPIO_CHV_S1_DIV_SHIFT |
7353 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7354 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7355 1 << DPIO_CHV_K_DIV_SHIFT);
7356
7357 /* Feedback post-divider - m2 */
7358 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7359
7360 /* Feedback refclk divider - n and m1 */
7361 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7362 DPIO_CHV_M1_DIV_BY_2 |
7363 1 << DPIO_CHV_N_DIV_SHIFT);
7364
7365 /* M2 fraction division */
7366 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7367
7368 /* M2 fraction division enable */
7369 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7370 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7371 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7372 if (bestm2_frac)
7373 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7374 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7375
7376 /* Program digital lock detect threshold */
7377 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7378 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7379 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7380 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7381 if (!bestm2_frac)
7382 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7383 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7384
7385 /* Loop filter */
7386 if (vco == 5400000) {
7387 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7388 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7389 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7390 tribuf_calcntr = 0x9;
7391 } else if (vco <= 6200000) {
7392 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7393 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7394 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7395 tribuf_calcntr = 0x9;
7396 } else if (vco <= 6480000) {
7397 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7398 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7399 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7400 tribuf_calcntr = 0x8;
7401 } else {
7402 /* Not supported. Apply the same limits as in the max case */
7403 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7404 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7405 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7406 tribuf_calcntr = 0;
7407 }
7408 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7409
7410 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7411 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7412 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7413 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7414
7415 /* AFC Recal */
7416 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7417 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7418 DPIO_AFC_RECAL);
7419
7420 mutex_unlock(&dev_priv->sb_lock);
7421 }
7422
7423 /**
7424 * vlv_force_pll_on - forcibly enable just the PLL
7425 * @dev_priv: i915 private structure
7426 * @pipe: pipe PLL to enable
7427 * @dpll: PLL configuration
7428 *
7429 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7430 * in cases where we need the PLL enabled even when @pipe is not going to
7431 * be enabled.
7432 */
7433 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7434 const struct dpll *dpll)
7435 {
7436 struct intel_crtc *crtc =
7437 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7438 struct intel_crtc_state *pipe_config;
7439
7440 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7441 if (!pipe_config)
7442 return -ENOMEM;
7443
7444 pipe_config->base.crtc = &crtc->base;
7445 pipe_config->pixel_multiplier = 1;
7446 pipe_config->dpll = *dpll;
7447
7448 if (IS_CHERRYVIEW(dev)) {
7449 chv_compute_dpll(crtc, pipe_config);
7450 chv_prepare_pll(crtc, pipe_config);
7451 chv_enable_pll(crtc, pipe_config);
7452 } else {
7453 vlv_compute_dpll(crtc, pipe_config);
7454 vlv_prepare_pll(crtc, pipe_config);
7455 vlv_enable_pll(crtc, pipe_config);
7456 }
7457
7458 kfree(pipe_config);
7459
7460 return 0;
7461 }
7462
7463 /**
7464 * vlv_force_pll_off - forcibly disable just the PLL
7465 * @dev_priv: i915 private structure
7466 * @pipe: pipe PLL to disable
7467 *
7468 * Disable the PLL for @pipe. To be used in cases where we need
7469 * the PLL enabled even when @pipe is not going to be enabled.
7470 */
7471 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7472 {
7473 if (IS_CHERRYVIEW(dev))
7474 chv_disable_pll(to_i915(dev), pipe);
7475 else
7476 vlv_disable_pll(to_i915(dev), pipe);
7477 }
7478
7479 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7480 struct intel_crtc_state *crtc_state,
7481 struct dpll *reduced_clock)
7482 {
7483 struct drm_device *dev = crtc->base.dev;
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485 u32 dpll;
7486 bool is_sdvo;
7487 struct dpll *clock = &crtc_state->dpll;
7488
7489 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7490
7491 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7492 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7493
7494 dpll = DPLL_VGA_MODE_DIS;
7495
7496 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7497 dpll |= DPLLB_MODE_LVDS;
7498 else
7499 dpll |= DPLLB_MODE_DAC_SERIAL;
7500
7501 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7502 dpll |= (crtc_state->pixel_multiplier - 1)
7503 << SDVO_MULTIPLIER_SHIFT_HIRES;
7504 }
7505
7506 if (is_sdvo)
7507 dpll |= DPLL_SDVO_HIGH_SPEED;
7508
7509 if (crtc_state->has_dp_encoder)
7510 dpll |= DPLL_SDVO_HIGH_SPEED;
7511
7512 /* compute bitmask from p1 value */
7513 if (IS_PINEVIEW(dev))
7514 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7515 else {
7516 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7517 if (IS_G4X(dev) && reduced_clock)
7518 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7519 }
7520 switch (clock->p2) {
7521 case 5:
7522 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7523 break;
7524 case 7:
7525 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7526 break;
7527 case 10:
7528 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7529 break;
7530 case 14:
7531 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7532 break;
7533 }
7534 if (INTEL_INFO(dev)->gen >= 4)
7535 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7536
7537 if (crtc_state->sdvo_tv_clock)
7538 dpll |= PLL_REF_INPUT_TVCLKINBC;
7539 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7540 intel_panel_use_ssc(dev_priv))
7541 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7542 else
7543 dpll |= PLL_REF_INPUT_DREFCLK;
7544
7545 dpll |= DPLL_VCO_ENABLE;
7546 crtc_state->dpll_hw_state.dpll = dpll;
7547
7548 if (INTEL_INFO(dev)->gen >= 4) {
7549 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7550 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7551 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7552 }
7553 }
7554
7555 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7556 struct intel_crtc_state *crtc_state,
7557 struct dpll *reduced_clock)
7558 {
7559 struct drm_device *dev = crtc->base.dev;
7560 struct drm_i915_private *dev_priv = dev->dev_private;
7561 u32 dpll;
7562 struct dpll *clock = &crtc_state->dpll;
7563
7564 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7565
7566 dpll = DPLL_VGA_MODE_DIS;
7567
7568 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7569 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7570 } else {
7571 if (clock->p1 == 2)
7572 dpll |= PLL_P1_DIVIDE_BY_TWO;
7573 else
7574 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7575 if (clock->p2 == 4)
7576 dpll |= PLL_P2_DIVIDE_BY_4;
7577 }
7578
7579 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7580 dpll |= DPLL_DVO_2X_MODE;
7581
7582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7583 intel_panel_use_ssc(dev_priv))
7584 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7585 else
7586 dpll |= PLL_REF_INPUT_DREFCLK;
7587
7588 dpll |= DPLL_VCO_ENABLE;
7589 crtc_state->dpll_hw_state.dpll = dpll;
7590 }
7591
7592 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7593 {
7594 struct drm_device *dev = intel_crtc->base.dev;
7595 struct drm_i915_private *dev_priv = dev->dev_private;
7596 enum pipe pipe = intel_crtc->pipe;
7597 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7598 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7599 uint32_t crtc_vtotal, crtc_vblank_end;
7600 int vsyncshift = 0;
7601
7602 /* We need to be careful not to changed the adjusted mode, for otherwise
7603 * the hw state checker will get angry at the mismatch. */
7604 crtc_vtotal = adjusted_mode->crtc_vtotal;
7605 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7606
7607 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7608 /* the chip adds 2 halflines automatically */
7609 crtc_vtotal -= 1;
7610 crtc_vblank_end -= 1;
7611
7612 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7613 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7614 else
7615 vsyncshift = adjusted_mode->crtc_hsync_start -
7616 adjusted_mode->crtc_htotal / 2;
7617 if (vsyncshift < 0)
7618 vsyncshift += adjusted_mode->crtc_htotal;
7619 }
7620
7621 if (INTEL_INFO(dev)->gen > 3)
7622 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7623
7624 I915_WRITE(HTOTAL(cpu_transcoder),
7625 (adjusted_mode->crtc_hdisplay - 1) |
7626 ((adjusted_mode->crtc_htotal - 1) << 16));
7627 I915_WRITE(HBLANK(cpu_transcoder),
7628 (adjusted_mode->crtc_hblank_start - 1) |
7629 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7630 I915_WRITE(HSYNC(cpu_transcoder),
7631 (adjusted_mode->crtc_hsync_start - 1) |
7632 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7633
7634 I915_WRITE(VTOTAL(cpu_transcoder),
7635 (adjusted_mode->crtc_vdisplay - 1) |
7636 ((crtc_vtotal - 1) << 16));
7637 I915_WRITE(VBLANK(cpu_transcoder),
7638 (adjusted_mode->crtc_vblank_start - 1) |
7639 ((crtc_vblank_end - 1) << 16));
7640 I915_WRITE(VSYNC(cpu_transcoder),
7641 (adjusted_mode->crtc_vsync_start - 1) |
7642 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7643
7644 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7645 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7646 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7647 * bits. */
7648 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7649 (pipe == PIPE_B || pipe == PIPE_C))
7650 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7651
7652 }
7653
7654 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7655 {
7656 struct drm_device *dev = intel_crtc->base.dev;
7657 struct drm_i915_private *dev_priv = dev->dev_private;
7658 enum pipe pipe = intel_crtc->pipe;
7659
7660 /* pipesrc controls the size that is scaled from, which should
7661 * always be the user's requested size.
7662 */
7663 I915_WRITE(PIPESRC(pipe),
7664 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7665 (intel_crtc->config->pipe_src_h - 1));
7666 }
7667
7668 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7669 struct intel_crtc_state *pipe_config)
7670 {
7671 struct drm_device *dev = crtc->base.dev;
7672 struct drm_i915_private *dev_priv = dev->dev_private;
7673 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7674 uint32_t tmp;
7675
7676 tmp = I915_READ(HTOTAL(cpu_transcoder));
7677 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7678 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7679 tmp = I915_READ(HBLANK(cpu_transcoder));
7680 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7681 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7682 tmp = I915_READ(HSYNC(cpu_transcoder));
7683 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7684 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7685
7686 tmp = I915_READ(VTOTAL(cpu_transcoder));
7687 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7688 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7689 tmp = I915_READ(VBLANK(cpu_transcoder));
7690 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7691 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7692 tmp = I915_READ(VSYNC(cpu_transcoder));
7693 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7694 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7695
7696 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7697 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7698 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7699 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7700 }
7701 }
7702
7703 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7704 struct intel_crtc_state *pipe_config)
7705 {
7706 struct drm_device *dev = crtc->base.dev;
7707 struct drm_i915_private *dev_priv = dev->dev_private;
7708 u32 tmp;
7709
7710 tmp = I915_READ(PIPESRC(crtc->pipe));
7711 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7712 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7713
7714 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7715 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7716 }
7717
7718 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7719 struct intel_crtc_state *pipe_config)
7720 {
7721 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7722 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7723 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7724 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7725
7726 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7727 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7728 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7729 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7730
7731 mode->flags = pipe_config->base.adjusted_mode.flags;
7732 mode->type = DRM_MODE_TYPE_DRIVER;
7733
7734 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7735 mode->flags |= pipe_config->base.adjusted_mode.flags;
7736
7737 mode->hsync = drm_mode_hsync(mode);
7738 mode->vrefresh = drm_mode_vrefresh(mode);
7739 drm_mode_set_name(mode);
7740 }
7741
7742 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7743 {
7744 struct drm_device *dev = intel_crtc->base.dev;
7745 struct drm_i915_private *dev_priv = dev->dev_private;
7746 uint32_t pipeconf;
7747
7748 pipeconf = 0;
7749
7750 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7751 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7752 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7753
7754 if (intel_crtc->config->double_wide)
7755 pipeconf |= PIPECONF_DOUBLE_WIDE;
7756
7757 /* only g4x and later have fancy bpc/dither controls */
7758 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7759 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7760 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7761 pipeconf |= PIPECONF_DITHER_EN |
7762 PIPECONF_DITHER_TYPE_SP;
7763
7764 switch (intel_crtc->config->pipe_bpp) {
7765 case 18:
7766 pipeconf |= PIPECONF_6BPC;
7767 break;
7768 case 24:
7769 pipeconf |= PIPECONF_8BPC;
7770 break;
7771 case 30:
7772 pipeconf |= PIPECONF_10BPC;
7773 break;
7774 default:
7775 /* Case prevented by intel_choose_pipe_bpp_dither. */
7776 BUG();
7777 }
7778 }
7779
7780 if (HAS_PIPE_CXSR(dev)) {
7781 if (intel_crtc->lowfreq_avail) {
7782 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7783 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7784 } else {
7785 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7786 }
7787 }
7788
7789 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7790 if (INTEL_INFO(dev)->gen < 4 ||
7791 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7792 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7793 else
7794 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7795 } else
7796 pipeconf |= PIPECONF_PROGRESSIVE;
7797
7798 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7799 intel_crtc->config->limited_color_range)
7800 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7801
7802 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7803 POSTING_READ(PIPECONF(intel_crtc->pipe));
7804 }
7805
7806 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7807 struct intel_crtc_state *crtc_state)
7808 {
7809 struct drm_device *dev = crtc->base.dev;
7810 struct drm_i915_private *dev_priv = dev->dev_private;
7811 const struct intel_limit *limit;
7812 int refclk = 48000;
7813
7814 memset(&crtc_state->dpll_hw_state, 0,
7815 sizeof(crtc_state->dpll_hw_state));
7816
7817 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7818 if (intel_panel_use_ssc(dev_priv)) {
7819 refclk = dev_priv->vbt.lvds_ssc_freq;
7820 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7821 }
7822
7823 limit = &intel_limits_i8xx_lvds;
7824 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7825 limit = &intel_limits_i8xx_dvo;
7826 } else {
7827 limit = &intel_limits_i8xx_dac;
7828 }
7829
7830 if (!crtc_state->clock_set &&
7831 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7832 refclk, NULL, &crtc_state->dpll)) {
7833 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7834 return -EINVAL;
7835 }
7836
7837 i8xx_compute_dpll(crtc, crtc_state, NULL);
7838
7839 return 0;
7840 }
7841
7842 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7843 struct intel_crtc_state *crtc_state)
7844 {
7845 struct drm_device *dev = crtc->base.dev;
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847 const struct intel_limit *limit;
7848 int refclk = 96000;
7849
7850 memset(&crtc_state->dpll_hw_state, 0,
7851 sizeof(crtc_state->dpll_hw_state));
7852
7853 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7854 if (intel_panel_use_ssc(dev_priv)) {
7855 refclk = dev_priv->vbt.lvds_ssc_freq;
7856 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7857 }
7858
7859 if (intel_is_dual_link_lvds(dev))
7860 limit = &intel_limits_g4x_dual_channel_lvds;
7861 else
7862 limit = &intel_limits_g4x_single_channel_lvds;
7863 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7864 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7865 limit = &intel_limits_g4x_hdmi;
7866 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7867 limit = &intel_limits_g4x_sdvo;
7868 } else {
7869 /* The option is for other outputs */
7870 limit = &intel_limits_i9xx_sdvo;
7871 }
7872
7873 if (!crtc_state->clock_set &&
7874 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7875 refclk, NULL, &crtc_state->dpll)) {
7876 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7877 return -EINVAL;
7878 }
7879
7880 i9xx_compute_dpll(crtc, crtc_state, NULL);
7881
7882 return 0;
7883 }
7884
7885 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7886 struct intel_crtc_state *crtc_state)
7887 {
7888 struct drm_device *dev = crtc->base.dev;
7889 struct drm_i915_private *dev_priv = dev->dev_private;
7890 const struct intel_limit *limit;
7891 int refclk = 96000;
7892
7893 memset(&crtc_state->dpll_hw_state, 0,
7894 sizeof(crtc_state->dpll_hw_state));
7895
7896 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7897 if (intel_panel_use_ssc(dev_priv)) {
7898 refclk = dev_priv->vbt.lvds_ssc_freq;
7899 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7900 }
7901
7902 limit = &intel_limits_pineview_lvds;
7903 } else {
7904 limit = &intel_limits_pineview_sdvo;
7905 }
7906
7907 if (!crtc_state->clock_set &&
7908 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7909 refclk, NULL, &crtc_state->dpll)) {
7910 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7911 return -EINVAL;
7912 }
7913
7914 i9xx_compute_dpll(crtc, crtc_state, NULL);
7915
7916 return 0;
7917 }
7918
7919 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7920 struct intel_crtc_state *crtc_state)
7921 {
7922 struct drm_device *dev = crtc->base.dev;
7923 struct drm_i915_private *dev_priv = dev->dev_private;
7924 const struct intel_limit *limit;
7925 int refclk = 96000;
7926
7927 memset(&crtc_state->dpll_hw_state, 0,
7928 sizeof(crtc_state->dpll_hw_state));
7929
7930 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7931 if (intel_panel_use_ssc(dev_priv)) {
7932 refclk = dev_priv->vbt.lvds_ssc_freq;
7933 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7934 }
7935
7936 limit = &intel_limits_i9xx_lvds;
7937 } else {
7938 limit = &intel_limits_i9xx_sdvo;
7939 }
7940
7941 if (!crtc_state->clock_set &&
7942 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7943 refclk, NULL, &crtc_state->dpll)) {
7944 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7945 return -EINVAL;
7946 }
7947
7948 i9xx_compute_dpll(crtc, crtc_state, NULL);
7949
7950 return 0;
7951 }
7952
7953 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7954 struct intel_crtc_state *crtc_state)
7955 {
7956 int refclk = 100000;
7957 const struct intel_limit *limit = &intel_limits_chv;
7958
7959 memset(&crtc_state->dpll_hw_state, 0,
7960 sizeof(crtc_state->dpll_hw_state));
7961
7962 if (!crtc_state->clock_set &&
7963 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7964 refclk, NULL, &crtc_state->dpll)) {
7965 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7966 return -EINVAL;
7967 }
7968
7969 chv_compute_dpll(crtc, crtc_state);
7970
7971 return 0;
7972 }
7973
7974 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7975 struct intel_crtc_state *crtc_state)
7976 {
7977 int refclk = 100000;
7978 const struct intel_limit *limit = &intel_limits_vlv;
7979
7980 memset(&crtc_state->dpll_hw_state, 0,
7981 sizeof(crtc_state->dpll_hw_state));
7982
7983 if (!crtc_state->clock_set &&
7984 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7985 refclk, NULL, &crtc_state->dpll)) {
7986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7987 return -EINVAL;
7988 }
7989
7990 vlv_compute_dpll(crtc, crtc_state);
7991
7992 return 0;
7993 }
7994
7995 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7996 struct intel_crtc_state *pipe_config)
7997 {
7998 struct drm_device *dev = crtc->base.dev;
7999 struct drm_i915_private *dev_priv = dev->dev_private;
8000 uint32_t tmp;
8001
8002 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8003 return;
8004
8005 tmp = I915_READ(PFIT_CONTROL);
8006 if (!(tmp & PFIT_ENABLE))
8007 return;
8008
8009 /* Check whether the pfit is attached to our pipe. */
8010 if (INTEL_INFO(dev)->gen < 4) {
8011 if (crtc->pipe != PIPE_B)
8012 return;
8013 } else {
8014 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8015 return;
8016 }
8017
8018 pipe_config->gmch_pfit.control = tmp;
8019 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8020 }
8021
8022 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8023 struct intel_crtc_state *pipe_config)
8024 {
8025 struct drm_device *dev = crtc->base.dev;
8026 struct drm_i915_private *dev_priv = dev->dev_private;
8027 int pipe = pipe_config->cpu_transcoder;
8028 struct dpll clock;
8029 u32 mdiv;
8030 int refclk = 100000;
8031
8032 /* In case of DSI, DPLL will not be used */
8033 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8034 return;
8035
8036 mutex_lock(&dev_priv->sb_lock);
8037 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8038 mutex_unlock(&dev_priv->sb_lock);
8039
8040 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8041 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8042 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8043 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8044 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8045
8046 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8047 }
8048
8049 static void
8050 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8051 struct intel_initial_plane_config *plane_config)
8052 {
8053 struct drm_device *dev = crtc->base.dev;
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8055 u32 val, base, offset;
8056 int pipe = crtc->pipe, plane = crtc->plane;
8057 int fourcc, pixel_format;
8058 unsigned int aligned_height;
8059 struct drm_framebuffer *fb;
8060 struct intel_framebuffer *intel_fb;
8061
8062 val = I915_READ(DSPCNTR(plane));
8063 if (!(val & DISPLAY_PLANE_ENABLE))
8064 return;
8065
8066 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8067 if (!intel_fb) {
8068 DRM_DEBUG_KMS("failed to alloc fb\n");
8069 return;
8070 }
8071
8072 fb = &intel_fb->base;
8073
8074 if (INTEL_INFO(dev)->gen >= 4) {
8075 if (val & DISPPLANE_TILED) {
8076 plane_config->tiling = I915_TILING_X;
8077 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8078 }
8079 }
8080
8081 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8082 fourcc = i9xx_format_to_fourcc(pixel_format);
8083 fb->pixel_format = fourcc;
8084 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8085
8086 if (INTEL_INFO(dev)->gen >= 4) {
8087 if (plane_config->tiling)
8088 offset = I915_READ(DSPTILEOFF(plane));
8089 else
8090 offset = I915_READ(DSPLINOFF(plane));
8091 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8092 } else {
8093 base = I915_READ(DSPADDR(plane));
8094 }
8095 plane_config->base = base;
8096
8097 val = I915_READ(PIPESRC(pipe));
8098 fb->width = ((val >> 16) & 0xfff) + 1;
8099 fb->height = ((val >> 0) & 0xfff) + 1;
8100
8101 val = I915_READ(DSPSTRIDE(pipe));
8102 fb->pitches[0] = val & 0xffffffc0;
8103
8104 aligned_height = intel_fb_align_height(dev, fb->height,
8105 fb->pixel_format,
8106 fb->modifier[0]);
8107
8108 plane_config->size = fb->pitches[0] * aligned_height;
8109
8110 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8111 pipe_name(pipe), plane, fb->width, fb->height,
8112 fb->bits_per_pixel, base, fb->pitches[0],
8113 plane_config->size);
8114
8115 plane_config->fb = intel_fb;
8116 }
8117
8118 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8119 struct intel_crtc_state *pipe_config)
8120 {
8121 struct drm_device *dev = crtc->base.dev;
8122 struct drm_i915_private *dev_priv = dev->dev_private;
8123 int pipe = pipe_config->cpu_transcoder;
8124 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8125 struct dpll clock;
8126 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8127 int refclk = 100000;
8128
8129 /* In case of DSI, DPLL will not be used */
8130 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8131 return;
8132
8133 mutex_lock(&dev_priv->sb_lock);
8134 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8135 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8136 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8137 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8138 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8139 mutex_unlock(&dev_priv->sb_lock);
8140
8141 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8142 clock.m2 = (pll_dw0 & 0xff) << 22;
8143 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8144 clock.m2 |= pll_dw2 & 0x3fffff;
8145 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8146 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8147 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8148
8149 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8150 }
8151
8152 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8153 struct intel_crtc_state *pipe_config)
8154 {
8155 struct drm_device *dev = crtc->base.dev;
8156 struct drm_i915_private *dev_priv = dev->dev_private;
8157 enum intel_display_power_domain power_domain;
8158 uint32_t tmp;
8159 bool ret;
8160
8161 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8162 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8163 return false;
8164
8165 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8166 pipe_config->shared_dpll = NULL;
8167
8168 ret = false;
8169
8170 tmp = I915_READ(PIPECONF(crtc->pipe));
8171 if (!(tmp & PIPECONF_ENABLE))
8172 goto out;
8173
8174 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8175 switch (tmp & PIPECONF_BPC_MASK) {
8176 case PIPECONF_6BPC:
8177 pipe_config->pipe_bpp = 18;
8178 break;
8179 case PIPECONF_8BPC:
8180 pipe_config->pipe_bpp = 24;
8181 break;
8182 case PIPECONF_10BPC:
8183 pipe_config->pipe_bpp = 30;
8184 break;
8185 default:
8186 break;
8187 }
8188 }
8189
8190 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8191 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8192 pipe_config->limited_color_range = true;
8193
8194 if (INTEL_INFO(dev)->gen < 4)
8195 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8196
8197 intel_get_pipe_timings(crtc, pipe_config);
8198 intel_get_pipe_src_size(crtc, pipe_config);
8199
8200 i9xx_get_pfit_config(crtc, pipe_config);
8201
8202 if (INTEL_INFO(dev)->gen >= 4) {
8203 /* No way to read it out on pipes B and C */
8204 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8205 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8206 else
8207 tmp = I915_READ(DPLL_MD(crtc->pipe));
8208 pipe_config->pixel_multiplier =
8209 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8210 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8211 pipe_config->dpll_hw_state.dpll_md = tmp;
8212 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8213 tmp = I915_READ(DPLL(crtc->pipe));
8214 pipe_config->pixel_multiplier =
8215 ((tmp & SDVO_MULTIPLIER_MASK)
8216 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8217 } else {
8218 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8219 * port and will be fixed up in the encoder->get_config
8220 * function. */
8221 pipe_config->pixel_multiplier = 1;
8222 }
8223 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8224 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8225 /*
8226 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8227 * on 830. Filter it out here so that we don't
8228 * report errors due to that.
8229 */
8230 if (IS_I830(dev))
8231 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8232
8233 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8234 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8235 } else {
8236 /* Mask out read-only status bits. */
8237 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8238 DPLL_PORTC_READY_MASK |
8239 DPLL_PORTB_READY_MASK);
8240 }
8241
8242 if (IS_CHERRYVIEW(dev))
8243 chv_crtc_clock_get(crtc, pipe_config);
8244 else if (IS_VALLEYVIEW(dev))
8245 vlv_crtc_clock_get(crtc, pipe_config);
8246 else
8247 i9xx_crtc_clock_get(crtc, pipe_config);
8248
8249 /*
8250 * Normally the dotclock is filled in by the encoder .get_config()
8251 * but in case the pipe is enabled w/o any ports we need a sane
8252 * default.
8253 */
8254 pipe_config->base.adjusted_mode.crtc_clock =
8255 pipe_config->port_clock / pipe_config->pixel_multiplier;
8256
8257 ret = true;
8258
8259 out:
8260 intel_display_power_put(dev_priv, power_domain);
8261
8262 return ret;
8263 }
8264
8265 static void ironlake_init_pch_refclk(struct drm_device *dev)
8266 {
8267 struct drm_i915_private *dev_priv = dev->dev_private;
8268 struct intel_encoder *encoder;
8269 u32 val, final;
8270 bool has_lvds = false;
8271 bool has_cpu_edp = false;
8272 bool has_panel = false;
8273 bool has_ck505 = false;
8274 bool can_ssc = false;
8275
8276 /* We need to take the global config into account */
8277 for_each_intel_encoder(dev, encoder) {
8278 switch (encoder->type) {
8279 case INTEL_OUTPUT_LVDS:
8280 has_panel = true;
8281 has_lvds = true;
8282 break;
8283 case INTEL_OUTPUT_EDP:
8284 has_panel = true;
8285 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8286 has_cpu_edp = true;
8287 break;
8288 default:
8289 break;
8290 }
8291 }
8292
8293 if (HAS_PCH_IBX(dev)) {
8294 has_ck505 = dev_priv->vbt.display_clock_mode;
8295 can_ssc = has_ck505;
8296 } else {
8297 has_ck505 = false;
8298 can_ssc = true;
8299 }
8300
8301 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8302 has_panel, has_lvds, has_ck505);
8303
8304 /* Ironlake: try to setup display ref clock before DPLL
8305 * enabling. This is only under driver's control after
8306 * PCH B stepping, previous chipset stepping should be
8307 * ignoring this setting.
8308 */
8309 val = I915_READ(PCH_DREF_CONTROL);
8310
8311 /* As we must carefully and slowly disable/enable each source in turn,
8312 * compute the final state we want first and check if we need to
8313 * make any changes at all.
8314 */
8315 final = val;
8316 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8317 if (has_ck505)
8318 final |= DREF_NONSPREAD_CK505_ENABLE;
8319 else
8320 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8321
8322 final &= ~DREF_SSC_SOURCE_MASK;
8323 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8324 final &= ~DREF_SSC1_ENABLE;
8325
8326 if (has_panel) {
8327 final |= DREF_SSC_SOURCE_ENABLE;
8328
8329 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8330 final |= DREF_SSC1_ENABLE;
8331
8332 if (has_cpu_edp) {
8333 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8334 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8335 else
8336 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8337 } else
8338 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8339 } else {
8340 final |= DREF_SSC_SOURCE_DISABLE;
8341 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8342 }
8343
8344 if (final == val)
8345 return;
8346
8347 /* Always enable nonspread source */
8348 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8349
8350 if (has_ck505)
8351 val |= DREF_NONSPREAD_CK505_ENABLE;
8352 else
8353 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8354
8355 if (has_panel) {
8356 val &= ~DREF_SSC_SOURCE_MASK;
8357 val |= DREF_SSC_SOURCE_ENABLE;
8358
8359 /* SSC must be turned on before enabling the CPU output */
8360 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8361 DRM_DEBUG_KMS("Using SSC on panel\n");
8362 val |= DREF_SSC1_ENABLE;
8363 } else
8364 val &= ~DREF_SSC1_ENABLE;
8365
8366 /* Get SSC going before enabling the outputs */
8367 I915_WRITE(PCH_DREF_CONTROL, val);
8368 POSTING_READ(PCH_DREF_CONTROL);
8369 udelay(200);
8370
8371 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8372
8373 /* Enable CPU source on CPU attached eDP */
8374 if (has_cpu_edp) {
8375 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8376 DRM_DEBUG_KMS("Using SSC on eDP\n");
8377 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8378 } else
8379 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8380 } else
8381 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8382
8383 I915_WRITE(PCH_DREF_CONTROL, val);
8384 POSTING_READ(PCH_DREF_CONTROL);
8385 udelay(200);
8386 } else {
8387 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8388
8389 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8390
8391 /* Turn off CPU output */
8392 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8393
8394 I915_WRITE(PCH_DREF_CONTROL, val);
8395 POSTING_READ(PCH_DREF_CONTROL);
8396 udelay(200);
8397
8398 /* Turn off the SSC source */
8399 val &= ~DREF_SSC_SOURCE_MASK;
8400 val |= DREF_SSC_SOURCE_DISABLE;
8401
8402 /* Turn off SSC1 */
8403 val &= ~DREF_SSC1_ENABLE;
8404
8405 I915_WRITE(PCH_DREF_CONTROL, val);
8406 POSTING_READ(PCH_DREF_CONTROL);
8407 udelay(200);
8408 }
8409
8410 BUG_ON(val != final);
8411 }
8412
8413 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8414 {
8415 uint32_t tmp;
8416
8417 tmp = I915_READ(SOUTH_CHICKEN2);
8418 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8419 I915_WRITE(SOUTH_CHICKEN2, tmp);
8420
8421 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8422 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8423 DRM_ERROR("FDI mPHY reset assert timeout\n");
8424
8425 tmp = I915_READ(SOUTH_CHICKEN2);
8426 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8427 I915_WRITE(SOUTH_CHICKEN2, tmp);
8428
8429 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8430 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8431 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8432 }
8433
8434 /* WaMPhyProgramming:hsw */
8435 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8436 {
8437 uint32_t tmp;
8438
8439 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8440 tmp &= ~(0xFF << 24);
8441 tmp |= (0x12 << 24);
8442 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8443
8444 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8445 tmp |= (1 << 11);
8446 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8447
8448 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8449 tmp |= (1 << 11);
8450 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8451
8452 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8453 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8454 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8455
8456 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8457 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8458 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8459
8460 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8461 tmp &= ~(7 << 13);
8462 tmp |= (5 << 13);
8463 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8464
8465 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8466 tmp &= ~(7 << 13);
8467 tmp |= (5 << 13);
8468 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8469
8470 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8471 tmp &= ~0xFF;
8472 tmp |= 0x1C;
8473 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8474
8475 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8476 tmp &= ~0xFF;
8477 tmp |= 0x1C;
8478 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8479
8480 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8481 tmp &= ~(0xFF << 16);
8482 tmp |= (0x1C << 16);
8483 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8484
8485 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8486 tmp &= ~(0xFF << 16);
8487 tmp |= (0x1C << 16);
8488 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8489
8490 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8491 tmp |= (1 << 27);
8492 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8493
8494 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8495 tmp |= (1 << 27);
8496 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8497
8498 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8499 tmp &= ~(0xF << 28);
8500 tmp |= (4 << 28);
8501 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8502
8503 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8504 tmp &= ~(0xF << 28);
8505 tmp |= (4 << 28);
8506 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8507 }
8508
8509 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8510 * Programming" based on the parameters passed:
8511 * - Sequence to enable CLKOUT_DP
8512 * - Sequence to enable CLKOUT_DP without spread
8513 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8514 */
8515 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8516 bool with_fdi)
8517 {
8518 struct drm_i915_private *dev_priv = dev->dev_private;
8519 uint32_t reg, tmp;
8520
8521 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8522 with_spread = true;
8523 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8524 with_fdi = false;
8525
8526 mutex_lock(&dev_priv->sb_lock);
8527
8528 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8529 tmp &= ~SBI_SSCCTL_DISABLE;
8530 tmp |= SBI_SSCCTL_PATHALT;
8531 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8532
8533 udelay(24);
8534
8535 if (with_spread) {
8536 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8537 tmp &= ~SBI_SSCCTL_PATHALT;
8538 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8539
8540 if (with_fdi) {
8541 lpt_reset_fdi_mphy(dev_priv);
8542 lpt_program_fdi_mphy(dev_priv);
8543 }
8544 }
8545
8546 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8547 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8548 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8549 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8550
8551 mutex_unlock(&dev_priv->sb_lock);
8552 }
8553
8554 /* Sequence to disable CLKOUT_DP */
8555 static void lpt_disable_clkout_dp(struct drm_device *dev)
8556 {
8557 struct drm_i915_private *dev_priv = dev->dev_private;
8558 uint32_t reg, tmp;
8559
8560 mutex_lock(&dev_priv->sb_lock);
8561
8562 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8563 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8564 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8565 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8566
8567 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8568 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8569 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8570 tmp |= SBI_SSCCTL_PATHALT;
8571 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8572 udelay(32);
8573 }
8574 tmp |= SBI_SSCCTL_DISABLE;
8575 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8576 }
8577
8578 mutex_unlock(&dev_priv->sb_lock);
8579 }
8580
8581 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8582
8583 static const uint16_t sscdivintphase[] = {
8584 [BEND_IDX( 50)] = 0x3B23,
8585 [BEND_IDX( 45)] = 0x3B23,
8586 [BEND_IDX( 40)] = 0x3C23,
8587 [BEND_IDX( 35)] = 0x3C23,
8588 [BEND_IDX( 30)] = 0x3D23,
8589 [BEND_IDX( 25)] = 0x3D23,
8590 [BEND_IDX( 20)] = 0x3E23,
8591 [BEND_IDX( 15)] = 0x3E23,
8592 [BEND_IDX( 10)] = 0x3F23,
8593 [BEND_IDX( 5)] = 0x3F23,
8594 [BEND_IDX( 0)] = 0x0025,
8595 [BEND_IDX( -5)] = 0x0025,
8596 [BEND_IDX(-10)] = 0x0125,
8597 [BEND_IDX(-15)] = 0x0125,
8598 [BEND_IDX(-20)] = 0x0225,
8599 [BEND_IDX(-25)] = 0x0225,
8600 [BEND_IDX(-30)] = 0x0325,
8601 [BEND_IDX(-35)] = 0x0325,
8602 [BEND_IDX(-40)] = 0x0425,
8603 [BEND_IDX(-45)] = 0x0425,
8604 [BEND_IDX(-50)] = 0x0525,
8605 };
8606
8607 /*
8608 * Bend CLKOUT_DP
8609 * steps -50 to 50 inclusive, in steps of 5
8610 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8611 * change in clock period = -(steps / 10) * 5.787 ps
8612 */
8613 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8614 {
8615 uint32_t tmp;
8616 int idx = BEND_IDX(steps);
8617
8618 if (WARN_ON(steps % 5 != 0))
8619 return;
8620
8621 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8622 return;
8623
8624 mutex_lock(&dev_priv->sb_lock);
8625
8626 if (steps % 10 != 0)
8627 tmp = 0xAAAAAAAB;
8628 else
8629 tmp = 0x00000000;
8630 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8631
8632 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8633 tmp &= 0xffff0000;
8634 tmp |= sscdivintphase[idx];
8635 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8636
8637 mutex_unlock(&dev_priv->sb_lock);
8638 }
8639
8640 #undef BEND_IDX
8641
8642 static void lpt_init_pch_refclk(struct drm_device *dev)
8643 {
8644 struct intel_encoder *encoder;
8645 bool has_vga = false;
8646
8647 for_each_intel_encoder(dev, encoder) {
8648 switch (encoder->type) {
8649 case INTEL_OUTPUT_ANALOG:
8650 has_vga = true;
8651 break;
8652 default:
8653 break;
8654 }
8655 }
8656
8657 if (has_vga) {
8658 lpt_bend_clkout_dp(to_i915(dev), 0);
8659 lpt_enable_clkout_dp(dev, true, true);
8660 } else {
8661 lpt_disable_clkout_dp(dev);
8662 }
8663 }
8664
8665 /*
8666 * Initialize reference clocks when the driver loads
8667 */
8668 void intel_init_pch_refclk(struct drm_device *dev)
8669 {
8670 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8671 ironlake_init_pch_refclk(dev);
8672 else if (HAS_PCH_LPT(dev))
8673 lpt_init_pch_refclk(dev);
8674 }
8675
8676 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8677 {
8678 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8680 int pipe = intel_crtc->pipe;
8681 uint32_t val;
8682
8683 val = 0;
8684
8685 switch (intel_crtc->config->pipe_bpp) {
8686 case 18:
8687 val |= PIPECONF_6BPC;
8688 break;
8689 case 24:
8690 val |= PIPECONF_8BPC;
8691 break;
8692 case 30:
8693 val |= PIPECONF_10BPC;
8694 break;
8695 case 36:
8696 val |= PIPECONF_12BPC;
8697 break;
8698 default:
8699 /* Case prevented by intel_choose_pipe_bpp_dither. */
8700 BUG();
8701 }
8702
8703 if (intel_crtc->config->dither)
8704 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8705
8706 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8707 val |= PIPECONF_INTERLACED_ILK;
8708 else
8709 val |= PIPECONF_PROGRESSIVE;
8710
8711 if (intel_crtc->config->limited_color_range)
8712 val |= PIPECONF_COLOR_RANGE_SELECT;
8713
8714 I915_WRITE(PIPECONF(pipe), val);
8715 POSTING_READ(PIPECONF(pipe));
8716 }
8717
8718 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8719 {
8720 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8722 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8723 u32 val = 0;
8724
8725 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8726 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8727
8728 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8729 val |= PIPECONF_INTERLACED_ILK;
8730 else
8731 val |= PIPECONF_PROGRESSIVE;
8732
8733 I915_WRITE(PIPECONF(cpu_transcoder), val);
8734 POSTING_READ(PIPECONF(cpu_transcoder));
8735 }
8736
8737 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8738 {
8739 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8741
8742 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8743 u32 val = 0;
8744
8745 switch (intel_crtc->config->pipe_bpp) {
8746 case 18:
8747 val |= PIPEMISC_DITHER_6_BPC;
8748 break;
8749 case 24:
8750 val |= PIPEMISC_DITHER_8_BPC;
8751 break;
8752 case 30:
8753 val |= PIPEMISC_DITHER_10_BPC;
8754 break;
8755 case 36:
8756 val |= PIPEMISC_DITHER_12_BPC;
8757 break;
8758 default:
8759 /* Case prevented by pipe_config_set_bpp. */
8760 BUG();
8761 }
8762
8763 if (intel_crtc->config->dither)
8764 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8765
8766 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8767 }
8768 }
8769
8770 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8771 {
8772 /*
8773 * Account for spread spectrum to avoid
8774 * oversubscribing the link. Max center spread
8775 * is 2.5%; use 5% for safety's sake.
8776 */
8777 u32 bps = target_clock * bpp * 21 / 20;
8778 return DIV_ROUND_UP(bps, link_bw * 8);
8779 }
8780
8781 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8782 {
8783 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8784 }
8785
8786 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8787 struct intel_crtc_state *crtc_state,
8788 struct dpll *reduced_clock)
8789 {
8790 struct drm_crtc *crtc = &intel_crtc->base;
8791 struct drm_device *dev = crtc->dev;
8792 struct drm_i915_private *dev_priv = dev->dev_private;
8793 struct drm_atomic_state *state = crtc_state->base.state;
8794 struct drm_connector *connector;
8795 struct drm_connector_state *connector_state;
8796 struct intel_encoder *encoder;
8797 u32 dpll, fp, fp2;
8798 int factor, i;
8799 bool is_lvds = false, is_sdvo = false;
8800
8801 for_each_connector_in_state(state, connector, connector_state, i) {
8802 if (connector_state->crtc != crtc_state->base.crtc)
8803 continue;
8804
8805 encoder = to_intel_encoder(connector_state->best_encoder);
8806
8807 switch (encoder->type) {
8808 case INTEL_OUTPUT_LVDS:
8809 is_lvds = true;
8810 break;
8811 case INTEL_OUTPUT_SDVO:
8812 case INTEL_OUTPUT_HDMI:
8813 is_sdvo = true;
8814 break;
8815 default:
8816 break;
8817 }
8818 }
8819
8820 /* Enable autotuning of the PLL clock (if permissible) */
8821 factor = 21;
8822 if (is_lvds) {
8823 if ((intel_panel_use_ssc(dev_priv) &&
8824 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8825 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8826 factor = 25;
8827 } else if (crtc_state->sdvo_tv_clock)
8828 factor = 20;
8829
8830 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8831
8832 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8833 fp |= FP_CB_TUNE;
8834
8835 if (reduced_clock) {
8836 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8837
8838 if (reduced_clock->m < factor * reduced_clock->n)
8839 fp2 |= FP_CB_TUNE;
8840 } else {
8841 fp2 = fp;
8842 }
8843
8844 dpll = 0;
8845
8846 if (is_lvds)
8847 dpll |= DPLLB_MODE_LVDS;
8848 else
8849 dpll |= DPLLB_MODE_DAC_SERIAL;
8850
8851 dpll |= (crtc_state->pixel_multiplier - 1)
8852 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8853
8854 if (is_sdvo)
8855 dpll |= DPLL_SDVO_HIGH_SPEED;
8856 if (crtc_state->has_dp_encoder)
8857 dpll |= DPLL_SDVO_HIGH_SPEED;
8858
8859 /* compute bitmask from p1 value */
8860 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8861 /* also FPA1 */
8862 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8863
8864 switch (crtc_state->dpll.p2) {
8865 case 5:
8866 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8867 break;
8868 case 7:
8869 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8870 break;
8871 case 10:
8872 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8873 break;
8874 case 14:
8875 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8876 break;
8877 }
8878
8879 if (is_lvds && intel_panel_use_ssc(dev_priv))
8880 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8881 else
8882 dpll |= PLL_REF_INPUT_DREFCLK;
8883
8884 dpll |= DPLL_VCO_ENABLE;
8885
8886 crtc_state->dpll_hw_state.dpll = dpll;
8887 crtc_state->dpll_hw_state.fp0 = fp;
8888 crtc_state->dpll_hw_state.fp1 = fp2;
8889 }
8890
8891 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8892 struct intel_crtc_state *crtc_state)
8893 {
8894 struct drm_device *dev = crtc->base.dev;
8895 struct drm_i915_private *dev_priv = dev->dev_private;
8896 struct dpll reduced_clock;
8897 bool has_reduced_clock = false;
8898 struct intel_shared_dpll *pll;
8899 const struct intel_limit *limit;
8900 int refclk = 120000;
8901
8902 memset(&crtc_state->dpll_hw_state, 0,
8903 sizeof(crtc_state->dpll_hw_state));
8904
8905 crtc->lowfreq_avail = false;
8906
8907 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8908 if (!crtc_state->has_pch_encoder)
8909 return 0;
8910
8911 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8912 if (intel_panel_use_ssc(dev_priv)) {
8913 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8914 dev_priv->vbt.lvds_ssc_freq);
8915 refclk = dev_priv->vbt.lvds_ssc_freq;
8916 }
8917
8918 if (intel_is_dual_link_lvds(dev)) {
8919 if (refclk == 100000)
8920 limit = &intel_limits_ironlake_dual_lvds_100m;
8921 else
8922 limit = &intel_limits_ironlake_dual_lvds;
8923 } else {
8924 if (refclk == 100000)
8925 limit = &intel_limits_ironlake_single_lvds_100m;
8926 else
8927 limit = &intel_limits_ironlake_single_lvds;
8928 }
8929 } else {
8930 limit = &intel_limits_ironlake_dac;
8931 }
8932
8933 if (!crtc_state->clock_set &&
8934 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8935 refclk, NULL, &crtc_state->dpll)) {
8936 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8937 return -EINVAL;
8938 }
8939
8940 ironlake_compute_dpll(crtc, crtc_state,
8941 has_reduced_clock ? &reduced_clock : NULL);
8942
8943 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8944 if (pll == NULL) {
8945 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8946 pipe_name(crtc->pipe));
8947 return -EINVAL;
8948 }
8949
8950 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8951 has_reduced_clock)
8952 crtc->lowfreq_avail = true;
8953
8954 return 0;
8955 }
8956
8957 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8958 struct intel_link_m_n *m_n)
8959 {
8960 struct drm_device *dev = crtc->base.dev;
8961 struct drm_i915_private *dev_priv = dev->dev_private;
8962 enum pipe pipe = crtc->pipe;
8963
8964 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8965 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8966 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8967 & ~TU_SIZE_MASK;
8968 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8969 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8970 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8971 }
8972
8973 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8974 enum transcoder transcoder,
8975 struct intel_link_m_n *m_n,
8976 struct intel_link_m_n *m2_n2)
8977 {
8978 struct drm_device *dev = crtc->base.dev;
8979 struct drm_i915_private *dev_priv = dev->dev_private;
8980 enum pipe pipe = crtc->pipe;
8981
8982 if (INTEL_INFO(dev)->gen >= 5) {
8983 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8984 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8985 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8986 & ~TU_SIZE_MASK;
8987 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8988 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8989 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8990 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8991 * gen < 8) and if DRRS is supported (to make sure the
8992 * registers are not unnecessarily read).
8993 */
8994 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8995 crtc->config->has_drrs) {
8996 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8997 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8998 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8999 & ~TU_SIZE_MASK;
9000 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9001 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9002 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9003 }
9004 } else {
9005 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9006 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9007 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9008 & ~TU_SIZE_MASK;
9009 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9010 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9011 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9012 }
9013 }
9014
9015 void intel_dp_get_m_n(struct intel_crtc *crtc,
9016 struct intel_crtc_state *pipe_config)
9017 {
9018 if (pipe_config->has_pch_encoder)
9019 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9020 else
9021 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9022 &pipe_config->dp_m_n,
9023 &pipe_config->dp_m2_n2);
9024 }
9025
9026 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9027 struct intel_crtc_state *pipe_config)
9028 {
9029 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9030 &pipe_config->fdi_m_n, NULL);
9031 }
9032
9033 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9034 struct intel_crtc_state *pipe_config)
9035 {
9036 struct drm_device *dev = crtc->base.dev;
9037 struct drm_i915_private *dev_priv = dev->dev_private;
9038 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9039 uint32_t ps_ctrl = 0;
9040 int id = -1;
9041 int i;
9042
9043 /* find scaler attached to this pipe */
9044 for (i = 0; i < crtc->num_scalers; i++) {
9045 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9046 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9047 id = i;
9048 pipe_config->pch_pfit.enabled = true;
9049 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9050 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9051 break;
9052 }
9053 }
9054
9055 scaler_state->scaler_id = id;
9056 if (id >= 0) {
9057 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9058 } else {
9059 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9060 }
9061 }
9062
9063 static void
9064 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9065 struct intel_initial_plane_config *plane_config)
9066 {
9067 struct drm_device *dev = crtc->base.dev;
9068 struct drm_i915_private *dev_priv = dev->dev_private;
9069 u32 val, base, offset, stride_mult, tiling;
9070 int pipe = crtc->pipe;
9071 int fourcc, pixel_format;
9072 unsigned int aligned_height;
9073 struct drm_framebuffer *fb;
9074 struct intel_framebuffer *intel_fb;
9075
9076 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9077 if (!intel_fb) {
9078 DRM_DEBUG_KMS("failed to alloc fb\n");
9079 return;
9080 }
9081
9082 fb = &intel_fb->base;
9083
9084 val = I915_READ(PLANE_CTL(pipe, 0));
9085 if (!(val & PLANE_CTL_ENABLE))
9086 goto error;
9087
9088 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9089 fourcc = skl_format_to_fourcc(pixel_format,
9090 val & PLANE_CTL_ORDER_RGBX,
9091 val & PLANE_CTL_ALPHA_MASK);
9092 fb->pixel_format = fourcc;
9093 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9094
9095 tiling = val & PLANE_CTL_TILED_MASK;
9096 switch (tiling) {
9097 case PLANE_CTL_TILED_LINEAR:
9098 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9099 break;
9100 case PLANE_CTL_TILED_X:
9101 plane_config->tiling = I915_TILING_X;
9102 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9103 break;
9104 case PLANE_CTL_TILED_Y:
9105 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9106 break;
9107 case PLANE_CTL_TILED_YF:
9108 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9109 break;
9110 default:
9111 MISSING_CASE(tiling);
9112 goto error;
9113 }
9114
9115 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9116 plane_config->base = base;
9117
9118 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9119
9120 val = I915_READ(PLANE_SIZE(pipe, 0));
9121 fb->height = ((val >> 16) & 0xfff) + 1;
9122 fb->width = ((val >> 0) & 0x1fff) + 1;
9123
9124 val = I915_READ(PLANE_STRIDE(pipe, 0));
9125 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9126 fb->pixel_format);
9127 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9128
9129 aligned_height = intel_fb_align_height(dev, fb->height,
9130 fb->pixel_format,
9131 fb->modifier[0]);
9132
9133 plane_config->size = fb->pitches[0] * aligned_height;
9134
9135 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9136 pipe_name(pipe), fb->width, fb->height,
9137 fb->bits_per_pixel, base, fb->pitches[0],
9138 plane_config->size);
9139
9140 plane_config->fb = intel_fb;
9141 return;
9142
9143 error:
9144 kfree(fb);
9145 }
9146
9147 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9148 struct intel_crtc_state *pipe_config)
9149 {
9150 struct drm_device *dev = crtc->base.dev;
9151 struct drm_i915_private *dev_priv = dev->dev_private;
9152 uint32_t tmp;
9153
9154 tmp = I915_READ(PF_CTL(crtc->pipe));
9155
9156 if (tmp & PF_ENABLE) {
9157 pipe_config->pch_pfit.enabled = true;
9158 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9159 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9160
9161 /* We currently do not free assignements of panel fitters on
9162 * ivb/hsw (since we don't use the higher upscaling modes which
9163 * differentiates them) so just WARN about this case for now. */
9164 if (IS_GEN7(dev)) {
9165 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9166 PF_PIPE_SEL_IVB(crtc->pipe));
9167 }
9168 }
9169 }
9170
9171 static void
9172 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9173 struct intel_initial_plane_config *plane_config)
9174 {
9175 struct drm_device *dev = crtc->base.dev;
9176 struct drm_i915_private *dev_priv = dev->dev_private;
9177 u32 val, base, offset;
9178 int pipe = crtc->pipe;
9179 int fourcc, pixel_format;
9180 unsigned int aligned_height;
9181 struct drm_framebuffer *fb;
9182 struct intel_framebuffer *intel_fb;
9183
9184 val = I915_READ(DSPCNTR(pipe));
9185 if (!(val & DISPLAY_PLANE_ENABLE))
9186 return;
9187
9188 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9189 if (!intel_fb) {
9190 DRM_DEBUG_KMS("failed to alloc fb\n");
9191 return;
9192 }
9193
9194 fb = &intel_fb->base;
9195
9196 if (INTEL_INFO(dev)->gen >= 4) {
9197 if (val & DISPPLANE_TILED) {
9198 plane_config->tiling = I915_TILING_X;
9199 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9200 }
9201 }
9202
9203 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9204 fourcc = i9xx_format_to_fourcc(pixel_format);
9205 fb->pixel_format = fourcc;
9206 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9207
9208 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9209 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9210 offset = I915_READ(DSPOFFSET(pipe));
9211 } else {
9212 if (plane_config->tiling)
9213 offset = I915_READ(DSPTILEOFF(pipe));
9214 else
9215 offset = I915_READ(DSPLINOFF(pipe));
9216 }
9217 plane_config->base = base;
9218
9219 val = I915_READ(PIPESRC(pipe));
9220 fb->width = ((val >> 16) & 0xfff) + 1;
9221 fb->height = ((val >> 0) & 0xfff) + 1;
9222
9223 val = I915_READ(DSPSTRIDE(pipe));
9224 fb->pitches[0] = val & 0xffffffc0;
9225
9226 aligned_height = intel_fb_align_height(dev, fb->height,
9227 fb->pixel_format,
9228 fb->modifier[0]);
9229
9230 plane_config->size = fb->pitches[0] * aligned_height;
9231
9232 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9233 pipe_name(pipe), fb->width, fb->height,
9234 fb->bits_per_pixel, base, fb->pitches[0],
9235 plane_config->size);
9236
9237 plane_config->fb = intel_fb;
9238 }
9239
9240 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9241 struct intel_crtc_state *pipe_config)
9242 {
9243 struct drm_device *dev = crtc->base.dev;
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245 enum intel_display_power_domain power_domain;
9246 uint32_t tmp;
9247 bool ret;
9248
9249 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9250 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9251 return false;
9252
9253 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9254 pipe_config->shared_dpll = NULL;
9255
9256 ret = false;
9257 tmp = I915_READ(PIPECONF(crtc->pipe));
9258 if (!(tmp & PIPECONF_ENABLE))
9259 goto out;
9260
9261 switch (tmp & PIPECONF_BPC_MASK) {
9262 case PIPECONF_6BPC:
9263 pipe_config->pipe_bpp = 18;
9264 break;
9265 case PIPECONF_8BPC:
9266 pipe_config->pipe_bpp = 24;
9267 break;
9268 case PIPECONF_10BPC:
9269 pipe_config->pipe_bpp = 30;
9270 break;
9271 case PIPECONF_12BPC:
9272 pipe_config->pipe_bpp = 36;
9273 break;
9274 default:
9275 break;
9276 }
9277
9278 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9279 pipe_config->limited_color_range = true;
9280
9281 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9282 struct intel_shared_dpll *pll;
9283 enum intel_dpll_id pll_id;
9284
9285 pipe_config->has_pch_encoder = true;
9286
9287 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9288 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9289 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9290
9291 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9292
9293 if (HAS_PCH_IBX(dev_priv)) {
9294 /*
9295 * The pipe->pch transcoder and pch transcoder->pll
9296 * mapping is fixed.
9297 */
9298 pll_id = (enum intel_dpll_id) crtc->pipe;
9299 } else {
9300 tmp = I915_READ(PCH_DPLL_SEL);
9301 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9302 pll_id = DPLL_ID_PCH_PLL_B;
9303 else
9304 pll_id= DPLL_ID_PCH_PLL_A;
9305 }
9306
9307 pipe_config->shared_dpll =
9308 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9309 pll = pipe_config->shared_dpll;
9310
9311 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9312 &pipe_config->dpll_hw_state));
9313
9314 tmp = pipe_config->dpll_hw_state.dpll;
9315 pipe_config->pixel_multiplier =
9316 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9317 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9318
9319 ironlake_pch_clock_get(crtc, pipe_config);
9320 } else {
9321 pipe_config->pixel_multiplier = 1;
9322 }
9323
9324 intel_get_pipe_timings(crtc, pipe_config);
9325 intel_get_pipe_src_size(crtc, pipe_config);
9326
9327 ironlake_get_pfit_config(crtc, pipe_config);
9328
9329 ret = true;
9330
9331 out:
9332 intel_display_power_put(dev_priv, power_domain);
9333
9334 return ret;
9335 }
9336
9337 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9338 {
9339 struct drm_device *dev = dev_priv->dev;
9340 struct intel_crtc *crtc;
9341
9342 for_each_intel_crtc(dev, crtc)
9343 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9344 pipe_name(crtc->pipe));
9345
9346 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9347 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9348 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9349 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9350 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9351 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9352 "CPU PWM1 enabled\n");
9353 if (IS_HASWELL(dev))
9354 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9355 "CPU PWM2 enabled\n");
9356 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9357 "PCH PWM1 enabled\n");
9358 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9359 "Utility pin enabled\n");
9360 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9361
9362 /*
9363 * In theory we can still leave IRQs enabled, as long as only the HPD
9364 * interrupts remain enabled. We used to check for that, but since it's
9365 * gen-specific and since we only disable LCPLL after we fully disable
9366 * the interrupts, the check below should be enough.
9367 */
9368 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9369 }
9370
9371 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9372 {
9373 struct drm_device *dev = dev_priv->dev;
9374
9375 if (IS_HASWELL(dev))
9376 return I915_READ(D_COMP_HSW);
9377 else
9378 return I915_READ(D_COMP_BDW);
9379 }
9380
9381 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9382 {
9383 struct drm_device *dev = dev_priv->dev;
9384
9385 if (IS_HASWELL(dev)) {
9386 mutex_lock(&dev_priv->rps.hw_lock);
9387 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9388 val))
9389 DRM_ERROR("Failed to write to D_COMP\n");
9390 mutex_unlock(&dev_priv->rps.hw_lock);
9391 } else {
9392 I915_WRITE(D_COMP_BDW, val);
9393 POSTING_READ(D_COMP_BDW);
9394 }
9395 }
9396
9397 /*
9398 * This function implements pieces of two sequences from BSpec:
9399 * - Sequence for display software to disable LCPLL
9400 * - Sequence for display software to allow package C8+
9401 * The steps implemented here are just the steps that actually touch the LCPLL
9402 * register. Callers should take care of disabling all the display engine
9403 * functions, doing the mode unset, fixing interrupts, etc.
9404 */
9405 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9406 bool switch_to_fclk, bool allow_power_down)
9407 {
9408 uint32_t val;
9409
9410 assert_can_disable_lcpll(dev_priv);
9411
9412 val = I915_READ(LCPLL_CTL);
9413
9414 if (switch_to_fclk) {
9415 val |= LCPLL_CD_SOURCE_FCLK;
9416 I915_WRITE(LCPLL_CTL, val);
9417
9418 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9419 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9420 DRM_ERROR("Switching to FCLK failed\n");
9421
9422 val = I915_READ(LCPLL_CTL);
9423 }
9424
9425 val |= LCPLL_PLL_DISABLE;
9426 I915_WRITE(LCPLL_CTL, val);
9427 POSTING_READ(LCPLL_CTL);
9428
9429 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9430 DRM_ERROR("LCPLL still locked\n");
9431
9432 val = hsw_read_dcomp(dev_priv);
9433 val |= D_COMP_COMP_DISABLE;
9434 hsw_write_dcomp(dev_priv, val);
9435 ndelay(100);
9436
9437 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9438 1))
9439 DRM_ERROR("D_COMP RCOMP still in progress\n");
9440
9441 if (allow_power_down) {
9442 val = I915_READ(LCPLL_CTL);
9443 val |= LCPLL_POWER_DOWN_ALLOW;
9444 I915_WRITE(LCPLL_CTL, val);
9445 POSTING_READ(LCPLL_CTL);
9446 }
9447 }
9448
9449 /*
9450 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9451 * source.
9452 */
9453 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9454 {
9455 uint32_t val;
9456
9457 val = I915_READ(LCPLL_CTL);
9458
9459 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9460 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9461 return;
9462
9463 /*
9464 * Make sure we're not on PC8 state before disabling PC8, otherwise
9465 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9466 */
9467 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9468
9469 if (val & LCPLL_POWER_DOWN_ALLOW) {
9470 val &= ~LCPLL_POWER_DOWN_ALLOW;
9471 I915_WRITE(LCPLL_CTL, val);
9472 POSTING_READ(LCPLL_CTL);
9473 }
9474
9475 val = hsw_read_dcomp(dev_priv);
9476 val |= D_COMP_COMP_FORCE;
9477 val &= ~D_COMP_COMP_DISABLE;
9478 hsw_write_dcomp(dev_priv, val);
9479
9480 val = I915_READ(LCPLL_CTL);
9481 val &= ~LCPLL_PLL_DISABLE;
9482 I915_WRITE(LCPLL_CTL, val);
9483
9484 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9485 DRM_ERROR("LCPLL not locked yet\n");
9486
9487 if (val & LCPLL_CD_SOURCE_FCLK) {
9488 val = I915_READ(LCPLL_CTL);
9489 val &= ~LCPLL_CD_SOURCE_FCLK;
9490 I915_WRITE(LCPLL_CTL, val);
9491
9492 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9493 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9494 DRM_ERROR("Switching back to LCPLL failed\n");
9495 }
9496
9497 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9498 intel_update_cdclk(dev_priv->dev);
9499 }
9500
9501 /*
9502 * Package states C8 and deeper are really deep PC states that can only be
9503 * reached when all the devices on the system allow it, so even if the graphics
9504 * device allows PC8+, it doesn't mean the system will actually get to these
9505 * states. Our driver only allows PC8+ when going into runtime PM.
9506 *
9507 * The requirements for PC8+ are that all the outputs are disabled, the power
9508 * well is disabled and most interrupts are disabled, and these are also
9509 * requirements for runtime PM. When these conditions are met, we manually do
9510 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9511 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9512 * hang the machine.
9513 *
9514 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9515 * the state of some registers, so when we come back from PC8+ we need to
9516 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9517 * need to take care of the registers kept by RC6. Notice that this happens even
9518 * if we don't put the device in PCI D3 state (which is what currently happens
9519 * because of the runtime PM support).
9520 *
9521 * For more, read "Display Sequences for Package C8" on the hardware
9522 * documentation.
9523 */
9524 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9525 {
9526 struct drm_device *dev = dev_priv->dev;
9527 uint32_t val;
9528
9529 DRM_DEBUG_KMS("Enabling package C8+\n");
9530
9531 if (HAS_PCH_LPT_LP(dev)) {
9532 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9533 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9534 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9535 }
9536
9537 lpt_disable_clkout_dp(dev);
9538 hsw_disable_lcpll(dev_priv, true, true);
9539 }
9540
9541 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9542 {
9543 struct drm_device *dev = dev_priv->dev;
9544 uint32_t val;
9545
9546 DRM_DEBUG_KMS("Disabling package C8+\n");
9547
9548 hsw_restore_lcpll(dev_priv);
9549 lpt_init_pch_refclk(dev);
9550
9551 if (HAS_PCH_LPT_LP(dev)) {
9552 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9553 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9554 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9555 }
9556 }
9557
9558 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9559 {
9560 struct drm_device *dev = old_state->dev;
9561 struct intel_atomic_state *old_intel_state =
9562 to_intel_atomic_state(old_state);
9563 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9564
9565 broxton_set_cdclk(to_i915(dev), req_cdclk);
9566 }
9567
9568 /* compute the max rate for new configuration */
9569 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9570 {
9571 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9572 struct drm_i915_private *dev_priv = state->dev->dev_private;
9573 struct drm_crtc *crtc;
9574 struct drm_crtc_state *cstate;
9575 struct intel_crtc_state *crtc_state;
9576 unsigned max_pixel_rate = 0, i;
9577 enum pipe pipe;
9578
9579 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9580 sizeof(intel_state->min_pixclk));
9581
9582 for_each_crtc_in_state(state, crtc, cstate, i) {
9583 int pixel_rate;
9584
9585 crtc_state = to_intel_crtc_state(cstate);
9586 if (!crtc_state->base.enable) {
9587 intel_state->min_pixclk[i] = 0;
9588 continue;
9589 }
9590
9591 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9592
9593 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9594 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9595 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9596
9597 intel_state->min_pixclk[i] = pixel_rate;
9598 }
9599
9600 for_each_pipe(dev_priv, pipe)
9601 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9602
9603 return max_pixel_rate;
9604 }
9605
9606 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9607 {
9608 struct drm_i915_private *dev_priv = dev->dev_private;
9609 uint32_t val, data;
9610 int ret;
9611
9612 if (WARN((I915_READ(LCPLL_CTL) &
9613 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9614 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9615 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9616 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9617 "trying to change cdclk frequency with cdclk not enabled\n"))
9618 return;
9619
9620 mutex_lock(&dev_priv->rps.hw_lock);
9621 ret = sandybridge_pcode_write(dev_priv,
9622 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9623 mutex_unlock(&dev_priv->rps.hw_lock);
9624 if (ret) {
9625 DRM_ERROR("failed to inform pcode about cdclk change\n");
9626 return;
9627 }
9628
9629 val = I915_READ(LCPLL_CTL);
9630 val |= LCPLL_CD_SOURCE_FCLK;
9631 I915_WRITE(LCPLL_CTL, val);
9632
9633 if (wait_for_us(I915_READ(LCPLL_CTL) &
9634 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9635 DRM_ERROR("Switching to FCLK failed\n");
9636
9637 val = I915_READ(LCPLL_CTL);
9638 val &= ~LCPLL_CLK_FREQ_MASK;
9639
9640 switch (cdclk) {
9641 case 450000:
9642 val |= LCPLL_CLK_FREQ_450;
9643 data = 0;
9644 break;
9645 case 540000:
9646 val |= LCPLL_CLK_FREQ_54O_BDW;
9647 data = 1;
9648 break;
9649 case 337500:
9650 val |= LCPLL_CLK_FREQ_337_5_BDW;
9651 data = 2;
9652 break;
9653 case 675000:
9654 val |= LCPLL_CLK_FREQ_675_BDW;
9655 data = 3;
9656 break;
9657 default:
9658 WARN(1, "invalid cdclk frequency\n");
9659 return;
9660 }
9661
9662 I915_WRITE(LCPLL_CTL, val);
9663
9664 val = I915_READ(LCPLL_CTL);
9665 val &= ~LCPLL_CD_SOURCE_FCLK;
9666 I915_WRITE(LCPLL_CTL, val);
9667
9668 if (wait_for_us((I915_READ(LCPLL_CTL) &
9669 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9670 DRM_ERROR("Switching back to LCPLL failed\n");
9671
9672 mutex_lock(&dev_priv->rps.hw_lock);
9673 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9674 mutex_unlock(&dev_priv->rps.hw_lock);
9675
9676 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9677
9678 intel_update_cdclk(dev);
9679
9680 WARN(cdclk != dev_priv->cdclk_freq,
9681 "cdclk requested %d kHz but got %d kHz\n",
9682 cdclk, dev_priv->cdclk_freq);
9683 }
9684
9685 static int broadwell_calc_cdclk(int max_pixclk)
9686 {
9687 if (max_pixclk > 540000)
9688 return 675000;
9689 else if (max_pixclk > 450000)
9690 return 540000;
9691 else if (max_pixclk > 337500)
9692 return 450000;
9693 else
9694 return 337500;
9695 }
9696
9697 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9698 {
9699 struct drm_i915_private *dev_priv = to_i915(state->dev);
9700 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9701 int max_pixclk = ilk_max_pixel_rate(state);
9702 int cdclk;
9703
9704 /*
9705 * FIXME should also account for plane ratio
9706 * once 64bpp pixel formats are supported.
9707 */
9708 cdclk = broadwell_calc_cdclk(max_pixclk);
9709
9710 if (cdclk > dev_priv->max_cdclk_freq) {
9711 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9712 cdclk, dev_priv->max_cdclk_freq);
9713 return -EINVAL;
9714 }
9715
9716 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9717 if (!intel_state->active_crtcs)
9718 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9719
9720 return 0;
9721 }
9722
9723 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9724 {
9725 struct drm_device *dev = old_state->dev;
9726 struct intel_atomic_state *old_intel_state =
9727 to_intel_atomic_state(old_state);
9728 unsigned req_cdclk = old_intel_state->dev_cdclk;
9729
9730 broadwell_set_cdclk(dev, req_cdclk);
9731 }
9732
9733 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9734 {
9735 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9736 struct drm_i915_private *dev_priv = to_i915(state->dev);
9737 const int max_pixclk = ilk_max_pixel_rate(state);
9738 int vco = intel_state->cdclk_pll_vco;
9739 int cdclk;
9740
9741 /*
9742 * FIXME should also account for plane ratio
9743 * once 64bpp pixel formats are supported.
9744 */
9745 cdclk = skl_calc_cdclk(max_pixclk, vco);
9746
9747 /*
9748 * FIXME move the cdclk caclulation to
9749 * compute_config() so we can fail gracegully.
9750 */
9751 if (cdclk > dev_priv->max_cdclk_freq) {
9752 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9753 cdclk, dev_priv->max_cdclk_freq);
9754 cdclk = dev_priv->max_cdclk_freq;
9755 }
9756
9757 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9758 if (!intel_state->active_crtcs)
9759 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9760
9761 return 0;
9762 }
9763
9764 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9765 {
9766 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9767 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9768 unsigned int req_cdclk = intel_state->dev_cdclk;
9769 unsigned int req_vco = intel_state->cdclk_pll_vco;
9770
9771 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9772 }
9773
9774 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9775 struct intel_crtc_state *crtc_state)
9776 {
9777 struct intel_encoder *intel_encoder =
9778 intel_ddi_get_crtc_new_encoder(crtc_state);
9779
9780 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9781 if (!intel_ddi_pll_select(crtc, crtc_state))
9782 return -EINVAL;
9783 }
9784
9785 crtc->lowfreq_avail = false;
9786
9787 return 0;
9788 }
9789
9790 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9791 enum port port,
9792 struct intel_crtc_state *pipe_config)
9793 {
9794 enum intel_dpll_id id;
9795
9796 switch (port) {
9797 case PORT_A:
9798 pipe_config->ddi_pll_sel = SKL_DPLL0;
9799 id = DPLL_ID_SKL_DPLL0;
9800 break;
9801 case PORT_B:
9802 pipe_config->ddi_pll_sel = SKL_DPLL1;
9803 id = DPLL_ID_SKL_DPLL1;
9804 break;
9805 case PORT_C:
9806 pipe_config->ddi_pll_sel = SKL_DPLL2;
9807 id = DPLL_ID_SKL_DPLL2;
9808 break;
9809 default:
9810 DRM_ERROR("Incorrect port type\n");
9811 return;
9812 }
9813
9814 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9815 }
9816
9817 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9818 enum port port,
9819 struct intel_crtc_state *pipe_config)
9820 {
9821 enum intel_dpll_id id;
9822 u32 temp;
9823
9824 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9825 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9826
9827 switch (pipe_config->ddi_pll_sel) {
9828 case SKL_DPLL0:
9829 id = DPLL_ID_SKL_DPLL0;
9830 break;
9831 case SKL_DPLL1:
9832 id = DPLL_ID_SKL_DPLL1;
9833 break;
9834 case SKL_DPLL2:
9835 id = DPLL_ID_SKL_DPLL2;
9836 break;
9837 case SKL_DPLL3:
9838 id = DPLL_ID_SKL_DPLL3;
9839 break;
9840 default:
9841 MISSING_CASE(pipe_config->ddi_pll_sel);
9842 return;
9843 }
9844
9845 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9846 }
9847
9848 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9849 enum port port,
9850 struct intel_crtc_state *pipe_config)
9851 {
9852 enum intel_dpll_id id;
9853
9854 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9855
9856 switch (pipe_config->ddi_pll_sel) {
9857 case PORT_CLK_SEL_WRPLL1:
9858 id = DPLL_ID_WRPLL1;
9859 break;
9860 case PORT_CLK_SEL_WRPLL2:
9861 id = DPLL_ID_WRPLL2;
9862 break;
9863 case PORT_CLK_SEL_SPLL:
9864 id = DPLL_ID_SPLL;
9865 break;
9866 case PORT_CLK_SEL_LCPLL_810:
9867 id = DPLL_ID_LCPLL_810;
9868 break;
9869 case PORT_CLK_SEL_LCPLL_1350:
9870 id = DPLL_ID_LCPLL_1350;
9871 break;
9872 case PORT_CLK_SEL_LCPLL_2700:
9873 id = DPLL_ID_LCPLL_2700;
9874 break;
9875 default:
9876 MISSING_CASE(pipe_config->ddi_pll_sel);
9877 /* fall through */
9878 case PORT_CLK_SEL_NONE:
9879 return;
9880 }
9881
9882 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9883 }
9884
9885 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9886 struct intel_crtc_state *pipe_config,
9887 unsigned long *power_domain_mask)
9888 {
9889 struct drm_device *dev = crtc->base.dev;
9890 struct drm_i915_private *dev_priv = dev->dev_private;
9891 enum intel_display_power_domain power_domain;
9892 u32 tmp;
9893
9894 /*
9895 * The pipe->transcoder mapping is fixed with the exception of the eDP
9896 * transcoder handled below.
9897 */
9898 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9899
9900 /*
9901 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9902 * consistency and less surprising code; it's in always on power).
9903 */
9904 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9905 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9906 enum pipe trans_edp_pipe;
9907 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9908 default:
9909 WARN(1, "unknown pipe linked to edp transcoder\n");
9910 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9911 case TRANS_DDI_EDP_INPUT_A_ON:
9912 trans_edp_pipe = PIPE_A;
9913 break;
9914 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9915 trans_edp_pipe = PIPE_B;
9916 break;
9917 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9918 trans_edp_pipe = PIPE_C;
9919 break;
9920 }
9921
9922 if (trans_edp_pipe == crtc->pipe)
9923 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9924 }
9925
9926 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9927 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9928 return false;
9929 *power_domain_mask |= BIT(power_domain);
9930
9931 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9932
9933 return tmp & PIPECONF_ENABLE;
9934 }
9935
9936 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9937 struct intel_crtc_state *pipe_config,
9938 unsigned long *power_domain_mask)
9939 {
9940 struct drm_device *dev = crtc->base.dev;
9941 struct drm_i915_private *dev_priv = dev->dev_private;
9942 enum intel_display_power_domain power_domain;
9943 enum port port;
9944 enum transcoder cpu_transcoder;
9945 u32 tmp;
9946
9947 pipe_config->has_dsi_encoder = false;
9948
9949 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9950 if (port == PORT_A)
9951 cpu_transcoder = TRANSCODER_DSI_A;
9952 else
9953 cpu_transcoder = TRANSCODER_DSI_C;
9954
9955 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9956 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9957 continue;
9958 *power_domain_mask |= BIT(power_domain);
9959
9960 /*
9961 * The PLL needs to be enabled with a valid divider
9962 * configuration, otherwise accessing DSI registers will hang
9963 * the machine. See BSpec North Display Engine
9964 * registers/MIPI[BXT]. We can break out here early, since we
9965 * need the same DSI PLL to be enabled for both DSI ports.
9966 */
9967 if (!intel_dsi_pll_is_enabled(dev_priv))
9968 break;
9969
9970 /* XXX: this works for video mode only */
9971 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9972 if (!(tmp & DPI_ENABLE))
9973 continue;
9974
9975 tmp = I915_READ(MIPI_CTRL(port));
9976 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9977 continue;
9978
9979 pipe_config->cpu_transcoder = cpu_transcoder;
9980 pipe_config->has_dsi_encoder = true;
9981 break;
9982 }
9983
9984 return pipe_config->has_dsi_encoder;
9985 }
9986
9987 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9988 struct intel_crtc_state *pipe_config)
9989 {
9990 struct drm_device *dev = crtc->base.dev;
9991 struct drm_i915_private *dev_priv = dev->dev_private;
9992 struct intel_shared_dpll *pll;
9993 enum port port;
9994 uint32_t tmp;
9995
9996 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9997
9998 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9999
10000 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10001 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10002 else if (IS_BROXTON(dev))
10003 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10004 else
10005 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10006
10007 pll = pipe_config->shared_dpll;
10008 if (pll) {
10009 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10010 &pipe_config->dpll_hw_state));
10011 }
10012
10013 /*
10014 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10015 * DDI E. So just check whether this pipe is wired to DDI E and whether
10016 * the PCH transcoder is on.
10017 */
10018 if (INTEL_INFO(dev)->gen < 9 &&
10019 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10020 pipe_config->has_pch_encoder = true;
10021
10022 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10023 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10024 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10025
10026 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10027 }
10028 }
10029
10030 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10031 struct intel_crtc_state *pipe_config)
10032 {
10033 struct drm_device *dev = crtc->base.dev;
10034 struct drm_i915_private *dev_priv = dev->dev_private;
10035 enum intel_display_power_domain power_domain;
10036 unsigned long power_domain_mask;
10037 bool active;
10038
10039 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10040 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10041 return false;
10042 power_domain_mask = BIT(power_domain);
10043
10044 pipe_config->shared_dpll = NULL;
10045
10046 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10047
10048 if (IS_BROXTON(dev_priv)) {
10049 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10050 &power_domain_mask);
10051 WARN_ON(active && pipe_config->has_dsi_encoder);
10052 if (pipe_config->has_dsi_encoder)
10053 active = true;
10054 }
10055
10056 if (!active)
10057 goto out;
10058
10059 if (!pipe_config->has_dsi_encoder) {
10060 haswell_get_ddi_port_state(crtc, pipe_config);
10061 intel_get_pipe_timings(crtc, pipe_config);
10062 }
10063
10064 intel_get_pipe_src_size(crtc, pipe_config);
10065
10066 pipe_config->gamma_mode =
10067 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10068
10069 if (INTEL_INFO(dev)->gen >= 9) {
10070 skl_init_scalers(dev, crtc, pipe_config);
10071 }
10072
10073 if (INTEL_INFO(dev)->gen >= 9) {
10074 pipe_config->scaler_state.scaler_id = -1;
10075 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10076 }
10077
10078 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10079 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10080 power_domain_mask |= BIT(power_domain);
10081 if (INTEL_INFO(dev)->gen >= 9)
10082 skylake_get_pfit_config(crtc, pipe_config);
10083 else
10084 ironlake_get_pfit_config(crtc, pipe_config);
10085 }
10086
10087 if (IS_HASWELL(dev))
10088 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10089 (I915_READ(IPS_CTL) & IPS_ENABLE);
10090
10091 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10092 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10093 pipe_config->pixel_multiplier =
10094 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10095 } else {
10096 pipe_config->pixel_multiplier = 1;
10097 }
10098
10099 out:
10100 for_each_power_domain(power_domain, power_domain_mask)
10101 intel_display_power_put(dev_priv, power_domain);
10102
10103 return active;
10104 }
10105
10106 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10107 const struct intel_plane_state *plane_state)
10108 {
10109 struct drm_device *dev = crtc->dev;
10110 struct drm_i915_private *dev_priv = dev->dev_private;
10111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10112 uint32_t cntl = 0, size = 0;
10113
10114 if (plane_state && plane_state->visible) {
10115 unsigned int width = plane_state->base.crtc_w;
10116 unsigned int height = plane_state->base.crtc_h;
10117 unsigned int stride = roundup_pow_of_two(width) * 4;
10118
10119 switch (stride) {
10120 default:
10121 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10122 width, stride);
10123 stride = 256;
10124 /* fallthrough */
10125 case 256:
10126 case 512:
10127 case 1024:
10128 case 2048:
10129 break;
10130 }
10131
10132 cntl |= CURSOR_ENABLE |
10133 CURSOR_GAMMA_ENABLE |
10134 CURSOR_FORMAT_ARGB |
10135 CURSOR_STRIDE(stride);
10136
10137 size = (height << 12) | width;
10138 }
10139
10140 if (intel_crtc->cursor_cntl != 0 &&
10141 (intel_crtc->cursor_base != base ||
10142 intel_crtc->cursor_size != size ||
10143 intel_crtc->cursor_cntl != cntl)) {
10144 /* On these chipsets we can only modify the base/size/stride
10145 * whilst the cursor is disabled.
10146 */
10147 I915_WRITE(CURCNTR(PIPE_A), 0);
10148 POSTING_READ(CURCNTR(PIPE_A));
10149 intel_crtc->cursor_cntl = 0;
10150 }
10151
10152 if (intel_crtc->cursor_base != base) {
10153 I915_WRITE(CURBASE(PIPE_A), base);
10154 intel_crtc->cursor_base = base;
10155 }
10156
10157 if (intel_crtc->cursor_size != size) {
10158 I915_WRITE(CURSIZE, size);
10159 intel_crtc->cursor_size = size;
10160 }
10161
10162 if (intel_crtc->cursor_cntl != cntl) {
10163 I915_WRITE(CURCNTR(PIPE_A), cntl);
10164 POSTING_READ(CURCNTR(PIPE_A));
10165 intel_crtc->cursor_cntl = cntl;
10166 }
10167 }
10168
10169 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10170 const struct intel_plane_state *plane_state)
10171 {
10172 struct drm_device *dev = crtc->dev;
10173 struct drm_i915_private *dev_priv = dev->dev_private;
10174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10175 int pipe = intel_crtc->pipe;
10176 uint32_t cntl = 0;
10177
10178 if (plane_state && plane_state->visible) {
10179 cntl = MCURSOR_GAMMA_ENABLE;
10180 switch (plane_state->base.crtc_w) {
10181 case 64:
10182 cntl |= CURSOR_MODE_64_ARGB_AX;
10183 break;
10184 case 128:
10185 cntl |= CURSOR_MODE_128_ARGB_AX;
10186 break;
10187 case 256:
10188 cntl |= CURSOR_MODE_256_ARGB_AX;
10189 break;
10190 default:
10191 MISSING_CASE(plane_state->base.crtc_w);
10192 return;
10193 }
10194 cntl |= pipe << 28; /* Connect to correct pipe */
10195
10196 if (HAS_DDI(dev))
10197 cntl |= CURSOR_PIPE_CSC_ENABLE;
10198
10199 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10200 cntl |= CURSOR_ROTATE_180;
10201 }
10202
10203 if (intel_crtc->cursor_cntl != cntl) {
10204 I915_WRITE(CURCNTR(pipe), cntl);
10205 POSTING_READ(CURCNTR(pipe));
10206 intel_crtc->cursor_cntl = cntl;
10207 }
10208
10209 /* and commit changes on next vblank */
10210 I915_WRITE(CURBASE(pipe), base);
10211 POSTING_READ(CURBASE(pipe));
10212
10213 intel_crtc->cursor_base = base;
10214 }
10215
10216 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10217 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10218 const struct intel_plane_state *plane_state)
10219 {
10220 struct drm_device *dev = crtc->dev;
10221 struct drm_i915_private *dev_priv = dev->dev_private;
10222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10223 int pipe = intel_crtc->pipe;
10224 u32 base = intel_crtc->cursor_addr;
10225 u32 pos = 0;
10226
10227 if (plane_state) {
10228 int x = plane_state->base.crtc_x;
10229 int y = plane_state->base.crtc_y;
10230
10231 if (x < 0) {
10232 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10233 x = -x;
10234 }
10235 pos |= x << CURSOR_X_SHIFT;
10236
10237 if (y < 0) {
10238 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10239 y = -y;
10240 }
10241 pos |= y << CURSOR_Y_SHIFT;
10242
10243 /* ILK+ do this automagically */
10244 if (HAS_GMCH_DISPLAY(dev) &&
10245 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10246 base += (plane_state->base.crtc_h *
10247 plane_state->base.crtc_w - 1) * 4;
10248 }
10249 }
10250
10251 I915_WRITE(CURPOS(pipe), pos);
10252
10253 if (IS_845G(dev) || IS_I865G(dev))
10254 i845_update_cursor(crtc, base, plane_state);
10255 else
10256 i9xx_update_cursor(crtc, base, plane_state);
10257 }
10258
10259 static bool cursor_size_ok(struct drm_device *dev,
10260 uint32_t width, uint32_t height)
10261 {
10262 if (width == 0 || height == 0)
10263 return false;
10264
10265 /*
10266 * 845g/865g are special in that they are only limited by
10267 * the width of their cursors, the height is arbitrary up to
10268 * the precision of the register. Everything else requires
10269 * square cursors, limited to a few power-of-two sizes.
10270 */
10271 if (IS_845G(dev) || IS_I865G(dev)) {
10272 if ((width & 63) != 0)
10273 return false;
10274
10275 if (width > (IS_845G(dev) ? 64 : 512))
10276 return false;
10277
10278 if (height > 1023)
10279 return false;
10280 } else {
10281 switch (width | height) {
10282 case 256:
10283 case 128:
10284 if (IS_GEN2(dev))
10285 return false;
10286 case 64:
10287 break;
10288 default:
10289 return false;
10290 }
10291 }
10292
10293 return true;
10294 }
10295
10296 /* VESA 640x480x72Hz mode to set on the pipe */
10297 static struct drm_display_mode load_detect_mode = {
10298 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10299 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10300 };
10301
10302 struct drm_framebuffer *
10303 __intel_framebuffer_create(struct drm_device *dev,
10304 struct drm_mode_fb_cmd2 *mode_cmd,
10305 struct drm_i915_gem_object *obj)
10306 {
10307 struct intel_framebuffer *intel_fb;
10308 int ret;
10309
10310 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10311 if (!intel_fb)
10312 return ERR_PTR(-ENOMEM);
10313
10314 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10315 if (ret)
10316 goto err;
10317
10318 return &intel_fb->base;
10319
10320 err:
10321 kfree(intel_fb);
10322 return ERR_PTR(ret);
10323 }
10324
10325 static struct drm_framebuffer *
10326 intel_framebuffer_create(struct drm_device *dev,
10327 struct drm_mode_fb_cmd2 *mode_cmd,
10328 struct drm_i915_gem_object *obj)
10329 {
10330 struct drm_framebuffer *fb;
10331 int ret;
10332
10333 ret = i915_mutex_lock_interruptible(dev);
10334 if (ret)
10335 return ERR_PTR(ret);
10336 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10337 mutex_unlock(&dev->struct_mutex);
10338
10339 return fb;
10340 }
10341
10342 static u32
10343 intel_framebuffer_pitch_for_width(int width, int bpp)
10344 {
10345 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10346 return ALIGN(pitch, 64);
10347 }
10348
10349 static u32
10350 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10351 {
10352 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10353 return PAGE_ALIGN(pitch * mode->vdisplay);
10354 }
10355
10356 static struct drm_framebuffer *
10357 intel_framebuffer_create_for_mode(struct drm_device *dev,
10358 struct drm_display_mode *mode,
10359 int depth, int bpp)
10360 {
10361 struct drm_framebuffer *fb;
10362 struct drm_i915_gem_object *obj;
10363 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10364
10365 obj = i915_gem_object_create(dev,
10366 intel_framebuffer_size_for_mode(mode, bpp));
10367 if (IS_ERR(obj))
10368 return ERR_CAST(obj);
10369
10370 mode_cmd.width = mode->hdisplay;
10371 mode_cmd.height = mode->vdisplay;
10372 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10373 bpp);
10374 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10375
10376 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10377 if (IS_ERR(fb))
10378 drm_gem_object_unreference_unlocked(&obj->base);
10379
10380 return fb;
10381 }
10382
10383 static struct drm_framebuffer *
10384 mode_fits_in_fbdev(struct drm_device *dev,
10385 struct drm_display_mode *mode)
10386 {
10387 #ifdef CONFIG_DRM_FBDEV_EMULATION
10388 struct drm_i915_private *dev_priv = dev->dev_private;
10389 struct drm_i915_gem_object *obj;
10390 struct drm_framebuffer *fb;
10391
10392 if (!dev_priv->fbdev)
10393 return NULL;
10394
10395 if (!dev_priv->fbdev->fb)
10396 return NULL;
10397
10398 obj = dev_priv->fbdev->fb->obj;
10399 BUG_ON(!obj);
10400
10401 fb = &dev_priv->fbdev->fb->base;
10402 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10403 fb->bits_per_pixel))
10404 return NULL;
10405
10406 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10407 return NULL;
10408
10409 drm_framebuffer_reference(fb);
10410 return fb;
10411 #else
10412 return NULL;
10413 #endif
10414 }
10415
10416 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10417 struct drm_crtc *crtc,
10418 struct drm_display_mode *mode,
10419 struct drm_framebuffer *fb,
10420 int x, int y)
10421 {
10422 struct drm_plane_state *plane_state;
10423 int hdisplay, vdisplay;
10424 int ret;
10425
10426 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10427 if (IS_ERR(plane_state))
10428 return PTR_ERR(plane_state);
10429
10430 if (mode)
10431 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10432 else
10433 hdisplay = vdisplay = 0;
10434
10435 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10436 if (ret)
10437 return ret;
10438 drm_atomic_set_fb_for_plane(plane_state, fb);
10439 plane_state->crtc_x = 0;
10440 plane_state->crtc_y = 0;
10441 plane_state->crtc_w = hdisplay;
10442 plane_state->crtc_h = vdisplay;
10443 plane_state->src_x = x << 16;
10444 plane_state->src_y = y << 16;
10445 plane_state->src_w = hdisplay << 16;
10446 plane_state->src_h = vdisplay << 16;
10447
10448 return 0;
10449 }
10450
10451 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10452 struct drm_display_mode *mode,
10453 struct intel_load_detect_pipe *old,
10454 struct drm_modeset_acquire_ctx *ctx)
10455 {
10456 struct intel_crtc *intel_crtc;
10457 struct intel_encoder *intel_encoder =
10458 intel_attached_encoder(connector);
10459 struct drm_crtc *possible_crtc;
10460 struct drm_encoder *encoder = &intel_encoder->base;
10461 struct drm_crtc *crtc = NULL;
10462 struct drm_device *dev = encoder->dev;
10463 struct drm_framebuffer *fb;
10464 struct drm_mode_config *config = &dev->mode_config;
10465 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10466 struct drm_connector_state *connector_state;
10467 struct intel_crtc_state *crtc_state;
10468 int ret, i = -1;
10469
10470 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10471 connector->base.id, connector->name,
10472 encoder->base.id, encoder->name);
10473
10474 old->restore_state = NULL;
10475
10476 retry:
10477 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10478 if (ret)
10479 goto fail;
10480
10481 /*
10482 * Algorithm gets a little messy:
10483 *
10484 * - if the connector already has an assigned crtc, use it (but make
10485 * sure it's on first)
10486 *
10487 * - try to find the first unused crtc that can drive this connector,
10488 * and use that if we find one
10489 */
10490
10491 /* See if we already have a CRTC for this connector */
10492 if (connector->state->crtc) {
10493 crtc = connector->state->crtc;
10494
10495 ret = drm_modeset_lock(&crtc->mutex, ctx);
10496 if (ret)
10497 goto fail;
10498
10499 /* Make sure the crtc and connector are running */
10500 goto found;
10501 }
10502
10503 /* Find an unused one (if possible) */
10504 for_each_crtc(dev, possible_crtc) {
10505 i++;
10506 if (!(encoder->possible_crtcs & (1 << i)))
10507 continue;
10508
10509 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10510 if (ret)
10511 goto fail;
10512
10513 if (possible_crtc->state->enable) {
10514 drm_modeset_unlock(&possible_crtc->mutex);
10515 continue;
10516 }
10517
10518 crtc = possible_crtc;
10519 break;
10520 }
10521
10522 /*
10523 * If we didn't find an unused CRTC, don't use any.
10524 */
10525 if (!crtc) {
10526 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10527 goto fail;
10528 }
10529
10530 found:
10531 intel_crtc = to_intel_crtc(crtc);
10532
10533 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10534 if (ret)
10535 goto fail;
10536
10537 state = drm_atomic_state_alloc(dev);
10538 restore_state = drm_atomic_state_alloc(dev);
10539 if (!state || !restore_state) {
10540 ret = -ENOMEM;
10541 goto fail;
10542 }
10543
10544 state->acquire_ctx = ctx;
10545 restore_state->acquire_ctx = ctx;
10546
10547 connector_state = drm_atomic_get_connector_state(state, connector);
10548 if (IS_ERR(connector_state)) {
10549 ret = PTR_ERR(connector_state);
10550 goto fail;
10551 }
10552
10553 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10554 if (ret)
10555 goto fail;
10556
10557 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10558 if (IS_ERR(crtc_state)) {
10559 ret = PTR_ERR(crtc_state);
10560 goto fail;
10561 }
10562
10563 crtc_state->base.active = crtc_state->base.enable = true;
10564
10565 if (!mode)
10566 mode = &load_detect_mode;
10567
10568 /* We need a framebuffer large enough to accommodate all accesses
10569 * that the plane may generate whilst we perform load detection.
10570 * We can not rely on the fbcon either being present (we get called
10571 * during its initialisation to detect all boot displays, or it may
10572 * not even exist) or that it is large enough to satisfy the
10573 * requested mode.
10574 */
10575 fb = mode_fits_in_fbdev(dev, mode);
10576 if (fb == NULL) {
10577 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10578 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10579 } else
10580 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10581 if (IS_ERR(fb)) {
10582 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10583 goto fail;
10584 }
10585
10586 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10587 if (ret)
10588 goto fail;
10589
10590 drm_framebuffer_unreference(fb);
10591
10592 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10593 if (ret)
10594 goto fail;
10595
10596 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10597 if (!ret)
10598 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10599 if (!ret)
10600 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10601 if (ret) {
10602 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10603 goto fail;
10604 }
10605
10606 ret = drm_atomic_commit(state);
10607 if (ret) {
10608 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10609 goto fail;
10610 }
10611
10612 old->restore_state = restore_state;
10613
10614 /* let the connector get through one full cycle before testing */
10615 intel_wait_for_vblank(dev, intel_crtc->pipe);
10616 return true;
10617
10618 fail:
10619 drm_atomic_state_free(state);
10620 drm_atomic_state_free(restore_state);
10621 restore_state = state = NULL;
10622
10623 if (ret == -EDEADLK) {
10624 drm_modeset_backoff(ctx);
10625 goto retry;
10626 }
10627
10628 return false;
10629 }
10630
10631 void intel_release_load_detect_pipe(struct drm_connector *connector,
10632 struct intel_load_detect_pipe *old,
10633 struct drm_modeset_acquire_ctx *ctx)
10634 {
10635 struct intel_encoder *intel_encoder =
10636 intel_attached_encoder(connector);
10637 struct drm_encoder *encoder = &intel_encoder->base;
10638 struct drm_atomic_state *state = old->restore_state;
10639 int ret;
10640
10641 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10642 connector->base.id, connector->name,
10643 encoder->base.id, encoder->name);
10644
10645 if (!state)
10646 return;
10647
10648 ret = drm_atomic_commit(state);
10649 if (ret) {
10650 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10651 drm_atomic_state_free(state);
10652 }
10653 }
10654
10655 static int i9xx_pll_refclk(struct drm_device *dev,
10656 const struct intel_crtc_state *pipe_config)
10657 {
10658 struct drm_i915_private *dev_priv = dev->dev_private;
10659 u32 dpll = pipe_config->dpll_hw_state.dpll;
10660
10661 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10662 return dev_priv->vbt.lvds_ssc_freq;
10663 else if (HAS_PCH_SPLIT(dev))
10664 return 120000;
10665 else if (!IS_GEN2(dev))
10666 return 96000;
10667 else
10668 return 48000;
10669 }
10670
10671 /* Returns the clock of the currently programmed mode of the given pipe. */
10672 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10673 struct intel_crtc_state *pipe_config)
10674 {
10675 struct drm_device *dev = crtc->base.dev;
10676 struct drm_i915_private *dev_priv = dev->dev_private;
10677 int pipe = pipe_config->cpu_transcoder;
10678 u32 dpll = pipe_config->dpll_hw_state.dpll;
10679 u32 fp;
10680 struct dpll clock;
10681 int port_clock;
10682 int refclk = i9xx_pll_refclk(dev, pipe_config);
10683
10684 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10685 fp = pipe_config->dpll_hw_state.fp0;
10686 else
10687 fp = pipe_config->dpll_hw_state.fp1;
10688
10689 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10690 if (IS_PINEVIEW(dev)) {
10691 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10692 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10693 } else {
10694 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10695 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10696 }
10697
10698 if (!IS_GEN2(dev)) {
10699 if (IS_PINEVIEW(dev))
10700 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10701 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10702 else
10703 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10704 DPLL_FPA01_P1_POST_DIV_SHIFT);
10705
10706 switch (dpll & DPLL_MODE_MASK) {
10707 case DPLLB_MODE_DAC_SERIAL:
10708 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10709 5 : 10;
10710 break;
10711 case DPLLB_MODE_LVDS:
10712 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10713 7 : 14;
10714 break;
10715 default:
10716 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10717 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10718 return;
10719 }
10720
10721 if (IS_PINEVIEW(dev))
10722 port_clock = pnv_calc_dpll_params(refclk, &clock);
10723 else
10724 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10725 } else {
10726 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10727 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10728
10729 if (is_lvds) {
10730 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10731 DPLL_FPA01_P1_POST_DIV_SHIFT);
10732
10733 if (lvds & LVDS_CLKB_POWER_UP)
10734 clock.p2 = 7;
10735 else
10736 clock.p2 = 14;
10737 } else {
10738 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10739 clock.p1 = 2;
10740 else {
10741 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10742 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10743 }
10744 if (dpll & PLL_P2_DIVIDE_BY_4)
10745 clock.p2 = 4;
10746 else
10747 clock.p2 = 2;
10748 }
10749
10750 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10751 }
10752
10753 /*
10754 * This value includes pixel_multiplier. We will use
10755 * port_clock to compute adjusted_mode.crtc_clock in the
10756 * encoder's get_config() function.
10757 */
10758 pipe_config->port_clock = port_clock;
10759 }
10760
10761 int intel_dotclock_calculate(int link_freq,
10762 const struct intel_link_m_n *m_n)
10763 {
10764 /*
10765 * The calculation for the data clock is:
10766 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10767 * But we want to avoid losing precison if possible, so:
10768 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10769 *
10770 * and the link clock is simpler:
10771 * link_clock = (m * link_clock) / n
10772 */
10773
10774 if (!m_n->link_n)
10775 return 0;
10776
10777 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10778 }
10779
10780 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10781 struct intel_crtc_state *pipe_config)
10782 {
10783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10784
10785 /* read out port_clock from the DPLL */
10786 i9xx_crtc_clock_get(crtc, pipe_config);
10787
10788 /*
10789 * In case there is an active pipe without active ports,
10790 * we may need some idea for the dotclock anyway.
10791 * Calculate one based on the FDI configuration.
10792 */
10793 pipe_config->base.adjusted_mode.crtc_clock =
10794 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10795 &pipe_config->fdi_m_n);
10796 }
10797
10798 /** Returns the currently programmed mode of the given pipe. */
10799 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10800 struct drm_crtc *crtc)
10801 {
10802 struct drm_i915_private *dev_priv = dev->dev_private;
10803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10804 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10805 struct drm_display_mode *mode;
10806 struct intel_crtc_state *pipe_config;
10807 int htot = I915_READ(HTOTAL(cpu_transcoder));
10808 int hsync = I915_READ(HSYNC(cpu_transcoder));
10809 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10810 int vsync = I915_READ(VSYNC(cpu_transcoder));
10811 enum pipe pipe = intel_crtc->pipe;
10812
10813 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10814 if (!mode)
10815 return NULL;
10816
10817 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10818 if (!pipe_config) {
10819 kfree(mode);
10820 return NULL;
10821 }
10822
10823 /*
10824 * Construct a pipe_config sufficient for getting the clock info
10825 * back out of crtc_clock_get.
10826 *
10827 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10828 * to use a real value here instead.
10829 */
10830 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10831 pipe_config->pixel_multiplier = 1;
10832 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10833 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10834 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10835 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10836
10837 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10838 mode->hdisplay = (htot & 0xffff) + 1;
10839 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10840 mode->hsync_start = (hsync & 0xffff) + 1;
10841 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10842 mode->vdisplay = (vtot & 0xffff) + 1;
10843 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10844 mode->vsync_start = (vsync & 0xffff) + 1;
10845 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10846
10847 drm_mode_set_name(mode);
10848
10849 kfree(pipe_config);
10850
10851 return mode;
10852 }
10853
10854 void intel_mark_busy(struct drm_i915_private *dev_priv)
10855 {
10856 if (dev_priv->mm.busy)
10857 return;
10858
10859 intel_runtime_pm_get(dev_priv);
10860 i915_update_gfx_val(dev_priv);
10861 if (INTEL_GEN(dev_priv) >= 6)
10862 gen6_rps_busy(dev_priv);
10863 dev_priv->mm.busy = true;
10864 }
10865
10866 void intel_mark_idle(struct drm_i915_private *dev_priv)
10867 {
10868 if (!dev_priv->mm.busy)
10869 return;
10870
10871 dev_priv->mm.busy = false;
10872
10873 if (INTEL_GEN(dev_priv) >= 6)
10874 gen6_rps_idle(dev_priv);
10875
10876 intel_runtime_pm_put(dev_priv);
10877 }
10878
10879 void intel_free_flip_work(struct intel_flip_work *work)
10880 {
10881 kfree(work->old_connector_state);
10882 kfree(work->new_connector_state);
10883 kfree(work);
10884 }
10885
10886 static void intel_crtc_destroy(struct drm_crtc *crtc)
10887 {
10888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10889 struct drm_device *dev = crtc->dev;
10890 struct intel_flip_work *work;
10891
10892 spin_lock_irq(&dev->event_lock);
10893 while (!list_empty(&intel_crtc->flip_work)) {
10894 work = list_first_entry(&intel_crtc->flip_work,
10895 struct intel_flip_work, head);
10896 list_del_init(&work->head);
10897 spin_unlock_irq(&dev->event_lock);
10898
10899 cancel_work_sync(&work->mmio_work);
10900 cancel_work_sync(&work->unpin_work);
10901 intel_free_flip_work(work);
10902
10903 spin_lock_irq(&dev->event_lock);
10904 }
10905 spin_unlock_irq(&dev->event_lock);
10906
10907 drm_crtc_cleanup(crtc);
10908
10909 kfree(intel_crtc);
10910 }
10911
10912 static void intel_crtc_post_flip_update(struct intel_flip_work *work,
10913 struct drm_crtc *crtc)
10914 {
10915 struct intel_crtc_state *crtc_state = work->new_crtc_state;
10916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10917
10918 if (crtc_state->disable_cxsr)
10919 intel_crtc->wm.cxsr_allowed = true;
10920
10921 if (crtc_state->update_wm_post && crtc_state->base.active)
10922 intel_update_watermarks(crtc);
10923
10924 if (work->num_planes > 0 &&
10925 work->old_plane_state[0]->base.plane == crtc->primary) {
10926 struct intel_plane_state *plane_state =
10927 work->new_plane_state[0];
10928
10929 if (plane_state->visible &&
10930 (needs_modeset(&crtc_state->base) ||
10931 !work->old_plane_state[0]->visible))
10932 intel_post_enable_primary(crtc);
10933 }
10934 }
10935
10936 static void intel_unpin_work_fn(struct work_struct *__work)
10937 {
10938 struct intel_flip_work *work =
10939 container_of(__work, struct intel_flip_work, unpin_work);
10940 struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
10941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10942 struct drm_device *dev = crtc->dev;
10943 struct drm_i915_private *dev_priv = dev->dev_private;
10944 int i;
10945
10946 if (work->fb_bits)
10947 intel_frontbuffer_flip_complete(dev, work->fb_bits);
10948
10949 /*
10950 * Unless work->can_async_unpin is false, there's no way to ensure
10951 * that work->new_crtc_state contains valid memory during unpin
10952 * because intel_atomic_commit may free it before this runs.
10953 */
10954 if (!work->can_async_unpin) {
10955 intel_crtc_post_flip_update(work, crtc);
10956
10957 if (dev_priv->display.optimize_watermarks)
10958 dev_priv->display.optimize_watermarks(work->new_crtc_state);
10959 }
10960
10961 if (work->fb_bits & to_intel_plane(crtc->primary)->frontbuffer_bit)
10962 intel_fbc_post_update(intel_crtc);
10963
10964 if (work->put_power_domains)
10965 modeset_put_power_domains(dev_priv, work->put_power_domains);
10966
10967 /* Make sure mmio work is completely finished before freeing all state here. */
10968 flush_work(&work->mmio_work);
10969
10970 if (!work->can_async_unpin &&
10971 (work->new_crtc_state->update_pipe ||
10972 needs_modeset(&work->new_crtc_state->base))) {
10973 /* This must be called before work is unpinned for serialization. */
10974 intel_modeset_verify_crtc(crtc, &work->old_crtc_state->base,
10975 &work->new_crtc_state->base);
10976
10977 for (i = 0; i < work->num_new_connectors; i++) {
10978 struct drm_connector_state *conn_state =
10979 work->new_connector_state[i];
10980 struct drm_connector *con = conn_state->connector;
10981
10982 WARN_ON(!con);
10983
10984 intel_connector_verify_state(to_intel_connector(con),
10985 conn_state);
10986 }
10987 }
10988
10989 for (i = 0; i < work->num_old_connectors; i++) {
10990 struct drm_connector_state *old_con_state =
10991 work->old_connector_state[i];
10992 struct drm_connector *con =
10993 old_con_state->connector;
10994
10995 con->funcs->atomic_destroy_state(con, old_con_state);
10996 }
10997
10998 if (!work->can_async_unpin || !list_empty(&work->head)) {
10999 spin_lock_irq(&dev->event_lock);
11000 WARN(list_empty(&work->head) != work->can_async_unpin,
11001 "[CRTC:%i] Pin work %p async %i with %i planes, active %i -> %i ms %i\n",
11002 crtc->base.id, work, work->can_async_unpin, work->num_planes,
11003 work->old_crtc_state->base.active, work->new_crtc_state->base.active,
11004 needs_modeset(&work->new_crtc_state->base));
11005
11006 if (!list_empty(&work->head))
11007 list_del(&work->head);
11008
11009 wake_up_all(&dev_priv->pending_flip_queue);
11010 spin_unlock_irq(&dev->event_lock);
11011 }
11012
11013 /* New crtc_state freed? */
11014 if (work->free_new_crtc_state)
11015 intel_crtc_destroy_state(crtc, &work->new_crtc_state->base);
11016
11017 intel_crtc_destroy_state(crtc, &work->old_crtc_state->base);
11018
11019 for (i = 0; i < work->num_planes; i++) {
11020 struct intel_plane_state *old_plane_state =
11021 work->old_plane_state[i];
11022 struct drm_framebuffer *old_fb = old_plane_state->base.fb;
11023 struct drm_plane *plane = old_plane_state->base.plane;
11024 struct drm_i915_gem_request *req;
11025
11026 req = old_plane_state->wait_req;
11027 old_plane_state->wait_req = NULL;
11028 if (req)
11029 i915_gem_request_unreference(req);
11030
11031 fence_put(old_plane_state->base.fence);
11032 old_plane_state->base.fence = NULL;
11033
11034 if (old_fb &&
11035 (plane->type != DRM_PLANE_TYPE_CURSOR ||
11036 !INTEL_INFO(dev_priv)->cursor_needs_physical)) {
11037 mutex_lock(&dev->struct_mutex);
11038 intel_unpin_fb_obj(old_fb, old_plane_state->base.rotation);
11039 mutex_unlock(&dev->struct_mutex);
11040 }
11041
11042 intel_plane_destroy_state(plane, &old_plane_state->base);
11043 }
11044
11045 if (!WARN_ON(atomic_read(&intel_crtc->unpin_work_count) == 0))
11046 atomic_dec(&intel_crtc->unpin_work_count);
11047
11048 intel_free_flip_work(work);
11049 }
11050
11051
11052 static bool pageflip_finished(struct intel_crtc *crtc,
11053 struct intel_flip_work *work)
11054 {
11055 if (!atomic_read(&work->pending))
11056 return false;
11057
11058 smp_rmb();
11059
11060 /*
11061 * MMIO work completes when vblank is different from
11062 * flip_queued_vblank.
11063 */
11064 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11065 }
11066
11067 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11068 {
11069 struct drm_device *dev = dev_priv->dev;
11070 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11072 struct intel_flip_work *work;
11073 unsigned long flags;
11074
11075 /* Ignore early vblank irqs */
11076 if (!crtc)
11077 return;
11078
11079 /*
11080 * This is called both by irq handlers and the reset code (to complete
11081 * lost pageflips) so needs the full irqsave spinlocks.
11082 */
11083 spin_lock_irqsave(&dev->event_lock, flags);
11084 while (!list_empty(&intel_crtc->flip_work)) {
11085 work = list_first_entry(&intel_crtc->flip_work,
11086 struct intel_flip_work,
11087 head);
11088
11089 if (!pageflip_finished(intel_crtc, work) ||
11090 work_busy(&work->unpin_work))
11091 break;
11092
11093 page_flip_completed(intel_crtc, work);
11094 }
11095 spin_unlock_irqrestore(&dev->event_lock, flags);
11096 }
11097
11098 static void intel_mmio_flip_work_func(struct work_struct *w)
11099 {
11100 struct intel_flip_work *work =
11101 container_of(w, struct intel_flip_work, mmio_work);
11102 struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
11103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11104 struct intel_crtc_state *crtc_state = work->new_crtc_state;
11105 struct drm_device *dev = crtc->dev;
11106 struct drm_i915_private *dev_priv = dev->dev_private;
11107 struct drm_i915_gem_request *req;
11108 int i, ret;
11109
11110 if (!needs_modeset(&crtc_state->base) && crtc_state->update_pipe) {
11111 work->put_power_domains =
11112 modeset_get_crtc_power_domains(crtc, crtc_state);
11113 }
11114
11115 for (i = 0; i < work->num_planes; i++) {
11116 struct intel_plane_state *old_plane_state = work->old_plane_state[i];
11117
11118 /* For framebuffer backed by dmabuf, wait for fence */
11119 if (old_plane_state->base.fence)
11120 WARN_ON(fence_wait(old_plane_state->base.fence, false) < 0);
11121
11122 req = old_plane_state->wait_req;
11123 if (!req)
11124 continue;
11125
11126 WARN_ON(__i915_wait_request(req, false, NULL,
11127 &dev_priv->rps.mmioflips));
11128 }
11129
11130 ret = drm_crtc_vblank_get(crtc);
11131 I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
11132
11133 if (work->num_planes &&
11134 work->old_plane_state[0]->base.plane == crtc->primary)
11135 intel_fbc_enable(intel_crtc, work->new_crtc_state, work->new_plane_state[0]);
11136
11137 intel_frontbuffer_flip_prepare(dev, work->fb_bits);
11138
11139 intel_pipe_update_start(intel_crtc);
11140 if (!needs_modeset(&crtc_state->base)) {
11141 if (crtc_state->base.color_mgmt_changed || crtc_state->update_pipe) {
11142 intel_color_set_csc(&crtc_state->base);
11143 intel_color_load_luts(&crtc_state->base);
11144 }
11145
11146 if (crtc_state->update_pipe)
11147 intel_update_pipe_config(intel_crtc, work->old_crtc_state);
11148 else if (INTEL_INFO(dev)->gen >= 9)
11149 skl_detach_scalers(intel_crtc);
11150 }
11151
11152 for (i = 0; i < work->num_planes; i++) {
11153 struct intel_plane_state *new_plane_state = work->new_plane_state[i];
11154 struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
11155
11156 if (new_plane_state->visible)
11157 plane->update_plane(&plane->base, crtc_state, new_plane_state);
11158 else
11159 plane->disable_plane(&plane->base, crtc);
11160 }
11161
11162 intel_pipe_update_end(intel_crtc, work);
11163 }
11164
11165 /**
11166 * intel_wm_need_update - Check whether watermarks need updating
11167 * @plane: drm plane
11168 * @state: new plane state
11169 *
11170 * Check current plane state versus the new one to determine whether
11171 * watermarks need to be recalculated.
11172 *
11173 * Returns true or false.
11174 */
11175 static bool intel_wm_need_update(struct drm_plane *plane,
11176 struct drm_plane_state *state)
11177 {
11178 struct intel_plane_state *new = to_intel_plane_state(state);
11179 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11180
11181 /* Update watermarks on tiling or size changes. */
11182 if (new->visible != cur->visible)
11183 return true;
11184
11185 if (!cur->base.fb || !new->base.fb)
11186 return false;
11187
11188 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11189 cur->base.rotation != new->base.rotation ||
11190 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11191 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11192 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11193 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11194 return true;
11195
11196 return false;
11197 }
11198
11199 static bool needs_scaling(struct intel_plane_state *state)
11200 {
11201 int src_w = drm_rect_width(&state->src) >> 16;
11202 int src_h = drm_rect_height(&state->src) >> 16;
11203 int dst_w = drm_rect_width(&state->dst);
11204 int dst_h = drm_rect_height(&state->dst);
11205
11206 return (src_w != dst_w || src_h != dst_h);
11207 }
11208
11209 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11210 struct drm_plane_state *plane_state)
11211 {
11212 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11213 struct drm_crtc *crtc = crtc_state->crtc;
11214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11215 struct drm_plane *plane = plane_state->plane;
11216 struct drm_device *dev = crtc->dev;
11217 struct drm_i915_private *dev_priv = to_i915(dev);
11218 struct intel_plane_state *old_plane_state =
11219 to_intel_plane_state(plane->state);
11220 int idx = intel_crtc->base.base.id, ret;
11221 bool mode_changed = needs_modeset(crtc_state);
11222 bool was_crtc_enabled = crtc->state->active;
11223 bool is_crtc_enabled = crtc_state->active;
11224 bool turn_off, turn_on, visible, was_visible;
11225 struct drm_framebuffer *fb = plane_state->fb;
11226
11227 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11228 plane->type != DRM_PLANE_TYPE_CURSOR) {
11229 ret = skl_update_scaler_plane(
11230 to_intel_crtc_state(crtc_state),
11231 to_intel_plane_state(plane_state));
11232 if (ret)
11233 return ret;
11234 }
11235
11236 was_visible = old_plane_state->visible;
11237 visible = to_intel_plane_state(plane_state)->visible;
11238
11239 if (!was_crtc_enabled && WARN_ON(was_visible))
11240 was_visible = false;
11241
11242 /*
11243 * Visibility is calculated as if the crtc was on, but
11244 * after scaler setup everything depends on it being off
11245 * when the crtc isn't active.
11246 *
11247 * FIXME this is wrong for watermarks. Watermarks should also
11248 * be computed as if the pipe would be active. Perhaps move
11249 * per-plane wm computation to the .check_plane() hook, and
11250 * only combine the results from all planes in the current place?
11251 */
11252 if (!is_crtc_enabled)
11253 to_intel_plane_state(plane_state)->visible = visible = false;
11254
11255 if (!was_visible && !visible)
11256 return 0;
11257
11258 if (fb != old_plane_state->base.fb)
11259 pipe_config->fb_changed = true;
11260
11261 turn_off = was_visible && (!visible || mode_changed);
11262 turn_on = visible && (!was_visible || mode_changed);
11263
11264 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11265 plane->base.id, fb ? fb->base.id : -1);
11266
11267 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11268 plane->base.id, was_visible, visible,
11269 turn_off, turn_on, mode_changed);
11270
11271 if (turn_on) {
11272 pipe_config->update_wm_pre = true;
11273
11274 /* must disable cxsr around plane enable/disable */
11275 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11276 pipe_config->disable_cxsr = true;
11277 } else if (turn_off) {
11278 pipe_config->update_wm_post = true;
11279
11280 /* must disable cxsr around plane enable/disable */
11281 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11282 pipe_config->disable_cxsr = true;
11283 } else if (intel_wm_need_update(plane, plane_state)) {
11284 /* FIXME bollocks */
11285 pipe_config->update_wm_pre = true;
11286 pipe_config->update_wm_post = true;
11287 }
11288
11289 /* Pre-gen9 platforms need two-step watermark updates */
11290 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11291 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11292 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11293
11294 if (visible || was_visible)
11295 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11296
11297 /*
11298 * WaCxSRDisabledForSpriteScaling:ivb
11299 *
11300 * cstate->update_wm was already set above, so this flag will
11301 * take effect when we commit and program watermarks.
11302 */
11303 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11304 needs_scaling(to_intel_plane_state(plane_state)) &&
11305 !needs_scaling(old_plane_state))
11306 pipe_config->disable_lp_wm = true;
11307
11308 return 0;
11309 }
11310
11311 static bool encoders_cloneable(const struct intel_encoder *a,
11312 const struct intel_encoder *b)
11313 {
11314 /* masks could be asymmetric, so check both ways */
11315 return a == b || (a->cloneable & (1 << b->type) &&
11316 b->cloneable & (1 << a->type));
11317 }
11318
11319 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11320 struct intel_crtc *crtc,
11321 struct intel_encoder *encoder)
11322 {
11323 struct intel_encoder *source_encoder;
11324 struct drm_connector *connector;
11325 struct drm_connector_state *connector_state;
11326 int i;
11327
11328 for_each_connector_in_state(state, connector, connector_state, i) {
11329 if (connector_state->crtc != &crtc->base)
11330 continue;
11331
11332 source_encoder =
11333 to_intel_encoder(connector_state->best_encoder);
11334 if (!encoders_cloneable(encoder, source_encoder))
11335 return false;
11336 }
11337
11338 return true;
11339 }
11340
11341 static bool check_encoder_cloning(struct drm_atomic_state *state,
11342 struct intel_crtc *crtc)
11343 {
11344 struct intel_encoder *encoder;
11345 struct drm_connector *connector;
11346 struct drm_connector_state *connector_state;
11347 int i;
11348
11349 for_each_connector_in_state(state, connector, connector_state, i) {
11350 if (connector_state->crtc != &crtc->base)
11351 continue;
11352
11353 encoder = to_intel_encoder(connector_state->best_encoder);
11354 if (!check_single_encoder_cloning(state, crtc, encoder))
11355 return false;
11356 }
11357
11358 return true;
11359 }
11360
11361 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11362 struct drm_crtc_state *crtc_state)
11363 {
11364 struct drm_device *dev = crtc->dev;
11365 struct drm_i915_private *dev_priv = dev->dev_private;
11366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11367 struct intel_crtc_state *pipe_config =
11368 to_intel_crtc_state(crtc_state);
11369 struct drm_atomic_state *state = crtc_state->state;
11370 int ret;
11371 bool mode_changed = needs_modeset(crtc_state);
11372
11373 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11374 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11375 return -EINVAL;
11376 }
11377
11378 if (mode_changed && !crtc_state->active)
11379 pipe_config->update_wm_post = true;
11380
11381 if (mode_changed && crtc_state->enable &&
11382 dev_priv->display.crtc_compute_clock &&
11383 !WARN_ON(pipe_config->shared_dpll)) {
11384 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11385 pipe_config);
11386 if (ret)
11387 return ret;
11388 }
11389
11390 if (crtc_state->color_mgmt_changed) {
11391 ret = intel_color_check(crtc, crtc_state);
11392 if (ret)
11393 return ret;
11394 }
11395
11396 ret = 0;
11397 if (dev_priv->display.compute_pipe_wm) {
11398 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11399 if (ret) {
11400 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11401 return ret;
11402 }
11403 }
11404
11405 if (dev_priv->display.compute_intermediate_wm &&
11406 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11407 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11408 return 0;
11409
11410 /*
11411 * Calculate 'intermediate' watermarks that satisfy both the
11412 * old state and the new state. We can program these
11413 * immediately.
11414 */
11415 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11416 intel_crtc,
11417 pipe_config);
11418 if (ret) {
11419 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11420 return ret;
11421 }
11422 } else if (dev_priv->display.compute_intermediate_wm) {
11423 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11424 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11425 }
11426
11427 if (INTEL_INFO(dev)->gen >= 9) {
11428 if (mode_changed)
11429 ret = skl_update_scaler_crtc(pipe_config);
11430
11431 if (!ret)
11432 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11433 pipe_config);
11434 }
11435
11436 return ret;
11437 }
11438
11439 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11440 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11441 .atomic_check = intel_crtc_atomic_check,
11442 };
11443
11444 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11445 {
11446 struct intel_connector *connector;
11447
11448 for_each_intel_connector(dev, connector) {
11449 if (connector->base.state->crtc)
11450 drm_connector_unreference(&connector->base);
11451
11452 if (connector->base.encoder) {
11453 connector->base.state->best_encoder =
11454 connector->base.encoder;
11455 connector->base.state->crtc =
11456 connector->base.encoder->crtc;
11457
11458 drm_connector_reference(&connector->base);
11459 } else {
11460 connector->base.state->best_encoder = NULL;
11461 connector->base.state->crtc = NULL;
11462 }
11463 }
11464 }
11465
11466 static void
11467 connected_sink_compute_bpp(struct intel_connector *connector,
11468 struct intel_crtc_state *pipe_config)
11469 {
11470 int bpp = pipe_config->pipe_bpp;
11471
11472 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11473 connector->base.base.id,
11474 connector->base.name);
11475
11476 /* Don't use an invalid EDID bpc value */
11477 if (connector->base.display_info.bpc &&
11478 connector->base.display_info.bpc * 3 < bpp) {
11479 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11480 bpp, connector->base.display_info.bpc*3);
11481 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11482 }
11483
11484 /* Clamp bpp to default limit on screens without EDID 1.4 */
11485 if (connector->base.display_info.bpc == 0) {
11486 int type = connector->base.connector_type;
11487 int clamp_bpp = 24;
11488
11489 /* Fall back to 18 bpp when DP sink capability is unknown. */
11490 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
11491 type == DRM_MODE_CONNECTOR_eDP)
11492 clamp_bpp = 18;
11493
11494 if (bpp > clamp_bpp) {
11495 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
11496 bpp, clamp_bpp);
11497 pipe_config->pipe_bpp = clamp_bpp;
11498 }
11499 }
11500 }
11501
11502 static int
11503 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11504 struct intel_crtc_state *pipe_config)
11505 {
11506 struct drm_device *dev = crtc->base.dev;
11507 struct drm_atomic_state *state;
11508 struct drm_connector *connector;
11509 struct drm_connector_state *connector_state;
11510 int bpp, i;
11511
11512 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
11513 bpp = 10*3;
11514 else if (INTEL_INFO(dev)->gen >= 5)
11515 bpp = 12*3;
11516 else
11517 bpp = 8*3;
11518
11519
11520 pipe_config->pipe_bpp = bpp;
11521
11522 state = pipe_config->base.state;
11523
11524 /* Clamp display bpp to EDID value */
11525 for_each_connector_in_state(state, connector, connector_state, i) {
11526 if (connector_state->crtc != &crtc->base)
11527 continue;
11528
11529 connected_sink_compute_bpp(to_intel_connector(connector),
11530 pipe_config);
11531 }
11532
11533 return bpp;
11534 }
11535
11536 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11537 {
11538 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11539 "type: 0x%x flags: 0x%x\n",
11540 mode->crtc_clock,
11541 mode->crtc_hdisplay, mode->crtc_hsync_start,
11542 mode->crtc_hsync_end, mode->crtc_htotal,
11543 mode->crtc_vdisplay, mode->crtc_vsync_start,
11544 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11545 }
11546
11547 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11548 struct intel_crtc_state *pipe_config,
11549 const char *context)
11550 {
11551 struct drm_device *dev = crtc->base.dev;
11552 struct drm_plane *plane;
11553 struct intel_plane *intel_plane;
11554 struct intel_plane_state *state;
11555 struct drm_framebuffer *fb;
11556
11557 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11558 context, pipe_config, pipe_name(crtc->pipe));
11559
11560 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
11561 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11562 pipe_config->pipe_bpp, pipe_config->dither);
11563 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11564 pipe_config->has_pch_encoder,
11565 pipe_config->fdi_lanes,
11566 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11567 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11568 pipe_config->fdi_m_n.tu);
11569 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11570 pipe_config->has_dp_encoder,
11571 pipe_config->lane_count,
11572 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11573 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11574 pipe_config->dp_m_n.tu);
11575
11576 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11577 pipe_config->has_dp_encoder,
11578 pipe_config->lane_count,
11579 pipe_config->dp_m2_n2.gmch_m,
11580 pipe_config->dp_m2_n2.gmch_n,
11581 pipe_config->dp_m2_n2.link_m,
11582 pipe_config->dp_m2_n2.link_n,
11583 pipe_config->dp_m2_n2.tu);
11584
11585 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11586 pipe_config->has_audio,
11587 pipe_config->has_infoframe);
11588
11589 DRM_DEBUG_KMS("requested mode:\n");
11590 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11591 DRM_DEBUG_KMS("adjusted mode:\n");
11592 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11593 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11594 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11595 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11596 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11597 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11598 crtc->num_scalers,
11599 pipe_config->scaler_state.scaler_users,
11600 pipe_config->scaler_state.scaler_id);
11601 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11602 pipe_config->gmch_pfit.control,
11603 pipe_config->gmch_pfit.pgm_ratios,
11604 pipe_config->gmch_pfit.lvds_border_bits);
11605 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11606 pipe_config->pch_pfit.pos,
11607 pipe_config->pch_pfit.size,
11608 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11609 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11610 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11611
11612 if (IS_BROXTON(dev)) {
11613 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11614 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11615 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11616 pipe_config->ddi_pll_sel,
11617 pipe_config->dpll_hw_state.ebb0,
11618 pipe_config->dpll_hw_state.ebb4,
11619 pipe_config->dpll_hw_state.pll0,
11620 pipe_config->dpll_hw_state.pll1,
11621 pipe_config->dpll_hw_state.pll2,
11622 pipe_config->dpll_hw_state.pll3,
11623 pipe_config->dpll_hw_state.pll6,
11624 pipe_config->dpll_hw_state.pll8,
11625 pipe_config->dpll_hw_state.pll9,
11626 pipe_config->dpll_hw_state.pll10,
11627 pipe_config->dpll_hw_state.pcsdw12);
11628 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
11629 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11630 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11631 pipe_config->ddi_pll_sel,
11632 pipe_config->dpll_hw_state.ctrl1,
11633 pipe_config->dpll_hw_state.cfgcr1,
11634 pipe_config->dpll_hw_state.cfgcr2);
11635 } else if (HAS_DDI(dev)) {
11636 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
11637 pipe_config->ddi_pll_sel,
11638 pipe_config->dpll_hw_state.wrpll,
11639 pipe_config->dpll_hw_state.spll);
11640 } else {
11641 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11642 "fp0: 0x%x, fp1: 0x%x\n",
11643 pipe_config->dpll_hw_state.dpll,
11644 pipe_config->dpll_hw_state.dpll_md,
11645 pipe_config->dpll_hw_state.fp0,
11646 pipe_config->dpll_hw_state.fp1);
11647 }
11648
11649 DRM_DEBUG_KMS("planes on this crtc\n");
11650 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11651 intel_plane = to_intel_plane(plane);
11652 if (intel_plane->pipe != crtc->pipe)
11653 continue;
11654
11655 state = to_intel_plane_state(plane->state);
11656 fb = state->base.fb;
11657 if (!fb) {
11658 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11659 "disabled, scaler_id = %d\n",
11660 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11661 plane->base.id, intel_plane->pipe,
11662 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11663 drm_plane_index(plane), state->scaler_id);
11664 continue;
11665 }
11666
11667 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11668 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11669 plane->base.id, intel_plane->pipe,
11670 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11671 drm_plane_index(plane));
11672 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11673 fb->base.id, fb->width, fb->height, fb->pixel_format);
11674 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11675 state->scaler_id,
11676 state->src.x1 >> 16, state->src.y1 >> 16,
11677 drm_rect_width(&state->src) >> 16,
11678 drm_rect_height(&state->src) >> 16,
11679 state->dst.x1, state->dst.y1,
11680 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11681 }
11682 }
11683
11684 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11685 {
11686 struct drm_device *dev = state->dev;
11687 struct drm_connector *connector;
11688 unsigned int used_ports = 0;
11689
11690 /*
11691 * Walk the connector list instead of the encoder
11692 * list to detect the problem on ddi platforms
11693 * where there's just one encoder per digital port.
11694 */
11695 drm_for_each_connector(connector, dev) {
11696 struct drm_connector_state *connector_state;
11697 struct intel_encoder *encoder;
11698
11699 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11700 if (!connector_state)
11701 connector_state = connector->state;
11702
11703 if (!connector_state->best_encoder)
11704 continue;
11705
11706 encoder = to_intel_encoder(connector_state->best_encoder);
11707
11708 WARN_ON(!connector_state->crtc);
11709
11710 switch (encoder->type) {
11711 unsigned int port_mask;
11712 case INTEL_OUTPUT_UNKNOWN:
11713 if (WARN_ON(!HAS_DDI(dev)))
11714 break;
11715 case INTEL_OUTPUT_DISPLAYPORT:
11716 case INTEL_OUTPUT_HDMI:
11717 case INTEL_OUTPUT_EDP:
11718 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11719
11720 /* the same port mustn't appear more than once */
11721 if (used_ports & port_mask)
11722 return false;
11723
11724 used_ports |= port_mask;
11725 default:
11726 break;
11727 }
11728 }
11729
11730 return true;
11731 }
11732
11733 static void
11734 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11735 {
11736 struct drm_crtc_state tmp_state;
11737 struct intel_crtc_scaler_state scaler_state;
11738 struct intel_dpll_hw_state dpll_hw_state;
11739 struct intel_shared_dpll *shared_dpll;
11740 uint32_t ddi_pll_sel;
11741 bool force_thru;
11742
11743 /* FIXME: before the switch to atomic started, a new pipe_config was
11744 * kzalloc'd. Code that depends on any field being zero should be
11745 * fixed, so that the crtc_state can be safely duplicated. For now,
11746 * only fields that are know to not cause problems are preserved. */
11747
11748 tmp_state = crtc_state->base;
11749 scaler_state = crtc_state->scaler_state;
11750 shared_dpll = crtc_state->shared_dpll;
11751 dpll_hw_state = crtc_state->dpll_hw_state;
11752 ddi_pll_sel = crtc_state->ddi_pll_sel;
11753 force_thru = crtc_state->pch_pfit.force_thru;
11754
11755 memset(crtc_state, 0, sizeof *crtc_state);
11756
11757 crtc_state->base = tmp_state;
11758 crtc_state->scaler_state = scaler_state;
11759 crtc_state->shared_dpll = shared_dpll;
11760 crtc_state->dpll_hw_state = dpll_hw_state;
11761 crtc_state->ddi_pll_sel = ddi_pll_sel;
11762 crtc_state->pch_pfit.force_thru = force_thru;
11763 }
11764
11765 static int
11766 intel_modeset_pipe_config(struct drm_crtc *crtc,
11767 struct intel_crtc_state *pipe_config)
11768 {
11769 struct drm_atomic_state *state = pipe_config->base.state;
11770 struct intel_encoder *encoder;
11771 struct drm_connector *connector;
11772 struct drm_connector_state *connector_state;
11773 int base_bpp, ret = -EINVAL;
11774 int i;
11775 bool retry = true;
11776
11777 clear_intel_crtc_state(pipe_config);
11778
11779 pipe_config->cpu_transcoder =
11780 (enum transcoder) to_intel_crtc(crtc)->pipe;
11781
11782 /*
11783 * Sanitize sync polarity flags based on requested ones. If neither
11784 * positive or negative polarity is requested, treat this as meaning
11785 * negative polarity.
11786 */
11787 if (!(pipe_config->base.adjusted_mode.flags &
11788 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11789 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11790
11791 if (!(pipe_config->base.adjusted_mode.flags &
11792 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11793 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11794
11795 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11796 pipe_config);
11797 if (base_bpp < 0)
11798 goto fail;
11799
11800 /*
11801 * Determine the real pipe dimensions. Note that stereo modes can
11802 * increase the actual pipe size due to the frame doubling and
11803 * insertion of additional space for blanks between the frame. This
11804 * is stored in the crtc timings. We use the requested mode to do this
11805 * computation to clearly distinguish it from the adjusted mode, which
11806 * can be changed by the connectors in the below retry loop.
11807 */
11808 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11809 &pipe_config->pipe_src_w,
11810 &pipe_config->pipe_src_h);
11811
11812 encoder_retry:
11813 /* Ensure the port clock defaults are reset when retrying. */
11814 pipe_config->port_clock = 0;
11815 pipe_config->pixel_multiplier = 1;
11816
11817 /* Fill in default crtc timings, allow encoders to overwrite them. */
11818 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11819 CRTC_STEREO_DOUBLE);
11820
11821 /* Pass our mode to the connectors and the CRTC to give them a chance to
11822 * adjust it according to limitations or connector properties, and also
11823 * a chance to reject the mode entirely.
11824 */
11825 for_each_connector_in_state(state, connector, connector_state, i) {
11826 if (connector_state->crtc != crtc)
11827 continue;
11828
11829 encoder = to_intel_encoder(connector_state->best_encoder);
11830
11831 if (!(encoder->compute_config(encoder, pipe_config))) {
11832 DRM_DEBUG_KMS("Encoder config failure\n");
11833 goto fail;
11834 }
11835 }
11836
11837 /* Set default port clock if not overwritten by the encoder. Needs to be
11838 * done afterwards in case the encoder adjusts the mode. */
11839 if (!pipe_config->port_clock)
11840 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11841 * pipe_config->pixel_multiplier;
11842
11843 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11844 if (ret < 0) {
11845 DRM_DEBUG_KMS("CRTC fixup failed\n");
11846 goto fail;
11847 }
11848
11849 if (ret == RETRY) {
11850 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11851 ret = -EINVAL;
11852 goto fail;
11853 }
11854
11855 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11856 retry = false;
11857 goto encoder_retry;
11858 }
11859
11860 /* Dithering seems to not pass-through bits correctly when it should, so
11861 * only enable it on 6bpc panels. */
11862 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
11863 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11864 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11865
11866 fail:
11867 return ret;
11868 }
11869
11870 static void
11871 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11872 {
11873 struct drm_crtc *crtc;
11874 struct drm_crtc_state *crtc_state;
11875 int i;
11876
11877 /* Double check state. */
11878 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11879 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11880
11881 /* Update hwmode for vblank functions */
11882 if (crtc->state->active)
11883 crtc->hwmode = crtc->state->adjusted_mode;
11884 else
11885 crtc->hwmode.crtc_clock = 0;
11886
11887 /*
11888 * Update legacy state to satisfy fbc code. This can
11889 * be removed when fbc uses the atomic state.
11890 */
11891 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11892 struct drm_plane_state *plane_state = crtc->primary->state;
11893
11894 crtc->primary->fb = plane_state->fb;
11895 crtc->x = plane_state->src_x >> 16;
11896 crtc->y = plane_state->src_y >> 16;
11897 }
11898 }
11899 }
11900
11901 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11902 {
11903 int diff;
11904
11905 if (clock1 == clock2)
11906 return true;
11907
11908 if (!clock1 || !clock2)
11909 return false;
11910
11911 diff = abs(clock1 - clock2);
11912
11913 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11914 return true;
11915
11916 return false;
11917 }
11918
11919 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11920 list_for_each_entry((intel_crtc), \
11921 &(dev)->mode_config.crtc_list, \
11922 base.head) \
11923 for_each_if (mask & (1 <<(intel_crtc)->pipe))
11924
11925 static bool
11926 intel_compare_m_n(unsigned int m, unsigned int n,
11927 unsigned int m2, unsigned int n2,
11928 bool exact)
11929 {
11930 if (m == m2 && n == n2)
11931 return true;
11932
11933 if (exact || !m || !n || !m2 || !n2)
11934 return false;
11935
11936 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11937
11938 if (n > n2) {
11939 while (n > n2) {
11940 m2 <<= 1;
11941 n2 <<= 1;
11942 }
11943 } else if (n < n2) {
11944 while (n < n2) {
11945 m <<= 1;
11946 n <<= 1;
11947 }
11948 }
11949
11950 if (n != n2)
11951 return false;
11952
11953 return intel_fuzzy_clock_check(m, m2);
11954 }
11955
11956 static bool
11957 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11958 struct intel_link_m_n *m2_n2,
11959 bool adjust)
11960 {
11961 if (m_n->tu == m2_n2->tu &&
11962 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11963 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11964 intel_compare_m_n(m_n->link_m, m_n->link_n,
11965 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11966 if (adjust)
11967 *m2_n2 = *m_n;
11968
11969 return true;
11970 }
11971
11972 return false;
11973 }
11974
11975 static bool
11976 intel_pipe_config_compare(struct drm_device *dev,
11977 struct intel_crtc_state *current_config,
11978 struct intel_crtc_state *pipe_config,
11979 bool adjust)
11980 {
11981 bool ret = true;
11982
11983 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
11984 do { \
11985 if (!adjust) \
11986 DRM_ERROR(fmt, ##__VA_ARGS__); \
11987 else \
11988 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
11989 } while (0)
11990
11991 #define PIPE_CONF_CHECK_X(name) \
11992 if (current_config->name != pipe_config->name) { \
11993 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11994 "(expected 0x%08x, found 0x%08x)\n", \
11995 current_config->name, \
11996 pipe_config->name); \
11997 ret = false; \
11998 }
11999
12000 #define PIPE_CONF_CHECK_I(name) \
12001 if (current_config->name != pipe_config->name) { \
12002 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12003 "(expected %i, found %i)\n", \
12004 current_config->name, \
12005 pipe_config->name); \
12006 ret = false; \
12007 }
12008
12009 #define PIPE_CONF_CHECK_P(name) \
12010 if (current_config->name != pipe_config->name) { \
12011 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12012 "(expected %p, found %p)\n", \
12013 current_config->name, \
12014 pipe_config->name); \
12015 ret = false; \
12016 }
12017
12018 #define PIPE_CONF_CHECK_M_N(name) \
12019 if (!intel_compare_link_m_n(&current_config->name, \
12020 &pipe_config->name,\
12021 adjust)) { \
12022 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12023 "(expected tu %i gmch %i/%i link %i/%i, " \
12024 "found tu %i, gmch %i/%i link %i/%i)\n", \
12025 current_config->name.tu, \
12026 current_config->name.gmch_m, \
12027 current_config->name.gmch_n, \
12028 current_config->name.link_m, \
12029 current_config->name.link_n, \
12030 pipe_config->name.tu, \
12031 pipe_config->name.gmch_m, \
12032 pipe_config->name.gmch_n, \
12033 pipe_config->name.link_m, \
12034 pipe_config->name.link_n); \
12035 ret = false; \
12036 }
12037
12038 /* This is required for BDW+ where there is only one set of registers for
12039 * switching between high and low RR.
12040 * This macro can be used whenever a comparison has to be made between one
12041 * hw state and multiple sw state variables.
12042 */
12043 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12044 if (!intel_compare_link_m_n(&current_config->name, \
12045 &pipe_config->name, adjust) && \
12046 !intel_compare_link_m_n(&current_config->alt_name, \
12047 &pipe_config->name, adjust)) { \
12048 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12049 "(expected tu %i gmch %i/%i link %i/%i, " \
12050 "or tu %i gmch %i/%i link %i/%i, " \
12051 "found tu %i, gmch %i/%i link %i/%i)\n", \
12052 current_config->name.tu, \
12053 current_config->name.gmch_m, \
12054 current_config->name.gmch_n, \
12055 current_config->name.link_m, \
12056 current_config->name.link_n, \
12057 current_config->alt_name.tu, \
12058 current_config->alt_name.gmch_m, \
12059 current_config->alt_name.gmch_n, \
12060 current_config->alt_name.link_m, \
12061 current_config->alt_name.link_n, \
12062 pipe_config->name.tu, \
12063 pipe_config->name.gmch_m, \
12064 pipe_config->name.gmch_n, \
12065 pipe_config->name.link_m, \
12066 pipe_config->name.link_n); \
12067 ret = false; \
12068 }
12069
12070 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12071 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12072 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12073 "(expected %i, found %i)\n", \
12074 current_config->name & (mask), \
12075 pipe_config->name & (mask)); \
12076 ret = false; \
12077 }
12078
12079 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12080 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12081 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12082 "(expected %i, found %i)\n", \
12083 current_config->name, \
12084 pipe_config->name); \
12085 ret = false; \
12086 }
12087
12088 #define PIPE_CONF_QUIRK(quirk) \
12089 ((current_config->quirks | pipe_config->quirks) & (quirk))
12090
12091 PIPE_CONF_CHECK_I(cpu_transcoder);
12092
12093 PIPE_CONF_CHECK_I(has_pch_encoder);
12094 PIPE_CONF_CHECK_I(fdi_lanes);
12095 PIPE_CONF_CHECK_M_N(fdi_m_n);
12096
12097 PIPE_CONF_CHECK_I(has_dp_encoder);
12098 PIPE_CONF_CHECK_I(lane_count);
12099
12100 if (INTEL_INFO(dev)->gen < 8) {
12101 PIPE_CONF_CHECK_M_N(dp_m_n);
12102
12103 if (current_config->has_drrs)
12104 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12105 } else
12106 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12107
12108 PIPE_CONF_CHECK_I(has_dsi_encoder);
12109
12110 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12111 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12112 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12113 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12114 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12115 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12116
12117 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12118 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12119 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12120 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12121 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12122 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12123
12124 PIPE_CONF_CHECK_I(pixel_multiplier);
12125 PIPE_CONF_CHECK_I(has_hdmi_sink);
12126 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12127 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12128 PIPE_CONF_CHECK_I(limited_color_range);
12129 PIPE_CONF_CHECK_I(has_infoframe);
12130
12131 PIPE_CONF_CHECK_I(has_audio);
12132
12133 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12134 DRM_MODE_FLAG_INTERLACE);
12135
12136 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12137 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12138 DRM_MODE_FLAG_PHSYNC);
12139 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12140 DRM_MODE_FLAG_NHSYNC);
12141 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12142 DRM_MODE_FLAG_PVSYNC);
12143 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12144 DRM_MODE_FLAG_NVSYNC);
12145 }
12146
12147 PIPE_CONF_CHECK_X(gmch_pfit.control);
12148 /* pfit ratios are autocomputed by the hw on gen4+ */
12149 if (INTEL_INFO(dev)->gen < 4)
12150 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12151 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12152
12153 if (!adjust) {
12154 PIPE_CONF_CHECK_I(pipe_src_w);
12155 PIPE_CONF_CHECK_I(pipe_src_h);
12156
12157 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12158 if (current_config->pch_pfit.enabled) {
12159 PIPE_CONF_CHECK_X(pch_pfit.pos);
12160 PIPE_CONF_CHECK_X(pch_pfit.size);
12161 }
12162
12163 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12164 }
12165
12166 /* BDW+ don't expose a synchronous way to read the state */
12167 if (IS_HASWELL(dev))
12168 PIPE_CONF_CHECK_I(ips_enabled);
12169
12170 PIPE_CONF_CHECK_I(double_wide);
12171
12172 PIPE_CONF_CHECK_X(ddi_pll_sel);
12173
12174 PIPE_CONF_CHECK_P(shared_dpll);
12175 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12176 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12177 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12178 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12179 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12180 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12181 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12182 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12183 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12184
12185 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12186 PIPE_CONF_CHECK_X(dsi_pll.div);
12187
12188 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12189 PIPE_CONF_CHECK_I(pipe_bpp);
12190
12191 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12192 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12193
12194 #undef PIPE_CONF_CHECK_X
12195 #undef PIPE_CONF_CHECK_I
12196 #undef PIPE_CONF_CHECK_P
12197 #undef PIPE_CONF_CHECK_FLAGS
12198 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12199 #undef PIPE_CONF_QUIRK
12200 #undef INTEL_ERR_OR_DBG_KMS
12201
12202 return ret;
12203 }
12204
12205 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12206 const struct intel_crtc_state *pipe_config)
12207 {
12208 if (pipe_config->has_pch_encoder) {
12209 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12210 &pipe_config->fdi_m_n);
12211 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12212
12213 /*
12214 * FDI already provided one idea for the dotclock.
12215 * Yell if the encoder disagrees.
12216 */
12217 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12218 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12219 fdi_dotclock, dotclock);
12220 }
12221 }
12222
12223 static void verify_wm_state(struct drm_crtc *crtc,
12224 struct drm_crtc_state *new_state)
12225 {
12226 struct drm_device *dev = crtc->dev;
12227 struct drm_i915_private *dev_priv = dev->dev_private;
12228 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12229 struct skl_ddb_entry *hw_entry, *sw_entry;
12230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12231 const enum pipe pipe = intel_crtc->pipe;
12232 int plane;
12233
12234 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12235 return;
12236
12237 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12238 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12239
12240 /* planes */
12241 for_each_plane(dev_priv, pipe, plane) {
12242 hw_entry = &hw_ddb.plane[pipe][plane];
12243 sw_entry = &sw_ddb->plane[pipe][plane];
12244
12245 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12246 continue;
12247
12248 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12249 "(expected (%u,%u), found (%u,%u))\n",
12250 pipe_name(pipe), plane + 1,
12251 sw_entry->start, sw_entry->end,
12252 hw_entry->start, hw_entry->end);
12253 }
12254
12255 /* cursor */
12256 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12257 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12258
12259 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12260 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12261 "(expected (%u,%u), found (%u,%u))\n",
12262 pipe_name(pipe),
12263 sw_entry->start, sw_entry->end,
12264 hw_entry->start, hw_entry->end);
12265 }
12266 }
12267
12268 static void
12269 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12270 {
12271 struct drm_connector *connector;
12272
12273 drm_for_each_connector(connector, dev) {
12274 struct drm_encoder *encoder = connector->encoder;
12275 struct drm_connector_state *state = connector->state;
12276
12277 if (state->crtc != crtc)
12278 continue;
12279
12280 intel_connector_verify_state(to_intel_connector(connector),
12281 connector->state);
12282
12283 I915_STATE_WARN(state->best_encoder != encoder,
12284 "connector's atomic encoder doesn't match legacy encoder\n");
12285 }
12286 }
12287
12288 static void
12289 verify_encoder_state(struct drm_device *dev)
12290 {
12291 struct intel_encoder *encoder;
12292 struct intel_connector *connector;
12293
12294 for_each_intel_encoder(dev, encoder) {
12295 bool enabled = false;
12296 enum pipe pipe;
12297
12298 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12299 encoder->base.base.id,
12300 encoder->base.name);
12301
12302 for_each_intel_connector(dev, connector) {
12303 if (connector->base.state->best_encoder != &encoder->base)
12304 continue;
12305 enabled = true;
12306
12307 I915_STATE_WARN(connector->base.state->crtc !=
12308 encoder->base.crtc,
12309 "connector's crtc doesn't match encoder crtc\n");
12310 }
12311
12312 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12313 "encoder's enabled state mismatch "
12314 "(expected %i, found %i)\n",
12315 !!encoder->base.crtc, enabled);
12316
12317 if (!encoder->base.crtc) {
12318 bool active;
12319
12320 active = encoder->get_hw_state(encoder, &pipe);
12321 I915_STATE_WARN(active,
12322 "encoder detached but still enabled on pipe %c.\n",
12323 pipe_name(pipe));
12324 }
12325 }
12326 }
12327
12328 static void
12329 verify_crtc_state(struct drm_crtc *crtc,
12330 struct drm_crtc_state *old_crtc_state,
12331 struct drm_crtc_state *new_crtc_state)
12332 {
12333 struct drm_device *dev = crtc->dev;
12334 struct drm_i915_private *dev_priv = dev->dev_private;
12335 struct intel_encoder *encoder;
12336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12337 struct intel_crtc_state *pipe_config, *sw_config;
12338 struct drm_atomic_state *old_state;
12339 bool active;
12340
12341 old_state = old_crtc_state->state;
12342 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12343 pipe_config = to_intel_crtc_state(old_crtc_state);
12344 memset(pipe_config, 0, sizeof(*pipe_config));
12345 pipe_config->base.crtc = crtc;
12346 pipe_config->base.state = old_state;
12347
12348 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12349
12350 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12351
12352 /* hw state is inconsistent with the pipe quirk */
12353 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12354 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12355 active = new_crtc_state->active;
12356
12357 I915_STATE_WARN(new_crtc_state->active != active,
12358 "crtc active state doesn't match with hw state "
12359 "(expected %i, found %i)\n", new_crtc_state->active, active);
12360
12361 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12362 "transitional active state does not match atomic hw state "
12363 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12364
12365 for_each_encoder_on_crtc(dev, crtc, encoder) {
12366 enum pipe pipe;
12367
12368 active = encoder->get_hw_state(encoder, &pipe);
12369 I915_STATE_WARN(active != new_crtc_state->active,
12370 "[ENCODER:%i] active %i with crtc active %i\n",
12371 encoder->base.base.id, active, new_crtc_state->active);
12372
12373 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12374 "Encoder connected to wrong pipe %c\n",
12375 pipe_name(pipe));
12376
12377 if (active)
12378 encoder->get_config(encoder, pipe_config);
12379 }
12380
12381 if (!new_crtc_state->active)
12382 return;
12383
12384 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12385
12386 sw_config = to_intel_crtc_state(crtc->state);
12387 if (!intel_pipe_config_compare(dev, sw_config,
12388 pipe_config, false)) {
12389 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12390 intel_dump_pipe_config(intel_crtc, pipe_config,
12391 "[hw state]");
12392 intel_dump_pipe_config(intel_crtc, sw_config,
12393 "[sw state]");
12394 }
12395 }
12396
12397 static void
12398 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12399 struct intel_shared_dpll *pll,
12400 struct drm_crtc *crtc,
12401 struct drm_crtc_state *new_state)
12402 {
12403 struct intel_dpll_hw_state dpll_hw_state;
12404 unsigned crtc_mask;
12405 bool active;
12406
12407 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12408
12409 DRM_DEBUG_KMS("%s\n", pll->name);
12410
12411 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12412
12413 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12414 I915_STATE_WARN(!pll->on && pll->active_mask,
12415 "pll in active use but not on in sw tracking\n");
12416 I915_STATE_WARN(pll->on && !pll->active_mask,
12417 "pll is on but not used by any active crtc\n");
12418 I915_STATE_WARN(pll->on != active,
12419 "pll on state mismatch (expected %i, found %i)\n",
12420 pll->on, active);
12421 }
12422
12423 if (!crtc) {
12424 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12425 "more active pll users than references: %x vs %x\n",
12426 pll->active_mask, pll->config.crtc_mask);
12427
12428 return;
12429 }
12430
12431 crtc_mask = 1 << drm_crtc_index(crtc);
12432
12433 if (new_state->active)
12434 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12435 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12436 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12437 else
12438 I915_STATE_WARN(pll->active_mask & crtc_mask,
12439 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12440 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12441
12442 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12443 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12444 crtc_mask, pll->config.crtc_mask);
12445
12446 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12447 &dpll_hw_state,
12448 sizeof(dpll_hw_state)),
12449 "pll hw state mismatch\n");
12450 }
12451
12452 static void
12453 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12454 struct drm_crtc_state *old_crtc_state,
12455 struct drm_crtc_state *new_crtc_state)
12456 {
12457 struct drm_i915_private *dev_priv = dev->dev_private;
12458 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12459 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12460
12461 if (new_state->shared_dpll)
12462 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12463
12464 if (old_state->shared_dpll &&
12465 old_state->shared_dpll != new_state->shared_dpll) {
12466 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12467 struct intel_shared_dpll *pll = old_state->shared_dpll;
12468
12469 I915_STATE_WARN(pll->active_mask & crtc_mask,
12470 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12471 pipe_name(drm_crtc_index(crtc)));
12472 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
12473 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12474 pipe_name(drm_crtc_index(crtc)));
12475 }
12476 }
12477
12478 static void
12479 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12480 struct drm_crtc_state *old_state,
12481 struct drm_crtc_state *new_state)
12482 {
12483 verify_wm_state(crtc, new_state);
12484 verify_crtc_state(crtc, old_state, new_state);
12485 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12486 }
12487
12488 static void
12489 verify_disabled_dpll_state(struct drm_device *dev)
12490 {
12491 struct drm_i915_private *dev_priv = dev->dev_private;
12492 int i;
12493
12494 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12495 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12496 }
12497
12498 static void
12499 intel_modeset_verify_disabled(struct drm_device *dev)
12500 {
12501 verify_encoder_state(dev);
12502 verify_connector_state(dev, NULL);
12503 verify_disabled_dpll_state(dev);
12504 }
12505
12506 static void update_scanline_offset(struct intel_crtc *crtc)
12507 {
12508 struct drm_device *dev = crtc->base.dev;
12509
12510 /*
12511 * The scanline counter increments at the leading edge of hsync.
12512 *
12513 * On most platforms it starts counting from vtotal-1 on the
12514 * first active line. That means the scanline counter value is
12515 * always one less than what we would expect. Ie. just after
12516 * start of vblank, which also occurs at start of hsync (on the
12517 * last active line), the scanline counter will read vblank_start-1.
12518 *
12519 * On gen2 the scanline counter starts counting from 1 instead
12520 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12521 * to keep the value positive), instead of adding one.
12522 *
12523 * On HSW+ the behaviour of the scanline counter depends on the output
12524 * type. For DP ports it behaves like most other platforms, but on HDMI
12525 * there's an extra 1 line difference. So we need to add two instead of
12526 * one to the value.
12527 */
12528 if (IS_GEN2(dev)) {
12529 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12530 int vtotal;
12531
12532 vtotal = adjusted_mode->crtc_vtotal;
12533 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12534 vtotal /= 2;
12535
12536 crtc->scanline_offset = vtotal - 1;
12537 } else if (HAS_DDI(dev) &&
12538 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12539 crtc->scanline_offset = 2;
12540 } else
12541 crtc->scanline_offset = 1;
12542 }
12543
12544 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12545 {
12546 struct drm_device *dev = state->dev;
12547 struct drm_i915_private *dev_priv = to_i915(dev);
12548 struct intel_shared_dpll_config *shared_dpll = NULL;
12549 struct drm_crtc *crtc;
12550 struct drm_crtc_state *crtc_state;
12551 int i;
12552
12553 if (!dev_priv->display.crtc_compute_clock)
12554 return;
12555
12556 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12558 struct intel_shared_dpll *old_dpll =
12559 to_intel_crtc_state(crtc->state)->shared_dpll;
12560
12561 if (!needs_modeset(crtc_state))
12562 continue;
12563
12564 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12565
12566 if (!old_dpll)
12567 continue;
12568
12569 if (!shared_dpll)
12570 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12571
12572 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
12573 }
12574 }
12575
12576 /*
12577 * This implements the workaround described in the "notes" section of the mode
12578 * set sequence documentation. When going from no pipes or single pipe to
12579 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12580 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12581 */
12582 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12583 {
12584 struct drm_crtc_state *crtc_state;
12585 struct intel_crtc *intel_crtc;
12586 struct drm_crtc *crtc;
12587 struct intel_crtc_state *first_crtc_state = NULL;
12588 struct intel_crtc_state *other_crtc_state = NULL;
12589 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12590 int i;
12591
12592 /* look at all crtc's that are going to be enabled in during modeset */
12593 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12594 intel_crtc = to_intel_crtc(crtc);
12595
12596 if (!crtc_state->active || !needs_modeset(crtc_state))
12597 continue;
12598
12599 if (first_crtc_state) {
12600 other_crtc_state = to_intel_crtc_state(crtc_state);
12601 break;
12602 } else {
12603 first_crtc_state = to_intel_crtc_state(crtc_state);
12604 first_pipe = intel_crtc->pipe;
12605 }
12606 }
12607
12608 /* No workaround needed? */
12609 if (!first_crtc_state)
12610 return 0;
12611
12612 /* w/a possibly needed, check how many crtc's are already enabled. */
12613 for_each_intel_crtc(state->dev, intel_crtc) {
12614 struct intel_crtc_state *pipe_config;
12615
12616 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12617 if (IS_ERR(pipe_config))
12618 return PTR_ERR(pipe_config);
12619
12620 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12621
12622 if (!pipe_config->base.active ||
12623 needs_modeset(&pipe_config->base))
12624 continue;
12625
12626 /* 2 or more enabled crtcs means no need for w/a */
12627 if (enabled_pipe != INVALID_PIPE)
12628 return 0;
12629
12630 enabled_pipe = intel_crtc->pipe;
12631 }
12632
12633 if (enabled_pipe != INVALID_PIPE)
12634 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12635 else if (other_crtc_state)
12636 other_crtc_state->hsw_workaround_pipe = first_pipe;
12637
12638 return 0;
12639 }
12640
12641 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12642 {
12643 struct drm_crtc *crtc;
12644 struct drm_crtc_state *crtc_state;
12645 int ret = 0;
12646
12647 /* add all active pipes to the state */
12648 for_each_crtc(state->dev, crtc) {
12649 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12650 if (IS_ERR(crtc_state))
12651 return PTR_ERR(crtc_state);
12652
12653 if (!crtc_state->active || needs_modeset(crtc_state))
12654 continue;
12655
12656 crtc_state->mode_changed = true;
12657
12658 ret = drm_atomic_add_affected_connectors(state, crtc);
12659 if (ret)
12660 break;
12661
12662 ret = drm_atomic_add_affected_planes(state, crtc);
12663 if (ret)
12664 break;
12665 }
12666
12667 return ret;
12668 }
12669
12670 static int intel_modeset_checks(struct drm_atomic_state *state)
12671 {
12672 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12673 struct drm_i915_private *dev_priv = state->dev->dev_private;
12674 struct drm_crtc *crtc;
12675 struct drm_crtc_state *crtc_state;
12676 int ret = 0, i;
12677
12678 if (!check_digital_port_conflicts(state)) {
12679 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12680 return -EINVAL;
12681 }
12682
12683 intel_state->modeset = true;
12684 intel_state->active_crtcs = dev_priv->active_crtcs;
12685
12686 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12687 if (crtc_state->active)
12688 intel_state->active_crtcs |= 1 << i;
12689 else
12690 intel_state->active_crtcs &= ~(1 << i);
12691
12692 if (crtc_state->active != crtc->state->active)
12693 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12694 }
12695
12696 /*
12697 * See if the config requires any additional preparation, e.g.
12698 * to adjust global state with pipes off. We need to do this
12699 * here so we can get the modeset_pipe updated config for the new
12700 * mode set on this crtc. For other crtcs we need to use the
12701 * adjusted_mode bits in the crtc directly.
12702 */
12703 if (dev_priv->display.modeset_calc_cdclk) {
12704 if (!intel_state->cdclk_pll_vco)
12705 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
12706 if (!intel_state->cdclk_pll_vco)
12707 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
12708
12709 ret = dev_priv->display.modeset_calc_cdclk(state);
12710 if (ret < 0)
12711 return ret;
12712
12713 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
12714 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
12715 ret = intel_modeset_all_pipes(state);
12716
12717 if (ret < 0)
12718 return ret;
12719
12720 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
12721 intel_state->cdclk, intel_state->dev_cdclk);
12722 } else
12723 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
12724
12725 intel_modeset_clear_plls(state);
12726
12727 if (IS_HASWELL(dev_priv))
12728 return haswell_mode_set_planes_workaround(state);
12729
12730 return 0;
12731 }
12732
12733 /*
12734 * Handle calculation of various watermark data at the end of the atomic check
12735 * phase. The code here should be run after the per-crtc and per-plane 'check'
12736 * handlers to ensure that all derived state has been updated.
12737 */
12738 static int calc_watermark_data(struct drm_atomic_state *state)
12739 {
12740 struct drm_device *dev = state->dev;
12741 struct drm_i915_private *dev_priv = to_i915(dev);
12742
12743 /* Is there platform-specific watermark information to calculate? */
12744 if (dev_priv->display.compute_global_watermarks)
12745 return dev_priv->display.compute_global_watermarks(state);
12746
12747 return 0;
12748 }
12749
12750 /**
12751 * intel_atomic_check - validate state object
12752 * @dev: drm device
12753 * @state: state to validate
12754 */
12755 static int intel_atomic_check(struct drm_device *dev,
12756 struct drm_atomic_state *state)
12757 {
12758 struct drm_i915_private *dev_priv = to_i915(dev);
12759 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12760 struct drm_crtc *crtc;
12761 struct drm_crtc_state *crtc_state;
12762 int ret, i;
12763 bool any_ms = false;
12764
12765 ret = drm_atomic_helper_check_modeset(dev, state);
12766 if (ret)
12767 return ret;
12768
12769 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12770 struct intel_crtc_state *pipe_config =
12771 to_intel_crtc_state(crtc_state);
12772
12773 /* Catch I915_MODE_FLAG_INHERITED */
12774 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12775 crtc_state->mode_changed = true;
12776
12777 if (!needs_modeset(crtc_state))
12778 continue;
12779
12780 if (!crtc_state->enable) {
12781 any_ms = true;
12782 continue;
12783 }
12784
12785 /* FIXME: For only active_changed we shouldn't need to do any
12786 * state recomputation at all. */
12787
12788 ret = drm_atomic_add_affected_connectors(state, crtc);
12789 if (ret)
12790 return ret;
12791
12792 ret = intel_modeset_pipe_config(crtc, pipe_config);
12793 if (ret) {
12794 intel_dump_pipe_config(to_intel_crtc(crtc),
12795 pipe_config, "[failed]");
12796 return ret;
12797 }
12798
12799 if (i915.fastboot &&
12800 intel_pipe_config_compare(dev,
12801 to_intel_crtc_state(crtc->state),
12802 pipe_config, true)) {
12803 crtc_state->mode_changed = false;
12804 to_intel_crtc_state(crtc_state)->update_pipe = true;
12805 }
12806
12807 if (needs_modeset(crtc_state))
12808 any_ms = true;
12809
12810 ret = drm_atomic_add_affected_planes(state, crtc);
12811 if (ret)
12812 return ret;
12813
12814 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12815 needs_modeset(crtc_state) ?
12816 "[modeset]" : "[fastset]");
12817 }
12818
12819 if (any_ms) {
12820 ret = intel_modeset_checks(state);
12821
12822 if (ret)
12823 return ret;
12824 } else
12825 intel_state->cdclk = dev_priv->cdclk_freq;
12826
12827 ret = drm_atomic_helper_check_planes(dev, state);
12828 if (ret)
12829 return ret;
12830
12831 intel_fbc_choose_crtc(dev_priv, state);
12832 return calc_watermark_data(state);
12833 }
12834
12835 static bool needs_work(struct drm_crtc_state *crtc_state)
12836 {
12837 /* hw state checker needs to run */
12838 if (needs_modeset(crtc_state))
12839 return true;
12840
12841 /* unpin old fb's, possibly vblank update */
12842 if (crtc_state->planes_changed)
12843 return true;
12844
12845 /* pipe parameters need to be updated, and hw state checker */
12846 if (to_intel_crtc_state(crtc_state)->update_pipe)
12847 return true;
12848
12849 /* vblank event requested? */
12850 if (crtc_state->event)
12851 return true;
12852
12853 return false;
12854 }
12855
12856 static int intel_atomic_prepare_commit(struct drm_device *dev,
12857 struct drm_atomic_state *state,
12858 bool nonblock)
12859 {
12860 struct drm_i915_private *dev_priv = dev->dev_private;
12861 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12862 struct drm_plane_state *plane_state;
12863 struct drm_crtc_state *crtc_state;
12864 struct drm_plane *plane;
12865 struct drm_crtc *crtc;
12866 int i, ret;
12867
12868 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12870 struct intel_flip_work *work;
12871
12872 if (!state->legacy_cursor_update) {
12873 ret = intel_crtc_wait_for_pending_flips(crtc);
12874 if (ret)
12875 return ret;
12876
12877 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12878 flush_workqueue(dev_priv->wq);
12879 }
12880
12881 /* test if we need to update something */
12882 if (!needs_work(crtc_state))
12883 continue;
12884
12885 intel_state->work[i] = work =
12886 kzalloc(sizeof(**intel_state->work), GFP_KERNEL);
12887
12888 if (!work)
12889 return -ENOMEM;
12890
12891 if (needs_modeset(crtc_state) ||
12892 to_intel_crtc_state(crtc_state)->update_pipe) {
12893 work->num_old_connectors = hweight32(crtc->state->connector_mask);
12894
12895 work->old_connector_state = kcalloc(work->num_old_connectors,
12896 sizeof(*work->old_connector_state),
12897 GFP_KERNEL);
12898
12899 work->num_new_connectors = hweight32(crtc_state->connector_mask);
12900 work->new_connector_state = kcalloc(work->num_new_connectors,
12901 sizeof(*work->new_connector_state),
12902 GFP_KERNEL);
12903
12904 if (!work->old_connector_state || !work->new_connector_state)
12905 return -ENOMEM;
12906 }
12907 }
12908
12909 if (intel_state->modeset && nonblock) {
12910 DRM_DEBUG_ATOMIC("Nonblock modesets are not yet supported!\n");
12911 return -EINVAL;
12912 }
12913
12914 ret = mutex_lock_interruptible(&dev->struct_mutex);
12915 if (ret)
12916 return ret;
12917
12918 ret = drm_atomic_helper_prepare_planes(dev, state);
12919 mutex_unlock(&dev->struct_mutex);
12920
12921 if (!ret && !nonblock) {
12922 for_each_plane_in_state(state, plane, plane_state, i) {
12923 struct intel_plane_state *intel_plane_state =
12924 to_intel_plane_state(plane_state);
12925
12926 if (plane_state->fence) {
12927 long lret = fence_wait(plane_state->fence, true);
12928
12929 if (lret < 0) {
12930 ret = lret;
12931 break;
12932 }
12933 }
12934
12935 if (!intel_plane_state->wait_req)
12936 continue;
12937
12938 ret = __i915_wait_request(intel_plane_state->wait_req,
12939 true, NULL, NULL);
12940 if (ret) {
12941 /* Any hang should be swallowed by the wait */
12942 WARN_ON(ret == -EIO);
12943 mutex_lock(&dev->struct_mutex);
12944 drm_atomic_helper_cleanup_planes(dev, state);
12945 mutex_unlock(&dev->struct_mutex);
12946 break;
12947 }
12948 }
12949 }
12950
12951 return ret;
12952 }
12953
12954 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12955 {
12956 struct drm_device *dev = crtc->base.dev;
12957
12958 if (!dev->max_vblank_count)
12959 return drm_accurate_vblank_count(&crtc->base);
12960
12961 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12962 }
12963
12964 static void intel_prepare_work(struct drm_crtc *crtc,
12965 struct intel_flip_work *work,
12966 struct drm_atomic_state *state,
12967 struct drm_crtc_state *old_crtc_state)
12968 {
12969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12970 struct drm_plane_state *old_plane_state;
12971 struct drm_plane *plane;
12972 int i, j = 0;
12973
12974 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12975 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12976 atomic_inc(&intel_crtc->unpin_work_count);
12977
12978 for_each_plane_in_state(state, plane, old_plane_state, i) {
12979 struct intel_plane_state *old_state = to_intel_plane_state(old_plane_state);
12980 struct intel_plane_state *new_state = to_intel_plane_state(plane->state);
12981
12982 if (old_state->base.crtc != crtc &&
12983 new_state->base.crtc != crtc)
12984 continue;
12985
12986 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
12987 plane->fb = new_state->base.fb;
12988 crtc->x = new_state->base.src_x >> 16;
12989 crtc->y = new_state->base.src_y >> 16;
12990 }
12991
12992 old_state->wait_req = new_state->wait_req;
12993 new_state->wait_req = NULL;
12994
12995 old_state->base.fence = new_state->base.fence;
12996 new_state->base.fence = NULL;
12997
12998 /* remove plane state from the atomic state and move it to work */
12999 old_plane_state->state = NULL;
13000 state->planes[i] = NULL;
13001 state->plane_states[i] = NULL;
13002
13003 work->old_plane_state[j] = old_state;
13004 work->new_plane_state[j++] = new_state;
13005 }
13006
13007 old_crtc_state->state = NULL;
13008 state->crtcs[drm_crtc_index(crtc)] = NULL;
13009 state->crtc_states[drm_crtc_index(crtc)] = NULL;
13010
13011 work->old_crtc_state = to_intel_crtc_state(old_crtc_state);
13012 work->new_crtc_state = to_intel_crtc_state(crtc->state);
13013 work->num_planes = j;
13014
13015 work->event = crtc->state->event;
13016 crtc->state->event = NULL;
13017
13018 if (needs_modeset(crtc->state) || work->new_crtc_state->update_pipe) {
13019 struct drm_connector *conn;
13020 struct drm_connector_state *old_conn_state;
13021 int k = 0;
13022
13023 j = 0;
13024
13025 /*
13026 * intel_unpin_work_fn cannot depend on the connector list
13027 * because it may be freed from underneath it, so add
13028 * them all to the work struct while we're holding locks.
13029 */
13030 for_each_connector_in_state(state, conn, old_conn_state, i) {
13031 if (old_conn_state->crtc == crtc) {
13032 work->old_connector_state[j++] = old_conn_state;
13033
13034 state->connectors[i] = NULL;
13035 state->connector_states[i] = NULL;
13036 }
13037 }
13038
13039 /* If another crtc has stolen the connector from state,
13040 * then for_each_connector_in_state is no longer reliable,
13041 * so use drm_for_each_connector here.
13042 */
13043 drm_for_each_connector(conn, state->dev)
13044 if (conn->state->crtc == crtc)
13045 work->new_connector_state[k++] = conn->state;
13046
13047 WARN(j != work->num_old_connectors, "j = %i, expected %i\n", j, work->num_old_connectors);
13048 WARN(k != work->num_new_connectors, "k = %i, expected %i\n", k, work->num_new_connectors);
13049 } else if (!work->new_crtc_state->update_wm_post)
13050 work->can_async_unpin = true;
13051
13052 work->fb_bits = work->new_crtc_state->fb_bits;
13053 }
13054
13055 static void intel_schedule_unpin(struct drm_crtc *crtc,
13056 struct intel_atomic_state *state,
13057 struct intel_flip_work *work)
13058 {
13059 struct drm_device *dev = crtc->dev;
13060 struct drm_i915_private *dev_priv = dev->dev_private;
13061
13062 to_intel_crtc(crtc)->config = work->new_crtc_state;
13063
13064 queue_work(dev_priv->wq, &work->unpin_work);
13065 }
13066
13067 static void intel_schedule_flip(struct drm_crtc *crtc,
13068 struct intel_atomic_state *state,
13069 struct intel_flip_work *work,
13070 bool nonblock)
13071 {
13072 struct intel_crtc_state *crtc_state = work->new_crtc_state;
13073
13074 if (crtc_state->base.planes_changed ||
13075 needs_modeset(&crtc_state->base) ||
13076 crtc_state->update_pipe) {
13077 if (nonblock)
13078 schedule_work(&work->mmio_work);
13079 else
13080 intel_mmio_flip_work_func(&work->mmio_work);
13081 } else {
13082 int ret;
13083
13084 ret = drm_crtc_vblank_get(crtc);
13085 I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
13086
13087 work->flip_queued_vblank = intel_crtc_get_vblank_counter(to_intel_crtc(crtc));
13088 smp_mb__before_atomic();
13089 atomic_set(&work->pending, 1);
13090 }
13091 }
13092
13093 static void intel_schedule_update(struct drm_crtc *crtc,
13094 struct intel_atomic_state *state,
13095 struct intel_flip_work *work,
13096 bool nonblock)
13097 {
13098 struct drm_device *dev = crtc->dev;
13099 struct intel_crtc_state *pipe_config = work->new_crtc_state;
13100
13101 if (!pipe_config->base.active && work->can_async_unpin) {
13102 INIT_LIST_HEAD(&work->head);
13103 intel_schedule_unpin(crtc, state, work);
13104 return;
13105 }
13106
13107 spin_lock_irq(&dev->event_lock);
13108 list_add_tail(&work->head, &to_intel_crtc(crtc)->flip_work);
13109 spin_unlock_irq(&dev->event_lock);
13110
13111 if (!pipe_config->base.active)
13112 intel_schedule_unpin(crtc, state, work);
13113 else
13114 intel_schedule_flip(crtc, state, work, nonblock);
13115 }
13116
13117 /**
13118 * intel_atomic_commit - commit validated state object
13119 * @dev: DRM device
13120 * @state: the top-level driver state object
13121 * @nonblock: nonblocking commit
13122 *
13123 * This function commits a top-level state object that has been validated
13124 * with drm_atomic_helper_check().
13125 *
13126 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13127 * we can only handle plane-related operations and do not yet support
13128 * nonblocking commit.
13129 *
13130 * RETURNS
13131 * Zero for success or -errno.
13132 */
13133 static int intel_atomic_commit(struct drm_device *dev,
13134 struct drm_atomic_state *state,
13135 bool nonblock)
13136 {
13137 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13138 struct drm_i915_private *dev_priv = dev->dev_private;
13139 struct drm_crtc_state *old_crtc_state;
13140 struct drm_crtc *crtc;
13141 int ret = 0, i;
13142
13143 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13144 if (ret) {
13145 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13146 return ret;
13147 }
13148
13149 drm_atomic_helper_swap_state(dev, state);
13150 dev_priv->wm.distrust_bios_wm = false;
13151 dev_priv->wm.skl_results = intel_state->wm_results;
13152 intel_shared_dpll_commit(state);
13153
13154 if (intel_state->modeset) {
13155 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13156 sizeof(intel_state->min_pixclk));
13157 dev_priv->active_crtcs = intel_state->active_crtcs;
13158 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13159 }
13160
13161 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13163
13164 if (!needs_modeset(crtc->state))
13165 continue;
13166
13167 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13168
13169 intel_state->work[i]->put_power_domains =
13170 modeset_get_crtc_power_domains(crtc,
13171 to_intel_crtc_state(crtc->state));
13172
13173 if (old_crtc_state->active) {
13174 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13175 dev_priv->display.crtc_disable(crtc);
13176 intel_crtc->active = false;
13177 intel_fbc_disable(intel_crtc);
13178 intel_disable_shared_dpll(intel_crtc);
13179
13180 /*
13181 * Underruns don't always raise
13182 * interrupts, so check manually.
13183 */
13184 intel_check_cpu_fifo_underruns(dev_priv);
13185 intel_check_pch_fifo_underruns(dev_priv);
13186
13187 if (!crtc->state->active)
13188 intel_update_watermarks(crtc);
13189 }
13190 }
13191
13192 /* Only after disabling all output pipelines that will be changed can we
13193 * update the the output configuration. */
13194 intel_modeset_update_crtc_state(state);
13195
13196 if (intel_state->modeset) {
13197 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13198
13199 if (dev_priv->display.modeset_commit_cdclk &&
13200 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13201 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13202 dev_priv->display.modeset_commit_cdclk(state);
13203
13204 intel_modeset_verify_disabled(dev);
13205 }
13206
13207 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13208 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13209 struct intel_flip_work *work = intel_state->work[i];
13210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13211 bool modeset = needs_modeset(crtc->state);
13212
13213 if (modeset && crtc->state->active) {
13214 update_scanline_offset(to_intel_crtc(crtc));
13215 dev_priv->display.crtc_enable(crtc);
13216 }
13217
13218 if (!modeset)
13219 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13220
13221 if (!work) {
13222 if (!list_empty_careful(&intel_crtc->flip_work)) {
13223 spin_lock_irq(&dev->event_lock);
13224 if (!list_empty(&intel_crtc->flip_work))
13225 work = list_last_entry(&intel_crtc->flip_work,
13226 struct intel_flip_work, head);
13227
13228 if (work && work->new_crtc_state == to_intel_crtc_state(old_crtc_state)) {
13229 work->free_new_crtc_state = true;
13230 state->crtc_states[i] = NULL;
13231 state->crtcs[i] = NULL;
13232 }
13233 spin_unlock_irq(&dev->event_lock);
13234 }
13235 continue;
13236 }
13237
13238 intel_state->work[i] = NULL;
13239 intel_prepare_work(crtc, work, state, old_crtc_state);
13240 intel_schedule_update(crtc, intel_state, work, nonblock);
13241 }
13242
13243 /* FIXME: add subpixel order */
13244
13245 drm_atomic_state_free(state);
13246
13247 /* As one of the primary mmio accessors, KMS has a high likelihood
13248 * of triggering bugs in unclaimed access. After we finish
13249 * modesetting, see if an error has been flagged, and if so
13250 * enable debugging for the next modeset - and hope we catch
13251 * the culprit.
13252 *
13253 * XXX note that we assume display power is on at this point.
13254 * This might hold true now but we need to add pm helper to check
13255 * unclaimed only when the hardware is on, as atomic commits
13256 * can happen also when the device is completely off.
13257 */
13258 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13259
13260 return 0;
13261 }
13262
13263 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13264 {
13265 struct drm_device *dev = crtc->dev;
13266 struct drm_atomic_state *state;
13267 struct drm_crtc_state *crtc_state;
13268 int ret;
13269
13270 state = drm_atomic_state_alloc(dev);
13271 if (!state) {
13272 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13273 crtc->base.id);
13274 return;
13275 }
13276
13277 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13278
13279 retry:
13280 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13281 ret = PTR_ERR_OR_ZERO(crtc_state);
13282 if (!ret) {
13283 if (!crtc_state->active)
13284 goto out;
13285
13286 crtc_state->mode_changed = true;
13287 ret = drm_atomic_commit(state);
13288 }
13289
13290 if (ret == -EDEADLK) {
13291 drm_atomic_state_clear(state);
13292 drm_modeset_backoff(state->acquire_ctx);
13293 goto retry;
13294 }
13295
13296 if (ret)
13297 out:
13298 drm_atomic_state_free(state);
13299 }
13300
13301 #undef for_each_intel_crtc_masked
13302
13303 static const struct drm_crtc_funcs intel_crtc_funcs = {
13304 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13305 .set_config = drm_atomic_helper_set_config,
13306 .set_property = drm_atomic_helper_crtc_set_property,
13307 .destroy = intel_crtc_destroy,
13308 .page_flip = drm_atomic_helper_page_flip,
13309 .atomic_duplicate_state = intel_crtc_duplicate_state,
13310 .atomic_destroy_state = intel_crtc_destroy_state,
13311 };
13312
13313 static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
13314 {
13315 struct reservation_object *resv;
13316
13317
13318 if (!obj->base.dma_buf)
13319 return NULL;
13320
13321 resv = obj->base.dma_buf->resv;
13322
13323 /* For framebuffer backed by dmabuf, wait for fence */
13324 while (1) {
13325 struct fence *fence_excl, *ret = NULL;
13326
13327 rcu_read_lock();
13328
13329 fence_excl = rcu_dereference(resv->fence_excl);
13330 if (fence_excl)
13331 ret = fence_get_rcu(fence_excl);
13332
13333 rcu_read_unlock();
13334
13335 if (ret == fence_excl)
13336 return ret;
13337 }
13338 }
13339
13340 /**
13341 * intel_prepare_plane_fb - Prepare fb for usage on plane
13342 * @plane: drm plane to prepare for
13343 * @fb: framebuffer to prepare for presentation
13344 *
13345 * Prepares a framebuffer for usage on a display plane. Generally this
13346 * involves pinning the underlying object and updating the frontbuffer tracking
13347 * bits. Some older platforms need special physical address handling for
13348 * cursor planes.
13349 *
13350 * Must be called with struct_mutex held.
13351 *
13352 * Returns 0 on success, negative error code on failure.
13353 */
13354 int
13355 intel_prepare_plane_fb(struct drm_plane *plane,
13356 const struct drm_plane_state *new_state)
13357 {
13358 struct drm_device *dev = plane->dev;
13359 struct drm_framebuffer *fb = new_state->fb;
13360 struct intel_plane *intel_plane = to_intel_plane(plane);
13361 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13362 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13363 struct drm_crtc *crtc = new_state->crtc ?: plane->state->crtc;
13364 int ret = 0;
13365
13366 if (!obj && !old_obj)
13367 return 0;
13368
13369 if (WARN_ON(!new_state->state) || WARN_ON(!crtc) ||
13370 WARN_ON(!to_intel_atomic_state(new_state->state)->work[to_intel_crtc(crtc)->pipe])) {
13371 if (WARN_ON(old_obj != obj))
13372 return -EINVAL;
13373
13374 return 0;
13375 }
13376
13377 if (old_obj) {
13378 struct drm_crtc_state *crtc_state =
13379 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13380
13381 /* Big Hammer, we also need to ensure that any pending
13382 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13383 * current scanout is retired before unpinning the old
13384 * framebuffer. Note that we rely on userspace rendering
13385 * into the buffer attached to the pipe they are waiting
13386 * on. If not, userspace generates a GPU hang with IPEHR
13387 * point to the MI_WAIT_FOR_EVENT.
13388 *
13389 * This should only fail upon a hung GPU, in which case we
13390 * can safely continue.
13391 */
13392 if (needs_modeset(crtc_state))
13393 ret = i915_gem_object_wait_rendering(old_obj, true);
13394 if (ret) {
13395 /* GPU hangs should have been swallowed by the wait */
13396 WARN_ON(ret == -EIO);
13397 return ret;
13398 }
13399 }
13400
13401 if (!obj) {
13402 ret = 0;
13403 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13404 INTEL_INFO(dev)->cursor_needs_physical) {
13405 int align = IS_I830(dev) ? 16 * 1024 : 256;
13406 ret = i915_gem_object_attach_phys(obj, align);
13407 if (ret)
13408 DRM_DEBUG_KMS("failed to attach phys object\n");
13409 } else {
13410 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13411 }
13412
13413 if (ret == 0) {
13414 if (obj) {
13415 struct intel_plane_state *plane_state =
13416 to_intel_plane_state(new_state);
13417
13418 i915_gem_request_assign(&plane_state->wait_req,
13419 obj->last_write_req);
13420
13421 plane_state->base.fence = intel_get_excl_fence(obj);
13422 }
13423
13424 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13425 }
13426
13427 return ret;
13428 }
13429
13430 /**
13431 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13432 * @plane: drm plane to clean up for
13433 * @fb: old framebuffer that was on plane
13434 *
13435 * Cleans up a framebuffer that has just been removed from a plane.
13436 *
13437 * Must be called with struct_mutex held.
13438 */
13439 void
13440 intel_cleanup_plane_fb(struct drm_plane *plane,
13441 const struct drm_plane_state *old_state)
13442 {
13443 struct drm_device *dev = plane->dev;
13444 struct intel_plane *intel_plane = to_intel_plane(plane);
13445 struct intel_plane_state *old_intel_state;
13446 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13447 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13448
13449 old_intel_state = to_intel_plane_state(old_state);
13450
13451 if (!obj && !old_obj)
13452 return;
13453
13454 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13455 !INTEL_INFO(dev)->cursor_needs_physical))
13456 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13457
13458 /* prepare_fb aborted? */
13459 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13460 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13461 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13462
13463 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13464
13465 fence_put(old_intel_state->base.fence);
13466 old_intel_state->base.fence = NULL;
13467 }
13468
13469 int
13470 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13471 {
13472 int max_scale;
13473 struct drm_device *dev;
13474 struct drm_i915_private *dev_priv;
13475 int crtc_clock, cdclk;
13476
13477 if (!intel_crtc || !crtc_state->base.enable)
13478 return DRM_PLANE_HELPER_NO_SCALING;
13479
13480 dev = intel_crtc->base.dev;
13481 dev_priv = dev->dev_private;
13482 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13483 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13484
13485 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13486 return DRM_PLANE_HELPER_NO_SCALING;
13487
13488 /*
13489 * skl max scale is lower of:
13490 * close to 3 but not 3, -1 is for that purpose
13491 * or
13492 * cdclk/crtc_clock
13493 */
13494 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13495
13496 return max_scale;
13497 }
13498
13499 static int
13500 intel_check_primary_plane(struct drm_plane *plane,
13501 struct intel_crtc_state *crtc_state,
13502 struct intel_plane_state *state)
13503 {
13504 struct drm_crtc *crtc = state->base.crtc;
13505 struct drm_framebuffer *fb = state->base.fb;
13506 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13507 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13508 bool can_position = false;
13509
13510 if (INTEL_INFO(plane->dev)->gen >= 9) {
13511 /* use scaler when colorkey is not required */
13512 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13513 min_scale = 1;
13514 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13515 }
13516 can_position = true;
13517 }
13518
13519 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13520 &state->dst, &state->clip,
13521 min_scale, max_scale,
13522 can_position, true,
13523 &state->visible);
13524 }
13525
13526 /**
13527 * intel_plane_destroy - destroy a plane
13528 * @plane: plane to destroy
13529 *
13530 * Common destruction function for all types of planes (primary, cursor,
13531 * sprite).
13532 */
13533 void intel_plane_destroy(struct drm_plane *plane)
13534 {
13535 struct intel_plane *intel_plane = to_intel_plane(plane);
13536 drm_plane_cleanup(plane);
13537 kfree(intel_plane);
13538 }
13539
13540 const struct drm_plane_funcs intel_plane_funcs = {
13541 .update_plane = drm_atomic_helper_update_plane,
13542 .disable_plane = drm_atomic_helper_disable_plane,
13543 .destroy = intel_plane_destroy,
13544 .set_property = drm_atomic_helper_plane_set_property,
13545 .atomic_get_property = intel_plane_atomic_get_property,
13546 .atomic_set_property = intel_plane_atomic_set_property,
13547 .atomic_duplicate_state = intel_plane_duplicate_state,
13548 .atomic_destroy_state = intel_plane_destroy_state,
13549
13550 };
13551
13552 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13553 int pipe)
13554 {
13555 struct intel_plane *primary = NULL;
13556 struct intel_plane_state *state = NULL;
13557 const uint32_t *intel_primary_formats;
13558 unsigned int num_formats;
13559 int ret;
13560
13561 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13562 if (!primary)
13563 goto fail;
13564
13565 state = intel_create_plane_state(&primary->base);
13566 if (!state)
13567 goto fail;
13568 primary->base.state = &state->base;
13569
13570 primary->can_scale = false;
13571 primary->max_downscale = 1;
13572 if (INTEL_INFO(dev)->gen >= 9) {
13573 primary->can_scale = true;
13574 state->scaler_id = -1;
13575 }
13576 primary->pipe = pipe;
13577 primary->plane = pipe;
13578 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13579 primary->check_plane = intel_check_primary_plane;
13580 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13581 primary->plane = !pipe;
13582
13583 if (INTEL_INFO(dev)->gen >= 9) {
13584 intel_primary_formats = skl_primary_formats;
13585 num_formats = ARRAY_SIZE(skl_primary_formats);
13586
13587 primary->update_plane = skylake_update_primary_plane;
13588 primary->disable_plane = skylake_disable_primary_plane;
13589 } else if (HAS_PCH_SPLIT(dev)) {
13590 intel_primary_formats = i965_primary_formats;
13591 num_formats = ARRAY_SIZE(i965_primary_formats);
13592
13593 primary->update_plane = ironlake_update_primary_plane;
13594 primary->disable_plane = i9xx_disable_primary_plane;
13595 } else if (INTEL_INFO(dev)->gen >= 4) {
13596 intel_primary_formats = i965_primary_formats;
13597 num_formats = ARRAY_SIZE(i965_primary_formats);
13598
13599 primary->update_plane = i9xx_update_primary_plane;
13600 primary->disable_plane = i9xx_disable_primary_plane;
13601 } else {
13602 intel_primary_formats = i8xx_primary_formats;
13603 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13604
13605 primary->update_plane = i9xx_update_primary_plane;
13606 primary->disable_plane = i9xx_disable_primary_plane;
13607 }
13608
13609 ret = drm_universal_plane_init(dev, &primary->base, 0,
13610 &intel_plane_funcs,
13611 intel_primary_formats, num_formats,
13612 DRM_PLANE_TYPE_PRIMARY, NULL);
13613 if (ret)
13614 goto fail;
13615
13616 if (INTEL_INFO(dev)->gen >= 4)
13617 intel_create_rotation_property(dev, primary);
13618
13619 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13620
13621 return &primary->base;
13622
13623 fail:
13624 kfree(state);
13625 kfree(primary);
13626
13627 return NULL;
13628 }
13629
13630 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13631 {
13632 if (!dev->mode_config.rotation_property) {
13633 unsigned long flags = BIT(DRM_ROTATE_0) |
13634 BIT(DRM_ROTATE_180);
13635
13636 if (INTEL_INFO(dev)->gen >= 9)
13637 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13638
13639 dev->mode_config.rotation_property =
13640 drm_mode_create_rotation_property(dev, flags);
13641 }
13642 if (dev->mode_config.rotation_property)
13643 drm_object_attach_property(&plane->base.base,
13644 dev->mode_config.rotation_property,
13645 plane->base.state->rotation);
13646 }
13647
13648 static int
13649 intel_check_cursor_plane(struct drm_plane *plane,
13650 struct intel_crtc_state *crtc_state,
13651 struct intel_plane_state *state)
13652 {
13653 struct drm_crtc *crtc = crtc_state->base.crtc;
13654 struct drm_framebuffer *fb = state->base.fb;
13655 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13656 enum pipe pipe = to_intel_plane(plane)->pipe;
13657 unsigned stride;
13658 int ret;
13659
13660 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13661 &state->dst, &state->clip,
13662 DRM_PLANE_HELPER_NO_SCALING,
13663 DRM_PLANE_HELPER_NO_SCALING,
13664 true, true, &state->visible);
13665 if (ret)
13666 return ret;
13667
13668 /* if we want to turn off the cursor ignore width and height */
13669 if (!obj)
13670 return 0;
13671
13672 /* Check for which cursor types we support */
13673 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13674 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13675 state->base.crtc_w, state->base.crtc_h);
13676 return -EINVAL;
13677 }
13678
13679 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13680 if (obj->base.size < stride * state->base.crtc_h) {
13681 DRM_DEBUG_KMS("buffer is too small\n");
13682 return -ENOMEM;
13683 }
13684
13685 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13686 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13687 return -EINVAL;
13688 }
13689
13690 /*
13691 * There's something wrong with the cursor on CHV pipe C.
13692 * If it straddles the left edge of the screen then
13693 * moving it away from the edge or disabling it often
13694 * results in a pipe underrun, and often that can lead to
13695 * dead pipe (constant underrun reported, and it scans
13696 * out just a solid color). To recover from that, the
13697 * display power well must be turned off and on again.
13698 * Refuse the put the cursor into that compromised position.
13699 */
13700 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
13701 state->visible && state->base.crtc_x < 0) {
13702 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13703 return -EINVAL;
13704 }
13705
13706 return 0;
13707 }
13708
13709 static void
13710 intel_disable_cursor_plane(struct drm_plane *plane,
13711 struct drm_crtc *crtc)
13712 {
13713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13714
13715 intel_crtc->cursor_addr = 0;
13716 intel_crtc_update_cursor(crtc, NULL);
13717 }
13718
13719 static void
13720 intel_update_cursor_plane(struct drm_plane *plane,
13721 const struct intel_crtc_state *crtc_state,
13722 const struct intel_plane_state *state)
13723 {
13724 struct drm_crtc *crtc = crtc_state->base.crtc;
13725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13726 struct drm_device *dev = plane->dev;
13727 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13728 uint32_t addr;
13729
13730 if (!obj)
13731 addr = 0;
13732 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13733 addr = i915_gem_obj_ggtt_offset(obj);
13734 else
13735 addr = obj->phys_handle->busaddr;
13736
13737 intel_crtc->cursor_addr = addr;
13738 intel_crtc_update_cursor(crtc, state);
13739 }
13740
13741 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13742 int pipe)
13743 {
13744 struct intel_plane *cursor = NULL;
13745 struct intel_plane_state *state = NULL;
13746 int ret;
13747
13748 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13749 if (!cursor)
13750 goto fail;
13751
13752 state = intel_create_plane_state(&cursor->base);
13753 if (!state)
13754 goto fail;
13755 cursor->base.state = &state->base;
13756
13757 cursor->can_scale = false;
13758 cursor->max_downscale = 1;
13759 cursor->pipe = pipe;
13760 cursor->plane = pipe;
13761 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13762 cursor->check_plane = intel_check_cursor_plane;
13763 cursor->update_plane = intel_update_cursor_plane;
13764 cursor->disable_plane = intel_disable_cursor_plane;
13765
13766 ret = drm_universal_plane_init(dev, &cursor->base, 0,
13767 &intel_plane_funcs,
13768 intel_cursor_formats,
13769 ARRAY_SIZE(intel_cursor_formats),
13770 DRM_PLANE_TYPE_CURSOR, NULL);
13771 if (ret)
13772 goto fail;
13773
13774 if (INTEL_INFO(dev)->gen >= 4) {
13775 if (!dev->mode_config.rotation_property)
13776 dev->mode_config.rotation_property =
13777 drm_mode_create_rotation_property(dev,
13778 BIT(DRM_ROTATE_0) |
13779 BIT(DRM_ROTATE_180));
13780 if (dev->mode_config.rotation_property)
13781 drm_object_attach_property(&cursor->base.base,
13782 dev->mode_config.rotation_property,
13783 state->base.rotation);
13784 }
13785
13786 if (INTEL_INFO(dev)->gen >=9)
13787 state->scaler_id = -1;
13788
13789 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13790
13791 return &cursor->base;
13792
13793 fail:
13794 kfree(state);
13795 kfree(cursor);
13796
13797 return NULL;
13798 }
13799
13800 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13801 struct intel_crtc_state *crtc_state)
13802 {
13803 int i;
13804 struct intel_scaler *intel_scaler;
13805 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13806
13807 for (i = 0; i < intel_crtc->num_scalers; i++) {
13808 intel_scaler = &scaler_state->scalers[i];
13809 intel_scaler->in_use = 0;
13810 intel_scaler->mode = PS_SCALER_MODE_DYN;
13811 }
13812
13813 scaler_state->scaler_id = -1;
13814 }
13815
13816 static void intel_crtc_init(struct drm_device *dev, int pipe)
13817 {
13818 struct drm_i915_private *dev_priv = dev->dev_private;
13819 struct intel_crtc *intel_crtc;
13820 struct intel_crtc_state *crtc_state = NULL;
13821 struct drm_plane *primary = NULL;
13822 struct drm_plane *cursor = NULL;
13823 int ret;
13824
13825 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13826 if (intel_crtc == NULL)
13827 return;
13828
13829 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13830 if (!crtc_state)
13831 goto fail;
13832 intel_crtc->config = crtc_state;
13833 intel_crtc->base.state = &crtc_state->base;
13834 crtc_state->base.crtc = &intel_crtc->base;
13835
13836 INIT_LIST_HEAD(&intel_crtc->flip_work);
13837
13838 /* initialize shared scalers */
13839 if (INTEL_INFO(dev)->gen >= 9) {
13840 if (pipe == PIPE_C)
13841 intel_crtc->num_scalers = 1;
13842 else
13843 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13844
13845 skl_init_scalers(dev, intel_crtc, crtc_state);
13846 }
13847
13848 primary = intel_primary_plane_create(dev, pipe);
13849 if (!primary)
13850 goto fail;
13851
13852 cursor = intel_cursor_plane_create(dev, pipe);
13853 if (!cursor)
13854 goto fail;
13855
13856 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13857 cursor, &intel_crtc_funcs, NULL);
13858 if (ret)
13859 goto fail;
13860
13861 /*
13862 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13863 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13864 */
13865 intel_crtc->pipe = pipe;
13866 intel_crtc->plane = pipe;
13867 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13868 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13869 intel_crtc->plane = !pipe;
13870 }
13871
13872 intel_crtc->cursor_base = ~0;
13873 intel_crtc->cursor_cntl = ~0;
13874 intel_crtc->cursor_size = ~0;
13875
13876 intel_crtc->wm.cxsr_allowed = true;
13877
13878 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13879 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13880 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13881 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13882
13883 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13884
13885 intel_color_init(&intel_crtc->base);
13886
13887 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13888 return;
13889
13890 fail:
13891 if (primary)
13892 drm_plane_cleanup(primary);
13893 if (cursor)
13894 drm_plane_cleanup(cursor);
13895 kfree(crtc_state);
13896 kfree(intel_crtc);
13897 }
13898
13899 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13900 {
13901 struct drm_encoder *encoder = connector->base.encoder;
13902 struct drm_device *dev = connector->base.dev;
13903
13904 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13905
13906 if (!encoder || WARN_ON(!encoder->crtc))
13907 return INVALID_PIPE;
13908
13909 return to_intel_crtc(encoder->crtc)->pipe;
13910 }
13911
13912 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13913 struct drm_file *file)
13914 {
13915 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13916 struct drm_crtc *drmmode_crtc;
13917 struct intel_crtc *crtc;
13918
13919 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13920
13921 if (!drmmode_crtc) {
13922 DRM_ERROR("no such CRTC id\n");
13923 return -ENOENT;
13924 }
13925
13926 crtc = to_intel_crtc(drmmode_crtc);
13927 pipe_from_crtc_id->pipe = crtc->pipe;
13928
13929 return 0;
13930 }
13931
13932 static int intel_encoder_clones(struct intel_encoder *encoder)
13933 {
13934 struct drm_device *dev = encoder->base.dev;
13935 struct intel_encoder *source_encoder;
13936 int index_mask = 0;
13937 int entry = 0;
13938
13939 for_each_intel_encoder(dev, source_encoder) {
13940 if (encoders_cloneable(encoder, source_encoder))
13941 index_mask |= (1 << entry);
13942
13943 entry++;
13944 }
13945
13946 return index_mask;
13947 }
13948
13949 static bool has_edp_a(struct drm_device *dev)
13950 {
13951 struct drm_i915_private *dev_priv = dev->dev_private;
13952
13953 if (!IS_MOBILE(dev))
13954 return false;
13955
13956 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13957 return false;
13958
13959 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13960 return false;
13961
13962 return true;
13963 }
13964
13965 static bool intel_crt_present(struct drm_device *dev)
13966 {
13967 struct drm_i915_private *dev_priv = dev->dev_private;
13968
13969 if (INTEL_INFO(dev)->gen >= 9)
13970 return false;
13971
13972 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13973 return false;
13974
13975 if (IS_CHERRYVIEW(dev))
13976 return false;
13977
13978 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13979 return false;
13980
13981 /* DDI E can't be used if DDI A requires 4 lanes */
13982 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13983 return false;
13984
13985 if (!dev_priv->vbt.int_crt_support)
13986 return false;
13987
13988 return true;
13989 }
13990
13991 static void intel_setup_outputs(struct drm_device *dev)
13992 {
13993 struct drm_i915_private *dev_priv = dev->dev_private;
13994 struct intel_encoder *encoder;
13995 bool dpd_is_edp = false;
13996
13997 intel_lvds_init(dev);
13998
13999 if (intel_crt_present(dev))
14000 intel_crt_init(dev);
14001
14002 if (IS_BROXTON(dev)) {
14003 /*
14004 * FIXME: Broxton doesn't support port detection via the
14005 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14006 * detect the ports.
14007 */
14008 intel_ddi_init(dev, PORT_A);
14009 intel_ddi_init(dev, PORT_B);
14010 intel_ddi_init(dev, PORT_C);
14011
14012 intel_dsi_init(dev);
14013 } else if (HAS_DDI(dev)) {
14014 int found;
14015
14016 /*
14017 * Haswell uses DDI functions to detect digital outputs.
14018 * On SKL pre-D0 the strap isn't connected, so we assume
14019 * it's there.
14020 */
14021 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14022 /* WaIgnoreDDIAStrap: skl */
14023 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14024 intel_ddi_init(dev, PORT_A);
14025
14026 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14027 * register */
14028 found = I915_READ(SFUSE_STRAP);
14029
14030 if (found & SFUSE_STRAP_DDIB_DETECTED)
14031 intel_ddi_init(dev, PORT_B);
14032 if (found & SFUSE_STRAP_DDIC_DETECTED)
14033 intel_ddi_init(dev, PORT_C);
14034 if (found & SFUSE_STRAP_DDID_DETECTED)
14035 intel_ddi_init(dev, PORT_D);
14036 /*
14037 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14038 */
14039 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14040 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14041 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14042 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14043 intel_ddi_init(dev, PORT_E);
14044
14045 } else if (HAS_PCH_SPLIT(dev)) {
14046 int found;
14047 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14048
14049 if (has_edp_a(dev))
14050 intel_dp_init(dev, DP_A, PORT_A);
14051
14052 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14053 /* PCH SDVOB multiplex with HDMIB */
14054 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14055 if (!found)
14056 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14057 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14058 intel_dp_init(dev, PCH_DP_B, PORT_B);
14059 }
14060
14061 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14062 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14063
14064 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14065 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14066
14067 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14068 intel_dp_init(dev, PCH_DP_C, PORT_C);
14069
14070 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14071 intel_dp_init(dev, PCH_DP_D, PORT_D);
14072 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14073 /*
14074 * The DP_DETECTED bit is the latched state of the DDC
14075 * SDA pin at boot. However since eDP doesn't require DDC
14076 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14077 * eDP ports may have been muxed to an alternate function.
14078 * Thus we can't rely on the DP_DETECTED bit alone to detect
14079 * eDP ports. Consult the VBT as well as DP_DETECTED to
14080 * detect eDP ports.
14081 */
14082 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14083 !intel_dp_is_edp(dev, PORT_B))
14084 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14085 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14086 intel_dp_is_edp(dev, PORT_B))
14087 intel_dp_init(dev, VLV_DP_B, PORT_B);
14088
14089 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14090 !intel_dp_is_edp(dev, PORT_C))
14091 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14092 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14093 intel_dp_is_edp(dev, PORT_C))
14094 intel_dp_init(dev, VLV_DP_C, PORT_C);
14095
14096 if (IS_CHERRYVIEW(dev)) {
14097 /* eDP not supported on port D, so don't check VBT */
14098 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14099 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14100 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14101 intel_dp_init(dev, CHV_DP_D, PORT_D);
14102 }
14103
14104 intel_dsi_init(dev);
14105 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14106 bool found = false;
14107
14108 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14109 DRM_DEBUG_KMS("probing SDVOB\n");
14110 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14111 if (!found && IS_G4X(dev)) {
14112 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14113 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14114 }
14115
14116 if (!found && IS_G4X(dev))
14117 intel_dp_init(dev, DP_B, PORT_B);
14118 }
14119
14120 /* Before G4X SDVOC doesn't have its own detect register */
14121
14122 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14123 DRM_DEBUG_KMS("probing SDVOC\n");
14124 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14125 }
14126
14127 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14128
14129 if (IS_G4X(dev)) {
14130 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14131 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14132 }
14133 if (IS_G4X(dev))
14134 intel_dp_init(dev, DP_C, PORT_C);
14135 }
14136
14137 if (IS_G4X(dev) &&
14138 (I915_READ(DP_D) & DP_DETECTED))
14139 intel_dp_init(dev, DP_D, PORT_D);
14140 } else if (IS_GEN2(dev))
14141 intel_dvo_init(dev);
14142
14143 if (SUPPORTS_TV(dev))
14144 intel_tv_init(dev);
14145
14146 intel_psr_init(dev);
14147
14148 for_each_intel_encoder(dev, encoder) {
14149 encoder->base.possible_crtcs = encoder->crtc_mask;
14150 encoder->base.possible_clones =
14151 intel_encoder_clones(encoder);
14152 }
14153
14154 intel_init_pch_refclk(dev);
14155
14156 drm_helper_move_panel_connectors_to_head(dev);
14157 }
14158
14159 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14160 {
14161 struct drm_device *dev = fb->dev;
14162 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14163
14164 drm_framebuffer_cleanup(fb);
14165 mutex_lock(&dev->struct_mutex);
14166 WARN_ON(!intel_fb->obj->framebuffer_references--);
14167 drm_gem_object_unreference(&intel_fb->obj->base);
14168 mutex_unlock(&dev->struct_mutex);
14169 kfree(intel_fb);
14170 }
14171
14172 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14173 struct drm_file *file,
14174 unsigned int *handle)
14175 {
14176 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14177 struct drm_i915_gem_object *obj = intel_fb->obj;
14178
14179 if (obj->userptr.mm) {
14180 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14181 return -EINVAL;
14182 }
14183
14184 return drm_gem_handle_create(file, &obj->base, handle);
14185 }
14186
14187 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14188 struct drm_file *file,
14189 unsigned flags, unsigned color,
14190 struct drm_clip_rect *clips,
14191 unsigned num_clips)
14192 {
14193 struct drm_device *dev = fb->dev;
14194 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14195 struct drm_i915_gem_object *obj = intel_fb->obj;
14196
14197 mutex_lock(&dev->struct_mutex);
14198 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14199 mutex_unlock(&dev->struct_mutex);
14200
14201 return 0;
14202 }
14203
14204 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14205 .destroy = intel_user_framebuffer_destroy,
14206 .create_handle = intel_user_framebuffer_create_handle,
14207 .dirty = intel_user_framebuffer_dirty,
14208 };
14209
14210 static
14211 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14212 uint32_t pixel_format)
14213 {
14214 u32 gen = INTEL_INFO(dev)->gen;
14215
14216 if (gen >= 9) {
14217 int cpp = drm_format_plane_cpp(pixel_format, 0);
14218
14219 /* "The stride in bytes must not exceed the of the size of 8K
14220 * pixels and 32K bytes."
14221 */
14222 return min(8192 * cpp, 32768);
14223 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14224 return 32*1024;
14225 } else if (gen >= 4) {
14226 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14227 return 16*1024;
14228 else
14229 return 32*1024;
14230 } else if (gen >= 3) {
14231 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14232 return 8*1024;
14233 else
14234 return 16*1024;
14235 } else {
14236 /* XXX DSPC is limited to 4k tiled */
14237 return 8*1024;
14238 }
14239 }
14240
14241 static int intel_framebuffer_init(struct drm_device *dev,
14242 struct intel_framebuffer *intel_fb,
14243 struct drm_mode_fb_cmd2 *mode_cmd,
14244 struct drm_i915_gem_object *obj)
14245 {
14246 struct drm_i915_private *dev_priv = to_i915(dev);
14247 unsigned int aligned_height;
14248 int ret;
14249 u32 pitch_limit, stride_alignment;
14250
14251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14252
14253 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14254 /* Enforce that fb modifier and tiling mode match, but only for
14255 * X-tiled. This is needed for FBC. */
14256 if (!!(obj->tiling_mode == I915_TILING_X) !=
14257 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14258 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14259 return -EINVAL;
14260 }
14261 } else {
14262 if (obj->tiling_mode == I915_TILING_X)
14263 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14264 else if (obj->tiling_mode == I915_TILING_Y) {
14265 DRM_DEBUG("No Y tiling for legacy addfb\n");
14266 return -EINVAL;
14267 }
14268 }
14269
14270 /* Passed in modifier sanity checking. */
14271 switch (mode_cmd->modifier[0]) {
14272 case I915_FORMAT_MOD_Y_TILED:
14273 case I915_FORMAT_MOD_Yf_TILED:
14274 if (INTEL_INFO(dev)->gen < 9) {
14275 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14276 mode_cmd->modifier[0]);
14277 return -EINVAL;
14278 }
14279 case DRM_FORMAT_MOD_NONE:
14280 case I915_FORMAT_MOD_X_TILED:
14281 break;
14282 default:
14283 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14284 mode_cmd->modifier[0]);
14285 return -EINVAL;
14286 }
14287
14288 stride_alignment = intel_fb_stride_alignment(dev_priv,
14289 mode_cmd->modifier[0],
14290 mode_cmd->pixel_format);
14291 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14292 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14293 mode_cmd->pitches[0], stride_alignment);
14294 return -EINVAL;
14295 }
14296
14297 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14298 mode_cmd->pixel_format);
14299 if (mode_cmd->pitches[0] > pitch_limit) {
14300 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14301 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14302 "tiled" : "linear",
14303 mode_cmd->pitches[0], pitch_limit);
14304 return -EINVAL;
14305 }
14306
14307 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14308 mode_cmd->pitches[0] != obj->stride) {
14309 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14310 mode_cmd->pitches[0], obj->stride);
14311 return -EINVAL;
14312 }
14313
14314 /* Reject formats not supported by any plane early. */
14315 switch (mode_cmd->pixel_format) {
14316 case DRM_FORMAT_C8:
14317 case DRM_FORMAT_RGB565:
14318 case DRM_FORMAT_XRGB8888:
14319 case DRM_FORMAT_ARGB8888:
14320 break;
14321 case DRM_FORMAT_XRGB1555:
14322 if (INTEL_INFO(dev)->gen > 3) {
14323 DRM_DEBUG("unsupported pixel format: %s\n",
14324 drm_get_format_name(mode_cmd->pixel_format));
14325 return -EINVAL;
14326 }
14327 break;
14328 case DRM_FORMAT_ABGR8888:
14329 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14330 INTEL_INFO(dev)->gen < 9) {
14331 DRM_DEBUG("unsupported pixel format: %s\n",
14332 drm_get_format_name(mode_cmd->pixel_format));
14333 return -EINVAL;
14334 }
14335 break;
14336 case DRM_FORMAT_XBGR8888:
14337 case DRM_FORMAT_XRGB2101010:
14338 case DRM_FORMAT_XBGR2101010:
14339 if (INTEL_INFO(dev)->gen < 4) {
14340 DRM_DEBUG("unsupported pixel format: %s\n",
14341 drm_get_format_name(mode_cmd->pixel_format));
14342 return -EINVAL;
14343 }
14344 break;
14345 case DRM_FORMAT_ABGR2101010:
14346 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14347 DRM_DEBUG("unsupported pixel format: %s\n",
14348 drm_get_format_name(mode_cmd->pixel_format));
14349 return -EINVAL;
14350 }
14351 break;
14352 case DRM_FORMAT_YUYV:
14353 case DRM_FORMAT_UYVY:
14354 case DRM_FORMAT_YVYU:
14355 case DRM_FORMAT_VYUY:
14356 if (INTEL_INFO(dev)->gen < 5) {
14357 DRM_DEBUG("unsupported pixel format: %s\n",
14358 drm_get_format_name(mode_cmd->pixel_format));
14359 return -EINVAL;
14360 }
14361 break;
14362 default:
14363 DRM_DEBUG("unsupported pixel format: %s\n",
14364 drm_get_format_name(mode_cmd->pixel_format));
14365 return -EINVAL;
14366 }
14367
14368 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14369 if (mode_cmd->offsets[0] != 0)
14370 return -EINVAL;
14371
14372 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14373 mode_cmd->pixel_format,
14374 mode_cmd->modifier[0]);
14375 /* FIXME drm helper for size checks (especially planar formats)? */
14376 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14377 return -EINVAL;
14378
14379 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14380 intel_fb->obj = obj;
14381
14382 intel_fill_fb_info(dev_priv, &intel_fb->base);
14383
14384 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14385 if (ret) {
14386 DRM_ERROR("framebuffer init failed %d\n", ret);
14387 return ret;
14388 }
14389
14390 intel_fb->obj->framebuffer_references++;
14391
14392 return 0;
14393 }
14394
14395 static struct drm_framebuffer *
14396 intel_user_framebuffer_create(struct drm_device *dev,
14397 struct drm_file *filp,
14398 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14399 {
14400 struct drm_framebuffer *fb;
14401 struct drm_i915_gem_object *obj;
14402 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14403
14404 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14405 mode_cmd.handles[0]));
14406 if (&obj->base == NULL)
14407 return ERR_PTR(-ENOENT);
14408
14409 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14410 if (IS_ERR(fb))
14411 drm_gem_object_unreference_unlocked(&obj->base);
14412
14413 return fb;
14414 }
14415
14416 #ifndef CONFIG_DRM_FBDEV_EMULATION
14417 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14418 {
14419 }
14420 #endif
14421
14422 static const struct drm_mode_config_funcs intel_mode_funcs = {
14423 .fb_create = intel_user_framebuffer_create,
14424 .output_poll_changed = intel_fbdev_output_poll_changed,
14425 .atomic_check = intel_atomic_check,
14426 .atomic_commit = intel_atomic_commit,
14427 .atomic_state_alloc = intel_atomic_state_alloc,
14428 .atomic_state_clear = intel_atomic_state_clear,
14429 };
14430
14431 /**
14432 * intel_init_display_hooks - initialize the display modesetting hooks
14433 * @dev_priv: device private
14434 */
14435 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14436 {
14437 if (INTEL_INFO(dev_priv)->gen >= 9) {
14438 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14439 dev_priv->display.get_initial_plane_config =
14440 skylake_get_initial_plane_config;
14441 dev_priv->display.crtc_compute_clock =
14442 haswell_crtc_compute_clock;
14443 dev_priv->display.crtc_enable = haswell_crtc_enable;
14444 dev_priv->display.crtc_disable = haswell_crtc_disable;
14445 } else if (HAS_DDI(dev_priv)) {
14446 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14447 dev_priv->display.get_initial_plane_config =
14448 ironlake_get_initial_plane_config;
14449 dev_priv->display.crtc_compute_clock =
14450 haswell_crtc_compute_clock;
14451 dev_priv->display.crtc_enable = haswell_crtc_enable;
14452 dev_priv->display.crtc_disable = haswell_crtc_disable;
14453 } else if (HAS_PCH_SPLIT(dev_priv)) {
14454 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14455 dev_priv->display.get_initial_plane_config =
14456 ironlake_get_initial_plane_config;
14457 dev_priv->display.crtc_compute_clock =
14458 ironlake_crtc_compute_clock;
14459 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14460 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14461 } else if (IS_CHERRYVIEW(dev_priv)) {
14462 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14463 dev_priv->display.get_initial_plane_config =
14464 i9xx_get_initial_plane_config;
14465 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14466 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14467 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14468 } else if (IS_VALLEYVIEW(dev_priv)) {
14469 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14470 dev_priv->display.get_initial_plane_config =
14471 i9xx_get_initial_plane_config;
14472 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14473 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14474 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14475 } else if (IS_G4X(dev_priv)) {
14476 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14477 dev_priv->display.get_initial_plane_config =
14478 i9xx_get_initial_plane_config;
14479 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14480 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14481 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14482 } else if (IS_PINEVIEW(dev_priv)) {
14483 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14484 dev_priv->display.get_initial_plane_config =
14485 i9xx_get_initial_plane_config;
14486 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14487 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14488 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14489 } else if (!IS_GEN2(dev_priv)) {
14490 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14491 dev_priv->display.get_initial_plane_config =
14492 i9xx_get_initial_plane_config;
14493 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14494 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14495 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14496 } else {
14497 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14498 dev_priv->display.get_initial_plane_config =
14499 i9xx_get_initial_plane_config;
14500 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14501 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14502 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14503 }
14504
14505 /* Returns the core display clock speed */
14506 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14507 dev_priv->display.get_display_clock_speed =
14508 skylake_get_display_clock_speed;
14509 else if (IS_BROXTON(dev_priv))
14510 dev_priv->display.get_display_clock_speed =
14511 broxton_get_display_clock_speed;
14512 else if (IS_BROADWELL(dev_priv))
14513 dev_priv->display.get_display_clock_speed =
14514 broadwell_get_display_clock_speed;
14515 else if (IS_HASWELL(dev_priv))
14516 dev_priv->display.get_display_clock_speed =
14517 haswell_get_display_clock_speed;
14518 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14519 dev_priv->display.get_display_clock_speed =
14520 valleyview_get_display_clock_speed;
14521 else if (IS_GEN5(dev_priv))
14522 dev_priv->display.get_display_clock_speed =
14523 ilk_get_display_clock_speed;
14524 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14525 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14526 dev_priv->display.get_display_clock_speed =
14527 i945_get_display_clock_speed;
14528 else if (IS_GM45(dev_priv))
14529 dev_priv->display.get_display_clock_speed =
14530 gm45_get_display_clock_speed;
14531 else if (IS_CRESTLINE(dev_priv))
14532 dev_priv->display.get_display_clock_speed =
14533 i965gm_get_display_clock_speed;
14534 else if (IS_PINEVIEW(dev_priv))
14535 dev_priv->display.get_display_clock_speed =
14536 pnv_get_display_clock_speed;
14537 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14538 dev_priv->display.get_display_clock_speed =
14539 g33_get_display_clock_speed;
14540 else if (IS_I915G(dev_priv))
14541 dev_priv->display.get_display_clock_speed =
14542 i915_get_display_clock_speed;
14543 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14544 dev_priv->display.get_display_clock_speed =
14545 i9xx_misc_get_display_clock_speed;
14546 else if (IS_I915GM(dev_priv))
14547 dev_priv->display.get_display_clock_speed =
14548 i915gm_get_display_clock_speed;
14549 else if (IS_I865G(dev_priv))
14550 dev_priv->display.get_display_clock_speed =
14551 i865_get_display_clock_speed;
14552 else if (IS_I85X(dev_priv))
14553 dev_priv->display.get_display_clock_speed =
14554 i85x_get_display_clock_speed;
14555 else { /* 830 */
14556 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14557 dev_priv->display.get_display_clock_speed =
14558 i830_get_display_clock_speed;
14559 }
14560
14561 if (IS_GEN5(dev_priv)) {
14562 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14563 } else if (IS_GEN6(dev_priv)) {
14564 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14565 } else if (IS_IVYBRIDGE(dev_priv)) {
14566 /* FIXME: detect B0+ stepping and use auto training */
14567 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14568 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14569 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14570 }
14571
14572 if (IS_BROADWELL(dev_priv)) {
14573 dev_priv->display.modeset_commit_cdclk =
14574 broadwell_modeset_commit_cdclk;
14575 dev_priv->display.modeset_calc_cdclk =
14576 broadwell_modeset_calc_cdclk;
14577 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14578 dev_priv->display.modeset_commit_cdclk =
14579 valleyview_modeset_commit_cdclk;
14580 dev_priv->display.modeset_calc_cdclk =
14581 valleyview_modeset_calc_cdclk;
14582 } else if (IS_BROXTON(dev_priv)) {
14583 dev_priv->display.modeset_commit_cdclk =
14584 broxton_modeset_commit_cdclk;
14585 dev_priv->display.modeset_calc_cdclk =
14586 broxton_modeset_calc_cdclk;
14587 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
14588 dev_priv->display.modeset_commit_cdclk =
14589 skl_modeset_commit_cdclk;
14590 dev_priv->display.modeset_calc_cdclk =
14591 skl_modeset_calc_cdclk;
14592 }
14593 }
14594
14595 /*
14596 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14597 * resume, or other times. This quirk makes sure that's the case for
14598 * affected systems.
14599 */
14600 static void quirk_pipea_force(struct drm_device *dev)
14601 {
14602 struct drm_i915_private *dev_priv = dev->dev_private;
14603
14604 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14605 DRM_INFO("applying pipe a force quirk\n");
14606 }
14607
14608 static void quirk_pipeb_force(struct drm_device *dev)
14609 {
14610 struct drm_i915_private *dev_priv = dev->dev_private;
14611
14612 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14613 DRM_INFO("applying pipe b force quirk\n");
14614 }
14615
14616 /*
14617 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14618 */
14619 static void quirk_ssc_force_disable(struct drm_device *dev)
14620 {
14621 struct drm_i915_private *dev_priv = dev->dev_private;
14622 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14623 DRM_INFO("applying lvds SSC disable quirk\n");
14624 }
14625
14626 /*
14627 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14628 * brightness value
14629 */
14630 static void quirk_invert_brightness(struct drm_device *dev)
14631 {
14632 struct drm_i915_private *dev_priv = dev->dev_private;
14633 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14634 DRM_INFO("applying inverted panel brightness quirk\n");
14635 }
14636
14637 /* Some VBT's incorrectly indicate no backlight is present */
14638 static void quirk_backlight_present(struct drm_device *dev)
14639 {
14640 struct drm_i915_private *dev_priv = dev->dev_private;
14641 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14642 DRM_INFO("applying backlight present quirk\n");
14643 }
14644
14645 struct intel_quirk {
14646 int device;
14647 int subsystem_vendor;
14648 int subsystem_device;
14649 void (*hook)(struct drm_device *dev);
14650 };
14651
14652 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14653 struct intel_dmi_quirk {
14654 void (*hook)(struct drm_device *dev);
14655 const struct dmi_system_id (*dmi_id_list)[];
14656 };
14657
14658 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14659 {
14660 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14661 return 1;
14662 }
14663
14664 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14665 {
14666 .dmi_id_list = &(const struct dmi_system_id[]) {
14667 {
14668 .callback = intel_dmi_reverse_brightness,
14669 .ident = "NCR Corporation",
14670 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14671 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14672 },
14673 },
14674 { } /* terminating entry */
14675 },
14676 .hook = quirk_invert_brightness,
14677 },
14678 };
14679
14680 static struct intel_quirk intel_quirks[] = {
14681 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14682 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14683
14684 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14685 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14686
14687 /* 830 needs to leave pipe A & dpll A up */
14688 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14689
14690 /* 830 needs to leave pipe B & dpll B up */
14691 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14692
14693 /* Lenovo U160 cannot use SSC on LVDS */
14694 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14695
14696 /* Sony Vaio Y cannot use SSC on LVDS */
14697 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14698
14699 /* Acer Aspire 5734Z must invert backlight brightness */
14700 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14701
14702 /* Acer/eMachines G725 */
14703 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14704
14705 /* Acer/eMachines e725 */
14706 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14707
14708 /* Acer/Packard Bell NCL20 */
14709 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14710
14711 /* Acer Aspire 4736Z */
14712 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14713
14714 /* Acer Aspire 5336 */
14715 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14716
14717 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14718 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14719
14720 /* Acer C720 Chromebook (Core i3 4005U) */
14721 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14722
14723 /* Apple Macbook 2,1 (Core 2 T7400) */
14724 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14725
14726 /* Apple Macbook 4,1 */
14727 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14728
14729 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14730 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14731
14732 /* HP Chromebook 14 (Celeron 2955U) */
14733 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14734
14735 /* Dell Chromebook 11 */
14736 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14737
14738 /* Dell Chromebook 11 (2015 version) */
14739 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14740 };
14741
14742 static void intel_init_quirks(struct drm_device *dev)
14743 {
14744 struct pci_dev *d = dev->pdev;
14745 int i;
14746
14747 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14748 struct intel_quirk *q = &intel_quirks[i];
14749
14750 if (d->device == q->device &&
14751 (d->subsystem_vendor == q->subsystem_vendor ||
14752 q->subsystem_vendor == PCI_ANY_ID) &&
14753 (d->subsystem_device == q->subsystem_device ||
14754 q->subsystem_device == PCI_ANY_ID))
14755 q->hook(dev);
14756 }
14757 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14758 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14759 intel_dmi_quirks[i].hook(dev);
14760 }
14761 }
14762
14763 /* Disable the VGA plane that we never use */
14764 static void i915_disable_vga(struct drm_device *dev)
14765 {
14766 struct drm_i915_private *dev_priv = dev->dev_private;
14767 u8 sr1;
14768 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
14769
14770 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14771 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14772 outb(SR01, VGA_SR_INDEX);
14773 sr1 = inb(VGA_SR_DATA);
14774 outb(sr1 | 1<<5, VGA_SR_DATA);
14775 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14776 udelay(300);
14777
14778 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14779 POSTING_READ(vga_reg);
14780 }
14781
14782 void intel_modeset_init_hw(struct drm_device *dev)
14783 {
14784 struct drm_i915_private *dev_priv = dev->dev_private;
14785
14786 intel_update_cdclk(dev);
14787
14788 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
14789
14790 intel_init_clock_gating(dev);
14791 intel_enable_gt_powersave(dev_priv);
14792 }
14793
14794 /*
14795 * Calculate what we think the watermarks should be for the state we've read
14796 * out of the hardware and then immediately program those watermarks so that
14797 * we ensure the hardware settings match our internal state.
14798 *
14799 * We can calculate what we think WM's should be by creating a duplicate of the
14800 * current state (which was constructed during hardware readout) and running it
14801 * through the atomic check code to calculate new watermark values in the
14802 * state object.
14803 */
14804 static void sanitize_watermarks(struct drm_device *dev)
14805 {
14806 struct drm_i915_private *dev_priv = to_i915(dev);
14807 struct drm_atomic_state *state;
14808 struct drm_crtc *crtc;
14809 struct drm_crtc_state *cstate;
14810 struct drm_modeset_acquire_ctx ctx;
14811 int ret;
14812 int i;
14813
14814 /* Only supported on platforms that use atomic watermark design */
14815 if (!dev_priv->display.optimize_watermarks)
14816 return;
14817
14818 /*
14819 * We need to hold connection_mutex before calling duplicate_state so
14820 * that the connector loop is protected.
14821 */
14822 drm_modeset_acquire_init(&ctx, 0);
14823 retry:
14824 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14825 if (ret == -EDEADLK) {
14826 drm_modeset_backoff(&ctx);
14827 goto retry;
14828 } else if (WARN_ON(ret)) {
14829 goto fail;
14830 }
14831
14832 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14833 if (WARN_ON(IS_ERR(state)))
14834 goto fail;
14835
14836 /*
14837 * Hardware readout is the only time we don't want to calculate
14838 * intermediate watermarks (since we don't trust the current
14839 * watermarks).
14840 */
14841 to_intel_atomic_state(state)->skip_intermediate_wm = true;
14842
14843 ret = intel_atomic_check(dev, state);
14844 if (ret) {
14845 /*
14846 * If we fail here, it means that the hardware appears to be
14847 * programmed in a way that shouldn't be possible, given our
14848 * understanding of watermark requirements. This might mean a
14849 * mistake in the hardware readout code or a mistake in the
14850 * watermark calculations for a given platform. Raise a WARN
14851 * so that this is noticeable.
14852 *
14853 * If this actually happens, we'll have to just leave the
14854 * BIOS-programmed watermarks untouched and hope for the best.
14855 */
14856 WARN(true, "Could not determine valid watermarks for inherited state\n");
14857 goto fail;
14858 }
14859
14860 /* Write calculated watermark values back */
14861 for_each_crtc_in_state(state, crtc, cstate, i) {
14862 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14863
14864 cs->wm.need_postvbl_update = true;
14865 dev_priv->display.optimize_watermarks(cs);
14866 }
14867
14868 drm_atomic_state_free(state);
14869 fail:
14870 drm_modeset_drop_locks(&ctx);
14871 drm_modeset_acquire_fini(&ctx);
14872 }
14873
14874 void intel_modeset_init(struct drm_device *dev)
14875 {
14876 struct drm_i915_private *dev_priv = to_i915(dev);
14877 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14878 int sprite, ret;
14879 enum pipe pipe;
14880 struct intel_crtc *crtc;
14881
14882 drm_mode_config_init(dev);
14883
14884 dev->mode_config.min_width = 0;
14885 dev->mode_config.min_height = 0;
14886
14887 dev->mode_config.preferred_depth = 24;
14888 dev->mode_config.prefer_shadow = 1;
14889
14890 dev->mode_config.allow_fb_modifiers = true;
14891
14892 dev->mode_config.funcs = &intel_mode_funcs;
14893
14894 intel_init_quirks(dev);
14895
14896 intel_init_pm(dev);
14897
14898 if (INTEL_INFO(dev)->num_pipes == 0)
14899 return;
14900
14901 /*
14902 * There may be no VBT; and if the BIOS enabled SSC we can
14903 * just keep using it to avoid unnecessary flicker. Whereas if the
14904 * BIOS isn't using it, don't assume it will work even if the VBT
14905 * indicates as much.
14906 */
14907 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14908 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14909 DREF_SSC1_ENABLE);
14910
14911 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14912 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14913 bios_lvds_use_ssc ? "en" : "dis",
14914 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14915 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14916 }
14917 }
14918
14919 if (IS_GEN2(dev)) {
14920 dev->mode_config.max_width = 2048;
14921 dev->mode_config.max_height = 2048;
14922 } else if (IS_GEN3(dev)) {
14923 dev->mode_config.max_width = 4096;
14924 dev->mode_config.max_height = 4096;
14925 } else {
14926 dev->mode_config.max_width = 8192;
14927 dev->mode_config.max_height = 8192;
14928 }
14929
14930 if (IS_845G(dev) || IS_I865G(dev)) {
14931 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14932 dev->mode_config.cursor_height = 1023;
14933 } else if (IS_GEN2(dev)) {
14934 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14935 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14936 } else {
14937 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14938 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14939 }
14940
14941 dev->mode_config.fb_base = ggtt->mappable_base;
14942
14943 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14944 INTEL_INFO(dev)->num_pipes,
14945 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14946
14947 for_each_pipe(dev_priv, pipe) {
14948 intel_crtc_init(dev, pipe);
14949 for_each_sprite(dev_priv, pipe, sprite) {
14950 ret = intel_plane_init(dev, pipe, sprite);
14951 if (ret)
14952 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14953 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14954 }
14955 }
14956
14957 intel_update_czclk(dev_priv);
14958 intel_update_cdclk(dev);
14959
14960 intel_shared_dpll_init(dev);
14961
14962 if (dev_priv->max_cdclk_freq == 0)
14963 intel_update_max_cdclk(dev);
14964
14965 /* Just disable it once at startup */
14966 i915_disable_vga(dev);
14967 intel_setup_outputs(dev);
14968
14969 drm_modeset_lock_all(dev);
14970 intel_modeset_setup_hw_state(dev);
14971 drm_modeset_unlock_all(dev);
14972
14973 for_each_intel_crtc(dev, crtc) {
14974 struct intel_initial_plane_config plane_config = {};
14975
14976 if (!crtc->active)
14977 continue;
14978
14979 /*
14980 * Note that reserving the BIOS fb up front prevents us
14981 * from stuffing other stolen allocations like the ring
14982 * on top. This prevents some ugliness at boot time, and
14983 * can even allow for smooth boot transitions if the BIOS
14984 * fb is large enough for the active pipe configuration.
14985 */
14986 dev_priv->display.get_initial_plane_config(crtc,
14987 &plane_config);
14988
14989 /*
14990 * If the fb is shared between multiple heads, we'll
14991 * just get the first one.
14992 */
14993 intel_find_initial_plane_obj(crtc, &plane_config);
14994 }
14995
14996 /*
14997 * Make sure hardware watermarks really match the state we read out.
14998 * Note that we need to do this after reconstructing the BIOS fb's
14999 * since the watermark calculation done here will use pstate->fb.
15000 */
15001 sanitize_watermarks(dev);
15002 }
15003
15004 static void intel_enable_pipe_a(struct drm_device *dev)
15005 {
15006 struct intel_connector *connector;
15007 struct drm_connector *crt = NULL;
15008 struct intel_load_detect_pipe load_detect_temp;
15009 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15010
15011 /* We can't just switch on the pipe A, we need to set things up with a
15012 * proper mode and output configuration. As a gross hack, enable pipe A
15013 * by enabling the load detect pipe once. */
15014 for_each_intel_connector(dev, connector) {
15015 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15016 crt = &connector->base;
15017 break;
15018 }
15019 }
15020
15021 if (!crt)
15022 return;
15023
15024 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15025 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15026 }
15027
15028 static bool
15029 intel_check_plane_mapping(struct intel_crtc *crtc)
15030 {
15031 struct drm_device *dev = crtc->base.dev;
15032 struct drm_i915_private *dev_priv = dev->dev_private;
15033 u32 val;
15034
15035 if (INTEL_INFO(dev)->num_pipes == 1)
15036 return true;
15037
15038 val = I915_READ(DSPCNTR(!crtc->plane));
15039
15040 if ((val & DISPLAY_PLANE_ENABLE) &&
15041 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15042 return false;
15043
15044 return true;
15045 }
15046
15047 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15048 {
15049 struct drm_device *dev = crtc->base.dev;
15050 struct intel_encoder *encoder;
15051
15052 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15053 return true;
15054
15055 return false;
15056 }
15057
15058 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15059 {
15060 struct drm_device *dev = encoder->base.dev;
15061 struct intel_connector *connector;
15062
15063 for_each_connector_on_encoder(dev, &encoder->base, connector)
15064 return true;
15065
15066 return false;
15067 }
15068
15069 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15070 {
15071 struct drm_device *dev = crtc->base.dev;
15072 struct drm_i915_private *dev_priv = dev->dev_private;
15073 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15074
15075 /* Clear any frame start delays used for debugging left by the BIOS */
15076 if (!transcoder_is_dsi(cpu_transcoder)) {
15077 i915_reg_t reg = PIPECONF(cpu_transcoder);
15078
15079 I915_WRITE(reg,
15080 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15081 }
15082
15083 /* restore vblank interrupts to correct state */
15084 drm_crtc_vblank_reset(&crtc->base);
15085 if (crtc->active) {
15086 struct intel_plane *plane;
15087
15088 drm_crtc_vblank_on(&crtc->base);
15089
15090 /* Disable everything but the primary plane */
15091 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15092 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15093 continue;
15094
15095 plane->disable_plane(&plane->base, &crtc->base);
15096 }
15097 }
15098
15099 /* We need to sanitize the plane -> pipe mapping first because this will
15100 * disable the crtc (and hence change the state) if it is wrong. Note
15101 * that gen4+ has a fixed plane -> pipe mapping. */
15102 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15103 bool plane;
15104
15105 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15106 crtc->base.base.id);
15107
15108 /* Pipe has the wrong plane attached and the plane is active.
15109 * Temporarily change the plane mapping and disable everything
15110 * ... */
15111 plane = crtc->plane;
15112 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15113 crtc->plane = !plane;
15114 intel_crtc_disable_noatomic(&crtc->base);
15115 crtc->plane = plane;
15116 }
15117
15118 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15119 crtc->pipe == PIPE_A && !crtc->active) {
15120 /* BIOS forgot to enable pipe A, this mostly happens after
15121 * resume. Force-enable the pipe to fix this, the update_dpms
15122 * call below we restore the pipe to the right state, but leave
15123 * the required bits on. */
15124 intel_enable_pipe_a(dev);
15125 }
15126
15127 /* Adjust the state of the output pipe according to whether we
15128 * have active connectors/encoders. */
15129 if (crtc->active && !intel_crtc_has_encoders(crtc))
15130 intel_crtc_disable_noatomic(&crtc->base);
15131
15132 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15133 /*
15134 * We start out with underrun reporting disabled to avoid races.
15135 * For correct bookkeeping mark this on active crtcs.
15136 *
15137 * Also on gmch platforms we dont have any hardware bits to
15138 * disable the underrun reporting. Which means we need to start
15139 * out with underrun reporting disabled also on inactive pipes,
15140 * since otherwise we'll complain about the garbage we read when
15141 * e.g. coming up after runtime pm.
15142 *
15143 * No protection against concurrent access is required - at
15144 * worst a fifo underrun happens which also sets this to false.
15145 */
15146 crtc->cpu_fifo_underrun_disabled = true;
15147 crtc->pch_fifo_underrun_disabled = true;
15148 }
15149 }
15150
15151 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15152 {
15153 struct intel_connector *connector;
15154 struct drm_device *dev = encoder->base.dev;
15155
15156 /* We need to check both for a crtc link (meaning that the
15157 * encoder is active and trying to read from a pipe) and the
15158 * pipe itself being active. */
15159 bool has_active_crtc = encoder->base.crtc &&
15160 to_intel_crtc(encoder->base.crtc)->active;
15161
15162 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15163 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15164 encoder->base.base.id,
15165 encoder->base.name);
15166
15167 /* Connector is active, but has no active pipe. This is
15168 * fallout from our resume register restoring. Disable
15169 * the encoder manually again. */
15170 if (encoder->base.crtc) {
15171 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15172 encoder->base.base.id,
15173 encoder->base.name);
15174 encoder->disable(encoder);
15175 if (encoder->post_disable)
15176 encoder->post_disable(encoder);
15177 }
15178 encoder->base.crtc = NULL;
15179
15180 /* Inconsistent output/port/pipe state happens presumably due to
15181 * a bug in one of the get_hw_state functions. Or someplace else
15182 * in our code, like the register restore mess on resume. Clamp
15183 * things to off as a safer default. */
15184 for_each_intel_connector(dev, connector) {
15185 if (connector->encoder != encoder)
15186 continue;
15187 connector->base.dpms = DRM_MODE_DPMS_OFF;
15188 connector->base.encoder = NULL;
15189 }
15190 }
15191 /* Enabled encoders without active connectors will be fixed in
15192 * the crtc fixup. */
15193 }
15194
15195 void i915_redisable_vga_power_on(struct drm_device *dev)
15196 {
15197 struct drm_i915_private *dev_priv = dev->dev_private;
15198 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15199
15200 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15201 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15202 i915_disable_vga(dev);
15203 }
15204 }
15205
15206 void i915_redisable_vga(struct drm_device *dev)
15207 {
15208 struct drm_i915_private *dev_priv = dev->dev_private;
15209
15210 /* This function can be called both from intel_modeset_setup_hw_state or
15211 * at a very early point in our resume sequence, where the power well
15212 * structures are not yet restored. Since this function is at a very
15213 * paranoid "someone might have enabled VGA while we were not looking"
15214 * level, just check if the power well is enabled instead of trying to
15215 * follow the "don't touch the power well if we don't need it" policy
15216 * the rest of the driver uses. */
15217 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15218 return;
15219
15220 i915_redisable_vga_power_on(dev);
15221
15222 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15223 }
15224
15225 static bool primary_get_hw_state(struct intel_plane *plane)
15226 {
15227 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15228
15229 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15230 }
15231
15232 /* FIXME read out full plane state for all planes */
15233 static void readout_plane_state(struct intel_crtc *crtc)
15234 {
15235 struct drm_plane *primary = crtc->base.primary;
15236 struct intel_plane_state *plane_state =
15237 to_intel_plane_state(primary->state);
15238
15239 plane_state->visible = crtc->active &&
15240 primary_get_hw_state(to_intel_plane(primary));
15241
15242 if (plane_state->visible)
15243 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15244 }
15245
15246 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15247 {
15248 struct drm_i915_private *dev_priv = dev->dev_private;
15249 enum pipe pipe;
15250 struct intel_crtc *crtc;
15251 struct intel_encoder *encoder;
15252 struct intel_connector *connector;
15253 int i;
15254
15255 dev_priv->active_crtcs = 0;
15256
15257 for_each_intel_crtc(dev, crtc) {
15258 struct intel_crtc_state *crtc_state = crtc->config;
15259 int pixclk = 0;
15260
15261 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15262 memset(crtc_state, 0, sizeof(*crtc_state));
15263 crtc_state->base.crtc = &crtc->base;
15264
15265 crtc_state->base.active = crtc_state->base.enable =
15266 dev_priv->display.get_pipe_config(crtc, crtc_state);
15267
15268 crtc->base.enabled = crtc_state->base.enable;
15269 crtc->active = crtc_state->base.active;
15270
15271 if (crtc_state->base.active) {
15272 dev_priv->active_crtcs |= 1 << crtc->pipe;
15273
15274 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15275 pixclk = ilk_pipe_pixel_rate(crtc_state);
15276 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15277 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15278 else
15279 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15280
15281 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15282 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15283 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15284 }
15285
15286 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15287
15288 readout_plane_state(crtc);
15289
15290 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15291 crtc->base.base.id,
15292 crtc->active ? "enabled" : "disabled");
15293 }
15294
15295 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15296 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15297
15298 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15299 &pll->config.hw_state);
15300 pll->config.crtc_mask = 0;
15301 for_each_intel_crtc(dev, crtc) {
15302 if (crtc->active && crtc->config->shared_dpll == pll)
15303 pll->config.crtc_mask |= 1 << crtc->pipe;
15304 }
15305 pll->active_mask = pll->config.crtc_mask;
15306
15307 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15308 pll->name, pll->config.crtc_mask, pll->on);
15309 }
15310
15311 for_each_intel_encoder(dev, encoder) {
15312 pipe = 0;
15313
15314 if (encoder->get_hw_state(encoder, &pipe)) {
15315 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15316 encoder->base.crtc = &crtc->base;
15317 encoder->get_config(encoder, crtc->config);
15318 } else {
15319 encoder->base.crtc = NULL;
15320 }
15321
15322 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15323 encoder->base.base.id,
15324 encoder->base.name,
15325 encoder->base.crtc ? "enabled" : "disabled",
15326 pipe_name(pipe));
15327 }
15328
15329 for_each_intel_connector(dev, connector) {
15330 if (connector->get_hw_state(connector)) {
15331 connector->base.dpms = DRM_MODE_DPMS_ON;
15332
15333 encoder = connector->encoder;
15334 connector->base.encoder = &encoder->base;
15335
15336 if (encoder->base.crtc &&
15337 encoder->base.crtc->state->active) {
15338 /*
15339 * This has to be done during hardware readout
15340 * because anything calling .crtc_disable may
15341 * rely on the connector_mask being accurate.
15342 */
15343 encoder->base.crtc->state->connector_mask |=
15344 1 << drm_connector_index(&connector->base);
15345 encoder->base.crtc->state->encoder_mask |=
15346 1 << drm_encoder_index(&encoder->base);
15347 }
15348
15349 } else {
15350 connector->base.dpms = DRM_MODE_DPMS_OFF;
15351 connector->base.encoder = NULL;
15352 }
15353 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15354 connector->base.base.id,
15355 connector->base.name,
15356 connector->base.encoder ? "enabled" : "disabled");
15357 }
15358
15359 for_each_intel_crtc(dev, crtc) {
15360 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15361
15362 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15363 if (crtc->base.state->active) {
15364 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15365 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15366 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15367
15368 /*
15369 * The initial mode needs to be set in order to keep
15370 * the atomic core happy. It wants a valid mode if the
15371 * crtc's enabled, so we do the above call.
15372 *
15373 * At this point some state updated by the connectors
15374 * in their ->detect() callback has not run yet, so
15375 * no recalculation can be done yet.
15376 *
15377 * Even if we could do a recalculation and modeset
15378 * right now it would cause a double modeset if
15379 * fbdev or userspace chooses a different initial mode.
15380 *
15381 * If that happens, someone indicated they wanted a
15382 * mode change, which means it's safe to do a full
15383 * recalculation.
15384 */
15385 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15386
15387 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15388 update_scanline_offset(crtc);
15389 }
15390
15391 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15392 }
15393 }
15394
15395 /* Scan out the current hw modeset state,
15396 * and sanitizes it to the current state
15397 */
15398 static void
15399 intel_modeset_setup_hw_state(struct drm_device *dev)
15400 {
15401 struct drm_i915_private *dev_priv = dev->dev_private;
15402 enum pipe pipe;
15403 struct intel_crtc *crtc;
15404 struct intel_encoder *encoder;
15405 int i;
15406
15407 intel_modeset_readout_hw_state(dev);
15408
15409 /* HW state is read out, now we need to sanitize this mess. */
15410 for_each_intel_encoder(dev, encoder) {
15411 intel_sanitize_encoder(encoder);
15412 }
15413
15414 for_each_pipe(dev_priv, pipe) {
15415 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15416 intel_sanitize_crtc(crtc);
15417 intel_dump_pipe_config(crtc, crtc->config,
15418 "[setup_hw_state]");
15419 }
15420
15421 intel_modeset_update_connector_atomic_state(dev);
15422
15423 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15424 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15425
15426 if (!pll->on || pll->active_mask)
15427 continue;
15428
15429 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15430
15431 pll->funcs.disable(dev_priv, pll);
15432 pll->on = false;
15433 }
15434
15435 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15436 vlv_wm_get_hw_state(dev);
15437 else if (IS_GEN9(dev))
15438 skl_wm_get_hw_state(dev);
15439 else if (HAS_PCH_SPLIT(dev))
15440 ilk_wm_get_hw_state(dev);
15441
15442 for_each_intel_crtc(dev, crtc) {
15443 unsigned long put_domains;
15444
15445 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15446 if (WARN_ON(put_domains))
15447 modeset_put_power_domains(dev_priv, put_domains);
15448 }
15449 intel_display_set_init_power(dev_priv, false);
15450
15451 intel_fbc_init_pipe_state(dev_priv);
15452 }
15453
15454 void intel_display_resume(struct drm_device *dev)
15455 {
15456 struct drm_i915_private *dev_priv = to_i915(dev);
15457 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15458 struct drm_modeset_acquire_ctx ctx;
15459 int ret;
15460 bool setup = false;
15461
15462 dev_priv->modeset_restore_state = NULL;
15463
15464 /*
15465 * This is a cludge because with real atomic modeset mode_config.mutex
15466 * won't be taken. Unfortunately some probed state like
15467 * audio_codec_enable is still protected by mode_config.mutex, so lock
15468 * it here for now.
15469 */
15470 mutex_lock(&dev->mode_config.mutex);
15471 drm_modeset_acquire_init(&ctx, 0);
15472
15473 retry:
15474 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15475
15476 if (ret == 0 && !setup) {
15477 setup = true;
15478
15479 intel_modeset_setup_hw_state(dev);
15480 i915_redisable_vga(dev);
15481 }
15482
15483 if (ret == 0 && state) {
15484 struct drm_crtc_state *crtc_state;
15485 struct drm_crtc *crtc;
15486 int i;
15487
15488 state->acquire_ctx = &ctx;
15489
15490 /* ignore any reset values/BIOS leftovers in the WM registers */
15491 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15492
15493 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15494 /*
15495 * Force recalculation even if we restore
15496 * current state. With fast modeset this may not result
15497 * in a modeset when the state is compatible.
15498 */
15499 crtc_state->mode_changed = true;
15500 }
15501
15502 ret = drm_atomic_commit(state);
15503 }
15504
15505 if (ret == -EDEADLK) {
15506 drm_modeset_backoff(&ctx);
15507 goto retry;
15508 }
15509
15510 drm_modeset_drop_locks(&ctx);
15511 drm_modeset_acquire_fini(&ctx);
15512 mutex_unlock(&dev->mode_config.mutex);
15513
15514 if (ret) {
15515 DRM_ERROR("Restoring old state failed with %i\n", ret);
15516 drm_atomic_state_free(state);
15517 }
15518 }
15519
15520 void intel_modeset_gem_init(struct drm_device *dev)
15521 {
15522 struct drm_i915_private *dev_priv = to_i915(dev);
15523 struct drm_crtc *c;
15524 struct drm_i915_gem_object *obj;
15525 int ret;
15526
15527 intel_init_gt_powersave(dev_priv);
15528
15529 intel_modeset_init_hw(dev);
15530
15531 intel_setup_overlay(dev_priv);
15532
15533 /*
15534 * Make sure any fbs we allocated at startup are properly
15535 * pinned & fenced. When we do the allocation it's too early
15536 * for this.
15537 */
15538 for_each_crtc(dev, c) {
15539 obj = intel_fb_obj(c->primary->fb);
15540 if (obj == NULL)
15541 continue;
15542
15543 mutex_lock(&dev->struct_mutex);
15544 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15545 c->primary->state->rotation);
15546 mutex_unlock(&dev->struct_mutex);
15547 if (ret) {
15548 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15549 to_intel_crtc(c)->pipe);
15550 drm_framebuffer_unreference(c->primary->fb);
15551 drm_framebuffer_unreference(c->primary->state->fb);
15552 c->primary->fb = c->primary->state->fb = NULL;
15553 c->primary->crtc = c->primary->state->crtc = NULL;
15554 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15555 }
15556 }
15557
15558 intel_backlight_register(dev);
15559 }
15560
15561 void intel_connector_unregister(struct intel_connector *intel_connector)
15562 {
15563 struct drm_connector *connector = &intel_connector->base;
15564
15565 intel_panel_destroy_backlight(connector);
15566 drm_connector_unregister(connector);
15567 }
15568
15569 void intel_modeset_cleanup(struct drm_device *dev)
15570 {
15571 struct drm_i915_private *dev_priv = dev->dev_private;
15572 struct intel_connector *connector;
15573
15574 intel_disable_gt_powersave(dev_priv);
15575
15576 intel_backlight_unregister(dev);
15577
15578 /*
15579 * Interrupts and polling as the first thing to avoid creating havoc.
15580 * Too much stuff here (turning of connectors, ...) would
15581 * experience fancy races otherwise.
15582 */
15583 intel_irq_uninstall(dev_priv);
15584
15585 /*
15586 * Due to the hpd irq storm handling the hotplug work can re-arm the
15587 * poll handlers. Hence disable polling after hpd handling is shut down.
15588 */
15589 drm_kms_helper_poll_fini(dev);
15590
15591 intel_unregister_dsm_handler();
15592
15593 intel_fbc_global_disable(dev_priv);
15594
15595 /* flush any delayed tasks or pending work */
15596 flush_scheduled_work();
15597
15598 /* destroy the backlight and sysfs files before encoders/connectors */
15599 for_each_intel_connector(dev, connector)
15600 connector->unregister(connector);
15601
15602 drm_mode_config_cleanup(dev);
15603
15604 intel_cleanup_overlay(dev_priv);
15605
15606 intel_cleanup_gt_powersave(dev_priv);
15607
15608 intel_teardown_gmbus(dev);
15609 }
15610
15611 /*
15612 * Return which encoder is currently attached for connector.
15613 */
15614 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15615 {
15616 return &intel_attached_encoder(connector)->base;
15617 }
15618
15619 void intel_connector_attach_encoder(struct intel_connector *connector,
15620 struct intel_encoder *encoder)
15621 {
15622 connector->encoder = encoder;
15623 drm_mode_connector_attach_encoder(&connector->base,
15624 &encoder->base);
15625 }
15626
15627 /*
15628 * set vga decode state - true == enable VGA decode
15629 */
15630 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15631 {
15632 struct drm_i915_private *dev_priv = dev->dev_private;
15633 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15634 u16 gmch_ctrl;
15635
15636 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15637 DRM_ERROR("failed to read control word\n");
15638 return -EIO;
15639 }
15640
15641 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15642 return 0;
15643
15644 if (state)
15645 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15646 else
15647 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15648
15649 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15650 DRM_ERROR("failed to write control word\n");
15651 return -EIO;
15652 }
15653
15654 return 0;
15655 }
15656
15657 struct intel_display_error_state {
15658
15659 u32 power_well_driver;
15660
15661 int num_transcoders;
15662
15663 struct intel_cursor_error_state {
15664 u32 control;
15665 u32 position;
15666 u32 base;
15667 u32 size;
15668 } cursor[I915_MAX_PIPES];
15669
15670 struct intel_pipe_error_state {
15671 bool power_domain_on;
15672 u32 source;
15673 u32 stat;
15674 } pipe[I915_MAX_PIPES];
15675
15676 struct intel_plane_error_state {
15677 u32 control;
15678 u32 stride;
15679 u32 size;
15680 u32 pos;
15681 u32 addr;
15682 u32 surface;
15683 u32 tile_offset;
15684 } plane[I915_MAX_PIPES];
15685
15686 struct intel_transcoder_error_state {
15687 bool power_domain_on;
15688 enum transcoder cpu_transcoder;
15689
15690 u32 conf;
15691
15692 u32 htotal;
15693 u32 hblank;
15694 u32 hsync;
15695 u32 vtotal;
15696 u32 vblank;
15697 u32 vsync;
15698 } transcoder[4];
15699 };
15700
15701 struct intel_display_error_state *
15702 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15703 {
15704 struct intel_display_error_state *error;
15705 int transcoders[] = {
15706 TRANSCODER_A,
15707 TRANSCODER_B,
15708 TRANSCODER_C,
15709 TRANSCODER_EDP,
15710 };
15711 int i;
15712
15713 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15714 return NULL;
15715
15716 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15717 if (error == NULL)
15718 return NULL;
15719
15720 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15721 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15722
15723 for_each_pipe(dev_priv, i) {
15724 error->pipe[i].power_domain_on =
15725 __intel_display_power_is_enabled(dev_priv,
15726 POWER_DOMAIN_PIPE(i));
15727 if (!error->pipe[i].power_domain_on)
15728 continue;
15729
15730 error->cursor[i].control = I915_READ(CURCNTR(i));
15731 error->cursor[i].position = I915_READ(CURPOS(i));
15732 error->cursor[i].base = I915_READ(CURBASE(i));
15733
15734 error->plane[i].control = I915_READ(DSPCNTR(i));
15735 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15736 if (INTEL_GEN(dev_priv) <= 3) {
15737 error->plane[i].size = I915_READ(DSPSIZE(i));
15738 error->plane[i].pos = I915_READ(DSPPOS(i));
15739 }
15740 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15741 error->plane[i].addr = I915_READ(DSPADDR(i));
15742 if (INTEL_GEN(dev_priv) >= 4) {
15743 error->plane[i].surface = I915_READ(DSPSURF(i));
15744 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15745 }
15746
15747 error->pipe[i].source = I915_READ(PIPESRC(i));
15748
15749 if (HAS_GMCH_DISPLAY(dev_priv))
15750 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15751 }
15752
15753 /* Note: this does not include DSI transcoders. */
15754 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15755 if (HAS_DDI(dev_priv))
15756 error->num_transcoders++; /* Account for eDP. */
15757
15758 for (i = 0; i < error->num_transcoders; i++) {
15759 enum transcoder cpu_transcoder = transcoders[i];
15760
15761 error->transcoder[i].power_domain_on =
15762 __intel_display_power_is_enabled(dev_priv,
15763 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15764 if (!error->transcoder[i].power_domain_on)
15765 continue;
15766
15767 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15768
15769 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15770 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15771 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15772 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15773 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15774 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15775 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15776 }
15777
15778 return error;
15779 }
15780
15781 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15782
15783 void
15784 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15785 struct drm_device *dev,
15786 struct intel_display_error_state *error)
15787 {
15788 struct drm_i915_private *dev_priv = dev->dev_private;
15789 int i;
15790
15791 if (!error)
15792 return;
15793
15794 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15795 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15796 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15797 error->power_well_driver);
15798 for_each_pipe(dev_priv, i) {
15799 err_printf(m, "Pipe [%d]:\n", i);
15800 err_printf(m, " Power: %s\n",
15801 onoff(error->pipe[i].power_domain_on));
15802 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15803 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15804
15805 err_printf(m, "Plane [%d]:\n", i);
15806 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15807 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15808 if (INTEL_INFO(dev)->gen <= 3) {
15809 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15810 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15811 }
15812 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15813 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15814 if (INTEL_INFO(dev)->gen >= 4) {
15815 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15816 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15817 }
15818
15819 err_printf(m, "Cursor [%d]:\n", i);
15820 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15821 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15822 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15823 }
15824
15825 for (i = 0; i < error->num_transcoders; i++) {
15826 err_printf(m, "CPU transcoder: %s\n",
15827 transcoder_name(error->transcoder[i].cpu_transcoder));
15828 err_printf(m, " Power: %s\n",
15829 onoff(error->transcoder[i].power_domain_on));
15830 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15831 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15832 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15833 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15834 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15835 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15836 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15837 }
15838 }
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