2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
32 #include "drm_crtc_helper.h"
33 #include "intel_drv.h"
38 #define DP_LINK_STATUS_SIZE 6
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41 #define DP_LINK_CONFIGURATION_SIZE 9
43 struct intel_dp_priv
{
46 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
48 uint8_t save_link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
54 struct intel_output
*intel_output
;
55 struct i2c_adapter adapter
;
56 struct i2c_algo_dp_aux_data algo
;
60 intel_dp_link_train(struct intel_output
*intel_output
, uint32_t DP
,
61 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
]);
64 intel_dp_link_down(struct intel_output
*intel_output
, uint32_t DP
);
67 intel_dp_max_lane_count(struct intel_output
*intel_output
)
69 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
70 int max_lane_count
= 4;
72 if (dp_priv
->dpcd
[0] >= 0x11) {
73 max_lane_count
= dp_priv
->dpcd
[2] & 0x1f;
74 switch (max_lane_count
) {
75 case 1: case 2: case 4:
81 return max_lane_count
;
85 intel_dp_max_link_bw(struct intel_output
*intel_output
)
87 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
88 int max_link_bw
= dp_priv
->dpcd
[1];
90 switch (max_link_bw
) {
95 max_link_bw
= DP_LINK_BW_1_62
;
102 intel_dp_link_clock(uint8_t link_bw
)
104 if (link_bw
== DP_LINK_BW_2_7
)
110 /* I think this is a fiction */
112 intel_dp_link_required(int pixel_clock
)
114 return pixel_clock
* 3;
118 intel_dp_mode_valid(struct drm_connector
*connector
,
119 struct drm_display_mode
*mode
)
121 struct intel_output
*intel_output
= to_intel_output(connector
);
122 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_output
));
123 int max_lanes
= intel_dp_max_lane_count(intel_output
);
125 if (intel_dp_link_required(mode
->clock
) > max_link_clock
* max_lanes
)
126 return MODE_CLOCK_HIGH
;
128 if (mode
->clock
< 10000)
129 return MODE_CLOCK_LOW
;
135 pack_aux(uint8_t *src
, int src_bytes
)
142 for (i
= 0; i
< src_bytes
; i
++)
143 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
148 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
153 for (i
= 0; i
< dst_bytes
; i
++)
154 dst
[i
] = src
>> ((3-i
) * 8);
157 /* hrawclock is 1/4 the FSB frequency */
159 intel_hrawclk(struct drm_device
*dev
)
161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
164 clkcfg
= I915_READ(CLKCFG
);
165 switch (clkcfg
& CLKCFG_FSB_MASK
) {
174 case CLKCFG_FSB_1067
:
176 case CLKCFG_FSB_1333
:
178 /* these two are just a guess; one of them might be right */
179 case CLKCFG_FSB_1600
:
180 case CLKCFG_FSB_1600_ALT
:
188 intel_dp_aux_ch(struct intel_output
*intel_output
,
189 uint8_t *send
, int send_bytes
,
190 uint8_t *recv
, int recv_size
)
192 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
193 uint32_t output_reg
= dp_priv
->output_reg
;
194 struct drm_device
*dev
= intel_output
->base
.dev
;
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 uint32_t ch_ctl
= output_reg
+ 0x10;
197 uint32_t ch_data
= ch_ctl
+ 4;
202 uint32_t aux_clock_divider
;
205 /* The clock divider is based off the hrawclk,
206 * and would like to run at 2MHz. So, take the
207 * hrawclk value and divide by 2 and use that
209 /* IGDNG: input clock fixed at 125Mhz, so aux_bit_clk always 62 */
211 aux_clock_divider
= 62;
213 aux_clock_divider
= intel_hrawclk(dev
) / 2;
215 /* Must try at least 3 times according to DP spec */
216 for (try = 0; try < 5; try++) {
217 /* Load the send data into the aux channel data registers */
218 for (i
= 0; i
< send_bytes
; i
+= 4) {
219 uint32_t d
= pack_aux(send
+ i
, send_bytes
- i
);;
221 I915_WRITE(ch_data
+ i
, d
);
224 ctl
= (DP_AUX_CH_CTL_SEND_BUSY
|
225 DP_AUX_CH_CTL_TIME_OUT_400us
|
226 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
227 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
228 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
230 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
231 DP_AUX_CH_CTL_RECEIVE_ERROR
);
233 /* Send the command and wait for it to complete */
234 I915_WRITE(ch_ctl
, ctl
);
235 (void) I915_READ(ch_ctl
);
238 status
= I915_READ(ch_ctl
);
239 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
243 /* Clear done status and any errors */
244 I915_WRITE(ch_ctl
, (status
|
246 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
247 DP_AUX_CH_CTL_RECEIVE_ERROR
));
248 (void) I915_READ(ch_ctl
);
249 if ((status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) == 0)
253 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
254 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
258 /* Check for timeout or receive error.
259 * Timeouts occur when the sink is not connected
261 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
262 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
266 /* Timeouts occur when the device isn't connected, so they're
267 * "normal" -- don't fill the kernel log with these */
268 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
269 DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status
);
273 /* Unload any bytes sent back from the other side */
274 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
275 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
277 if (recv_bytes
> recv_size
)
278 recv_bytes
= recv_size
;
280 for (i
= 0; i
< recv_bytes
; i
+= 4) {
281 uint32_t d
= I915_READ(ch_data
+ i
);
283 unpack_aux(d
, recv
+ i
, recv_bytes
- i
);
289 /* Write data to the aux channel in native mode */
291 intel_dp_aux_native_write(struct intel_output
*intel_output
,
292 uint16_t address
, uint8_t *send
, int send_bytes
)
301 msg
[0] = AUX_NATIVE_WRITE
<< 4;
302 msg
[1] = address
>> 8;
303 msg
[2] = address
& 0xff;
304 msg
[3] = send_bytes
- 1;
305 memcpy(&msg
[4], send
, send_bytes
);
306 msg_bytes
= send_bytes
+ 4;
308 ret
= intel_dp_aux_ch(intel_output
, msg
, msg_bytes
, &ack
, 1);
311 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
313 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
321 /* Write a single byte to the aux channel in native mode */
323 intel_dp_aux_native_write_1(struct intel_output
*intel_output
,
324 uint16_t address
, uint8_t byte
)
326 return intel_dp_aux_native_write(intel_output
, address
, &byte
, 1);
329 /* read bytes from a native aux channel */
331 intel_dp_aux_native_read(struct intel_output
*intel_output
,
332 uint16_t address
, uint8_t *recv
, int recv_bytes
)
341 msg
[0] = AUX_NATIVE_READ
<< 4;
342 msg
[1] = address
>> 8;
343 msg
[2] = address
& 0xff;
344 msg
[3] = recv_bytes
- 1;
347 reply_bytes
= recv_bytes
+ 1;
350 ret
= intel_dp_aux_ch(intel_output
, msg
, msg_bytes
,
357 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
358 memcpy(recv
, reply
+ 1, ret
- 1);
361 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
369 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
,
370 uint8_t *send
, int send_bytes
,
371 uint8_t *recv
, int recv_bytes
)
373 struct intel_dp_priv
*dp_priv
= container_of(adapter
,
374 struct intel_dp_priv
,
376 struct intel_output
*intel_output
= dp_priv
->intel_output
;
378 return intel_dp_aux_ch(intel_output
,
379 send
, send_bytes
, recv
, recv_bytes
);
383 intel_dp_i2c_init(struct intel_output
*intel_output
, const char *name
)
385 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
387 DRM_ERROR("i2c_init %s\n", name
);
388 dp_priv
->algo
.running
= false;
389 dp_priv
->algo
.address
= 0;
390 dp_priv
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
392 memset(&dp_priv
->adapter
, '\0', sizeof (dp_priv
->adapter
));
393 dp_priv
->adapter
.owner
= THIS_MODULE
;
394 dp_priv
->adapter
.class = I2C_CLASS_DDC
;
395 strncpy (dp_priv
->adapter
.name
, name
, sizeof(dp_priv
->adapter
.name
) - 1);
396 dp_priv
->adapter
.name
[sizeof(dp_priv
->adapter
.name
) - 1] = '\0';
397 dp_priv
->adapter
.algo_data
= &dp_priv
->algo
;
398 dp_priv
->adapter
.dev
.parent
= &intel_output
->base
.kdev
;
400 return i2c_dp_aux_add_bus(&dp_priv
->adapter
);
404 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
405 struct drm_display_mode
*adjusted_mode
)
407 struct intel_output
*intel_output
= enc_to_intel_output(encoder
);
408 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
409 int lane_count
, clock
;
410 int max_lane_count
= intel_dp_max_lane_count(intel_output
);
411 int max_clock
= intel_dp_max_link_bw(intel_output
) == DP_LINK_BW_2_7
? 1 : 0;
412 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
414 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
415 for (clock
= 0; clock
<= max_clock
; clock
++) {
416 int link_avail
= intel_dp_link_clock(bws
[clock
]) * lane_count
;
418 if (intel_dp_link_required(mode
->clock
) <= link_avail
) {
419 dp_priv
->link_bw
= bws
[clock
];
420 dp_priv
->lane_count
= lane_count
;
421 adjusted_mode
->clock
= intel_dp_link_clock(dp_priv
->link_bw
);
422 DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n",
423 dp_priv
->link_bw
, dp_priv
->lane_count
,
424 adjusted_mode
->clock
);
432 struct intel_dp_m_n
{
441 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
443 while (*num
> 0xffffff || *den
> 0xffffff) {
450 intel_dp_compute_m_n(int bytes_per_pixel
,
454 struct intel_dp_m_n
*m_n
)
457 m_n
->gmch_m
= pixel_clock
* bytes_per_pixel
;
458 m_n
->gmch_n
= link_clock
* nlanes
;
459 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
460 m_n
->link_m
= pixel_clock
;
461 m_n
->link_n
= link_clock
;
462 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
466 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
467 struct drm_display_mode
*adjusted_mode
)
469 struct drm_device
*dev
= crtc
->dev
;
470 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
471 struct drm_connector
*connector
;
472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
473 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
475 struct intel_dp_m_n m_n
;
478 * Find the lane count in the intel_output private
480 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
481 struct intel_output
*intel_output
= to_intel_output(connector
);
482 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
484 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
487 if (intel_output
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
488 lane_count
= dp_priv
->lane_count
;
494 * Compute the GMCH and Link ratios. The '3' here is
495 * the number of bytes_per_pixel post-LUT, which we always
496 * set up for 8-bits of R/G/B, or 3 bytes total.
498 intel_dp_compute_m_n(3, lane_count
,
499 mode
->clock
, adjusted_mode
->clock
, &m_n
);
502 if (intel_crtc
->pipe
== 0) {
503 I915_WRITE(TRANSA_DATA_M1
,
504 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
506 I915_WRITE(TRANSA_DATA_N1
, m_n
.gmch_n
);
507 I915_WRITE(TRANSA_DP_LINK_M1
, m_n
.link_m
);
508 I915_WRITE(TRANSA_DP_LINK_N1
, m_n
.link_n
);
510 I915_WRITE(TRANSB_DATA_M1
,
511 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
513 I915_WRITE(TRANSB_DATA_N1
, m_n
.gmch_n
);
514 I915_WRITE(TRANSB_DP_LINK_M1
, m_n
.link_m
);
515 I915_WRITE(TRANSB_DP_LINK_N1
, m_n
.link_n
);
518 if (intel_crtc
->pipe
== 0) {
519 I915_WRITE(PIPEA_GMCH_DATA_M
,
520 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
522 I915_WRITE(PIPEA_GMCH_DATA_N
,
524 I915_WRITE(PIPEA_DP_LINK_M
, m_n
.link_m
);
525 I915_WRITE(PIPEA_DP_LINK_N
, m_n
.link_n
);
527 I915_WRITE(PIPEB_GMCH_DATA_M
,
528 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
530 I915_WRITE(PIPEB_GMCH_DATA_N
,
532 I915_WRITE(PIPEB_DP_LINK_M
, m_n
.link_m
);
533 I915_WRITE(PIPEB_DP_LINK_N
, m_n
.link_n
);
539 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
540 struct drm_display_mode
*adjusted_mode
)
542 struct intel_output
*intel_output
= enc_to_intel_output(encoder
);
543 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
544 struct drm_crtc
*crtc
= intel_output
->enc
.crtc
;
545 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
547 dp_priv
->DP
= (DP_LINK_TRAIN_OFF
|
553 switch (dp_priv
->lane_count
) {
555 dp_priv
->DP
|= DP_PORT_WIDTH_1
;
558 dp_priv
->DP
|= DP_PORT_WIDTH_2
;
561 dp_priv
->DP
|= DP_PORT_WIDTH_4
;
564 if (dp_priv
->has_audio
)
565 dp_priv
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
567 memset(dp_priv
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
568 dp_priv
->link_configuration
[0] = dp_priv
->link_bw
;
569 dp_priv
->link_configuration
[1] = dp_priv
->lane_count
;
572 * Check for DPCD version > 1.1,
573 * enable enahanced frame stuff in that case
575 if (dp_priv
->dpcd
[0] >= 0x11) {
576 dp_priv
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
577 dp_priv
->DP
|= DP_ENHANCED_FRAMING
;
580 if (intel_crtc
->pipe
== 1)
581 dp_priv
->DP
|= DP_PIPEB_SELECT
;
586 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
588 struct intel_output
*intel_output
= enc_to_intel_output(encoder
);
589 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
590 struct drm_device
*dev
= intel_output
->base
.dev
;
591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
592 uint32_t dp_reg
= I915_READ(dp_priv
->output_reg
);
594 if (mode
!= DRM_MODE_DPMS_ON
) {
595 if (dp_reg
& DP_PORT_EN
)
596 intel_dp_link_down(intel_output
, dp_priv
->DP
);
598 if (!(dp_reg
& DP_PORT_EN
))
599 intel_dp_link_train(intel_output
, dp_priv
->DP
, dp_priv
->link_configuration
);
601 dp_priv
->dpms_mode
= mode
;
605 * Fetch AUX CH registers 0x202 - 0x207 which contain
606 * link status information
609 intel_dp_get_link_status(struct intel_output
*intel_output
,
610 uint8_t link_status
[DP_LINK_STATUS_SIZE
])
614 ret
= intel_dp_aux_native_read(intel_output
,
616 link_status
, DP_LINK_STATUS_SIZE
);
617 if (ret
!= DP_LINK_STATUS_SIZE
)
623 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
626 return link_status
[r
- DP_LANE0_1_STATUS
];
630 intel_dp_save(struct drm_connector
*connector
)
632 struct intel_output
*intel_output
= to_intel_output(connector
);
633 struct drm_device
*dev
= intel_output
->base
.dev
;
634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
635 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
637 dp_priv
->save_DP
= I915_READ(dp_priv
->output_reg
);
638 intel_dp_aux_native_read(intel_output
, DP_LINK_BW_SET
,
639 dp_priv
->save_link_configuration
,
640 sizeof (dp_priv
->save_link_configuration
));
644 intel_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
647 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
648 int s
= ((lane
& 1) ?
649 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
650 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
651 uint8_t l
= intel_dp_link_status(link_status
, i
);
653 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
657 intel_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
660 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
661 int s
= ((lane
& 1) ?
662 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
663 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
664 uint8_t l
= intel_dp_link_status(link_status
, i
);
666 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
671 static char *voltage_names
[] = {
672 "0.4V", "0.6V", "0.8V", "1.2V"
674 static char *pre_emph_names
[] = {
675 "0dB", "3.5dB", "6dB", "9.5dB"
677 static char *link_train_names
[] = {
678 "pattern 1", "pattern 2", "idle", "off"
683 * These are source-specific values; current Intel hardware supports
684 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
686 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
689 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
691 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
692 case DP_TRAIN_VOLTAGE_SWING_400
:
693 return DP_TRAIN_PRE_EMPHASIS_6
;
694 case DP_TRAIN_VOLTAGE_SWING_600
:
695 return DP_TRAIN_PRE_EMPHASIS_6
;
696 case DP_TRAIN_VOLTAGE_SWING_800
:
697 return DP_TRAIN_PRE_EMPHASIS_3_5
;
698 case DP_TRAIN_VOLTAGE_SWING_1200
:
700 return DP_TRAIN_PRE_EMPHASIS_0
;
705 intel_get_adjust_train(struct intel_output
*intel_output
,
706 uint8_t link_status
[DP_LINK_STATUS_SIZE
],
708 uint8_t train_set
[4])
714 for (lane
= 0; lane
< lane_count
; lane
++) {
715 uint8_t this_v
= intel_get_adjust_request_voltage(link_status
, lane
);
716 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(link_status
, lane
);
724 if (v
>= I830_DP_VOLTAGE_MAX
)
725 v
= I830_DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
727 if (p
>= intel_dp_pre_emphasis_max(v
))
728 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
730 for (lane
= 0; lane
< 4; lane
++)
731 train_set
[lane
] = v
| p
;
735 intel_dp_signal_levels(uint8_t train_set
, int lane_count
)
737 uint32_t signal_levels
= 0;
739 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
740 case DP_TRAIN_VOLTAGE_SWING_400
:
742 signal_levels
|= DP_VOLTAGE_0_4
;
744 case DP_TRAIN_VOLTAGE_SWING_600
:
745 signal_levels
|= DP_VOLTAGE_0_6
;
747 case DP_TRAIN_VOLTAGE_SWING_800
:
748 signal_levels
|= DP_VOLTAGE_0_8
;
750 case DP_TRAIN_VOLTAGE_SWING_1200
:
751 signal_levels
|= DP_VOLTAGE_1_2
;
754 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
755 case DP_TRAIN_PRE_EMPHASIS_0
:
757 signal_levels
|= DP_PRE_EMPHASIS_0
;
759 case DP_TRAIN_PRE_EMPHASIS_3_5
:
760 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
762 case DP_TRAIN_PRE_EMPHASIS_6
:
763 signal_levels
|= DP_PRE_EMPHASIS_6
;
765 case DP_TRAIN_PRE_EMPHASIS_9_5
:
766 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
769 return signal_levels
;
773 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
776 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
777 int s
= (lane
& 1) * 4;
778 uint8_t l
= intel_dp_link_status(link_status
, i
);
780 return (l
>> s
) & 0xf;
783 /* Check for clock recovery is done on all channels */
785 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
790 for (lane
= 0; lane
< lane_count
; lane
++) {
791 lane_status
= intel_get_lane_status(link_status
, lane
);
792 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
798 /* Check to see if channel eq is done on all channels */
799 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
800 DP_LANE_CHANNEL_EQ_DONE|\
801 DP_LANE_SYMBOL_LOCKED)
803 intel_channel_eq_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
809 lane_align
= intel_dp_link_status(link_status
,
810 DP_LANE_ALIGN_STATUS_UPDATED
);
811 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
813 for (lane
= 0; lane
< lane_count
; lane
++) {
814 lane_status
= intel_get_lane_status(link_status
, lane
);
815 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
822 intel_dp_set_link_train(struct intel_output
*intel_output
,
823 uint32_t dp_reg_value
,
824 uint8_t dp_train_pat
,
825 uint8_t train_set
[4],
828 struct drm_device
*dev
= intel_output
->base
.dev
;
829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
830 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
833 I915_WRITE(dp_priv
->output_reg
, dp_reg_value
);
834 POSTING_READ(dp_priv
->output_reg
);
836 intel_wait_for_vblank(dev
);
838 intel_dp_aux_native_write_1(intel_output
,
839 DP_TRAINING_PATTERN_SET
,
842 ret
= intel_dp_aux_native_write(intel_output
,
843 DP_TRAINING_LANE0_SET
, train_set
, 4);
851 intel_dp_link_train(struct intel_output
*intel_output
, uint32_t DP
,
852 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
])
854 struct drm_device
*dev
= intel_output
->base
.dev
;
855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
856 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
857 uint8_t train_set
[4];
858 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
861 bool clock_recovery
= false;
862 bool channel_eq
= false;
866 /* Write the link configuration data */
867 intel_dp_aux_native_write(intel_output
, 0x100,
868 link_configuration
, DP_LINK_CONFIGURATION_SIZE
);
871 DP
&= ~DP_LINK_TRAIN_MASK
;
872 memset(train_set
, 0, 4);
875 clock_recovery
= false;
877 /* Use train_set[0] to set the voltage and pre emphasis values */
878 uint32_t signal_levels
= intel_dp_signal_levels(train_set
[0], dp_priv
->lane_count
);
879 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
881 if (!intel_dp_set_link_train(intel_output
, DP
| DP_LINK_TRAIN_PAT_1
,
882 DP_TRAINING_PATTERN_1
, train_set
, first
))
885 /* Set training pattern 1 */
888 if (!intel_dp_get_link_status(intel_output
, link_status
))
891 if (intel_clock_recovery_ok(link_status
, dp_priv
->lane_count
)) {
892 clock_recovery
= true;
896 /* Check to see if we've tried the max voltage */
897 for (i
= 0; i
< dp_priv
->lane_count
; i
++)
898 if ((train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
900 if (i
== dp_priv
->lane_count
)
903 /* Check to see if we've tried the same voltage 5 times */
904 if ((train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
910 voltage
= train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
912 /* Compute new train_set as requested by target */
913 intel_get_adjust_train(intel_output
, link_status
, dp_priv
->lane_count
, train_set
);
916 /* channel equalization */
920 /* Use train_set[0] to set the voltage and pre emphasis values */
921 uint32_t signal_levels
= intel_dp_signal_levels(train_set
[0], dp_priv
->lane_count
);
922 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
924 /* channel eq pattern */
925 if (!intel_dp_set_link_train(intel_output
, DP
| DP_LINK_TRAIN_PAT_2
,
926 DP_TRAINING_PATTERN_2
, train_set
,
931 if (!intel_dp_get_link_status(intel_output
, link_status
))
934 if (intel_channel_eq_ok(link_status
, dp_priv
->lane_count
)) {
943 /* Compute new train_set as requested by target */
944 intel_get_adjust_train(intel_output
, link_status
, dp_priv
->lane_count
, train_set
);
948 I915_WRITE(dp_priv
->output_reg
, DP
| DP_LINK_TRAIN_OFF
);
949 POSTING_READ(dp_priv
->output_reg
);
950 intel_dp_aux_native_write_1(intel_output
,
951 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
955 intel_dp_link_down(struct intel_output
*intel_output
, uint32_t DP
)
957 struct drm_device
*dev
= intel_output
->base
.dev
;
958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
959 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
961 DP
&= ~DP_LINK_TRAIN_MASK
;
962 I915_WRITE(dp_priv
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
963 POSTING_READ(dp_priv
->output_reg
);
967 I915_WRITE(dp_priv
->output_reg
, DP
& ~DP_PORT_EN
);
968 POSTING_READ(dp_priv
->output_reg
);
972 intel_dp_restore(struct drm_connector
*connector
)
974 struct intel_output
*intel_output
= to_intel_output(connector
);
975 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
977 if (dp_priv
->save_DP
& DP_PORT_EN
)
978 intel_dp_link_train(intel_output
, dp_priv
->save_DP
, dp_priv
->save_link_configuration
);
980 intel_dp_link_down(intel_output
, dp_priv
->save_DP
);
984 * According to DP spec
987 * 2. Configure link according to Receiver Capabilities
988 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
989 * 4. Check link status on receipt of hot-plug interrupt
993 intel_dp_check_link_status(struct intel_output
*intel_output
)
995 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
996 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
998 if (!intel_output
->enc
.crtc
)
1001 if (!intel_dp_get_link_status(intel_output
, link_status
)) {
1002 intel_dp_link_down(intel_output
, dp_priv
->DP
);
1006 if (!intel_channel_eq_ok(link_status
, dp_priv
->lane_count
))
1007 intel_dp_link_train(intel_output
, dp_priv
->DP
, dp_priv
->link_configuration
);
1010 static enum drm_connector_status
1011 igdng_dp_detect(struct drm_connector
*connector
)
1013 struct intel_output
*intel_output
= to_intel_output(connector
);
1014 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
1015 enum drm_connector_status status
;
1017 status
= connector_status_disconnected
;
1018 if (intel_dp_aux_native_read(intel_output
,
1019 0x000, dp_priv
->dpcd
,
1020 sizeof (dp_priv
->dpcd
)) == sizeof (dp_priv
->dpcd
))
1022 if (dp_priv
->dpcd
[0] != 0)
1023 status
= connector_status_connected
;
1029 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1031 * \return true if DP port is connected.
1032 * \return false if DP port is disconnected.
1034 static enum drm_connector_status
1035 intel_dp_detect(struct drm_connector
*connector
)
1037 struct intel_output
*intel_output
= to_intel_output(connector
);
1038 struct drm_device
*dev
= intel_output
->base
.dev
;
1039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
1042 enum drm_connector_status status
;
1044 dp_priv
->has_audio
= false;
1047 return igdng_dp_detect(connector
);
1049 temp
= I915_READ(PORT_HOTPLUG_EN
);
1051 I915_WRITE(PORT_HOTPLUG_EN
,
1053 DPB_HOTPLUG_INT_EN
|
1054 DPC_HOTPLUG_INT_EN
|
1055 DPD_HOTPLUG_INT_EN
);
1057 POSTING_READ(PORT_HOTPLUG_EN
);
1059 switch (dp_priv
->output_reg
) {
1061 bit
= DPB_HOTPLUG_INT_STATUS
;
1064 bit
= DPC_HOTPLUG_INT_STATUS
;
1067 bit
= DPD_HOTPLUG_INT_STATUS
;
1070 return connector_status_unknown
;
1073 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1075 if ((temp
& bit
) == 0)
1076 return connector_status_disconnected
;
1078 status
= connector_status_disconnected
;
1079 if (intel_dp_aux_native_read(intel_output
,
1080 0x000, dp_priv
->dpcd
,
1081 sizeof (dp_priv
->dpcd
)) == sizeof (dp_priv
->dpcd
))
1083 if (dp_priv
->dpcd
[0] != 0)
1084 status
= connector_status_connected
;
1089 static int intel_dp_get_modes(struct drm_connector
*connector
)
1091 struct intel_output
*intel_output
= to_intel_output(connector
);
1093 /* We should parse the EDID data and find out if it has an audio sink
1096 return intel_ddc_get_modes(intel_output
);
1100 intel_dp_destroy (struct drm_connector
*connector
)
1102 struct intel_output
*intel_output
= to_intel_output(connector
);
1104 if (intel_output
->i2c_bus
)
1105 intel_i2c_destroy(intel_output
->i2c_bus
);
1106 drm_sysfs_connector_remove(connector
);
1107 drm_connector_cleanup(connector
);
1108 kfree(intel_output
);
1111 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
1112 .dpms
= intel_dp_dpms
,
1113 .mode_fixup
= intel_dp_mode_fixup
,
1114 .prepare
= intel_encoder_prepare
,
1115 .mode_set
= intel_dp_mode_set
,
1116 .commit
= intel_encoder_commit
,
1119 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
1120 .dpms
= drm_helper_connector_dpms
,
1121 .save
= intel_dp_save
,
1122 .restore
= intel_dp_restore
,
1123 .detect
= intel_dp_detect
,
1124 .fill_modes
= drm_helper_probe_single_connector_modes
,
1125 .destroy
= intel_dp_destroy
,
1128 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
1129 .get_modes
= intel_dp_get_modes
,
1130 .mode_valid
= intel_dp_mode_valid
,
1131 .best_encoder
= intel_best_encoder
,
1134 static void intel_dp_enc_destroy(struct drm_encoder
*encoder
)
1136 drm_encoder_cleanup(encoder
);
1139 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
1140 .destroy
= intel_dp_enc_destroy
,
1144 intel_dp_hot_plug(struct intel_output
*intel_output
)
1146 struct intel_dp_priv
*dp_priv
= intel_output
->dev_priv
;
1148 if (dp_priv
->dpms_mode
== DRM_MODE_DPMS_ON
)
1149 intel_dp_check_link_status(intel_output
);
1153 intel_dp_init(struct drm_device
*dev
, int output_reg
)
1155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1156 struct drm_connector
*connector
;
1157 struct intel_output
*intel_output
;
1158 struct intel_dp_priv
*dp_priv
;
1159 const char *name
= NULL
;
1161 intel_output
= kcalloc(sizeof(struct intel_output
) +
1162 sizeof(struct intel_dp_priv
), 1, GFP_KERNEL
);
1166 dp_priv
= (struct intel_dp_priv
*)(intel_output
+ 1);
1168 connector
= &intel_output
->base
;
1169 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
,
1170 DRM_MODE_CONNECTOR_DisplayPort
);
1171 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
1173 intel_output
->type
= INTEL_OUTPUT_DISPLAYPORT
;
1175 connector
->interlace_allowed
= true;
1176 connector
->doublescan_allowed
= 0;
1178 dp_priv
->intel_output
= intel_output
;
1179 dp_priv
->output_reg
= output_reg
;
1180 dp_priv
->has_audio
= false;
1181 dp_priv
->dpms_mode
= DRM_MODE_DPMS_ON
;
1182 intel_output
->dev_priv
= dp_priv
;
1184 drm_encoder_init(dev
, &intel_output
->enc
, &intel_dp_enc_funcs
,
1185 DRM_MODE_ENCODER_TMDS
);
1186 drm_encoder_helper_add(&intel_output
->enc
, &intel_dp_helper_funcs
);
1188 drm_mode_connector_attach_encoder(&intel_output
->base
,
1189 &intel_output
->enc
);
1190 drm_sysfs_connector_add(connector
);
1192 /* Set up the DDC bus. */
1193 switch (output_reg
) {
1208 intel_dp_i2c_init(intel_output
, name
);
1209 intel_output
->ddc_bus
= &dp_priv
->adapter
;
1210 intel_output
->hot_plug
= intel_dp_hot_plug
;
1212 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1213 * 0xd. Failure to do so will result in spurious interrupts being
1214 * generated on the port when a cable is not attached.
1216 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1217 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1218 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);