2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 /* Compliance test status bits */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
48 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
57 static const struct dp_link_dpll gen4_dpll
[] = {
59 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
61 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
64 static const struct dp_link_dpll pch_dpll
[] = {
66 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
68 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
71 static const struct dp_link_dpll vlv_dpll
[] = {
73 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
75 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
79 * CHV supports eDP 1.4 that have more link rates.
80 * Below only provides the fixed rate but exclude variable rate.
82 static const struct dp_link_dpll chv_dpll
[] = {
84 * CHV requires to program fractional division for m2.
85 * m2 is stored in fixed point format using formula below
86 * (m2_int << 22) | m2_fraction
88 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
89 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
90 { 270000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
92 { 540000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
96 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
97 324000, 432000, 540000 };
98 static const int skl_rates
[] = { 162000, 216000, 270000,
99 324000, 432000, 540000 };
100 static const int default_rates
[] = { 162000, 270000, 540000 };
103 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104 * @intel_dp: DP struct
106 * If a CPU or PCH DP output is attached to an eDP panel, this function
107 * will return true, and false otherwise.
109 static bool is_edp(struct intel_dp
*intel_dp
)
111 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
113 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
116 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
118 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
120 return intel_dig_port
->base
.base
.dev
;
123 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
125 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
128 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
129 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
130 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
131 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
132 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
134 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
136 static int intel_dp_num_rates(u8 link_bw_code
)
138 switch (link_bw_code
) {
140 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
142 case DP_LINK_BW_1_62
:
151 /* update sink rates from dpcd */
152 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
156 num_rates
= intel_dp_num_rates(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
158 for (i
= 0; i
< num_rates
; i
++)
159 intel_dp
->sink_rates
[i
] = default_rates
[i
];
161 intel_dp
->num_sink_rates
= num_rates
;
164 static int intel_dp_max_sink_rate(struct intel_dp
*intel_dp
)
166 return intel_dp
->sink_rates
[intel_dp
->num_sink_rates
- 1];
169 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
171 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
172 u8 source_max
, sink_max
;
174 source_max
= intel_dig_port
->max_lanes
;
175 sink_max
= intel_dp
->max_sink_lane_count
;
177 return min(source_max
, sink_max
);
181 intel_dp_link_required(int pixel_clock
, int bpp
)
183 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
184 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
191 * link rate that is generally expressed in Gbps. Since, 8 bits of data
192 * is transmitted every LS_Clk per lane, there is no need to account for
193 * the channel encoding that is done in the PHY layer here.
196 return max_link_clock
* max_lanes
;
200 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
202 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
203 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
204 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
205 int max_dotclk
= dev_priv
->max_dotclk_freq
;
208 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
210 if (type
!= DP_DS_PORT_TYPE_VGA
)
213 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
214 intel_dp
->downstream_ports
);
216 if (ds_max_dotclk
!= 0)
217 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
223 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
225 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
226 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
227 const int *source_rates
;
230 /* This should only be done once */
231 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
233 if (IS_GEN9_LP(dev_priv
)) {
234 source_rates
= bxt_rates
;
235 size
= ARRAY_SIZE(bxt_rates
);
236 } else if (IS_GEN9_BC(dev_priv
)) {
237 source_rates
= skl_rates
;
238 size
= ARRAY_SIZE(skl_rates
);
240 source_rates
= default_rates
;
241 size
= ARRAY_SIZE(default_rates
);
244 /* This depends on the fact that 5.4 is last value in the array */
245 if (!intel_dp_source_supports_hbr2(intel_dp
))
248 intel_dp
->source_rates
= source_rates
;
249 intel_dp
->num_source_rates
= size
;
252 static int intersect_rates(const int *source_rates
, int source_len
,
253 const int *sink_rates
, int sink_len
,
256 int i
= 0, j
= 0, k
= 0;
258 while (i
< source_len
&& j
< sink_len
) {
259 if (source_rates
[i
] == sink_rates
[j
]) {
260 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
262 common_rates
[k
] = source_rates
[i
];
266 } else if (source_rates
[i
] < sink_rates
[j
]) {
275 /* return index of rate in rates array, or -1 if not found */
276 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
280 for (i
= 0; i
< len
; i
++)
281 if (rate
== rates
[i
])
287 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
289 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
291 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
292 intel_dp
->num_source_rates
,
293 intel_dp
->sink_rates
,
294 intel_dp
->num_sink_rates
,
295 intel_dp
->common_rates
);
297 /* Paranoia, there should always be something in common. */
298 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
299 intel_dp
->common_rates
[0] = default_rates
[0];
300 intel_dp
->num_common_rates
= 1;
304 /* get length of common rates potentially limited by max_rate */
305 static int intel_dp_common_len_rate_limit(struct intel_dp
*intel_dp
,
308 const int *common_rates
= intel_dp
->common_rates
;
309 int i
, common_len
= intel_dp
->num_common_rates
;
311 /* Limit results by potentially reduced max rate */
312 for (i
= 0; i
< common_len
; i
++) {
313 if (common_rates
[common_len
- i
- 1] <= max_rate
)
314 return common_len
- i
;
320 static int intel_dp_link_rate_index(struct intel_dp
*intel_dp
, int link_rate
)
324 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
325 intel_dp
->max_sink_link_rate
);
327 return intel_dp_rate_index(intel_dp
->common_rates
, common_len
, link_rate
);
330 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
331 int link_rate
, uint8_t lane_count
)
333 const int *common_rates
= intel_dp
->common_rates
;
336 link_rate_index
= intel_dp_link_rate_index(intel_dp
, link_rate
);
337 if (link_rate_index
> 0) {
338 intel_dp
->max_sink_link_rate
= common_rates
[link_rate_index
- 1];
339 intel_dp
->max_sink_lane_count
= lane_count
;
340 } else if (lane_count
> 1) {
341 intel_dp
->max_sink_link_rate
= intel_dp_max_sink_rate(intel_dp
);
342 intel_dp
->max_sink_lane_count
= lane_count
>> 1;
344 DRM_ERROR("Link Training Unsuccessful\n");
351 static enum drm_mode_status
352 intel_dp_mode_valid(struct drm_connector
*connector
,
353 struct drm_display_mode
*mode
)
355 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
356 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
357 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
358 int target_clock
= mode
->clock
;
359 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
362 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
364 if (is_edp(intel_dp
) && fixed_mode
) {
365 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
368 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
371 target_clock
= fixed_mode
->clock
;
374 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
375 max_lanes
= intel_dp_max_lane_count(intel_dp
);
377 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
378 mode_rate
= intel_dp_link_required(target_clock
, 18);
380 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
381 return MODE_CLOCK_HIGH
;
383 if (mode
->clock
< 10000)
384 return MODE_CLOCK_LOW
;
386 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
387 return MODE_H_ILLEGAL
;
392 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
399 for (i
= 0; i
< src_bytes
; i
++)
400 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
404 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
409 for (i
= 0; i
< dst_bytes
; i
++)
410 dst
[i
] = src
>> ((3-i
) * 8);
414 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
415 struct intel_dp
*intel_dp
);
417 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
418 struct intel_dp
*intel_dp
,
419 bool force_disable_vdd
);
421 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
423 static void pps_lock(struct intel_dp
*intel_dp
)
425 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
426 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
427 struct drm_device
*dev
= encoder
->base
.dev
;
428 struct drm_i915_private
*dev_priv
= to_i915(dev
);
431 * See vlv_power_sequencer_reset() why we need
432 * a power domain reference here.
434 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
436 mutex_lock(&dev_priv
->pps_mutex
);
439 static void pps_unlock(struct intel_dp
*intel_dp
)
441 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
442 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
443 struct drm_device
*dev
= encoder
->base
.dev
;
444 struct drm_i915_private
*dev_priv
= to_i915(dev
);
446 mutex_unlock(&dev_priv
->pps_mutex
);
448 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
452 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
454 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
455 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
456 enum pipe pipe
= intel_dp
->pps_pipe
;
457 bool pll_enabled
, release_cl_override
= false;
458 enum dpio_phy phy
= DPIO_PHY(pipe
);
459 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
462 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
463 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
464 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
467 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
468 pipe_name(pipe
), port_name(intel_dig_port
->port
));
470 /* Preserve the BIOS-computed detected bit. This is
471 * supposed to be read-only.
473 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
474 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
475 DP
|= DP_PORT_WIDTH(1);
476 DP
|= DP_LINK_TRAIN_PAT_1
;
478 if (IS_CHERRYVIEW(dev_priv
))
479 DP
|= DP_PIPE_SELECT_CHV(pipe
);
480 else if (pipe
== PIPE_B
)
481 DP
|= DP_PIPEB_SELECT
;
483 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
486 * The DPLL for the pipe must be enabled for this to work.
487 * So enable temporarily it if it's not already enabled.
490 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
491 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
493 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
494 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
495 DRM_ERROR("Failed to force on pll for pipe %c!\n",
502 * Similar magic as in intel_dp_enable_port().
503 * We _must_ do this port enable + disable trick
504 * to make this power seqeuencer lock onto the port.
505 * Otherwise even VDD force bit won't work.
507 I915_WRITE(intel_dp
->output_reg
, DP
);
508 POSTING_READ(intel_dp
->output_reg
);
510 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
511 POSTING_READ(intel_dp
->output_reg
);
513 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
514 POSTING_READ(intel_dp
->output_reg
);
517 vlv_force_pll_off(dev_priv
, pipe
);
519 if (release_cl_override
)
520 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
524 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
526 struct intel_encoder
*encoder
;
527 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
530 * We don't have power sequencer currently.
531 * Pick one that's not used by other ports.
533 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
534 struct intel_dp
*intel_dp
;
536 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
537 encoder
->type
!= INTEL_OUTPUT_EDP
)
540 intel_dp
= enc_to_intel_dp(&encoder
->base
);
542 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
543 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
544 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
546 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
547 pipes
&= ~(1 << intel_dp
->pps_pipe
);
549 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
551 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
552 pipes
&= ~(1 << intel_dp
->active_pipe
);
559 return ffs(pipes
) - 1;
563 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
565 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
566 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
567 struct drm_i915_private
*dev_priv
= to_i915(dev
);
570 lockdep_assert_held(&dev_priv
->pps_mutex
);
572 /* We should never land here with regular DP ports */
573 WARN_ON(!is_edp(intel_dp
));
575 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
576 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
578 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
579 return intel_dp
->pps_pipe
;
581 pipe
= vlv_find_free_pps(dev_priv
);
584 * Didn't find one. This should not happen since there
585 * are two power sequencers and up to two eDP ports.
587 if (WARN_ON(pipe
== INVALID_PIPE
))
590 vlv_steal_power_sequencer(dev
, pipe
);
591 intel_dp
->pps_pipe
= pipe
;
593 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
594 pipe_name(intel_dp
->pps_pipe
),
595 port_name(intel_dig_port
->port
));
597 /* init power sequencer on this pipe and port */
598 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
599 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
602 * Even vdd force doesn't work until we've made
603 * the power sequencer lock in on the port.
605 vlv_power_sequencer_kick(intel_dp
);
607 return intel_dp
->pps_pipe
;
611 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
613 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
614 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
615 struct drm_i915_private
*dev_priv
= to_i915(dev
);
617 lockdep_assert_held(&dev_priv
->pps_mutex
);
619 /* We should never land here with regular DP ports */
620 WARN_ON(!is_edp(intel_dp
));
623 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
624 * mapping needs to be retrieved from VBT, for now just hard-code to
625 * use instance #0 always.
627 if (!intel_dp
->pps_reset
)
630 intel_dp
->pps_reset
= false;
633 * Only the HW needs to be reprogrammed, the SW state is fixed and
634 * has been setup during connector init.
636 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
641 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
644 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
647 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
650 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
653 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
656 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
663 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
665 vlv_pipe_check pipe_check
)
669 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
670 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
671 PANEL_PORT_SELECT_MASK
;
673 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
676 if (!pipe_check(dev_priv
, pipe
))
686 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
688 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
689 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
690 struct drm_i915_private
*dev_priv
= to_i915(dev
);
691 enum port port
= intel_dig_port
->port
;
693 lockdep_assert_held(&dev_priv
->pps_mutex
);
695 /* try to find a pipe with this port selected */
696 /* first pick one where the panel is on */
697 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
699 /* didn't find one? pick one where vdd is on */
700 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
701 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
702 vlv_pipe_has_vdd_on
);
703 /* didn't find one? pick one with just the correct port */
704 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
705 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
708 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
709 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
710 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
715 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
716 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
718 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
719 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
722 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
724 struct drm_device
*dev
= &dev_priv
->drm
;
725 struct intel_encoder
*encoder
;
727 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
728 !IS_GEN9_LP(dev_priv
)))
732 * We can't grab pps_mutex here due to deadlock with power_domain
733 * mutex when power_domain functions are called while holding pps_mutex.
734 * That also means that in order to use pps_pipe the code needs to
735 * hold both a power domain reference and pps_mutex, and the power domain
736 * reference get/put must be done while _not_ holding pps_mutex.
737 * pps_{lock,unlock}() do these steps in the correct order, so one
738 * should use them always.
741 for_each_intel_encoder(dev
, encoder
) {
742 struct intel_dp
*intel_dp
;
744 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
745 encoder
->type
!= INTEL_OUTPUT_EDP
)
748 intel_dp
= enc_to_intel_dp(&encoder
->base
);
750 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
752 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
755 if (IS_GEN9_LP(dev_priv
))
756 intel_dp
->pps_reset
= true;
758 intel_dp
->pps_pipe
= INVALID_PIPE
;
762 struct pps_registers
{
770 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
771 struct intel_dp
*intel_dp
,
772 struct pps_registers
*regs
)
776 memset(regs
, 0, sizeof(*regs
));
778 if (IS_GEN9_LP(dev_priv
))
779 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
780 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
781 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
783 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
784 regs
->pp_stat
= PP_STATUS(pps_idx
);
785 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
786 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
787 if (!IS_GEN9_LP(dev_priv
))
788 regs
->pp_div
= PP_DIVISOR(pps_idx
);
792 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
794 struct pps_registers regs
;
796 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
803 _pp_stat_reg(struct intel_dp
*intel_dp
)
805 struct pps_registers regs
;
807 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
813 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
814 This function only applicable when panel PM state is not to be tracked */
815 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
818 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
820 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
821 struct drm_i915_private
*dev_priv
= to_i915(dev
);
823 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
828 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
829 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
830 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
833 pp_ctrl_reg
= PP_CONTROL(pipe
);
834 pp_div_reg
= PP_DIVISOR(pipe
);
835 pp_div
= I915_READ(pp_div_reg
);
836 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
838 /* 0x1F write to PP_DIV_REG sets max cycle delay */
839 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
840 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
841 msleep(intel_dp
->panel_power_cycle_delay
);
844 pps_unlock(intel_dp
);
849 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
851 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
852 struct drm_i915_private
*dev_priv
= to_i915(dev
);
854 lockdep_assert_held(&dev_priv
->pps_mutex
);
856 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
857 intel_dp
->pps_pipe
== INVALID_PIPE
)
860 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
863 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
865 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
866 struct drm_i915_private
*dev_priv
= to_i915(dev
);
868 lockdep_assert_held(&dev_priv
->pps_mutex
);
870 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
871 intel_dp
->pps_pipe
== INVALID_PIPE
)
874 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
878 intel_dp_check_edp(struct intel_dp
*intel_dp
)
880 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
881 struct drm_i915_private
*dev_priv
= to_i915(dev
);
883 if (!is_edp(intel_dp
))
886 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
887 WARN(1, "eDP powered off while attempting aux channel communication.\n");
888 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
889 I915_READ(_pp_stat_reg(intel_dp
)),
890 I915_READ(_pp_ctrl_reg(intel_dp
)));
895 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
897 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
898 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
899 struct drm_i915_private
*dev_priv
= to_i915(dev
);
900 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
904 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
906 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
907 msecs_to_jiffies_timeout(10));
909 done
= wait_for(C
, 10) == 0;
911 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
918 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
920 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
921 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
927 * The clock divider is based off the hrawclk, and would like to run at
928 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
930 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
933 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
935 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
936 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
942 * The clock divider is based off the cdclk or PCH rawclk, and would
943 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
944 * divide by 2000 and use that
946 if (intel_dig_port
->port
== PORT_A
)
947 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
949 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
952 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
954 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
955 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
957 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
958 /* Workaround for non-ULT HSW */
966 return ilk_get_aux_clock_divider(intel_dp
, index
);
969 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
972 * SKL doesn't need us to program the AUX clock divider (Hardware will
973 * derive the clock from CDCLK automatically). We still implement the
974 * get_aux_clock_divider vfunc to plug-in into the existing code.
976 return index
? 0 : 1;
979 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
982 uint32_t aux_clock_divider
)
984 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
985 struct drm_i915_private
*dev_priv
=
986 to_i915(intel_dig_port
->base
.base
.dev
);
987 uint32_t precharge
, timeout
;
989 if (IS_GEN6(dev_priv
))
994 if (IS_BROADWELL(dev_priv
) && intel_dig_port
->port
== PORT_A
)
995 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
997 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
999 return DP_AUX_CH_CTL_SEND_BUSY
|
1000 DP_AUX_CH_CTL_DONE
|
1001 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1002 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1004 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1005 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1006 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1007 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1010 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1015 return DP_AUX_CH_CTL_SEND_BUSY
|
1016 DP_AUX_CH_CTL_DONE
|
1017 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1018 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1019 DP_AUX_CH_CTL_TIME_OUT_1600us
|
1020 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1021 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1022 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1023 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1027 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
1028 const uint8_t *send
, int send_bytes
,
1029 uint8_t *recv
, int recv_size
)
1031 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1032 struct drm_i915_private
*dev_priv
=
1033 to_i915(intel_dig_port
->base
.base
.dev
);
1034 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
1035 uint32_t aux_clock_divider
;
1036 int i
, ret
, recv_bytes
;
1039 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1045 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1046 * In such cases we want to leave VDD enabled and it's up to upper layers
1047 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1050 vdd
= edp_panel_vdd_on(intel_dp
);
1052 /* dp aux is extremely sensitive to irq latency, hence request the
1053 * lowest possible wakeup latency and so prevent the cpu from going into
1054 * deep sleep states.
1056 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1058 intel_dp_check_edp(intel_dp
);
1060 /* Try to wait for any previous AUX channel activity */
1061 for (try = 0; try < 3; try++) {
1062 status
= I915_READ_NOTRACE(ch_ctl
);
1063 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1069 static u32 last_status
= -1;
1070 const u32 status
= I915_READ(ch_ctl
);
1072 if (status
!= last_status
) {
1073 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1075 last_status
= status
;
1082 /* Only 5 data registers! */
1083 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1088 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1089 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1094 /* Must try at least 3 times according to DP spec */
1095 for (try = 0; try < 5; try++) {
1096 /* Load the send data into the aux channel data registers */
1097 for (i
= 0; i
< send_bytes
; i
+= 4)
1098 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
1099 intel_dp_pack_aux(send
+ i
,
1102 /* Send the command and wait for it to complete */
1103 I915_WRITE(ch_ctl
, send_ctl
);
1105 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1107 /* Clear done status and any errors */
1110 DP_AUX_CH_CTL_DONE
|
1111 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1112 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1114 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1117 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1118 * 400us delay required for errors and timeouts
1119 * Timeout errors from the HW already meet this
1120 * requirement so skip to next iteration
1122 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1123 usleep_range(400, 500);
1126 if (status
& DP_AUX_CH_CTL_DONE
)
1131 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1132 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1138 /* Check for timeout or receive error.
1139 * Timeouts occur when the sink is not connected
1141 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1142 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1147 /* Timeouts occur when the device isn't connected, so they're
1148 * "normal" -- don't fill the kernel log with these */
1149 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1150 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1155 /* Unload any bytes sent back from the other side */
1156 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1157 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1160 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1161 * We have no idea of what happened so we return -EBUSY so
1162 * drm layer takes care for the necessary retries.
1164 if (recv_bytes
== 0 || recv_bytes
> 20) {
1165 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1168 * FIXME: This patch was created on top of a series that
1169 * organize the retries at drm level. There EBUSY should
1170 * also take care for 1ms wait before retrying.
1171 * That aux retries re-org is still needed and after that is
1172 * merged we remove this sleep from here.
1174 usleep_range(1000, 1500);
1179 if (recv_bytes
> recv_size
)
1180 recv_bytes
= recv_size
;
1182 for (i
= 0; i
< recv_bytes
; i
+= 4)
1183 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1184 recv
+ i
, recv_bytes
- i
);
1188 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1191 edp_panel_vdd_off(intel_dp
, false);
1193 pps_unlock(intel_dp
);
1198 #define BARE_ADDRESS_SIZE 3
1199 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1201 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1203 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1204 uint8_t txbuf
[20], rxbuf
[20];
1205 size_t txsize
, rxsize
;
1208 txbuf
[0] = (msg
->request
<< 4) |
1209 ((msg
->address
>> 16) & 0xf);
1210 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1211 txbuf
[2] = msg
->address
& 0xff;
1212 txbuf
[3] = msg
->size
- 1;
1214 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1215 case DP_AUX_NATIVE_WRITE
:
1216 case DP_AUX_I2C_WRITE
:
1217 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1218 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1219 rxsize
= 2; /* 0 or 1 data bytes */
1221 if (WARN_ON(txsize
> 20))
1224 WARN_ON(!msg
->buffer
!= !msg
->size
);
1227 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1229 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1231 msg
->reply
= rxbuf
[0] >> 4;
1234 /* Number of bytes written in a short write. */
1235 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1237 /* Return payload size. */
1243 case DP_AUX_NATIVE_READ
:
1244 case DP_AUX_I2C_READ
:
1245 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1246 rxsize
= msg
->size
+ 1;
1248 if (WARN_ON(rxsize
> 20))
1251 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1253 msg
->reply
= rxbuf
[0] >> 4;
1255 * Assume happy day, and copy the data. The caller is
1256 * expected to check msg->reply before touching it.
1258 * Return payload size.
1261 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1273 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1276 const struct ddi_vbt_port_info
*info
=
1277 &dev_priv
->vbt
.ddi_port_info
[port
];
1280 if (!info
->alternate_aux_channel
) {
1281 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1282 port_name(port
), port_name(port
));
1286 switch (info
->alternate_aux_channel
) {
1300 MISSING_CASE(info
->alternate_aux_channel
);
1305 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1306 port_name(aux_port
), port_name(port
));
1311 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1318 return DP_AUX_CH_CTL(port
);
1321 return DP_AUX_CH_CTL(PORT_B
);
1325 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1326 enum port port
, int index
)
1332 return DP_AUX_CH_DATA(port
, index
);
1335 return DP_AUX_CH_DATA(PORT_B
, index
);
1339 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1344 return DP_AUX_CH_CTL(port
);
1348 return PCH_DP_AUX_CH_CTL(port
);
1351 return DP_AUX_CH_CTL(PORT_A
);
1355 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1356 enum port port
, int index
)
1360 return DP_AUX_CH_DATA(port
, index
);
1364 return PCH_DP_AUX_CH_DATA(port
, index
);
1367 return DP_AUX_CH_DATA(PORT_A
, index
);
1371 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1379 return DP_AUX_CH_CTL(port
);
1382 return DP_AUX_CH_CTL(PORT_A
);
1386 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1387 enum port port
, int index
)
1394 return DP_AUX_CH_DATA(port
, index
);
1397 return DP_AUX_CH_DATA(PORT_A
, index
);
1401 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1404 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1405 return skl_aux_ctl_reg(dev_priv
, port
);
1406 else if (HAS_PCH_SPLIT(dev_priv
))
1407 return ilk_aux_ctl_reg(dev_priv
, port
);
1409 return g4x_aux_ctl_reg(dev_priv
, port
);
1412 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1413 enum port port
, int index
)
1415 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1416 return skl_aux_data_reg(dev_priv
, port
, index
);
1417 else if (HAS_PCH_SPLIT(dev_priv
))
1418 return ilk_aux_data_reg(dev_priv
, port
, index
);
1420 return g4x_aux_data_reg(dev_priv
, port
, index
);
1423 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1425 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1426 enum port port
= intel_aux_port(dev_priv
,
1427 dp_to_dig_port(intel_dp
)->port
);
1430 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1431 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1432 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1436 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1438 kfree(intel_dp
->aux
.name
);
1442 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1444 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1445 enum port port
= intel_dig_port
->port
;
1447 intel_aux_reg_init(intel_dp
);
1448 drm_dp_aux_init(&intel_dp
->aux
);
1450 /* Failure to allocate our preferred name is not critical */
1451 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1452 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1455 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1457 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1458 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1460 if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
1461 IS_BROADWELL(dev_priv
) || (INTEL_GEN(dev_priv
) >= 9))
1468 intel_dp_set_clock(struct intel_encoder
*encoder
,
1469 struct intel_crtc_state
*pipe_config
)
1471 struct drm_device
*dev
= encoder
->base
.dev
;
1472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1473 const struct dp_link_dpll
*divisor
= NULL
;
1476 if (IS_G4X(dev_priv
)) {
1477 divisor
= gen4_dpll
;
1478 count
= ARRAY_SIZE(gen4_dpll
);
1479 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1481 count
= ARRAY_SIZE(pch_dpll
);
1482 } else if (IS_CHERRYVIEW(dev_priv
)) {
1484 count
= ARRAY_SIZE(chv_dpll
);
1485 } else if (IS_VALLEYVIEW(dev_priv
)) {
1487 count
= ARRAY_SIZE(vlv_dpll
);
1490 if (divisor
&& count
) {
1491 for (i
= 0; i
< count
; i
++) {
1492 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1493 pipe_config
->dpll
= divisor
[i
].dpll
;
1494 pipe_config
->clock_set
= true;
1501 static void snprintf_int_array(char *str
, size_t len
,
1502 const int *array
, int nelem
)
1508 for (i
= 0; i
< nelem
; i
++) {
1509 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1517 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1519 char str
[128]; /* FIXME: too big for stack? */
1521 if ((drm_debug
& DRM_UT_KMS
) == 0)
1524 snprintf_int_array(str
, sizeof(str
),
1525 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1526 DRM_DEBUG_KMS("source rates: %s\n", str
);
1528 snprintf_int_array(str
, sizeof(str
),
1529 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1530 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1532 snprintf_int_array(str
, sizeof(str
),
1533 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1534 DRM_DEBUG_KMS("common rates: %s\n", str
);
1538 __intel_dp_read_desc(struct intel_dp
*intel_dp
, struct intel_dp_desc
*desc
)
1540 u32 base
= drm_dp_is_branch(intel_dp
->dpcd
) ? DP_BRANCH_OUI
:
1543 return drm_dp_dpcd_read(&intel_dp
->aux
, base
, desc
, sizeof(*desc
)) ==
1547 bool intel_dp_read_desc(struct intel_dp
*intel_dp
)
1549 struct intel_dp_desc
*desc
= &intel_dp
->desc
;
1550 bool oui_sup
= intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] &
1554 if (!__intel_dp_read_desc(intel_dp
, desc
))
1557 dev_id_len
= strnlen(desc
->device_id
, sizeof(desc
->device_id
));
1558 DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1559 drm_dp_is_branch(intel_dp
->dpcd
) ? "branch" : "sink",
1560 (int)sizeof(desc
->oui
), desc
->oui
, oui_sup
? "" : "(NS)",
1561 dev_id_len
, desc
->device_id
,
1562 desc
->hw_rev
>> 4, desc
->hw_rev
& 0xf,
1563 desc
->sw_major_rev
, desc
->sw_minor_rev
);
1569 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1573 len
= intel_dp_common_len_rate_limit(intel_dp
,
1574 intel_dp
->max_sink_link_rate
);
1575 if (WARN_ON(len
<= 0))
1578 return intel_dp
->common_rates
[len
- 1];
1581 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1583 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1584 intel_dp
->num_sink_rates
, rate
);
1592 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1593 uint8_t *link_bw
, uint8_t *rate_select
)
1595 /* eDP 1.4 rate select method. */
1596 if (intel_dp
->use_rate_select
) {
1599 intel_dp_rate_select(intel_dp
, port_clock
);
1601 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1606 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1607 struct intel_crtc_state
*pipe_config
)
1611 bpp
= pipe_config
->pipe_bpp
;
1612 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1615 bpp
= min(bpp
, 3*bpc
);
1617 /* For DP Compliance we override the computed bpp for the pipe */
1618 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1619 pipe_config
->pipe_bpp
= 3*intel_dp
->compliance
.test_data
.bpc
;
1620 pipe_config
->dither_force_disable
= pipe_config
->pipe_bpp
== 6*3;
1621 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1622 pipe_config
->pipe_bpp
);
1628 intel_dp_compute_config(struct intel_encoder
*encoder
,
1629 struct intel_crtc_state
*pipe_config
,
1630 struct drm_connector_state
*conn_state
)
1632 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1633 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1634 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1635 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1636 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1637 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1638 int lane_count
, clock
;
1639 int min_lane_count
= 1;
1640 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1641 /* Conveniently, the link BW constants become indices with a shift...*/
1644 int link_rate_index
;
1646 int link_avail
, link_clock
;
1648 uint8_t link_bw
, rate_select
;
1650 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1651 intel_dp
->max_sink_link_rate
);
1653 /* No common link rates between source and sink */
1654 WARN_ON(common_len
<= 0);
1656 max_clock
= common_len
- 1;
1658 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1659 pipe_config
->has_pch_encoder
= true;
1661 pipe_config
->has_drrs
= false;
1662 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1664 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1665 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1668 if (INTEL_GEN(dev_priv
) >= 9) {
1670 ret
= skl_update_scaler_crtc(pipe_config
);
1675 if (HAS_GMCH_DISPLAY(dev_priv
))
1676 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1677 intel_connector
->panel
.fitting_mode
);
1679 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1680 intel_connector
->panel
.fitting_mode
);
1683 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1686 /* Use values requested by Compliance Test Request */
1687 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1688 link_rate_index
= intel_dp_link_rate_index(intel_dp
,
1689 intel_dp
->compliance
.test_link_rate
);
1690 if (link_rate_index
>= 0)
1691 min_clock
= max_clock
= link_rate_index
;
1692 min_lane_count
= max_lane_count
= intel_dp
->compliance
.test_lane_count
;
1694 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1695 "max bw %d pixel clock %iKHz\n",
1696 max_lane_count
, intel_dp
->common_rates
[max_clock
],
1697 adjusted_mode
->crtc_clock
);
1699 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1700 * bpc in between. */
1701 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1702 if (is_edp(intel_dp
)) {
1704 /* Get bpp from vbt only for panels that dont have bpp in edid */
1705 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1706 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1707 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1708 dev_priv
->vbt
.edp
.bpp
);
1709 bpp
= dev_priv
->vbt
.edp
.bpp
;
1713 * Use the maximum clock and number of lanes the eDP panel
1714 * advertizes being capable of. The panels are generally
1715 * designed to support only a single clock and lane
1716 * configuration, and typically these values correspond to the
1717 * native resolution of the panel.
1719 min_lane_count
= max_lane_count
;
1720 min_clock
= max_clock
;
1723 for (; bpp
>= 6*3; bpp
-= 2*3) {
1724 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1727 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1728 for (lane_count
= min_lane_count
;
1729 lane_count
<= max_lane_count
;
1732 link_clock
= intel_dp
->common_rates
[clock
];
1733 link_avail
= intel_dp_max_data_rate(link_clock
,
1736 if (mode_rate
<= link_avail
) {
1746 if (intel_dp
->color_range_auto
) {
1749 * CEA-861-E - 5.1 Default Encoding Parameters
1750 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1752 pipe_config
->limited_color_range
=
1754 drm_default_rgb_quant_range(adjusted_mode
) ==
1755 HDMI_QUANTIZATION_RANGE_LIMITED
;
1757 pipe_config
->limited_color_range
=
1758 intel_dp
->limited_color_range
;
1761 pipe_config
->lane_count
= lane_count
;
1763 pipe_config
->pipe_bpp
= bpp
;
1764 pipe_config
->port_clock
= intel_dp
->common_rates
[clock
];
1766 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1767 &link_bw
, &rate_select
);
1769 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1770 link_bw
, rate_select
, pipe_config
->lane_count
,
1771 pipe_config
->port_clock
, bpp
);
1772 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1773 mode_rate
, link_avail
);
1775 intel_link_compute_m_n(bpp
, lane_count
,
1776 adjusted_mode
->crtc_clock
,
1777 pipe_config
->port_clock
,
1778 &pipe_config
->dp_m_n
);
1780 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1781 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1782 pipe_config
->has_drrs
= true;
1783 intel_link_compute_m_n(bpp
, lane_count
,
1784 intel_connector
->panel
.downclock_mode
->clock
,
1785 pipe_config
->port_clock
,
1786 &pipe_config
->dp_m2_n2
);
1790 * DPLL0 VCO may need to be adjusted to get the correct
1791 * clock for eDP. This will affect cdclk as well.
1793 if (is_edp(intel_dp
) && IS_GEN9_BC(dev_priv
)) {
1796 switch (pipe_config
->port_clock
/ 2) {
1806 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk
.logical
.vco
= vco
;
1809 if (!HAS_DDI(dev_priv
))
1810 intel_dp_set_clock(encoder
, pipe_config
);
1815 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1816 int link_rate
, uint8_t lane_count
,
1819 intel_dp
->link_rate
= link_rate
;
1820 intel_dp
->lane_count
= lane_count
;
1821 intel_dp
->link_mst
= link_mst
;
1824 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1825 struct intel_crtc_state
*pipe_config
)
1827 struct drm_device
*dev
= encoder
->base
.dev
;
1828 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1829 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1830 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1831 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1832 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1834 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1835 pipe_config
->lane_count
,
1836 intel_crtc_has_type(pipe_config
,
1837 INTEL_OUTPUT_DP_MST
));
1840 * There are four kinds of DP registers:
1847 * IBX PCH and CPU are the same for almost everything,
1848 * except that the CPU DP PLL is configured in this
1851 * CPT PCH is quite different, having many bits moved
1852 * to the TRANS_DP_CTL register instead. That
1853 * configuration happens (oddly) in ironlake_pch_enable
1856 /* Preserve the BIOS-computed detected bit. This is
1857 * supposed to be read-only.
1859 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1861 /* Handle DP bits in common between all three register formats */
1862 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1863 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1865 /* Split out the IBX/CPU vs CPT settings */
1867 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1868 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1869 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1870 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1871 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1872 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1874 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1875 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1877 intel_dp
->DP
|= crtc
->pipe
<< 29;
1878 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1881 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1883 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1884 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1885 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1887 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1888 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1890 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
1891 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1893 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1894 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1895 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1896 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1897 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1899 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1900 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1902 if (IS_CHERRYVIEW(dev_priv
))
1903 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1904 else if (crtc
->pipe
== PIPE_B
)
1905 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1909 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1910 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1912 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1913 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1915 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1916 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1918 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1919 struct intel_dp
*intel_dp
);
1921 static void wait_panel_status(struct intel_dp
*intel_dp
,
1925 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1926 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1927 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1929 lockdep_assert_held(&dev_priv
->pps_mutex
);
1931 intel_pps_verify_state(dev_priv
, intel_dp
);
1933 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1934 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1936 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1938 I915_READ(pp_stat_reg
),
1939 I915_READ(pp_ctrl_reg
));
1941 if (intel_wait_for_register(dev_priv
,
1942 pp_stat_reg
, mask
, value
,
1944 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1945 I915_READ(pp_stat_reg
),
1946 I915_READ(pp_ctrl_reg
));
1948 DRM_DEBUG_KMS("Wait complete\n");
1951 static void wait_panel_on(struct intel_dp
*intel_dp
)
1953 DRM_DEBUG_KMS("Wait for panel power on\n");
1954 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1957 static void wait_panel_off(struct intel_dp
*intel_dp
)
1959 DRM_DEBUG_KMS("Wait for panel power off time\n");
1960 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1963 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1965 ktime_t panel_power_on_time
;
1966 s64 panel_power_off_duration
;
1968 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1970 /* take the difference of currrent time and panel power off time
1971 * and then make panel wait for t11_t12 if needed. */
1972 panel_power_on_time
= ktime_get_boottime();
1973 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1975 /* When we disable the VDD override bit last we have to do the manual
1977 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1978 wait_remaining_ms_from_jiffies(jiffies
,
1979 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1981 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1984 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1986 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1987 intel_dp
->backlight_on_delay
);
1990 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1992 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1993 intel_dp
->backlight_off_delay
);
1996 /* Read the current pp_control value, unlocking the register if it
2000 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2002 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2003 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2006 lockdep_assert_held(&dev_priv
->pps_mutex
);
2008 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2009 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2010 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2011 control
&= ~PANEL_UNLOCK_MASK
;
2012 control
|= PANEL_UNLOCK_REGS
;
2018 * Must be paired with edp_panel_vdd_off().
2019 * Must hold pps_mutex around the whole on/off sequence.
2020 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2022 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2024 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2025 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2026 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2028 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2029 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2031 lockdep_assert_held(&dev_priv
->pps_mutex
);
2033 if (!is_edp(intel_dp
))
2036 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2037 intel_dp
->want_panel_vdd
= true;
2039 if (edp_have_panel_vdd(intel_dp
))
2040 return need_to_disable
;
2042 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2044 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2045 port_name(intel_dig_port
->port
));
2047 if (!edp_have_panel_power(intel_dp
))
2048 wait_panel_power_cycle(intel_dp
);
2050 pp
= ironlake_get_pp_control(intel_dp
);
2051 pp
|= EDP_FORCE_VDD
;
2053 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2054 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2056 I915_WRITE(pp_ctrl_reg
, pp
);
2057 POSTING_READ(pp_ctrl_reg
);
2058 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2059 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2061 * If the panel wasn't on, delay before accessing aux channel
2063 if (!edp_have_panel_power(intel_dp
)) {
2064 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2065 port_name(intel_dig_port
->port
));
2066 msleep(intel_dp
->panel_power_up_delay
);
2069 return need_to_disable
;
2073 * Must be paired with intel_edp_panel_vdd_off() or
2074 * intel_edp_panel_off().
2075 * Nested calls to these functions are not allowed since
2076 * we drop the lock. Caller must use some higher level
2077 * locking to prevent nested calls from other threads.
2079 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2083 if (!is_edp(intel_dp
))
2087 vdd
= edp_panel_vdd_on(intel_dp
);
2088 pps_unlock(intel_dp
);
2090 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2091 port_name(dp_to_dig_port(intel_dp
)->port
));
2094 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2096 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2097 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2098 struct intel_digital_port
*intel_dig_port
=
2099 dp_to_dig_port(intel_dp
);
2101 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2103 lockdep_assert_held(&dev_priv
->pps_mutex
);
2105 WARN_ON(intel_dp
->want_panel_vdd
);
2107 if (!edp_have_panel_vdd(intel_dp
))
2110 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2111 port_name(intel_dig_port
->port
));
2113 pp
= ironlake_get_pp_control(intel_dp
);
2114 pp
&= ~EDP_FORCE_VDD
;
2116 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2117 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2119 I915_WRITE(pp_ctrl_reg
, pp
);
2120 POSTING_READ(pp_ctrl_reg
);
2122 /* Make sure sequencer is idle before allowing subsequent activity */
2123 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2124 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2126 if ((pp
& PANEL_POWER_ON
) == 0)
2127 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2129 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2132 static void edp_panel_vdd_work(struct work_struct
*__work
)
2134 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2135 struct intel_dp
, panel_vdd_work
);
2138 if (!intel_dp
->want_panel_vdd
)
2139 edp_panel_vdd_off_sync(intel_dp
);
2140 pps_unlock(intel_dp
);
2143 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2145 unsigned long delay
;
2148 * Queue the timer to fire a long time from now (relative to the power
2149 * down delay) to keep the panel power up across a sequence of
2152 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2153 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2157 * Must be paired with edp_panel_vdd_on().
2158 * Must hold pps_mutex around the whole on/off sequence.
2159 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2161 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2163 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2165 lockdep_assert_held(&dev_priv
->pps_mutex
);
2167 if (!is_edp(intel_dp
))
2170 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2171 port_name(dp_to_dig_port(intel_dp
)->port
));
2173 intel_dp
->want_panel_vdd
= false;
2176 edp_panel_vdd_off_sync(intel_dp
);
2178 edp_panel_vdd_schedule_off(intel_dp
);
2181 static void edp_panel_on(struct intel_dp
*intel_dp
)
2183 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2184 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2186 i915_reg_t pp_ctrl_reg
;
2188 lockdep_assert_held(&dev_priv
->pps_mutex
);
2190 if (!is_edp(intel_dp
))
2193 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2194 port_name(dp_to_dig_port(intel_dp
)->port
));
2196 if (WARN(edp_have_panel_power(intel_dp
),
2197 "eDP port %c panel power already on\n",
2198 port_name(dp_to_dig_port(intel_dp
)->port
)))
2201 wait_panel_power_cycle(intel_dp
);
2203 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2204 pp
= ironlake_get_pp_control(intel_dp
);
2205 if (IS_GEN5(dev_priv
)) {
2206 /* ILK workaround: disable reset around power sequence */
2207 pp
&= ~PANEL_POWER_RESET
;
2208 I915_WRITE(pp_ctrl_reg
, pp
);
2209 POSTING_READ(pp_ctrl_reg
);
2212 pp
|= PANEL_POWER_ON
;
2213 if (!IS_GEN5(dev_priv
))
2214 pp
|= PANEL_POWER_RESET
;
2216 I915_WRITE(pp_ctrl_reg
, pp
);
2217 POSTING_READ(pp_ctrl_reg
);
2219 wait_panel_on(intel_dp
);
2220 intel_dp
->last_power_on
= jiffies
;
2222 if (IS_GEN5(dev_priv
)) {
2223 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2224 I915_WRITE(pp_ctrl_reg
, pp
);
2225 POSTING_READ(pp_ctrl_reg
);
2229 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2231 if (!is_edp(intel_dp
))
2235 edp_panel_on(intel_dp
);
2236 pps_unlock(intel_dp
);
2240 static void edp_panel_off(struct intel_dp
*intel_dp
)
2242 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2243 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2245 i915_reg_t pp_ctrl_reg
;
2247 lockdep_assert_held(&dev_priv
->pps_mutex
);
2249 if (!is_edp(intel_dp
))
2252 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2253 port_name(dp_to_dig_port(intel_dp
)->port
));
2255 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2256 port_name(dp_to_dig_port(intel_dp
)->port
));
2258 pp
= ironlake_get_pp_control(intel_dp
);
2259 /* We need to switch off panel power _and_ force vdd, for otherwise some
2260 * panels get very unhappy and cease to work. */
2261 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2264 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2266 intel_dp
->want_panel_vdd
= false;
2268 I915_WRITE(pp_ctrl_reg
, pp
);
2269 POSTING_READ(pp_ctrl_reg
);
2271 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2272 wait_panel_off(intel_dp
);
2274 /* We got a reference when we enabled the VDD. */
2275 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2278 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2280 if (!is_edp(intel_dp
))
2284 edp_panel_off(intel_dp
);
2285 pps_unlock(intel_dp
);
2288 /* Enable backlight in the panel power control. */
2289 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2291 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2292 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2293 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2295 i915_reg_t pp_ctrl_reg
;
2298 * If we enable the backlight right away following a panel power
2299 * on, we may see slight flicker as the panel syncs with the eDP
2300 * link. So delay a bit to make sure the image is solid before
2301 * allowing it to appear.
2303 wait_backlight_on(intel_dp
);
2307 pp
= ironlake_get_pp_control(intel_dp
);
2308 pp
|= EDP_BLC_ENABLE
;
2310 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2312 I915_WRITE(pp_ctrl_reg
, pp
);
2313 POSTING_READ(pp_ctrl_reg
);
2315 pps_unlock(intel_dp
);
2318 /* Enable backlight PWM and backlight PP control. */
2319 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2321 if (!is_edp(intel_dp
))
2324 DRM_DEBUG_KMS("\n");
2326 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2327 _intel_edp_backlight_on(intel_dp
);
2330 /* Disable backlight in the panel power control. */
2331 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2333 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2334 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2336 i915_reg_t pp_ctrl_reg
;
2338 if (!is_edp(intel_dp
))
2343 pp
= ironlake_get_pp_control(intel_dp
);
2344 pp
&= ~EDP_BLC_ENABLE
;
2346 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2348 I915_WRITE(pp_ctrl_reg
, pp
);
2349 POSTING_READ(pp_ctrl_reg
);
2351 pps_unlock(intel_dp
);
2353 intel_dp
->last_backlight_off
= jiffies
;
2354 edp_wait_backlight_off(intel_dp
);
2357 /* Disable backlight PP control and backlight PWM. */
2358 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2360 if (!is_edp(intel_dp
))
2363 DRM_DEBUG_KMS("\n");
2365 _intel_edp_backlight_off(intel_dp
);
2366 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2370 * Hook for controlling the panel power control backlight through the bl_power
2371 * sysfs attribute. Take care to handle multiple calls.
2373 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2376 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2380 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2381 pps_unlock(intel_dp
);
2383 if (is_enabled
== enable
)
2386 DRM_DEBUG_KMS("panel power control backlight %s\n",
2387 enable
? "enable" : "disable");
2390 _intel_edp_backlight_on(intel_dp
);
2392 _intel_edp_backlight_off(intel_dp
);
2395 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2397 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2398 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2399 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2401 I915_STATE_WARN(cur_state
!= state
,
2402 "DP port %c state assertion failure (expected %s, current %s)\n",
2403 port_name(dig_port
->port
),
2404 onoff(state
), onoff(cur_state
));
2406 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2408 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2410 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2412 I915_STATE_WARN(cur_state
!= state
,
2413 "eDP PLL state assertion failure (expected %s, current %s)\n",
2414 onoff(state
), onoff(cur_state
));
2416 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2417 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2419 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2420 struct intel_crtc_state
*pipe_config
)
2422 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2423 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2425 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2426 assert_dp_port_disabled(intel_dp
);
2427 assert_edp_pll_disabled(dev_priv
);
2429 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2430 pipe_config
->port_clock
);
2432 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2434 if (pipe_config
->port_clock
== 162000)
2435 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2437 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2439 I915_WRITE(DP_A
, intel_dp
->DP
);
2444 * [DevILK] Work around required when enabling DP PLL
2445 * while a pipe is enabled going to FDI:
2446 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2447 * 2. Program DP PLL enable
2449 if (IS_GEN5(dev_priv
))
2450 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2452 intel_dp
->DP
|= DP_PLL_ENABLE
;
2454 I915_WRITE(DP_A
, intel_dp
->DP
);
2459 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2461 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2462 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2463 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2465 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2466 assert_dp_port_disabled(intel_dp
);
2467 assert_edp_pll_enabled(dev_priv
);
2469 DRM_DEBUG_KMS("disabling eDP PLL\n");
2471 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2473 I915_WRITE(DP_A
, intel_dp
->DP
);
2478 /* If the sink supports it, try to set the power state appropriately */
2479 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2483 /* Should have a valid DPCD by this point */
2484 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2487 if (mode
!= DRM_MODE_DPMS_ON
) {
2488 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2491 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2494 * When turning on, we need to retry for 1ms to give the sink
2497 for (i
= 0; i
< 3; i
++) {
2498 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2505 if (ret
== 1 && lspcon
->active
)
2506 lspcon_wait_pcon_mode(lspcon
);
2510 DRM_DEBUG_KMS("failed to %s sink power state\n",
2511 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2514 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2517 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2518 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2519 struct drm_device
*dev
= encoder
->base
.dev
;
2520 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2524 if (!intel_display_power_get_if_enabled(dev_priv
,
2525 encoder
->power_domain
))
2530 tmp
= I915_READ(intel_dp
->output_reg
);
2532 if (!(tmp
& DP_PORT_EN
))
2535 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2536 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2537 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2540 for_each_pipe(dev_priv
, p
) {
2541 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2542 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2550 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2551 i915_mmio_reg_offset(intel_dp
->output_reg
));
2552 } else if (IS_CHERRYVIEW(dev_priv
)) {
2553 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2555 *pipe
= PORT_TO_PIPE(tmp
);
2561 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2566 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2567 struct intel_crtc_state
*pipe_config
)
2569 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2571 struct drm_device
*dev
= encoder
->base
.dev
;
2572 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2573 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2574 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2576 tmp
= I915_READ(intel_dp
->output_reg
);
2578 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2580 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2581 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2583 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2584 flags
|= DRM_MODE_FLAG_PHSYNC
;
2586 flags
|= DRM_MODE_FLAG_NHSYNC
;
2588 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2589 flags
|= DRM_MODE_FLAG_PVSYNC
;
2591 flags
|= DRM_MODE_FLAG_NVSYNC
;
2593 if (tmp
& DP_SYNC_HS_HIGH
)
2594 flags
|= DRM_MODE_FLAG_PHSYNC
;
2596 flags
|= DRM_MODE_FLAG_NHSYNC
;
2598 if (tmp
& DP_SYNC_VS_HIGH
)
2599 flags
|= DRM_MODE_FLAG_PVSYNC
;
2601 flags
|= DRM_MODE_FLAG_NVSYNC
;
2604 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2606 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2607 pipe_config
->limited_color_range
= true;
2609 pipe_config
->lane_count
=
2610 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2612 intel_dp_get_m_n(crtc
, pipe_config
);
2614 if (port
== PORT_A
) {
2615 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2616 pipe_config
->port_clock
= 162000;
2618 pipe_config
->port_clock
= 270000;
2621 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2622 intel_dotclock_calculate(pipe_config
->port_clock
,
2623 &pipe_config
->dp_m_n
);
2625 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2626 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2628 * This is a big fat ugly hack.
2630 * Some machines in UEFI boot mode provide us a VBT that has 18
2631 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2632 * unknown we fail to light up. Yet the same BIOS boots up with
2633 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2634 * max, not what it tells us to use.
2636 * Note: This will still be broken if the eDP panel is not lit
2637 * up by the BIOS, and thus we can't get the mode at module
2640 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2641 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2642 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2646 static void intel_disable_dp(struct intel_encoder
*encoder
,
2647 struct intel_crtc_state
*old_crtc_state
,
2648 struct drm_connector_state
*old_conn_state
)
2650 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2651 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2653 if (old_crtc_state
->has_audio
)
2654 intel_audio_codec_disable(encoder
);
2656 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2657 intel_psr_disable(intel_dp
);
2659 /* Make sure the panel is off before trying to change the mode. But also
2660 * ensure that we have vdd while we switch off the panel. */
2661 intel_edp_panel_vdd_on(intel_dp
);
2662 intel_edp_backlight_off(intel_dp
);
2663 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2664 intel_edp_panel_off(intel_dp
);
2666 /* disable the port before the pipe on g4x */
2667 if (INTEL_GEN(dev_priv
) < 5)
2668 intel_dp_link_down(intel_dp
);
2671 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2672 struct intel_crtc_state
*old_crtc_state
,
2673 struct drm_connector_state
*old_conn_state
)
2675 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2676 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2678 intel_dp_link_down(intel_dp
);
2680 /* Only ilk+ has port A */
2682 ironlake_edp_pll_off(intel_dp
);
2685 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2686 struct intel_crtc_state
*old_crtc_state
,
2687 struct drm_connector_state
*old_conn_state
)
2689 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2691 intel_dp_link_down(intel_dp
);
2694 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2695 struct intel_crtc_state
*old_crtc_state
,
2696 struct drm_connector_state
*old_conn_state
)
2698 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2699 struct drm_device
*dev
= encoder
->base
.dev
;
2700 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2702 intel_dp_link_down(intel_dp
);
2704 mutex_lock(&dev_priv
->sb_lock
);
2706 /* Assert data lane reset */
2707 chv_data_lane_soft_reset(encoder
, true);
2709 mutex_unlock(&dev_priv
->sb_lock
);
2713 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2715 uint8_t dp_train_pat
)
2717 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2718 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2719 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2720 enum port port
= intel_dig_port
->port
;
2722 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2723 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2724 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2726 if (HAS_DDI(dev_priv
)) {
2727 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2729 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2730 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2732 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2734 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2735 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2736 case DP_TRAINING_PATTERN_DISABLE
:
2737 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2740 case DP_TRAINING_PATTERN_1
:
2741 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2743 case DP_TRAINING_PATTERN_2
:
2744 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2746 case DP_TRAINING_PATTERN_3
:
2747 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2750 I915_WRITE(DP_TP_CTL(port
), temp
);
2752 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2753 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2754 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2756 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2757 case DP_TRAINING_PATTERN_DISABLE
:
2758 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2760 case DP_TRAINING_PATTERN_1
:
2761 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2763 case DP_TRAINING_PATTERN_2
:
2764 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2766 case DP_TRAINING_PATTERN_3
:
2767 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2768 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2773 if (IS_CHERRYVIEW(dev_priv
))
2774 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2776 *DP
&= ~DP_LINK_TRAIN_MASK
;
2778 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2779 case DP_TRAINING_PATTERN_DISABLE
:
2780 *DP
|= DP_LINK_TRAIN_OFF
;
2782 case DP_TRAINING_PATTERN_1
:
2783 *DP
|= DP_LINK_TRAIN_PAT_1
;
2785 case DP_TRAINING_PATTERN_2
:
2786 *DP
|= DP_LINK_TRAIN_PAT_2
;
2788 case DP_TRAINING_PATTERN_3
:
2789 if (IS_CHERRYVIEW(dev_priv
)) {
2790 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2792 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2793 *DP
|= DP_LINK_TRAIN_PAT_2
;
2800 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2801 struct intel_crtc_state
*old_crtc_state
)
2803 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2804 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2806 /* enable with pattern 1 (as per spec) */
2808 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2811 * Magic for VLV/CHV. We _must_ first set up the register
2812 * without actually enabling the port, and then do another
2813 * write to enable the port. Otherwise link training will
2814 * fail when the power sequencer is freshly used for this port.
2816 intel_dp
->DP
|= DP_PORT_EN
;
2817 if (old_crtc_state
->has_audio
)
2818 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2820 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2821 POSTING_READ(intel_dp
->output_reg
);
2824 static void intel_enable_dp(struct intel_encoder
*encoder
,
2825 struct intel_crtc_state
*pipe_config
,
2826 struct drm_connector_state
*conn_state
)
2828 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2829 struct drm_device
*dev
= encoder
->base
.dev
;
2830 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2831 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2832 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2833 enum pipe pipe
= crtc
->pipe
;
2835 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2840 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2841 vlv_init_panel_power_sequencer(intel_dp
);
2843 intel_dp_enable_port(intel_dp
, pipe_config
);
2845 edp_panel_vdd_on(intel_dp
);
2846 edp_panel_on(intel_dp
);
2847 edp_panel_vdd_off(intel_dp
, true);
2849 pps_unlock(intel_dp
);
2851 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2852 unsigned int lane_mask
= 0x0;
2854 if (IS_CHERRYVIEW(dev_priv
))
2855 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2857 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2861 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2862 intel_dp_start_link_train(intel_dp
);
2863 intel_dp_stop_link_train(intel_dp
);
2865 if (pipe_config
->has_audio
) {
2866 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2868 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
2872 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2873 struct intel_crtc_state
*pipe_config
,
2874 struct drm_connector_state
*conn_state
)
2876 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2878 intel_enable_dp(encoder
, pipe_config
, conn_state
);
2879 intel_edp_backlight_on(intel_dp
);
2882 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2883 struct intel_crtc_state
*pipe_config
,
2884 struct drm_connector_state
*conn_state
)
2886 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2888 intel_edp_backlight_on(intel_dp
);
2889 intel_psr_enable(intel_dp
);
2892 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2893 struct intel_crtc_state
*pipe_config
,
2894 struct drm_connector_state
*conn_state
)
2896 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2897 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2899 intel_dp_prepare(encoder
, pipe_config
);
2901 /* Only ilk+ has port A */
2903 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2906 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2908 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2909 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2910 enum pipe pipe
= intel_dp
->pps_pipe
;
2911 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2913 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
2915 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2918 edp_panel_vdd_off_sync(intel_dp
);
2921 * VLV seems to get confused when multiple power seqeuencers
2922 * have the same port selected (even if only one has power/vdd
2923 * enabled). The failure manifests as vlv_wait_port_ready() failing
2924 * CHV on the other hand doesn't seem to mind having the same port
2925 * selected in multiple power seqeuencers, but let's clear the
2926 * port select always when logically disconnecting a power sequencer
2929 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2930 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2931 I915_WRITE(pp_on_reg
, 0);
2932 POSTING_READ(pp_on_reg
);
2934 intel_dp
->pps_pipe
= INVALID_PIPE
;
2937 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2940 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2941 struct intel_encoder
*encoder
;
2943 lockdep_assert_held(&dev_priv
->pps_mutex
);
2945 for_each_intel_encoder(dev
, encoder
) {
2946 struct intel_dp
*intel_dp
;
2949 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
2950 encoder
->type
!= INTEL_OUTPUT_EDP
)
2953 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2954 port
= dp_to_dig_port(intel_dp
)->port
;
2956 WARN(intel_dp
->active_pipe
== pipe
,
2957 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2958 pipe_name(pipe
), port_name(port
));
2960 if (intel_dp
->pps_pipe
!= pipe
)
2963 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2964 pipe_name(pipe
), port_name(port
));
2966 /* make sure vdd is off before we steal it */
2967 vlv_detach_power_sequencer(intel_dp
);
2971 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2973 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2974 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2975 struct drm_device
*dev
= encoder
->base
.dev
;
2976 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2977 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2979 lockdep_assert_held(&dev_priv
->pps_mutex
);
2981 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
2983 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
2984 intel_dp
->pps_pipe
!= crtc
->pipe
) {
2986 * If another power sequencer was being used on this
2987 * port previously make sure to turn off vdd there while
2988 * we still have control of it.
2990 vlv_detach_power_sequencer(intel_dp
);
2994 * We may be stealing the power
2995 * sequencer from another port.
2997 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2999 intel_dp
->active_pipe
= crtc
->pipe
;
3001 if (!is_edp(intel_dp
))
3004 /* now it's all ours */
3005 intel_dp
->pps_pipe
= crtc
->pipe
;
3007 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3008 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
3010 /* init power sequencer on this pipe and port */
3011 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
3012 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
3015 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3016 struct intel_crtc_state
*pipe_config
,
3017 struct drm_connector_state
*conn_state
)
3019 vlv_phy_pre_encoder_enable(encoder
);
3021 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3024 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3025 struct intel_crtc_state
*pipe_config
,
3026 struct drm_connector_state
*conn_state
)
3028 intel_dp_prepare(encoder
, pipe_config
);
3030 vlv_phy_pre_pll_enable(encoder
);
3033 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3034 struct intel_crtc_state
*pipe_config
,
3035 struct drm_connector_state
*conn_state
)
3037 chv_phy_pre_encoder_enable(encoder
);
3039 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3041 /* Second common lane will stay alive on its own now */
3042 chv_phy_release_cl2_override(encoder
);
3045 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3046 struct intel_crtc_state
*pipe_config
,
3047 struct drm_connector_state
*conn_state
)
3049 intel_dp_prepare(encoder
, pipe_config
);
3051 chv_phy_pre_pll_enable(encoder
);
3054 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3055 struct intel_crtc_state
*pipe_config
,
3056 struct drm_connector_state
*conn_state
)
3058 chv_phy_post_pll_disable(encoder
);
3062 * Fetch AUX CH registers 0x202 - 0x207 which contain
3063 * link status information
3066 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3068 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3069 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3072 static bool intel_dp_get_y_cord_status(struct intel_dp
*intel_dp
)
3074 uint8_t psr_caps
= 0;
3076 drm_dp_dpcd_readb(&intel_dp
->aux
, DP_PSR_CAPS
, &psr_caps
);
3077 return psr_caps
& DP_PSR2_SU_Y_COORDINATE_REQUIRED
;
3080 static bool intel_dp_get_colorimetry_status(struct intel_dp
*intel_dp
)
3084 drm_dp_dpcd_readb(&intel_dp
->aux
,
3085 DP_DPRX_FEATURE_ENUMERATION_LIST
,
3087 return dprx
& DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
;
3090 static bool intel_dp_get_alpm_status(struct intel_dp
*intel_dp
)
3092 uint8_t alpm_caps
= 0;
3094 drm_dp_dpcd_readb(&intel_dp
->aux
, DP_RECEIVER_ALPM_CAP
, &alpm_caps
);
3095 return alpm_caps
& DP_ALPM_CAP
;
3098 /* These are source-specific values. */
3100 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3102 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3103 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3105 if (IS_GEN9_LP(dev_priv
))
3106 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3107 else if (INTEL_GEN(dev_priv
) >= 9) {
3108 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3109 return intel_ddi_dp_voltage_max(encoder
);
3110 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3111 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3112 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3113 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3114 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3115 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3117 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3121 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3123 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3124 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3126 if (INTEL_GEN(dev_priv
) >= 9) {
3127 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3129 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3131 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3133 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3135 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3137 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3139 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3140 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3142 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3144 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3146 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3149 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3151 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3152 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3154 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3156 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3158 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3161 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3163 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3164 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3166 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3169 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3171 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3174 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3176 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3178 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3180 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3183 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3188 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3190 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3191 unsigned long demph_reg_value
, preemph_reg_value
,
3192 uniqtranscale_reg_value
;
3193 uint8_t train_set
= intel_dp
->train_set
[0];
3195 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3196 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3197 preemph_reg_value
= 0x0004000;
3198 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3200 demph_reg_value
= 0x2B405555;
3201 uniqtranscale_reg_value
= 0x552AB83A;
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3204 demph_reg_value
= 0x2B404040;
3205 uniqtranscale_reg_value
= 0x5548B83A;
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3208 demph_reg_value
= 0x2B245555;
3209 uniqtranscale_reg_value
= 0x5560B83A;
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3212 demph_reg_value
= 0x2B405555;
3213 uniqtranscale_reg_value
= 0x5598DA3A;
3219 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3220 preemph_reg_value
= 0x0002000;
3221 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3223 demph_reg_value
= 0x2B404040;
3224 uniqtranscale_reg_value
= 0x5552B83A;
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3227 demph_reg_value
= 0x2B404848;
3228 uniqtranscale_reg_value
= 0x5580B83A;
3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3231 demph_reg_value
= 0x2B404040;
3232 uniqtranscale_reg_value
= 0x55ADDA3A;
3238 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3239 preemph_reg_value
= 0x0000000;
3240 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3242 demph_reg_value
= 0x2B305555;
3243 uniqtranscale_reg_value
= 0x5570B83A;
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3246 demph_reg_value
= 0x2B2B4040;
3247 uniqtranscale_reg_value
= 0x55ADDA3A;
3253 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3254 preemph_reg_value
= 0x0006000;
3255 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3257 demph_reg_value
= 0x1B405555;
3258 uniqtranscale_reg_value
= 0x55ADDA3A;
3268 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3269 uniqtranscale_reg_value
, 0);
3274 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3276 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3277 u32 deemph_reg_value
, margin_reg_value
;
3278 bool uniq_trans_scale
= false;
3279 uint8_t train_set
= intel_dp
->train_set
[0];
3281 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3282 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3283 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3285 deemph_reg_value
= 128;
3286 margin_reg_value
= 52;
3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3289 deemph_reg_value
= 128;
3290 margin_reg_value
= 77;
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3293 deemph_reg_value
= 128;
3294 margin_reg_value
= 102;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3297 deemph_reg_value
= 128;
3298 margin_reg_value
= 154;
3299 uniq_trans_scale
= true;
3305 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3306 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3308 deemph_reg_value
= 85;
3309 margin_reg_value
= 78;
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3312 deemph_reg_value
= 85;
3313 margin_reg_value
= 116;
3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3316 deemph_reg_value
= 85;
3317 margin_reg_value
= 154;
3323 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3324 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3326 deemph_reg_value
= 64;
3327 margin_reg_value
= 104;
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3330 deemph_reg_value
= 64;
3331 margin_reg_value
= 154;
3337 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3338 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3340 deemph_reg_value
= 43;
3341 margin_reg_value
= 154;
3351 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3352 margin_reg_value
, uniq_trans_scale
);
3358 gen4_signal_levels(uint8_t train_set
)
3360 uint32_t signal_levels
= 0;
3362 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3363 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3365 signal_levels
|= DP_VOLTAGE_0_4
;
3367 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3368 signal_levels
|= DP_VOLTAGE_0_6
;
3370 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3371 signal_levels
|= DP_VOLTAGE_0_8
;
3373 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3374 signal_levels
|= DP_VOLTAGE_1_2
;
3377 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3378 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3380 signal_levels
|= DP_PRE_EMPHASIS_0
;
3382 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3383 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3385 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3386 signal_levels
|= DP_PRE_EMPHASIS_6
;
3388 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3389 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3392 return signal_levels
;
3395 /* Gen6's DP voltage swing and pre-emphasis control */
3397 gen6_edp_signal_levels(uint8_t train_set
)
3399 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3400 DP_TRAIN_PRE_EMPHASIS_MASK
);
3401 switch (signal_levels
) {
3402 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3404 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3406 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3407 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3409 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3411 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3412 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3413 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3415 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3417 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3418 "0x%x\n", signal_levels
);
3419 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3423 /* Gen7's DP voltage swing and pre-emphasis control */
3425 gen7_edp_signal_levels(uint8_t train_set
)
3427 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3428 DP_TRAIN_PRE_EMPHASIS_MASK
);
3429 switch (signal_levels
) {
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3431 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3433 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3435 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3438 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3439 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3440 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3442 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3443 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3445 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3448 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3449 "0x%x\n", signal_levels
);
3450 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3455 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3457 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3458 enum port port
= intel_dig_port
->port
;
3459 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3460 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3461 uint32_t signal_levels
, mask
= 0;
3462 uint8_t train_set
= intel_dp
->train_set
[0];
3464 if (HAS_DDI(dev_priv
)) {
3465 signal_levels
= ddi_signal_levels(intel_dp
);
3467 if (IS_GEN9_LP(dev_priv
))
3470 mask
= DDI_BUF_EMP_MASK
;
3471 } else if (IS_CHERRYVIEW(dev_priv
)) {
3472 signal_levels
= chv_signal_levels(intel_dp
);
3473 } else if (IS_VALLEYVIEW(dev_priv
)) {
3474 signal_levels
= vlv_signal_levels(intel_dp
);
3475 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3476 signal_levels
= gen7_edp_signal_levels(train_set
);
3477 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3478 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3479 signal_levels
= gen6_edp_signal_levels(train_set
);
3480 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3482 signal_levels
= gen4_signal_levels(train_set
);
3483 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3487 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3489 DRM_DEBUG_KMS("Using vswing level %d\n",
3490 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3491 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3492 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3493 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3495 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3497 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3498 POSTING_READ(intel_dp
->output_reg
);
3502 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3503 uint8_t dp_train_pat
)
3505 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3506 struct drm_i915_private
*dev_priv
=
3507 to_i915(intel_dig_port
->base
.base
.dev
);
3509 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3511 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3512 POSTING_READ(intel_dp
->output_reg
);
3515 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3517 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3518 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3519 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3520 enum port port
= intel_dig_port
->port
;
3523 if (!HAS_DDI(dev_priv
))
3526 val
= I915_READ(DP_TP_CTL(port
));
3527 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3528 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3529 I915_WRITE(DP_TP_CTL(port
), val
);
3532 * On PORT_A we can have only eDP in SST mode. There the only reason
3533 * we need to set idle transmission mode is to work around a HW issue
3534 * where we enable the pipe while not in idle link-training mode.
3535 * In this case there is requirement to wait for a minimum number of
3536 * idle patterns to be sent.
3541 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3542 DP_TP_STATUS_IDLE_DONE
,
3543 DP_TP_STATUS_IDLE_DONE
,
3545 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3549 intel_dp_link_down(struct intel_dp
*intel_dp
)
3551 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3552 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3553 enum port port
= intel_dig_port
->port
;
3554 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3555 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3556 uint32_t DP
= intel_dp
->DP
;
3558 if (WARN_ON(HAS_DDI(dev_priv
)))
3561 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3564 DRM_DEBUG_KMS("\n");
3566 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3567 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3568 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3569 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3571 if (IS_CHERRYVIEW(dev_priv
))
3572 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3574 DP
&= ~DP_LINK_TRAIN_MASK
;
3575 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3577 I915_WRITE(intel_dp
->output_reg
, DP
);
3578 POSTING_READ(intel_dp
->output_reg
);
3580 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3581 I915_WRITE(intel_dp
->output_reg
, DP
);
3582 POSTING_READ(intel_dp
->output_reg
);
3585 * HW workaround for IBX, we need to move the port
3586 * to transcoder A after disabling it to allow the
3587 * matching HDMI port to be enabled on transcoder A.
3589 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3591 * We get CPU/PCH FIFO underruns on the other pipe when
3592 * doing the workaround. Sweep them under the rug.
3594 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3595 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3597 /* always enable with pattern 1 (as per spec) */
3598 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3599 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3600 I915_WRITE(intel_dp
->output_reg
, DP
);
3601 POSTING_READ(intel_dp
->output_reg
);
3604 I915_WRITE(intel_dp
->output_reg
, DP
);
3605 POSTING_READ(intel_dp
->output_reg
);
3607 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3608 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3609 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3612 msleep(intel_dp
->panel_power_down_delay
);
3616 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3618 intel_dp
->active_pipe
= INVALID_PIPE
;
3619 pps_unlock(intel_dp
);
3624 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3626 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3627 sizeof(intel_dp
->dpcd
)) < 0)
3628 return false; /* aux transfer failed */
3630 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3632 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3636 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3638 struct drm_i915_private
*dev_priv
=
3639 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3641 /* this function is meant to be called only once */
3642 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3644 if (!intel_dp_read_dpcd(intel_dp
))
3647 intel_dp_read_desc(intel_dp
);
3649 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3650 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3651 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3653 /* Check if the panel supports PSR */
3654 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3656 sizeof(intel_dp
->psr_dpcd
));
3657 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3658 dev_priv
->psr
.sink_support
= true;
3659 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3662 if (INTEL_GEN(dev_priv
) >= 9 &&
3663 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3664 uint8_t frame_sync_cap
;
3666 dev_priv
->psr
.sink_support
= true;
3667 drm_dp_dpcd_read(&intel_dp
->aux
,
3668 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3669 &frame_sync_cap
, 1);
3670 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3671 /* PSR2 needs frame sync as well */
3672 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3673 DRM_DEBUG_KMS("PSR2 %s on sink",
3674 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3676 if (dev_priv
->psr
.psr2_support
) {
3677 dev_priv
->psr
.y_cord_support
=
3678 intel_dp_get_y_cord_status(intel_dp
);
3679 dev_priv
->psr
.colorimetry_support
=
3680 intel_dp_get_colorimetry_status(intel_dp
);
3681 dev_priv
->psr
.alpm
=
3682 intel_dp_get_alpm_status(intel_dp
);
3687 /* Read the eDP Display control capabilities registers */
3688 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3689 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3690 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3691 sizeof(intel_dp
->edp_dpcd
))
3692 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3693 intel_dp
->edp_dpcd
);
3695 /* Intermediate frequency support */
3696 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3697 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3700 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3701 sink_rates
, sizeof(sink_rates
));
3703 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3704 int val
= le16_to_cpu(sink_rates
[i
]);
3709 /* Value read multiplied by 200kHz gives the per-lane
3710 * link rate in kHz. The source rates are, however,
3711 * stored in terms of LS_Clk kHz. The full conversion
3712 * back to symbols is
3713 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3715 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3717 intel_dp
->num_sink_rates
= i
;
3720 if (intel_dp
->num_sink_rates
)
3721 intel_dp
->use_rate_select
= true;
3723 intel_dp_set_sink_rates(intel_dp
);
3725 intel_dp_set_common_rates(intel_dp
);
3732 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3734 if (!intel_dp_read_dpcd(intel_dp
))
3737 /* Don't clobber cached eDP rates. */
3738 if (!is_edp(intel_dp
)) {
3739 intel_dp_set_sink_rates(intel_dp
);
3740 intel_dp_set_common_rates(intel_dp
);
3743 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3744 &intel_dp
->sink_count
, 1) < 0)
3748 * Sink count can change between short pulse hpd hence
3749 * a member variable in intel_dp will track any changes
3750 * between short pulse interrupts.
3752 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3755 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3756 * a dongle is present but no display. Unless we require to know
3757 * if a dongle is present or not, we don't need to update
3758 * downstream port information. So, an early return here saves
3759 * time from performing other operations which are not required.
3761 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3764 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3765 return true; /* native DP sink */
3767 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3768 return true; /* no per-port downstream info */
3770 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3771 intel_dp
->downstream_ports
,
3772 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3773 return false; /* downstream port status fetch failed */
3779 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3783 if (!i915
.enable_dp_mst
)
3786 if (!intel_dp
->can_mst
)
3789 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3792 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1) != 1)
3795 return buf
[0] & DP_MST_CAP
;
3799 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3801 if (!i915
.enable_dp_mst
)
3804 if (!intel_dp
->can_mst
)
3807 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3809 if (intel_dp
->is_mst
)
3810 DRM_DEBUG_KMS("Sink is MST capable\n");
3812 DRM_DEBUG_KMS("Sink is not MST capable\n");
3814 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3818 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3820 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3821 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3822 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3828 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3829 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3834 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3835 buf
& ~DP_TEST_SINK_START
) < 0) {
3836 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3842 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3844 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3845 DP_TEST_SINK_MISC
, &buf
) < 0) {
3849 count
= buf
& DP_TEST_COUNT_MASK
;
3850 } while (--attempts
&& count
);
3852 if (attempts
== 0) {
3853 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3858 hsw_enable_ips(intel_crtc
);
3862 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3864 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3865 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3866 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3870 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3873 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3876 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3879 if (buf
& DP_TEST_SINK_START
) {
3880 ret
= intel_dp_sink_crc_stop(intel_dp
);
3885 hsw_disable_ips(intel_crtc
);
3887 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3888 buf
| DP_TEST_SINK_START
) < 0) {
3889 hsw_enable_ips(intel_crtc
);
3893 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3897 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3899 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3900 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3901 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3906 ret
= intel_dp_sink_crc_start(intel_dp
);
3911 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3913 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3914 DP_TEST_SINK_MISC
, &buf
) < 0) {
3918 count
= buf
& DP_TEST_COUNT_MASK
;
3920 } while (--attempts
&& count
== 0);
3922 if (attempts
== 0) {
3923 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3928 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3934 intel_dp_sink_crc_stop(intel_dp
);
3939 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3941 return drm_dp_dpcd_read(&intel_dp
->aux
,
3942 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3943 sink_irq_vector
, 1) == 1;
3947 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3951 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3953 sink_irq_vector
, 14);
3960 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3963 int min_lane_count
= 1;
3964 int link_rate_index
, test_link_rate
;
3965 uint8_t test_lane_count
, test_link_bw
;
3969 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3970 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
3974 DRM_DEBUG_KMS("Lane count read failed\n");
3977 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
3978 /* Validate the requested lane count */
3979 if (test_lane_count
< min_lane_count
||
3980 test_lane_count
> intel_dp
->max_sink_lane_count
)
3983 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
3986 DRM_DEBUG_KMS("Link Rate read failed\n");
3989 /* Validate the requested link rate */
3990 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
3991 link_rate_index
= intel_dp_link_rate_index(intel_dp
,
3993 if (link_rate_index
< 0)
3996 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
3997 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4002 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4004 uint8_t test_pattern
;
4006 __be16 h_width
, v_height
;
4009 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4010 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_PATTERN
,
4013 DRM_DEBUG_KMS("Test pattern read failed\n");
4016 if (test_pattern
!= DP_COLOR_RAMP
)
4019 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4022 DRM_DEBUG_KMS("H Width read failed\n");
4026 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4029 DRM_DEBUG_KMS("V Height read failed\n");
4033 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_MISC0
,
4036 DRM_DEBUG_KMS("TEST MISC read failed\n");
4039 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4041 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4043 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4044 case DP_TEST_BIT_DEPTH_6
:
4045 intel_dp
->compliance
.test_data
.bpc
= 6;
4047 case DP_TEST_BIT_DEPTH_8
:
4048 intel_dp
->compliance
.test_data
.bpc
= 8;
4054 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4055 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4056 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4057 /* Set test active flag here so userspace doesn't interrupt things */
4058 intel_dp
->compliance
.test_active
= 1;
4063 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4065 uint8_t test_result
= DP_TEST_ACK
;
4066 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4067 struct drm_connector
*connector
= &intel_connector
->base
;
4069 if (intel_connector
->detect_edid
== NULL
||
4070 connector
->edid_corrupt
||
4071 intel_dp
->aux
.i2c_defer_count
> 6) {
4072 /* Check EDID read for NACKs, DEFERs and corruption
4073 * (DP CTS 1.2 Core r1.1)
4074 * 4.2.2.4 : Failed EDID read, I2C_NAK
4075 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4076 * 4.2.2.6 : EDID corruption detected
4077 * Use failsafe mode for all cases
4079 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4080 intel_dp
->aux
.i2c_defer_count
> 0)
4081 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4082 intel_dp
->aux
.i2c_nack_count
,
4083 intel_dp
->aux
.i2c_defer_count
);
4084 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4086 struct edid
*block
= intel_connector
->detect_edid
;
4088 /* We have to write the checksum
4089 * of the last block read
4091 block
+= intel_connector
->detect_edid
->extensions
;
4093 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4094 DP_TEST_EDID_CHECKSUM
,
4097 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4099 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4100 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4103 /* Set test active flag here so userspace doesn't interrupt things */
4104 intel_dp
->compliance
.test_active
= 1;
4109 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4111 uint8_t test_result
= DP_TEST_NAK
;
4115 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4117 uint8_t response
= DP_TEST_NAK
;
4118 uint8_t request
= 0;
4121 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4123 DRM_DEBUG_KMS("Could not read test request from sink\n");
4128 case DP_TEST_LINK_TRAINING
:
4129 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4130 response
= intel_dp_autotest_link_training(intel_dp
);
4132 case DP_TEST_LINK_VIDEO_PATTERN
:
4133 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4134 response
= intel_dp_autotest_video_pattern(intel_dp
);
4136 case DP_TEST_LINK_EDID_READ
:
4137 DRM_DEBUG_KMS("EDID test requested\n");
4138 response
= intel_dp_autotest_edid(intel_dp
);
4140 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4141 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4142 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4145 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4149 if (response
& DP_TEST_ACK
)
4150 intel_dp
->compliance
.test_type
= request
;
4153 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4155 DRM_DEBUG_KMS("Could not write test response to sink\n");
4159 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4163 if (intel_dp
->is_mst
) {
4168 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4172 /* check link status - esi[10] = 0x200c */
4173 if (intel_dp
->active_mst_links
&&
4174 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4175 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4176 intel_dp_start_link_train(intel_dp
);
4177 intel_dp_stop_link_train(intel_dp
);
4180 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4181 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4184 for (retry
= 0; retry
< 3; retry
++) {
4186 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4187 DP_SINK_COUNT_ESI
+1,
4194 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4196 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4204 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4205 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4206 intel_dp
->is_mst
= false;
4207 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4208 /* send a hotplug event */
4209 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4216 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
4218 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4219 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4220 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4222 /* Suppress underruns caused by re-training */
4223 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4224 if (crtc
->config
->has_pch_encoder
)
4225 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4226 intel_crtc_pch_transcoder(crtc
), false);
4228 intel_dp_start_link_train(intel_dp
);
4229 intel_dp_stop_link_train(intel_dp
);
4231 /* Keep underrun reporting disabled until things are stable */
4232 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4234 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4235 if (crtc
->config
->has_pch_encoder
)
4236 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4237 intel_crtc_pch_transcoder(crtc
), true);
4241 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4243 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4244 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4245 u8 link_status
[DP_LINK_STATUS_SIZE
];
4247 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4249 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4250 DRM_ERROR("Failed to get link status\n");
4254 if (!intel_encoder
->base
.crtc
)
4257 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4260 /* FIXME: we need to synchronize this sort of stuff with hardware
4261 * readout. Currently fast link training doesn't work on boot-up. */
4262 if (!intel_dp
->lane_count
)
4265 /* Retrain if Channel EQ or CR not ok */
4266 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4267 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4268 intel_encoder
->base
.name
);
4270 intel_dp_retrain_link(intel_dp
);
4275 * According to DP spec
4278 * 2. Configure link according to Receiver Capabilities
4279 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4280 * 4. Check link status on receipt of hot-plug interrupt
4282 * intel_dp_short_pulse - handles short pulse interrupts
4283 * when full detection is not required.
4284 * Returns %true if short pulse is handled and full detection
4285 * is NOT required and %false otherwise.
4288 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4290 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4291 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4292 u8 sink_irq_vector
= 0;
4293 u8 old_sink_count
= intel_dp
->sink_count
;
4297 * Clearing compliance test variables to allow capturing
4298 * of values for next automated test request.
4300 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4303 * Now read the DPCD to see if it's actually running
4304 * If the current value of sink count doesn't match with
4305 * the value that was stored earlier or dpcd read failed
4306 * we need to do full detection
4308 ret
= intel_dp_get_dpcd(intel_dp
);
4310 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4311 /* No need to proceed if we are going to do full detect */
4315 /* Try to read the source of the interrupt */
4316 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4317 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4318 sink_irq_vector
!= 0) {
4319 /* Clear interrupt source */
4320 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4321 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4324 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4325 intel_dp_handle_test_request(intel_dp
);
4326 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4327 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4330 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4331 intel_dp_check_link_status(intel_dp
);
4332 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4333 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4334 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4335 /* Send a Hotplug Uevent to userspace to start modeset */
4336 drm_kms_helper_hotplug_event(intel_encoder
->base
.dev
);
4342 /* XXX this is probably wrong for multiple downstream ports */
4343 static enum drm_connector_status
4344 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4346 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4347 uint8_t *dpcd
= intel_dp
->dpcd
;
4351 lspcon_resume(lspcon
);
4353 if (!intel_dp_get_dpcd(intel_dp
))
4354 return connector_status_disconnected
;
4356 if (is_edp(intel_dp
))
4357 return connector_status_connected
;
4359 /* if there's no downstream port, we're done */
4360 if (!drm_dp_is_branch(dpcd
))
4361 return connector_status_connected
;
4363 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4364 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4365 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4367 return intel_dp
->sink_count
?
4368 connector_status_connected
: connector_status_disconnected
;
4371 if (intel_dp_can_mst(intel_dp
))
4372 return connector_status_connected
;
4374 /* If no HPD, poke DDC gently */
4375 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4376 return connector_status_connected
;
4378 /* Well we tried, say unknown for unreliable port types */
4379 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4380 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4381 if (type
== DP_DS_PORT_TYPE_VGA
||
4382 type
== DP_DS_PORT_TYPE_NON_EDID
)
4383 return connector_status_unknown
;
4385 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4386 DP_DWN_STRM_PORT_TYPE_MASK
;
4387 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4388 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4389 return connector_status_unknown
;
4392 /* Anything else is out of spec, warn and ignore */
4393 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4394 return connector_status_disconnected
;
4397 static enum drm_connector_status
4398 edp_detect(struct intel_dp
*intel_dp
)
4400 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4401 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4402 enum drm_connector_status status
;
4404 status
= intel_panel_detect(dev_priv
);
4405 if (status
== connector_status_unknown
)
4406 status
= connector_status_connected
;
4411 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4412 struct intel_digital_port
*port
)
4416 switch (port
->port
) {
4420 bit
= SDE_PORTB_HOTPLUG
;
4423 bit
= SDE_PORTC_HOTPLUG
;
4426 bit
= SDE_PORTD_HOTPLUG
;
4429 MISSING_CASE(port
->port
);
4433 return I915_READ(SDEISR
) & bit
;
4436 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4437 struct intel_digital_port
*port
)
4441 switch (port
->port
) {
4445 bit
= SDE_PORTB_HOTPLUG_CPT
;
4448 bit
= SDE_PORTC_HOTPLUG_CPT
;
4451 bit
= SDE_PORTD_HOTPLUG_CPT
;
4454 bit
= SDE_PORTE_HOTPLUG_SPT
;
4457 MISSING_CASE(port
->port
);
4461 return I915_READ(SDEISR
) & bit
;
4464 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4465 struct intel_digital_port
*port
)
4469 switch (port
->port
) {
4471 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4474 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4477 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4480 MISSING_CASE(port
->port
);
4484 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4487 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4488 struct intel_digital_port
*port
)
4492 switch (port
->port
) {
4494 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4497 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4500 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4503 MISSING_CASE(port
->port
);
4507 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4510 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4511 struct intel_digital_port
*intel_dig_port
)
4513 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4517 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4520 bit
= BXT_DE_PORT_HP_DDIA
;
4523 bit
= BXT_DE_PORT_HP_DDIB
;
4526 bit
= BXT_DE_PORT_HP_DDIC
;
4533 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4537 * intel_digital_port_connected - is the specified port connected?
4538 * @dev_priv: i915 private structure
4539 * @port: the port to test
4541 * Return %true if @port is connected, %false otherwise.
4543 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4544 struct intel_digital_port
*port
)
4546 if (HAS_PCH_IBX(dev_priv
))
4547 return ibx_digital_port_connected(dev_priv
, port
);
4548 else if (HAS_PCH_SPLIT(dev_priv
))
4549 return cpt_digital_port_connected(dev_priv
, port
);
4550 else if (IS_GEN9_LP(dev_priv
))
4551 return bxt_digital_port_connected(dev_priv
, port
);
4552 else if (IS_GM45(dev_priv
))
4553 return gm45_digital_port_connected(dev_priv
, port
);
4555 return g4x_digital_port_connected(dev_priv
, port
);
4558 static struct edid
*
4559 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4561 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4563 /* use cached edid if we have one */
4564 if (intel_connector
->edid
) {
4566 if (IS_ERR(intel_connector
->edid
))
4569 return drm_edid_duplicate(intel_connector
->edid
);
4571 return drm_get_edid(&intel_connector
->base
,
4572 &intel_dp
->aux
.ddc
);
4576 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4578 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4581 intel_dp_unset_edid(intel_dp
);
4582 edid
= intel_dp_get_edid(intel_dp
);
4583 intel_connector
->detect_edid
= edid
;
4585 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4586 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4588 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4592 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4594 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4596 kfree(intel_connector
->detect_edid
);
4597 intel_connector
->detect_edid
= NULL
;
4599 intel_dp
->has_audio
= false;
4602 static enum drm_connector_status
4603 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4605 struct drm_connector
*connector
= &intel_connector
->base
;
4606 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4607 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4608 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4609 struct drm_device
*dev
= connector
->dev
;
4610 enum drm_connector_status status
;
4611 u8 sink_irq_vector
= 0;
4613 intel_display_power_get(to_i915(dev
), intel_dp
->aux_power_domain
);
4615 /* Can't disconnect eDP, but you can close the lid... */
4616 if (is_edp(intel_dp
))
4617 status
= edp_detect(intel_dp
);
4618 else if (intel_digital_port_connected(to_i915(dev
),
4619 dp_to_dig_port(intel_dp
)))
4620 status
= intel_dp_detect_dpcd(intel_dp
);
4622 status
= connector_status_disconnected
;
4624 if (status
== connector_status_disconnected
) {
4625 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4627 if (intel_dp
->is_mst
) {
4628 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4630 intel_dp
->mst_mgr
.mst_state
);
4631 intel_dp
->is_mst
= false;
4632 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4639 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4640 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4642 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4643 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4644 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4646 if (intel_dp
->reset_link_params
) {
4647 /* Set the max lane count for sink */
4648 intel_dp
->max_sink_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
4650 /* Set the max link rate for sink */
4651 intel_dp
->max_sink_link_rate
= intel_dp_max_sink_rate(intel_dp
);
4653 intel_dp
->reset_link_params
= false;
4656 intel_dp_print_rates(intel_dp
);
4658 intel_dp_read_desc(intel_dp
);
4660 intel_dp_configure_mst(intel_dp
);
4662 if (intel_dp
->is_mst
) {
4664 * If we are in MST mode then this connector
4665 * won't appear connected or have anything
4668 status
= connector_status_disconnected
;
4670 } else if (connector
->status
== connector_status_connected
) {
4672 * If display was connected already and is still connected
4673 * check links status, there has been known issues of
4674 * link loss triggerring long pulse!!!!
4676 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4677 intel_dp_check_link_status(intel_dp
);
4678 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4683 * Clearing NACK and defer counts to get their exact values
4684 * while reading EDID which are required by Compliance tests
4685 * 4.2.2.4 and 4.2.2.5
4687 intel_dp
->aux
.i2c_nack_count
= 0;
4688 intel_dp
->aux
.i2c_defer_count
= 0;
4690 intel_dp_set_edid(intel_dp
);
4691 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4692 status
= connector_status_connected
;
4693 intel_dp
->detect_done
= true;
4695 /* Try to read the source of the interrupt */
4696 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4697 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4698 sink_irq_vector
!= 0) {
4699 /* Clear interrupt source */
4700 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4701 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4704 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4705 intel_dp_handle_test_request(intel_dp
);
4706 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4707 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4711 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4712 intel_dp_unset_edid(intel_dp
);
4714 intel_display_power_put(to_i915(dev
), intel_dp
->aux_power_domain
);
4718 static enum drm_connector_status
4719 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4721 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4722 enum drm_connector_status status
= connector
->status
;
4724 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4725 connector
->base
.id
, connector
->name
);
4727 /* If full detect is not performed yet, do a full detect */
4728 if (!intel_dp
->detect_done
)
4729 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4731 intel_dp
->detect_done
= false;
4737 intel_dp_force(struct drm_connector
*connector
)
4739 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4740 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4741 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4743 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4744 connector
->base
.id
, connector
->name
);
4745 intel_dp_unset_edid(intel_dp
);
4747 if (connector
->status
!= connector_status_connected
)
4750 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4752 intel_dp_set_edid(intel_dp
);
4754 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4756 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4757 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4760 static int intel_dp_get_modes(struct drm_connector
*connector
)
4762 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4765 edid
= intel_connector
->detect_edid
;
4767 int ret
= intel_connector_update_modes(connector
, edid
);
4772 /* if eDP has no EDID, fall back to fixed mode */
4773 if (is_edp(intel_attached_dp(connector
)) &&
4774 intel_connector
->panel
.fixed_mode
) {
4775 struct drm_display_mode
*mode
;
4777 mode
= drm_mode_duplicate(connector
->dev
,
4778 intel_connector
->panel
.fixed_mode
);
4780 drm_mode_probed_add(connector
, mode
);
4789 intel_dp_detect_audio(struct drm_connector
*connector
)
4791 bool has_audio
= false;
4794 edid
= to_intel_connector(connector
)->detect_edid
;
4796 has_audio
= drm_detect_monitor_audio(edid
);
4802 intel_dp_set_property(struct drm_connector
*connector
,
4803 struct drm_property
*property
,
4806 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
4807 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4808 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4809 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4812 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4816 if (property
== dev_priv
->force_audio_property
) {
4820 if (i
== intel_dp
->force_audio
)
4823 intel_dp
->force_audio
= i
;
4825 if (i
== HDMI_AUDIO_AUTO
)
4826 has_audio
= intel_dp_detect_audio(connector
);
4828 has_audio
= (i
== HDMI_AUDIO_ON
);
4830 if (has_audio
== intel_dp
->has_audio
)
4833 intel_dp
->has_audio
= has_audio
;
4837 if (property
== dev_priv
->broadcast_rgb_property
) {
4838 bool old_auto
= intel_dp
->color_range_auto
;
4839 bool old_range
= intel_dp
->limited_color_range
;
4842 case INTEL_BROADCAST_RGB_AUTO
:
4843 intel_dp
->color_range_auto
= true;
4845 case INTEL_BROADCAST_RGB_FULL
:
4846 intel_dp
->color_range_auto
= false;
4847 intel_dp
->limited_color_range
= false;
4849 case INTEL_BROADCAST_RGB_LIMITED
:
4850 intel_dp
->color_range_auto
= false;
4851 intel_dp
->limited_color_range
= true;
4857 if (old_auto
== intel_dp
->color_range_auto
&&
4858 old_range
== intel_dp
->limited_color_range
)
4864 if (is_edp(intel_dp
) &&
4865 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4866 if (val
== DRM_MODE_SCALE_NONE
) {
4867 DRM_DEBUG_KMS("no scaling not supported\n");
4870 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4871 val
== DRM_MODE_SCALE_CENTER
) {
4872 DRM_DEBUG_KMS("centering not supported\n");
4876 if (intel_connector
->panel
.fitting_mode
== val
) {
4877 /* the eDP scaling property is not changed */
4880 intel_connector
->panel
.fitting_mode
= val
;
4888 if (intel_encoder
->base
.crtc
)
4889 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4895 intel_dp_connector_register(struct drm_connector
*connector
)
4897 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4900 ret
= intel_connector_register(connector
);
4904 i915_debugfs_connector_add(connector
);
4906 DRM_DEBUG_KMS("registering %s bus for %s\n",
4907 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4909 intel_dp
->aux
.dev
= connector
->kdev
;
4910 return drm_dp_aux_register(&intel_dp
->aux
);
4914 intel_dp_connector_unregister(struct drm_connector
*connector
)
4916 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4917 intel_connector_unregister(connector
);
4921 intel_dp_connector_destroy(struct drm_connector
*connector
)
4923 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4925 kfree(intel_connector
->detect_edid
);
4927 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4928 kfree(intel_connector
->edid
);
4930 /* Can't call is_edp() since the encoder may have been destroyed
4932 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4933 intel_panel_fini(&intel_connector
->panel
);
4935 drm_connector_cleanup(connector
);
4939 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4941 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4942 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4944 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4945 if (is_edp(intel_dp
)) {
4946 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4948 * vdd might still be enabled do to the delayed vdd off.
4949 * Make sure vdd is actually turned off here.
4952 edp_panel_vdd_off_sync(intel_dp
);
4953 pps_unlock(intel_dp
);
4955 if (intel_dp
->edp_notifier
.notifier_call
) {
4956 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4957 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4961 intel_dp_aux_fini(intel_dp
);
4963 drm_encoder_cleanup(encoder
);
4964 kfree(intel_dig_port
);
4967 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4969 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4971 if (!is_edp(intel_dp
))
4975 * vdd might still be enabled do to the delayed vdd off.
4976 * Make sure vdd is actually turned off here.
4978 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4980 edp_panel_vdd_off_sync(intel_dp
);
4981 pps_unlock(intel_dp
);
4984 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4986 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4987 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4988 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4990 lockdep_assert_held(&dev_priv
->pps_mutex
);
4992 if (!edp_have_panel_vdd(intel_dp
))
4996 * The VDD bit needs a power domain reference, so if the bit is
4997 * already enabled when we boot or resume, grab this reference and
4998 * schedule a vdd off, so we don't hold on to the reference
5001 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5002 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5004 edp_panel_vdd_schedule_off(intel_dp
);
5007 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
5009 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5011 if ((intel_dp
->DP
& DP_PORT_EN
) == 0)
5012 return INVALID_PIPE
;
5014 if (IS_CHERRYVIEW(dev_priv
))
5015 return DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5017 return PORT_TO_PIPE(intel_dp
->DP
);
5020 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
5022 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
5023 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
5024 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
5026 if (!HAS_DDI(dev_priv
))
5027 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5030 lspcon_resume(lspcon
);
5032 intel_dp
->reset_link_params
= true;
5036 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5037 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5039 if (is_edp(intel_dp
)) {
5040 /* Reinit the power sequencer, in case BIOS did something with it. */
5041 intel_dp_pps_init(encoder
->dev
, intel_dp
);
5042 intel_edp_panel_vdd_sanitize(intel_dp
);
5045 pps_unlock(intel_dp
);
5048 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5049 .dpms
= drm_atomic_helper_connector_dpms
,
5050 .detect
= intel_dp_detect
,
5051 .force
= intel_dp_force
,
5052 .fill_modes
= drm_helper_probe_single_connector_modes
,
5053 .set_property
= intel_dp_set_property
,
5054 .atomic_get_property
= intel_connector_atomic_get_property
,
5055 .late_register
= intel_dp_connector_register
,
5056 .early_unregister
= intel_dp_connector_unregister
,
5057 .destroy
= intel_dp_connector_destroy
,
5058 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5059 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
5062 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5063 .get_modes
= intel_dp_get_modes
,
5064 .mode_valid
= intel_dp_mode_valid
,
5067 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5068 .reset
= intel_dp_encoder_reset
,
5069 .destroy
= intel_dp_encoder_destroy
,
5073 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5075 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5076 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
5077 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5078 enum irqreturn ret
= IRQ_NONE
;
5080 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
5081 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
5082 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
5084 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5086 * vdd off can generate a long pulse on eDP which
5087 * would require vdd on to handle it, and thus we
5088 * would end up in an endless cycle of
5089 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5091 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5092 port_name(intel_dig_port
->port
));
5096 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5097 port_name(intel_dig_port
->port
),
5098 long_hpd
? "long" : "short");
5101 intel_dp
->reset_link_params
= true;
5102 intel_dp
->detect_done
= false;
5106 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5108 if (intel_dp
->is_mst
) {
5109 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5111 * If we were in MST mode, and device is not
5112 * there, get out of MST mode
5114 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5115 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5116 intel_dp
->is_mst
= false;
5117 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5119 intel_dp
->detect_done
= false;
5124 if (!intel_dp
->is_mst
) {
5125 if (!intel_dp_short_pulse(intel_dp
)) {
5126 intel_dp
->detect_done
= false;
5134 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5139 /* check the VBT to see whether the eDP is on another port */
5140 bool intel_dp_is_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5143 * eDP not supported on g4x. so bail out early just
5144 * for a bit extra safety in case the VBT is bonkers.
5146 if (INTEL_GEN(dev_priv
) < 5)
5149 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5152 return intel_bios_is_port_edp(dev_priv
, port
);
5156 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5158 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5160 intel_attach_force_audio_property(connector
);
5161 intel_attach_broadcast_rgb_property(connector
);
5162 intel_dp
->color_range_auto
= true;
5164 if (is_edp(intel_dp
)) {
5165 drm_mode_create_scaling_mode_property(connector
->dev
);
5166 drm_object_attach_property(
5168 connector
->dev
->mode_config
.scaling_mode_property
,
5169 DRM_MODE_SCALE_ASPECT
);
5170 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5174 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5176 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5177 intel_dp
->last_power_on
= jiffies
;
5178 intel_dp
->last_backlight_off
= jiffies
;
5182 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
5183 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5185 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5186 struct pps_registers regs
;
5188 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5190 /* Workaround: Need to write PP_CONTROL with the unlock key as
5191 * the very first thing. */
5192 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5194 pp_on
= I915_READ(regs
.pp_on
);
5195 pp_off
= I915_READ(regs
.pp_off
);
5196 if (!IS_GEN9_LP(dev_priv
)) {
5197 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5198 pp_div
= I915_READ(regs
.pp_div
);
5201 /* Pull timing values out of registers */
5202 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5203 PANEL_POWER_UP_DELAY_SHIFT
;
5205 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5206 PANEL_LIGHT_ON_DELAY_SHIFT
;
5208 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5209 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5211 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5212 PANEL_POWER_DOWN_DELAY_SHIFT
;
5214 if (IS_GEN9_LP(dev_priv
)) {
5215 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5216 BXT_POWER_CYCLE_DELAY_SHIFT
;
5218 seq
->t11_t12
= (tmp
- 1) * 1000;
5222 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5223 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5228 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5230 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5232 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5236 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
5237 struct intel_dp
*intel_dp
)
5239 struct edp_power_seq hw
;
5240 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5242 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
5244 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5245 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5246 DRM_ERROR("PPS state mismatch\n");
5247 intel_pps_dump_state("sw", sw
);
5248 intel_pps_dump_state("hw", &hw
);
5253 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5254 struct intel_dp
*intel_dp
)
5256 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5257 struct edp_power_seq cur
, vbt
, spec
,
5258 *final
= &intel_dp
->pps_delays
;
5260 lockdep_assert_held(&dev_priv
->pps_mutex
);
5262 /* already initialized? */
5263 if (final
->t11_t12
!= 0)
5266 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
5268 intel_pps_dump_state("cur", &cur
);
5270 vbt
= dev_priv
->vbt
.edp
.pps
;
5272 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5273 * our hw here, which are all in 100usec. */
5274 spec
.t1_t3
= 210 * 10;
5275 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5276 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5277 spec
.t10
= 500 * 10;
5278 /* This one is special and actually in units of 100ms, but zero
5279 * based in the hw (so we need to add 100 ms). But the sw vbt
5280 * table multiplies it with 1000 to make it in units of 100usec,
5282 spec
.t11_t12
= (510 + 100) * 10;
5284 intel_pps_dump_state("vbt", &vbt
);
5286 /* Use the max of the register settings and vbt. If both are
5287 * unset, fall back to the spec limits. */
5288 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5290 max(cur.field, vbt.field))
5291 assign_final(t1_t3
);
5295 assign_final(t11_t12
);
5298 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5299 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5300 intel_dp
->backlight_on_delay
= get_delay(t8
);
5301 intel_dp
->backlight_off_delay
= get_delay(t9
);
5302 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5303 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5306 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5307 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5308 intel_dp
->panel_power_cycle_delay
);
5310 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5311 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5314 * We override the HW backlight delays to 1 because we do manual waits
5315 * on them. For T8, even BSpec recommends doing it. For T9, if we
5316 * don't do this, we'll end up waiting for the backlight off delay
5317 * twice: once when we do the manual sleep, and once when we disable
5318 * the panel and wait for the PP_STATUS bit to become zero.
5325 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5326 struct intel_dp
*intel_dp
,
5327 bool force_disable_vdd
)
5329 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5330 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5331 int div
= dev_priv
->rawclk_freq
/ 1000;
5332 struct pps_registers regs
;
5333 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5334 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5336 lockdep_assert_held(&dev_priv
->pps_mutex
);
5338 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5341 * On some VLV machines the BIOS can leave the VDD
5342 * enabled even on power seqeuencers which aren't
5343 * hooked up to any port. This would mess up the
5344 * power domain tracking the first time we pick
5345 * one of these power sequencers for use since
5346 * edp_panel_vdd_on() would notice that the VDD was
5347 * already on and therefore wouldn't grab the power
5348 * domain reference. Disable VDD first to avoid this.
5349 * This also avoids spuriously turning the VDD on as
5350 * soon as the new power seqeuencer gets initialized.
5352 if (force_disable_vdd
) {
5353 u32 pp
= ironlake_get_pp_control(intel_dp
);
5355 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5357 if (pp
& EDP_FORCE_VDD
)
5358 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5360 pp
&= ~EDP_FORCE_VDD
;
5362 I915_WRITE(regs
.pp_ctrl
, pp
);
5365 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5366 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5367 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5368 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5369 /* Compute the divisor for the pp clock, simply match the Bspec
5371 if (IS_GEN9_LP(dev_priv
)) {
5372 pp_div
= I915_READ(regs
.pp_ctrl
);
5373 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5374 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5375 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5377 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5378 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5379 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5382 /* Haswell doesn't have any port selection bits for the panel
5383 * power sequencer any more. */
5384 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5385 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5386 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5388 port_sel
= PANEL_PORT_SELECT_DPA
;
5390 port_sel
= PANEL_PORT_SELECT_DPD
;
5395 I915_WRITE(regs
.pp_on
, pp_on
);
5396 I915_WRITE(regs
.pp_off
, pp_off
);
5397 if (IS_GEN9_LP(dev_priv
))
5398 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5400 I915_WRITE(regs
.pp_div
, pp_div
);
5402 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5403 I915_READ(regs
.pp_on
),
5404 I915_READ(regs
.pp_off
),
5405 IS_GEN9_LP(dev_priv
) ?
5406 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5407 I915_READ(regs
.pp_div
));
5410 static void intel_dp_pps_init(struct drm_device
*dev
,
5411 struct intel_dp
*intel_dp
)
5413 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5415 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5416 vlv_initial_power_sequencer_setup(intel_dp
);
5418 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5419 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
5424 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5425 * @dev_priv: i915 device
5426 * @crtc_state: a pointer to the active intel_crtc_state
5427 * @refresh_rate: RR to be programmed
5429 * This function gets called when refresh rate (RR) has to be changed from
5430 * one frequency to another. Switches can be between high and low RR
5431 * supported by the panel or to any other RR based on media playback (in
5432 * this case, RR value needs to be passed from user space).
5434 * The caller of this function needs to take a lock on dev_priv->drrs.
5436 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5437 struct intel_crtc_state
*crtc_state
,
5440 struct intel_encoder
*encoder
;
5441 struct intel_digital_port
*dig_port
= NULL
;
5442 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5444 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5446 if (refresh_rate
<= 0) {
5447 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5451 if (intel_dp
== NULL
) {
5452 DRM_DEBUG_KMS("DRRS not supported.\n");
5457 * FIXME: This needs proper synchronization with psr state for some
5458 * platforms that cannot have PSR and DRRS enabled at the same time.
5461 dig_port
= dp_to_dig_port(intel_dp
);
5462 encoder
= &dig_port
->base
;
5463 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5466 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5470 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5471 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5475 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5477 index
= DRRS_LOW_RR
;
5479 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5481 "DRRS requested for previously set RR...ignoring\n");
5485 if (!crtc_state
->base
.active
) {
5486 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5490 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5493 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5496 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5500 DRM_ERROR("Unsupported refreshrate type\n");
5502 } else if (INTEL_GEN(dev_priv
) > 6) {
5503 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5506 val
= I915_READ(reg
);
5507 if (index
> DRRS_HIGH_RR
) {
5508 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5509 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5511 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5513 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5514 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5516 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5518 I915_WRITE(reg
, val
);
5521 dev_priv
->drrs
.refresh_rate_type
= index
;
5523 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5527 * intel_edp_drrs_enable - init drrs struct if supported
5528 * @intel_dp: DP struct
5529 * @crtc_state: A pointer to the active crtc state.
5531 * Initializes frontbuffer_bits and drrs.dp
5533 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5534 struct intel_crtc_state
*crtc_state
)
5536 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5537 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5539 if (!crtc_state
->has_drrs
) {
5540 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5544 mutex_lock(&dev_priv
->drrs
.mutex
);
5545 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5546 DRM_ERROR("DRRS already enabled\n");
5550 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5552 dev_priv
->drrs
.dp
= intel_dp
;
5555 mutex_unlock(&dev_priv
->drrs
.mutex
);
5559 * intel_edp_drrs_disable - Disable DRRS
5560 * @intel_dp: DP struct
5561 * @old_crtc_state: Pointer to old crtc_state.
5564 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5565 struct intel_crtc_state
*old_crtc_state
)
5567 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5568 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5570 if (!old_crtc_state
->has_drrs
)
5573 mutex_lock(&dev_priv
->drrs
.mutex
);
5574 if (!dev_priv
->drrs
.dp
) {
5575 mutex_unlock(&dev_priv
->drrs
.mutex
);
5579 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5580 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5581 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5583 dev_priv
->drrs
.dp
= NULL
;
5584 mutex_unlock(&dev_priv
->drrs
.mutex
);
5586 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5589 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5591 struct drm_i915_private
*dev_priv
=
5592 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5593 struct intel_dp
*intel_dp
;
5595 mutex_lock(&dev_priv
->drrs
.mutex
);
5597 intel_dp
= dev_priv
->drrs
.dp
;
5603 * The delayed work can race with an invalidate hence we need to
5607 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5610 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5611 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5613 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5614 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5618 mutex_unlock(&dev_priv
->drrs
.mutex
);
5622 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5623 * @dev_priv: i915 device
5624 * @frontbuffer_bits: frontbuffer plane tracking bits
5626 * This function gets called everytime rendering on the given planes start.
5627 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5629 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5631 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5632 unsigned int frontbuffer_bits
)
5634 struct drm_crtc
*crtc
;
5637 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5640 cancel_delayed_work(&dev_priv
->drrs
.work
);
5642 mutex_lock(&dev_priv
->drrs
.mutex
);
5643 if (!dev_priv
->drrs
.dp
) {
5644 mutex_unlock(&dev_priv
->drrs
.mutex
);
5648 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5649 pipe
= to_intel_crtc(crtc
)->pipe
;
5651 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5652 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5654 /* invalidate means busy screen hence upclock */
5655 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5656 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5657 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5659 mutex_unlock(&dev_priv
->drrs
.mutex
);
5663 * intel_edp_drrs_flush - Restart Idleness DRRS
5664 * @dev_priv: i915 device
5665 * @frontbuffer_bits: frontbuffer plane tracking bits
5667 * This function gets called every time rendering on the given planes has
5668 * completed or flip on a crtc is completed. So DRRS should be upclocked
5669 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5670 * if no other planes are dirty.
5672 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5674 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5675 unsigned int frontbuffer_bits
)
5677 struct drm_crtc
*crtc
;
5680 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5683 cancel_delayed_work(&dev_priv
->drrs
.work
);
5685 mutex_lock(&dev_priv
->drrs
.mutex
);
5686 if (!dev_priv
->drrs
.dp
) {
5687 mutex_unlock(&dev_priv
->drrs
.mutex
);
5691 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5692 pipe
= to_intel_crtc(crtc
)->pipe
;
5694 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5695 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5697 /* flush means busy screen hence upclock */
5698 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5699 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5700 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5703 * flush also means no more activity hence schedule downclock, if all
5704 * other fbs are quiescent too
5706 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5707 schedule_delayed_work(&dev_priv
->drrs
.work
,
5708 msecs_to_jiffies(1000));
5709 mutex_unlock(&dev_priv
->drrs
.mutex
);
5713 * DOC: Display Refresh Rate Switching (DRRS)
5715 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5716 * which enables swtching between low and high refresh rates,
5717 * dynamically, based on the usage scenario. This feature is applicable
5718 * for internal panels.
5720 * Indication that the panel supports DRRS is given by the panel EDID, which
5721 * would list multiple refresh rates for one resolution.
5723 * DRRS is of 2 types - static and seamless.
5724 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5725 * (may appear as a blink on screen) and is used in dock-undock scenario.
5726 * Seamless DRRS involves changing RR without any visual effect to the user
5727 * and can be used during normal system usage. This is done by programming
5728 * certain registers.
5730 * Support for static/seamless DRRS may be indicated in the VBT based on
5731 * inputs from the panel spec.
5733 * DRRS saves power by switching to low RR based on usage scenarios.
5735 * The implementation is based on frontbuffer tracking implementation. When
5736 * there is a disturbance on the screen triggered by user activity or a periodic
5737 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5738 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5741 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5742 * and intel_edp_drrs_flush() are called.
5744 * DRRS can be further extended to support other internal panels and also
5745 * the scenario of video playback wherein RR is set based on the rate
5746 * requested by userspace.
5750 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5751 * @intel_connector: eDP connector
5752 * @fixed_mode: preferred mode of panel
5754 * This function is called only once at driver load to initialize basic
5758 * Downclock mode if panel supports it, else return NULL.
5759 * DRRS support is determined by the presence of downclock mode (apart
5760 * from VBT setting).
5762 static struct drm_display_mode
*
5763 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5764 struct drm_display_mode
*fixed_mode
)
5766 struct drm_connector
*connector
= &intel_connector
->base
;
5767 struct drm_device
*dev
= connector
->dev
;
5768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5769 struct drm_display_mode
*downclock_mode
= NULL
;
5771 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5772 mutex_init(&dev_priv
->drrs
.mutex
);
5774 if (INTEL_GEN(dev_priv
) <= 6) {
5775 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5779 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5780 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5784 downclock_mode
= intel_find_panel_downclock
5785 (dev_priv
, fixed_mode
, connector
);
5787 if (!downclock_mode
) {
5788 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5792 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5794 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5795 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5796 return downclock_mode
;
5799 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5800 struct intel_connector
*intel_connector
)
5802 struct drm_connector
*connector
= &intel_connector
->base
;
5803 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5804 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5805 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5806 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5807 struct drm_display_mode
*fixed_mode
= NULL
;
5808 struct drm_display_mode
*downclock_mode
= NULL
;
5810 struct drm_display_mode
*scan
;
5812 enum pipe pipe
= INVALID_PIPE
;
5814 if (!is_edp(intel_dp
))
5818 * On IBX/CPT we may get here with LVDS already registered. Since the
5819 * driver uses the only internal power sequencer available for both
5820 * eDP and LVDS bail out early in this case to prevent interfering
5821 * with an already powered-on LVDS power sequencer.
5823 if (intel_get_lvds_encoder(dev
)) {
5824 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5825 DRM_INFO("LVDS was detected, not registering eDP\n");
5832 intel_dp_init_panel_power_timestamps(intel_dp
);
5833 intel_dp_pps_init(dev
, intel_dp
);
5834 intel_edp_panel_vdd_sanitize(intel_dp
);
5836 pps_unlock(intel_dp
);
5838 /* Cache DPCD and EDID for edp. */
5839 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5842 /* if this fails, presume the device is a ghost */
5843 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5847 mutex_lock(&dev
->mode_config
.mutex
);
5848 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5850 if (drm_add_edid_modes(connector
, edid
)) {
5851 drm_mode_connector_update_edid_property(connector
,
5853 drm_edid_to_eld(connector
, edid
);
5856 edid
= ERR_PTR(-EINVAL
);
5859 edid
= ERR_PTR(-ENOENT
);
5861 intel_connector
->edid
= edid
;
5863 /* prefer fixed mode from EDID if available */
5864 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5865 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5866 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5867 downclock_mode
= intel_dp_drrs_init(
5868 intel_connector
, fixed_mode
);
5873 /* fallback to VBT if available for eDP */
5874 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5875 fixed_mode
= drm_mode_duplicate(dev
,
5876 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5878 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5879 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5880 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5883 mutex_unlock(&dev
->mode_config
.mutex
);
5885 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5886 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5887 register_reboot_notifier(&intel_dp
->edp_notifier
);
5890 * Figure out the current pipe for the initial backlight setup.
5891 * If the current pipe isn't valid, try the PPS pipe, and if that
5892 * fails just assume pipe A.
5894 pipe
= vlv_active_pipe(intel_dp
);
5896 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5897 pipe
= intel_dp
->pps_pipe
;
5899 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5902 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5906 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5907 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5908 intel_panel_setup_backlight(connector
, pipe
);
5913 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5915 * vdd might still be enabled do to the delayed vdd off.
5916 * Make sure vdd is actually turned off here.
5919 edp_panel_vdd_off_sync(intel_dp
);
5920 pps_unlock(intel_dp
);
5925 /* Set up the hotplug pin and aux power domain. */
5927 intel_dp_init_connector_port_info(struct intel_digital_port
*intel_dig_port
)
5929 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
5930 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5932 switch (intel_dig_port
->port
) {
5934 encoder
->hpd_pin
= HPD_PORT_A
;
5935 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_A
;
5938 encoder
->hpd_pin
= HPD_PORT_B
;
5939 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_B
;
5942 encoder
->hpd_pin
= HPD_PORT_C
;
5943 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_C
;
5946 encoder
->hpd_pin
= HPD_PORT_D
;
5947 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5950 encoder
->hpd_pin
= HPD_PORT_E
;
5952 /* FIXME: Check VBT for actual wiring of PORT E */
5953 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5956 MISSING_CASE(intel_dig_port
->port
);
5961 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5962 struct intel_connector
*intel_connector
)
5964 struct drm_connector
*connector
= &intel_connector
->base
;
5965 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5966 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5967 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5968 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5969 enum port port
= intel_dig_port
->port
;
5972 if (WARN(intel_dig_port
->max_lanes
< 1,
5973 "Not enough lanes (%d) for DP on port %c\n",
5974 intel_dig_port
->max_lanes
, port_name(port
)))
5977 intel_dp_set_source_rates(intel_dp
);
5979 intel_dp
->reset_link_params
= true;
5980 intel_dp
->pps_pipe
= INVALID_PIPE
;
5981 intel_dp
->active_pipe
= INVALID_PIPE
;
5983 /* intel_dp vfuncs */
5984 if (INTEL_GEN(dev_priv
) >= 9)
5985 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5986 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5987 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5988 else if (HAS_PCH_SPLIT(dev_priv
))
5989 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5991 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5993 if (INTEL_GEN(dev_priv
) >= 9)
5994 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5996 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5998 if (HAS_DDI(dev_priv
))
5999 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6001 /* Preserve the current hw state. */
6002 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6003 intel_dp
->attached_connector
= intel_connector
;
6005 if (intel_dp_is_edp(dev_priv
, port
))
6006 type
= DRM_MODE_CONNECTOR_eDP
;
6008 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6010 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6011 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6014 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6015 * for DP the encoder type can be set by the caller to
6016 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6018 if (type
== DRM_MODE_CONNECTOR_eDP
)
6019 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6021 /* eDP only on port B and/or C on vlv/chv */
6022 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6023 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
6026 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6027 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6030 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6031 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6033 connector
->interlace_allowed
= true;
6034 connector
->doublescan_allowed
= 0;
6036 intel_dp_init_connector_port_info(intel_dig_port
);
6038 intel_dp_aux_init(intel_dp
);
6040 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6041 edp_panel_vdd_work
);
6043 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6045 if (HAS_DDI(dev_priv
))
6046 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6048 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6050 /* init MST on ports that can support it */
6051 if (HAS_DP_MST(dev_priv
) && !is_edp(intel_dp
) &&
6052 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
6053 intel_dp_mst_encoder_init(intel_dig_port
,
6054 intel_connector
->base
.base
.id
);
6056 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6057 intel_dp_aux_fini(intel_dp
);
6058 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6062 intel_dp_add_properties(intel_dp
, connector
);
6064 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6065 * 0xd. Failure to do so will result in spurious interrupts being
6066 * generated on the port when a cable is not attached.
6068 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
6069 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6070 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6076 drm_connector_cleanup(connector
);
6081 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6082 i915_reg_t output_reg
,
6085 struct intel_digital_port
*intel_dig_port
;
6086 struct intel_encoder
*intel_encoder
;
6087 struct drm_encoder
*encoder
;
6088 struct intel_connector
*intel_connector
;
6090 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6091 if (!intel_dig_port
)
6094 intel_connector
= intel_connector_alloc();
6095 if (!intel_connector
)
6096 goto err_connector_alloc
;
6098 intel_encoder
= &intel_dig_port
->base
;
6099 encoder
= &intel_encoder
->base
;
6101 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6102 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6103 "DP %c", port_name(port
)))
6104 goto err_encoder_init
;
6106 intel_encoder
->compute_config
= intel_dp_compute_config
;
6107 intel_encoder
->disable
= intel_disable_dp
;
6108 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6109 intel_encoder
->get_config
= intel_dp_get_config
;
6110 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6111 if (IS_CHERRYVIEW(dev_priv
)) {
6112 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6113 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6114 intel_encoder
->enable
= vlv_enable_dp
;
6115 intel_encoder
->post_disable
= chv_post_disable_dp
;
6116 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6117 } else if (IS_VALLEYVIEW(dev_priv
)) {
6118 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6119 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6120 intel_encoder
->enable
= vlv_enable_dp
;
6121 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6123 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6124 intel_encoder
->enable
= g4x_enable_dp
;
6125 if (INTEL_GEN(dev_priv
) >= 5)
6126 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6129 intel_dig_port
->port
= port
;
6130 intel_dig_port
->dp
.output_reg
= output_reg
;
6131 intel_dig_port
->max_lanes
= 4;
6133 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6134 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6135 if (IS_CHERRYVIEW(dev_priv
)) {
6137 intel_encoder
->crtc_mask
= 1 << 2;
6139 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6141 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6143 intel_encoder
->cloneable
= 0;
6144 intel_encoder
->port
= port
;
6146 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6147 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6149 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6150 goto err_init_connector
;
6155 drm_encoder_cleanup(encoder
);
6157 kfree(intel_connector
);
6158 err_connector_alloc
:
6159 kfree(intel_dig_port
);
6163 void intel_dp_mst_suspend(struct drm_device
*dev
)
6165 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6169 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6170 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6172 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6175 if (intel_dig_port
->dp
.is_mst
)
6176 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6180 void intel_dp_mst_resume(struct drm_device
*dev
)
6182 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6185 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6186 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6189 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6192 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6194 intel_dp_check_mst_status(&intel_dig_port
->dp
);