2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp
*intel_dp
)
50 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
52 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp
*intel_dp
)
65 return intel_dp
->is_pch_edp
;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
76 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
79 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
81 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
83 return intel_dig_port
->base
.base
.dev
;
86 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
88 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
98 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
100 struct intel_dp
*intel_dp
;
105 intel_dp
= enc_to_intel_dp(encoder
);
107 return is_pch_edp(intel_dp
);
110 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
113 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
115 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
117 switch (max_link_bw
) {
118 case DP_LINK_BW_1_62
:
122 max_link_bw
= DP_LINK_BW_1_62
;
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
134 * 270000 * 1 * 8 / 10 == 216000
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
146 intel_dp_link_required(int pixel_clock
, int bpp
)
148 return (pixel_clock
* bpp
+ 9) / 10;
152 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
154 return (max_link_clock
* max_lanes
* 8) / 10;
158 intel_dp_mode_valid(struct drm_connector
*connector
,
159 struct drm_display_mode
*mode
)
161 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
162 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
163 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
164 int target_clock
= mode
->clock
;
165 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
167 if (is_edp(intel_dp
) && fixed_mode
) {
168 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
171 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
174 target_clock
= fixed_mode
->clock
;
177 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
178 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
180 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
181 mode_rate
= intel_dp_link_required(target_clock
, 18);
183 if (mode_rate
> max_rate
)
184 return MODE_CLOCK_HIGH
;
186 if (mode
->clock
< 10000)
187 return MODE_CLOCK_LOW
;
189 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
190 return MODE_H_ILLEGAL
;
196 pack_aux(uint8_t *src
, int src_bytes
)
203 for (i
= 0; i
< src_bytes
; i
++)
204 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
209 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
214 for (i
= 0; i
< dst_bytes
; i
++)
215 dst
[i
] = src
>> ((3-i
) * 8);
218 /* hrawclock is 1/4 the FSB frequency */
220 intel_hrawclk(struct drm_device
*dev
)
222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev
))
229 clkcfg
= I915_READ(CLKCFG
);
230 switch (clkcfg
& CLKCFG_FSB_MASK
) {
239 case CLKCFG_FSB_1067
:
241 case CLKCFG_FSB_1333
:
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600
:
245 case CLKCFG_FSB_1600_ALT
:
252 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
254 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
259 return (I915_READ(pp_stat_reg
) & PP_ON
) != 0;
262 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
264 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
268 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
269 return (I915_READ(pp_ctrl_reg
) & EDP_FORCE_VDD
) != 0;
273 intel_dp_check_edp(struct intel_dp
*intel_dp
)
275 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
277 u32 pp_stat_reg
, pp_ctrl_reg
;
279 if (!is_edp(intel_dp
))
282 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
283 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
285 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
288 I915_READ(pp_stat_reg
),
289 I915_READ(pp_ctrl_reg
));
294 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
305 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
306 msecs_to_jiffies(10));
308 done
= wait_for_atomic(C
, 10) == 0;
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
318 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
319 uint8_t *send
, int send_bytes
,
320 uint8_t *recv
, int recv_size
)
322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
323 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
325 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
326 uint32_t ch_data
= ch_ctl
+ 4;
327 int i
, ret
, recv_bytes
;
329 uint32_t aux_clock_divider
;
331 bool has_aux_irq
= INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
);
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
337 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
339 intel_dp_check_edp(intel_dp
);
340 /* The clock divider is based off the hrawclk,
341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
344 * Note that PCH attached eDP panels should use a 125MHz input
347 if (is_cpu_edp(intel_dp
)) {
349 aux_clock_divider
= intel_ddi_get_cdclk_freq(dev_priv
) >> 1;
350 else if (IS_VALLEYVIEW(dev
))
351 aux_clock_divider
= 100;
352 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
353 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
355 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
356 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider
= 74;
359 } else if (HAS_PCH_SPLIT(dev
)) {
360 aux_clock_divider
= DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
362 aux_clock_divider
= intel_hrawclk(dev
) / 2;
370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
372 status
= I915_READ_NOTRACE(ch_ctl
);
373 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
388 for (i
= 0; i
< send_bytes
; i
+= 4)
389 I915_WRITE(ch_data
+ i
,
390 pack_aux(send
+ i
, send_bytes
- i
));
392 /* Send the command and wait for it to complete */
394 DP_AUX_CH_CTL_SEND_BUSY
|
395 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
396 DP_AUX_CH_CTL_TIME_OUT_400us
|
397 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
398 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
399 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
402 DP_AUX_CH_CTL_RECEIVE_ERROR
);
404 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
406 /* Clear done status and any errors */
410 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
411 DP_AUX_CH_CTL_RECEIVE_ERROR
);
413 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
414 DP_AUX_CH_CTL_RECEIVE_ERROR
))
416 if (status
& DP_AUX_CH_CTL_DONE
)
420 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
429 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
437 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
443 /* Unload any bytes sent back from the other side */
444 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
446 if (recv_bytes
> recv_size
)
447 recv_bytes
= recv_size
;
449 for (i
= 0; i
< recv_bytes
; i
+= 4)
450 unpack_aux(I915_READ(ch_data
+ i
),
451 recv
+ i
, recv_bytes
- i
);
455 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
460 /* Write data to the aux channel in native mode */
462 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
463 uint16_t address
, uint8_t *send
, int send_bytes
)
470 intel_dp_check_edp(intel_dp
);
473 msg
[0] = AUX_NATIVE_WRITE
<< 4;
474 msg
[1] = address
>> 8;
475 msg
[2] = address
& 0xff;
476 msg
[3] = send_bytes
- 1;
477 memcpy(&msg
[4], send
, send_bytes
);
478 msg_bytes
= send_bytes
+ 4;
480 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
483 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
485 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
493 /* Write a single byte to the aux channel in native mode */
495 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
496 uint16_t address
, uint8_t byte
)
498 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
501 /* read bytes from a native aux channel */
503 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
504 uint16_t address
, uint8_t *recv
, int recv_bytes
)
513 intel_dp_check_edp(intel_dp
);
514 msg
[0] = AUX_NATIVE_READ
<< 4;
515 msg
[1] = address
>> 8;
516 msg
[2] = address
& 0xff;
517 msg
[3] = recv_bytes
- 1;
520 reply_bytes
= recv_bytes
+ 1;
523 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
530 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
531 memcpy(recv
, reply
+ 1, ret
- 1);
534 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
542 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
543 uint8_t write_byte
, uint8_t *read_byte
)
545 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
546 struct intel_dp
*intel_dp
= container_of(adapter
,
549 uint16_t address
= algo_data
->address
;
557 intel_dp_check_edp(intel_dp
);
558 /* Set up the command byte */
559 if (mode
& MODE_I2C_READ
)
560 msg
[0] = AUX_I2C_READ
<< 4;
562 msg
[0] = AUX_I2C_WRITE
<< 4;
564 if (!(mode
& MODE_I2C_STOP
))
565 msg
[0] |= AUX_I2C_MOT
<< 4;
567 msg
[1] = address
>> 8;
588 for (retry
= 0; retry
< 5; retry
++) {
589 ret
= intel_dp_aux_ch(intel_dp
,
593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
597 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
598 case AUX_NATIVE_REPLY_ACK
:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
603 case AUX_NATIVE_REPLY_NACK
:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
606 case AUX_NATIVE_REPLY_DEFER
:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
615 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
616 case AUX_I2C_REPLY_ACK
:
617 if (mode
== MODE_I2C_READ
) {
618 *read_byte
= reply
[1];
620 return reply_bytes
- 1;
621 case AUX_I2C_REPLY_NACK
:
622 DRM_DEBUG_KMS("aux_i2c nack\n");
624 case AUX_I2C_REPLY_DEFER
:
625 DRM_DEBUG_KMS("aux_i2c defer\n");
629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
634 DRM_ERROR("too many retries, giving up\n");
639 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
640 struct intel_connector
*intel_connector
, const char *name
)
644 DRM_DEBUG_KMS("i2c_init %s\n", name
);
645 intel_dp
->algo
.running
= false;
646 intel_dp
->algo
.address
= 0;
647 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
649 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
650 intel_dp
->adapter
.owner
= THIS_MODULE
;
651 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
652 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
653 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
654 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
655 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
657 ironlake_edp_panel_vdd_on(intel_dp
);
658 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
659 ironlake_edp_panel_vdd_off(intel_dp
, false);
664 intel_dp_compute_config(struct intel_encoder
*encoder
,
665 struct intel_crtc_config
*pipe_config
)
667 struct drm_device
*dev
= encoder
->base
.dev
;
668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
669 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
670 struct drm_display_mode
*mode
= &pipe_config
->requested_mode
;
671 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
672 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
673 int lane_count
, clock
;
674 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
675 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
677 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
678 int target_clock
, link_avail
, link_clock
;
680 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && !is_cpu_edp(intel_dp
))
681 pipe_config
->has_pch_encoder
= true;
683 pipe_config
->has_dp_encoder
= true;
685 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
686 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
688 intel_pch_panel_fitting(dev
,
689 intel_connector
->panel
.fitting_mode
,
690 mode
, adjusted_mode
);
692 /* We need to take the panel's fixed mode into account. */
693 target_clock
= adjusted_mode
->clock
;
695 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
698 DRM_DEBUG_KMS("DP link computation with max lane count %i "
699 "max bw %02x pixel clock %iKHz\n",
700 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
702 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
704 bpp
= min_t(int, 8*3, pipe_config
->pipe_bpp
);
705 if (is_edp(intel_dp
) && dev_priv
->edp
.bpp
)
706 bpp
= min_t(int, bpp
, dev_priv
->edp
.bpp
);
708 for (; bpp
>= 6*3; bpp
-= 2*3) {
709 mode_rate
= intel_dp_link_required(target_clock
, bpp
);
711 for (clock
= 0; clock
<= max_clock
; clock
++) {
712 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
713 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
714 link_avail
= intel_dp_max_data_rate(link_clock
,
717 if (mode_rate
<= link_avail
) {
727 if (intel_dp
->color_range_auto
) {
730 * CEA-861-E - 5.1 Default Encoding Parameters
731 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
733 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
734 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
736 intel_dp
->color_range
= 0;
739 if (intel_dp
->color_range
)
740 pipe_config
->limited_color_range
= true;
742 intel_dp
->link_bw
= bws
[clock
];
743 intel_dp
->lane_count
= lane_count
;
744 adjusted_mode
->clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
745 pipe_config
->pipe_bpp
= bpp
;
746 pipe_config
->pixel_target_clock
= target_clock
;
748 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
749 intel_dp
->link_bw
, intel_dp
->lane_count
,
750 adjusted_mode
->clock
, bpp
);
751 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
752 mode_rate
, link_avail
);
754 intel_link_compute_m_n(bpp
, lane_count
,
755 target_clock
, adjusted_mode
->clock
,
756 &pipe_config
->dp_m_n
);
761 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
763 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
764 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
765 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
766 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
768 * Check for DPCD version > 1.1 and enhanced framing support
770 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
771 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
772 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
776 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
778 struct drm_device
*dev
= crtc
->dev
;
779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
782 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
783 dpa_ctl
= I915_READ(DP_A
);
784 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
786 if (clock
< 200000) {
787 /* For a long time we've carried around a ILK-DevA w/a for the
788 * 160MHz clock. If we're really unlucky, it's still required.
790 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
791 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
793 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
796 I915_WRITE(DP_A
, dpa_ctl
);
803 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
804 struct drm_display_mode
*adjusted_mode
)
806 struct drm_device
*dev
= encoder
->dev
;
807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
808 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
809 struct drm_crtc
*crtc
= encoder
->crtc
;
810 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
813 * There are four kinds of DP registers:
820 * IBX PCH and CPU are the same for almost everything,
821 * except that the CPU DP PLL is configured in this
824 * CPT PCH is quite different, having many bits moved
825 * to the TRANS_DP_CTL register instead. That
826 * configuration happens (oddly) in ironlake_pch_enable
829 /* Preserve the BIOS-computed detected bit. This is
830 * supposed to be read-only.
832 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
834 /* Handle DP bits in common between all three register formats */
835 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
837 switch (intel_dp
->lane_count
) {
839 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
842 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
845 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
848 if (intel_dp
->has_audio
) {
849 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
850 pipe_name(intel_crtc
->pipe
));
851 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
852 intel_write_eld(encoder
, adjusted_mode
);
855 intel_dp_init_link_config(intel_dp
);
857 /* Split out the IBX/CPU vs CPT settings */
859 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
860 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
861 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
862 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
863 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
864 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
866 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
867 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
869 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
871 /* don't miss out required setting for eDP */
872 if (adjusted_mode
->clock
< 200000)
873 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
875 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
876 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
877 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
878 intel_dp
->DP
|= intel_dp
->color_range
;
880 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
881 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
882 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
883 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
884 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
886 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
887 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
889 if (intel_crtc
->pipe
== 1)
890 intel_dp
->DP
|= DP_PIPEB_SELECT
;
892 if (is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
893 /* don't miss out required setting for eDP */
894 if (adjusted_mode
->clock
< 200000)
895 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
897 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
900 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
903 if (is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
))
904 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
907 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
908 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
910 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
911 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
913 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
914 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
916 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
920 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
922 u32 pp_stat_reg
, pp_ctrl_reg
;
924 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
925 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
927 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
929 I915_READ(pp_stat_reg
),
930 I915_READ(pp_ctrl_reg
));
932 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
933 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
934 I915_READ(pp_stat_reg
),
935 I915_READ(pp_ctrl_reg
));
939 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
941 DRM_DEBUG_KMS("Wait for panel power on\n");
942 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
945 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
947 DRM_DEBUG_KMS("Wait for panel power off time\n");
948 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
951 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
953 DRM_DEBUG_KMS("Wait for panel power cycle\n");
954 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
958 /* Read the current pp_control value, unlocking the register if it
962 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
964 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
969 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
970 control
= I915_READ(pp_ctrl_reg
);
972 control
&= ~PANEL_UNLOCK_MASK
;
973 control
|= PANEL_UNLOCK_REGS
;
977 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
979 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
982 u32 pp_stat_reg
, pp_ctrl_reg
;
984 if (!is_edp(intel_dp
))
986 DRM_DEBUG_KMS("Turn eDP VDD on\n");
988 WARN(intel_dp
->want_panel_vdd
,
989 "eDP VDD already requested on\n");
991 intel_dp
->want_panel_vdd
= true;
993 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
994 DRM_DEBUG_KMS("eDP VDD already on\n");
998 if (!ironlake_edp_have_panel_power(intel_dp
))
999 ironlake_wait_panel_power_cycle(intel_dp
);
1001 pp
= ironlake_get_pp_control(intel_dp
);
1002 pp
|= EDP_FORCE_VDD
;
1004 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
1005 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1007 I915_WRITE(pp_ctrl_reg
, pp
);
1008 POSTING_READ(pp_ctrl_reg
);
1009 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1010 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1012 * If the panel wasn't on, delay before accessing aux channel
1014 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1015 DRM_DEBUG_KMS("eDP was not running\n");
1016 msleep(intel_dp
->panel_power_up_delay
);
1020 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1022 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1025 u32 pp_stat_reg
, pp_ctrl_reg
;
1027 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1029 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1030 pp
= ironlake_get_pp_control(intel_dp
);
1031 pp
&= ~EDP_FORCE_VDD
;
1033 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
1034 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1036 I915_WRITE(pp_ctrl_reg
, pp
);
1037 POSTING_READ(pp_ctrl_reg
);
1039 /* Make sure sequencer is idle before allowing subsequent activity */
1040 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1041 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1042 msleep(intel_dp
->panel_power_down_delay
);
1046 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1048 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1049 struct intel_dp
, panel_vdd_work
);
1050 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1052 mutex_lock(&dev
->mode_config
.mutex
);
1053 ironlake_panel_vdd_off_sync(intel_dp
);
1054 mutex_unlock(&dev
->mode_config
.mutex
);
1057 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1059 if (!is_edp(intel_dp
))
1062 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1063 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1065 intel_dp
->want_panel_vdd
= false;
1068 ironlake_panel_vdd_off_sync(intel_dp
);
1071 * Queue the timer to fire a long
1072 * time from now (relative to the power down delay)
1073 * to keep the panel power up across a sequence of operations
1075 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1076 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1080 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1082 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1087 if (!is_edp(intel_dp
))
1090 DRM_DEBUG_KMS("Turn eDP power on\n");
1092 if (ironlake_edp_have_panel_power(intel_dp
)) {
1093 DRM_DEBUG_KMS("eDP power already on\n");
1097 ironlake_wait_panel_power_cycle(intel_dp
);
1099 pp
= ironlake_get_pp_control(intel_dp
);
1101 /* ILK workaround: disable reset around power sequence */
1102 pp
&= ~PANEL_POWER_RESET
;
1103 I915_WRITE(PCH_PP_CONTROL
, pp
);
1104 POSTING_READ(PCH_PP_CONTROL
);
1107 pp
|= POWER_TARGET_ON
;
1109 pp
|= PANEL_POWER_RESET
;
1111 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1113 I915_WRITE(pp_ctrl_reg
, pp
);
1114 POSTING_READ(pp_ctrl_reg
);
1116 ironlake_wait_panel_on(intel_dp
);
1119 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1120 I915_WRITE(PCH_PP_CONTROL
, pp
);
1121 POSTING_READ(PCH_PP_CONTROL
);
1125 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1127 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1132 if (!is_edp(intel_dp
))
1135 DRM_DEBUG_KMS("Turn eDP power off\n");
1137 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1139 pp
= ironlake_get_pp_control(intel_dp
);
1140 /* We need to switch off panel power _and_ force vdd, for otherwise some
1141 * panels get very unhappy and cease to work. */
1142 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1144 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1146 I915_WRITE(pp_ctrl_reg
, pp
);
1147 POSTING_READ(pp_ctrl_reg
);
1149 intel_dp
->want_panel_vdd
= false;
1151 ironlake_wait_panel_off(intel_dp
);
1154 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1156 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1157 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1159 int pipe
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
)->pipe
;
1163 if (!is_edp(intel_dp
))
1166 DRM_DEBUG_KMS("\n");
1168 * If we enable the backlight right away following a panel power
1169 * on, we may see slight flicker as the panel syncs with the eDP
1170 * link. So delay a bit to make sure the image is solid before
1171 * allowing it to appear.
1173 msleep(intel_dp
->backlight_on_delay
);
1174 pp
= ironlake_get_pp_control(intel_dp
);
1175 pp
|= EDP_BLC_ENABLE
;
1177 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1179 I915_WRITE(pp_ctrl_reg
, pp
);
1180 POSTING_READ(pp_ctrl_reg
);
1182 intel_panel_enable_backlight(dev
, pipe
);
1185 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1187 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1192 if (!is_edp(intel_dp
))
1195 intel_panel_disable_backlight(dev
);
1197 DRM_DEBUG_KMS("\n");
1198 pp
= ironlake_get_pp_control(intel_dp
);
1199 pp
&= ~EDP_BLC_ENABLE
;
1201 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1203 I915_WRITE(pp_ctrl_reg
, pp
);
1204 POSTING_READ(pp_ctrl_reg
);
1205 msleep(intel_dp
->backlight_off_delay
);
1208 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1210 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1211 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1212 struct drm_device
*dev
= crtc
->dev
;
1213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1216 assert_pipe_disabled(dev_priv
,
1217 to_intel_crtc(crtc
)->pipe
);
1219 DRM_DEBUG_KMS("\n");
1220 dpa_ctl
= I915_READ(DP_A
);
1221 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1222 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1224 /* We don't adjust intel_dp->DP while tearing down the link, to
1225 * facilitate link retraining (e.g. after hotplug). Hence clear all
1226 * enable bits here to ensure that we don't enable too much. */
1227 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1228 intel_dp
->DP
|= DP_PLL_ENABLE
;
1229 I915_WRITE(DP_A
, intel_dp
->DP
);
1234 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1236 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1237 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1238 struct drm_device
*dev
= crtc
->dev
;
1239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1242 assert_pipe_disabled(dev_priv
,
1243 to_intel_crtc(crtc
)->pipe
);
1245 dpa_ctl
= I915_READ(DP_A
);
1246 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1247 "dp pll off, should be on\n");
1248 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1250 /* We can't rely on the value tracked for the DP register in
1251 * intel_dp->DP because link_down must not change that (otherwise link
1252 * re-training will fail. */
1253 dpa_ctl
&= ~DP_PLL_ENABLE
;
1254 I915_WRITE(DP_A
, dpa_ctl
);
1259 /* If the sink supports it, try to set the power state appropriately */
1260 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1264 /* Should have a valid DPCD by this point */
1265 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1268 if (mode
!= DRM_MODE_DPMS_ON
) {
1269 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1272 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1275 * When turning on, we need to retry for 1ms to give the sink
1278 for (i
= 0; i
< 3; i
++) {
1279 ret
= intel_dp_aux_native_write_1(intel_dp
,
1289 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1292 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1293 struct drm_device
*dev
= encoder
->base
.dev
;
1294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1295 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1297 if (!(tmp
& DP_PORT_EN
))
1300 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1301 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1302 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1303 *pipe
= PORT_TO_PIPE(tmp
);
1309 switch (intel_dp
->output_reg
) {
1311 trans_sel
= TRANS_DP_PORT_SEL_B
;
1314 trans_sel
= TRANS_DP_PORT_SEL_C
;
1317 trans_sel
= TRANS_DP_PORT_SEL_D
;
1324 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1325 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1331 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1332 intel_dp
->output_reg
);
1338 static void intel_disable_dp(struct intel_encoder
*encoder
)
1340 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1342 /* Make sure the panel is off before trying to change the mode. But also
1343 * ensure that we have vdd while we switch off the panel. */
1344 ironlake_edp_panel_vdd_on(intel_dp
);
1345 ironlake_edp_backlight_off(intel_dp
);
1346 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1347 ironlake_edp_panel_off(intel_dp
);
1349 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1350 if (!is_cpu_edp(intel_dp
))
1351 intel_dp_link_down(intel_dp
);
1354 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1356 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1357 struct drm_device
*dev
= encoder
->base
.dev
;
1359 if (is_cpu_edp(intel_dp
)) {
1360 intel_dp_link_down(intel_dp
);
1361 if (!IS_VALLEYVIEW(dev
))
1362 ironlake_edp_pll_off(intel_dp
);
1366 static void intel_enable_dp(struct intel_encoder
*encoder
)
1368 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1369 struct drm_device
*dev
= encoder
->base
.dev
;
1370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1371 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1373 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1376 ironlake_edp_panel_vdd_on(intel_dp
);
1377 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1378 intel_dp_start_link_train(intel_dp
);
1379 ironlake_edp_panel_on(intel_dp
);
1380 ironlake_edp_panel_vdd_off(intel_dp
, true);
1381 intel_dp_complete_link_train(intel_dp
);
1382 intel_dp_stop_link_train(intel_dp
);
1383 ironlake_edp_backlight_on(intel_dp
);
1386 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1388 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1389 struct drm_device
*dev
= encoder
->base
.dev
;
1391 if (is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
))
1392 ironlake_edp_pll_on(intel_dp
);
1396 * Native read with retry for link status and receiver capability reads for
1397 * cases where the sink may still be asleep.
1400 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1401 uint8_t *recv
, int recv_bytes
)
1406 * Sinks are *supposed* to come up within 1ms from an off state,
1407 * but we're also supposed to retry 3 times per the spec.
1409 for (i
= 0; i
< 3; i
++) {
1410 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1412 if (ret
== recv_bytes
)
1421 * Fetch AUX CH registers 0x202 - 0x207 which contain
1422 * link status information
1425 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1427 return intel_dp_aux_native_read_retry(intel_dp
,
1430 DP_LINK_STATUS_SIZE
);
1434 static char *voltage_names
[] = {
1435 "0.4V", "0.6V", "0.8V", "1.2V"
1437 static char *pre_emph_names
[] = {
1438 "0dB", "3.5dB", "6dB", "9.5dB"
1440 static char *link_train_names
[] = {
1441 "pattern 1", "pattern 2", "idle", "off"
1446 * These are source-specific values; current Intel hardware supports
1447 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1451 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1453 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1455 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1456 return DP_TRAIN_VOLTAGE_SWING_800
;
1457 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1458 return DP_TRAIN_VOLTAGE_SWING_1200
;
1460 return DP_TRAIN_VOLTAGE_SWING_800
;
1464 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1466 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1469 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1470 case DP_TRAIN_VOLTAGE_SWING_400
:
1471 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1472 case DP_TRAIN_VOLTAGE_SWING_600
:
1473 return DP_TRAIN_PRE_EMPHASIS_6
;
1474 case DP_TRAIN_VOLTAGE_SWING_800
:
1475 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1476 case DP_TRAIN_VOLTAGE_SWING_1200
:
1478 return DP_TRAIN_PRE_EMPHASIS_0
;
1480 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1481 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1482 case DP_TRAIN_VOLTAGE_SWING_400
:
1483 return DP_TRAIN_PRE_EMPHASIS_6
;
1484 case DP_TRAIN_VOLTAGE_SWING_600
:
1485 case DP_TRAIN_VOLTAGE_SWING_800
:
1486 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1488 return DP_TRAIN_PRE_EMPHASIS_0
;
1491 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1492 case DP_TRAIN_VOLTAGE_SWING_400
:
1493 return DP_TRAIN_PRE_EMPHASIS_6
;
1494 case DP_TRAIN_VOLTAGE_SWING_600
:
1495 return DP_TRAIN_PRE_EMPHASIS_6
;
1496 case DP_TRAIN_VOLTAGE_SWING_800
:
1497 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1498 case DP_TRAIN_VOLTAGE_SWING_1200
:
1500 return DP_TRAIN_PRE_EMPHASIS_0
;
1506 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1511 uint8_t voltage_max
;
1512 uint8_t preemph_max
;
1514 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1515 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
1516 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
1524 voltage_max
= intel_dp_voltage_max(intel_dp
);
1525 if (v
>= voltage_max
)
1526 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1528 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1529 if (p
>= preemph_max
)
1530 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1532 for (lane
= 0; lane
< 4; lane
++)
1533 intel_dp
->train_set
[lane
] = v
| p
;
1537 intel_gen4_signal_levels(uint8_t train_set
)
1539 uint32_t signal_levels
= 0;
1541 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1542 case DP_TRAIN_VOLTAGE_SWING_400
:
1544 signal_levels
|= DP_VOLTAGE_0_4
;
1546 case DP_TRAIN_VOLTAGE_SWING_600
:
1547 signal_levels
|= DP_VOLTAGE_0_6
;
1549 case DP_TRAIN_VOLTAGE_SWING_800
:
1550 signal_levels
|= DP_VOLTAGE_0_8
;
1552 case DP_TRAIN_VOLTAGE_SWING_1200
:
1553 signal_levels
|= DP_VOLTAGE_1_2
;
1556 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1557 case DP_TRAIN_PRE_EMPHASIS_0
:
1559 signal_levels
|= DP_PRE_EMPHASIS_0
;
1561 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1562 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1564 case DP_TRAIN_PRE_EMPHASIS_6
:
1565 signal_levels
|= DP_PRE_EMPHASIS_6
;
1567 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1568 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1571 return signal_levels
;
1574 /* Gen6's DP voltage swing and pre-emphasis control */
1576 intel_gen6_edp_signal_levels(uint8_t train_set
)
1578 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1579 DP_TRAIN_PRE_EMPHASIS_MASK
);
1580 switch (signal_levels
) {
1581 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1582 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1583 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1584 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1585 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1586 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1587 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1588 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1589 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1590 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1591 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1592 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1593 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1594 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1596 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1597 "0x%x\n", signal_levels
);
1598 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1602 /* Gen7's DP voltage swing and pre-emphasis control */
1604 intel_gen7_edp_signal_levels(uint8_t train_set
)
1606 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1607 DP_TRAIN_PRE_EMPHASIS_MASK
);
1608 switch (signal_levels
) {
1609 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1610 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1611 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1612 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1613 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1614 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1616 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1617 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1618 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1619 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1621 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1622 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1623 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1624 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1627 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1628 "0x%x\n", signal_levels
);
1629 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1633 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1635 intel_hsw_signal_levels(uint8_t train_set
)
1637 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1638 DP_TRAIN_PRE_EMPHASIS_MASK
);
1639 switch (signal_levels
) {
1640 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1641 return DDI_BUF_EMP_400MV_0DB_HSW
;
1642 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1643 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1644 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1645 return DDI_BUF_EMP_400MV_6DB_HSW
;
1646 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1647 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1649 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1650 return DDI_BUF_EMP_600MV_0DB_HSW
;
1651 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1652 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1653 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1654 return DDI_BUF_EMP_600MV_6DB_HSW
;
1656 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1657 return DDI_BUF_EMP_800MV_0DB_HSW
;
1658 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1659 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1661 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1662 "0x%x\n", signal_levels
);
1663 return DDI_BUF_EMP_400MV_0DB_HSW
;
1667 /* Properly updates "DP" with the correct signal levels. */
1669 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
1671 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1672 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1673 uint32_t signal_levels
, mask
;
1674 uint8_t train_set
= intel_dp
->train_set
[0];
1677 signal_levels
= intel_hsw_signal_levels(train_set
);
1678 mask
= DDI_BUF_EMP_MASK
;
1679 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1680 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
1681 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
1682 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1683 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
1684 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
1686 signal_levels
= intel_gen4_signal_levels(train_set
);
1687 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
1690 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
1692 *DP
= (*DP
& ~mask
) | signal_levels
;
1696 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1697 uint32_t dp_reg_value
,
1698 uint8_t dp_train_pat
)
1700 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1701 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 enum port port
= intel_dig_port
->port
;
1707 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
1709 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1710 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1712 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1714 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1715 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1716 case DP_TRAINING_PATTERN_DISABLE
:
1717 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1720 case DP_TRAINING_PATTERN_1
:
1721 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1723 case DP_TRAINING_PATTERN_2
:
1724 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1726 case DP_TRAINING_PATTERN_3
:
1727 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1730 I915_WRITE(DP_TP_CTL(port
), temp
);
1732 } else if (HAS_PCH_CPT(dev
) &&
1733 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1734 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1736 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1737 case DP_TRAINING_PATTERN_DISABLE
:
1738 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1740 case DP_TRAINING_PATTERN_1
:
1741 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1743 case DP_TRAINING_PATTERN_2
:
1744 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1746 case DP_TRAINING_PATTERN_3
:
1747 DRM_ERROR("DP training pattern 3 not supported\n");
1748 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1753 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1755 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1756 case DP_TRAINING_PATTERN_DISABLE
:
1757 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1759 case DP_TRAINING_PATTERN_1
:
1760 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1762 case DP_TRAINING_PATTERN_2
:
1763 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1765 case DP_TRAINING_PATTERN_3
:
1766 DRM_ERROR("DP training pattern 3 not supported\n");
1767 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1772 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1773 POSTING_READ(intel_dp
->output_reg
);
1775 intel_dp_aux_native_write_1(intel_dp
,
1776 DP_TRAINING_PATTERN_SET
,
1779 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1780 DP_TRAINING_PATTERN_DISABLE
) {
1781 ret
= intel_dp_aux_native_write(intel_dp
,
1782 DP_TRAINING_LANE0_SET
,
1783 intel_dp
->train_set
,
1784 intel_dp
->lane_count
);
1785 if (ret
!= intel_dp
->lane_count
)
1792 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
1794 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1795 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1797 enum port port
= intel_dig_port
->port
;
1803 val
= I915_READ(DP_TP_CTL(port
));
1804 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1805 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1806 I915_WRITE(DP_TP_CTL(port
), val
);
1809 * On PORT_A we can have only eDP in SST mode. There the only reason
1810 * we need to set idle transmission mode is to work around a HW issue
1811 * where we enable the pipe while not in idle link-training mode.
1812 * In this case there is requirement to wait for a minimum number of
1813 * idle patterns to be sent.
1818 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
1820 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1823 /* Enable corresponding port and start training pattern 1 */
1825 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1827 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
1828 struct drm_device
*dev
= encoder
->dev
;
1831 bool clock_recovery
= false;
1832 int voltage_tries
, loop_tries
;
1833 uint32_t DP
= intel_dp
->DP
;
1836 intel_ddi_prepare_link_retrain(encoder
);
1838 /* Write the link configuration data */
1839 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1840 intel_dp
->link_configuration
,
1841 DP_LINK_CONFIGURATION_SIZE
);
1845 memset(intel_dp
->train_set
, 0, 4);
1849 clock_recovery
= false;
1851 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1852 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1854 intel_dp_set_signal_levels(intel_dp
, &DP
);
1856 /* Set training pattern 1 */
1857 if (!intel_dp_set_link_train(intel_dp
, DP
,
1858 DP_TRAINING_PATTERN_1
|
1859 DP_LINK_SCRAMBLING_DISABLE
))
1862 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
1863 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1864 DRM_ERROR("failed to get link status\n");
1868 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1869 DRM_DEBUG_KMS("clock recovery OK\n");
1870 clock_recovery
= true;
1874 /* Check to see if we've tried the max voltage */
1875 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1876 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1878 if (i
== intel_dp
->lane_count
) {
1880 if (loop_tries
== 5) {
1881 DRM_DEBUG_KMS("too many full retries, give up\n");
1884 memset(intel_dp
->train_set
, 0, 4);
1889 /* Check to see if we've tried the same voltage 5 times */
1890 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1892 if (voltage_tries
== 5) {
1893 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1898 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1900 /* Compute new intel_dp->train_set as requested by target */
1901 intel_get_adjust_train(intel_dp
, link_status
);
1908 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1910 bool channel_eq
= false;
1911 int tries
, cr_tries
;
1912 uint32_t DP
= intel_dp
->DP
;
1914 /* channel equalization */
1919 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1922 DRM_ERROR("failed to train DP, aborting\n");
1923 intel_dp_link_down(intel_dp
);
1927 intel_dp_set_signal_levels(intel_dp
, &DP
);
1929 /* channel eq pattern */
1930 if (!intel_dp_set_link_train(intel_dp
, DP
,
1931 DP_TRAINING_PATTERN_2
|
1932 DP_LINK_SCRAMBLING_DISABLE
))
1935 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
1936 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1939 /* Make sure clock is still ok */
1940 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1941 intel_dp_start_link_train(intel_dp
);
1946 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
1951 /* Try 5 times, then try clock recovery if that fails */
1953 intel_dp_link_down(intel_dp
);
1954 intel_dp_start_link_train(intel_dp
);
1960 /* Compute new intel_dp->train_set as requested by target */
1961 intel_get_adjust_train(intel_dp
, link_status
);
1965 intel_dp_set_idle_link_train(intel_dp
);
1970 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
1974 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
1976 intel_dp_set_link_train(intel_dp
, intel_dp
->DP
,
1977 DP_TRAINING_PATTERN_DISABLE
);
1981 intel_dp_link_down(struct intel_dp
*intel_dp
)
1983 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1984 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 struct intel_crtc
*intel_crtc
=
1987 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
1988 uint32_t DP
= intel_dp
->DP
;
1991 * DDI code has a strict mode set sequence and we should try to respect
1992 * it, otherwise we might hang the machine in many different ways. So we
1993 * really should be disabling the port only on a complete crtc_disable
1994 * sequence. This function is just called under two conditions on DDI
1996 * - Link train failed while doing crtc_enable, and on this case we
1997 * really should respect the mode set sequence and wait for a
1999 * - Someone turned the monitor off and intel_dp_check_link_status
2000 * called us. We don't need to disable the whole port on this case, so
2001 * when someone turns the monitor on again,
2002 * intel_ddi_prepare_link_retrain will take care of redoing the link
2008 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2011 DRM_DEBUG_KMS("\n");
2013 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
2014 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2015 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2017 DP
&= ~DP_LINK_TRAIN_MASK
;
2018 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2020 POSTING_READ(intel_dp
->output_reg
);
2022 /* We don't really know why we're doing this */
2023 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2025 if (HAS_PCH_IBX(dev
) &&
2026 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2027 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2029 /* Hardware workaround: leaving our transcoder select
2030 * set to transcoder B while it's off will prevent the
2031 * corresponding HDMI output on transcoder A.
2033 * Combine this with another hardware workaround:
2034 * transcoder select bit can only be cleared while the
2037 DP
&= ~DP_PIPEB_SELECT
;
2038 I915_WRITE(intel_dp
->output_reg
, DP
);
2040 /* Changes to enable or select take place the vblank
2041 * after being written.
2043 if (WARN_ON(crtc
== NULL
)) {
2044 /* We should never try to disable a port without a crtc
2045 * attached. For paranoia keep the code around for a
2047 POSTING_READ(intel_dp
->output_reg
);
2050 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2053 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2054 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2055 POSTING_READ(intel_dp
->output_reg
);
2056 msleep(intel_dp
->panel_power_down_delay
);
2060 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2062 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2064 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2065 sizeof(intel_dp
->dpcd
)) == 0)
2066 return false; /* aux transfer failed */
2068 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2069 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2070 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2072 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2073 return false; /* DPCD not present */
2075 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2076 DP_DWN_STRM_PORT_PRESENT
))
2077 return true; /* native DP sink */
2079 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2080 return true; /* no per-port downstream info */
2082 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2083 intel_dp
->downstream_ports
,
2084 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2085 return false; /* downstream port status fetch failed */
2091 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2095 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2098 ironlake_edp_panel_vdd_on(intel_dp
);
2100 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2101 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2102 buf
[0], buf
[1], buf
[2]);
2104 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2105 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2106 buf
[0], buf
[1], buf
[2]);
2108 ironlake_edp_panel_vdd_off(intel_dp
, false);
2112 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2116 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2117 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2118 sink_irq_vector
, 1);
2126 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2128 /* NAK by default */
2129 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2133 * According to DP spec
2136 * 2. Configure link according to Receiver Capabilities
2137 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2138 * 4. Check link status on receipt of hot-plug interrupt
2142 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2144 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2146 u8 link_status
[DP_LINK_STATUS_SIZE
];
2148 if (!intel_encoder
->connectors_active
)
2151 if (WARN_ON(!intel_encoder
->base
.crtc
))
2154 /* Try to read receiver status if the link appears to be up */
2155 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2156 intel_dp_link_down(intel_dp
);
2160 /* Now read the DPCD to see if it's actually running */
2161 if (!intel_dp_get_dpcd(intel_dp
)) {
2162 intel_dp_link_down(intel_dp
);
2166 /* Try to read the source of the interrupt */
2167 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2168 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2169 /* Clear interrupt source */
2170 intel_dp_aux_native_write_1(intel_dp
,
2171 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2174 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2175 intel_dp_handle_test_request(intel_dp
);
2176 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2177 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2180 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2181 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2182 drm_get_encoder_name(&intel_encoder
->base
));
2183 intel_dp_start_link_train(intel_dp
);
2184 intel_dp_complete_link_train(intel_dp
);
2185 intel_dp_stop_link_train(intel_dp
);
2189 /* XXX this is probably wrong for multiple downstream ports */
2190 static enum drm_connector_status
2191 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2193 uint8_t *dpcd
= intel_dp
->dpcd
;
2197 if (!intel_dp_get_dpcd(intel_dp
))
2198 return connector_status_disconnected
;
2200 /* if there's no downstream port, we're done */
2201 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2202 return connector_status_connected
;
2204 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2205 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2208 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2210 return connector_status_unknown
;
2211 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2212 : connector_status_disconnected
;
2215 /* If no HPD, poke DDC gently */
2216 if (drm_probe_ddc(&intel_dp
->adapter
))
2217 return connector_status_connected
;
2219 /* Well we tried, say unknown for unreliable port types */
2220 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2221 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2222 return connector_status_unknown
;
2224 /* Anything else is out of spec, warn and ignore */
2225 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2226 return connector_status_disconnected
;
2229 static enum drm_connector_status
2230 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2232 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2234 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2235 enum drm_connector_status status
;
2237 /* Can't disconnect eDP, but you can close the lid... */
2238 if (is_edp(intel_dp
)) {
2239 status
= intel_panel_detect(dev
);
2240 if (status
== connector_status_unknown
)
2241 status
= connector_status_connected
;
2245 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
2246 return connector_status_disconnected
;
2248 return intel_dp_detect_dpcd(intel_dp
);
2251 static enum drm_connector_status
2252 g4x_dp_detect(struct intel_dp
*intel_dp
)
2254 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2256 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2259 /* Can't disconnect eDP, but you can close the lid... */
2260 if (is_edp(intel_dp
)) {
2261 enum drm_connector_status status
;
2263 status
= intel_panel_detect(dev
);
2264 if (status
== connector_status_unknown
)
2265 status
= connector_status_connected
;
2269 switch (intel_dig_port
->port
) {
2271 bit
= PORTB_HOTPLUG_LIVE_STATUS
;
2274 bit
= PORTC_HOTPLUG_LIVE_STATUS
;
2277 bit
= PORTD_HOTPLUG_LIVE_STATUS
;
2280 return connector_status_unknown
;
2283 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2284 return connector_status_disconnected
;
2286 return intel_dp_detect_dpcd(intel_dp
);
2289 static struct edid
*
2290 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2292 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2294 /* use cached edid if we have one */
2295 if (intel_connector
->edid
) {
2300 if (IS_ERR(intel_connector
->edid
))
2303 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2304 edid
= kmalloc(size
, GFP_KERNEL
);
2308 memcpy(edid
, intel_connector
->edid
, size
);
2312 return drm_get_edid(connector
, adapter
);
2316 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2318 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2320 /* use cached edid if we have one */
2321 if (intel_connector
->edid
) {
2323 if (IS_ERR(intel_connector
->edid
))
2326 return intel_connector_update_modes(connector
,
2327 intel_connector
->edid
);
2330 return intel_ddc_get_modes(connector
, adapter
);
2333 static enum drm_connector_status
2334 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2336 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2337 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2338 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2339 struct drm_device
*dev
= connector
->dev
;
2340 enum drm_connector_status status
;
2341 struct edid
*edid
= NULL
;
2343 intel_dp
->has_audio
= false;
2345 if (HAS_PCH_SPLIT(dev
))
2346 status
= ironlake_dp_detect(intel_dp
);
2348 status
= g4x_dp_detect(intel_dp
);
2350 if (status
!= connector_status_connected
)
2353 intel_dp_probe_oui(intel_dp
);
2355 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2356 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2358 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2360 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2365 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
2366 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2367 return connector_status_connected
;
2370 static int intel_dp_get_modes(struct drm_connector
*connector
)
2372 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2373 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2374 struct drm_device
*dev
= connector
->dev
;
2377 /* We should parse the EDID data and find out if it has an audio sink
2380 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2384 /* if eDP has no EDID, fall back to fixed mode */
2385 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2386 struct drm_display_mode
*mode
;
2387 mode
= drm_mode_duplicate(dev
,
2388 intel_connector
->panel
.fixed_mode
);
2390 drm_mode_probed_add(connector
, mode
);
2398 intel_dp_detect_audio(struct drm_connector
*connector
)
2400 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2402 bool has_audio
= false;
2404 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2406 has_audio
= drm_detect_monitor_audio(edid
);
2414 intel_dp_set_property(struct drm_connector
*connector
,
2415 struct drm_property
*property
,
2418 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2419 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2420 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
2421 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2424 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
2428 if (property
== dev_priv
->force_audio_property
) {
2432 if (i
== intel_dp
->force_audio
)
2435 intel_dp
->force_audio
= i
;
2437 if (i
== HDMI_AUDIO_AUTO
)
2438 has_audio
= intel_dp_detect_audio(connector
);
2440 has_audio
= (i
== HDMI_AUDIO_ON
);
2442 if (has_audio
== intel_dp
->has_audio
)
2445 intel_dp
->has_audio
= has_audio
;
2449 if (property
== dev_priv
->broadcast_rgb_property
) {
2450 bool old_auto
= intel_dp
->color_range_auto
;
2451 uint32_t old_range
= intel_dp
->color_range
;
2454 case INTEL_BROADCAST_RGB_AUTO
:
2455 intel_dp
->color_range_auto
= true;
2457 case INTEL_BROADCAST_RGB_FULL
:
2458 intel_dp
->color_range_auto
= false;
2459 intel_dp
->color_range
= 0;
2461 case INTEL_BROADCAST_RGB_LIMITED
:
2462 intel_dp
->color_range_auto
= false;
2463 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
2469 if (old_auto
== intel_dp
->color_range_auto
&&
2470 old_range
== intel_dp
->color_range
)
2476 if (is_edp(intel_dp
) &&
2477 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
2478 if (val
== DRM_MODE_SCALE_NONE
) {
2479 DRM_DEBUG_KMS("no scaling not supported\n");
2483 if (intel_connector
->panel
.fitting_mode
== val
) {
2484 /* the eDP scaling property is not changed */
2487 intel_connector
->panel
.fitting_mode
= val
;
2495 if (intel_encoder
->base
.crtc
)
2496 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
2502 intel_dp_destroy(struct drm_connector
*connector
)
2504 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2505 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2507 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
2508 kfree(intel_connector
->edid
);
2510 if (is_edp(intel_dp
))
2511 intel_panel_fini(&intel_connector
->panel
);
2513 drm_sysfs_connector_remove(connector
);
2514 drm_connector_cleanup(connector
);
2518 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2520 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2521 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2522 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2524 i2c_del_adapter(&intel_dp
->adapter
);
2525 drm_encoder_cleanup(encoder
);
2526 if (is_edp(intel_dp
)) {
2527 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2528 mutex_lock(&dev
->mode_config
.mutex
);
2529 ironlake_panel_vdd_off_sync(intel_dp
);
2530 mutex_unlock(&dev
->mode_config
.mutex
);
2532 kfree(intel_dig_port
);
2535 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2536 .mode_set
= intel_dp_mode_set
,
2539 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2540 .dpms
= intel_connector_dpms
,
2541 .detect
= intel_dp_detect
,
2542 .fill_modes
= drm_helper_probe_single_connector_modes
,
2543 .set_property
= intel_dp_set_property
,
2544 .destroy
= intel_dp_destroy
,
2547 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2548 .get_modes
= intel_dp_get_modes
,
2549 .mode_valid
= intel_dp_mode_valid
,
2550 .best_encoder
= intel_best_encoder
,
2553 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2554 .destroy
= intel_dp_encoder_destroy
,
2558 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2560 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2562 intel_dp_check_link_status(intel_dp
);
2565 /* Return which DP Port should be selected for Transcoder DP control */
2567 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2569 struct drm_device
*dev
= crtc
->dev
;
2570 struct intel_encoder
*intel_encoder
;
2571 struct intel_dp
*intel_dp
;
2573 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2574 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2576 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2577 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2578 return intel_dp
->output_reg
;
2584 /* check the VBT to see whether the eDP is on DP-D port */
2585 bool intel_dpd_is_edp(struct drm_device
*dev
)
2587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2588 struct child_device_config
*p_child
;
2591 if (!dev_priv
->child_dev_num
)
2594 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2595 p_child
= dev_priv
->child_dev
+ i
;
2597 if (p_child
->dvo_port
== PORT_IDPD
&&
2598 p_child
->device_type
== DEVICE_TYPE_eDP
)
2605 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2607 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2609 intel_attach_force_audio_property(connector
);
2610 intel_attach_broadcast_rgb_property(connector
);
2611 intel_dp
->color_range_auto
= true;
2613 if (is_edp(intel_dp
)) {
2614 drm_mode_create_scaling_mode_property(connector
->dev
);
2615 drm_object_attach_property(
2617 connector
->dev
->mode_config
.scaling_mode_property
,
2618 DRM_MODE_SCALE_ASPECT
);
2619 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
2624 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
2625 struct intel_dp
*intel_dp
,
2626 struct edp_power_seq
*out
)
2628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2629 struct edp_power_seq cur
, vbt
, spec
, final
;
2630 u32 pp_on
, pp_off
, pp_div
, pp
;
2631 int pp_control_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
2633 if (HAS_PCH_SPLIT(dev
)) {
2634 pp_control_reg
= PCH_PP_CONTROL
;
2635 pp_on_reg
= PCH_PP_ON_DELAYS
;
2636 pp_off_reg
= PCH_PP_OFF_DELAYS
;
2637 pp_div_reg
= PCH_PP_DIVISOR
;
2639 pp_control_reg
= PIPEA_PP_CONTROL
;
2640 pp_on_reg
= PIPEA_PP_ON_DELAYS
;
2641 pp_off_reg
= PIPEA_PP_OFF_DELAYS
;
2642 pp_div_reg
= PIPEA_PP_DIVISOR
;
2645 /* Workaround: Need to write PP_CONTROL with the unlock key as
2646 * the very first thing. */
2647 pp
= ironlake_get_pp_control(intel_dp
);
2648 I915_WRITE(pp_control_reg
, pp
);
2650 pp_on
= I915_READ(pp_on_reg
);
2651 pp_off
= I915_READ(pp_off_reg
);
2652 pp_div
= I915_READ(pp_div_reg
);
2654 /* Pull timing values out of registers */
2655 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2656 PANEL_POWER_UP_DELAY_SHIFT
;
2658 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2659 PANEL_LIGHT_ON_DELAY_SHIFT
;
2661 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2662 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2664 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2665 PANEL_POWER_DOWN_DELAY_SHIFT
;
2667 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2668 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2670 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2671 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2673 vbt
= dev_priv
->edp
.pps
;
2675 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2676 * our hw here, which are all in 100usec. */
2677 spec
.t1_t3
= 210 * 10;
2678 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
2679 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
2680 spec
.t10
= 500 * 10;
2681 /* This one is special and actually in units of 100ms, but zero
2682 * based in the hw (so we need to add 100 ms). But the sw vbt
2683 * table multiplies it with 1000 to make it in units of 100usec,
2685 spec
.t11_t12
= (510 + 100) * 10;
2687 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2688 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2690 /* Use the max of the register settings and vbt. If both are
2691 * unset, fall back to the spec limits. */
2692 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2694 max(cur.field, vbt.field))
2695 assign_final(t1_t3
);
2699 assign_final(t11_t12
);
2702 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2703 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2704 intel_dp
->backlight_on_delay
= get_delay(t8
);
2705 intel_dp
->backlight_off_delay
= get_delay(t9
);
2706 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2707 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2710 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2711 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2712 intel_dp
->panel_power_cycle_delay
);
2714 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2715 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2722 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
2723 struct intel_dp
*intel_dp
,
2724 struct edp_power_seq
*seq
)
2726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2727 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
2728 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
2729 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
2731 if (HAS_PCH_SPLIT(dev
)) {
2732 pp_on_reg
= PCH_PP_ON_DELAYS
;
2733 pp_off_reg
= PCH_PP_OFF_DELAYS
;
2734 pp_div_reg
= PCH_PP_DIVISOR
;
2736 pp_on_reg
= PIPEA_PP_ON_DELAYS
;
2737 pp_off_reg
= PIPEA_PP_OFF_DELAYS
;
2738 pp_div_reg
= PIPEA_PP_DIVISOR
;
2741 if (IS_VALLEYVIEW(dev
))
2742 port_sel
= I915_READ(pp_on_reg
) & 0xc0000000;
2744 /* And finally store the new values in the power sequencer. */
2745 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
2746 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
2747 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
2748 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
2749 /* Compute the divisor for the pp clock, simply match the Bspec
2751 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
2752 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
2753 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
2755 /* Haswell doesn't have any port selection bits for the panel
2756 * power sequencer any more. */
2757 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
2758 if (is_cpu_edp(intel_dp
))
2759 port_sel
= PANEL_POWER_PORT_DP_A
;
2761 port_sel
= PANEL_POWER_PORT_DP_D
;
2766 I915_WRITE(pp_on_reg
, pp_on
);
2767 I915_WRITE(pp_off_reg
, pp_off
);
2768 I915_WRITE(pp_div_reg
, pp_div
);
2770 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2771 I915_READ(pp_on_reg
),
2772 I915_READ(pp_off_reg
),
2773 I915_READ(pp_div_reg
));
2777 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
2778 struct intel_connector
*intel_connector
)
2780 struct drm_connector
*connector
= &intel_connector
->base
;
2781 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2782 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2783 struct drm_device
*dev
= intel_encoder
->base
.dev
;
2784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2785 struct drm_display_mode
*fixed_mode
= NULL
;
2786 struct edp_power_seq power_seq
= { 0 };
2787 enum port port
= intel_dig_port
->port
;
2788 const char *name
= NULL
;
2791 /* Preserve the current hw state. */
2792 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2793 intel_dp
->attached_connector
= intel_connector
;
2795 if (HAS_PCH_SPLIT(dev
) && port
== PORT_D
)
2796 if (intel_dpd_is_edp(dev
))
2797 intel_dp
->is_pch_edp
= true;
2800 * FIXME : We need to initialize built-in panels before external panels.
2801 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2803 if (IS_VALLEYVIEW(dev
) && port
== PORT_C
) {
2804 type
= DRM_MODE_CONNECTOR_eDP
;
2805 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2806 } else if (port
== PORT_A
|| is_pch_edp(intel_dp
)) {
2807 type
= DRM_MODE_CONNECTOR_eDP
;
2808 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2810 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2811 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2814 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2817 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2818 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2820 connector
->interlace_allowed
= true;
2821 connector
->doublescan_allowed
= 0;
2823 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2824 ironlake_panel_vdd_work
);
2826 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2827 drm_sysfs_connector_add(connector
);
2830 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
2832 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2834 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
2836 switch (intel_dig_port
->port
) {
2838 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
2841 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
2844 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
2847 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
2854 /* Set up the DDC bus. */
2857 intel_encoder
->hpd_pin
= HPD_PORT_A
;
2861 intel_encoder
->hpd_pin
= HPD_PORT_B
;
2865 intel_encoder
->hpd_pin
= HPD_PORT_C
;
2869 intel_encoder
->hpd_pin
= HPD_PORT_D
;
2876 if (is_edp(intel_dp
))
2877 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2879 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2881 /* Cache DPCD and EDID for edp. */
2882 if (is_edp(intel_dp
)) {
2884 struct drm_display_mode
*scan
;
2887 ironlake_edp_panel_vdd_on(intel_dp
);
2888 ret
= intel_dp_get_dpcd(intel_dp
);
2889 ironlake_edp_panel_vdd_off(intel_dp
, false);
2892 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2893 dev_priv
->no_aux_handshake
=
2894 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2895 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2897 /* if this fails, presume the device is a ghost */
2898 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2899 intel_dp_encoder_destroy(&intel_encoder
->base
);
2900 intel_dp_destroy(connector
);
2904 /* We now know it's not a ghost, init power sequence regs. */
2905 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2908 ironlake_edp_panel_vdd_on(intel_dp
);
2909 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2911 if (drm_add_edid_modes(connector
, edid
)) {
2912 drm_mode_connector_update_edid_property(connector
, edid
);
2913 drm_edid_to_eld(connector
, edid
);
2916 edid
= ERR_PTR(-EINVAL
);
2919 edid
= ERR_PTR(-ENOENT
);
2921 intel_connector
->edid
= edid
;
2923 /* prefer fixed mode from EDID if available */
2924 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
2925 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2926 fixed_mode
= drm_mode_duplicate(dev
, scan
);
2931 /* fallback to VBT if available for eDP */
2932 if (!fixed_mode
&& dev_priv
->lfp_lvds_vbt_mode
) {
2933 fixed_mode
= drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2935 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2938 ironlake_edp_panel_vdd_off(intel_dp
, false);
2941 if (is_edp(intel_dp
)) {
2942 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
2943 intel_panel_setup_backlight(connector
);
2946 intel_dp_add_properties(intel_dp
, connector
);
2948 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2949 * 0xd. Failure to do so will result in spurious interrupts being
2950 * generated on the port when a cable is not attached.
2952 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2953 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2954 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
2959 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2961 struct intel_digital_port
*intel_dig_port
;
2962 struct intel_encoder
*intel_encoder
;
2963 struct drm_encoder
*encoder
;
2964 struct intel_connector
*intel_connector
;
2966 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
2967 if (!intel_dig_port
)
2970 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2971 if (!intel_connector
) {
2972 kfree(intel_dig_port
);
2976 intel_encoder
= &intel_dig_port
->base
;
2977 encoder
= &intel_encoder
->base
;
2979 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2980 DRM_MODE_ENCODER_TMDS
);
2981 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2983 intel_encoder
->compute_config
= intel_dp_compute_config
;
2984 intel_encoder
->enable
= intel_enable_dp
;
2985 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2986 intel_encoder
->disable
= intel_disable_dp
;
2987 intel_encoder
->post_disable
= intel_post_disable_dp
;
2988 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2990 intel_dig_port
->port
= port
;
2991 intel_dig_port
->dp
.output_reg
= output_reg
;
2993 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2994 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2995 intel_encoder
->cloneable
= false;
2996 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2998 intel_dp_init_connector(intel_dig_port
, intel_connector
);