2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
116 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
117 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
121 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
123 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
124 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
126 switch (max_link_bw
) {
127 case DP_LINK_BW_1_62
:
130 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
131 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
132 INTEL_INFO(dev
)->gen
>= 8) &&
133 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
134 max_link_bw
= DP_LINK_BW_5_4
;
136 max_link_bw
= DP_LINK_BW_2_7
;
139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
141 max_link_bw
= DP_LINK_BW_1_62
;
147 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
149 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
150 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
151 u8 source_max
, sink_max
;
154 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
155 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
158 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
160 return min(source_max
, sink_max
);
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 * 270000 * 1 * 8 / 10 == 216000
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
181 intel_dp_link_required(int pixel_clock
, int bpp
)
183 return (pixel_clock
* bpp
+ 9) / 10;
187 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
189 return (max_link_clock
* max_lanes
* 8) / 10;
192 static enum drm_mode_status
193 intel_dp_mode_valid(struct drm_connector
*connector
,
194 struct drm_display_mode
*mode
)
196 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
197 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
198 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
199 int target_clock
= mode
->clock
;
200 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 if (is_edp(intel_dp
) && fixed_mode
) {
203 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
206 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
209 target_clock
= fixed_mode
->clock
;
212 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
213 max_lanes
= intel_dp_max_lane_count(intel_dp
);
215 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
216 mode_rate
= intel_dp_link_required(target_clock
, 18);
218 if (mode_rate
> max_rate
)
219 return MODE_CLOCK_HIGH
;
221 if (mode
->clock
< 10000)
222 return MODE_CLOCK_LOW
;
224 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
225 return MODE_H_ILLEGAL
;
231 pack_aux(const uint8_t *src
, int src_bytes
)
238 for (i
= 0; i
< src_bytes
; i
++)
239 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
244 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
249 for (i
= 0; i
< dst_bytes
; i
++)
250 dst
[i
] = src
>> ((3-i
) * 8);
253 /* hrawclock is 1/4 the FSB frequency */
255 intel_hrawclk(struct drm_device
*dev
)
257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
260 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
261 if (IS_VALLEYVIEW(dev
))
264 clkcfg
= I915_READ(CLKCFG
);
265 switch (clkcfg
& CLKCFG_FSB_MASK
) {
274 case CLKCFG_FSB_1067
:
276 case CLKCFG_FSB_1333
:
278 /* these two are just a guess; one of them might be right */
279 case CLKCFG_FSB_1600
:
280 case CLKCFG_FSB_1600_ALT
:
288 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
289 struct intel_dp
*intel_dp
);
291 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
292 struct intel_dp
*intel_dp
);
294 static void pps_lock(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
298 struct drm_device
*dev
= encoder
->base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum intel_display_power_domain power_domain
;
303 * See vlv_power_sequencer_reset() why we need
304 * a power domain reference here.
306 power_domain
= intel_display_port_power_domain(encoder
);
307 intel_display_power_get(dev_priv
, power_domain
);
309 mutex_lock(&dev_priv
->pps_mutex
);
312 static void pps_unlock(struct intel_dp
*intel_dp
)
314 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
315 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
316 struct drm_device
*dev
= encoder
->base
.dev
;
317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
318 enum intel_display_power_domain power_domain
;
320 mutex_unlock(&dev_priv
->pps_mutex
);
322 power_domain
= intel_display_port_power_domain(encoder
);
323 intel_display_power_put(dev_priv
, power_domain
);
327 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
329 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
330 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
332 enum pipe pipe
= intel_dp
->pps_pipe
;
336 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
337 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
338 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
341 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
342 pipe_name(pipe
), port_name(intel_dig_port
->port
));
344 /* Preserve the BIOS-computed detected bit. This is
345 * supposed to be read-only.
347 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
348 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
349 DP
|= DP_PORT_WIDTH(1);
350 DP
|= DP_LINK_TRAIN_PAT_1
;
352 if (IS_CHERRYVIEW(dev
))
353 DP
|= DP_PIPE_SELECT_CHV(pipe
);
354 else if (pipe
== PIPE_B
)
355 DP
|= DP_PIPEB_SELECT
;
357 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
360 * The DPLL for the pipe must be enabled for this to work.
361 * So enable temporarily it if it's not already enabled.
364 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
365 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
368 * Similar magic as in intel_dp_enable_port().
369 * We _must_ do this port enable + disable trick
370 * to make this power seqeuencer lock onto the port.
371 * Otherwise even VDD force bit won't work.
373 I915_WRITE(intel_dp
->output_reg
, DP
);
374 POSTING_READ(intel_dp
->output_reg
);
376 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
377 POSTING_READ(intel_dp
->output_reg
);
379 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
380 POSTING_READ(intel_dp
->output_reg
);
383 vlv_force_pll_off(dev
, pipe
);
387 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
389 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
390 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
392 struct intel_encoder
*encoder
;
393 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
396 lockdep_assert_held(&dev_priv
->pps_mutex
);
398 /* We should never land here with regular DP ports */
399 WARN_ON(!is_edp(intel_dp
));
401 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
402 return intel_dp
->pps_pipe
;
405 * We don't have power sequencer currently.
406 * Pick one that's not used by other ports.
408 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
410 struct intel_dp
*tmp
;
412 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
415 tmp
= enc_to_intel_dp(&encoder
->base
);
417 if (tmp
->pps_pipe
!= INVALID_PIPE
)
418 pipes
&= ~(1 << tmp
->pps_pipe
);
422 * Didn't find one. This should not happen since there
423 * are two power sequencers and up to two eDP ports.
425 if (WARN_ON(pipes
== 0))
428 pipe
= ffs(pipes
) - 1;
430 vlv_steal_power_sequencer(dev
, pipe
);
431 intel_dp
->pps_pipe
= pipe
;
433 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
434 pipe_name(intel_dp
->pps_pipe
),
435 port_name(intel_dig_port
->port
));
437 /* init power sequencer on this pipe and port */
438 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
439 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
442 * Even vdd force doesn't work until we've made
443 * the power sequencer lock in on the port.
445 vlv_power_sequencer_kick(intel_dp
);
447 return intel_dp
->pps_pipe
;
450 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
453 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
456 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
459 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
462 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
465 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
472 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
474 vlv_pipe_check pipe_check
)
478 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
479 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
480 PANEL_PORT_SELECT_MASK
;
482 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
485 if (!pipe_check(dev_priv
, pipe
))
495 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
497 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
498 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
500 enum port port
= intel_dig_port
->port
;
502 lockdep_assert_held(&dev_priv
->pps_mutex
);
504 /* try to find a pipe with this port selected */
505 /* first pick one where the panel is on */
506 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
508 /* didn't find one? pick one where vdd is on */
509 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
510 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
511 vlv_pipe_has_vdd_on
);
512 /* didn't find one? pick one with just the correct port */
513 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
514 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
517 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
518 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
519 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
524 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
525 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
527 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
528 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
531 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
533 struct drm_device
*dev
= dev_priv
->dev
;
534 struct intel_encoder
*encoder
;
536 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
540 * We can't grab pps_mutex here due to deadlock with power_domain
541 * mutex when power_domain functions are called while holding pps_mutex.
542 * That also means that in order to use pps_pipe the code needs to
543 * hold both a power domain reference and pps_mutex, and the power domain
544 * reference get/put must be done while _not_ holding pps_mutex.
545 * pps_{lock,unlock}() do these steps in the correct order, so one
546 * should use them always.
549 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
550 struct intel_dp
*intel_dp
;
552 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
555 intel_dp
= enc_to_intel_dp(&encoder
->base
);
556 intel_dp
->pps_pipe
= INVALID_PIPE
;
560 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
562 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
564 if (HAS_PCH_SPLIT(dev
))
565 return PCH_PP_CONTROL
;
567 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
570 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
572 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
574 if (HAS_PCH_SPLIT(dev
))
575 return PCH_PP_STATUS
;
577 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
580 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
581 This function only applicable when panel PM state is not to be tracked */
582 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
585 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
587 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
590 u32 pp_ctrl_reg
, pp_div_reg
;
592 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
597 if (IS_VALLEYVIEW(dev
)) {
598 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
600 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
601 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
602 pp_div
= I915_READ(pp_div_reg
);
603 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
605 /* 0x1F write to PP_DIV_REG sets max cycle delay */
606 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
607 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
608 msleep(intel_dp
->panel_power_cycle_delay
);
611 pps_unlock(intel_dp
);
616 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
618 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
621 lockdep_assert_held(&dev_priv
->pps_mutex
);
623 if (IS_VALLEYVIEW(dev
) &&
624 intel_dp
->pps_pipe
== INVALID_PIPE
)
627 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
630 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
632 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
635 lockdep_assert_held(&dev_priv
->pps_mutex
);
637 if (IS_VALLEYVIEW(dev
) &&
638 intel_dp
->pps_pipe
== INVALID_PIPE
)
641 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
645 intel_dp_check_edp(struct intel_dp
*intel_dp
)
647 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
650 if (!is_edp(intel_dp
))
653 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
654 WARN(1, "eDP powered off while attempting aux channel communication.\n");
655 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
656 I915_READ(_pp_stat_reg(intel_dp
)),
657 I915_READ(_pp_ctrl_reg(intel_dp
)));
662 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
664 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
665 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
667 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
671 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
673 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
674 msecs_to_jiffies_timeout(10));
676 done
= wait_for_atomic(C
, 10) == 0;
678 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
685 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
687 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
688 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
691 * The clock divider is based off the hrawclk, and would like to run at
692 * 2MHz. So, take the hrawclk value and divide by 2 and use that
694 return index
? 0 : intel_hrawclk(dev
) / 2;
697 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
699 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
700 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
705 if (intel_dig_port
->port
== PORT_A
) {
706 if (IS_GEN6(dev
) || IS_GEN7(dev
))
707 return 200; /* SNB & IVB eDP input clock at 400Mhz */
709 return 225; /* eDP input clock at 450Mhz */
711 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
715 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
717 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
718 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
721 if (intel_dig_port
->port
== PORT_A
) {
724 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
725 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
726 /* Workaround for non-ULT HSW */
733 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
737 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
739 return index
? 0 : 100;
742 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
745 * SKL doesn't need us to program the AUX clock divider (Hardware will
746 * derive the clock from CDCLK automatically). We still implement the
747 * get_aux_clock_divider vfunc to plug-in into the existing code.
749 return index
? 0 : 1;
752 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
755 uint32_t aux_clock_divider
)
757 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
758 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
759 uint32_t precharge
, timeout
;
766 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
767 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
769 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
771 return DP_AUX_CH_CTL_SEND_BUSY
|
773 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
776 DP_AUX_CH_CTL_RECEIVE_ERROR
|
777 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
778 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
779 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
782 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
787 return DP_AUX_CH_CTL_SEND_BUSY
|
789 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
790 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
791 DP_AUX_CH_CTL_TIME_OUT_1600us
|
792 DP_AUX_CH_CTL_RECEIVE_ERROR
|
793 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
794 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
798 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
799 const uint8_t *send
, int send_bytes
,
800 uint8_t *recv
, int recv_size
)
802 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
803 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
805 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
806 uint32_t ch_data
= ch_ctl
+ 4;
807 uint32_t aux_clock_divider
;
808 int i
, ret
, recv_bytes
;
811 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
817 * We will be called with VDD already enabled for dpcd/edid/oui reads.
818 * In such cases we want to leave VDD enabled and it's up to upper layers
819 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
822 vdd
= edp_panel_vdd_on(intel_dp
);
824 /* dp aux is extremely sensitive to irq latency, hence request the
825 * lowest possible wakeup latency and so prevent the cpu from going into
828 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
830 intel_dp_check_edp(intel_dp
);
832 intel_aux_display_runtime_get(dev_priv
);
834 /* Try to wait for any previous AUX channel activity */
835 for (try = 0; try < 3; try++) {
836 status
= I915_READ_NOTRACE(ch_ctl
);
837 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
843 WARN(1, "dp_aux_ch not started status 0x%08x\n",
849 /* Only 5 data registers! */
850 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
855 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
856 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
861 /* Must try at least 3 times according to DP spec */
862 for (try = 0; try < 5; try++) {
863 /* Load the send data into the aux channel data registers */
864 for (i
= 0; i
< send_bytes
; i
+= 4)
865 I915_WRITE(ch_data
+ i
,
866 pack_aux(send
+ i
, send_bytes
- i
));
868 /* Send the command and wait for it to complete */
869 I915_WRITE(ch_ctl
, send_ctl
);
871 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
873 /* Clear done status and any errors */
877 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
878 DP_AUX_CH_CTL_RECEIVE_ERROR
);
880 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
881 DP_AUX_CH_CTL_RECEIVE_ERROR
))
883 if (status
& DP_AUX_CH_CTL_DONE
)
886 if (status
& DP_AUX_CH_CTL_DONE
)
890 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
891 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
899 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
907 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
913 /* Unload any bytes sent back from the other side */
914 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
916 if (recv_bytes
> recv_size
)
917 recv_bytes
= recv_size
;
919 for (i
= 0; i
< recv_bytes
; i
+= 4)
920 unpack_aux(I915_READ(ch_data
+ i
),
921 recv
+ i
, recv_bytes
- i
);
925 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
926 intel_aux_display_runtime_put(dev_priv
);
929 edp_panel_vdd_off(intel_dp
, false);
931 pps_unlock(intel_dp
);
936 #define BARE_ADDRESS_SIZE 3
937 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
939 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
941 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
942 uint8_t txbuf
[20], rxbuf
[20];
943 size_t txsize
, rxsize
;
946 txbuf
[0] = msg
->request
<< 4;
947 txbuf
[1] = msg
->address
>> 8;
948 txbuf
[2] = msg
->address
& 0xff;
949 txbuf
[3] = msg
->size
- 1;
951 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
952 case DP_AUX_NATIVE_WRITE
:
953 case DP_AUX_I2C_WRITE
:
954 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
957 if (WARN_ON(txsize
> 20))
960 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
962 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
964 msg
->reply
= rxbuf
[0] >> 4;
966 /* Return payload size. */
971 case DP_AUX_NATIVE_READ
:
972 case DP_AUX_I2C_READ
:
973 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
974 rxsize
= msg
->size
+ 1;
976 if (WARN_ON(rxsize
> 20))
979 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
981 msg
->reply
= rxbuf
[0] >> 4;
983 * Assume happy day, and copy the data. The caller is
984 * expected to check msg->reply before touching it.
986 * Return payload size.
989 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1002 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1004 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1005 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1006 enum port port
= intel_dig_port
->port
;
1007 const char *name
= NULL
;
1012 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1016 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1020 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1024 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1032 * The AUX_CTL register is usually DP_CTL + 0x10.
1034 * On Haswell and Broadwell though:
1035 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1036 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1038 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1040 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1041 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1043 intel_dp
->aux
.name
= name
;
1044 intel_dp
->aux
.dev
= dev
->dev
;
1045 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1047 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1048 connector
->base
.kdev
->kobj
.name
);
1050 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1052 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1057 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1058 &intel_dp
->aux
.ddc
.dev
.kobj
,
1059 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1061 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1062 drm_dp_aux_unregister(&intel_dp
->aux
);
1067 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1069 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1071 if (!intel_connector
->mst_port
)
1072 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1073 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1074 intel_connector_unregister(intel_connector
);
1078 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
1081 case DP_LINK_BW_1_62
:
1082 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1084 case DP_LINK_BW_2_7
:
1085 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1087 case DP_LINK_BW_5_4
:
1088 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1094 intel_dp_set_clock(struct intel_encoder
*encoder
,
1095 struct intel_crtc_config
*pipe_config
, int link_bw
)
1097 struct drm_device
*dev
= encoder
->base
.dev
;
1098 const struct dp_link_dpll
*divisor
= NULL
;
1102 divisor
= gen4_dpll
;
1103 count
= ARRAY_SIZE(gen4_dpll
);
1104 } else if (HAS_PCH_SPLIT(dev
)) {
1106 count
= ARRAY_SIZE(pch_dpll
);
1107 } else if (IS_CHERRYVIEW(dev
)) {
1109 count
= ARRAY_SIZE(chv_dpll
);
1110 } else if (IS_VALLEYVIEW(dev
)) {
1112 count
= ARRAY_SIZE(vlv_dpll
);
1115 if (divisor
&& count
) {
1116 for (i
= 0; i
< count
; i
++) {
1117 if (link_bw
== divisor
[i
].link_bw
) {
1118 pipe_config
->dpll
= divisor
[i
].dpll
;
1119 pipe_config
->clock_set
= true;
1127 intel_dp_compute_config(struct intel_encoder
*encoder
,
1128 struct intel_crtc_config
*pipe_config
)
1130 struct drm_device
*dev
= encoder
->base
.dev
;
1131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1132 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1133 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1134 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1135 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1136 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1137 int lane_count
, clock
;
1138 int min_lane_count
= 1;
1139 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1140 /* Conveniently, the link BW constants become indices with a shift...*/
1142 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1144 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1145 int link_avail
, link_clock
;
1147 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1148 pipe_config
->has_pch_encoder
= true;
1150 pipe_config
->has_dp_encoder
= true;
1151 pipe_config
->has_drrs
= false;
1152 pipe_config
->has_audio
= intel_dp
->has_audio
;
1154 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1155 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1157 if (!HAS_PCH_SPLIT(dev
))
1158 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1159 intel_connector
->panel
.fitting_mode
);
1161 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1162 intel_connector
->panel
.fitting_mode
);
1165 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1168 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1169 "max bw %02x pixel clock %iKHz\n",
1170 max_lane_count
, bws
[max_clock
],
1171 adjusted_mode
->crtc_clock
);
1173 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1174 * bpc in between. */
1175 bpp
= pipe_config
->pipe_bpp
;
1176 if (is_edp(intel_dp
)) {
1177 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1178 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1179 dev_priv
->vbt
.edp_bpp
);
1180 bpp
= dev_priv
->vbt
.edp_bpp
;
1184 * Use the maximum clock and number of lanes the eDP panel
1185 * advertizes being capable of. The panels are generally
1186 * designed to support only a single clock and lane
1187 * configuration, and typically these values correspond to the
1188 * native resolution of the panel.
1190 min_lane_count
= max_lane_count
;
1191 min_clock
= max_clock
;
1194 for (; bpp
>= 6*3; bpp
-= 2*3) {
1195 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1198 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1199 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1200 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1201 link_avail
= intel_dp_max_data_rate(link_clock
,
1204 if (mode_rate
<= link_avail
) {
1214 if (intel_dp
->color_range_auto
) {
1217 * CEA-861-E - 5.1 Default Encoding Parameters
1218 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1220 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1221 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1223 intel_dp
->color_range
= 0;
1226 if (intel_dp
->color_range
)
1227 pipe_config
->limited_color_range
= true;
1229 intel_dp
->link_bw
= bws
[clock
];
1230 intel_dp
->lane_count
= lane_count
;
1231 pipe_config
->pipe_bpp
= bpp
;
1232 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1234 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1235 intel_dp
->link_bw
, intel_dp
->lane_count
,
1236 pipe_config
->port_clock
, bpp
);
1237 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1238 mode_rate
, link_avail
);
1240 intel_link_compute_m_n(bpp
, lane_count
,
1241 adjusted_mode
->crtc_clock
,
1242 pipe_config
->port_clock
,
1243 &pipe_config
->dp_m_n
);
1245 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1246 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1247 pipe_config
->has_drrs
= true;
1248 intel_link_compute_m_n(bpp
, lane_count
,
1249 intel_connector
->panel
.downclock_mode
->clock
,
1250 pipe_config
->port_clock
,
1251 &pipe_config
->dp_m2_n2
);
1254 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1255 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1257 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1262 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1264 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1265 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1266 struct drm_device
*dev
= crtc
->base
.dev
;
1267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1270 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1271 dpa_ctl
= I915_READ(DP_A
);
1272 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1274 if (crtc
->config
.port_clock
== 162000) {
1275 /* For a long time we've carried around a ILK-DevA w/a for the
1276 * 160MHz clock. If we're really unlucky, it's still required.
1278 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1279 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1280 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1282 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1283 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1286 I915_WRITE(DP_A
, dpa_ctl
);
1292 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1294 struct drm_device
*dev
= encoder
->base
.dev
;
1295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1296 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1297 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1298 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1299 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1302 * There are four kinds of DP registers:
1309 * IBX PCH and CPU are the same for almost everything,
1310 * except that the CPU DP PLL is configured in this
1313 * CPT PCH is quite different, having many bits moved
1314 * to the TRANS_DP_CTL register instead. That
1315 * configuration happens (oddly) in ironlake_pch_enable
1318 /* Preserve the BIOS-computed detected bit. This is
1319 * supposed to be read-only.
1321 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1323 /* Handle DP bits in common between all three register formats */
1324 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1325 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1327 if (crtc
->config
.has_audio
)
1328 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1330 /* Split out the IBX/CPU vs CPT settings */
1332 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1333 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1334 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1335 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1336 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1337 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1339 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1340 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1342 intel_dp
->DP
|= crtc
->pipe
<< 29;
1343 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1344 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1345 intel_dp
->DP
|= intel_dp
->color_range
;
1347 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1348 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1349 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1350 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1351 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1353 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1354 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1356 if (!IS_CHERRYVIEW(dev
)) {
1357 if (crtc
->pipe
== 1)
1358 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1360 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1363 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1367 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1368 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1370 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1371 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1373 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1374 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1376 static void wait_panel_status(struct intel_dp
*intel_dp
,
1380 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1382 u32 pp_stat_reg
, pp_ctrl_reg
;
1384 lockdep_assert_held(&dev_priv
->pps_mutex
);
1386 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1387 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1389 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1391 I915_READ(pp_stat_reg
),
1392 I915_READ(pp_ctrl_reg
));
1394 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1395 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1396 I915_READ(pp_stat_reg
),
1397 I915_READ(pp_ctrl_reg
));
1400 DRM_DEBUG_KMS("Wait complete\n");
1403 static void wait_panel_on(struct intel_dp
*intel_dp
)
1405 DRM_DEBUG_KMS("Wait for panel power on\n");
1406 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1409 static void wait_panel_off(struct intel_dp
*intel_dp
)
1411 DRM_DEBUG_KMS("Wait for panel power off time\n");
1412 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1415 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1417 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1419 /* When we disable the VDD override bit last we have to do the manual
1421 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1422 intel_dp
->panel_power_cycle_delay
);
1424 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1427 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1429 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1430 intel_dp
->backlight_on_delay
);
1433 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1435 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1436 intel_dp
->backlight_off_delay
);
1439 /* Read the current pp_control value, unlocking the register if it
1443 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1445 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1449 lockdep_assert_held(&dev_priv
->pps_mutex
);
1451 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1452 control
&= ~PANEL_UNLOCK_MASK
;
1453 control
|= PANEL_UNLOCK_REGS
;
1458 * Must be paired with edp_panel_vdd_off().
1459 * Must hold pps_mutex around the whole on/off sequence.
1460 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1462 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1464 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1465 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1466 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1468 enum intel_display_power_domain power_domain
;
1470 u32 pp_stat_reg
, pp_ctrl_reg
;
1471 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1473 lockdep_assert_held(&dev_priv
->pps_mutex
);
1475 if (!is_edp(intel_dp
))
1478 intel_dp
->want_panel_vdd
= true;
1480 if (edp_have_panel_vdd(intel_dp
))
1481 return need_to_disable
;
1483 power_domain
= intel_display_port_power_domain(intel_encoder
);
1484 intel_display_power_get(dev_priv
, power_domain
);
1486 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1487 port_name(intel_dig_port
->port
));
1489 if (!edp_have_panel_power(intel_dp
))
1490 wait_panel_power_cycle(intel_dp
);
1492 pp
= ironlake_get_pp_control(intel_dp
);
1493 pp
|= EDP_FORCE_VDD
;
1495 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1496 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1498 I915_WRITE(pp_ctrl_reg
, pp
);
1499 POSTING_READ(pp_ctrl_reg
);
1500 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1501 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1503 * If the panel wasn't on, delay before accessing aux channel
1505 if (!edp_have_panel_power(intel_dp
)) {
1506 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1507 port_name(intel_dig_port
->port
));
1508 msleep(intel_dp
->panel_power_up_delay
);
1511 return need_to_disable
;
1515 * Must be paired with intel_edp_panel_vdd_off() or
1516 * intel_edp_panel_off().
1517 * Nested calls to these functions are not allowed since
1518 * we drop the lock. Caller must use some higher level
1519 * locking to prevent nested calls from other threads.
1521 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1525 if (!is_edp(intel_dp
))
1529 vdd
= edp_panel_vdd_on(intel_dp
);
1530 pps_unlock(intel_dp
);
1532 WARN(!vdd
, "eDP port %c VDD already requested on\n",
1533 port_name(dp_to_dig_port(intel_dp
)->port
));
1536 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1538 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1540 struct intel_digital_port
*intel_dig_port
=
1541 dp_to_dig_port(intel_dp
);
1542 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1543 enum intel_display_power_domain power_domain
;
1545 u32 pp_stat_reg
, pp_ctrl_reg
;
1547 lockdep_assert_held(&dev_priv
->pps_mutex
);
1549 WARN_ON(intel_dp
->want_panel_vdd
);
1551 if (!edp_have_panel_vdd(intel_dp
))
1554 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1555 port_name(intel_dig_port
->port
));
1557 pp
= ironlake_get_pp_control(intel_dp
);
1558 pp
&= ~EDP_FORCE_VDD
;
1560 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1561 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1563 I915_WRITE(pp_ctrl_reg
, pp
);
1564 POSTING_READ(pp_ctrl_reg
);
1566 /* Make sure sequencer is idle before allowing subsequent activity */
1567 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1568 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1570 if ((pp
& POWER_TARGET_ON
) == 0)
1571 intel_dp
->last_power_cycle
= jiffies
;
1573 power_domain
= intel_display_port_power_domain(intel_encoder
);
1574 intel_display_power_put(dev_priv
, power_domain
);
1577 static void edp_panel_vdd_work(struct work_struct
*__work
)
1579 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1580 struct intel_dp
, panel_vdd_work
);
1583 if (!intel_dp
->want_panel_vdd
)
1584 edp_panel_vdd_off_sync(intel_dp
);
1585 pps_unlock(intel_dp
);
1588 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1590 unsigned long delay
;
1593 * Queue the timer to fire a long time from now (relative to the power
1594 * down delay) to keep the panel power up across a sequence of
1597 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1598 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1602 * Must be paired with edp_panel_vdd_on().
1603 * Must hold pps_mutex around the whole on/off sequence.
1604 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1606 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1608 struct drm_i915_private
*dev_priv
=
1609 intel_dp_to_dev(intel_dp
)->dev_private
;
1611 lockdep_assert_held(&dev_priv
->pps_mutex
);
1613 if (!is_edp(intel_dp
))
1616 WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1617 port_name(dp_to_dig_port(intel_dp
)->port
));
1619 intel_dp
->want_panel_vdd
= false;
1622 edp_panel_vdd_off_sync(intel_dp
);
1624 edp_panel_vdd_schedule_off(intel_dp
);
1627 static void edp_panel_on(struct intel_dp
*intel_dp
)
1629 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1634 lockdep_assert_held(&dev_priv
->pps_mutex
);
1636 if (!is_edp(intel_dp
))
1639 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1640 port_name(dp_to_dig_port(intel_dp
)->port
));
1642 if (WARN(edp_have_panel_power(intel_dp
),
1643 "eDP port %c panel power already on\n",
1644 port_name(dp_to_dig_port(intel_dp
)->port
)))
1647 wait_panel_power_cycle(intel_dp
);
1649 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1650 pp
= ironlake_get_pp_control(intel_dp
);
1652 /* ILK workaround: disable reset around power sequence */
1653 pp
&= ~PANEL_POWER_RESET
;
1654 I915_WRITE(pp_ctrl_reg
, pp
);
1655 POSTING_READ(pp_ctrl_reg
);
1658 pp
|= POWER_TARGET_ON
;
1660 pp
|= PANEL_POWER_RESET
;
1662 I915_WRITE(pp_ctrl_reg
, pp
);
1663 POSTING_READ(pp_ctrl_reg
);
1665 wait_panel_on(intel_dp
);
1666 intel_dp
->last_power_on
= jiffies
;
1669 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1670 I915_WRITE(pp_ctrl_reg
, pp
);
1671 POSTING_READ(pp_ctrl_reg
);
1675 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1677 if (!is_edp(intel_dp
))
1681 edp_panel_on(intel_dp
);
1682 pps_unlock(intel_dp
);
1686 static void edp_panel_off(struct intel_dp
*intel_dp
)
1688 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1689 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1690 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1692 enum intel_display_power_domain power_domain
;
1696 lockdep_assert_held(&dev_priv
->pps_mutex
);
1698 if (!is_edp(intel_dp
))
1701 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1702 port_name(dp_to_dig_port(intel_dp
)->port
));
1704 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1705 port_name(dp_to_dig_port(intel_dp
)->port
));
1707 pp
= ironlake_get_pp_control(intel_dp
);
1708 /* We need to switch off panel power _and_ force vdd, for otherwise some
1709 * panels get very unhappy and cease to work. */
1710 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1713 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1715 intel_dp
->want_panel_vdd
= false;
1717 I915_WRITE(pp_ctrl_reg
, pp
);
1718 POSTING_READ(pp_ctrl_reg
);
1720 intel_dp
->last_power_cycle
= jiffies
;
1721 wait_panel_off(intel_dp
);
1723 /* We got a reference when we enabled the VDD. */
1724 power_domain
= intel_display_port_power_domain(intel_encoder
);
1725 intel_display_power_put(dev_priv
, power_domain
);
1728 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1730 if (!is_edp(intel_dp
))
1734 edp_panel_off(intel_dp
);
1735 pps_unlock(intel_dp
);
1738 /* Enable backlight in the panel power control. */
1739 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1741 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1742 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1748 * If we enable the backlight right away following a panel power
1749 * on, we may see slight flicker as the panel syncs with the eDP
1750 * link. So delay a bit to make sure the image is solid before
1751 * allowing it to appear.
1753 wait_backlight_on(intel_dp
);
1757 pp
= ironlake_get_pp_control(intel_dp
);
1758 pp
|= EDP_BLC_ENABLE
;
1760 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1762 I915_WRITE(pp_ctrl_reg
, pp
);
1763 POSTING_READ(pp_ctrl_reg
);
1765 pps_unlock(intel_dp
);
1768 /* Enable backlight PWM and backlight PP control. */
1769 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1771 if (!is_edp(intel_dp
))
1774 DRM_DEBUG_KMS("\n");
1776 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1777 _intel_edp_backlight_on(intel_dp
);
1780 /* Disable backlight in the panel power control. */
1781 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1783 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1788 if (!is_edp(intel_dp
))
1793 pp
= ironlake_get_pp_control(intel_dp
);
1794 pp
&= ~EDP_BLC_ENABLE
;
1796 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1798 I915_WRITE(pp_ctrl_reg
, pp
);
1799 POSTING_READ(pp_ctrl_reg
);
1801 pps_unlock(intel_dp
);
1803 intel_dp
->last_backlight_off
= jiffies
;
1804 edp_wait_backlight_off(intel_dp
);
1807 /* Disable backlight PP control and backlight PWM. */
1808 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1810 if (!is_edp(intel_dp
))
1813 DRM_DEBUG_KMS("\n");
1815 _intel_edp_backlight_off(intel_dp
);
1816 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1820 * Hook for controlling the panel power control backlight through the bl_power
1821 * sysfs attribute. Take care to handle multiple calls.
1823 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1826 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1830 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1831 pps_unlock(intel_dp
);
1833 if (is_enabled
== enable
)
1836 DRM_DEBUG_KMS("panel power control backlight %s\n",
1837 enable
? "enable" : "disable");
1840 _intel_edp_backlight_on(intel_dp
);
1842 _intel_edp_backlight_off(intel_dp
);
1845 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1847 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1848 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1849 struct drm_device
*dev
= crtc
->dev
;
1850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 assert_pipe_disabled(dev_priv
,
1854 to_intel_crtc(crtc
)->pipe
);
1856 DRM_DEBUG_KMS("\n");
1857 dpa_ctl
= I915_READ(DP_A
);
1858 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1859 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1861 /* We don't adjust intel_dp->DP while tearing down the link, to
1862 * facilitate link retraining (e.g. after hotplug). Hence clear all
1863 * enable bits here to ensure that we don't enable too much. */
1864 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1865 intel_dp
->DP
|= DP_PLL_ENABLE
;
1866 I915_WRITE(DP_A
, intel_dp
->DP
);
1871 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1873 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1874 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1875 struct drm_device
*dev
= crtc
->dev
;
1876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1879 assert_pipe_disabled(dev_priv
,
1880 to_intel_crtc(crtc
)->pipe
);
1882 dpa_ctl
= I915_READ(DP_A
);
1883 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1884 "dp pll off, should be on\n");
1885 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1887 /* We can't rely on the value tracked for the DP register in
1888 * intel_dp->DP because link_down must not change that (otherwise link
1889 * re-training will fail. */
1890 dpa_ctl
&= ~DP_PLL_ENABLE
;
1891 I915_WRITE(DP_A
, dpa_ctl
);
1896 /* If the sink supports it, try to set the power state appropriately */
1897 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1901 /* Should have a valid DPCD by this point */
1902 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1905 if (mode
!= DRM_MODE_DPMS_ON
) {
1906 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1910 * When turning on, we need to retry for 1ms to give the sink
1913 for (i
= 0; i
< 3; i
++) {
1914 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1923 DRM_DEBUG_KMS("failed to %s sink power state\n",
1924 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1927 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1930 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1931 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1932 struct drm_device
*dev
= encoder
->base
.dev
;
1933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1934 enum intel_display_power_domain power_domain
;
1937 power_domain
= intel_display_port_power_domain(encoder
);
1938 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1941 tmp
= I915_READ(intel_dp
->output_reg
);
1943 if (!(tmp
& DP_PORT_EN
))
1946 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1947 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1948 } else if (IS_CHERRYVIEW(dev
)) {
1949 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1950 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1951 *pipe
= PORT_TO_PIPE(tmp
);
1957 switch (intel_dp
->output_reg
) {
1959 trans_sel
= TRANS_DP_PORT_SEL_B
;
1962 trans_sel
= TRANS_DP_PORT_SEL_C
;
1965 trans_sel
= TRANS_DP_PORT_SEL_D
;
1971 for_each_pipe(dev_priv
, i
) {
1972 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1973 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1979 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1980 intel_dp
->output_reg
);
1986 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1987 struct intel_crtc_config
*pipe_config
)
1989 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1991 struct drm_device
*dev
= encoder
->base
.dev
;
1992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1993 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1994 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1997 tmp
= I915_READ(intel_dp
->output_reg
);
1998 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1999 pipe_config
->has_audio
= true;
2001 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
2002 if (tmp
& DP_SYNC_HS_HIGH
)
2003 flags
|= DRM_MODE_FLAG_PHSYNC
;
2005 flags
|= DRM_MODE_FLAG_NHSYNC
;
2007 if (tmp
& DP_SYNC_VS_HIGH
)
2008 flags
|= DRM_MODE_FLAG_PVSYNC
;
2010 flags
|= DRM_MODE_FLAG_NVSYNC
;
2012 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2013 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2014 flags
|= DRM_MODE_FLAG_PHSYNC
;
2016 flags
|= DRM_MODE_FLAG_NHSYNC
;
2018 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2019 flags
|= DRM_MODE_FLAG_PVSYNC
;
2021 flags
|= DRM_MODE_FLAG_NVSYNC
;
2024 pipe_config
->adjusted_mode
.flags
|= flags
;
2026 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2027 tmp
& DP_COLOR_RANGE_16_235
)
2028 pipe_config
->limited_color_range
= true;
2030 pipe_config
->has_dp_encoder
= true;
2032 intel_dp_get_m_n(crtc
, pipe_config
);
2034 if (port
== PORT_A
) {
2035 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2036 pipe_config
->port_clock
= 162000;
2038 pipe_config
->port_clock
= 270000;
2041 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2042 &pipe_config
->dp_m_n
);
2044 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2045 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2047 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
2049 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2050 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2052 * This is a big fat ugly hack.
2054 * Some machines in UEFI boot mode provide us a VBT that has 18
2055 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2056 * unknown we fail to light up. Yet the same BIOS boots up with
2057 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2058 * max, not what it tells us to use.
2060 * Note: This will still be broken if the eDP panel is not lit
2061 * up by the BIOS, and thus we can't get the mode at module
2064 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2065 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2066 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2070 static bool is_edp_psr(struct intel_dp
*intel_dp
)
2072 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
2075 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
2077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2082 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2085 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
2086 struct edp_vsc_psr
*vsc_psr
)
2088 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2089 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2091 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
2092 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
2093 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
2094 uint32_t *data
= (uint32_t *) vsc_psr
;
2097 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2098 the video DIP being updated before program video DIP data buffer
2099 registers for DIP being updated. */
2100 I915_WRITE(ctl_reg
, 0);
2101 POSTING_READ(ctl_reg
);
2103 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
2104 if (i
< sizeof(struct edp_vsc_psr
))
2105 I915_WRITE(data_reg
+ i
, *data
++);
2107 I915_WRITE(data_reg
+ i
, 0);
2110 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
2111 POSTING_READ(ctl_reg
);
2114 static void intel_edp_psr_setup_vsc(struct intel_dp
*intel_dp
)
2116 struct edp_vsc_psr psr_vsc
;
2118 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2119 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
2120 psr_vsc
.sdp_header
.HB0
= 0;
2121 psr_vsc
.sdp_header
.HB1
= 0x7;
2122 psr_vsc
.sdp_header
.HB2
= 0x2;
2123 psr_vsc
.sdp_header
.HB3
= 0x8;
2124 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
2127 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2129 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2130 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2132 uint32_t aux_clock_divider
;
2133 int precharge
= 0x3;
2134 bool only_standby
= false;
2135 static const uint8_t aux_msg
[] = {
2136 [0] = DP_AUX_NATIVE_WRITE
<< 4,
2137 [1] = DP_SET_POWER
>> 8,
2138 [2] = DP_SET_POWER
& 0xff,
2140 [4] = DP_SET_POWER_D0
,
2144 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
2146 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2148 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2149 only_standby
= true;
2151 /* Enable PSR in sink */
2152 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2153 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2154 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2156 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2157 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2159 /* Setup AUX registers */
2160 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
2161 I915_WRITE(EDP_PSR_AUX_DATA1(dev
) + i
,
2162 pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
2164 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2165 DP_AUX_CH_CTL_TIME_OUT_400us
|
2166 (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2167 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2168 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2171 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2173 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2174 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2176 uint32_t max_sleep_time
= 0x1f;
2177 uint32_t idle_frames
= 1;
2179 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2180 bool only_standby
= false;
2182 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2183 only_standby
= true;
2185 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2186 val
|= EDP_PSR_LINK_STANDBY
;
2187 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2188 val
|= EDP_PSR_TP1_TIME_0us
;
2189 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2190 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2192 val
|= EDP_PSR_LINK_DISABLE
;
2194 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2195 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2196 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2197 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2201 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2203 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2204 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2206 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2209 lockdep_assert_held(&dev_priv
->psr
.lock
);
2210 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2211 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2213 dev_priv
->psr
.source_ok
= false;
2215 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2216 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2220 if (!i915
.enable_psr
) {
2221 DRM_DEBUG_KMS("PSR disable by flag\n");
2225 /* Below limitations aren't valid for Broadwell */
2226 if (IS_BROADWELL(dev
))
2229 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2231 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2235 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2236 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2241 dev_priv
->psr
.source_ok
= true;
2245 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2247 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2248 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2251 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2252 WARN_ON(dev_priv
->psr
.active
);
2253 lockdep_assert_held(&dev_priv
->psr
.lock
);
2255 /* Enable/Re-enable PSR on the host */
2256 intel_edp_psr_enable_source(intel_dp
);
2258 dev_priv
->psr
.active
= true;
2261 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2263 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2266 if (!HAS_PSR(dev
)) {
2267 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2271 if (!is_edp_psr(intel_dp
)) {
2272 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2276 mutex_lock(&dev_priv
->psr
.lock
);
2277 if (dev_priv
->psr
.enabled
) {
2278 DRM_DEBUG_KMS("PSR already in use\n");
2282 if (!intel_edp_psr_match_conditions(intel_dp
))
2285 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2287 intel_edp_psr_setup_vsc(intel_dp
);
2289 /* Avoid continuous PSR exit by masking memup and hpd */
2290 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
2291 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
2293 /* Enable PSR on the panel */
2294 intel_edp_psr_enable_sink(intel_dp
);
2296 dev_priv
->psr
.enabled
= intel_dp
;
2298 mutex_unlock(&dev_priv
->psr
.lock
);
2301 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2303 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 mutex_lock(&dev_priv
->psr
.lock
);
2307 if (!dev_priv
->psr
.enabled
) {
2308 mutex_unlock(&dev_priv
->psr
.lock
);
2312 if (dev_priv
->psr
.active
) {
2313 I915_WRITE(EDP_PSR_CTL(dev
),
2314 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2316 /* Wait till PSR is idle */
2317 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2318 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2319 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2321 dev_priv
->psr
.active
= false;
2323 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2326 dev_priv
->psr
.enabled
= NULL
;
2327 mutex_unlock(&dev_priv
->psr
.lock
);
2329 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2332 static void intel_edp_psr_work(struct work_struct
*work
)
2334 struct drm_i915_private
*dev_priv
=
2335 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2336 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2338 /* We have to make sure PSR is ready for re-enable
2339 * otherwise it keeps disabled until next full enable/disable cycle.
2340 * PSR might take some time to get fully disabled
2341 * and be ready for re-enable.
2343 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv
->dev
)) &
2344 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
2345 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2349 mutex_lock(&dev_priv
->psr
.lock
);
2350 intel_dp
= dev_priv
->psr
.enabled
;
2356 * The delayed work can race with an invalidate hence we need to
2357 * recheck. Since psr_flush first clears this and then reschedules we
2358 * won't ever miss a flush when bailing out here.
2360 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2363 intel_edp_psr_do_enable(intel_dp
);
2365 mutex_unlock(&dev_priv
->psr
.lock
);
2368 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2372 if (dev_priv
->psr
.active
) {
2373 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2375 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2377 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2379 dev_priv
->psr
.active
= false;
2384 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2385 unsigned frontbuffer_bits
)
2387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2388 struct drm_crtc
*crtc
;
2391 mutex_lock(&dev_priv
->psr
.lock
);
2392 if (!dev_priv
->psr
.enabled
) {
2393 mutex_unlock(&dev_priv
->psr
.lock
);
2397 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2398 pipe
= to_intel_crtc(crtc
)->pipe
;
2400 intel_edp_psr_do_exit(dev
);
2402 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2404 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2405 mutex_unlock(&dev_priv
->psr
.lock
);
2408 void intel_edp_psr_flush(struct drm_device
*dev
,
2409 unsigned frontbuffer_bits
)
2411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2412 struct drm_crtc
*crtc
;
2415 mutex_lock(&dev_priv
->psr
.lock
);
2416 if (!dev_priv
->psr
.enabled
) {
2417 mutex_unlock(&dev_priv
->psr
.lock
);
2421 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2422 pipe
= to_intel_crtc(crtc
)->pipe
;
2423 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2426 * On Haswell sprite plane updates don't result in a psr invalidating
2427 * signal in the hardware. Which means we need to manually fake this in
2428 * software for all flushes, not just when we've seen a preceding
2429 * invalidation through frontbuffer rendering.
2431 if (IS_HASWELL(dev
) &&
2432 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2433 intel_edp_psr_do_exit(dev
);
2435 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2436 schedule_delayed_work(&dev_priv
->psr
.work
,
2437 msecs_to_jiffies(100));
2438 mutex_unlock(&dev_priv
->psr
.lock
);
2441 void intel_edp_psr_init(struct drm_device
*dev
)
2443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2445 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2446 mutex_init(&dev_priv
->psr
.lock
);
2449 static void intel_disable_dp(struct intel_encoder
*encoder
)
2451 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2452 struct drm_device
*dev
= encoder
->base
.dev
;
2453 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2455 if (crtc
->config
.has_audio
)
2456 intel_audio_codec_disable(encoder
);
2458 /* Make sure the panel is off before trying to change the mode. But also
2459 * ensure that we have vdd while we switch off the panel. */
2460 intel_edp_panel_vdd_on(intel_dp
);
2461 intel_edp_backlight_off(intel_dp
);
2462 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2463 intel_edp_panel_off(intel_dp
);
2465 /* disable the port before the pipe on g4x */
2466 if (INTEL_INFO(dev
)->gen
< 5)
2467 intel_dp_link_down(intel_dp
);
2470 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2472 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2473 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2475 intel_dp_link_down(intel_dp
);
2477 ironlake_edp_pll_off(intel_dp
);
2480 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2482 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2484 intel_dp_link_down(intel_dp
);
2487 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2489 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2490 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2491 struct drm_device
*dev
= encoder
->base
.dev
;
2492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2493 struct intel_crtc
*intel_crtc
=
2494 to_intel_crtc(encoder
->base
.crtc
);
2495 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2496 enum pipe pipe
= intel_crtc
->pipe
;
2499 intel_dp_link_down(intel_dp
);
2501 mutex_lock(&dev_priv
->dpio_lock
);
2503 /* Propagate soft reset to data lane reset */
2504 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2505 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2506 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2508 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2509 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2510 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2512 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2513 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2514 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2516 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2517 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2518 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2520 mutex_unlock(&dev_priv
->dpio_lock
);
2524 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2526 uint8_t dp_train_pat
)
2528 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2529 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2531 enum port port
= intel_dig_port
->port
;
2534 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2536 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2537 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2539 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2541 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2542 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2543 case DP_TRAINING_PATTERN_DISABLE
:
2544 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2547 case DP_TRAINING_PATTERN_1
:
2548 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2550 case DP_TRAINING_PATTERN_2
:
2551 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2553 case DP_TRAINING_PATTERN_3
:
2554 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2557 I915_WRITE(DP_TP_CTL(port
), temp
);
2559 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2560 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2562 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2563 case DP_TRAINING_PATTERN_DISABLE
:
2564 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2566 case DP_TRAINING_PATTERN_1
:
2567 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2569 case DP_TRAINING_PATTERN_2
:
2570 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2572 case DP_TRAINING_PATTERN_3
:
2573 DRM_ERROR("DP training pattern 3 not supported\n");
2574 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2579 if (IS_CHERRYVIEW(dev
))
2580 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2582 *DP
&= ~DP_LINK_TRAIN_MASK
;
2584 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2585 case DP_TRAINING_PATTERN_DISABLE
:
2586 *DP
|= DP_LINK_TRAIN_OFF
;
2588 case DP_TRAINING_PATTERN_1
:
2589 *DP
|= DP_LINK_TRAIN_PAT_1
;
2591 case DP_TRAINING_PATTERN_2
:
2592 *DP
|= DP_LINK_TRAIN_PAT_2
;
2594 case DP_TRAINING_PATTERN_3
:
2595 if (IS_CHERRYVIEW(dev
)) {
2596 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2598 DRM_ERROR("DP training pattern 3 not supported\n");
2599 *DP
|= DP_LINK_TRAIN_PAT_2
;
2606 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2608 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2611 /* enable with pattern 1 (as per spec) */
2612 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2613 DP_TRAINING_PATTERN_1
);
2615 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2616 POSTING_READ(intel_dp
->output_reg
);
2619 * Magic for VLV/CHV. We _must_ first set up the register
2620 * without actually enabling the port, and then do another
2621 * write to enable the port. Otherwise link training will
2622 * fail when the power sequencer is freshly used for this port.
2624 intel_dp
->DP
|= DP_PORT_EN
;
2626 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2627 POSTING_READ(intel_dp
->output_reg
);
2630 static void intel_enable_dp(struct intel_encoder
*encoder
)
2632 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2633 struct drm_device
*dev
= encoder
->base
.dev
;
2634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2635 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2636 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2638 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2643 if (IS_VALLEYVIEW(dev
))
2644 vlv_init_panel_power_sequencer(intel_dp
);
2646 intel_dp_enable_port(intel_dp
);
2648 edp_panel_vdd_on(intel_dp
);
2649 edp_panel_on(intel_dp
);
2650 edp_panel_vdd_off(intel_dp
, true);
2652 pps_unlock(intel_dp
);
2654 if (IS_VALLEYVIEW(dev
))
2655 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
));
2657 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2658 intel_dp_start_link_train(intel_dp
);
2659 intel_dp_complete_link_train(intel_dp
);
2660 intel_dp_stop_link_train(intel_dp
);
2662 if (crtc
->config
.has_audio
) {
2663 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2664 pipe_name(crtc
->pipe
));
2665 intel_audio_codec_enable(encoder
);
2669 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2671 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2673 intel_enable_dp(encoder
);
2674 intel_edp_backlight_on(intel_dp
);
2677 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2679 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2681 intel_edp_backlight_on(intel_dp
);
2684 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2686 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2687 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2689 intel_dp_prepare(encoder
);
2691 /* Only ilk+ has port A */
2692 if (dport
->port
== PORT_A
) {
2693 ironlake_set_pll_cpu_edp(intel_dp
);
2694 ironlake_edp_pll_on(intel_dp
);
2698 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2700 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2701 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2702 enum pipe pipe
= intel_dp
->pps_pipe
;
2703 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2705 edp_panel_vdd_off_sync(intel_dp
);
2708 * VLV seems to get confused when multiple power seqeuencers
2709 * have the same port selected (even if only one has power/vdd
2710 * enabled). The failure manifests as vlv_wait_port_ready() failing
2711 * CHV on the other hand doesn't seem to mind having the same port
2712 * selected in multiple power seqeuencers, but let's clear the
2713 * port select always when logically disconnecting a power sequencer
2716 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2717 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2718 I915_WRITE(pp_on_reg
, 0);
2719 POSTING_READ(pp_on_reg
);
2721 intel_dp
->pps_pipe
= INVALID_PIPE
;
2724 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2728 struct intel_encoder
*encoder
;
2730 lockdep_assert_held(&dev_priv
->pps_mutex
);
2732 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2735 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2737 struct intel_dp
*intel_dp
;
2740 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2743 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2744 port
= dp_to_dig_port(intel_dp
)->port
;
2746 if (intel_dp
->pps_pipe
!= pipe
)
2749 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2750 pipe_name(pipe
), port_name(port
));
2752 WARN(encoder
->connectors_active
,
2753 "stealing pipe %c power sequencer from active eDP port %c\n",
2754 pipe_name(pipe
), port_name(port
));
2756 /* make sure vdd is off before we steal it */
2757 vlv_detach_power_sequencer(intel_dp
);
2761 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2763 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2764 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2765 struct drm_device
*dev
= encoder
->base
.dev
;
2766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2767 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2769 lockdep_assert_held(&dev_priv
->pps_mutex
);
2771 if (!is_edp(intel_dp
))
2774 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2778 * If another power sequencer was being used on this
2779 * port previously make sure to turn off vdd there while
2780 * we still have control of it.
2782 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2783 vlv_detach_power_sequencer(intel_dp
);
2786 * We may be stealing the power
2787 * sequencer from another port.
2789 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2791 /* now it's all ours */
2792 intel_dp
->pps_pipe
= crtc
->pipe
;
2794 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2795 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2797 /* init power sequencer on this pipe and port */
2798 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2799 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2802 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2804 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2805 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2806 struct drm_device
*dev
= encoder
->base
.dev
;
2807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2808 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2809 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2810 int pipe
= intel_crtc
->pipe
;
2813 mutex_lock(&dev_priv
->dpio_lock
);
2815 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2822 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2823 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2824 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2826 mutex_unlock(&dev_priv
->dpio_lock
);
2828 intel_enable_dp(encoder
);
2831 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2833 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2834 struct drm_device
*dev
= encoder
->base
.dev
;
2835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2836 struct intel_crtc
*intel_crtc
=
2837 to_intel_crtc(encoder
->base
.crtc
);
2838 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2839 int pipe
= intel_crtc
->pipe
;
2841 intel_dp_prepare(encoder
);
2843 /* Program Tx lane resets to default */
2844 mutex_lock(&dev_priv
->dpio_lock
);
2845 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2846 DPIO_PCS_TX_LANE2_RESET
|
2847 DPIO_PCS_TX_LANE1_RESET
);
2848 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2849 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2850 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2851 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2852 DPIO_PCS_CLK_SOFT_RESET
);
2854 /* Fix up inter-pair skew failure */
2855 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2856 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2857 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2858 mutex_unlock(&dev_priv
->dpio_lock
);
2861 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2863 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2864 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2865 struct drm_device
*dev
= encoder
->base
.dev
;
2866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2867 struct intel_crtc
*intel_crtc
=
2868 to_intel_crtc(encoder
->base
.crtc
);
2869 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2870 int pipe
= intel_crtc
->pipe
;
2874 mutex_lock(&dev_priv
->dpio_lock
);
2876 /* allow hardware to manage TX FIFO reset source */
2877 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2878 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2879 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2881 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2882 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2883 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2885 /* Deassert soft data lane reset*/
2886 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2887 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2888 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2890 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2891 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2892 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2894 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2895 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2896 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2898 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2899 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2900 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2902 /* Program Tx lane latency optimal setting*/
2903 for (i
= 0; i
< 4; i
++) {
2904 /* Set the latency optimal bit */
2905 data
= (i
== 1) ? 0x0 : 0x6;
2906 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2907 data
<< DPIO_FRC_LATENCY_SHFIT
);
2909 /* Set the upar bit */
2910 data
= (i
== 1) ? 0x0 : 0x1;
2911 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2912 data
<< DPIO_UPAR_SHIFT
);
2915 /* Data lane stagger programming */
2916 /* FIXME: Fix up value only after power analysis */
2918 mutex_unlock(&dev_priv
->dpio_lock
);
2920 intel_enable_dp(encoder
);
2923 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2925 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2926 struct drm_device
*dev
= encoder
->base
.dev
;
2927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2928 struct intel_crtc
*intel_crtc
=
2929 to_intel_crtc(encoder
->base
.crtc
);
2930 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2931 enum pipe pipe
= intel_crtc
->pipe
;
2934 intel_dp_prepare(encoder
);
2936 mutex_lock(&dev_priv
->dpio_lock
);
2938 /* program left/right clock distribution */
2939 if (pipe
!= PIPE_B
) {
2940 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2941 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2943 val
|= CHV_BUFLEFTENA1_FORCE
;
2945 val
|= CHV_BUFRIGHTENA1_FORCE
;
2946 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2948 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2949 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2951 val
|= CHV_BUFLEFTENA2_FORCE
;
2953 val
|= CHV_BUFRIGHTENA2_FORCE
;
2954 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2957 /* program clock channel usage */
2958 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2959 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2961 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2963 val
|= CHV_PCS_USEDCLKCHANNEL
;
2964 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2966 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2967 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2969 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2971 val
|= CHV_PCS_USEDCLKCHANNEL
;
2972 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2975 * This a a bit weird since generally CL
2976 * matches the pipe, but here we need to
2977 * pick the CL based on the port.
2979 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2981 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2983 val
|= CHV_CMN_USEDCLKCHANNEL
;
2984 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2986 mutex_unlock(&dev_priv
->dpio_lock
);
2990 * Native read with retry for link status and receiver capability reads for
2991 * cases where the sink may still be asleep.
2993 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2994 * supposed to retry 3 times per the spec.
2997 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2998 void *buffer
, size_t size
)
3004 * Sometime we just get the same incorrect byte repeated
3005 * over the entire buffer. Doing just one throw away read
3006 * initially seems to "solve" it.
3008 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
3010 for (i
= 0; i
< 3; i
++) {
3011 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
3021 * Fetch AUX CH registers 0x202 - 0x207 which contain
3022 * link status information
3025 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3027 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3030 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3033 /* These are source-specific values. */
3035 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3037 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3038 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3040 if (INTEL_INFO(dev
)->gen
>= 9)
3041 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3042 else if (IS_VALLEYVIEW(dev
))
3043 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3044 else if (IS_GEN7(dev
) && port
== PORT_A
)
3045 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3046 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
3047 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3049 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3053 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3055 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3056 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3058 if (INTEL_INFO(dev
)->gen
>= 9) {
3059 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3061 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3063 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3065 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3067 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3069 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3070 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3072 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3074 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3075 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3076 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3079 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3081 } else if (IS_VALLEYVIEW(dev
)) {
3082 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3084 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3086 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3088 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3091 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3093 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3094 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3096 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3099 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3101 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3104 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3106 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3108 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3110 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3113 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3118 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
3120 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3122 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3123 struct intel_crtc
*intel_crtc
=
3124 to_intel_crtc(dport
->base
.base
.crtc
);
3125 unsigned long demph_reg_value
, preemph_reg_value
,
3126 uniqtranscale_reg_value
;
3127 uint8_t train_set
= intel_dp
->train_set
[0];
3128 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3129 int pipe
= intel_crtc
->pipe
;
3131 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3132 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3133 preemph_reg_value
= 0x0004000;
3134 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3136 demph_reg_value
= 0x2B405555;
3137 uniqtranscale_reg_value
= 0x552AB83A;
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3140 demph_reg_value
= 0x2B404040;
3141 uniqtranscale_reg_value
= 0x5548B83A;
3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3144 demph_reg_value
= 0x2B245555;
3145 uniqtranscale_reg_value
= 0x5560B83A;
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3148 demph_reg_value
= 0x2B405555;
3149 uniqtranscale_reg_value
= 0x5598DA3A;
3155 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3156 preemph_reg_value
= 0x0002000;
3157 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3159 demph_reg_value
= 0x2B404040;
3160 uniqtranscale_reg_value
= 0x5552B83A;
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3163 demph_reg_value
= 0x2B404848;
3164 uniqtranscale_reg_value
= 0x5580B83A;
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3167 demph_reg_value
= 0x2B404040;
3168 uniqtranscale_reg_value
= 0x55ADDA3A;
3174 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3175 preemph_reg_value
= 0x0000000;
3176 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3178 demph_reg_value
= 0x2B305555;
3179 uniqtranscale_reg_value
= 0x5570B83A;
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3182 demph_reg_value
= 0x2B2B4040;
3183 uniqtranscale_reg_value
= 0x55ADDA3A;
3189 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3190 preemph_reg_value
= 0x0006000;
3191 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3193 demph_reg_value
= 0x1B405555;
3194 uniqtranscale_reg_value
= 0x55ADDA3A;
3204 mutex_lock(&dev_priv
->dpio_lock
);
3205 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3206 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3207 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3208 uniqtranscale_reg_value
);
3209 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3210 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3211 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3212 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3213 mutex_unlock(&dev_priv
->dpio_lock
);
3218 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3220 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3222 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3223 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3224 u32 deemph_reg_value
, margin_reg_value
, val
;
3225 uint8_t train_set
= intel_dp
->train_set
[0];
3226 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3227 enum pipe pipe
= intel_crtc
->pipe
;
3230 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3231 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3232 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3234 deemph_reg_value
= 128;
3235 margin_reg_value
= 52;
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3238 deemph_reg_value
= 128;
3239 margin_reg_value
= 77;
3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3242 deemph_reg_value
= 128;
3243 margin_reg_value
= 102;
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3246 deemph_reg_value
= 128;
3247 margin_reg_value
= 154;
3248 /* FIXME extra to set for 1200 */
3254 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3255 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3257 deemph_reg_value
= 85;
3258 margin_reg_value
= 78;
3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3261 deemph_reg_value
= 85;
3262 margin_reg_value
= 116;
3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3265 deemph_reg_value
= 85;
3266 margin_reg_value
= 154;
3272 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3273 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3275 deemph_reg_value
= 64;
3276 margin_reg_value
= 104;
3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3279 deemph_reg_value
= 64;
3280 margin_reg_value
= 154;
3286 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3287 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3289 deemph_reg_value
= 43;
3290 margin_reg_value
= 154;
3300 mutex_lock(&dev_priv
->dpio_lock
);
3302 /* Clear calc init */
3303 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3304 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3305 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3306 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3307 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3309 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3310 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3311 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3312 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3313 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3315 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3316 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3317 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3318 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3320 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3321 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3322 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3323 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3325 /* Program swing deemph */
3326 for (i
= 0; i
< 4; i
++) {
3327 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3328 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3329 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3330 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3333 /* Program swing margin */
3334 for (i
= 0; i
< 4; i
++) {
3335 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3336 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3337 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3338 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3341 /* Disable unique transition scale */
3342 for (i
= 0; i
< 4; i
++) {
3343 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3344 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3345 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3348 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3349 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3350 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3351 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3354 * The document said it needs to set bit 27 for ch0 and bit 26
3355 * for ch1. Might be a typo in the doc.
3356 * For now, for this unique transition scale selection, set bit
3357 * 27 for ch0 and ch1.
3359 for (i
= 0; i
< 4; i
++) {
3360 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3361 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3362 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3365 for (i
= 0; i
< 4; i
++) {
3366 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3367 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3368 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3369 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3373 /* Start swing calculation */
3374 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3375 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3376 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3378 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3379 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3380 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3383 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3384 val
|= DPIO_LRC_BYPASS
;
3385 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3387 mutex_unlock(&dev_priv
->dpio_lock
);
3393 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3394 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3399 uint8_t voltage_max
;
3400 uint8_t preemph_max
;
3402 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3403 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3404 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3412 voltage_max
= intel_dp_voltage_max(intel_dp
);
3413 if (v
>= voltage_max
)
3414 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3416 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3417 if (p
>= preemph_max
)
3418 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3420 for (lane
= 0; lane
< 4; lane
++)
3421 intel_dp
->train_set
[lane
] = v
| p
;
3425 intel_gen4_signal_levels(uint8_t train_set
)
3427 uint32_t signal_levels
= 0;
3429 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3432 signal_levels
|= DP_VOLTAGE_0_4
;
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3435 signal_levels
|= DP_VOLTAGE_0_6
;
3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3438 signal_levels
|= DP_VOLTAGE_0_8
;
3440 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3441 signal_levels
|= DP_VOLTAGE_1_2
;
3444 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3445 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3447 signal_levels
|= DP_PRE_EMPHASIS_0
;
3449 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3450 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3452 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3453 signal_levels
|= DP_PRE_EMPHASIS_6
;
3455 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3456 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3459 return signal_levels
;
3462 /* Gen6's DP voltage swing and pre-emphasis control */
3464 intel_gen6_edp_signal_levels(uint8_t train_set
)
3466 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3467 DP_TRAIN_PRE_EMPHASIS_MASK
);
3468 switch (signal_levels
) {
3469 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3470 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3471 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3472 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3473 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3474 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3475 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3476 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3478 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3479 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3481 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3482 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3484 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3485 "0x%x\n", signal_levels
);
3486 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3490 /* Gen7's DP voltage swing and pre-emphasis control */
3492 intel_gen7_edp_signal_levels(uint8_t train_set
)
3494 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3495 DP_TRAIN_PRE_EMPHASIS_MASK
);
3496 switch (signal_levels
) {
3497 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3498 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3500 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3502 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3504 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3505 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3507 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3509 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3510 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3511 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3512 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3515 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3516 "0x%x\n", signal_levels
);
3517 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3521 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3523 intel_hsw_signal_levels(uint8_t train_set
)
3525 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3526 DP_TRAIN_PRE_EMPHASIS_MASK
);
3527 switch (signal_levels
) {
3528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3529 return DDI_BUF_TRANS_SELECT(0);
3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3531 return DDI_BUF_TRANS_SELECT(1);
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3533 return DDI_BUF_TRANS_SELECT(2);
3534 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3535 return DDI_BUF_TRANS_SELECT(3);
3537 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3538 return DDI_BUF_TRANS_SELECT(4);
3539 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3540 return DDI_BUF_TRANS_SELECT(5);
3541 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3542 return DDI_BUF_TRANS_SELECT(6);
3544 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3545 return DDI_BUF_TRANS_SELECT(7);
3546 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3547 return DDI_BUF_TRANS_SELECT(8);
3549 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3550 "0x%x\n", signal_levels
);
3551 return DDI_BUF_TRANS_SELECT(0);
3555 /* Properly updates "DP" with the correct signal levels. */
3557 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3559 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3560 enum port port
= intel_dig_port
->port
;
3561 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3562 uint32_t signal_levels
, mask
;
3563 uint8_t train_set
= intel_dp
->train_set
[0];
3565 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3566 signal_levels
= intel_hsw_signal_levels(train_set
);
3567 mask
= DDI_BUF_EMP_MASK
;
3568 } else if (IS_CHERRYVIEW(dev
)) {
3569 signal_levels
= intel_chv_signal_levels(intel_dp
);
3571 } else if (IS_VALLEYVIEW(dev
)) {
3572 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3574 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3575 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3576 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3577 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3578 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3579 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3581 signal_levels
= intel_gen4_signal_levels(train_set
);
3582 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3585 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3587 *DP
= (*DP
& ~mask
) | signal_levels
;
3591 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3593 uint8_t dp_train_pat
)
3595 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3596 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3598 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3601 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3603 I915_WRITE(intel_dp
->output_reg
, *DP
);
3604 POSTING_READ(intel_dp
->output_reg
);
3606 buf
[0] = dp_train_pat
;
3607 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3608 DP_TRAINING_PATTERN_DISABLE
) {
3609 /* don't write DP_TRAINING_LANEx_SET on disable */
3612 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3613 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3614 len
= intel_dp
->lane_count
+ 1;
3617 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3624 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3625 uint8_t dp_train_pat
)
3627 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3628 intel_dp_set_signal_levels(intel_dp
, DP
);
3629 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3633 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3634 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3636 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3637 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3641 intel_get_adjust_train(intel_dp
, link_status
);
3642 intel_dp_set_signal_levels(intel_dp
, DP
);
3644 I915_WRITE(intel_dp
->output_reg
, *DP
);
3645 POSTING_READ(intel_dp
->output_reg
);
3647 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3648 intel_dp
->train_set
, intel_dp
->lane_count
);
3650 return ret
== intel_dp
->lane_count
;
3653 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3655 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3656 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3658 enum port port
= intel_dig_port
->port
;
3664 val
= I915_READ(DP_TP_CTL(port
));
3665 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3666 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3667 I915_WRITE(DP_TP_CTL(port
), val
);
3670 * On PORT_A we can have only eDP in SST mode. There the only reason
3671 * we need to set idle transmission mode is to work around a HW issue
3672 * where we enable the pipe while not in idle link-training mode.
3673 * In this case there is requirement to wait for a minimum number of
3674 * idle patterns to be sent.
3679 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3681 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3684 /* Enable corresponding port and start training pattern 1 */
3686 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3688 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3689 struct drm_device
*dev
= encoder
->dev
;
3692 int voltage_tries
, loop_tries
;
3693 uint32_t DP
= intel_dp
->DP
;
3694 uint8_t link_config
[2];
3697 intel_ddi_prepare_link_retrain(encoder
);
3699 /* Write the link configuration data */
3700 link_config
[0] = intel_dp
->link_bw
;
3701 link_config
[1] = intel_dp
->lane_count
;
3702 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3703 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3704 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3707 link_config
[1] = DP_SET_ANSI_8B10B
;
3708 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3712 /* clock recovery */
3713 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3714 DP_TRAINING_PATTERN_1
|
3715 DP_LINK_SCRAMBLING_DISABLE
)) {
3716 DRM_ERROR("failed to enable link training\n");
3724 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3726 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3727 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3728 DRM_ERROR("failed to get link status\n");
3732 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3733 DRM_DEBUG_KMS("clock recovery OK\n");
3737 /* Check to see if we've tried the max voltage */
3738 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3739 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3741 if (i
== intel_dp
->lane_count
) {
3743 if (loop_tries
== 5) {
3744 DRM_ERROR("too many full retries, give up\n");
3747 intel_dp_reset_link_train(intel_dp
, &DP
,
3748 DP_TRAINING_PATTERN_1
|
3749 DP_LINK_SCRAMBLING_DISABLE
);
3754 /* Check to see if we've tried the same voltage 5 times */
3755 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3757 if (voltage_tries
== 5) {
3758 DRM_ERROR("too many voltage retries, give up\n");
3763 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3765 /* Update training set as requested by target */
3766 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3767 DRM_ERROR("failed to update link training\n");
3776 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3778 bool channel_eq
= false;
3779 int tries
, cr_tries
;
3780 uint32_t DP
= intel_dp
->DP
;
3781 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3783 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3784 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3785 training_pattern
= DP_TRAINING_PATTERN_3
;
3787 /* channel equalization */
3788 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3790 DP_LINK_SCRAMBLING_DISABLE
)) {
3791 DRM_ERROR("failed to start channel equalization\n");
3799 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3802 DRM_ERROR("failed to train DP, aborting\n");
3806 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3807 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3808 DRM_ERROR("failed to get link status\n");
3812 /* Make sure clock is still ok */
3813 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3814 intel_dp_start_link_train(intel_dp
);
3815 intel_dp_set_link_train(intel_dp
, &DP
,
3817 DP_LINK_SCRAMBLING_DISABLE
);
3822 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3827 /* Try 5 times, then try clock recovery if that fails */
3829 intel_dp_start_link_train(intel_dp
);
3830 intel_dp_set_link_train(intel_dp
, &DP
,
3832 DP_LINK_SCRAMBLING_DISABLE
);
3838 /* Update training set as requested by target */
3839 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3840 DRM_ERROR("failed to update link training\n");
3846 intel_dp_set_idle_link_train(intel_dp
);
3851 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3855 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3857 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3858 DP_TRAINING_PATTERN_DISABLE
);
3862 intel_dp_link_down(struct intel_dp
*intel_dp
)
3864 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3865 enum port port
= intel_dig_port
->port
;
3866 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3868 struct intel_crtc
*intel_crtc
=
3869 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3870 uint32_t DP
= intel_dp
->DP
;
3872 if (WARN_ON(HAS_DDI(dev
)))
3875 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3878 DRM_DEBUG_KMS("\n");
3880 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3881 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3882 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3884 if (IS_CHERRYVIEW(dev
))
3885 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3887 DP
&= ~DP_LINK_TRAIN_MASK
;
3888 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3890 POSTING_READ(intel_dp
->output_reg
);
3892 if (HAS_PCH_IBX(dev
) &&
3893 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3894 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3896 /* Hardware workaround: leaving our transcoder select
3897 * set to transcoder B while it's off will prevent the
3898 * corresponding HDMI output on transcoder A.
3900 * Combine this with another hardware workaround:
3901 * transcoder select bit can only be cleared while the
3904 DP
&= ~DP_PIPEB_SELECT
;
3905 I915_WRITE(intel_dp
->output_reg
, DP
);
3907 /* Changes to enable or select take place the vblank
3908 * after being written.
3910 if (WARN_ON(crtc
== NULL
)) {
3911 /* We should never try to disable a port without a crtc
3912 * attached. For paranoia keep the code around for a
3914 POSTING_READ(intel_dp
->output_reg
);
3917 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3920 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3921 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3922 POSTING_READ(intel_dp
->output_reg
);
3923 msleep(intel_dp
->panel_power_down_delay
);
3927 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3929 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3930 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3933 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3934 sizeof(intel_dp
->dpcd
)) < 0)
3935 return false; /* aux transfer failed */
3937 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3939 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3940 return false; /* DPCD not present */
3942 /* Check if the panel supports PSR */
3943 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3944 if (is_edp(intel_dp
)) {
3945 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3947 sizeof(intel_dp
->psr_dpcd
));
3948 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3949 dev_priv
->psr
.sink_support
= true;
3950 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3954 /* Training Pattern 3 support, both source and sink */
3955 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3956 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3957 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3958 intel_dp
->use_tps3
= true;
3959 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3961 intel_dp
->use_tps3
= false;
3963 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3964 DP_DWN_STRM_PORT_PRESENT
))
3965 return true; /* native DP sink */
3967 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3968 return true; /* no per-port downstream info */
3970 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3971 intel_dp
->downstream_ports
,
3972 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3973 return false; /* downstream port status fetch failed */
3979 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3983 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3986 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3987 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3988 buf
[0], buf
[1], buf
[2]);
3990 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3991 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3992 buf
[0], buf
[1], buf
[2]);
3996 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
4000 if (!intel_dp
->can_mst
)
4003 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
4006 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
4007 if (buf
[0] & DP_MST_CAP
) {
4008 DRM_DEBUG_KMS("Sink is MST capable\n");
4009 intel_dp
->is_mst
= true;
4011 DRM_DEBUG_KMS("Sink is not MST capable\n");
4012 intel_dp
->is_mst
= false;
4016 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4017 return intel_dp
->is_mst
;
4020 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
4022 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4023 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4024 struct intel_crtc
*intel_crtc
=
4025 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
4030 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4033 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
4036 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4039 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4040 buf
| DP_TEST_SINK_START
) < 0)
4043 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4045 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4048 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4049 DP_TEST_SINK_MISC
, &buf
) < 0)
4051 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4052 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4054 if (attempts
== 0) {
4055 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
4059 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
4062 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4064 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4065 buf
& ~DP_TEST_SINK_START
) < 0)
4072 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4074 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4075 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4076 sink_irq_vector
, 1) == 1;
4080 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4084 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4086 sink_irq_vector
, 14);
4094 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4096 /* NAK by default */
4097 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
4101 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4105 if (intel_dp
->is_mst
) {
4110 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4114 /* check link status - esi[10] = 0x200c */
4115 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4116 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4117 intel_dp_start_link_train(intel_dp
);
4118 intel_dp_complete_link_train(intel_dp
);
4119 intel_dp_stop_link_train(intel_dp
);
4122 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
4123 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4126 for (retry
= 0; retry
< 3; retry
++) {
4128 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4129 DP_SINK_COUNT_ESI
+1,
4136 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4138 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
4146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4147 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4148 intel_dp
->is_mst
= false;
4149 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4150 /* send a hotplug event */
4151 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4158 * According to DP spec
4161 * 2. Configure link according to Receiver Capabilities
4162 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4163 * 4. Check link status on receipt of hot-plug interrupt
4166 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4168 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4169 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4171 u8 link_status
[DP_LINK_STATUS_SIZE
];
4173 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4175 if (!intel_encoder
->connectors_active
)
4178 if (WARN_ON(!intel_encoder
->base
.crtc
))
4181 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4184 /* Try to read receiver status if the link appears to be up */
4185 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4189 /* Now read the DPCD to see if it's actually running */
4190 if (!intel_dp_get_dpcd(intel_dp
)) {
4194 /* Try to read the source of the interrupt */
4195 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4196 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4197 /* Clear interrupt source */
4198 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4199 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4202 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4203 intel_dp_handle_test_request(intel_dp
);
4204 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4205 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4208 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4209 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4210 intel_encoder
->base
.name
);
4211 intel_dp_start_link_train(intel_dp
);
4212 intel_dp_complete_link_train(intel_dp
);
4213 intel_dp_stop_link_train(intel_dp
);
4217 /* XXX this is probably wrong for multiple downstream ports */
4218 static enum drm_connector_status
4219 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4221 uint8_t *dpcd
= intel_dp
->dpcd
;
4224 if (!intel_dp_get_dpcd(intel_dp
))
4225 return connector_status_disconnected
;
4227 /* if there's no downstream port, we're done */
4228 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4229 return connector_status_connected
;
4231 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4232 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4233 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4236 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4238 return connector_status_unknown
;
4240 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4241 : connector_status_disconnected
;
4244 /* If no HPD, poke DDC gently */
4245 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4246 return connector_status_connected
;
4248 /* Well we tried, say unknown for unreliable port types */
4249 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4250 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4251 if (type
== DP_DS_PORT_TYPE_VGA
||
4252 type
== DP_DS_PORT_TYPE_NON_EDID
)
4253 return connector_status_unknown
;
4255 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4256 DP_DWN_STRM_PORT_TYPE_MASK
;
4257 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4258 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4259 return connector_status_unknown
;
4262 /* Anything else is out of spec, warn and ignore */
4263 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4264 return connector_status_disconnected
;
4267 static enum drm_connector_status
4268 edp_detect(struct intel_dp
*intel_dp
)
4270 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4271 enum drm_connector_status status
;
4273 status
= intel_panel_detect(dev
);
4274 if (status
== connector_status_unknown
)
4275 status
= connector_status_connected
;
4280 static enum drm_connector_status
4281 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4283 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4285 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4287 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4288 return connector_status_disconnected
;
4290 return intel_dp_detect_dpcd(intel_dp
);
4293 static int g4x_digital_port_connected(struct drm_device
*dev
,
4294 struct intel_digital_port
*intel_dig_port
)
4296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4299 if (IS_VALLEYVIEW(dev
)) {
4300 switch (intel_dig_port
->port
) {
4302 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4305 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4308 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4314 switch (intel_dig_port
->port
) {
4316 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4319 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4322 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4329 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4334 static enum drm_connector_status
4335 g4x_dp_detect(struct intel_dp
*intel_dp
)
4337 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4338 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4341 /* Can't disconnect eDP, but you can close the lid... */
4342 if (is_edp(intel_dp
)) {
4343 enum drm_connector_status status
;
4345 status
= intel_panel_detect(dev
);
4346 if (status
== connector_status_unknown
)
4347 status
= connector_status_connected
;
4351 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4353 return connector_status_unknown
;
4355 return connector_status_disconnected
;
4357 return intel_dp_detect_dpcd(intel_dp
);
4360 static struct edid
*
4361 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4363 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4365 /* use cached edid if we have one */
4366 if (intel_connector
->edid
) {
4368 if (IS_ERR(intel_connector
->edid
))
4371 return drm_edid_duplicate(intel_connector
->edid
);
4373 return drm_get_edid(&intel_connector
->base
,
4374 &intel_dp
->aux
.ddc
);
4378 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4380 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4383 edid
= intel_dp_get_edid(intel_dp
);
4384 intel_connector
->detect_edid
= edid
;
4386 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4387 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4389 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4393 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4395 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4397 kfree(intel_connector
->detect_edid
);
4398 intel_connector
->detect_edid
= NULL
;
4400 intel_dp
->has_audio
= false;
4403 static enum intel_display_power_domain
4404 intel_dp_power_get(struct intel_dp
*dp
)
4406 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4407 enum intel_display_power_domain power_domain
;
4409 power_domain
= intel_display_port_power_domain(encoder
);
4410 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4412 return power_domain
;
4416 intel_dp_power_put(struct intel_dp
*dp
,
4417 enum intel_display_power_domain power_domain
)
4419 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4420 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4423 static enum drm_connector_status
4424 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4426 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4427 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4428 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4429 struct drm_device
*dev
= connector
->dev
;
4430 enum drm_connector_status status
;
4431 enum intel_display_power_domain power_domain
;
4434 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4435 connector
->base
.id
, connector
->name
);
4436 intel_dp_unset_edid(intel_dp
);
4438 if (intel_dp
->is_mst
) {
4439 /* MST devices are disconnected from a monitor POV */
4440 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4441 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4442 return connector_status_disconnected
;
4445 power_domain
= intel_dp_power_get(intel_dp
);
4447 /* Can't disconnect eDP, but you can close the lid... */
4448 if (is_edp(intel_dp
))
4449 status
= edp_detect(intel_dp
);
4450 else if (HAS_PCH_SPLIT(dev
))
4451 status
= ironlake_dp_detect(intel_dp
);
4453 status
= g4x_dp_detect(intel_dp
);
4454 if (status
!= connector_status_connected
)
4457 intel_dp_probe_oui(intel_dp
);
4459 ret
= intel_dp_probe_mst(intel_dp
);
4461 /* if we are in MST mode then this connector
4462 won't appear connected or have anything with EDID on it */
4463 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4464 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4465 status
= connector_status_disconnected
;
4469 intel_dp_set_edid(intel_dp
);
4471 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4472 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4473 status
= connector_status_connected
;
4476 intel_dp_power_put(intel_dp
, power_domain
);
4481 intel_dp_force(struct drm_connector
*connector
)
4483 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4484 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4485 enum intel_display_power_domain power_domain
;
4487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4488 connector
->base
.id
, connector
->name
);
4489 intel_dp_unset_edid(intel_dp
);
4491 if (connector
->status
!= connector_status_connected
)
4494 power_domain
= intel_dp_power_get(intel_dp
);
4496 intel_dp_set_edid(intel_dp
);
4498 intel_dp_power_put(intel_dp
, power_domain
);
4500 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4501 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4504 static int intel_dp_get_modes(struct drm_connector
*connector
)
4506 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4509 edid
= intel_connector
->detect_edid
;
4511 int ret
= intel_connector_update_modes(connector
, edid
);
4516 /* if eDP has no EDID, fall back to fixed mode */
4517 if (is_edp(intel_attached_dp(connector
)) &&
4518 intel_connector
->panel
.fixed_mode
) {
4519 struct drm_display_mode
*mode
;
4521 mode
= drm_mode_duplicate(connector
->dev
,
4522 intel_connector
->panel
.fixed_mode
);
4524 drm_mode_probed_add(connector
, mode
);
4533 intel_dp_detect_audio(struct drm_connector
*connector
)
4535 bool has_audio
= false;
4538 edid
= to_intel_connector(connector
)->detect_edid
;
4540 has_audio
= drm_detect_monitor_audio(edid
);
4546 intel_dp_set_property(struct drm_connector
*connector
,
4547 struct drm_property
*property
,
4550 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4551 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4552 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4553 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4556 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4560 if (property
== dev_priv
->force_audio_property
) {
4564 if (i
== intel_dp
->force_audio
)
4567 intel_dp
->force_audio
= i
;
4569 if (i
== HDMI_AUDIO_AUTO
)
4570 has_audio
= intel_dp_detect_audio(connector
);
4572 has_audio
= (i
== HDMI_AUDIO_ON
);
4574 if (has_audio
== intel_dp
->has_audio
)
4577 intel_dp
->has_audio
= has_audio
;
4581 if (property
== dev_priv
->broadcast_rgb_property
) {
4582 bool old_auto
= intel_dp
->color_range_auto
;
4583 uint32_t old_range
= intel_dp
->color_range
;
4586 case INTEL_BROADCAST_RGB_AUTO
:
4587 intel_dp
->color_range_auto
= true;
4589 case INTEL_BROADCAST_RGB_FULL
:
4590 intel_dp
->color_range_auto
= false;
4591 intel_dp
->color_range
= 0;
4593 case INTEL_BROADCAST_RGB_LIMITED
:
4594 intel_dp
->color_range_auto
= false;
4595 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4601 if (old_auto
== intel_dp
->color_range_auto
&&
4602 old_range
== intel_dp
->color_range
)
4608 if (is_edp(intel_dp
) &&
4609 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4610 if (val
== DRM_MODE_SCALE_NONE
) {
4611 DRM_DEBUG_KMS("no scaling not supported\n");
4615 if (intel_connector
->panel
.fitting_mode
== val
) {
4616 /* the eDP scaling property is not changed */
4619 intel_connector
->panel
.fitting_mode
= val
;
4627 if (intel_encoder
->base
.crtc
)
4628 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4634 intel_dp_connector_destroy(struct drm_connector
*connector
)
4636 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4638 kfree(intel_connector
->detect_edid
);
4640 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4641 kfree(intel_connector
->edid
);
4643 /* Can't call is_edp() since the encoder may have been destroyed
4645 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4646 intel_panel_fini(&intel_connector
->panel
);
4648 drm_connector_cleanup(connector
);
4652 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4654 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4655 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4657 drm_dp_aux_unregister(&intel_dp
->aux
);
4658 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4659 drm_encoder_cleanup(encoder
);
4660 if (is_edp(intel_dp
)) {
4661 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4663 * vdd might still be enabled do to the delayed vdd off.
4664 * Make sure vdd is actually turned off here.
4667 edp_panel_vdd_off_sync(intel_dp
);
4668 pps_unlock(intel_dp
);
4670 if (intel_dp
->edp_notifier
.notifier_call
) {
4671 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4672 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4675 kfree(intel_dig_port
);
4678 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4680 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4682 if (!is_edp(intel_dp
))
4686 * vdd might still be enabled do to the delayed vdd off.
4687 * Make sure vdd is actually turned off here.
4689 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4691 edp_panel_vdd_off_sync(intel_dp
);
4692 pps_unlock(intel_dp
);
4695 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4697 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4698 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4700 enum intel_display_power_domain power_domain
;
4702 lockdep_assert_held(&dev_priv
->pps_mutex
);
4704 if (!edp_have_panel_vdd(intel_dp
))
4708 * The VDD bit needs a power domain reference, so if the bit is
4709 * already enabled when we boot or resume, grab this reference and
4710 * schedule a vdd off, so we don't hold on to the reference
4713 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4714 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4715 intel_display_power_get(dev_priv
, power_domain
);
4717 edp_panel_vdd_schedule_off(intel_dp
);
4720 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4722 struct intel_dp
*intel_dp
;
4724 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4727 intel_dp
= enc_to_intel_dp(encoder
);
4732 * Read out the current power sequencer assignment,
4733 * in case the BIOS did something with it.
4735 if (IS_VALLEYVIEW(encoder
->dev
))
4736 vlv_initial_power_sequencer_setup(intel_dp
);
4738 intel_edp_panel_vdd_sanitize(intel_dp
);
4740 pps_unlock(intel_dp
);
4743 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4744 .dpms
= intel_connector_dpms
,
4745 .detect
= intel_dp_detect
,
4746 .force
= intel_dp_force
,
4747 .fill_modes
= drm_helper_probe_single_connector_modes
,
4748 .set_property
= intel_dp_set_property
,
4749 .destroy
= intel_dp_connector_destroy
,
4752 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4753 .get_modes
= intel_dp_get_modes
,
4754 .mode_valid
= intel_dp_mode_valid
,
4755 .best_encoder
= intel_best_encoder
,
4758 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4759 .reset
= intel_dp_encoder_reset
,
4760 .destroy
= intel_dp_encoder_destroy
,
4764 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4770 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4772 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4773 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4774 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4776 enum intel_display_power_domain power_domain
;
4779 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4780 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4782 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4784 * vdd off can generate a long pulse on eDP which
4785 * would require vdd on to handle it, and thus we
4786 * would end up in an endless cycle of
4787 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4789 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4790 port_name(intel_dig_port
->port
));
4794 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4795 port_name(intel_dig_port
->port
),
4796 long_hpd
? "long" : "short");
4798 power_domain
= intel_display_port_power_domain(intel_encoder
);
4799 intel_display_power_get(dev_priv
, power_domain
);
4803 if (HAS_PCH_SPLIT(dev
)) {
4804 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4807 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4811 if (!intel_dp_get_dpcd(intel_dp
)) {
4815 intel_dp_probe_oui(intel_dp
);
4817 if (!intel_dp_probe_mst(intel_dp
))
4821 if (intel_dp
->is_mst
) {
4822 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4826 if (!intel_dp
->is_mst
) {
4828 * we'll check the link status via the normal hot plug path later -
4829 * but for short hpds we should check it now
4831 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4832 intel_dp_check_link_status(intel_dp
);
4833 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4839 /* if we were in MST mode, and device is not there get out of MST mode */
4840 if (intel_dp
->is_mst
) {
4841 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4842 intel_dp
->is_mst
= false;
4843 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4846 intel_display_power_put(dev_priv
, power_domain
);
4851 /* Return which DP Port should be selected for Transcoder DP control */
4853 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4855 struct drm_device
*dev
= crtc
->dev
;
4856 struct intel_encoder
*intel_encoder
;
4857 struct intel_dp
*intel_dp
;
4859 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4860 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4862 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4863 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4864 return intel_dp
->output_reg
;
4870 /* check the VBT to see whether the eDP is on DP-D port */
4871 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4874 union child_device_config
*p_child
;
4876 static const short port_mapping
[] = {
4877 [PORT_B
] = PORT_IDPB
,
4878 [PORT_C
] = PORT_IDPC
,
4879 [PORT_D
] = PORT_IDPD
,
4885 if (!dev_priv
->vbt
.child_dev_num
)
4888 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4889 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4891 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4892 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4893 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4900 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4902 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4904 intel_attach_force_audio_property(connector
);
4905 intel_attach_broadcast_rgb_property(connector
);
4906 intel_dp
->color_range_auto
= true;
4908 if (is_edp(intel_dp
)) {
4909 drm_mode_create_scaling_mode_property(connector
->dev
);
4910 drm_object_attach_property(
4912 connector
->dev
->mode_config
.scaling_mode_property
,
4913 DRM_MODE_SCALE_ASPECT
);
4914 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4918 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4920 intel_dp
->last_power_cycle
= jiffies
;
4921 intel_dp
->last_power_on
= jiffies
;
4922 intel_dp
->last_backlight_off
= jiffies
;
4926 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4927 struct intel_dp
*intel_dp
)
4929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4930 struct edp_power_seq cur
, vbt
, spec
,
4931 *final
= &intel_dp
->pps_delays
;
4932 u32 pp_on
, pp_off
, pp_div
, pp
;
4933 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4935 lockdep_assert_held(&dev_priv
->pps_mutex
);
4937 /* already initialized? */
4938 if (final
->t11_t12
!= 0)
4941 if (HAS_PCH_SPLIT(dev
)) {
4942 pp_ctrl_reg
= PCH_PP_CONTROL
;
4943 pp_on_reg
= PCH_PP_ON_DELAYS
;
4944 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4945 pp_div_reg
= PCH_PP_DIVISOR
;
4947 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4949 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4950 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4951 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4952 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4955 /* Workaround: Need to write PP_CONTROL with the unlock key as
4956 * the very first thing. */
4957 pp
= ironlake_get_pp_control(intel_dp
);
4958 I915_WRITE(pp_ctrl_reg
, pp
);
4960 pp_on
= I915_READ(pp_on_reg
);
4961 pp_off
= I915_READ(pp_off_reg
);
4962 pp_div
= I915_READ(pp_div_reg
);
4964 /* Pull timing values out of registers */
4965 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4966 PANEL_POWER_UP_DELAY_SHIFT
;
4968 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4969 PANEL_LIGHT_ON_DELAY_SHIFT
;
4971 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4972 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4974 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4975 PANEL_POWER_DOWN_DELAY_SHIFT
;
4977 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4978 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4980 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4981 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4983 vbt
= dev_priv
->vbt
.edp_pps
;
4985 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4986 * our hw here, which are all in 100usec. */
4987 spec
.t1_t3
= 210 * 10;
4988 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4989 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4990 spec
.t10
= 500 * 10;
4991 /* This one is special and actually in units of 100ms, but zero
4992 * based in the hw (so we need to add 100 ms). But the sw vbt
4993 * table multiplies it with 1000 to make it in units of 100usec,
4995 spec
.t11_t12
= (510 + 100) * 10;
4997 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4998 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5000 /* Use the max of the register settings and vbt. If both are
5001 * unset, fall back to the spec limits. */
5002 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5004 max(cur.field, vbt.field))
5005 assign_final(t1_t3
);
5009 assign_final(t11_t12
);
5012 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5013 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5014 intel_dp
->backlight_on_delay
= get_delay(t8
);
5015 intel_dp
->backlight_off_delay
= get_delay(t9
);
5016 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5017 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5020 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5021 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5022 intel_dp
->panel_power_cycle_delay
);
5024 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5025 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5029 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5030 struct intel_dp
*intel_dp
)
5032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5033 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5034 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5035 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
5036 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5037 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5039 lockdep_assert_held(&dev_priv
->pps_mutex
);
5041 if (HAS_PCH_SPLIT(dev
)) {
5042 pp_on_reg
= PCH_PP_ON_DELAYS
;
5043 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5044 pp_div_reg
= PCH_PP_DIVISOR
;
5046 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5048 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5049 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5050 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5054 * And finally store the new values in the power sequencer. The
5055 * backlight delays are set to 1 because we do manual waits on them. For
5056 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5057 * we'll end up waiting for the backlight off delay twice: once when we
5058 * do the manual sleep, and once when we disable the panel and wait for
5059 * the PP_STATUS bit to become zero.
5061 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5062 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5063 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5064 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5065 /* Compute the divisor for the pp clock, simply match the Bspec
5067 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5068 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5069 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5071 /* Haswell doesn't have any port selection bits for the panel
5072 * power sequencer any more. */
5073 if (IS_VALLEYVIEW(dev
)) {
5074 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5075 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5077 port_sel
= PANEL_PORT_SELECT_DPA
;
5079 port_sel
= PANEL_PORT_SELECT_DPD
;
5084 I915_WRITE(pp_on_reg
, pp_on
);
5085 I915_WRITE(pp_off_reg
, pp_off
);
5086 I915_WRITE(pp_div_reg
, pp_div
);
5088 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5089 I915_READ(pp_on_reg
),
5090 I915_READ(pp_off_reg
),
5091 I915_READ(pp_div_reg
));
5094 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5097 struct intel_encoder
*encoder
;
5098 struct intel_dp
*intel_dp
= NULL
;
5099 struct intel_crtc_config
*config
= NULL
;
5100 struct intel_crtc
*intel_crtc
= NULL
;
5101 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
5103 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5105 if (refresh_rate
<= 0) {
5106 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5110 if (intel_connector
== NULL
) {
5111 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
5116 * FIXME: This needs proper synchronization with psr state. But really
5117 * hard to tell without seeing the user of this function of this code.
5118 * Check locking and ordering once that lands.
5120 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
5121 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
5125 encoder
= intel_attached_encoder(&intel_connector
->base
);
5126 intel_dp
= enc_to_intel_dp(&encoder
->base
);
5127 intel_crtc
= encoder
->new_crtc
;
5130 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5134 config
= &intel_crtc
->config
;
5136 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
5137 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5141 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
5142 index
= DRRS_LOW_RR
;
5144 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
5146 "DRRS requested for previously set RR...ignoring\n");
5150 if (!intel_crtc
->active
) {
5151 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5155 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
5156 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
5157 val
= I915_READ(reg
);
5158 if (index
> DRRS_HIGH_RR
) {
5159 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5160 intel_dp_set_m_n(intel_crtc
);
5162 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5164 I915_WRITE(reg
, val
);
5168 * mutex taken to ensure that there is no race between differnt
5169 * drrs calls trying to update refresh rate. This scenario may occur
5170 * in future when idleness detection based DRRS in kernel and
5171 * possible calls from user space to set differnt RR are made.
5174 mutex_lock(&intel_dp
->drrs_state
.mutex
);
5176 intel_dp
->drrs_state
.refresh_rate_type
= index
;
5178 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
5180 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5183 static struct drm_display_mode
*
5184 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
5185 struct intel_connector
*intel_connector
,
5186 struct drm_display_mode
*fixed_mode
)
5188 struct drm_connector
*connector
= &intel_connector
->base
;
5189 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5190 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
5191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5192 struct drm_display_mode
*downclock_mode
= NULL
;
5194 if (INTEL_INFO(dev
)->gen
<= 6) {
5195 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5199 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5200 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5204 downclock_mode
= intel_find_panel_downclock
5205 (dev
, fixed_mode
, connector
);
5207 if (!downclock_mode
) {
5208 DRM_DEBUG_KMS("DRRS not supported\n");
5212 dev_priv
->drrs
.connector
= intel_connector
;
5214 mutex_init(&intel_dp
->drrs_state
.mutex
);
5216 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
5218 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
5219 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5220 return downclock_mode
;
5223 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5224 struct intel_connector
*intel_connector
)
5226 struct drm_connector
*connector
= &intel_connector
->base
;
5227 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5228 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5229 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5231 struct drm_display_mode
*fixed_mode
= NULL
;
5232 struct drm_display_mode
*downclock_mode
= NULL
;
5234 struct drm_display_mode
*scan
;
5237 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
5239 if (!is_edp(intel_dp
))
5243 intel_edp_panel_vdd_sanitize(intel_dp
);
5244 pps_unlock(intel_dp
);
5246 /* Cache DPCD and EDID for edp. */
5247 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5250 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5251 dev_priv
->no_aux_handshake
=
5252 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5253 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5255 /* if this fails, presume the device is a ghost */
5256 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5260 /* We now know it's not a ghost, init power sequence regs. */
5262 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5263 pps_unlock(intel_dp
);
5265 mutex_lock(&dev
->mode_config
.mutex
);
5266 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5268 if (drm_add_edid_modes(connector
, edid
)) {
5269 drm_mode_connector_update_edid_property(connector
,
5271 drm_edid_to_eld(connector
, edid
);
5274 edid
= ERR_PTR(-EINVAL
);
5277 edid
= ERR_PTR(-ENOENT
);
5279 intel_connector
->edid
= edid
;
5281 /* prefer fixed mode from EDID if available */
5282 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5283 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5284 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5285 downclock_mode
= intel_dp_drrs_init(
5287 intel_connector
, fixed_mode
);
5292 /* fallback to VBT if available for eDP */
5293 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5294 fixed_mode
= drm_mode_duplicate(dev
,
5295 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5297 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5299 mutex_unlock(&dev
->mode_config
.mutex
);
5301 if (IS_VALLEYVIEW(dev
)) {
5302 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5303 register_reboot_notifier(&intel_dp
->edp_notifier
);
5306 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5307 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5308 intel_panel_setup_backlight(connector
);
5314 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5315 struct intel_connector
*intel_connector
)
5317 struct drm_connector
*connector
= &intel_connector
->base
;
5318 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5319 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5320 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5322 enum port port
= intel_dig_port
->port
;
5325 intel_dp
->pps_pipe
= INVALID_PIPE
;
5327 /* intel_dp vfuncs */
5328 if (INTEL_INFO(dev
)->gen
>= 9)
5329 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5330 else if (IS_VALLEYVIEW(dev
))
5331 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5332 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5333 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5334 else if (HAS_PCH_SPLIT(dev
))
5335 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5337 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5339 if (INTEL_INFO(dev
)->gen
>= 9)
5340 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5342 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5344 /* Preserve the current hw state. */
5345 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5346 intel_dp
->attached_connector
= intel_connector
;
5348 if (intel_dp_is_edp(dev
, port
))
5349 type
= DRM_MODE_CONNECTOR_eDP
;
5351 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5354 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5355 * for DP the encoder type can be set by the caller to
5356 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5358 if (type
== DRM_MODE_CONNECTOR_eDP
)
5359 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5361 /* eDP only on port B and/or C on vlv/chv */
5362 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5363 port
!= PORT_B
&& port
!= PORT_C
))
5366 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5367 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5370 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5371 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5373 connector
->interlace_allowed
= true;
5374 connector
->doublescan_allowed
= 0;
5376 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5377 edp_panel_vdd_work
);
5379 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5380 drm_connector_register(connector
);
5383 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5385 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5386 intel_connector
->unregister
= intel_dp_connector_unregister
;
5388 /* Set up the hotplug pin. */
5391 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5394 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5397 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5400 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5406 if (is_edp(intel_dp
)) {
5408 intel_dp_init_panel_power_timestamps(intel_dp
);
5409 if (IS_VALLEYVIEW(dev
))
5410 vlv_initial_power_sequencer_setup(intel_dp
);
5412 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5413 pps_unlock(intel_dp
);
5416 intel_dp_aux_init(intel_dp
, intel_connector
);
5418 /* init MST on ports that can support it */
5419 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5420 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5421 intel_dp_mst_encoder_init(intel_dig_port
,
5422 intel_connector
->base
.base
.id
);
5426 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5427 drm_dp_aux_unregister(&intel_dp
->aux
);
5428 if (is_edp(intel_dp
)) {
5429 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5431 * vdd might still be enabled do to the delayed vdd off.
5432 * Make sure vdd is actually turned off here.
5435 edp_panel_vdd_off_sync(intel_dp
);
5436 pps_unlock(intel_dp
);
5438 drm_connector_unregister(connector
);
5439 drm_connector_cleanup(connector
);
5443 intel_dp_add_properties(intel_dp
, connector
);
5445 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5446 * 0xd. Failure to do so will result in spurious interrupts being
5447 * generated on the port when a cable is not attached.
5449 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5450 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5451 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5458 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5461 struct intel_digital_port
*intel_dig_port
;
5462 struct intel_encoder
*intel_encoder
;
5463 struct drm_encoder
*encoder
;
5464 struct intel_connector
*intel_connector
;
5466 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5467 if (!intel_dig_port
)
5470 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5471 if (!intel_connector
) {
5472 kfree(intel_dig_port
);
5476 intel_encoder
= &intel_dig_port
->base
;
5477 encoder
= &intel_encoder
->base
;
5479 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5480 DRM_MODE_ENCODER_TMDS
);
5482 intel_encoder
->compute_config
= intel_dp_compute_config
;
5483 intel_encoder
->disable
= intel_disable_dp
;
5484 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5485 intel_encoder
->get_config
= intel_dp_get_config
;
5486 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5487 if (IS_CHERRYVIEW(dev
)) {
5488 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5489 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5490 intel_encoder
->enable
= vlv_enable_dp
;
5491 intel_encoder
->post_disable
= chv_post_disable_dp
;
5492 } else if (IS_VALLEYVIEW(dev
)) {
5493 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5494 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5495 intel_encoder
->enable
= vlv_enable_dp
;
5496 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5498 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5499 intel_encoder
->enable
= g4x_enable_dp
;
5500 if (INTEL_INFO(dev
)->gen
>= 5)
5501 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5504 intel_dig_port
->port
= port
;
5505 intel_dig_port
->dp
.output_reg
= output_reg
;
5507 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5508 if (IS_CHERRYVIEW(dev
)) {
5510 intel_encoder
->crtc_mask
= 1 << 2;
5512 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5514 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5516 intel_encoder
->cloneable
= 0;
5517 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5519 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5520 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5522 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5523 drm_encoder_cleanup(encoder
);
5524 kfree(intel_dig_port
);
5525 kfree(intel_connector
);
5529 void intel_dp_mst_suspend(struct drm_device
*dev
)
5531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5535 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5536 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5537 if (!intel_dig_port
)
5540 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5541 if (!intel_dig_port
->dp
.can_mst
)
5543 if (intel_dig_port
->dp
.is_mst
)
5544 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5549 void intel_dp_mst_resume(struct drm_device
*dev
)
5551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5555 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5556 if (!intel_dig_port
)
5558 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5561 if (!intel_dig_port
->dp
.can_mst
)
5564 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5566 intel_dp_check_mst_status(&intel_dig_port
->dp
);