2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include "intel_drv.h"
43 #include <drm/i915_drm.h>
46 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
47 #define DP_DPRX_ESI_LEN 14
49 /* Compliance test status bits */
50 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
51 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
52 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
53 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
60 static const struct dp_link_dpll gen4_dpll
[] = {
62 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
64 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
67 static const struct dp_link_dpll pch_dpll
[] = {
69 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
71 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
74 static const struct dp_link_dpll vlv_dpll
[] = {
76 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
78 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
82 * CHV supports eDP 1.4 that have more link rates.
83 * Below only provides the fixed rate but exclude variable rate.
85 static const struct dp_link_dpll chv_dpll
[] = {
87 * CHV requires to program fractional division for m2.
88 * m2 is stored in fixed point format using formula below
89 * (m2_int << 22) | m2_fraction
91 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
92 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
93 { 270000, /* m2_int = 27, m2_fraction = 0 */
94 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
95 { 540000, /* m2_int = 27, m2_fraction = 0 */
96 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
100 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
101 * @intel_dp: DP struct
103 * If a CPU or PCH DP output is attached to an eDP panel, this function
104 * will return true, and false otherwise.
106 bool intel_dp_is_edp(struct intel_dp
*intel_dp
)
108 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
110 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
113 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
115 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
117 return intel_dig_port
->base
.base
.dev
;
120 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
122 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
125 static void intel_dp_link_down(struct intel_encoder
*encoder
,
126 const struct intel_crtc_state
*old_crtc_state
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
130 const struct intel_crtc_state
*crtc_state
);
131 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
133 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 /* update sink rates from dpcd */
136 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
138 static const int dp_rates
[] = {
139 162000, 270000, 540000, 810000
143 max_rate
= drm_dp_bw_code_to_link_rate(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
145 for (i
= 0; i
< ARRAY_SIZE(dp_rates
); i
++) {
146 if (dp_rates
[i
] > max_rate
)
148 intel_dp
->sink_rates
[i
] = dp_rates
[i
];
151 intel_dp
->num_sink_rates
= i
;
154 /* Get length of rates array potentially limited by max_rate. */
155 static int intel_dp_rate_limit_len(const int *rates
, int len
, int max_rate
)
159 /* Limit results by potentially reduced max rate */
160 for (i
= 0; i
< len
; i
++) {
161 if (rates
[len
- i
- 1] <= max_rate
)
168 /* Get length of common rates array potentially limited by max_rate. */
169 static int intel_dp_common_len_rate_limit(const struct intel_dp
*intel_dp
,
172 return intel_dp_rate_limit_len(intel_dp
->common_rates
,
173 intel_dp
->num_common_rates
, max_rate
);
176 /* Theoretical max between source and sink */
177 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
179 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
182 /* Theoretical max between source and sink */
183 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
185 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
186 int source_max
= intel_dig_port
->max_lanes
;
187 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
189 return min(source_max
, sink_max
);
192 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
194 return intel_dp
->max_link_lane_count
;
198 intel_dp_link_required(int pixel_clock
, int bpp
)
200 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
201 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
205 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
207 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
208 * link rate that is generally expressed in Gbps. Since, 8 bits of data
209 * is transmitted every LS_Clk per lane, there is no need to account for
210 * the channel encoding that is done in the PHY layer here.
213 return max_link_clock
* max_lanes
;
217 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
219 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
220 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
221 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
222 int max_dotclk
= dev_priv
->max_dotclk_freq
;
225 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
227 if (type
!= DP_DS_PORT_TYPE_VGA
)
230 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
231 intel_dp
->downstream_ports
);
233 if (ds_max_dotclk
!= 0)
234 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
239 static int cnl_max_source_rate(struct intel_dp
*intel_dp
)
241 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
242 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
243 enum port port
= dig_port
->base
.port
;
245 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
247 /* Low voltage SKUs are limited to max of 5.4G */
248 if (voltage
== VOLTAGE_INFO_0_85V
)
251 /* For this SKU 8.1G is supported in all ports */
252 if (IS_CNL_WITH_PORT_F(dev_priv
))
255 /* For other SKUs, max rate on ports A and D is 5.4G */
256 if (port
== PORT_A
|| port
== PORT_D
)
263 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
265 /* The values must be in increasing order */
266 static const int cnl_rates
[] = {
267 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
269 static const int bxt_rates
[] = {
270 162000, 216000, 243000, 270000, 324000, 432000, 540000
272 static const int skl_rates
[] = {
273 162000, 216000, 270000, 324000, 432000, 540000
275 static const int hsw_rates
[] = {
276 162000, 270000, 540000
278 static const int g4x_rates
[] = {
281 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
282 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
283 const struct ddi_vbt_port_info
*info
=
284 &dev_priv
->vbt
.ddi_port_info
[dig_port
->base
.port
];
285 const int *source_rates
;
286 int size
, max_rate
= 0, vbt_max_rate
= info
->dp_max_link_rate
;
288 /* This should only be done once */
289 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
291 if (IS_CANNONLAKE(dev_priv
)) {
292 source_rates
= cnl_rates
;
293 size
= ARRAY_SIZE(cnl_rates
);
294 max_rate
= cnl_max_source_rate(intel_dp
);
295 } else if (IS_GEN9_LP(dev_priv
)) {
296 source_rates
= bxt_rates
;
297 size
= ARRAY_SIZE(bxt_rates
);
298 } else if (IS_GEN9_BC(dev_priv
)) {
299 source_rates
= skl_rates
;
300 size
= ARRAY_SIZE(skl_rates
);
301 } else if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
302 IS_BROADWELL(dev_priv
)) {
303 source_rates
= hsw_rates
;
304 size
= ARRAY_SIZE(hsw_rates
);
306 source_rates
= g4x_rates
;
307 size
= ARRAY_SIZE(g4x_rates
);
310 if (max_rate
&& vbt_max_rate
)
311 max_rate
= min(max_rate
, vbt_max_rate
);
312 else if (vbt_max_rate
)
313 max_rate
= vbt_max_rate
;
316 size
= intel_dp_rate_limit_len(source_rates
, size
, max_rate
);
318 intel_dp
->source_rates
= source_rates
;
319 intel_dp
->num_source_rates
= size
;
322 static int intersect_rates(const int *source_rates
, int source_len
,
323 const int *sink_rates
, int sink_len
,
326 int i
= 0, j
= 0, k
= 0;
328 while (i
< source_len
&& j
< sink_len
) {
329 if (source_rates
[i
] == sink_rates
[j
]) {
330 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
332 common_rates
[k
] = source_rates
[i
];
336 } else if (source_rates
[i
] < sink_rates
[j
]) {
345 /* return index of rate in rates array, or -1 if not found */
346 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
350 for (i
= 0; i
< len
; i
++)
351 if (rate
== rates
[i
])
357 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
359 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
361 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
362 intel_dp
->num_source_rates
,
363 intel_dp
->sink_rates
,
364 intel_dp
->num_sink_rates
,
365 intel_dp
->common_rates
);
367 /* Paranoia, there should always be something in common. */
368 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
369 intel_dp
->common_rates
[0] = 162000;
370 intel_dp
->num_common_rates
= 1;
374 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
, int link_rate
,
378 * FIXME: we need to synchronize the current link parameters with
379 * hardware readout. Currently fast link training doesn't work on
382 if (link_rate
== 0 ||
383 link_rate
> intel_dp
->max_link_rate
)
386 if (lane_count
== 0 ||
387 lane_count
> intel_dp_max_lane_count(intel_dp
))
393 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
394 int link_rate
, uint8_t lane_count
)
398 index
= intel_dp_rate_index(intel_dp
->common_rates
,
399 intel_dp
->num_common_rates
,
402 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
403 intel_dp
->max_link_lane_count
= lane_count
;
404 } else if (lane_count
> 1) {
405 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
406 intel_dp
->max_link_lane_count
= lane_count
>> 1;
408 DRM_ERROR("Link Training Unsuccessful\n");
415 static enum drm_mode_status
416 intel_dp_mode_valid(struct drm_connector
*connector
,
417 struct drm_display_mode
*mode
)
419 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
420 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
421 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
422 int target_clock
= mode
->clock
;
423 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
426 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
428 if (intel_dp_is_edp(intel_dp
) && fixed_mode
) {
429 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
432 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
435 target_clock
= fixed_mode
->clock
;
438 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
439 max_lanes
= intel_dp_max_lane_count(intel_dp
);
441 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
442 mode_rate
= intel_dp_link_required(target_clock
, 18);
444 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
445 return MODE_CLOCK_HIGH
;
447 if (mode
->clock
< 10000)
448 return MODE_CLOCK_LOW
;
450 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
451 return MODE_H_ILLEGAL
;
456 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
463 for (i
= 0; i
< src_bytes
; i
++)
464 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
468 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
473 for (i
= 0; i
< dst_bytes
; i
++)
474 dst
[i
] = src
>> ((3-i
) * 8);
478 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
480 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
481 bool force_disable_vdd
);
483 intel_dp_pps_init(struct intel_dp
*intel_dp
);
485 static void pps_lock(struct intel_dp
*intel_dp
)
487 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
490 * See intel_power_sequencer_reset() why we need
491 * a power domain reference here.
493 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
495 mutex_lock(&dev_priv
->pps_mutex
);
498 static void pps_unlock(struct intel_dp
*intel_dp
)
500 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
502 mutex_unlock(&dev_priv
->pps_mutex
);
504 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
508 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
510 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
511 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
512 enum pipe pipe
= intel_dp
->pps_pipe
;
513 bool pll_enabled
, release_cl_override
= false;
514 enum dpio_phy phy
= DPIO_PHY(pipe
);
515 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
518 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
519 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
520 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
)))
523 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
524 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
526 /* Preserve the BIOS-computed detected bit. This is
527 * supposed to be read-only.
529 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
530 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
531 DP
|= DP_PORT_WIDTH(1);
532 DP
|= DP_LINK_TRAIN_PAT_1
;
534 if (IS_CHERRYVIEW(dev_priv
))
535 DP
|= DP_PIPE_SELECT_CHV(pipe
);
536 else if (pipe
== PIPE_B
)
537 DP
|= DP_PIPEB_SELECT
;
539 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
542 * The DPLL for the pipe must be enabled for this to work.
543 * So enable temporarily it if it's not already enabled.
546 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
547 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
549 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
550 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
551 DRM_ERROR("Failed to force on pll for pipe %c!\n",
558 * Similar magic as in intel_dp_enable_port().
559 * We _must_ do this port enable + disable trick
560 * to make this power seqeuencer lock onto the port.
561 * Otherwise even VDD force bit won't work.
563 I915_WRITE(intel_dp
->output_reg
, DP
);
564 POSTING_READ(intel_dp
->output_reg
);
566 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
567 POSTING_READ(intel_dp
->output_reg
);
569 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
570 POSTING_READ(intel_dp
->output_reg
);
573 vlv_force_pll_off(dev_priv
, pipe
);
575 if (release_cl_override
)
576 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
580 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
582 struct intel_encoder
*encoder
;
583 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
586 * We don't have power sequencer currently.
587 * Pick one that's not used by other ports.
589 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
590 struct intel_dp
*intel_dp
;
592 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
593 encoder
->type
!= INTEL_OUTPUT_EDP
)
596 intel_dp
= enc_to_intel_dp(&encoder
->base
);
598 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
599 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
600 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
602 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
603 pipes
&= ~(1 << intel_dp
->pps_pipe
);
605 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
607 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
608 pipes
&= ~(1 << intel_dp
->active_pipe
);
615 return ffs(pipes
) - 1;
619 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
621 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
622 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
625 lockdep_assert_held(&dev_priv
->pps_mutex
);
627 /* We should never land here with regular DP ports */
628 WARN_ON(!intel_dp_is_edp(intel_dp
));
630 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
631 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
633 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
634 return intel_dp
->pps_pipe
;
636 pipe
= vlv_find_free_pps(dev_priv
);
639 * Didn't find one. This should not happen since there
640 * are two power sequencers and up to two eDP ports.
642 if (WARN_ON(pipe
== INVALID_PIPE
))
645 vlv_steal_power_sequencer(dev_priv
, pipe
);
646 intel_dp
->pps_pipe
= pipe
;
648 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
649 pipe_name(intel_dp
->pps_pipe
),
650 port_name(intel_dig_port
->base
.port
));
652 /* init power sequencer on this pipe and port */
653 intel_dp_init_panel_power_sequencer(intel_dp
);
654 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
657 * Even vdd force doesn't work until we've made
658 * the power sequencer lock in on the port.
660 vlv_power_sequencer_kick(intel_dp
);
662 return intel_dp
->pps_pipe
;
666 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
668 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
669 int backlight_controller
= dev_priv
->vbt
.backlight
.controller
;
671 lockdep_assert_held(&dev_priv
->pps_mutex
);
673 /* We should never land here with regular DP ports */
674 WARN_ON(!intel_dp_is_edp(intel_dp
));
676 if (!intel_dp
->pps_reset
)
677 return backlight_controller
;
679 intel_dp
->pps_reset
= false;
682 * Only the HW needs to be reprogrammed, the SW state is fixed and
683 * has been setup during connector init.
685 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
687 return backlight_controller
;
690 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
693 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
696 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
699 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
702 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
705 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
712 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
714 vlv_pipe_check pipe_check
)
718 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
719 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
720 PANEL_PORT_SELECT_MASK
;
722 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
725 if (!pipe_check(dev_priv
, pipe
))
735 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
737 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
738 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
739 enum port port
= intel_dig_port
->base
.port
;
741 lockdep_assert_held(&dev_priv
->pps_mutex
);
743 /* try to find a pipe with this port selected */
744 /* first pick one where the panel is on */
745 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
747 /* didn't find one? pick one where vdd is on */
748 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
749 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
750 vlv_pipe_has_vdd_on
);
751 /* didn't find one? pick one with just the correct port */
752 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
753 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
756 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
757 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
758 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
763 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
764 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
766 intel_dp_init_panel_power_sequencer(intel_dp
);
767 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
770 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
772 struct intel_encoder
*encoder
;
774 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
775 !IS_GEN9_LP(dev_priv
)))
779 * We can't grab pps_mutex here due to deadlock with power_domain
780 * mutex when power_domain functions are called while holding pps_mutex.
781 * That also means that in order to use pps_pipe the code needs to
782 * hold both a power domain reference and pps_mutex, and the power domain
783 * reference get/put must be done while _not_ holding pps_mutex.
784 * pps_{lock,unlock}() do these steps in the correct order, so one
785 * should use them always.
788 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
789 struct intel_dp
*intel_dp
;
791 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
792 encoder
->type
!= INTEL_OUTPUT_EDP
&&
793 encoder
->type
!= INTEL_OUTPUT_DDI
)
796 intel_dp
= enc_to_intel_dp(&encoder
->base
);
798 /* Skip pure DVI/HDMI DDI encoders */
799 if (!i915_mmio_reg_valid(intel_dp
->output_reg
))
802 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
804 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
807 if (IS_GEN9_LP(dev_priv
))
808 intel_dp
->pps_reset
= true;
810 intel_dp
->pps_pipe
= INVALID_PIPE
;
814 struct pps_registers
{
822 static void intel_pps_get_registers(struct intel_dp
*intel_dp
,
823 struct pps_registers
*regs
)
825 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
828 memset(regs
, 0, sizeof(*regs
));
830 if (IS_GEN9_LP(dev_priv
))
831 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
832 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
833 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
835 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
836 regs
->pp_stat
= PP_STATUS(pps_idx
);
837 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
838 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
839 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
840 !HAS_PCH_ICP(dev_priv
))
841 regs
->pp_div
= PP_DIVISOR(pps_idx
);
845 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
847 struct pps_registers regs
;
849 intel_pps_get_registers(intel_dp
, ®s
);
855 _pp_stat_reg(struct intel_dp
*intel_dp
)
857 struct pps_registers regs
;
859 intel_pps_get_registers(intel_dp
, ®s
);
864 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
865 This function only applicable when panel PM state is not to be tracked */
866 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
869 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
871 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
873 if (!intel_dp_is_edp(intel_dp
) || code
!= SYS_RESTART
)
878 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
879 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
880 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
883 pp_ctrl_reg
= PP_CONTROL(pipe
);
884 pp_div_reg
= PP_DIVISOR(pipe
);
885 pp_div
= I915_READ(pp_div_reg
);
886 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
888 /* 0x1F write to PP_DIV_REG sets max cycle delay */
889 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
890 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
891 msleep(intel_dp
->panel_power_cycle_delay
);
894 pps_unlock(intel_dp
);
899 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
901 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
903 lockdep_assert_held(&dev_priv
->pps_mutex
);
905 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
906 intel_dp
->pps_pipe
== INVALID_PIPE
)
909 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
912 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
914 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
916 lockdep_assert_held(&dev_priv
->pps_mutex
);
918 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
919 intel_dp
->pps_pipe
== INVALID_PIPE
)
922 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
926 intel_dp_check_edp(struct intel_dp
*intel_dp
)
928 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
930 if (!intel_dp_is_edp(intel_dp
))
933 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
934 WARN(1, "eDP powered off while attempting aux channel communication.\n");
935 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
936 I915_READ(_pp_stat_reg(intel_dp
)),
937 I915_READ(_pp_ctrl_reg(intel_dp
)));
942 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
944 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
945 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
949 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
951 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
952 msecs_to_jiffies_timeout(10));
954 done
= wait_for(C
, 10) == 0;
956 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
963 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
965 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
971 * The clock divider is based off the hrawclk, and would like to run at
972 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
974 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
977 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
979 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
985 * The clock divider is based off the cdclk or PCH rawclk, and would
986 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
987 * divide by 2000 and use that
989 if (intel_dp
->aux_ch
== AUX_CH_A
)
990 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
992 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
995 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
997 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
999 if (intel_dp
->aux_ch
!= AUX_CH_A
&& HAS_PCH_LPT_H(dev_priv
)) {
1000 /* Workaround for non-ULT HSW */
1008 return ilk_get_aux_clock_divider(intel_dp
, index
);
1011 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1014 * SKL doesn't need us to program the AUX clock divider (Hardware will
1015 * derive the clock from CDCLK automatically). We still implement the
1016 * get_aux_clock_divider vfunc to plug-in into the existing code.
1018 return index
? 0 : 1;
1021 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1024 uint32_t aux_clock_divider
)
1026 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1027 struct drm_i915_private
*dev_priv
=
1028 to_i915(intel_dig_port
->base
.base
.dev
);
1029 uint32_t precharge
, timeout
;
1031 if (IS_GEN6(dev_priv
))
1036 if (IS_BROADWELL(dev_priv
))
1037 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1039 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1041 return DP_AUX_CH_CTL_SEND_BUSY
|
1042 DP_AUX_CH_CTL_DONE
|
1043 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1044 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1046 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1047 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1048 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1049 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1052 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1057 return DP_AUX_CH_CTL_SEND_BUSY
|
1058 DP_AUX_CH_CTL_DONE
|
1059 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1060 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1061 DP_AUX_CH_CTL_TIME_OUT_MAX
|
1062 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1063 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1064 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1065 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1069 intel_dp_aux_xfer(struct intel_dp
*intel_dp
,
1070 const uint8_t *send
, int send_bytes
,
1071 uint8_t *recv
, int recv_size
,
1072 u32 aux_send_ctl_flags
)
1074 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1075 struct drm_i915_private
*dev_priv
=
1076 to_i915(intel_dig_port
->base
.base
.dev
);
1077 i915_reg_t ch_ctl
, ch_data
[5];
1078 uint32_t aux_clock_divider
;
1079 int i
, ret
, recv_bytes
;
1082 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1085 ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
1086 for (i
= 0; i
< ARRAY_SIZE(ch_data
); i
++)
1087 ch_data
[i
] = intel_dp
->aux_ch_data_reg(intel_dp
, i
);
1092 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1093 * In such cases we want to leave VDD enabled and it's up to upper layers
1094 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1097 vdd
= edp_panel_vdd_on(intel_dp
);
1099 /* dp aux is extremely sensitive to irq latency, hence request the
1100 * lowest possible wakeup latency and so prevent the cpu from going into
1101 * deep sleep states.
1103 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1105 intel_dp_check_edp(intel_dp
);
1107 /* Try to wait for any previous AUX channel activity */
1108 for (try = 0; try < 3; try++) {
1109 status
= I915_READ_NOTRACE(ch_ctl
);
1110 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1116 static u32 last_status
= -1;
1117 const u32 status
= I915_READ(ch_ctl
);
1119 if (status
!= last_status
) {
1120 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1122 last_status
= status
;
1129 /* Only 5 data registers! */
1130 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1135 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1136 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1141 send_ctl
|= aux_send_ctl_flags
;
1143 /* Must try at least 3 times according to DP spec */
1144 for (try = 0; try < 5; try++) {
1145 /* Load the send data into the aux channel data registers */
1146 for (i
= 0; i
< send_bytes
; i
+= 4)
1147 I915_WRITE(ch_data
[i
>> 2],
1148 intel_dp_pack_aux(send
+ i
,
1151 /* Send the command and wait for it to complete */
1152 I915_WRITE(ch_ctl
, send_ctl
);
1154 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1156 /* Clear done status and any errors */
1159 DP_AUX_CH_CTL_DONE
|
1160 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1161 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1163 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1164 * 400us delay required for errors and timeouts
1165 * Timeout errors from the HW already meet this
1166 * requirement so skip to next iteration
1168 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1171 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1172 usleep_range(400, 500);
1175 if (status
& DP_AUX_CH_CTL_DONE
)
1180 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1181 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1187 /* Check for timeout or receive error.
1188 * Timeouts occur when the sink is not connected
1190 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1191 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1196 /* Timeouts occur when the device isn't connected, so they're
1197 * "normal" -- don't fill the kernel log with these */
1198 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1199 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1204 /* Unload any bytes sent back from the other side */
1205 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1206 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1209 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1210 * We have no idea of what happened so we return -EBUSY so
1211 * drm layer takes care for the necessary retries.
1213 if (recv_bytes
== 0 || recv_bytes
> 20) {
1214 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1220 if (recv_bytes
> recv_size
)
1221 recv_bytes
= recv_size
;
1223 for (i
= 0; i
< recv_bytes
; i
+= 4)
1224 intel_dp_unpack_aux(I915_READ(ch_data
[i
>> 2]),
1225 recv
+ i
, recv_bytes
- i
);
1229 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1232 edp_panel_vdd_off(intel_dp
, false);
1234 pps_unlock(intel_dp
);
1239 #define BARE_ADDRESS_SIZE 3
1240 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1243 intel_dp_aux_header(u8 txbuf
[HEADER_SIZE
],
1244 const struct drm_dp_aux_msg
*msg
)
1246 txbuf
[0] = (msg
->request
<< 4) | ((msg
->address
>> 16) & 0xf);
1247 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1248 txbuf
[2] = msg
->address
& 0xff;
1249 txbuf
[3] = msg
->size
- 1;
1253 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1255 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1256 uint8_t txbuf
[20], rxbuf
[20];
1257 size_t txsize
, rxsize
;
1260 intel_dp_aux_header(txbuf
, msg
);
1262 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1263 case DP_AUX_NATIVE_WRITE
:
1264 case DP_AUX_I2C_WRITE
:
1265 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1266 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1267 rxsize
= 2; /* 0 or 1 data bytes */
1269 if (WARN_ON(txsize
> 20))
1272 WARN_ON(!msg
->buffer
!= !msg
->size
);
1275 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1277 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1280 msg
->reply
= rxbuf
[0] >> 4;
1283 /* Number of bytes written in a short write. */
1284 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1286 /* Return payload size. */
1292 case DP_AUX_NATIVE_READ
:
1293 case DP_AUX_I2C_READ
:
1294 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1295 rxsize
= msg
->size
+ 1;
1297 if (WARN_ON(rxsize
> 20))
1300 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1303 msg
->reply
= rxbuf
[0] >> 4;
1305 * Assume happy day, and copy the data. The caller is
1306 * expected to check msg->reply before touching it.
1308 * Return payload size.
1311 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1323 static enum aux_ch
intel_aux_ch(struct intel_dp
*intel_dp
)
1325 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
1326 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1327 enum port port
= encoder
->port
;
1328 const struct ddi_vbt_port_info
*info
=
1329 &dev_priv
->vbt
.ddi_port_info
[port
];
1332 if (!info
->alternate_aux_channel
) {
1333 aux_ch
= (enum aux_ch
) port
;
1335 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1336 aux_ch_name(aux_ch
), port_name(port
));
1340 switch (info
->alternate_aux_channel
) {
1357 MISSING_CASE(info
->alternate_aux_channel
);
1362 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1363 aux_ch_name(aux_ch
), port_name(port
));
1368 static enum intel_display_power_domain
1369 intel_aux_power_domain(struct intel_dp
*intel_dp
)
1371 switch (intel_dp
->aux_ch
) {
1373 return POWER_DOMAIN_AUX_A
;
1375 return POWER_DOMAIN_AUX_B
;
1377 return POWER_DOMAIN_AUX_C
;
1379 return POWER_DOMAIN_AUX_D
;
1381 return POWER_DOMAIN_AUX_F
;
1383 MISSING_CASE(intel_dp
->aux_ch
);
1384 return POWER_DOMAIN_AUX_A
;
1388 static i915_reg_t
g4x_aux_ctl_reg(struct intel_dp
*intel_dp
)
1390 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1391 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1397 return DP_AUX_CH_CTL(aux_ch
);
1399 MISSING_CASE(aux_ch
);
1400 return DP_AUX_CH_CTL(AUX_CH_B
);
1404 static i915_reg_t
g4x_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1406 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1407 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1413 return DP_AUX_CH_DATA(aux_ch
, index
);
1415 MISSING_CASE(aux_ch
);
1416 return DP_AUX_CH_DATA(AUX_CH_B
, index
);
1420 static i915_reg_t
ilk_aux_ctl_reg(struct intel_dp
*intel_dp
)
1422 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1423 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1427 return DP_AUX_CH_CTL(aux_ch
);
1431 return PCH_DP_AUX_CH_CTL(aux_ch
);
1433 MISSING_CASE(aux_ch
);
1434 return DP_AUX_CH_CTL(AUX_CH_A
);
1438 static i915_reg_t
ilk_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1440 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1441 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1445 return DP_AUX_CH_DATA(aux_ch
, index
);
1449 return PCH_DP_AUX_CH_DATA(aux_ch
, index
);
1451 MISSING_CASE(aux_ch
);
1452 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1456 static i915_reg_t
skl_aux_ctl_reg(struct intel_dp
*intel_dp
)
1458 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1459 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1467 return DP_AUX_CH_CTL(aux_ch
);
1469 MISSING_CASE(aux_ch
);
1470 return DP_AUX_CH_CTL(AUX_CH_A
);
1474 static i915_reg_t
skl_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1476 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1477 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1485 return DP_AUX_CH_DATA(aux_ch
, index
);
1487 MISSING_CASE(aux_ch
);
1488 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1493 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1495 kfree(intel_dp
->aux
.name
);
1499 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1501 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1502 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
1504 intel_dp
->aux_ch
= intel_aux_ch(intel_dp
);
1505 intel_dp
->aux_power_domain
= intel_aux_power_domain(intel_dp
);
1507 if (INTEL_GEN(dev_priv
) >= 9) {
1508 intel_dp
->aux_ch_ctl_reg
= skl_aux_ctl_reg
;
1509 intel_dp
->aux_ch_data_reg
= skl_aux_data_reg
;
1510 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1511 intel_dp
->aux_ch_ctl_reg
= ilk_aux_ctl_reg
;
1512 intel_dp
->aux_ch_data_reg
= ilk_aux_data_reg
;
1514 intel_dp
->aux_ch_ctl_reg
= g4x_aux_ctl_reg
;
1515 intel_dp
->aux_ch_data_reg
= g4x_aux_data_reg
;
1518 if (INTEL_GEN(dev_priv
) >= 9)
1519 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
1520 else if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
1521 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
1522 else if (HAS_PCH_SPLIT(dev_priv
))
1523 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
1525 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
1527 if (INTEL_GEN(dev_priv
) >= 9)
1528 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
1530 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
1532 drm_dp_aux_init(&intel_dp
->aux
);
1534 /* Failure to allocate our preferred name is not critical */
1535 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c",
1536 port_name(encoder
->port
));
1537 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1540 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1542 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1544 return max_rate
>= 540000;
1548 intel_dp_set_clock(struct intel_encoder
*encoder
,
1549 struct intel_crtc_state
*pipe_config
)
1551 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1552 const struct dp_link_dpll
*divisor
= NULL
;
1555 if (IS_G4X(dev_priv
)) {
1556 divisor
= gen4_dpll
;
1557 count
= ARRAY_SIZE(gen4_dpll
);
1558 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1560 count
= ARRAY_SIZE(pch_dpll
);
1561 } else if (IS_CHERRYVIEW(dev_priv
)) {
1563 count
= ARRAY_SIZE(chv_dpll
);
1564 } else if (IS_VALLEYVIEW(dev_priv
)) {
1566 count
= ARRAY_SIZE(vlv_dpll
);
1569 if (divisor
&& count
) {
1570 for (i
= 0; i
< count
; i
++) {
1571 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1572 pipe_config
->dpll
= divisor
[i
].dpll
;
1573 pipe_config
->clock_set
= true;
1580 static void snprintf_int_array(char *str
, size_t len
,
1581 const int *array
, int nelem
)
1587 for (i
= 0; i
< nelem
; i
++) {
1588 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1596 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1598 char str
[128]; /* FIXME: too big for stack? */
1600 if ((drm_debug
& DRM_UT_KMS
) == 0)
1603 snprintf_int_array(str
, sizeof(str
),
1604 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1605 DRM_DEBUG_KMS("source rates: %s\n", str
);
1607 snprintf_int_array(str
, sizeof(str
),
1608 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1609 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1611 snprintf_int_array(str
, sizeof(str
),
1612 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1613 DRM_DEBUG_KMS("common rates: %s\n", str
);
1617 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1621 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1622 if (WARN_ON(len
<= 0))
1625 return intel_dp
->common_rates
[len
- 1];
1628 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1630 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1631 intel_dp
->num_sink_rates
, rate
);
1639 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1640 uint8_t *link_bw
, uint8_t *rate_select
)
1642 /* eDP 1.4 rate select method. */
1643 if (intel_dp
->use_rate_select
) {
1646 intel_dp_rate_select(intel_dp
, port_clock
);
1648 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1653 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1654 struct intel_crtc_state
*pipe_config
)
1658 bpp
= pipe_config
->pipe_bpp
;
1659 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1662 bpp
= min(bpp
, 3*bpc
);
1664 /* For DP Compliance we override the computed bpp for the pipe */
1665 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1666 pipe_config
->pipe_bpp
= 3*intel_dp
->compliance
.test_data
.bpc
;
1667 pipe_config
->dither_force_disable
= pipe_config
->pipe_bpp
== 6*3;
1668 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1669 pipe_config
->pipe_bpp
);
1674 static bool intel_edp_compare_alt_mode(struct drm_display_mode
*m1
,
1675 struct drm_display_mode
*m2
)
1680 bres
= (m1
->hdisplay
== m2
->hdisplay
&&
1681 m1
->hsync_start
== m2
->hsync_start
&&
1682 m1
->hsync_end
== m2
->hsync_end
&&
1683 m1
->htotal
== m2
->htotal
&&
1684 m1
->vdisplay
== m2
->vdisplay
&&
1685 m1
->vsync_start
== m2
->vsync_start
&&
1686 m1
->vsync_end
== m2
->vsync_end
&&
1687 m1
->vtotal
== m2
->vtotal
);
1692 intel_dp_compute_config(struct intel_encoder
*encoder
,
1693 struct intel_crtc_state
*pipe_config
,
1694 struct drm_connector_state
*conn_state
)
1696 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1697 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1698 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1699 enum port port
= encoder
->port
;
1700 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1701 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1702 struct intel_digital_connector_state
*intel_conn_state
=
1703 to_intel_digital_connector_state(conn_state
);
1704 int lane_count
, clock
;
1705 int min_lane_count
= 1;
1706 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1707 /* Conveniently, the link BW constants become indices with a shift...*/
1711 int link_avail
, link_clock
;
1713 uint8_t link_bw
, rate_select
;
1714 bool reduce_m_n
= drm_dp_has_quirk(&intel_dp
->desc
,
1715 DP_DPCD_QUIRK_LIMITED_M_N
);
1717 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1718 intel_dp
->max_link_rate
);
1720 /* No common link rates between source and sink */
1721 WARN_ON(common_len
<= 0);
1723 max_clock
= common_len
- 1;
1725 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1726 pipe_config
->has_pch_encoder
= true;
1728 pipe_config
->has_drrs
= false;
1729 if (IS_G4X(dev_priv
) || port
== PORT_A
)
1730 pipe_config
->has_audio
= false;
1731 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1732 pipe_config
->has_audio
= intel_dp
->has_audio
;
1734 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1736 if (intel_dp_is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1737 struct drm_display_mode
*panel_mode
=
1738 intel_connector
->panel
.alt_fixed_mode
;
1739 struct drm_display_mode
*req_mode
= &pipe_config
->base
.mode
;
1741 if (!intel_edp_compare_alt_mode(req_mode
, panel_mode
))
1742 panel_mode
= intel_connector
->panel
.fixed_mode
;
1744 drm_mode_debug_printmodeline(panel_mode
);
1746 intel_fixed_panel_mode(panel_mode
, adjusted_mode
);
1748 if (INTEL_GEN(dev_priv
) >= 9) {
1750 ret
= skl_update_scaler_crtc(pipe_config
);
1755 if (HAS_GMCH_DISPLAY(dev_priv
))
1756 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1757 conn_state
->scaling_mode
);
1759 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1760 conn_state
->scaling_mode
);
1763 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1764 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1767 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1770 /* Use values requested by Compliance Test Request */
1771 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1774 /* Validate the compliance test data since max values
1775 * might have changed due to link train fallback.
1777 if (intel_dp_link_params_valid(intel_dp
, intel_dp
->compliance
.test_link_rate
,
1778 intel_dp
->compliance
.test_lane_count
)) {
1779 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1780 intel_dp
->num_common_rates
,
1781 intel_dp
->compliance
.test_link_rate
);
1783 min_clock
= max_clock
= index
;
1784 min_lane_count
= max_lane_count
= intel_dp
->compliance
.test_lane_count
;
1787 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1788 "max bw %d pixel clock %iKHz\n",
1789 max_lane_count
, intel_dp
->common_rates
[max_clock
],
1790 adjusted_mode
->crtc_clock
);
1792 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1793 * bpc in between. */
1794 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1795 if (intel_dp_is_edp(intel_dp
)) {
1797 /* Get bpp from vbt only for panels that dont have bpp in edid */
1798 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1799 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1800 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1801 dev_priv
->vbt
.edp
.bpp
);
1802 bpp
= dev_priv
->vbt
.edp
.bpp
;
1806 * Use the maximum clock and number of lanes the eDP panel
1807 * advertizes being capable of. The panels are generally
1808 * designed to support only a single clock and lane
1809 * configuration, and typically these values correspond to the
1810 * native resolution of the panel.
1812 min_lane_count
= max_lane_count
;
1813 min_clock
= max_clock
;
1816 for (; bpp
>= 6*3; bpp
-= 2*3) {
1817 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1820 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1821 for (lane_count
= min_lane_count
;
1822 lane_count
<= max_lane_count
;
1825 link_clock
= intel_dp
->common_rates
[clock
];
1826 link_avail
= intel_dp_max_data_rate(link_clock
,
1829 if (mode_rate
<= link_avail
) {
1839 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1842 * CEA-861-E - 5.1 Default Encoding Parameters
1843 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1845 pipe_config
->limited_color_range
=
1847 drm_default_rgb_quant_range(adjusted_mode
) ==
1848 HDMI_QUANTIZATION_RANGE_LIMITED
;
1850 pipe_config
->limited_color_range
=
1851 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1854 pipe_config
->lane_count
= lane_count
;
1856 pipe_config
->pipe_bpp
= bpp
;
1857 pipe_config
->port_clock
= intel_dp
->common_rates
[clock
];
1859 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1860 &link_bw
, &rate_select
);
1862 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1863 link_bw
, rate_select
, pipe_config
->lane_count
,
1864 pipe_config
->port_clock
, bpp
);
1865 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1866 mode_rate
, link_avail
);
1868 intel_link_compute_m_n(bpp
, lane_count
,
1869 adjusted_mode
->crtc_clock
,
1870 pipe_config
->port_clock
,
1871 &pipe_config
->dp_m_n
,
1874 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1875 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1876 pipe_config
->has_drrs
= true;
1877 intel_link_compute_m_n(bpp
, lane_count
,
1878 intel_connector
->panel
.downclock_mode
->clock
,
1879 pipe_config
->port_clock
,
1880 &pipe_config
->dp_m2_n2
,
1885 * DPLL0 VCO may need to be adjusted to get the correct
1886 * clock for eDP. This will affect cdclk as well.
1888 if (intel_dp_is_edp(intel_dp
) && IS_GEN9_BC(dev_priv
)) {
1891 switch (pipe_config
->port_clock
/ 2) {
1901 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk
.logical
.vco
= vco
;
1904 if (!HAS_DDI(dev_priv
))
1905 intel_dp_set_clock(encoder
, pipe_config
);
1907 intel_psr_compute_config(intel_dp
, pipe_config
);
1912 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1913 int link_rate
, uint8_t lane_count
,
1916 intel_dp
->link_rate
= link_rate
;
1917 intel_dp
->lane_count
= lane_count
;
1918 intel_dp
->link_mst
= link_mst
;
1921 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1922 const struct intel_crtc_state
*pipe_config
)
1924 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1925 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1926 enum port port
= encoder
->port
;
1927 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1928 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1930 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1931 pipe_config
->lane_count
,
1932 intel_crtc_has_type(pipe_config
,
1933 INTEL_OUTPUT_DP_MST
));
1936 * There are four kinds of DP registers:
1943 * IBX PCH and CPU are the same for almost everything,
1944 * except that the CPU DP PLL is configured in this
1947 * CPT PCH is quite different, having many bits moved
1948 * to the TRANS_DP_CTL register instead. That
1949 * configuration happens (oddly) in ironlake_pch_enable
1952 /* Preserve the BIOS-computed detected bit. This is
1953 * supposed to be read-only.
1955 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1957 /* Handle DP bits in common between all three register formats */
1958 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1959 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1961 /* Split out the IBX/CPU vs CPT settings */
1963 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1964 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1965 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1966 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1967 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1968 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1970 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1971 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1973 intel_dp
->DP
|= crtc
->pipe
<< 29;
1974 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1977 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1979 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1980 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1981 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1983 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1984 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1986 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
1987 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1989 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1990 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1991 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1992 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1993 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1995 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1996 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1998 if (IS_CHERRYVIEW(dev_priv
))
1999 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
2000 else if (crtc
->pipe
== PIPE_B
)
2001 intel_dp
->DP
|= DP_PIPEB_SELECT
;
2005 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2006 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2008 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2009 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2011 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2012 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2014 static void intel_pps_verify_state(struct intel_dp
*intel_dp
);
2016 static void wait_panel_status(struct intel_dp
*intel_dp
,
2020 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2021 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2023 lockdep_assert_held(&dev_priv
->pps_mutex
);
2025 intel_pps_verify_state(intel_dp
);
2027 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2028 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2030 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2032 I915_READ(pp_stat_reg
),
2033 I915_READ(pp_ctrl_reg
));
2035 if (intel_wait_for_register(dev_priv
,
2036 pp_stat_reg
, mask
, value
,
2038 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2039 I915_READ(pp_stat_reg
),
2040 I915_READ(pp_ctrl_reg
));
2042 DRM_DEBUG_KMS("Wait complete\n");
2045 static void wait_panel_on(struct intel_dp
*intel_dp
)
2047 DRM_DEBUG_KMS("Wait for panel power on\n");
2048 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
2051 static void wait_panel_off(struct intel_dp
*intel_dp
)
2053 DRM_DEBUG_KMS("Wait for panel power off time\n");
2054 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
2057 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
2059 ktime_t panel_power_on_time
;
2060 s64 panel_power_off_duration
;
2062 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2064 /* take the difference of currrent time and panel power off time
2065 * and then make panel wait for t11_t12 if needed. */
2066 panel_power_on_time
= ktime_get_boottime();
2067 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
2069 /* When we disable the VDD override bit last we have to do the manual
2071 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
2072 wait_remaining_ms_from_jiffies(jiffies
,
2073 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
2075 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2078 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2080 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2081 intel_dp
->backlight_on_delay
);
2084 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2086 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2087 intel_dp
->backlight_off_delay
);
2090 /* Read the current pp_control value, unlocking the register if it
2094 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2096 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2099 lockdep_assert_held(&dev_priv
->pps_mutex
);
2101 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2102 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2103 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2104 control
&= ~PANEL_UNLOCK_MASK
;
2105 control
|= PANEL_UNLOCK_REGS
;
2111 * Must be paired with edp_panel_vdd_off().
2112 * Must hold pps_mutex around the whole on/off sequence.
2113 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2115 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2117 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2118 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2120 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2121 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2123 lockdep_assert_held(&dev_priv
->pps_mutex
);
2125 if (!intel_dp_is_edp(intel_dp
))
2128 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2129 intel_dp
->want_panel_vdd
= true;
2131 if (edp_have_panel_vdd(intel_dp
))
2132 return need_to_disable
;
2134 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2136 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2137 port_name(intel_dig_port
->base
.port
));
2139 if (!edp_have_panel_power(intel_dp
))
2140 wait_panel_power_cycle(intel_dp
);
2142 pp
= ironlake_get_pp_control(intel_dp
);
2143 pp
|= EDP_FORCE_VDD
;
2145 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2146 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2148 I915_WRITE(pp_ctrl_reg
, pp
);
2149 POSTING_READ(pp_ctrl_reg
);
2150 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2151 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2153 * If the panel wasn't on, delay before accessing aux channel
2155 if (!edp_have_panel_power(intel_dp
)) {
2156 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2157 port_name(intel_dig_port
->base
.port
));
2158 msleep(intel_dp
->panel_power_up_delay
);
2161 return need_to_disable
;
2165 * Must be paired with intel_edp_panel_vdd_off() or
2166 * intel_edp_panel_off().
2167 * Nested calls to these functions are not allowed since
2168 * we drop the lock. Caller must use some higher level
2169 * locking to prevent nested calls from other threads.
2171 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2175 if (!intel_dp_is_edp(intel_dp
))
2179 vdd
= edp_panel_vdd_on(intel_dp
);
2180 pps_unlock(intel_dp
);
2182 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2183 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2186 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2188 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2189 struct intel_digital_port
*intel_dig_port
=
2190 dp_to_dig_port(intel_dp
);
2192 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2194 lockdep_assert_held(&dev_priv
->pps_mutex
);
2196 WARN_ON(intel_dp
->want_panel_vdd
);
2198 if (!edp_have_panel_vdd(intel_dp
))
2201 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2202 port_name(intel_dig_port
->base
.port
));
2204 pp
= ironlake_get_pp_control(intel_dp
);
2205 pp
&= ~EDP_FORCE_VDD
;
2207 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2208 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2210 I915_WRITE(pp_ctrl_reg
, pp
);
2211 POSTING_READ(pp_ctrl_reg
);
2213 /* Make sure sequencer is idle before allowing subsequent activity */
2214 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2215 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2217 if ((pp
& PANEL_POWER_ON
) == 0)
2218 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2220 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2223 static void edp_panel_vdd_work(struct work_struct
*__work
)
2225 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2226 struct intel_dp
, panel_vdd_work
);
2229 if (!intel_dp
->want_panel_vdd
)
2230 edp_panel_vdd_off_sync(intel_dp
);
2231 pps_unlock(intel_dp
);
2234 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2236 unsigned long delay
;
2239 * Queue the timer to fire a long time from now (relative to the power
2240 * down delay) to keep the panel power up across a sequence of
2243 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2244 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2248 * Must be paired with edp_panel_vdd_on().
2249 * Must hold pps_mutex around the whole on/off sequence.
2250 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2252 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2254 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2256 lockdep_assert_held(&dev_priv
->pps_mutex
);
2258 if (!intel_dp_is_edp(intel_dp
))
2261 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2262 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2264 intel_dp
->want_panel_vdd
= false;
2267 edp_panel_vdd_off_sync(intel_dp
);
2269 edp_panel_vdd_schedule_off(intel_dp
);
2272 static void edp_panel_on(struct intel_dp
*intel_dp
)
2274 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2276 i915_reg_t pp_ctrl_reg
;
2278 lockdep_assert_held(&dev_priv
->pps_mutex
);
2280 if (!intel_dp_is_edp(intel_dp
))
2283 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2284 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2286 if (WARN(edp_have_panel_power(intel_dp
),
2287 "eDP port %c panel power already on\n",
2288 port_name(dp_to_dig_port(intel_dp
)->base
.port
)))
2291 wait_panel_power_cycle(intel_dp
);
2293 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2294 pp
= ironlake_get_pp_control(intel_dp
);
2295 if (IS_GEN5(dev_priv
)) {
2296 /* ILK workaround: disable reset around power sequence */
2297 pp
&= ~PANEL_POWER_RESET
;
2298 I915_WRITE(pp_ctrl_reg
, pp
);
2299 POSTING_READ(pp_ctrl_reg
);
2302 pp
|= PANEL_POWER_ON
;
2303 if (!IS_GEN5(dev_priv
))
2304 pp
|= PANEL_POWER_RESET
;
2306 I915_WRITE(pp_ctrl_reg
, pp
);
2307 POSTING_READ(pp_ctrl_reg
);
2309 wait_panel_on(intel_dp
);
2310 intel_dp
->last_power_on
= jiffies
;
2312 if (IS_GEN5(dev_priv
)) {
2313 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2314 I915_WRITE(pp_ctrl_reg
, pp
);
2315 POSTING_READ(pp_ctrl_reg
);
2319 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2321 if (!intel_dp_is_edp(intel_dp
))
2325 edp_panel_on(intel_dp
);
2326 pps_unlock(intel_dp
);
2330 static void edp_panel_off(struct intel_dp
*intel_dp
)
2332 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2334 i915_reg_t pp_ctrl_reg
;
2336 lockdep_assert_held(&dev_priv
->pps_mutex
);
2338 if (!intel_dp_is_edp(intel_dp
))
2341 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2342 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2344 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2345 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2347 pp
= ironlake_get_pp_control(intel_dp
);
2348 /* We need to switch off panel power _and_ force vdd, for otherwise some
2349 * panels get very unhappy and cease to work. */
2350 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2353 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2355 intel_dp
->want_panel_vdd
= false;
2357 I915_WRITE(pp_ctrl_reg
, pp
);
2358 POSTING_READ(pp_ctrl_reg
);
2360 wait_panel_off(intel_dp
);
2361 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2363 /* We got a reference when we enabled the VDD. */
2364 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2367 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2369 if (!intel_dp_is_edp(intel_dp
))
2373 edp_panel_off(intel_dp
);
2374 pps_unlock(intel_dp
);
2377 /* Enable backlight in the panel power control. */
2378 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2380 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2382 i915_reg_t pp_ctrl_reg
;
2385 * If we enable the backlight right away following a panel power
2386 * on, we may see slight flicker as the panel syncs with the eDP
2387 * link. So delay a bit to make sure the image is solid before
2388 * allowing it to appear.
2390 wait_backlight_on(intel_dp
);
2394 pp
= ironlake_get_pp_control(intel_dp
);
2395 pp
|= EDP_BLC_ENABLE
;
2397 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2399 I915_WRITE(pp_ctrl_reg
, pp
);
2400 POSTING_READ(pp_ctrl_reg
);
2402 pps_unlock(intel_dp
);
2405 /* Enable backlight PWM and backlight PP control. */
2406 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2407 const struct drm_connector_state
*conn_state
)
2409 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2411 if (!intel_dp_is_edp(intel_dp
))
2414 DRM_DEBUG_KMS("\n");
2416 intel_panel_enable_backlight(crtc_state
, conn_state
);
2417 _intel_edp_backlight_on(intel_dp
);
2420 /* Disable backlight in the panel power control. */
2421 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2423 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2425 i915_reg_t pp_ctrl_reg
;
2427 if (!intel_dp_is_edp(intel_dp
))
2432 pp
= ironlake_get_pp_control(intel_dp
);
2433 pp
&= ~EDP_BLC_ENABLE
;
2435 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2437 I915_WRITE(pp_ctrl_reg
, pp
);
2438 POSTING_READ(pp_ctrl_reg
);
2440 pps_unlock(intel_dp
);
2442 intel_dp
->last_backlight_off
= jiffies
;
2443 edp_wait_backlight_off(intel_dp
);
2446 /* Disable backlight PP control and backlight PWM. */
2447 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2449 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2451 if (!intel_dp_is_edp(intel_dp
))
2454 DRM_DEBUG_KMS("\n");
2456 _intel_edp_backlight_off(intel_dp
);
2457 intel_panel_disable_backlight(old_conn_state
);
2461 * Hook for controlling the panel power control backlight through the bl_power
2462 * sysfs attribute. Take care to handle multiple calls.
2464 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2467 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2471 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2472 pps_unlock(intel_dp
);
2474 if (is_enabled
== enable
)
2477 DRM_DEBUG_KMS("panel power control backlight %s\n",
2478 enable
? "enable" : "disable");
2481 _intel_edp_backlight_on(intel_dp
);
2483 _intel_edp_backlight_off(intel_dp
);
2486 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2488 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2489 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2490 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2492 I915_STATE_WARN(cur_state
!= state
,
2493 "DP port %c state assertion failure (expected %s, current %s)\n",
2494 port_name(dig_port
->base
.port
),
2495 onoff(state
), onoff(cur_state
));
2497 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2499 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2501 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2503 I915_STATE_WARN(cur_state
!= state
,
2504 "eDP PLL state assertion failure (expected %s, current %s)\n",
2505 onoff(state
), onoff(cur_state
));
2507 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2508 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2510 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2511 const struct intel_crtc_state
*pipe_config
)
2513 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2514 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2516 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2517 assert_dp_port_disabled(intel_dp
);
2518 assert_edp_pll_disabled(dev_priv
);
2520 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2521 pipe_config
->port_clock
);
2523 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2525 if (pipe_config
->port_clock
== 162000)
2526 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2528 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2530 I915_WRITE(DP_A
, intel_dp
->DP
);
2535 * [DevILK] Work around required when enabling DP PLL
2536 * while a pipe is enabled going to FDI:
2537 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2538 * 2. Program DP PLL enable
2540 if (IS_GEN5(dev_priv
))
2541 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2543 intel_dp
->DP
|= DP_PLL_ENABLE
;
2545 I915_WRITE(DP_A
, intel_dp
->DP
);
2550 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
,
2551 const struct intel_crtc_state
*old_crtc_state
)
2553 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
2554 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2556 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2557 assert_dp_port_disabled(intel_dp
);
2558 assert_edp_pll_enabled(dev_priv
);
2560 DRM_DEBUG_KMS("disabling eDP PLL\n");
2562 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2564 I915_WRITE(DP_A
, intel_dp
->DP
);
2569 static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp
)
2572 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2573 * be capable of signalling downstream hpd with a long pulse.
2574 * Whether or not that means D3 is safe to use is not clear,
2575 * but let's assume so until proven otherwise.
2577 * FIXME should really check all downstream ports...
2579 return intel_dp
->dpcd
[DP_DPCD_REV
] == 0x11 &&
2580 intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
&&
2581 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
;
2584 /* If the sink supports it, try to set the power state appropriately */
2585 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2589 /* Should have a valid DPCD by this point */
2590 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2593 if (mode
!= DRM_MODE_DPMS_ON
) {
2594 if (downstream_hpd_needs_d0(intel_dp
))
2597 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2600 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2603 * When turning on, we need to retry for 1ms to give the sink
2606 for (i
= 0; i
< 3; i
++) {
2607 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2614 if (ret
== 1 && lspcon
->active
)
2615 lspcon_wait_pcon_mode(lspcon
);
2619 DRM_DEBUG_KMS("failed to %s sink power state\n",
2620 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2623 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2626 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2627 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2628 enum port port
= encoder
->port
;
2632 if (!intel_display_power_get_if_enabled(dev_priv
,
2633 encoder
->power_domain
))
2638 tmp
= I915_READ(intel_dp
->output_reg
);
2640 if (!(tmp
& DP_PORT_EN
))
2643 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2644 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2645 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2648 for_each_pipe(dev_priv
, p
) {
2649 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2650 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2658 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2659 i915_mmio_reg_offset(intel_dp
->output_reg
));
2660 } else if (IS_CHERRYVIEW(dev_priv
)) {
2661 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2663 *pipe
= PORT_TO_PIPE(tmp
);
2669 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2674 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2675 struct intel_crtc_state
*pipe_config
)
2677 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2678 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2680 enum port port
= encoder
->port
;
2681 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2683 if (encoder
->type
== INTEL_OUTPUT_EDP
)
2684 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_EDP
);
2686 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_DP
);
2688 tmp
= I915_READ(intel_dp
->output_reg
);
2690 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2692 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2693 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2695 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2696 flags
|= DRM_MODE_FLAG_PHSYNC
;
2698 flags
|= DRM_MODE_FLAG_NHSYNC
;
2700 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2701 flags
|= DRM_MODE_FLAG_PVSYNC
;
2703 flags
|= DRM_MODE_FLAG_NVSYNC
;
2705 if (tmp
& DP_SYNC_HS_HIGH
)
2706 flags
|= DRM_MODE_FLAG_PHSYNC
;
2708 flags
|= DRM_MODE_FLAG_NHSYNC
;
2710 if (tmp
& DP_SYNC_VS_HIGH
)
2711 flags
|= DRM_MODE_FLAG_PVSYNC
;
2713 flags
|= DRM_MODE_FLAG_NVSYNC
;
2716 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2718 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2719 pipe_config
->limited_color_range
= true;
2721 pipe_config
->lane_count
=
2722 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2724 intel_dp_get_m_n(crtc
, pipe_config
);
2726 if (port
== PORT_A
) {
2727 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2728 pipe_config
->port_clock
= 162000;
2730 pipe_config
->port_clock
= 270000;
2733 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2734 intel_dotclock_calculate(pipe_config
->port_clock
,
2735 &pipe_config
->dp_m_n
);
2737 if (intel_dp_is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2738 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2740 * This is a big fat ugly hack.
2742 * Some machines in UEFI boot mode provide us a VBT that has 18
2743 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2744 * unknown we fail to light up. Yet the same BIOS boots up with
2745 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2746 * max, not what it tells us to use.
2748 * Note: This will still be broken if the eDP panel is not lit
2749 * up by the BIOS, and thus we can't get the mode at module
2752 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2753 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2754 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2758 static void intel_disable_dp(struct intel_encoder
*encoder
,
2759 const struct intel_crtc_state
*old_crtc_state
,
2760 const struct drm_connector_state
*old_conn_state
)
2762 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2764 if (old_crtc_state
->has_audio
)
2765 intel_audio_codec_disable(encoder
,
2766 old_crtc_state
, old_conn_state
);
2768 /* Make sure the panel is off before trying to change the mode. But also
2769 * ensure that we have vdd while we switch off the panel. */
2770 intel_edp_panel_vdd_on(intel_dp
);
2771 intel_edp_backlight_off(old_conn_state
);
2772 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2773 intel_edp_panel_off(intel_dp
);
2776 static void g4x_disable_dp(struct intel_encoder
*encoder
,
2777 const struct intel_crtc_state
*old_crtc_state
,
2778 const struct drm_connector_state
*old_conn_state
)
2780 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2782 /* disable the port before the pipe on g4x */
2783 intel_dp_link_down(encoder
, old_crtc_state
);
2786 static void ilk_disable_dp(struct intel_encoder
*encoder
,
2787 const struct intel_crtc_state
*old_crtc_state
,
2788 const struct drm_connector_state
*old_conn_state
)
2790 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2793 static void vlv_disable_dp(struct intel_encoder
*encoder
,
2794 const struct intel_crtc_state
*old_crtc_state
,
2795 const struct drm_connector_state
*old_conn_state
)
2797 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2799 intel_psr_disable(intel_dp
, old_crtc_state
);
2801 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2804 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2805 const struct intel_crtc_state
*old_crtc_state
,
2806 const struct drm_connector_state
*old_conn_state
)
2808 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2809 enum port port
= encoder
->port
;
2811 intel_dp_link_down(encoder
, old_crtc_state
);
2813 /* Only ilk+ has port A */
2815 ironlake_edp_pll_off(intel_dp
, old_crtc_state
);
2818 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2819 const struct intel_crtc_state
*old_crtc_state
,
2820 const struct drm_connector_state
*old_conn_state
)
2822 intel_dp_link_down(encoder
, old_crtc_state
);
2825 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2826 const struct intel_crtc_state
*old_crtc_state
,
2827 const struct drm_connector_state
*old_conn_state
)
2829 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2831 intel_dp_link_down(encoder
, old_crtc_state
);
2833 mutex_lock(&dev_priv
->sb_lock
);
2835 /* Assert data lane reset */
2836 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
2838 mutex_unlock(&dev_priv
->sb_lock
);
2842 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2844 uint8_t dp_train_pat
)
2846 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2847 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2848 enum port port
= intel_dig_port
->base
.port
;
2850 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2851 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2852 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2854 if (HAS_DDI(dev_priv
)) {
2855 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2857 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2858 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2860 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2862 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2863 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2864 case DP_TRAINING_PATTERN_DISABLE
:
2865 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2868 case DP_TRAINING_PATTERN_1
:
2869 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2871 case DP_TRAINING_PATTERN_2
:
2872 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2874 case DP_TRAINING_PATTERN_3
:
2875 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2878 I915_WRITE(DP_TP_CTL(port
), temp
);
2880 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2881 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2882 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2884 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2885 case DP_TRAINING_PATTERN_DISABLE
:
2886 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2888 case DP_TRAINING_PATTERN_1
:
2889 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2891 case DP_TRAINING_PATTERN_2
:
2892 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2894 case DP_TRAINING_PATTERN_3
:
2895 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2896 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2901 if (IS_CHERRYVIEW(dev_priv
))
2902 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2904 *DP
&= ~DP_LINK_TRAIN_MASK
;
2906 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2907 case DP_TRAINING_PATTERN_DISABLE
:
2908 *DP
|= DP_LINK_TRAIN_OFF
;
2910 case DP_TRAINING_PATTERN_1
:
2911 *DP
|= DP_LINK_TRAIN_PAT_1
;
2913 case DP_TRAINING_PATTERN_2
:
2914 *DP
|= DP_LINK_TRAIN_PAT_2
;
2916 case DP_TRAINING_PATTERN_3
:
2917 if (IS_CHERRYVIEW(dev_priv
)) {
2918 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2920 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2921 *DP
|= DP_LINK_TRAIN_PAT_2
;
2928 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2929 const struct intel_crtc_state
*old_crtc_state
)
2931 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2933 /* enable with pattern 1 (as per spec) */
2935 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2938 * Magic for VLV/CHV. We _must_ first set up the register
2939 * without actually enabling the port, and then do another
2940 * write to enable the port. Otherwise link training will
2941 * fail when the power sequencer is freshly used for this port.
2943 intel_dp
->DP
|= DP_PORT_EN
;
2944 if (old_crtc_state
->has_audio
)
2945 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2947 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2948 POSTING_READ(intel_dp
->output_reg
);
2951 static void intel_enable_dp(struct intel_encoder
*encoder
,
2952 const struct intel_crtc_state
*pipe_config
,
2953 const struct drm_connector_state
*conn_state
)
2955 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2956 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2957 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2958 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2959 enum pipe pipe
= crtc
->pipe
;
2961 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2966 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2967 vlv_init_panel_power_sequencer(encoder
, pipe_config
);
2969 intel_dp_enable_port(intel_dp
, pipe_config
);
2971 edp_panel_vdd_on(intel_dp
);
2972 edp_panel_on(intel_dp
);
2973 edp_panel_vdd_off(intel_dp
, true);
2975 pps_unlock(intel_dp
);
2977 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2978 unsigned int lane_mask
= 0x0;
2980 if (IS_CHERRYVIEW(dev_priv
))
2981 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2983 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2987 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2988 intel_dp_start_link_train(intel_dp
);
2989 intel_dp_stop_link_train(intel_dp
);
2991 if (pipe_config
->has_audio
) {
2992 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2994 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
2998 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2999 const struct intel_crtc_state
*pipe_config
,
3000 const struct drm_connector_state
*conn_state
)
3002 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3003 intel_edp_backlight_on(pipe_config
, conn_state
);
3006 static void vlv_enable_dp(struct intel_encoder
*encoder
,
3007 const struct intel_crtc_state
*pipe_config
,
3008 const struct drm_connector_state
*conn_state
)
3010 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3012 intel_edp_backlight_on(pipe_config
, conn_state
);
3013 intel_psr_enable(intel_dp
, pipe_config
);
3016 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
3017 const struct intel_crtc_state
*pipe_config
,
3018 const struct drm_connector_state
*conn_state
)
3020 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3021 enum port port
= encoder
->port
;
3023 intel_dp_prepare(encoder
, pipe_config
);
3025 /* Only ilk+ has port A */
3027 ironlake_edp_pll_on(intel_dp
, pipe_config
);
3030 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
3032 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3033 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
3034 enum pipe pipe
= intel_dp
->pps_pipe
;
3035 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
3037 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3039 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
3042 edp_panel_vdd_off_sync(intel_dp
);
3045 * VLV seems to get confused when multiple power seqeuencers
3046 * have the same port selected (even if only one has power/vdd
3047 * enabled). The failure manifests as vlv_wait_port_ready() failing
3048 * CHV on the other hand doesn't seem to mind having the same port
3049 * selected in multiple power seqeuencers, but let's clear the
3050 * port select always when logically disconnecting a power sequencer
3053 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3054 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
3055 I915_WRITE(pp_on_reg
, 0);
3056 POSTING_READ(pp_on_reg
);
3058 intel_dp
->pps_pipe
= INVALID_PIPE
;
3061 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
3064 struct intel_encoder
*encoder
;
3066 lockdep_assert_held(&dev_priv
->pps_mutex
);
3068 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
3069 struct intel_dp
*intel_dp
;
3072 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
3073 encoder
->type
!= INTEL_OUTPUT_EDP
)
3076 intel_dp
= enc_to_intel_dp(&encoder
->base
);
3077 port
= dp_to_dig_port(intel_dp
)->base
.port
;
3079 WARN(intel_dp
->active_pipe
== pipe
,
3080 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3081 pipe_name(pipe
), port_name(port
));
3083 if (intel_dp
->pps_pipe
!= pipe
)
3086 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3087 pipe_name(pipe
), port_name(port
));
3089 /* make sure vdd is off before we steal it */
3090 vlv_detach_power_sequencer(intel_dp
);
3094 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
3095 const struct intel_crtc_state
*crtc_state
)
3097 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3098 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3099 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3101 lockdep_assert_held(&dev_priv
->pps_mutex
);
3103 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3105 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3106 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3108 * If another power sequencer was being used on this
3109 * port previously make sure to turn off vdd there while
3110 * we still have control of it.
3112 vlv_detach_power_sequencer(intel_dp
);
3116 * We may be stealing the power
3117 * sequencer from another port.
3119 vlv_steal_power_sequencer(dev_priv
, crtc
->pipe
);
3121 intel_dp
->active_pipe
= crtc
->pipe
;
3123 if (!intel_dp_is_edp(intel_dp
))
3126 /* now it's all ours */
3127 intel_dp
->pps_pipe
= crtc
->pipe
;
3129 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3130 pipe_name(intel_dp
->pps_pipe
), port_name(encoder
->port
));
3132 /* init power sequencer on this pipe and port */
3133 intel_dp_init_panel_power_sequencer(intel_dp
);
3134 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
3137 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3138 const struct intel_crtc_state
*pipe_config
,
3139 const struct drm_connector_state
*conn_state
)
3141 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
3143 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3146 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3147 const struct intel_crtc_state
*pipe_config
,
3148 const struct drm_connector_state
*conn_state
)
3150 intel_dp_prepare(encoder
, pipe_config
);
3152 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
3155 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3156 const struct intel_crtc_state
*pipe_config
,
3157 const struct drm_connector_state
*conn_state
)
3159 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
3161 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3163 /* Second common lane will stay alive on its own now */
3164 chv_phy_release_cl2_override(encoder
);
3167 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3168 const struct intel_crtc_state
*pipe_config
,
3169 const struct drm_connector_state
*conn_state
)
3171 intel_dp_prepare(encoder
, pipe_config
);
3173 chv_phy_pre_pll_enable(encoder
, pipe_config
);
3176 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3177 const struct intel_crtc_state
*old_crtc_state
,
3178 const struct drm_connector_state
*old_conn_state
)
3180 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
3184 * Fetch AUX CH registers 0x202 - 0x207 which contain
3185 * link status information
3188 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3190 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3191 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3194 /* These are source-specific values. */
3196 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3198 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3199 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
3201 if (INTEL_GEN(dev_priv
) >= 9) {
3202 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3203 return intel_ddi_dp_voltage_max(encoder
);
3204 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3205 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3206 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3207 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3208 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3209 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3211 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3215 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3217 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3218 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
3220 if (INTEL_GEN(dev_priv
) >= 9) {
3221 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3223 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3225 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3227 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3229 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3231 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3233 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3234 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3236 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3238 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3240 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3243 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3245 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3246 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3248 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3250 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3252 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3255 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3257 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3258 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3260 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3263 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3265 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3268 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3270 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3272 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3274 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3277 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3282 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3284 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3285 unsigned long demph_reg_value
, preemph_reg_value
,
3286 uniqtranscale_reg_value
;
3287 uint8_t train_set
= intel_dp
->train_set
[0];
3289 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3290 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3291 preemph_reg_value
= 0x0004000;
3292 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3294 demph_reg_value
= 0x2B405555;
3295 uniqtranscale_reg_value
= 0x552AB83A;
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3298 demph_reg_value
= 0x2B404040;
3299 uniqtranscale_reg_value
= 0x5548B83A;
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3302 demph_reg_value
= 0x2B245555;
3303 uniqtranscale_reg_value
= 0x5560B83A;
3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3306 demph_reg_value
= 0x2B405555;
3307 uniqtranscale_reg_value
= 0x5598DA3A;
3313 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3314 preemph_reg_value
= 0x0002000;
3315 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3317 demph_reg_value
= 0x2B404040;
3318 uniqtranscale_reg_value
= 0x5552B83A;
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3321 demph_reg_value
= 0x2B404848;
3322 uniqtranscale_reg_value
= 0x5580B83A;
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3325 demph_reg_value
= 0x2B404040;
3326 uniqtranscale_reg_value
= 0x55ADDA3A;
3332 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3333 preemph_reg_value
= 0x0000000;
3334 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3336 demph_reg_value
= 0x2B305555;
3337 uniqtranscale_reg_value
= 0x5570B83A;
3339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3340 demph_reg_value
= 0x2B2B4040;
3341 uniqtranscale_reg_value
= 0x55ADDA3A;
3347 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3348 preemph_reg_value
= 0x0006000;
3349 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3350 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3351 demph_reg_value
= 0x1B405555;
3352 uniqtranscale_reg_value
= 0x55ADDA3A;
3362 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3363 uniqtranscale_reg_value
, 0);
3368 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3370 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3371 u32 deemph_reg_value
, margin_reg_value
;
3372 bool uniq_trans_scale
= false;
3373 uint8_t train_set
= intel_dp
->train_set
[0];
3375 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3376 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3377 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3378 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3379 deemph_reg_value
= 128;
3380 margin_reg_value
= 52;
3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3383 deemph_reg_value
= 128;
3384 margin_reg_value
= 77;
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3387 deemph_reg_value
= 128;
3388 margin_reg_value
= 102;
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3391 deemph_reg_value
= 128;
3392 margin_reg_value
= 154;
3393 uniq_trans_scale
= true;
3399 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3400 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3402 deemph_reg_value
= 85;
3403 margin_reg_value
= 78;
3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3406 deemph_reg_value
= 85;
3407 margin_reg_value
= 116;
3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3410 deemph_reg_value
= 85;
3411 margin_reg_value
= 154;
3417 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3418 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3420 deemph_reg_value
= 64;
3421 margin_reg_value
= 104;
3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3424 deemph_reg_value
= 64;
3425 margin_reg_value
= 154;
3431 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3432 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3434 deemph_reg_value
= 43;
3435 margin_reg_value
= 154;
3445 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3446 margin_reg_value
, uniq_trans_scale
);
3452 gen4_signal_levels(uint8_t train_set
)
3454 uint32_t signal_levels
= 0;
3456 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3459 signal_levels
|= DP_VOLTAGE_0_4
;
3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3462 signal_levels
|= DP_VOLTAGE_0_6
;
3464 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3465 signal_levels
|= DP_VOLTAGE_0_8
;
3467 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3468 signal_levels
|= DP_VOLTAGE_1_2
;
3471 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3472 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3474 signal_levels
|= DP_PRE_EMPHASIS_0
;
3476 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3477 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3479 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3480 signal_levels
|= DP_PRE_EMPHASIS_6
;
3482 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3483 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3486 return signal_levels
;
3489 /* Gen6's DP voltage swing and pre-emphasis control */
3491 gen6_edp_signal_levels(uint8_t train_set
)
3493 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3494 DP_TRAIN_PRE_EMPHASIS_MASK
);
3495 switch (signal_levels
) {
3496 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3497 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3498 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3500 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3502 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3503 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3504 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3505 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3506 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3507 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3508 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3509 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3511 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3512 "0x%x\n", signal_levels
);
3513 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3517 /* Gen7's DP voltage swing and pre-emphasis control */
3519 gen7_edp_signal_levels(uint8_t train_set
)
3521 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3522 DP_TRAIN_PRE_EMPHASIS_MASK
);
3523 switch (signal_levels
) {
3524 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3525 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3527 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3529 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3531 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3532 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3533 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3534 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3536 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3537 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3538 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3539 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3542 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3543 "0x%x\n", signal_levels
);
3544 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3549 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3551 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3552 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3553 enum port port
= intel_dig_port
->base
.port
;
3554 uint32_t signal_levels
, mask
= 0;
3555 uint8_t train_set
= intel_dp
->train_set
[0];
3557 if (IS_GEN9_LP(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
3558 signal_levels
= bxt_signal_levels(intel_dp
);
3559 } else if (HAS_DDI(dev_priv
)) {
3560 signal_levels
= ddi_signal_levels(intel_dp
);
3561 mask
= DDI_BUF_EMP_MASK
;
3562 } else if (IS_CHERRYVIEW(dev_priv
)) {
3563 signal_levels
= chv_signal_levels(intel_dp
);
3564 } else if (IS_VALLEYVIEW(dev_priv
)) {
3565 signal_levels
= vlv_signal_levels(intel_dp
);
3566 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3567 signal_levels
= gen7_edp_signal_levels(train_set
);
3568 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3569 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3570 signal_levels
= gen6_edp_signal_levels(train_set
);
3571 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3573 signal_levels
= gen4_signal_levels(train_set
);
3574 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3578 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3580 DRM_DEBUG_KMS("Using vswing level %d\n",
3581 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3582 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3583 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3584 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3586 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3588 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3589 POSTING_READ(intel_dp
->output_reg
);
3593 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3594 uint8_t dp_train_pat
)
3596 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3597 struct drm_i915_private
*dev_priv
=
3598 to_i915(intel_dig_port
->base
.base
.dev
);
3600 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3602 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3603 POSTING_READ(intel_dp
->output_reg
);
3606 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3608 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3609 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3610 enum port port
= intel_dig_port
->base
.port
;
3613 if (!HAS_DDI(dev_priv
))
3616 val
= I915_READ(DP_TP_CTL(port
));
3617 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3618 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3619 I915_WRITE(DP_TP_CTL(port
), val
);
3622 * On PORT_A we can have only eDP in SST mode. There the only reason
3623 * we need to set idle transmission mode is to work around a HW issue
3624 * where we enable the pipe while not in idle link-training mode.
3625 * In this case there is requirement to wait for a minimum number of
3626 * idle patterns to be sent.
3631 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3632 DP_TP_STATUS_IDLE_DONE
,
3633 DP_TP_STATUS_IDLE_DONE
,
3635 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3639 intel_dp_link_down(struct intel_encoder
*encoder
,
3640 const struct intel_crtc_state
*old_crtc_state
)
3642 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3643 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3644 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
3645 enum port port
= encoder
->port
;
3646 uint32_t DP
= intel_dp
->DP
;
3648 if (WARN_ON(HAS_DDI(dev_priv
)))
3651 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3654 DRM_DEBUG_KMS("\n");
3656 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3657 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3658 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3659 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3661 if (IS_CHERRYVIEW(dev_priv
))
3662 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3664 DP
&= ~DP_LINK_TRAIN_MASK
;
3665 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3667 I915_WRITE(intel_dp
->output_reg
, DP
);
3668 POSTING_READ(intel_dp
->output_reg
);
3670 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3671 I915_WRITE(intel_dp
->output_reg
, DP
);
3672 POSTING_READ(intel_dp
->output_reg
);
3675 * HW workaround for IBX, we need to move the port
3676 * to transcoder A after disabling it to allow the
3677 * matching HDMI port to be enabled on transcoder A.
3679 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3681 * We get CPU/PCH FIFO underruns on the other pipe when
3682 * doing the workaround. Sweep them under the rug.
3684 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3685 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3687 /* always enable with pattern 1 (as per spec) */
3688 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3689 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3690 I915_WRITE(intel_dp
->output_reg
, DP
);
3691 POSTING_READ(intel_dp
->output_reg
);
3694 I915_WRITE(intel_dp
->output_reg
, DP
);
3695 POSTING_READ(intel_dp
->output_reg
);
3697 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3698 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3699 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3702 msleep(intel_dp
->panel_power_down_delay
);
3706 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3708 intel_dp
->active_pipe
= INVALID_PIPE
;
3709 pps_unlock(intel_dp
);
3714 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3716 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3717 sizeof(intel_dp
->dpcd
)) < 0)
3718 return false; /* aux transfer failed */
3720 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3722 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3726 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3728 struct drm_i915_private
*dev_priv
=
3729 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3731 /* this function is meant to be called only once */
3732 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3734 if (!intel_dp_read_dpcd(intel_dp
))
3737 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
3738 drm_dp_is_branch(intel_dp
->dpcd
));
3740 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3741 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3742 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3744 intel_psr_init_dpcd(intel_dp
);
3747 * Read the eDP display control registers.
3749 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3750 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3751 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3752 * method). The display control registers should read zero if they're
3753 * not supported anyway.
3755 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3756 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3757 sizeof(intel_dp
->edp_dpcd
))
3758 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3759 intel_dp
->edp_dpcd
);
3761 /* Read the eDP 1.4+ supported link rates. */
3762 if (intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
3763 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3766 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3767 sink_rates
, sizeof(sink_rates
));
3769 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3770 int val
= le16_to_cpu(sink_rates
[i
]);
3775 /* Value read multiplied by 200kHz gives the per-lane
3776 * link rate in kHz. The source rates are, however,
3777 * stored in terms of LS_Clk kHz. The full conversion
3778 * back to symbols is
3779 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3781 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3783 intel_dp
->num_sink_rates
= i
;
3787 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3788 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3790 if (intel_dp
->num_sink_rates
)
3791 intel_dp
->use_rate_select
= true;
3793 intel_dp_set_sink_rates(intel_dp
);
3795 intel_dp_set_common_rates(intel_dp
);
3802 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3806 if (!intel_dp_read_dpcd(intel_dp
))
3809 /* Don't clobber cached eDP rates. */
3810 if (!intel_dp_is_edp(intel_dp
)) {
3811 intel_dp_set_sink_rates(intel_dp
);
3812 intel_dp_set_common_rates(intel_dp
);
3815 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &sink_count
) <= 0)
3819 * Sink count can change between short pulse hpd hence
3820 * a member variable in intel_dp will track any changes
3821 * between short pulse interrupts.
3823 intel_dp
->sink_count
= DP_GET_SINK_COUNT(sink_count
);
3826 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3827 * a dongle is present but no display. Unless we require to know
3828 * if a dongle is present or not, we don't need to update
3829 * downstream port information. So, an early return here saves
3830 * time from performing other operations which are not required.
3832 if (!intel_dp_is_edp(intel_dp
) && !intel_dp
->sink_count
)
3835 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3836 return true; /* native DP sink */
3838 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3839 return true; /* no per-port downstream info */
3841 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3842 intel_dp
->downstream_ports
,
3843 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3844 return false; /* downstream port status fetch failed */
3850 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3854 if (!i915_modparams
.enable_dp_mst
)
3857 if (!intel_dp
->can_mst
)
3860 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3863 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
3866 return mstm_cap
& DP_MST_CAP
;
3870 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3872 if (!i915_modparams
.enable_dp_mst
)
3875 if (!intel_dp
->can_mst
)
3878 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3880 if (intel_dp
->is_mst
)
3881 DRM_DEBUG_KMS("Sink is MST capable\n");
3883 DRM_DEBUG_KMS("Sink is not MST capable\n");
3885 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3889 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
,
3890 struct intel_crtc_state
*crtc_state
, bool disable_wa
)
3892 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3893 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3894 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3900 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3901 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3906 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3907 buf
& ~DP_TEST_SINK_START
) < 0) {
3908 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3914 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3916 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3917 DP_TEST_SINK_MISC
, &buf
) < 0) {
3921 count
= buf
& DP_TEST_COUNT_MASK
;
3922 } while (--attempts
&& count
);
3924 if (attempts
== 0) {
3925 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3931 hsw_enable_ips(crtc_state
);
3935 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
,
3936 struct intel_crtc_state
*crtc_state
)
3938 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3939 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3944 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3947 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3950 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3953 if (buf
& DP_TEST_SINK_START
) {
3954 ret
= intel_dp_sink_crc_stop(intel_dp
, crtc_state
, false);
3959 hsw_disable_ips(crtc_state
);
3961 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3962 buf
| DP_TEST_SINK_START
) < 0) {
3963 hsw_enable_ips(crtc_state
);
3967 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3971 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, struct intel_crtc_state
*crtc_state
, u8
*crc
)
3973 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3974 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3975 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3980 ret
= intel_dp_sink_crc_start(intel_dp
, crtc_state
);
3985 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3987 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3988 DP_TEST_SINK_MISC
, &buf
) < 0) {
3992 count
= buf
& DP_TEST_COUNT_MASK
;
3994 } while (--attempts
&& count
== 0);
3996 if (attempts
== 0) {
3997 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4002 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4008 intel_dp_sink_crc_stop(intel_dp
, crtc_state
, true);
4013 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4015 return drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
4016 sink_irq_vector
) == 1;
4020 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4022 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT_ESI
,
4023 sink_irq_vector
, DP_DPRX_ESI_LEN
) ==
4027 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4031 uint8_t test_lane_count
, test_link_bw
;
4035 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4036 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4040 DRM_DEBUG_KMS("Lane count read failed\n");
4043 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4045 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4048 DRM_DEBUG_KMS("Link Rate read failed\n");
4051 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4053 /* Validate the requested link rate and lane count */
4054 if (!intel_dp_link_params_valid(intel_dp
, test_link_rate
,
4058 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4059 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4064 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4066 uint8_t test_pattern
;
4068 __be16 h_width
, v_height
;
4071 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4072 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4075 DRM_DEBUG_KMS("Test pattern read failed\n");
4078 if (test_pattern
!= DP_COLOR_RAMP
)
4081 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4084 DRM_DEBUG_KMS("H Width read failed\n");
4088 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4091 DRM_DEBUG_KMS("V Height read failed\n");
4095 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4098 DRM_DEBUG_KMS("TEST MISC read failed\n");
4101 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4103 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4105 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4106 case DP_TEST_BIT_DEPTH_6
:
4107 intel_dp
->compliance
.test_data
.bpc
= 6;
4109 case DP_TEST_BIT_DEPTH_8
:
4110 intel_dp
->compliance
.test_data
.bpc
= 8;
4116 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4117 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4118 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4119 /* Set test active flag here so userspace doesn't interrupt things */
4120 intel_dp
->compliance
.test_active
= 1;
4125 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4127 uint8_t test_result
= DP_TEST_ACK
;
4128 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4129 struct drm_connector
*connector
= &intel_connector
->base
;
4131 if (intel_connector
->detect_edid
== NULL
||
4132 connector
->edid_corrupt
||
4133 intel_dp
->aux
.i2c_defer_count
> 6) {
4134 /* Check EDID read for NACKs, DEFERs and corruption
4135 * (DP CTS 1.2 Core r1.1)
4136 * 4.2.2.4 : Failed EDID read, I2C_NAK
4137 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4138 * 4.2.2.6 : EDID corruption detected
4139 * Use failsafe mode for all cases
4141 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4142 intel_dp
->aux
.i2c_defer_count
> 0)
4143 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4144 intel_dp
->aux
.i2c_nack_count
,
4145 intel_dp
->aux
.i2c_defer_count
);
4146 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4148 struct edid
*block
= intel_connector
->detect_edid
;
4150 /* We have to write the checksum
4151 * of the last block read
4153 block
+= intel_connector
->detect_edid
->extensions
;
4155 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4156 block
->checksum
) <= 0)
4157 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4159 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4160 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4163 /* Set test active flag here so userspace doesn't interrupt things */
4164 intel_dp
->compliance
.test_active
= 1;
4169 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4171 uint8_t test_result
= DP_TEST_NAK
;
4175 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4177 uint8_t response
= DP_TEST_NAK
;
4178 uint8_t request
= 0;
4181 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4183 DRM_DEBUG_KMS("Could not read test request from sink\n");
4188 case DP_TEST_LINK_TRAINING
:
4189 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4190 response
= intel_dp_autotest_link_training(intel_dp
);
4192 case DP_TEST_LINK_VIDEO_PATTERN
:
4193 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4194 response
= intel_dp_autotest_video_pattern(intel_dp
);
4196 case DP_TEST_LINK_EDID_READ
:
4197 DRM_DEBUG_KMS("EDID test requested\n");
4198 response
= intel_dp_autotest_edid(intel_dp
);
4200 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4201 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4202 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4205 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4209 if (response
& DP_TEST_ACK
)
4210 intel_dp
->compliance
.test_type
= request
;
4213 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4215 DRM_DEBUG_KMS("Could not write test response to sink\n");
4219 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4223 if (intel_dp
->is_mst
) {
4224 u8 esi
[DP_DPRX_ESI_LEN
] = { 0 };
4228 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4232 /* check link status - esi[10] = 0x200c */
4233 if (intel_dp
->active_mst_links
&&
4234 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4235 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4236 intel_dp_start_link_train(intel_dp
);
4237 intel_dp_stop_link_train(intel_dp
);
4240 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4241 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4244 for (retry
= 0; retry
< 3; retry
++) {
4246 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4247 DP_SINK_COUNT_ESI
+1,
4254 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4256 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4264 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4265 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4266 intel_dp
->is_mst
= false;
4267 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4268 /* send a hotplug event */
4269 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4276 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
4278 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4279 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4280 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4282 /* Suppress underruns caused by re-training */
4283 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4284 if (crtc
->config
->has_pch_encoder
)
4285 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4286 intel_crtc_pch_transcoder(crtc
), false);
4288 intel_dp_start_link_train(intel_dp
);
4289 intel_dp_stop_link_train(intel_dp
);
4291 /* Keep underrun reporting disabled until things are stable */
4292 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4294 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4295 if (crtc
->config
->has_pch_encoder
)
4296 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4297 intel_crtc_pch_transcoder(crtc
), true);
4301 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4303 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4304 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4305 struct drm_connector_state
*conn_state
=
4306 intel_dp
->attached_connector
->base
.state
;
4307 u8 link_status
[DP_LINK_STATUS_SIZE
];
4309 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
4311 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4312 DRM_ERROR("Failed to get link status\n");
4316 if (!conn_state
->crtc
)
4319 WARN_ON(!drm_modeset_is_locked(&conn_state
->crtc
->mutex
));
4321 if (!conn_state
->crtc
->state
->active
)
4324 if (conn_state
->commit
&&
4325 !try_wait_for_completion(&conn_state
->commit
->hw_done
))
4329 * Validate the cached values of intel_dp->link_rate and
4330 * intel_dp->lane_count before attempting to retrain.
4332 if (!intel_dp_link_params_valid(intel_dp
, intel_dp
->link_rate
,
4333 intel_dp
->lane_count
))
4336 /* Retrain if Channel EQ or CR not ok */
4337 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4338 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4339 intel_encoder
->base
.name
);
4341 intel_dp_retrain_link(intel_dp
);
4346 * According to DP spec
4349 * 2. Configure link according to Receiver Capabilities
4350 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4351 * 4. Check link status on receipt of hot-plug interrupt
4353 * intel_dp_short_pulse - handles short pulse interrupts
4354 * when full detection is not required.
4355 * Returns %true if short pulse is handled and full detection
4356 * is NOT required and %false otherwise.
4359 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4361 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4362 u8 sink_irq_vector
= 0;
4363 u8 old_sink_count
= intel_dp
->sink_count
;
4367 * Clearing compliance test variables to allow capturing
4368 * of values for next automated test request.
4370 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4373 * Now read the DPCD to see if it's actually running
4374 * If the current value of sink count doesn't match with
4375 * the value that was stored earlier or dpcd read failed
4376 * we need to do full detection
4378 ret
= intel_dp_get_dpcd(intel_dp
);
4380 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4381 /* No need to proceed if we are going to do full detect */
4385 /* Try to read the source of the interrupt */
4386 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4387 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4388 sink_irq_vector
!= 0) {
4389 /* Clear interrupt source */
4390 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4391 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4394 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4395 intel_dp_handle_test_request(intel_dp
);
4396 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4397 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4400 intel_dp_check_link_status(intel_dp
);
4402 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4403 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4404 /* Send a Hotplug Uevent to userspace to start modeset */
4405 drm_kms_helper_hotplug_event(&dev_priv
->drm
);
4411 /* XXX this is probably wrong for multiple downstream ports */
4412 static enum drm_connector_status
4413 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4415 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4416 uint8_t *dpcd
= intel_dp
->dpcd
;
4420 lspcon_resume(lspcon
);
4422 if (!intel_dp_get_dpcd(intel_dp
))
4423 return connector_status_disconnected
;
4425 if (intel_dp_is_edp(intel_dp
))
4426 return connector_status_connected
;
4428 /* if there's no downstream port, we're done */
4429 if (!drm_dp_is_branch(dpcd
))
4430 return connector_status_connected
;
4432 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4433 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4434 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4436 return intel_dp
->sink_count
?
4437 connector_status_connected
: connector_status_disconnected
;
4440 if (intel_dp_can_mst(intel_dp
))
4441 return connector_status_connected
;
4443 /* If no HPD, poke DDC gently */
4444 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4445 return connector_status_connected
;
4447 /* Well we tried, say unknown for unreliable port types */
4448 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4449 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4450 if (type
== DP_DS_PORT_TYPE_VGA
||
4451 type
== DP_DS_PORT_TYPE_NON_EDID
)
4452 return connector_status_unknown
;
4454 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4455 DP_DWN_STRM_PORT_TYPE_MASK
;
4456 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4457 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4458 return connector_status_unknown
;
4461 /* Anything else is out of spec, warn and ignore */
4462 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4463 return connector_status_disconnected
;
4466 static enum drm_connector_status
4467 edp_detect(struct intel_dp
*intel_dp
)
4469 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4470 enum drm_connector_status status
;
4472 status
= intel_panel_detect(dev_priv
);
4473 if (status
== connector_status_unknown
)
4474 status
= connector_status_connected
;
4479 static bool ibx_digital_port_connected(struct intel_encoder
*encoder
)
4481 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4484 switch (encoder
->hpd_pin
) {
4486 bit
= SDE_PORTB_HOTPLUG
;
4489 bit
= SDE_PORTC_HOTPLUG
;
4492 bit
= SDE_PORTD_HOTPLUG
;
4495 MISSING_CASE(encoder
->hpd_pin
);
4499 return I915_READ(SDEISR
) & bit
;
4502 static bool cpt_digital_port_connected(struct intel_encoder
*encoder
)
4504 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4507 switch (encoder
->hpd_pin
) {
4509 bit
= SDE_PORTB_HOTPLUG_CPT
;
4512 bit
= SDE_PORTC_HOTPLUG_CPT
;
4515 bit
= SDE_PORTD_HOTPLUG_CPT
;
4518 MISSING_CASE(encoder
->hpd_pin
);
4522 return I915_READ(SDEISR
) & bit
;
4525 static bool spt_digital_port_connected(struct intel_encoder
*encoder
)
4527 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4530 switch (encoder
->hpd_pin
) {
4532 bit
= SDE_PORTA_HOTPLUG_SPT
;
4535 bit
= SDE_PORTE_HOTPLUG_SPT
;
4538 return cpt_digital_port_connected(encoder
);
4541 return I915_READ(SDEISR
) & bit
;
4544 static bool g4x_digital_port_connected(struct intel_encoder
*encoder
)
4546 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4549 switch (encoder
->hpd_pin
) {
4551 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4554 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4557 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4560 MISSING_CASE(encoder
->hpd_pin
);
4564 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4567 static bool gm45_digital_port_connected(struct intel_encoder
*encoder
)
4569 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4572 switch (encoder
->hpd_pin
) {
4574 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4577 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4580 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4583 MISSING_CASE(encoder
->hpd_pin
);
4587 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4590 static bool ilk_digital_port_connected(struct intel_encoder
*encoder
)
4592 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4594 if (encoder
->hpd_pin
== HPD_PORT_A
)
4595 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4597 return ibx_digital_port_connected(encoder
);
4600 static bool snb_digital_port_connected(struct intel_encoder
*encoder
)
4602 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4604 if (encoder
->hpd_pin
== HPD_PORT_A
)
4605 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4607 return cpt_digital_port_connected(encoder
);
4610 static bool ivb_digital_port_connected(struct intel_encoder
*encoder
)
4612 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4614 if (encoder
->hpd_pin
== HPD_PORT_A
)
4615 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
4617 return cpt_digital_port_connected(encoder
);
4620 static bool bdw_digital_port_connected(struct intel_encoder
*encoder
)
4622 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4624 if (encoder
->hpd_pin
== HPD_PORT_A
)
4625 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
4627 return cpt_digital_port_connected(encoder
);
4630 static bool bxt_digital_port_connected(struct intel_encoder
*encoder
)
4632 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4635 switch (encoder
->hpd_pin
) {
4637 bit
= BXT_DE_PORT_HP_DDIA
;
4640 bit
= BXT_DE_PORT_HP_DDIB
;
4643 bit
= BXT_DE_PORT_HP_DDIC
;
4646 MISSING_CASE(encoder
->hpd_pin
);
4650 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4654 * intel_digital_port_connected - is the specified port connected?
4655 * @encoder: intel_encoder
4657 * Return %true if port is connected, %false otherwise.
4659 bool intel_digital_port_connected(struct intel_encoder
*encoder
)
4661 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4663 if (HAS_GMCH_DISPLAY(dev_priv
)) {
4664 if (IS_GM45(dev_priv
))
4665 return gm45_digital_port_connected(encoder
);
4667 return g4x_digital_port_connected(encoder
);
4670 if (IS_GEN5(dev_priv
))
4671 return ilk_digital_port_connected(encoder
);
4672 else if (IS_GEN6(dev_priv
))
4673 return snb_digital_port_connected(encoder
);
4674 else if (IS_GEN7(dev_priv
))
4675 return ivb_digital_port_connected(encoder
);
4676 else if (IS_GEN8(dev_priv
))
4677 return bdw_digital_port_connected(encoder
);
4678 else if (IS_GEN9_LP(dev_priv
))
4679 return bxt_digital_port_connected(encoder
);
4681 return spt_digital_port_connected(encoder
);
4684 static struct edid
*
4685 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4687 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4689 /* use cached edid if we have one */
4690 if (intel_connector
->edid
) {
4692 if (IS_ERR(intel_connector
->edid
))
4695 return drm_edid_duplicate(intel_connector
->edid
);
4697 return drm_get_edid(&intel_connector
->base
,
4698 &intel_dp
->aux
.ddc
);
4702 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4704 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4707 intel_dp_unset_edid(intel_dp
);
4708 edid
= intel_dp_get_edid(intel_dp
);
4709 intel_connector
->detect_edid
= edid
;
4711 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4715 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4717 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4719 kfree(intel_connector
->detect_edid
);
4720 intel_connector
->detect_edid
= NULL
;
4722 intel_dp
->has_audio
= false;
4726 intel_dp_long_pulse(struct intel_connector
*connector
)
4728 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
4729 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
4730 enum drm_connector_status status
;
4731 u8 sink_irq_vector
= 0;
4733 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
4735 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4737 /* Can't disconnect eDP, but you can close the lid... */
4738 if (intel_dp_is_edp(intel_dp
))
4739 status
= edp_detect(intel_dp
);
4740 else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp
)->base
))
4741 status
= intel_dp_detect_dpcd(intel_dp
);
4743 status
= connector_status_disconnected
;
4745 if (status
== connector_status_disconnected
) {
4746 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4748 if (intel_dp
->is_mst
) {
4749 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4751 intel_dp
->mst_mgr
.mst_state
);
4752 intel_dp
->is_mst
= false;
4753 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4760 if (intel_dp
->reset_link_params
) {
4761 /* Initial max link lane count */
4762 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
4764 /* Initial max link rate */
4765 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
4767 intel_dp
->reset_link_params
= false;
4770 intel_dp_print_rates(intel_dp
);
4772 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4773 drm_dp_is_branch(intel_dp
->dpcd
));
4775 intel_dp_configure_mst(intel_dp
);
4777 if (intel_dp
->is_mst
) {
4779 * If we are in MST mode then this connector
4780 * won't appear connected or have anything
4783 status
= connector_status_disconnected
;
4787 * If display is now connected check links status,
4788 * there has been known issues of link loss triggerring
4791 * Some sinks (eg. ASUS PB287Q) seem to perform some
4792 * weird HPD ping pong during modesets. So we can apparently
4793 * end up with HPD going low during a modeset, and then
4794 * going back up soon after. And once that happens we must
4795 * retrain the link to get a picture. That's in case no
4796 * userspace component reacted to intermittent HPD dip.
4798 intel_dp_check_link_status(intel_dp
);
4802 * Clearing NACK and defer counts to get their exact values
4803 * while reading EDID which are required by Compliance tests
4804 * 4.2.2.4 and 4.2.2.5
4806 intel_dp
->aux
.i2c_nack_count
= 0;
4807 intel_dp
->aux
.i2c_defer_count
= 0;
4809 intel_dp_set_edid(intel_dp
);
4810 if (intel_dp_is_edp(intel_dp
) || connector
->detect_edid
)
4811 status
= connector_status_connected
;
4812 intel_dp
->detect_done
= true;
4814 /* Try to read the source of the interrupt */
4815 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4816 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4817 sink_irq_vector
!= 0) {
4818 /* Clear interrupt source */
4819 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4820 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4823 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4824 intel_dp_handle_test_request(intel_dp
);
4825 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4826 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4830 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4831 intel_dp_unset_edid(intel_dp
);
4833 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4838 intel_dp_detect(struct drm_connector
*connector
,
4839 struct drm_modeset_acquire_ctx
*ctx
,
4842 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4843 int status
= connector
->status
;
4845 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4846 connector
->base
.id
, connector
->name
);
4848 /* If full detect is not performed yet, do a full detect */
4849 if (!intel_dp
->detect_done
) {
4850 struct drm_crtc
*crtc
;
4853 crtc
= connector
->state
->crtc
;
4855 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
4860 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4863 intel_dp
->detect_done
= false;
4869 intel_dp_force(struct drm_connector
*connector
)
4871 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4872 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4873 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4875 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4876 connector
->base
.id
, connector
->name
);
4877 intel_dp_unset_edid(intel_dp
);
4879 if (connector
->status
!= connector_status_connected
)
4882 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4884 intel_dp_set_edid(intel_dp
);
4886 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4889 static int intel_dp_get_modes(struct drm_connector
*connector
)
4891 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4894 edid
= intel_connector
->detect_edid
;
4896 int ret
= intel_connector_update_modes(connector
, edid
);
4901 /* if eDP has no EDID, fall back to fixed mode */
4902 if (intel_dp_is_edp(intel_attached_dp(connector
)) &&
4903 intel_connector
->panel
.fixed_mode
) {
4904 struct drm_display_mode
*mode
;
4906 mode
= drm_mode_duplicate(connector
->dev
,
4907 intel_connector
->panel
.fixed_mode
);
4909 drm_mode_probed_add(connector
, mode
);
4918 intel_dp_connector_register(struct drm_connector
*connector
)
4920 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4923 ret
= intel_connector_register(connector
);
4927 i915_debugfs_connector_add(connector
);
4929 DRM_DEBUG_KMS("registering %s bus for %s\n",
4930 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4932 intel_dp
->aux
.dev
= connector
->kdev
;
4933 return drm_dp_aux_register(&intel_dp
->aux
);
4937 intel_dp_connector_unregister(struct drm_connector
*connector
)
4939 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4940 intel_connector_unregister(connector
);
4944 intel_dp_connector_destroy(struct drm_connector
*connector
)
4946 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4948 kfree(intel_connector
->detect_edid
);
4950 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4951 kfree(intel_connector
->edid
);
4954 * Can't call intel_dp_is_edp() since the encoder may have been
4955 * destroyed already.
4957 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4958 intel_panel_fini(&intel_connector
->panel
);
4960 drm_connector_cleanup(connector
);
4964 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4966 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4967 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4969 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4970 if (intel_dp_is_edp(intel_dp
)) {
4971 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4973 * vdd might still be enabled do to the delayed vdd off.
4974 * Make sure vdd is actually turned off here.
4977 edp_panel_vdd_off_sync(intel_dp
);
4978 pps_unlock(intel_dp
);
4980 if (intel_dp
->edp_notifier
.notifier_call
) {
4981 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4982 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4986 intel_dp_aux_fini(intel_dp
);
4988 drm_encoder_cleanup(encoder
);
4989 kfree(intel_dig_port
);
4992 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4994 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4996 if (!intel_dp_is_edp(intel_dp
))
5000 * vdd might still be enabled do to the delayed vdd off.
5001 * Make sure vdd is actually turned off here.
5003 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5005 edp_panel_vdd_off_sync(intel_dp
);
5006 pps_unlock(intel_dp
);
5010 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port
,
5013 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_dig_port
->base
.base
);
5014 static const struct drm_dp_aux_msg msg
= {
5015 .request
= DP_AUX_NATIVE_WRITE
,
5016 .address
= DP_AUX_HDCP_AKSV
,
5017 .size
= DRM_HDCP_KSV_LEN
,
5019 uint8_t txbuf
[HEADER_SIZE
+ DRM_HDCP_KSV_LEN
] = {}, rxbuf
[2], reply
= 0;
5023 /* Output An first, that's easy */
5024 dpcd_ret
= drm_dp_dpcd_write(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_AN
,
5025 an
, DRM_HDCP_AN_LEN
);
5026 if (dpcd_ret
!= DRM_HDCP_AN_LEN
) {
5027 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret
);
5028 return dpcd_ret
>= 0 ? -EIO
: dpcd_ret
;
5032 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5033 * order to get it on the wire, we need to create the AUX header as if
5034 * we were writing the data, and then tickle the hardware to output the
5035 * data once the header is sent out.
5037 intel_dp_aux_header(txbuf
, &msg
);
5039 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, HEADER_SIZE
+ msg
.size
,
5040 rxbuf
, sizeof(rxbuf
),
5041 DP_AUX_CH_CTL_AUX_AKSV_SELECT
);
5043 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret
);
5045 } else if (ret
== 0) {
5046 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5050 reply
= (rxbuf
[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK
;
5051 return reply
== DP_AUX_NATIVE_REPLY_ACK
? 0 : -EIO
;
5054 static int intel_dp_hdcp_read_bksv(struct intel_digital_port
*intel_dig_port
,
5058 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BKSV
, bksv
,
5060 if (ret
!= DRM_HDCP_KSV_LEN
) {
5061 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret
);
5062 return ret
>= 0 ? -EIO
: ret
;
5067 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port
,
5072 * For some reason the HDMI and DP HDCP specs call this register
5073 * definition by different names. In the HDMI spec, it's called BSTATUS,
5074 * but in DP it's called BINFO.
5076 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BINFO
,
5077 bstatus
, DRM_HDCP_BSTATUS_LEN
);
5078 if (ret
!= DRM_HDCP_BSTATUS_LEN
) {
5079 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5080 return ret
>= 0 ? -EIO
: ret
;
5086 int intel_dp_hdcp_read_bcaps(struct intel_digital_port
*intel_dig_port
,
5091 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BCAPS
,
5094 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret
);
5095 return ret
>= 0 ? -EIO
: ret
;
5102 int intel_dp_hdcp_repeater_present(struct intel_digital_port
*intel_dig_port
,
5103 bool *repeater_present
)
5108 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5112 *repeater_present
= bcaps
& DP_BCAPS_REPEATER_PRESENT
;
5117 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port
*intel_dig_port
,
5121 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_RI_PRIME
,
5122 ri_prime
, DRM_HDCP_RI_LEN
);
5123 if (ret
!= DRM_HDCP_RI_LEN
) {
5124 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret
);
5125 return ret
>= 0 ? -EIO
: ret
;
5131 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port
*intel_dig_port
,
5136 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5139 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5140 return ret
>= 0 ? -EIO
: ret
;
5142 *ksv_ready
= bstatus
& DP_BSTATUS_READY
;
5147 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port
*intel_dig_port
,
5148 int num_downstream
, u8
*ksv_fifo
)
5153 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5154 for (i
= 0; i
< num_downstream
; i
+= 3) {
5155 size_t len
= min(num_downstream
- i
, 3) * DRM_HDCP_KSV_LEN
;
5156 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5157 DP_AUX_HDCP_KSV_FIFO
,
5158 ksv_fifo
+ i
* DRM_HDCP_KSV_LEN
,
5161 DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i
,
5163 return ret
>= 0 ? -EIO
: ret
;
5170 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port
*intel_dig_port
,
5175 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
5178 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5179 DP_AUX_HDCP_V_PRIME(i
), part
,
5180 DRM_HDCP_V_PRIME_PART_LEN
);
5181 if (ret
!= DRM_HDCP_V_PRIME_PART_LEN
) {
5182 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i
, ret
);
5183 return ret
>= 0 ? -EIO
: ret
;
5189 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port
*intel_dig_port
,
5192 /* Not used for single stream DisplayPort setups */
5197 bool intel_dp_hdcp_check_link(struct intel_digital_port
*intel_dig_port
)
5202 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5205 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5209 return !(bstatus
& (DP_BSTATUS_LINK_FAILURE
| DP_BSTATUS_REAUTH_REQ
));
5213 int intel_dp_hdcp_capable(struct intel_digital_port
*intel_dig_port
,
5219 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5223 *hdcp_capable
= bcaps
& DP_BCAPS_HDCP_CAPABLE
;
5227 static const struct intel_hdcp_shim intel_dp_hdcp_shim
= {
5228 .write_an_aksv
= intel_dp_hdcp_write_an_aksv
,
5229 .read_bksv
= intel_dp_hdcp_read_bksv
,
5230 .read_bstatus
= intel_dp_hdcp_read_bstatus
,
5231 .repeater_present
= intel_dp_hdcp_repeater_present
,
5232 .read_ri_prime
= intel_dp_hdcp_read_ri_prime
,
5233 .read_ksv_ready
= intel_dp_hdcp_read_ksv_ready
,
5234 .read_ksv_fifo
= intel_dp_hdcp_read_ksv_fifo
,
5235 .read_v_prime_part
= intel_dp_hdcp_read_v_prime_part
,
5236 .toggle_signalling
= intel_dp_hdcp_toggle_signalling
,
5237 .check_link
= intel_dp_hdcp_check_link
,
5238 .hdcp_capable
= intel_dp_hdcp_capable
,
5241 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
5243 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5245 lockdep_assert_held(&dev_priv
->pps_mutex
);
5247 if (!edp_have_panel_vdd(intel_dp
))
5251 * The VDD bit needs a power domain reference, so if the bit is
5252 * already enabled when we boot or resume, grab this reference and
5253 * schedule a vdd off, so we don't hold on to the reference
5256 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5257 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5259 edp_panel_vdd_schedule_off(intel_dp
);
5262 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
5264 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5266 if ((intel_dp
->DP
& DP_PORT_EN
) == 0)
5267 return INVALID_PIPE
;
5269 if (IS_CHERRYVIEW(dev_priv
))
5270 return DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5272 return PORT_TO_PIPE(intel_dp
->DP
);
5275 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
5277 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
5278 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
5279 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
5281 if (!HAS_DDI(dev_priv
))
5282 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5285 lspcon_resume(lspcon
);
5287 intel_dp
->reset_link_params
= true;
5291 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5292 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5294 if (intel_dp_is_edp(intel_dp
)) {
5295 /* Reinit the power sequencer, in case BIOS did something with it. */
5296 intel_dp_pps_init(intel_dp
);
5297 intel_edp_panel_vdd_sanitize(intel_dp
);
5300 pps_unlock(intel_dp
);
5303 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5304 .force
= intel_dp_force
,
5305 .fill_modes
= drm_helper_probe_single_connector_modes
,
5306 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
5307 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
5308 .late_register
= intel_dp_connector_register
,
5309 .early_unregister
= intel_dp_connector_unregister
,
5310 .destroy
= intel_dp_connector_destroy
,
5311 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5312 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5315 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5316 .detect_ctx
= intel_dp_detect
,
5317 .get_modes
= intel_dp_get_modes
,
5318 .mode_valid
= intel_dp_mode_valid
,
5319 .atomic_check
= intel_digital_connector_atomic_check
,
5322 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5323 .reset
= intel_dp_encoder_reset
,
5324 .destroy
= intel_dp_encoder_destroy
,
5328 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5330 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5331 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5332 enum irqreturn ret
= IRQ_NONE
;
5334 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5336 * vdd off can generate a long pulse on eDP which
5337 * would require vdd on to handle it, and thus we
5338 * would end up in an endless cycle of
5339 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5341 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5342 port_name(intel_dig_port
->base
.port
));
5346 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5347 port_name(intel_dig_port
->base
.port
),
5348 long_hpd
? "long" : "short");
5351 intel_dp
->reset_link_params
= true;
5352 intel_dp
->detect_done
= false;
5356 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5358 if (intel_dp
->is_mst
) {
5359 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5361 * If we were in MST mode, and device is not
5362 * there, get out of MST mode
5364 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5365 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5366 intel_dp
->is_mst
= false;
5367 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5369 intel_dp
->detect_done
= false;
5374 if (!intel_dp
->is_mst
) {
5375 struct drm_modeset_acquire_ctx ctx
;
5376 struct drm_connector
*connector
= &intel_dp
->attached_connector
->base
;
5377 struct drm_crtc
*crtc
;
5379 bool handled
= false;
5381 drm_modeset_acquire_init(&ctx
, 0);
5383 iret
= drm_modeset_lock(&dev_priv
->drm
.mode_config
.connection_mutex
, &ctx
);
5387 crtc
= connector
->state
->crtc
;
5389 iret
= drm_modeset_lock(&crtc
->mutex
, &ctx
);
5394 handled
= intel_dp_short_pulse(intel_dp
);
5397 if (iret
== -EDEADLK
) {
5398 drm_modeset_backoff(&ctx
);
5402 drm_modeset_drop_locks(&ctx
);
5403 drm_modeset_acquire_fini(&ctx
);
5404 WARN(iret
, "Acquiring modeset locks failed with %i\n", iret
);
5406 /* Short pulse can signify loss of hdcp authentication */
5407 intel_hdcp_check_link(intel_dp
->attached_connector
);
5410 intel_dp
->detect_done
= false;
5418 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5423 /* check the VBT to see whether the eDP is on another port */
5424 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5427 * eDP not supported on g4x. so bail out early just
5428 * for a bit extra safety in case the VBT is bonkers.
5430 if (INTEL_GEN(dev_priv
) < 5)
5433 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5436 return intel_bios_is_port_edp(dev_priv
, port
);
5440 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5442 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5443 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5445 if (!IS_G4X(dev_priv
) && port
!= PORT_A
)
5446 intel_attach_force_audio_property(connector
);
5448 intel_attach_broadcast_rgb_property(connector
);
5450 if (intel_dp_is_edp(intel_dp
)) {
5451 u32 allowed_scalers
;
5453 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
5454 if (!HAS_GMCH_DISPLAY(dev_priv
))
5455 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
5457 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
5459 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
5464 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5466 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5467 intel_dp
->last_power_on
= jiffies
;
5468 intel_dp
->last_backlight_off
= jiffies
;
5472 intel_pps_readout_hw_state(struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5474 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5475 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5476 struct pps_registers regs
;
5478 intel_pps_get_registers(intel_dp
, ®s
);
5480 /* Workaround: Need to write PP_CONTROL with the unlock key as
5481 * the very first thing. */
5482 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5484 pp_on
= I915_READ(regs
.pp_on
);
5485 pp_off
= I915_READ(regs
.pp_off
);
5486 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
5487 !HAS_PCH_ICP(dev_priv
)) {
5488 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5489 pp_div
= I915_READ(regs
.pp_div
);
5492 /* Pull timing values out of registers */
5493 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5494 PANEL_POWER_UP_DELAY_SHIFT
;
5496 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5497 PANEL_LIGHT_ON_DELAY_SHIFT
;
5499 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5500 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5502 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5503 PANEL_POWER_DOWN_DELAY_SHIFT
;
5505 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5506 HAS_PCH_ICP(dev_priv
)) {
5507 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5508 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5510 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5511 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5516 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5518 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5520 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5524 intel_pps_verify_state(struct intel_dp
*intel_dp
)
5526 struct edp_power_seq hw
;
5527 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5529 intel_pps_readout_hw_state(intel_dp
, &hw
);
5531 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5532 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5533 DRM_ERROR("PPS state mismatch\n");
5534 intel_pps_dump_state("sw", sw
);
5535 intel_pps_dump_state("hw", &hw
);
5540 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
5542 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5543 struct edp_power_seq cur
, vbt
, spec
,
5544 *final
= &intel_dp
->pps_delays
;
5546 lockdep_assert_held(&dev_priv
->pps_mutex
);
5548 /* already initialized? */
5549 if (final
->t11_t12
!= 0)
5552 intel_pps_readout_hw_state(intel_dp
, &cur
);
5554 intel_pps_dump_state("cur", &cur
);
5556 vbt
= dev_priv
->vbt
.edp
.pps
;
5557 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5558 * of 500ms appears to be too short. Ocassionally the panel
5559 * just fails to power back on. Increasing the delay to 800ms
5560 * seems sufficient to avoid this problem.
5562 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
5563 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 1300 * 10);
5564 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5567 /* T11_T12 delay is special and actually in units of 100ms, but zero
5568 * based in the hw (so we need to add 100 ms). But the sw vbt
5569 * table multiplies it with 1000 to make it in units of 100usec,
5571 vbt
.t11_t12
+= 100 * 10;
5573 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5574 * our hw here, which are all in 100usec. */
5575 spec
.t1_t3
= 210 * 10;
5576 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5577 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5578 spec
.t10
= 500 * 10;
5579 /* This one is special and actually in units of 100ms, but zero
5580 * based in the hw (so we need to add 100 ms). But the sw vbt
5581 * table multiplies it with 1000 to make it in units of 100usec,
5583 spec
.t11_t12
= (510 + 100) * 10;
5585 intel_pps_dump_state("vbt", &vbt
);
5587 /* Use the max of the register settings and vbt. If both are
5588 * unset, fall back to the spec limits. */
5589 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5591 max(cur.field, vbt.field))
5592 assign_final(t1_t3
);
5596 assign_final(t11_t12
);
5599 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5600 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5601 intel_dp
->backlight_on_delay
= get_delay(t8
);
5602 intel_dp
->backlight_off_delay
= get_delay(t9
);
5603 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5604 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5607 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5608 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5609 intel_dp
->panel_power_cycle_delay
);
5611 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5612 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5615 * We override the HW backlight delays to 1 because we do manual waits
5616 * on them. For T8, even BSpec recommends doing it. For T9, if we
5617 * don't do this, we'll end up waiting for the backlight off delay
5618 * twice: once when we do the manual sleep, and once when we disable
5619 * the panel and wait for the PP_STATUS bit to become zero.
5625 * HW has only a 100msec granularity for t11_t12 so round it up
5628 final
->t11_t12
= roundup(final
->t11_t12
, 100 * 10);
5632 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
5633 bool force_disable_vdd
)
5635 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5636 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5637 int div
= dev_priv
->rawclk_freq
/ 1000;
5638 struct pps_registers regs
;
5639 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5640 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5642 lockdep_assert_held(&dev_priv
->pps_mutex
);
5644 intel_pps_get_registers(intel_dp
, ®s
);
5647 * On some VLV machines the BIOS can leave the VDD
5648 * enabled even on power seqeuencers which aren't
5649 * hooked up to any port. This would mess up the
5650 * power domain tracking the first time we pick
5651 * one of these power sequencers for use since
5652 * edp_panel_vdd_on() would notice that the VDD was
5653 * already on and therefore wouldn't grab the power
5654 * domain reference. Disable VDD first to avoid this.
5655 * This also avoids spuriously turning the VDD on as
5656 * soon as the new power seqeuencer gets initialized.
5658 if (force_disable_vdd
) {
5659 u32 pp
= ironlake_get_pp_control(intel_dp
);
5661 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5663 if (pp
& EDP_FORCE_VDD
)
5664 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5666 pp
&= ~EDP_FORCE_VDD
;
5668 I915_WRITE(regs
.pp_ctrl
, pp
);
5671 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5672 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5673 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5674 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5675 /* Compute the divisor for the pp clock, simply match the Bspec
5677 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5678 HAS_PCH_ICP(dev_priv
)) {
5679 pp_div
= I915_READ(regs
.pp_ctrl
);
5680 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5681 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5682 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5684 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5685 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5686 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5689 /* Haswell doesn't have any port selection bits for the panel
5690 * power sequencer any more. */
5691 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5692 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5693 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5695 port_sel
= PANEL_PORT_SELECT_DPA
;
5697 port_sel
= PANEL_PORT_SELECT_DPD
;
5702 I915_WRITE(regs
.pp_on
, pp_on
);
5703 I915_WRITE(regs
.pp_off
, pp_off
);
5704 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5705 HAS_PCH_ICP(dev_priv
))
5706 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5708 I915_WRITE(regs
.pp_div
, pp_div
);
5710 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5711 I915_READ(regs
.pp_on
),
5712 I915_READ(regs
.pp_off
),
5713 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5714 HAS_PCH_ICP(dev_priv
)) ?
5715 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5716 I915_READ(regs
.pp_div
));
5719 static void intel_dp_pps_init(struct intel_dp
*intel_dp
)
5721 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5723 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5724 vlv_initial_power_sequencer_setup(intel_dp
);
5726 intel_dp_init_panel_power_sequencer(intel_dp
);
5727 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
5732 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5733 * @dev_priv: i915 device
5734 * @crtc_state: a pointer to the active intel_crtc_state
5735 * @refresh_rate: RR to be programmed
5737 * This function gets called when refresh rate (RR) has to be changed from
5738 * one frequency to another. Switches can be between high and low RR
5739 * supported by the panel or to any other RR based on media playback (in
5740 * this case, RR value needs to be passed from user space).
5742 * The caller of this function needs to take a lock on dev_priv->drrs.
5744 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5745 const struct intel_crtc_state
*crtc_state
,
5748 struct intel_encoder
*encoder
;
5749 struct intel_digital_port
*dig_port
= NULL
;
5750 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5752 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5754 if (refresh_rate
<= 0) {
5755 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5759 if (intel_dp
== NULL
) {
5760 DRM_DEBUG_KMS("DRRS not supported.\n");
5764 dig_port
= dp_to_dig_port(intel_dp
);
5765 encoder
= &dig_port
->base
;
5768 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5772 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5773 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5777 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5779 index
= DRRS_LOW_RR
;
5781 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5783 "DRRS requested for previously set RR...ignoring\n");
5787 if (!crtc_state
->base
.active
) {
5788 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5792 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5795 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5798 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5802 DRM_ERROR("Unsupported refreshrate type\n");
5804 } else if (INTEL_GEN(dev_priv
) > 6) {
5805 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5808 val
= I915_READ(reg
);
5809 if (index
> DRRS_HIGH_RR
) {
5810 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5811 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5813 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5815 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5816 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5818 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5820 I915_WRITE(reg
, val
);
5823 dev_priv
->drrs
.refresh_rate_type
= index
;
5825 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5829 * intel_edp_drrs_enable - init drrs struct if supported
5830 * @intel_dp: DP struct
5831 * @crtc_state: A pointer to the active crtc state.
5833 * Initializes frontbuffer_bits and drrs.dp
5835 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5836 const struct intel_crtc_state
*crtc_state
)
5838 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5840 if (!crtc_state
->has_drrs
) {
5841 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5845 if (dev_priv
->psr
.enabled
) {
5846 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5850 mutex_lock(&dev_priv
->drrs
.mutex
);
5851 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5852 DRM_ERROR("DRRS already enabled\n");
5856 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5858 dev_priv
->drrs
.dp
= intel_dp
;
5861 mutex_unlock(&dev_priv
->drrs
.mutex
);
5865 * intel_edp_drrs_disable - Disable DRRS
5866 * @intel_dp: DP struct
5867 * @old_crtc_state: Pointer to old crtc_state.
5870 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5871 const struct intel_crtc_state
*old_crtc_state
)
5873 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5875 if (!old_crtc_state
->has_drrs
)
5878 mutex_lock(&dev_priv
->drrs
.mutex
);
5879 if (!dev_priv
->drrs
.dp
) {
5880 mutex_unlock(&dev_priv
->drrs
.mutex
);
5884 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5885 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5886 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5888 dev_priv
->drrs
.dp
= NULL
;
5889 mutex_unlock(&dev_priv
->drrs
.mutex
);
5891 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5894 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5896 struct drm_i915_private
*dev_priv
=
5897 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5898 struct intel_dp
*intel_dp
;
5900 mutex_lock(&dev_priv
->drrs
.mutex
);
5902 intel_dp
= dev_priv
->drrs
.dp
;
5908 * The delayed work can race with an invalidate hence we need to
5912 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5915 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5916 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5918 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5919 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5923 mutex_unlock(&dev_priv
->drrs
.mutex
);
5927 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5928 * @dev_priv: i915 device
5929 * @frontbuffer_bits: frontbuffer plane tracking bits
5931 * This function gets called everytime rendering on the given planes start.
5932 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5934 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5936 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5937 unsigned int frontbuffer_bits
)
5939 struct drm_crtc
*crtc
;
5942 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5945 cancel_delayed_work(&dev_priv
->drrs
.work
);
5947 mutex_lock(&dev_priv
->drrs
.mutex
);
5948 if (!dev_priv
->drrs
.dp
) {
5949 mutex_unlock(&dev_priv
->drrs
.mutex
);
5953 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5954 pipe
= to_intel_crtc(crtc
)->pipe
;
5956 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5957 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5959 /* invalidate means busy screen hence upclock */
5960 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5961 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5962 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5964 mutex_unlock(&dev_priv
->drrs
.mutex
);
5968 * intel_edp_drrs_flush - Restart Idleness DRRS
5969 * @dev_priv: i915 device
5970 * @frontbuffer_bits: frontbuffer plane tracking bits
5972 * This function gets called every time rendering on the given planes has
5973 * completed or flip on a crtc is completed. So DRRS should be upclocked
5974 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5975 * if no other planes are dirty.
5977 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5979 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5980 unsigned int frontbuffer_bits
)
5982 struct drm_crtc
*crtc
;
5985 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5988 cancel_delayed_work(&dev_priv
->drrs
.work
);
5990 mutex_lock(&dev_priv
->drrs
.mutex
);
5991 if (!dev_priv
->drrs
.dp
) {
5992 mutex_unlock(&dev_priv
->drrs
.mutex
);
5996 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5997 pipe
= to_intel_crtc(crtc
)->pipe
;
5999 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6000 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
6002 /* flush means busy screen hence upclock */
6003 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6004 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6005 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6008 * flush also means no more activity hence schedule downclock, if all
6009 * other fbs are quiescent too
6011 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
6012 schedule_delayed_work(&dev_priv
->drrs
.work
,
6013 msecs_to_jiffies(1000));
6014 mutex_unlock(&dev_priv
->drrs
.mutex
);
6018 * DOC: Display Refresh Rate Switching (DRRS)
6020 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6021 * which enables swtching between low and high refresh rates,
6022 * dynamically, based on the usage scenario. This feature is applicable
6023 * for internal panels.
6025 * Indication that the panel supports DRRS is given by the panel EDID, which
6026 * would list multiple refresh rates for one resolution.
6028 * DRRS is of 2 types - static and seamless.
6029 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6030 * (may appear as a blink on screen) and is used in dock-undock scenario.
6031 * Seamless DRRS involves changing RR without any visual effect to the user
6032 * and can be used during normal system usage. This is done by programming
6033 * certain registers.
6035 * Support for static/seamless DRRS may be indicated in the VBT based on
6036 * inputs from the panel spec.
6038 * DRRS saves power by switching to low RR based on usage scenarios.
6040 * The implementation is based on frontbuffer tracking implementation. When
6041 * there is a disturbance on the screen triggered by user activity or a periodic
6042 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6043 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6046 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6047 * and intel_edp_drrs_flush() are called.
6049 * DRRS can be further extended to support other internal panels and also
6050 * the scenario of video playback wherein RR is set based on the rate
6051 * requested by userspace.
6055 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6056 * @connector: eDP connector
6057 * @fixed_mode: preferred mode of panel
6059 * This function is called only once at driver load to initialize basic
6063 * Downclock mode if panel supports it, else return NULL.
6064 * DRRS support is determined by the presence of downclock mode (apart
6065 * from VBT setting).
6067 static struct drm_display_mode
*
6068 intel_dp_drrs_init(struct intel_connector
*connector
,
6069 struct drm_display_mode
*fixed_mode
)
6071 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
6072 struct drm_display_mode
*downclock_mode
= NULL
;
6074 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
6075 mutex_init(&dev_priv
->drrs
.mutex
);
6077 if (INTEL_GEN(dev_priv
) <= 6) {
6078 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6082 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
6083 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6087 downclock_mode
= intel_find_panel_downclock(dev_priv
, fixed_mode
,
6090 if (!downclock_mode
) {
6091 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6095 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
6097 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
6098 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6099 return downclock_mode
;
6102 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
6103 struct intel_connector
*intel_connector
)
6105 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
6106 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6107 struct drm_connector
*connector
= &intel_connector
->base
;
6108 struct drm_display_mode
*fixed_mode
= NULL
;
6109 struct drm_display_mode
*alt_fixed_mode
= NULL
;
6110 struct drm_display_mode
*downclock_mode
= NULL
;
6112 struct drm_display_mode
*scan
;
6114 enum pipe pipe
= INVALID_PIPE
;
6116 if (!intel_dp_is_edp(intel_dp
))
6120 * On IBX/CPT we may get here with LVDS already registered. Since the
6121 * driver uses the only internal power sequencer available for both
6122 * eDP and LVDS bail out early in this case to prevent interfering
6123 * with an already powered-on LVDS power sequencer.
6125 if (intel_get_lvds_encoder(&dev_priv
->drm
)) {
6126 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
6127 DRM_INFO("LVDS was detected, not registering eDP\n");
6134 intel_dp_init_panel_power_timestamps(intel_dp
);
6135 intel_dp_pps_init(intel_dp
);
6136 intel_edp_panel_vdd_sanitize(intel_dp
);
6138 pps_unlock(intel_dp
);
6140 /* Cache DPCD and EDID for edp. */
6141 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
6144 /* if this fails, presume the device is a ghost */
6145 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6149 mutex_lock(&dev
->mode_config
.mutex
);
6150 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
6152 if (drm_add_edid_modes(connector
, edid
)) {
6153 drm_mode_connector_update_edid_property(connector
,
6157 edid
= ERR_PTR(-EINVAL
);
6160 edid
= ERR_PTR(-ENOENT
);
6162 intel_connector
->edid
= edid
;
6164 /* prefer fixed mode from EDID if available, save an alt mode also */
6165 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
6166 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
6167 fixed_mode
= drm_mode_duplicate(dev
, scan
);
6168 downclock_mode
= intel_dp_drrs_init(
6169 intel_connector
, fixed_mode
);
6170 } else if (!alt_fixed_mode
) {
6171 alt_fixed_mode
= drm_mode_duplicate(dev
, scan
);
6175 /* fallback to VBT if available for eDP */
6176 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
6177 fixed_mode
= drm_mode_duplicate(dev
,
6178 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
6180 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
6181 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
6182 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
6185 mutex_unlock(&dev
->mode_config
.mutex
);
6187 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6188 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
6189 register_reboot_notifier(&intel_dp
->edp_notifier
);
6192 * Figure out the current pipe for the initial backlight setup.
6193 * If the current pipe isn't valid, try the PPS pipe, and if that
6194 * fails just assume pipe A.
6196 pipe
= vlv_active_pipe(intel_dp
);
6198 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6199 pipe
= intel_dp
->pps_pipe
;
6201 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6204 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6208 intel_panel_init(&intel_connector
->panel
, fixed_mode
, alt_fixed_mode
,
6210 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
6211 intel_panel_setup_backlight(connector
, pipe
);
6216 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
6218 * vdd might still be enabled do to the delayed vdd off.
6219 * Make sure vdd is actually turned off here.
6222 edp_panel_vdd_off_sync(intel_dp
);
6223 pps_unlock(intel_dp
);
6228 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
6230 struct intel_connector
*intel_connector
;
6231 struct drm_connector
*connector
;
6233 intel_connector
= container_of(work
, typeof(*intel_connector
),
6234 modeset_retry_work
);
6235 connector
= &intel_connector
->base
;
6236 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
6239 /* Grab the locks before changing connector property*/
6240 mutex_lock(&connector
->dev
->mode_config
.mutex
);
6241 /* Set connector link status to BAD and send a Uevent to notify
6242 * userspace to do a modeset.
6244 drm_mode_connector_set_link_status_property(connector
,
6245 DRM_MODE_LINK_STATUS_BAD
);
6246 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
6247 /* Send Hotplug uevent so userspace can reprobe */
6248 drm_kms_helper_hotplug_event(connector
->dev
);
6252 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
6253 struct intel_connector
*intel_connector
)
6255 struct drm_connector
*connector
= &intel_connector
->base
;
6256 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
6257 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
6258 struct drm_device
*dev
= intel_encoder
->base
.dev
;
6259 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6260 enum port port
= intel_encoder
->port
;
6263 /* Initialize the work for modeset in case of link train failure */
6264 INIT_WORK(&intel_connector
->modeset_retry_work
,
6265 intel_dp_modeset_retry_work_fn
);
6267 if (WARN(intel_dig_port
->max_lanes
< 1,
6268 "Not enough lanes (%d) for DP on port %c\n",
6269 intel_dig_port
->max_lanes
, port_name(port
)))
6272 intel_dp_set_source_rates(intel_dp
);
6274 intel_dp
->reset_link_params
= true;
6275 intel_dp
->pps_pipe
= INVALID_PIPE
;
6276 intel_dp
->active_pipe
= INVALID_PIPE
;
6278 /* intel_dp vfuncs */
6279 if (HAS_DDI(dev_priv
))
6280 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6282 /* Preserve the current hw state. */
6283 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6284 intel_dp
->attached_connector
= intel_connector
;
6286 if (intel_dp_is_port_edp(dev_priv
, port
))
6287 type
= DRM_MODE_CONNECTOR_eDP
;
6289 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6291 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6292 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6295 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6296 * for DP the encoder type can be set by the caller to
6297 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6299 if (type
== DRM_MODE_CONNECTOR_eDP
)
6300 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6302 /* eDP only on port B and/or C on vlv/chv */
6303 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6304 intel_dp_is_edp(intel_dp
) &&
6305 port
!= PORT_B
&& port
!= PORT_C
))
6308 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6309 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6312 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6313 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6315 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
6316 connector
->interlace_allowed
= true;
6317 connector
->doublescan_allowed
= 0;
6319 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
6321 intel_dp_aux_init(intel_dp
);
6323 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6324 edp_panel_vdd_work
);
6326 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6328 if (HAS_DDI(dev_priv
))
6329 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6331 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6333 /* init MST on ports that can support it */
6334 if (HAS_DP_MST(dev_priv
) && !intel_dp_is_edp(intel_dp
) &&
6335 (port
== PORT_B
|| port
== PORT_C
||
6336 port
== PORT_D
|| port
== PORT_F
))
6337 intel_dp_mst_encoder_init(intel_dig_port
,
6338 intel_connector
->base
.base
.id
);
6340 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6341 intel_dp_aux_fini(intel_dp
);
6342 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6346 intel_dp_add_properties(intel_dp
, connector
);
6348 if (is_hdcp_supported(dev_priv
, port
) && !intel_dp_is_edp(intel_dp
)) {
6349 int ret
= intel_hdcp_init(intel_connector
, &intel_dp_hdcp_shim
);
6351 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6354 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6355 * 0xd. Failure to do so will result in spurious interrupts being
6356 * generated on the port when a cable is not attached.
6358 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
6359 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6360 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6366 drm_connector_cleanup(connector
);
6371 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6372 i915_reg_t output_reg
,
6375 struct intel_digital_port
*intel_dig_port
;
6376 struct intel_encoder
*intel_encoder
;
6377 struct drm_encoder
*encoder
;
6378 struct intel_connector
*intel_connector
;
6380 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6381 if (!intel_dig_port
)
6384 intel_connector
= intel_connector_alloc();
6385 if (!intel_connector
)
6386 goto err_connector_alloc
;
6388 intel_encoder
= &intel_dig_port
->base
;
6389 encoder
= &intel_encoder
->base
;
6391 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6392 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6393 "DP %c", port_name(port
)))
6394 goto err_encoder_init
;
6396 intel_encoder
->hotplug
= intel_encoder_hotplug
;
6397 intel_encoder
->compute_config
= intel_dp_compute_config
;
6398 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6399 intel_encoder
->get_config
= intel_dp_get_config
;
6400 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6401 if (IS_CHERRYVIEW(dev_priv
)) {
6402 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6403 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6404 intel_encoder
->enable
= vlv_enable_dp
;
6405 intel_encoder
->disable
= vlv_disable_dp
;
6406 intel_encoder
->post_disable
= chv_post_disable_dp
;
6407 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6408 } else if (IS_VALLEYVIEW(dev_priv
)) {
6409 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6410 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6411 intel_encoder
->enable
= vlv_enable_dp
;
6412 intel_encoder
->disable
= vlv_disable_dp
;
6413 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6414 } else if (INTEL_GEN(dev_priv
) >= 5) {
6415 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6416 intel_encoder
->enable
= g4x_enable_dp
;
6417 intel_encoder
->disable
= ilk_disable_dp
;
6418 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6420 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6421 intel_encoder
->enable
= g4x_enable_dp
;
6422 intel_encoder
->disable
= g4x_disable_dp
;
6425 intel_dig_port
->dp
.output_reg
= output_reg
;
6426 intel_dig_port
->max_lanes
= 4;
6428 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6429 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6430 if (IS_CHERRYVIEW(dev_priv
)) {
6432 intel_encoder
->crtc_mask
= 1 << 2;
6434 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6436 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6438 intel_encoder
->cloneable
= 0;
6439 intel_encoder
->port
= port
;
6441 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6442 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6445 intel_infoframe_init(intel_dig_port
);
6447 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6448 goto err_init_connector
;
6453 drm_encoder_cleanup(encoder
);
6455 kfree(intel_connector
);
6456 err_connector_alloc
:
6457 kfree(intel_dig_port
);
6461 void intel_dp_mst_suspend(struct drm_device
*dev
)
6463 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6467 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6468 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6470 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6473 if (intel_dig_port
->dp
.is_mst
)
6474 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6478 void intel_dp_mst_resume(struct drm_device
*dev
)
6480 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6483 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6484 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6487 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6490 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6492 intel_dp_check_mst_status(&intel_dig_port
->dp
);