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drm/i915: Unlock PCH_PP_CONTROL always
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 struct intel_dp {
46 struct intel_encoder base;
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 bool has_audio;
51 int force_audio;
52 uint32_t color_range;
53 int dpms_mode;
54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[8];
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59 bool is_pch_edp;
60 uint8_t train_set[4];
61 uint8_t link_status[DP_LINK_STATUS_SIZE];
62 };
63
64 /**
65 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
66 * @intel_dp: DP struct
67 *
68 * If a CPU or PCH DP output is attached to an eDP panel, this function
69 * will return true, and false otherwise.
70 */
71 static bool is_edp(struct intel_dp *intel_dp)
72 {
73 return intel_dp->base.type == INTEL_OUTPUT_EDP;
74 }
75
76 /**
77 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
78 * @intel_dp: DP struct
79 *
80 * Returns true if the given DP struct corresponds to a PCH DP port attached
81 * to an eDP panel, false otherwise. Helpful for determining whether we
82 * may need FDI resources for a given DP output or not.
83 */
84 static bool is_pch_edp(struct intel_dp *intel_dp)
85 {
86 return intel_dp->is_pch_edp;
87 }
88
89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
90 {
91 return container_of(encoder, struct intel_dp, base.base);
92 }
93
94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
95 {
96 return container_of(intel_attached_encoder(connector),
97 struct intel_dp, base);
98 }
99
100 /**
101 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
102 * @encoder: DRM encoder
103 *
104 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
105 * by intel_display.c.
106 */
107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
108 {
109 struct intel_dp *intel_dp;
110
111 if (!encoder)
112 return false;
113
114 intel_dp = enc_to_intel_dp(encoder);
115
116 return is_pch_edp(intel_dp);
117 }
118
119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_link_down(struct intel_dp *intel_dp);
122
123 void
124 intel_edp_link_config (struct intel_encoder *intel_encoder,
125 int *lane_num, int *link_bw)
126 {
127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
128
129 *lane_num = intel_dp->lane_count;
130 if (intel_dp->link_bw == DP_LINK_BW_1_62)
131 *link_bw = 162000;
132 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
133 *link_bw = 270000;
134 }
135
136 static int
137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
138 {
139 int max_lane_count = 4;
140
141 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
142 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) {
144 case 1: case 2: case 4:
145 break;
146 default:
147 max_lane_count = 4;
148 }
149 }
150 return max_lane_count;
151 }
152
153 static int
154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
155 {
156 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
157
158 switch (max_link_bw) {
159 case DP_LINK_BW_1_62:
160 case DP_LINK_BW_2_7:
161 break;
162 default:
163 max_link_bw = DP_LINK_BW_1_62;
164 break;
165 }
166 return max_link_bw;
167 }
168
169 static int
170 intel_dp_link_clock(uint8_t link_bw)
171 {
172 if (link_bw == DP_LINK_BW_2_7)
173 return 270000;
174 else
175 return 162000;
176 }
177
178 /* I think this is a fiction */
179 static int
180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
181 {
182 struct drm_crtc *crtc = intel_dp->base.base.crtc;
183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
184 int bpp = 24;
185
186 if (intel_crtc)
187 bpp = intel_crtc->bpp;
188
189 return (pixel_clock * bpp + 7) / 8;
190 }
191
192 static int
193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194 {
195 return (max_link_clock * max_lanes * 8) / 10;
196 }
197
198 static int
199 intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode)
201 {
202 struct intel_dp *intel_dp = intel_attached_dp(connector);
203 struct drm_device *dev = connector->dev;
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
206 int max_lanes = intel_dp_max_lane_count(intel_dp);
207
208 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
209 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
210 return MODE_PANEL;
211
212 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
213 return MODE_PANEL;
214 }
215
216 /* only refuse the mode on non eDP since we have seen some weird eDP panels
217 which are outside spec tolerances but somehow work by magic */
218 if (!is_edp(intel_dp) &&
219 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
220 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
221 return MODE_CLOCK_HIGH;
222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
226 return MODE_OK;
227 }
228
229 static uint32_t
230 pack_aux(uint8_t *src, int src_bytes)
231 {
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240 }
241
242 static void
243 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
244 {
245 int i;
246 if (dst_bytes > 4)
247 dst_bytes = 4;
248 for (i = 0; i < dst_bytes; i++)
249 dst[i] = src >> ((3-i) * 8);
250 }
251
252 /* hrawclock is 1/4 the FSB frequency */
253 static int
254 intel_hrawclk(struct drm_device *dev)
255 {
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 uint32_t clkcfg;
258
259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280 }
281
282 static void
283 intel_dp_check_edp(struct intel_dp *intel_dp)
284 {
285 struct drm_device *dev = intel_dp->base.base.dev;
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 u32 pp_status, pp_control;
288 if (!is_edp(intel_dp))
289 return;
290 pp_status = I915_READ(PCH_PP_STATUS);
291 pp_control = I915_READ(PCH_PP_CONTROL);
292 if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) {
293 WARN(1, "eDP powered off while attempting aux channel communication.\n");
294 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
295 pp_status,
296 I915_READ(PCH_PP_CONTROL));
297 }
298 }
299
300 static int
301 intel_dp_aux_ch(struct intel_dp *intel_dp,
302 uint8_t *send, int send_bytes,
303 uint8_t *recv, int recv_size)
304 {
305 uint32_t output_reg = intel_dp->output_reg;
306 struct drm_device *dev = intel_dp->base.base.dev;
307 struct drm_i915_private *dev_priv = dev->dev_private;
308 uint32_t ch_ctl = output_reg + 0x10;
309 uint32_t ch_data = ch_ctl + 4;
310 int i;
311 int recv_bytes;
312 uint32_t status;
313 uint32_t aux_clock_divider;
314 int try, precharge;
315
316 intel_dp_check_edp(intel_dp);
317 /* The clock divider is based off the hrawclk,
318 * and would like to run at 2MHz. So, take the
319 * hrawclk value and divide by 2 and use that
320 *
321 * Note that PCH attached eDP panels should use a 125MHz input
322 * clock divider.
323 */
324 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
325 if (IS_GEN6(dev))
326 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
327 else
328 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
329 } else if (HAS_PCH_SPLIT(dev))
330 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
331 else
332 aux_clock_divider = intel_hrawclk(dev) / 2;
333
334 if (IS_GEN6(dev))
335 precharge = 3;
336 else
337 precharge = 5;
338
339 /* Try to wait for any previous AUX channel activity */
340 for (try = 0; try < 3; try++) {
341 status = I915_READ(ch_ctl);
342 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
343 break;
344 msleep(1);
345 }
346
347 if (try == 3) {
348 WARN(1, "dp_aux_ch not started status 0x%08x\n",
349 I915_READ(ch_ctl));
350 return -EBUSY;
351 }
352
353 /* Must try at least 3 times according to DP spec */
354 for (try = 0; try < 5; try++) {
355 /* Load the send data into the aux channel data registers */
356 for (i = 0; i < send_bytes; i += 4)
357 I915_WRITE(ch_data + i,
358 pack_aux(send + i, send_bytes - i));
359
360 /* Send the command and wait for it to complete */
361 I915_WRITE(ch_ctl,
362 DP_AUX_CH_CTL_SEND_BUSY |
363 DP_AUX_CH_CTL_TIME_OUT_400us |
364 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
365 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
366 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
367 DP_AUX_CH_CTL_DONE |
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
370 for (;;) {
371 status = I915_READ(ch_ctl);
372 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
373 break;
374 udelay(100);
375 }
376
377 /* Clear done status and any errors */
378 I915_WRITE(ch_ctl,
379 status |
380 DP_AUX_CH_CTL_DONE |
381 DP_AUX_CH_CTL_TIME_OUT_ERROR |
382 DP_AUX_CH_CTL_RECEIVE_ERROR);
383 if (status & DP_AUX_CH_CTL_DONE)
384 break;
385 }
386
387 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
388 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
389 return -EBUSY;
390 }
391
392 /* Check for timeout or receive error.
393 * Timeouts occur when the sink is not connected
394 */
395 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
396 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
397 return -EIO;
398 }
399
400 /* Timeouts occur when the device isn't connected, so they're
401 * "normal" -- don't fill the kernel log with these */
402 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
403 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
404 return -ETIMEDOUT;
405 }
406
407 /* Unload any bytes sent back from the other side */
408 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
409 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
410 if (recv_bytes > recv_size)
411 recv_bytes = recv_size;
412
413 for (i = 0; i < recv_bytes; i += 4)
414 unpack_aux(I915_READ(ch_data + i),
415 recv + i, recv_bytes - i);
416
417 return recv_bytes;
418 }
419
420 /* Write data to the aux channel in native mode */
421 static int
422 intel_dp_aux_native_write(struct intel_dp *intel_dp,
423 uint16_t address, uint8_t *send, int send_bytes)
424 {
425 int ret;
426 uint8_t msg[20];
427 int msg_bytes;
428 uint8_t ack;
429
430 intel_dp_check_edp(intel_dp);
431 if (send_bytes > 16)
432 return -1;
433 msg[0] = AUX_NATIVE_WRITE << 4;
434 msg[1] = address >> 8;
435 msg[2] = address & 0xff;
436 msg[3] = send_bytes - 1;
437 memcpy(&msg[4], send, send_bytes);
438 msg_bytes = send_bytes + 4;
439 for (;;) {
440 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
441 if (ret < 0)
442 return ret;
443 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
444 break;
445 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
446 udelay(100);
447 else
448 return -EIO;
449 }
450 return send_bytes;
451 }
452
453 /* Write a single byte to the aux channel in native mode */
454 static int
455 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
456 uint16_t address, uint8_t byte)
457 {
458 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
459 }
460
461 /* read bytes from a native aux channel */
462 static int
463 intel_dp_aux_native_read(struct intel_dp *intel_dp,
464 uint16_t address, uint8_t *recv, int recv_bytes)
465 {
466 uint8_t msg[4];
467 int msg_bytes;
468 uint8_t reply[20];
469 int reply_bytes;
470 uint8_t ack;
471 int ret;
472
473 intel_dp_check_edp(intel_dp);
474 msg[0] = AUX_NATIVE_READ << 4;
475 msg[1] = address >> 8;
476 msg[2] = address & 0xff;
477 msg[3] = recv_bytes - 1;
478
479 msg_bytes = 4;
480 reply_bytes = recv_bytes + 1;
481
482 for (;;) {
483 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
484 reply, reply_bytes);
485 if (ret == 0)
486 return -EPROTO;
487 if (ret < 0)
488 return ret;
489 ack = reply[0];
490 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
491 memcpy(recv, reply + 1, ret - 1);
492 return ret - 1;
493 }
494 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
495 udelay(100);
496 else
497 return -EIO;
498 }
499 }
500
501 static int
502 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
503 uint8_t write_byte, uint8_t *read_byte)
504 {
505 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
506 struct intel_dp *intel_dp = container_of(adapter,
507 struct intel_dp,
508 adapter);
509 uint16_t address = algo_data->address;
510 uint8_t msg[5];
511 uint8_t reply[2];
512 unsigned retry;
513 int msg_bytes;
514 int reply_bytes;
515 int ret;
516
517 intel_dp_check_edp(intel_dp);
518 /* Set up the command byte */
519 if (mode & MODE_I2C_READ)
520 msg[0] = AUX_I2C_READ << 4;
521 else
522 msg[0] = AUX_I2C_WRITE << 4;
523
524 if (!(mode & MODE_I2C_STOP))
525 msg[0] |= AUX_I2C_MOT << 4;
526
527 msg[1] = address >> 8;
528 msg[2] = address;
529
530 switch (mode) {
531 case MODE_I2C_WRITE:
532 msg[3] = 0;
533 msg[4] = write_byte;
534 msg_bytes = 5;
535 reply_bytes = 1;
536 break;
537 case MODE_I2C_READ:
538 msg[3] = 0;
539 msg_bytes = 4;
540 reply_bytes = 2;
541 break;
542 default:
543 msg_bytes = 3;
544 reply_bytes = 1;
545 break;
546 }
547
548 for (retry = 0; retry < 5; retry++) {
549 ret = intel_dp_aux_ch(intel_dp,
550 msg, msg_bytes,
551 reply, reply_bytes);
552 if (ret < 0) {
553 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
554 return ret;
555 }
556
557 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
558 case AUX_NATIVE_REPLY_ACK:
559 /* I2C-over-AUX Reply field is only valid
560 * when paired with AUX ACK.
561 */
562 break;
563 case AUX_NATIVE_REPLY_NACK:
564 DRM_DEBUG_KMS("aux_ch native nack\n");
565 return -EREMOTEIO;
566 case AUX_NATIVE_REPLY_DEFER:
567 udelay(100);
568 continue;
569 default:
570 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
571 reply[0]);
572 return -EREMOTEIO;
573 }
574
575 switch (reply[0] & AUX_I2C_REPLY_MASK) {
576 case AUX_I2C_REPLY_ACK:
577 if (mode == MODE_I2C_READ) {
578 *read_byte = reply[1];
579 }
580 return reply_bytes - 1;
581 case AUX_I2C_REPLY_NACK:
582 DRM_DEBUG_KMS("aux_i2c nack\n");
583 return -EREMOTEIO;
584 case AUX_I2C_REPLY_DEFER:
585 DRM_DEBUG_KMS("aux_i2c defer\n");
586 udelay(100);
587 break;
588 default:
589 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
590 return -EREMOTEIO;
591 }
592 }
593
594 DRM_ERROR("too many retries, giving up\n");
595 return -EREMOTEIO;
596 }
597
598 static int
599 intel_dp_i2c_init(struct intel_dp *intel_dp,
600 struct intel_connector *intel_connector, const char *name)
601 {
602 DRM_DEBUG_KMS("i2c_init %s\n", name);
603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
606
607 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
610 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
614
615 return i2c_dp_aux_add_bus(&intel_dp->adapter);
616 }
617
618 static bool
619 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
620 struct drm_display_mode *adjusted_mode)
621 {
622 struct drm_device *dev = encoder->dev;
623 struct drm_i915_private *dev_priv = dev->dev_private;
624 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
625 int lane_count, clock;
626 int max_lane_count = intel_dp_max_lane_count(intel_dp);
627 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
628 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
629
630 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
631 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
632 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
633 mode, adjusted_mode);
634 /*
635 * the mode->clock is used to calculate the Data&Link M/N
636 * of the pipe. For the eDP the fixed clock should be used.
637 */
638 mode->clock = dev_priv->panel_fixed_mode->clock;
639 }
640
641 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
642 for (clock = 0; clock <= max_clock; clock++) {
643 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
644
645 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
646 <= link_avail) {
647 intel_dp->link_bw = bws[clock];
648 intel_dp->lane_count = lane_count;
649 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
650 DRM_DEBUG_KMS("Display port link bw %02x lane "
651 "count %d clock %d\n",
652 intel_dp->link_bw, intel_dp->lane_count,
653 adjusted_mode->clock);
654 return true;
655 }
656 }
657 }
658
659 if (is_edp(intel_dp)) {
660 /* okay we failed just pick the highest */
661 intel_dp->lane_count = max_lane_count;
662 intel_dp->link_bw = bws[max_clock];
663 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
664 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
665 "count %d clock %d\n",
666 intel_dp->link_bw, intel_dp->lane_count,
667 adjusted_mode->clock);
668
669 return true;
670 }
671
672 return false;
673 }
674
675 struct intel_dp_m_n {
676 uint32_t tu;
677 uint32_t gmch_m;
678 uint32_t gmch_n;
679 uint32_t link_m;
680 uint32_t link_n;
681 };
682
683 static void
684 intel_reduce_ratio(uint32_t *num, uint32_t *den)
685 {
686 while (*num > 0xffffff || *den > 0xffffff) {
687 *num >>= 1;
688 *den >>= 1;
689 }
690 }
691
692 static void
693 intel_dp_compute_m_n(int bpp,
694 int nlanes,
695 int pixel_clock,
696 int link_clock,
697 struct intel_dp_m_n *m_n)
698 {
699 m_n->tu = 64;
700 m_n->gmch_m = (pixel_clock * bpp) >> 3;
701 m_n->gmch_n = link_clock * nlanes;
702 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
703 m_n->link_m = pixel_clock;
704 m_n->link_n = link_clock;
705 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
706 }
707
708 void
709 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
710 struct drm_display_mode *adjusted_mode)
711 {
712 struct drm_device *dev = crtc->dev;
713 struct drm_mode_config *mode_config = &dev->mode_config;
714 struct drm_encoder *encoder;
715 struct drm_i915_private *dev_priv = dev->dev_private;
716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
717 int lane_count = 4;
718 struct intel_dp_m_n m_n;
719 int pipe = intel_crtc->pipe;
720
721 /*
722 * Find the lane count in the intel_encoder private
723 */
724 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
725 struct intel_dp *intel_dp;
726
727 if (encoder->crtc != crtc)
728 continue;
729
730 intel_dp = enc_to_intel_dp(encoder);
731 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
732 lane_count = intel_dp->lane_count;
733 break;
734 } else if (is_edp(intel_dp)) {
735 lane_count = dev_priv->edp.lanes;
736 break;
737 }
738 }
739
740 /*
741 * Compute the GMCH and Link ratios. The '3' here is
742 * the number of bytes_per_pixel post-LUT, which we always
743 * set up for 8-bits of R/G/B, or 3 bytes total.
744 */
745 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
746 mode->clock, adjusted_mode->clock, &m_n);
747
748 if (HAS_PCH_SPLIT(dev)) {
749 I915_WRITE(TRANSDATA_M1(pipe),
750 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
751 m_n.gmch_m);
752 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
753 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
754 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
755 } else {
756 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
757 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
758 m_n.gmch_m);
759 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
760 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
761 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
762 }
763 }
764
765 static void
766 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
767 struct drm_display_mode *adjusted_mode)
768 {
769 struct drm_device *dev = encoder->dev;
770 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
771 struct drm_crtc *crtc = intel_dp->base.base.crtc;
772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
773
774 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
775 intel_dp->DP |= intel_dp->color_range;
776
777 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
778 intel_dp->DP |= DP_SYNC_HS_HIGH;
779 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
780 intel_dp->DP |= DP_SYNC_VS_HIGH;
781
782 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
783 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
784 else
785 intel_dp->DP |= DP_LINK_TRAIN_OFF;
786
787 switch (intel_dp->lane_count) {
788 case 1:
789 intel_dp->DP |= DP_PORT_WIDTH_1;
790 break;
791 case 2:
792 intel_dp->DP |= DP_PORT_WIDTH_2;
793 break;
794 case 4:
795 intel_dp->DP |= DP_PORT_WIDTH_4;
796 break;
797 }
798 if (intel_dp->has_audio)
799 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
800
801 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
802 intel_dp->link_configuration[0] = intel_dp->link_bw;
803 intel_dp->link_configuration[1] = intel_dp->lane_count;
804 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
805
806 /*
807 * Check for DPCD version > 1.1 and enhanced framing support
808 */
809 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
810 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
811 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
812 intel_dp->DP |= DP_ENHANCED_FRAMING;
813 }
814
815 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
816 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
817 intel_dp->DP |= DP_PIPEB_SELECT;
818
819 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
820 /* don't miss out required setting for eDP */
821 intel_dp->DP |= DP_PLL_ENABLE;
822 if (adjusted_mode->clock < 200000)
823 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
824 else
825 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
826 }
827 }
828
829 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
830 {
831 struct drm_device *dev = intel_dp->base.base.dev;
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 u32 pp;
834
835 /*
836 * If the panel wasn't on, make sure there's not a currently
837 * active PP sequence before enabling AUX VDD.
838 */
839 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
840 msleep(dev_priv->panel_t3);
841
842 pp = I915_READ(PCH_PP_CONTROL);
843 pp &= ~PANEL_UNLOCK_MASK;
844 pp |= PANEL_UNLOCK_REGS;
845 pp |= EDP_FORCE_VDD;
846 I915_WRITE(PCH_PP_CONTROL, pp);
847 POSTING_READ(PCH_PP_CONTROL);
848 }
849
850 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
851 {
852 struct drm_device *dev = intel_dp->base.base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 u32 pp;
855
856 pp = I915_READ(PCH_PP_CONTROL);
857 pp &= ~PANEL_UNLOCK_MASK;
858 pp |= PANEL_UNLOCK_REGS;
859 pp &= ~EDP_FORCE_VDD;
860 I915_WRITE(PCH_PP_CONTROL, pp);
861 POSTING_READ(PCH_PP_CONTROL);
862
863 /* Make sure sequencer is idle before allowing subsequent activity */
864 msleep(dev_priv->panel_t12);
865 }
866
867 /* Returns true if the panel was already on when called */
868 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
869 {
870 struct drm_device *dev = intel_dp->base.base.dev;
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
873
874 if (I915_READ(PCH_PP_STATUS) & PP_ON)
875 return true;
876
877 pp = I915_READ(PCH_PP_CONTROL);
878 pp &= ~PANEL_UNLOCK_MASK;
879 pp |= PANEL_UNLOCK_REGS;
880
881 /* ILK workaround: disable reset around power sequence */
882 pp &= ~PANEL_POWER_RESET;
883 I915_WRITE(PCH_PP_CONTROL, pp);
884 POSTING_READ(PCH_PP_CONTROL);
885
886 pp |= POWER_TARGET_ON;
887 I915_WRITE(PCH_PP_CONTROL, pp);
888 POSTING_READ(PCH_PP_CONTROL);
889
890 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
891 5000))
892 DRM_ERROR("panel on wait timed out: 0x%08x\n",
893 I915_READ(PCH_PP_STATUS));
894
895 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
896 I915_WRITE(PCH_PP_CONTROL, pp);
897 POSTING_READ(PCH_PP_CONTROL);
898
899 return false;
900 }
901
902 static void ironlake_edp_panel_off (struct drm_device *dev)
903 {
904 struct drm_i915_private *dev_priv = dev->dev_private;
905 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
906 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
907
908 pp = I915_READ(PCH_PP_CONTROL);
909 pp &= ~PANEL_UNLOCK_MASK;
910 pp |= PANEL_UNLOCK_REGS;
911
912 /* ILK workaround: disable reset around power sequence */
913 pp &= ~PANEL_POWER_RESET;
914 I915_WRITE(PCH_PP_CONTROL, pp);
915 POSTING_READ(PCH_PP_CONTROL);
916
917 pp &= ~POWER_TARGET_ON;
918 I915_WRITE(PCH_PP_CONTROL, pp);
919 POSTING_READ(PCH_PP_CONTROL);
920
921 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
922 DRM_ERROR("panel off wait timed out: 0x%08x\n",
923 I915_READ(PCH_PP_STATUS));
924
925 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
926 I915_WRITE(PCH_PP_CONTROL, pp);
927 POSTING_READ(PCH_PP_CONTROL);
928 }
929
930 static void ironlake_edp_backlight_on (struct drm_device *dev)
931 {
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 pp;
934
935 DRM_DEBUG_KMS("\n");
936 /*
937 * If we enable the backlight right away following a panel power
938 * on, we may see slight flicker as the panel syncs with the eDP
939 * link. So delay a bit to make sure the image is solid before
940 * allowing it to appear.
941 */
942 msleep(300);
943 pp = I915_READ(PCH_PP_CONTROL);
944 pp &= ~PANEL_UNLOCK_MASK;
945 pp |= PANEL_UNLOCK_REGS;
946 pp |= EDP_BLC_ENABLE;
947 I915_WRITE(PCH_PP_CONTROL, pp);
948 }
949
950 static void ironlake_edp_backlight_off (struct drm_device *dev)
951 {
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 u32 pp;
954
955 DRM_DEBUG_KMS("\n");
956 pp = I915_READ(PCH_PP_CONTROL);
957 pp &= ~PANEL_UNLOCK_MASK;
958 pp |= PANEL_UNLOCK_REGS;
959 pp &= ~EDP_BLC_ENABLE;
960 I915_WRITE(PCH_PP_CONTROL, pp);
961 }
962
963 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
964 {
965 struct drm_device *dev = encoder->dev;
966 struct drm_i915_private *dev_priv = dev->dev_private;
967 u32 dpa_ctl;
968
969 DRM_DEBUG_KMS("\n");
970 dpa_ctl = I915_READ(DP_A);
971 dpa_ctl |= DP_PLL_ENABLE;
972 I915_WRITE(DP_A, dpa_ctl);
973 POSTING_READ(DP_A);
974 udelay(200);
975 }
976
977 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
978 {
979 struct drm_device *dev = encoder->dev;
980 struct drm_i915_private *dev_priv = dev->dev_private;
981 u32 dpa_ctl;
982
983 dpa_ctl = I915_READ(DP_A);
984 dpa_ctl &= ~DP_PLL_ENABLE;
985 I915_WRITE(DP_A, dpa_ctl);
986 POSTING_READ(DP_A);
987 udelay(200);
988 }
989
990 /* If the sink supports it, try to set the power state appropriately */
991 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
992 {
993 int ret, i;
994
995 /* Should have a valid DPCD by this point */
996 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
997 return;
998
999 if (mode != DRM_MODE_DPMS_ON) {
1000 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1001 DP_SET_POWER_D3);
1002 if (ret != 1)
1003 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1004 } else {
1005 /*
1006 * When turning on, we need to retry for 1ms to give the sink
1007 * time to wake up.
1008 */
1009 for (i = 0; i < 3; i++) {
1010 ret = intel_dp_aux_native_write_1(intel_dp,
1011 DP_SET_POWER,
1012 DP_SET_POWER_D0);
1013 if (ret == 1)
1014 break;
1015 msleep(1);
1016 }
1017 }
1018 }
1019
1020 static void intel_dp_prepare(struct drm_encoder *encoder)
1021 {
1022 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1023 struct drm_device *dev = encoder->dev;
1024
1025 /* Wake up the sink first */
1026 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1027
1028 if (is_edp(intel_dp)) {
1029 ironlake_edp_backlight_off(dev);
1030 ironlake_edp_panel_off(dev);
1031 if (!is_pch_edp(intel_dp))
1032 ironlake_edp_pll_on(encoder);
1033 else
1034 ironlake_edp_pll_off(encoder);
1035 }
1036 intel_dp_link_down(intel_dp);
1037 }
1038
1039 static void intel_dp_commit(struct drm_encoder *encoder)
1040 {
1041 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1042 struct drm_device *dev = encoder->dev;
1043
1044 if (is_edp(intel_dp))
1045 ironlake_edp_panel_vdd_on(intel_dp);
1046
1047 intel_dp_start_link_train(intel_dp);
1048
1049 if (is_edp(intel_dp)) {
1050 ironlake_edp_panel_on(intel_dp);
1051 ironlake_edp_panel_vdd_off(intel_dp);
1052 }
1053
1054 intel_dp_complete_link_train(intel_dp);
1055
1056 if (is_edp(intel_dp))
1057 ironlake_edp_backlight_on(dev);
1058
1059 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1060 }
1061
1062 static void
1063 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1064 {
1065 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1066 struct drm_device *dev = encoder->dev;
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1069
1070 if (mode != DRM_MODE_DPMS_ON) {
1071 if (is_edp(intel_dp))
1072 ironlake_edp_backlight_off(dev);
1073 intel_dp_sink_dpms(intel_dp, mode);
1074 intel_dp_link_down(intel_dp);
1075 if (is_edp(intel_dp))
1076 ironlake_edp_panel_off(dev);
1077 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1078 ironlake_edp_pll_off(encoder);
1079 } else {
1080 if (is_edp(intel_dp))
1081 ironlake_edp_panel_vdd_on(intel_dp);
1082 intel_dp_sink_dpms(intel_dp, mode);
1083 if (!(dp_reg & DP_PORT_EN)) {
1084 intel_dp_start_link_train(intel_dp);
1085 if (is_edp(intel_dp)) {
1086 ironlake_edp_panel_on(intel_dp);
1087 ironlake_edp_panel_vdd_off(intel_dp);
1088 }
1089 intel_dp_complete_link_train(intel_dp);
1090 }
1091 if (is_edp(intel_dp))
1092 ironlake_edp_backlight_on(dev);
1093 }
1094 intel_dp->dpms_mode = mode;
1095 }
1096
1097 /*
1098 * Native read with retry for link status and receiver capability reads for
1099 * cases where the sink may still be asleep.
1100 */
1101 static bool
1102 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1103 uint8_t *recv, int recv_bytes)
1104 {
1105 int ret, i;
1106
1107 /*
1108 * Sinks are *supposed* to come up within 1ms from an off state,
1109 * but we're also supposed to retry 3 times per the spec.
1110 */
1111 for (i = 0; i < 3; i++) {
1112 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1113 recv_bytes);
1114 if (ret == recv_bytes)
1115 return true;
1116 msleep(1);
1117 }
1118
1119 return false;
1120 }
1121
1122 /*
1123 * Fetch AUX CH registers 0x202 - 0x207 which contain
1124 * link status information
1125 */
1126 static bool
1127 intel_dp_get_link_status(struct intel_dp *intel_dp)
1128 {
1129 return intel_dp_aux_native_read_retry(intel_dp,
1130 DP_LANE0_1_STATUS,
1131 intel_dp->link_status,
1132 DP_LINK_STATUS_SIZE);
1133 }
1134
1135 static uint8_t
1136 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1137 int r)
1138 {
1139 return link_status[r - DP_LANE0_1_STATUS];
1140 }
1141
1142 static uint8_t
1143 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1144 int lane)
1145 {
1146 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1147 int s = ((lane & 1) ?
1148 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1149 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1150 uint8_t l = intel_dp_link_status(link_status, i);
1151
1152 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1153 }
1154
1155 static uint8_t
1156 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1157 int lane)
1158 {
1159 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1160 int s = ((lane & 1) ?
1161 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1162 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1163 uint8_t l = intel_dp_link_status(link_status, i);
1164
1165 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1166 }
1167
1168
1169 #if 0
1170 static char *voltage_names[] = {
1171 "0.4V", "0.6V", "0.8V", "1.2V"
1172 };
1173 static char *pre_emph_names[] = {
1174 "0dB", "3.5dB", "6dB", "9.5dB"
1175 };
1176 static char *link_train_names[] = {
1177 "pattern 1", "pattern 2", "idle", "off"
1178 };
1179 #endif
1180
1181 /*
1182 * These are source-specific values; current Intel hardware supports
1183 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1184 */
1185 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1186
1187 static uint8_t
1188 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1189 {
1190 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1191 case DP_TRAIN_VOLTAGE_SWING_400:
1192 return DP_TRAIN_PRE_EMPHASIS_6;
1193 case DP_TRAIN_VOLTAGE_SWING_600:
1194 return DP_TRAIN_PRE_EMPHASIS_6;
1195 case DP_TRAIN_VOLTAGE_SWING_800:
1196 return DP_TRAIN_PRE_EMPHASIS_3_5;
1197 case DP_TRAIN_VOLTAGE_SWING_1200:
1198 default:
1199 return DP_TRAIN_PRE_EMPHASIS_0;
1200 }
1201 }
1202
1203 static void
1204 intel_get_adjust_train(struct intel_dp *intel_dp)
1205 {
1206 uint8_t v = 0;
1207 uint8_t p = 0;
1208 int lane;
1209
1210 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1211 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1212 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1213
1214 if (this_v > v)
1215 v = this_v;
1216 if (this_p > p)
1217 p = this_p;
1218 }
1219
1220 if (v >= I830_DP_VOLTAGE_MAX)
1221 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1222
1223 if (p >= intel_dp_pre_emphasis_max(v))
1224 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1225
1226 for (lane = 0; lane < 4; lane++)
1227 intel_dp->train_set[lane] = v | p;
1228 }
1229
1230 static uint32_t
1231 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1232 {
1233 uint32_t signal_levels = 0;
1234
1235 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1236 case DP_TRAIN_VOLTAGE_SWING_400:
1237 default:
1238 signal_levels |= DP_VOLTAGE_0_4;
1239 break;
1240 case DP_TRAIN_VOLTAGE_SWING_600:
1241 signal_levels |= DP_VOLTAGE_0_6;
1242 break;
1243 case DP_TRAIN_VOLTAGE_SWING_800:
1244 signal_levels |= DP_VOLTAGE_0_8;
1245 break;
1246 case DP_TRAIN_VOLTAGE_SWING_1200:
1247 signal_levels |= DP_VOLTAGE_1_2;
1248 break;
1249 }
1250 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1251 case DP_TRAIN_PRE_EMPHASIS_0:
1252 default:
1253 signal_levels |= DP_PRE_EMPHASIS_0;
1254 break;
1255 case DP_TRAIN_PRE_EMPHASIS_3_5:
1256 signal_levels |= DP_PRE_EMPHASIS_3_5;
1257 break;
1258 case DP_TRAIN_PRE_EMPHASIS_6:
1259 signal_levels |= DP_PRE_EMPHASIS_6;
1260 break;
1261 case DP_TRAIN_PRE_EMPHASIS_9_5:
1262 signal_levels |= DP_PRE_EMPHASIS_9_5;
1263 break;
1264 }
1265 return signal_levels;
1266 }
1267
1268 /* Gen6's DP voltage swing and pre-emphasis control */
1269 static uint32_t
1270 intel_gen6_edp_signal_levels(uint8_t train_set)
1271 {
1272 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1273 DP_TRAIN_PRE_EMPHASIS_MASK);
1274 switch (signal_levels) {
1275 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1276 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1277 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1278 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1279 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1280 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1281 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1282 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1283 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1284 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1285 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1286 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1287 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1288 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1289 default:
1290 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1291 "0x%x\n", signal_levels);
1292 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1293 }
1294 }
1295
1296 static uint8_t
1297 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1298 int lane)
1299 {
1300 int i = DP_LANE0_1_STATUS + (lane >> 1);
1301 int s = (lane & 1) * 4;
1302 uint8_t l = intel_dp_link_status(link_status, i);
1303
1304 return (l >> s) & 0xf;
1305 }
1306
1307 /* Check for clock recovery is done on all channels */
1308 static bool
1309 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1310 {
1311 int lane;
1312 uint8_t lane_status;
1313
1314 for (lane = 0; lane < lane_count; lane++) {
1315 lane_status = intel_get_lane_status(link_status, lane);
1316 if ((lane_status & DP_LANE_CR_DONE) == 0)
1317 return false;
1318 }
1319 return true;
1320 }
1321
1322 /* Check to see if channel eq is done on all channels */
1323 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1324 DP_LANE_CHANNEL_EQ_DONE|\
1325 DP_LANE_SYMBOL_LOCKED)
1326 static bool
1327 intel_channel_eq_ok(struct intel_dp *intel_dp)
1328 {
1329 uint8_t lane_align;
1330 uint8_t lane_status;
1331 int lane;
1332
1333 lane_align = intel_dp_link_status(intel_dp->link_status,
1334 DP_LANE_ALIGN_STATUS_UPDATED);
1335 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1336 return false;
1337 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1338 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1339 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1340 return false;
1341 }
1342 return true;
1343 }
1344
1345 static bool
1346 intel_dp_set_link_train(struct intel_dp *intel_dp,
1347 uint32_t dp_reg_value,
1348 uint8_t dp_train_pat)
1349 {
1350 struct drm_device *dev = intel_dp->base.base.dev;
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 int ret;
1353
1354 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1355 POSTING_READ(intel_dp->output_reg);
1356
1357 intel_dp_aux_native_write_1(intel_dp,
1358 DP_TRAINING_PATTERN_SET,
1359 dp_train_pat);
1360
1361 ret = intel_dp_aux_native_write(intel_dp,
1362 DP_TRAINING_LANE0_SET,
1363 intel_dp->train_set, 4);
1364 if (ret != 4)
1365 return false;
1366
1367 return true;
1368 }
1369
1370 /* Enable corresponding port and start training pattern 1 */
1371 static void
1372 intel_dp_start_link_train(struct intel_dp *intel_dp)
1373 {
1374 struct drm_device *dev = intel_dp->base.base.dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1377 int i;
1378 uint8_t voltage;
1379 bool clock_recovery = false;
1380 int tries;
1381 u32 reg;
1382 uint32_t DP = intel_dp->DP;
1383
1384 /*
1385 * On CPT we have to enable the port in training pattern 1, which
1386 * will happen below in intel_dp_set_link_train. Otherwise, enable
1387 * the port and wait for it to become active.
1388 */
1389 if (!HAS_PCH_CPT(dev)) {
1390 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1391 POSTING_READ(intel_dp->output_reg);
1392 intel_wait_for_vblank(dev, intel_crtc->pipe);
1393 }
1394
1395 /* Write the link configuration data */
1396 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1397 intel_dp->link_configuration,
1398 DP_LINK_CONFIGURATION_SIZE);
1399
1400 DP |= DP_PORT_EN;
1401 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1402 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1403 else
1404 DP &= ~DP_LINK_TRAIN_MASK;
1405 memset(intel_dp->train_set, 0, 4);
1406 voltage = 0xff;
1407 tries = 0;
1408 clock_recovery = false;
1409 for (;;) {
1410 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1411 uint32_t signal_levels;
1412 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1413 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1414 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1415 } else {
1416 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1417 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1418 }
1419
1420 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1421 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1422 else
1423 reg = DP | DP_LINK_TRAIN_PAT_1;
1424
1425 if (!intel_dp_set_link_train(intel_dp, reg,
1426 DP_TRAINING_PATTERN_1 |
1427 DP_LINK_SCRAMBLING_DISABLE))
1428 break;
1429 /* Set training pattern 1 */
1430
1431 udelay(100);
1432 if (!intel_dp_get_link_status(intel_dp))
1433 break;
1434
1435 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1436 clock_recovery = true;
1437 break;
1438 }
1439
1440 /* Check to see if we've tried the max voltage */
1441 for (i = 0; i < intel_dp->lane_count; i++)
1442 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1443 break;
1444 if (i == intel_dp->lane_count)
1445 break;
1446
1447 /* Check to see if we've tried the same voltage 5 times */
1448 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1449 ++tries;
1450 if (tries == 5)
1451 break;
1452 } else
1453 tries = 0;
1454 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1455
1456 /* Compute new intel_dp->train_set as requested by target */
1457 intel_get_adjust_train(intel_dp);
1458 }
1459
1460 intel_dp->DP = DP;
1461 }
1462
1463 static void
1464 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1465 {
1466 struct drm_device *dev = intel_dp->base.base.dev;
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468 bool channel_eq = false;
1469 int tries, cr_tries;
1470 u32 reg;
1471 uint32_t DP = intel_dp->DP;
1472
1473 /* channel equalization */
1474 tries = 0;
1475 cr_tries = 0;
1476 channel_eq = false;
1477 for (;;) {
1478 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1479 uint32_t signal_levels;
1480
1481 if (cr_tries > 5) {
1482 DRM_ERROR("failed to train DP, aborting\n");
1483 intel_dp_link_down(intel_dp);
1484 break;
1485 }
1486
1487 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1488 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1489 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1490 } else {
1491 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1492 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1493 }
1494
1495 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1496 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1497 else
1498 reg = DP | DP_LINK_TRAIN_PAT_2;
1499
1500 /* channel eq pattern */
1501 if (!intel_dp_set_link_train(intel_dp, reg,
1502 DP_TRAINING_PATTERN_2 |
1503 DP_LINK_SCRAMBLING_DISABLE))
1504 break;
1505
1506 udelay(400);
1507 if (!intel_dp_get_link_status(intel_dp))
1508 break;
1509
1510 /* Make sure clock is still ok */
1511 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1512 intel_dp_start_link_train(intel_dp);
1513 cr_tries++;
1514 continue;
1515 }
1516
1517 if (intel_channel_eq_ok(intel_dp)) {
1518 channel_eq = true;
1519 break;
1520 }
1521
1522 /* Try 5 times, then try clock recovery if that fails */
1523 if (tries > 5) {
1524 intel_dp_link_down(intel_dp);
1525 intel_dp_start_link_train(intel_dp);
1526 tries = 0;
1527 cr_tries++;
1528 continue;
1529 }
1530
1531 /* Compute new intel_dp->train_set as requested by target */
1532 intel_get_adjust_train(intel_dp);
1533 ++tries;
1534 }
1535
1536 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1537 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1538 else
1539 reg = DP | DP_LINK_TRAIN_OFF;
1540
1541 I915_WRITE(intel_dp->output_reg, reg);
1542 POSTING_READ(intel_dp->output_reg);
1543 intel_dp_aux_native_write_1(intel_dp,
1544 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1545 }
1546
1547 static void
1548 intel_dp_link_down(struct intel_dp *intel_dp)
1549 {
1550 struct drm_device *dev = intel_dp->base.base.dev;
1551 struct drm_i915_private *dev_priv = dev->dev_private;
1552 uint32_t DP = intel_dp->DP;
1553
1554 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1555 return;
1556
1557 DRM_DEBUG_KMS("\n");
1558
1559 if (is_edp(intel_dp)) {
1560 DP &= ~DP_PLL_ENABLE;
1561 I915_WRITE(intel_dp->output_reg, DP);
1562 POSTING_READ(intel_dp->output_reg);
1563 udelay(100);
1564 }
1565
1566 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1567 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1568 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1569 } else {
1570 DP &= ~DP_LINK_TRAIN_MASK;
1571 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1572 }
1573 POSTING_READ(intel_dp->output_reg);
1574
1575 msleep(17);
1576
1577 if (is_edp(intel_dp))
1578 DP |= DP_LINK_TRAIN_OFF;
1579
1580 if (!HAS_PCH_CPT(dev) &&
1581 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1582 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1583
1584 /* Hardware workaround: leaving our transcoder select
1585 * set to transcoder B while it's off will prevent the
1586 * corresponding HDMI output on transcoder A.
1587 *
1588 * Combine this with another hardware workaround:
1589 * transcoder select bit can only be cleared while the
1590 * port is enabled.
1591 */
1592 DP &= ~DP_PIPEB_SELECT;
1593 I915_WRITE(intel_dp->output_reg, DP);
1594
1595 /* Changes to enable or select take place the vblank
1596 * after being written.
1597 */
1598 if (crtc == NULL) {
1599 /* We can arrive here never having been attached
1600 * to a CRTC, for instance, due to inheriting
1601 * random state from the BIOS.
1602 *
1603 * If the pipe is not running, play safe and
1604 * wait for the clocks to stabilise before
1605 * continuing.
1606 */
1607 POSTING_READ(intel_dp->output_reg);
1608 msleep(50);
1609 } else
1610 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1611 }
1612
1613 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1614 POSTING_READ(intel_dp->output_reg);
1615 }
1616
1617 static bool
1618 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1619 {
1620 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1621 sizeof (intel_dp->dpcd)) &&
1622 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1623 return true;
1624 }
1625
1626 return false;
1627 }
1628
1629 /*
1630 * According to DP spec
1631 * 5.1.2:
1632 * 1. Read DPCD
1633 * 2. Configure link according to Receiver Capabilities
1634 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1635 * 4. Check link status on receipt of hot-plug interrupt
1636 */
1637
1638 static void
1639 intel_dp_check_link_status(struct intel_dp *intel_dp)
1640 {
1641 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1642 return;
1643
1644 if (!intel_dp->base.base.crtc)
1645 return;
1646
1647 /* Try to read receiver status if the link appears to be up */
1648 if (!intel_dp_get_link_status(intel_dp)) {
1649 intel_dp_link_down(intel_dp);
1650 return;
1651 }
1652
1653 /* Now read the DPCD to see if it's actually running */
1654 if (!intel_dp_get_dpcd(intel_dp)) {
1655 intel_dp_link_down(intel_dp);
1656 return;
1657 }
1658
1659 if (!intel_channel_eq_ok(intel_dp)) {
1660 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1661 drm_get_encoder_name(&intel_dp->base.base));
1662 intel_dp_start_link_train(intel_dp);
1663 intel_dp_complete_link_train(intel_dp);
1664 }
1665 }
1666
1667 static enum drm_connector_status
1668 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1669 {
1670 if (intel_dp_get_dpcd(intel_dp))
1671 return connector_status_connected;
1672 return connector_status_disconnected;
1673 }
1674
1675 static enum drm_connector_status
1676 ironlake_dp_detect(struct intel_dp *intel_dp)
1677 {
1678 enum drm_connector_status status;
1679
1680 /* Can't disconnect eDP, but you can close the lid... */
1681 if (is_edp(intel_dp)) {
1682 status = intel_panel_detect(intel_dp->base.base.dev);
1683 if (status == connector_status_unknown)
1684 status = connector_status_connected;
1685 return status;
1686 }
1687
1688 return intel_dp_detect_dpcd(intel_dp);
1689 }
1690
1691 static enum drm_connector_status
1692 g4x_dp_detect(struct intel_dp *intel_dp)
1693 {
1694 struct drm_device *dev = intel_dp->base.base.dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 uint32_t temp, bit;
1697
1698 switch (intel_dp->output_reg) {
1699 case DP_B:
1700 bit = DPB_HOTPLUG_INT_STATUS;
1701 break;
1702 case DP_C:
1703 bit = DPC_HOTPLUG_INT_STATUS;
1704 break;
1705 case DP_D:
1706 bit = DPD_HOTPLUG_INT_STATUS;
1707 break;
1708 default:
1709 return connector_status_unknown;
1710 }
1711
1712 temp = I915_READ(PORT_HOTPLUG_STAT);
1713
1714 if ((temp & bit) == 0)
1715 return connector_status_disconnected;
1716
1717 return intel_dp_detect_dpcd(intel_dp);
1718 }
1719
1720 /**
1721 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1722 *
1723 * \return true if DP port is connected.
1724 * \return false if DP port is disconnected.
1725 */
1726 static enum drm_connector_status
1727 intel_dp_detect(struct drm_connector *connector, bool force)
1728 {
1729 struct intel_dp *intel_dp = intel_attached_dp(connector);
1730 struct drm_device *dev = intel_dp->base.base.dev;
1731 enum drm_connector_status status;
1732 struct edid *edid = NULL;
1733
1734 intel_dp->has_audio = false;
1735
1736 if (HAS_PCH_SPLIT(dev))
1737 status = ironlake_dp_detect(intel_dp);
1738 else
1739 status = g4x_dp_detect(intel_dp);
1740
1741 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1742 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1743 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1744 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1745
1746 if (status != connector_status_connected)
1747 return status;
1748
1749 if (intel_dp->force_audio) {
1750 intel_dp->has_audio = intel_dp->force_audio > 0;
1751 } else {
1752 edid = drm_get_edid(connector, &intel_dp->adapter);
1753 if (edid) {
1754 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1755 connector->display_info.raw_edid = NULL;
1756 kfree(edid);
1757 }
1758 }
1759
1760 return connector_status_connected;
1761 }
1762
1763 static int intel_dp_get_modes(struct drm_connector *connector)
1764 {
1765 struct intel_dp *intel_dp = intel_attached_dp(connector);
1766 struct drm_device *dev = intel_dp->base.base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 int ret;
1769
1770 /* We should parse the EDID data and find out if it has an audio sink
1771 */
1772
1773 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1774 if (ret) {
1775 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1776 struct drm_display_mode *newmode;
1777 list_for_each_entry(newmode, &connector->probed_modes,
1778 head) {
1779 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1780 dev_priv->panel_fixed_mode =
1781 drm_mode_duplicate(dev, newmode);
1782 break;
1783 }
1784 }
1785 }
1786
1787 return ret;
1788 }
1789
1790 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1791 if (is_edp(intel_dp)) {
1792 /* initialize panel mode from VBT if available for eDP */
1793 if (dev_priv->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1794 dev_priv->panel_fixed_mode =
1795 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1796 if (dev_priv->panel_fixed_mode) {
1797 dev_priv->panel_fixed_mode->type |=
1798 DRM_MODE_TYPE_PREFERRED;
1799 }
1800 }
1801 if (dev_priv->panel_fixed_mode) {
1802 struct drm_display_mode *mode;
1803 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1804 drm_mode_probed_add(connector, mode);
1805 return 1;
1806 }
1807 }
1808 return 0;
1809 }
1810
1811 static bool
1812 intel_dp_detect_audio(struct drm_connector *connector)
1813 {
1814 struct intel_dp *intel_dp = intel_attached_dp(connector);
1815 struct edid *edid;
1816 bool has_audio = false;
1817
1818 edid = drm_get_edid(connector, &intel_dp->adapter);
1819 if (edid) {
1820 has_audio = drm_detect_monitor_audio(edid);
1821
1822 connector->display_info.raw_edid = NULL;
1823 kfree(edid);
1824 }
1825
1826 return has_audio;
1827 }
1828
1829 static int
1830 intel_dp_set_property(struct drm_connector *connector,
1831 struct drm_property *property,
1832 uint64_t val)
1833 {
1834 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1835 struct intel_dp *intel_dp = intel_attached_dp(connector);
1836 int ret;
1837
1838 ret = drm_connector_property_set_value(connector, property, val);
1839 if (ret)
1840 return ret;
1841
1842 if (property == dev_priv->force_audio_property) {
1843 int i = val;
1844 bool has_audio;
1845
1846 if (i == intel_dp->force_audio)
1847 return 0;
1848
1849 intel_dp->force_audio = i;
1850
1851 if (i == 0)
1852 has_audio = intel_dp_detect_audio(connector);
1853 else
1854 has_audio = i > 0;
1855
1856 if (has_audio == intel_dp->has_audio)
1857 return 0;
1858
1859 intel_dp->has_audio = has_audio;
1860 goto done;
1861 }
1862
1863 if (property == dev_priv->broadcast_rgb_property) {
1864 if (val == !!intel_dp->color_range)
1865 return 0;
1866
1867 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1868 goto done;
1869 }
1870
1871 return -EINVAL;
1872
1873 done:
1874 if (intel_dp->base.base.crtc) {
1875 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1876 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1877 crtc->x, crtc->y,
1878 crtc->fb);
1879 }
1880
1881 return 0;
1882 }
1883
1884 static void
1885 intel_dp_destroy (struct drm_connector *connector)
1886 {
1887 struct drm_device *dev = connector->dev;
1888
1889 if (intel_dpd_is_edp(dev))
1890 intel_panel_destroy_backlight(dev);
1891
1892 drm_sysfs_connector_remove(connector);
1893 drm_connector_cleanup(connector);
1894 kfree(connector);
1895 }
1896
1897 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1898 {
1899 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1900
1901 i2c_del_adapter(&intel_dp->adapter);
1902 drm_encoder_cleanup(encoder);
1903 kfree(intel_dp);
1904 }
1905
1906 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1907 .dpms = intel_dp_dpms,
1908 .mode_fixup = intel_dp_mode_fixup,
1909 .prepare = intel_dp_prepare,
1910 .mode_set = intel_dp_mode_set,
1911 .commit = intel_dp_commit,
1912 };
1913
1914 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1915 .dpms = drm_helper_connector_dpms,
1916 .detect = intel_dp_detect,
1917 .fill_modes = drm_helper_probe_single_connector_modes,
1918 .set_property = intel_dp_set_property,
1919 .destroy = intel_dp_destroy,
1920 };
1921
1922 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1923 .get_modes = intel_dp_get_modes,
1924 .mode_valid = intel_dp_mode_valid,
1925 .best_encoder = intel_best_encoder,
1926 };
1927
1928 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1929 .destroy = intel_dp_encoder_destroy,
1930 };
1931
1932 static void
1933 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1934 {
1935 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1936
1937 intel_dp_check_link_status(intel_dp);
1938 }
1939
1940 /* Return which DP Port should be selected for Transcoder DP control */
1941 int
1942 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1943 {
1944 struct drm_device *dev = crtc->dev;
1945 struct drm_mode_config *mode_config = &dev->mode_config;
1946 struct drm_encoder *encoder;
1947
1948 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1949 struct intel_dp *intel_dp;
1950
1951 if (encoder->crtc != crtc)
1952 continue;
1953
1954 intel_dp = enc_to_intel_dp(encoder);
1955 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1956 return intel_dp->output_reg;
1957 }
1958
1959 return -1;
1960 }
1961
1962 /* check the VBT to see whether the eDP is on DP-D port */
1963 bool intel_dpd_is_edp(struct drm_device *dev)
1964 {
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 struct child_device_config *p_child;
1967 int i;
1968
1969 if (!dev_priv->child_dev_num)
1970 return false;
1971
1972 for (i = 0; i < dev_priv->child_dev_num; i++) {
1973 p_child = dev_priv->child_dev + i;
1974
1975 if (p_child->dvo_port == PORT_IDPD &&
1976 p_child->device_type == DEVICE_TYPE_eDP)
1977 return true;
1978 }
1979 return false;
1980 }
1981
1982 static void
1983 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1984 {
1985 intel_attach_force_audio_property(connector);
1986 intel_attach_broadcast_rgb_property(connector);
1987 }
1988
1989 void
1990 intel_dp_init(struct drm_device *dev, int output_reg)
1991 {
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1993 struct drm_connector *connector;
1994 struct intel_dp *intel_dp;
1995 struct intel_encoder *intel_encoder;
1996 struct intel_connector *intel_connector;
1997 const char *name = NULL;
1998 int type;
1999
2000 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2001 if (!intel_dp)
2002 return;
2003
2004 intel_dp->output_reg = output_reg;
2005 intel_dp->dpms_mode = -1;
2006
2007 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2008 if (!intel_connector) {
2009 kfree(intel_dp);
2010 return;
2011 }
2012 intel_encoder = &intel_dp->base;
2013
2014 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2015 if (intel_dpd_is_edp(dev))
2016 intel_dp->is_pch_edp = true;
2017
2018 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2019 type = DRM_MODE_CONNECTOR_eDP;
2020 intel_encoder->type = INTEL_OUTPUT_EDP;
2021 } else {
2022 type = DRM_MODE_CONNECTOR_DisplayPort;
2023 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2024 }
2025
2026 connector = &intel_connector->base;
2027 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2028 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2029
2030 connector->polled = DRM_CONNECTOR_POLL_HPD;
2031
2032 if (output_reg == DP_B || output_reg == PCH_DP_B)
2033 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2034 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2035 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2036 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2037 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2038
2039 if (is_edp(intel_dp))
2040 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2041
2042 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2043 connector->interlace_allowed = true;
2044 connector->doublescan_allowed = 0;
2045
2046 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2047 DRM_MODE_ENCODER_TMDS);
2048 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2049
2050 intel_connector_attach_encoder(intel_connector, intel_encoder);
2051 drm_sysfs_connector_add(connector);
2052
2053 /* Set up the DDC bus. */
2054 switch (output_reg) {
2055 case DP_A:
2056 name = "DPDDC-A";
2057 break;
2058 case DP_B:
2059 case PCH_DP_B:
2060 dev_priv->hotplug_supported_mask |=
2061 HDMIB_HOTPLUG_INT_STATUS;
2062 name = "DPDDC-B";
2063 break;
2064 case DP_C:
2065 case PCH_DP_C:
2066 dev_priv->hotplug_supported_mask |=
2067 HDMIC_HOTPLUG_INT_STATUS;
2068 name = "DPDDC-C";
2069 break;
2070 case DP_D:
2071 case PCH_DP_D:
2072 dev_priv->hotplug_supported_mask |=
2073 HDMID_HOTPLUG_INT_STATUS;
2074 name = "DPDDC-D";
2075 break;
2076 }
2077
2078 intel_dp_i2c_init(intel_dp, intel_connector, name);
2079
2080 /* Cache some DPCD data in the eDP case */
2081 if (is_edp(intel_dp)) {
2082 bool ret;
2083 u32 pp_on, pp_div;
2084
2085 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2086 pp_div = I915_READ(PCH_PP_DIVISOR);
2087
2088 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2089 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2090 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2091 dev_priv->panel_t12 = pp_div & 0xf;
2092 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2093
2094 ironlake_edp_panel_vdd_on(intel_dp);
2095 ret = intel_dp_get_dpcd(intel_dp);
2096 ironlake_edp_panel_vdd_off(intel_dp);
2097 if (ret) {
2098 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2099 dev_priv->no_aux_handshake =
2100 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2101 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2102 } else {
2103 /* if this fails, presume the device is a ghost */
2104 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2105 intel_dp_encoder_destroy(&intel_dp->base.base);
2106 intel_dp_destroy(&intel_connector->base);
2107 return;
2108 }
2109 }
2110
2111 intel_encoder->hot_plug = intel_dp_hot_plug;
2112
2113 if (is_edp(intel_dp)) {
2114 dev_priv->int_edp_connector = connector;
2115 intel_panel_setup_backlight(dev);
2116 }
2117
2118 intel_dp_add_properties(intel_dp, connector);
2119
2120 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2121 * 0xd. Failure to do so will result in spurious interrupts being
2122 * generated on the port when a cable is not attached.
2123 */
2124 if (IS_G4X(dev) && !IS_GM45(dev)) {
2125 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2126 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2127 }
2128 }
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