2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
194 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
196 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
197 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
198 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
199 int max_dotclk
= dev_priv
->max_dotclk_freq
;
202 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
204 if (type
!= DP_DS_PORT_TYPE_VGA
)
207 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
208 intel_dp
->downstream_ports
);
210 if (ds_max_dotclk
!= 0)
211 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
216 static enum drm_mode_status
217 intel_dp_mode_valid(struct drm_connector
*connector
,
218 struct drm_display_mode
*mode
)
220 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
221 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
222 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
223 int target_clock
= mode
->clock
;
224 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
227 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
229 if (is_edp(intel_dp
) && fixed_mode
) {
230 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
233 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
236 target_clock
= fixed_mode
->clock
;
239 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
240 max_lanes
= intel_dp_max_lane_count(intel_dp
);
242 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
243 mode_rate
= intel_dp_link_required(target_clock
, 18);
245 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
246 return MODE_CLOCK_HIGH
;
248 if (mode
->clock
< 10000)
249 return MODE_CLOCK_LOW
;
251 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
252 return MODE_H_ILLEGAL
;
257 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
264 for (i
= 0; i
< src_bytes
; i
++)
265 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
269 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
274 for (i
= 0; i
< dst_bytes
; i
++)
275 dst
[i
] = src
>> ((3-i
) * 8);
279 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
280 struct intel_dp
*intel_dp
);
282 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
283 struct intel_dp
*intel_dp
);
285 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
287 static void pps_lock(struct intel_dp
*intel_dp
)
289 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
290 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
291 struct drm_device
*dev
= encoder
->base
.dev
;
292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
293 enum intel_display_power_domain power_domain
;
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
299 power_domain
= intel_display_port_aux_power_domain(encoder
);
300 intel_display_power_get(dev_priv
, power_domain
);
302 mutex_lock(&dev_priv
->pps_mutex
);
305 static void pps_unlock(struct intel_dp
*intel_dp
)
307 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
308 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
309 struct drm_device
*dev
= encoder
->base
.dev
;
310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
311 enum intel_display_power_domain power_domain
;
313 mutex_unlock(&dev_priv
->pps_mutex
);
315 power_domain
= intel_display_port_aux_power_domain(encoder
);
316 intel_display_power_put(dev_priv
, power_domain
);
320 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
323 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
324 struct drm_i915_private
*dev_priv
= to_i915(dev
);
325 enum pipe pipe
= intel_dp
->pps_pipe
;
326 bool pll_enabled
, release_cl_override
= false;
327 enum dpio_phy phy
= DPIO_PHY(pipe
);
328 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
331 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe
), port_name(intel_dig_port
->port
));
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
342 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
343 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
344 DP
|= DP_PORT_WIDTH(1);
345 DP
|= DP_LINK_TRAIN_PAT_1
;
347 if (IS_CHERRYVIEW(dev
))
348 DP
|= DP_PIPE_SELECT_CHV(pipe
);
349 else if (pipe
== PIPE_B
)
350 DP
|= DP_PIPEB_SELECT
;
352 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
359 release_cl_override
= IS_CHERRYVIEW(dev
) &&
360 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
362 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
363 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
376 I915_WRITE(intel_dp
->output_reg
, DP
);
377 POSTING_READ(intel_dp
->output_reg
);
379 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
386 vlv_force_pll_off(dev
, pipe
);
388 if (release_cl_override
)
389 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
394 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
396 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
397 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
398 struct drm_i915_private
*dev_priv
= to_i915(dev
);
399 struct intel_encoder
*encoder
;
400 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
403 lockdep_assert_held(&dev_priv
->pps_mutex
);
405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp
));
408 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
409 return intel_dp
->pps_pipe
;
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
415 for_each_intel_encoder(dev
, encoder
) {
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
457 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
459 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
460 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
461 struct drm_i915_private
*dev_priv
= to_i915(dev
);
463 lockdep_assert_held(&dev_priv
->pps_mutex
);
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp
));
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
473 if (!intel_dp
->pps_reset
)
476 intel_dp
->pps_reset
= false;
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
482 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
487 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
490 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
493 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
499 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
502 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
509 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
511 vlv_pipe_check pipe_check
)
515 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
516 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
517 PANEL_PORT_SELECT_MASK
;
519 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
522 if (!pipe_check(dev_priv
, pipe
))
532 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
534 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
535 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
536 struct drm_i915_private
*dev_priv
= to_i915(dev
);
537 enum port port
= intel_dig_port
->port
;
539 lockdep_assert_held(&dev_priv
->pps_mutex
);
541 /* try to find a pipe with this port selected */
542 /* first pick one where the panel is on */
543 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
547 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
548 vlv_pipe_has_vdd_on
);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
551 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
564 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
565 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
568 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
570 struct drm_device
*dev
= &dev_priv
->drm
;
571 struct intel_encoder
*encoder
;
573 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
587 for_each_intel_encoder(dev
, encoder
) {
588 struct intel_dp
*intel_dp
;
590 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
593 intel_dp
= enc_to_intel_dp(&encoder
->base
);
595 intel_dp
->pps_reset
= true;
597 intel_dp
->pps_pipe
= INVALID_PIPE
;
601 struct pps_registers
{
609 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
610 struct intel_dp
*intel_dp
,
611 struct pps_registers
*regs
)
615 memset(regs
, 0, sizeof(*regs
));
617 if (IS_BROXTON(dev_priv
))
618 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
619 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
620 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
622 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
623 regs
->pp_stat
= PP_STATUS(pps_idx
);
624 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
625 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
626 if (!IS_BROXTON(dev_priv
))
627 regs
->pp_div
= PP_DIVISOR(pps_idx
);
631 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
633 struct pps_registers regs
;
635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
642 _pp_stat_reg(struct intel_dp
*intel_dp
)
644 struct pps_registers regs
;
646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
657 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
659 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
660 struct drm_i915_private
*dev_priv
= to_i915(dev
);
662 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
667 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
668 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
669 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
672 pp_ctrl_reg
= PP_CONTROL(pipe
);
673 pp_div_reg
= PP_DIVISOR(pipe
);
674 pp_div
= I915_READ(pp_div_reg
);
675 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
679 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
680 msleep(intel_dp
->panel_power_cycle_delay
);
683 pps_unlock(intel_dp
);
688 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
690 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
691 struct drm_i915_private
*dev_priv
= to_i915(dev
);
693 lockdep_assert_held(&dev_priv
->pps_mutex
);
695 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
696 intel_dp
->pps_pipe
== INVALID_PIPE
)
699 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
702 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
704 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
705 struct drm_i915_private
*dev_priv
= to_i915(dev
);
707 lockdep_assert_held(&dev_priv
->pps_mutex
);
709 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
710 intel_dp
->pps_pipe
== INVALID_PIPE
)
713 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
717 intel_dp_check_edp(struct intel_dp
*intel_dp
)
719 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
722 if (!is_edp(intel_dp
))
725 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
728 I915_READ(_pp_stat_reg(intel_dp
)),
729 I915_READ(_pp_ctrl_reg(intel_dp
)));
734 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
736 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
737 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
739 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
743 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
745 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
746 msecs_to_jiffies_timeout(10));
748 done
= wait_for(C
, 10) == 0;
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
757 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
759 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
760 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
766 * The clock divider is based off the hrawclk, and would like to run at
767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
769 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
772 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
774 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
775 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
785 if (intel_dig_port
->port
== PORT_A
)
786 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
788 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
791 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
793 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
794 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
796 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
797 /* Workaround for non-ULT HSW */
805 return ilk_get_aux_clock_divider(intel_dp
, index
);
808 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
815 return index
? 0 : 1;
818 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
821 uint32_t aux_clock_divider
)
823 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
824 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
825 uint32_t precharge
, timeout
;
832 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
833 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
835 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
837 return DP_AUX_CH_CTL_SEND_BUSY
|
839 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
840 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
842 DP_AUX_CH_CTL_RECEIVE_ERROR
|
843 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
844 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
845 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
848 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
853 return DP_AUX_CH_CTL_SEND_BUSY
|
855 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
856 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
857 DP_AUX_CH_CTL_TIME_OUT_1600us
|
858 DP_AUX_CH_CTL_RECEIVE_ERROR
|
859 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
860 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
861 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
865 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
866 const uint8_t *send
, int send_bytes
,
867 uint8_t *recv
, int recv_size
)
869 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
870 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
871 struct drm_i915_private
*dev_priv
= to_i915(dev
);
872 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
873 uint32_t aux_clock_divider
;
874 int i
, ret
, recv_bytes
;
877 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
883 * We will be called with VDD already enabled for dpcd/edid/oui reads.
884 * In such cases we want to leave VDD enabled and it's up to upper layers
885 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
888 vdd
= edp_panel_vdd_on(intel_dp
);
890 /* dp aux is extremely sensitive to irq latency, hence request the
891 * lowest possible wakeup latency and so prevent the cpu from going into
894 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
896 intel_dp_check_edp(intel_dp
);
898 /* Try to wait for any previous AUX channel activity */
899 for (try = 0; try < 3; try++) {
900 status
= I915_READ_NOTRACE(ch_ctl
);
901 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
907 static u32 last_status
= -1;
908 const u32 status
= I915_READ(ch_ctl
);
910 if (status
!= last_status
) {
911 WARN(1, "dp_aux_ch not started status 0x%08x\n",
913 last_status
= status
;
920 /* Only 5 data registers! */
921 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
926 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
927 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
932 /* Must try at least 3 times according to DP spec */
933 for (try = 0; try < 5; try++) {
934 /* Load the send data into the aux channel data registers */
935 for (i
= 0; i
< send_bytes
; i
+= 4)
936 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
937 intel_dp_pack_aux(send
+ i
,
940 /* Send the command and wait for it to complete */
941 I915_WRITE(ch_ctl
, send_ctl
);
943 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
945 /* Clear done status and any errors */
949 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
950 DP_AUX_CH_CTL_RECEIVE_ERROR
);
952 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
955 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
956 * 400us delay required for errors and timeouts
957 * Timeout errors from the HW already meet this
958 * requirement so skip to next iteration
960 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
961 usleep_range(400, 500);
964 if (status
& DP_AUX_CH_CTL_DONE
)
969 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
970 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
976 /* Check for timeout or receive error.
977 * Timeouts occur when the sink is not connected
979 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
980 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
985 /* Timeouts occur when the device isn't connected, so they're
986 * "normal" -- don't fill the kernel log with these */
987 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
988 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
993 /* Unload any bytes sent back from the other side */
994 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
995 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
998 * By BSpec: "Message sizes of 0 or >20 are not allowed."
999 * We have no idea of what happened so we return -EBUSY so
1000 * drm layer takes care for the necessary retries.
1002 if (recv_bytes
== 0 || recv_bytes
> 20) {
1003 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1006 * FIXME: This patch was created on top of a series that
1007 * organize the retries at drm level. There EBUSY should
1008 * also take care for 1ms wait before retrying.
1009 * That aux retries re-org is still needed and after that is
1010 * merged we remove this sleep from here.
1012 usleep_range(1000, 1500);
1017 if (recv_bytes
> recv_size
)
1018 recv_bytes
= recv_size
;
1020 for (i
= 0; i
< recv_bytes
; i
+= 4)
1021 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1022 recv
+ i
, recv_bytes
- i
);
1026 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1029 edp_panel_vdd_off(intel_dp
, false);
1031 pps_unlock(intel_dp
);
1036 #define BARE_ADDRESS_SIZE 3
1037 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1039 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1041 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1042 uint8_t txbuf
[20], rxbuf
[20];
1043 size_t txsize
, rxsize
;
1046 txbuf
[0] = (msg
->request
<< 4) |
1047 ((msg
->address
>> 16) & 0xf);
1048 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1049 txbuf
[2] = msg
->address
& 0xff;
1050 txbuf
[3] = msg
->size
- 1;
1052 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1053 case DP_AUX_NATIVE_WRITE
:
1054 case DP_AUX_I2C_WRITE
:
1055 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1056 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1057 rxsize
= 2; /* 0 or 1 data bytes */
1059 if (WARN_ON(txsize
> 20))
1062 WARN_ON(!msg
->buffer
!= !msg
->size
);
1065 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1067 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1069 msg
->reply
= rxbuf
[0] >> 4;
1072 /* Number of bytes written in a short write. */
1073 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1075 /* Return payload size. */
1081 case DP_AUX_NATIVE_READ
:
1082 case DP_AUX_I2C_READ
:
1083 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1084 rxsize
= msg
->size
+ 1;
1086 if (WARN_ON(rxsize
> 20))
1089 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1091 msg
->reply
= rxbuf
[0] >> 4;
1093 * Assume happy day, and copy the data. The caller is
1094 * expected to check msg->reply before touching it.
1096 * Return payload size.
1099 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1111 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1118 return DP_AUX_CH_CTL(port
);
1121 return DP_AUX_CH_CTL(PORT_B
);
1125 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1126 enum port port
, int index
)
1132 return DP_AUX_CH_DATA(port
, index
);
1135 return DP_AUX_CH_DATA(PORT_B
, index
);
1139 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1144 return DP_AUX_CH_CTL(port
);
1148 return PCH_DP_AUX_CH_CTL(port
);
1151 return DP_AUX_CH_CTL(PORT_A
);
1155 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1156 enum port port
, int index
)
1160 return DP_AUX_CH_DATA(port
, index
);
1164 return PCH_DP_AUX_CH_DATA(port
, index
);
1167 return DP_AUX_CH_DATA(PORT_A
, index
);
1172 * On SKL we don't have Aux for port E so we rely
1173 * on VBT to set a proper alternate aux channel.
1175 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1177 const struct ddi_vbt_port_info
*info
=
1178 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1180 switch (info
->alternate_aux_channel
) {
1190 MISSING_CASE(info
->alternate_aux_channel
);
1195 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1199 port
= skl_porte_aux_port(dev_priv
);
1206 return DP_AUX_CH_CTL(port
);
1209 return DP_AUX_CH_CTL(PORT_A
);
1213 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1214 enum port port
, int index
)
1217 port
= skl_porte_aux_port(dev_priv
);
1224 return DP_AUX_CH_DATA(port
, index
);
1227 return DP_AUX_CH_DATA(PORT_A
, index
);
1231 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1234 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1235 return skl_aux_ctl_reg(dev_priv
, port
);
1236 else if (HAS_PCH_SPLIT(dev_priv
))
1237 return ilk_aux_ctl_reg(dev_priv
, port
);
1239 return g4x_aux_ctl_reg(dev_priv
, port
);
1242 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1243 enum port port
, int index
)
1245 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1246 return skl_aux_data_reg(dev_priv
, port
, index
);
1247 else if (HAS_PCH_SPLIT(dev_priv
))
1248 return ilk_aux_data_reg(dev_priv
, port
, index
);
1250 return g4x_aux_data_reg(dev_priv
, port
, index
);
1253 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1255 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1256 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1259 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1260 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1261 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1265 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1267 kfree(intel_dp
->aux
.name
);
1271 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1273 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1274 enum port port
= intel_dig_port
->port
;
1276 intel_aux_reg_init(intel_dp
);
1277 drm_dp_aux_init(&intel_dp
->aux
);
1279 /* Failure to allocate our preferred name is not critical */
1280 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1281 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1285 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1287 if (intel_dp
->num_sink_rates
) {
1288 *sink_rates
= intel_dp
->sink_rates
;
1289 return intel_dp
->num_sink_rates
;
1292 *sink_rates
= default_rates
;
1294 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1297 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1299 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1300 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1302 if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
1303 IS_BROADWELL(dev_priv
) || (INTEL_GEN(dev_priv
) >= 9))
1310 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1312 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1313 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1316 if (IS_BROXTON(dev_priv
)) {
1317 *source_rates
= bxt_rates
;
1318 size
= ARRAY_SIZE(bxt_rates
);
1319 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
1320 *source_rates
= skl_rates
;
1321 size
= ARRAY_SIZE(skl_rates
);
1323 *source_rates
= default_rates
;
1324 size
= ARRAY_SIZE(default_rates
);
1327 /* This depends on the fact that 5.4 is last value in the array */
1328 if (!intel_dp_source_supports_hbr2(intel_dp
))
1335 intel_dp_set_clock(struct intel_encoder
*encoder
,
1336 struct intel_crtc_state
*pipe_config
)
1338 struct drm_device
*dev
= encoder
->base
.dev
;
1339 const struct dp_link_dpll
*divisor
= NULL
;
1343 divisor
= gen4_dpll
;
1344 count
= ARRAY_SIZE(gen4_dpll
);
1345 } else if (HAS_PCH_SPLIT(dev
)) {
1347 count
= ARRAY_SIZE(pch_dpll
);
1348 } else if (IS_CHERRYVIEW(dev
)) {
1350 count
= ARRAY_SIZE(chv_dpll
);
1351 } else if (IS_VALLEYVIEW(dev
)) {
1353 count
= ARRAY_SIZE(vlv_dpll
);
1356 if (divisor
&& count
) {
1357 for (i
= 0; i
< count
; i
++) {
1358 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1359 pipe_config
->dpll
= divisor
[i
].dpll
;
1360 pipe_config
->clock_set
= true;
1367 static int intersect_rates(const int *source_rates
, int source_len
,
1368 const int *sink_rates
, int sink_len
,
1371 int i
= 0, j
= 0, k
= 0;
1373 while (i
< source_len
&& j
< sink_len
) {
1374 if (source_rates
[i
] == sink_rates
[j
]) {
1375 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1377 common_rates
[k
] = source_rates
[i
];
1381 } else if (source_rates
[i
] < sink_rates
[j
]) {
1390 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1393 const int *source_rates
, *sink_rates
;
1394 int source_len
, sink_len
;
1396 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1397 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1399 return intersect_rates(source_rates
, source_len
,
1400 sink_rates
, sink_len
,
1404 static void snprintf_int_array(char *str
, size_t len
,
1405 const int *array
, int nelem
)
1411 for (i
= 0; i
< nelem
; i
++) {
1412 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1420 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1422 const int *source_rates
, *sink_rates
;
1423 int source_len
, sink_len
, common_len
;
1424 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1425 char str
[128]; /* FIXME: too big for stack? */
1427 if ((drm_debug
& DRM_UT_KMS
) == 0)
1430 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1431 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1432 DRM_DEBUG_KMS("source rates: %s\n", str
);
1434 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1435 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1436 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1438 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1439 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1440 DRM_DEBUG_KMS("common rates: %s\n", str
);
1443 static void intel_dp_print_hw_revision(struct intel_dp
*intel_dp
)
1448 if ((drm_debug
& DRM_UT_KMS
) == 0)
1451 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1452 DP_DWN_STRM_PORT_PRESENT
))
1455 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_HW_REV
, &rev
, 1);
1459 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev
& 0xf0) >> 4, rev
& 0xf);
1462 static void intel_dp_print_sw_revision(struct intel_dp
*intel_dp
)
1467 if ((drm_debug
& DRM_UT_KMS
) == 0)
1470 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1471 DP_DWN_STRM_PORT_PRESENT
))
1474 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_SW_REV
, &rev
, 2);
1478 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev
[0], rev
[1]);
1481 static int rate_to_index(int find
, const int *rates
)
1485 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1486 if (find
== rates
[i
])
1493 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1495 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1498 len
= intel_dp_common_rates(intel_dp
, rates
);
1499 if (WARN_ON(len
<= 0))
1502 return rates
[len
- 1];
1505 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1507 return rate_to_index(rate
, intel_dp
->sink_rates
);
1510 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1511 uint8_t *link_bw
, uint8_t *rate_select
)
1513 if (intel_dp
->num_sink_rates
) {
1516 intel_dp_rate_select(intel_dp
, port_clock
);
1518 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1523 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1524 struct intel_crtc_state
*pipe_config
)
1528 bpp
= pipe_config
->pipe_bpp
;
1529 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1532 bpp
= min(bpp
, 3*bpc
);
1538 intel_dp_compute_config(struct intel_encoder
*encoder
,
1539 struct intel_crtc_state
*pipe_config
,
1540 struct drm_connector_state
*conn_state
)
1542 struct drm_device
*dev
= encoder
->base
.dev
;
1543 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1544 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1545 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1546 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1547 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1548 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1549 int lane_count
, clock
;
1550 int min_lane_count
= 1;
1551 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1552 /* Conveniently, the link BW constants become indices with a shift...*/
1556 int link_avail
, link_clock
;
1557 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1559 uint8_t link_bw
, rate_select
;
1561 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1563 /* No common link rates between source and sink */
1564 WARN_ON(common_len
<= 0);
1566 max_clock
= common_len
- 1;
1568 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1569 pipe_config
->has_pch_encoder
= true;
1571 pipe_config
->has_drrs
= false;
1572 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1574 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1575 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1578 if (INTEL_INFO(dev
)->gen
>= 9) {
1580 ret
= skl_update_scaler_crtc(pipe_config
);
1585 if (HAS_GMCH_DISPLAY(dev
))
1586 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1587 intel_connector
->panel
.fitting_mode
);
1589 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1590 intel_connector
->panel
.fitting_mode
);
1593 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1596 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1597 "max bw %d pixel clock %iKHz\n",
1598 max_lane_count
, common_rates
[max_clock
],
1599 adjusted_mode
->crtc_clock
);
1601 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1602 * bpc in between. */
1603 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1604 if (is_edp(intel_dp
)) {
1606 /* Get bpp from vbt only for panels that dont have bpp in edid */
1607 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1608 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1609 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1610 dev_priv
->vbt
.edp
.bpp
);
1611 bpp
= dev_priv
->vbt
.edp
.bpp
;
1615 * Use the maximum clock and number of lanes the eDP panel
1616 * advertizes being capable of. The panels are generally
1617 * designed to support only a single clock and lane
1618 * configuration, and typically these values correspond to the
1619 * native resolution of the panel.
1621 min_lane_count
= max_lane_count
;
1622 min_clock
= max_clock
;
1625 for (; bpp
>= 6*3; bpp
-= 2*3) {
1626 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1629 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1630 for (lane_count
= min_lane_count
;
1631 lane_count
<= max_lane_count
;
1634 link_clock
= common_rates
[clock
];
1635 link_avail
= intel_dp_max_data_rate(link_clock
,
1638 if (mode_rate
<= link_avail
) {
1648 if (intel_dp
->color_range_auto
) {
1651 * CEA-861-E - 5.1 Default Encoding Parameters
1652 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1654 pipe_config
->limited_color_range
=
1655 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1657 pipe_config
->limited_color_range
=
1658 intel_dp
->limited_color_range
;
1661 pipe_config
->lane_count
= lane_count
;
1663 pipe_config
->pipe_bpp
= bpp
;
1664 pipe_config
->port_clock
= common_rates
[clock
];
1666 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1667 &link_bw
, &rate_select
);
1669 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1670 link_bw
, rate_select
, pipe_config
->lane_count
,
1671 pipe_config
->port_clock
, bpp
);
1672 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1673 mode_rate
, link_avail
);
1675 intel_link_compute_m_n(bpp
, lane_count
,
1676 adjusted_mode
->crtc_clock
,
1677 pipe_config
->port_clock
,
1678 &pipe_config
->dp_m_n
);
1680 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1681 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1682 pipe_config
->has_drrs
= true;
1683 intel_link_compute_m_n(bpp
, lane_count
,
1684 intel_connector
->panel
.downclock_mode
->clock
,
1685 pipe_config
->port_clock
,
1686 &pipe_config
->dp_m2_n2
);
1690 * DPLL0 VCO may need to be adjusted to get the correct
1691 * clock for eDP. This will affect cdclk as well.
1693 if (is_edp(intel_dp
) &&
1694 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1697 switch (pipe_config
->port_clock
/ 2) {
1707 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1710 if (!HAS_DDI(dev_priv
))
1711 intel_dp_set_clock(encoder
, pipe_config
);
1716 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1717 int link_rate
, uint8_t lane_count
,
1720 intel_dp
->link_rate
= link_rate
;
1721 intel_dp
->lane_count
= lane_count
;
1722 intel_dp
->link_mst
= link_mst
;
1725 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1726 struct intel_crtc_state
*pipe_config
)
1728 struct drm_device
*dev
= encoder
->base
.dev
;
1729 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1730 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1731 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1732 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1733 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1735 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1736 pipe_config
->lane_count
,
1737 intel_crtc_has_type(pipe_config
,
1738 INTEL_OUTPUT_DP_MST
));
1741 * There are four kinds of DP registers:
1748 * IBX PCH and CPU are the same for almost everything,
1749 * except that the CPU DP PLL is configured in this
1752 * CPT PCH is quite different, having many bits moved
1753 * to the TRANS_DP_CTL register instead. That
1754 * configuration happens (oddly) in ironlake_pch_enable
1757 /* Preserve the BIOS-computed detected bit. This is
1758 * supposed to be read-only.
1760 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1762 /* Handle DP bits in common between all three register formats */
1763 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1764 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1766 /* Split out the IBX/CPU vs CPT settings */
1768 if (IS_GEN7(dev
) && port
== PORT_A
) {
1769 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1770 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1771 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1772 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1773 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1775 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1776 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1778 intel_dp
->DP
|= crtc
->pipe
<< 29;
1779 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1782 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1784 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1785 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1786 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1788 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1789 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1791 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1792 !IS_CHERRYVIEW(dev
) && pipe_config
->limited_color_range
)
1793 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1795 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1796 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1797 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1798 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1799 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1801 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1802 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1804 if (IS_CHERRYVIEW(dev
))
1805 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1806 else if (crtc
->pipe
== PIPE_B
)
1807 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1811 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1812 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1814 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1815 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1817 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1818 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1820 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1821 struct intel_dp
*intel_dp
);
1823 static void wait_panel_status(struct intel_dp
*intel_dp
,
1827 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1828 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1829 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1831 lockdep_assert_held(&dev_priv
->pps_mutex
);
1833 intel_pps_verify_state(dev_priv
, intel_dp
);
1835 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1836 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1838 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1840 I915_READ(pp_stat_reg
),
1841 I915_READ(pp_ctrl_reg
));
1843 if (intel_wait_for_register(dev_priv
,
1844 pp_stat_reg
, mask
, value
,
1846 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1847 I915_READ(pp_stat_reg
),
1848 I915_READ(pp_ctrl_reg
));
1850 DRM_DEBUG_KMS("Wait complete\n");
1853 static void wait_panel_on(struct intel_dp
*intel_dp
)
1855 DRM_DEBUG_KMS("Wait for panel power on\n");
1856 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1859 static void wait_panel_off(struct intel_dp
*intel_dp
)
1861 DRM_DEBUG_KMS("Wait for panel power off time\n");
1862 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1865 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1867 ktime_t panel_power_on_time
;
1868 s64 panel_power_off_duration
;
1870 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1872 /* take the difference of currrent time and panel power off time
1873 * and then make panel wait for t11_t12 if needed. */
1874 panel_power_on_time
= ktime_get_boottime();
1875 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1877 /* When we disable the VDD override bit last we have to do the manual
1879 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1880 wait_remaining_ms_from_jiffies(jiffies
,
1881 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1883 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1886 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1888 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1889 intel_dp
->backlight_on_delay
);
1892 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1894 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1895 intel_dp
->backlight_off_delay
);
1898 /* Read the current pp_control value, unlocking the register if it
1902 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1904 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1905 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1908 lockdep_assert_held(&dev_priv
->pps_mutex
);
1910 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1911 if (WARN_ON(!HAS_DDI(dev_priv
) &&
1912 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
1913 control
&= ~PANEL_UNLOCK_MASK
;
1914 control
|= PANEL_UNLOCK_REGS
;
1920 * Must be paired with edp_panel_vdd_off().
1921 * Must hold pps_mutex around the whole on/off sequence.
1922 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1924 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1926 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1927 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1928 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1929 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1930 enum intel_display_power_domain power_domain
;
1932 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1933 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1935 lockdep_assert_held(&dev_priv
->pps_mutex
);
1937 if (!is_edp(intel_dp
))
1940 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1941 intel_dp
->want_panel_vdd
= true;
1943 if (edp_have_panel_vdd(intel_dp
))
1944 return need_to_disable
;
1946 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1947 intel_display_power_get(dev_priv
, power_domain
);
1949 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1950 port_name(intel_dig_port
->port
));
1952 if (!edp_have_panel_power(intel_dp
))
1953 wait_panel_power_cycle(intel_dp
);
1955 pp
= ironlake_get_pp_control(intel_dp
);
1956 pp
|= EDP_FORCE_VDD
;
1958 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1959 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1961 I915_WRITE(pp_ctrl_reg
, pp
);
1962 POSTING_READ(pp_ctrl_reg
);
1963 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1964 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1966 * If the panel wasn't on, delay before accessing aux channel
1968 if (!edp_have_panel_power(intel_dp
)) {
1969 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1970 port_name(intel_dig_port
->port
));
1971 msleep(intel_dp
->panel_power_up_delay
);
1974 return need_to_disable
;
1978 * Must be paired with intel_edp_panel_vdd_off() or
1979 * intel_edp_panel_off().
1980 * Nested calls to these functions are not allowed since
1981 * we drop the lock. Caller must use some higher level
1982 * locking to prevent nested calls from other threads.
1984 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1988 if (!is_edp(intel_dp
))
1992 vdd
= edp_panel_vdd_on(intel_dp
);
1993 pps_unlock(intel_dp
);
1995 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1996 port_name(dp_to_dig_port(intel_dp
)->port
));
1999 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2001 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2002 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2003 struct intel_digital_port
*intel_dig_port
=
2004 dp_to_dig_port(intel_dp
);
2005 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2006 enum intel_display_power_domain power_domain
;
2008 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2010 lockdep_assert_held(&dev_priv
->pps_mutex
);
2012 WARN_ON(intel_dp
->want_panel_vdd
);
2014 if (!edp_have_panel_vdd(intel_dp
))
2017 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2018 port_name(intel_dig_port
->port
));
2020 pp
= ironlake_get_pp_control(intel_dp
);
2021 pp
&= ~EDP_FORCE_VDD
;
2023 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2024 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2026 I915_WRITE(pp_ctrl_reg
, pp
);
2027 POSTING_READ(pp_ctrl_reg
);
2029 /* Make sure sequencer is idle before allowing subsequent activity */
2030 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2031 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2033 if ((pp
& PANEL_POWER_ON
) == 0)
2034 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2036 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2037 intel_display_power_put(dev_priv
, power_domain
);
2040 static void edp_panel_vdd_work(struct work_struct
*__work
)
2042 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2043 struct intel_dp
, panel_vdd_work
);
2046 if (!intel_dp
->want_panel_vdd
)
2047 edp_panel_vdd_off_sync(intel_dp
);
2048 pps_unlock(intel_dp
);
2051 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2053 unsigned long delay
;
2056 * Queue the timer to fire a long time from now (relative to the power
2057 * down delay) to keep the panel power up across a sequence of
2060 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2061 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2065 * Must be paired with edp_panel_vdd_on().
2066 * Must hold pps_mutex around the whole on/off sequence.
2067 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2069 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2071 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2073 lockdep_assert_held(&dev_priv
->pps_mutex
);
2075 if (!is_edp(intel_dp
))
2078 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2079 port_name(dp_to_dig_port(intel_dp
)->port
));
2081 intel_dp
->want_panel_vdd
= false;
2084 edp_panel_vdd_off_sync(intel_dp
);
2086 edp_panel_vdd_schedule_off(intel_dp
);
2089 static void edp_panel_on(struct intel_dp
*intel_dp
)
2091 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2092 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2094 i915_reg_t pp_ctrl_reg
;
2096 lockdep_assert_held(&dev_priv
->pps_mutex
);
2098 if (!is_edp(intel_dp
))
2101 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2102 port_name(dp_to_dig_port(intel_dp
)->port
));
2104 if (WARN(edp_have_panel_power(intel_dp
),
2105 "eDP port %c panel power already on\n",
2106 port_name(dp_to_dig_port(intel_dp
)->port
)))
2109 wait_panel_power_cycle(intel_dp
);
2111 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2112 pp
= ironlake_get_pp_control(intel_dp
);
2114 /* ILK workaround: disable reset around power sequence */
2115 pp
&= ~PANEL_POWER_RESET
;
2116 I915_WRITE(pp_ctrl_reg
, pp
);
2117 POSTING_READ(pp_ctrl_reg
);
2120 pp
|= PANEL_POWER_ON
;
2122 pp
|= PANEL_POWER_RESET
;
2124 I915_WRITE(pp_ctrl_reg
, pp
);
2125 POSTING_READ(pp_ctrl_reg
);
2127 wait_panel_on(intel_dp
);
2128 intel_dp
->last_power_on
= jiffies
;
2131 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2132 I915_WRITE(pp_ctrl_reg
, pp
);
2133 POSTING_READ(pp_ctrl_reg
);
2137 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2139 if (!is_edp(intel_dp
))
2143 edp_panel_on(intel_dp
);
2144 pps_unlock(intel_dp
);
2148 static void edp_panel_off(struct intel_dp
*intel_dp
)
2150 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2151 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2152 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2153 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2154 enum intel_display_power_domain power_domain
;
2156 i915_reg_t pp_ctrl_reg
;
2158 lockdep_assert_held(&dev_priv
->pps_mutex
);
2160 if (!is_edp(intel_dp
))
2163 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2164 port_name(dp_to_dig_port(intel_dp
)->port
));
2166 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2167 port_name(dp_to_dig_port(intel_dp
)->port
));
2169 pp
= ironlake_get_pp_control(intel_dp
);
2170 /* We need to switch off panel power _and_ force vdd, for otherwise some
2171 * panels get very unhappy and cease to work. */
2172 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2175 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2177 intel_dp
->want_panel_vdd
= false;
2179 I915_WRITE(pp_ctrl_reg
, pp
);
2180 POSTING_READ(pp_ctrl_reg
);
2182 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2183 wait_panel_off(intel_dp
);
2185 /* We got a reference when we enabled the VDD. */
2186 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2187 intel_display_power_put(dev_priv
, power_domain
);
2190 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2192 if (!is_edp(intel_dp
))
2196 edp_panel_off(intel_dp
);
2197 pps_unlock(intel_dp
);
2200 /* Enable backlight in the panel power control. */
2201 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2203 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2204 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2205 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2207 i915_reg_t pp_ctrl_reg
;
2210 * If we enable the backlight right away following a panel power
2211 * on, we may see slight flicker as the panel syncs with the eDP
2212 * link. So delay a bit to make sure the image is solid before
2213 * allowing it to appear.
2215 wait_backlight_on(intel_dp
);
2219 pp
= ironlake_get_pp_control(intel_dp
);
2220 pp
|= EDP_BLC_ENABLE
;
2222 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2224 I915_WRITE(pp_ctrl_reg
, pp
);
2225 POSTING_READ(pp_ctrl_reg
);
2227 pps_unlock(intel_dp
);
2230 /* Enable backlight PWM and backlight PP control. */
2231 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2233 if (!is_edp(intel_dp
))
2236 DRM_DEBUG_KMS("\n");
2238 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2239 _intel_edp_backlight_on(intel_dp
);
2242 /* Disable backlight in the panel power control. */
2243 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2245 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2246 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2248 i915_reg_t pp_ctrl_reg
;
2250 if (!is_edp(intel_dp
))
2255 pp
= ironlake_get_pp_control(intel_dp
);
2256 pp
&= ~EDP_BLC_ENABLE
;
2258 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2260 I915_WRITE(pp_ctrl_reg
, pp
);
2261 POSTING_READ(pp_ctrl_reg
);
2263 pps_unlock(intel_dp
);
2265 intel_dp
->last_backlight_off
= jiffies
;
2266 edp_wait_backlight_off(intel_dp
);
2269 /* Disable backlight PP control and backlight PWM. */
2270 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2272 if (!is_edp(intel_dp
))
2275 DRM_DEBUG_KMS("\n");
2277 _intel_edp_backlight_off(intel_dp
);
2278 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2282 * Hook for controlling the panel power control backlight through the bl_power
2283 * sysfs attribute. Take care to handle multiple calls.
2285 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2288 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2292 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2293 pps_unlock(intel_dp
);
2295 if (is_enabled
== enable
)
2298 DRM_DEBUG_KMS("panel power control backlight %s\n",
2299 enable
? "enable" : "disable");
2302 _intel_edp_backlight_on(intel_dp
);
2304 _intel_edp_backlight_off(intel_dp
);
2307 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2309 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2310 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2311 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2313 I915_STATE_WARN(cur_state
!= state
,
2314 "DP port %c state assertion failure (expected %s, current %s)\n",
2315 port_name(dig_port
->port
),
2316 onoff(state
), onoff(cur_state
));
2318 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2320 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2322 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2324 I915_STATE_WARN(cur_state
!= state
,
2325 "eDP PLL state assertion failure (expected %s, current %s)\n",
2326 onoff(state
), onoff(cur_state
));
2328 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2329 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2331 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2332 struct intel_crtc_state
*pipe_config
)
2334 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2335 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2337 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2338 assert_dp_port_disabled(intel_dp
);
2339 assert_edp_pll_disabled(dev_priv
);
2341 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2342 pipe_config
->port_clock
);
2344 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2346 if (pipe_config
->port_clock
== 162000)
2347 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2349 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2351 I915_WRITE(DP_A
, intel_dp
->DP
);
2356 * [DevILK] Work around required when enabling DP PLL
2357 * while a pipe is enabled going to FDI:
2358 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2359 * 2. Program DP PLL enable
2361 if (IS_GEN5(dev_priv
))
2362 intel_wait_for_vblank_if_active(&dev_priv
->drm
, !crtc
->pipe
);
2364 intel_dp
->DP
|= DP_PLL_ENABLE
;
2366 I915_WRITE(DP_A
, intel_dp
->DP
);
2371 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2373 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2374 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2375 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2377 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2378 assert_dp_port_disabled(intel_dp
);
2379 assert_edp_pll_enabled(dev_priv
);
2381 DRM_DEBUG_KMS("disabling eDP PLL\n");
2383 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2385 I915_WRITE(DP_A
, intel_dp
->DP
);
2390 /* If the sink supports it, try to set the power state appropriately */
2391 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2395 /* Should have a valid DPCD by this point */
2396 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2399 if (mode
!= DRM_MODE_DPMS_ON
) {
2400 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2404 * When turning on, we need to retry for 1ms to give the sink
2407 for (i
= 0; i
< 3; i
++) {
2408 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2417 DRM_DEBUG_KMS("failed to %s sink power state\n",
2418 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2421 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2424 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2425 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2426 struct drm_device
*dev
= encoder
->base
.dev
;
2427 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2428 enum intel_display_power_domain power_domain
;
2432 power_domain
= intel_display_port_power_domain(encoder
);
2433 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2438 tmp
= I915_READ(intel_dp
->output_reg
);
2440 if (!(tmp
& DP_PORT_EN
))
2443 if (IS_GEN7(dev
) && port
== PORT_A
) {
2444 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2445 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2448 for_each_pipe(dev_priv
, p
) {
2449 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2450 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2458 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2459 i915_mmio_reg_offset(intel_dp
->output_reg
));
2460 } else if (IS_CHERRYVIEW(dev
)) {
2461 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2463 *pipe
= PORT_TO_PIPE(tmp
);
2469 intel_display_power_put(dev_priv
, power_domain
);
2474 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2475 struct intel_crtc_state
*pipe_config
)
2477 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2479 struct drm_device
*dev
= encoder
->base
.dev
;
2480 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2481 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2482 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2484 tmp
= I915_READ(intel_dp
->output_reg
);
2486 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2488 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2489 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2491 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2492 flags
|= DRM_MODE_FLAG_PHSYNC
;
2494 flags
|= DRM_MODE_FLAG_NHSYNC
;
2496 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2497 flags
|= DRM_MODE_FLAG_PVSYNC
;
2499 flags
|= DRM_MODE_FLAG_NVSYNC
;
2501 if (tmp
& DP_SYNC_HS_HIGH
)
2502 flags
|= DRM_MODE_FLAG_PHSYNC
;
2504 flags
|= DRM_MODE_FLAG_NHSYNC
;
2506 if (tmp
& DP_SYNC_VS_HIGH
)
2507 flags
|= DRM_MODE_FLAG_PVSYNC
;
2509 flags
|= DRM_MODE_FLAG_NVSYNC
;
2512 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2514 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2515 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2516 pipe_config
->limited_color_range
= true;
2518 pipe_config
->lane_count
=
2519 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2521 intel_dp_get_m_n(crtc
, pipe_config
);
2523 if (port
== PORT_A
) {
2524 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2525 pipe_config
->port_clock
= 162000;
2527 pipe_config
->port_clock
= 270000;
2530 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2531 intel_dotclock_calculate(pipe_config
->port_clock
,
2532 &pipe_config
->dp_m_n
);
2534 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2535 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2537 * This is a big fat ugly hack.
2539 * Some machines in UEFI boot mode provide us a VBT that has 18
2540 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2541 * unknown we fail to light up. Yet the same BIOS boots up with
2542 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2543 * max, not what it tells us to use.
2545 * Note: This will still be broken if the eDP panel is not lit
2546 * up by the BIOS, and thus we can't get the mode at module
2549 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2550 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2551 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2555 static void intel_disable_dp(struct intel_encoder
*encoder
,
2556 struct intel_crtc_state
*old_crtc_state
,
2557 struct drm_connector_state
*old_conn_state
)
2559 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2560 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2562 if (old_crtc_state
->has_audio
)
2563 intel_audio_codec_disable(encoder
);
2565 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2566 intel_psr_disable(intel_dp
);
2568 /* Make sure the panel is off before trying to change the mode. But also
2569 * ensure that we have vdd while we switch off the panel. */
2570 intel_edp_panel_vdd_on(intel_dp
);
2571 intel_edp_backlight_off(intel_dp
);
2572 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2573 intel_edp_panel_off(intel_dp
);
2575 /* disable the port before the pipe on g4x */
2576 if (INTEL_GEN(dev_priv
) < 5)
2577 intel_dp_link_down(intel_dp
);
2580 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2581 struct intel_crtc_state
*old_crtc_state
,
2582 struct drm_connector_state
*old_conn_state
)
2584 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2585 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2587 intel_dp_link_down(intel_dp
);
2589 /* Only ilk+ has port A */
2591 ironlake_edp_pll_off(intel_dp
);
2594 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2595 struct intel_crtc_state
*old_crtc_state
,
2596 struct drm_connector_state
*old_conn_state
)
2598 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2600 intel_dp_link_down(intel_dp
);
2603 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2604 struct intel_crtc_state
*old_crtc_state
,
2605 struct drm_connector_state
*old_conn_state
)
2607 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2608 struct drm_device
*dev
= encoder
->base
.dev
;
2609 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2611 intel_dp_link_down(intel_dp
);
2613 mutex_lock(&dev_priv
->sb_lock
);
2615 /* Assert data lane reset */
2616 chv_data_lane_soft_reset(encoder
, true);
2618 mutex_unlock(&dev_priv
->sb_lock
);
2622 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2624 uint8_t dp_train_pat
)
2626 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2627 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2628 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2629 enum port port
= intel_dig_port
->port
;
2631 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2632 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2633 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2635 if (HAS_DDI(dev_priv
)) {
2636 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2638 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2639 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2641 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2643 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2644 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2645 case DP_TRAINING_PATTERN_DISABLE
:
2646 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2649 case DP_TRAINING_PATTERN_1
:
2650 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2652 case DP_TRAINING_PATTERN_2
:
2653 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2655 case DP_TRAINING_PATTERN_3
:
2656 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2659 I915_WRITE(DP_TP_CTL(port
), temp
);
2661 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2662 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2663 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2665 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2666 case DP_TRAINING_PATTERN_DISABLE
:
2667 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2669 case DP_TRAINING_PATTERN_1
:
2670 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2672 case DP_TRAINING_PATTERN_2
:
2673 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2675 case DP_TRAINING_PATTERN_3
:
2676 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2677 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2682 if (IS_CHERRYVIEW(dev
))
2683 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2685 *DP
&= ~DP_LINK_TRAIN_MASK
;
2687 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2688 case DP_TRAINING_PATTERN_DISABLE
:
2689 *DP
|= DP_LINK_TRAIN_OFF
;
2691 case DP_TRAINING_PATTERN_1
:
2692 *DP
|= DP_LINK_TRAIN_PAT_1
;
2694 case DP_TRAINING_PATTERN_2
:
2695 *DP
|= DP_LINK_TRAIN_PAT_2
;
2697 case DP_TRAINING_PATTERN_3
:
2698 if (IS_CHERRYVIEW(dev
)) {
2699 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2701 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2702 *DP
|= DP_LINK_TRAIN_PAT_2
;
2709 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2710 struct intel_crtc_state
*old_crtc_state
)
2712 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2713 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2715 /* enable with pattern 1 (as per spec) */
2717 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2720 * Magic for VLV/CHV. We _must_ first set up the register
2721 * without actually enabling the port, and then do another
2722 * write to enable the port. Otherwise link training will
2723 * fail when the power sequencer is freshly used for this port.
2725 intel_dp
->DP
|= DP_PORT_EN
;
2726 if (old_crtc_state
->has_audio
)
2727 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2729 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2730 POSTING_READ(intel_dp
->output_reg
);
2733 static void intel_enable_dp(struct intel_encoder
*encoder
,
2734 struct intel_crtc_state
*pipe_config
)
2736 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2737 struct drm_device
*dev
= encoder
->base
.dev
;
2738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2739 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2740 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2741 enum pipe pipe
= crtc
->pipe
;
2743 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2748 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2749 vlv_init_panel_power_sequencer(intel_dp
);
2751 intel_dp_enable_port(intel_dp
, pipe_config
);
2753 edp_panel_vdd_on(intel_dp
);
2754 edp_panel_on(intel_dp
);
2755 edp_panel_vdd_off(intel_dp
, true);
2757 pps_unlock(intel_dp
);
2759 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2760 unsigned int lane_mask
= 0x0;
2762 if (IS_CHERRYVIEW(dev
))
2763 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2765 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2769 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2770 intel_dp_start_link_train(intel_dp
);
2771 intel_dp_stop_link_train(intel_dp
);
2773 if (pipe_config
->has_audio
) {
2774 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2776 intel_audio_codec_enable(encoder
);
2780 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2781 struct intel_crtc_state
*pipe_config
,
2782 struct drm_connector_state
*conn_state
)
2784 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2786 intel_enable_dp(encoder
, pipe_config
);
2787 intel_edp_backlight_on(intel_dp
);
2790 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2791 struct intel_crtc_state
*pipe_config
,
2792 struct drm_connector_state
*conn_state
)
2794 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2796 intel_edp_backlight_on(intel_dp
);
2797 intel_psr_enable(intel_dp
);
2800 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2801 struct intel_crtc_state
*pipe_config
,
2802 struct drm_connector_state
*conn_state
)
2804 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2805 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2807 intel_dp_prepare(encoder
, pipe_config
);
2809 /* Only ilk+ has port A */
2811 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2814 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2816 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2817 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2818 enum pipe pipe
= intel_dp
->pps_pipe
;
2819 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2821 edp_panel_vdd_off_sync(intel_dp
);
2824 * VLV seems to get confused when multiple power seqeuencers
2825 * have the same port selected (even if only one has power/vdd
2826 * enabled). The failure manifests as vlv_wait_port_ready() failing
2827 * CHV on the other hand doesn't seem to mind having the same port
2828 * selected in multiple power seqeuencers, but let's clear the
2829 * port select always when logically disconnecting a power sequencer
2832 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2833 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2834 I915_WRITE(pp_on_reg
, 0);
2835 POSTING_READ(pp_on_reg
);
2837 intel_dp
->pps_pipe
= INVALID_PIPE
;
2840 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2844 struct intel_encoder
*encoder
;
2846 lockdep_assert_held(&dev_priv
->pps_mutex
);
2848 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2851 for_each_intel_encoder(dev
, encoder
) {
2852 struct intel_dp
*intel_dp
;
2855 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2858 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2859 port
= dp_to_dig_port(intel_dp
)->port
;
2861 if (intel_dp
->pps_pipe
!= pipe
)
2864 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2865 pipe_name(pipe
), port_name(port
));
2867 WARN(encoder
->base
.crtc
,
2868 "stealing pipe %c power sequencer from active eDP port %c\n",
2869 pipe_name(pipe
), port_name(port
));
2871 /* make sure vdd is off before we steal it */
2872 vlv_detach_power_sequencer(intel_dp
);
2876 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2878 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2879 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2880 struct drm_device
*dev
= encoder
->base
.dev
;
2881 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2882 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2884 lockdep_assert_held(&dev_priv
->pps_mutex
);
2886 if (!is_edp(intel_dp
))
2889 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2893 * If another power sequencer was being used on this
2894 * port previously make sure to turn off vdd there while
2895 * we still have control of it.
2897 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2898 vlv_detach_power_sequencer(intel_dp
);
2901 * We may be stealing the power
2902 * sequencer from another port.
2904 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2906 /* now it's all ours */
2907 intel_dp
->pps_pipe
= crtc
->pipe
;
2909 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2910 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2912 /* init power sequencer on this pipe and port */
2913 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2914 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2917 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
2918 struct intel_crtc_state
*pipe_config
,
2919 struct drm_connector_state
*conn_state
)
2921 vlv_phy_pre_encoder_enable(encoder
);
2923 intel_enable_dp(encoder
, pipe_config
);
2926 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2927 struct intel_crtc_state
*pipe_config
,
2928 struct drm_connector_state
*conn_state
)
2930 intel_dp_prepare(encoder
, pipe_config
);
2932 vlv_phy_pre_pll_enable(encoder
);
2935 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
2936 struct intel_crtc_state
*pipe_config
,
2937 struct drm_connector_state
*conn_state
)
2939 chv_phy_pre_encoder_enable(encoder
);
2941 intel_enable_dp(encoder
, pipe_config
);
2943 /* Second common lane will stay alive on its own now */
2944 chv_phy_release_cl2_override(encoder
);
2947 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2948 struct intel_crtc_state
*pipe_config
,
2949 struct drm_connector_state
*conn_state
)
2951 intel_dp_prepare(encoder
, pipe_config
);
2953 chv_phy_pre_pll_enable(encoder
);
2956 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
2957 struct intel_crtc_state
*pipe_config
,
2958 struct drm_connector_state
*conn_state
)
2960 chv_phy_post_pll_disable(encoder
);
2964 * Fetch AUX CH registers 0x202 - 0x207 which contain
2965 * link status information
2968 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2970 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2971 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2974 /* These are source-specific values. */
2976 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2978 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2979 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2980 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2982 if (IS_BROXTON(dev
))
2983 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2984 else if (INTEL_INFO(dev
)->gen
>= 9) {
2985 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2986 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2988 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2989 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2990 else if (IS_GEN7(dev
) && port
== PORT_A
)
2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2992 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2995 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2999 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3001 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3002 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3004 if (INTEL_INFO(dev
)->gen
>= 9) {
3005 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3011 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3013 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3015 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3017 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3018 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3027 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3029 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
3030 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3041 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3042 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3049 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3052 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3054 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3061 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3066 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3068 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3069 unsigned long demph_reg_value
, preemph_reg_value
,
3070 uniqtranscale_reg_value
;
3071 uint8_t train_set
= intel_dp
->train_set
[0];
3073 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3074 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3075 preemph_reg_value
= 0x0004000;
3076 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3078 demph_reg_value
= 0x2B405555;
3079 uniqtranscale_reg_value
= 0x552AB83A;
3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3082 demph_reg_value
= 0x2B404040;
3083 uniqtranscale_reg_value
= 0x5548B83A;
3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3086 demph_reg_value
= 0x2B245555;
3087 uniqtranscale_reg_value
= 0x5560B83A;
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3090 demph_reg_value
= 0x2B405555;
3091 uniqtranscale_reg_value
= 0x5598DA3A;
3097 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3098 preemph_reg_value
= 0x0002000;
3099 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3101 demph_reg_value
= 0x2B404040;
3102 uniqtranscale_reg_value
= 0x5552B83A;
3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3105 demph_reg_value
= 0x2B404848;
3106 uniqtranscale_reg_value
= 0x5580B83A;
3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3109 demph_reg_value
= 0x2B404040;
3110 uniqtranscale_reg_value
= 0x55ADDA3A;
3116 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3117 preemph_reg_value
= 0x0000000;
3118 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3120 demph_reg_value
= 0x2B305555;
3121 uniqtranscale_reg_value
= 0x5570B83A;
3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3124 demph_reg_value
= 0x2B2B4040;
3125 uniqtranscale_reg_value
= 0x55ADDA3A;
3131 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3132 preemph_reg_value
= 0x0006000;
3133 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3135 demph_reg_value
= 0x1B405555;
3136 uniqtranscale_reg_value
= 0x55ADDA3A;
3146 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3147 uniqtranscale_reg_value
, 0);
3152 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3154 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3155 u32 deemph_reg_value
, margin_reg_value
;
3156 bool uniq_trans_scale
= false;
3157 uint8_t train_set
= intel_dp
->train_set
[0];
3159 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3160 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3161 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3163 deemph_reg_value
= 128;
3164 margin_reg_value
= 52;
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3167 deemph_reg_value
= 128;
3168 margin_reg_value
= 77;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3171 deemph_reg_value
= 128;
3172 margin_reg_value
= 102;
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3175 deemph_reg_value
= 128;
3176 margin_reg_value
= 154;
3177 uniq_trans_scale
= true;
3183 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3184 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3186 deemph_reg_value
= 85;
3187 margin_reg_value
= 78;
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3190 deemph_reg_value
= 85;
3191 margin_reg_value
= 116;
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3194 deemph_reg_value
= 85;
3195 margin_reg_value
= 154;
3201 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3202 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3204 deemph_reg_value
= 64;
3205 margin_reg_value
= 104;
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3208 deemph_reg_value
= 64;
3209 margin_reg_value
= 154;
3215 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3216 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3218 deemph_reg_value
= 43;
3219 margin_reg_value
= 154;
3229 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3230 margin_reg_value
, uniq_trans_scale
);
3236 gen4_signal_levels(uint8_t train_set
)
3238 uint32_t signal_levels
= 0;
3240 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3243 signal_levels
|= DP_VOLTAGE_0_4
;
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3246 signal_levels
|= DP_VOLTAGE_0_6
;
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3249 signal_levels
|= DP_VOLTAGE_0_8
;
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3252 signal_levels
|= DP_VOLTAGE_1_2
;
3255 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3256 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3258 signal_levels
|= DP_PRE_EMPHASIS_0
;
3260 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3261 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3263 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3264 signal_levels
|= DP_PRE_EMPHASIS_6
;
3266 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3267 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3270 return signal_levels
;
3273 /* Gen6's DP voltage swing and pre-emphasis control */
3275 gen6_edp_signal_levels(uint8_t train_set
)
3277 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3278 DP_TRAIN_PRE_EMPHASIS_MASK
);
3279 switch (signal_levels
) {
3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3282 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3284 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3287 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3290 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3293 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3295 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3296 "0x%x\n", signal_levels
);
3297 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3301 /* Gen7's DP voltage swing and pre-emphasis control */
3303 gen7_edp_signal_levels(uint8_t train_set
)
3305 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3306 DP_TRAIN_PRE_EMPHASIS_MASK
);
3307 switch (signal_levels
) {
3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3309 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3311 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3312 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3313 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3316 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3318 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3321 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3323 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3326 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3327 "0x%x\n", signal_levels
);
3328 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3333 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3336 enum port port
= intel_dig_port
->port
;
3337 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3338 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3339 uint32_t signal_levels
, mask
= 0;
3340 uint8_t train_set
= intel_dp
->train_set
[0];
3342 if (HAS_DDI(dev_priv
)) {
3343 signal_levels
= ddi_signal_levels(intel_dp
);
3345 if (IS_BROXTON(dev
))
3348 mask
= DDI_BUF_EMP_MASK
;
3349 } else if (IS_CHERRYVIEW(dev
)) {
3350 signal_levels
= chv_signal_levels(intel_dp
);
3351 } else if (IS_VALLEYVIEW(dev
)) {
3352 signal_levels
= vlv_signal_levels(intel_dp
);
3353 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3354 signal_levels
= gen7_edp_signal_levels(train_set
);
3355 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3356 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3357 signal_levels
= gen6_edp_signal_levels(train_set
);
3358 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3360 signal_levels
= gen4_signal_levels(train_set
);
3361 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3365 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3367 DRM_DEBUG_KMS("Using vswing level %d\n",
3368 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3369 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3370 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3371 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3373 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3375 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3376 POSTING_READ(intel_dp
->output_reg
);
3380 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3381 uint8_t dp_train_pat
)
3383 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3384 struct drm_i915_private
*dev_priv
=
3385 to_i915(intel_dig_port
->base
.base
.dev
);
3387 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3389 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3390 POSTING_READ(intel_dp
->output_reg
);
3393 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3397 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3398 enum port port
= intel_dig_port
->port
;
3401 if (!HAS_DDI(dev_priv
))
3404 val
= I915_READ(DP_TP_CTL(port
));
3405 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3406 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3407 I915_WRITE(DP_TP_CTL(port
), val
);
3410 * On PORT_A we can have only eDP in SST mode. There the only reason
3411 * we need to set idle transmission mode is to work around a HW issue
3412 * where we enable the pipe while not in idle link-training mode.
3413 * In this case there is requirement to wait for a minimum number of
3414 * idle patterns to be sent.
3419 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3420 DP_TP_STATUS_IDLE_DONE
,
3421 DP_TP_STATUS_IDLE_DONE
,
3423 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3427 intel_dp_link_down(struct intel_dp
*intel_dp
)
3429 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3430 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3431 enum port port
= intel_dig_port
->port
;
3432 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3433 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3434 uint32_t DP
= intel_dp
->DP
;
3436 if (WARN_ON(HAS_DDI(dev_priv
)))
3439 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3442 DRM_DEBUG_KMS("\n");
3444 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3445 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3446 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3447 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3449 if (IS_CHERRYVIEW(dev
))
3450 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3452 DP
&= ~DP_LINK_TRAIN_MASK
;
3453 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3455 I915_WRITE(intel_dp
->output_reg
, DP
);
3456 POSTING_READ(intel_dp
->output_reg
);
3458 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3459 I915_WRITE(intel_dp
->output_reg
, DP
);
3460 POSTING_READ(intel_dp
->output_reg
);
3463 * HW workaround for IBX, we need to move the port
3464 * to transcoder A after disabling it to allow the
3465 * matching HDMI port to be enabled on transcoder A.
3467 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3469 * We get CPU/PCH FIFO underruns on the other pipe when
3470 * doing the workaround. Sweep them under the rug.
3472 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3473 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3475 /* always enable with pattern 1 (as per spec) */
3476 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3477 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3478 I915_WRITE(intel_dp
->output_reg
, DP
);
3479 POSTING_READ(intel_dp
->output_reg
);
3482 I915_WRITE(intel_dp
->output_reg
, DP
);
3483 POSTING_READ(intel_dp
->output_reg
);
3485 intel_wait_for_vblank_if_active(&dev_priv
->drm
, PIPE_A
);
3486 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3487 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3490 msleep(intel_dp
->panel_power_down_delay
);
3496 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3498 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3499 sizeof(intel_dp
->dpcd
)) < 0)
3500 return false; /* aux transfer failed */
3502 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3504 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3508 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3510 struct drm_i915_private
*dev_priv
=
3511 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3513 /* this function is meant to be called only once */
3514 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3516 if (!intel_dp_read_dpcd(intel_dp
))
3519 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3520 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3521 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3523 /* Check if the panel supports PSR */
3524 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3526 sizeof(intel_dp
->psr_dpcd
));
3527 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3528 dev_priv
->psr
.sink_support
= true;
3529 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3532 if (INTEL_GEN(dev_priv
) >= 9 &&
3533 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3534 uint8_t frame_sync_cap
;
3536 dev_priv
->psr
.sink_support
= true;
3537 drm_dp_dpcd_read(&intel_dp
->aux
,
3538 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3539 &frame_sync_cap
, 1);
3540 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3541 /* PSR2 needs frame sync as well */
3542 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3543 DRM_DEBUG_KMS("PSR2 %s on sink",
3544 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3547 /* Read the eDP Display control capabilities registers */
3548 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3549 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3550 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3551 sizeof(intel_dp
->edp_dpcd
))
3552 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3553 intel_dp
->edp_dpcd
);
3555 /* Intermediate frequency support */
3556 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3557 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3560 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3561 sink_rates
, sizeof(sink_rates
));
3563 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3564 int val
= le16_to_cpu(sink_rates
[i
]);
3569 /* Value read is in kHz while drm clock is saved in deca-kHz */
3570 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3572 intel_dp
->num_sink_rates
= i
;
3580 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3582 if (!intel_dp_read_dpcd(intel_dp
))
3585 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3586 &intel_dp
->sink_count
, 1) < 0)
3590 * Sink count can change between short pulse hpd hence
3591 * a member variable in intel_dp will track any changes
3592 * between short pulse interrupts.
3594 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3597 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3598 * a dongle is present but no display. Unless we require to know
3599 * if a dongle is present or not, we don't need to update
3600 * downstream port information. So, an early return here saves
3601 * time from performing other operations which are not required.
3603 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3606 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3607 DP_DWN_STRM_PORT_PRESENT
))
3608 return true; /* native DP sink */
3610 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3611 return true; /* no per-port downstream info */
3613 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3614 intel_dp
->downstream_ports
,
3615 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3616 return false; /* downstream port status fetch failed */
3622 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3626 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3629 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3630 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3631 buf
[0], buf
[1], buf
[2]);
3633 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3634 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3635 buf
[0], buf
[1], buf
[2]);
3639 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3643 if (!i915
.enable_dp_mst
)
3646 if (!intel_dp
->can_mst
)
3649 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3652 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1) != 1)
3655 return buf
[0] & DP_MST_CAP
;
3659 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3661 if (!i915
.enable_dp_mst
)
3664 if (!intel_dp
->can_mst
)
3667 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3669 if (intel_dp
->is_mst
)
3670 DRM_DEBUG_KMS("Sink is MST capable\n");
3672 DRM_DEBUG_KMS("Sink is not MST capable\n");
3674 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3678 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3680 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3681 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3682 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3688 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3689 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3694 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3695 buf
& ~DP_TEST_SINK_START
) < 0) {
3696 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3702 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3704 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3705 DP_TEST_SINK_MISC
, &buf
) < 0) {
3709 count
= buf
& DP_TEST_COUNT_MASK
;
3710 } while (--attempts
&& count
);
3712 if (attempts
== 0) {
3713 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3718 hsw_enable_ips(intel_crtc
);
3722 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3724 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3725 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3726 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3730 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3733 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3736 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3739 if (buf
& DP_TEST_SINK_START
) {
3740 ret
= intel_dp_sink_crc_stop(intel_dp
);
3745 hsw_disable_ips(intel_crtc
);
3747 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3748 buf
| DP_TEST_SINK_START
) < 0) {
3749 hsw_enable_ips(intel_crtc
);
3753 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3757 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3759 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3760 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3761 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3766 ret
= intel_dp_sink_crc_start(intel_dp
);
3771 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3773 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3774 DP_TEST_SINK_MISC
, &buf
) < 0) {
3778 count
= buf
& DP_TEST_COUNT_MASK
;
3780 } while (--attempts
&& count
== 0);
3782 if (attempts
== 0) {
3783 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3788 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3794 intel_dp_sink_crc_stop(intel_dp
);
3799 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3801 return drm_dp_dpcd_read(&intel_dp
->aux
,
3802 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3803 sink_irq_vector
, 1) == 1;
3807 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3811 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3813 sink_irq_vector
, 14);
3820 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3822 uint8_t test_result
= DP_TEST_ACK
;
3826 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3828 uint8_t test_result
= DP_TEST_NAK
;
3832 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3834 uint8_t test_result
= DP_TEST_NAK
;
3835 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3836 struct drm_connector
*connector
= &intel_connector
->base
;
3838 if (intel_connector
->detect_edid
== NULL
||
3839 connector
->edid_corrupt
||
3840 intel_dp
->aux
.i2c_defer_count
> 6) {
3841 /* Check EDID read for NACKs, DEFERs and corruption
3842 * (DP CTS 1.2 Core r1.1)
3843 * 4.2.2.4 : Failed EDID read, I2C_NAK
3844 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3845 * 4.2.2.6 : EDID corruption detected
3846 * Use failsafe mode for all cases
3848 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3849 intel_dp
->aux
.i2c_defer_count
> 0)
3850 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3851 intel_dp
->aux
.i2c_nack_count
,
3852 intel_dp
->aux
.i2c_defer_count
);
3853 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3855 struct edid
*block
= intel_connector
->detect_edid
;
3857 /* We have to write the checksum
3858 * of the last block read
3860 block
+= intel_connector
->detect_edid
->extensions
;
3862 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3863 DP_TEST_EDID_CHECKSUM
,
3866 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3868 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3869 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3872 /* Set test active flag here so userspace doesn't interrupt things */
3873 intel_dp
->compliance_test_active
= 1;
3878 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3880 uint8_t test_result
= DP_TEST_NAK
;
3884 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3886 uint8_t response
= DP_TEST_NAK
;
3890 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3892 DRM_DEBUG_KMS("Could not read test request from sink\n");
3897 case DP_TEST_LINK_TRAINING
:
3898 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3899 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3900 response
= intel_dp_autotest_link_training(intel_dp
);
3902 case DP_TEST_LINK_VIDEO_PATTERN
:
3903 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3904 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3905 response
= intel_dp_autotest_video_pattern(intel_dp
);
3907 case DP_TEST_LINK_EDID_READ
:
3908 DRM_DEBUG_KMS("EDID test requested\n");
3909 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3910 response
= intel_dp_autotest_edid(intel_dp
);
3912 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3913 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3914 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3915 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3918 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3923 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3927 DRM_DEBUG_KMS("Could not write test response to sink\n");
3931 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3935 if (intel_dp
->is_mst
) {
3940 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3944 /* check link status - esi[10] = 0x200c */
3945 if (intel_dp
->active_mst_links
&&
3946 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3947 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3948 intel_dp_start_link_train(intel_dp
);
3949 intel_dp_stop_link_train(intel_dp
);
3952 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3953 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3956 for (retry
= 0; retry
< 3; retry
++) {
3958 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3959 DP_SINK_COUNT_ESI
+1,
3966 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3968 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3976 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3977 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3978 intel_dp
->is_mst
= false;
3979 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3980 /* send a hotplug event */
3981 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3988 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3990 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3991 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3992 u8 link_status
[DP_LINK_STATUS_SIZE
];
3994 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3996 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3997 DRM_ERROR("Failed to get link status\n");
4001 if (!intel_encoder
->base
.crtc
)
4004 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4007 /* if link training is requested we should perform it always */
4008 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
4009 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
4010 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4011 intel_encoder
->base
.name
);
4012 intel_dp_start_link_train(intel_dp
);
4013 intel_dp_stop_link_train(intel_dp
);
4018 * According to DP spec
4021 * 2. Configure link according to Receiver Capabilities
4022 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4023 * 4. Check link status on receipt of hot-plug interrupt
4025 * intel_dp_short_pulse - handles short pulse interrupts
4026 * when full detection is not required.
4027 * Returns %true if short pulse is handled and full detection
4028 * is NOT required and %false otherwise.
4031 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4033 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4034 u8 sink_irq_vector
= 0;
4035 u8 old_sink_count
= intel_dp
->sink_count
;
4039 * Clearing compliance test variables to allow capturing
4040 * of values for next automated test request.
4042 intel_dp
->compliance_test_active
= 0;
4043 intel_dp
->compliance_test_type
= 0;
4044 intel_dp
->compliance_test_data
= 0;
4047 * Now read the DPCD to see if it's actually running
4048 * If the current value of sink count doesn't match with
4049 * the value that was stored earlier or dpcd read failed
4050 * we need to do full detection
4052 ret
= intel_dp_get_dpcd(intel_dp
);
4054 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4055 /* No need to proceed if we are going to do full detect */
4059 /* Try to read the source of the interrupt */
4060 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4061 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4062 sink_irq_vector
!= 0) {
4063 /* Clear interrupt source */
4064 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4065 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4068 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4069 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4070 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4071 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4074 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4075 intel_dp_check_link_status(intel_dp
);
4076 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4081 /* XXX this is probably wrong for multiple downstream ports */
4082 static enum drm_connector_status
4083 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4085 uint8_t *dpcd
= intel_dp
->dpcd
;
4088 if (!intel_dp_get_dpcd(intel_dp
))
4089 return connector_status_disconnected
;
4091 if (is_edp(intel_dp
))
4092 return connector_status_connected
;
4094 /* if there's no downstream port, we're done */
4095 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4096 return connector_status_connected
;
4098 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4099 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4100 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4102 return intel_dp
->sink_count
?
4103 connector_status_connected
: connector_status_disconnected
;
4106 if (intel_dp_can_mst(intel_dp
))
4107 return connector_status_connected
;
4109 /* If no HPD, poke DDC gently */
4110 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4111 return connector_status_connected
;
4113 /* Well we tried, say unknown for unreliable port types */
4114 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4115 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4116 if (type
== DP_DS_PORT_TYPE_VGA
||
4117 type
== DP_DS_PORT_TYPE_NON_EDID
)
4118 return connector_status_unknown
;
4120 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4121 DP_DWN_STRM_PORT_TYPE_MASK
;
4122 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4123 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4124 return connector_status_unknown
;
4127 /* Anything else is out of spec, warn and ignore */
4128 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4129 return connector_status_disconnected
;
4132 static enum drm_connector_status
4133 edp_detect(struct intel_dp
*intel_dp
)
4135 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4136 enum drm_connector_status status
;
4138 status
= intel_panel_detect(dev
);
4139 if (status
== connector_status_unknown
)
4140 status
= connector_status_connected
;
4145 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4146 struct intel_digital_port
*port
)
4150 switch (port
->port
) {
4154 bit
= SDE_PORTB_HOTPLUG
;
4157 bit
= SDE_PORTC_HOTPLUG
;
4160 bit
= SDE_PORTD_HOTPLUG
;
4163 MISSING_CASE(port
->port
);
4167 return I915_READ(SDEISR
) & bit
;
4170 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4171 struct intel_digital_port
*port
)
4175 switch (port
->port
) {
4179 bit
= SDE_PORTB_HOTPLUG_CPT
;
4182 bit
= SDE_PORTC_HOTPLUG_CPT
;
4185 bit
= SDE_PORTD_HOTPLUG_CPT
;
4188 bit
= SDE_PORTE_HOTPLUG_SPT
;
4191 MISSING_CASE(port
->port
);
4195 return I915_READ(SDEISR
) & bit
;
4198 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4199 struct intel_digital_port
*port
)
4203 switch (port
->port
) {
4205 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4208 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4211 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4214 MISSING_CASE(port
->port
);
4218 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4221 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4222 struct intel_digital_port
*port
)
4226 switch (port
->port
) {
4228 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4231 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4234 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4237 MISSING_CASE(port
->port
);
4241 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4244 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4245 struct intel_digital_port
*intel_dig_port
)
4247 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4251 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4254 bit
= BXT_DE_PORT_HP_DDIA
;
4257 bit
= BXT_DE_PORT_HP_DDIB
;
4260 bit
= BXT_DE_PORT_HP_DDIC
;
4267 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4271 * intel_digital_port_connected - is the specified port connected?
4272 * @dev_priv: i915 private structure
4273 * @port: the port to test
4275 * Return %true if @port is connected, %false otherwise.
4277 static bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4278 struct intel_digital_port
*port
)
4280 if (HAS_PCH_IBX(dev_priv
))
4281 return ibx_digital_port_connected(dev_priv
, port
);
4282 else if (HAS_PCH_SPLIT(dev_priv
))
4283 return cpt_digital_port_connected(dev_priv
, port
);
4284 else if (IS_BROXTON(dev_priv
))
4285 return bxt_digital_port_connected(dev_priv
, port
);
4286 else if (IS_GM45(dev_priv
))
4287 return gm45_digital_port_connected(dev_priv
, port
);
4289 return g4x_digital_port_connected(dev_priv
, port
);
4292 static struct edid
*
4293 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4295 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4297 /* use cached edid if we have one */
4298 if (intel_connector
->edid
) {
4300 if (IS_ERR(intel_connector
->edid
))
4303 return drm_edid_duplicate(intel_connector
->edid
);
4305 return drm_get_edid(&intel_connector
->base
,
4306 &intel_dp
->aux
.ddc
);
4310 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4312 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4315 intel_dp_unset_edid(intel_dp
);
4316 edid
= intel_dp_get_edid(intel_dp
);
4317 intel_connector
->detect_edid
= edid
;
4319 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4320 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4322 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4326 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4328 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4330 kfree(intel_connector
->detect_edid
);
4331 intel_connector
->detect_edid
= NULL
;
4333 intel_dp
->has_audio
= false;
4336 static enum drm_connector_status
4337 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4339 struct drm_connector
*connector
= &intel_connector
->base
;
4340 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4341 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4342 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4343 struct drm_device
*dev
= connector
->dev
;
4344 enum drm_connector_status status
;
4345 enum intel_display_power_domain power_domain
;
4346 u8 sink_irq_vector
= 0;
4348 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4349 intel_display_power_get(to_i915(dev
), power_domain
);
4351 /* Can't disconnect eDP, but you can close the lid... */
4352 if (is_edp(intel_dp
))
4353 status
= edp_detect(intel_dp
);
4354 else if (intel_digital_port_connected(to_i915(dev
),
4355 dp_to_dig_port(intel_dp
)))
4356 status
= intel_dp_detect_dpcd(intel_dp
);
4358 status
= connector_status_disconnected
;
4360 if (status
== connector_status_disconnected
) {
4361 intel_dp
->compliance_test_active
= 0;
4362 intel_dp
->compliance_test_type
= 0;
4363 intel_dp
->compliance_test_data
= 0;
4365 if (intel_dp
->is_mst
) {
4366 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4368 intel_dp
->mst_mgr
.mst_state
);
4369 intel_dp
->is_mst
= false;
4370 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4377 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4378 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4380 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4381 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4382 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4384 intel_dp_print_rates(intel_dp
);
4386 intel_dp_probe_oui(intel_dp
);
4388 intel_dp_print_hw_revision(intel_dp
);
4389 intel_dp_print_sw_revision(intel_dp
);
4391 intel_dp_configure_mst(intel_dp
);
4393 if (intel_dp
->is_mst
) {
4395 * If we are in MST mode then this connector
4396 * won't appear connected or have anything
4399 status
= connector_status_disconnected
;
4401 } else if (connector
->status
== connector_status_connected
) {
4403 * If display was connected already and is still connected
4404 * check links status, there has been known issues of
4405 * link loss triggerring long pulse!!!!
4407 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4408 intel_dp_check_link_status(intel_dp
);
4409 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4414 * Clearing NACK and defer counts to get their exact values
4415 * while reading EDID which are required by Compliance tests
4416 * 4.2.2.4 and 4.2.2.5
4418 intel_dp
->aux
.i2c_nack_count
= 0;
4419 intel_dp
->aux
.i2c_defer_count
= 0;
4421 intel_dp_set_edid(intel_dp
);
4422 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4423 status
= connector_status_connected
;
4424 intel_dp
->detect_done
= true;
4426 /* Try to read the source of the interrupt */
4427 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4428 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4429 sink_irq_vector
!= 0) {
4430 /* Clear interrupt source */
4431 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4432 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4435 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4436 intel_dp_handle_test_request(intel_dp
);
4437 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4438 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4442 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4443 intel_dp_unset_edid(intel_dp
);
4445 intel_display_power_put(to_i915(dev
), power_domain
);
4449 static enum drm_connector_status
4450 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4452 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4453 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4454 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4455 enum drm_connector_status status
= connector
->status
;
4457 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4458 connector
->base
.id
, connector
->name
);
4460 if (intel_dp
->is_mst
) {
4461 /* MST devices are disconnected from a monitor POV */
4462 intel_dp_unset_edid(intel_dp
);
4463 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4464 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4465 return connector_status_disconnected
;
4468 /* If full detect is not performed yet, do a full detect */
4469 if (!intel_dp
->detect_done
)
4470 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4472 intel_dp
->detect_done
= false;
4478 intel_dp_force(struct drm_connector
*connector
)
4480 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4481 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4482 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4483 enum intel_display_power_domain power_domain
;
4485 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4486 connector
->base
.id
, connector
->name
);
4487 intel_dp_unset_edid(intel_dp
);
4489 if (connector
->status
!= connector_status_connected
)
4492 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4493 intel_display_power_get(dev_priv
, power_domain
);
4495 intel_dp_set_edid(intel_dp
);
4497 intel_display_power_put(dev_priv
, power_domain
);
4499 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4500 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4503 static int intel_dp_get_modes(struct drm_connector
*connector
)
4505 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4508 edid
= intel_connector
->detect_edid
;
4510 int ret
= intel_connector_update_modes(connector
, edid
);
4515 /* if eDP has no EDID, fall back to fixed mode */
4516 if (is_edp(intel_attached_dp(connector
)) &&
4517 intel_connector
->panel
.fixed_mode
) {
4518 struct drm_display_mode
*mode
;
4520 mode
= drm_mode_duplicate(connector
->dev
,
4521 intel_connector
->panel
.fixed_mode
);
4523 drm_mode_probed_add(connector
, mode
);
4532 intel_dp_detect_audio(struct drm_connector
*connector
)
4534 bool has_audio
= false;
4537 edid
= to_intel_connector(connector
)->detect_edid
;
4539 has_audio
= drm_detect_monitor_audio(edid
);
4545 intel_dp_set_property(struct drm_connector
*connector
,
4546 struct drm_property
*property
,
4549 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
4550 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4551 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4552 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4555 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4559 if (property
== dev_priv
->force_audio_property
) {
4563 if (i
== intel_dp
->force_audio
)
4566 intel_dp
->force_audio
= i
;
4568 if (i
== HDMI_AUDIO_AUTO
)
4569 has_audio
= intel_dp_detect_audio(connector
);
4571 has_audio
= (i
== HDMI_AUDIO_ON
);
4573 if (has_audio
== intel_dp
->has_audio
)
4576 intel_dp
->has_audio
= has_audio
;
4580 if (property
== dev_priv
->broadcast_rgb_property
) {
4581 bool old_auto
= intel_dp
->color_range_auto
;
4582 bool old_range
= intel_dp
->limited_color_range
;
4585 case INTEL_BROADCAST_RGB_AUTO
:
4586 intel_dp
->color_range_auto
= true;
4588 case INTEL_BROADCAST_RGB_FULL
:
4589 intel_dp
->color_range_auto
= false;
4590 intel_dp
->limited_color_range
= false;
4592 case INTEL_BROADCAST_RGB_LIMITED
:
4593 intel_dp
->color_range_auto
= false;
4594 intel_dp
->limited_color_range
= true;
4600 if (old_auto
== intel_dp
->color_range_auto
&&
4601 old_range
== intel_dp
->limited_color_range
)
4607 if (is_edp(intel_dp
) &&
4608 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4609 if (val
== DRM_MODE_SCALE_NONE
) {
4610 DRM_DEBUG_KMS("no scaling not supported\n");
4613 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4614 val
== DRM_MODE_SCALE_CENTER
) {
4615 DRM_DEBUG_KMS("centering not supported\n");
4619 if (intel_connector
->panel
.fitting_mode
== val
) {
4620 /* the eDP scaling property is not changed */
4623 intel_connector
->panel
.fitting_mode
= val
;
4631 if (intel_encoder
->base
.crtc
)
4632 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4638 intel_dp_connector_register(struct drm_connector
*connector
)
4640 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4643 ret
= intel_connector_register(connector
);
4647 i915_debugfs_connector_add(connector
);
4649 DRM_DEBUG_KMS("registering %s bus for %s\n",
4650 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4652 intel_dp
->aux
.dev
= connector
->kdev
;
4653 return drm_dp_aux_register(&intel_dp
->aux
);
4657 intel_dp_connector_unregister(struct drm_connector
*connector
)
4659 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4660 intel_connector_unregister(connector
);
4664 intel_dp_connector_destroy(struct drm_connector
*connector
)
4666 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4668 kfree(intel_connector
->detect_edid
);
4670 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4671 kfree(intel_connector
->edid
);
4673 /* Can't call is_edp() since the encoder may have been destroyed
4675 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4676 intel_panel_fini(&intel_connector
->panel
);
4678 drm_connector_cleanup(connector
);
4682 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4684 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4685 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4687 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4688 if (is_edp(intel_dp
)) {
4689 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4691 * vdd might still be enabled do to the delayed vdd off.
4692 * Make sure vdd is actually turned off here.
4695 edp_panel_vdd_off_sync(intel_dp
);
4696 pps_unlock(intel_dp
);
4698 if (intel_dp
->edp_notifier
.notifier_call
) {
4699 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4700 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4704 intel_dp_aux_fini(intel_dp
);
4706 drm_encoder_cleanup(encoder
);
4707 kfree(intel_dig_port
);
4710 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4712 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4714 if (!is_edp(intel_dp
))
4718 * vdd might still be enabled do to the delayed vdd off.
4719 * Make sure vdd is actually turned off here.
4721 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4723 edp_panel_vdd_off_sync(intel_dp
);
4724 pps_unlock(intel_dp
);
4727 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4729 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4730 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4731 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4732 enum intel_display_power_domain power_domain
;
4734 lockdep_assert_held(&dev_priv
->pps_mutex
);
4736 if (!edp_have_panel_vdd(intel_dp
))
4740 * The VDD bit needs a power domain reference, so if the bit is
4741 * already enabled when we boot or resume, grab this reference and
4742 * schedule a vdd off, so we don't hold on to the reference
4745 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4746 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4747 intel_display_power_get(dev_priv
, power_domain
);
4749 edp_panel_vdd_schedule_off(intel_dp
);
4752 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4754 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4755 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4757 if (!HAS_DDI(dev_priv
))
4758 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4760 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4765 /* Reinit the power sequencer, in case BIOS did something with it. */
4766 intel_dp_pps_init(encoder
->dev
, intel_dp
);
4767 intel_edp_panel_vdd_sanitize(intel_dp
);
4769 pps_unlock(intel_dp
);
4772 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4773 .dpms
= drm_atomic_helper_connector_dpms
,
4774 .detect
= intel_dp_detect
,
4775 .force
= intel_dp_force
,
4776 .fill_modes
= drm_helper_probe_single_connector_modes
,
4777 .set_property
= intel_dp_set_property
,
4778 .atomic_get_property
= intel_connector_atomic_get_property
,
4779 .late_register
= intel_dp_connector_register
,
4780 .early_unregister
= intel_dp_connector_unregister
,
4781 .destroy
= intel_dp_connector_destroy
,
4782 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4783 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4786 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4787 .get_modes
= intel_dp_get_modes
,
4788 .mode_valid
= intel_dp_mode_valid
,
4791 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4792 .reset
= intel_dp_encoder_reset
,
4793 .destroy
= intel_dp_encoder_destroy
,
4797 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4799 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4800 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4801 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4802 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4803 enum intel_display_power_domain power_domain
;
4804 enum irqreturn ret
= IRQ_NONE
;
4806 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4807 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4808 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
4810 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4812 * vdd off can generate a long pulse on eDP which
4813 * would require vdd on to handle it, and thus we
4814 * would end up in an endless cycle of
4815 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4817 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4818 port_name(intel_dig_port
->port
));
4822 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4823 port_name(intel_dig_port
->port
),
4824 long_hpd
? "long" : "short");
4827 intel_dp
->detect_done
= false;
4831 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4832 intel_display_power_get(dev_priv
, power_domain
);
4834 if (intel_dp
->is_mst
) {
4835 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4837 * If we were in MST mode, and device is not
4838 * there, get out of MST mode
4840 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4841 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4842 intel_dp
->is_mst
= false;
4843 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4845 intel_dp
->detect_done
= false;
4850 if (!intel_dp
->is_mst
) {
4851 if (!intel_dp_short_pulse(intel_dp
)) {
4852 intel_dp
->detect_done
= false;
4860 intel_display_power_put(dev_priv
, power_domain
);
4865 /* check the VBT to see whether the eDP is on another port */
4866 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4868 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4871 * eDP not supported on g4x. so bail out early just
4872 * for a bit extra safety in case the VBT is bonkers.
4874 if (INTEL_INFO(dev
)->gen
< 5)
4880 return intel_bios_is_port_edp(dev_priv
, port
);
4884 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4886 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4888 intel_attach_force_audio_property(connector
);
4889 intel_attach_broadcast_rgb_property(connector
);
4890 intel_dp
->color_range_auto
= true;
4892 if (is_edp(intel_dp
)) {
4893 drm_mode_create_scaling_mode_property(connector
->dev
);
4894 drm_object_attach_property(
4896 connector
->dev
->mode_config
.scaling_mode_property
,
4897 DRM_MODE_SCALE_ASPECT
);
4898 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4902 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4904 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4905 intel_dp
->last_power_on
= jiffies
;
4906 intel_dp
->last_backlight_off
= jiffies
;
4910 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4911 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4913 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4914 struct pps_registers regs
;
4916 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4918 /* Workaround: Need to write PP_CONTROL with the unlock key as
4919 * the very first thing. */
4920 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4922 pp_on
= I915_READ(regs
.pp_on
);
4923 pp_off
= I915_READ(regs
.pp_off
);
4924 if (!IS_BROXTON(dev_priv
)) {
4925 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4926 pp_div
= I915_READ(regs
.pp_div
);
4929 /* Pull timing values out of registers */
4930 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4931 PANEL_POWER_UP_DELAY_SHIFT
;
4933 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4934 PANEL_LIGHT_ON_DELAY_SHIFT
;
4936 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4937 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4939 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4940 PANEL_POWER_DOWN_DELAY_SHIFT
;
4942 if (IS_BROXTON(dev_priv
)) {
4943 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4944 BXT_POWER_CYCLE_DELAY_SHIFT
;
4946 seq
->t11_t12
= (tmp
- 1) * 1000;
4950 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4951 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4956 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
4958 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4960 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
4964 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
4965 struct intel_dp
*intel_dp
)
4967 struct edp_power_seq hw
;
4968 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
4970 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
4972 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
4973 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
4974 DRM_ERROR("PPS state mismatch\n");
4975 intel_pps_dump_state("sw", sw
);
4976 intel_pps_dump_state("hw", &hw
);
4981 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4982 struct intel_dp
*intel_dp
)
4984 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4985 struct edp_power_seq cur
, vbt
, spec
,
4986 *final
= &intel_dp
->pps_delays
;
4988 lockdep_assert_held(&dev_priv
->pps_mutex
);
4990 /* already initialized? */
4991 if (final
->t11_t12
!= 0)
4994 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
4996 intel_pps_dump_state("cur", &cur
);
4998 vbt
= dev_priv
->vbt
.edp
.pps
;
5000 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5001 * our hw here, which are all in 100usec. */
5002 spec
.t1_t3
= 210 * 10;
5003 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5004 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5005 spec
.t10
= 500 * 10;
5006 /* This one is special and actually in units of 100ms, but zero
5007 * based in the hw (so we need to add 100 ms). But the sw vbt
5008 * table multiplies it with 1000 to make it in units of 100usec,
5010 spec
.t11_t12
= (510 + 100) * 10;
5012 intel_pps_dump_state("vbt", &vbt
);
5014 /* Use the max of the register settings and vbt. If both are
5015 * unset, fall back to the spec limits. */
5016 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5018 max(cur.field, vbt.field))
5019 assign_final(t1_t3
);
5023 assign_final(t11_t12
);
5026 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5027 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5028 intel_dp
->backlight_on_delay
= get_delay(t8
);
5029 intel_dp
->backlight_off_delay
= get_delay(t9
);
5030 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5031 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5034 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5035 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5036 intel_dp
->panel_power_cycle_delay
);
5038 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5039 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5042 * We override the HW backlight delays to 1 because we do manual waits
5043 * on them. For T8, even BSpec recommends doing it. For T9, if we
5044 * don't do this, we'll end up waiting for the backlight off delay
5045 * twice: once when we do the manual sleep, and once when we disable
5046 * the panel and wait for the PP_STATUS bit to become zero.
5053 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5054 struct intel_dp
*intel_dp
)
5056 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5057 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5058 int div
= dev_priv
->rawclk_freq
/ 1000;
5059 struct pps_registers regs
;
5060 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5061 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5063 lockdep_assert_held(&dev_priv
->pps_mutex
);
5065 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5067 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5068 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5069 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5070 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5071 /* Compute the divisor for the pp clock, simply match the Bspec
5073 if (IS_BROXTON(dev
)) {
5074 pp_div
= I915_READ(regs
.pp_ctrl
);
5075 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5076 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5077 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5079 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5080 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5081 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5084 /* Haswell doesn't have any port selection bits for the panel
5085 * power sequencer any more. */
5086 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5087 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5088 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5090 port_sel
= PANEL_PORT_SELECT_DPA
;
5092 port_sel
= PANEL_PORT_SELECT_DPD
;
5097 I915_WRITE(regs
.pp_on
, pp_on
);
5098 I915_WRITE(regs
.pp_off
, pp_off
);
5099 if (IS_BROXTON(dev
))
5100 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5102 I915_WRITE(regs
.pp_div
, pp_div
);
5104 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5105 I915_READ(regs
.pp_on
),
5106 I915_READ(regs
.pp_off
),
5108 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5109 I915_READ(regs
.pp_div
));
5112 static void intel_dp_pps_init(struct drm_device
*dev
,
5113 struct intel_dp
*intel_dp
)
5115 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5116 vlv_initial_power_sequencer_setup(intel_dp
);
5118 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5119 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5124 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5125 * @dev_priv: i915 device
5126 * @crtc_state: a pointer to the active intel_crtc_state
5127 * @refresh_rate: RR to be programmed
5129 * This function gets called when refresh rate (RR) has to be changed from
5130 * one frequency to another. Switches can be between high and low RR
5131 * supported by the panel or to any other RR based on media playback (in
5132 * this case, RR value needs to be passed from user space).
5134 * The caller of this function needs to take a lock on dev_priv->drrs.
5136 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5137 struct intel_crtc_state
*crtc_state
,
5140 struct intel_encoder
*encoder
;
5141 struct intel_digital_port
*dig_port
= NULL
;
5142 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5143 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5144 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5146 if (refresh_rate
<= 0) {
5147 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5151 if (intel_dp
== NULL
) {
5152 DRM_DEBUG_KMS("DRRS not supported.\n");
5157 * FIXME: This needs proper synchronization with psr state for some
5158 * platforms that cannot have PSR and DRRS enabled at the same time.
5161 dig_port
= dp_to_dig_port(intel_dp
);
5162 encoder
= &dig_port
->base
;
5163 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5166 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5170 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5171 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5175 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5177 index
= DRRS_LOW_RR
;
5179 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5181 "DRRS requested for previously set RR...ignoring\n");
5185 if (!crtc_state
->base
.active
) {
5186 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5190 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5193 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5196 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5200 DRM_ERROR("Unsupported refreshrate type\n");
5202 } else if (INTEL_GEN(dev_priv
) > 6) {
5203 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5206 val
= I915_READ(reg
);
5207 if (index
> DRRS_HIGH_RR
) {
5208 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5209 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5211 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5213 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5214 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5216 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5218 I915_WRITE(reg
, val
);
5221 dev_priv
->drrs
.refresh_rate_type
= index
;
5223 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5227 * intel_edp_drrs_enable - init drrs struct if supported
5228 * @intel_dp: DP struct
5229 * @crtc_state: A pointer to the active crtc state.
5231 * Initializes frontbuffer_bits and drrs.dp
5233 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5234 struct intel_crtc_state
*crtc_state
)
5236 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5237 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5239 if (!crtc_state
->has_drrs
) {
5240 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5244 mutex_lock(&dev_priv
->drrs
.mutex
);
5245 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5246 DRM_ERROR("DRRS already enabled\n");
5250 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5252 dev_priv
->drrs
.dp
= intel_dp
;
5255 mutex_unlock(&dev_priv
->drrs
.mutex
);
5259 * intel_edp_drrs_disable - Disable DRRS
5260 * @intel_dp: DP struct
5261 * @old_crtc_state: Pointer to old crtc_state.
5264 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5265 struct intel_crtc_state
*old_crtc_state
)
5267 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5268 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5270 if (!old_crtc_state
->has_drrs
)
5273 mutex_lock(&dev_priv
->drrs
.mutex
);
5274 if (!dev_priv
->drrs
.dp
) {
5275 mutex_unlock(&dev_priv
->drrs
.mutex
);
5279 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5280 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5281 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5283 dev_priv
->drrs
.dp
= NULL
;
5284 mutex_unlock(&dev_priv
->drrs
.mutex
);
5286 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5289 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5291 struct drm_i915_private
*dev_priv
=
5292 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5293 struct intel_dp
*intel_dp
;
5295 mutex_lock(&dev_priv
->drrs
.mutex
);
5297 intel_dp
= dev_priv
->drrs
.dp
;
5303 * The delayed work can race with an invalidate hence we need to
5307 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5310 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5311 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5313 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5314 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5318 mutex_unlock(&dev_priv
->drrs
.mutex
);
5322 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5323 * @dev_priv: i915 device
5324 * @frontbuffer_bits: frontbuffer plane tracking bits
5326 * This function gets called everytime rendering on the given planes start.
5327 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5329 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5331 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5332 unsigned int frontbuffer_bits
)
5334 struct drm_crtc
*crtc
;
5337 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5340 cancel_delayed_work(&dev_priv
->drrs
.work
);
5342 mutex_lock(&dev_priv
->drrs
.mutex
);
5343 if (!dev_priv
->drrs
.dp
) {
5344 mutex_unlock(&dev_priv
->drrs
.mutex
);
5348 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5349 pipe
= to_intel_crtc(crtc
)->pipe
;
5351 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5352 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5354 /* invalidate means busy screen hence upclock */
5355 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5356 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5357 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5359 mutex_unlock(&dev_priv
->drrs
.mutex
);
5363 * intel_edp_drrs_flush - Restart Idleness DRRS
5364 * @dev_priv: i915 device
5365 * @frontbuffer_bits: frontbuffer plane tracking bits
5367 * This function gets called every time rendering on the given planes has
5368 * completed or flip on a crtc is completed. So DRRS should be upclocked
5369 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5370 * if no other planes are dirty.
5372 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5374 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5375 unsigned int frontbuffer_bits
)
5377 struct drm_crtc
*crtc
;
5380 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5383 cancel_delayed_work(&dev_priv
->drrs
.work
);
5385 mutex_lock(&dev_priv
->drrs
.mutex
);
5386 if (!dev_priv
->drrs
.dp
) {
5387 mutex_unlock(&dev_priv
->drrs
.mutex
);
5391 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5392 pipe
= to_intel_crtc(crtc
)->pipe
;
5394 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5395 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5397 /* flush means busy screen hence upclock */
5398 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5399 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5400 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5403 * flush also means no more activity hence schedule downclock, if all
5404 * other fbs are quiescent too
5406 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5407 schedule_delayed_work(&dev_priv
->drrs
.work
,
5408 msecs_to_jiffies(1000));
5409 mutex_unlock(&dev_priv
->drrs
.mutex
);
5413 * DOC: Display Refresh Rate Switching (DRRS)
5415 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5416 * which enables swtching between low and high refresh rates,
5417 * dynamically, based on the usage scenario. This feature is applicable
5418 * for internal panels.
5420 * Indication that the panel supports DRRS is given by the panel EDID, which
5421 * would list multiple refresh rates for one resolution.
5423 * DRRS is of 2 types - static and seamless.
5424 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5425 * (may appear as a blink on screen) and is used in dock-undock scenario.
5426 * Seamless DRRS involves changing RR without any visual effect to the user
5427 * and can be used during normal system usage. This is done by programming
5428 * certain registers.
5430 * Support for static/seamless DRRS may be indicated in the VBT based on
5431 * inputs from the panel spec.
5433 * DRRS saves power by switching to low RR based on usage scenarios.
5435 * The implementation is based on frontbuffer tracking implementation. When
5436 * there is a disturbance on the screen triggered by user activity or a periodic
5437 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5438 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5441 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5442 * and intel_edp_drrs_flush() are called.
5444 * DRRS can be further extended to support other internal panels and also
5445 * the scenario of video playback wherein RR is set based on the rate
5446 * requested by userspace.
5450 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5451 * @intel_connector: eDP connector
5452 * @fixed_mode: preferred mode of panel
5454 * This function is called only once at driver load to initialize basic
5458 * Downclock mode if panel supports it, else return NULL.
5459 * DRRS support is determined by the presence of downclock mode (apart
5460 * from VBT setting).
5462 static struct drm_display_mode
*
5463 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5464 struct drm_display_mode
*fixed_mode
)
5466 struct drm_connector
*connector
= &intel_connector
->base
;
5467 struct drm_device
*dev
= connector
->dev
;
5468 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5469 struct drm_display_mode
*downclock_mode
= NULL
;
5471 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5472 mutex_init(&dev_priv
->drrs
.mutex
);
5474 if (INTEL_INFO(dev
)->gen
<= 6) {
5475 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5479 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5480 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5484 downclock_mode
= intel_find_panel_downclock
5485 (dev
, fixed_mode
, connector
);
5487 if (!downclock_mode
) {
5488 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5492 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5494 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5495 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5496 return downclock_mode
;
5499 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5500 struct intel_connector
*intel_connector
)
5502 struct drm_connector
*connector
= &intel_connector
->base
;
5503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5504 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5505 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5506 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5507 struct drm_display_mode
*fixed_mode
= NULL
;
5508 struct drm_display_mode
*downclock_mode
= NULL
;
5510 struct drm_display_mode
*scan
;
5512 enum pipe pipe
= INVALID_PIPE
;
5514 if (!is_edp(intel_dp
))
5518 * On IBX/CPT we may get here with LVDS already registered. Since the
5519 * driver uses the only internal power sequencer available for both
5520 * eDP and LVDS bail out early in this case to prevent interfering
5521 * with an already powered-on LVDS power sequencer.
5523 if (intel_get_lvds_encoder(dev
)) {
5524 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5525 DRM_INFO("LVDS was detected, not registering eDP\n");
5532 intel_dp_init_panel_power_timestamps(intel_dp
);
5533 intel_dp_pps_init(dev
, intel_dp
);
5534 intel_edp_panel_vdd_sanitize(intel_dp
);
5536 pps_unlock(intel_dp
);
5538 /* Cache DPCD and EDID for edp. */
5539 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5542 /* if this fails, presume the device is a ghost */
5543 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5547 mutex_lock(&dev
->mode_config
.mutex
);
5548 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5550 if (drm_add_edid_modes(connector
, edid
)) {
5551 drm_mode_connector_update_edid_property(connector
,
5553 drm_edid_to_eld(connector
, edid
);
5556 edid
= ERR_PTR(-EINVAL
);
5559 edid
= ERR_PTR(-ENOENT
);
5561 intel_connector
->edid
= edid
;
5563 /* prefer fixed mode from EDID if available */
5564 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5565 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5566 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5567 downclock_mode
= intel_dp_drrs_init(
5568 intel_connector
, fixed_mode
);
5573 /* fallback to VBT if available for eDP */
5574 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5575 fixed_mode
= drm_mode_duplicate(dev
,
5576 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5578 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5579 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5580 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5583 mutex_unlock(&dev
->mode_config
.mutex
);
5585 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5586 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5587 register_reboot_notifier(&intel_dp
->edp_notifier
);
5590 * Figure out the current pipe for the initial backlight setup.
5591 * If the current pipe isn't valid, try the PPS pipe, and if that
5592 * fails just assume pipe A.
5594 if (IS_CHERRYVIEW(dev
))
5595 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5597 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5599 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5600 pipe
= intel_dp
->pps_pipe
;
5602 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5605 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5609 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5610 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5611 intel_panel_setup_backlight(connector
, pipe
);
5616 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5618 * vdd might still be enabled do to the delayed vdd off.
5619 * Make sure vdd is actually turned off here.
5622 edp_panel_vdd_off_sync(intel_dp
);
5623 pps_unlock(intel_dp
);
5629 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5630 struct intel_connector
*intel_connector
)
5632 struct drm_connector
*connector
= &intel_connector
->base
;
5633 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5634 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5635 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5636 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5637 enum port port
= intel_dig_port
->port
;
5640 if (WARN(intel_dig_port
->max_lanes
< 1,
5641 "Not enough lanes (%d) for DP on port %c\n",
5642 intel_dig_port
->max_lanes
, port_name(port
)))
5645 intel_dp
->pps_pipe
= INVALID_PIPE
;
5647 /* intel_dp vfuncs */
5648 if (INTEL_INFO(dev
)->gen
>= 9)
5649 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5650 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5651 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5652 else if (HAS_PCH_SPLIT(dev
))
5653 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5655 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5657 if (INTEL_INFO(dev
)->gen
>= 9)
5658 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5660 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5662 if (HAS_DDI(dev_priv
))
5663 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5665 /* Preserve the current hw state. */
5666 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5667 intel_dp
->attached_connector
= intel_connector
;
5669 if (intel_dp_is_edp(dev
, port
))
5670 type
= DRM_MODE_CONNECTOR_eDP
;
5672 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5675 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5676 * for DP the encoder type can be set by the caller to
5677 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5679 if (type
== DRM_MODE_CONNECTOR_eDP
)
5680 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5682 /* eDP only on port B and/or C on vlv/chv */
5683 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5684 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5687 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5688 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5691 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5692 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5694 connector
->interlace_allowed
= true;
5695 connector
->doublescan_allowed
= 0;
5697 intel_dp_aux_init(intel_dp
);
5699 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5700 edp_panel_vdd_work
);
5702 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5704 if (HAS_DDI(dev_priv
))
5705 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5707 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5709 /* Set up the hotplug pin. */
5712 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5715 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5716 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5717 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5720 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5723 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5726 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5732 /* init MST on ports that can support it */
5733 if (HAS_DP_MST(dev
) && !is_edp(intel_dp
) &&
5734 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5735 intel_dp_mst_encoder_init(intel_dig_port
,
5736 intel_connector
->base
.base
.id
);
5738 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5739 intel_dp_aux_fini(intel_dp
);
5740 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5744 intel_dp_add_properties(intel_dp
, connector
);
5746 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5747 * 0xd. Failure to do so will result in spurious interrupts being
5748 * generated on the port when a cable is not attached.
5750 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5751 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5752 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5758 drm_connector_cleanup(connector
);
5763 bool intel_dp_init(struct drm_device
*dev
,
5764 i915_reg_t output_reg
,
5767 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5768 struct intel_digital_port
*intel_dig_port
;
5769 struct intel_encoder
*intel_encoder
;
5770 struct drm_encoder
*encoder
;
5771 struct intel_connector
*intel_connector
;
5773 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5774 if (!intel_dig_port
)
5777 intel_connector
= intel_connector_alloc();
5778 if (!intel_connector
)
5779 goto err_connector_alloc
;
5781 intel_encoder
= &intel_dig_port
->base
;
5782 encoder
= &intel_encoder
->base
;
5784 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5785 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5786 goto err_encoder_init
;
5788 intel_encoder
->compute_config
= intel_dp_compute_config
;
5789 intel_encoder
->disable
= intel_disable_dp
;
5790 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5791 intel_encoder
->get_config
= intel_dp_get_config
;
5792 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5793 if (IS_CHERRYVIEW(dev
)) {
5794 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5795 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5796 intel_encoder
->enable
= vlv_enable_dp
;
5797 intel_encoder
->post_disable
= chv_post_disable_dp
;
5798 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5799 } else if (IS_VALLEYVIEW(dev
)) {
5800 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5801 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5802 intel_encoder
->enable
= vlv_enable_dp
;
5803 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5805 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5806 intel_encoder
->enable
= g4x_enable_dp
;
5807 if (INTEL_INFO(dev
)->gen
>= 5)
5808 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5811 intel_dig_port
->port
= port
;
5812 intel_dig_port
->dp
.output_reg
= output_reg
;
5813 intel_dig_port
->max_lanes
= 4;
5815 intel_encoder
->type
= INTEL_OUTPUT_DP
;
5816 if (IS_CHERRYVIEW(dev
)) {
5818 intel_encoder
->crtc_mask
= 1 << 2;
5820 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5822 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5824 intel_encoder
->cloneable
= 0;
5825 intel_encoder
->port
= port
;
5827 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5828 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5830 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5831 goto err_init_connector
;
5836 drm_encoder_cleanup(encoder
);
5838 kfree(intel_connector
);
5839 err_connector_alloc
:
5840 kfree(intel_dig_port
);
5844 void intel_dp_mst_suspend(struct drm_device
*dev
)
5846 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5850 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5851 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5853 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5856 if (intel_dig_port
->dp
.is_mst
)
5857 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5861 void intel_dp_mst_resume(struct drm_device
*dev
)
5863 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5866 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5867 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5870 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5873 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5875 intel_dp_check_mst_status(&intel_dig_port
->dp
);