2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
45 #define DP_DPRX_ESI_LEN 14
47 /* Compliance test status bits */
48 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
49 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
51 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
58 static const struct dp_link_dpll gen4_dpll
[] = {
60 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
62 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
65 static const struct dp_link_dpll pch_dpll
[] = {
67 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
69 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
72 static const struct dp_link_dpll vlv_dpll
[] = {
74 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
76 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
80 * CHV supports eDP 1.4 that have more link rates.
81 * Below only provides the fixed rate but exclude variable rate.
83 static const struct dp_link_dpll chv_dpll
[] = {
85 * CHV requires to program fractional division for m2.
86 * m2 is stored in fixed point format using formula below
87 * (m2_int << 22) | m2_fraction
89 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
90 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
91 { 270000, /* m2_int = 27, m2_fraction = 0 */
92 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
93 { 540000, /* m2_int = 27, m2_fraction = 0 */
94 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
97 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
98 324000, 432000, 540000 };
99 static const int skl_rates
[] = { 162000, 216000, 270000,
100 324000, 432000, 540000 };
101 static const int cnl_rates
[] = { 162000, 216000, 270000,
102 324000, 432000, 540000,
104 static const int default_rates
[] = { 162000, 270000, 540000 };
107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
108 * @intel_dp: DP struct
110 * If a CPU or PCH DP output is attached to an eDP panel, this function
111 * will return true, and false otherwise.
113 bool intel_dp_is_edp(struct intel_dp
*intel_dp
)
115 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
117 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
120 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
122 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
124 return intel_dig_port
->base
.base
.dev
;
127 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
129 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
132 static void intel_dp_link_down(struct intel_encoder
*encoder
,
133 const struct intel_crtc_state
*old_crtc_state
);
134 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
135 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
136 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
137 const struct intel_crtc_state
*crtc_state
);
138 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
140 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
142 /* update sink rates from dpcd */
143 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
147 max_rate
= drm_dp_bw_code_to_link_rate(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
149 for (i
= 0; i
< ARRAY_SIZE(default_rates
); i
++) {
150 if (default_rates
[i
] > max_rate
)
152 intel_dp
->sink_rates
[i
] = default_rates
[i
];
155 intel_dp
->num_sink_rates
= i
;
158 /* Theoretical max between source and sink */
159 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
161 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
164 /* Theoretical max between source and sink */
165 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
167 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
168 int source_max
= intel_dig_port
->max_lanes
;
169 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
171 return min(source_max
, sink_max
);
174 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
176 return intel_dp
->max_link_lane_count
;
180 intel_dp_link_required(int pixel_clock
, int bpp
)
182 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
183 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
187 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
189 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
190 * link rate that is generally expressed in Gbps. Since, 8 bits of data
191 * is transmitted every LS_Clk per lane, there is no need to account for
192 * the channel encoding that is done in the PHY layer here.
195 return max_link_clock
* max_lanes
;
199 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
201 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
202 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
203 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
204 int max_dotclk
= dev_priv
->max_dotclk_freq
;
207 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
209 if (type
!= DP_DS_PORT_TYPE_VGA
)
212 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
213 intel_dp
->downstream_ports
);
215 if (ds_max_dotclk
!= 0)
216 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
222 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
224 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
225 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
226 enum port port
= dig_port
->base
.port
;
227 const int *source_rates
;
231 /* This should only be done once */
232 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
234 if (IS_GEN9_LP(dev_priv
)) {
235 source_rates
= bxt_rates
;
236 size
= ARRAY_SIZE(bxt_rates
);
237 } else if (IS_CANNONLAKE(dev_priv
)) {
238 source_rates
= cnl_rates
;
239 size
= ARRAY_SIZE(cnl_rates
);
240 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
241 if (port
== PORT_A
|| port
== PORT_D
||
242 voltage
== VOLTAGE_INFO_0_85V
)
244 } else if (IS_GEN9_BC(dev_priv
)) {
245 source_rates
= skl_rates
;
246 size
= ARRAY_SIZE(skl_rates
);
247 } else if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
248 IS_BROADWELL(dev_priv
)) {
249 source_rates
= default_rates
;
250 size
= ARRAY_SIZE(default_rates
);
252 source_rates
= default_rates
;
253 size
= ARRAY_SIZE(default_rates
) - 1;
256 intel_dp
->source_rates
= source_rates
;
257 intel_dp
->num_source_rates
= size
;
260 static int intersect_rates(const int *source_rates
, int source_len
,
261 const int *sink_rates
, int sink_len
,
264 int i
= 0, j
= 0, k
= 0;
266 while (i
< source_len
&& j
< sink_len
) {
267 if (source_rates
[i
] == sink_rates
[j
]) {
268 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
270 common_rates
[k
] = source_rates
[i
];
274 } else if (source_rates
[i
] < sink_rates
[j
]) {
283 /* return index of rate in rates array, or -1 if not found */
284 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
288 for (i
= 0; i
< len
; i
++)
289 if (rate
== rates
[i
])
295 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
297 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
299 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
300 intel_dp
->num_source_rates
,
301 intel_dp
->sink_rates
,
302 intel_dp
->num_sink_rates
,
303 intel_dp
->common_rates
);
305 /* Paranoia, there should always be something in common. */
306 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
307 intel_dp
->common_rates
[0] = default_rates
[0];
308 intel_dp
->num_common_rates
= 1;
312 /* get length of common rates potentially limited by max_rate */
313 static int intel_dp_common_len_rate_limit(struct intel_dp
*intel_dp
,
316 const int *common_rates
= intel_dp
->common_rates
;
317 int i
, common_len
= intel_dp
->num_common_rates
;
319 /* Limit results by potentially reduced max rate */
320 for (i
= 0; i
< common_len
; i
++) {
321 if (common_rates
[common_len
- i
- 1] <= max_rate
)
322 return common_len
- i
;
328 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
, int link_rate
,
332 * FIXME: we need to synchronize the current link parameters with
333 * hardware readout. Currently fast link training doesn't work on
336 if (link_rate
== 0 ||
337 link_rate
> intel_dp
->max_link_rate
)
340 if (lane_count
== 0 ||
341 lane_count
> intel_dp_max_lane_count(intel_dp
))
347 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
348 int link_rate
, uint8_t lane_count
)
352 index
= intel_dp_rate_index(intel_dp
->common_rates
,
353 intel_dp
->num_common_rates
,
356 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
357 intel_dp
->max_link_lane_count
= lane_count
;
358 } else if (lane_count
> 1) {
359 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
360 intel_dp
->max_link_lane_count
= lane_count
>> 1;
362 DRM_ERROR("Link Training Unsuccessful\n");
369 static enum drm_mode_status
370 intel_dp_mode_valid(struct drm_connector
*connector
,
371 struct drm_display_mode
*mode
)
373 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
374 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
375 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
376 int target_clock
= mode
->clock
;
377 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
380 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
382 if (intel_dp_is_edp(intel_dp
) && fixed_mode
) {
383 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
386 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
389 target_clock
= fixed_mode
->clock
;
392 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
393 max_lanes
= intel_dp_max_lane_count(intel_dp
);
395 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
396 mode_rate
= intel_dp_link_required(target_clock
, 18);
398 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
399 return MODE_CLOCK_HIGH
;
401 if (mode
->clock
< 10000)
402 return MODE_CLOCK_LOW
;
404 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
405 return MODE_H_ILLEGAL
;
410 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
417 for (i
= 0; i
< src_bytes
; i
++)
418 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
422 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
427 for (i
= 0; i
< dst_bytes
; i
++)
428 dst
[i
] = src
>> ((3-i
) * 8);
432 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
434 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
435 bool force_disable_vdd
);
437 intel_dp_pps_init(struct intel_dp
*intel_dp
);
439 static void pps_lock(struct intel_dp
*intel_dp
)
441 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
444 * See intel_power_sequencer_reset() why we need
445 * a power domain reference here.
447 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
449 mutex_lock(&dev_priv
->pps_mutex
);
452 static void pps_unlock(struct intel_dp
*intel_dp
)
454 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
456 mutex_unlock(&dev_priv
->pps_mutex
);
458 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
462 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
464 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
465 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
466 enum pipe pipe
= intel_dp
->pps_pipe
;
467 bool pll_enabled
, release_cl_override
= false;
468 enum dpio_phy phy
= DPIO_PHY(pipe
);
469 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
472 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
473 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
474 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
)))
477 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
478 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
480 /* Preserve the BIOS-computed detected bit. This is
481 * supposed to be read-only.
483 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
484 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
485 DP
|= DP_PORT_WIDTH(1);
486 DP
|= DP_LINK_TRAIN_PAT_1
;
488 if (IS_CHERRYVIEW(dev_priv
))
489 DP
|= DP_PIPE_SELECT_CHV(pipe
);
490 else if (pipe
== PIPE_B
)
491 DP
|= DP_PIPEB_SELECT
;
493 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
496 * The DPLL for the pipe must be enabled for this to work.
497 * So enable temporarily it if it's not already enabled.
500 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
501 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
503 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
504 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
505 DRM_ERROR("Failed to force on pll for pipe %c!\n",
512 * Similar magic as in intel_dp_enable_port().
513 * We _must_ do this port enable + disable trick
514 * to make this power seqeuencer lock onto the port.
515 * Otherwise even VDD force bit won't work.
517 I915_WRITE(intel_dp
->output_reg
, DP
);
518 POSTING_READ(intel_dp
->output_reg
);
520 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
521 POSTING_READ(intel_dp
->output_reg
);
523 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
524 POSTING_READ(intel_dp
->output_reg
);
527 vlv_force_pll_off(dev_priv
, pipe
);
529 if (release_cl_override
)
530 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
534 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
536 struct intel_encoder
*encoder
;
537 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
540 * We don't have power sequencer currently.
541 * Pick one that's not used by other ports.
543 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
544 struct intel_dp
*intel_dp
;
546 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
547 encoder
->type
!= INTEL_OUTPUT_EDP
)
550 intel_dp
= enc_to_intel_dp(&encoder
->base
);
552 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
553 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
554 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
556 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
557 pipes
&= ~(1 << intel_dp
->pps_pipe
);
559 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
561 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
562 pipes
&= ~(1 << intel_dp
->active_pipe
);
569 return ffs(pipes
) - 1;
573 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
575 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
576 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
579 lockdep_assert_held(&dev_priv
->pps_mutex
);
581 /* We should never land here with regular DP ports */
582 WARN_ON(!intel_dp_is_edp(intel_dp
));
584 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
585 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
587 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
588 return intel_dp
->pps_pipe
;
590 pipe
= vlv_find_free_pps(dev_priv
);
593 * Didn't find one. This should not happen since there
594 * are two power sequencers and up to two eDP ports.
596 if (WARN_ON(pipe
== INVALID_PIPE
))
599 vlv_steal_power_sequencer(dev_priv
, pipe
);
600 intel_dp
->pps_pipe
= pipe
;
602 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
603 pipe_name(intel_dp
->pps_pipe
),
604 port_name(intel_dig_port
->base
.port
));
606 /* init power sequencer on this pipe and port */
607 intel_dp_init_panel_power_sequencer(intel_dp
);
608 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
611 * Even vdd force doesn't work until we've made
612 * the power sequencer lock in on the port.
614 vlv_power_sequencer_kick(intel_dp
);
616 return intel_dp
->pps_pipe
;
620 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
622 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
624 lockdep_assert_held(&dev_priv
->pps_mutex
);
626 /* We should never land here with regular DP ports */
627 WARN_ON(!intel_dp_is_edp(intel_dp
));
630 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
631 * mapping needs to be retrieved from VBT, for now just hard-code to
632 * use instance #0 always.
634 if (!intel_dp
->pps_reset
)
637 intel_dp
->pps_reset
= false;
640 * Only the HW needs to be reprogrammed, the SW state is fixed and
641 * has been setup during connector init.
643 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
648 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
651 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
654 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
657 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
660 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
663 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
670 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
672 vlv_pipe_check pipe_check
)
676 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
677 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
678 PANEL_PORT_SELECT_MASK
;
680 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
683 if (!pipe_check(dev_priv
, pipe
))
693 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
695 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
696 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
697 enum port port
= intel_dig_port
->base
.port
;
699 lockdep_assert_held(&dev_priv
->pps_mutex
);
701 /* try to find a pipe with this port selected */
702 /* first pick one where the panel is on */
703 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
705 /* didn't find one? pick one where vdd is on */
706 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
707 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
708 vlv_pipe_has_vdd_on
);
709 /* didn't find one? pick one with just the correct port */
710 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
711 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
714 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
715 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
716 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
721 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
722 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
724 intel_dp_init_panel_power_sequencer(intel_dp
);
725 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
728 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
730 struct intel_encoder
*encoder
;
732 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
733 !IS_GEN9_LP(dev_priv
)))
737 * We can't grab pps_mutex here due to deadlock with power_domain
738 * mutex when power_domain functions are called while holding pps_mutex.
739 * That also means that in order to use pps_pipe the code needs to
740 * hold both a power domain reference and pps_mutex, and the power domain
741 * reference get/put must be done while _not_ holding pps_mutex.
742 * pps_{lock,unlock}() do these steps in the correct order, so one
743 * should use them always.
746 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
747 struct intel_dp
*intel_dp
;
749 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
750 encoder
->type
!= INTEL_OUTPUT_EDP
&&
751 encoder
->type
!= INTEL_OUTPUT_DDI
)
754 intel_dp
= enc_to_intel_dp(&encoder
->base
);
756 /* Skip pure DVI/HDMI DDI encoders */
757 if (!i915_mmio_reg_valid(intel_dp
->output_reg
))
760 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
762 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
765 if (IS_GEN9_LP(dev_priv
))
766 intel_dp
->pps_reset
= true;
768 intel_dp
->pps_pipe
= INVALID_PIPE
;
772 struct pps_registers
{
780 static void intel_pps_get_registers(struct intel_dp
*intel_dp
,
781 struct pps_registers
*regs
)
783 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
786 memset(regs
, 0, sizeof(*regs
));
788 if (IS_GEN9_LP(dev_priv
))
789 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
790 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
791 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
793 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
794 regs
->pp_stat
= PP_STATUS(pps_idx
);
795 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
796 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
797 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
798 !HAS_PCH_ICP(dev_priv
))
799 regs
->pp_div
= PP_DIVISOR(pps_idx
);
803 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
805 struct pps_registers regs
;
807 intel_pps_get_registers(intel_dp
, ®s
);
813 _pp_stat_reg(struct intel_dp
*intel_dp
)
815 struct pps_registers regs
;
817 intel_pps_get_registers(intel_dp
, ®s
);
822 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
823 This function only applicable when panel PM state is not to be tracked */
824 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
827 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
829 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
831 if (!intel_dp_is_edp(intel_dp
) || code
!= SYS_RESTART
)
836 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
837 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
838 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
841 pp_ctrl_reg
= PP_CONTROL(pipe
);
842 pp_div_reg
= PP_DIVISOR(pipe
);
843 pp_div
= I915_READ(pp_div_reg
);
844 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
846 /* 0x1F write to PP_DIV_REG sets max cycle delay */
847 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
848 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
849 msleep(intel_dp
->panel_power_cycle_delay
);
852 pps_unlock(intel_dp
);
857 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
859 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
861 lockdep_assert_held(&dev_priv
->pps_mutex
);
863 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
864 intel_dp
->pps_pipe
== INVALID_PIPE
)
867 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
870 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
872 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
874 lockdep_assert_held(&dev_priv
->pps_mutex
);
876 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
877 intel_dp
->pps_pipe
== INVALID_PIPE
)
880 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
884 intel_dp_check_edp(struct intel_dp
*intel_dp
)
886 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
888 if (!intel_dp_is_edp(intel_dp
))
891 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
892 WARN(1, "eDP powered off while attempting aux channel communication.\n");
893 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
894 I915_READ(_pp_stat_reg(intel_dp
)),
895 I915_READ(_pp_ctrl_reg(intel_dp
)));
900 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
902 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
903 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
907 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
909 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
910 msecs_to_jiffies_timeout(10));
912 done
= wait_for(C
, 10) == 0;
914 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
921 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
923 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
924 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
930 * The clock divider is based off the hrawclk, and would like to run at
931 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
933 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
936 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
938 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
939 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
945 * The clock divider is based off the cdclk or PCH rawclk, and would
946 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
947 * divide by 2000 and use that
949 if (intel_dig_port
->base
.port
== PORT_A
)
950 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
952 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
955 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
957 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
958 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
960 if (intel_dig_port
->base
.port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
961 /* Workaround for non-ULT HSW */
969 return ilk_get_aux_clock_divider(intel_dp
, index
);
972 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
975 * SKL doesn't need us to program the AUX clock divider (Hardware will
976 * derive the clock from CDCLK automatically). We still implement the
977 * get_aux_clock_divider vfunc to plug-in into the existing code.
979 return index
? 0 : 1;
982 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
985 uint32_t aux_clock_divider
)
987 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
988 struct drm_i915_private
*dev_priv
=
989 to_i915(intel_dig_port
->base
.base
.dev
);
990 uint32_t precharge
, timeout
;
992 if (IS_GEN6(dev_priv
))
997 if (IS_BROADWELL(dev_priv
))
998 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1000 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1002 return DP_AUX_CH_CTL_SEND_BUSY
|
1003 DP_AUX_CH_CTL_DONE
|
1004 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1005 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1007 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1008 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1009 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1010 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1013 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1018 return DP_AUX_CH_CTL_SEND_BUSY
|
1019 DP_AUX_CH_CTL_DONE
|
1020 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1021 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1022 DP_AUX_CH_CTL_TIME_OUT_MAX
|
1023 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1024 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1025 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1026 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1030 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
1031 const uint8_t *send
, int send_bytes
,
1032 uint8_t *recv
, int recv_size
)
1034 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1035 struct drm_i915_private
*dev_priv
=
1036 to_i915(intel_dig_port
->base
.base
.dev
);
1037 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
1038 uint32_t aux_clock_divider
;
1039 int i
, ret
, recv_bytes
;
1042 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1048 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1049 * In such cases we want to leave VDD enabled and it's up to upper layers
1050 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1053 vdd
= edp_panel_vdd_on(intel_dp
);
1055 /* dp aux is extremely sensitive to irq latency, hence request the
1056 * lowest possible wakeup latency and so prevent the cpu from going into
1057 * deep sleep states.
1059 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1061 intel_dp_check_edp(intel_dp
);
1063 /* Try to wait for any previous AUX channel activity */
1064 for (try = 0; try < 3; try++) {
1065 status
= I915_READ_NOTRACE(ch_ctl
);
1066 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1072 static u32 last_status
= -1;
1073 const u32 status
= I915_READ(ch_ctl
);
1075 if (status
!= last_status
) {
1076 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1078 last_status
= status
;
1085 /* Only 5 data registers! */
1086 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1091 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1092 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1097 /* Must try at least 3 times according to DP spec */
1098 for (try = 0; try < 5; try++) {
1099 /* Load the send data into the aux channel data registers */
1100 for (i
= 0; i
< send_bytes
; i
+= 4)
1101 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
1102 intel_dp_pack_aux(send
+ i
,
1105 /* Send the command and wait for it to complete */
1106 I915_WRITE(ch_ctl
, send_ctl
);
1108 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1110 /* Clear done status and any errors */
1113 DP_AUX_CH_CTL_DONE
|
1114 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1115 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1117 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1120 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1121 * 400us delay required for errors and timeouts
1122 * Timeout errors from the HW already meet this
1123 * requirement so skip to next iteration
1125 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1126 usleep_range(400, 500);
1129 if (status
& DP_AUX_CH_CTL_DONE
)
1134 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1135 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1141 /* Check for timeout or receive error.
1142 * Timeouts occur when the sink is not connected
1144 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1145 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1150 /* Timeouts occur when the device isn't connected, so they're
1151 * "normal" -- don't fill the kernel log with these */
1152 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1153 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1158 /* Unload any bytes sent back from the other side */
1159 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1160 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1163 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1164 * We have no idea of what happened so we return -EBUSY so
1165 * drm layer takes care for the necessary retries.
1167 if (recv_bytes
== 0 || recv_bytes
> 20) {
1168 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1171 * FIXME: This patch was created on top of a series that
1172 * organize the retries at drm level. There EBUSY should
1173 * also take care for 1ms wait before retrying.
1174 * That aux retries re-org is still needed and after that is
1175 * merged we remove this sleep from here.
1177 usleep_range(1000, 1500);
1182 if (recv_bytes
> recv_size
)
1183 recv_bytes
= recv_size
;
1185 for (i
= 0; i
< recv_bytes
; i
+= 4)
1186 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1187 recv
+ i
, recv_bytes
- i
);
1191 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1194 edp_panel_vdd_off(intel_dp
, false);
1196 pps_unlock(intel_dp
);
1201 #define BARE_ADDRESS_SIZE 3
1202 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1204 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1206 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1207 uint8_t txbuf
[20], rxbuf
[20];
1208 size_t txsize
, rxsize
;
1211 txbuf
[0] = (msg
->request
<< 4) |
1212 ((msg
->address
>> 16) & 0xf);
1213 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1214 txbuf
[2] = msg
->address
& 0xff;
1215 txbuf
[3] = msg
->size
- 1;
1217 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1218 case DP_AUX_NATIVE_WRITE
:
1219 case DP_AUX_I2C_WRITE
:
1220 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1221 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1222 rxsize
= 2; /* 0 or 1 data bytes */
1224 if (WARN_ON(txsize
> 20))
1227 WARN_ON(!msg
->buffer
!= !msg
->size
);
1230 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1232 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1234 msg
->reply
= rxbuf
[0] >> 4;
1237 /* Number of bytes written in a short write. */
1238 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1240 /* Return payload size. */
1246 case DP_AUX_NATIVE_READ
:
1247 case DP_AUX_I2C_READ
:
1248 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1249 rxsize
= msg
->size
+ 1;
1251 if (WARN_ON(rxsize
> 20))
1254 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1256 msg
->reply
= rxbuf
[0] >> 4;
1258 * Assume happy day, and copy the data. The caller is
1259 * expected to check msg->reply before touching it.
1261 * Return payload size.
1264 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1276 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1279 const struct ddi_vbt_port_info
*info
=
1280 &dev_priv
->vbt
.ddi_port_info
[port
];
1283 if (!info
->alternate_aux_channel
) {
1284 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1285 port_name(port
), port_name(port
));
1289 switch (info
->alternate_aux_channel
) {
1306 MISSING_CASE(info
->alternate_aux_channel
);
1311 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1312 port_name(aux_port
), port_name(port
));
1317 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1324 return DP_AUX_CH_CTL(port
);
1327 return DP_AUX_CH_CTL(PORT_B
);
1331 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1332 enum port port
, int index
)
1338 return DP_AUX_CH_DATA(port
, index
);
1341 return DP_AUX_CH_DATA(PORT_B
, index
);
1345 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1350 return DP_AUX_CH_CTL(port
);
1354 return PCH_DP_AUX_CH_CTL(port
);
1357 return DP_AUX_CH_CTL(PORT_A
);
1361 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1362 enum port port
, int index
)
1366 return DP_AUX_CH_DATA(port
, index
);
1370 return PCH_DP_AUX_CH_DATA(port
, index
);
1373 return DP_AUX_CH_DATA(PORT_A
, index
);
1377 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1386 return DP_AUX_CH_CTL(port
);
1389 return DP_AUX_CH_CTL(PORT_A
);
1393 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1394 enum port port
, int index
)
1402 return DP_AUX_CH_DATA(port
, index
);
1405 return DP_AUX_CH_DATA(PORT_A
, index
);
1409 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1412 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1413 return skl_aux_ctl_reg(dev_priv
, port
);
1414 else if (HAS_PCH_SPLIT(dev_priv
))
1415 return ilk_aux_ctl_reg(dev_priv
, port
);
1417 return g4x_aux_ctl_reg(dev_priv
, port
);
1420 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1421 enum port port
, int index
)
1423 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1424 return skl_aux_data_reg(dev_priv
, port
, index
);
1425 else if (HAS_PCH_SPLIT(dev_priv
))
1426 return ilk_aux_data_reg(dev_priv
, port
, index
);
1428 return g4x_aux_data_reg(dev_priv
, port
, index
);
1431 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1433 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1434 enum port port
= intel_aux_port(dev_priv
,
1435 dp_to_dig_port(intel_dp
)->base
.port
);
1438 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1439 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1440 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1444 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1446 kfree(intel_dp
->aux
.name
);
1450 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1452 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1453 enum port port
= intel_dig_port
->base
.port
;
1455 intel_aux_reg_init(intel_dp
);
1456 drm_dp_aux_init(&intel_dp
->aux
);
1458 /* Failure to allocate our preferred name is not critical */
1459 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1460 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1463 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1465 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1467 return max_rate
>= 540000;
1471 intel_dp_set_clock(struct intel_encoder
*encoder
,
1472 struct intel_crtc_state
*pipe_config
)
1474 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1475 const struct dp_link_dpll
*divisor
= NULL
;
1478 if (IS_G4X(dev_priv
)) {
1479 divisor
= gen4_dpll
;
1480 count
= ARRAY_SIZE(gen4_dpll
);
1481 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1483 count
= ARRAY_SIZE(pch_dpll
);
1484 } else if (IS_CHERRYVIEW(dev_priv
)) {
1486 count
= ARRAY_SIZE(chv_dpll
);
1487 } else if (IS_VALLEYVIEW(dev_priv
)) {
1489 count
= ARRAY_SIZE(vlv_dpll
);
1492 if (divisor
&& count
) {
1493 for (i
= 0; i
< count
; i
++) {
1494 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1495 pipe_config
->dpll
= divisor
[i
].dpll
;
1496 pipe_config
->clock_set
= true;
1503 static void snprintf_int_array(char *str
, size_t len
,
1504 const int *array
, int nelem
)
1510 for (i
= 0; i
< nelem
; i
++) {
1511 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1519 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1521 char str
[128]; /* FIXME: too big for stack? */
1523 if ((drm_debug
& DRM_UT_KMS
) == 0)
1526 snprintf_int_array(str
, sizeof(str
),
1527 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1528 DRM_DEBUG_KMS("source rates: %s\n", str
);
1530 snprintf_int_array(str
, sizeof(str
),
1531 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1532 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1534 snprintf_int_array(str
, sizeof(str
),
1535 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1536 DRM_DEBUG_KMS("common rates: %s\n", str
);
1540 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1544 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1545 if (WARN_ON(len
<= 0))
1548 return intel_dp
->common_rates
[len
- 1];
1551 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1553 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1554 intel_dp
->num_sink_rates
, rate
);
1562 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1563 uint8_t *link_bw
, uint8_t *rate_select
)
1565 /* eDP 1.4 rate select method. */
1566 if (intel_dp
->use_rate_select
) {
1569 intel_dp_rate_select(intel_dp
, port_clock
);
1571 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1576 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1577 struct intel_crtc_state
*pipe_config
)
1581 bpp
= pipe_config
->pipe_bpp
;
1582 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1585 bpp
= min(bpp
, 3*bpc
);
1587 /* For DP Compliance we override the computed bpp for the pipe */
1588 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1589 pipe_config
->pipe_bpp
= 3*intel_dp
->compliance
.test_data
.bpc
;
1590 pipe_config
->dither_force_disable
= pipe_config
->pipe_bpp
== 6*3;
1591 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1592 pipe_config
->pipe_bpp
);
1597 static bool intel_edp_compare_alt_mode(struct drm_display_mode
*m1
,
1598 struct drm_display_mode
*m2
)
1603 bres
= (m1
->hdisplay
== m2
->hdisplay
&&
1604 m1
->hsync_start
== m2
->hsync_start
&&
1605 m1
->hsync_end
== m2
->hsync_end
&&
1606 m1
->htotal
== m2
->htotal
&&
1607 m1
->vdisplay
== m2
->vdisplay
&&
1608 m1
->vsync_start
== m2
->vsync_start
&&
1609 m1
->vsync_end
== m2
->vsync_end
&&
1610 m1
->vtotal
== m2
->vtotal
);
1615 intel_dp_compute_config(struct intel_encoder
*encoder
,
1616 struct intel_crtc_state
*pipe_config
,
1617 struct drm_connector_state
*conn_state
)
1619 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1620 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1621 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1622 enum port port
= encoder
->port
;
1623 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1624 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1625 struct intel_digital_connector_state
*intel_conn_state
=
1626 to_intel_digital_connector_state(conn_state
);
1627 int lane_count
, clock
;
1628 int min_lane_count
= 1;
1629 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1630 /* Conveniently, the link BW constants become indices with a shift...*/
1634 int link_avail
, link_clock
;
1636 uint8_t link_bw
, rate_select
;
1637 bool reduce_m_n
= drm_dp_has_quirk(&intel_dp
->desc
,
1638 DP_DPCD_QUIRK_LIMITED_M_N
);
1640 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1641 intel_dp
->max_link_rate
);
1643 /* No common link rates between source and sink */
1644 WARN_ON(common_len
<= 0);
1646 max_clock
= common_len
- 1;
1648 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1649 pipe_config
->has_pch_encoder
= true;
1651 pipe_config
->has_drrs
= false;
1652 if (IS_G4X(dev_priv
) || port
== PORT_A
)
1653 pipe_config
->has_audio
= false;
1654 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1655 pipe_config
->has_audio
= intel_dp
->has_audio
;
1657 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1659 if (intel_dp_is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1660 struct drm_display_mode
*panel_mode
=
1661 intel_connector
->panel
.alt_fixed_mode
;
1662 struct drm_display_mode
*req_mode
= &pipe_config
->base
.mode
;
1664 if (!intel_edp_compare_alt_mode(req_mode
, panel_mode
))
1665 panel_mode
= intel_connector
->panel
.fixed_mode
;
1667 drm_mode_debug_printmodeline(panel_mode
);
1669 intel_fixed_panel_mode(panel_mode
, adjusted_mode
);
1671 if (INTEL_GEN(dev_priv
) >= 9) {
1673 ret
= skl_update_scaler_crtc(pipe_config
);
1678 if (HAS_GMCH_DISPLAY(dev_priv
))
1679 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1680 conn_state
->scaling_mode
);
1682 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1683 conn_state
->scaling_mode
);
1686 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1687 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1690 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1693 /* Use values requested by Compliance Test Request */
1694 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1697 /* Validate the compliance test data since max values
1698 * might have changed due to link train fallback.
1700 if (intel_dp_link_params_valid(intel_dp
, intel_dp
->compliance
.test_link_rate
,
1701 intel_dp
->compliance
.test_lane_count
)) {
1702 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1703 intel_dp
->num_common_rates
,
1704 intel_dp
->compliance
.test_link_rate
);
1706 min_clock
= max_clock
= index
;
1707 min_lane_count
= max_lane_count
= intel_dp
->compliance
.test_lane_count
;
1710 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1711 "max bw %d pixel clock %iKHz\n",
1712 max_lane_count
, intel_dp
->common_rates
[max_clock
],
1713 adjusted_mode
->crtc_clock
);
1715 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1716 * bpc in between. */
1717 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1718 if (intel_dp_is_edp(intel_dp
)) {
1720 /* Get bpp from vbt only for panels that dont have bpp in edid */
1721 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1722 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1723 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1724 dev_priv
->vbt
.edp
.bpp
);
1725 bpp
= dev_priv
->vbt
.edp
.bpp
;
1729 * Use the maximum clock and number of lanes the eDP panel
1730 * advertizes being capable of. The panels are generally
1731 * designed to support only a single clock and lane
1732 * configuration, and typically these values correspond to the
1733 * native resolution of the panel.
1735 min_lane_count
= max_lane_count
;
1736 min_clock
= max_clock
;
1739 for (; bpp
>= 6*3; bpp
-= 2*3) {
1740 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1743 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1744 for (lane_count
= min_lane_count
;
1745 lane_count
<= max_lane_count
;
1748 link_clock
= intel_dp
->common_rates
[clock
];
1749 link_avail
= intel_dp_max_data_rate(link_clock
,
1752 if (mode_rate
<= link_avail
) {
1762 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1765 * CEA-861-E - 5.1 Default Encoding Parameters
1766 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1768 pipe_config
->limited_color_range
=
1770 drm_default_rgb_quant_range(adjusted_mode
) ==
1771 HDMI_QUANTIZATION_RANGE_LIMITED
;
1773 pipe_config
->limited_color_range
=
1774 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1777 pipe_config
->lane_count
= lane_count
;
1779 pipe_config
->pipe_bpp
= bpp
;
1780 pipe_config
->port_clock
= intel_dp
->common_rates
[clock
];
1782 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1783 &link_bw
, &rate_select
);
1785 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1786 link_bw
, rate_select
, pipe_config
->lane_count
,
1787 pipe_config
->port_clock
, bpp
);
1788 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1789 mode_rate
, link_avail
);
1791 intel_link_compute_m_n(bpp
, lane_count
,
1792 adjusted_mode
->crtc_clock
,
1793 pipe_config
->port_clock
,
1794 &pipe_config
->dp_m_n
,
1797 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1798 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1799 pipe_config
->has_drrs
= true;
1800 intel_link_compute_m_n(bpp
, lane_count
,
1801 intel_connector
->panel
.downclock_mode
->clock
,
1802 pipe_config
->port_clock
,
1803 &pipe_config
->dp_m2_n2
,
1808 * DPLL0 VCO may need to be adjusted to get the correct
1809 * clock for eDP. This will affect cdclk as well.
1811 if (intel_dp_is_edp(intel_dp
) && IS_GEN9_BC(dev_priv
)) {
1814 switch (pipe_config
->port_clock
/ 2) {
1824 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk
.logical
.vco
= vco
;
1827 if (!HAS_DDI(dev_priv
))
1828 intel_dp_set_clock(encoder
, pipe_config
);
1830 intel_psr_compute_config(intel_dp
, pipe_config
);
1835 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1836 int link_rate
, uint8_t lane_count
,
1839 intel_dp
->link_rate
= link_rate
;
1840 intel_dp
->lane_count
= lane_count
;
1841 intel_dp
->link_mst
= link_mst
;
1844 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1845 const struct intel_crtc_state
*pipe_config
)
1847 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1848 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1849 enum port port
= encoder
->port
;
1850 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1851 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1853 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1854 pipe_config
->lane_count
,
1855 intel_crtc_has_type(pipe_config
,
1856 INTEL_OUTPUT_DP_MST
));
1859 * There are four kinds of DP registers:
1866 * IBX PCH and CPU are the same for almost everything,
1867 * except that the CPU DP PLL is configured in this
1870 * CPT PCH is quite different, having many bits moved
1871 * to the TRANS_DP_CTL register instead. That
1872 * configuration happens (oddly) in ironlake_pch_enable
1875 /* Preserve the BIOS-computed detected bit. This is
1876 * supposed to be read-only.
1878 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1880 /* Handle DP bits in common between all three register formats */
1881 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1882 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1884 /* Split out the IBX/CPU vs CPT settings */
1886 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1887 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1888 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1889 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1890 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1891 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1893 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1894 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1896 intel_dp
->DP
|= crtc
->pipe
<< 29;
1897 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1900 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1902 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1903 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1904 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1906 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1907 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1909 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
1910 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1912 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1913 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1914 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1915 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1916 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1918 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1919 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1921 if (IS_CHERRYVIEW(dev_priv
))
1922 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1923 else if (crtc
->pipe
== PIPE_B
)
1924 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1928 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1929 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1931 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1932 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1934 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1935 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1937 static void intel_pps_verify_state(struct intel_dp
*intel_dp
);
1939 static void wait_panel_status(struct intel_dp
*intel_dp
,
1943 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1944 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1946 lockdep_assert_held(&dev_priv
->pps_mutex
);
1948 intel_pps_verify_state(intel_dp
);
1950 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1951 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1953 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1955 I915_READ(pp_stat_reg
),
1956 I915_READ(pp_ctrl_reg
));
1958 if (intel_wait_for_register(dev_priv
,
1959 pp_stat_reg
, mask
, value
,
1961 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1962 I915_READ(pp_stat_reg
),
1963 I915_READ(pp_ctrl_reg
));
1965 DRM_DEBUG_KMS("Wait complete\n");
1968 static void wait_panel_on(struct intel_dp
*intel_dp
)
1970 DRM_DEBUG_KMS("Wait for panel power on\n");
1971 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1974 static void wait_panel_off(struct intel_dp
*intel_dp
)
1976 DRM_DEBUG_KMS("Wait for panel power off time\n");
1977 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1980 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1982 ktime_t panel_power_on_time
;
1983 s64 panel_power_off_duration
;
1985 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1987 /* take the difference of currrent time and panel power off time
1988 * and then make panel wait for t11_t12 if needed. */
1989 panel_power_on_time
= ktime_get_boottime();
1990 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1992 /* When we disable the VDD override bit last we have to do the manual
1994 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1995 wait_remaining_ms_from_jiffies(jiffies
,
1996 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1998 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2001 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2003 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2004 intel_dp
->backlight_on_delay
);
2007 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2009 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2010 intel_dp
->backlight_off_delay
);
2013 /* Read the current pp_control value, unlocking the register if it
2017 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2019 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2022 lockdep_assert_held(&dev_priv
->pps_mutex
);
2024 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2025 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2026 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2027 control
&= ~PANEL_UNLOCK_MASK
;
2028 control
|= PANEL_UNLOCK_REGS
;
2034 * Must be paired with edp_panel_vdd_off().
2035 * Must hold pps_mutex around the whole on/off sequence.
2036 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2038 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2040 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2041 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2043 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2044 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2046 lockdep_assert_held(&dev_priv
->pps_mutex
);
2048 if (!intel_dp_is_edp(intel_dp
))
2051 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2052 intel_dp
->want_panel_vdd
= true;
2054 if (edp_have_panel_vdd(intel_dp
))
2055 return need_to_disable
;
2057 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2059 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2060 port_name(intel_dig_port
->base
.port
));
2062 if (!edp_have_panel_power(intel_dp
))
2063 wait_panel_power_cycle(intel_dp
);
2065 pp
= ironlake_get_pp_control(intel_dp
);
2066 pp
|= EDP_FORCE_VDD
;
2068 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2069 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2071 I915_WRITE(pp_ctrl_reg
, pp
);
2072 POSTING_READ(pp_ctrl_reg
);
2073 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2074 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2076 * If the panel wasn't on, delay before accessing aux channel
2078 if (!edp_have_panel_power(intel_dp
)) {
2079 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2080 port_name(intel_dig_port
->base
.port
));
2081 msleep(intel_dp
->panel_power_up_delay
);
2084 return need_to_disable
;
2088 * Must be paired with intel_edp_panel_vdd_off() or
2089 * intel_edp_panel_off().
2090 * Nested calls to these functions are not allowed since
2091 * we drop the lock. Caller must use some higher level
2092 * locking to prevent nested calls from other threads.
2094 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2098 if (!intel_dp_is_edp(intel_dp
))
2102 vdd
= edp_panel_vdd_on(intel_dp
);
2103 pps_unlock(intel_dp
);
2105 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2106 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2109 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2111 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2112 struct intel_digital_port
*intel_dig_port
=
2113 dp_to_dig_port(intel_dp
);
2115 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2117 lockdep_assert_held(&dev_priv
->pps_mutex
);
2119 WARN_ON(intel_dp
->want_panel_vdd
);
2121 if (!edp_have_panel_vdd(intel_dp
))
2124 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2125 port_name(intel_dig_port
->base
.port
));
2127 pp
= ironlake_get_pp_control(intel_dp
);
2128 pp
&= ~EDP_FORCE_VDD
;
2130 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2131 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2133 I915_WRITE(pp_ctrl_reg
, pp
);
2134 POSTING_READ(pp_ctrl_reg
);
2136 /* Make sure sequencer is idle before allowing subsequent activity */
2137 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2138 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2140 if ((pp
& PANEL_POWER_ON
) == 0)
2141 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2143 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2146 static void edp_panel_vdd_work(struct work_struct
*__work
)
2148 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2149 struct intel_dp
, panel_vdd_work
);
2152 if (!intel_dp
->want_panel_vdd
)
2153 edp_panel_vdd_off_sync(intel_dp
);
2154 pps_unlock(intel_dp
);
2157 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2159 unsigned long delay
;
2162 * Queue the timer to fire a long time from now (relative to the power
2163 * down delay) to keep the panel power up across a sequence of
2166 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2167 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2171 * Must be paired with edp_panel_vdd_on().
2172 * Must hold pps_mutex around the whole on/off sequence.
2173 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2175 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2177 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2179 lockdep_assert_held(&dev_priv
->pps_mutex
);
2181 if (!intel_dp_is_edp(intel_dp
))
2184 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2185 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2187 intel_dp
->want_panel_vdd
= false;
2190 edp_panel_vdd_off_sync(intel_dp
);
2192 edp_panel_vdd_schedule_off(intel_dp
);
2195 static void edp_panel_on(struct intel_dp
*intel_dp
)
2197 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2199 i915_reg_t pp_ctrl_reg
;
2201 lockdep_assert_held(&dev_priv
->pps_mutex
);
2203 if (!intel_dp_is_edp(intel_dp
))
2206 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2207 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2209 if (WARN(edp_have_panel_power(intel_dp
),
2210 "eDP port %c panel power already on\n",
2211 port_name(dp_to_dig_port(intel_dp
)->base
.port
)))
2214 wait_panel_power_cycle(intel_dp
);
2216 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2217 pp
= ironlake_get_pp_control(intel_dp
);
2218 if (IS_GEN5(dev_priv
)) {
2219 /* ILK workaround: disable reset around power sequence */
2220 pp
&= ~PANEL_POWER_RESET
;
2221 I915_WRITE(pp_ctrl_reg
, pp
);
2222 POSTING_READ(pp_ctrl_reg
);
2225 pp
|= PANEL_POWER_ON
;
2226 if (!IS_GEN5(dev_priv
))
2227 pp
|= PANEL_POWER_RESET
;
2229 I915_WRITE(pp_ctrl_reg
, pp
);
2230 POSTING_READ(pp_ctrl_reg
);
2232 wait_panel_on(intel_dp
);
2233 intel_dp
->last_power_on
= jiffies
;
2235 if (IS_GEN5(dev_priv
)) {
2236 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2237 I915_WRITE(pp_ctrl_reg
, pp
);
2238 POSTING_READ(pp_ctrl_reg
);
2242 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2244 if (!intel_dp_is_edp(intel_dp
))
2248 edp_panel_on(intel_dp
);
2249 pps_unlock(intel_dp
);
2253 static void edp_panel_off(struct intel_dp
*intel_dp
)
2255 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2257 i915_reg_t pp_ctrl_reg
;
2259 lockdep_assert_held(&dev_priv
->pps_mutex
);
2261 if (!intel_dp_is_edp(intel_dp
))
2264 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2265 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2267 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2268 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2270 pp
= ironlake_get_pp_control(intel_dp
);
2271 /* We need to switch off panel power _and_ force vdd, for otherwise some
2272 * panels get very unhappy and cease to work. */
2273 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2276 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2278 intel_dp
->want_panel_vdd
= false;
2280 I915_WRITE(pp_ctrl_reg
, pp
);
2281 POSTING_READ(pp_ctrl_reg
);
2283 wait_panel_off(intel_dp
);
2284 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2286 /* We got a reference when we enabled the VDD. */
2287 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2290 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2292 if (!intel_dp_is_edp(intel_dp
))
2296 edp_panel_off(intel_dp
);
2297 pps_unlock(intel_dp
);
2300 /* Enable backlight in the panel power control. */
2301 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2303 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2305 i915_reg_t pp_ctrl_reg
;
2308 * If we enable the backlight right away following a panel power
2309 * on, we may see slight flicker as the panel syncs with the eDP
2310 * link. So delay a bit to make sure the image is solid before
2311 * allowing it to appear.
2313 wait_backlight_on(intel_dp
);
2317 pp
= ironlake_get_pp_control(intel_dp
);
2318 pp
|= EDP_BLC_ENABLE
;
2320 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2322 I915_WRITE(pp_ctrl_reg
, pp
);
2323 POSTING_READ(pp_ctrl_reg
);
2325 pps_unlock(intel_dp
);
2328 /* Enable backlight PWM and backlight PP control. */
2329 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2330 const struct drm_connector_state
*conn_state
)
2332 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2334 if (!intel_dp_is_edp(intel_dp
))
2337 DRM_DEBUG_KMS("\n");
2339 intel_panel_enable_backlight(crtc_state
, conn_state
);
2340 _intel_edp_backlight_on(intel_dp
);
2343 /* Disable backlight in the panel power control. */
2344 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2346 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2348 i915_reg_t pp_ctrl_reg
;
2350 if (!intel_dp_is_edp(intel_dp
))
2355 pp
= ironlake_get_pp_control(intel_dp
);
2356 pp
&= ~EDP_BLC_ENABLE
;
2358 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2360 I915_WRITE(pp_ctrl_reg
, pp
);
2361 POSTING_READ(pp_ctrl_reg
);
2363 pps_unlock(intel_dp
);
2365 intel_dp
->last_backlight_off
= jiffies
;
2366 edp_wait_backlight_off(intel_dp
);
2369 /* Disable backlight PP control and backlight PWM. */
2370 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2372 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2374 if (!intel_dp_is_edp(intel_dp
))
2377 DRM_DEBUG_KMS("\n");
2379 _intel_edp_backlight_off(intel_dp
);
2380 intel_panel_disable_backlight(old_conn_state
);
2384 * Hook for controlling the panel power control backlight through the bl_power
2385 * sysfs attribute. Take care to handle multiple calls.
2387 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2390 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2394 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2395 pps_unlock(intel_dp
);
2397 if (is_enabled
== enable
)
2400 DRM_DEBUG_KMS("panel power control backlight %s\n",
2401 enable
? "enable" : "disable");
2404 _intel_edp_backlight_on(intel_dp
);
2406 _intel_edp_backlight_off(intel_dp
);
2409 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2411 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2412 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2413 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2415 I915_STATE_WARN(cur_state
!= state
,
2416 "DP port %c state assertion failure (expected %s, current %s)\n",
2417 port_name(dig_port
->base
.port
),
2418 onoff(state
), onoff(cur_state
));
2420 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2422 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2424 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2426 I915_STATE_WARN(cur_state
!= state
,
2427 "eDP PLL state assertion failure (expected %s, current %s)\n",
2428 onoff(state
), onoff(cur_state
));
2430 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2431 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2433 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2434 const struct intel_crtc_state
*pipe_config
)
2436 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2437 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2439 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2440 assert_dp_port_disabled(intel_dp
);
2441 assert_edp_pll_disabled(dev_priv
);
2443 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2444 pipe_config
->port_clock
);
2446 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2448 if (pipe_config
->port_clock
== 162000)
2449 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2451 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2453 I915_WRITE(DP_A
, intel_dp
->DP
);
2458 * [DevILK] Work around required when enabling DP PLL
2459 * while a pipe is enabled going to FDI:
2460 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2461 * 2. Program DP PLL enable
2463 if (IS_GEN5(dev_priv
))
2464 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2466 intel_dp
->DP
|= DP_PLL_ENABLE
;
2468 I915_WRITE(DP_A
, intel_dp
->DP
);
2473 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
,
2474 const struct intel_crtc_state
*old_crtc_state
)
2476 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
2477 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2479 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2480 assert_dp_port_disabled(intel_dp
);
2481 assert_edp_pll_enabled(dev_priv
);
2483 DRM_DEBUG_KMS("disabling eDP PLL\n");
2485 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2487 I915_WRITE(DP_A
, intel_dp
->DP
);
2492 static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp
)
2495 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2496 * be capable of signalling downstream hpd with a long pulse.
2497 * Whether or not that means D3 is safe to use is not clear,
2498 * but let's assume so until proven otherwise.
2500 * FIXME should really check all downstream ports...
2502 return intel_dp
->dpcd
[DP_DPCD_REV
] == 0x11 &&
2503 intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
&&
2504 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
;
2507 /* If the sink supports it, try to set the power state appropriately */
2508 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2512 /* Should have a valid DPCD by this point */
2513 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2516 if (mode
!= DRM_MODE_DPMS_ON
) {
2517 if (downstream_hpd_needs_d0(intel_dp
))
2520 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2523 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2526 * When turning on, we need to retry for 1ms to give the sink
2529 for (i
= 0; i
< 3; i
++) {
2530 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2537 if (ret
== 1 && lspcon
->active
)
2538 lspcon_wait_pcon_mode(lspcon
);
2542 DRM_DEBUG_KMS("failed to %s sink power state\n",
2543 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2546 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2549 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2550 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2551 enum port port
= encoder
->port
;
2555 if (!intel_display_power_get_if_enabled(dev_priv
,
2556 encoder
->power_domain
))
2561 tmp
= I915_READ(intel_dp
->output_reg
);
2563 if (!(tmp
& DP_PORT_EN
))
2566 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2567 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2568 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2571 for_each_pipe(dev_priv
, p
) {
2572 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2573 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2581 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2582 i915_mmio_reg_offset(intel_dp
->output_reg
));
2583 } else if (IS_CHERRYVIEW(dev_priv
)) {
2584 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2586 *pipe
= PORT_TO_PIPE(tmp
);
2592 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2597 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2598 struct intel_crtc_state
*pipe_config
)
2600 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2601 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2603 enum port port
= encoder
->port
;
2604 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2606 if (encoder
->type
== INTEL_OUTPUT_EDP
)
2607 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_EDP
);
2609 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_DP
);
2611 tmp
= I915_READ(intel_dp
->output_reg
);
2613 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2615 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2616 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2618 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2619 flags
|= DRM_MODE_FLAG_PHSYNC
;
2621 flags
|= DRM_MODE_FLAG_NHSYNC
;
2623 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2624 flags
|= DRM_MODE_FLAG_PVSYNC
;
2626 flags
|= DRM_MODE_FLAG_NVSYNC
;
2628 if (tmp
& DP_SYNC_HS_HIGH
)
2629 flags
|= DRM_MODE_FLAG_PHSYNC
;
2631 flags
|= DRM_MODE_FLAG_NHSYNC
;
2633 if (tmp
& DP_SYNC_VS_HIGH
)
2634 flags
|= DRM_MODE_FLAG_PVSYNC
;
2636 flags
|= DRM_MODE_FLAG_NVSYNC
;
2639 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2641 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2642 pipe_config
->limited_color_range
= true;
2644 pipe_config
->lane_count
=
2645 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2647 intel_dp_get_m_n(crtc
, pipe_config
);
2649 if (port
== PORT_A
) {
2650 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2651 pipe_config
->port_clock
= 162000;
2653 pipe_config
->port_clock
= 270000;
2656 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2657 intel_dotclock_calculate(pipe_config
->port_clock
,
2658 &pipe_config
->dp_m_n
);
2660 if (intel_dp_is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2661 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2663 * This is a big fat ugly hack.
2665 * Some machines in UEFI boot mode provide us a VBT that has 18
2666 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2667 * unknown we fail to light up. Yet the same BIOS boots up with
2668 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2669 * max, not what it tells us to use.
2671 * Note: This will still be broken if the eDP panel is not lit
2672 * up by the BIOS, and thus we can't get the mode at module
2675 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2676 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2677 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2681 static void intel_disable_dp(struct intel_encoder
*encoder
,
2682 const struct intel_crtc_state
*old_crtc_state
,
2683 const struct drm_connector_state
*old_conn_state
)
2685 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2687 if (old_crtc_state
->has_audio
)
2688 intel_audio_codec_disable(encoder
,
2689 old_crtc_state
, old_conn_state
);
2691 /* Make sure the panel is off before trying to change the mode. But also
2692 * ensure that we have vdd while we switch off the panel. */
2693 intel_edp_panel_vdd_on(intel_dp
);
2694 intel_edp_backlight_off(old_conn_state
);
2695 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2696 intel_edp_panel_off(intel_dp
);
2699 static void g4x_disable_dp(struct intel_encoder
*encoder
,
2700 const struct intel_crtc_state
*old_crtc_state
,
2701 const struct drm_connector_state
*old_conn_state
)
2703 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2705 /* disable the port before the pipe on g4x */
2706 intel_dp_link_down(encoder
, old_crtc_state
);
2709 static void ilk_disable_dp(struct intel_encoder
*encoder
,
2710 const struct intel_crtc_state
*old_crtc_state
,
2711 const struct drm_connector_state
*old_conn_state
)
2713 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2716 static void vlv_disable_dp(struct intel_encoder
*encoder
,
2717 const struct intel_crtc_state
*old_crtc_state
,
2718 const struct drm_connector_state
*old_conn_state
)
2720 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2722 intel_psr_disable(intel_dp
, old_crtc_state
);
2724 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2727 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2728 const struct intel_crtc_state
*old_crtc_state
,
2729 const struct drm_connector_state
*old_conn_state
)
2731 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2732 enum port port
= encoder
->port
;
2734 intel_dp_link_down(encoder
, old_crtc_state
);
2736 /* Only ilk+ has port A */
2738 ironlake_edp_pll_off(intel_dp
, old_crtc_state
);
2741 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2742 const struct intel_crtc_state
*old_crtc_state
,
2743 const struct drm_connector_state
*old_conn_state
)
2745 intel_dp_link_down(encoder
, old_crtc_state
);
2748 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2749 const struct intel_crtc_state
*old_crtc_state
,
2750 const struct drm_connector_state
*old_conn_state
)
2752 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2754 intel_dp_link_down(encoder
, old_crtc_state
);
2756 mutex_lock(&dev_priv
->sb_lock
);
2758 /* Assert data lane reset */
2759 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
2761 mutex_unlock(&dev_priv
->sb_lock
);
2765 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2767 uint8_t dp_train_pat
)
2769 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2770 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2771 enum port port
= intel_dig_port
->base
.port
;
2773 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2774 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2775 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2777 if (HAS_DDI(dev_priv
)) {
2778 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2780 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2781 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2783 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2785 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2786 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2787 case DP_TRAINING_PATTERN_DISABLE
:
2788 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2791 case DP_TRAINING_PATTERN_1
:
2792 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2794 case DP_TRAINING_PATTERN_2
:
2795 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2797 case DP_TRAINING_PATTERN_3
:
2798 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2801 I915_WRITE(DP_TP_CTL(port
), temp
);
2803 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2804 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2805 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2807 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2808 case DP_TRAINING_PATTERN_DISABLE
:
2809 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2811 case DP_TRAINING_PATTERN_1
:
2812 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2814 case DP_TRAINING_PATTERN_2
:
2815 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2817 case DP_TRAINING_PATTERN_3
:
2818 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2819 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2824 if (IS_CHERRYVIEW(dev_priv
))
2825 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2827 *DP
&= ~DP_LINK_TRAIN_MASK
;
2829 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2830 case DP_TRAINING_PATTERN_DISABLE
:
2831 *DP
|= DP_LINK_TRAIN_OFF
;
2833 case DP_TRAINING_PATTERN_1
:
2834 *DP
|= DP_LINK_TRAIN_PAT_1
;
2836 case DP_TRAINING_PATTERN_2
:
2837 *DP
|= DP_LINK_TRAIN_PAT_2
;
2839 case DP_TRAINING_PATTERN_3
:
2840 if (IS_CHERRYVIEW(dev_priv
)) {
2841 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2843 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2844 *DP
|= DP_LINK_TRAIN_PAT_2
;
2851 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2852 const struct intel_crtc_state
*old_crtc_state
)
2854 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2856 /* enable with pattern 1 (as per spec) */
2858 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2861 * Magic for VLV/CHV. We _must_ first set up the register
2862 * without actually enabling the port, and then do another
2863 * write to enable the port. Otherwise link training will
2864 * fail when the power sequencer is freshly used for this port.
2866 intel_dp
->DP
|= DP_PORT_EN
;
2867 if (old_crtc_state
->has_audio
)
2868 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2870 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2871 POSTING_READ(intel_dp
->output_reg
);
2874 static void intel_enable_dp(struct intel_encoder
*encoder
,
2875 const struct intel_crtc_state
*pipe_config
,
2876 const struct drm_connector_state
*conn_state
)
2878 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2879 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2880 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2881 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2882 enum pipe pipe
= crtc
->pipe
;
2884 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2889 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2890 vlv_init_panel_power_sequencer(encoder
, pipe_config
);
2892 intel_dp_enable_port(intel_dp
, pipe_config
);
2894 edp_panel_vdd_on(intel_dp
);
2895 edp_panel_on(intel_dp
);
2896 edp_panel_vdd_off(intel_dp
, true);
2898 pps_unlock(intel_dp
);
2900 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2901 unsigned int lane_mask
= 0x0;
2903 if (IS_CHERRYVIEW(dev_priv
))
2904 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2906 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2910 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2911 intel_dp_start_link_train(intel_dp
);
2912 intel_dp_stop_link_train(intel_dp
);
2914 if (pipe_config
->has_audio
) {
2915 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2917 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
2921 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2922 const struct intel_crtc_state
*pipe_config
,
2923 const struct drm_connector_state
*conn_state
)
2925 intel_enable_dp(encoder
, pipe_config
, conn_state
);
2926 intel_edp_backlight_on(pipe_config
, conn_state
);
2929 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2930 const struct intel_crtc_state
*pipe_config
,
2931 const struct drm_connector_state
*conn_state
)
2933 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2935 intel_edp_backlight_on(pipe_config
, conn_state
);
2936 intel_psr_enable(intel_dp
, pipe_config
);
2939 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2940 const struct intel_crtc_state
*pipe_config
,
2941 const struct drm_connector_state
*conn_state
)
2943 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2944 enum port port
= encoder
->port
;
2946 intel_dp_prepare(encoder
, pipe_config
);
2948 /* Only ilk+ has port A */
2950 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2953 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2955 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2956 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2957 enum pipe pipe
= intel_dp
->pps_pipe
;
2958 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2960 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
2962 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2965 edp_panel_vdd_off_sync(intel_dp
);
2968 * VLV seems to get confused when multiple power seqeuencers
2969 * have the same port selected (even if only one has power/vdd
2970 * enabled). The failure manifests as vlv_wait_port_ready() failing
2971 * CHV on the other hand doesn't seem to mind having the same port
2972 * selected in multiple power seqeuencers, but let's clear the
2973 * port select always when logically disconnecting a power sequencer
2976 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2977 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
2978 I915_WRITE(pp_on_reg
, 0);
2979 POSTING_READ(pp_on_reg
);
2981 intel_dp
->pps_pipe
= INVALID_PIPE
;
2984 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
2987 struct intel_encoder
*encoder
;
2989 lockdep_assert_held(&dev_priv
->pps_mutex
);
2991 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
2992 struct intel_dp
*intel_dp
;
2995 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
2996 encoder
->type
!= INTEL_OUTPUT_EDP
)
2999 intel_dp
= enc_to_intel_dp(&encoder
->base
);
3000 port
= dp_to_dig_port(intel_dp
)->base
.port
;
3002 WARN(intel_dp
->active_pipe
== pipe
,
3003 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3004 pipe_name(pipe
), port_name(port
));
3006 if (intel_dp
->pps_pipe
!= pipe
)
3009 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3010 pipe_name(pipe
), port_name(port
));
3012 /* make sure vdd is off before we steal it */
3013 vlv_detach_power_sequencer(intel_dp
);
3017 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
3018 const struct intel_crtc_state
*crtc_state
)
3020 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3021 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3022 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3024 lockdep_assert_held(&dev_priv
->pps_mutex
);
3026 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3028 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3029 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3031 * If another power sequencer was being used on this
3032 * port previously make sure to turn off vdd there while
3033 * we still have control of it.
3035 vlv_detach_power_sequencer(intel_dp
);
3039 * We may be stealing the power
3040 * sequencer from another port.
3042 vlv_steal_power_sequencer(dev_priv
, crtc
->pipe
);
3044 intel_dp
->active_pipe
= crtc
->pipe
;
3046 if (!intel_dp_is_edp(intel_dp
))
3049 /* now it's all ours */
3050 intel_dp
->pps_pipe
= crtc
->pipe
;
3052 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3053 pipe_name(intel_dp
->pps_pipe
), port_name(encoder
->port
));
3055 /* init power sequencer on this pipe and port */
3056 intel_dp_init_panel_power_sequencer(intel_dp
);
3057 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
3060 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3061 const struct intel_crtc_state
*pipe_config
,
3062 const struct drm_connector_state
*conn_state
)
3064 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
3066 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3069 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3070 const struct intel_crtc_state
*pipe_config
,
3071 const struct drm_connector_state
*conn_state
)
3073 intel_dp_prepare(encoder
, pipe_config
);
3075 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
3078 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3079 const struct intel_crtc_state
*pipe_config
,
3080 const struct drm_connector_state
*conn_state
)
3082 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
3084 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3086 /* Second common lane will stay alive on its own now */
3087 chv_phy_release_cl2_override(encoder
);
3090 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3091 const struct intel_crtc_state
*pipe_config
,
3092 const struct drm_connector_state
*conn_state
)
3094 intel_dp_prepare(encoder
, pipe_config
);
3096 chv_phy_pre_pll_enable(encoder
, pipe_config
);
3099 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3100 const struct intel_crtc_state
*old_crtc_state
,
3101 const struct drm_connector_state
*old_conn_state
)
3103 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
3107 * Fetch AUX CH registers 0x202 - 0x207 which contain
3108 * link status information
3111 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3113 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3114 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3117 static bool intel_dp_get_y_cord_status(struct intel_dp
*intel_dp
)
3119 uint8_t psr_caps
= 0;
3121 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_PSR_CAPS
, &psr_caps
) != 1)
3123 return psr_caps
& DP_PSR2_SU_Y_COORDINATE_REQUIRED
;
3126 static bool intel_dp_get_colorimetry_status(struct intel_dp
*intel_dp
)
3130 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DPRX_FEATURE_ENUMERATION_LIST
,
3133 return dprx
& DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
;
3136 static bool intel_dp_get_alpm_status(struct intel_dp
*intel_dp
)
3138 uint8_t alpm_caps
= 0;
3140 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_RECEIVER_ALPM_CAP
,
3143 return alpm_caps
& DP_ALPM_CAP
;
3146 /* These are source-specific values. */
3148 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3150 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3151 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
3153 if (INTEL_GEN(dev_priv
) >= 9) {
3154 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3155 return intel_ddi_dp_voltage_max(encoder
);
3156 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3157 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3158 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3159 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3160 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3161 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3163 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3167 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3169 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3170 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
3172 if (INTEL_GEN(dev_priv
) >= 9) {
3173 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3175 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3177 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3179 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3181 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3183 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3185 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3186 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3188 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3190 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3192 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3195 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3197 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3198 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3200 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3202 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3204 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3207 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3209 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3210 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3212 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3215 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3217 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3220 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3222 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3224 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3226 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3229 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3234 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3236 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3237 unsigned long demph_reg_value
, preemph_reg_value
,
3238 uniqtranscale_reg_value
;
3239 uint8_t train_set
= intel_dp
->train_set
[0];
3241 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3242 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3243 preemph_reg_value
= 0x0004000;
3244 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3246 demph_reg_value
= 0x2B405555;
3247 uniqtranscale_reg_value
= 0x552AB83A;
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3250 demph_reg_value
= 0x2B404040;
3251 uniqtranscale_reg_value
= 0x5548B83A;
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3254 demph_reg_value
= 0x2B245555;
3255 uniqtranscale_reg_value
= 0x5560B83A;
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3258 demph_reg_value
= 0x2B405555;
3259 uniqtranscale_reg_value
= 0x5598DA3A;
3265 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3266 preemph_reg_value
= 0x0002000;
3267 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3268 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3269 demph_reg_value
= 0x2B404040;
3270 uniqtranscale_reg_value
= 0x5552B83A;
3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3273 demph_reg_value
= 0x2B404848;
3274 uniqtranscale_reg_value
= 0x5580B83A;
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3277 demph_reg_value
= 0x2B404040;
3278 uniqtranscale_reg_value
= 0x55ADDA3A;
3284 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3285 preemph_reg_value
= 0x0000000;
3286 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3288 demph_reg_value
= 0x2B305555;
3289 uniqtranscale_reg_value
= 0x5570B83A;
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3292 demph_reg_value
= 0x2B2B4040;
3293 uniqtranscale_reg_value
= 0x55ADDA3A;
3299 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3300 preemph_reg_value
= 0x0006000;
3301 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3303 demph_reg_value
= 0x1B405555;
3304 uniqtranscale_reg_value
= 0x55ADDA3A;
3314 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3315 uniqtranscale_reg_value
, 0);
3320 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3322 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3323 u32 deemph_reg_value
, margin_reg_value
;
3324 bool uniq_trans_scale
= false;
3325 uint8_t train_set
= intel_dp
->train_set
[0];
3327 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3328 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3329 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3331 deemph_reg_value
= 128;
3332 margin_reg_value
= 52;
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3335 deemph_reg_value
= 128;
3336 margin_reg_value
= 77;
3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3339 deemph_reg_value
= 128;
3340 margin_reg_value
= 102;
3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3343 deemph_reg_value
= 128;
3344 margin_reg_value
= 154;
3345 uniq_trans_scale
= true;
3351 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3352 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3354 deemph_reg_value
= 85;
3355 margin_reg_value
= 78;
3357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3358 deemph_reg_value
= 85;
3359 margin_reg_value
= 116;
3361 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3362 deemph_reg_value
= 85;
3363 margin_reg_value
= 154;
3369 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3370 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3372 deemph_reg_value
= 64;
3373 margin_reg_value
= 104;
3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3376 deemph_reg_value
= 64;
3377 margin_reg_value
= 154;
3383 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3384 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3386 deemph_reg_value
= 43;
3387 margin_reg_value
= 154;
3397 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3398 margin_reg_value
, uniq_trans_scale
);
3404 gen4_signal_levels(uint8_t train_set
)
3406 uint32_t signal_levels
= 0;
3408 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3411 signal_levels
|= DP_VOLTAGE_0_4
;
3413 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3414 signal_levels
|= DP_VOLTAGE_0_6
;
3416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3417 signal_levels
|= DP_VOLTAGE_0_8
;
3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3420 signal_levels
|= DP_VOLTAGE_1_2
;
3423 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3424 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3426 signal_levels
|= DP_PRE_EMPHASIS_0
;
3428 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3429 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3431 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3432 signal_levels
|= DP_PRE_EMPHASIS_6
;
3434 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3435 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3438 return signal_levels
;
3441 /* Gen6's DP voltage swing and pre-emphasis control */
3443 gen6_edp_signal_levels(uint8_t train_set
)
3445 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3446 DP_TRAIN_PRE_EMPHASIS_MASK
);
3447 switch (signal_levels
) {
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3450 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3452 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3455 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3458 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3461 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3463 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3464 "0x%x\n", signal_levels
);
3465 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3469 /* Gen7's DP voltage swing and pre-emphasis control */
3471 gen7_edp_signal_levels(uint8_t train_set
)
3473 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3474 DP_TRAIN_PRE_EMPHASIS_MASK
);
3475 switch (signal_levels
) {
3476 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3477 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3478 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3479 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3481 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3483 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3484 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3485 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3486 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3488 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3489 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3490 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3491 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3494 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3495 "0x%x\n", signal_levels
);
3496 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3501 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3503 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3504 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3505 enum port port
= intel_dig_port
->base
.port
;
3506 uint32_t signal_levels
, mask
= 0;
3507 uint8_t train_set
= intel_dp
->train_set
[0];
3509 if (IS_GEN9_LP(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
3510 signal_levels
= bxt_signal_levels(intel_dp
);
3511 } else if (HAS_DDI(dev_priv
)) {
3512 signal_levels
= ddi_signal_levels(intel_dp
);
3513 mask
= DDI_BUF_EMP_MASK
;
3514 } else if (IS_CHERRYVIEW(dev_priv
)) {
3515 signal_levels
= chv_signal_levels(intel_dp
);
3516 } else if (IS_VALLEYVIEW(dev_priv
)) {
3517 signal_levels
= vlv_signal_levels(intel_dp
);
3518 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3519 signal_levels
= gen7_edp_signal_levels(train_set
);
3520 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3521 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3522 signal_levels
= gen6_edp_signal_levels(train_set
);
3523 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3525 signal_levels
= gen4_signal_levels(train_set
);
3526 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3530 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3532 DRM_DEBUG_KMS("Using vswing level %d\n",
3533 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3534 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3535 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3536 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3538 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3540 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3541 POSTING_READ(intel_dp
->output_reg
);
3545 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3546 uint8_t dp_train_pat
)
3548 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3549 struct drm_i915_private
*dev_priv
=
3550 to_i915(intel_dig_port
->base
.base
.dev
);
3552 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3554 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3555 POSTING_READ(intel_dp
->output_reg
);
3558 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3560 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3561 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3562 enum port port
= intel_dig_port
->base
.port
;
3565 if (!HAS_DDI(dev_priv
))
3568 val
= I915_READ(DP_TP_CTL(port
));
3569 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3570 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3571 I915_WRITE(DP_TP_CTL(port
), val
);
3574 * On PORT_A we can have only eDP in SST mode. There the only reason
3575 * we need to set idle transmission mode is to work around a HW issue
3576 * where we enable the pipe while not in idle link-training mode.
3577 * In this case there is requirement to wait for a minimum number of
3578 * idle patterns to be sent.
3583 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3584 DP_TP_STATUS_IDLE_DONE
,
3585 DP_TP_STATUS_IDLE_DONE
,
3587 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3591 intel_dp_link_down(struct intel_encoder
*encoder
,
3592 const struct intel_crtc_state
*old_crtc_state
)
3594 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3595 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3596 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
3597 enum port port
= encoder
->port
;
3598 uint32_t DP
= intel_dp
->DP
;
3600 if (WARN_ON(HAS_DDI(dev_priv
)))
3603 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3606 DRM_DEBUG_KMS("\n");
3608 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3609 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3610 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3611 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3613 if (IS_CHERRYVIEW(dev_priv
))
3614 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3616 DP
&= ~DP_LINK_TRAIN_MASK
;
3617 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3619 I915_WRITE(intel_dp
->output_reg
, DP
);
3620 POSTING_READ(intel_dp
->output_reg
);
3622 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3623 I915_WRITE(intel_dp
->output_reg
, DP
);
3624 POSTING_READ(intel_dp
->output_reg
);
3627 * HW workaround for IBX, we need to move the port
3628 * to transcoder A after disabling it to allow the
3629 * matching HDMI port to be enabled on transcoder A.
3631 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3633 * We get CPU/PCH FIFO underruns on the other pipe when
3634 * doing the workaround. Sweep them under the rug.
3636 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3637 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3639 /* always enable with pattern 1 (as per spec) */
3640 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3641 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3642 I915_WRITE(intel_dp
->output_reg
, DP
);
3643 POSTING_READ(intel_dp
->output_reg
);
3646 I915_WRITE(intel_dp
->output_reg
, DP
);
3647 POSTING_READ(intel_dp
->output_reg
);
3649 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3650 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3651 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3654 msleep(intel_dp
->panel_power_down_delay
);
3658 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3660 intel_dp
->active_pipe
= INVALID_PIPE
;
3661 pps_unlock(intel_dp
);
3666 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3668 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3669 sizeof(intel_dp
->dpcd
)) < 0)
3670 return false; /* aux transfer failed */
3672 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3674 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3678 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3680 struct drm_i915_private
*dev_priv
=
3681 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3683 /* this function is meant to be called only once */
3684 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3686 if (!intel_dp_read_dpcd(intel_dp
))
3689 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
3690 drm_dp_is_branch(intel_dp
->dpcd
));
3692 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3693 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3694 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3696 /* Check if the panel supports PSR */
3697 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3699 sizeof(intel_dp
->psr_dpcd
));
3700 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3701 dev_priv
->psr
.sink_support
= true;
3702 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3705 if (INTEL_GEN(dev_priv
) >= 9 &&
3706 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3707 uint8_t frame_sync_cap
;
3709 dev_priv
->psr
.sink_support
= true;
3710 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3711 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3712 &frame_sync_cap
) != 1)
3714 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3715 /* PSR2 needs frame sync as well */
3716 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3717 DRM_DEBUG_KMS("PSR2 %s on sink",
3718 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3720 if (dev_priv
->psr
.psr2_support
) {
3721 dev_priv
->psr
.y_cord_support
=
3722 intel_dp_get_y_cord_status(intel_dp
);
3723 dev_priv
->psr
.colorimetry_support
=
3724 intel_dp_get_colorimetry_status(intel_dp
);
3725 dev_priv
->psr
.alpm
=
3726 intel_dp_get_alpm_status(intel_dp
);
3732 * Read the eDP display control registers.
3734 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3735 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3736 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3737 * method). The display control registers should read zero if they're
3738 * not supported anyway.
3740 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3741 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3742 sizeof(intel_dp
->edp_dpcd
))
3743 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3744 intel_dp
->edp_dpcd
);
3746 /* Read the eDP 1.4+ supported link rates. */
3747 if (intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
3748 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3751 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3752 sink_rates
, sizeof(sink_rates
));
3754 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3755 int val
= le16_to_cpu(sink_rates
[i
]);
3760 /* Value read multiplied by 200kHz gives the per-lane
3761 * link rate in kHz. The source rates are, however,
3762 * stored in terms of LS_Clk kHz. The full conversion
3763 * back to symbols is
3764 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3766 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3768 intel_dp
->num_sink_rates
= i
;
3772 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3773 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3775 if (intel_dp
->num_sink_rates
)
3776 intel_dp
->use_rate_select
= true;
3778 intel_dp_set_sink_rates(intel_dp
);
3780 intel_dp_set_common_rates(intel_dp
);
3787 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3791 if (!intel_dp_read_dpcd(intel_dp
))
3794 /* Don't clobber cached eDP rates. */
3795 if (!intel_dp_is_edp(intel_dp
)) {
3796 intel_dp_set_sink_rates(intel_dp
);
3797 intel_dp_set_common_rates(intel_dp
);
3800 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &sink_count
) <= 0)
3804 * Sink count can change between short pulse hpd hence
3805 * a member variable in intel_dp will track any changes
3806 * between short pulse interrupts.
3808 intel_dp
->sink_count
= DP_GET_SINK_COUNT(sink_count
);
3811 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3812 * a dongle is present but no display. Unless we require to know
3813 * if a dongle is present or not, we don't need to update
3814 * downstream port information. So, an early return here saves
3815 * time from performing other operations which are not required.
3817 if (!intel_dp_is_edp(intel_dp
) && !intel_dp
->sink_count
)
3820 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3821 return true; /* native DP sink */
3823 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3824 return true; /* no per-port downstream info */
3826 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3827 intel_dp
->downstream_ports
,
3828 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3829 return false; /* downstream port status fetch failed */
3835 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3839 if (!i915_modparams
.enable_dp_mst
)
3842 if (!intel_dp
->can_mst
)
3845 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3848 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
3851 return mstm_cap
& DP_MST_CAP
;
3855 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3857 if (!i915_modparams
.enable_dp_mst
)
3860 if (!intel_dp
->can_mst
)
3863 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3865 if (intel_dp
->is_mst
)
3866 DRM_DEBUG_KMS("Sink is MST capable\n");
3868 DRM_DEBUG_KMS("Sink is not MST capable\n");
3870 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3874 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
,
3875 struct intel_crtc_state
*crtc_state
, bool disable_wa
)
3877 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3878 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3879 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3885 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3886 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3891 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3892 buf
& ~DP_TEST_SINK_START
) < 0) {
3893 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3899 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3901 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3902 DP_TEST_SINK_MISC
, &buf
) < 0) {
3906 count
= buf
& DP_TEST_COUNT_MASK
;
3907 } while (--attempts
&& count
);
3909 if (attempts
== 0) {
3910 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3916 hsw_enable_ips(crtc_state
);
3920 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
,
3921 struct intel_crtc_state
*crtc_state
)
3923 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3924 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3925 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3929 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3932 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3935 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3938 if (buf
& DP_TEST_SINK_START
) {
3939 ret
= intel_dp_sink_crc_stop(intel_dp
, crtc_state
, false);
3944 hsw_disable_ips(crtc_state
);
3946 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3947 buf
| DP_TEST_SINK_START
) < 0) {
3948 hsw_enable_ips(crtc_state
);
3952 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3956 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, struct intel_crtc_state
*crtc_state
, u8
*crc
)
3958 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3959 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3960 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3965 ret
= intel_dp_sink_crc_start(intel_dp
, crtc_state
);
3970 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3972 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3973 DP_TEST_SINK_MISC
, &buf
) < 0) {
3977 count
= buf
& DP_TEST_COUNT_MASK
;
3979 } while (--attempts
&& count
== 0);
3981 if (attempts
== 0) {
3982 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3987 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3993 intel_dp_sink_crc_stop(intel_dp
, crtc_state
, true);
3998 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4000 return drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
4001 sink_irq_vector
) == 1;
4005 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4007 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT_ESI
,
4008 sink_irq_vector
, DP_DPRX_ESI_LEN
) ==
4012 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4016 uint8_t test_lane_count
, test_link_bw
;
4020 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4021 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4025 DRM_DEBUG_KMS("Lane count read failed\n");
4028 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4030 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4033 DRM_DEBUG_KMS("Link Rate read failed\n");
4036 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4038 /* Validate the requested link rate and lane count */
4039 if (!intel_dp_link_params_valid(intel_dp
, test_link_rate
,
4043 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4044 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4049 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4051 uint8_t test_pattern
;
4053 __be16 h_width
, v_height
;
4056 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4057 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4060 DRM_DEBUG_KMS("Test pattern read failed\n");
4063 if (test_pattern
!= DP_COLOR_RAMP
)
4066 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4069 DRM_DEBUG_KMS("H Width read failed\n");
4073 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4076 DRM_DEBUG_KMS("V Height read failed\n");
4080 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4083 DRM_DEBUG_KMS("TEST MISC read failed\n");
4086 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4088 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4090 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4091 case DP_TEST_BIT_DEPTH_6
:
4092 intel_dp
->compliance
.test_data
.bpc
= 6;
4094 case DP_TEST_BIT_DEPTH_8
:
4095 intel_dp
->compliance
.test_data
.bpc
= 8;
4101 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4102 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4103 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4104 /* Set test active flag here so userspace doesn't interrupt things */
4105 intel_dp
->compliance
.test_active
= 1;
4110 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4112 uint8_t test_result
= DP_TEST_ACK
;
4113 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4114 struct drm_connector
*connector
= &intel_connector
->base
;
4116 if (intel_connector
->detect_edid
== NULL
||
4117 connector
->edid_corrupt
||
4118 intel_dp
->aux
.i2c_defer_count
> 6) {
4119 /* Check EDID read for NACKs, DEFERs and corruption
4120 * (DP CTS 1.2 Core r1.1)
4121 * 4.2.2.4 : Failed EDID read, I2C_NAK
4122 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4123 * 4.2.2.6 : EDID corruption detected
4124 * Use failsafe mode for all cases
4126 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4127 intel_dp
->aux
.i2c_defer_count
> 0)
4128 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4129 intel_dp
->aux
.i2c_nack_count
,
4130 intel_dp
->aux
.i2c_defer_count
);
4131 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4133 struct edid
*block
= intel_connector
->detect_edid
;
4135 /* We have to write the checksum
4136 * of the last block read
4138 block
+= intel_connector
->detect_edid
->extensions
;
4140 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4141 block
->checksum
) <= 0)
4142 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4144 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4145 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4148 /* Set test active flag here so userspace doesn't interrupt things */
4149 intel_dp
->compliance
.test_active
= 1;
4154 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4156 uint8_t test_result
= DP_TEST_NAK
;
4160 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4162 uint8_t response
= DP_TEST_NAK
;
4163 uint8_t request
= 0;
4166 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4168 DRM_DEBUG_KMS("Could not read test request from sink\n");
4173 case DP_TEST_LINK_TRAINING
:
4174 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4175 response
= intel_dp_autotest_link_training(intel_dp
);
4177 case DP_TEST_LINK_VIDEO_PATTERN
:
4178 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4179 response
= intel_dp_autotest_video_pattern(intel_dp
);
4181 case DP_TEST_LINK_EDID_READ
:
4182 DRM_DEBUG_KMS("EDID test requested\n");
4183 response
= intel_dp_autotest_edid(intel_dp
);
4185 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4186 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4187 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4190 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4194 if (response
& DP_TEST_ACK
)
4195 intel_dp
->compliance
.test_type
= request
;
4198 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4200 DRM_DEBUG_KMS("Could not write test response to sink\n");
4204 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4208 if (intel_dp
->is_mst
) {
4209 u8 esi
[DP_DPRX_ESI_LEN
] = { 0 };
4213 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4217 /* check link status - esi[10] = 0x200c */
4218 if (intel_dp
->active_mst_links
&&
4219 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4220 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4221 intel_dp_start_link_train(intel_dp
);
4222 intel_dp_stop_link_train(intel_dp
);
4225 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4226 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4229 for (retry
= 0; retry
< 3; retry
++) {
4231 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4232 DP_SINK_COUNT_ESI
+1,
4239 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4241 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4249 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4250 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4251 intel_dp
->is_mst
= false;
4252 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4253 /* send a hotplug event */
4254 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4261 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
4263 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4264 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4265 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4267 /* Suppress underruns caused by re-training */
4268 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4269 if (crtc
->config
->has_pch_encoder
)
4270 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4271 intel_crtc_pch_transcoder(crtc
), false);
4273 intel_dp_start_link_train(intel_dp
);
4274 intel_dp_stop_link_train(intel_dp
);
4276 /* Keep underrun reporting disabled until things are stable */
4277 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4279 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4280 if (crtc
->config
->has_pch_encoder
)
4281 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4282 intel_crtc_pch_transcoder(crtc
), true);
4286 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4288 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4289 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4290 struct drm_connector_state
*conn_state
=
4291 intel_dp
->attached_connector
->base
.state
;
4292 u8 link_status
[DP_LINK_STATUS_SIZE
];
4294 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
4296 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4297 DRM_ERROR("Failed to get link status\n");
4301 if (!conn_state
->crtc
)
4304 WARN_ON(!drm_modeset_is_locked(&conn_state
->crtc
->mutex
));
4306 if (!conn_state
->crtc
->state
->active
)
4309 if (conn_state
->commit
&&
4310 !try_wait_for_completion(&conn_state
->commit
->hw_done
))
4314 * Validate the cached values of intel_dp->link_rate and
4315 * intel_dp->lane_count before attempting to retrain.
4317 if (!intel_dp_link_params_valid(intel_dp
, intel_dp
->link_rate
,
4318 intel_dp
->lane_count
))
4321 /* Retrain if Channel EQ or CR not ok */
4322 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4323 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4324 intel_encoder
->base
.name
);
4326 intel_dp_retrain_link(intel_dp
);
4331 * According to DP spec
4334 * 2. Configure link according to Receiver Capabilities
4335 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4336 * 4. Check link status on receipt of hot-plug interrupt
4338 * intel_dp_short_pulse - handles short pulse interrupts
4339 * when full detection is not required.
4340 * Returns %true if short pulse is handled and full detection
4341 * is NOT required and %false otherwise.
4344 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4346 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4347 u8 sink_irq_vector
= 0;
4348 u8 old_sink_count
= intel_dp
->sink_count
;
4352 * Clearing compliance test variables to allow capturing
4353 * of values for next automated test request.
4355 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4358 * Now read the DPCD to see if it's actually running
4359 * If the current value of sink count doesn't match with
4360 * the value that was stored earlier or dpcd read failed
4361 * we need to do full detection
4363 ret
= intel_dp_get_dpcd(intel_dp
);
4365 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4366 /* No need to proceed if we are going to do full detect */
4370 /* Try to read the source of the interrupt */
4371 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4372 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4373 sink_irq_vector
!= 0) {
4374 /* Clear interrupt source */
4375 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4376 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4379 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4380 intel_dp_handle_test_request(intel_dp
);
4381 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4382 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4385 intel_dp_check_link_status(intel_dp
);
4387 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4388 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4389 /* Send a Hotplug Uevent to userspace to start modeset */
4390 drm_kms_helper_hotplug_event(&dev_priv
->drm
);
4396 /* XXX this is probably wrong for multiple downstream ports */
4397 static enum drm_connector_status
4398 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4400 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4401 uint8_t *dpcd
= intel_dp
->dpcd
;
4405 lspcon_resume(lspcon
);
4407 if (!intel_dp_get_dpcd(intel_dp
))
4408 return connector_status_disconnected
;
4410 if (intel_dp_is_edp(intel_dp
))
4411 return connector_status_connected
;
4413 /* if there's no downstream port, we're done */
4414 if (!drm_dp_is_branch(dpcd
))
4415 return connector_status_connected
;
4417 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4418 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4419 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4421 return intel_dp
->sink_count
?
4422 connector_status_connected
: connector_status_disconnected
;
4425 if (intel_dp_can_mst(intel_dp
))
4426 return connector_status_connected
;
4428 /* If no HPD, poke DDC gently */
4429 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4430 return connector_status_connected
;
4432 /* Well we tried, say unknown for unreliable port types */
4433 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4434 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4435 if (type
== DP_DS_PORT_TYPE_VGA
||
4436 type
== DP_DS_PORT_TYPE_NON_EDID
)
4437 return connector_status_unknown
;
4439 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4440 DP_DWN_STRM_PORT_TYPE_MASK
;
4441 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4442 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4443 return connector_status_unknown
;
4446 /* Anything else is out of spec, warn and ignore */
4447 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4448 return connector_status_disconnected
;
4451 static enum drm_connector_status
4452 edp_detect(struct intel_dp
*intel_dp
)
4454 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4455 enum drm_connector_status status
;
4457 status
= intel_panel_detect(dev_priv
);
4458 if (status
== connector_status_unknown
)
4459 status
= connector_status_connected
;
4464 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4465 struct intel_digital_port
*port
)
4469 switch (port
->base
.port
) {
4471 bit
= SDE_PORTB_HOTPLUG
;
4474 bit
= SDE_PORTC_HOTPLUG
;
4477 bit
= SDE_PORTD_HOTPLUG
;
4480 MISSING_CASE(port
->base
.port
);
4484 return I915_READ(SDEISR
) & bit
;
4487 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4488 struct intel_digital_port
*port
)
4492 switch (port
->base
.port
) {
4494 bit
= SDE_PORTB_HOTPLUG_CPT
;
4497 bit
= SDE_PORTC_HOTPLUG_CPT
;
4500 bit
= SDE_PORTD_HOTPLUG_CPT
;
4503 MISSING_CASE(port
->base
.port
);
4507 return I915_READ(SDEISR
) & bit
;
4510 static bool spt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4511 struct intel_digital_port
*port
)
4515 switch (port
->base
.port
) {
4517 bit
= SDE_PORTA_HOTPLUG_SPT
;
4520 bit
= SDE_PORTE_HOTPLUG_SPT
;
4523 return cpt_digital_port_connected(dev_priv
, port
);
4526 return I915_READ(SDEISR
) & bit
;
4529 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4530 struct intel_digital_port
*port
)
4534 switch (port
->base
.port
) {
4536 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4539 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4542 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4545 MISSING_CASE(port
->base
.port
);
4549 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4552 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4553 struct intel_digital_port
*port
)
4557 switch (port
->base
.port
) {
4559 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4562 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4565 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4568 MISSING_CASE(port
->base
.port
);
4572 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4575 static bool ilk_digital_port_connected(struct drm_i915_private
*dev_priv
,
4576 struct intel_digital_port
*port
)
4578 if (port
->base
.port
== PORT_A
)
4579 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4581 return ibx_digital_port_connected(dev_priv
, port
);
4584 static bool snb_digital_port_connected(struct drm_i915_private
*dev_priv
,
4585 struct intel_digital_port
*port
)
4587 if (port
->base
.port
== PORT_A
)
4588 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4590 return cpt_digital_port_connected(dev_priv
, port
);
4593 static bool ivb_digital_port_connected(struct drm_i915_private
*dev_priv
,
4594 struct intel_digital_port
*port
)
4596 if (port
->base
.port
== PORT_A
)
4597 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
4599 return cpt_digital_port_connected(dev_priv
, port
);
4602 static bool bdw_digital_port_connected(struct drm_i915_private
*dev_priv
,
4603 struct intel_digital_port
*port
)
4605 if (port
->base
.port
== PORT_A
)
4606 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
4608 return cpt_digital_port_connected(dev_priv
, port
);
4611 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4612 struct intel_digital_port
*intel_dig_port
)
4614 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4618 port
= intel_hpd_pin_to_port(intel_encoder
->hpd_pin
);
4621 bit
= BXT_DE_PORT_HP_DDIA
;
4624 bit
= BXT_DE_PORT_HP_DDIB
;
4627 bit
= BXT_DE_PORT_HP_DDIC
;
4634 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4638 * intel_digital_port_connected - is the specified port connected?
4639 * @dev_priv: i915 private structure
4640 * @port: the port to test
4642 * Return %true if @port is connected, %false otherwise.
4644 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4645 struct intel_digital_port
*port
)
4647 if (HAS_GMCH_DISPLAY(dev_priv
)) {
4648 if (IS_GM45(dev_priv
))
4649 return gm45_digital_port_connected(dev_priv
, port
);
4651 return g4x_digital_port_connected(dev_priv
, port
);
4654 if (IS_GEN5(dev_priv
))
4655 return ilk_digital_port_connected(dev_priv
, port
);
4656 else if (IS_GEN6(dev_priv
))
4657 return snb_digital_port_connected(dev_priv
, port
);
4658 else if (IS_GEN7(dev_priv
))
4659 return ivb_digital_port_connected(dev_priv
, port
);
4660 else if (IS_GEN8(dev_priv
))
4661 return bdw_digital_port_connected(dev_priv
, port
);
4662 else if (IS_GEN9_LP(dev_priv
))
4663 return bxt_digital_port_connected(dev_priv
, port
);
4665 return spt_digital_port_connected(dev_priv
, port
);
4668 static struct edid
*
4669 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4671 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4673 /* use cached edid if we have one */
4674 if (intel_connector
->edid
) {
4676 if (IS_ERR(intel_connector
->edid
))
4679 return drm_edid_duplicate(intel_connector
->edid
);
4681 return drm_get_edid(&intel_connector
->base
,
4682 &intel_dp
->aux
.ddc
);
4686 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4688 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4691 intel_dp_unset_edid(intel_dp
);
4692 edid
= intel_dp_get_edid(intel_dp
);
4693 intel_connector
->detect_edid
= edid
;
4695 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4699 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4701 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4703 kfree(intel_connector
->detect_edid
);
4704 intel_connector
->detect_edid
= NULL
;
4706 intel_dp
->has_audio
= false;
4710 intel_dp_long_pulse(struct intel_connector
*connector
)
4712 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
4713 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
4714 enum drm_connector_status status
;
4715 u8 sink_irq_vector
= 0;
4717 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
4719 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4721 /* Can't disconnect eDP, but you can close the lid... */
4722 if (intel_dp_is_edp(intel_dp
))
4723 status
= edp_detect(intel_dp
);
4724 else if (intel_digital_port_connected(dev_priv
,
4725 dp_to_dig_port(intel_dp
)))
4726 status
= intel_dp_detect_dpcd(intel_dp
);
4728 status
= connector_status_disconnected
;
4730 if (status
== connector_status_disconnected
) {
4731 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4733 if (intel_dp
->is_mst
) {
4734 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4736 intel_dp
->mst_mgr
.mst_state
);
4737 intel_dp
->is_mst
= false;
4738 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4745 if (intel_dp
->reset_link_params
) {
4746 /* Initial max link lane count */
4747 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
4749 /* Initial max link rate */
4750 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
4752 intel_dp
->reset_link_params
= false;
4755 intel_dp_print_rates(intel_dp
);
4757 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4758 drm_dp_is_branch(intel_dp
->dpcd
));
4760 intel_dp_configure_mst(intel_dp
);
4762 if (intel_dp
->is_mst
) {
4764 * If we are in MST mode then this connector
4765 * won't appear connected or have anything
4768 status
= connector_status_disconnected
;
4772 * If display is now connected check links status,
4773 * there has been known issues of link loss triggerring
4776 * Some sinks (eg. ASUS PB287Q) seem to perform some
4777 * weird HPD ping pong during modesets. So we can apparently
4778 * end up with HPD going low during a modeset, and then
4779 * going back up soon after. And once that happens we must
4780 * retrain the link to get a picture. That's in case no
4781 * userspace component reacted to intermittent HPD dip.
4783 intel_dp_check_link_status(intel_dp
);
4787 * Clearing NACK and defer counts to get their exact values
4788 * while reading EDID which are required by Compliance tests
4789 * 4.2.2.4 and 4.2.2.5
4791 intel_dp
->aux
.i2c_nack_count
= 0;
4792 intel_dp
->aux
.i2c_defer_count
= 0;
4794 intel_dp_set_edid(intel_dp
);
4795 if (intel_dp_is_edp(intel_dp
) || connector
->detect_edid
)
4796 status
= connector_status_connected
;
4797 intel_dp
->detect_done
= true;
4799 /* Try to read the source of the interrupt */
4800 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4801 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4802 sink_irq_vector
!= 0) {
4803 /* Clear interrupt source */
4804 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4805 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4808 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4809 intel_dp_handle_test_request(intel_dp
);
4810 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4811 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4815 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4816 intel_dp_unset_edid(intel_dp
);
4818 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4823 intel_dp_detect(struct drm_connector
*connector
,
4824 struct drm_modeset_acquire_ctx
*ctx
,
4827 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4828 int status
= connector
->status
;
4830 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4831 connector
->base
.id
, connector
->name
);
4833 /* If full detect is not performed yet, do a full detect */
4834 if (!intel_dp
->detect_done
) {
4835 struct drm_crtc
*crtc
;
4838 crtc
= connector
->state
->crtc
;
4840 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
4845 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4848 intel_dp
->detect_done
= false;
4854 intel_dp_force(struct drm_connector
*connector
)
4856 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4857 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4858 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4860 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4861 connector
->base
.id
, connector
->name
);
4862 intel_dp_unset_edid(intel_dp
);
4864 if (connector
->status
!= connector_status_connected
)
4867 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4869 intel_dp_set_edid(intel_dp
);
4871 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4874 static int intel_dp_get_modes(struct drm_connector
*connector
)
4876 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4879 edid
= intel_connector
->detect_edid
;
4881 int ret
= intel_connector_update_modes(connector
, edid
);
4886 /* if eDP has no EDID, fall back to fixed mode */
4887 if (intel_dp_is_edp(intel_attached_dp(connector
)) &&
4888 intel_connector
->panel
.fixed_mode
) {
4889 struct drm_display_mode
*mode
;
4891 mode
= drm_mode_duplicate(connector
->dev
,
4892 intel_connector
->panel
.fixed_mode
);
4894 drm_mode_probed_add(connector
, mode
);
4903 intel_dp_connector_register(struct drm_connector
*connector
)
4905 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4908 ret
= intel_connector_register(connector
);
4912 i915_debugfs_connector_add(connector
);
4914 DRM_DEBUG_KMS("registering %s bus for %s\n",
4915 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4917 intel_dp
->aux
.dev
= connector
->kdev
;
4918 return drm_dp_aux_register(&intel_dp
->aux
);
4922 intel_dp_connector_unregister(struct drm_connector
*connector
)
4924 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4925 intel_connector_unregister(connector
);
4929 intel_dp_connector_destroy(struct drm_connector
*connector
)
4931 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4933 kfree(intel_connector
->detect_edid
);
4935 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4936 kfree(intel_connector
->edid
);
4939 * Can't call intel_dp_is_edp() since the encoder may have been
4940 * destroyed already.
4942 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4943 intel_panel_fini(&intel_connector
->panel
);
4945 drm_connector_cleanup(connector
);
4949 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4951 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4952 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4954 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4955 if (intel_dp_is_edp(intel_dp
)) {
4956 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4958 * vdd might still be enabled do to the delayed vdd off.
4959 * Make sure vdd is actually turned off here.
4962 edp_panel_vdd_off_sync(intel_dp
);
4963 pps_unlock(intel_dp
);
4965 if (intel_dp
->edp_notifier
.notifier_call
) {
4966 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4967 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4971 intel_dp_aux_fini(intel_dp
);
4973 drm_encoder_cleanup(encoder
);
4974 kfree(intel_dig_port
);
4977 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4979 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4981 if (!intel_dp_is_edp(intel_dp
))
4985 * vdd might still be enabled do to the delayed vdd off.
4986 * Make sure vdd is actually turned off here.
4988 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4990 edp_panel_vdd_off_sync(intel_dp
);
4991 pps_unlock(intel_dp
);
4994 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4996 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4998 lockdep_assert_held(&dev_priv
->pps_mutex
);
5000 if (!edp_have_panel_vdd(intel_dp
))
5004 * The VDD bit needs a power domain reference, so if the bit is
5005 * already enabled when we boot or resume, grab this reference and
5006 * schedule a vdd off, so we don't hold on to the reference
5009 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5010 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5012 edp_panel_vdd_schedule_off(intel_dp
);
5015 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
5017 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5019 if ((intel_dp
->DP
& DP_PORT_EN
) == 0)
5020 return INVALID_PIPE
;
5022 if (IS_CHERRYVIEW(dev_priv
))
5023 return DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5025 return PORT_TO_PIPE(intel_dp
->DP
);
5028 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
5030 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
5031 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
5032 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
5034 if (!HAS_DDI(dev_priv
))
5035 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5038 lspcon_resume(lspcon
);
5040 intel_dp
->reset_link_params
= true;
5044 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5045 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5047 if (intel_dp_is_edp(intel_dp
)) {
5048 /* Reinit the power sequencer, in case BIOS did something with it. */
5049 intel_dp_pps_init(intel_dp
);
5050 intel_edp_panel_vdd_sanitize(intel_dp
);
5053 pps_unlock(intel_dp
);
5056 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5057 .force
= intel_dp_force
,
5058 .fill_modes
= drm_helper_probe_single_connector_modes
,
5059 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
5060 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
5061 .late_register
= intel_dp_connector_register
,
5062 .early_unregister
= intel_dp_connector_unregister
,
5063 .destroy
= intel_dp_connector_destroy
,
5064 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5065 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5068 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5069 .detect_ctx
= intel_dp_detect
,
5070 .get_modes
= intel_dp_get_modes
,
5071 .mode_valid
= intel_dp_mode_valid
,
5072 .atomic_check
= intel_digital_connector_atomic_check
,
5075 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5076 .reset
= intel_dp_encoder_reset
,
5077 .destroy
= intel_dp_encoder_destroy
,
5081 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5083 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5084 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5085 enum irqreturn ret
= IRQ_NONE
;
5087 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5089 * vdd off can generate a long pulse on eDP which
5090 * would require vdd on to handle it, and thus we
5091 * would end up in an endless cycle of
5092 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5094 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5095 port_name(intel_dig_port
->base
.port
));
5099 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5100 port_name(intel_dig_port
->base
.port
),
5101 long_hpd
? "long" : "short");
5104 intel_dp
->reset_link_params
= true;
5105 intel_dp
->detect_done
= false;
5109 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5111 if (intel_dp
->is_mst
) {
5112 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5114 * If we were in MST mode, and device is not
5115 * there, get out of MST mode
5117 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5118 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5119 intel_dp
->is_mst
= false;
5120 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5122 intel_dp
->detect_done
= false;
5127 if (!intel_dp
->is_mst
) {
5128 struct drm_modeset_acquire_ctx ctx
;
5129 struct drm_connector
*connector
= &intel_dp
->attached_connector
->base
;
5130 struct drm_crtc
*crtc
;
5132 bool handled
= false;
5134 drm_modeset_acquire_init(&ctx
, 0);
5136 iret
= drm_modeset_lock(&dev_priv
->drm
.mode_config
.connection_mutex
, &ctx
);
5140 crtc
= connector
->state
->crtc
;
5142 iret
= drm_modeset_lock(&crtc
->mutex
, &ctx
);
5147 handled
= intel_dp_short_pulse(intel_dp
);
5150 if (iret
== -EDEADLK
) {
5151 drm_modeset_backoff(&ctx
);
5155 drm_modeset_drop_locks(&ctx
);
5156 drm_modeset_acquire_fini(&ctx
);
5157 WARN(iret
, "Acquiring modeset locks failed with %i\n", iret
);
5160 intel_dp
->detect_done
= false;
5168 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5173 /* check the VBT to see whether the eDP is on another port */
5174 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5177 * eDP not supported on g4x. so bail out early just
5178 * for a bit extra safety in case the VBT is bonkers.
5180 if (INTEL_GEN(dev_priv
) < 5)
5183 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5186 return intel_bios_is_port_edp(dev_priv
, port
);
5190 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5192 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5193 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5195 if (!IS_G4X(dev_priv
) && port
!= PORT_A
)
5196 intel_attach_force_audio_property(connector
);
5198 intel_attach_broadcast_rgb_property(connector
);
5200 if (intel_dp_is_edp(intel_dp
)) {
5201 u32 allowed_scalers
;
5203 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
5204 if (!HAS_GMCH_DISPLAY(dev_priv
))
5205 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
5207 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
5209 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
5214 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5216 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5217 intel_dp
->last_power_on
= jiffies
;
5218 intel_dp
->last_backlight_off
= jiffies
;
5222 intel_pps_readout_hw_state(struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5224 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5225 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5226 struct pps_registers regs
;
5228 intel_pps_get_registers(intel_dp
, ®s
);
5230 /* Workaround: Need to write PP_CONTROL with the unlock key as
5231 * the very first thing. */
5232 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5234 pp_on
= I915_READ(regs
.pp_on
);
5235 pp_off
= I915_READ(regs
.pp_off
);
5236 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
5237 !HAS_PCH_ICP(dev_priv
)) {
5238 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5239 pp_div
= I915_READ(regs
.pp_div
);
5242 /* Pull timing values out of registers */
5243 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5244 PANEL_POWER_UP_DELAY_SHIFT
;
5246 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5247 PANEL_LIGHT_ON_DELAY_SHIFT
;
5249 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5250 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5252 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5253 PANEL_POWER_DOWN_DELAY_SHIFT
;
5255 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5256 HAS_PCH_ICP(dev_priv
)) {
5257 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5258 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5260 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5261 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5266 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5268 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5270 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5274 intel_pps_verify_state(struct intel_dp
*intel_dp
)
5276 struct edp_power_seq hw
;
5277 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5279 intel_pps_readout_hw_state(intel_dp
, &hw
);
5281 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5282 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5283 DRM_ERROR("PPS state mismatch\n");
5284 intel_pps_dump_state("sw", sw
);
5285 intel_pps_dump_state("hw", &hw
);
5290 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
5292 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5293 struct edp_power_seq cur
, vbt
, spec
,
5294 *final
= &intel_dp
->pps_delays
;
5296 lockdep_assert_held(&dev_priv
->pps_mutex
);
5298 /* already initialized? */
5299 if (final
->t11_t12
!= 0)
5302 intel_pps_readout_hw_state(intel_dp
, &cur
);
5304 intel_pps_dump_state("cur", &cur
);
5306 vbt
= dev_priv
->vbt
.edp
.pps
;
5307 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5308 * of 500ms appears to be too short. Ocassionally the panel
5309 * just fails to power back on. Increasing the delay to 800ms
5310 * seems sufficient to avoid this problem.
5312 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
5313 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 1300 * 10);
5314 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5317 /* T11_T12 delay is special and actually in units of 100ms, but zero
5318 * based in the hw (so we need to add 100 ms). But the sw vbt
5319 * table multiplies it with 1000 to make it in units of 100usec,
5321 vbt
.t11_t12
+= 100 * 10;
5323 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5324 * our hw here, which are all in 100usec. */
5325 spec
.t1_t3
= 210 * 10;
5326 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5327 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5328 spec
.t10
= 500 * 10;
5329 /* This one is special and actually in units of 100ms, but zero
5330 * based in the hw (so we need to add 100 ms). But the sw vbt
5331 * table multiplies it with 1000 to make it in units of 100usec,
5333 spec
.t11_t12
= (510 + 100) * 10;
5335 intel_pps_dump_state("vbt", &vbt
);
5337 /* Use the max of the register settings and vbt. If both are
5338 * unset, fall back to the spec limits. */
5339 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5341 max(cur.field, vbt.field))
5342 assign_final(t1_t3
);
5346 assign_final(t11_t12
);
5349 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5350 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5351 intel_dp
->backlight_on_delay
= get_delay(t8
);
5352 intel_dp
->backlight_off_delay
= get_delay(t9
);
5353 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5354 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5357 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5358 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5359 intel_dp
->panel_power_cycle_delay
);
5361 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5362 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5365 * We override the HW backlight delays to 1 because we do manual waits
5366 * on them. For T8, even BSpec recommends doing it. For T9, if we
5367 * don't do this, we'll end up waiting for the backlight off delay
5368 * twice: once when we do the manual sleep, and once when we disable
5369 * the panel and wait for the PP_STATUS bit to become zero.
5375 * HW has only a 100msec granularity for t11_t12 so round it up
5378 final
->t11_t12
= roundup(final
->t11_t12
, 100 * 10);
5382 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
5383 bool force_disable_vdd
)
5385 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5386 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5387 int div
= dev_priv
->rawclk_freq
/ 1000;
5388 struct pps_registers regs
;
5389 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5390 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5392 lockdep_assert_held(&dev_priv
->pps_mutex
);
5394 intel_pps_get_registers(intel_dp
, ®s
);
5397 * On some VLV machines the BIOS can leave the VDD
5398 * enabled even on power seqeuencers which aren't
5399 * hooked up to any port. This would mess up the
5400 * power domain tracking the first time we pick
5401 * one of these power sequencers for use since
5402 * edp_panel_vdd_on() would notice that the VDD was
5403 * already on and therefore wouldn't grab the power
5404 * domain reference. Disable VDD first to avoid this.
5405 * This also avoids spuriously turning the VDD on as
5406 * soon as the new power seqeuencer gets initialized.
5408 if (force_disable_vdd
) {
5409 u32 pp
= ironlake_get_pp_control(intel_dp
);
5411 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5413 if (pp
& EDP_FORCE_VDD
)
5414 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5416 pp
&= ~EDP_FORCE_VDD
;
5418 I915_WRITE(regs
.pp_ctrl
, pp
);
5421 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5422 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5423 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5424 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5425 /* Compute the divisor for the pp clock, simply match the Bspec
5427 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5428 HAS_PCH_ICP(dev_priv
)) {
5429 pp_div
= I915_READ(regs
.pp_ctrl
);
5430 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5431 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5432 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5434 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5435 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5436 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5439 /* Haswell doesn't have any port selection bits for the panel
5440 * power sequencer any more. */
5441 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5442 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5443 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5445 port_sel
= PANEL_PORT_SELECT_DPA
;
5447 port_sel
= PANEL_PORT_SELECT_DPD
;
5452 I915_WRITE(regs
.pp_on
, pp_on
);
5453 I915_WRITE(regs
.pp_off
, pp_off
);
5454 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5455 HAS_PCH_ICP(dev_priv
))
5456 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5458 I915_WRITE(regs
.pp_div
, pp_div
);
5460 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5461 I915_READ(regs
.pp_on
),
5462 I915_READ(regs
.pp_off
),
5463 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5464 HAS_PCH_ICP(dev_priv
)) ?
5465 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5466 I915_READ(regs
.pp_div
));
5469 static void intel_dp_pps_init(struct intel_dp
*intel_dp
)
5471 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5473 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5474 vlv_initial_power_sequencer_setup(intel_dp
);
5476 intel_dp_init_panel_power_sequencer(intel_dp
);
5477 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
5482 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5483 * @dev_priv: i915 device
5484 * @crtc_state: a pointer to the active intel_crtc_state
5485 * @refresh_rate: RR to be programmed
5487 * This function gets called when refresh rate (RR) has to be changed from
5488 * one frequency to another. Switches can be between high and low RR
5489 * supported by the panel or to any other RR based on media playback (in
5490 * this case, RR value needs to be passed from user space).
5492 * The caller of this function needs to take a lock on dev_priv->drrs.
5494 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5495 const struct intel_crtc_state
*crtc_state
,
5498 struct intel_encoder
*encoder
;
5499 struct intel_digital_port
*dig_port
= NULL
;
5500 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5501 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5502 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5504 if (refresh_rate
<= 0) {
5505 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5509 if (intel_dp
== NULL
) {
5510 DRM_DEBUG_KMS("DRRS not supported.\n");
5514 dig_port
= dp_to_dig_port(intel_dp
);
5515 encoder
= &dig_port
->base
;
5518 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5522 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5523 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5527 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5529 index
= DRRS_LOW_RR
;
5531 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5533 "DRRS requested for previously set RR...ignoring\n");
5537 if (!crtc_state
->base
.active
) {
5538 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5542 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5545 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5548 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5552 DRM_ERROR("Unsupported refreshrate type\n");
5554 } else if (INTEL_GEN(dev_priv
) > 6) {
5555 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5558 val
= I915_READ(reg
);
5559 if (index
> DRRS_HIGH_RR
) {
5560 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5561 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5563 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5565 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5566 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5568 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5570 I915_WRITE(reg
, val
);
5573 dev_priv
->drrs
.refresh_rate_type
= index
;
5575 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5579 * intel_edp_drrs_enable - init drrs struct if supported
5580 * @intel_dp: DP struct
5581 * @crtc_state: A pointer to the active crtc state.
5583 * Initializes frontbuffer_bits and drrs.dp
5585 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5586 const struct intel_crtc_state
*crtc_state
)
5588 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5590 if (!crtc_state
->has_drrs
) {
5591 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5595 if (dev_priv
->psr
.enabled
) {
5596 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5600 mutex_lock(&dev_priv
->drrs
.mutex
);
5601 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5602 DRM_ERROR("DRRS already enabled\n");
5606 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5608 dev_priv
->drrs
.dp
= intel_dp
;
5611 mutex_unlock(&dev_priv
->drrs
.mutex
);
5615 * intel_edp_drrs_disable - Disable DRRS
5616 * @intel_dp: DP struct
5617 * @old_crtc_state: Pointer to old crtc_state.
5620 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5621 const struct intel_crtc_state
*old_crtc_state
)
5623 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5625 if (!old_crtc_state
->has_drrs
)
5628 mutex_lock(&dev_priv
->drrs
.mutex
);
5629 if (!dev_priv
->drrs
.dp
) {
5630 mutex_unlock(&dev_priv
->drrs
.mutex
);
5634 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5635 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5636 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5638 dev_priv
->drrs
.dp
= NULL
;
5639 mutex_unlock(&dev_priv
->drrs
.mutex
);
5641 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5644 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5646 struct drm_i915_private
*dev_priv
=
5647 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5648 struct intel_dp
*intel_dp
;
5650 mutex_lock(&dev_priv
->drrs
.mutex
);
5652 intel_dp
= dev_priv
->drrs
.dp
;
5658 * The delayed work can race with an invalidate hence we need to
5662 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5665 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5666 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5668 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5669 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5673 mutex_unlock(&dev_priv
->drrs
.mutex
);
5677 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5678 * @dev_priv: i915 device
5679 * @frontbuffer_bits: frontbuffer plane tracking bits
5681 * This function gets called everytime rendering on the given planes start.
5682 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5684 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5686 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5687 unsigned int frontbuffer_bits
)
5689 struct drm_crtc
*crtc
;
5692 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5695 cancel_delayed_work(&dev_priv
->drrs
.work
);
5697 mutex_lock(&dev_priv
->drrs
.mutex
);
5698 if (!dev_priv
->drrs
.dp
) {
5699 mutex_unlock(&dev_priv
->drrs
.mutex
);
5703 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5704 pipe
= to_intel_crtc(crtc
)->pipe
;
5706 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5707 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5709 /* invalidate means busy screen hence upclock */
5710 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5711 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5712 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5714 mutex_unlock(&dev_priv
->drrs
.mutex
);
5718 * intel_edp_drrs_flush - Restart Idleness DRRS
5719 * @dev_priv: i915 device
5720 * @frontbuffer_bits: frontbuffer plane tracking bits
5722 * This function gets called every time rendering on the given planes has
5723 * completed or flip on a crtc is completed. So DRRS should be upclocked
5724 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5725 * if no other planes are dirty.
5727 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5729 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5730 unsigned int frontbuffer_bits
)
5732 struct drm_crtc
*crtc
;
5735 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5738 cancel_delayed_work(&dev_priv
->drrs
.work
);
5740 mutex_lock(&dev_priv
->drrs
.mutex
);
5741 if (!dev_priv
->drrs
.dp
) {
5742 mutex_unlock(&dev_priv
->drrs
.mutex
);
5746 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5747 pipe
= to_intel_crtc(crtc
)->pipe
;
5749 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5750 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5752 /* flush means busy screen hence upclock */
5753 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5754 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5755 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5758 * flush also means no more activity hence schedule downclock, if all
5759 * other fbs are quiescent too
5761 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5762 schedule_delayed_work(&dev_priv
->drrs
.work
,
5763 msecs_to_jiffies(1000));
5764 mutex_unlock(&dev_priv
->drrs
.mutex
);
5768 * DOC: Display Refresh Rate Switching (DRRS)
5770 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5771 * which enables swtching between low and high refresh rates,
5772 * dynamically, based on the usage scenario. This feature is applicable
5773 * for internal panels.
5775 * Indication that the panel supports DRRS is given by the panel EDID, which
5776 * would list multiple refresh rates for one resolution.
5778 * DRRS is of 2 types - static and seamless.
5779 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5780 * (may appear as a blink on screen) and is used in dock-undock scenario.
5781 * Seamless DRRS involves changing RR without any visual effect to the user
5782 * and can be used during normal system usage. This is done by programming
5783 * certain registers.
5785 * Support for static/seamless DRRS may be indicated in the VBT based on
5786 * inputs from the panel spec.
5788 * DRRS saves power by switching to low RR based on usage scenarios.
5790 * The implementation is based on frontbuffer tracking implementation. When
5791 * there is a disturbance on the screen triggered by user activity or a periodic
5792 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5793 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5796 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5797 * and intel_edp_drrs_flush() are called.
5799 * DRRS can be further extended to support other internal panels and also
5800 * the scenario of video playback wherein RR is set based on the rate
5801 * requested by userspace.
5805 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5806 * @connector: eDP connector
5807 * @fixed_mode: preferred mode of panel
5809 * This function is called only once at driver load to initialize basic
5813 * Downclock mode if panel supports it, else return NULL.
5814 * DRRS support is determined by the presence of downclock mode (apart
5815 * from VBT setting).
5817 static struct drm_display_mode
*
5818 intel_dp_drrs_init(struct intel_connector
*connector
,
5819 struct drm_display_mode
*fixed_mode
)
5821 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
5822 struct drm_display_mode
*downclock_mode
= NULL
;
5824 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5825 mutex_init(&dev_priv
->drrs
.mutex
);
5827 if (INTEL_GEN(dev_priv
) <= 6) {
5828 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5832 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5833 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5837 downclock_mode
= intel_find_panel_downclock(dev_priv
, fixed_mode
,
5840 if (!downclock_mode
) {
5841 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5845 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5847 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5848 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5849 return downclock_mode
;
5852 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5853 struct intel_connector
*intel_connector
)
5855 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5856 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5857 struct drm_connector
*connector
= &intel_connector
->base
;
5858 struct drm_display_mode
*fixed_mode
= NULL
;
5859 struct drm_display_mode
*alt_fixed_mode
= NULL
;
5860 struct drm_display_mode
*downclock_mode
= NULL
;
5862 struct drm_display_mode
*scan
;
5864 enum pipe pipe
= INVALID_PIPE
;
5866 if (!intel_dp_is_edp(intel_dp
))
5870 * On IBX/CPT we may get here with LVDS already registered. Since the
5871 * driver uses the only internal power sequencer available for both
5872 * eDP and LVDS bail out early in this case to prevent interfering
5873 * with an already powered-on LVDS power sequencer.
5875 if (intel_get_lvds_encoder(&dev_priv
->drm
)) {
5876 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5877 DRM_INFO("LVDS was detected, not registering eDP\n");
5884 intel_dp_init_panel_power_timestamps(intel_dp
);
5885 intel_dp_pps_init(intel_dp
);
5886 intel_edp_panel_vdd_sanitize(intel_dp
);
5888 pps_unlock(intel_dp
);
5890 /* Cache DPCD and EDID for edp. */
5891 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5894 /* if this fails, presume the device is a ghost */
5895 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5899 mutex_lock(&dev
->mode_config
.mutex
);
5900 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5902 if (drm_add_edid_modes(connector
, edid
)) {
5903 drm_mode_connector_update_edid_property(connector
,
5907 edid
= ERR_PTR(-EINVAL
);
5910 edid
= ERR_PTR(-ENOENT
);
5912 intel_connector
->edid
= edid
;
5914 /* prefer fixed mode from EDID if available, save an alt mode also */
5915 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5916 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5917 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5918 downclock_mode
= intel_dp_drrs_init(
5919 intel_connector
, fixed_mode
);
5920 } else if (!alt_fixed_mode
) {
5921 alt_fixed_mode
= drm_mode_duplicate(dev
, scan
);
5925 /* fallback to VBT if available for eDP */
5926 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5927 fixed_mode
= drm_mode_duplicate(dev
,
5928 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5930 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5931 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5932 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5935 mutex_unlock(&dev
->mode_config
.mutex
);
5937 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5938 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5939 register_reboot_notifier(&intel_dp
->edp_notifier
);
5942 * Figure out the current pipe for the initial backlight setup.
5943 * If the current pipe isn't valid, try the PPS pipe, and if that
5944 * fails just assume pipe A.
5946 pipe
= vlv_active_pipe(intel_dp
);
5948 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5949 pipe
= intel_dp
->pps_pipe
;
5951 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5954 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5958 intel_panel_init(&intel_connector
->panel
, fixed_mode
, alt_fixed_mode
,
5960 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5961 intel_panel_setup_backlight(connector
, pipe
);
5966 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5968 * vdd might still be enabled do to the delayed vdd off.
5969 * Make sure vdd is actually turned off here.
5972 edp_panel_vdd_off_sync(intel_dp
);
5973 pps_unlock(intel_dp
);
5978 /* Set up the hotplug pin and aux power domain. */
5980 intel_dp_init_connector_port_info(struct intel_digital_port
*intel_dig_port
)
5982 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
5983 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5985 encoder
->hpd_pin
= intel_hpd_pin(encoder
->port
);
5987 switch (encoder
->port
) {
5989 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_A
;
5992 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_B
;
5995 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_C
;
5998 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
6001 /* FIXME: Check VBT for actual wiring of PORT E */
6002 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
6005 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_F
;
6008 MISSING_CASE(encoder
->port
);
6012 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
6014 struct intel_connector
*intel_connector
;
6015 struct drm_connector
*connector
;
6017 intel_connector
= container_of(work
, typeof(*intel_connector
),
6018 modeset_retry_work
);
6019 connector
= &intel_connector
->base
;
6020 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
6023 /* Grab the locks before changing connector property*/
6024 mutex_lock(&connector
->dev
->mode_config
.mutex
);
6025 /* Set connector link status to BAD and send a Uevent to notify
6026 * userspace to do a modeset.
6028 drm_mode_connector_set_link_status_property(connector
,
6029 DRM_MODE_LINK_STATUS_BAD
);
6030 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
6031 /* Send Hotplug uevent so userspace can reprobe */
6032 drm_kms_helper_hotplug_event(connector
->dev
);
6036 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
6037 struct intel_connector
*intel_connector
)
6039 struct drm_connector
*connector
= &intel_connector
->base
;
6040 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
6041 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
6042 struct drm_device
*dev
= intel_encoder
->base
.dev
;
6043 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6044 enum port port
= intel_encoder
->port
;
6047 /* Initialize the work for modeset in case of link train failure */
6048 INIT_WORK(&intel_connector
->modeset_retry_work
,
6049 intel_dp_modeset_retry_work_fn
);
6051 if (WARN(intel_dig_port
->max_lanes
< 1,
6052 "Not enough lanes (%d) for DP on port %c\n",
6053 intel_dig_port
->max_lanes
, port_name(port
)))
6056 intel_dp_set_source_rates(intel_dp
);
6058 intel_dp
->reset_link_params
= true;
6059 intel_dp
->pps_pipe
= INVALID_PIPE
;
6060 intel_dp
->active_pipe
= INVALID_PIPE
;
6062 /* intel_dp vfuncs */
6063 if (INTEL_GEN(dev_priv
) >= 9)
6064 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
6065 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6066 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
6067 else if (HAS_PCH_SPLIT(dev_priv
))
6068 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
6070 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
6072 if (INTEL_GEN(dev_priv
) >= 9)
6073 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
6075 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
6077 if (HAS_DDI(dev_priv
))
6078 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6080 /* Preserve the current hw state. */
6081 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6082 intel_dp
->attached_connector
= intel_connector
;
6084 if (intel_dp_is_port_edp(dev_priv
, port
))
6085 type
= DRM_MODE_CONNECTOR_eDP
;
6087 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6089 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6090 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6093 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6094 * for DP the encoder type can be set by the caller to
6095 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6097 if (type
== DRM_MODE_CONNECTOR_eDP
)
6098 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6100 /* eDP only on port B and/or C on vlv/chv */
6101 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6102 intel_dp_is_edp(intel_dp
) &&
6103 port
!= PORT_B
&& port
!= PORT_C
))
6106 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6107 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6110 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6111 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6113 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
6114 connector
->interlace_allowed
= true;
6115 connector
->doublescan_allowed
= 0;
6117 intel_dp_init_connector_port_info(intel_dig_port
);
6119 intel_dp_aux_init(intel_dp
);
6121 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6122 edp_panel_vdd_work
);
6124 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6126 if (HAS_DDI(dev_priv
))
6127 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6129 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6131 /* init MST on ports that can support it */
6132 if (HAS_DP_MST(dev_priv
) && !intel_dp_is_edp(intel_dp
) &&
6133 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
6134 intel_dp_mst_encoder_init(intel_dig_port
,
6135 intel_connector
->base
.base
.id
);
6137 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6138 intel_dp_aux_fini(intel_dp
);
6139 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6143 intel_dp_add_properties(intel_dp
, connector
);
6145 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6146 * 0xd. Failure to do so will result in spurious interrupts being
6147 * generated on the port when a cable is not attached.
6149 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
6150 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6151 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6157 drm_connector_cleanup(connector
);
6162 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6163 i915_reg_t output_reg
,
6166 struct intel_digital_port
*intel_dig_port
;
6167 struct intel_encoder
*intel_encoder
;
6168 struct drm_encoder
*encoder
;
6169 struct intel_connector
*intel_connector
;
6171 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6172 if (!intel_dig_port
)
6175 intel_connector
= intel_connector_alloc();
6176 if (!intel_connector
)
6177 goto err_connector_alloc
;
6179 intel_encoder
= &intel_dig_port
->base
;
6180 encoder
= &intel_encoder
->base
;
6182 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6183 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6184 "DP %c", port_name(port
)))
6185 goto err_encoder_init
;
6187 intel_encoder
->compute_config
= intel_dp_compute_config
;
6188 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6189 intel_encoder
->get_config
= intel_dp_get_config
;
6190 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6191 if (IS_CHERRYVIEW(dev_priv
)) {
6192 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6193 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6194 intel_encoder
->enable
= vlv_enable_dp
;
6195 intel_encoder
->disable
= vlv_disable_dp
;
6196 intel_encoder
->post_disable
= chv_post_disable_dp
;
6197 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6198 } else if (IS_VALLEYVIEW(dev_priv
)) {
6199 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6200 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6201 intel_encoder
->enable
= vlv_enable_dp
;
6202 intel_encoder
->disable
= vlv_disable_dp
;
6203 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6204 } else if (INTEL_GEN(dev_priv
) >= 5) {
6205 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6206 intel_encoder
->enable
= g4x_enable_dp
;
6207 intel_encoder
->disable
= ilk_disable_dp
;
6208 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6210 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6211 intel_encoder
->enable
= g4x_enable_dp
;
6212 intel_encoder
->disable
= g4x_disable_dp
;
6215 intel_dig_port
->dp
.output_reg
= output_reg
;
6216 intel_dig_port
->max_lanes
= 4;
6218 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6219 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6220 if (IS_CHERRYVIEW(dev_priv
)) {
6222 intel_encoder
->crtc_mask
= 1 << 2;
6224 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6226 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6228 intel_encoder
->cloneable
= 0;
6229 intel_encoder
->port
= port
;
6231 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6232 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6235 intel_infoframe_init(intel_dig_port
);
6237 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6238 goto err_init_connector
;
6243 drm_encoder_cleanup(encoder
);
6245 kfree(intel_connector
);
6246 err_connector_alloc
:
6247 kfree(intel_dig_port
);
6251 void intel_dp_mst_suspend(struct drm_device
*dev
)
6253 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6257 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6258 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6260 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6263 if (intel_dig_port
->dp
.is_mst
)
6264 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6268 void intel_dp_mst_resume(struct drm_device
*dev
)
6270 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6273 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6274 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6277 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6280 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6282 intel_dp_check_mst_status(&intel_dig_port
->dp
);