2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include "intel_drv.h"
43 #include <drm/i915_drm.h>
46 #define DP_DPRX_ESI_LEN 14
48 /* Compliance test status bits */
49 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
50 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
51 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
52 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
59 static const struct dp_link_dpll g4x_dpll
[] = {
61 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
63 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
66 static const struct dp_link_dpll pch_dpll
[] = {
68 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
70 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
73 static const struct dp_link_dpll vlv_dpll
[] = {
75 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
77 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
81 * CHV supports eDP 1.4 that have more link rates.
82 * Below only provides the fixed rate but exclude variable rate.
84 static const struct dp_link_dpll chv_dpll
[] = {
86 * CHV requires to program fractional division for m2.
87 * m2 is stored in fixed point format using formula below
88 * (m2_int << 22) | m2_fraction
90 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
91 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
92 { 270000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
97 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
98 * @intel_dp: DP struct
100 * If a CPU or PCH DP output is attached to an eDP panel, this function
101 * will return true, and false otherwise.
103 bool intel_dp_is_edp(struct intel_dp
*intel_dp
)
105 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
107 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
110 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
112 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
114 return intel_dig_port
->base
.base
.dev
;
117 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
119 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
122 static void intel_dp_link_down(struct intel_encoder
*encoder
,
123 const struct intel_crtc_state
*old_crtc_state
);
124 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
125 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
126 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
127 const struct intel_crtc_state
*crtc_state
);
128 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
130 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
132 /* update sink rates from dpcd */
133 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
135 static const int dp_rates
[] = {
136 162000, 270000, 540000, 810000
140 max_rate
= drm_dp_bw_code_to_link_rate(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
142 for (i
= 0; i
< ARRAY_SIZE(dp_rates
); i
++) {
143 if (dp_rates
[i
] > max_rate
)
145 intel_dp
->sink_rates
[i
] = dp_rates
[i
];
148 intel_dp
->num_sink_rates
= i
;
151 /* Get length of rates array potentially limited by max_rate. */
152 static int intel_dp_rate_limit_len(const int *rates
, int len
, int max_rate
)
156 /* Limit results by potentially reduced max rate */
157 for (i
= 0; i
< len
; i
++) {
158 if (rates
[len
- i
- 1] <= max_rate
)
165 /* Get length of common rates array potentially limited by max_rate. */
166 static int intel_dp_common_len_rate_limit(const struct intel_dp
*intel_dp
,
169 return intel_dp_rate_limit_len(intel_dp
->common_rates
,
170 intel_dp
->num_common_rates
, max_rate
);
173 /* Theoretical max between source and sink */
174 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
176 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
179 /* Theoretical max between source and sink */
180 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
182 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
183 int source_max
= intel_dig_port
->max_lanes
;
184 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
186 return min(source_max
, sink_max
);
189 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
191 return intel_dp
->max_link_lane_count
;
195 intel_dp_link_required(int pixel_clock
, int bpp
)
197 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
198 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
202 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
204 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
205 * link rate that is generally expressed in Gbps. Since, 8 bits of data
206 * is transmitted every LS_Clk per lane, there is no need to account for
207 * the channel encoding that is done in the PHY layer here.
210 return max_link_clock
* max_lanes
;
214 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
216 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
217 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
218 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
219 int max_dotclk
= dev_priv
->max_dotclk_freq
;
222 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
224 if (type
!= DP_DS_PORT_TYPE_VGA
)
227 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
228 intel_dp
->downstream_ports
);
230 if (ds_max_dotclk
!= 0)
231 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
236 static int cnl_max_source_rate(struct intel_dp
*intel_dp
)
238 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
239 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
240 enum port port
= dig_port
->base
.port
;
242 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
244 /* Low voltage SKUs are limited to max of 5.4G */
245 if (voltage
== VOLTAGE_INFO_0_85V
)
248 /* For this SKU 8.1G is supported in all ports */
249 if (IS_CNL_WITH_PORT_F(dev_priv
))
252 /* For other SKUs, max rate on ports A and D is 5.4G */
253 if (port
== PORT_A
|| port
== PORT_D
)
259 static int icl_max_source_rate(struct intel_dp
*intel_dp
)
261 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
262 enum port port
= dig_port
->base
.port
;
271 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
273 /* The values must be in increasing order */
274 static const int cnl_rates
[] = {
275 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
277 static const int bxt_rates
[] = {
278 162000, 216000, 243000, 270000, 324000, 432000, 540000
280 static const int skl_rates
[] = {
281 162000, 216000, 270000, 324000, 432000, 540000
283 static const int hsw_rates
[] = {
284 162000, 270000, 540000
286 static const int g4x_rates
[] = {
289 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
290 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
291 const struct ddi_vbt_port_info
*info
=
292 &dev_priv
->vbt
.ddi_port_info
[dig_port
->base
.port
];
293 const int *source_rates
;
294 int size
, max_rate
= 0, vbt_max_rate
= info
->dp_max_link_rate
;
296 /* This should only be done once */
297 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
299 if (INTEL_GEN(dev_priv
) >= 10) {
300 source_rates
= cnl_rates
;
301 size
= ARRAY_SIZE(cnl_rates
);
302 if (INTEL_GEN(dev_priv
) == 10)
303 max_rate
= cnl_max_source_rate(intel_dp
);
305 max_rate
= icl_max_source_rate(intel_dp
);
306 } else if (IS_GEN9_LP(dev_priv
)) {
307 source_rates
= bxt_rates
;
308 size
= ARRAY_SIZE(bxt_rates
);
309 } else if (IS_GEN9_BC(dev_priv
)) {
310 source_rates
= skl_rates
;
311 size
= ARRAY_SIZE(skl_rates
);
312 } else if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
313 IS_BROADWELL(dev_priv
)) {
314 source_rates
= hsw_rates
;
315 size
= ARRAY_SIZE(hsw_rates
);
317 source_rates
= g4x_rates
;
318 size
= ARRAY_SIZE(g4x_rates
);
321 if (max_rate
&& vbt_max_rate
)
322 max_rate
= min(max_rate
, vbt_max_rate
);
323 else if (vbt_max_rate
)
324 max_rate
= vbt_max_rate
;
327 size
= intel_dp_rate_limit_len(source_rates
, size
, max_rate
);
329 intel_dp
->source_rates
= source_rates
;
330 intel_dp
->num_source_rates
= size
;
333 static int intersect_rates(const int *source_rates
, int source_len
,
334 const int *sink_rates
, int sink_len
,
337 int i
= 0, j
= 0, k
= 0;
339 while (i
< source_len
&& j
< sink_len
) {
340 if (source_rates
[i
] == sink_rates
[j
]) {
341 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
343 common_rates
[k
] = source_rates
[i
];
347 } else if (source_rates
[i
] < sink_rates
[j
]) {
356 /* return index of rate in rates array, or -1 if not found */
357 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
361 for (i
= 0; i
< len
; i
++)
362 if (rate
== rates
[i
])
368 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
370 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
372 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
373 intel_dp
->num_source_rates
,
374 intel_dp
->sink_rates
,
375 intel_dp
->num_sink_rates
,
376 intel_dp
->common_rates
);
378 /* Paranoia, there should always be something in common. */
379 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
380 intel_dp
->common_rates
[0] = 162000;
381 intel_dp
->num_common_rates
= 1;
385 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
, int link_rate
,
389 * FIXME: we need to synchronize the current link parameters with
390 * hardware readout. Currently fast link training doesn't work on
393 if (link_rate
== 0 ||
394 link_rate
> intel_dp
->max_link_rate
)
397 if (lane_count
== 0 ||
398 lane_count
> intel_dp_max_lane_count(intel_dp
))
404 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
405 int link_rate
, uint8_t lane_count
)
409 index
= intel_dp_rate_index(intel_dp
->common_rates
,
410 intel_dp
->num_common_rates
,
413 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
414 intel_dp
->max_link_lane_count
= lane_count
;
415 } else if (lane_count
> 1) {
416 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
417 intel_dp
->max_link_lane_count
= lane_count
>> 1;
419 DRM_ERROR("Link Training Unsuccessful\n");
426 static enum drm_mode_status
427 intel_dp_mode_valid(struct drm_connector
*connector
,
428 struct drm_display_mode
*mode
)
430 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
431 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
432 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
433 int target_clock
= mode
->clock
;
434 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
437 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
438 return MODE_NO_DBLESCAN
;
440 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
442 if (intel_dp_is_edp(intel_dp
) && fixed_mode
) {
443 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
446 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
449 target_clock
= fixed_mode
->clock
;
452 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
453 max_lanes
= intel_dp_max_lane_count(intel_dp
);
455 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
456 mode_rate
= intel_dp_link_required(target_clock
, 18);
458 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
459 return MODE_CLOCK_HIGH
;
461 if (mode
->clock
< 10000)
462 return MODE_CLOCK_LOW
;
464 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
465 return MODE_H_ILLEGAL
;
470 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
477 for (i
= 0; i
< src_bytes
; i
++)
478 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
482 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
487 for (i
= 0; i
< dst_bytes
; i
++)
488 dst
[i
] = src
>> ((3-i
) * 8);
492 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
494 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
495 bool force_disable_vdd
);
497 intel_dp_pps_init(struct intel_dp
*intel_dp
);
499 static void pps_lock(struct intel_dp
*intel_dp
)
501 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
504 * See intel_power_sequencer_reset() why we need
505 * a power domain reference here.
507 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
509 mutex_lock(&dev_priv
->pps_mutex
);
512 static void pps_unlock(struct intel_dp
*intel_dp
)
514 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
516 mutex_unlock(&dev_priv
->pps_mutex
);
518 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
522 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
524 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
525 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
526 enum pipe pipe
= intel_dp
->pps_pipe
;
527 bool pll_enabled
, release_cl_override
= false;
528 enum dpio_phy phy
= DPIO_PHY(pipe
);
529 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
532 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
533 "skipping pipe %c power sequencer kick due to port %c being active\n",
534 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
)))
537 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
538 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
540 /* Preserve the BIOS-computed detected bit. This is
541 * supposed to be read-only.
543 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
544 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
545 DP
|= DP_PORT_WIDTH(1);
546 DP
|= DP_LINK_TRAIN_PAT_1
;
548 if (IS_CHERRYVIEW(dev_priv
))
549 DP
|= DP_PIPE_SEL_CHV(pipe
);
551 DP
|= DP_PIPE_SEL(pipe
);
553 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
556 * The DPLL for the pipe must be enabled for this to work.
557 * So enable temporarily it if it's not already enabled.
560 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
561 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
563 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
564 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
565 DRM_ERROR("Failed to force on pll for pipe %c!\n",
572 * Similar magic as in intel_dp_enable_port().
573 * We _must_ do this port enable + disable trick
574 * to make this power sequencer lock onto the port.
575 * Otherwise even VDD force bit won't work.
577 I915_WRITE(intel_dp
->output_reg
, DP
);
578 POSTING_READ(intel_dp
->output_reg
);
580 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
581 POSTING_READ(intel_dp
->output_reg
);
583 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
584 POSTING_READ(intel_dp
->output_reg
);
587 vlv_force_pll_off(dev_priv
, pipe
);
589 if (release_cl_override
)
590 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
594 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
596 struct intel_encoder
*encoder
;
597 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
600 * We don't have power sequencer currently.
601 * Pick one that's not used by other ports.
603 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
604 struct intel_dp
*intel_dp
;
606 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
607 encoder
->type
!= INTEL_OUTPUT_EDP
)
610 intel_dp
= enc_to_intel_dp(&encoder
->base
);
612 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
613 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
614 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
616 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
617 pipes
&= ~(1 << intel_dp
->pps_pipe
);
619 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
621 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
622 pipes
&= ~(1 << intel_dp
->active_pipe
);
629 return ffs(pipes
) - 1;
633 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
635 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
636 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
639 lockdep_assert_held(&dev_priv
->pps_mutex
);
641 /* We should never land here with regular DP ports */
642 WARN_ON(!intel_dp_is_edp(intel_dp
));
644 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
645 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
647 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
648 return intel_dp
->pps_pipe
;
650 pipe
= vlv_find_free_pps(dev_priv
);
653 * Didn't find one. This should not happen since there
654 * are two power sequencers and up to two eDP ports.
656 if (WARN_ON(pipe
== INVALID_PIPE
))
659 vlv_steal_power_sequencer(dev_priv
, pipe
);
660 intel_dp
->pps_pipe
= pipe
;
662 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
663 pipe_name(intel_dp
->pps_pipe
),
664 port_name(intel_dig_port
->base
.port
));
666 /* init power sequencer on this pipe and port */
667 intel_dp_init_panel_power_sequencer(intel_dp
);
668 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
671 * Even vdd force doesn't work until we've made
672 * the power sequencer lock in on the port.
674 vlv_power_sequencer_kick(intel_dp
);
676 return intel_dp
->pps_pipe
;
680 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
682 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
683 int backlight_controller
= dev_priv
->vbt
.backlight
.controller
;
685 lockdep_assert_held(&dev_priv
->pps_mutex
);
687 /* We should never land here with regular DP ports */
688 WARN_ON(!intel_dp_is_edp(intel_dp
));
690 if (!intel_dp
->pps_reset
)
691 return backlight_controller
;
693 intel_dp
->pps_reset
= false;
696 * Only the HW needs to be reprogrammed, the SW state is fixed and
697 * has been setup during connector init.
699 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
701 return backlight_controller
;
704 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
707 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
710 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
713 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
716 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
719 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
726 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
728 vlv_pipe_check pipe_check
)
732 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
733 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
734 PANEL_PORT_SELECT_MASK
;
736 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
739 if (!pipe_check(dev_priv
, pipe
))
749 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
751 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
752 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
753 enum port port
= intel_dig_port
->base
.port
;
755 lockdep_assert_held(&dev_priv
->pps_mutex
);
757 /* try to find a pipe with this port selected */
758 /* first pick one where the panel is on */
759 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
761 /* didn't find one? pick one where vdd is on */
762 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
763 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
764 vlv_pipe_has_vdd_on
);
765 /* didn't find one? pick one with just the correct port */
766 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
767 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
770 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
771 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
772 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
777 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
778 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
780 intel_dp_init_panel_power_sequencer(intel_dp
);
781 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
784 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
786 struct intel_encoder
*encoder
;
788 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
789 !IS_GEN9_LP(dev_priv
)))
793 * We can't grab pps_mutex here due to deadlock with power_domain
794 * mutex when power_domain functions are called while holding pps_mutex.
795 * That also means that in order to use pps_pipe the code needs to
796 * hold both a power domain reference and pps_mutex, and the power domain
797 * reference get/put must be done while _not_ holding pps_mutex.
798 * pps_{lock,unlock}() do these steps in the correct order, so one
799 * should use them always.
802 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
803 struct intel_dp
*intel_dp
;
805 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
806 encoder
->type
!= INTEL_OUTPUT_EDP
&&
807 encoder
->type
!= INTEL_OUTPUT_DDI
)
810 intel_dp
= enc_to_intel_dp(&encoder
->base
);
812 /* Skip pure DVI/HDMI DDI encoders */
813 if (!i915_mmio_reg_valid(intel_dp
->output_reg
))
816 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
818 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
821 if (IS_GEN9_LP(dev_priv
))
822 intel_dp
->pps_reset
= true;
824 intel_dp
->pps_pipe
= INVALID_PIPE
;
828 struct pps_registers
{
836 static void intel_pps_get_registers(struct intel_dp
*intel_dp
,
837 struct pps_registers
*regs
)
839 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
842 memset(regs
, 0, sizeof(*regs
));
844 if (IS_GEN9_LP(dev_priv
))
845 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
846 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
847 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
849 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
850 regs
->pp_stat
= PP_STATUS(pps_idx
);
851 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
852 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
853 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
854 !HAS_PCH_ICP(dev_priv
))
855 regs
->pp_div
= PP_DIVISOR(pps_idx
);
859 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
861 struct pps_registers regs
;
863 intel_pps_get_registers(intel_dp
, ®s
);
869 _pp_stat_reg(struct intel_dp
*intel_dp
)
871 struct pps_registers regs
;
873 intel_pps_get_registers(intel_dp
, ®s
);
878 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
879 This function only applicable when panel PM state is not to be tracked */
880 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
883 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
885 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
887 if (!intel_dp_is_edp(intel_dp
) || code
!= SYS_RESTART
)
892 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
893 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
894 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
897 pp_ctrl_reg
= PP_CONTROL(pipe
);
898 pp_div_reg
= PP_DIVISOR(pipe
);
899 pp_div
= I915_READ(pp_div_reg
);
900 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
902 /* 0x1F write to PP_DIV_REG sets max cycle delay */
903 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
904 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
905 msleep(intel_dp
->panel_power_cycle_delay
);
908 pps_unlock(intel_dp
);
913 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
915 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
917 lockdep_assert_held(&dev_priv
->pps_mutex
);
919 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
920 intel_dp
->pps_pipe
== INVALID_PIPE
)
923 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
926 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
928 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
930 lockdep_assert_held(&dev_priv
->pps_mutex
);
932 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
933 intel_dp
->pps_pipe
== INVALID_PIPE
)
936 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
940 intel_dp_check_edp(struct intel_dp
*intel_dp
)
942 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
944 if (!intel_dp_is_edp(intel_dp
))
947 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
948 WARN(1, "eDP powered off while attempting aux channel communication.\n");
949 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
950 I915_READ(_pp_stat_reg(intel_dp
)),
951 I915_READ(_pp_ctrl_reg(intel_dp
)));
956 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
958 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
959 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
963 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
965 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
966 msecs_to_jiffies_timeout(10));
968 done
= wait_for(C
, 10) == 0;
970 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
977 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
979 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
985 * The clock divider is based off the hrawclk, and would like to run at
986 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
988 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
991 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
993 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
999 * The clock divider is based off the cdclk or PCH rawclk, and would
1000 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1001 * divide by 2000 and use that
1003 if (intel_dp
->aux_ch
== AUX_CH_A
)
1004 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
1006 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
1009 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1011 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1013 if (intel_dp
->aux_ch
!= AUX_CH_A
&& HAS_PCH_LPT_H(dev_priv
)) {
1014 /* Workaround for non-ULT HSW */
1022 return ilk_get_aux_clock_divider(intel_dp
, index
);
1025 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1028 * SKL doesn't need us to program the AUX clock divider (Hardware will
1029 * derive the clock from CDCLK automatically). We still implement the
1030 * get_aux_clock_divider vfunc to plug-in into the existing code.
1032 return index
? 0 : 1;
1035 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1038 uint32_t aux_clock_divider
)
1040 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1041 struct drm_i915_private
*dev_priv
=
1042 to_i915(intel_dig_port
->base
.base
.dev
);
1043 uint32_t precharge
, timeout
;
1045 if (IS_GEN6(dev_priv
))
1050 if (IS_BROADWELL(dev_priv
))
1051 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1053 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1055 return DP_AUX_CH_CTL_SEND_BUSY
|
1056 DP_AUX_CH_CTL_DONE
|
1057 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1058 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1060 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1061 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1062 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1063 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1066 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1071 return DP_AUX_CH_CTL_SEND_BUSY
|
1072 DP_AUX_CH_CTL_DONE
|
1073 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1074 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1075 DP_AUX_CH_CTL_TIME_OUT_MAX
|
1076 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1077 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1078 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1079 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1083 intel_dp_aux_xfer(struct intel_dp
*intel_dp
,
1084 const uint8_t *send
, int send_bytes
,
1085 uint8_t *recv
, int recv_size
,
1086 u32 aux_send_ctl_flags
)
1088 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1089 struct drm_i915_private
*dev_priv
=
1090 to_i915(intel_dig_port
->base
.base
.dev
);
1091 i915_reg_t ch_ctl
, ch_data
[5];
1092 uint32_t aux_clock_divider
;
1093 int i
, ret
, recv_bytes
;
1096 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1099 ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
1100 for (i
= 0; i
< ARRAY_SIZE(ch_data
); i
++)
1101 ch_data
[i
] = intel_dp
->aux_ch_data_reg(intel_dp
, i
);
1106 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1107 * In such cases we want to leave VDD enabled and it's up to upper layers
1108 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1111 vdd
= edp_panel_vdd_on(intel_dp
);
1113 /* dp aux is extremely sensitive to irq latency, hence request the
1114 * lowest possible wakeup latency and so prevent the cpu from going into
1115 * deep sleep states.
1117 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1119 intel_dp_check_edp(intel_dp
);
1121 /* Try to wait for any previous AUX channel activity */
1122 for (try = 0; try < 3; try++) {
1123 status
= I915_READ_NOTRACE(ch_ctl
);
1124 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1130 static u32 last_status
= -1;
1131 const u32 status
= I915_READ(ch_ctl
);
1133 if (status
!= last_status
) {
1134 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1136 last_status
= status
;
1143 /* Only 5 data registers! */
1144 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1149 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1150 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1155 send_ctl
|= aux_send_ctl_flags
;
1157 /* Must try at least 3 times according to DP spec */
1158 for (try = 0; try < 5; try++) {
1159 /* Load the send data into the aux channel data registers */
1160 for (i
= 0; i
< send_bytes
; i
+= 4)
1161 I915_WRITE(ch_data
[i
>> 2],
1162 intel_dp_pack_aux(send
+ i
,
1165 /* Send the command and wait for it to complete */
1166 I915_WRITE(ch_ctl
, send_ctl
);
1168 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1170 /* Clear done status and any errors */
1173 DP_AUX_CH_CTL_DONE
|
1174 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1175 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1177 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1178 * 400us delay required for errors and timeouts
1179 * Timeout errors from the HW already meet this
1180 * requirement so skip to next iteration
1182 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1185 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1186 usleep_range(400, 500);
1189 if (status
& DP_AUX_CH_CTL_DONE
)
1194 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1195 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1201 /* Check for timeout or receive error.
1202 * Timeouts occur when the sink is not connected
1204 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1205 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1210 /* Timeouts occur when the device isn't connected, so they're
1211 * "normal" -- don't fill the kernel log with these */
1212 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1213 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1218 /* Unload any bytes sent back from the other side */
1219 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1220 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1223 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1224 * We have no idea of what happened so we return -EBUSY so
1225 * drm layer takes care for the necessary retries.
1227 if (recv_bytes
== 0 || recv_bytes
> 20) {
1228 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1234 if (recv_bytes
> recv_size
)
1235 recv_bytes
= recv_size
;
1237 for (i
= 0; i
< recv_bytes
; i
+= 4)
1238 intel_dp_unpack_aux(I915_READ(ch_data
[i
>> 2]),
1239 recv
+ i
, recv_bytes
- i
);
1243 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1246 edp_panel_vdd_off(intel_dp
, false);
1248 pps_unlock(intel_dp
);
1253 #define BARE_ADDRESS_SIZE 3
1254 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1257 intel_dp_aux_header(u8 txbuf
[HEADER_SIZE
],
1258 const struct drm_dp_aux_msg
*msg
)
1260 txbuf
[0] = (msg
->request
<< 4) | ((msg
->address
>> 16) & 0xf);
1261 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1262 txbuf
[2] = msg
->address
& 0xff;
1263 txbuf
[3] = msg
->size
- 1;
1267 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1269 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1270 uint8_t txbuf
[20], rxbuf
[20];
1271 size_t txsize
, rxsize
;
1274 intel_dp_aux_header(txbuf
, msg
);
1276 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1277 case DP_AUX_NATIVE_WRITE
:
1278 case DP_AUX_I2C_WRITE
:
1279 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1280 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1281 rxsize
= 2; /* 0 or 1 data bytes */
1283 if (WARN_ON(txsize
> 20))
1286 WARN_ON(!msg
->buffer
!= !msg
->size
);
1289 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1291 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1294 msg
->reply
= rxbuf
[0] >> 4;
1297 /* Number of bytes written in a short write. */
1298 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1300 /* Return payload size. */
1306 case DP_AUX_NATIVE_READ
:
1307 case DP_AUX_I2C_READ
:
1308 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1309 rxsize
= msg
->size
+ 1;
1311 if (WARN_ON(rxsize
> 20))
1314 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1317 msg
->reply
= rxbuf
[0] >> 4;
1319 * Assume happy day, and copy the data. The caller is
1320 * expected to check msg->reply before touching it.
1322 * Return payload size.
1325 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1337 static enum aux_ch
intel_aux_ch(struct intel_dp
*intel_dp
)
1339 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
1340 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1341 enum port port
= encoder
->port
;
1342 const struct ddi_vbt_port_info
*info
=
1343 &dev_priv
->vbt
.ddi_port_info
[port
];
1346 if (!info
->alternate_aux_channel
) {
1347 aux_ch
= (enum aux_ch
) port
;
1349 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1350 aux_ch_name(aux_ch
), port_name(port
));
1354 switch (info
->alternate_aux_channel
) {
1374 MISSING_CASE(info
->alternate_aux_channel
);
1379 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1380 aux_ch_name(aux_ch
), port_name(port
));
1385 static enum intel_display_power_domain
1386 intel_aux_power_domain(struct intel_dp
*intel_dp
)
1388 switch (intel_dp
->aux_ch
) {
1390 return POWER_DOMAIN_AUX_A
;
1392 return POWER_DOMAIN_AUX_B
;
1394 return POWER_DOMAIN_AUX_C
;
1396 return POWER_DOMAIN_AUX_D
;
1398 return POWER_DOMAIN_AUX_E
;
1400 return POWER_DOMAIN_AUX_F
;
1402 MISSING_CASE(intel_dp
->aux_ch
);
1403 return POWER_DOMAIN_AUX_A
;
1407 static i915_reg_t
g4x_aux_ctl_reg(struct intel_dp
*intel_dp
)
1409 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1410 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1416 return DP_AUX_CH_CTL(aux_ch
);
1418 MISSING_CASE(aux_ch
);
1419 return DP_AUX_CH_CTL(AUX_CH_B
);
1423 static i915_reg_t
g4x_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1425 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1426 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1432 return DP_AUX_CH_DATA(aux_ch
, index
);
1434 MISSING_CASE(aux_ch
);
1435 return DP_AUX_CH_DATA(AUX_CH_B
, index
);
1439 static i915_reg_t
ilk_aux_ctl_reg(struct intel_dp
*intel_dp
)
1441 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1442 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1446 return DP_AUX_CH_CTL(aux_ch
);
1450 return PCH_DP_AUX_CH_CTL(aux_ch
);
1452 MISSING_CASE(aux_ch
);
1453 return DP_AUX_CH_CTL(AUX_CH_A
);
1457 static i915_reg_t
ilk_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1459 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1460 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1464 return DP_AUX_CH_DATA(aux_ch
, index
);
1468 return PCH_DP_AUX_CH_DATA(aux_ch
, index
);
1470 MISSING_CASE(aux_ch
);
1471 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1475 static i915_reg_t
skl_aux_ctl_reg(struct intel_dp
*intel_dp
)
1477 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1478 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1487 return DP_AUX_CH_CTL(aux_ch
);
1489 MISSING_CASE(aux_ch
);
1490 return DP_AUX_CH_CTL(AUX_CH_A
);
1494 static i915_reg_t
skl_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1496 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1497 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1506 return DP_AUX_CH_DATA(aux_ch
, index
);
1508 MISSING_CASE(aux_ch
);
1509 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1514 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1516 kfree(intel_dp
->aux
.name
);
1520 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1522 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1523 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
1525 intel_dp
->aux_ch
= intel_aux_ch(intel_dp
);
1526 intel_dp
->aux_power_domain
= intel_aux_power_domain(intel_dp
);
1528 if (INTEL_GEN(dev_priv
) >= 9) {
1529 intel_dp
->aux_ch_ctl_reg
= skl_aux_ctl_reg
;
1530 intel_dp
->aux_ch_data_reg
= skl_aux_data_reg
;
1531 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1532 intel_dp
->aux_ch_ctl_reg
= ilk_aux_ctl_reg
;
1533 intel_dp
->aux_ch_data_reg
= ilk_aux_data_reg
;
1535 intel_dp
->aux_ch_ctl_reg
= g4x_aux_ctl_reg
;
1536 intel_dp
->aux_ch_data_reg
= g4x_aux_data_reg
;
1539 if (INTEL_GEN(dev_priv
) >= 9)
1540 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
1541 else if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
1542 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
1543 else if (HAS_PCH_SPLIT(dev_priv
))
1544 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
1546 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
1548 if (INTEL_GEN(dev_priv
) >= 9)
1549 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
1551 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
1553 drm_dp_aux_init(&intel_dp
->aux
);
1555 /* Failure to allocate our preferred name is not critical */
1556 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c",
1557 port_name(encoder
->port
));
1558 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1561 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1563 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1565 return max_rate
>= 540000;
1568 bool intel_dp_source_supports_hbr3(struct intel_dp
*intel_dp
)
1570 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1572 return max_rate
>= 810000;
1576 intel_dp_set_clock(struct intel_encoder
*encoder
,
1577 struct intel_crtc_state
*pipe_config
)
1579 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1580 const struct dp_link_dpll
*divisor
= NULL
;
1583 if (IS_G4X(dev_priv
)) {
1585 count
= ARRAY_SIZE(g4x_dpll
);
1586 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1588 count
= ARRAY_SIZE(pch_dpll
);
1589 } else if (IS_CHERRYVIEW(dev_priv
)) {
1591 count
= ARRAY_SIZE(chv_dpll
);
1592 } else if (IS_VALLEYVIEW(dev_priv
)) {
1594 count
= ARRAY_SIZE(vlv_dpll
);
1597 if (divisor
&& count
) {
1598 for (i
= 0; i
< count
; i
++) {
1599 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1600 pipe_config
->dpll
= divisor
[i
].dpll
;
1601 pipe_config
->clock_set
= true;
1608 static void snprintf_int_array(char *str
, size_t len
,
1609 const int *array
, int nelem
)
1615 for (i
= 0; i
< nelem
; i
++) {
1616 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1624 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1626 char str
[128]; /* FIXME: too big for stack? */
1628 if ((drm_debug
& DRM_UT_KMS
) == 0)
1631 snprintf_int_array(str
, sizeof(str
),
1632 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1633 DRM_DEBUG_KMS("source rates: %s\n", str
);
1635 snprintf_int_array(str
, sizeof(str
),
1636 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1637 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1639 snprintf_int_array(str
, sizeof(str
),
1640 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1641 DRM_DEBUG_KMS("common rates: %s\n", str
);
1645 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1649 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1650 if (WARN_ON(len
<= 0))
1653 return intel_dp
->common_rates
[len
- 1];
1656 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1658 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1659 intel_dp
->num_sink_rates
, rate
);
1667 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1668 uint8_t *link_bw
, uint8_t *rate_select
)
1670 /* eDP 1.4 rate select method. */
1671 if (intel_dp
->use_rate_select
) {
1674 intel_dp_rate_select(intel_dp
, port_clock
);
1676 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1681 struct link_config_limits
{
1682 int min_clock
, max_clock
;
1683 int min_lane_count
, max_lane_count
;
1684 int min_bpp
, max_bpp
;
1687 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1688 struct intel_crtc_state
*pipe_config
)
1690 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1691 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1694 bpp
= pipe_config
->pipe_bpp
;
1695 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1698 bpp
= min(bpp
, 3*bpc
);
1700 if (intel_dp_is_edp(intel_dp
)) {
1701 /* Get bpp from vbt only for panels that dont have bpp in edid */
1702 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1703 dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
) {
1704 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1705 dev_priv
->vbt
.edp
.bpp
);
1706 bpp
= dev_priv
->vbt
.edp
.bpp
;
1713 /* Adjust link config limits based on compliance test requests. */
1715 intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp
,
1716 struct intel_crtc_state
*pipe_config
,
1717 struct link_config_limits
*limits
)
1719 /* For DP Compliance we override the computed bpp for the pipe */
1720 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1721 int bpp
= 3 * intel_dp
->compliance
.test_data
.bpc
;
1723 limits
->min_bpp
= limits
->max_bpp
= bpp
;
1724 pipe_config
->dither_force_disable
= bpp
== 6 * 3;
1726 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp
);
1729 /* Use values requested by Compliance Test Request */
1730 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1733 /* Validate the compliance test data since max values
1734 * might have changed due to link train fallback.
1736 if (intel_dp_link_params_valid(intel_dp
, intel_dp
->compliance
.test_link_rate
,
1737 intel_dp
->compliance
.test_lane_count
)) {
1738 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1739 intel_dp
->num_common_rates
,
1740 intel_dp
->compliance
.test_link_rate
);
1742 limits
->min_clock
= limits
->max_clock
= index
;
1743 limits
->min_lane_count
= limits
->max_lane_count
=
1744 intel_dp
->compliance
.test_lane_count
;
1749 /* Optimize link config in order: max bpp, min clock, min lanes */
1751 intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp
,
1752 struct intel_crtc_state
*pipe_config
,
1753 const struct link_config_limits
*limits
)
1755 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1756 int bpp
, clock
, lane_count
;
1757 int mode_rate
, link_clock
, link_avail
;
1759 for (bpp
= limits
->max_bpp
; bpp
>= limits
->min_bpp
; bpp
-= 2 * 3) {
1760 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1763 for (clock
= limits
->min_clock
; clock
<= limits
->max_clock
; clock
++) {
1764 for (lane_count
= limits
->min_lane_count
;
1765 lane_count
<= limits
->max_lane_count
;
1767 link_clock
= intel_dp
->common_rates
[clock
];
1768 link_avail
= intel_dp_max_data_rate(link_clock
,
1771 if (mode_rate
<= link_avail
) {
1772 pipe_config
->lane_count
= lane_count
;
1773 pipe_config
->pipe_bpp
= bpp
;
1774 pipe_config
->port_clock
= link_clock
;
1786 intel_dp_compute_link_config(struct intel_encoder
*encoder
,
1787 struct intel_crtc_state
*pipe_config
)
1789 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1790 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1791 struct link_config_limits limits
;
1794 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1795 intel_dp
->max_link_rate
);
1797 /* No common link rates between source and sink */
1798 WARN_ON(common_len
<= 0);
1800 limits
.min_clock
= 0;
1801 limits
.max_clock
= common_len
- 1;
1803 limits
.min_lane_count
= 1;
1804 limits
.max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1806 limits
.min_bpp
= 6 * 3;
1807 limits
.max_bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1809 if (intel_dp_is_edp(intel_dp
)) {
1811 * Use the maximum clock and number of lanes the eDP panel
1812 * advertizes being capable of. The panels are generally
1813 * designed to support only a single clock and lane
1814 * configuration, and typically these values correspond to the
1815 * native resolution of the panel.
1817 limits
.min_lane_count
= limits
.max_lane_count
;
1818 limits
.min_clock
= limits
.max_clock
;
1821 intel_dp_adjust_compliance_config(intel_dp
, pipe_config
, &limits
);
1823 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1824 "max rate %d max bpp %d pixel clock %iKHz\n",
1825 limits
.max_lane_count
,
1826 intel_dp
->common_rates
[limits
.max_clock
],
1827 limits
.max_bpp
, adjusted_mode
->crtc_clock
);
1830 * Optimize for slow and wide. This is the place to add alternative
1831 * optimization policy.
1833 if (!intel_dp_compute_link_config_wide(intel_dp
, pipe_config
, &limits
))
1836 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1837 pipe_config
->lane_count
, pipe_config
->port_clock
,
1838 pipe_config
->pipe_bpp
);
1840 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1841 intel_dp_link_required(adjusted_mode
->crtc_clock
,
1842 pipe_config
->pipe_bpp
),
1843 intel_dp_max_data_rate(pipe_config
->port_clock
,
1844 pipe_config
->lane_count
));
1850 intel_dp_compute_config(struct intel_encoder
*encoder
,
1851 struct intel_crtc_state
*pipe_config
,
1852 struct drm_connector_state
*conn_state
)
1854 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1855 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1856 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1857 enum port port
= encoder
->port
;
1858 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1859 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1860 struct intel_digital_connector_state
*intel_conn_state
=
1861 to_intel_digital_connector_state(conn_state
);
1862 bool reduce_m_n
= drm_dp_has_quirk(&intel_dp
->desc
,
1863 DP_DPCD_QUIRK_LIMITED_M_N
);
1865 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1866 pipe_config
->has_pch_encoder
= true;
1868 pipe_config
->has_drrs
= false;
1869 if (IS_G4X(dev_priv
) || port
== PORT_A
)
1870 pipe_config
->has_audio
= false;
1871 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1872 pipe_config
->has_audio
= intel_dp
->has_audio
;
1874 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1876 if (intel_dp_is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1877 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1880 if (INTEL_GEN(dev_priv
) >= 9) {
1883 ret
= skl_update_scaler_crtc(pipe_config
);
1888 if (HAS_GMCH_DISPLAY(dev_priv
))
1889 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1890 conn_state
->scaling_mode
);
1892 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1893 conn_state
->scaling_mode
);
1896 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
1899 if (HAS_GMCH_DISPLAY(dev_priv
) &&
1900 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1903 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1906 if (!intel_dp_compute_link_config(encoder
, pipe_config
))
1909 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1912 * CEA-861-E - 5.1 Default Encoding Parameters
1913 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1915 pipe_config
->limited_color_range
=
1916 pipe_config
->pipe_bpp
!= 18 &&
1917 drm_default_rgb_quant_range(adjusted_mode
) ==
1918 HDMI_QUANTIZATION_RANGE_LIMITED
;
1920 pipe_config
->limited_color_range
=
1921 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1924 intel_link_compute_m_n(pipe_config
->pipe_bpp
, pipe_config
->lane_count
,
1925 adjusted_mode
->crtc_clock
,
1926 pipe_config
->port_clock
,
1927 &pipe_config
->dp_m_n
,
1930 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1931 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1932 pipe_config
->has_drrs
= true;
1933 intel_link_compute_m_n(pipe_config
->pipe_bpp
,
1934 pipe_config
->lane_count
,
1935 intel_connector
->panel
.downclock_mode
->clock
,
1936 pipe_config
->port_clock
,
1937 &pipe_config
->dp_m2_n2
,
1941 if (!HAS_DDI(dev_priv
))
1942 intel_dp_set_clock(encoder
, pipe_config
);
1944 intel_psr_compute_config(intel_dp
, pipe_config
);
1949 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1950 int link_rate
, uint8_t lane_count
,
1953 intel_dp
->link_trained
= false;
1954 intel_dp
->link_rate
= link_rate
;
1955 intel_dp
->lane_count
= lane_count
;
1956 intel_dp
->link_mst
= link_mst
;
1959 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1960 const struct intel_crtc_state
*pipe_config
)
1962 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1963 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1964 enum port port
= encoder
->port
;
1965 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1966 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1968 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1969 pipe_config
->lane_count
,
1970 intel_crtc_has_type(pipe_config
,
1971 INTEL_OUTPUT_DP_MST
));
1974 * There are four kinds of DP registers:
1981 * IBX PCH and CPU are the same for almost everything,
1982 * except that the CPU DP PLL is configured in this
1985 * CPT PCH is quite different, having many bits moved
1986 * to the TRANS_DP_CTL register instead. That
1987 * configuration happens (oddly) in ironlake_pch_enable
1990 /* Preserve the BIOS-computed detected bit. This is
1991 * supposed to be read-only.
1993 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1995 /* Handle DP bits in common between all three register formats */
1996 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1997 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1999 /* Split out the IBX/CPU vs CPT settings */
2001 if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
2002 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
2003 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
2004 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
2005 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
2006 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
2008 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2009 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2011 intel_dp
->DP
|= DP_PIPE_SEL_IVB(crtc
->pipe
);
2012 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2015 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
2017 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2018 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2019 trans_dp
|= TRANS_DP_ENH_FRAMING
;
2021 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
2022 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
2024 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
2025 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
2027 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
2028 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
2029 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
2030 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
2031 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
2033 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2034 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2036 if (IS_CHERRYVIEW(dev_priv
))
2037 intel_dp
->DP
|= DP_PIPE_SEL_CHV(crtc
->pipe
);
2039 intel_dp
->DP
|= DP_PIPE_SEL(crtc
->pipe
);
2043 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2044 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2046 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2047 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2049 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2050 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2052 static void intel_pps_verify_state(struct intel_dp
*intel_dp
);
2054 static void wait_panel_status(struct intel_dp
*intel_dp
,
2058 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2059 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2061 lockdep_assert_held(&dev_priv
->pps_mutex
);
2063 intel_pps_verify_state(intel_dp
);
2065 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2066 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2068 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2070 I915_READ(pp_stat_reg
),
2071 I915_READ(pp_ctrl_reg
));
2073 if (intel_wait_for_register(dev_priv
,
2074 pp_stat_reg
, mask
, value
,
2076 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2077 I915_READ(pp_stat_reg
),
2078 I915_READ(pp_ctrl_reg
));
2080 DRM_DEBUG_KMS("Wait complete\n");
2083 static void wait_panel_on(struct intel_dp
*intel_dp
)
2085 DRM_DEBUG_KMS("Wait for panel power on\n");
2086 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
2089 static void wait_panel_off(struct intel_dp
*intel_dp
)
2091 DRM_DEBUG_KMS("Wait for panel power off time\n");
2092 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
2095 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
2097 ktime_t panel_power_on_time
;
2098 s64 panel_power_off_duration
;
2100 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2102 /* take the difference of currrent time and panel power off time
2103 * and then make panel wait for t11_t12 if needed. */
2104 panel_power_on_time
= ktime_get_boottime();
2105 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
2107 /* When we disable the VDD override bit last we have to do the manual
2109 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
2110 wait_remaining_ms_from_jiffies(jiffies
,
2111 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
2113 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2116 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2118 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2119 intel_dp
->backlight_on_delay
);
2122 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2124 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2125 intel_dp
->backlight_off_delay
);
2128 /* Read the current pp_control value, unlocking the register if it
2132 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2134 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2137 lockdep_assert_held(&dev_priv
->pps_mutex
);
2139 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2140 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2141 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2142 control
&= ~PANEL_UNLOCK_MASK
;
2143 control
|= PANEL_UNLOCK_REGS
;
2149 * Must be paired with edp_panel_vdd_off().
2150 * Must hold pps_mutex around the whole on/off sequence.
2151 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2153 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2155 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2156 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2158 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2159 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2161 lockdep_assert_held(&dev_priv
->pps_mutex
);
2163 if (!intel_dp_is_edp(intel_dp
))
2166 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2167 intel_dp
->want_panel_vdd
= true;
2169 if (edp_have_panel_vdd(intel_dp
))
2170 return need_to_disable
;
2172 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2174 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2175 port_name(intel_dig_port
->base
.port
));
2177 if (!edp_have_panel_power(intel_dp
))
2178 wait_panel_power_cycle(intel_dp
);
2180 pp
= ironlake_get_pp_control(intel_dp
);
2181 pp
|= EDP_FORCE_VDD
;
2183 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2184 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2186 I915_WRITE(pp_ctrl_reg
, pp
);
2187 POSTING_READ(pp_ctrl_reg
);
2188 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2189 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2191 * If the panel wasn't on, delay before accessing aux channel
2193 if (!edp_have_panel_power(intel_dp
)) {
2194 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2195 port_name(intel_dig_port
->base
.port
));
2196 msleep(intel_dp
->panel_power_up_delay
);
2199 return need_to_disable
;
2203 * Must be paired with intel_edp_panel_vdd_off() or
2204 * intel_edp_panel_off().
2205 * Nested calls to these functions are not allowed since
2206 * we drop the lock. Caller must use some higher level
2207 * locking to prevent nested calls from other threads.
2209 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2213 if (!intel_dp_is_edp(intel_dp
))
2217 vdd
= edp_panel_vdd_on(intel_dp
);
2218 pps_unlock(intel_dp
);
2220 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2221 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2224 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2226 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2227 struct intel_digital_port
*intel_dig_port
=
2228 dp_to_dig_port(intel_dp
);
2230 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2232 lockdep_assert_held(&dev_priv
->pps_mutex
);
2234 WARN_ON(intel_dp
->want_panel_vdd
);
2236 if (!edp_have_panel_vdd(intel_dp
))
2239 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2240 port_name(intel_dig_port
->base
.port
));
2242 pp
= ironlake_get_pp_control(intel_dp
);
2243 pp
&= ~EDP_FORCE_VDD
;
2245 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2246 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2248 I915_WRITE(pp_ctrl_reg
, pp
);
2249 POSTING_READ(pp_ctrl_reg
);
2251 /* Make sure sequencer is idle before allowing subsequent activity */
2252 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2253 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2255 if ((pp
& PANEL_POWER_ON
) == 0)
2256 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2258 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2261 static void edp_panel_vdd_work(struct work_struct
*__work
)
2263 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2264 struct intel_dp
, panel_vdd_work
);
2267 if (!intel_dp
->want_panel_vdd
)
2268 edp_panel_vdd_off_sync(intel_dp
);
2269 pps_unlock(intel_dp
);
2272 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2274 unsigned long delay
;
2277 * Queue the timer to fire a long time from now (relative to the power
2278 * down delay) to keep the panel power up across a sequence of
2281 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2282 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2286 * Must be paired with edp_panel_vdd_on().
2287 * Must hold pps_mutex around the whole on/off sequence.
2288 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2290 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2292 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2294 lockdep_assert_held(&dev_priv
->pps_mutex
);
2296 if (!intel_dp_is_edp(intel_dp
))
2299 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2300 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2302 intel_dp
->want_panel_vdd
= false;
2305 edp_panel_vdd_off_sync(intel_dp
);
2307 edp_panel_vdd_schedule_off(intel_dp
);
2310 static void edp_panel_on(struct intel_dp
*intel_dp
)
2312 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2314 i915_reg_t pp_ctrl_reg
;
2316 lockdep_assert_held(&dev_priv
->pps_mutex
);
2318 if (!intel_dp_is_edp(intel_dp
))
2321 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2322 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2324 if (WARN(edp_have_panel_power(intel_dp
),
2325 "eDP port %c panel power already on\n",
2326 port_name(dp_to_dig_port(intel_dp
)->base
.port
)))
2329 wait_panel_power_cycle(intel_dp
);
2331 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2332 pp
= ironlake_get_pp_control(intel_dp
);
2333 if (IS_GEN5(dev_priv
)) {
2334 /* ILK workaround: disable reset around power sequence */
2335 pp
&= ~PANEL_POWER_RESET
;
2336 I915_WRITE(pp_ctrl_reg
, pp
);
2337 POSTING_READ(pp_ctrl_reg
);
2340 pp
|= PANEL_POWER_ON
;
2341 if (!IS_GEN5(dev_priv
))
2342 pp
|= PANEL_POWER_RESET
;
2344 I915_WRITE(pp_ctrl_reg
, pp
);
2345 POSTING_READ(pp_ctrl_reg
);
2347 wait_panel_on(intel_dp
);
2348 intel_dp
->last_power_on
= jiffies
;
2350 if (IS_GEN5(dev_priv
)) {
2351 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2352 I915_WRITE(pp_ctrl_reg
, pp
);
2353 POSTING_READ(pp_ctrl_reg
);
2357 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2359 if (!intel_dp_is_edp(intel_dp
))
2363 edp_panel_on(intel_dp
);
2364 pps_unlock(intel_dp
);
2368 static void edp_panel_off(struct intel_dp
*intel_dp
)
2370 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2372 i915_reg_t pp_ctrl_reg
;
2374 lockdep_assert_held(&dev_priv
->pps_mutex
);
2376 if (!intel_dp_is_edp(intel_dp
))
2379 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2380 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2382 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2383 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2385 pp
= ironlake_get_pp_control(intel_dp
);
2386 /* We need to switch off panel power _and_ force vdd, for otherwise some
2387 * panels get very unhappy and cease to work. */
2388 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2391 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2393 intel_dp
->want_panel_vdd
= false;
2395 I915_WRITE(pp_ctrl_reg
, pp
);
2396 POSTING_READ(pp_ctrl_reg
);
2398 wait_panel_off(intel_dp
);
2399 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2401 /* We got a reference when we enabled the VDD. */
2402 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2405 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2407 if (!intel_dp_is_edp(intel_dp
))
2411 edp_panel_off(intel_dp
);
2412 pps_unlock(intel_dp
);
2415 /* Enable backlight in the panel power control. */
2416 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2418 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2420 i915_reg_t pp_ctrl_reg
;
2423 * If we enable the backlight right away following a panel power
2424 * on, we may see slight flicker as the panel syncs with the eDP
2425 * link. So delay a bit to make sure the image is solid before
2426 * allowing it to appear.
2428 wait_backlight_on(intel_dp
);
2432 pp
= ironlake_get_pp_control(intel_dp
);
2433 pp
|= EDP_BLC_ENABLE
;
2435 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2437 I915_WRITE(pp_ctrl_reg
, pp
);
2438 POSTING_READ(pp_ctrl_reg
);
2440 pps_unlock(intel_dp
);
2443 /* Enable backlight PWM and backlight PP control. */
2444 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2445 const struct drm_connector_state
*conn_state
)
2447 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2449 if (!intel_dp_is_edp(intel_dp
))
2452 DRM_DEBUG_KMS("\n");
2454 intel_panel_enable_backlight(crtc_state
, conn_state
);
2455 _intel_edp_backlight_on(intel_dp
);
2458 /* Disable backlight in the panel power control. */
2459 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2461 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2463 i915_reg_t pp_ctrl_reg
;
2465 if (!intel_dp_is_edp(intel_dp
))
2470 pp
= ironlake_get_pp_control(intel_dp
);
2471 pp
&= ~EDP_BLC_ENABLE
;
2473 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2475 I915_WRITE(pp_ctrl_reg
, pp
);
2476 POSTING_READ(pp_ctrl_reg
);
2478 pps_unlock(intel_dp
);
2480 intel_dp
->last_backlight_off
= jiffies
;
2481 edp_wait_backlight_off(intel_dp
);
2484 /* Disable backlight PP control and backlight PWM. */
2485 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2487 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2489 if (!intel_dp_is_edp(intel_dp
))
2492 DRM_DEBUG_KMS("\n");
2494 _intel_edp_backlight_off(intel_dp
);
2495 intel_panel_disable_backlight(old_conn_state
);
2499 * Hook for controlling the panel power control backlight through the bl_power
2500 * sysfs attribute. Take care to handle multiple calls.
2502 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2505 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2509 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2510 pps_unlock(intel_dp
);
2512 if (is_enabled
== enable
)
2515 DRM_DEBUG_KMS("panel power control backlight %s\n",
2516 enable
? "enable" : "disable");
2519 _intel_edp_backlight_on(intel_dp
);
2521 _intel_edp_backlight_off(intel_dp
);
2524 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2526 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2527 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2528 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2530 I915_STATE_WARN(cur_state
!= state
,
2531 "DP port %c state assertion failure (expected %s, current %s)\n",
2532 port_name(dig_port
->base
.port
),
2533 onoff(state
), onoff(cur_state
));
2535 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2537 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2539 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2541 I915_STATE_WARN(cur_state
!= state
,
2542 "eDP PLL state assertion failure (expected %s, current %s)\n",
2543 onoff(state
), onoff(cur_state
));
2545 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2546 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2548 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2549 const struct intel_crtc_state
*pipe_config
)
2551 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2552 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2554 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2555 assert_dp_port_disabled(intel_dp
);
2556 assert_edp_pll_disabled(dev_priv
);
2558 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2559 pipe_config
->port_clock
);
2561 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2563 if (pipe_config
->port_clock
== 162000)
2564 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2566 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2568 I915_WRITE(DP_A
, intel_dp
->DP
);
2573 * [DevILK] Work around required when enabling DP PLL
2574 * while a pipe is enabled going to FDI:
2575 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2576 * 2. Program DP PLL enable
2578 if (IS_GEN5(dev_priv
))
2579 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2581 intel_dp
->DP
|= DP_PLL_ENABLE
;
2583 I915_WRITE(DP_A
, intel_dp
->DP
);
2588 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
,
2589 const struct intel_crtc_state
*old_crtc_state
)
2591 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
2592 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2594 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2595 assert_dp_port_disabled(intel_dp
);
2596 assert_edp_pll_enabled(dev_priv
);
2598 DRM_DEBUG_KMS("disabling eDP PLL\n");
2600 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2602 I915_WRITE(DP_A
, intel_dp
->DP
);
2607 static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp
)
2610 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2611 * be capable of signalling downstream hpd with a long pulse.
2612 * Whether or not that means D3 is safe to use is not clear,
2613 * but let's assume so until proven otherwise.
2615 * FIXME should really check all downstream ports...
2617 return intel_dp
->dpcd
[DP_DPCD_REV
] == 0x11 &&
2618 intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
&&
2619 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
;
2622 /* If the sink supports it, try to set the power state appropriately */
2623 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2627 /* Should have a valid DPCD by this point */
2628 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2631 if (mode
!= DRM_MODE_DPMS_ON
) {
2632 if (downstream_hpd_needs_d0(intel_dp
))
2635 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2638 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2641 * When turning on, we need to retry for 1ms to give the sink
2644 for (i
= 0; i
< 3; i
++) {
2645 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2652 if (ret
== 1 && lspcon
->active
)
2653 lspcon_wait_pcon_mode(lspcon
);
2657 DRM_DEBUG_KMS("failed to %s sink power state\n",
2658 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2661 static bool cpt_dp_port_selected(struct drm_i915_private
*dev_priv
,
2662 enum port port
, enum pipe
*pipe
)
2666 for_each_pipe(dev_priv
, p
) {
2667 u32 val
= I915_READ(TRANS_DP_CTL(p
));
2669 if ((val
& TRANS_DP_PORT_SEL_MASK
) == TRANS_DP_PORT_SEL(port
)) {
2675 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port
));
2677 /* must initialize pipe to something for the asserts */
2683 bool intel_dp_port_enabled(struct drm_i915_private
*dev_priv
,
2684 i915_reg_t dp_reg
, enum port port
,
2690 val
= I915_READ(dp_reg
);
2692 ret
= val
& DP_PORT_EN
;
2694 /* asserts want to know the pipe even if the port is disabled */
2695 if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
)
2696 *pipe
= (val
& DP_PIPE_SEL_MASK_IVB
) >> DP_PIPE_SEL_SHIFT_IVB
;
2697 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
2698 ret
&= cpt_dp_port_selected(dev_priv
, port
, pipe
);
2699 else if (IS_CHERRYVIEW(dev_priv
))
2700 *pipe
= (val
& DP_PIPE_SEL_MASK_CHV
) >> DP_PIPE_SEL_SHIFT_CHV
;
2702 *pipe
= (val
& DP_PIPE_SEL_MASK
) >> DP_PIPE_SEL_SHIFT
;
2707 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2710 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2711 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2714 if (!intel_display_power_get_if_enabled(dev_priv
,
2715 encoder
->power_domain
))
2718 ret
= intel_dp_port_enabled(dev_priv
, intel_dp
->output_reg
,
2719 encoder
->port
, pipe
);
2721 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2726 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2727 struct intel_crtc_state
*pipe_config
)
2729 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2730 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2732 enum port port
= encoder
->port
;
2733 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2735 if (encoder
->type
== INTEL_OUTPUT_EDP
)
2736 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_EDP
);
2738 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_DP
);
2740 tmp
= I915_READ(intel_dp
->output_reg
);
2742 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2744 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2745 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2747 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2748 flags
|= DRM_MODE_FLAG_PHSYNC
;
2750 flags
|= DRM_MODE_FLAG_NHSYNC
;
2752 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2753 flags
|= DRM_MODE_FLAG_PVSYNC
;
2755 flags
|= DRM_MODE_FLAG_NVSYNC
;
2757 if (tmp
& DP_SYNC_HS_HIGH
)
2758 flags
|= DRM_MODE_FLAG_PHSYNC
;
2760 flags
|= DRM_MODE_FLAG_NHSYNC
;
2762 if (tmp
& DP_SYNC_VS_HIGH
)
2763 flags
|= DRM_MODE_FLAG_PVSYNC
;
2765 flags
|= DRM_MODE_FLAG_NVSYNC
;
2768 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2770 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2771 pipe_config
->limited_color_range
= true;
2773 pipe_config
->lane_count
=
2774 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2776 intel_dp_get_m_n(crtc
, pipe_config
);
2778 if (port
== PORT_A
) {
2779 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2780 pipe_config
->port_clock
= 162000;
2782 pipe_config
->port_clock
= 270000;
2785 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2786 intel_dotclock_calculate(pipe_config
->port_clock
,
2787 &pipe_config
->dp_m_n
);
2789 if (intel_dp_is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2790 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2792 * This is a big fat ugly hack.
2794 * Some machines in UEFI boot mode provide us a VBT that has 18
2795 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2796 * unknown we fail to light up. Yet the same BIOS boots up with
2797 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2798 * max, not what it tells us to use.
2800 * Note: This will still be broken if the eDP panel is not lit
2801 * up by the BIOS, and thus we can't get the mode at module
2804 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2805 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2806 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2810 static void intel_disable_dp(struct intel_encoder
*encoder
,
2811 const struct intel_crtc_state
*old_crtc_state
,
2812 const struct drm_connector_state
*old_conn_state
)
2814 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2816 intel_dp
->link_trained
= false;
2818 if (old_crtc_state
->has_audio
)
2819 intel_audio_codec_disable(encoder
,
2820 old_crtc_state
, old_conn_state
);
2822 /* Make sure the panel is off before trying to change the mode. But also
2823 * ensure that we have vdd while we switch off the panel. */
2824 intel_edp_panel_vdd_on(intel_dp
);
2825 intel_edp_backlight_off(old_conn_state
);
2826 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2827 intel_edp_panel_off(intel_dp
);
2830 static void g4x_disable_dp(struct intel_encoder
*encoder
,
2831 const struct intel_crtc_state
*old_crtc_state
,
2832 const struct drm_connector_state
*old_conn_state
)
2834 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2837 static void vlv_disable_dp(struct intel_encoder
*encoder
,
2838 const struct intel_crtc_state
*old_crtc_state
,
2839 const struct drm_connector_state
*old_conn_state
)
2841 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2843 intel_psr_disable(intel_dp
, old_crtc_state
);
2845 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2848 static void g4x_post_disable_dp(struct intel_encoder
*encoder
,
2849 const struct intel_crtc_state
*old_crtc_state
,
2850 const struct drm_connector_state
*old_conn_state
)
2852 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2853 enum port port
= encoder
->port
;
2856 * Bspec does not list a specific disable sequence for g4x DP.
2857 * Follow the ilk+ sequence (disable pipe before the port) for
2858 * g4x DP as it does not suffer from underruns like the normal
2859 * g4x modeset sequence (disable pipe after the port).
2861 intel_dp_link_down(encoder
, old_crtc_state
);
2863 /* Only ilk+ has port A */
2865 ironlake_edp_pll_off(intel_dp
, old_crtc_state
);
2868 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2869 const struct intel_crtc_state
*old_crtc_state
,
2870 const struct drm_connector_state
*old_conn_state
)
2872 intel_dp_link_down(encoder
, old_crtc_state
);
2875 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2876 const struct intel_crtc_state
*old_crtc_state
,
2877 const struct drm_connector_state
*old_conn_state
)
2879 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2881 intel_dp_link_down(encoder
, old_crtc_state
);
2883 mutex_lock(&dev_priv
->sb_lock
);
2885 /* Assert data lane reset */
2886 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
2888 mutex_unlock(&dev_priv
->sb_lock
);
2892 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2894 uint8_t dp_train_pat
)
2896 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2897 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2898 enum port port
= intel_dig_port
->base
.port
;
2899 uint8_t train_pat_mask
= drm_dp_training_pattern_mask(intel_dp
->dpcd
);
2901 if (dp_train_pat
& train_pat_mask
)
2902 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2903 dp_train_pat
& train_pat_mask
);
2905 if (HAS_DDI(dev_priv
)) {
2906 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2908 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2909 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2911 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2913 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2914 switch (dp_train_pat
& train_pat_mask
) {
2915 case DP_TRAINING_PATTERN_DISABLE
:
2916 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2919 case DP_TRAINING_PATTERN_1
:
2920 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2922 case DP_TRAINING_PATTERN_2
:
2923 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2925 case DP_TRAINING_PATTERN_3
:
2926 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2928 case DP_TRAINING_PATTERN_4
:
2929 temp
|= DP_TP_CTL_LINK_TRAIN_PAT4
;
2932 I915_WRITE(DP_TP_CTL(port
), temp
);
2934 } else if ((IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) ||
2935 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2936 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2938 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2939 case DP_TRAINING_PATTERN_DISABLE
:
2940 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2942 case DP_TRAINING_PATTERN_1
:
2943 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2945 case DP_TRAINING_PATTERN_2
:
2946 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2948 case DP_TRAINING_PATTERN_3
:
2949 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2950 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2955 *DP
&= ~DP_LINK_TRAIN_MASK
;
2957 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2958 case DP_TRAINING_PATTERN_DISABLE
:
2959 *DP
|= DP_LINK_TRAIN_OFF
;
2961 case DP_TRAINING_PATTERN_1
:
2962 *DP
|= DP_LINK_TRAIN_PAT_1
;
2964 case DP_TRAINING_PATTERN_2
:
2965 *DP
|= DP_LINK_TRAIN_PAT_2
;
2967 case DP_TRAINING_PATTERN_3
:
2968 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2969 *DP
|= DP_LINK_TRAIN_PAT_2
;
2975 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2976 const struct intel_crtc_state
*old_crtc_state
)
2978 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2980 /* enable with pattern 1 (as per spec) */
2982 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2985 * Magic for VLV/CHV. We _must_ first set up the register
2986 * without actually enabling the port, and then do another
2987 * write to enable the port. Otherwise link training will
2988 * fail when the power sequencer is freshly used for this port.
2990 intel_dp
->DP
|= DP_PORT_EN
;
2991 if (old_crtc_state
->has_audio
)
2992 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2994 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2995 POSTING_READ(intel_dp
->output_reg
);
2998 static void intel_enable_dp(struct intel_encoder
*encoder
,
2999 const struct intel_crtc_state
*pipe_config
,
3000 const struct drm_connector_state
*conn_state
)
3002 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3003 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3004 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
3005 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
3006 enum pipe pipe
= crtc
->pipe
;
3008 if (WARN_ON(dp_reg
& DP_PORT_EN
))
3013 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3014 vlv_init_panel_power_sequencer(encoder
, pipe_config
);
3016 intel_dp_enable_port(intel_dp
, pipe_config
);
3018 edp_panel_vdd_on(intel_dp
);
3019 edp_panel_on(intel_dp
);
3020 edp_panel_vdd_off(intel_dp
, true);
3022 pps_unlock(intel_dp
);
3024 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3025 unsigned int lane_mask
= 0x0;
3027 if (IS_CHERRYVIEW(dev_priv
))
3028 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
3030 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
3034 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
3035 intel_dp_start_link_train(intel_dp
);
3036 intel_dp_stop_link_train(intel_dp
);
3038 if (pipe_config
->has_audio
) {
3039 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3041 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
3045 static void g4x_enable_dp(struct intel_encoder
*encoder
,
3046 const struct intel_crtc_state
*pipe_config
,
3047 const struct drm_connector_state
*conn_state
)
3049 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3050 intel_edp_backlight_on(pipe_config
, conn_state
);
3053 static void vlv_enable_dp(struct intel_encoder
*encoder
,
3054 const struct intel_crtc_state
*pipe_config
,
3055 const struct drm_connector_state
*conn_state
)
3057 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3059 intel_edp_backlight_on(pipe_config
, conn_state
);
3060 intel_psr_enable(intel_dp
, pipe_config
);
3063 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
3064 const struct intel_crtc_state
*pipe_config
,
3065 const struct drm_connector_state
*conn_state
)
3067 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3068 enum port port
= encoder
->port
;
3070 intel_dp_prepare(encoder
, pipe_config
);
3072 /* Only ilk+ has port A */
3074 ironlake_edp_pll_on(intel_dp
, pipe_config
);
3077 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
3079 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3080 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
3081 enum pipe pipe
= intel_dp
->pps_pipe
;
3082 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
3084 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3086 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
3089 edp_panel_vdd_off_sync(intel_dp
);
3092 * VLV seems to get confused when multiple power sequencers
3093 * have the same port selected (even if only one has power/vdd
3094 * enabled). The failure manifests as vlv_wait_port_ready() failing
3095 * CHV on the other hand doesn't seem to mind having the same port
3096 * selected in multiple power sequencers, but let's clear the
3097 * port select always when logically disconnecting a power sequencer
3100 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3101 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
3102 I915_WRITE(pp_on_reg
, 0);
3103 POSTING_READ(pp_on_reg
);
3105 intel_dp
->pps_pipe
= INVALID_PIPE
;
3108 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
3111 struct intel_encoder
*encoder
;
3113 lockdep_assert_held(&dev_priv
->pps_mutex
);
3115 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
3116 struct intel_dp
*intel_dp
;
3119 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
3120 encoder
->type
!= INTEL_OUTPUT_EDP
)
3123 intel_dp
= enc_to_intel_dp(&encoder
->base
);
3124 port
= dp_to_dig_port(intel_dp
)->base
.port
;
3126 WARN(intel_dp
->active_pipe
== pipe
,
3127 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3128 pipe_name(pipe
), port_name(port
));
3130 if (intel_dp
->pps_pipe
!= pipe
)
3133 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3134 pipe_name(pipe
), port_name(port
));
3136 /* make sure vdd is off before we steal it */
3137 vlv_detach_power_sequencer(intel_dp
);
3141 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
3142 const struct intel_crtc_state
*crtc_state
)
3144 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3145 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3146 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3148 lockdep_assert_held(&dev_priv
->pps_mutex
);
3150 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3152 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3153 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3155 * If another power sequencer was being used on this
3156 * port previously make sure to turn off vdd there while
3157 * we still have control of it.
3159 vlv_detach_power_sequencer(intel_dp
);
3163 * We may be stealing the power
3164 * sequencer from another port.
3166 vlv_steal_power_sequencer(dev_priv
, crtc
->pipe
);
3168 intel_dp
->active_pipe
= crtc
->pipe
;
3170 if (!intel_dp_is_edp(intel_dp
))
3173 /* now it's all ours */
3174 intel_dp
->pps_pipe
= crtc
->pipe
;
3176 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3177 pipe_name(intel_dp
->pps_pipe
), port_name(encoder
->port
));
3179 /* init power sequencer on this pipe and port */
3180 intel_dp_init_panel_power_sequencer(intel_dp
);
3181 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
3184 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3185 const struct intel_crtc_state
*pipe_config
,
3186 const struct drm_connector_state
*conn_state
)
3188 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
3190 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3193 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3194 const struct intel_crtc_state
*pipe_config
,
3195 const struct drm_connector_state
*conn_state
)
3197 intel_dp_prepare(encoder
, pipe_config
);
3199 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
3202 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3203 const struct intel_crtc_state
*pipe_config
,
3204 const struct drm_connector_state
*conn_state
)
3206 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
3208 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3210 /* Second common lane will stay alive on its own now */
3211 chv_phy_release_cl2_override(encoder
);
3214 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3215 const struct intel_crtc_state
*pipe_config
,
3216 const struct drm_connector_state
*conn_state
)
3218 intel_dp_prepare(encoder
, pipe_config
);
3220 chv_phy_pre_pll_enable(encoder
, pipe_config
);
3223 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3224 const struct intel_crtc_state
*old_crtc_state
,
3225 const struct drm_connector_state
*old_conn_state
)
3227 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
3231 * Fetch AUX CH registers 0x202 - 0x207 which contain
3232 * link status information
3235 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3237 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3238 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3241 /* These are source-specific values. */
3243 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3245 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3246 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3247 enum port port
= encoder
->port
;
3249 if (HAS_DDI(dev_priv
))
3250 return intel_ddi_dp_voltage_max(encoder
);
3251 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3252 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3253 else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
)
3254 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3255 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3256 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3258 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3262 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3264 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3265 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3266 enum port port
= encoder
->port
;
3268 if (HAS_DDI(dev_priv
)) {
3269 return intel_ddi_dp_pre_emphasis_max(encoder
, voltage_swing
);
3270 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3271 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3273 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3275 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3277 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3280 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3282 } else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
3283 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3285 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3288 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3290 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3293 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3295 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3297 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3298 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3299 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3302 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3307 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3309 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3310 unsigned long demph_reg_value
, preemph_reg_value
,
3311 uniqtranscale_reg_value
;
3312 uint8_t train_set
= intel_dp
->train_set
[0];
3314 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3315 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3316 preemph_reg_value
= 0x0004000;
3317 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3319 demph_reg_value
= 0x2B405555;
3320 uniqtranscale_reg_value
= 0x552AB83A;
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3323 demph_reg_value
= 0x2B404040;
3324 uniqtranscale_reg_value
= 0x5548B83A;
3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3327 demph_reg_value
= 0x2B245555;
3328 uniqtranscale_reg_value
= 0x5560B83A;
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3331 demph_reg_value
= 0x2B405555;
3332 uniqtranscale_reg_value
= 0x5598DA3A;
3338 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3339 preemph_reg_value
= 0x0002000;
3340 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3342 demph_reg_value
= 0x2B404040;
3343 uniqtranscale_reg_value
= 0x5552B83A;
3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3346 demph_reg_value
= 0x2B404848;
3347 uniqtranscale_reg_value
= 0x5580B83A;
3349 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3350 demph_reg_value
= 0x2B404040;
3351 uniqtranscale_reg_value
= 0x55ADDA3A;
3357 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3358 preemph_reg_value
= 0x0000000;
3359 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3361 demph_reg_value
= 0x2B305555;
3362 uniqtranscale_reg_value
= 0x5570B83A;
3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3365 demph_reg_value
= 0x2B2B4040;
3366 uniqtranscale_reg_value
= 0x55ADDA3A;
3372 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3373 preemph_reg_value
= 0x0006000;
3374 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3376 demph_reg_value
= 0x1B405555;
3377 uniqtranscale_reg_value
= 0x55ADDA3A;
3387 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3388 uniqtranscale_reg_value
, 0);
3393 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3395 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3396 u32 deemph_reg_value
, margin_reg_value
;
3397 bool uniq_trans_scale
= false;
3398 uint8_t train_set
= intel_dp
->train_set
[0];
3400 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3401 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3402 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3404 deemph_reg_value
= 128;
3405 margin_reg_value
= 52;
3407 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3408 deemph_reg_value
= 128;
3409 margin_reg_value
= 77;
3411 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3412 deemph_reg_value
= 128;
3413 margin_reg_value
= 102;
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3416 deemph_reg_value
= 128;
3417 margin_reg_value
= 154;
3418 uniq_trans_scale
= true;
3424 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3425 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3427 deemph_reg_value
= 85;
3428 margin_reg_value
= 78;
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3431 deemph_reg_value
= 85;
3432 margin_reg_value
= 116;
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3435 deemph_reg_value
= 85;
3436 margin_reg_value
= 154;
3442 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3443 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3445 deemph_reg_value
= 64;
3446 margin_reg_value
= 104;
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3449 deemph_reg_value
= 64;
3450 margin_reg_value
= 154;
3456 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3457 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3458 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3459 deemph_reg_value
= 43;
3460 margin_reg_value
= 154;
3470 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3471 margin_reg_value
, uniq_trans_scale
);
3477 g4x_signal_levels(uint8_t train_set
)
3479 uint32_t signal_levels
= 0;
3481 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3482 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3484 signal_levels
|= DP_VOLTAGE_0_4
;
3486 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3487 signal_levels
|= DP_VOLTAGE_0_6
;
3489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3490 signal_levels
|= DP_VOLTAGE_0_8
;
3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3493 signal_levels
|= DP_VOLTAGE_1_2
;
3496 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3497 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3499 signal_levels
|= DP_PRE_EMPHASIS_0
;
3501 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3502 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3504 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3505 signal_levels
|= DP_PRE_EMPHASIS_6
;
3507 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3508 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3511 return signal_levels
;
3514 /* SNB CPU eDP voltage swing and pre-emphasis control */
3516 snb_cpu_edp_signal_levels(uint8_t train_set
)
3518 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3519 DP_TRAIN_PRE_EMPHASIS_MASK
);
3520 switch (signal_levels
) {
3521 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3523 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3524 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3525 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3527 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3528 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3531 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3533 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3534 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3536 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3537 "0x%x\n", signal_levels
);
3538 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3542 /* IVB CPU eDP voltage swing and pre-emphasis control */
3544 ivb_cpu_edp_signal_levels(uint8_t train_set
)
3546 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3547 DP_TRAIN_PRE_EMPHASIS_MASK
);
3548 switch (signal_levels
) {
3549 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3550 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3551 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3552 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3553 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3554 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3556 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3557 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3558 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3559 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3561 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3562 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3564 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3567 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3568 "0x%x\n", signal_levels
);
3569 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3574 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3576 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3577 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3578 enum port port
= intel_dig_port
->base
.port
;
3579 uint32_t signal_levels
, mask
= 0;
3580 uint8_t train_set
= intel_dp
->train_set
[0];
3582 if (IS_GEN9_LP(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
3583 signal_levels
= bxt_signal_levels(intel_dp
);
3584 } else if (HAS_DDI(dev_priv
)) {
3585 signal_levels
= ddi_signal_levels(intel_dp
);
3586 mask
= DDI_BUF_EMP_MASK
;
3587 } else if (IS_CHERRYVIEW(dev_priv
)) {
3588 signal_levels
= chv_signal_levels(intel_dp
);
3589 } else if (IS_VALLEYVIEW(dev_priv
)) {
3590 signal_levels
= vlv_signal_levels(intel_dp
);
3591 } else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
3592 signal_levels
= ivb_cpu_edp_signal_levels(train_set
);
3593 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3594 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3595 signal_levels
= snb_cpu_edp_signal_levels(train_set
);
3596 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3598 signal_levels
= g4x_signal_levels(train_set
);
3599 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3603 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3605 DRM_DEBUG_KMS("Using vswing level %d\n",
3606 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3607 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3608 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3609 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3611 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3613 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3614 POSTING_READ(intel_dp
->output_reg
);
3618 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3619 uint8_t dp_train_pat
)
3621 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3622 struct drm_i915_private
*dev_priv
=
3623 to_i915(intel_dig_port
->base
.base
.dev
);
3625 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3627 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3628 POSTING_READ(intel_dp
->output_reg
);
3631 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3633 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3634 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3635 enum port port
= intel_dig_port
->base
.port
;
3638 if (!HAS_DDI(dev_priv
))
3641 val
= I915_READ(DP_TP_CTL(port
));
3642 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3643 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3644 I915_WRITE(DP_TP_CTL(port
), val
);
3647 * On PORT_A we can have only eDP in SST mode. There the only reason
3648 * we need to set idle transmission mode is to work around a HW issue
3649 * where we enable the pipe while not in idle link-training mode.
3650 * In this case there is requirement to wait for a minimum number of
3651 * idle patterns to be sent.
3656 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3657 DP_TP_STATUS_IDLE_DONE
,
3658 DP_TP_STATUS_IDLE_DONE
,
3660 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3664 intel_dp_link_down(struct intel_encoder
*encoder
,
3665 const struct intel_crtc_state
*old_crtc_state
)
3667 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3668 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3669 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
3670 enum port port
= encoder
->port
;
3671 uint32_t DP
= intel_dp
->DP
;
3673 if (WARN_ON(HAS_DDI(dev_priv
)))
3676 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3679 DRM_DEBUG_KMS("\n");
3681 if ((IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) ||
3682 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3683 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3684 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3686 DP
&= ~DP_LINK_TRAIN_MASK
;
3687 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3689 I915_WRITE(intel_dp
->output_reg
, DP
);
3690 POSTING_READ(intel_dp
->output_reg
);
3692 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3693 I915_WRITE(intel_dp
->output_reg
, DP
);
3694 POSTING_READ(intel_dp
->output_reg
);
3697 * HW workaround for IBX, we need to move the port
3698 * to transcoder A after disabling it to allow the
3699 * matching HDMI port to be enabled on transcoder A.
3701 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3703 * We get CPU/PCH FIFO underruns on the other pipe when
3704 * doing the workaround. Sweep them under the rug.
3706 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3707 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3709 /* always enable with pattern 1 (as per spec) */
3710 DP
&= ~(DP_PIPE_SEL_MASK
| DP_LINK_TRAIN_MASK
);
3711 DP
|= DP_PORT_EN
| DP_PIPE_SEL(PIPE_A
) |
3712 DP_LINK_TRAIN_PAT_1
;
3713 I915_WRITE(intel_dp
->output_reg
, DP
);
3714 POSTING_READ(intel_dp
->output_reg
);
3717 I915_WRITE(intel_dp
->output_reg
, DP
);
3718 POSTING_READ(intel_dp
->output_reg
);
3720 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3721 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3722 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3725 msleep(intel_dp
->panel_power_down_delay
);
3729 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3731 intel_dp
->active_pipe
= INVALID_PIPE
;
3732 pps_unlock(intel_dp
);
3737 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3739 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3740 sizeof(intel_dp
->dpcd
)) < 0)
3741 return false; /* aux transfer failed */
3743 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3745 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3749 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3751 struct drm_i915_private
*dev_priv
=
3752 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3754 /* this function is meant to be called only once */
3755 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3757 if (!intel_dp_read_dpcd(intel_dp
))
3760 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
3761 drm_dp_is_branch(intel_dp
->dpcd
));
3763 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3764 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3765 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3768 * Read the eDP display control registers.
3770 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3771 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3772 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3773 * method). The display control registers should read zero if they're
3774 * not supported anyway.
3776 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3777 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3778 sizeof(intel_dp
->edp_dpcd
))
3779 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3780 intel_dp
->edp_dpcd
);
3783 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3784 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3786 intel_psr_init_dpcd(intel_dp
);
3788 /* Read the eDP 1.4+ supported link rates. */
3789 if (intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
3790 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3793 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3794 sink_rates
, sizeof(sink_rates
));
3796 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3797 int val
= le16_to_cpu(sink_rates
[i
]);
3802 /* Value read multiplied by 200kHz gives the per-lane
3803 * link rate in kHz. The source rates are, however,
3804 * stored in terms of LS_Clk kHz. The full conversion
3805 * back to symbols is
3806 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3808 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3810 intel_dp
->num_sink_rates
= i
;
3814 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3815 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3817 if (intel_dp
->num_sink_rates
)
3818 intel_dp
->use_rate_select
= true;
3820 intel_dp_set_sink_rates(intel_dp
);
3822 intel_dp_set_common_rates(intel_dp
);
3829 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3833 if (!intel_dp_read_dpcd(intel_dp
))
3836 /* Don't clobber cached eDP rates. */
3837 if (!intel_dp_is_edp(intel_dp
)) {
3838 intel_dp_set_sink_rates(intel_dp
);
3839 intel_dp_set_common_rates(intel_dp
);
3842 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &sink_count
) <= 0)
3846 * Sink count can change between short pulse hpd hence
3847 * a member variable in intel_dp will track any changes
3848 * between short pulse interrupts.
3850 intel_dp
->sink_count
= DP_GET_SINK_COUNT(sink_count
);
3853 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3854 * a dongle is present but no display. Unless we require to know
3855 * if a dongle is present or not, we don't need to update
3856 * downstream port information. So, an early return here saves
3857 * time from performing other operations which are not required.
3859 if (!intel_dp_is_edp(intel_dp
) && !intel_dp
->sink_count
)
3862 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3863 return true; /* native DP sink */
3865 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3866 return true; /* no per-port downstream info */
3868 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3869 intel_dp
->downstream_ports
,
3870 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3871 return false; /* downstream port status fetch failed */
3877 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3881 if (!i915_modparams
.enable_dp_mst
)
3884 if (!intel_dp
->can_mst
)
3887 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3890 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
3893 return mstm_cap
& DP_MST_CAP
;
3897 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3899 if (!i915_modparams
.enable_dp_mst
)
3902 if (!intel_dp
->can_mst
)
3905 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3907 if (intel_dp
->is_mst
)
3908 DRM_DEBUG_KMS("Sink is MST capable\n");
3910 DRM_DEBUG_KMS("Sink is not MST capable\n");
3912 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3916 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
,
3917 struct intel_crtc_state
*crtc_state
, bool disable_wa
)
3919 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3920 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3927 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3928 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3933 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3934 buf
& ~DP_TEST_SINK_START
) < 0) {
3935 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3941 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3943 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3944 DP_TEST_SINK_MISC
, &buf
) < 0) {
3948 count
= buf
& DP_TEST_COUNT_MASK
;
3949 } while (--attempts
&& count
);
3951 if (attempts
== 0) {
3952 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3958 hsw_enable_ips(crtc_state
);
3962 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
,
3963 struct intel_crtc_state
*crtc_state
)
3965 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3966 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3971 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3974 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3977 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3980 if (buf
& DP_TEST_SINK_START
) {
3981 ret
= intel_dp_sink_crc_stop(intel_dp
, crtc_state
, false);
3986 hsw_disable_ips(crtc_state
);
3988 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3989 buf
| DP_TEST_SINK_START
) < 0) {
3990 hsw_enable_ips(crtc_state
);
3994 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3998 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, struct intel_crtc_state
*crtc_state
, u8
*crc
)
4000 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4001 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
4002 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4007 ret
= intel_dp_sink_crc_start(intel_dp
, crtc_state
);
4012 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
4014 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4015 DP_TEST_SINK_MISC
, &buf
) < 0) {
4019 count
= buf
& DP_TEST_COUNT_MASK
;
4021 } while (--attempts
&& count
== 0);
4023 if (attempts
== 0) {
4024 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4029 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4035 intel_dp_sink_crc_stop(intel_dp
, crtc_state
, true);
4040 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4042 return drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
4043 sink_irq_vector
) == 1;
4047 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4049 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT_ESI
,
4050 sink_irq_vector
, DP_DPRX_ESI_LEN
) ==
4054 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4058 uint8_t test_lane_count
, test_link_bw
;
4062 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4063 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4067 DRM_DEBUG_KMS("Lane count read failed\n");
4070 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4072 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4075 DRM_DEBUG_KMS("Link Rate read failed\n");
4078 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4080 /* Validate the requested link rate and lane count */
4081 if (!intel_dp_link_params_valid(intel_dp
, test_link_rate
,
4085 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4086 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4091 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4093 uint8_t test_pattern
;
4095 __be16 h_width
, v_height
;
4098 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4099 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4102 DRM_DEBUG_KMS("Test pattern read failed\n");
4105 if (test_pattern
!= DP_COLOR_RAMP
)
4108 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4111 DRM_DEBUG_KMS("H Width read failed\n");
4115 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4118 DRM_DEBUG_KMS("V Height read failed\n");
4122 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4125 DRM_DEBUG_KMS("TEST MISC read failed\n");
4128 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4130 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4132 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4133 case DP_TEST_BIT_DEPTH_6
:
4134 intel_dp
->compliance
.test_data
.bpc
= 6;
4136 case DP_TEST_BIT_DEPTH_8
:
4137 intel_dp
->compliance
.test_data
.bpc
= 8;
4143 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4144 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4145 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4146 /* Set test active flag here so userspace doesn't interrupt things */
4147 intel_dp
->compliance
.test_active
= 1;
4152 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4154 uint8_t test_result
= DP_TEST_ACK
;
4155 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4156 struct drm_connector
*connector
= &intel_connector
->base
;
4158 if (intel_connector
->detect_edid
== NULL
||
4159 connector
->edid_corrupt
||
4160 intel_dp
->aux
.i2c_defer_count
> 6) {
4161 /* Check EDID read for NACKs, DEFERs and corruption
4162 * (DP CTS 1.2 Core r1.1)
4163 * 4.2.2.4 : Failed EDID read, I2C_NAK
4164 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4165 * 4.2.2.6 : EDID corruption detected
4166 * Use failsafe mode for all cases
4168 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4169 intel_dp
->aux
.i2c_defer_count
> 0)
4170 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4171 intel_dp
->aux
.i2c_nack_count
,
4172 intel_dp
->aux
.i2c_defer_count
);
4173 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4175 struct edid
*block
= intel_connector
->detect_edid
;
4177 /* We have to write the checksum
4178 * of the last block read
4180 block
+= intel_connector
->detect_edid
->extensions
;
4182 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4183 block
->checksum
) <= 0)
4184 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4186 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4187 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4190 /* Set test active flag here so userspace doesn't interrupt things */
4191 intel_dp
->compliance
.test_active
= 1;
4196 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4198 uint8_t test_result
= DP_TEST_NAK
;
4202 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4204 uint8_t response
= DP_TEST_NAK
;
4205 uint8_t request
= 0;
4208 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4210 DRM_DEBUG_KMS("Could not read test request from sink\n");
4215 case DP_TEST_LINK_TRAINING
:
4216 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4217 response
= intel_dp_autotest_link_training(intel_dp
);
4219 case DP_TEST_LINK_VIDEO_PATTERN
:
4220 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4221 response
= intel_dp_autotest_video_pattern(intel_dp
);
4223 case DP_TEST_LINK_EDID_READ
:
4224 DRM_DEBUG_KMS("EDID test requested\n");
4225 response
= intel_dp_autotest_edid(intel_dp
);
4227 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4228 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4229 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4232 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4236 if (response
& DP_TEST_ACK
)
4237 intel_dp
->compliance
.test_type
= request
;
4240 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4242 DRM_DEBUG_KMS("Could not write test response to sink\n");
4246 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4250 if (intel_dp
->is_mst
) {
4251 u8 esi
[DP_DPRX_ESI_LEN
] = { 0 };
4255 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4259 /* check link status - esi[10] = 0x200c */
4260 if (intel_dp
->active_mst_links
&&
4261 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4262 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4263 intel_dp_start_link_train(intel_dp
);
4264 intel_dp_stop_link_train(intel_dp
);
4267 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4268 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4271 for (retry
= 0; retry
< 3; retry
++) {
4273 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4274 DP_SINK_COUNT_ESI
+1,
4281 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4283 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4291 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4292 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4293 intel_dp
->is_mst
= false;
4294 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4295 /* send a hotplug event */
4296 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4303 intel_dp_needs_link_retrain(struct intel_dp
*intel_dp
)
4305 u8 link_status
[DP_LINK_STATUS_SIZE
];
4307 if (!intel_dp
->link_trained
)
4310 if (!intel_dp_get_link_status(intel_dp
, link_status
))
4314 * Validate the cached values of intel_dp->link_rate and
4315 * intel_dp->lane_count before attempting to retrain.
4317 if (!intel_dp_link_params_valid(intel_dp
, intel_dp
->link_rate
,
4318 intel_dp
->lane_count
))
4321 /* Retrain if Channel EQ or CR not ok */
4322 return !drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
);
4326 * If display is now connected check links status,
4327 * there has been known issues of link loss triggering
4330 * Some sinks (eg. ASUS PB287Q) seem to perform some
4331 * weird HPD ping pong during modesets. So we can apparently
4332 * end up with HPD going low during a modeset, and then
4333 * going back up soon after. And once that happens we must
4334 * retrain the link to get a picture. That's in case no
4335 * userspace component reacted to intermittent HPD dip.
4337 int intel_dp_retrain_link(struct intel_encoder
*encoder
,
4338 struct drm_modeset_acquire_ctx
*ctx
)
4340 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4341 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
4342 struct intel_connector
*connector
= intel_dp
->attached_connector
;
4343 struct drm_connector_state
*conn_state
;
4344 struct intel_crtc_state
*crtc_state
;
4345 struct intel_crtc
*crtc
;
4348 /* FIXME handle the MST connectors as well */
4350 if (!connector
|| connector
->base
.status
!= connector_status_connected
)
4353 ret
= drm_modeset_lock(&dev_priv
->drm
.mode_config
.connection_mutex
,
4358 conn_state
= connector
->base
.state
;
4360 crtc
= to_intel_crtc(conn_state
->crtc
);
4364 ret
= drm_modeset_lock(&crtc
->base
.mutex
, ctx
);
4368 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
4370 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state
));
4372 if (!crtc_state
->base
.active
)
4375 if (conn_state
->commit
&&
4376 !try_wait_for_completion(&conn_state
->commit
->hw_done
))
4379 if (!intel_dp_needs_link_retrain(intel_dp
))
4382 /* Suppress underruns caused by re-training */
4383 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4384 if (crtc
->config
->has_pch_encoder
)
4385 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4386 intel_crtc_pch_transcoder(crtc
), false);
4388 intel_dp_start_link_train(intel_dp
);
4389 intel_dp_stop_link_train(intel_dp
);
4391 /* Keep underrun reporting disabled until things are stable */
4392 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4394 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4395 if (crtc
->config
->has_pch_encoder
)
4396 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4397 intel_crtc_pch_transcoder(crtc
), true);
4403 * If display is now connected check links status,
4404 * there has been known issues of link loss triggering
4407 * Some sinks (eg. ASUS PB287Q) seem to perform some
4408 * weird HPD ping pong during modesets. So we can apparently
4409 * end up with HPD going low during a modeset, and then
4410 * going back up soon after. And once that happens we must
4411 * retrain the link to get a picture. That's in case no
4412 * userspace component reacted to intermittent HPD dip.
4414 static bool intel_dp_hotplug(struct intel_encoder
*encoder
,
4415 struct intel_connector
*connector
)
4417 struct drm_modeset_acquire_ctx ctx
;
4421 changed
= intel_encoder_hotplug(encoder
, connector
);
4423 drm_modeset_acquire_init(&ctx
, 0);
4426 ret
= intel_dp_retrain_link(encoder
, &ctx
);
4428 if (ret
== -EDEADLK
) {
4429 drm_modeset_backoff(&ctx
);
4436 drm_modeset_drop_locks(&ctx
);
4437 drm_modeset_acquire_fini(&ctx
);
4438 WARN(ret
, "Acquiring modeset locks failed with %i\n", ret
);
4444 * According to DP spec
4447 * 2. Configure link according to Receiver Capabilities
4448 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4449 * 4. Check link status on receipt of hot-plug interrupt
4451 * intel_dp_short_pulse - handles short pulse interrupts
4452 * when full detection is not required.
4453 * Returns %true if short pulse is handled and full detection
4454 * is NOT required and %false otherwise.
4457 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4459 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4460 u8 sink_irq_vector
= 0;
4461 u8 old_sink_count
= intel_dp
->sink_count
;
4465 * Clearing compliance test variables to allow capturing
4466 * of values for next automated test request.
4468 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4471 * Now read the DPCD to see if it's actually running
4472 * If the current value of sink count doesn't match with
4473 * the value that was stored earlier or dpcd read failed
4474 * we need to do full detection
4476 ret
= intel_dp_get_dpcd(intel_dp
);
4478 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4479 /* No need to proceed if we are going to do full detect */
4483 /* Try to read the source of the interrupt */
4484 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4485 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4486 sink_irq_vector
!= 0) {
4487 /* Clear interrupt source */
4488 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4489 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4492 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4493 intel_dp_handle_test_request(intel_dp
);
4494 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4495 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4498 /* Handle CEC interrupts, if any */
4499 drm_dp_cec_irq(&intel_dp
->aux
);
4501 /* defer to the hotplug work for link retraining if needed */
4502 if (intel_dp_needs_link_retrain(intel_dp
))
4505 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4506 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4507 /* Send a Hotplug Uevent to userspace to start modeset */
4508 drm_kms_helper_hotplug_event(&dev_priv
->drm
);
4514 /* XXX this is probably wrong for multiple downstream ports */
4515 static enum drm_connector_status
4516 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4518 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4519 uint8_t *dpcd
= intel_dp
->dpcd
;
4523 lspcon_resume(lspcon
);
4525 if (!intel_dp_get_dpcd(intel_dp
))
4526 return connector_status_disconnected
;
4528 if (intel_dp_is_edp(intel_dp
))
4529 return connector_status_connected
;
4531 /* if there's no downstream port, we're done */
4532 if (!drm_dp_is_branch(dpcd
))
4533 return connector_status_connected
;
4535 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4536 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4537 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4539 return intel_dp
->sink_count
?
4540 connector_status_connected
: connector_status_disconnected
;
4543 if (intel_dp_can_mst(intel_dp
))
4544 return connector_status_connected
;
4546 /* If no HPD, poke DDC gently */
4547 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4548 return connector_status_connected
;
4550 /* Well we tried, say unknown for unreliable port types */
4551 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4552 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4553 if (type
== DP_DS_PORT_TYPE_VGA
||
4554 type
== DP_DS_PORT_TYPE_NON_EDID
)
4555 return connector_status_unknown
;
4557 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4558 DP_DWN_STRM_PORT_TYPE_MASK
;
4559 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4560 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4561 return connector_status_unknown
;
4564 /* Anything else is out of spec, warn and ignore */
4565 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4566 return connector_status_disconnected
;
4569 static enum drm_connector_status
4570 edp_detect(struct intel_dp
*intel_dp
)
4572 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4573 enum drm_connector_status status
;
4575 status
= intel_panel_detect(dev_priv
);
4576 if (status
== connector_status_unknown
)
4577 status
= connector_status_connected
;
4582 static bool ibx_digital_port_connected(struct intel_encoder
*encoder
)
4584 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4587 switch (encoder
->hpd_pin
) {
4589 bit
= SDE_PORTB_HOTPLUG
;
4592 bit
= SDE_PORTC_HOTPLUG
;
4595 bit
= SDE_PORTD_HOTPLUG
;
4598 MISSING_CASE(encoder
->hpd_pin
);
4602 return I915_READ(SDEISR
) & bit
;
4605 static bool cpt_digital_port_connected(struct intel_encoder
*encoder
)
4607 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4610 switch (encoder
->hpd_pin
) {
4612 bit
= SDE_PORTB_HOTPLUG_CPT
;
4615 bit
= SDE_PORTC_HOTPLUG_CPT
;
4618 bit
= SDE_PORTD_HOTPLUG_CPT
;
4621 MISSING_CASE(encoder
->hpd_pin
);
4625 return I915_READ(SDEISR
) & bit
;
4628 static bool spt_digital_port_connected(struct intel_encoder
*encoder
)
4630 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4633 switch (encoder
->hpd_pin
) {
4635 bit
= SDE_PORTA_HOTPLUG_SPT
;
4638 bit
= SDE_PORTE_HOTPLUG_SPT
;
4641 return cpt_digital_port_connected(encoder
);
4644 return I915_READ(SDEISR
) & bit
;
4647 static bool g4x_digital_port_connected(struct intel_encoder
*encoder
)
4649 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4652 switch (encoder
->hpd_pin
) {
4654 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4657 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4660 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4663 MISSING_CASE(encoder
->hpd_pin
);
4667 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4670 static bool gm45_digital_port_connected(struct intel_encoder
*encoder
)
4672 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4675 switch (encoder
->hpd_pin
) {
4677 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4680 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4683 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4686 MISSING_CASE(encoder
->hpd_pin
);
4690 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4693 static bool ilk_digital_port_connected(struct intel_encoder
*encoder
)
4695 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4697 if (encoder
->hpd_pin
== HPD_PORT_A
)
4698 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4700 return ibx_digital_port_connected(encoder
);
4703 static bool snb_digital_port_connected(struct intel_encoder
*encoder
)
4705 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4707 if (encoder
->hpd_pin
== HPD_PORT_A
)
4708 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4710 return cpt_digital_port_connected(encoder
);
4713 static bool ivb_digital_port_connected(struct intel_encoder
*encoder
)
4715 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4717 if (encoder
->hpd_pin
== HPD_PORT_A
)
4718 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
4720 return cpt_digital_port_connected(encoder
);
4723 static bool bdw_digital_port_connected(struct intel_encoder
*encoder
)
4725 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4727 if (encoder
->hpd_pin
== HPD_PORT_A
)
4728 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
4730 return cpt_digital_port_connected(encoder
);
4733 static bool bxt_digital_port_connected(struct intel_encoder
*encoder
)
4735 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4738 switch (encoder
->hpd_pin
) {
4740 bit
= BXT_DE_PORT_HP_DDIA
;
4743 bit
= BXT_DE_PORT_HP_DDIB
;
4746 bit
= BXT_DE_PORT_HP_DDIC
;
4749 MISSING_CASE(encoder
->hpd_pin
);
4753 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4757 * intel_digital_port_connected - is the specified port connected?
4758 * @encoder: intel_encoder
4760 * Return %true if port is connected, %false otherwise.
4762 bool intel_digital_port_connected(struct intel_encoder
*encoder
)
4764 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4766 if (HAS_GMCH_DISPLAY(dev_priv
)) {
4767 if (IS_GM45(dev_priv
))
4768 return gm45_digital_port_connected(encoder
);
4770 return g4x_digital_port_connected(encoder
);
4773 if (IS_GEN5(dev_priv
))
4774 return ilk_digital_port_connected(encoder
);
4775 else if (IS_GEN6(dev_priv
))
4776 return snb_digital_port_connected(encoder
);
4777 else if (IS_GEN7(dev_priv
))
4778 return ivb_digital_port_connected(encoder
);
4779 else if (IS_GEN8(dev_priv
))
4780 return bdw_digital_port_connected(encoder
);
4781 else if (IS_GEN9_LP(dev_priv
))
4782 return bxt_digital_port_connected(encoder
);
4784 return spt_digital_port_connected(encoder
);
4787 static struct edid
*
4788 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4790 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4792 /* use cached edid if we have one */
4793 if (intel_connector
->edid
) {
4795 if (IS_ERR(intel_connector
->edid
))
4798 return drm_edid_duplicate(intel_connector
->edid
);
4800 return drm_get_edid(&intel_connector
->base
,
4801 &intel_dp
->aux
.ddc
);
4805 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4807 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4810 intel_dp_unset_edid(intel_dp
);
4811 edid
= intel_dp_get_edid(intel_dp
);
4812 intel_connector
->detect_edid
= edid
;
4814 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4815 drm_dp_cec_set_edid(&intel_dp
->aux
, edid
);
4819 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4821 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4823 drm_dp_cec_unset_edid(&intel_dp
->aux
);
4824 kfree(intel_connector
->detect_edid
);
4825 intel_connector
->detect_edid
= NULL
;
4827 intel_dp
->has_audio
= false;
4831 intel_dp_long_pulse(struct intel_connector
*connector
)
4833 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
4834 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
4835 enum drm_connector_status status
;
4836 u8 sink_irq_vector
= 0;
4838 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
4840 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4842 /* Can't disconnect eDP, but you can close the lid... */
4843 if (intel_dp_is_edp(intel_dp
))
4844 status
= edp_detect(intel_dp
);
4845 else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp
)->base
))
4846 status
= intel_dp_detect_dpcd(intel_dp
);
4848 status
= connector_status_disconnected
;
4850 if (status
== connector_status_disconnected
) {
4851 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4853 if (intel_dp
->is_mst
) {
4854 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4856 intel_dp
->mst_mgr
.mst_state
);
4857 intel_dp
->is_mst
= false;
4858 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4865 if (intel_dp
->reset_link_params
) {
4866 /* Initial max link lane count */
4867 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
4869 /* Initial max link rate */
4870 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
4872 intel_dp
->reset_link_params
= false;
4875 intel_dp_print_rates(intel_dp
);
4877 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4878 drm_dp_is_branch(intel_dp
->dpcd
));
4880 intel_dp_configure_mst(intel_dp
);
4882 if (intel_dp
->is_mst
) {
4884 * If we are in MST mode then this connector
4885 * won't appear connected or have anything
4888 status
= connector_status_disconnected
;
4893 * Clearing NACK and defer counts to get their exact values
4894 * while reading EDID which are required by Compliance tests
4895 * 4.2.2.4 and 4.2.2.5
4897 intel_dp
->aux
.i2c_nack_count
= 0;
4898 intel_dp
->aux
.i2c_defer_count
= 0;
4900 intel_dp_set_edid(intel_dp
);
4901 if (intel_dp_is_edp(intel_dp
) || connector
->detect_edid
)
4902 status
= connector_status_connected
;
4903 intel_dp
->detect_done
= true;
4905 /* Try to read the source of the interrupt */
4906 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4907 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4908 sink_irq_vector
!= 0) {
4909 /* Clear interrupt source */
4910 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4911 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4914 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4915 intel_dp_handle_test_request(intel_dp
);
4916 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4917 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4921 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4922 intel_dp_unset_edid(intel_dp
);
4924 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4929 intel_dp_detect(struct drm_connector
*connector
,
4930 struct drm_modeset_acquire_ctx
*ctx
,
4933 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4934 int status
= connector
->status
;
4936 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4937 connector
->base
.id
, connector
->name
);
4939 /* If full detect is not performed yet, do a full detect */
4940 if (!intel_dp
->detect_done
) {
4941 struct drm_crtc
*crtc
;
4944 crtc
= connector
->state
->crtc
;
4946 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
4951 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4954 intel_dp
->detect_done
= false;
4960 intel_dp_force(struct drm_connector
*connector
)
4962 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4963 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4964 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4966 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4967 connector
->base
.id
, connector
->name
);
4968 intel_dp_unset_edid(intel_dp
);
4970 if (connector
->status
!= connector_status_connected
)
4973 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4975 intel_dp_set_edid(intel_dp
);
4977 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4980 static int intel_dp_get_modes(struct drm_connector
*connector
)
4982 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4985 edid
= intel_connector
->detect_edid
;
4987 int ret
= intel_connector_update_modes(connector
, edid
);
4992 /* if eDP has no EDID, fall back to fixed mode */
4993 if (intel_dp_is_edp(intel_attached_dp(connector
)) &&
4994 intel_connector
->panel
.fixed_mode
) {
4995 struct drm_display_mode
*mode
;
4997 mode
= drm_mode_duplicate(connector
->dev
,
4998 intel_connector
->panel
.fixed_mode
);
5000 drm_mode_probed_add(connector
, mode
);
5009 intel_dp_connector_register(struct drm_connector
*connector
)
5011 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5012 struct drm_device
*dev
= connector
->dev
;
5015 ret
= intel_connector_register(connector
);
5019 i915_debugfs_connector_add(connector
);
5021 DRM_DEBUG_KMS("registering %s bus for %s\n",
5022 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
5024 intel_dp
->aux
.dev
= connector
->kdev
;
5025 ret
= drm_dp_aux_register(&intel_dp
->aux
);
5027 drm_dp_cec_register_connector(&intel_dp
->aux
,
5028 connector
->name
, dev
->dev
);
5033 intel_dp_connector_unregister(struct drm_connector
*connector
)
5035 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5037 drm_dp_cec_unregister_connector(&intel_dp
->aux
);
5038 drm_dp_aux_unregister(&intel_dp
->aux
);
5039 intel_connector_unregister(connector
);
5043 intel_dp_connector_destroy(struct drm_connector
*connector
)
5045 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5047 kfree(intel_connector
->detect_edid
);
5049 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
5050 kfree(intel_connector
->edid
);
5053 * Can't call intel_dp_is_edp() since the encoder may have been
5054 * destroyed already.
5056 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5057 intel_panel_fini(&intel_connector
->panel
);
5059 drm_connector_cleanup(connector
);
5063 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
5065 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
5066 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5068 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5069 if (intel_dp_is_edp(intel_dp
)) {
5070 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5072 * vdd might still be enabled do to the delayed vdd off.
5073 * Make sure vdd is actually turned off here.
5076 edp_panel_vdd_off_sync(intel_dp
);
5077 pps_unlock(intel_dp
);
5079 if (intel_dp
->edp_notifier
.notifier_call
) {
5080 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
5081 intel_dp
->edp_notifier
.notifier_call
= NULL
;
5085 intel_dp_aux_fini(intel_dp
);
5087 drm_encoder_cleanup(encoder
);
5088 kfree(intel_dig_port
);
5091 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
5093 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5095 if (!intel_dp_is_edp(intel_dp
))
5099 * vdd might still be enabled do to the delayed vdd off.
5100 * Make sure vdd is actually turned off here.
5102 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5104 edp_panel_vdd_off_sync(intel_dp
);
5105 pps_unlock(intel_dp
);
5109 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port
,
5112 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_dig_port
->base
.base
);
5113 static const struct drm_dp_aux_msg msg
= {
5114 .request
= DP_AUX_NATIVE_WRITE
,
5115 .address
= DP_AUX_HDCP_AKSV
,
5116 .size
= DRM_HDCP_KSV_LEN
,
5118 uint8_t txbuf
[HEADER_SIZE
+ DRM_HDCP_KSV_LEN
] = {}, rxbuf
[2], reply
= 0;
5122 /* Output An first, that's easy */
5123 dpcd_ret
= drm_dp_dpcd_write(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_AN
,
5124 an
, DRM_HDCP_AN_LEN
);
5125 if (dpcd_ret
!= DRM_HDCP_AN_LEN
) {
5126 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret
);
5127 return dpcd_ret
>= 0 ? -EIO
: dpcd_ret
;
5131 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5132 * order to get it on the wire, we need to create the AUX header as if
5133 * we were writing the data, and then tickle the hardware to output the
5134 * data once the header is sent out.
5136 intel_dp_aux_header(txbuf
, &msg
);
5138 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, HEADER_SIZE
+ msg
.size
,
5139 rxbuf
, sizeof(rxbuf
),
5140 DP_AUX_CH_CTL_AUX_AKSV_SELECT
);
5142 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret
);
5144 } else if (ret
== 0) {
5145 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5149 reply
= (rxbuf
[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK
;
5150 return reply
== DP_AUX_NATIVE_REPLY_ACK
? 0 : -EIO
;
5153 static int intel_dp_hdcp_read_bksv(struct intel_digital_port
*intel_dig_port
,
5157 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BKSV
, bksv
,
5159 if (ret
!= DRM_HDCP_KSV_LEN
) {
5160 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret
);
5161 return ret
>= 0 ? -EIO
: ret
;
5166 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port
,
5171 * For some reason the HDMI and DP HDCP specs call this register
5172 * definition by different names. In the HDMI spec, it's called BSTATUS,
5173 * but in DP it's called BINFO.
5175 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BINFO
,
5176 bstatus
, DRM_HDCP_BSTATUS_LEN
);
5177 if (ret
!= DRM_HDCP_BSTATUS_LEN
) {
5178 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5179 return ret
>= 0 ? -EIO
: ret
;
5185 int intel_dp_hdcp_read_bcaps(struct intel_digital_port
*intel_dig_port
,
5190 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BCAPS
,
5193 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret
);
5194 return ret
>= 0 ? -EIO
: ret
;
5201 int intel_dp_hdcp_repeater_present(struct intel_digital_port
*intel_dig_port
,
5202 bool *repeater_present
)
5207 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5211 *repeater_present
= bcaps
& DP_BCAPS_REPEATER_PRESENT
;
5216 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port
*intel_dig_port
,
5220 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_RI_PRIME
,
5221 ri_prime
, DRM_HDCP_RI_LEN
);
5222 if (ret
!= DRM_HDCP_RI_LEN
) {
5223 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret
);
5224 return ret
>= 0 ? -EIO
: ret
;
5230 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port
*intel_dig_port
,
5235 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5238 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5239 return ret
>= 0 ? -EIO
: ret
;
5241 *ksv_ready
= bstatus
& DP_BSTATUS_READY
;
5246 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port
*intel_dig_port
,
5247 int num_downstream
, u8
*ksv_fifo
)
5252 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5253 for (i
= 0; i
< num_downstream
; i
+= 3) {
5254 size_t len
= min(num_downstream
- i
, 3) * DRM_HDCP_KSV_LEN
;
5255 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5256 DP_AUX_HDCP_KSV_FIFO
,
5257 ksv_fifo
+ i
* DRM_HDCP_KSV_LEN
,
5260 DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i
,
5262 return ret
>= 0 ? -EIO
: ret
;
5269 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port
*intel_dig_port
,
5274 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
5277 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5278 DP_AUX_HDCP_V_PRIME(i
), part
,
5279 DRM_HDCP_V_PRIME_PART_LEN
);
5280 if (ret
!= DRM_HDCP_V_PRIME_PART_LEN
) {
5281 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i
, ret
);
5282 return ret
>= 0 ? -EIO
: ret
;
5288 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port
*intel_dig_port
,
5291 /* Not used for single stream DisplayPort setups */
5296 bool intel_dp_hdcp_check_link(struct intel_digital_port
*intel_dig_port
)
5301 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5304 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5308 return !(bstatus
& (DP_BSTATUS_LINK_FAILURE
| DP_BSTATUS_REAUTH_REQ
));
5312 int intel_dp_hdcp_capable(struct intel_digital_port
*intel_dig_port
,
5318 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5322 *hdcp_capable
= bcaps
& DP_BCAPS_HDCP_CAPABLE
;
5326 static const struct intel_hdcp_shim intel_dp_hdcp_shim
= {
5327 .write_an_aksv
= intel_dp_hdcp_write_an_aksv
,
5328 .read_bksv
= intel_dp_hdcp_read_bksv
,
5329 .read_bstatus
= intel_dp_hdcp_read_bstatus
,
5330 .repeater_present
= intel_dp_hdcp_repeater_present
,
5331 .read_ri_prime
= intel_dp_hdcp_read_ri_prime
,
5332 .read_ksv_ready
= intel_dp_hdcp_read_ksv_ready
,
5333 .read_ksv_fifo
= intel_dp_hdcp_read_ksv_fifo
,
5334 .read_v_prime_part
= intel_dp_hdcp_read_v_prime_part
,
5335 .toggle_signalling
= intel_dp_hdcp_toggle_signalling
,
5336 .check_link
= intel_dp_hdcp_check_link
,
5337 .hdcp_capable
= intel_dp_hdcp_capable
,
5340 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
5342 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5344 lockdep_assert_held(&dev_priv
->pps_mutex
);
5346 if (!edp_have_panel_vdd(intel_dp
))
5350 * The VDD bit needs a power domain reference, so if the bit is
5351 * already enabled when we boot or resume, grab this reference and
5352 * schedule a vdd off, so we don't hold on to the reference
5355 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5356 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5358 edp_panel_vdd_schedule_off(intel_dp
);
5361 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
5363 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5364 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
5367 if (intel_dp_port_enabled(dev_priv
, intel_dp
->output_reg
,
5368 encoder
->port
, &pipe
))
5371 return INVALID_PIPE
;
5374 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
5376 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
5377 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
5378 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
5380 if (!HAS_DDI(dev_priv
))
5381 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5384 lspcon_resume(lspcon
);
5386 intel_dp
->reset_link_params
= true;
5390 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5391 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5393 if (intel_dp_is_edp(intel_dp
)) {
5394 /* Reinit the power sequencer, in case BIOS did something with it. */
5395 intel_dp_pps_init(intel_dp
);
5396 intel_edp_panel_vdd_sanitize(intel_dp
);
5399 pps_unlock(intel_dp
);
5402 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5403 .force
= intel_dp_force
,
5404 .fill_modes
= drm_helper_probe_single_connector_modes
,
5405 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
5406 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
5407 .late_register
= intel_dp_connector_register
,
5408 .early_unregister
= intel_dp_connector_unregister
,
5409 .destroy
= intel_dp_connector_destroy
,
5410 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5411 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5414 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5415 .detect_ctx
= intel_dp_detect
,
5416 .get_modes
= intel_dp_get_modes
,
5417 .mode_valid
= intel_dp_mode_valid
,
5418 .atomic_check
= intel_digital_connector_atomic_check
,
5421 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5422 .reset
= intel_dp_encoder_reset
,
5423 .destroy
= intel_dp_encoder_destroy
,
5427 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5429 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5430 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5431 enum irqreturn ret
= IRQ_NONE
;
5433 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5435 * vdd off can generate a long pulse on eDP which
5436 * would require vdd on to handle it, and thus we
5437 * would end up in an endless cycle of
5438 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5440 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5441 port_name(intel_dig_port
->base
.port
));
5445 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5446 port_name(intel_dig_port
->base
.port
),
5447 long_hpd
? "long" : "short");
5450 intel_dp
->reset_link_params
= true;
5451 intel_dp
->detect_done
= false;
5455 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5457 if (intel_dp
->is_mst
) {
5458 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5460 * If we were in MST mode, and device is not
5461 * there, get out of MST mode
5463 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5464 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5465 intel_dp
->is_mst
= false;
5466 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5468 intel_dp
->detect_done
= false;
5473 if (!intel_dp
->is_mst
) {
5476 handled
= intel_dp_short_pulse(intel_dp
);
5478 /* Short pulse can signify loss of hdcp authentication */
5479 intel_hdcp_check_link(intel_dp
->attached_connector
);
5482 intel_dp
->detect_done
= false;
5490 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5495 /* check the VBT to see whether the eDP is on another port */
5496 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5499 * eDP not supported on g4x. so bail out early just
5500 * for a bit extra safety in case the VBT is bonkers.
5502 if (INTEL_GEN(dev_priv
) < 5)
5505 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5508 return intel_bios_is_port_edp(dev_priv
, port
);
5512 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5514 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5515 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5517 if (!IS_G4X(dev_priv
) && port
!= PORT_A
)
5518 intel_attach_force_audio_property(connector
);
5520 intel_attach_broadcast_rgb_property(connector
);
5522 if (intel_dp_is_edp(intel_dp
)) {
5523 u32 allowed_scalers
;
5525 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
5526 if (!HAS_GMCH_DISPLAY(dev_priv
))
5527 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
5529 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
5531 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
5536 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5538 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5539 intel_dp
->last_power_on
= jiffies
;
5540 intel_dp
->last_backlight_off
= jiffies
;
5544 intel_pps_readout_hw_state(struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5546 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5547 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5548 struct pps_registers regs
;
5550 intel_pps_get_registers(intel_dp
, ®s
);
5552 /* Workaround: Need to write PP_CONTROL with the unlock key as
5553 * the very first thing. */
5554 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5556 pp_on
= I915_READ(regs
.pp_on
);
5557 pp_off
= I915_READ(regs
.pp_off
);
5558 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
5559 !HAS_PCH_ICP(dev_priv
)) {
5560 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5561 pp_div
= I915_READ(regs
.pp_div
);
5564 /* Pull timing values out of registers */
5565 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5566 PANEL_POWER_UP_DELAY_SHIFT
;
5568 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5569 PANEL_LIGHT_ON_DELAY_SHIFT
;
5571 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5572 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5574 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5575 PANEL_POWER_DOWN_DELAY_SHIFT
;
5577 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5578 HAS_PCH_ICP(dev_priv
)) {
5579 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5580 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5582 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5583 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5588 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5590 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5592 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5596 intel_pps_verify_state(struct intel_dp
*intel_dp
)
5598 struct edp_power_seq hw
;
5599 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5601 intel_pps_readout_hw_state(intel_dp
, &hw
);
5603 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5604 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5605 DRM_ERROR("PPS state mismatch\n");
5606 intel_pps_dump_state("sw", sw
);
5607 intel_pps_dump_state("hw", &hw
);
5612 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
5614 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5615 struct edp_power_seq cur
, vbt
, spec
,
5616 *final
= &intel_dp
->pps_delays
;
5618 lockdep_assert_held(&dev_priv
->pps_mutex
);
5620 /* already initialized? */
5621 if (final
->t11_t12
!= 0)
5624 intel_pps_readout_hw_state(intel_dp
, &cur
);
5626 intel_pps_dump_state("cur", &cur
);
5628 vbt
= dev_priv
->vbt
.edp
.pps
;
5629 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5630 * of 500ms appears to be too short. Ocassionally the panel
5631 * just fails to power back on. Increasing the delay to 800ms
5632 * seems sufficient to avoid this problem.
5634 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
5635 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 1300 * 10);
5636 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5639 /* T11_T12 delay is special and actually in units of 100ms, but zero
5640 * based in the hw (so we need to add 100 ms). But the sw vbt
5641 * table multiplies it with 1000 to make it in units of 100usec,
5643 vbt
.t11_t12
+= 100 * 10;
5645 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5646 * our hw here, which are all in 100usec. */
5647 spec
.t1_t3
= 210 * 10;
5648 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5649 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5650 spec
.t10
= 500 * 10;
5651 /* This one is special and actually in units of 100ms, but zero
5652 * based in the hw (so we need to add 100 ms). But the sw vbt
5653 * table multiplies it with 1000 to make it in units of 100usec,
5655 spec
.t11_t12
= (510 + 100) * 10;
5657 intel_pps_dump_state("vbt", &vbt
);
5659 /* Use the max of the register settings and vbt. If both are
5660 * unset, fall back to the spec limits. */
5661 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5663 max(cur.field, vbt.field))
5664 assign_final(t1_t3
);
5668 assign_final(t11_t12
);
5671 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5672 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5673 intel_dp
->backlight_on_delay
= get_delay(t8
);
5674 intel_dp
->backlight_off_delay
= get_delay(t9
);
5675 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5676 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5679 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5680 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5681 intel_dp
->panel_power_cycle_delay
);
5683 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5684 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5687 * We override the HW backlight delays to 1 because we do manual waits
5688 * on them. For T8, even BSpec recommends doing it. For T9, if we
5689 * don't do this, we'll end up waiting for the backlight off delay
5690 * twice: once when we do the manual sleep, and once when we disable
5691 * the panel and wait for the PP_STATUS bit to become zero.
5697 * HW has only a 100msec granularity for t11_t12 so round it up
5700 final
->t11_t12
= roundup(final
->t11_t12
, 100 * 10);
5704 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
5705 bool force_disable_vdd
)
5707 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5708 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5709 int div
= dev_priv
->rawclk_freq
/ 1000;
5710 struct pps_registers regs
;
5711 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5712 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5714 lockdep_assert_held(&dev_priv
->pps_mutex
);
5716 intel_pps_get_registers(intel_dp
, ®s
);
5719 * On some VLV machines the BIOS can leave the VDD
5720 * enabled even on power sequencers which aren't
5721 * hooked up to any port. This would mess up the
5722 * power domain tracking the first time we pick
5723 * one of these power sequencers for use since
5724 * edp_panel_vdd_on() would notice that the VDD was
5725 * already on and therefore wouldn't grab the power
5726 * domain reference. Disable VDD first to avoid this.
5727 * This also avoids spuriously turning the VDD on as
5728 * soon as the new power sequencer gets initialized.
5730 if (force_disable_vdd
) {
5731 u32 pp
= ironlake_get_pp_control(intel_dp
);
5733 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5735 if (pp
& EDP_FORCE_VDD
)
5736 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5738 pp
&= ~EDP_FORCE_VDD
;
5740 I915_WRITE(regs
.pp_ctrl
, pp
);
5743 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5744 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5745 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5746 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5747 /* Compute the divisor for the pp clock, simply match the Bspec
5749 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5750 HAS_PCH_ICP(dev_priv
)) {
5751 pp_div
= I915_READ(regs
.pp_ctrl
);
5752 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5753 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5754 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5756 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5757 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5758 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5761 /* Haswell doesn't have any port selection bits for the panel
5762 * power sequencer any more. */
5763 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5764 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5765 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5768 port_sel
= PANEL_PORT_SELECT_DPA
;
5771 port_sel
= PANEL_PORT_SELECT_DPC
;
5774 port_sel
= PANEL_PORT_SELECT_DPD
;
5784 I915_WRITE(regs
.pp_on
, pp_on
);
5785 I915_WRITE(regs
.pp_off
, pp_off
);
5786 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5787 HAS_PCH_ICP(dev_priv
))
5788 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5790 I915_WRITE(regs
.pp_div
, pp_div
);
5792 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5793 I915_READ(regs
.pp_on
),
5794 I915_READ(regs
.pp_off
),
5795 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5796 HAS_PCH_ICP(dev_priv
)) ?
5797 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5798 I915_READ(regs
.pp_div
));
5801 static void intel_dp_pps_init(struct intel_dp
*intel_dp
)
5803 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5805 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5806 vlv_initial_power_sequencer_setup(intel_dp
);
5808 intel_dp_init_panel_power_sequencer(intel_dp
);
5809 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
5814 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5815 * @dev_priv: i915 device
5816 * @crtc_state: a pointer to the active intel_crtc_state
5817 * @refresh_rate: RR to be programmed
5819 * This function gets called when refresh rate (RR) has to be changed from
5820 * one frequency to another. Switches can be between high and low RR
5821 * supported by the panel or to any other RR based on media playback (in
5822 * this case, RR value needs to be passed from user space).
5824 * The caller of this function needs to take a lock on dev_priv->drrs.
5826 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5827 const struct intel_crtc_state
*crtc_state
,
5830 struct intel_encoder
*encoder
;
5831 struct intel_digital_port
*dig_port
= NULL
;
5832 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5833 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5834 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5836 if (refresh_rate
<= 0) {
5837 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5841 if (intel_dp
== NULL
) {
5842 DRM_DEBUG_KMS("DRRS not supported.\n");
5846 dig_port
= dp_to_dig_port(intel_dp
);
5847 encoder
= &dig_port
->base
;
5850 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5854 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5855 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5859 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5861 index
= DRRS_LOW_RR
;
5863 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5865 "DRRS requested for previously set RR...ignoring\n");
5869 if (!crtc_state
->base
.active
) {
5870 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5874 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5877 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5880 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5884 DRM_ERROR("Unsupported refreshrate type\n");
5886 } else if (INTEL_GEN(dev_priv
) > 6) {
5887 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5890 val
= I915_READ(reg
);
5891 if (index
> DRRS_HIGH_RR
) {
5892 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5893 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5895 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5897 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5898 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5900 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5902 I915_WRITE(reg
, val
);
5905 dev_priv
->drrs
.refresh_rate_type
= index
;
5907 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5911 * intel_edp_drrs_enable - init drrs struct if supported
5912 * @intel_dp: DP struct
5913 * @crtc_state: A pointer to the active crtc state.
5915 * Initializes frontbuffer_bits and drrs.dp
5917 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5918 const struct intel_crtc_state
*crtc_state
)
5920 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5922 if (!crtc_state
->has_drrs
) {
5923 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5927 if (dev_priv
->psr
.enabled
) {
5928 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5932 mutex_lock(&dev_priv
->drrs
.mutex
);
5933 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5934 DRM_ERROR("DRRS already enabled\n");
5938 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5940 dev_priv
->drrs
.dp
= intel_dp
;
5943 mutex_unlock(&dev_priv
->drrs
.mutex
);
5947 * intel_edp_drrs_disable - Disable DRRS
5948 * @intel_dp: DP struct
5949 * @old_crtc_state: Pointer to old crtc_state.
5952 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5953 const struct intel_crtc_state
*old_crtc_state
)
5955 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5957 if (!old_crtc_state
->has_drrs
)
5960 mutex_lock(&dev_priv
->drrs
.mutex
);
5961 if (!dev_priv
->drrs
.dp
) {
5962 mutex_unlock(&dev_priv
->drrs
.mutex
);
5966 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5967 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5968 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5970 dev_priv
->drrs
.dp
= NULL
;
5971 mutex_unlock(&dev_priv
->drrs
.mutex
);
5973 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5976 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5978 struct drm_i915_private
*dev_priv
=
5979 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5980 struct intel_dp
*intel_dp
;
5982 mutex_lock(&dev_priv
->drrs
.mutex
);
5984 intel_dp
= dev_priv
->drrs
.dp
;
5990 * The delayed work can race with an invalidate hence we need to
5994 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5997 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5998 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
6000 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6001 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
6005 mutex_unlock(&dev_priv
->drrs
.mutex
);
6009 * intel_edp_drrs_invalidate - Disable Idleness DRRS
6010 * @dev_priv: i915 device
6011 * @frontbuffer_bits: frontbuffer plane tracking bits
6013 * This function gets called everytime rendering on the given planes start.
6014 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6016 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6018 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
6019 unsigned int frontbuffer_bits
)
6021 struct drm_crtc
*crtc
;
6024 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
6027 cancel_delayed_work(&dev_priv
->drrs
.work
);
6029 mutex_lock(&dev_priv
->drrs
.mutex
);
6030 if (!dev_priv
->drrs
.dp
) {
6031 mutex_unlock(&dev_priv
->drrs
.mutex
);
6035 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6036 pipe
= to_intel_crtc(crtc
)->pipe
;
6038 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6039 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
6041 /* invalidate means busy screen hence upclock */
6042 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6043 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6044 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6046 mutex_unlock(&dev_priv
->drrs
.mutex
);
6050 * intel_edp_drrs_flush - Restart Idleness DRRS
6051 * @dev_priv: i915 device
6052 * @frontbuffer_bits: frontbuffer plane tracking bits
6054 * This function gets called every time rendering on the given planes has
6055 * completed or flip on a crtc is completed. So DRRS should be upclocked
6056 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6057 * if no other planes are dirty.
6059 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6061 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
6062 unsigned int frontbuffer_bits
)
6064 struct drm_crtc
*crtc
;
6067 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
6070 cancel_delayed_work(&dev_priv
->drrs
.work
);
6072 mutex_lock(&dev_priv
->drrs
.mutex
);
6073 if (!dev_priv
->drrs
.dp
) {
6074 mutex_unlock(&dev_priv
->drrs
.mutex
);
6078 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6079 pipe
= to_intel_crtc(crtc
)->pipe
;
6081 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6082 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
6084 /* flush means busy screen hence upclock */
6085 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6086 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6087 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6090 * flush also means no more activity hence schedule downclock, if all
6091 * other fbs are quiescent too
6093 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
6094 schedule_delayed_work(&dev_priv
->drrs
.work
,
6095 msecs_to_jiffies(1000));
6096 mutex_unlock(&dev_priv
->drrs
.mutex
);
6100 * DOC: Display Refresh Rate Switching (DRRS)
6102 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6103 * which enables swtching between low and high refresh rates,
6104 * dynamically, based on the usage scenario. This feature is applicable
6105 * for internal panels.
6107 * Indication that the panel supports DRRS is given by the panel EDID, which
6108 * would list multiple refresh rates for one resolution.
6110 * DRRS is of 2 types - static and seamless.
6111 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6112 * (may appear as a blink on screen) and is used in dock-undock scenario.
6113 * Seamless DRRS involves changing RR without any visual effect to the user
6114 * and can be used during normal system usage. This is done by programming
6115 * certain registers.
6117 * Support for static/seamless DRRS may be indicated in the VBT based on
6118 * inputs from the panel spec.
6120 * DRRS saves power by switching to low RR based on usage scenarios.
6122 * The implementation is based on frontbuffer tracking implementation. When
6123 * there is a disturbance on the screen triggered by user activity or a periodic
6124 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6125 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6128 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6129 * and intel_edp_drrs_flush() are called.
6131 * DRRS can be further extended to support other internal panels and also
6132 * the scenario of video playback wherein RR is set based on the rate
6133 * requested by userspace.
6137 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6138 * @connector: eDP connector
6139 * @fixed_mode: preferred mode of panel
6141 * This function is called only once at driver load to initialize basic
6145 * Downclock mode if panel supports it, else return NULL.
6146 * DRRS support is determined by the presence of downclock mode (apart
6147 * from VBT setting).
6149 static struct drm_display_mode
*
6150 intel_dp_drrs_init(struct intel_connector
*connector
,
6151 struct drm_display_mode
*fixed_mode
)
6153 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
6154 struct drm_display_mode
*downclock_mode
= NULL
;
6156 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
6157 mutex_init(&dev_priv
->drrs
.mutex
);
6159 if (INTEL_GEN(dev_priv
) <= 6) {
6160 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6164 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
6165 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6169 downclock_mode
= intel_find_panel_downclock(dev_priv
, fixed_mode
,
6172 if (!downclock_mode
) {
6173 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6177 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
6179 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
6180 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6181 return downclock_mode
;
6184 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
6185 struct intel_connector
*intel_connector
)
6187 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
6188 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6189 struct drm_connector
*connector
= &intel_connector
->base
;
6190 struct drm_display_mode
*fixed_mode
= NULL
;
6191 struct drm_display_mode
*downclock_mode
= NULL
;
6193 struct drm_display_mode
*scan
;
6195 enum pipe pipe
= INVALID_PIPE
;
6197 if (!intel_dp_is_edp(intel_dp
))
6201 * On IBX/CPT we may get here with LVDS already registered. Since the
6202 * driver uses the only internal power sequencer available for both
6203 * eDP and LVDS bail out early in this case to prevent interfering
6204 * with an already powered-on LVDS power sequencer.
6206 if (intel_get_lvds_encoder(&dev_priv
->drm
)) {
6207 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
6208 DRM_INFO("LVDS was detected, not registering eDP\n");
6215 intel_dp_init_panel_power_timestamps(intel_dp
);
6216 intel_dp_pps_init(intel_dp
);
6217 intel_edp_panel_vdd_sanitize(intel_dp
);
6219 pps_unlock(intel_dp
);
6221 /* Cache DPCD and EDID for edp. */
6222 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
6225 /* if this fails, presume the device is a ghost */
6226 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6230 mutex_lock(&dev
->mode_config
.mutex
);
6231 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
6233 if (drm_add_edid_modes(connector
, edid
)) {
6234 drm_connector_update_edid_property(connector
,
6238 edid
= ERR_PTR(-EINVAL
);
6241 edid
= ERR_PTR(-ENOENT
);
6243 intel_connector
->edid
= edid
;
6245 /* prefer fixed mode from EDID if available */
6246 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
6247 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
6248 fixed_mode
= drm_mode_duplicate(dev
, scan
);
6249 downclock_mode
= intel_dp_drrs_init(
6250 intel_connector
, fixed_mode
);
6255 /* fallback to VBT if available for eDP */
6256 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
6257 fixed_mode
= drm_mode_duplicate(dev
,
6258 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
6260 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
6261 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
6262 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
6265 mutex_unlock(&dev
->mode_config
.mutex
);
6267 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6268 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
6269 register_reboot_notifier(&intel_dp
->edp_notifier
);
6272 * Figure out the current pipe for the initial backlight setup.
6273 * If the current pipe isn't valid, try the PPS pipe, and if that
6274 * fails just assume pipe A.
6276 pipe
= vlv_active_pipe(intel_dp
);
6278 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6279 pipe
= intel_dp
->pps_pipe
;
6281 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6284 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6288 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
6289 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
6290 intel_panel_setup_backlight(connector
, pipe
);
6295 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
6297 * vdd might still be enabled do to the delayed vdd off.
6298 * Make sure vdd is actually turned off here.
6301 edp_panel_vdd_off_sync(intel_dp
);
6302 pps_unlock(intel_dp
);
6307 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
6309 struct intel_connector
*intel_connector
;
6310 struct drm_connector
*connector
;
6312 intel_connector
= container_of(work
, typeof(*intel_connector
),
6313 modeset_retry_work
);
6314 connector
= &intel_connector
->base
;
6315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
6318 /* Grab the locks before changing connector property*/
6319 mutex_lock(&connector
->dev
->mode_config
.mutex
);
6320 /* Set connector link status to BAD and send a Uevent to notify
6321 * userspace to do a modeset.
6323 drm_mode_connector_set_link_status_property(connector
,
6324 DRM_MODE_LINK_STATUS_BAD
);
6325 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
6326 /* Send Hotplug uevent so userspace can reprobe */
6327 drm_kms_helper_hotplug_event(connector
->dev
);
6331 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
6332 struct intel_connector
*intel_connector
)
6334 struct drm_connector
*connector
= &intel_connector
->base
;
6335 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
6336 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
6337 struct drm_device
*dev
= intel_encoder
->base
.dev
;
6338 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6339 enum port port
= intel_encoder
->port
;
6342 /* Initialize the work for modeset in case of link train failure */
6343 INIT_WORK(&intel_connector
->modeset_retry_work
,
6344 intel_dp_modeset_retry_work_fn
);
6346 if (WARN(intel_dig_port
->max_lanes
< 1,
6347 "Not enough lanes (%d) for DP on port %c\n",
6348 intel_dig_port
->max_lanes
, port_name(port
)))
6351 intel_dp_set_source_rates(intel_dp
);
6353 intel_dp
->reset_link_params
= true;
6354 intel_dp
->pps_pipe
= INVALID_PIPE
;
6355 intel_dp
->active_pipe
= INVALID_PIPE
;
6357 /* intel_dp vfuncs */
6358 if (HAS_DDI(dev_priv
))
6359 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6361 /* Preserve the current hw state. */
6362 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6363 intel_dp
->attached_connector
= intel_connector
;
6365 if (intel_dp_is_port_edp(dev_priv
, port
))
6366 type
= DRM_MODE_CONNECTOR_eDP
;
6368 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6370 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6371 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6374 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6375 * for DP the encoder type can be set by the caller to
6376 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6378 if (type
== DRM_MODE_CONNECTOR_eDP
)
6379 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6381 /* eDP only on port B and/or C on vlv/chv */
6382 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6383 intel_dp_is_edp(intel_dp
) &&
6384 port
!= PORT_B
&& port
!= PORT_C
))
6387 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6388 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6391 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6392 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6394 if (!HAS_GMCH_DISPLAY(dev_priv
))
6395 connector
->interlace_allowed
= true;
6396 connector
->doublescan_allowed
= 0;
6398 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
6400 intel_dp_aux_init(intel_dp
);
6402 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6403 edp_panel_vdd_work
);
6405 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6407 if (HAS_DDI(dev_priv
))
6408 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6410 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6412 /* init MST on ports that can support it */
6413 if (HAS_DP_MST(dev_priv
) && !intel_dp_is_edp(intel_dp
) &&
6414 (port
== PORT_B
|| port
== PORT_C
||
6415 port
== PORT_D
|| port
== PORT_F
))
6416 intel_dp_mst_encoder_init(intel_dig_port
,
6417 intel_connector
->base
.base
.id
);
6419 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6420 intel_dp_aux_fini(intel_dp
);
6421 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6425 intel_dp_add_properties(intel_dp
, connector
);
6427 if (is_hdcp_supported(dev_priv
, port
) && !intel_dp_is_edp(intel_dp
)) {
6428 int ret
= intel_hdcp_init(intel_connector
, &intel_dp_hdcp_shim
);
6430 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6433 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6434 * 0xd. Failure to do so will result in spurious interrupts being
6435 * generated on the port when a cable is not attached.
6437 if (IS_G45(dev_priv
)) {
6438 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6439 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6445 drm_connector_cleanup(connector
);
6450 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6451 i915_reg_t output_reg
,
6454 struct intel_digital_port
*intel_dig_port
;
6455 struct intel_encoder
*intel_encoder
;
6456 struct drm_encoder
*encoder
;
6457 struct intel_connector
*intel_connector
;
6459 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6460 if (!intel_dig_port
)
6463 intel_connector
= intel_connector_alloc();
6464 if (!intel_connector
)
6465 goto err_connector_alloc
;
6467 intel_encoder
= &intel_dig_port
->base
;
6468 encoder
= &intel_encoder
->base
;
6470 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6471 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6472 "DP %c", port_name(port
)))
6473 goto err_encoder_init
;
6475 intel_encoder
->hotplug
= intel_dp_hotplug
;
6476 intel_encoder
->compute_config
= intel_dp_compute_config
;
6477 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6478 intel_encoder
->get_config
= intel_dp_get_config
;
6479 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6480 if (IS_CHERRYVIEW(dev_priv
)) {
6481 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6482 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6483 intel_encoder
->enable
= vlv_enable_dp
;
6484 intel_encoder
->disable
= vlv_disable_dp
;
6485 intel_encoder
->post_disable
= chv_post_disable_dp
;
6486 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6487 } else if (IS_VALLEYVIEW(dev_priv
)) {
6488 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6489 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6490 intel_encoder
->enable
= vlv_enable_dp
;
6491 intel_encoder
->disable
= vlv_disable_dp
;
6492 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6494 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6495 intel_encoder
->enable
= g4x_enable_dp
;
6496 intel_encoder
->disable
= g4x_disable_dp
;
6497 intel_encoder
->post_disable
= g4x_post_disable_dp
;
6500 intel_dig_port
->dp
.output_reg
= output_reg
;
6501 intel_dig_port
->max_lanes
= 4;
6503 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6504 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6505 if (IS_CHERRYVIEW(dev_priv
)) {
6507 intel_encoder
->crtc_mask
= 1 << 2;
6509 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6511 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6513 intel_encoder
->cloneable
= 0;
6514 intel_encoder
->port
= port
;
6516 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6517 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6520 intel_infoframe_init(intel_dig_port
);
6522 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6523 goto err_init_connector
;
6528 drm_encoder_cleanup(encoder
);
6530 kfree(intel_connector
);
6531 err_connector_alloc
:
6532 kfree(intel_dig_port
);
6536 void intel_dp_mst_suspend(struct drm_device
*dev
)
6538 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6542 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6543 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6545 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6548 if (intel_dig_port
->dp
.is_mst
)
6549 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6553 void intel_dp_mst_resume(struct drm_device
*dev
)
6555 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6558 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6559 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6562 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6565 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6567 intel_dp_check_mst_status(&intel_dig_port
->dp
);