2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include "intel_drv.h"
43 #include <drm/i915_drm.h>
46 #define DP_DPRX_ESI_LEN 14
48 /* Compliance test status bits */
49 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
50 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
51 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
52 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
59 static const struct dp_link_dpll gen4_dpll
[] = {
61 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
63 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
66 static const struct dp_link_dpll pch_dpll
[] = {
68 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
70 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
73 static const struct dp_link_dpll vlv_dpll
[] = {
75 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
77 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
81 * CHV supports eDP 1.4 that have more link rates.
82 * Below only provides the fixed rate but exclude variable rate.
84 static const struct dp_link_dpll chv_dpll
[] = {
86 * CHV requires to program fractional division for m2.
87 * m2 is stored in fixed point format using formula below
88 * (m2_int << 22) | m2_fraction
90 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
91 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
92 { 270000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
97 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
98 * @intel_dp: DP struct
100 * If a CPU or PCH DP output is attached to an eDP panel, this function
101 * will return true, and false otherwise.
103 bool intel_dp_is_edp(struct intel_dp
*intel_dp
)
105 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
107 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
110 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
112 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
114 return intel_dig_port
->base
.base
.dev
;
117 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
119 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
122 static void intel_dp_link_down(struct intel_encoder
*encoder
,
123 const struct intel_crtc_state
*old_crtc_state
);
124 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
125 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
126 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
127 const struct intel_crtc_state
*crtc_state
);
128 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
130 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
132 /* update sink rates from dpcd */
133 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
135 static const int dp_rates
[] = {
136 162000, 270000, 540000, 810000
140 max_rate
= drm_dp_bw_code_to_link_rate(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
142 for (i
= 0; i
< ARRAY_SIZE(dp_rates
); i
++) {
143 if (dp_rates
[i
] > max_rate
)
145 intel_dp
->sink_rates
[i
] = dp_rates
[i
];
148 intel_dp
->num_sink_rates
= i
;
151 /* Get length of rates array potentially limited by max_rate. */
152 static int intel_dp_rate_limit_len(const int *rates
, int len
, int max_rate
)
156 /* Limit results by potentially reduced max rate */
157 for (i
= 0; i
< len
; i
++) {
158 if (rates
[len
- i
- 1] <= max_rate
)
165 /* Get length of common rates array potentially limited by max_rate. */
166 static int intel_dp_common_len_rate_limit(const struct intel_dp
*intel_dp
,
169 return intel_dp_rate_limit_len(intel_dp
->common_rates
,
170 intel_dp
->num_common_rates
, max_rate
);
173 /* Theoretical max between source and sink */
174 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
176 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
179 /* Theoretical max between source and sink */
180 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
182 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
183 int source_max
= intel_dig_port
->max_lanes
;
184 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
186 return min(source_max
, sink_max
);
189 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
191 return intel_dp
->max_link_lane_count
;
195 intel_dp_link_required(int pixel_clock
, int bpp
)
197 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
198 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
202 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
204 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
205 * link rate that is generally expressed in Gbps. Since, 8 bits of data
206 * is transmitted every LS_Clk per lane, there is no need to account for
207 * the channel encoding that is done in the PHY layer here.
210 return max_link_clock
* max_lanes
;
214 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
216 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
217 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
218 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
219 int max_dotclk
= dev_priv
->max_dotclk_freq
;
222 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
224 if (type
!= DP_DS_PORT_TYPE_VGA
)
227 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
228 intel_dp
->downstream_ports
);
230 if (ds_max_dotclk
!= 0)
231 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
236 static int cnl_max_source_rate(struct intel_dp
*intel_dp
)
238 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
239 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
240 enum port port
= dig_port
->base
.port
;
242 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
244 /* Low voltage SKUs are limited to max of 5.4G */
245 if (voltage
== VOLTAGE_INFO_0_85V
)
248 /* For this SKU 8.1G is supported in all ports */
249 if (IS_CNL_WITH_PORT_F(dev_priv
))
252 /* For other SKUs, max rate on ports A and D is 5.4G */
253 if (port
== PORT_A
|| port
== PORT_D
)
260 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
262 /* The values must be in increasing order */
263 static const int cnl_rates
[] = {
264 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
266 static const int bxt_rates
[] = {
267 162000, 216000, 243000, 270000, 324000, 432000, 540000
269 static const int skl_rates
[] = {
270 162000, 216000, 270000, 324000, 432000, 540000
272 static const int hsw_rates
[] = {
273 162000, 270000, 540000
275 static const int g4x_rates
[] = {
278 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
279 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
280 const struct ddi_vbt_port_info
*info
=
281 &dev_priv
->vbt
.ddi_port_info
[dig_port
->base
.port
];
282 const int *source_rates
;
283 int size
, max_rate
= 0, vbt_max_rate
= info
->dp_max_link_rate
;
285 /* This should only be done once */
286 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
288 if (IS_CANNONLAKE(dev_priv
)) {
289 source_rates
= cnl_rates
;
290 size
= ARRAY_SIZE(cnl_rates
);
291 max_rate
= cnl_max_source_rate(intel_dp
);
292 } else if (IS_GEN9_LP(dev_priv
)) {
293 source_rates
= bxt_rates
;
294 size
= ARRAY_SIZE(bxt_rates
);
295 } else if (IS_GEN9_BC(dev_priv
)) {
296 source_rates
= skl_rates
;
297 size
= ARRAY_SIZE(skl_rates
);
298 } else if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
299 IS_BROADWELL(dev_priv
)) {
300 source_rates
= hsw_rates
;
301 size
= ARRAY_SIZE(hsw_rates
);
303 source_rates
= g4x_rates
;
304 size
= ARRAY_SIZE(g4x_rates
);
307 if (max_rate
&& vbt_max_rate
)
308 max_rate
= min(max_rate
, vbt_max_rate
);
309 else if (vbt_max_rate
)
310 max_rate
= vbt_max_rate
;
313 size
= intel_dp_rate_limit_len(source_rates
, size
, max_rate
);
315 intel_dp
->source_rates
= source_rates
;
316 intel_dp
->num_source_rates
= size
;
319 static int intersect_rates(const int *source_rates
, int source_len
,
320 const int *sink_rates
, int sink_len
,
323 int i
= 0, j
= 0, k
= 0;
325 while (i
< source_len
&& j
< sink_len
) {
326 if (source_rates
[i
] == sink_rates
[j
]) {
327 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
329 common_rates
[k
] = source_rates
[i
];
333 } else if (source_rates
[i
] < sink_rates
[j
]) {
342 /* return index of rate in rates array, or -1 if not found */
343 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
347 for (i
= 0; i
< len
; i
++)
348 if (rate
== rates
[i
])
354 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
356 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
358 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
359 intel_dp
->num_source_rates
,
360 intel_dp
->sink_rates
,
361 intel_dp
->num_sink_rates
,
362 intel_dp
->common_rates
);
364 /* Paranoia, there should always be something in common. */
365 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
366 intel_dp
->common_rates
[0] = 162000;
367 intel_dp
->num_common_rates
= 1;
371 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
, int link_rate
,
375 * FIXME: we need to synchronize the current link parameters with
376 * hardware readout. Currently fast link training doesn't work on
379 if (link_rate
== 0 ||
380 link_rate
> intel_dp
->max_link_rate
)
383 if (lane_count
== 0 ||
384 lane_count
> intel_dp_max_lane_count(intel_dp
))
390 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
391 int link_rate
, uint8_t lane_count
)
395 index
= intel_dp_rate_index(intel_dp
->common_rates
,
396 intel_dp
->num_common_rates
,
399 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
400 intel_dp
->max_link_lane_count
= lane_count
;
401 } else if (lane_count
> 1) {
402 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
403 intel_dp
->max_link_lane_count
= lane_count
>> 1;
405 DRM_ERROR("Link Training Unsuccessful\n");
412 static enum drm_mode_status
413 intel_dp_mode_valid(struct drm_connector
*connector
,
414 struct drm_display_mode
*mode
)
416 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
417 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
418 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
419 int target_clock
= mode
->clock
;
420 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
423 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
425 if (intel_dp_is_edp(intel_dp
) && fixed_mode
) {
426 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
429 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
432 target_clock
= fixed_mode
->clock
;
435 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
436 max_lanes
= intel_dp_max_lane_count(intel_dp
);
438 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
439 mode_rate
= intel_dp_link_required(target_clock
, 18);
441 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
442 return MODE_CLOCK_HIGH
;
444 if (mode
->clock
< 10000)
445 return MODE_CLOCK_LOW
;
447 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
448 return MODE_H_ILLEGAL
;
453 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
460 for (i
= 0; i
< src_bytes
; i
++)
461 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
465 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
470 for (i
= 0; i
< dst_bytes
; i
++)
471 dst
[i
] = src
>> ((3-i
) * 8);
475 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
477 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
478 bool force_disable_vdd
);
480 intel_dp_pps_init(struct intel_dp
*intel_dp
);
482 static void pps_lock(struct intel_dp
*intel_dp
)
484 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
487 * See intel_power_sequencer_reset() why we need
488 * a power domain reference here.
490 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
492 mutex_lock(&dev_priv
->pps_mutex
);
495 static void pps_unlock(struct intel_dp
*intel_dp
)
497 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
499 mutex_unlock(&dev_priv
->pps_mutex
);
501 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
505 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
507 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
508 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
509 enum pipe pipe
= intel_dp
->pps_pipe
;
510 bool pll_enabled
, release_cl_override
= false;
511 enum dpio_phy phy
= DPIO_PHY(pipe
);
512 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
515 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
516 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
517 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
)))
520 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
521 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
523 /* Preserve the BIOS-computed detected bit. This is
524 * supposed to be read-only.
526 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
527 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
528 DP
|= DP_PORT_WIDTH(1);
529 DP
|= DP_LINK_TRAIN_PAT_1
;
531 if (IS_CHERRYVIEW(dev_priv
))
532 DP
|= DP_PIPE_SELECT_CHV(pipe
);
533 else if (pipe
== PIPE_B
)
534 DP
|= DP_PIPEB_SELECT
;
536 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
539 * The DPLL for the pipe must be enabled for this to work.
540 * So enable temporarily it if it's not already enabled.
543 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
544 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
546 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
547 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
548 DRM_ERROR("Failed to force on pll for pipe %c!\n",
555 * Similar magic as in intel_dp_enable_port().
556 * We _must_ do this port enable + disable trick
557 * to make this power seqeuencer lock onto the port.
558 * Otherwise even VDD force bit won't work.
560 I915_WRITE(intel_dp
->output_reg
, DP
);
561 POSTING_READ(intel_dp
->output_reg
);
563 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
564 POSTING_READ(intel_dp
->output_reg
);
566 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
567 POSTING_READ(intel_dp
->output_reg
);
570 vlv_force_pll_off(dev_priv
, pipe
);
572 if (release_cl_override
)
573 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
577 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
579 struct intel_encoder
*encoder
;
580 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
583 * We don't have power sequencer currently.
584 * Pick one that's not used by other ports.
586 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
587 struct intel_dp
*intel_dp
;
589 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
590 encoder
->type
!= INTEL_OUTPUT_EDP
)
593 intel_dp
= enc_to_intel_dp(&encoder
->base
);
595 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
596 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
597 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
599 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
600 pipes
&= ~(1 << intel_dp
->pps_pipe
);
602 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
604 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
605 pipes
&= ~(1 << intel_dp
->active_pipe
);
612 return ffs(pipes
) - 1;
616 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
618 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
619 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
622 lockdep_assert_held(&dev_priv
->pps_mutex
);
624 /* We should never land here with regular DP ports */
625 WARN_ON(!intel_dp_is_edp(intel_dp
));
627 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
628 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
630 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
631 return intel_dp
->pps_pipe
;
633 pipe
= vlv_find_free_pps(dev_priv
);
636 * Didn't find one. This should not happen since there
637 * are two power sequencers and up to two eDP ports.
639 if (WARN_ON(pipe
== INVALID_PIPE
))
642 vlv_steal_power_sequencer(dev_priv
, pipe
);
643 intel_dp
->pps_pipe
= pipe
;
645 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
646 pipe_name(intel_dp
->pps_pipe
),
647 port_name(intel_dig_port
->base
.port
));
649 /* init power sequencer on this pipe and port */
650 intel_dp_init_panel_power_sequencer(intel_dp
);
651 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
654 * Even vdd force doesn't work until we've made
655 * the power sequencer lock in on the port.
657 vlv_power_sequencer_kick(intel_dp
);
659 return intel_dp
->pps_pipe
;
663 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
665 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
666 int backlight_controller
= dev_priv
->vbt
.backlight
.controller
;
668 lockdep_assert_held(&dev_priv
->pps_mutex
);
670 /* We should never land here with regular DP ports */
671 WARN_ON(!intel_dp_is_edp(intel_dp
));
673 if (!intel_dp
->pps_reset
)
674 return backlight_controller
;
676 intel_dp
->pps_reset
= false;
679 * Only the HW needs to be reprogrammed, the SW state is fixed and
680 * has been setup during connector init.
682 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
684 return backlight_controller
;
687 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
690 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
693 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
696 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
699 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
702 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
709 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
711 vlv_pipe_check pipe_check
)
715 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
716 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
717 PANEL_PORT_SELECT_MASK
;
719 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
722 if (!pipe_check(dev_priv
, pipe
))
732 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
734 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
735 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
736 enum port port
= intel_dig_port
->base
.port
;
738 lockdep_assert_held(&dev_priv
->pps_mutex
);
740 /* try to find a pipe with this port selected */
741 /* first pick one where the panel is on */
742 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
744 /* didn't find one? pick one where vdd is on */
745 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
746 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
747 vlv_pipe_has_vdd_on
);
748 /* didn't find one? pick one with just the correct port */
749 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
750 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
753 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
754 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
755 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
760 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
761 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
763 intel_dp_init_panel_power_sequencer(intel_dp
);
764 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
767 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
769 struct intel_encoder
*encoder
;
771 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
772 !IS_GEN9_LP(dev_priv
)))
776 * We can't grab pps_mutex here due to deadlock with power_domain
777 * mutex when power_domain functions are called while holding pps_mutex.
778 * That also means that in order to use pps_pipe the code needs to
779 * hold both a power domain reference and pps_mutex, and the power domain
780 * reference get/put must be done while _not_ holding pps_mutex.
781 * pps_{lock,unlock}() do these steps in the correct order, so one
782 * should use them always.
785 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
786 struct intel_dp
*intel_dp
;
788 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
789 encoder
->type
!= INTEL_OUTPUT_EDP
&&
790 encoder
->type
!= INTEL_OUTPUT_DDI
)
793 intel_dp
= enc_to_intel_dp(&encoder
->base
);
795 /* Skip pure DVI/HDMI DDI encoders */
796 if (!i915_mmio_reg_valid(intel_dp
->output_reg
))
799 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
801 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
804 if (IS_GEN9_LP(dev_priv
))
805 intel_dp
->pps_reset
= true;
807 intel_dp
->pps_pipe
= INVALID_PIPE
;
811 struct pps_registers
{
819 static void intel_pps_get_registers(struct intel_dp
*intel_dp
,
820 struct pps_registers
*regs
)
822 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
825 memset(regs
, 0, sizeof(*regs
));
827 if (IS_GEN9_LP(dev_priv
))
828 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
829 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
830 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
832 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
833 regs
->pp_stat
= PP_STATUS(pps_idx
);
834 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
835 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
836 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
837 !HAS_PCH_ICP(dev_priv
))
838 regs
->pp_div
= PP_DIVISOR(pps_idx
);
842 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
844 struct pps_registers regs
;
846 intel_pps_get_registers(intel_dp
, ®s
);
852 _pp_stat_reg(struct intel_dp
*intel_dp
)
854 struct pps_registers regs
;
856 intel_pps_get_registers(intel_dp
, ®s
);
861 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
862 This function only applicable when panel PM state is not to be tracked */
863 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
866 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
868 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
870 if (!intel_dp_is_edp(intel_dp
) || code
!= SYS_RESTART
)
875 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
876 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
877 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
880 pp_ctrl_reg
= PP_CONTROL(pipe
);
881 pp_div_reg
= PP_DIVISOR(pipe
);
882 pp_div
= I915_READ(pp_div_reg
);
883 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
885 /* 0x1F write to PP_DIV_REG sets max cycle delay */
886 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
887 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
888 msleep(intel_dp
->panel_power_cycle_delay
);
891 pps_unlock(intel_dp
);
896 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
898 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
900 lockdep_assert_held(&dev_priv
->pps_mutex
);
902 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
903 intel_dp
->pps_pipe
== INVALID_PIPE
)
906 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
909 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
911 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
913 lockdep_assert_held(&dev_priv
->pps_mutex
);
915 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
916 intel_dp
->pps_pipe
== INVALID_PIPE
)
919 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
923 intel_dp_check_edp(struct intel_dp
*intel_dp
)
925 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
927 if (!intel_dp_is_edp(intel_dp
))
930 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
931 WARN(1, "eDP powered off while attempting aux channel communication.\n");
932 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
933 I915_READ(_pp_stat_reg(intel_dp
)),
934 I915_READ(_pp_ctrl_reg(intel_dp
)));
939 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
941 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
942 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
946 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
948 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
949 msecs_to_jiffies_timeout(10));
951 done
= wait_for(C
, 10) == 0;
953 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
960 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
962 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
968 * The clock divider is based off the hrawclk, and would like to run at
969 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
971 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
974 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
976 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
982 * The clock divider is based off the cdclk or PCH rawclk, and would
983 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
984 * divide by 2000 and use that
986 if (intel_dp
->aux_ch
== AUX_CH_A
)
987 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
989 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
992 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
994 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
996 if (intel_dp
->aux_ch
!= AUX_CH_A
&& HAS_PCH_LPT_H(dev_priv
)) {
997 /* Workaround for non-ULT HSW */
1005 return ilk_get_aux_clock_divider(intel_dp
, index
);
1008 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1011 * SKL doesn't need us to program the AUX clock divider (Hardware will
1012 * derive the clock from CDCLK automatically). We still implement the
1013 * get_aux_clock_divider vfunc to plug-in into the existing code.
1015 return index
? 0 : 1;
1018 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1021 uint32_t aux_clock_divider
)
1023 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1024 struct drm_i915_private
*dev_priv
=
1025 to_i915(intel_dig_port
->base
.base
.dev
);
1026 uint32_t precharge
, timeout
;
1028 if (IS_GEN6(dev_priv
))
1033 if (IS_BROADWELL(dev_priv
))
1034 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1036 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1038 return DP_AUX_CH_CTL_SEND_BUSY
|
1039 DP_AUX_CH_CTL_DONE
|
1040 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1041 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1043 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1044 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1045 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1046 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1049 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1054 return DP_AUX_CH_CTL_SEND_BUSY
|
1055 DP_AUX_CH_CTL_DONE
|
1056 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1057 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1058 DP_AUX_CH_CTL_TIME_OUT_MAX
|
1059 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1060 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1061 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1062 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1066 intel_dp_aux_xfer(struct intel_dp
*intel_dp
,
1067 const uint8_t *send
, int send_bytes
,
1068 uint8_t *recv
, int recv_size
,
1069 u32 aux_send_ctl_flags
)
1071 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1072 struct drm_i915_private
*dev_priv
=
1073 to_i915(intel_dig_port
->base
.base
.dev
);
1074 i915_reg_t ch_ctl
, ch_data
[5];
1075 uint32_t aux_clock_divider
;
1076 int i
, ret
, recv_bytes
;
1079 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1082 ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
1083 for (i
= 0; i
< ARRAY_SIZE(ch_data
); i
++)
1084 ch_data
[i
] = intel_dp
->aux_ch_data_reg(intel_dp
, i
);
1089 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1090 * In such cases we want to leave VDD enabled and it's up to upper layers
1091 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1094 vdd
= edp_panel_vdd_on(intel_dp
);
1096 /* dp aux is extremely sensitive to irq latency, hence request the
1097 * lowest possible wakeup latency and so prevent the cpu from going into
1098 * deep sleep states.
1100 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1102 intel_dp_check_edp(intel_dp
);
1104 /* Try to wait for any previous AUX channel activity */
1105 for (try = 0; try < 3; try++) {
1106 status
= I915_READ_NOTRACE(ch_ctl
);
1107 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1113 static u32 last_status
= -1;
1114 const u32 status
= I915_READ(ch_ctl
);
1116 if (status
!= last_status
) {
1117 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1119 last_status
= status
;
1126 /* Only 5 data registers! */
1127 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1132 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1133 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1138 send_ctl
|= aux_send_ctl_flags
;
1140 /* Must try at least 3 times according to DP spec */
1141 for (try = 0; try < 5; try++) {
1142 /* Load the send data into the aux channel data registers */
1143 for (i
= 0; i
< send_bytes
; i
+= 4)
1144 I915_WRITE(ch_data
[i
>> 2],
1145 intel_dp_pack_aux(send
+ i
,
1148 /* Send the command and wait for it to complete */
1149 I915_WRITE(ch_ctl
, send_ctl
);
1151 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1153 /* Clear done status and any errors */
1156 DP_AUX_CH_CTL_DONE
|
1157 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1158 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1160 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1161 * 400us delay required for errors and timeouts
1162 * Timeout errors from the HW already meet this
1163 * requirement so skip to next iteration
1165 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1168 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1169 usleep_range(400, 500);
1172 if (status
& DP_AUX_CH_CTL_DONE
)
1177 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1178 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1184 /* Check for timeout or receive error.
1185 * Timeouts occur when the sink is not connected
1187 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1188 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1193 /* Timeouts occur when the device isn't connected, so they're
1194 * "normal" -- don't fill the kernel log with these */
1195 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1196 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1201 /* Unload any bytes sent back from the other side */
1202 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1203 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1206 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1207 * We have no idea of what happened so we return -EBUSY so
1208 * drm layer takes care for the necessary retries.
1210 if (recv_bytes
== 0 || recv_bytes
> 20) {
1211 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1217 if (recv_bytes
> recv_size
)
1218 recv_bytes
= recv_size
;
1220 for (i
= 0; i
< recv_bytes
; i
+= 4)
1221 intel_dp_unpack_aux(I915_READ(ch_data
[i
>> 2]),
1222 recv
+ i
, recv_bytes
- i
);
1226 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1229 edp_panel_vdd_off(intel_dp
, false);
1231 pps_unlock(intel_dp
);
1236 #define BARE_ADDRESS_SIZE 3
1237 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1240 intel_dp_aux_header(u8 txbuf
[HEADER_SIZE
],
1241 const struct drm_dp_aux_msg
*msg
)
1243 txbuf
[0] = (msg
->request
<< 4) | ((msg
->address
>> 16) & 0xf);
1244 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1245 txbuf
[2] = msg
->address
& 0xff;
1246 txbuf
[3] = msg
->size
- 1;
1250 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1252 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1253 uint8_t txbuf
[20], rxbuf
[20];
1254 size_t txsize
, rxsize
;
1257 intel_dp_aux_header(txbuf
, msg
);
1259 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1260 case DP_AUX_NATIVE_WRITE
:
1261 case DP_AUX_I2C_WRITE
:
1262 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1263 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1264 rxsize
= 2; /* 0 or 1 data bytes */
1266 if (WARN_ON(txsize
> 20))
1269 WARN_ON(!msg
->buffer
!= !msg
->size
);
1272 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1274 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1277 msg
->reply
= rxbuf
[0] >> 4;
1280 /* Number of bytes written in a short write. */
1281 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1283 /* Return payload size. */
1289 case DP_AUX_NATIVE_READ
:
1290 case DP_AUX_I2C_READ
:
1291 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1292 rxsize
= msg
->size
+ 1;
1294 if (WARN_ON(rxsize
> 20))
1297 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1300 msg
->reply
= rxbuf
[0] >> 4;
1302 * Assume happy day, and copy the data. The caller is
1303 * expected to check msg->reply before touching it.
1305 * Return payload size.
1308 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1320 static enum aux_ch
intel_aux_ch(struct intel_dp
*intel_dp
)
1322 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
1323 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1324 enum port port
= encoder
->port
;
1325 const struct ddi_vbt_port_info
*info
=
1326 &dev_priv
->vbt
.ddi_port_info
[port
];
1329 if (!info
->alternate_aux_channel
) {
1330 aux_ch
= (enum aux_ch
) port
;
1332 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1333 aux_ch_name(aux_ch
), port_name(port
));
1337 switch (info
->alternate_aux_channel
) {
1354 MISSING_CASE(info
->alternate_aux_channel
);
1359 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1360 aux_ch_name(aux_ch
), port_name(port
));
1365 static enum intel_display_power_domain
1366 intel_aux_power_domain(struct intel_dp
*intel_dp
)
1368 switch (intel_dp
->aux_ch
) {
1370 return POWER_DOMAIN_AUX_A
;
1372 return POWER_DOMAIN_AUX_B
;
1374 return POWER_DOMAIN_AUX_C
;
1376 return POWER_DOMAIN_AUX_D
;
1378 return POWER_DOMAIN_AUX_F
;
1380 MISSING_CASE(intel_dp
->aux_ch
);
1381 return POWER_DOMAIN_AUX_A
;
1385 static i915_reg_t
g4x_aux_ctl_reg(struct intel_dp
*intel_dp
)
1387 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1388 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1394 return DP_AUX_CH_CTL(aux_ch
);
1396 MISSING_CASE(aux_ch
);
1397 return DP_AUX_CH_CTL(AUX_CH_B
);
1401 static i915_reg_t
g4x_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1403 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1404 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1410 return DP_AUX_CH_DATA(aux_ch
, index
);
1412 MISSING_CASE(aux_ch
);
1413 return DP_AUX_CH_DATA(AUX_CH_B
, index
);
1417 static i915_reg_t
ilk_aux_ctl_reg(struct intel_dp
*intel_dp
)
1419 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1420 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1424 return DP_AUX_CH_CTL(aux_ch
);
1428 return PCH_DP_AUX_CH_CTL(aux_ch
);
1430 MISSING_CASE(aux_ch
);
1431 return DP_AUX_CH_CTL(AUX_CH_A
);
1435 static i915_reg_t
ilk_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1437 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1438 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1442 return DP_AUX_CH_DATA(aux_ch
, index
);
1446 return PCH_DP_AUX_CH_DATA(aux_ch
, index
);
1448 MISSING_CASE(aux_ch
);
1449 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1453 static i915_reg_t
skl_aux_ctl_reg(struct intel_dp
*intel_dp
)
1455 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1456 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1464 return DP_AUX_CH_CTL(aux_ch
);
1466 MISSING_CASE(aux_ch
);
1467 return DP_AUX_CH_CTL(AUX_CH_A
);
1471 static i915_reg_t
skl_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1473 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1474 enum aux_ch aux_ch
= intel_dp
->aux_ch
;
1482 return DP_AUX_CH_DATA(aux_ch
, index
);
1484 MISSING_CASE(aux_ch
);
1485 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1490 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1492 kfree(intel_dp
->aux
.name
);
1496 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1498 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1499 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
1501 intel_dp
->aux_ch
= intel_aux_ch(intel_dp
);
1502 intel_dp
->aux_power_domain
= intel_aux_power_domain(intel_dp
);
1504 if (INTEL_GEN(dev_priv
) >= 9) {
1505 intel_dp
->aux_ch_ctl_reg
= skl_aux_ctl_reg
;
1506 intel_dp
->aux_ch_data_reg
= skl_aux_data_reg
;
1507 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1508 intel_dp
->aux_ch_ctl_reg
= ilk_aux_ctl_reg
;
1509 intel_dp
->aux_ch_data_reg
= ilk_aux_data_reg
;
1511 intel_dp
->aux_ch_ctl_reg
= g4x_aux_ctl_reg
;
1512 intel_dp
->aux_ch_data_reg
= g4x_aux_data_reg
;
1515 if (INTEL_GEN(dev_priv
) >= 9)
1516 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
1517 else if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
1518 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
1519 else if (HAS_PCH_SPLIT(dev_priv
))
1520 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
1522 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
1524 if (INTEL_GEN(dev_priv
) >= 9)
1525 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
1527 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
1529 drm_dp_aux_init(&intel_dp
->aux
);
1531 /* Failure to allocate our preferred name is not critical */
1532 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c",
1533 port_name(encoder
->port
));
1534 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1537 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1539 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1541 return max_rate
>= 540000;
1545 intel_dp_set_clock(struct intel_encoder
*encoder
,
1546 struct intel_crtc_state
*pipe_config
)
1548 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1549 const struct dp_link_dpll
*divisor
= NULL
;
1552 if (IS_G4X(dev_priv
)) {
1553 divisor
= gen4_dpll
;
1554 count
= ARRAY_SIZE(gen4_dpll
);
1555 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1557 count
= ARRAY_SIZE(pch_dpll
);
1558 } else if (IS_CHERRYVIEW(dev_priv
)) {
1560 count
= ARRAY_SIZE(chv_dpll
);
1561 } else if (IS_VALLEYVIEW(dev_priv
)) {
1563 count
= ARRAY_SIZE(vlv_dpll
);
1566 if (divisor
&& count
) {
1567 for (i
= 0; i
< count
; i
++) {
1568 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1569 pipe_config
->dpll
= divisor
[i
].dpll
;
1570 pipe_config
->clock_set
= true;
1577 static void snprintf_int_array(char *str
, size_t len
,
1578 const int *array
, int nelem
)
1584 for (i
= 0; i
< nelem
; i
++) {
1585 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1593 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1595 char str
[128]; /* FIXME: too big for stack? */
1597 if ((drm_debug
& DRM_UT_KMS
) == 0)
1600 snprintf_int_array(str
, sizeof(str
),
1601 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1602 DRM_DEBUG_KMS("source rates: %s\n", str
);
1604 snprintf_int_array(str
, sizeof(str
),
1605 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1606 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1608 snprintf_int_array(str
, sizeof(str
),
1609 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1610 DRM_DEBUG_KMS("common rates: %s\n", str
);
1614 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1618 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1619 if (WARN_ON(len
<= 0))
1622 return intel_dp
->common_rates
[len
- 1];
1625 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1627 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1628 intel_dp
->num_sink_rates
, rate
);
1636 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1637 uint8_t *link_bw
, uint8_t *rate_select
)
1639 /* eDP 1.4 rate select method. */
1640 if (intel_dp
->use_rate_select
) {
1643 intel_dp_rate_select(intel_dp
, port_clock
);
1645 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1650 struct link_config_limits
{
1651 int min_clock
, max_clock
;
1652 int min_lane_count
, max_lane_count
;
1653 int min_bpp
, max_bpp
;
1656 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1657 struct intel_crtc_state
*pipe_config
)
1659 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1660 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1663 bpp
= pipe_config
->pipe_bpp
;
1664 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1667 bpp
= min(bpp
, 3*bpc
);
1669 if (intel_dp_is_edp(intel_dp
)) {
1670 /* Get bpp from vbt only for panels that dont have bpp in edid */
1671 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1672 dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
) {
1673 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1674 dev_priv
->vbt
.edp
.bpp
);
1675 bpp
= dev_priv
->vbt
.edp
.bpp
;
1682 static bool intel_edp_compare_alt_mode(struct drm_display_mode
*m1
,
1683 struct drm_display_mode
*m2
)
1688 bres
= (m1
->hdisplay
== m2
->hdisplay
&&
1689 m1
->hsync_start
== m2
->hsync_start
&&
1690 m1
->hsync_end
== m2
->hsync_end
&&
1691 m1
->htotal
== m2
->htotal
&&
1692 m1
->vdisplay
== m2
->vdisplay
&&
1693 m1
->vsync_start
== m2
->vsync_start
&&
1694 m1
->vsync_end
== m2
->vsync_end
&&
1695 m1
->vtotal
== m2
->vtotal
);
1699 /* Adjust link config limits based on compliance test requests. */
1701 intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp
,
1702 struct intel_crtc_state
*pipe_config
,
1703 struct link_config_limits
*limits
)
1705 /* For DP Compliance we override the computed bpp for the pipe */
1706 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1707 int bpp
= 3 * intel_dp
->compliance
.test_data
.bpc
;
1709 limits
->min_bpp
= limits
->max_bpp
= bpp
;
1710 pipe_config
->dither_force_disable
= bpp
== 6 * 3;
1712 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp
);
1715 /* Use values requested by Compliance Test Request */
1716 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1719 /* Validate the compliance test data since max values
1720 * might have changed due to link train fallback.
1722 if (intel_dp_link_params_valid(intel_dp
, intel_dp
->compliance
.test_link_rate
,
1723 intel_dp
->compliance
.test_lane_count
)) {
1724 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1725 intel_dp
->num_common_rates
,
1726 intel_dp
->compliance
.test_link_rate
);
1728 limits
->min_clock
= limits
->max_clock
= index
;
1729 limits
->min_lane_count
= limits
->max_lane_count
=
1730 intel_dp
->compliance
.test_lane_count
;
1735 /* Optimize link config in order: max bpp, min clock, min lanes */
1737 intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp
,
1738 struct intel_crtc_state
*pipe_config
,
1739 const struct link_config_limits
*limits
)
1741 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1742 int bpp
, clock
, lane_count
;
1743 int mode_rate
, link_clock
, link_avail
;
1745 for (bpp
= limits
->max_bpp
; bpp
>= limits
->min_bpp
; bpp
-= 2 * 3) {
1746 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1749 for (clock
= limits
->min_clock
; clock
<= limits
->max_clock
; clock
++) {
1750 for (lane_count
= limits
->min_lane_count
;
1751 lane_count
<= limits
->max_lane_count
;
1753 link_clock
= intel_dp
->common_rates
[clock
];
1754 link_avail
= intel_dp_max_data_rate(link_clock
,
1757 if (mode_rate
<= link_avail
) {
1758 pipe_config
->lane_count
= lane_count
;
1759 pipe_config
->pipe_bpp
= bpp
;
1760 pipe_config
->port_clock
= link_clock
;
1772 intel_dp_compute_link_config(struct intel_encoder
*encoder
,
1773 struct intel_crtc_state
*pipe_config
)
1775 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1776 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1777 struct link_config_limits limits
;
1780 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1781 intel_dp
->max_link_rate
);
1783 /* No common link rates between source and sink */
1784 WARN_ON(common_len
<= 0);
1786 limits
.min_clock
= 0;
1787 limits
.max_clock
= common_len
- 1;
1789 limits
.min_lane_count
= 1;
1790 limits
.max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1792 limits
.min_bpp
= 6 * 3;
1793 limits
.max_bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1795 if (intel_dp_is_edp(intel_dp
)) {
1797 * Use the maximum clock and number of lanes the eDP panel
1798 * advertizes being capable of. The panels are generally
1799 * designed to support only a single clock and lane
1800 * configuration, and typically these values correspond to the
1801 * native resolution of the panel.
1803 limits
.min_lane_count
= limits
.max_lane_count
;
1804 limits
.min_clock
= limits
.max_clock
;
1807 intel_dp_adjust_compliance_config(intel_dp
, pipe_config
, &limits
);
1809 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1810 "max rate %d max bpp %d pixel clock %iKHz\n",
1811 limits
.max_lane_count
,
1812 intel_dp
->common_rates
[limits
.max_clock
],
1813 limits
.max_bpp
, adjusted_mode
->crtc_clock
);
1816 * Optimize for slow and wide. This is the place to add alternative
1817 * optimization policy.
1819 if (!intel_dp_compute_link_config_wide(intel_dp
, pipe_config
, &limits
))
1822 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1823 pipe_config
->lane_count
, pipe_config
->port_clock
,
1824 pipe_config
->pipe_bpp
);
1826 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1827 intel_dp_link_required(adjusted_mode
->crtc_clock
,
1828 pipe_config
->pipe_bpp
),
1829 intel_dp_max_data_rate(pipe_config
->port_clock
,
1830 pipe_config
->lane_count
));
1836 intel_dp_compute_config(struct intel_encoder
*encoder
,
1837 struct intel_crtc_state
*pipe_config
,
1838 struct drm_connector_state
*conn_state
)
1840 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1841 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1842 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1843 enum port port
= encoder
->port
;
1844 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1845 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1846 struct intel_digital_connector_state
*intel_conn_state
=
1847 to_intel_digital_connector_state(conn_state
);
1848 bool reduce_m_n
= drm_dp_has_quirk(&intel_dp
->desc
,
1849 DP_DPCD_QUIRK_LIMITED_M_N
);
1851 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1852 pipe_config
->has_pch_encoder
= true;
1854 pipe_config
->has_drrs
= false;
1855 if (IS_G4X(dev_priv
) || port
== PORT_A
)
1856 pipe_config
->has_audio
= false;
1857 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1858 pipe_config
->has_audio
= intel_dp
->has_audio
;
1860 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1862 if (intel_dp_is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1863 struct drm_display_mode
*panel_mode
=
1864 intel_connector
->panel
.alt_fixed_mode
;
1865 struct drm_display_mode
*req_mode
= &pipe_config
->base
.mode
;
1867 if (!intel_edp_compare_alt_mode(req_mode
, panel_mode
))
1868 panel_mode
= intel_connector
->panel
.fixed_mode
;
1870 drm_mode_debug_printmodeline(panel_mode
);
1872 intel_fixed_panel_mode(panel_mode
, adjusted_mode
);
1874 if (INTEL_GEN(dev_priv
) >= 9) {
1877 ret
= skl_update_scaler_crtc(pipe_config
);
1882 if (HAS_GMCH_DISPLAY(dev_priv
))
1883 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1884 conn_state
->scaling_mode
);
1886 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1887 conn_state
->scaling_mode
);
1890 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1891 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1894 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1897 if (!intel_dp_compute_link_config(encoder
, pipe_config
))
1900 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1903 * CEA-861-E - 5.1 Default Encoding Parameters
1904 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1906 pipe_config
->limited_color_range
=
1907 pipe_config
->pipe_bpp
!= 18 &&
1908 drm_default_rgb_quant_range(adjusted_mode
) ==
1909 HDMI_QUANTIZATION_RANGE_LIMITED
;
1911 pipe_config
->limited_color_range
=
1912 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1915 intel_link_compute_m_n(pipe_config
->pipe_bpp
, pipe_config
->lane_count
,
1916 adjusted_mode
->crtc_clock
,
1917 pipe_config
->port_clock
,
1918 &pipe_config
->dp_m_n
,
1921 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1922 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1923 pipe_config
->has_drrs
= true;
1924 intel_link_compute_m_n(pipe_config
->pipe_bpp
,
1925 pipe_config
->lane_count
,
1926 intel_connector
->panel
.downclock_mode
->clock
,
1927 pipe_config
->port_clock
,
1928 &pipe_config
->dp_m2_n2
,
1932 if (!HAS_DDI(dev_priv
))
1933 intel_dp_set_clock(encoder
, pipe_config
);
1935 intel_psr_compute_config(intel_dp
, pipe_config
);
1940 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1941 int link_rate
, uint8_t lane_count
,
1944 intel_dp
->link_trained
= false;
1945 intel_dp
->link_rate
= link_rate
;
1946 intel_dp
->lane_count
= lane_count
;
1947 intel_dp
->link_mst
= link_mst
;
1950 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1951 const struct intel_crtc_state
*pipe_config
)
1953 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1954 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1955 enum port port
= encoder
->port
;
1956 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1957 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1959 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1960 pipe_config
->lane_count
,
1961 intel_crtc_has_type(pipe_config
,
1962 INTEL_OUTPUT_DP_MST
));
1965 * There are four kinds of DP registers:
1972 * IBX PCH and CPU are the same for almost everything,
1973 * except that the CPU DP PLL is configured in this
1976 * CPT PCH is quite different, having many bits moved
1977 * to the TRANS_DP_CTL register instead. That
1978 * configuration happens (oddly) in ironlake_pch_enable
1981 /* Preserve the BIOS-computed detected bit. This is
1982 * supposed to be read-only.
1984 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1986 /* Handle DP bits in common between all three register formats */
1987 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1988 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1990 /* Split out the IBX/CPU vs CPT settings */
1992 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1993 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1994 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1995 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1996 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1997 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1999 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2000 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2002 intel_dp
->DP
|= crtc
->pipe
<< 29;
2003 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2006 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
2008 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2009 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2010 trans_dp
|= TRANS_DP_ENH_FRAMING
;
2012 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
2013 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
2015 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
2016 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
2018 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
2019 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
2020 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
2021 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
2022 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
2024 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2025 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2027 if (IS_CHERRYVIEW(dev_priv
))
2028 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
2029 else if (crtc
->pipe
== PIPE_B
)
2030 intel_dp
->DP
|= DP_PIPEB_SELECT
;
2034 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2035 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2037 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2038 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2040 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2041 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2043 static void intel_pps_verify_state(struct intel_dp
*intel_dp
);
2045 static void wait_panel_status(struct intel_dp
*intel_dp
,
2049 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2050 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2052 lockdep_assert_held(&dev_priv
->pps_mutex
);
2054 intel_pps_verify_state(intel_dp
);
2056 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2057 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2059 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2061 I915_READ(pp_stat_reg
),
2062 I915_READ(pp_ctrl_reg
));
2064 if (intel_wait_for_register(dev_priv
,
2065 pp_stat_reg
, mask
, value
,
2067 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2068 I915_READ(pp_stat_reg
),
2069 I915_READ(pp_ctrl_reg
));
2071 DRM_DEBUG_KMS("Wait complete\n");
2074 static void wait_panel_on(struct intel_dp
*intel_dp
)
2076 DRM_DEBUG_KMS("Wait for panel power on\n");
2077 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
2080 static void wait_panel_off(struct intel_dp
*intel_dp
)
2082 DRM_DEBUG_KMS("Wait for panel power off time\n");
2083 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
2086 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
2088 ktime_t panel_power_on_time
;
2089 s64 panel_power_off_duration
;
2091 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2093 /* take the difference of currrent time and panel power off time
2094 * and then make panel wait for t11_t12 if needed. */
2095 panel_power_on_time
= ktime_get_boottime();
2096 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
2098 /* When we disable the VDD override bit last we have to do the manual
2100 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
2101 wait_remaining_ms_from_jiffies(jiffies
,
2102 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
2104 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2107 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2109 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2110 intel_dp
->backlight_on_delay
);
2113 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2115 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2116 intel_dp
->backlight_off_delay
);
2119 /* Read the current pp_control value, unlocking the register if it
2123 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2125 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2128 lockdep_assert_held(&dev_priv
->pps_mutex
);
2130 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2131 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2132 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2133 control
&= ~PANEL_UNLOCK_MASK
;
2134 control
|= PANEL_UNLOCK_REGS
;
2140 * Must be paired with edp_panel_vdd_off().
2141 * Must hold pps_mutex around the whole on/off sequence.
2142 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2144 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2146 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2147 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2149 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2150 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2152 lockdep_assert_held(&dev_priv
->pps_mutex
);
2154 if (!intel_dp_is_edp(intel_dp
))
2157 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2158 intel_dp
->want_panel_vdd
= true;
2160 if (edp_have_panel_vdd(intel_dp
))
2161 return need_to_disable
;
2163 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2165 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2166 port_name(intel_dig_port
->base
.port
));
2168 if (!edp_have_panel_power(intel_dp
))
2169 wait_panel_power_cycle(intel_dp
);
2171 pp
= ironlake_get_pp_control(intel_dp
);
2172 pp
|= EDP_FORCE_VDD
;
2174 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2175 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2177 I915_WRITE(pp_ctrl_reg
, pp
);
2178 POSTING_READ(pp_ctrl_reg
);
2179 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2180 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2182 * If the panel wasn't on, delay before accessing aux channel
2184 if (!edp_have_panel_power(intel_dp
)) {
2185 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2186 port_name(intel_dig_port
->base
.port
));
2187 msleep(intel_dp
->panel_power_up_delay
);
2190 return need_to_disable
;
2194 * Must be paired with intel_edp_panel_vdd_off() or
2195 * intel_edp_panel_off().
2196 * Nested calls to these functions are not allowed since
2197 * we drop the lock. Caller must use some higher level
2198 * locking to prevent nested calls from other threads.
2200 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2204 if (!intel_dp_is_edp(intel_dp
))
2208 vdd
= edp_panel_vdd_on(intel_dp
);
2209 pps_unlock(intel_dp
);
2211 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2212 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2215 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2217 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2218 struct intel_digital_port
*intel_dig_port
=
2219 dp_to_dig_port(intel_dp
);
2221 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2223 lockdep_assert_held(&dev_priv
->pps_mutex
);
2225 WARN_ON(intel_dp
->want_panel_vdd
);
2227 if (!edp_have_panel_vdd(intel_dp
))
2230 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2231 port_name(intel_dig_port
->base
.port
));
2233 pp
= ironlake_get_pp_control(intel_dp
);
2234 pp
&= ~EDP_FORCE_VDD
;
2236 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2237 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2239 I915_WRITE(pp_ctrl_reg
, pp
);
2240 POSTING_READ(pp_ctrl_reg
);
2242 /* Make sure sequencer is idle before allowing subsequent activity */
2243 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2244 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2246 if ((pp
& PANEL_POWER_ON
) == 0)
2247 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2249 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2252 static void edp_panel_vdd_work(struct work_struct
*__work
)
2254 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2255 struct intel_dp
, panel_vdd_work
);
2258 if (!intel_dp
->want_panel_vdd
)
2259 edp_panel_vdd_off_sync(intel_dp
);
2260 pps_unlock(intel_dp
);
2263 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2265 unsigned long delay
;
2268 * Queue the timer to fire a long time from now (relative to the power
2269 * down delay) to keep the panel power up across a sequence of
2272 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2273 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2277 * Must be paired with edp_panel_vdd_on().
2278 * Must hold pps_mutex around the whole on/off sequence.
2279 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2281 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2283 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2285 lockdep_assert_held(&dev_priv
->pps_mutex
);
2287 if (!intel_dp_is_edp(intel_dp
))
2290 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2291 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2293 intel_dp
->want_panel_vdd
= false;
2296 edp_panel_vdd_off_sync(intel_dp
);
2298 edp_panel_vdd_schedule_off(intel_dp
);
2301 static void edp_panel_on(struct intel_dp
*intel_dp
)
2303 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2305 i915_reg_t pp_ctrl_reg
;
2307 lockdep_assert_held(&dev_priv
->pps_mutex
);
2309 if (!intel_dp_is_edp(intel_dp
))
2312 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2313 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2315 if (WARN(edp_have_panel_power(intel_dp
),
2316 "eDP port %c panel power already on\n",
2317 port_name(dp_to_dig_port(intel_dp
)->base
.port
)))
2320 wait_panel_power_cycle(intel_dp
);
2322 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2323 pp
= ironlake_get_pp_control(intel_dp
);
2324 if (IS_GEN5(dev_priv
)) {
2325 /* ILK workaround: disable reset around power sequence */
2326 pp
&= ~PANEL_POWER_RESET
;
2327 I915_WRITE(pp_ctrl_reg
, pp
);
2328 POSTING_READ(pp_ctrl_reg
);
2331 pp
|= PANEL_POWER_ON
;
2332 if (!IS_GEN5(dev_priv
))
2333 pp
|= PANEL_POWER_RESET
;
2335 I915_WRITE(pp_ctrl_reg
, pp
);
2336 POSTING_READ(pp_ctrl_reg
);
2338 wait_panel_on(intel_dp
);
2339 intel_dp
->last_power_on
= jiffies
;
2341 if (IS_GEN5(dev_priv
)) {
2342 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2343 I915_WRITE(pp_ctrl_reg
, pp
);
2344 POSTING_READ(pp_ctrl_reg
);
2348 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2350 if (!intel_dp_is_edp(intel_dp
))
2354 edp_panel_on(intel_dp
);
2355 pps_unlock(intel_dp
);
2359 static void edp_panel_off(struct intel_dp
*intel_dp
)
2361 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2363 i915_reg_t pp_ctrl_reg
;
2365 lockdep_assert_held(&dev_priv
->pps_mutex
);
2367 if (!intel_dp_is_edp(intel_dp
))
2370 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2371 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2373 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2374 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2376 pp
= ironlake_get_pp_control(intel_dp
);
2377 /* We need to switch off panel power _and_ force vdd, for otherwise some
2378 * panels get very unhappy and cease to work. */
2379 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2382 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2384 intel_dp
->want_panel_vdd
= false;
2386 I915_WRITE(pp_ctrl_reg
, pp
);
2387 POSTING_READ(pp_ctrl_reg
);
2389 wait_panel_off(intel_dp
);
2390 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2392 /* We got a reference when we enabled the VDD. */
2393 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2396 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2398 if (!intel_dp_is_edp(intel_dp
))
2402 edp_panel_off(intel_dp
);
2403 pps_unlock(intel_dp
);
2406 /* Enable backlight in the panel power control. */
2407 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2409 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2411 i915_reg_t pp_ctrl_reg
;
2414 * If we enable the backlight right away following a panel power
2415 * on, we may see slight flicker as the panel syncs with the eDP
2416 * link. So delay a bit to make sure the image is solid before
2417 * allowing it to appear.
2419 wait_backlight_on(intel_dp
);
2423 pp
= ironlake_get_pp_control(intel_dp
);
2424 pp
|= EDP_BLC_ENABLE
;
2426 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2428 I915_WRITE(pp_ctrl_reg
, pp
);
2429 POSTING_READ(pp_ctrl_reg
);
2431 pps_unlock(intel_dp
);
2434 /* Enable backlight PWM and backlight PP control. */
2435 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2436 const struct drm_connector_state
*conn_state
)
2438 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2440 if (!intel_dp_is_edp(intel_dp
))
2443 DRM_DEBUG_KMS("\n");
2445 intel_panel_enable_backlight(crtc_state
, conn_state
);
2446 _intel_edp_backlight_on(intel_dp
);
2449 /* Disable backlight in the panel power control. */
2450 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2452 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2454 i915_reg_t pp_ctrl_reg
;
2456 if (!intel_dp_is_edp(intel_dp
))
2461 pp
= ironlake_get_pp_control(intel_dp
);
2462 pp
&= ~EDP_BLC_ENABLE
;
2464 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2466 I915_WRITE(pp_ctrl_reg
, pp
);
2467 POSTING_READ(pp_ctrl_reg
);
2469 pps_unlock(intel_dp
);
2471 intel_dp
->last_backlight_off
= jiffies
;
2472 edp_wait_backlight_off(intel_dp
);
2475 /* Disable backlight PP control and backlight PWM. */
2476 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2478 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2480 if (!intel_dp_is_edp(intel_dp
))
2483 DRM_DEBUG_KMS("\n");
2485 _intel_edp_backlight_off(intel_dp
);
2486 intel_panel_disable_backlight(old_conn_state
);
2490 * Hook for controlling the panel power control backlight through the bl_power
2491 * sysfs attribute. Take care to handle multiple calls.
2493 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2496 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2500 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2501 pps_unlock(intel_dp
);
2503 if (is_enabled
== enable
)
2506 DRM_DEBUG_KMS("panel power control backlight %s\n",
2507 enable
? "enable" : "disable");
2510 _intel_edp_backlight_on(intel_dp
);
2512 _intel_edp_backlight_off(intel_dp
);
2515 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2517 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2518 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2519 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2521 I915_STATE_WARN(cur_state
!= state
,
2522 "DP port %c state assertion failure (expected %s, current %s)\n",
2523 port_name(dig_port
->base
.port
),
2524 onoff(state
), onoff(cur_state
));
2526 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2528 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2530 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2532 I915_STATE_WARN(cur_state
!= state
,
2533 "eDP PLL state assertion failure (expected %s, current %s)\n",
2534 onoff(state
), onoff(cur_state
));
2536 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2537 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2539 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2540 const struct intel_crtc_state
*pipe_config
)
2542 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2543 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2545 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2546 assert_dp_port_disabled(intel_dp
);
2547 assert_edp_pll_disabled(dev_priv
);
2549 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2550 pipe_config
->port_clock
);
2552 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2554 if (pipe_config
->port_clock
== 162000)
2555 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2557 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2559 I915_WRITE(DP_A
, intel_dp
->DP
);
2564 * [DevILK] Work around required when enabling DP PLL
2565 * while a pipe is enabled going to FDI:
2566 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2567 * 2. Program DP PLL enable
2569 if (IS_GEN5(dev_priv
))
2570 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2572 intel_dp
->DP
|= DP_PLL_ENABLE
;
2574 I915_WRITE(DP_A
, intel_dp
->DP
);
2579 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
,
2580 const struct intel_crtc_state
*old_crtc_state
)
2582 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
2583 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2585 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2586 assert_dp_port_disabled(intel_dp
);
2587 assert_edp_pll_enabled(dev_priv
);
2589 DRM_DEBUG_KMS("disabling eDP PLL\n");
2591 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2593 I915_WRITE(DP_A
, intel_dp
->DP
);
2598 static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp
)
2601 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2602 * be capable of signalling downstream hpd with a long pulse.
2603 * Whether or not that means D3 is safe to use is not clear,
2604 * but let's assume so until proven otherwise.
2606 * FIXME should really check all downstream ports...
2608 return intel_dp
->dpcd
[DP_DPCD_REV
] == 0x11 &&
2609 intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
&&
2610 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
;
2613 /* If the sink supports it, try to set the power state appropriately */
2614 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2618 /* Should have a valid DPCD by this point */
2619 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2622 if (mode
!= DRM_MODE_DPMS_ON
) {
2623 if (downstream_hpd_needs_d0(intel_dp
))
2626 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2629 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2632 * When turning on, we need to retry for 1ms to give the sink
2635 for (i
= 0; i
< 3; i
++) {
2636 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2643 if (ret
== 1 && lspcon
->active
)
2644 lspcon_wait_pcon_mode(lspcon
);
2648 DRM_DEBUG_KMS("failed to %s sink power state\n",
2649 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2652 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2655 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2656 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2657 enum port port
= encoder
->port
;
2661 if (!intel_display_power_get_if_enabled(dev_priv
,
2662 encoder
->power_domain
))
2667 tmp
= I915_READ(intel_dp
->output_reg
);
2669 if (!(tmp
& DP_PORT_EN
))
2672 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2673 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2674 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2677 for_each_pipe(dev_priv
, p
) {
2678 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2679 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2687 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2688 i915_mmio_reg_offset(intel_dp
->output_reg
));
2689 } else if (IS_CHERRYVIEW(dev_priv
)) {
2690 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2692 *pipe
= PORT_TO_PIPE(tmp
);
2698 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2703 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2704 struct intel_crtc_state
*pipe_config
)
2706 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2707 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2709 enum port port
= encoder
->port
;
2710 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2712 if (encoder
->type
== INTEL_OUTPUT_EDP
)
2713 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_EDP
);
2715 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_DP
);
2717 tmp
= I915_READ(intel_dp
->output_reg
);
2719 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2721 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2722 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2724 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2725 flags
|= DRM_MODE_FLAG_PHSYNC
;
2727 flags
|= DRM_MODE_FLAG_NHSYNC
;
2729 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2730 flags
|= DRM_MODE_FLAG_PVSYNC
;
2732 flags
|= DRM_MODE_FLAG_NVSYNC
;
2734 if (tmp
& DP_SYNC_HS_HIGH
)
2735 flags
|= DRM_MODE_FLAG_PHSYNC
;
2737 flags
|= DRM_MODE_FLAG_NHSYNC
;
2739 if (tmp
& DP_SYNC_VS_HIGH
)
2740 flags
|= DRM_MODE_FLAG_PVSYNC
;
2742 flags
|= DRM_MODE_FLAG_NVSYNC
;
2745 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2747 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2748 pipe_config
->limited_color_range
= true;
2750 pipe_config
->lane_count
=
2751 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2753 intel_dp_get_m_n(crtc
, pipe_config
);
2755 if (port
== PORT_A
) {
2756 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2757 pipe_config
->port_clock
= 162000;
2759 pipe_config
->port_clock
= 270000;
2762 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2763 intel_dotclock_calculate(pipe_config
->port_clock
,
2764 &pipe_config
->dp_m_n
);
2766 if (intel_dp_is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2767 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2769 * This is a big fat ugly hack.
2771 * Some machines in UEFI boot mode provide us a VBT that has 18
2772 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2773 * unknown we fail to light up. Yet the same BIOS boots up with
2774 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2775 * max, not what it tells us to use.
2777 * Note: This will still be broken if the eDP panel is not lit
2778 * up by the BIOS, and thus we can't get the mode at module
2781 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2782 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2783 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2787 static void intel_disable_dp(struct intel_encoder
*encoder
,
2788 const struct intel_crtc_state
*old_crtc_state
,
2789 const struct drm_connector_state
*old_conn_state
)
2791 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2793 intel_dp
->link_trained
= false;
2795 if (old_crtc_state
->has_audio
)
2796 intel_audio_codec_disable(encoder
,
2797 old_crtc_state
, old_conn_state
);
2799 /* Make sure the panel is off before trying to change the mode. But also
2800 * ensure that we have vdd while we switch off the panel. */
2801 intel_edp_panel_vdd_on(intel_dp
);
2802 intel_edp_backlight_off(old_conn_state
);
2803 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2804 intel_edp_panel_off(intel_dp
);
2807 static void g4x_disable_dp(struct intel_encoder
*encoder
,
2808 const struct intel_crtc_state
*old_crtc_state
,
2809 const struct drm_connector_state
*old_conn_state
)
2811 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2813 /* disable the port before the pipe on g4x */
2814 intel_dp_link_down(encoder
, old_crtc_state
);
2817 static void ilk_disable_dp(struct intel_encoder
*encoder
,
2818 const struct intel_crtc_state
*old_crtc_state
,
2819 const struct drm_connector_state
*old_conn_state
)
2821 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2824 static void vlv_disable_dp(struct intel_encoder
*encoder
,
2825 const struct intel_crtc_state
*old_crtc_state
,
2826 const struct drm_connector_state
*old_conn_state
)
2828 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2830 intel_psr_disable(intel_dp
, old_crtc_state
);
2832 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
2835 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2836 const struct intel_crtc_state
*old_crtc_state
,
2837 const struct drm_connector_state
*old_conn_state
)
2839 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2840 enum port port
= encoder
->port
;
2842 intel_dp_link_down(encoder
, old_crtc_state
);
2844 /* Only ilk+ has port A */
2846 ironlake_edp_pll_off(intel_dp
, old_crtc_state
);
2849 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2850 const struct intel_crtc_state
*old_crtc_state
,
2851 const struct drm_connector_state
*old_conn_state
)
2853 intel_dp_link_down(encoder
, old_crtc_state
);
2856 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2857 const struct intel_crtc_state
*old_crtc_state
,
2858 const struct drm_connector_state
*old_conn_state
)
2860 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2862 intel_dp_link_down(encoder
, old_crtc_state
);
2864 mutex_lock(&dev_priv
->sb_lock
);
2866 /* Assert data lane reset */
2867 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
2869 mutex_unlock(&dev_priv
->sb_lock
);
2873 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2875 uint8_t dp_train_pat
)
2877 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2878 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2879 enum port port
= intel_dig_port
->base
.port
;
2881 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2882 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2883 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2885 if (HAS_DDI(dev_priv
)) {
2886 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2888 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2889 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2891 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2893 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2894 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2895 case DP_TRAINING_PATTERN_DISABLE
:
2896 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2899 case DP_TRAINING_PATTERN_1
:
2900 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2902 case DP_TRAINING_PATTERN_2
:
2903 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2905 case DP_TRAINING_PATTERN_3
:
2906 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2909 I915_WRITE(DP_TP_CTL(port
), temp
);
2911 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2912 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2913 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2915 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2916 case DP_TRAINING_PATTERN_DISABLE
:
2917 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2919 case DP_TRAINING_PATTERN_1
:
2920 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2922 case DP_TRAINING_PATTERN_2
:
2923 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2925 case DP_TRAINING_PATTERN_3
:
2926 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2927 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2932 *DP
&= ~DP_LINK_TRAIN_MASK
;
2934 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2935 case DP_TRAINING_PATTERN_DISABLE
:
2936 *DP
|= DP_LINK_TRAIN_OFF
;
2938 case DP_TRAINING_PATTERN_1
:
2939 *DP
|= DP_LINK_TRAIN_PAT_1
;
2941 case DP_TRAINING_PATTERN_2
:
2942 *DP
|= DP_LINK_TRAIN_PAT_2
;
2944 case DP_TRAINING_PATTERN_3
:
2945 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2946 *DP
|= DP_LINK_TRAIN_PAT_2
;
2952 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2953 const struct intel_crtc_state
*old_crtc_state
)
2955 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2957 /* enable with pattern 1 (as per spec) */
2959 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2962 * Magic for VLV/CHV. We _must_ first set up the register
2963 * without actually enabling the port, and then do another
2964 * write to enable the port. Otherwise link training will
2965 * fail when the power sequencer is freshly used for this port.
2967 intel_dp
->DP
|= DP_PORT_EN
;
2968 if (old_crtc_state
->has_audio
)
2969 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2971 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2972 POSTING_READ(intel_dp
->output_reg
);
2975 static void intel_enable_dp(struct intel_encoder
*encoder
,
2976 const struct intel_crtc_state
*pipe_config
,
2977 const struct drm_connector_state
*conn_state
)
2979 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2980 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2981 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2982 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2983 enum pipe pipe
= crtc
->pipe
;
2985 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2990 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2991 vlv_init_panel_power_sequencer(encoder
, pipe_config
);
2993 intel_dp_enable_port(intel_dp
, pipe_config
);
2995 edp_panel_vdd_on(intel_dp
);
2996 edp_panel_on(intel_dp
);
2997 edp_panel_vdd_off(intel_dp
, true);
2999 pps_unlock(intel_dp
);
3001 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3002 unsigned int lane_mask
= 0x0;
3004 if (IS_CHERRYVIEW(dev_priv
))
3005 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
3007 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
3011 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
3012 intel_dp_start_link_train(intel_dp
);
3013 intel_dp_stop_link_train(intel_dp
);
3015 if (pipe_config
->has_audio
) {
3016 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3018 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
3022 static void g4x_enable_dp(struct intel_encoder
*encoder
,
3023 const struct intel_crtc_state
*pipe_config
,
3024 const struct drm_connector_state
*conn_state
)
3026 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3027 intel_edp_backlight_on(pipe_config
, conn_state
);
3030 static void vlv_enable_dp(struct intel_encoder
*encoder
,
3031 const struct intel_crtc_state
*pipe_config
,
3032 const struct drm_connector_state
*conn_state
)
3034 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3036 intel_edp_backlight_on(pipe_config
, conn_state
);
3037 intel_psr_enable(intel_dp
, pipe_config
);
3040 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
3041 const struct intel_crtc_state
*pipe_config
,
3042 const struct drm_connector_state
*conn_state
)
3044 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3045 enum port port
= encoder
->port
;
3047 intel_dp_prepare(encoder
, pipe_config
);
3049 /* Only ilk+ has port A */
3051 ironlake_edp_pll_on(intel_dp
, pipe_config
);
3054 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
3056 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3057 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
3058 enum pipe pipe
= intel_dp
->pps_pipe
;
3059 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
3061 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3063 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
3066 edp_panel_vdd_off_sync(intel_dp
);
3069 * VLV seems to get confused when multiple power seqeuencers
3070 * have the same port selected (even if only one has power/vdd
3071 * enabled). The failure manifests as vlv_wait_port_ready() failing
3072 * CHV on the other hand doesn't seem to mind having the same port
3073 * selected in multiple power seqeuencers, but let's clear the
3074 * port select always when logically disconnecting a power sequencer
3077 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3078 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
3079 I915_WRITE(pp_on_reg
, 0);
3080 POSTING_READ(pp_on_reg
);
3082 intel_dp
->pps_pipe
= INVALID_PIPE
;
3085 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
3088 struct intel_encoder
*encoder
;
3090 lockdep_assert_held(&dev_priv
->pps_mutex
);
3092 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
3093 struct intel_dp
*intel_dp
;
3096 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
3097 encoder
->type
!= INTEL_OUTPUT_EDP
)
3100 intel_dp
= enc_to_intel_dp(&encoder
->base
);
3101 port
= dp_to_dig_port(intel_dp
)->base
.port
;
3103 WARN(intel_dp
->active_pipe
== pipe
,
3104 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3105 pipe_name(pipe
), port_name(port
));
3107 if (intel_dp
->pps_pipe
!= pipe
)
3110 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3111 pipe_name(pipe
), port_name(port
));
3113 /* make sure vdd is off before we steal it */
3114 vlv_detach_power_sequencer(intel_dp
);
3118 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
3119 const struct intel_crtc_state
*crtc_state
)
3121 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3122 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3123 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3125 lockdep_assert_held(&dev_priv
->pps_mutex
);
3127 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3129 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3130 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3132 * If another power sequencer was being used on this
3133 * port previously make sure to turn off vdd there while
3134 * we still have control of it.
3136 vlv_detach_power_sequencer(intel_dp
);
3140 * We may be stealing the power
3141 * sequencer from another port.
3143 vlv_steal_power_sequencer(dev_priv
, crtc
->pipe
);
3145 intel_dp
->active_pipe
= crtc
->pipe
;
3147 if (!intel_dp_is_edp(intel_dp
))
3150 /* now it's all ours */
3151 intel_dp
->pps_pipe
= crtc
->pipe
;
3153 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3154 pipe_name(intel_dp
->pps_pipe
), port_name(encoder
->port
));
3156 /* init power sequencer on this pipe and port */
3157 intel_dp_init_panel_power_sequencer(intel_dp
);
3158 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
3161 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3162 const struct intel_crtc_state
*pipe_config
,
3163 const struct drm_connector_state
*conn_state
)
3165 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
3167 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3170 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3171 const struct intel_crtc_state
*pipe_config
,
3172 const struct drm_connector_state
*conn_state
)
3174 intel_dp_prepare(encoder
, pipe_config
);
3176 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
3179 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3180 const struct intel_crtc_state
*pipe_config
,
3181 const struct drm_connector_state
*conn_state
)
3183 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
3185 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3187 /* Second common lane will stay alive on its own now */
3188 chv_phy_release_cl2_override(encoder
);
3191 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3192 const struct intel_crtc_state
*pipe_config
,
3193 const struct drm_connector_state
*conn_state
)
3195 intel_dp_prepare(encoder
, pipe_config
);
3197 chv_phy_pre_pll_enable(encoder
, pipe_config
);
3200 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3201 const struct intel_crtc_state
*old_crtc_state
,
3202 const struct drm_connector_state
*old_conn_state
)
3204 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
3208 * Fetch AUX CH registers 0x202 - 0x207 which contain
3209 * link status information
3212 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3214 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3215 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3218 /* These are source-specific values. */
3220 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3222 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3223 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
3225 if (INTEL_GEN(dev_priv
) >= 9) {
3226 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3227 return intel_ddi_dp_voltage_max(encoder
);
3228 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3229 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3230 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3231 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3232 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3233 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3235 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3239 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3241 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3242 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
3244 if (INTEL_GEN(dev_priv
) >= 9) {
3245 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3247 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3249 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3251 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3253 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3255 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3257 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3258 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3260 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3262 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3264 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3267 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3269 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3270 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3272 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3274 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3276 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3279 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3281 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3282 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3284 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3287 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3289 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3292 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3294 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3296 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3298 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3301 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3306 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3308 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3309 unsigned long demph_reg_value
, preemph_reg_value
,
3310 uniqtranscale_reg_value
;
3311 uint8_t train_set
= intel_dp
->train_set
[0];
3313 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3314 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3315 preemph_reg_value
= 0x0004000;
3316 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3318 demph_reg_value
= 0x2B405555;
3319 uniqtranscale_reg_value
= 0x552AB83A;
3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3322 demph_reg_value
= 0x2B404040;
3323 uniqtranscale_reg_value
= 0x5548B83A;
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3326 demph_reg_value
= 0x2B245555;
3327 uniqtranscale_reg_value
= 0x5560B83A;
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3330 demph_reg_value
= 0x2B405555;
3331 uniqtranscale_reg_value
= 0x5598DA3A;
3337 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3338 preemph_reg_value
= 0x0002000;
3339 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3341 demph_reg_value
= 0x2B404040;
3342 uniqtranscale_reg_value
= 0x5552B83A;
3344 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3345 demph_reg_value
= 0x2B404848;
3346 uniqtranscale_reg_value
= 0x5580B83A;
3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3349 demph_reg_value
= 0x2B404040;
3350 uniqtranscale_reg_value
= 0x55ADDA3A;
3356 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3357 preemph_reg_value
= 0x0000000;
3358 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3360 demph_reg_value
= 0x2B305555;
3361 uniqtranscale_reg_value
= 0x5570B83A;
3363 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3364 demph_reg_value
= 0x2B2B4040;
3365 uniqtranscale_reg_value
= 0x55ADDA3A;
3371 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3372 preemph_reg_value
= 0x0006000;
3373 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3375 demph_reg_value
= 0x1B405555;
3376 uniqtranscale_reg_value
= 0x55ADDA3A;
3386 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3387 uniqtranscale_reg_value
, 0);
3392 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3394 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3395 u32 deemph_reg_value
, margin_reg_value
;
3396 bool uniq_trans_scale
= false;
3397 uint8_t train_set
= intel_dp
->train_set
[0];
3399 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3400 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3401 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3402 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3403 deemph_reg_value
= 128;
3404 margin_reg_value
= 52;
3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3407 deemph_reg_value
= 128;
3408 margin_reg_value
= 77;
3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3411 deemph_reg_value
= 128;
3412 margin_reg_value
= 102;
3414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3415 deemph_reg_value
= 128;
3416 margin_reg_value
= 154;
3417 uniq_trans_scale
= true;
3423 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3424 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3426 deemph_reg_value
= 85;
3427 margin_reg_value
= 78;
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3430 deemph_reg_value
= 85;
3431 margin_reg_value
= 116;
3433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3434 deemph_reg_value
= 85;
3435 margin_reg_value
= 154;
3441 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3442 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3444 deemph_reg_value
= 64;
3445 margin_reg_value
= 104;
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3448 deemph_reg_value
= 64;
3449 margin_reg_value
= 154;
3455 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3456 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3458 deemph_reg_value
= 43;
3459 margin_reg_value
= 154;
3469 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3470 margin_reg_value
, uniq_trans_scale
);
3476 gen4_signal_levels(uint8_t train_set
)
3478 uint32_t signal_levels
= 0;
3480 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3481 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3483 signal_levels
|= DP_VOLTAGE_0_4
;
3485 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3486 signal_levels
|= DP_VOLTAGE_0_6
;
3488 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3489 signal_levels
|= DP_VOLTAGE_0_8
;
3491 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3492 signal_levels
|= DP_VOLTAGE_1_2
;
3495 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3496 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3498 signal_levels
|= DP_PRE_EMPHASIS_0
;
3500 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3501 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3503 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3504 signal_levels
|= DP_PRE_EMPHASIS_6
;
3506 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3507 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3510 return signal_levels
;
3513 /* Gen6's DP voltage swing and pre-emphasis control */
3515 gen6_edp_signal_levels(uint8_t train_set
)
3517 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3518 DP_TRAIN_PRE_EMPHASIS_MASK
);
3519 switch (signal_levels
) {
3520 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3521 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3522 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3523 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3524 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3527 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3530 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3531 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3533 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3535 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3536 "0x%x\n", signal_levels
);
3537 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3541 /* Gen7's DP voltage swing and pre-emphasis control */
3543 gen7_edp_signal_levels(uint8_t train_set
)
3545 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3546 DP_TRAIN_PRE_EMPHASIS_MASK
);
3547 switch (signal_levels
) {
3548 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3549 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3550 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3551 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3552 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3553 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3555 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3556 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3557 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3558 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3560 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3561 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3562 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3563 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3566 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3567 "0x%x\n", signal_levels
);
3568 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3573 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3575 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3576 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3577 enum port port
= intel_dig_port
->base
.port
;
3578 uint32_t signal_levels
, mask
= 0;
3579 uint8_t train_set
= intel_dp
->train_set
[0];
3581 if (IS_GEN9_LP(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
3582 signal_levels
= bxt_signal_levels(intel_dp
);
3583 } else if (HAS_DDI(dev_priv
)) {
3584 signal_levels
= ddi_signal_levels(intel_dp
);
3585 mask
= DDI_BUF_EMP_MASK
;
3586 } else if (IS_CHERRYVIEW(dev_priv
)) {
3587 signal_levels
= chv_signal_levels(intel_dp
);
3588 } else if (IS_VALLEYVIEW(dev_priv
)) {
3589 signal_levels
= vlv_signal_levels(intel_dp
);
3590 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3591 signal_levels
= gen7_edp_signal_levels(train_set
);
3592 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3593 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3594 signal_levels
= gen6_edp_signal_levels(train_set
);
3595 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3597 signal_levels
= gen4_signal_levels(train_set
);
3598 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3602 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3604 DRM_DEBUG_KMS("Using vswing level %d\n",
3605 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3606 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3607 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3608 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3610 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3612 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3613 POSTING_READ(intel_dp
->output_reg
);
3617 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3618 uint8_t dp_train_pat
)
3620 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3621 struct drm_i915_private
*dev_priv
=
3622 to_i915(intel_dig_port
->base
.base
.dev
);
3624 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3626 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3627 POSTING_READ(intel_dp
->output_reg
);
3630 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3632 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3633 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3634 enum port port
= intel_dig_port
->base
.port
;
3637 if (!HAS_DDI(dev_priv
))
3640 val
= I915_READ(DP_TP_CTL(port
));
3641 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3642 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3643 I915_WRITE(DP_TP_CTL(port
), val
);
3646 * On PORT_A we can have only eDP in SST mode. There the only reason
3647 * we need to set idle transmission mode is to work around a HW issue
3648 * where we enable the pipe while not in idle link-training mode.
3649 * In this case there is requirement to wait for a minimum number of
3650 * idle patterns to be sent.
3655 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3656 DP_TP_STATUS_IDLE_DONE
,
3657 DP_TP_STATUS_IDLE_DONE
,
3659 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3663 intel_dp_link_down(struct intel_encoder
*encoder
,
3664 const struct intel_crtc_state
*old_crtc_state
)
3666 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3667 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3668 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
3669 enum port port
= encoder
->port
;
3670 uint32_t DP
= intel_dp
->DP
;
3672 if (WARN_ON(HAS_DDI(dev_priv
)))
3675 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3678 DRM_DEBUG_KMS("\n");
3680 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3681 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3682 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3683 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3685 DP
&= ~DP_LINK_TRAIN_MASK
;
3686 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3688 I915_WRITE(intel_dp
->output_reg
, DP
);
3689 POSTING_READ(intel_dp
->output_reg
);
3691 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3692 I915_WRITE(intel_dp
->output_reg
, DP
);
3693 POSTING_READ(intel_dp
->output_reg
);
3696 * HW workaround for IBX, we need to move the port
3697 * to transcoder A after disabling it to allow the
3698 * matching HDMI port to be enabled on transcoder A.
3700 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3702 * We get CPU/PCH FIFO underruns on the other pipe when
3703 * doing the workaround. Sweep them under the rug.
3705 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3706 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3708 /* always enable with pattern 1 (as per spec) */
3709 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3710 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3711 I915_WRITE(intel_dp
->output_reg
, DP
);
3712 POSTING_READ(intel_dp
->output_reg
);
3715 I915_WRITE(intel_dp
->output_reg
, DP
);
3716 POSTING_READ(intel_dp
->output_reg
);
3718 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3719 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3720 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3723 msleep(intel_dp
->panel_power_down_delay
);
3727 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3729 intel_dp
->active_pipe
= INVALID_PIPE
;
3730 pps_unlock(intel_dp
);
3735 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3737 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3738 sizeof(intel_dp
->dpcd
)) < 0)
3739 return false; /* aux transfer failed */
3741 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3743 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3747 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3749 struct drm_i915_private
*dev_priv
=
3750 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3752 /* this function is meant to be called only once */
3753 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3755 if (!intel_dp_read_dpcd(intel_dp
))
3758 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
3759 drm_dp_is_branch(intel_dp
->dpcd
));
3761 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3762 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3763 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3765 intel_psr_init_dpcd(intel_dp
);
3768 * Read the eDP display control registers.
3770 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3771 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3772 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3773 * method). The display control registers should read zero if they're
3774 * not supported anyway.
3776 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3777 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3778 sizeof(intel_dp
->edp_dpcd
))
3779 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3780 intel_dp
->edp_dpcd
);
3782 /* Read the eDP 1.4+ supported link rates. */
3783 if (intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
3784 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3787 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3788 sink_rates
, sizeof(sink_rates
));
3790 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3791 int val
= le16_to_cpu(sink_rates
[i
]);
3796 /* Value read multiplied by 200kHz gives the per-lane
3797 * link rate in kHz. The source rates are, however,
3798 * stored in terms of LS_Clk kHz. The full conversion
3799 * back to symbols is
3800 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3802 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3804 intel_dp
->num_sink_rates
= i
;
3808 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3809 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3811 if (intel_dp
->num_sink_rates
)
3812 intel_dp
->use_rate_select
= true;
3814 intel_dp_set_sink_rates(intel_dp
);
3816 intel_dp_set_common_rates(intel_dp
);
3823 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3827 if (!intel_dp_read_dpcd(intel_dp
))
3830 /* Don't clobber cached eDP rates. */
3831 if (!intel_dp_is_edp(intel_dp
)) {
3832 intel_dp_set_sink_rates(intel_dp
);
3833 intel_dp_set_common_rates(intel_dp
);
3836 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &sink_count
) <= 0)
3840 * Sink count can change between short pulse hpd hence
3841 * a member variable in intel_dp will track any changes
3842 * between short pulse interrupts.
3844 intel_dp
->sink_count
= DP_GET_SINK_COUNT(sink_count
);
3847 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3848 * a dongle is present but no display. Unless we require to know
3849 * if a dongle is present or not, we don't need to update
3850 * downstream port information. So, an early return here saves
3851 * time from performing other operations which are not required.
3853 if (!intel_dp_is_edp(intel_dp
) && !intel_dp
->sink_count
)
3856 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3857 return true; /* native DP sink */
3859 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3860 return true; /* no per-port downstream info */
3862 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3863 intel_dp
->downstream_ports
,
3864 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3865 return false; /* downstream port status fetch failed */
3871 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3875 if (!i915_modparams
.enable_dp_mst
)
3878 if (!intel_dp
->can_mst
)
3881 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3884 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
3887 return mstm_cap
& DP_MST_CAP
;
3891 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3893 if (!i915_modparams
.enable_dp_mst
)
3896 if (!intel_dp
->can_mst
)
3899 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3901 if (intel_dp
->is_mst
)
3902 DRM_DEBUG_KMS("Sink is MST capable\n");
3904 DRM_DEBUG_KMS("Sink is not MST capable\n");
3906 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3910 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
,
3911 struct intel_crtc_state
*crtc_state
, bool disable_wa
)
3913 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3914 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3915 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3921 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3922 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3927 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3928 buf
& ~DP_TEST_SINK_START
) < 0) {
3929 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3935 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3937 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3938 DP_TEST_SINK_MISC
, &buf
) < 0) {
3942 count
= buf
& DP_TEST_COUNT_MASK
;
3943 } while (--attempts
&& count
);
3945 if (attempts
== 0) {
3946 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3952 hsw_enable_ips(crtc_state
);
3956 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
,
3957 struct intel_crtc_state
*crtc_state
)
3959 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3960 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3961 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3965 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3968 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3971 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3974 if (buf
& DP_TEST_SINK_START
) {
3975 ret
= intel_dp_sink_crc_stop(intel_dp
, crtc_state
, false);
3980 hsw_disable_ips(crtc_state
);
3982 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3983 buf
| DP_TEST_SINK_START
) < 0) {
3984 hsw_enable_ips(crtc_state
);
3988 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3992 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, struct intel_crtc_state
*crtc_state
, u8
*crc
)
3994 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3995 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3996 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4001 ret
= intel_dp_sink_crc_start(intel_dp
, crtc_state
);
4006 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
4008 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4009 DP_TEST_SINK_MISC
, &buf
) < 0) {
4013 count
= buf
& DP_TEST_COUNT_MASK
;
4015 } while (--attempts
&& count
== 0);
4017 if (attempts
== 0) {
4018 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4023 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4029 intel_dp_sink_crc_stop(intel_dp
, crtc_state
, true);
4034 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4036 return drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
4037 sink_irq_vector
) == 1;
4041 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4043 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT_ESI
,
4044 sink_irq_vector
, DP_DPRX_ESI_LEN
) ==
4048 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4052 uint8_t test_lane_count
, test_link_bw
;
4056 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4057 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4061 DRM_DEBUG_KMS("Lane count read failed\n");
4064 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4066 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4069 DRM_DEBUG_KMS("Link Rate read failed\n");
4072 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4074 /* Validate the requested link rate and lane count */
4075 if (!intel_dp_link_params_valid(intel_dp
, test_link_rate
,
4079 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4080 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4085 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4087 uint8_t test_pattern
;
4089 __be16 h_width
, v_height
;
4092 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4093 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4096 DRM_DEBUG_KMS("Test pattern read failed\n");
4099 if (test_pattern
!= DP_COLOR_RAMP
)
4102 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4105 DRM_DEBUG_KMS("H Width read failed\n");
4109 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4112 DRM_DEBUG_KMS("V Height read failed\n");
4116 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4119 DRM_DEBUG_KMS("TEST MISC read failed\n");
4122 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4124 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4126 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4127 case DP_TEST_BIT_DEPTH_6
:
4128 intel_dp
->compliance
.test_data
.bpc
= 6;
4130 case DP_TEST_BIT_DEPTH_8
:
4131 intel_dp
->compliance
.test_data
.bpc
= 8;
4137 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4138 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4139 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4140 /* Set test active flag here so userspace doesn't interrupt things */
4141 intel_dp
->compliance
.test_active
= 1;
4146 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4148 uint8_t test_result
= DP_TEST_ACK
;
4149 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4150 struct drm_connector
*connector
= &intel_connector
->base
;
4152 if (intel_connector
->detect_edid
== NULL
||
4153 connector
->edid_corrupt
||
4154 intel_dp
->aux
.i2c_defer_count
> 6) {
4155 /* Check EDID read for NACKs, DEFERs and corruption
4156 * (DP CTS 1.2 Core r1.1)
4157 * 4.2.2.4 : Failed EDID read, I2C_NAK
4158 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4159 * 4.2.2.6 : EDID corruption detected
4160 * Use failsafe mode for all cases
4162 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4163 intel_dp
->aux
.i2c_defer_count
> 0)
4164 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4165 intel_dp
->aux
.i2c_nack_count
,
4166 intel_dp
->aux
.i2c_defer_count
);
4167 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4169 struct edid
*block
= intel_connector
->detect_edid
;
4171 /* We have to write the checksum
4172 * of the last block read
4174 block
+= intel_connector
->detect_edid
->extensions
;
4176 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4177 block
->checksum
) <= 0)
4178 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4180 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4181 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4184 /* Set test active flag here so userspace doesn't interrupt things */
4185 intel_dp
->compliance
.test_active
= 1;
4190 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4192 uint8_t test_result
= DP_TEST_NAK
;
4196 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4198 uint8_t response
= DP_TEST_NAK
;
4199 uint8_t request
= 0;
4202 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4204 DRM_DEBUG_KMS("Could not read test request from sink\n");
4209 case DP_TEST_LINK_TRAINING
:
4210 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4211 response
= intel_dp_autotest_link_training(intel_dp
);
4213 case DP_TEST_LINK_VIDEO_PATTERN
:
4214 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4215 response
= intel_dp_autotest_video_pattern(intel_dp
);
4217 case DP_TEST_LINK_EDID_READ
:
4218 DRM_DEBUG_KMS("EDID test requested\n");
4219 response
= intel_dp_autotest_edid(intel_dp
);
4221 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4222 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4223 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4226 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4230 if (response
& DP_TEST_ACK
)
4231 intel_dp
->compliance
.test_type
= request
;
4234 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4236 DRM_DEBUG_KMS("Could not write test response to sink\n");
4240 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4244 if (intel_dp
->is_mst
) {
4245 u8 esi
[DP_DPRX_ESI_LEN
] = { 0 };
4249 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4253 /* check link status - esi[10] = 0x200c */
4254 if (intel_dp
->active_mst_links
&&
4255 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4256 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4257 intel_dp_start_link_train(intel_dp
);
4258 intel_dp_stop_link_train(intel_dp
);
4261 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4262 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4265 for (retry
= 0; retry
< 3; retry
++) {
4267 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4268 DP_SINK_COUNT_ESI
+1,
4275 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4277 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4285 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4286 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4287 intel_dp
->is_mst
= false;
4288 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4289 /* send a hotplug event */
4290 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4297 intel_dp_needs_link_retrain(struct intel_dp
*intel_dp
)
4299 u8 link_status
[DP_LINK_STATUS_SIZE
];
4301 if (!intel_dp
->link_trained
)
4304 if (!intel_dp_get_link_status(intel_dp
, link_status
))
4308 * Validate the cached values of intel_dp->link_rate and
4309 * intel_dp->lane_count before attempting to retrain.
4311 if (!intel_dp_link_params_valid(intel_dp
, intel_dp
->link_rate
,
4312 intel_dp
->lane_count
))
4315 /* Retrain if Channel EQ or CR not ok */
4316 return !drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
);
4320 * If display is now connected check links status,
4321 * there has been known issues of link loss triggering
4324 * Some sinks (eg. ASUS PB287Q) seem to perform some
4325 * weird HPD ping pong during modesets. So we can apparently
4326 * end up with HPD going low during a modeset, and then
4327 * going back up soon after. And once that happens we must
4328 * retrain the link to get a picture. That's in case no
4329 * userspace component reacted to intermittent HPD dip.
4331 int intel_dp_retrain_link(struct intel_encoder
*encoder
,
4332 struct drm_modeset_acquire_ctx
*ctx
)
4334 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4335 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
4336 struct intel_connector
*connector
= intel_dp
->attached_connector
;
4337 struct drm_connector_state
*conn_state
;
4338 struct intel_crtc_state
*crtc_state
;
4339 struct intel_crtc
*crtc
;
4342 /* FIXME handle the MST connectors as well */
4344 if (!connector
|| connector
->base
.status
!= connector_status_connected
)
4347 ret
= drm_modeset_lock(&dev_priv
->drm
.mode_config
.connection_mutex
,
4352 conn_state
= connector
->base
.state
;
4354 crtc
= to_intel_crtc(conn_state
->crtc
);
4358 ret
= drm_modeset_lock(&crtc
->base
.mutex
, ctx
);
4362 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
4364 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state
));
4366 if (!crtc_state
->base
.active
)
4369 if (conn_state
->commit
&&
4370 !try_wait_for_completion(&conn_state
->commit
->hw_done
))
4373 if (!intel_dp_needs_link_retrain(intel_dp
))
4376 /* Suppress underruns caused by re-training */
4377 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4378 if (crtc
->config
->has_pch_encoder
)
4379 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4380 intel_crtc_pch_transcoder(crtc
), false);
4382 intel_dp_start_link_train(intel_dp
);
4383 intel_dp_stop_link_train(intel_dp
);
4385 /* Keep underrun reporting disabled until things are stable */
4386 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4388 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4389 if (crtc
->config
->has_pch_encoder
)
4390 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4391 intel_crtc_pch_transcoder(crtc
), true);
4397 * If display is now connected check links status,
4398 * there has been known issues of link loss triggering
4401 * Some sinks (eg. ASUS PB287Q) seem to perform some
4402 * weird HPD ping pong during modesets. So we can apparently
4403 * end up with HPD going low during a modeset, and then
4404 * going back up soon after. And once that happens we must
4405 * retrain the link to get a picture. That's in case no
4406 * userspace component reacted to intermittent HPD dip.
4408 static bool intel_dp_hotplug(struct intel_encoder
*encoder
,
4409 struct intel_connector
*connector
)
4411 struct drm_modeset_acquire_ctx ctx
;
4415 changed
= intel_encoder_hotplug(encoder
, connector
);
4417 drm_modeset_acquire_init(&ctx
, 0);
4420 ret
= intel_dp_retrain_link(encoder
, &ctx
);
4422 if (ret
== -EDEADLK
) {
4423 drm_modeset_backoff(&ctx
);
4430 drm_modeset_drop_locks(&ctx
);
4431 drm_modeset_acquire_fini(&ctx
);
4432 WARN(ret
, "Acquiring modeset locks failed with %i\n", ret
);
4438 * According to DP spec
4441 * 2. Configure link according to Receiver Capabilities
4442 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4443 * 4. Check link status on receipt of hot-plug interrupt
4445 * intel_dp_short_pulse - handles short pulse interrupts
4446 * when full detection is not required.
4447 * Returns %true if short pulse is handled and full detection
4448 * is NOT required and %false otherwise.
4451 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4453 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4454 u8 sink_irq_vector
= 0;
4455 u8 old_sink_count
= intel_dp
->sink_count
;
4459 * Clearing compliance test variables to allow capturing
4460 * of values for next automated test request.
4462 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4465 * Now read the DPCD to see if it's actually running
4466 * If the current value of sink count doesn't match with
4467 * the value that was stored earlier or dpcd read failed
4468 * we need to do full detection
4470 ret
= intel_dp_get_dpcd(intel_dp
);
4472 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4473 /* No need to proceed if we are going to do full detect */
4477 /* Try to read the source of the interrupt */
4478 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4479 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4480 sink_irq_vector
!= 0) {
4481 /* Clear interrupt source */
4482 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4483 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4486 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4487 intel_dp_handle_test_request(intel_dp
);
4488 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4489 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4492 /* defer to the hotplug work for link retraining if needed */
4493 if (intel_dp_needs_link_retrain(intel_dp
))
4496 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4497 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4498 /* Send a Hotplug Uevent to userspace to start modeset */
4499 drm_kms_helper_hotplug_event(&dev_priv
->drm
);
4505 /* XXX this is probably wrong for multiple downstream ports */
4506 static enum drm_connector_status
4507 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4509 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4510 uint8_t *dpcd
= intel_dp
->dpcd
;
4514 lspcon_resume(lspcon
);
4516 if (!intel_dp_get_dpcd(intel_dp
))
4517 return connector_status_disconnected
;
4519 if (intel_dp_is_edp(intel_dp
))
4520 return connector_status_connected
;
4522 /* if there's no downstream port, we're done */
4523 if (!drm_dp_is_branch(dpcd
))
4524 return connector_status_connected
;
4526 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4527 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4528 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4530 return intel_dp
->sink_count
?
4531 connector_status_connected
: connector_status_disconnected
;
4534 if (intel_dp_can_mst(intel_dp
))
4535 return connector_status_connected
;
4537 /* If no HPD, poke DDC gently */
4538 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4539 return connector_status_connected
;
4541 /* Well we tried, say unknown for unreliable port types */
4542 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4543 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4544 if (type
== DP_DS_PORT_TYPE_VGA
||
4545 type
== DP_DS_PORT_TYPE_NON_EDID
)
4546 return connector_status_unknown
;
4548 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4549 DP_DWN_STRM_PORT_TYPE_MASK
;
4550 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4551 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4552 return connector_status_unknown
;
4555 /* Anything else is out of spec, warn and ignore */
4556 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4557 return connector_status_disconnected
;
4560 static enum drm_connector_status
4561 edp_detect(struct intel_dp
*intel_dp
)
4563 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4564 enum drm_connector_status status
;
4566 status
= intel_panel_detect(dev_priv
);
4567 if (status
== connector_status_unknown
)
4568 status
= connector_status_connected
;
4573 static bool ibx_digital_port_connected(struct intel_encoder
*encoder
)
4575 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4578 switch (encoder
->hpd_pin
) {
4580 bit
= SDE_PORTB_HOTPLUG
;
4583 bit
= SDE_PORTC_HOTPLUG
;
4586 bit
= SDE_PORTD_HOTPLUG
;
4589 MISSING_CASE(encoder
->hpd_pin
);
4593 return I915_READ(SDEISR
) & bit
;
4596 static bool cpt_digital_port_connected(struct intel_encoder
*encoder
)
4598 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4601 switch (encoder
->hpd_pin
) {
4603 bit
= SDE_PORTB_HOTPLUG_CPT
;
4606 bit
= SDE_PORTC_HOTPLUG_CPT
;
4609 bit
= SDE_PORTD_HOTPLUG_CPT
;
4612 MISSING_CASE(encoder
->hpd_pin
);
4616 return I915_READ(SDEISR
) & bit
;
4619 static bool spt_digital_port_connected(struct intel_encoder
*encoder
)
4621 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4624 switch (encoder
->hpd_pin
) {
4626 bit
= SDE_PORTA_HOTPLUG_SPT
;
4629 bit
= SDE_PORTE_HOTPLUG_SPT
;
4632 return cpt_digital_port_connected(encoder
);
4635 return I915_READ(SDEISR
) & bit
;
4638 static bool g4x_digital_port_connected(struct intel_encoder
*encoder
)
4640 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4643 switch (encoder
->hpd_pin
) {
4645 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4648 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4651 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4654 MISSING_CASE(encoder
->hpd_pin
);
4658 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4661 static bool gm45_digital_port_connected(struct intel_encoder
*encoder
)
4663 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4666 switch (encoder
->hpd_pin
) {
4668 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4671 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4674 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4677 MISSING_CASE(encoder
->hpd_pin
);
4681 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4684 static bool ilk_digital_port_connected(struct intel_encoder
*encoder
)
4686 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4688 if (encoder
->hpd_pin
== HPD_PORT_A
)
4689 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4691 return ibx_digital_port_connected(encoder
);
4694 static bool snb_digital_port_connected(struct intel_encoder
*encoder
)
4696 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4698 if (encoder
->hpd_pin
== HPD_PORT_A
)
4699 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4701 return cpt_digital_port_connected(encoder
);
4704 static bool ivb_digital_port_connected(struct intel_encoder
*encoder
)
4706 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4708 if (encoder
->hpd_pin
== HPD_PORT_A
)
4709 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
4711 return cpt_digital_port_connected(encoder
);
4714 static bool bdw_digital_port_connected(struct intel_encoder
*encoder
)
4716 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4718 if (encoder
->hpd_pin
== HPD_PORT_A
)
4719 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
4721 return cpt_digital_port_connected(encoder
);
4724 static bool bxt_digital_port_connected(struct intel_encoder
*encoder
)
4726 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4729 switch (encoder
->hpd_pin
) {
4731 bit
= BXT_DE_PORT_HP_DDIA
;
4734 bit
= BXT_DE_PORT_HP_DDIB
;
4737 bit
= BXT_DE_PORT_HP_DDIC
;
4740 MISSING_CASE(encoder
->hpd_pin
);
4744 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4748 * intel_digital_port_connected - is the specified port connected?
4749 * @encoder: intel_encoder
4751 * Return %true if port is connected, %false otherwise.
4753 bool intel_digital_port_connected(struct intel_encoder
*encoder
)
4755 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4757 if (HAS_GMCH_DISPLAY(dev_priv
)) {
4758 if (IS_GM45(dev_priv
))
4759 return gm45_digital_port_connected(encoder
);
4761 return g4x_digital_port_connected(encoder
);
4764 if (IS_GEN5(dev_priv
))
4765 return ilk_digital_port_connected(encoder
);
4766 else if (IS_GEN6(dev_priv
))
4767 return snb_digital_port_connected(encoder
);
4768 else if (IS_GEN7(dev_priv
))
4769 return ivb_digital_port_connected(encoder
);
4770 else if (IS_GEN8(dev_priv
))
4771 return bdw_digital_port_connected(encoder
);
4772 else if (IS_GEN9_LP(dev_priv
))
4773 return bxt_digital_port_connected(encoder
);
4775 return spt_digital_port_connected(encoder
);
4778 static struct edid
*
4779 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4781 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4783 /* use cached edid if we have one */
4784 if (intel_connector
->edid
) {
4786 if (IS_ERR(intel_connector
->edid
))
4789 return drm_edid_duplicate(intel_connector
->edid
);
4791 return drm_get_edid(&intel_connector
->base
,
4792 &intel_dp
->aux
.ddc
);
4796 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4798 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4801 intel_dp_unset_edid(intel_dp
);
4802 edid
= intel_dp_get_edid(intel_dp
);
4803 intel_connector
->detect_edid
= edid
;
4805 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4809 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4811 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4813 kfree(intel_connector
->detect_edid
);
4814 intel_connector
->detect_edid
= NULL
;
4816 intel_dp
->has_audio
= false;
4820 intel_dp_long_pulse(struct intel_connector
*connector
)
4822 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
4823 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
4824 enum drm_connector_status status
;
4825 u8 sink_irq_vector
= 0;
4827 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
4829 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4831 /* Can't disconnect eDP, but you can close the lid... */
4832 if (intel_dp_is_edp(intel_dp
))
4833 status
= edp_detect(intel_dp
);
4834 else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp
)->base
))
4835 status
= intel_dp_detect_dpcd(intel_dp
);
4837 status
= connector_status_disconnected
;
4839 if (status
== connector_status_disconnected
) {
4840 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4842 if (intel_dp
->is_mst
) {
4843 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4845 intel_dp
->mst_mgr
.mst_state
);
4846 intel_dp
->is_mst
= false;
4847 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4854 if (intel_dp
->reset_link_params
) {
4855 /* Initial max link lane count */
4856 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
4858 /* Initial max link rate */
4859 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
4861 intel_dp
->reset_link_params
= false;
4864 intel_dp_print_rates(intel_dp
);
4866 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4867 drm_dp_is_branch(intel_dp
->dpcd
));
4869 intel_dp_configure_mst(intel_dp
);
4871 if (intel_dp
->is_mst
) {
4873 * If we are in MST mode then this connector
4874 * won't appear connected or have anything
4877 status
= connector_status_disconnected
;
4882 * Clearing NACK and defer counts to get their exact values
4883 * while reading EDID which are required by Compliance tests
4884 * 4.2.2.4 and 4.2.2.5
4886 intel_dp
->aux
.i2c_nack_count
= 0;
4887 intel_dp
->aux
.i2c_defer_count
= 0;
4889 intel_dp_set_edid(intel_dp
);
4890 if (intel_dp_is_edp(intel_dp
) || connector
->detect_edid
)
4891 status
= connector_status_connected
;
4892 intel_dp
->detect_done
= true;
4894 /* Try to read the source of the interrupt */
4895 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4896 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4897 sink_irq_vector
!= 0) {
4898 /* Clear interrupt source */
4899 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4900 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4903 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4904 intel_dp_handle_test_request(intel_dp
);
4905 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4906 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4910 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4911 intel_dp_unset_edid(intel_dp
);
4913 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4918 intel_dp_detect(struct drm_connector
*connector
,
4919 struct drm_modeset_acquire_ctx
*ctx
,
4922 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4923 int status
= connector
->status
;
4925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4926 connector
->base
.id
, connector
->name
);
4928 /* If full detect is not performed yet, do a full detect */
4929 if (!intel_dp
->detect_done
) {
4930 struct drm_crtc
*crtc
;
4933 crtc
= connector
->state
->crtc
;
4935 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
4940 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4943 intel_dp
->detect_done
= false;
4949 intel_dp_force(struct drm_connector
*connector
)
4951 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4952 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4953 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4956 connector
->base
.id
, connector
->name
);
4957 intel_dp_unset_edid(intel_dp
);
4959 if (connector
->status
!= connector_status_connected
)
4962 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4964 intel_dp_set_edid(intel_dp
);
4966 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4969 static int intel_dp_get_modes(struct drm_connector
*connector
)
4971 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4974 edid
= intel_connector
->detect_edid
;
4976 int ret
= intel_connector_update_modes(connector
, edid
);
4981 /* if eDP has no EDID, fall back to fixed mode */
4982 if (intel_dp_is_edp(intel_attached_dp(connector
)) &&
4983 intel_connector
->panel
.fixed_mode
) {
4984 struct drm_display_mode
*mode
;
4986 mode
= drm_mode_duplicate(connector
->dev
,
4987 intel_connector
->panel
.fixed_mode
);
4989 drm_mode_probed_add(connector
, mode
);
4998 intel_dp_connector_register(struct drm_connector
*connector
)
5000 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5003 ret
= intel_connector_register(connector
);
5007 i915_debugfs_connector_add(connector
);
5009 DRM_DEBUG_KMS("registering %s bus for %s\n",
5010 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
5012 intel_dp
->aux
.dev
= connector
->kdev
;
5013 return drm_dp_aux_register(&intel_dp
->aux
);
5017 intel_dp_connector_unregister(struct drm_connector
*connector
)
5019 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
5020 intel_connector_unregister(connector
);
5024 intel_dp_connector_destroy(struct drm_connector
*connector
)
5026 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5028 kfree(intel_connector
->detect_edid
);
5030 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
5031 kfree(intel_connector
->edid
);
5034 * Can't call intel_dp_is_edp() since the encoder may have been
5035 * destroyed already.
5037 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5038 intel_panel_fini(&intel_connector
->panel
);
5040 drm_connector_cleanup(connector
);
5044 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
5046 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
5047 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5049 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5050 if (intel_dp_is_edp(intel_dp
)) {
5051 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5053 * vdd might still be enabled do to the delayed vdd off.
5054 * Make sure vdd is actually turned off here.
5057 edp_panel_vdd_off_sync(intel_dp
);
5058 pps_unlock(intel_dp
);
5060 if (intel_dp
->edp_notifier
.notifier_call
) {
5061 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
5062 intel_dp
->edp_notifier
.notifier_call
= NULL
;
5066 intel_dp_aux_fini(intel_dp
);
5068 drm_encoder_cleanup(encoder
);
5069 kfree(intel_dig_port
);
5072 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
5074 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5076 if (!intel_dp_is_edp(intel_dp
))
5080 * vdd might still be enabled do to the delayed vdd off.
5081 * Make sure vdd is actually turned off here.
5083 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5085 edp_panel_vdd_off_sync(intel_dp
);
5086 pps_unlock(intel_dp
);
5090 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port
,
5093 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_dig_port
->base
.base
);
5094 static const struct drm_dp_aux_msg msg
= {
5095 .request
= DP_AUX_NATIVE_WRITE
,
5096 .address
= DP_AUX_HDCP_AKSV
,
5097 .size
= DRM_HDCP_KSV_LEN
,
5099 uint8_t txbuf
[HEADER_SIZE
+ DRM_HDCP_KSV_LEN
] = {}, rxbuf
[2], reply
= 0;
5103 /* Output An first, that's easy */
5104 dpcd_ret
= drm_dp_dpcd_write(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_AN
,
5105 an
, DRM_HDCP_AN_LEN
);
5106 if (dpcd_ret
!= DRM_HDCP_AN_LEN
) {
5107 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret
);
5108 return dpcd_ret
>= 0 ? -EIO
: dpcd_ret
;
5112 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5113 * order to get it on the wire, we need to create the AUX header as if
5114 * we were writing the data, and then tickle the hardware to output the
5115 * data once the header is sent out.
5117 intel_dp_aux_header(txbuf
, &msg
);
5119 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, HEADER_SIZE
+ msg
.size
,
5120 rxbuf
, sizeof(rxbuf
),
5121 DP_AUX_CH_CTL_AUX_AKSV_SELECT
);
5123 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret
);
5125 } else if (ret
== 0) {
5126 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5130 reply
= (rxbuf
[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK
;
5131 return reply
== DP_AUX_NATIVE_REPLY_ACK
? 0 : -EIO
;
5134 static int intel_dp_hdcp_read_bksv(struct intel_digital_port
*intel_dig_port
,
5138 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BKSV
, bksv
,
5140 if (ret
!= DRM_HDCP_KSV_LEN
) {
5141 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret
);
5142 return ret
>= 0 ? -EIO
: ret
;
5147 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port
,
5152 * For some reason the HDMI and DP HDCP specs call this register
5153 * definition by different names. In the HDMI spec, it's called BSTATUS,
5154 * but in DP it's called BINFO.
5156 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BINFO
,
5157 bstatus
, DRM_HDCP_BSTATUS_LEN
);
5158 if (ret
!= DRM_HDCP_BSTATUS_LEN
) {
5159 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5160 return ret
>= 0 ? -EIO
: ret
;
5166 int intel_dp_hdcp_read_bcaps(struct intel_digital_port
*intel_dig_port
,
5171 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BCAPS
,
5174 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret
);
5175 return ret
>= 0 ? -EIO
: ret
;
5182 int intel_dp_hdcp_repeater_present(struct intel_digital_port
*intel_dig_port
,
5183 bool *repeater_present
)
5188 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5192 *repeater_present
= bcaps
& DP_BCAPS_REPEATER_PRESENT
;
5197 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port
*intel_dig_port
,
5201 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_RI_PRIME
,
5202 ri_prime
, DRM_HDCP_RI_LEN
);
5203 if (ret
!= DRM_HDCP_RI_LEN
) {
5204 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret
);
5205 return ret
>= 0 ? -EIO
: ret
;
5211 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port
*intel_dig_port
,
5216 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5219 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5220 return ret
>= 0 ? -EIO
: ret
;
5222 *ksv_ready
= bstatus
& DP_BSTATUS_READY
;
5227 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port
*intel_dig_port
,
5228 int num_downstream
, u8
*ksv_fifo
)
5233 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5234 for (i
= 0; i
< num_downstream
; i
+= 3) {
5235 size_t len
= min(num_downstream
- i
, 3) * DRM_HDCP_KSV_LEN
;
5236 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5237 DP_AUX_HDCP_KSV_FIFO
,
5238 ksv_fifo
+ i
* DRM_HDCP_KSV_LEN
,
5241 DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i
,
5243 return ret
>= 0 ? -EIO
: ret
;
5250 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port
*intel_dig_port
,
5255 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
5258 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5259 DP_AUX_HDCP_V_PRIME(i
), part
,
5260 DRM_HDCP_V_PRIME_PART_LEN
);
5261 if (ret
!= DRM_HDCP_V_PRIME_PART_LEN
) {
5262 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i
, ret
);
5263 return ret
>= 0 ? -EIO
: ret
;
5269 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port
*intel_dig_port
,
5272 /* Not used for single stream DisplayPort setups */
5277 bool intel_dp_hdcp_check_link(struct intel_digital_port
*intel_dig_port
)
5282 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5285 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5289 return !(bstatus
& (DP_BSTATUS_LINK_FAILURE
| DP_BSTATUS_REAUTH_REQ
));
5293 int intel_dp_hdcp_capable(struct intel_digital_port
*intel_dig_port
,
5299 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5303 *hdcp_capable
= bcaps
& DP_BCAPS_HDCP_CAPABLE
;
5307 static const struct intel_hdcp_shim intel_dp_hdcp_shim
= {
5308 .write_an_aksv
= intel_dp_hdcp_write_an_aksv
,
5309 .read_bksv
= intel_dp_hdcp_read_bksv
,
5310 .read_bstatus
= intel_dp_hdcp_read_bstatus
,
5311 .repeater_present
= intel_dp_hdcp_repeater_present
,
5312 .read_ri_prime
= intel_dp_hdcp_read_ri_prime
,
5313 .read_ksv_ready
= intel_dp_hdcp_read_ksv_ready
,
5314 .read_ksv_fifo
= intel_dp_hdcp_read_ksv_fifo
,
5315 .read_v_prime_part
= intel_dp_hdcp_read_v_prime_part
,
5316 .toggle_signalling
= intel_dp_hdcp_toggle_signalling
,
5317 .check_link
= intel_dp_hdcp_check_link
,
5318 .hdcp_capable
= intel_dp_hdcp_capable
,
5321 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
5323 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5325 lockdep_assert_held(&dev_priv
->pps_mutex
);
5327 if (!edp_have_panel_vdd(intel_dp
))
5331 * The VDD bit needs a power domain reference, so if the bit is
5332 * already enabled when we boot or resume, grab this reference and
5333 * schedule a vdd off, so we don't hold on to the reference
5336 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5337 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5339 edp_panel_vdd_schedule_off(intel_dp
);
5342 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
5344 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5346 if ((intel_dp
->DP
& DP_PORT_EN
) == 0)
5347 return INVALID_PIPE
;
5349 if (IS_CHERRYVIEW(dev_priv
))
5350 return DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5352 return PORT_TO_PIPE(intel_dp
->DP
);
5355 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
5357 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
5358 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
5359 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
5361 if (!HAS_DDI(dev_priv
))
5362 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5365 lspcon_resume(lspcon
);
5367 intel_dp
->reset_link_params
= true;
5371 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5372 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5374 if (intel_dp_is_edp(intel_dp
)) {
5375 /* Reinit the power sequencer, in case BIOS did something with it. */
5376 intel_dp_pps_init(intel_dp
);
5377 intel_edp_panel_vdd_sanitize(intel_dp
);
5380 pps_unlock(intel_dp
);
5383 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5384 .force
= intel_dp_force
,
5385 .fill_modes
= drm_helper_probe_single_connector_modes
,
5386 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
5387 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
5388 .late_register
= intel_dp_connector_register
,
5389 .early_unregister
= intel_dp_connector_unregister
,
5390 .destroy
= intel_dp_connector_destroy
,
5391 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5392 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5395 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5396 .detect_ctx
= intel_dp_detect
,
5397 .get_modes
= intel_dp_get_modes
,
5398 .mode_valid
= intel_dp_mode_valid
,
5399 .atomic_check
= intel_digital_connector_atomic_check
,
5402 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5403 .reset
= intel_dp_encoder_reset
,
5404 .destroy
= intel_dp_encoder_destroy
,
5408 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5410 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5411 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5412 enum irqreturn ret
= IRQ_NONE
;
5414 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5416 * vdd off can generate a long pulse on eDP which
5417 * would require vdd on to handle it, and thus we
5418 * would end up in an endless cycle of
5419 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5421 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5422 port_name(intel_dig_port
->base
.port
));
5426 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5427 port_name(intel_dig_port
->base
.port
),
5428 long_hpd
? "long" : "short");
5431 intel_dp
->reset_link_params
= true;
5432 intel_dp
->detect_done
= false;
5436 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5438 if (intel_dp
->is_mst
) {
5439 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5441 * If we were in MST mode, and device is not
5442 * there, get out of MST mode
5444 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5445 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5446 intel_dp
->is_mst
= false;
5447 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5449 intel_dp
->detect_done
= false;
5454 if (!intel_dp
->is_mst
) {
5457 handled
= intel_dp_short_pulse(intel_dp
);
5459 /* Short pulse can signify loss of hdcp authentication */
5460 intel_hdcp_check_link(intel_dp
->attached_connector
);
5463 intel_dp
->detect_done
= false;
5471 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5476 /* check the VBT to see whether the eDP is on another port */
5477 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5480 * eDP not supported on g4x. so bail out early just
5481 * for a bit extra safety in case the VBT is bonkers.
5483 if (INTEL_GEN(dev_priv
) < 5)
5486 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5489 return intel_bios_is_port_edp(dev_priv
, port
);
5493 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5495 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5496 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5498 if (!IS_G4X(dev_priv
) && port
!= PORT_A
)
5499 intel_attach_force_audio_property(connector
);
5501 intel_attach_broadcast_rgb_property(connector
);
5503 if (intel_dp_is_edp(intel_dp
)) {
5504 u32 allowed_scalers
;
5506 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
5507 if (!HAS_GMCH_DISPLAY(dev_priv
))
5508 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
5510 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
5512 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
5517 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5519 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5520 intel_dp
->last_power_on
= jiffies
;
5521 intel_dp
->last_backlight_off
= jiffies
;
5525 intel_pps_readout_hw_state(struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5527 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5528 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5529 struct pps_registers regs
;
5531 intel_pps_get_registers(intel_dp
, ®s
);
5533 /* Workaround: Need to write PP_CONTROL with the unlock key as
5534 * the very first thing. */
5535 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5537 pp_on
= I915_READ(regs
.pp_on
);
5538 pp_off
= I915_READ(regs
.pp_off
);
5539 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
) &&
5540 !HAS_PCH_ICP(dev_priv
)) {
5541 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5542 pp_div
= I915_READ(regs
.pp_div
);
5545 /* Pull timing values out of registers */
5546 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5547 PANEL_POWER_UP_DELAY_SHIFT
;
5549 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5550 PANEL_LIGHT_ON_DELAY_SHIFT
;
5552 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5553 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5555 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5556 PANEL_POWER_DOWN_DELAY_SHIFT
;
5558 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5559 HAS_PCH_ICP(dev_priv
)) {
5560 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5561 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5563 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5564 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5569 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5571 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5573 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5577 intel_pps_verify_state(struct intel_dp
*intel_dp
)
5579 struct edp_power_seq hw
;
5580 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5582 intel_pps_readout_hw_state(intel_dp
, &hw
);
5584 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5585 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5586 DRM_ERROR("PPS state mismatch\n");
5587 intel_pps_dump_state("sw", sw
);
5588 intel_pps_dump_state("hw", &hw
);
5593 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
5595 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5596 struct edp_power_seq cur
, vbt
, spec
,
5597 *final
= &intel_dp
->pps_delays
;
5599 lockdep_assert_held(&dev_priv
->pps_mutex
);
5601 /* already initialized? */
5602 if (final
->t11_t12
!= 0)
5605 intel_pps_readout_hw_state(intel_dp
, &cur
);
5607 intel_pps_dump_state("cur", &cur
);
5609 vbt
= dev_priv
->vbt
.edp
.pps
;
5610 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5611 * of 500ms appears to be too short. Ocassionally the panel
5612 * just fails to power back on. Increasing the delay to 800ms
5613 * seems sufficient to avoid this problem.
5615 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
5616 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 1300 * 10);
5617 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5620 /* T11_T12 delay is special and actually in units of 100ms, but zero
5621 * based in the hw (so we need to add 100 ms). But the sw vbt
5622 * table multiplies it with 1000 to make it in units of 100usec,
5624 vbt
.t11_t12
+= 100 * 10;
5626 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5627 * our hw here, which are all in 100usec. */
5628 spec
.t1_t3
= 210 * 10;
5629 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5630 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5631 spec
.t10
= 500 * 10;
5632 /* This one is special and actually in units of 100ms, but zero
5633 * based in the hw (so we need to add 100 ms). But the sw vbt
5634 * table multiplies it with 1000 to make it in units of 100usec,
5636 spec
.t11_t12
= (510 + 100) * 10;
5638 intel_pps_dump_state("vbt", &vbt
);
5640 /* Use the max of the register settings and vbt. If both are
5641 * unset, fall back to the spec limits. */
5642 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5644 max(cur.field, vbt.field))
5645 assign_final(t1_t3
);
5649 assign_final(t11_t12
);
5652 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5653 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5654 intel_dp
->backlight_on_delay
= get_delay(t8
);
5655 intel_dp
->backlight_off_delay
= get_delay(t9
);
5656 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5657 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5660 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5661 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5662 intel_dp
->panel_power_cycle_delay
);
5664 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5665 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5668 * We override the HW backlight delays to 1 because we do manual waits
5669 * on them. For T8, even BSpec recommends doing it. For T9, if we
5670 * don't do this, we'll end up waiting for the backlight off delay
5671 * twice: once when we do the manual sleep, and once when we disable
5672 * the panel and wait for the PP_STATUS bit to become zero.
5678 * HW has only a 100msec granularity for t11_t12 so round it up
5681 final
->t11_t12
= roundup(final
->t11_t12
, 100 * 10);
5685 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
5686 bool force_disable_vdd
)
5688 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5689 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5690 int div
= dev_priv
->rawclk_freq
/ 1000;
5691 struct pps_registers regs
;
5692 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
5693 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5695 lockdep_assert_held(&dev_priv
->pps_mutex
);
5697 intel_pps_get_registers(intel_dp
, ®s
);
5700 * On some VLV machines the BIOS can leave the VDD
5701 * enabled even on power seqeuencers which aren't
5702 * hooked up to any port. This would mess up the
5703 * power domain tracking the first time we pick
5704 * one of these power sequencers for use since
5705 * edp_panel_vdd_on() would notice that the VDD was
5706 * already on and therefore wouldn't grab the power
5707 * domain reference. Disable VDD first to avoid this.
5708 * This also avoids spuriously turning the VDD on as
5709 * soon as the new power seqeuencer gets initialized.
5711 if (force_disable_vdd
) {
5712 u32 pp
= ironlake_get_pp_control(intel_dp
);
5714 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5716 if (pp
& EDP_FORCE_VDD
)
5717 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5719 pp
&= ~EDP_FORCE_VDD
;
5721 I915_WRITE(regs
.pp_ctrl
, pp
);
5724 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5725 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5726 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5727 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5728 /* Compute the divisor for the pp clock, simply match the Bspec
5730 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5731 HAS_PCH_ICP(dev_priv
)) {
5732 pp_div
= I915_READ(regs
.pp_ctrl
);
5733 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5734 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5735 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5737 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5738 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5739 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5742 /* Haswell doesn't have any port selection bits for the panel
5743 * power sequencer any more. */
5744 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5745 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5746 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5748 port_sel
= PANEL_PORT_SELECT_DPA
;
5750 port_sel
= PANEL_PORT_SELECT_DPD
;
5755 I915_WRITE(regs
.pp_on
, pp_on
);
5756 I915_WRITE(regs
.pp_off
, pp_off
);
5757 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5758 HAS_PCH_ICP(dev_priv
))
5759 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5761 I915_WRITE(regs
.pp_div
, pp_div
);
5763 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5764 I915_READ(regs
.pp_on
),
5765 I915_READ(regs
.pp_off
),
5766 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
5767 HAS_PCH_ICP(dev_priv
)) ?
5768 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5769 I915_READ(regs
.pp_div
));
5772 static void intel_dp_pps_init(struct intel_dp
*intel_dp
)
5774 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5776 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5777 vlv_initial_power_sequencer_setup(intel_dp
);
5779 intel_dp_init_panel_power_sequencer(intel_dp
);
5780 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
5785 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5786 * @dev_priv: i915 device
5787 * @crtc_state: a pointer to the active intel_crtc_state
5788 * @refresh_rate: RR to be programmed
5790 * This function gets called when refresh rate (RR) has to be changed from
5791 * one frequency to another. Switches can be between high and low RR
5792 * supported by the panel or to any other RR based on media playback (in
5793 * this case, RR value needs to be passed from user space).
5795 * The caller of this function needs to take a lock on dev_priv->drrs.
5797 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5798 const struct intel_crtc_state
*crtc_state
,
5801 struct intel_encoder
*encoder
;
5802 struct intel_digital_port
*dig_port
= NULL
;
5803 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5804 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5805 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5807 if (refresh_rate
<= 0) {
5808 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5812 if (intel_dp
== NULL
) {
5813 DRM_DEBUG_KMS("DRRS not supported.\n");
5817 dig_port
= dp_to_dig_port(intel_dp
);
5818 encoder
= &dig_port
->base
;
5821 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5825 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5826 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5830 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5832 index
= DRRS_LOW_RR
;
5834 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5836 "DRRS requested for previously set RR...ignoring\n");
5840 if (!crtc_state
->base
.active
) {
5841 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5845 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5848 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5851 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5855 DRM_ERROR("Unsupported refreshrate type\n");
5857 } else if (INTEL_GEN(dev_priv
) > 6) {
5858 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5861 val
= I915_READ(reg
);
5862 if (index
> DRRS_HIGH_RR
) {
5863 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5864 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5866 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5868 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5869 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5871 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5873 I915_WRITE(reg
, val
);
5876 dev_priv
->drrs
.refresh_rate_type
= index
;
5878 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5882 * intel_edp_drrs_enable - init drrs struct if supported
5883 * @intel_dp: DP struct
5884 * @crtc_state: A pointer to the active crtc state.
5886 * Initializes frontbuffer_bits and drrs.dp
5888 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5889 const struct intel_crtc_state
*crtc_state
)
5891 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5893 if (!crtc_state
->has_drrs
) {
5894 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5898 if (dev_priv
->psr
.enabled
) {
5899 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5903 mutex_lock(&dev_priv
->drrs
.mutex
);
5904 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5905 DRM_ERROR("DRRS already enabled\n");
5909 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5911 dev_priv
->drrs
.dp
= intel_dp
;
5914 mutex_unlock(&dev_priv
->drrs
.mutex
);
5918 * intel_edp_drrs_disable - Disable DRRS
5919 * @intel_dp: DP struct
5920 * @old_crtc_state: Pointer to old crtc_state.
5923 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5924 const struct intel_crtc_state
*old_crtc_state
)
5926 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5928 if (!old_crtc_state
->has_drrs
)
5931 mutex_lock(&dev_priv
->drrs
.mutex
);
5932 if (!dev_priv
->drrs
.dp
) {
5933 mutex_unlock(&dev_priv
->drrs
.mutex
);
5937 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5938 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5939 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5941 dev_priv
->drrs
.dp
= NULL
;
5942 mutex_unlock(&dev_priv
->drrs
.mutex
);
5944 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5947 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5949 struct drm_i915_private
*dev_priv
=
5950 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5951 struct intel_dp
*intel_dp
;
5953 mutex_lock(&dev_priv
->drrs
.mutex
);
5955 intel_dp
= dev_priv
->drrs
.dp
;
5961 * The delayed work can race with an invalidate hence we need to
5965 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5968 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5969 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5971 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5972 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5976 mutex_unlock(&dev_priv
->drrs
.mutex
);
5980 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5981 * @dev_priv: i915 device
5982 * @frontbuffer_bits: frontbuffer plane tracking bits
5984 * This function gets called everytime rendering on the given planes start.
5985 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5987 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5989 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5990 unsigned int frontbuffer_bits
)
5992 struct drm_crtc
*crtc
;
5995 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5998 cancel_delayed_work(&dev_priv
->drrs
.work
);
6000 mutex_lock(&dev_priv
->drrs
.mutex
);
6001 if (!dev_priv
->drrs
.dp
) {
6002 mutex_unlock(&dev_priv
->drrs
.mutex
);
6006 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6007 pipe
= to_intel_crtc(crtc
)->pipe
;
6009 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6010 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
6012 /* invalidate means busy screen hence upclock */
6013 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6014 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6015 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6017 mutex_unlock(&dev_priv
->drrs
.mutex
);
6021 * intel_edp_drrs_flush - Restart Idleness DRRS
6022 * @dev_priv: i915 device
6023 * @frontbuffer_bits: frontbuffer plane tracking bits
6025 * This function gets called every time rendering on the given planes has
6026 * completed or flip on a crtc is completed. So DRRS should be upclocked
6027 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6028 * if no other planes are dirty.
6030 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6032 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
6033 unsigned int frontbuffer_bits
)
6035 struct drm_crtc
*crtc
;
6038 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
6041 cancel_delayed_work(&dev_priv
->drrs
.work
);
6043 mutex_lock(&dev_priv
->drrs
.mutex
);
6044 if (!dev_priv
->drrs
.dp
) {
6045 mutex_unlock(&dev_priv
->drrs
.mutex
);
6049 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6050 pipe
= to_intel_crtc(crtc
)->pipe
;
6052 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6053 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
6055 /* flush means busy screen hence upclock */
6056 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6057 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6058 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6061 * flush also means no more activity hence schedule downclock, if all
6062 * other fbs are quiescent too
6064 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
6065 schedule_delayed_work(&dev_priv
->drrs
.work
,
6066 msecs_to_jiffies(1000));
6067 mutex_unlock(&dev_priv
->drrs
.mutex
);
6071 * DOC: Display Refresh Rate Switching (DRRS)
6073 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6074 * which enables swtching between low and high refresh rates,
6075 * dynamically, based on the usage scenario. This feature is applicable
6076 * for internal panels.
6078 * Indication that the panel supports DRRS is given by the panel EDID, which
6079 * would list multiple refresh rates for one resolution.
6081 * DRRS is of 2 types - static and seamless.
6082 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6083 * (may appear as a blink on screen) and is used in dock-undock scenario.
6084 * Seamless DRRS involves changing RR without any visual effect to the user
6085 * and can be used during normal system usage. This is done by programming
6086 * certain registers.
6088 * Support for static/seamless DRRS may be indicated in the VBT based on
6089 * inputs from the panel spec.
6091 * DRRS saves power by switching to low RR based on usage scenarios.
6093 * The implementation is based on frontbuffer tracking implementation. When
6094 * there is a disturbance on the screen triggered by user activity or a periodic
6095 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6096 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6099 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6100 * and intel_edp_drrs_flush() are called.
6102 * DRRS can be further extended to support other internal panels and also
6103 * the scenario of video playback wherein RR is set based on the rate
6104 * requested by userspace.
6108 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6109 * @connector: eDP connector
6110 * @fixed_mode: preferred mode of panel
6112 * This function is called only once at driver load to initialize basic
6116 * Downclock mode if panel supports it, else return NULL.
6117 * DRRS support is determined by the presence of downclock mode (apart
6118 * from VBT setting).
6120 static struct drm_display_mode
*
6121 intel_dp_drrs_init(struct intel_connector
*connector
,
6122 struct drm_display_mode
*fixed_mode
)
6124 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
6125 struct drm_display_mode
*downclock_mode
= NULL
;
6127 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
6128 mutex_init(&dev_priv
->drrs
.mutex
);
6130 if (INTEL_GEN(dev_priv
) <= 6) {
6131 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6135 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
6136 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6140 downclock_mode
= intel_find_panel_downclock(dev_priv
, fixed_mode
,
6143 if (!downclock_mode
) {
6144 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6148 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
6150 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
6151 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6152 return downclock_mode
;
6155 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
6156 struct intel_connector
*intel_connector
)
6158 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
6159 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6160 struct drm_connector
*connector
= &intel_connector
->base
;
6161 struct drm_display_mode
*fixed_mode
= NULL
;
6162 struct drm_display_mode
*alt_fixed_mode
= NULL
;
6163 struct drm_display_mode
*downclock_mode
= NULL
;
6165 struct drm_display_mode
*scan
;
6167 enum pipe pipe
= INVALID_PIPE
;
6169 if (!intel_dp_is_edp(intel_dp
))
6173 * On IBX/CPT we may get here with LVDS already registered. Since the
6174 * driver uses the only internal power sequencer available for both
6175 * eDP and LVDS bail out early in this case to prevent interfering
6176 * with an already powered-on LVDS power sequencer.
6178 if (intel_get_lvds_encoder(&dev_priv
->drm
)) {
6179 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
6180 DRM_INFO("LVDS was detected, not registering eDP\n");
6187 intel_dp_init_panel_power_timestamps(intel_dp
);
6188 intel_dp_pps_init(intel_dp
);
6189 intel_edp_panel_vdd_sanitize(intel_dp
);
6191 pps_unlock(intel_dp
);
6193 /* Cache DPCD and EDID for edp. */
6194 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
6197 /* if this fails, presume the device is a ghost */
6198 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6202 mutex_lock(&dev
->mode_config
.mutex
);
6203 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
6205 if (drm_add_edid_modes(connector
, edid
)) {
6206 drm_mode_connector_update_edid_property(connector
,
6210 edid
= ERR_PTR(-EINVAL
);
6213 edid
= ERR_PTR(-ENOENT
);
6215 intel_connector
->edid
= edid
;
6217 /* prefer fixed mode from EDID if available, save an alt mode also */
6218 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
6219 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
6220 fixed_mode
= drm_mode_duplicate(dev
, scan
);
6221 downclock_mode
= intel_dp_drrs_init(
6222 intel_connector
, fixed_mode
);
6223 } else if (!alt_fixed_mode
) {
6224 alt_fixed_mode
= drm_mode_duplicate(dev
, scan
);
6228 /* fallback to VBT if available for eDP */
6229 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
6230 fixed_mode
= drm_mode_duplicate(dev
,
6231 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
6233 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
6234 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
6235 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
6238 mutex_unlock(&dev
->mode_config
.mutex
);
6240 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6241 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
6242 register_reboot_notifier(&intel_dp
->edp_notifier
);
6245 * Figure out the current pipe for the initial backlight setup.
6246 * If the current pipe isn't valid, try the PPS pipe, and if that
6247 * fails just assume pipe A.
6249 pipe
= vlv_active_pipe(intel_dp
);
6251 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6252 pipe
= intel_dp
->pps_pipe
;
6254 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
6257 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6261 intel_panel_init(&intel_connector
->panel
, fixed_mode
, alt_fixed_mode
,
6263 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
6264 intel_panel_setup_backlight(connector
, pipe
);
6269 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
6271 * vdd might still be enabled do to the delayed vdd off.
6272 * Make sure vdd is actually turned off here.
6275 edp_panel_vdd_off_sync(intel_dp
);
6276 pps_unlock(intel_dp
);
6281 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
6283 struct intel_connector
*intel_connector
;
6284 struct drm_connector
*connector
;
6286 intel_connector
= container_of(work
, typeof(*intel_connector
),
6287 modeset_retry_work
);
6288 connector
= &intel_connector
->base
;
6289 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
6292 /* Grab the locks before changing connector property*/
6293 mutex_lock(&connector
->dev
->mode_config
.mutex
);
6294 /* Set connector link status to BAD and send a Uevent to notify
6295 * userspace to do a modeset.
6297 drm_mode_connector_set_link_status_property(connector
,
6298 DRM_MODE_LINK_STATUS_BAD
);
6299 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
6300 /* Send Hotplug uevent so userspace can reprobe */
6301 drm_kms_helper_hotplug_event(connector
->dev
);
6305 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
6306 struct intel_connector
*intel_connector
)
6308 struct drm_connector
*connector
= &intel_connector
->base
;
6309 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
6310 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
6311 struct drm_device
*dev
= intel_encoder
->base
.dev
;
6312 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6313 enum port port
= intel_encoder
->port
;
6316 /* Initialize the work for modeset in case of link train failure */
6317 INIT_WORK(&intel_connector
->modeset_retry_work
,
6318 intel_dp_modeset_retry_work_fn
);
6320 if (WARN(intel_dig_port
->max_lanes
< 1,
6321 "Not enough lanes (%d) for DP on port %c\n",
6322 intel_dig_port
->max_lanes
, port_name(port
)))
6325 intel_dp_set_source_rates(intel_dp
);
6327 intel_dp
->reset_link_params
= true;
6328 intel_dp
->pps_pipe
= INVALID_PIPE
;
6329 intel_dp
->active_pipe
= INVALID_PIPE
;
6331 /* intel_dp vfuncs */
6332 if (HAS_DDI(dev_priv
))
6333 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6335 /* Preserve the current hw state. */
6336 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6337 intel_dp
->attached_connector
= intel_connector
;
6339 if (intel_dp_is_port_edp(dev_priv
, port
))
6340 type
= DRM_MODE_CONNECTOR_eDP
;
6342 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6344 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6345 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6348 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6349 * for DP the encoder type can be set by the caller to
6350 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6352 if (type
== DRM_MODE_CONNECTOR_eDP
)
6353 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6355 /* eDP only on port B and/or C on vlv/chv */
6356 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6357 intel_dp_is_edp(intel_dp
) &&
6358 port
!= PORT_B
&& port
!= PORT_C
))
6361 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6362 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6365 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6366 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6368 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
6369 connector
->interlace_allowed
= true;
6370 connector
->doublescan_allowed
= 0;
6372 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
6374 intel_dp_aux_init(intel_dp
);
6376 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6377 edp_panel_vdd_work
);
6379 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6381 if (HAS_DDI(dev_priv
))
6382 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6384 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6386 /* init MST on ports that can support it */
6387 if (HAS_DP_MST(dev_priv
) && !intel_dp_is_edp(intel_dp
) &&
6388 (port
== PORT_B
|| port
== PORT_C
||
6389 port
== PORT_D
|| port
== PORT_F
))
6390 intel_dp_mst_encoder_init(intel_dig_port
,
6391 intel_connector
->base
.base
.id
);
6393 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6394 intel_dp_aux_fini(intel_dp
);
6395 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6399 intel_dp_add_properties(intel_dp
, connector
);
6401 if (is_hdcp_supported(dev_priv
, port
) && !intel_dp_is_edp(intel_dp
)) {
6402 int ret
= intel_hdcp_init(intel_connector
, &intel_dp_hdcp_shim
);
6404 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6407 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6408 * 0xd. Failure to do so will result in spurious interrupts being
6409 * generated on the port when a cable is not attached.
6411 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
6412 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6413 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6419 drm_connector_cleanup(connector
);
6424 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6425 i915_reg_t output_reg
,
6428 struct intel_digital_port
*intel_dig_port
;
6429 struct intel_encoder
*intel_encoder
;
6430 struct drm_encoder
*encoder
;
6431 struct intel_connector
*intel_connector
;
6433 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6434 if (!intel_dig_port
)
6437 intel_connector
= intel_connector_alloc();
6438 if (!intel_connector
)
6439 goto err_connector_alloc
;
6441 intel_encoder
= &intel_dig_port
->base
;
6442 encoder
= &intel_encoder
->base
;
6444 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6445 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6446 "DP %c", port_name(port
)))
6447 goto err_encoder_init
;
6449 intel_encoder
->hotplug
= intel_dp_hotplug
;
6450 intel_encoder
->compute_config
= intel_dp_compute_config
;
6451 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6452 intel_encoder
->get_config
= intel_dp_get_config
;
6453 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6454 if (IS_CHERRYVIEW(dev_priv
)) {
6455 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6456 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6457 intel_encoder
->enable
= vlv_enable_dp
;
6458 intel_encoder
->disable
= vlv_disable_dp
;
6459 intel_encoder
->post_disable
= chv_post_disable_dp
;
6460 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6461 } else if (IS_VALLEYVIEW(dev_priv
)) {
6462 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6463 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6464 intel_encoder
->enable
= vlv_enable_dp
;
6465 intel_encoder
->disable
= vlv_disable_dp
;
6466 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6467 } else if (INTEL_GEN(dev_priv
) >= 5) {
6468 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6469 intel_encoder
->enable
= g4x_enable_dp
;
6470 intel_encoder
->disable
= ilk_disable_dp
;
6471 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6473 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6474 intel_encoder
->enable
= g4x_enable_dp
;
6475 intel_encoder
->disable
= g4x_disable_dp
;
6478 intel_dig_port
->dp
.output_reg
= output_reg
;
6479 intel_dig_port
->max_lanes
= 4;
6481 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6482 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6483 if (IS_CHERRYVIEW(dev_priv
)) {
6485 intel_encoder
->crtc_mask
= 1 << 2;
6487 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6489 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6491 intel_encoder
->cloneable
= 0;
6492 intel_encoder
->port
= port
;
6494 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6495 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6498 intel_infoframe_init(intel_dig_port
);
6500 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6501 goto err_init_connector
;
6506 drm_encoder_cleanup(encoder
);
6508 kfree(intel_connector
);
6509 err_connector_alloc
:
6510 kfree(intel_dig_port
);
6514 void intel_dp_mst_suspend(struct drm_device
*dev
)
6516 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6520 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6521 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6523 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6526 if (intel_dig_port
->dp
.is_mst
)
6527 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6531 void intel_dp_mst_resume(struct drm_device
*dev
)
6533 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6536 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6537 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6540 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6543 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6545 intel_dp_check_mst_status(&intel_dig_port
->dp
);