2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
294 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
298 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum port port
= intel_dig_port
->port
;
303 /* modeset should have pipe */
305 return to_intel_crtc(crtc
)->pipe
;
307 /* init time, try to find a pipe with this port selected */
308 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
309 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
310 PANEL_PORT_SELECT_MASK
;
311 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
313 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
321 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
323 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
325 if (HAS_PCH_SPLIT(dev
))
326 return PCH_PP_CONTROL
;
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
331 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
333 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
335 if (HAS_PCH_SPLIT(dev
))
336 return PCH_PP_STATUS
;
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
346 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
348 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 u32 pp_ctrl_reg
, pp_div_reg
;
352 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
354 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
357 if (IS_VALLEYVIEW(dev
)) {
358 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
359 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
360 pp_div
= I915_READ(pp_div_reg
);
361 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
365 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
366 msleep(intel_dp
->panel_power_cycle_delay
);
372 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
374 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
380 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
382 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
385 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
386 enum intel_display_power_domain power_domain
;
388 power_domain
= intel_display_port_power_domain(intel_encoder
);
389 return intel_display_power_enabled(dev_priv
, power_domain
) &&
390 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
394 intel_dp_check_edp(struct intel_dp
*intel_dp
)
396 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
399 if (!is_edp(intel_dp
))
402 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
405 I915_READ(_pp_stat_reg(intel_dp
)),
406 I915_READ(_pp_ctrl_reg(intel_dp
)));
411 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
413 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
414 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
422 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
423 msecs_to_jiffies_timeout(10));
425 done
= wait_for_atomic(C
, 10) == 0;
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
436 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
437 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
443 return index
? 0 : intel_hrawclk(dev
) / 2;
446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
448 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
449 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
454 if (intel_dig_port
->port
== PORT_A
) {
455 if (IS_GEN6(dev
) || IS_GEN7(dev
))
456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
458 return 225; /* eDP input clock at 450Mhz */
460 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
466 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
467 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
470 if (intel_dig_port
->port
== PORT_A
) {
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
474 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
475 /* Workaround for non-ULT HSW */
482 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
488 return index
? 0 : 100;
491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
494 uint32_t aux_clock_divider
)
496 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
497 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
498 uint32_t precharge
, timeout
;
505 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
506 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
508 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
510 return DP_AUX_CH_CTL_SEND_BUSY
|
512 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
513 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
515 DP_AUX_CH_CTL_RECEIVE_ERROR
|
516 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
517 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
518 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
522 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
523 uint8_t *send
, int send_bytes
,
524 uint8_t *recv
, int recv_size
)
526 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
527 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
529 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
530 uint32_t ch_data
= ch_ctl
+ 4;
531 uint32_t aux_clock_divider
;
532 int i
, ret
, recv_bytes
;
535 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
538 vdd
= _edp_panel_vdd_on(intel_dp
);
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
544 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
546 intel_dp_check_edp(intel_dp
);
548 intel_aux_display_runtime_get(dev_priv
);
550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
552 status
= I915_READ_NOTRACE(ch_ctl
);
553 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
571 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
572 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i
= 0; i
< send_bytes
; i
+= 4)
581 I915_WRITE(ch_data
+ i
,
582 pack_aux(send
+ i
, send_bytes
- i
));
584 /* Send the command and wait for it to complete */
585 I915_WRITE(ch_ctl
, send_ctl
);
587 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
589 /* Clear done status and any errors */
593 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
594 DP_AUX_CH_CTL_RECEIVE_ERROR
);
596 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
597 DP_AUX_CH_CTL_RECEIVE_ERROR
))
599 if (status
& DP_AUX_CH_CTL_DONE
)
602 if (status
& DP_AUX_CH_CTL_DONE
)
606 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
615 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
623 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
629 /* Unload any bytes sent back from the other side */
630 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
632 if (recv_bytes
> recv_size
)
633 recv_bytes
= recv_size
;
635 for (i
= 0; i
< recv_bytes
; i
+= 4)
636 unpack_aux(I915_READ(ch_data
+ i
),
637 recv
+ i
, recv_bytes
- i
);
641 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
642 intel_aux_display_runtime_put(dev_priv
);
645 edp_panel_vdd_off(intel_dp
, false);
650 #define BARE_ADDRESS_SIZE 3
651 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
653 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
655 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
656 uint8_t txbuf
[20], rxbuf
[20];
657 size_t txsize
, rxsize
;
660 txbuf
[0] = msg
->request
<< 4;
661 txbuf
[1] = msg
->address
>> 8;
662 txbuf
[2] = msg
->address
& 0xff;
663 txbuf
[3] = msg
->size
- 1;
665 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
666 case DP_AUX_NATIVE_WRITE
:
667 case DP_AUX_I2C_WRITE
:
668 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
671 if (WARN_ON(txsize
> 20))
674 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
676 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
678 msg
->reply
= rxbuf
[0] >> 4;
680 /* Return payload size. */
685 case DP_AUX_NATIVE_READ
:
686 case DP_AUX_I2C_READ
:
687 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
688 rxsize
= msg
->size
+ 1;
690 if (WARN_ON(rxsize
> 20))
693 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
695 msg
->reply
= rxbuf
[0] >> 4;
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
700 * Return payload size.
703 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
716 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
718 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
720 enum port port
= intel_dig_port
->port
;
721 const char *name
= NULL
;
726 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
730 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
734 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
738 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
746 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
748 intel_dp
->aux
.name
= name
;
749 intel_dp
->aux
.dev
= dev
->dev
;
750 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
752 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
753 connector
->base
.kdev
->kobj
.name
);
755 ret
= drm_dp_aux_register(&intel_dp
->aux
);
757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
762 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
763 &intel_dp
->aux
.ddc
.dev
.kobj
,
764 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
767 drm_dp_aux_unregister(&intel_dp
->aux
);
772 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
774 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
776 if (!intel_connector
->mst_port
)
777 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
778 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
779 intel_connector_unregister(intel_connector
);
783 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
786 case DP_LINK_BW_1_62
:
787 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
790 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
793 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
799 intel_dp_set_clock(struct intel_encoder
*encoder
,
800 struct intel_crtc_config
*pipe_config
, int link_bw
)
802 struct drm_device
*dev
= encoder
->base
.dev
;
803 const struct dp_link_dpll
*divisor
= NULL
;
808 count
= ARRAY_SIZE(gen4_dpll
);
809 } else if (HAS_PCH_SPLIT(dev
)) {
811 count
= ARRAY_SIZE(pch_dpll
);
812 } else if (IS_CHERRYVIEW(dev
)) {
814 count
= ARRAY_SIZE(chv_dpll
);
815 } else if (IS_VALLEYVIEW(dev
)) {
817 count
= ARRAY_SIZE(vlv_dpll
);
820 if (divisor
&& count
) {
821 for (i
= 0; i
< count
; i
++) {
822 if (link_bw
== divisor
[i
].link_bw
) {
823 pipe_config
->dpll
= divisor
[i
].dpll
;
824 pipe_config
->clock_set
= true;
832 intel_dp_set_m2_n2(struct intel_crtc
*crtc
, struct intel_link_m_n
*m_n
)
834 struct drm_device
*dev
= crtc
->base
.dev
;
835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
836 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
838 I915_WRITE(PIPE_DATA_M2(transcoder
),
839 TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
840 I915_WRITE(PIPE_DATA_N2(transcoder
), m_n
->gmch_n
);
841 I915_WRITE(PIPE_LINK_M2(transcoder
), m_n
->link_m
);
842 I915_WRITE(PIPE_LINK_N2(transcoder
), m_n
->link_n
);
846 intel_dp_compute_config(struct intel_encoder
*encoder
,
847 struct intel_crtc_config
*pipe_config
)
849 struct drm_device
*dev
= encoder
->base
.dev
;
850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
851 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
852 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
853 enum port port
= dp_to_dig_port(intel_dp
)->port
;
854 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
855 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
856 int lane_count
, clock
;
857 int min_lane_count
= 1;
858 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
859 /* Conveniently, the link BW constants become indices with a shift...*/
861 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
863 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
864 int link_avail
, link_clock
;
866 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
867 pipe_config
->has_pch_encoder
= true;
869 pipe_config
->has_dp_encoder
= true;
870 pipe_config
->has_audio
= intel_dp
->has_audio
;
872 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
873 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
875 if (!HAS_PCH_SPLIT(dev
))
876 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
877 intel_connector
->panel
.fitting_mode
);
879 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
880 intel_connector
->panel
.fitting_mode
);
883 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
886 DRM_DEBUG_KMS("DP link computation with max lane count %i "
887 "max bw %02x pixel clock %iKHz\n",
888 max_lane_count
, bws
[max_clock
],
889 adjusted_mode
->crtc_clock
);
891 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
893 bpp
= pipe_config
->pipe_bpp
;
894 if (is_edp(intel_dp
)) {
895 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
896 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
897 dev_priv
->vbt
.edp_bpp
);
898 bpp
= dev_priv
->vbt
.edp_bpp
;
901 if (IS_BROADWELL(dev
)) {
902 /* Yes, it's an ugly hack. */
903 min_lane_count
= max_lane_count
;
904 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
906 } else if (dev_priv
->vbt
.edp_lanes
) {
907 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
909 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
913 if (dev_priv
->vbt
.edp_rate
) {
914 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
915 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
920 for (; bpp
>= 6*3; bpp
-= 2*3) {
921 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
924 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
925 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
926 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
927 link_avail
= intel_dp_max_data_rate(link_clock
,
930 if (mode_rate
<= link_avail
) {
940 if (intel_dp
->color_range_auto
) {
943 * CEA-861-E - 5.1 Default Encoding Parameters
944 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
946 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
947 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
949 intel_dp
->color_range
= 0;
952 if (intel_dp
->color_range
)
953 pipe_config
->limited_color_range
= true;
955 intel_dp
->link_bw
= bws
[clock
];
956 intel_dp
->lane_count
= lane_count
;
957 pipe_config
->pipe_bpp
= bpp
;
958 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
960 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
961 intel_dp
->link_bw
, intel_dp
->lane_count
,
962 pipe_config
->port_clock
, bpp
);
963 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
964 mode_rate
, link_avail
);
966 intel_link_compute_m_n(bpp
, lane_count
,
967 adjusted_mode
->crtc_clock
,
968 pipe_config
->port_clock
,
969 &pipe_config
->dp_m_n
);
971 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
972 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
973 intel_link_compute_m_n(bpp
, lane_count
,
974 intel_connector
->panel
.downclock_mode
->clock
,
975 pipe_config
->port_clock
,
976 &pipe_config
->dp_m2_n2
);
980 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
982 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
987 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
989 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
990 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
991 struct drm_device
*dev
= crtc
->base
.dev
;
992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
995 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
996 dpa_ctl
= I915_READ(DP_A
);
997 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
999 if (crtc
->config
.port_clock
== 162000) {
1000 /* For a long time we've carried around a ILK-DevA w/a for the
1001 * 160MHz clock. If we're really unlucky, it's still required.
1003 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1004 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1005 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1007 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1008 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1011 I915_WRITE(DP_A
, dpa_ctl
);
1017 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1019 struct drm_device
*dev
= encoder
->base
.dev
;
1020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1021 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1022 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1023 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1024 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1027 * There are four kinds of DP registers:
1034 * IBX PCH and CPU are the same for almost everything,
1035 * except that the CPU DP PLL is configured in this
1038 * CPT PCH is quite different, having many bits moved
1039 * to the TRANS_DP_CTL register instead. That
1040 * configuration happens (oddly) in ironlake_pch_enable
1043 /* Preserve the BIOS-computed detected bit. This is
1044 * supposed to be read-only.
1046 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1048 /* Handle DP bits in common between all three register formats */
1049 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1050 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1052 if (crtc
->config
.has_audio
) {
1053 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1054 pipe_name(crtc
->pipe
));
1055 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1056 intel_write_eld(&encoder
->base
, adjusted_mode
);
1059 /* Split out the IBX/CPU vs CPT settings */
1061 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1062 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1063 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1064 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1065 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1066 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1068 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1069 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1071 intel_dp
->DP
|= crtc
->pipe
<< 29;
1072 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1073 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1074 intel_dp
->DP
|= intel_dp
->color_range
;
1076 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1077 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1078 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1079 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1080 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1082 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1083 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1085 if (!IS_CHERRYVIEW(dev
)) {
1086 if (crtc
->pipe
== 1)
1087 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1089 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1092 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1096 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1097 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1099 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1100 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1102 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1103 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1105 static void wait_panel_status(struct intel_dp
*intel_dp
,
1109 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1111 u32 pp_stat_reg
, pp_ctrl_reg
;
1113 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1114 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1116 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1118 I915_READ(pp_stat_reg
),
1119 I915_READ(pp_ctrl_reg
));
1121 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1122 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1123 I915_READ(pp_stat_reg
),
1124 I915_READ(pp_ctrl_reg
));
1127 DRM_DEBUG_KMS("Wait complete\n");
1130 static void wait_panel_on(struct intel_dp
*intel_dp
)
1132 DRM_DEBUG_KMS("Wait for panel power on\n");
1133 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1136 static void wait_panel_off(struct intel_dp
*intel_dp
)
1138 DRM_DEBUG_KMS("Wait for panel power off time\n");
1139 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1142 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1144 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1146 /* When we disable the VDD override bit last we have to do the manual
1148 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1149 intel_dp
->panel_power_cycle_delay
);
1151 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1154 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1156 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1157 intel_dp
->backlight_on_delay
);
1160 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1162 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1163 intel_dp
->backlight_off_delay
);
1166 /* Read the current pp_control value, unlocking the register if it
1170 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1172 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1176 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1177 control
&= ~PANEL_UNLOCK_MASK
;
1178 control
|= PANEL_UNLOCK_REGS
;
1182 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1184 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1185 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1186 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1188 enum intel_display_power_domain power_domain
;
1190 u32 pp_stat_reg
, pp_ctrl_reg
;
1191 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1193 if (!is_edp(intel_dp
))
1196 intel_dp
->want_panel_vdd
= true;
1198 if (edp_have_panel_vdd(intel_dp
))
1199 return need_to_disable
;
1201 power_domain
= intel_display_port_power_domain(intel_encoder
);
1202 intel_display_power_get(dev_priv
, power_domain
);
1204 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1206 if (!edp_have_panel_power(intel_dp
))
1207 wait_panel_power_cycle(intel_dp
);
1209 pp
= ironlake_get_pp_control(intel_dp
);
1210 pp
|= EDP_FORCE_VDD
;
1212 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1213 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1215 I915_WRITE(pp_ctrl_reg
, pp
);
1216 POSTING_READ(pp_ctrl_reg
);
1217 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1218 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1220 * If the panel wasn't on, delay before accessing aux channel
1222 if (!edp_have_panel_power(intel_dp
)) {
1223 DRM_DEBUG_KMS("eDP was not running\n");
1224 msleep(intel_dp
->panel_power_up_delay
);
1227 return need_to_disable
;
1230 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1232 if (is_edp(intel_dp
)) {
1233 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1235 WARN(!vdd
, "eDP VDD already requested on\n");
1239 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1241 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1244 u32 pp_stat_reg
, pp_ctrl_reg
;
1246 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1248 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1249 struct intel_digital_port
*intel_dig_port
=
1250 dp_to_dig_port(intel_dp
);
1251 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1252 enum intel_display_power_domain power_domain
;
1254 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1256 pp
= ironlake_get_pp_control(intel_dp
);
1257 pp
&= ~EDP_FORCE_VDD
;
1259 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1260 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1262 I915_WRITE(pp_ctrl_reg
, pp
);
1263 POSTING_READ(pp_ctrl_reg
);
1265 /* Make sure sequencer is idle before allowing subsequent activity */
1266 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1267 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1269 if ((pp
& POWER_TARGET_ON
) == 0)
1270 intel_dp
->last_power_cycle
= jiffies
;
1272 power_domain
= intel_display_port_power_domain(intel_encoder
);
1273 intel_display_power_put(dev_priv
, power_domain
);
1277 static void edp_panel_vdd_work(struct work_struct
*__work
)
1279 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1280 struct intel_dp
, panel_vdd_work
);
1281 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1283 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
1284 edp_panel_vdd_off_sync(intel_dp
);
1285 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
1288 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1290 if (!is_edp(intel_dp
))
1293 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1295 intel_dp
->want_panel_vdd
= false;
1298 edp_panel_vdd_off_sync(intel_dp
);
1301 * Queue the timer to fire a long
1302 * time from now (relative to the power down delay)
1303 * to keep the panel power up across a sequence of operations
1305 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1306 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1310 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1312 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1317 if (!is_edp(intel_dp
))
1320 DRM_DEBUG_KMS("Turn eDP power on\n");
1322 if (edp_have_panel_power(intel_dp
)) {
1323 DRM_DEBUG_KMS("eDP power already on\n");
1327 wait_panel_power_cycle(intel_dp
);
1329 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1330 pp
= ironlake_get_pp_control(intel_dp
);
1332 /* ILK workaround: disable reset around power sequence */
1333 pp
&= ~PANEL_POWER_RESET
;
1334 I915_WRITE(pp_ctrl_reg
, pp
);
1335 POSTING_READ(pp_ctrl_reg
);
1338 pp
|= POWER_TARGET_ON
;
1340 pp
|= PANEL_POWER_RESET
;
1342 I915_WRITE(pp_ctrl_reg
, pp
);
1343 POSTING_READ(pp_ctrl_reg
);
1345 wait_panel_on(intel_dp
);
1346 intel_dp
->last_power_on
= jiffies
;
1349 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1350 I915_WRITE(pp_ctrl_reg
, pp
);
1351 POSTING_READ(pp_ctrl_reg
);
1355 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1357 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1358 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1359 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 enum intel_display_power_domain power_domain
;
1365 if (!is_edp(intel_dp
))
1368 DRM_DEBUG_KMS("Turn eDP power off\n");
1370 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1372 pp
= ironlake_get_pp_control(intel_dp
);
1373 /* We need to switch off panel power _and_ force vdd, for otherwise some
1374 * panels get very unhappy and cease to work. */
1375 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1378 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1380 intel_dp
->want_panel_vdd
= false;
1382 I915_WRITE(pp_ctrl_reg
, pp
);
1383 POSTING_READ(pp_ctrl_reg
);
1385 intel_dp
->last_power_cycle
= jiffies
;
1386 wait_panel_off(intel_dp
);
1388 /* We got a reference when we enabled the VDD. */
1389 power_domain
= intel_display_port_power_domain(intel_encoder
);
1390 intel_display_power_put(dev_priv
, power_domain
);
1393 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1401 if (!is_edp(intel_dp
))
1404 DRM_DEBUG_KMS("\n");
1406 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1409 * If we enable the backlight right away following a panel power
1410 * on, we may see slight flicker as the panel syncs with the eDP
1411 * link. So delay a bit to make sure the image is solid before
1412 * allowing it to appear.
1414 wait_backlight_on(intel_dp
);
1415 pp
= ironlake_get_pp_control(intel_dp
);
1416 pp
|= EDP_BLC_ENABLE
;
1418 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1420 I915_WRITE(pp_ctrl_reg
, pp
);
1421 POSTING_READ(pp_ctrl_reg
);
1424 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1426 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1431 if (!is_edp(intel_dp
))
1434 DRM_DEBUG_KMS("\n");
1435 pp
= ironlake_get_pp_control(intel_dp
);
1436 pp
&= ~EDP_BLC_ENABLE
;
1438 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1440 I915_WRITE(pp_ctrl_reg
, pp
);
1441 POSTING_READ(pp_ctrl_reg
);
1442 intel_dp
->last_backlight_off
= jiffies
;
1444 edp_wait_backlight_off(intel_dp
);
1446 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1449 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1451 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1452 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1453 struct drm_device
*dev
= crtc
->dev
;
1454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1457 assert_pipe_disabled(dev_priv
,
1458 to_intel_crtc(crtc
)->pipe
);
1460 DRM_DEBUG_KMS("\n");
1461 dpa_ctl
= I915_READ(DP_A
);
1462 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1463 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1465 /* We don't adjust intel_dp->DP while tearing down the link, to
1466 * facilitate link retraining (e.g. after hotplug). Hence clear all
1467 * enable bits here to ensure that we don't enable too much. */
1468 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1469 intel_dp
->DP
|= DP_PLL_ENABLE
;
1470 I915_WRITE(DP_A
, intel_dp
->DP
);
1475 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1477 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1478 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1479 struct drm_device
*dev
= crtc
->dev
;
1480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1483 assert_pipe_disabled(dev_priv
,
1484 to_intel_crtc(crtc
)->pipe
);
1486 dpa_ctl
= I915_READ(DP_A
);
1487 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1488 "dp pll off, should be on\n");
1489 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1491 /* We can't rely on the value tracked for the DP register in
1492 * intel_dp->DP because link_down must not change that (otherwise link
1493 * re-training will fail. */
1494 dpa_ctl
&= ~DP_PLL_ENABLE
;
1495 I915_WRITE(DP_A
, dpa_ctl
);
1500 /* If the sink supports it, try to set the power state appropriately */
1501 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1505 /* Should have a valid DPCD by this point */
1506 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1509 if (mode
!= DRM_MODE_DPMS_ON
) {
1510 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1513 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1516 * When turning on, we need to retry for 1ms to give the sink
1519 for (i
= 0; i
< 3; i
++) {
1520 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1529 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1532 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1533 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1534 struct drm_device
*dev
= encoder
->base
.dev
;
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 enum intel_display_power_domain power_domain
;
1539 power_domain
= intel_display_port_power_domain(encoder
);
1540 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1543 tmp
= I915_READ(intel_dp
->output_reg
);
1545 if (!(tmp
& DP_PORT_EN
))
1548 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1549 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1550 } else if (IS_CHERRYVIEW(dev
)) {
1551 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1552 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1553 *pipe
= PORT_TO_PIPE(tmp
);
1559 switch (intel_dp
->output_reg
) {
1561 trans_sel
= TRANS_DP_PORT_SEL_B
;
1564 trans_sel
= TRANS_DP_PORT_SEL_C
;
1567 trans_sel
= TRANS_DP_PORT_SEL_D
;
1574 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1575 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1581 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1582 intel_dp
->output_reg
);
1588 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1589 struct intel_crtc_config
*pipe_config
)
1591 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1593 struct drm_device
*dev
= encoder
->base
.dev
;
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1595 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1596 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1599 tmp
= I915_READ(intel_dp
->output_reg
);
1600 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1601 pipe_config
->has_audio
= true;
1603 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1604 if (tmp
& DP_SYNC_HS_HIGH
)
1605 flags
|= DRM_MODE_FLAG_PHSYNC
;
1607 flags
|= DRM_MODE_FLAG_NHSYNC
;
1609 if (tmp
& DP_SYNC_VS_HIGH
)
1610 flags
|= DRM_MODE_FLAG_PVSYNC
;
1612 flags
|= DRM_MODE_FLAG_NVSYNC
;
1614 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1615 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1616 flags
|= DRM_MODE_FLAG_PHSYNC
;
1618 flags
|= DRM_MODE_FLAG_NHSYNC
;
1620 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1621 flags
|= DRM_MODE_FLAG_PVSYNC
;
1623 flags
|= DRM_MODE_FLAG_NVSYNC
;
1626 pipe_config
->adjusted_mode
.flags
|= flags
;
1628 pipe_config
->has_dp_encoder
= true;
1630 intel_dp_get_m_n(crtc
, pipe_config
);
1632 if (port
== PORT_A
) {
1633 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1634 pipe_config
->port_clock
= 162000;
1636 pipe_config
->port_clock
= 270000;
1639 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1640 &pipe_config
->dp_m_n
);
1642 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1643 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1645 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1647 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1648 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1650 * This is a big fat ugly hack.
1652 * Some machines in UEFI boot mode provide us a VBT that has 18
1653 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1654 * unknown we fail to light up. Yet the same BIOS boots up with
1655 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1656 * max, not what it tells us to use.
1658 * Note: This will still be broken if the eDP panel is not lit
1659 * up by the BIOS, and thus we can't get the mode at module
1662 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1663 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1664 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1668 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1670 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1673 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1683 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1684 struct edp_vsc_psr
*vsc_psr
)
1686 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1687 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1689 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1690 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1691 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1692 uint32_t *data
= (uint32_t *) vsc_psr
;
1695 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1696 the video DIP being updated before program video DIP data buffer
1697 registers for DIP being updated. */
1698 I915_WRITE(ctl_reg
, 0);
1699 POSTING_READ(ctl_reg
);
1701 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1702 if (i
< sizeof(struct edp_vsc_psr
))
1703 I915_WRITE(data_reg
+ i
, *data
++);
1705 I915_WRITE(data_reg
+ i
, 0);
1708 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1709 POSTING_READ(ctl_reg
);
1712 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1714 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1716 struct edp_vsc_psr psr_vsc
;
1718 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1719 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1720 psr_vsc
.sdp_header
.HB0
= 0;
1721 psr_vsc
.sdp_header
.HB1
= 0x7;
1722 psr_vsc
.sdp_header
.HB2
= 0x2;
1723 psr_vsc
.sdp_header
.HB3
= 0x8;
1724 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1726 /* Avoid continuous PSR exit by masking memup and hpd */
1727 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1728 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1731 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1733 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1734 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1736 uint32_t aux_clock_divider
;
1737 int precharge
= 0x3;
1738 int msg_size
= 5; /* Header(4) + Message(1) */
1739 bool only_standby
= false;
1741 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1743 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1744 only_standby
= true;
1746 /* Enable PSR in sink */
1747 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
1748 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1749 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1751 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1752 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1754 /* Setup AUX registers */
1755 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1756 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1757 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1758 DP_AUX_CH_CTL_TIME_OUT_400us
|
1759 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1760 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1761 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1764 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1766 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1767 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1769 uint32_t max_sleep_time
= 0x1f;
1770 uint32_t idle_frames
= 1;
1772 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1773 bool only_standby
= false;
1775 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1776 only_standby
= true;
1778 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
1779 val
|= EDP_PSR_LINK_STANDBY
;
1780 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1781 val
|= EDP_PSR_TP1_TIME_0us
;
1782 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1783 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
1785 val
|= EDP_PSR_LINK_DISABLE
;
1787 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1788 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1789 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1790 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1794 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1796 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1797 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1799 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1800 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1802 lockdep_assert_held(&dev_priv
->psr
.lock
);
1803 lockdep_assert_held(&dev
->struct_mutex
);
1804 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1805 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
1807 dev_priv
->psr
.source_ok
= false;
1809 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
1810 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1814 if (!i915
.enable_psr
) {
1815 DRM_DEBUG_KMS("PSR disable by flag\n");
1819 /* Below limitations aren't valid for Broadwell */
1820 if (IS_BROADWELL(dev
))
1823 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1825 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1829 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1830 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1835 dev_priv
->psr
.source_ok
= true;
1839 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1841 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1842 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1845 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1846 WARN_ON(dev_priv
->psr
.active
);
1847 lockdep_assert_held(&dev_priv
->psr
.lock
);
1849 /* Enable PSR on the panel */
1850 intel_edp_psr_enable_sink(intel_dp
);
1852 /* Enable PSR on the host */
1853 intel_edp_psr_enable_source(intel_dp
);
1855 dev_priv
->psr
.active
= true;
1858 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1860 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1863 if (!HAS_PSR(dev
)) {
1864 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1868 if (!is_edp_psr(intel_dp
)) {
1869 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1873 mutex_lock(&dev_priv
->psr
.lock
);
1874 if (dev_priv
->psr
.enabled
) {
1875 DRM_DEBUG_KMS("PSR already in use\n");
1876 mutex_unlock(&dev_priv
->psr
.lock
);
1880 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
1882 /* Setup PSR once */
1883 intel_edp_psr_setup(intel_dp
);
1885 if (intel_edp_psr_match_conditions(intel_dp
))
1886 dev_priv
->psr
.enabled
= intel_dp
;
1887 mutex_unlock(&dev_priv
->psr
.lock
);
1890 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1892 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1895 mutex_lock(&dev_priv
->psr
.lock
);
1896 if (!dev_priv
->psr
.enabled
) {
1897 mutex_unlock(&dev_priv
->psr
.lock
);
1901 if (dev_priv
->psr
.active
) {
1902 I915_WRITE(EDP_PSR_CTL(dev
),
1903 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1905 /* Wait till PSR is idle */
1906 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1907 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1908 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1910 dev_priv
->psr
.active
= false;
1912 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1915 dev_priv
->psr
.enabled
= NULL
;
1916 mutex_unlock(&dev_priv
->psr
.lock
);
1918 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
1921 static void intel_edp_psr_work(struct work_struct
*work
)
1923 struct drm_i915_private
*dev_priv
=
1924 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
1925 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
1927 mutex_lock(&dev_priv
->psr
.lock
);
1928 intel_dp
= dev_priv
->psr
.enabled
;
1934 * The delayed work can race with an invalidate hence we need to
1935 * recheck. Since psr_flush first clears this and then reschedules we
1936 * won't ever miss a flush when bailing out here.
1938 if (dev_priv
->psr
.busy_frontbuffer_bits
)
1941 intel_edp_psr_do_enable(intel_dp
);
1943 mutex_unlock(&dev_priv
->psr
.lock
);
1946 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
1948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1950 if (dev_priv
->psr
.active
) {
1951 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
1953 WARN_ON(!(val
& EDP_PSR_ENABLE
));
1955 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
1957 dev_priv
->psr
.active
= false;
1962 void intel_edp_psr_invalidate(struct drm_device
*dev
,
1963 unsigned frontbuffer_bits
)
1965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1966 struct drm_crtc
*crtc
;
1969 mutex_lock(&dev_priv
->psr
.lock
);
1970 if (!dev_priv
->psr
.enabled
) {
1971 mutex_unlock(&dev_priv
->psr
.lock
);
1975 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
1976 pipe
= to_intel_crtc(crtc
)->pipe
;
1978 intel_edp_psr_do_exit(dev
);
1980 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
1982 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
1983 mutex_unlock(&dev_priv
->psr
.lock
);
1986 void intel_edp_psr_flush(struct drm_device
*dev
,
1987 unsigned frontbuffer_bits
)
1989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1990 struct drm_crtc
*crtc
;
1993 mutex_lock(&dev_priv
->psr
.lock
);
1994 if (!dev_priv
->psr
.enabled
) {
1995 mutex_unlock(&dev_priv
->psr
.lock
);
1999 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2000 pipe
= to_intel_crtc(crtc
)->pipe
;
2001 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2004 * On Haswell sprite plane updates don't result in a psr invalidating
2005 * signal in the hardware. Which means we need to manually fake this in
2006 * software for all flushes, not just when we've seen a preceding
2007 * invalidation through frontbuffer rendering.
2009 if (IS_HASWELL(dev
) &&
2010 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2011 intel_edp_psr_do_exit(dev
);
2013 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2014 schedule_delayed_work(&dev_priv
->psr
.work
,
2015 msecs_to_jiffies(100));
2016 mutex_unlock(&dev_priv
->psr
.lock
);
2019 void intel_edp_psr_init(struct drm_device
*dev
)
2021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2023 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2024 mutex_init(&dev_priv
->psr
.lock
);
2027 static void intel_disable_dp(struct intel_encoder
*encoder
)
2029 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2030 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2031 struct drm_device
*dev
= encoder
->base
.dev
;
2033 /* Make sure the panel is off before trying to change the mode. But also
2034 * ensure that we have vdd while we switch off the panel. */
2035 intel_edp_panel_vdd_on(intel_dp
);
2036 intel_edp_backlight_off(intel_dp
);
2037 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2038 intel_edp_panel_off(intel_dp
);
2040 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2041 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
2042 intel_dp_link_down(intel_dp
);
2045 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
2047 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2048 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2053 intel_dp_link_down(intel_dp
);
2054 ironlake_edp_pll_off(intel_dp
);
2057 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2059 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2061 intel_dp_link_down(intel_dp
);
2064 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2066 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2067 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2068 struct drm_device
*dev
= encoder
->base
.dev
;
2069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2070 struct intel_crtc
*intel_crtc
=
2071 to_intel_crtc(encoder
->base
.crtc
);
2072 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2073 enum pipe pipe
= intel_crtc
->pipe
;
2076 intel_dp_link_down(intel_dp
);
2078 mutex_lock(&dev_priv
->dpio_lock
);
2080 /* Propagate soft reset to data lane reset */
2081 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2082 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2083 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2085 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2086 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2087 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2089 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2090 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2091 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2093 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2094 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2095 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2097 mutex_unlock(&dev_priv
->dpio_lock
);
2100 static void intel_enable_dp(struct intel_encoder
*encoder
)
2102 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2103 struct drm_device
*dev
= encoder
->base
.dev
;
2104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2105 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2107 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2110 intel_edp_panel_vdd_on(intel_dp
);
2111 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2112 intel_dp_start_link_train(intel_dp
);
2113 intel_edp_panel_on(intel_dp
);
2114 edp_panel_vdd_off(intel_dp
, true);
2115 intel_dp_complete_link_train(intel_dp
);
2116 intel_dp_stop_link_train(intel_dp
);
2119 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2121 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2123 intel_enable_dp(encoder
);
2124 intel_edp_backlight_on(intel_dp
);
2127 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2129 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2131 intel_edp_backlight_on(intel_dp
);
2134 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2136 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2137 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2139 intel_dp_prepare(encoder
);
2141 /* Only ilk+ has port A */
2142 if (dport
->port
== PORT_A
) {
2143 ironlake_set_pll_cpu_edp(intel_dp
);
2144 ironlake_edp_pll_on(intel_dp
);
2148 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2150 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2151 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2152 struct drm_device
*dev
= encoder
->base
.dev
;
2153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2154 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2155 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2156 int pipe
= intel_crtc
->pipe
;
2157 struct edp_power_seq power_seq
;
2160 mutex_lock(&dev_priv
->dpio_lock
);
2162 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2169 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2170 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2171 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2173 mutex_unlock(&dev_priv
->dpio_lock
);
2175 if (is_edp(intel_dp
)) {
2176 /* init power sequencer on this pipe and port */
2177 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2178 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2182 intel_enable_dp(encoder
);
2184 vlv_wait_port_ready(dev_priv
, dport
);
2187 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2189 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2190 struct drm_device
*dev
= encoder
->base
.dev
;
2191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2192 struct intel_crtc
*intel_crtc
=
2193 to_intel_crtc(encoder
->base
.crtc
);
2194 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2195 int pipe
= intel_crtc
->pipe
;
2197 intel_dp_prepare(encoder
);
2199 /* Program Tx lane resets to default */
2200 mutex_lock(&dev_priv
->dpio_lock
);
2201 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2202 DPIO_PCS_TX_LANE2_RESET
|
2203 DPIO_PCS_TX_LANE1_RESET
);
2204 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2205 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2206 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2207 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2208 DPIO_PCS_CLK_SOFT_RESET
);
2210 /* Fix up inter-pair skew failure */
2211 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2212 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2213 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2214 mutex_unlock(&dev_priv
->dpio_lock
);
2217 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2219 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2220 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2221 struct drm_device
*dev
= encoder
->base
.dev
;
2222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2223 struct edp_power_seq power_seq
;
2224 struct intel_crtc
*intel_crtc
=
2225 to_intel_crtc(encoder
->base
.crtc
);
2226 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2227 int pipe
= intel_crtc
->pipe
;
2231 mutex_lock(&dev_priv
->dpio_lock
);
2233 /* Deassert soft data lane reset*/
2234 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2235 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2236 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2238 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2239 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2240 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2242 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2243 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2244 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2246 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2247 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2248 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2250 /* Program Tx lane latency optimal setting*/
2251 for (i
= 0; i
< 4; i
++) {
2252 /* Set the latency optimal bit */
2253 data
= (i
== 1) ? 0x0 : 0x6;
2254 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2255 data
<< DPIO_FRC_LATENCY_SHFIT
);
2257 /* Set the upar bit */
2258 data
= (i
== 1) ? 0x0 : 0x1;
2259 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2260 data
<< DPIO_UPAR_SHIFT
);
2263 /* Data lane stagger programming */
2264 /* FIXME: Fix up value only after power analysis */
2266 mutex_unlock(&dev_priv
->dpio_lock
);
2268 if (is_edp(intel_dp
)) {
2269 /* init power sequencer on this pipe and port */
2270 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2271 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2275 intel_enable_dp(encoder
);
2277 vlv_wait_port_ready(dev_priv
, dport
);
2280 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2282 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2283 struct drm_device
*dev
= encoder
->base
.dev
;
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2285 struct intel_crtc
*intel_crtc
=
2286 to_intel_crtc(encoder
->base
.crtc
);
2287 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2288 enum pipe pipe
= intel_crtc
->pipe
;
2291 mutex_lock(&dev_priv
->dpio_lock
);
2293 /* program left/right clock distribution */
2294 if (pipe
!= PIPE_B
) {
2295 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2296 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2298 val
|= CHV_BUFLEFTENA1_FORCE
;
2300 val
|= CHV_BUFRIGHTENA1_FORCE
;
2301 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2303 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2304 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2306 val
|= CHV_BUFLEFTENA2_FORCE
;
2308 val
|= CHV_BUFRIGHTENA2_FORCE
;
2309 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2312 /* program clock channel usage */
2313 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2314 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2316 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2318 val
|= CHV_PCS_USEDCLKCHANNEL
;
2319 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2321 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2322 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2324 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2326 val
|= CHV_PCS_USEDCLKCHANNEL
;
2327 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2330 * This a a bit weird since generally CL
2331 * matches the pipe, but here we need to
2332 * pick the CL based on the port.
2334 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2336 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2338 val
|= CHV_CMN_USEDCLKCHANNEL
;
2339 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2341 mutex_unlock(&dev_priv
->dpio_lock
);
2345 * Native read with retry for link status and receiver capability reads for
2346 * cases where the sink may still be asleep.
2348 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2349 * supposed to retry 3 times per the spec.
2352 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2353 void *buffer
, size_t size
)
2358 for (i
= 0; i
< 3; i
++) {
2359 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2369 * Fetch AUX CH registers 0x202 - 0x207 which contain
2370 * link status information
2373 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2375 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2378 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2381 /* These are source-specific values. */
2383 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2385 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2386 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2388 if (IS_VALLEYVIEW(dev
))
2389 return DP_TRAIN_VOLTAGE_SWING_1200
;
2390 else if (IS_GEN7(dev
) && port
== PORT_A
)
2391 return DP_TRAIN_VOLTAGE_SWING_800
;
2392 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2393 return DP_TRAIN_VOLTAGE_SWING_1200
;
2395 return DP_TRAIN_VOLTAGE_SWING_800
;
2399 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2401 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2402 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2404 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2405 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2406 case DP_TRAIN_VOLTAGE_SWING_400
:
2407 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2408 case DP_TRAIN_VOLTAGE_SWING_600
:
2409 return DP_TRAIN_PRE_EMPHASIS_6
;
2410 case DP_TRAIN_VOLTAGE_SWING_800
:
2411 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2412 case DP_TRAIN_VOLTAGE_SWING_1200
:
2414 return DP_TRAIN_PRE_EMPHASIS_0
;
2416 } else if (IS_VALLEYVIEW(dev
)) {
2417 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2418 case DP_TRAIN_VOLTAGE_SWING_400
:
2419 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2420 case DP_TRAIN_VOLTAGE_SWING_600
:
2421 return DP_TRAIN_PRE_EMPHASIS_6
;
2422 case DP_TRAIN_VOLTAGE_SWING_800
:
2423 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2424 case DP_TRAIN_VOLTAGE_SWING_1200
:
2426 return DP_TRAIN_PRE_EMPHASIS_0
;
2428 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2429 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2430 case DP_TRAIN_VOLTAGE_SWING_400
:
2431 return DP_TRAIN_PRE_EMPHASIS_6
;
2432 case DP_TRAIN_VOLTAGE_SWING_600
:
2433 case DP_TRAIN_VOLTAGE_SWING_800
:
2434 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2436 return DP_TRAIN_PRE_EMPHASIS_0
;
2439 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2440 case DP_TRAIN_VOLTAGE_SWING_400
:
2441 return DP_TRAIN_PRE_EMPHASIS_6
;
2442 case DP_TRAIN_VOLTAGE_SWING_600
:
2443 return DP_TRAIN_PRE_EMPHASIS_6
;
2444 case DP_TRAIN_VOLTAGE_SWING_800
:
2445 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2446 case DP_TRAIN_VOLTAGE_SWING_1200
:
2448 return DP_TRAIN_PRE_EMPHASIS_0
;
2453 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2455 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2458 struct intel_crtc
*intel_crtc
=
2459 to_intel_crtc(dport
->base
.base
.crtc
);
2460 unsigned long demph_reg_value
, preemph_reg_value
,
2461 uniqtranscale_reg_value
;
2462 uint8_t train_set
= intel_dp
->train_set
[0];
2463 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2464 int pipe
= intel_crtc
->pipe
;
2466 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2467 case DP_TRAIN_PRE_EMPHASIS_0
:
2468 preemph_reg_value
= 0x0004000;
2469 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2470 case DP_TRAIN_VOLTAGE_SWING_400
:
2471 demph_reg_value
= 0x2B405555;
2472 uniqtranscale_reg_value
= 0x552AB83A;
2474 case DP_TRAIN_VOLTAGE_SWING_600
:
2475 demph_reg_value
= 0x2B404040;
2476 uniqtranscale_reg_value
= 0x5548B83A;
2478 case DP_TRAIN_VOLTAGE_SWING_800
:
2479 demph_reg_value
= 0x2B245555;
2480 uniqtranscale_reg_value
= 0x5560B83A;
2482 case DP_TRAIN_VOLTAGE_SWING_1200
:
2483 demph_reg_value
= 0x2B405555;
2484 uniqtranscale_reg_value
= 0x5598DA3A;
2490 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2491 preemph_reg_value
= 0x0002000;
2492 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2493 case DP_TRAIN_VOLTAGE_SWING_400
:
2494 demph_reg_value
= 0x2B404040;
2495 uniqtranscale_reg_value
= 0x5552B83A;
2497 case DP_TRAIN_VOLTAGE_SWING_600
:
2498 demph_reg_value
= 0x2B404848;
2499 uniqtranscale_reg_value
= 0x5580B83A;
2501 case DP_TRAIN_VOLTAGE_SWING_800
:
2502 demph_reg_value
= 0x2B404040;
2503 uniqtranscale_reg_value
= 0x55ADDA3A;
2509 case DP_TRAIN_PRE_EMPHASIS_6
:
2510 preemph_reg_value
= 0x0000000;
2511 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2512 case DP_TRAIN_VOLTAGE_SWING_400
:
2513 demph_reg_value
= 0x2B305555;
2514 uniqtranscale_reg_value
= 0x5570B83A;
2516 case DP_TRAIN_VOLTAGE_SWING_600
:
2517 demph_reg_value
= 0x2B2B4040;
2518 uniqtranscale_reg_value
= 0x55ADDA3A;
2524 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2525 preemph_reg_value
= 0x0006000;
2526 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2527 case DP_TRAIN_VOLTAGE_SWING_400
:
2528 demph_reg_value
= 0x1B405555;
2529 uniqtranscale_reg_value
= 0x55ADDA3A;
2539 mutex_lock(&dev_priv
->dpio_lock
);
2540 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2541 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2542 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2543 uniqtranscale_reg_value
);
2544 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2545 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2546 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2547 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2548 mutex_unlock(&dev_priv
->dpio_lock
);
2553 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2555 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2557 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2558 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2559 u32 deemph_reg_value
, margin_reg_value
, val
;
2560 uint8_t train_set
= intel_dp
->train_set
[0];
2561 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2562 enum pipe pipe
= intel_crtc
->pipe
;
2565 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2566 case DP_TRAIN_PRE_EMPHASIS_0
:
2567 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2568 case DP_TRAIN_VOLTAGE_SWING_400
:
2569 deemph_reg_value
= 128;
2570 margin_reg_value
= 52;
2572 case DP_TRAIN_VOLTAGE_SWING_600
:
2573 deemph_reg_value
= 128;
2574 margin_reg_value
= 77;
2576 case DP_TRAIN_VOLTAGE_SWING_800
:
2577 deemph_reg_value
= 128;
2578 margin_reg_value
= 102;
2580 case DP_TRAIN_VOLTAGE_SWING_1200
:
2581 deemph_reg_value
= 128;
2582 margin_reg_value
= 154;
2583 /* FIXME extra to set for 1200 */
2589 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2590 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2591 case DP_TRAIN_VOLTAGE_SWING_400
:
2592 deemph_reg_value
= 85;
2593 margin_reg_value
= 78;
2595 case DP_TRAIN_VOLTAGE_SWING_600
:
2596 deemph_reg_value
= 85;
2597 margin_reg_value
= 116;
2599 case DP_TRAIN_VOLTAGE_SWING_800
:
2600 deemph_reg_value
= 85;
2601 margin_reg_value
= 154;
2607 case DP_TRAIN_PRE_EMPHASIS_6
:
2608 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2609 case DP_TRAIN_VOLTAGE_SWING_400
:
2610 deemph_reg_value
= 64;
2611 margin_reg_value
= 104;
2613 case DP_TRAIN_VOLTAGE_SWING_600
:
2614 deemph_reg_value
= 64;
2615 margin_reg_value
= 154;
2621 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2622 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2623 case DP_TRAIN_VOLTAGE_SWING_400
:
2624 deemph_reg_value
= 43;
2625 margin_reg_value
= 154;
2635 mutex_lock(&dev_priv
->dpio_lock
);
2637 /* Clear calc init */
2638 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2639 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2640 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2642 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2643 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2644 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2646 /* Program swing deemph */
2647 for (i
= 0; i
< 4; i
++) {
2648 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2649 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2650 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2651 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2654 /* Program swing margin */
2655 for (i
= 0; i
< 4; i
++) {
2656 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2657 val
&= ~DPIO_SWING_MARGIN_MASK
;
2658 val
|= margin_reg_value
<< DPIO_SWING_MARGIN_SHIFT
;
2659 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2662 /* Disable unique transition scale */
2663 for (i
= 0; i
< 4; i
++) {
2664 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2665 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2666 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2669 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
2670 == DP_TRAIN_PRE_EMPHASIS_0
) &&
2671 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
2672 == DP_TRAIN_VOLTAGE_SWING_1200
)) {
2675 * The document said it needs to set bit 27 for ch0 and bit 26
2676 * for ch1. Might be a typo in the doc.
2677 * For now, for this unique transition scale selection, set bit
2678 * 27 for ch0 and ch1.
2680 for (i
= 0; i
< 4; i
++) {
2681 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2682 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2683 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2686 for (i
= 0; i
< 4; i
++) {
2687 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2688 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2689 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2690 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2694 /* Start swing calculation */
2695 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2696 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2697 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2699 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2700 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2701 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2704 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
2705 val
|= DPIO_LRC_BYPASS
;
2706 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
2708 mutex_unlock(&dev_priv
->dpio_lock
);
2714 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2715 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2720 uint8_t voltage_max
;
2721 uint8_t preemph_max
;
2723 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2724 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2725 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2733 voltage_max
= intel_dp_voltage_max(intel_dp
);
2734 if (v
>= voltage_max
)
2735 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2737 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2738 if (p
>= preemph_max
)
2739 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2741 for (lane
= 0; lane
< 4; lane
++)
2742 intel_dp
->train_set
[lane
] = v
| p
;
2746 intel_gen4_signal_levels(uint8_t train_set
)
2748 uint32_t signal_levels
= 0;
2750 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2751 case DP_TRAIN_VOLTAGE_SWING_400
:
2753 signal_levels
|= DP_VOLTAGE_0_4
;
2755 case DP_TRAIN_VOLTAGE_SWING_600
:
2756 signal_levels
|= DP_VOLTAGE_0_6
;
2758 case DP_TRAIN_VOLTAGE_SWING_800
:
2759 signal_levels
|= DP_VOLTAGE_0_8
;
2761 case DP_TRAIN_VOLTAGE_SWING_1200
:
2762 signal_levels
|= DP_VOLTAGE_1_2
;
2765 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2766 case DP_TRAIN_PRE_EMPHASIS_0
:
2768 signal_levels
|= DP_PRE_EMPHASIS_0
;
2770 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2771 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2773 case DP_TRAIN_PRE_EMPHASIS_6
:
2774 signal_levels
|= DP_PRE_EMPHASIS_6
;
2776 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2777 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2780 return signal_levels
;
2783 /* Gen6's DP voltage swing and pre-emphasis control */
2785 intel_gen6_edp_signal_levels(uint8_t train_set
)
2787 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2788 DP_TRAIN_PRE_EMPHASIS_MASK
);
2789 switch (signal_levels
) {
2790 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2791 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2792 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2793 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2794 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2795 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2796 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2797 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2798 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2799 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2800 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2801 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2802 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2803 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2805 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2806 "0x%x\n", signal_levels
);
2807 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2811 /* Gen7's DP voltage swing and pre-emphasis control */
2813 intel_gen7_edp_signal_levels(uint8_t train_set
)
2815 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2816 DP_TRAIN_PRE_EMPHASIS_MASK
);
2817 switch (signal_levels
) {
2818 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2819 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2820 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2821 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2822 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2823 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2825 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2826 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2827 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2828 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2830 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2831 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2832 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2833 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2836 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2837 "0x%x\n", signal_levels
);
2838 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2842 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2844 intel_hsw_signal_levels(uint8_t train_set
)
2846 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2847 DP_TRAIN_PRE_EMPHASIS_MASK
);
2848 switch (signal_levels
) {
2849 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2850 return DDI_BUF_EMP_400MV_0DB_HSW
;
2851 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2852 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2853 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2854 return DDI_BUF_EMP_400MV_6DB_HSW
;
2855 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2856 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2858 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2859 return DDI_BUF_EMP_600MV_0DB_HSW
;
2860 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2861 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2862 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2863 return DDI_BUF_EMP_600MV_6DB_HSW
;
2865 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2866 return DDI_BUF_EMP_800MV_0DB_HSW
;
2867 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2868 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2870 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2871 "0x%x\n", signal_levels
);
2872 return DDI_BUF_EMP_400MV_0DB_HSW
;
2876 /* Properly updates "DP" with the correct signal levels. */
2878 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2880 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2881 enum port port
= intel_dig_port
->port
;
2882 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2883 uint32_t signal_levels
, mask
;
2884 uint8_t train_set
= intel_dp
->train_set
[0];
2886 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2887 signal_levels
= intel_hsw_signal_levels(train_set
);
2888 mask
= DDI_BUF_EMP_MASK
;
2889 } else if (IS_CHERRYVIEW(dev
)) {
2890 signal_levels
= intel_chv_signal_levels(intel_dp
);
2892 } else if (IS_VALLEYVIEW(dev
)) {
2893 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2895 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2896 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2897 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2898 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2899 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2900 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2902 signal_levels
= intel_gen4_signal_levels(train_set
);
2903 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2906 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2908 *DP
= (*DP
& ~mask
) | signal_levels
;
2912 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2914 uint8_t dp_train_pat
)
2916 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2917 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2919 enum port port
= intel_dig_port
->port
;
2920 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2924 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2926 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2927 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2929 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2931 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2932 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2933 case DP_TRAINING_PATTERN_DISABLE
:
2934 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2937 case DP_TRAINING_PATTERN_1
:
2938 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2940 case DP_TRAINING_PATTERN_2
:
2941 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2943 case DP_TRAINING_PATTERN_3
:
2944 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2947 I915_WRITE(DP_TP_CTL(port
), temp
);
2949 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2950 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2952 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2953 case DP_TRAINING_PATTERN_DISABLE
:
2954 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2956 case DP_TRAINING_PATTERN_1
:
2957 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2959 case DP_TRAINING_PATTERN_2
:
2960 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2962 case DP_TRAINING_PATTERN_3
:
2963 DRM_ERROR("DP training pattern 3 not supported\n");
2964 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2969 *DP
&= ~DP_LINK_TRAIN_MASK
;
2971 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2972 case DP_TRAINING_PATTERN_DISABLE
:
2973 *DP
|= DP_LINK_TRAIN_OFF
;
2975 case DP_TRAINING_PATTERN_1
:
2976 *DP
|= DP_LINK_TRAIN_PAT_1
;
2978 case DP_TRAINING_PATTERN_2
:
2979 *DP
|= DP_LINK_TRAIN_PAT_2
;
2981 case DP_TRAINING_PATTERN_3
:
2982 DRM_ERROR("DP training pattern 3 not supported\n");
2983 *DP
|= DP_LINK_TRAIN_PAT_2
;
2988 I915_WRITE(intel_dp
->output_reg
, *DP
);
2989 POSTING_READ(intel_dp
->output_reg
);
2991 buf
[0] = dp_train_pat
;
2992 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2993 DP_TRAINING_PATTERN_DISABLE
) {
2994 /* don't write DP_TRAINING_LANEx_SET on disable */
2997 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2998 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
2999 len
= intel_dp
->lane_count
+ 1;
3002 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3009 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3010 uint8_t dp_train_pat
)
3012 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3013 intel_dp_set_signal_levels(intel_dp
, DP
);
3014 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3018 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3019 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3021 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3022 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3026 intel_get_adjust_train(intel_dp
, link_status
);
3027 intel_dp_set_signal_levels(intel_dp
, DP
);
3029 I915_WRITE(intel_dp
->output_reg
, *DP
);
3030 POSTING_READ(intel_dp
->output_reg
);
3032 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3033 intel_dp
->train_set
, intel_dp
->lane_count
);
3035 return ret
== intel_dp
->lane_count
;
3038 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3040 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3041 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3043 enum port port
= intel_dig_port
->port
;
3049 val
= I915_READ(DP_TP_CTL(port
));
3050 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3051 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3052 I915_WRITE(DP_TP_CTL(port
), val
);
3055 * On PORT_A we can have only eDP in SST mode. There the only reason
3056 * we need to set idle transmission mode is to work around a HW issue
3057 * where we enable the pipe while not in idle link-training mode.
3058 * In this case there is requirement to wait for a minimum number of
3059 * idle patterns to be sent.
3064 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3066 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3069 /* Enable corresponding port and start training pattern 1 */
3071 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3073 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3074 struct drm_device
*dev
= encoder
->dev
;
3077 int voltage_tries
, loop_tries
;
3078 uint32_t DP
= intel_dp
->DP
;
3079 uint8_t link_config
[2];
3082 intel_ddi_prepare_link_retrain(encoder
);
3084 /* Write the link configuration data */
3085 link_config
[0] = intel_dp
->link_bw
;
3086 link_config
[1] = intel_dp
->lane_count
;
3087 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3088 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3089 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3092 link_config
[1] = DP_SET_ANSI_8B10B
;
3093 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3097 /* clock recovery */
3098 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3099 DP_TRAINING_PATTERN_1
|
3100 DP_LINK_SCRAMBLING_DISABLE
)) {
3101 DRM_ERROR("failed to enable link training\n");
3109 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3111 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3112 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3113 DRM_ERROR("failed to get link status\n");
3117 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3118 DRM_DEBUG_KMS("clock recovery OK\n");
3122 /* Check to see if we've tried the max voltage */
3123 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3124 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3126 if (i
== intel_dp
->lane_count
) {
3128 if (loop_tries
== 5) {
3129 DRM_ERROR("too many full retries, give up\n");
3132 intel_dp_reset_link_train(intel_dp
, &DP
,
3133 DP_TRAINING_PATTERN_1
|
3134 DP_LINK_SCRAMBLING_DISABLE
);
3139 /* Check to see if we've tried the same voltage 5 times */
3140 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3142 if (voltage_tries
== 5) {
3143 DRM_ERROR("too many voltage retries, give up\n");
3148 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3150 /* Update training set as requested by target */
3151 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3152 DRM_ERROR("failed to update link training\n");
3161 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3163 bool channel_eq
= false;
3164 int tries
, cr_tries
;
3165 uint32_t DP
= intel_dp
->DP
;
3166 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3168 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3169 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3170 training_pattern
= DP_TRAINING_PATTERN_3
;
3172 /* channel equalization */
3173 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3175 DP_LINK_SCRAMBLING_DISABLE
)) {
3176 DRM_ERROR("failed to start channel equalization\n");
3184 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3187 DRM_ERROR("failed to train DP, aborting\n");
3191 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3192 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3193 DRM_ERROR("failed to get link status\n");
3197 /* Make sure clock is still ok */
3198 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3199 intel_dp_start_link_train(intel_dp
);
3200 intel_dp_set_link_train(intel_dp
, &DP
,
3202 DP_LINK_SCRAMBLING_DISABLE
);
3207 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3212 /* Try 5 times, then try clock recovery if that fails */
3214 intel_dp_link_down(intel_dp
);
3215 intel_dp_start_link_train(intel_dp
);
3216 intel_dp_set_link_train(intel_dp
, &DP
,
3218 DP_LINK_SCRAMBLING_DISABLE
);
3224 /* Update training set as requested by target */
3225 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3226 DRM_ERROR("failed to update link training\n");
3232 intel_dp_set_idle_link_train(intel_dp
);
3237 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3241 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3243 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3244 DP_TRAINING_PATTERN_DISABLE
);
3248 intel_dp_link_down(struct intel_dp
*intel_dp
)
3250 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3251 enum port port
= intel_dig_port
->port
;
3252 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3254 struct intel_crtc
*intel_crtc
=
3255 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3256 uint32_t DP
= intel_dp
->DP
;
3258 if (WARN_ON(HAS_DDI(dev
)))
3261 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3264 DRM_DEBUG_KMS("\n");
3266 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3267 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3268 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3270 DP
&= ~DP_LINK_TRAIN_MASK
;
3271 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3273 POSTING_READ(intel_dp
->output_reg
);
3275 if (HAS_PCH_IBX(dev
) &&
3276 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3277 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3279 /* Hardware workaround: leaving our transcoder select
3280 * set to transcoder B while it's off will prevent the
3281 * corresponding HDMI output on transcoder A.
3283 * Combine this with another hardware workaround:
3284 * transcoder select bit can only be cleared while the
3287 DP
&= ~DP_PIPEB_SELECT
;
3288 I915_WRITE(intel_dp
->output_reg
, DP
);
3290 /* Changes to enable or select take place the vblank
3291 * after being written.
3293 if (WARN_ON(crtc
== NULL
)) {
3294 /* We should never try to disable a port without a crtc
3295 * attached. For paranoia keep the code around for a
3297 POSTING_READ(intel_dp
->output_reg
);
3300 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3303 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3304 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3305 POSTING_READ(intel_dp
->output_reg
);
3306 msleep(intel_dp
->panel_power_down_delay
);
3310 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3312 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3313 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3316 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
3318 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3319 sizeof(intel_dp
->dpcd
)) < 0)
3320 return false; /* aux transfer failed */
3322 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
3323 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
3324 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
3326 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3327 return false; /* DPCD not present */
3329 /* Check if the panel supports PSR */
3330 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3331 if (is_edp(intel_dp
)) {
3332 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3334 sizeof(intel_dp
->psr_dpcd
));
3335 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3336 dev_priv
->psr
.sink_support
= true;
3337 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3341 /* Training Pattern 3 support */
3342 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3343 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3344 intel_dp
->use_tps3
= true;
3345 DRM_DEBUG_KMS("Displayport TPS3 supported");
3347 intel_dp
->use_tps3
= false;
3349 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3350 DP_DWN_STRM_PORT_PRESENT
))
3351 return true; /* native DP sink */
3353 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3354 return true; /* no per-port downstream info */
3356 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3357 intel_dp
->downstream_ports
,
3358 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3359 return false; /* downstream port status fetch failed */
3365 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3369 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3372 intel_edp_panel_vdd_on(intel_dp
);
3374 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3375 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3376 buf
[0], buf
[1], buf
[2]);
3378 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3379 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3380 buf
[0], buf
[1], buf
[2]);
3382 edp_panel_vdd_off(intel_dp
, false);
3386 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3390 if (!intel_dp
->can_mst
)
3393 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3396 _edp_panel_vdd_on(intel_dp
);
3397 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3398 if (buf
[0] & DP_MST_CAP
) {
3399 DRM_DEBUG_KMS("Sink is MST capable\n");
3400 intel_dp
->is_mst
= true;
3402 DRM_DEBUG_KMS("Sink is not MST capable\n");
3403 intel_dp
->is_mst
= false;
3406 edp_panel_vdd_off(intel_dp
, false);
3408 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3409 return intel_dp
->is_mst
;
3412 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3414 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3415 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3416 struct intel_crtc
*intel_crtc
=
3417 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3420 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3423 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3426 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3427 DP_TEST_SINK_START
) < 0)
3430 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3431 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3432 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3434 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3437 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3442 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3444 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3445 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3446 sink_irq_vector
, 1) == 1;
3450 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3454 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3456 sink_irq_vector
, 14);
3464 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3466 /* NAK by default */
3467 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3471 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3475 if (intel_dp
->is_mst
) {
3480 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3484 /* check link status - esi[10] = 0x200c */
3485 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3486 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3487 intel_dp_start_link_train(intel_dp
);
3488 intel_dp_complete_link_train(intel_dp
);
3489 intel_dp_stop_link_train(intel_dp
);
3492 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3493 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3496 for (retry
= 0; retry
< 3; retry
++) {
3498 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3499 DP_SINK_COUNT_ESI
+1,
3506 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3508 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3516 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3517 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3518 intel_dp
->is_mst
= false;
3519 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3520 /* send a hotplug event */
3521 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3528 * According to DP spec
3531 * 2. Configure link according to Receiver Capabilities
3532 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3533 * 4. Check link status on receipt of hot-plug interrupt
3536 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3538 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3540 u8 link_status
[DP_LINK_STATUS_SIZE
];
3542 /* FIXME: This access isn't protected by any locks. */
3543 if (!intel_encoder
->connectors_active
)
3546 if (WARN_ON(!intel_encoder
->base
.crtc
))
3549 /* Try to read receiver status if the link appears to be up */
3550 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3554 /* Now read the DPCD to see if it's actually running */
3555 if (!intel_dp_get_dpcd(intel_dp
)) {
3559 /* Try to read the source of the interrupt */
3560 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3561 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3562 /* Clear interrupt source */
3563 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3564 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3567 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3568 intel_dp_handle_test_request(intel_dp
);
3569 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3570 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3573 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3574 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3575 intel_encoder
->base
.name
);
3576 intel_dp_start_link_train(intel_dp
);
3577 intel_dp_complete_link_train(intel_dp
);
3578 intel_dp_stop_link_train(intel_dp
);
3582 /* XXX this is probably wrong for multiple downstream ports */
3583 static enum drm_connector_status
3584 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3586 uint8_t *dpcd
= intel_dp
->dpcd
;
3589 if (!intel_dp_get_dpcd(intel_dp
))
3590 return connector_status_disconnected
;
3592 /* if there's no downstream port, we're done */
3593 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3594 return connector_status_connected
;
3596 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3597 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3598 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3601 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3603 return connector_status_unknown
;
3605 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3606 : connector_status_disconnected
;
3609 /* If no HPD, poke DDC gently */
3610 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3611 return connector_status_connected
;
3613 /* Well we tried, say unknown for unreliable port types */
3614 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3615 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3616 if (type
== DP_DS_PORT_TYPE_VGA
||
3617 type
== DP_DS_PORT_TYPE_NON_EDID
)
3618 return connector_status_unknown
;
3620 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3621 DP_DWN_STRM_PORT_TYPE_MASK
;
3622 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3623 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3624 return connector_status_unknown
;
3627 /* Anything else is out of spec, warn and ignore */
3628 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3629 return connector_status_disconnected
;
3632 static enum drm_connector_status
3633 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3635 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3637 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3638 enum drm_connector_status status
;
3640 /* Can't disconnect eDP, but you can close the lid... */
3641 if (is_edp(intel_dp
)) {
3642 status
= intel_panel_detect(dev
);
3643 if (status
== connector_status_unknown
)
3644 status
= connector_status_connected
;
3648 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3649 return connector_status_disconnected
;
3651 return intel_dp_detect_dpcd(intel_dp
);
3654 static enum drm_connector_status
3655 g4x_dp_detect(struct intel_dp
*intel_dp
)
3657 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3659 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3662 /* Can't disconnect eDP, but you can close the lid... */
3663 if (is_edp(intel_dp
)) {
3664 enum drm_connector_status status
;
3666 status
= intel_panel_detect(dev
);
3667 if (status
== connector_status_unknown
)
3668 status
= connector_status_connected
;
3672 if (IS_VALLEYVIEW(dev
)) {
3673 switch (intel_dig_port
->port
) {
3675 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3678 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3681 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3684 return connector_status_unknown
;
3687 switch (intel_dig_port
->port
) {
3689 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3692 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3695 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3698 return connector_status_unknown
;
3702 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3703 return connector_status_disconnected
;
3705 return intel_dp_detect_dpcd(intel_dp
);
3708 static struct edid
*
3709 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3711 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3713 /* use cached edid if we have one */
3714 if (intel_connector
->edid
) {
3716 if (IS_ERR(intel_connector
->edid
))
3719 return drm_edid_duplicate(intel_connector
->edid
);
3722 return drm_get_edid(connector
, adapter
);
3726 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3728 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3730 /* use cached edid if we have one */
3731 if (intel_connector
->edid
) {
3733 if (IS_ERR(intel_connector
->edid
))
3736 return intel_connector_update_modes(connector
,
3737 intel_connector
->edid
);
3740 return intel_ddc_get_modes(connector
, adapter
);
3743 static enum drm_connector_status
3744 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3746 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3747 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3748 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3749 struct drm_device
*dev
= connector
->dev
;
3750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3751 enum drm_connector_status status
;
3752 enum intel_display_power_domain power_domain
;
3753 struct edid
*edid
= NULL
;
3756 power_domain
= intel_display_port_power_domain(intel_encoder
);
3757 intel_display_power_get(dev_priv
, power_domain
);
3759 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3760 connector
->base
.id
, connector
->name
);
3762 if (intel_dp
->is_mst
) {
3763 /* MST devices are disconnected from a monitor POV */
3764 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3765 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3766 status
= connector_status_disconnected
;
3770 intel_dp
->has_audio
= false;
3772 if (HAS_PCH_SPLIT(dev
))
3773 status
= ironlake_dp_detect(intel_dp
);
3775 status
= g4x_dp_detect(intel_dp
);
3777 if (status
!= connector_status_connected
)
3780 intel_dp_probe_oui(intel_dp
);
3782 ret
= intel_dp_probe_mst(intel_dp
);
3784 /* if we are in MST mode then this connector
3785 won't appear connected or have anything with EDID on it */
3786 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3787 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3788 status
= connector_status_disconnected
;
3792 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3793 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3795 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3797 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3802 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3803 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3804 status
= connector_status_connected
;
3807 intel_display_power_put(dev_priv
, power_domain
);
3811 static int intel_dp_get_modes(struct drm_connector
*connector
)
3813 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3814 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3815 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3816 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3817 struct drm_device
*dev
= connector
->dev
;
3818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3819 enum intel_display_power_domain power_domain
;
3822 /* We should parse the EDID data and find out if it has an audio sink
3825 power_domain
= intel_display_port_power_domain(intel_encoder
);
3826 intel_display_power_get(dev_priv
, power_domain
);
3828 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3829 intel_display_power_put(dev_priv
, power_domain
);
3833 /* if eDP has no EDID, fall back to fixed mode */
3834 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3835 struct drm_display_mode
*mode
;
3836 mode
= drm_mode_duplicate(dev
,
3837 intel_connector
->panel
.fixed_mode
);
3839 drm_mode_probed_add(connector
, mode
);
3847 intel_dp_detect_audio(struct drm_connector
*connector
)
3849 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3850 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3851 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3852 struct drm_device
*dev
= connector
->dev
;
3853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3854 enum intel_display_power_domain power_domain
;
3856 bool has_audio
= false;
3858 power_domain
= intel_display_port_power_domain(intel_encoder
);
3859 intel_display_power_get(dev_priv
, power_domain
);
3861 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3863 has_audio
= drm_detect_monitor_audio(edid
);
3867 intel_display_power_put(dev_priv
, power_domain
);
3873 intel_dp_set_property(struct drm_connector
*connector
,
3874 struct drm_property
*property
,
3877 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3878 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3879 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3880 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3883 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3887 if (property
== dev_priv
->force_audio_property
) {
3891 if (i
== intel_dp
->force_audio
)
3894 intel_dp
->force_audio
= i
;
3896 if (i
== HDMI_AUDIO_AUTO
)
3897 has_audio
= intel_dp_detect_audio(connector
);
3899 has_audio
= (i
== HDMI_AUDIO_ON
);
3901 if (has_audio
== intel_dp
->has_audio
)
3904 intel_dp
->has_audio
= has_audio
;
3908 if (property
== dev_priv
->broadcast_rgb_property
) {
3909 bool old_auto
= intel_dp
->color_range_auto
;
3910 uint32_t old_range
= intel_dp
->color_range
;
3913 case INTEL_BROADCAST_RGB_AUTO
:
3914 intel_dp
->color_range_auto
= true;
3916 case INTEL_BROADCAST_RGB_FULL
:
3917 intel_dp
->color_range_auto
= false;
3918 intel_dp
->color_range
= 0;
3920 case INTEL_BROADCAST_RGB_LIMITED
:
3921 intel_dp
->color_range_auto
= false;
3922 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3928 if (old_auto
== intel_dp
->color_range_auto
&&
3929 old_range
== intel_dp
->color_range
)
3935 if (is_edp(intel_dp
) &&
3936 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3937 if (val
== DRM_MODE_SCALE_NONE
) {
3938 DRM_DEBUG_KMS("no scaling not supported\n");
3942 if (intel_connector
->panel
.fitting_mode
== val
) {
3943 /* the eDP scaling property is not changed */
3946 intel_connector
->panel
.fitting_mode
= val
;
3954 if (intel_encoder
->base
.crtc
)
3955 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3961 intel_dp_connector_destroy(struct drm_connector
*connector
)
3963 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3965 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3966 kfree(intel_connector
->edid
);
3968 /* Can't call is_edp() since the encoder may have been destroyed
3970 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3971 intel_panel_fini(&intel_connector
->panel
);
3973 drm_connector_cleanup(connector
);
3977 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3979 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3980 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3981 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3983 drm_dp_aux_unregister(&intel_dp
->aux
);
3984 intel_dp_mst_encoder_cleanup(intel_dig_port
);
3985 drm_encoder_cleanup(encoder
);
3986 if (is_edp(intel_dp
)) {
3987 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3988 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3989 edp_panel_vdd_off_sync(intel_dp
);
3990 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
3991 if (intel_dp
->edp_notifier
.notifier_call
) {
3992 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
3993 intel_dp
->edp_notifier
.notifier_call
= NULL
;
3996 kfree(intel_dig_port
);
3999 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4000 .dpms
= intel_connector_dpms
,
4001 .detect
= intel_dp_detect
,
4002 .fill_modes
= drm_helper_probe_single_connector_modes
,
4003 .set_property
= intel_dp_set_property
,
4004 .destroy
= intel_dp_connector_destroy
,
4007 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4008 .get_modes
= intel_dp_get_modes
,
4009 .mode_valid
= intel_dp_mode_valid
,
4010 .best_encoder
= intel_best_encoder
,
4013 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4014 .destroy
= intel_dp_encoder_destroy
,
4018 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4024 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4026 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4027 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4030 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4031 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4033 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port
->port
,
4034 long_hpd
? "long" : "short");
4037 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4040 if (!intel_dp_get_dpcd(intel_dp
)) {
4044 intel_dp_probe_oui(intel_dp
);
4046 if (!intel_dp_probe_mst(intel_dp
))
4050 if (intel_dp
->is_mst
) {
4051 ret
= intel_dp_check_mst_status(intel_dp
);
4056 if (!intel_dp
->is_mst
) {
4058 * we'll check the link status via the normal hot plug path later -
4059 * but for short hpds we should check it now
4061 intel_dp_check_link_status(intel_dp
);
4066 /* if we were in MST mode, and device is not there get out of MST mode */
4067 if (intel_dp
->is_mst
) {
4068 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4069 intel_dp
->is_mst
= false;
4070 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4075 /* Return which DP Port should be selected for Transcoder DP control */
4077 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4079 struct drm_device
*dev
= crtc
->dev
;
4080 struct intel_encoder
*intel_encoder
;
4081 struct intel_dp
*intel_dp
;
4083 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4084 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4086 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4087 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4088 return intel_dp
->output_reg
;
4094 /* check the VBT to see whether the eDP is on DP-D port */
4095 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4098 union child_device_config
*p_child
;
4100 static const short port_mapping
[] = {
4101 [PORT_B
] = PORT_IDPB
,
4102 [PORT_C
] = PORT_IDPC
,
4103 [PORT_D
] = PORT_IDPD
,
4109 if (!dev_priv
->vbt
.child_dev_num
)
4112 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4113 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4115 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4116 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4117 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4124 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4126 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4128 intel_attach_force_audio_property(connector
);
4129 intel_attach_broadcast_rgb_property(connector
);
4130 intel_dp
->color_range_auto
= true;
4132 if (is_edp(intel_dp
)) {
4133 drm_mode_create_scaling_mode_property(connector
->dev
);
4134 drm_object_attach_property(
4136 connector
->dev
->mode_config
.scaling_mode_property
,
4137 DRM_MODE_SCALE_ASPECT
);
4138 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4142 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4144 intel_dp
->last_power_cycle
= jiffies
;
4145 intel_dp
->last_power_on
= jiffies
;
4146 intel_dp
->last_backlight_off
= jiffies
;
4150 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4151 struct intel_dp
*intel_dp
,
4152 struct edp_power_seq
*out
)
4154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4155 struct edp_power_seq cur
, vbt
, spec
, final
;
4156 u32 pp_on
, pp_off
, pp_div
, pp
;
4157 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4159 if (HAS_PCH_SPLIT(dev
)) {
4160 pp_ctrl_reg
= PCH_PP_CONTROL
;
4161 pp_on_reg
= PCH_PP_ON_DELAYS
;
4162 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4163 pp_div_reg
= PCH_PP_DIVISOR
;
4165 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4167 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4168 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4169 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4170 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4173 /* Workaround: Need to write PP_CONTROL with the unlock key as
4174 * the very first thing. */
4175 pp
= ironlake_get_pp_control(intel_dp
);
4176 I915_WRITE(pp_ctrl_reg
, pp
);
4178 pp_on
= I915_READ(pp_on_reg
);
4179 pp_off
= I915_READ(pp_off_reg
);
4180 pp_div
= I915_READ(pp_div_reg
);
4182 /* Pull timing values out of registers */
4183 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4184 PANEL_POWER_UP_DELAY_SHIFT
;
4186 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4187 PANEL_LIGHT_ON_DELAY_SHIFT
;
4189 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4190 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4192 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4193 PANEL_POWER_DOWN_DELAY_SHIFT
;
4195 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4196 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4198 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4199 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4201 vbt
= dev_priv
->vbt
.edp_pps
;
4203 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4204 * our hw here, which are all in 100usec. */
4205 spec
.t1_t3
= 210 * 10;
4206 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4207 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4208 spec
.t10
= 500 * 10;
4209 /* This one is special and actually in units of 100ms, but zero
4210 * based in the hw (so we need to add 100 ms). But the sw vbt
4211 * table multiplies it with 1000 to make it in units of 100usec,
4213 spec
.t11_t12
= (510 + 100) * 10;
4215 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4216 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4218 /* Use the max of the register settings and vbt. If both are
4219 * unset, fall back to the spec limits. */
4220 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4222 max(cur.field, vbt.field))
4223 assign_final(t1_t3
);
4227 assign_final(t11_t12
);
4230 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4231 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4232 intel_dp
->backlight_on_delay
= get_delay(t8
);
4233 intel_dp
->backlight_off_delay
= get_delay(t9
);
4234 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4235 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4238 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4239 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4240 intel_dp
->panel_power_cycle_delay
);
4242 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4243 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4250 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4251 struct intel_dp
*intel_dp
,
4252 struct edp_power_seq
*seq
)
4254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4255 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4256 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4257 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4259 if (HAS_PCH_SPLIT(dev
)) {
4260 pp_on_reg
= PCH_PP_ON_DELAYS
;
4261 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4262 pp_div_reg
= PCH_PP_DIVISOR
;
4264 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4266 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4267 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4268 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4272 * And finally store the new values in the power sequencer. The
4273 * backlight delays are set to 1 because we do manual waits on them. For
4274 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4275 * we'll end up waiting for the backlight off delay twice: once when we
4276 * do the manual sleep, and once when we disable the panel and wait for
4277 * the PP_STATUS bit to become zero.
4279 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4280 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4281 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4282 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4283 /* Compute the divisor for the pp clock, simply match the Bspec
4285 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4286 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4287 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4289 /* Haswell doesn't have any port selection bits for the panel
4290 * power sequencer any more. */
4291 if (IS_VALLEYVIEW(dev
)) {
4292 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
4293 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
4295 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
4296 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4297 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
4298 port_sel
= PANEL_PORT_SELECT_DPA
;
4300 port_sel
= PANEL_PORT_SELECT_DPD
;
4305 I915_WRITE(pp_on_reg
, pp_on
);
4306 I915_WRITE(pp_off_reg
, pp_off
);
4307 I915_WRITE(pp_div_reg
, pp_div
);
4309 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4310 I915_READ(pp_on_reg
),
4311 I915_READ(pp_off_reg
),
4312 I915_READ(pp_div_reg
));
4315 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4318 struct intel_encoder
*encoder
;
4319 struct intel_dp
*intel_dp
= NULL
;
4320 struct intel_crtc_config
*config
= NULL
;
4321 struct intel_crtc
*intel_crtc
= NULL
;
4322 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4324 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4326 if (refresh_rate
<= 0) {
4327 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4331 if (intel_connector
== NULL
) {
4332 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4337 * FIXME: This needs proper synchronization with psr state. But really
4338 * hard to tell without seeing the user of this function of this code.
4339 * Check locking and ordering once that lands.
4341 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4342 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4346 encoder
= intel_attached_encoder(&intel_connector
->base
);
4347 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4348 intel_crtc
= encoder
->new_crtc
;
4351 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4355 config
= &intel_crtc
->config
;
4357 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4358 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4362 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4363 index
= DRRS_LOW_RR
;
4365 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4367 "DRRS requested for previously set RR...ignoring\n");
4371 if (!intel_crtc
->active
) {
4372 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4376 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4377 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4378 val
= I915_READ(reg
);
4379 if (index
> DRRS_HIGH_RR
) {
4380 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4381 intel_dp_set_m2_n2(intel_crtc
, &config
->dp_m2_n2
);
4383 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4385 I915_WRITE(reg
, val
);
4389 * mutex taken to ensure that there is no race between differnt
4390 * drrs calls trying to update refresh rate. This scenario may occur
4391 * in future when idleness detection based DRRS in kernel and
4392 * possible calls from user space to set differnt RR are made.
4395 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4397 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4399 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4401 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4404 static struct drm_display_mode
*
4405 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4406 struct intel_connector
*intel_connector
,
4407 struct drm_display_mode
*fixed_mode
)
4409 struct drm_connector
*connector
= &intel_connector
->base
;
4410 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4411 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4413 struct drm_display_mode
*downclock_mode
= NULL
;
4415 if (INTEL_INFO(dev
)->gen
<= 6) {
4416 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4420 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4421 DRM_INFO("VBT doesn't support DRRS\n");
4425 downclock_mode
= intel_find_panel_downclock
4426 (dev
, fixed_mode
, connector
);
4428 if (!downclock_mode
) {
4429 DRM_INFO("DRRS not supported\n");
4433 dev_priv
->drrs
.connector
= intel_connector
;
4435 mutex_init(&intel_dp
->drrs_state
.mutex
);
4437 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4439 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4440 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4441 return downclock_mode
;
4444 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4445 struct intel_connector
*intel_connector
,
4446 struct edp_power_seq
*power_seq
)
4448 struct drm_connector
*connector
= &intel_connector
->base
;
4449 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4450 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4451 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4453 struct drm_display_mode
*fixed_mode
= NULL
;
4454 struct drm_display_mode
*downclock_mode
= NULL
;
4456 struct drm_display_mode
*scan
;
4459 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4461 if (!is_edp(intel_dp
))
4464 /* The VDD bit needs a power domain reference, so if the bit is already
4465 * enabled when we boot, grab this reference. */
4466 if (edp_have_panel_vdd(intel_dp
)) {
4467 enum intel_display_power_domain power_domain
;
4468 power_domain
= intel_display_port_power_domain(intel_encoder
);
4469 intel_display_power_get(dev_priv
, power_domain
);
4472 /* Cache DPCD and EDID for edp. */
4473 intel_edp_panel_vdd_on(intel_dp
);
4474 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4475 edp_panel_vdd_off(intel_dp
, false);
4478 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4479 dev_priv
->no_aux_handshake
=
4480 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4481 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4483 /* if this fails, presume the device is a ghost */
4484 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4488 /* We now know it's not a ghost, init power sequence regs. */
4489 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4491 mutex_lock(&dev
->mode_config
.mutex
);
4492 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4494 if (drm_add_edid_modes(connector
, edid
)) {
4495 drm_mode_connector_update_edid_property(connector
,
4497 drm_edid_to_eld(connector
, edid
);
4500 edid
= ERR_PTR(-EINVAL
);
4503 edid
= ERR_PTR(-ENOENT
);
4505 intel_connector
->edid
= edid
;
4507 /* prefer fixed mode from EDID if available */
4508 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4509 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4510 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4511 downclock_mode
= intel_dp_drrs_init(
4513 intel_connector
, fixed_mode
);
4518 /* fallback to VBT if available for eDP */
4519 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4520 fixed_mode
= drm_mode_duplicate(dev
,
4521 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4523 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4525 mutex_unlock(&dev
->mode_config
.mutex
);
4527 if (IS_VALLEYVIEW(dev
)) {
4528 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4529 register_reboot_notifier(&intel_dp
->edp_notifier
);
4532 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4533 intel_panel_setup_backlight(connector
);
4539 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4540 struct intel_connector
*intel_connector
)
4542 struct drm_connector
*connector
= &intel_connector
->base
;
4543 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4544 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4545 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4547 enum port port
= intel_dig_port
->port
;
4548 struct edp_power_seq power_seq
= { 0 };
4551 /* intel_dp vfuncs */
4552 if (IS_VALLEYVIEW(dev
))
4553 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4554 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4555 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4556 else if (HAS_PCH_SPLIT(dev
))
4557 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4559 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4561 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4563 /* Preserve the current hw state. */
4564 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4565 intel_dp
->attached_connector
= intel_connector
;
4567 if (intel_dp_is_edp(dev
, port
))
4568 type
= DRM_MODE_CONNECTOR_eDP
;
4570 type
= DRM_MODE_CONNECTOR_DisplayPort
;
4573 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4574 * for DP the encoder type can be set by the caller to
4575 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4577 if (type
== DRM_MODE_CONNECTOR_eDP
)
4578 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
4580 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4581 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
4584 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
4585 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
4587 connector
->interlace_allowed
= true;
4588 connector
->doublescan_allowed
= 0;
4590 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
4591 edp_panel_vdd_work
);
4593 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
4594 drm_connector_register(connector
);
4597 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
4599 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
4600 intel_connector
->unregister
= intel_dp_connector_unregister
;
4602 /* Set up the hotplug pin. */
4605 intel_encoder
->hpd_pin
= HPD_PORT_A
;
4608 intel_encoder
->hpd_pin
= HPD_PORT_B
;
4611 intel_encoder
->hpd_pin
= HPD_PORT_C
;
4614 intel_encoder
->hpd_pin
= HPD_PORT_D
;
4620 if (is_edp(intel_dp
)) {
4621 intel_dp_init_panel_power_timestamps(intel_dp
);
4622 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
4625 intel_dp_aux_init(intel_dp
, intel_connector
);
4627 /* init MST on ports that can support it */
4628 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4629 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
4630 intel_dp_mst_encoder_init(intel_dig_port
, intel_connector
->base
.base
.id
);
4634 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
4635 drm_dp_aux_unregister(&intel_dp
->aux
);
4636 if (is_edp(intel_dp
)) {
4637 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4638 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4639 edp_panel_vdd_off_sync(intel_dp
);
4640 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4642 drm_connector_unregister(connector
);
4643 drm_connector_cleanup(connector
);
4647 intel_dp_add_properties(intel_dp
, connector
);
4649 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4650 * 0xd. Failure to do so will result in spurious interrupts being
4651 * generated on the port when a cable is not attached.
4653 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
4654 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
4655 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
4662 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
4664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4665 struct intel_digital_port
*intel_dig_port
;
4666 struct intel_encoder
*intel_encoder
;
4667 struct drm_encoder
*encoder
;
4668 struct intel_connector
*intel_connector
;
4670 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
4671 if (!intel_dig_port
)
4674 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
4675 if (!intel_connector
) {
4676 kfree(intel_dig_port
);
4680 intel_encoder
= &intel_dig_port
->base
;
4681 encoder
= &intel_encoder
->base
;
4683 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4684 DRM_MODE_ENCODER_TMDS
);
4686 intel_encoder
->compute_config
= intel_dp_compute_config
;
4687 intel_encoder
->disable
= intel_disable_dp
;
4688 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4689 intel_encoder
->get_config
= intel_dp_get_config
;
4690 if (IS_CHERRYVIEW(dev
)) {
4691 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
4692 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
4693 intel_encoder
->enable
= vlv_enable_dp
;
4694 intel_encoder
->post_disable
= chv_post_disable_dp
;
4695 } else if (IS_VALLEYVIEW(dev
)) {
4696 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4697 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4698 intel_encoder
->enable
= vlv_enable_dp
;
4699 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4701 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4702 intel_encoder
->enable
= g4x_enable_dp
;
4703 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4706 intel_dig_port
->port
= port
;
4707 intel_dig_port
->dp
.output_reg
= output_reg
;
4709 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4710 if (IS_CHERRYVIEW(dev
)) {
4712 intel_encoder
->crtc_mask
= 1 << 2;
4714 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
4716 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4718 intel_encoder
->cloneable
= 0;
4719 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4721 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
4722 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
4724 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4725 drm_encoder_cleanup(encoder
);
4726 kfree(intel_dig_port
);
4727 kfree(intel_connector
);
4731 void intel_dp_mst_suspend(struct drm_device
*dev
)
4733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4737 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4738 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4739 if (!intel_dig_port
)
4742 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4743 if (!intel_dig_port
->dp
.can_mst
)
4745 if (intel_dig_port
->dp
.is_mst
)
4746 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
4751 void intel_dp_mst_resume(struct drm_device
*dev
)
4753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4756 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4757 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4758 if (!intel_dig_port
)
4760 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4763 if (!intel_dig_port
->dp
.can_mst
)
4766 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
4768 intel_dp_check_mst_status(&intel_dig_port
->dp
);