2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 /* Compliance test status bits */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
48 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
57 static const struct dp_link_dpll gen4_dpll
[] = {
59 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
61 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
64 static const struct dp_link_dpll pch_dpll
[] = {
66 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
68 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
71 static const struct dp_link_dpll vlv_dpll
[] = {
73 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
75 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
79 * CHV supports eDP 1.4 that have more link rates.
80 * Below only provides the fixed rate but exclude variable rate.
82 static const struct dp_link_dpll chv_dpll
[] = {
84 * CHV requires to program fractional division for m2.
85 * m2 is stored in fixed point format using formula below
86 * (m2_int << 22) | m2_fraction
88 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
89 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
90 { 270000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
92 { 540000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
96 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
97 324000, 432000, 540000 };
98 static const int skl_rates
[] = { 162000, 216000, 270000,
99 324000, 432000, 540000 };
100 static const int cnl_rates
[] = { 162000, 216000, 270000,
101 324000, 432000, 540000,
103 static const int default_rates
[] = { 162000, 270000, 540000 };
106 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
107 * @intel_dp: DP struct
109 * If a CPU or PCH DP output is attached to an eDP panel, this function
110 * will return true, and false otherwise.
112 static bool is_edp(struct intel_dp
*intel_dp
)
114 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
116 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
119 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
121 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
123 return intel_dig_port
->base
.base
.dev
;
126 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
128 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
131 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
132 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
133 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
134 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
135 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
137 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
139 static int intel_dp_num_rates(u8 link_bw_code
)
141 switch (link_bw_code
) {
143 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
145 case DP_LINK_BW_1_62
:
154 /* update sink rates from dpcd */
155 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
159 num_rates
= intel_dp_num_rates(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
161 for (i
= 0; i
< num_rates
; i
++)
162 intel_dp
->sink_rates
[i
] = default_rates
[i
];
164 intel_dp
->num_sink_rates
= num_rates
;
167 /* Theoretical max between source and sink */
168 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
170 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
173 /* Theoretical max between source and sink */
174 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
176 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
177 int source_max
= intel_dig_port
->max_lanes
;
178 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
180 return min(source_max
, sink_max
);
183 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
185 return intel_dp
->max_link_lane_count
;
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
192 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
196 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
198 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
199 * link rate that is generally expressed in Gbps. Since, 8 bits of data
200 * is transmitted every LS_Clk per lane, there is no need to account for
201 * the channel encoding that is done in the PHY layer here.
204 return max_link_clock
* max_lanes
;
208 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
210 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
211 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
212 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
213 int max_dotclk
= dev_priv
->max_dotclk_freq
;
216 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
218 if (type
!= DP_DS_PORT_TYPE_VGA
)
221 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
222 intel_dp
->downstream_ports
);
224 if (ds_max_dotclk
!= 0)
225 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
231 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
233 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
234 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
235 enum port port
= dig_port
->port
;
236 const int *source_rates
;
240 /* This should only be done once */
241 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
243 if (IS_GEN9_LP(dev_priv
)) {
244 source_rates
= bxt_rates
;
245 size
= ARRAY_SIZE(bxt_rates
);
246 } else if (IS_CANNONLAKE(dev_priv
)) {
247 source_rates
= cnl_rates
;
248 size
= ARRAY_SIZE(cnl_rates
);
249 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
250 if (port
== PORT_A
|| port
== PORT_D
||
251 voltage
== VOLTAGE_INFO_0_85V
)
253 } else if (IS_GEN9_BC(dev_priv
)) {
254 source_rates
= skl_rates
;
255 size
= ARRAY_SIZE(skl_rates
);
257 source_rates
= default_rates
;
258 size
= ARRAY_SIZE(default_rates
);
261 /* This depends on the fact that 5.4 is last value in the array */
262 if (!intel_dp_source_supports_hbr2(intel_dp
))
265 intel_dp
->source_rates
= source_rates
;
266 intel_dp
->num_source_rates
= size
;
269 static int intersect_rates(const int *source_rates
, int source_len
,
270 const int *sink_rates
, int sink_len
,
273 int i
= 0, j
= 0, k
= 0;
275 while (i
< source_len
&& j
< sink_len
) {
276 if (source_rates
[i
] == sink_rates
[j
]) {
277 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
279 common_rates
[k
] = source_rates
[i
];
283 } else if (source_rates
[i
] < sink_rates
[j
]) {
292 /* return index of rate in rates array, or -1 if not found */
293 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
297 for (i
= 0; i
< len
; i
++)
298 if (rate
== rates
[i
])
304 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
306 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
308 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
309 intel_dp
->num_source_rates
,
310 intel_dp
->sink_rates
,
311 intel_dp
->num_sink_rates
,
312 intel_dp
->common_rates
);
314 /* Paranoia, there should always be something in common. */
315 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
316 intel_dp
->common_rates
[0] = default_rates
[0];
317 intel_dp
->num_common_rates
= 1;
321 /* get length of common rates potentially limited by max_rate */
322 static int intel_dp_common_len_rate_limit(struct intel_dp
*intel_dp
,
325 const int *common_rates
= intel_dp
->common_rates
;
326 int i
, common_len
= intel_dp
->num_common_rates
;
328 /* Limit results by potentially reduced max rate */
329 for (i
= 0; i
< common_len
; i
++) {
330 if (common_rates
[common_len
- i
- 1] <= max_rate
)
331 return common_len
- i
;
337 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
)
340 * FIXME: we need to synchronize the current link parameters with
341 * hardware readout. Currently fast link training doesn't work on
344 if (intel_dp
->link_rate
== 0 ||
345 intel_dp
->link_rate
> intel_dp
->max_link_rate
)
348 if (intel_dp
->lane_count
== 0 ||
349 intel_dp
->lane_count
> intel_dp_max_lane_count(intel_dp
))
355 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
356 int link_rate
, uint8_t lane_count
)
360 index
= intel_dp_rate_index(intel_dp
->common_rates
,
361 intel_dp
->num_common_rates
,
364 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
365 intel_dp
->max_link_lane_count
= lane_count
;
366 } else if (lane_count
> 1) {
367 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
368 intel_dp
->max_link_lane_count
= lane_count
>> 1;
370 DRM_ERROR("Link Training Unsuccessful\n");
377 static enum drm_mode_status
378 intel_dp_mode_valid(struct drm_connector
*connector
,
379 struct drm_display_mode
*mode
)
381 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
382 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
383 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
384 int target_clock
= mode
->clock
;
385 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
388 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
390 if (is_edp(intel_dp
) && fixed_mode
) {
391 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
394 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
397 target_clock
= fixed_mode
->clock
;
400 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
401 max_lanes
= intel_dp_max_lane_count(intel_dp
);
403 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
404 mode_rate
= intel_dp_link_required(target_clock
, 18);
406 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
407 return MODE_CLOCK_HIGH
;
409 if (mode
->clock
< 10000)
410 return MODE_CLOCK_LOW
;
412 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
413 return MODE_H_ILLEGAL
;
418 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
425 for (i
= 0; i
< src_bytes
; i
++)
426 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
430 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
435 for (i
= 0; i
< dst_bytes
; i
++)
436 dst
[i
] = src
>> ((3-i
) * 8);
440 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
441 struct intel_dp
*intel_dp
);
443 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
444 struct intel_dp
*intel_dp
,
445 bool force_disable_vdd
);
447 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
449 static void pps_lock(struct intel_dp
*intel_dp
)
451 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
452 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
453 struct drm_device
*dev
= encoder
->base
.dev
;
454 struct drm_i915_private
*dev_priv
= to_i915(dev
);
457 * See vlv_power_sequencer_reset() why we need
458 * a power domain reference here.
460 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
462 mutex_lock(&dev_priv
->pps_mutex
);
465 static void pps_unlock(struct intel_dp
*intel_dp
)
467 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
468 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
469 struct drm_device
*dev
= encoder
->base
.dev
;
470 struct drm_i915_private
*dev_priv
= to_i915(dev
);
472 mutex_unlock(&dev_priv
->pps_mutex
);
474 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
478 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
480 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
481 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
482 enum pipe pipe
= intel_dp
->pps_pipe
;
483 bool pll_enabled
, release_cl_override
= false;
484 enum dpio_phy phy
= DPIO_PHY(pipe
);
485 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
488 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
489 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
490 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
493 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
494 pipe_name(pipe
), port_name(intel_dig_port
->port
));
496 /* Preserve the BIOS-computed detected bit. This is
497 * supposed to be read-only.
499 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
500 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
501 DP
|= DP_PORT_WIDTH(1);
502 DP
|= DP_LINK_TRAIN_PAT_1
;
504 if (IS_CHERRYVIEW(dev_priv
))
505 DP
|= DP_PIPE_SELECT_CHV(pipe
);
506 else if (pipe
== PIPE_B
)
507 DP
|= DP_PIPEB_SELECT
;
509 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
512 * The DPLL for the pipe must be enabled for this to work.
513 * So enable temporarily it if it's not already enabled.
516 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
517 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
519 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
520 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
521 DRM_ERROR("Failed to force on pll for pipe %c!\n",
528 * Similar magic as in intel_dp_enable_port().
529 * We _must_ do this port enable + disable trick
530 * to make this power seqeuencer lock onto the port.
531 * Otherwise even VDD force bit won't work.
533 I915_WRITE(intel_dp
->output_reg
, DP
);
534 POSTING_READ(intel_dp
->output_reg
);
536 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
537 POSTING_READ(intel_dp
->output_reg
);
539 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
540 POSTING_READ(intel_dp
->output_reg
);
543 vlv_force_pll_off(dev_priv
, pipe
);
545 if (release_cl_override
)
546 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
550 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
552 struct intel_encoder
*encoder
;
553 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
556 * We don't have power sequencer currently.
557 * Pick one that's not used by other ports.
559 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
560 struct intel_dp
*intel_dp
;
562 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
563 encoder
->type
!= INTEL_OUTPUT_EDP
)
566 intel_dp
= enc_to_intel_dp(&encoder
->base
);
568 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
569 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
570 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
572 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
573 pipes
&= ~(1 << intel_dp
->pps_pipe
);
575 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
577 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
578 pipes
&= ~(1 << intel_dp
->active_pipe
);
585 return ffs(pipes
) - 1;
589 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
591 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
592 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
593 struct drm_i915_private
*dev_priv
= to_i915(dev
);
596 lockdep_assert_held(&dev_priv
->pps_mutex
);
598 /* We should never land here with regular DP ports */
599 WARN_ON(!is_edp(intel_dp
));
601 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
602 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
604 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
605 return intel_dp
->pps_pipe
;
607 pipe
= vlv_find_free_pps(dev_priv
);
610 * Didn't find one. This should not happen since there
611 * are two power sequencers and up to two eDP ports.
613 if (WARN_ON(pipe
== INVALID_PIPE
))
616 vlv_steal_power_sequencer(dev
, pipe
);
617 intel_dp
->pps_pipe
= pipe
;
619 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
620 pipe_name(intel_dp
->pps_pipe
),
621 port_name(intel_dig_port
->port
));
623 /* init power sequencer on this pipe and port */
624 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
625 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
628 * Even vdd force doesn't work until we've made
629 * the power sequencer lock in on the port.
631 vlv_power_sequencer_kick(intel_dp
);
633 return intel_dp
->pps_pipe
;
637 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
639 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
640 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
641 struct drm_i915_private
*dev_priv
= to_i915(dev
);
643 lockdep_assert_held(&dev_priv
->pps_mutex
);
645 /* We should never land here with regular DP ports */
646 WARN_ON(!is_edp(intel_dp
));
649 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
650 * mapping needs to be retrieved from VBT, for now just hard-code to
651 * use instance #0 always.
653 if (!intel_dp
->pps_reset
)
656 intel_dp
->pps_reset
= false;
659 * Only the HW needs to be reprogrammed, the SW state is fixed and
660 * has been setup during connector init.
662 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
667 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
670 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
673 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
676 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
679 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
682 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
689 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
691 vlv_pipe_check pipe_check
)
695 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
696 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
697 PANEL_PORT_SELECT_MASK
;
699 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
702 if (!pipe_check(dev_priv
, pipe
))
712 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
714 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
715 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
716 struct drm_i915_private
*dev_priv
= to_i915(dev
);
717 enum port port
= intel_dig_port
->port
;
719 lockdep_assert_held(&dev_priv
->pps_mutex
);
721 /* try to find a pipe with this port selected */
722 /* first pick one where the panel is on */
723 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
725 /* didn't find one? pick one where vdd is on */
726 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
727 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
728 vlv_pipe_has_vdd_on
);
729 /* didn't find one? pick one with just the correct port */
730 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
731 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
734 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
735 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
736 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
741 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
742 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
744 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
745 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
748 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
750 struct drm_device
*dev
= &dev_priv
->drm
;
751 struct intel_encoder
*encoder
;
753 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
754 !IS_GEN9_LP(dev_priv
)))
758 * We can't grab pps_mutex here due to deadlock with power_domain
759 * mutex when power_domain functions are called while holding pps_mutex.
760 * That also means that in order to use pps_pipe the code needs to
761 * hold both a power domain reference and pps_mutex, and the power domain
762 * reference get/put must be done while _not_ holding pps_mutex.
763 * pps_{lock,unlock}() do these steps in the correct order, so one
764 * should use them always.
767 for_each_intel_encoder(dev
, encoder
) {
768 struct intel_dp
*intel_dp
;
770 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
771 encoder
->type
!= INTEL_OUTPUT_EDP
)
774 intel_dp
= enc_to_intel_dp(&encoder
->base
);
776 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
778 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
781 if (IS_GEN9_LP(dev_priv
))
782 intel_dp
->pps_reset
= true;
784 intel_dp
->pps_pipe
= INVALID_PIPE
;
788 struct pps_registers
{
796 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
797 struct intel_dp
*intel_dp
,
798 struct pps_registers
*regs
)
802 memset(regs
, 0, sizeof(*regs
));
804 if (IS_GEN9_LP(dev_priv
))
805 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
806 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
807 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
809 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
810 regs
->pp_stat
= PP_STATUS(pps_idx
);
811 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
812 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
813 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
))
814 regs
->pp_div
= PP_DIVISOR(pps_idx
);
818 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
820 struct pps_registers regs
;
822 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
829 _pp_stat_reg(struct intel_dp
*intel_dp
)
831 struct pps_registers regs
;
833 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
839 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
840 This function only applicable when panel PM state is not to be tracked */
841 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
844 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
846 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
847 struct drm_i915_private
*dev_priv
= to_i915(dev
);
849 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
854 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
855 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
856 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
859 pp_ctrl_reg
= PP_CONTROL(pipe
);
860 pp_div_reg
= PP_DIVISOR(pipe
);
861 pp_div
= I915_READ(pp_div_reg
);
862 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
864 /* 0x1F write to PP_DIV_REG sets max cycle delay */
865 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
866 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
867 msleep(intel_dp
->panel_power_cycle_delay
);
870 pps_unlock(intel_dp
);
875 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
877 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
878 struct drm_i915_private
*dev_priv
= to_i915(dev
);
880 lockdep_assert_held(&dev_priv
->pps_mutex
);
882 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
883 intel_dp
->pps_pipe
== INVALID_PIPE
)
886 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
889 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
891 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
892 struct drm_i915_private
*dev_priv
= to_i915(dev
);
894 lockdep_assert_held(&dev_priv
->pps_mutex
);
896 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
897 intel_dp
->pps_pipe
== INVALID_PIPE
)
900 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
904 intel_dp_check_edp(struct intel_dp
*intel_dp
)
906 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
907 struct drm_i915_private
*dev_priv
= to_i915(dev
);
909 if (!is_edp(intel_dp
))
912 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
913 WARN(1, "eDP powered off while attempting aux channel communication.\n");
914 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
915 I915_READ(_pp_stat_reg(intel_dp
)),
916 I915_READ(_pp_ctrl_reg(intel_dp
)));
921 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
923 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
924 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
925 struct drm_i915_private
*dev_priv
= to_i915(dev
);
926 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
930 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
932 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
933 msecs_to_jiffies_timeout(10));
935 done
= wait_for(C
, 10) == 0;
937 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
944 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
946 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
947 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
953 * The clock divider is based off the hrawclk, and would like to run at
954 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
956 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
959 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
961 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
962 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
968 * The clock divider is based off the cdclk or PCH rawclk, and would
969 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
970 * divide by 2000 and use that
972 if (intel_dig_port
->port
== PORT_A
)
973 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
975 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
978 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
980 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
981 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
983 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
984 /* Workaround for non-ULT HSW */
992 return ilk_get_aux_clock_divider(intel_dp
, index
);
995 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
998 * SKL doesn't need us to program the AUX clock divider (Hardware will
999 * derive the clock from CDCLK automatically). We still implement the
1000 * get_aux_clock_divider vfunc to plug-in into the existing code.
1002 return index
? 0 : 1;
1005 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1008 uint32_t aux_clock_divider
)
1010 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1011 struct drm_i915_private
*dev_priv
=
1012 to_i915(intel_dig_port
->base
.base
.dev
);
1013 uint32_t precharge
, timeout
;
1015 if (IS_GEN6(dev_priv
))
1020 if (IS_BROADWELL(dev_priv
) && intel_dig_port
->port
== PORT_A
)
1021 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1023 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1025 return DP_AUX_CH_CTL_SEND_BUSY
|
1026 DP_AUX_CH_CTL_DONE
|
1027 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1028 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1030 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1031 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1032 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1033 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1036 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1041 return DP_AUX_CH_CTL_SEND_BUSY
|
1042 DP_AUX_CH_CTL_DONE
|
1043 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1044 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1045 DP_AUX_CH_CTL_TIME_OUT_1600us
|
1046 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1047 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1048 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1049 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1053 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
1054 const uint8_t *send
, int send_bytes
,
1055 uint8_t *recv
, int recv_size
)
1057 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1058 struct drm_i915_private
*dev_priv
=
1059 to_i915(intel_dig_port
->base
.base
.dev
);
1060 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
1061 uint32_t aux_clock_divider
;
1062 int i
, ret
, recv_bytes
;
1065 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1071 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1072 * In such cases we want to leave VDD enabled and it's up to upper layers
1073 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1076 vdd
= edp_panel_vdd_on(intel_dp
);
1078 /* dp aux is extremely sensitive to irq latency, hence request the
1079 * lowest possible wakeup latency and so prevent the cpu from going into
1080 * deep sleep states.
1082 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1084 intel_dp_check_edp(intel_dp
);
1086 /* Try to wait for any previous AUX channel activity */
1087 for (try = 0; try < 3; try++) {
1088 status
= I915_READ_NOTRACE(ch_ctl
);
1089 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1095 static u32 last_status
= -1;
1096 const u32 status
= I915_READ(ch_ctl
);
1098 if (status
!= last_status
) {
1099 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1101 last_status
= status
;
1108 /* Only 5 data registers! */
1109 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1114 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1115 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1120 /* Must try at least 3 times according to DP spec */
1121 for (try = 0; try < 5; try++) {
1122 /* Load the send data into the aux channel data registers */
1123 for (i
= 0; i
< send_bytes
; i
+= 4)
1124 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
1125 intel_dp_pack_aux(send
+ i
,
1128 /* Send the command and wait for it to complete */
1129 I915_WRITE(ch_ctl
, send_ctl
);
1131 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1133 /* Clear done status and any errors */
1136 DP_AUX_CH_CTL_DONE
|
1137 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1138 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1140 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1143 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1144 * 400us delay required for errors and timeouts
1145 * Timeout errors from the HW already meet this
1146 * requirement so skip to next iteration
1148 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1149 usleep_range(400, 500);
1152 if (status
& DP_AUX_CH_CTL_DONE
)
1157 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1158 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1164 /* Check for timeout or receive error.
1165 * Timeouts occur when the sink is not connected
1167 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1168 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1173 /* Timeouts occur when the device isn't connected, so they're
1174 * "normal" -- don't fill the kernel log with these */
1175 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1176 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1181 /* Unload any bytes sent back from the other side */
1182 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1183 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1186 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1187 * We have no idea of what happened so we return -EBUSY so
1188 * drm layer takes care for the necessary retries.
1190 if (recv_bytes
== 0 || recv_bytes
> 20) {
1191 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1194 * FIXME: This patch was created on top of a series that
1195 * organize the retries at drm level. There EBUSY should
1196 * also take care for 1ms wait before retrying.
1197 * That aux retries re-org is still needed and after that is
1198 * merged we remove this sleep from here.
1200 usleep_range(1000, 1500);
1205 if (recv_bytes
> recv_size
)
1206 recv_bytes
= recv_size
;
1208 for (i
= 0; i
< recv_bytes
; i
+= 4)
1209 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1210 recv
+ i
, recv_bytes
- i
);
1214 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1217 edp_panel_vdd_off(intel_dp
, false);
1219 pps_unlock(intel_dp
);
1224 #define BARE_ADDRESS_SIZE 3
1225 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1227 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1229 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1230 uint8_t txbuf
[20], rxbuf
[20];
1231 size_t txsize
, rxsize
;
1234 txbuf
[0] = (msg
->request
<< 4) |
1235 ((msg
->address
>> 16) & 0xf);
1236 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1237 txbuf
[2] = msg
->address
& 0xff;
1238 txbuf
[3] = msg
->size
- 1;
1240 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1241 case DP_AUX_NATIVE_WRITE
:
1242 case DP_AUX_I2C_WRITE
:
1243 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1244 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1245 rxsize
= 2; /* 0 or 1 data bytes */
1247 if (WARN_ON(txsize
> 20))
1250 WARN_ON(!msg
->buffer
!= !msg
->size
);
1253 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1255 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1257 msg
->reply
= rxbuf
[0] >> 4;
1260 /* Number of bytes written in a short write. */
1261 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1263 /* Return payload size. */
1269 case DP_AUX_NATIVE_READ
:
1270 case DP_AUX_I2C_READ
:
1271 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1272 rxsize
= msg
->size
+ 1;
1274 if (WARN_ON(rxsize
> 20))
1277 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1279 msg
->reply
= rxbuf
[0] >> 4;
1281 * Assume happy day, and copy the data. The caller is
1282 * expected to check msg->reply before touching it.
1284 * Return payload size.
1287 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1299 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1302 const struct ddi_vbt_port_info
*info
=
1303 &dev_priv
->vbt
.ddi_port_info
[port
];
1306 if (!info
->alternate_aux_channel
) {
1307 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1308 port_name(port
), port_name(port
));
1312 switch (info
->alternate_aux_channel
) {
1326 MISSING_CASE(info
->alternate_aux_channel
);
1331 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1332 port_name(aux_port
), port_name(port
));
1337 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1344 return DP_AUX_CH_CTL(port
);
1347 return DP_AUX_CH_CTL(PORT_B
);
1351 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1352 enum port port
, int index
)
1358 return DP_AUX_CH_DATA(port
, index
);
1361 return DP_AUX_CH_DATA(PORT_B
, index
);
1365 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1370 return DP_AUX_CH_CTL(port
);
1374 return PCH_DP_AUX_CH_CTL(port
);
1377 return DP_AUX_CH_CTL(PORT_A
);
1381 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1382 enum port port
, int index
)
1386 return DP_AUX_CH_DATA(port
, index
);
1390 return PCH_DP_AUX_CH_DATA(port
, index
);
1393 return DP_AUX_CH_DATA(PORT_A
, index
);
1397 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1405 return DP_AUX_CH_CTL(port
);
1408 return DP_AUX_CH_CTL(PORT_A
);
1412 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1413 enum port port
, int index
)
1420 return DP_AUX_CH_DATA(port
, index
);
1423 return DP_AUX_CH_DATA(PORT_A
, index
);
1427 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1430 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1431 return skl_aux_ctl_reg(dev_priv
, port
);
1432 else if (HAS_PCH_SPLIT(dev_priv
))
1433 return ilk_aux_ctl_reg(dev_priv
, port
);
1435 return g4x_aux_ctl_reg(dev_priv
, port
);
1438 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1439 enum port port
, int index
)
1441 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1442 return skl_aux_data_reg(dev_priv
, port
, index
);
1443 else if (HAS_PCH_SPLIT(dev_priv
))
1444 return ilk_aux_data_reg(dev_priv
, port
, index
);
1446 return g4x_aux_data_reg(dev_priv
, port
, index
);
1449 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1451 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1452 enum port port
= intel_aux_port(dev_priv
,
1453 dp_to_dig_port(intel_dp
)->port
);
1456 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1457 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1458 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1462 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1464 kfree(intel_dp
->aux
.name
);
1468 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1470 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1471 enum port port
= intel_dig_port
->port
;
1473 intel_aux_reg_init(intel_dp
);
1474 drm_dp_aux_init(&intel_dp
->aux
);
1476 /* Failure to allocate our preferred name is not critical */
1477 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1478 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1481 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1483 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1484 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1486 if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
1487 IS_BROADWELL(dev_priv
) || (INTEL_GEN(dev_priv
) >= 9))
1494 intel_dp_set_clock(struct intel_encoder
*encoder
,
1495 struct intel_crtc_state
*pipe_config
)
1497 struct drm_device
*dev
= encoder
->base
.dev
;
1498 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1499 const struct dp_link_dpll
*divisor
= NULL
;
1502 if (IS_G4X(dev_priv
)) {
1503 divisor
= gen4_dpll
;
1504 count
= ARRAY_SIZE(gen4_dpll
);
1505 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1507 count
= ARRAY_SIZE(pch_dpll
);
1508 } else if (IS_CHERRYVIEW(dev_priv
)) {
1510 count
= ARRAY_SIZE(chv_dpll
);
1511 } else if (IS_VALLEYVIEW(dev_priv
)) {
1513 count
= ARRAY_SIZE(vlv_dpll
);
1516 if (divisor
&& count
) {
1517 for (i
= 0; i
< count
; i
++) {
1518 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1519 pipe_config
->dpll
= divisor
[i
].dpll
;
1520 pipe_config
->clock_set
= true;
1527 static void snprintf_int_array(char *str
, size_t len
,
1528 const int *array
, int nelem
)
1534 for (i
= 0; i
< nelem
; i
++) {
1535 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1543 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1545 char str
[128]; /* FIXME: too big for stack? */
1547 if ((drm_debug
& DRM_UT_KMS
) == 0)
1550 snprintf_int_array(str
, sizeof(str
),
1551 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1552 DRM_DEBUG_KMS("source rates: %s\n", str
);
1554 snprintf_int_array(str
, sizeof(str
),
1555 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1556 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1558 snprintf_int_array(str
, sizeof(str
),
1559 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1560 DRM_DEBUG_KMS("common rates: %s\n", str
);
1564 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1568 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1569 if (WARN_ON(len
<= 0))
1572 return intel_dp
->common_rates
[len
- 1];
1575 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1577 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1578 intel_dp
->num_sink_rates
, rate
);
1586 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1587 uint8_t *link_bw
, uint8_t *rate_select
)
1589 /* eDP 1.4 rate select method. */
1590 if (intel_dp
->use_rate_select
) {
1593 intel_dp_rate_select(intel_dp
, port_clock
);
1595 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1600 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1601 struct intel_crtc_state
*pipe_config
)
1605 bpp
= pipe_config
->pipe_bpp
;
1606 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1609 bpp
= min(bpp
, 3*bpc
);
1611 /* For DP Compliance we override the computed bpp for the pipe */
1612 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1613 pipe_config
->pipe_bpp
= 3*intel_dp
->compliance
.test_data
.bpc
;
1614 pipe_config
->dither_force_disable
= pipe_config
->pipe_bpp
== 6*3;
1615 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1616 pipe_config
->pipe_bpp
);
1622 intel_dp_compute_config(struct intel_encoder
*encoder
,
1623 struct intel_crtc_state
*pipe_config
,
1624 struct drm_connector_state
*conn_state
)
1626 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1627 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1628 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1629 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1630 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1631 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1632 struct intel_digital_connector_state
*intel_conn_state
=
1633 to_intel_digital_connector_state(conn_state
);
1634 int lane_count
, clock
;
1635 int min_lane_count
= 1;
1636 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1637 /* Conveniently, the link BW constants become indices with a shift...*/
1641 int link_avail
, link_clock
;
1643 uint8_t link_bw
, rate_select
;
1644 bool reduce_m_n
= drm_dp_has_quirk(&intel_dp
->desc
,
1645 DP_DPCD_QUIRK_LIMITED_M_N
);
1647 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1648 intel_dp
->max_link_rate
);
1650 /* No common link rates between source and sink */
1651 WARN_ON(common_len
<= 0);
1653 max_clock
= common_len
- 1;
1655 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1656 pipe_config
->has_pch_encoder
= true;
1658 pipe_config
->has_drrs
= false;
1660 pipe_config
->has_audio
= false;
1661 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1662 pipe_config
->has_audio
= intel_dp
->has_audio
;
1664 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1666 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1667 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1670 if (INTEL_GEN(dev_priv
) >= 9) {
1672 ret
= skl_update_scaler_crtc(pipe_config
);
1677 if (HAS_GMCH_DISPLAY(dev_priv
))
1678 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1679 conn_state
->scaling_mode
);
1681 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1682 conn_state
->scaling_mode
);
1685 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1688 /* Use values requested by Compliance Test Request */
1689 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1692 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1693 intel_dp
->num_common_rates
,
1694 intel_dp
->compliance
.test_link_rate
);
1696 min_clock
= max_clock
= index
;
1697 min_lane_count
= max_lane_count
= intel_dp
->compliance
.test_lane_count
;
1699 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1700 "max bw %d pixel clock %iKHz\n",
1701 max_lane_count
, intel_dp
->common_rates
[max_clock
],
1702 adjusted_mode
->crtc_clock
);
1704 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1705 * bpc in between. */
1706 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1707 if (is_edp(intel_dp
)) {
1709 /* Get bpp from vbt only for panels that dont have bpp in edid */
1710 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1711 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1712 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1713 dev_priv
->vbt
.edp
.bpp
);
1714 bpp
= dev_priv
->vbt
.edp
.bpp
;
1718 * Use the maximum clock and number of lanes the eDP panel
1719 * advertizes being capable of. The panels are generally
1720 * designed to support only a single clock and lane
1721 * configuration, and typically these values correspond to the
1722 * native resolution of the panel.
1724 min_lane_count
= max_lane_count
;
1725 min_clock
= max_clock
;
1728 for (; bpp
>= 6*3; bpp
-= 2*3) {
1729 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1732 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1733 for (lane_count
= min_lane_count
;
1734 lane_count
<= max_lane_count
;
1737 link_clock
= intel_dp
->common_rates
[clock
];
1738 link_avail
= intel_dp_max_data_rate(link_clock
,
1741 if (mode_rate
<= link_avail
) {
1751 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1754 * CEA-861-E - 5.1 Default Encoding Parameters
1755 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1757 pipe_config
->limited_color_range
=
1759 drm_default_rgb_quant_range(adjusted_mode
) ==
1760 HDMI_QUANTIZATION_RANGE_LIMITED
;
1762 pipe_config
->limited_color_range
=
1763 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1766 pipe_config
->lane_count
= lane_count
;
1768 pipe_config
->pipe_bpp
= bpp
;
1769 pipe_config
->port_clock
= intel_dp
->common_rates
[clock
];
1771 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1772 &link_bw
, &rate_select
);
1774 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1775 link_bw
, rate_select
, pipe_config
->lane_count
,
1776 pipe_config
->port_clock
, bpp
);
1777 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1778 mode_rate
, link_avail
);
1780 intel_link_compute_m_n(bpp
, lane_count
,
1781 adjusted_mode
->crtc_clock
,
1782 pipe_config
->port_clock
,
1783 &pipe_config
->dp_m_n
,
1786 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1787 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1788 pipe_config
->has_drrs
= true;
1789 intel_link_compute_m_n(bpp
, lane_count
,
1790 intel_connector
->panel
.downclock_mode
->clock
,
1791 pipe_config
->port_clock
,
1792 &pipe_config
->dp_m2_n2
,
1797 * DPLL0 VCO may need to be adjusted to get the correct
1798 * clock for eDP. This will affect cdclk as well.
1800 if (is_edp(intel_dp
) && IS_GEN9_BC(dev_priv
)) {
1803 switch (pipe_config
->port_clock
/ 2) {
1813 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk
.logical
.vco
= vco
;
1816 if (!HAS_DDI(dev_priv
))
1817 intel_dp_set_clock(encoder
, pipe_config
);
1822 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1823 int link_rate
, uint8_t lane_count
,
1826 intel_dp
->link_rate
= link_rate
;
1827 intel_dp
->lane_count
= lane_count
;
1828 intel_dp
->link_mst
= link_mst
;
1831 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1832 struct intel_crtc_state
*pipe_config
)
1834 struct drm_device
*dev
= encoder
->base
.dev
;
1835 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1836 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1837 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1838 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1839 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1841 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1842 pipe_config
->lane_count
,
1843 intel_crtc_has_type(pipe_config
,
1844 INTEL_OUTPUT_DP_MST
));
1847 * There are four kinds of DP registers:
1854 * IBX PCH and CPU are the same for almost everything,
1855 * except that the CPU DP PLL is configured in this
1858 * CPT PCH is quite different, having many bits moved
1859 * to the TRANS_DP_CTL register instead. That
1860 * configuration happens (oddly) in ironlake_pch_enable
1863 /* Preserve the BIOS-computed detected bit. This is
1864 * supposed to be read-only.
1866 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1868 /* Handle DP bits in common between all three register formats */
1869 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1870 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1872 /* Split out the IBX/CPU vs CPT settings */
1874 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1875 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1876 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1877 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1878 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1879 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1881 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1882 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1884 intel_dp
->DP
|= crtc
->pipe
<< 29;
1885 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1888 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1890 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1891 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1892 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1894 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1895 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1897 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
1898 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1900 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1901 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1902 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1903 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1904 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1906 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1907 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1909 if (IS_CHERRYVIEW(dev_priv
))
1910 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1911 else if (crtc
->pipe
== PIPE_B
)
1912 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1916 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1917 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1919 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1920 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1922 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1923 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1925 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1926 struct intel_dp
*intel_dp
);
1928 static void wait_panel_status(struct intel_dp
*intel_dp
,
1932 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1933 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1934 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1936 lockdep_assert_held(&dev_priv
->pps_mutex
);
1938 intel_pps_verify_state(dev_priv
, intel_dp
);
1940 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1941 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1943 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1945 I915_READ(pp_stat_reg
),
1946 I915_READ(pp_ctrl_reg
));
1948 if (intel_wait_for_register(dev_priv
,
1949 pp_stat_reg
, mask
, value
,
1951 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1952 I915_READ(pp_stat_reg
),
1953 I915_READ(pp_ctrl_reg
));
1955 DRM_DEBUG_KMS("Wait complete\n");
1958 static void wait_panel_on(struct intel_dp
*intel_dp
)
1960 DRM_DEBUG_KMS("Wait for panel power on\n");
1961 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1964 static void wait_panel_off(struct intel_dp
*intel_dp
)
1966 DRM_DEBUG_KMS("Wait for panel power off time\n");
1967 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1970 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1972 ktime_t panel_power_on_time
;
1973 s64 panel_power_off_duration
;
1975 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1977 /* take the difference of currrent time and panel power off time
1978 * and then make panel wait for t11_t12 if needed. */
1979 panel_power_on_time
= ktime_get_boottime();
1980 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1982 /* When we disable the VDD override bit last we have to do the manual
1984 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1985 wait_remaining_ms_from_jiffies(jiffies
,
1986 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1988 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1991 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1993 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1994 intel_dp
->backlight_on_delay
);
1997 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1999 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2000 intel_dp
->backlight_off_delay
);
2003 /* Read the current pp_control value, unlocking the register if it
2007 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2009 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2010 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2013 lockdep_assert_held(&dev_priv
->pps_mutex
);
2015 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2016 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2017 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2018 control
&= ~PANEL_UNLOCK_MASK
;
2019 control
|= PANEL_UNLOCK_REGS
;
2025 * Must be paired with edp_panel_vdd_off().
2026 * Must hold pps_mutex around the whole on/off sequence.
2027 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2029 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2031 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2032 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2033 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2035 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2036 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2038 lockdep_assert_held(&dev_priv
->pps_mutex
);
2040 if (!is_edp(intel_dp
))
2043 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2044 intel_dp
->want_panel_vdd
= true;
2046 if (edp_have_panel_vdd(intel_dp
))
2047 return need_to_disable
;
2049 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2051 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2052 port_name(intel_dig_port
->port
));
2054 if (!edp_have_panel_power(intel_dp
))
2055 wait_panel_power_cycle(intel_dp
);
2057 pp
= ironlake_get_pp_control(intel_dp
);
2058 pp
|= EDP_FORCE_VDD
;
2060 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2061 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2063 I915_WRITE(pp_ctrl_reg
, pp
);
2064 POSTING_READ(pp_ctrl_reg
);
2065 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2066 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2068 * If the panel wasn't on, delay before accessing aux channel
2070 if (!edp_have_panel_power(intel_dp
)) {
2071 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2072 port_name(intel_dig_port
->port
));
2073 msleep(intel_dp
->panel_power_up_delay
);
2076 return need_to_disable
;
2080 * Must be paired with intel_edp_panel_vdd_off() or
2081 * intel_edp_panel_off().
2082 * Nested calls to these functions are not allowed since
2083 * we drop the lock. Caller must use some higher level
2084 * locking to prevent nested calls from other threads.
2086 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2090 if (!is_edp(intel_dp
))
2094 vdd
= edp_panel_vdd_on(intel_dp
);
2095 pps_unlock(intel_dp
);
2097 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2098 port_name(dp_to_dig_port(intel_dp
)->port
));
2101 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2103 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2104 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2105 struct intel_digital_port
*intel_dig_port
=
2106 dp_to_dig_port(intel_dp
);
2108 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2110 lockdep_assert_held(&dev_priv
->pps_mutex
);
2112 WARN_ON(intel_dp
->want_panel_vdd
);
2114 if (!edp_have_panel_vdd(intel_dp
))
2117 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2118 port_name(intel_dig_port
->port
));
2120 pp
= ironlake_get_pp_control(intel_dp
);
2121 pp
&= ~EDP_FORCE_VDD
;
2123 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2124 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2126 I915_WRITE(pp_ctrl_reg
, pp
);
2127 POSTING_READ(pp_ctrl_reg
);
2129 /* Make sure sequencer is idle before allowing subsequent activity */
2130 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2131 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2133 if ((pp
& PANEL_POWER_ON
) == 0)
2134 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2136 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2139 static void edp_panel_vdd_work(struct work_struct
*__work
)
2141 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2142 struct intel_dp
, panel_vdd_work
);
2145 if (!intel_dp
->want_panel_vdd
)
2146 edp_panel_vdd_off_sync(intel_dp
);
2147 pps_unlock(intel_dp
);
2150 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2152 unsigned long delay
;
2155 * Queue the timer to fire a long time from now (relative to the power
2156 * down delay) to keep the panel power up across a sequence of
2159 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2160 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2164 * Must be paired with edp_panel_vdd_on().
2165 * Must hold pps_mutex around the whole on/off sequence.
2166 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2168 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2170 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2172 lockdep_assert_held(&dev_priv
->pps_mutex
);
2174 if (!is_edp(intel_dp
))
2177 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2178 port_name(dp_to_dig_port(intel_dp
)->port
));
2180 intel_dp
->want_panel_vdd
= false;
2183 edp_panel_vdd_off_sync(intel_dp
);
2185 edp_panel_vdd_schedule_off(intel_dp
);
2188 static void edp_panel_on(struct intel_dp
*intel_dp
)
2190 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2191 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2193 i915_reg_t pp_ctrl_reg
;
2195 lockdep_assert_held(&dev_priv
->pps_mutex
);
2197 if (!is_edp(intel_dp
))
2200 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2201 port_name(dp_to_dig_port(intel_dp
)->port
));
2203 if (WARN(edp_have_panel_power(intel_dp
),
2204 "eDP port %c panel power already on\n",
2205 port_name(dp_to_dig_port(intel_dp
)->port
)))
2208 wait_panel_power_cycle(intel_dp
);
2210 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2211 pp
= ironlake_get_pp_control(intel_dp
);
2212 if (IS_GEN5(dev_priv
)) {
2213 /* ILK workaround: disable reset around power sequence */
2214 pp
&= ~PANEL_POWER_RESET
;
2215 I915_WRITE(pp_ctrl_reg
, pp
);
2216 POSTING_READ(pp_ctrl_reg
);
2219 pp
|= PANEL_POWER_ON
;
2220 if (!IS_GEN5(dev_priv
))
2221 pp
|= PANEL_POWER_RESET
;
2223 I915_WRITE(pp_ctrl_reg
, pp
);
2224 POSTING_READ(pp_ctrl_reg
);
2226 wait_panel_on(intel_dp
);
2227 intel_dp
->last_power_on
= jiffies
;
2229 if (IS_GEN5(dev_priv
)) {
2230 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2231 I915_WRITE(pp_ctrl_reg
, pp
);
2232 POSTING_READ(pp_ctrl_reg
);
2236 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2238 if (!is_edp(intel_dp
))
2242 edp_panel_on(intel_dp
);
2243 pps_unlock(intel_dp
);
2247 static void edp_panel_off(struct intel_dp
*intel_dp
)
2249 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2250 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2252 i915_reg_t pp_ctrl_reg
;
2254 lockdep_assert_held(&dev_priv
->pps_mutex
);
2256 if (!is_edp(intel_dp
))
2259 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2260 port_name(dp_to_dig_port(intel_dp
)->port
));
2262 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2263 port_name(dp_to_dig_port(intel_dp
)->port
));
2265 pp
= ironlake_get_pp_control(intel_dp
);
2266 /* We need to switch off panel power _and_ force vdd, for otherwise some
2267 * panels get very unhappy and cease to work. */
2268 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2271 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2273 intel_dp
->want_panel_vdd
= false;
2275 I915_WRITE(pp_ctrl_reg
, pp
);
2276 POSTING_READ(pp_ctrl_reg
);
2278 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2279 wait_panel_off(intel_dp
);
2281 /* We got a reference when we enabled the VDD. */
2282 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2285 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2287 if (!is_edp(intel_dp
))
2291 edp_panel_off(intel_dp
);
2292 pps_unlock(intel_dp
);
2295 /* Enable backlight in the panel power control. */
2296 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2298 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2299 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2300 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2302 i915_reg_t pp_ctrl_reg
;
2305 * If we enable the backlight right away following a panel power
2306 * on, we may see slight flicker as the panel syncs with the eDP
2307 * link. So delay a bit to make sure the image is solid before
2308 * allowing it to appear.
2310 wait_backlight_on(intel_dp
);
2314 pp
= ironlake_get_pp_control(intel_dp
);
2315 pp
|= EDP_BLC_ENABLE
;
2317 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2319 I915_WRITE(pp_ctrl_reg
, pp
);
2320 POSTING_READ(pp_ctrl_reg
);
2322 pps_unlock(intel_dp
);
2325 /* Enable backlight PWM and backlight PP control. */
2326 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2327 const struct drm_connector_state
*conn_state
)
2329 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2331 if (!is_edp(intel_dp
))
2334 DRM_DEBUG_KMS("\n");
2336 intel_panel_enable_backlight(crtc_state
, conn_state
);
2337 _intel_edp_backlight_on(intel_dp
);
2340 /* Disable backlight in the panel power control. */
2341 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2343 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2344 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2346 i915_reg_t pp_ctrl_reg
;
2348 if (!is_edp(intel_dp
))
2353 pp
= ironlake_get_pp_control(intel_dp
);
2354 pp
&= ~EDP_BLC_ENABLE
;
2356 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2358 I915_WRITE(pp_ctrl_reg
, pp
);
2359 POSTING_READ(pp_ctrl_reg
);
2361 pps_unlock(intel_dp
);
2363 intel_dp
->last_backlight_off
= jiffies
;
2364 edp_wait_backlight_off(intel_dp
);
2367 /* Disable backlight PP control and backlight PWM. */
2368 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2370 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2372 if (!is_edp(intel_dp
))
2375 DRM_DEBUG_KMS("\n");
2377 _intel_edp_backlight_off(intel_dp
);
2378 intel_panel_disable_backlight(old_conn_state
);
2382 * Hook for controlling the panel power control backlight through the bl_power
2383 * sysfs attribute. Take care to handle multiple calls.
2385 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2388 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2392 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2393 pps_unlock(intel_dp
);
2395 if (is_enabled
== enable
)
2398 DRM_DEBUG_KMS("panel power control backlight %s\n",
2399 enable
? "enable" : "disable");
2402 _intel_edp_backlight_on(intel_dp
);
2404 _intel_edp_backlight_off(intel_dp
);
2407 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2409 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2410 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2411 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2413 I915_STATE_WARN(cur_state
!= state
,
2414 "DP port %c state assertion failure (expected %s, current %s)\n",
2415 port_name(dig_port
->port
),
2416 onoff(state
), onoff(cur_state
));
2418 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2420 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2422 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2424 I915_STATE_WARN(cur_state
!= state
,
2425 "eDP PLL state assertion failure (expected %s, current %s)\n",
2426 onoff(state
), onoff(cur_state
));
2428 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2429 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2431 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2432 struct intel_crtc_state
*pipe_config
)
2434 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2435 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2437 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2438 assert_dp_port_disabled(intel_dp
);
2439 assert_edp_pll_disabled(dev_priv
);
2441 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2442 pipe_config
->port_clock
);
2444 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2446 if (pipe_config
->port_clock
== 162000)
2447 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2449 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2451 I915_WRITE(DP_A
, intel_dp
->DP
);
2456 * [DevILK] Work around required when enabling DP PLL
2457 * while a pipe is enabled going to FDI:
2458 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2459 * 2. Program DP PLL enable
2461 if (IS_GEN5(dev_priv
))
2462 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2464 intel_dp
->DP
|= DP_PLL_ENABLE
;
2466 I915_WRITE(DP_A
, intel_dp
->DP
);
2471 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2473 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2474 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2475 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2477 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2478 assert_dp_port_disabled(intel_dp
);
2479 assert_edp_pll_enabled(dev_priv
);
2481 DRM_DEBUG_KMS("disabling eDP PLL\n");
2483 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2485 I915_WRITE(DP_A
, intel_dp
->DP
);
2490 /* If the sink supports it, try to set the power state appropriately */
2491 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2495 /* Should have a valid DPCD by this point */
2496 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2499 if (mode
!= DRM_MODE_DPMS_ON
) {
2500 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2503 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2506 * When turning on, we need to retry for 1ms to give the sink
2509 for (i
= 0; i
< 3; i
++) {
2510 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2517 if (ret
== 1 && lspcon
->active
)
2518 lspcon_wait_pcon_mode(lspcon
);
2522 DRM_DEBUG_KMS("failed to %s sink power state\n",
2523 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2526 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2529 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2530 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2531 struct drm_device
*dev
= encoder
->base
.dev
;
2532 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2536 if (!intel_display_power_get_if_enabled(dev_priv
,
2537 encoder
->power_domain
))
2542 tmp
= I915_READ(intel_dp
->output_reg
);
2544 if (!(tmp
& DP_PORT_EN
))
2547 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2548 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2549 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2552 for_each_pipe(dev_priv
, p
) {
2553 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2554 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2562 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2563 i915_mmio_reg_offset(intel_dp
->output_reg
));
2564 } else if (IS_CHERRYVIEW(dev_priv
)) {
2565 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2567 *pipe
= PORT_TO_PIPE(tmp
);
2573 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2578 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2579 struct intel_crtc_state
*pipe_config
)
2581 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2583 struct drm_device
*dev
= encoder
->base
.dev
;
2584 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2585 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2586 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2588 tmp
= I915_READ(intel_dp
->output_reg
);
2590 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2592 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2593 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2595 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2596 flags
|= DRM_MODE_FLAG_PHSYNC
;
2598 flags
|= DRM_MODE_FLAG_NHSYNC
;
2600 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2601 flags
|= DRM_MODE_FLAG_PVSYNC
;
2603 flags
|= DRM_MODE_FLAG_NVSYNC
;
2605 if (tmp
& DP_SYNC_HS_HIGH
)
2606 flags
|= DRM_MODE_FLAG_PHSYNC
;
2608 flags
|= DRM_MODE_FLAG_NHSYNC
;
2610 if (tmp
& DP_SYNC_VS_HIGH
)
2611 flags
|= DRM_MODE_FLAG_PVSYNC
;
2613 flags
|= DRM_MODE_FLAG_NVSYNC
;
2616 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2618 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2619 pipe_config
->limited_color_range
= true;
2621 pipe_config
->lane_count
=
2622 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2624 intel_dp_get_m_n(crtc
, pipe_config
);
2626 if (port
== PORT_A
) {
2627 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2628 pipe_config
->port_clock
= 162000;
2630 pipe_config
->port_clock
= 270000;
2633 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2634 intel_dotclock_calculate(pipe_config
->port_clock
,
2635 &pipe_config
->dp_m_n
);
2637 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2638 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2640 * This is a big fat ugly hack.
2642 * Some machines in UEFI boot mode provide us a VBT that has 18
2643 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2644 * unknown we fail to light up. Yet the same BIOS boots up with
2645 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2646 * max, not what it tells us to use.
2648 * Note: This will still be broken if the eDP panel is not lit
2649 * up by the BIOS, and thus we can't get the mode at module
2652 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2653 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2654 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2658 static void intel_disable_dp(struct intel_encoder
*encoder
,
2659 struct intel_crtc_state
*old_crtc_state
,
2660 struct drm_connector_state
*old_conn_state
)
2662 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2663 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2665 if (old_crtc_state
->has_audio
)
2666 intel_audio_codec_disable(encoder
);
2668 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2669 intel_psr_disable(intel_dp
);
2671 /* Make sure the panel is off before trying to change the mode. But also
2672 * ensure that we have vdd while we switch off the panel. */
2673 intel_edp_panel_vdd_on(intel_dp
);
2674 intel_edp_backlight_off(old_conn_state
);
2675 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2676 intel_edp_panel_off(intel_dp
);
2678 /* disable the port before the pipe on g4x */
2679 if (INTEL_GEN(dev_priv
) < 5)
2680 intel_dp_link_down(intel_dp
);
2683 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2684 struct intel_crtc_state
*old_crtc_state
,
2685 struct drm_connector_state
*old_conn_state
)
2687 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2688 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2690 intel_dp_link_down(intel_dp
);
2692 /* Only ilk+ has port A */
2694 ironlake_edp_pll_off(intel_dp
);
2697 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2698 struct intel_crtc_state
*old_crtc_state
,
2699 struct drm_connector_state
*old_conn_state
)
2701 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2703 intel_dp_link_down(intel_dp
);
2706 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2707 struct intel_crtc_state
*old_crtc_state
,
2708 struct drm_connector_state
*old_conn_state
)
2710 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2711 struct drm_device
*dev
= encoder
->base
.dev
;
2712 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2714 intel_dp_link_down(intel_dp
);
2716 mutex_lock(&dev_priv
->sb_lock
);
2718 /* Assert data lane reset */
2719 chv_data_lane_soft_reset(encoder
, true);
2721 mutex_unlock(&dev_priv
->sb_lock
);
2725 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2727 uint8_t dp_train_pat
)
2729 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2730 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2731 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2732 enum port port
= intel_dig_port
->port
;
2734 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2735 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2736 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2738 if (HAS_DDI(dev_priv
)) {
2739 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2741 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2742 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2744 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2746 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2747 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2748 case DP_TRAINING_PATTERN_DISABLE
:
2749 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2752 case DP_TRAINING_PATTERN_1
:
2753 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2755 case DP_TRAINING_PATTERN_2
:
2756 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2758 case DP_TRAINING_PATTERN_3
:
2759 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2762 I915_WRITE(DP_TP_CTL(port
), temp
);
2764 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2765 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2766 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2768 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2769 case DP_TRAINING_PATTERN_DISABLE
:
2770 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2772 case DP_TRAINING_PATTERN_1
:
2773 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2775 case DP_TRAINING_PATTERN_2
:
2776 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2778 case DP_TRAINING_PATTERN_3
:
2779 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2780 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2785 if (IS_CHERRYVIEW(dev_priv
))
2786 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2788 *DP
&= ~DP_LINK_TRAIN_MASK
;
2790 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2791 case DP_TRAINING_PATTERN_DISABLE
:
2792 *DP
|= DP_LINK_TRAIN_OFF
;
2794 case DP_TRAINING_PATTERN_1
:
2795 *DP
|= DP_LINK_TRAIN_PAT_1
;
2797 case DP_TRAINING_PATTERN_2
:
2798 *DP
|= DP_LINK_TRAIN_PAT_2
;
2800 case DP_TRAINING_PATTERN_3
:
2801 if (IS_CHERRYVIEW(dev_priv
)) {
2802 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2804 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2805 *DP
|= DP_LINK_TRAIN_PAT_2
;
2812 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2813 struct intel_crtc_state
*old_crtc_state
)
2815 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2816 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2818 /* enable with pattern 1 (as per spec) */
2820 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2823 * Magic for VLV/CHV. We _must_ first set up the register
2824 * without actually enabling the port, and then do another
2825 * write to enable the port. Otherwise link training will
2826 * fail when the power sequencer is freshly used for this port.
2828 intel_dp
->DP
|= DP_PORT_EN
;
2829 if (old_crtc_state
->has_audio
)
2830 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2832 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2833 POSTING_READ(intel_dp
->output_reg
);
2836 static void intel_enable_dp(struct intel_encoder
*encoder
,
2837 struct intel_crtc_state
*pipe_config
,
2838 struct drm_connector_state
*conn_state
)
2840 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2841 struct drm_device
*dev
= encoder
->base
.dev
;
2842 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2843 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2844 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2845 enum pipe pipe
= crtc
->pipe
;
2847 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2852 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2853 vlv_init_panel_power_sequencer(intel_dp
);
2855 intel_dp_enable_port(intel_dp
, pipe_config
);
2857 edp_panel_vdd_on(intel_dp
);
2858 edp_panel_on(intel_dp
);
2859 edp_panel_vdd_off(intel_dp
, true);
2861 pps_unlock(intel_dp
);
2863 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2864 unsigned int lane_mask
= 0x0;
2866 if (IS_CHERRYVIEW(dev_priv
))
2867 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2869 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2873 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2874 intel_dp_start_link_train(intel_dp
);
2875 intel_dp_stop_link_train(intel_dp
);
2877 if (pipe_config
->has_audio
) {
2878 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2880 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
2884 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2885 struct intel_crtc_state
*pipe_config
,
2886 struct drm_connector_state
*conn_state
)
2888 intel_enable_dp(encoder
, pipe_config
, conn_state
);
2889 intel_edp_backlight_on(pipe_config
, conn_state
);
2892 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2893 struct intel_crtc_state
*pipe_config
,
2894 struct drm_connector_state
*conn_state
)
2896 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2898 intel_edp_backlight_on(pipe_config
, conn_state
);
2899 intel_psr_enable(intel_dp
);
2902 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2903 struct intel_crtc_state
*pipe_config
,
2904 struct drm_connector_state
*conn_state
)
2906 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2907 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2909 intel_dp_prepare(encoder
, pipe_config
);
2911 /* Only ilk+ has port A */
2913 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2916 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2918 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2919 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2920 enum pipe pipe
= intel_dp
->pps_pipe
;
2921 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2923 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
2925 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2928 edp_panel_vdd_off_sync(intel_dp
);
2931 * VLV seems to get confused when multiple power seqeuencers
2932 * have the same port selected (even if only one has power/vdd
2933 * enabled). The failure manifests as vlv_wait_port_ready() failing
2934 * CHV on the other hand doesn't seem to mind having the same port
2935 * selected in multiple power seqeuencers, but let's clear the
2936 * port select always when logically disconnecting a power sequencer
2939 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2940 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2941 I915_WRITE(pp_on_reg
, 0);
2942 POSTING_READ(pp_on_reg
);
2944 intel_dp
->pps_pipe
= INVALID_PIPE
;
2947 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2950 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2951 struct intel_encoder
*encoder
;
2953 lockdep_assert_held(&dev_priv
->pps_mutex
);
2955 for_each_intel_encoder(dev
, encoder
) {
2956 struct intel_dp
*intel_dp
;
2959 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
2960 encoder
->type
!= INTEL_OUTPUT_EDP
)
2963 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2964 port
= dp_to_dig_port(intel_dp
)->port
;
2966 WARN(intel_dp
->active_pipe
== pipe
,
2967 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2968 pipe_name(pipe
), port_name(port
));
2970 if (intel_dp
->pps_pipe
!= pipe
)
2973 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2974 pipe_name(pipe
), port_name(port
));
2976 /* make sure vdd is off before we steal it */
2977 vlv_detach_power_sequencer(intel_dp
);
2981 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2983 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2984 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2985 struct drm_device
*dev
= encoder
->base
.dev
;
2986 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2987 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2989 lockdep_assert_held(&dev_priv
->pps_mutex
);
2991 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
2993 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
2994 intel_dp
->pps_pipe
!= crtc
->pipe
) {
2996 * If another power sequencer was being used on this
2997 * port previously make sure to turn off vdd there while
2998 * we still have control of it.
3000 vlv_detach_power_sequencer(intel_dp
);
3004 * We may be stealing the power
3005 * sequencer from another port.
3007 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
3009 intel_dp
->active_pipe
= crtc
->pipe
;
3011 if (!is_edp(intel_dp
))
3014 /* now it's all ours */
3015 intel_dp
->pps_pipe
= crtc
->pipe
;
3017 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3018 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
3020 /* init power sequencer on this pipe and port */
3021 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
3022 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
3025 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3026 struct intel_crtc_state
*pipe_config
,
3027 struct drm_connector_state
*conn_state
)
3029 vlv_phy_pre_encoder_enable(encoder
);
3031 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3034 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3035 struct intel_crtc_state
*pipe_config
,
3036 struct drm_connector_state
*conn_state
)
3038 intel_dp_prepare(encoder
, pipe_config
);
3040 vlv_phy_pre_pll_enable(encoder
);
3043 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3044 struct intel_crtc_state
*pipe_config
,
3045 struct drm_connector_state
*conn_state
)
3047 chv_phy_pre_encoder_enable(encoder
);
3049 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3051 /* Second common lane will stay alive on its own now */
3052 chv_phy_release_cl2_override(encoder
);
3055 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3056 struct intel_crtc_state
*pipe_config
,
3057 struct drm_connector_state
*conn_state
)
3059 intel_dp_prepare(encoder
, pipe_config
);
3061 chv_phy_pre_pll_enable(encoder
);
3064 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3065 struct intel_crtc_state
*pipe_config
,
3066 struct drm_connector_state
*conn_state
)
3068 chv_phy_post_pll_disable(encoder
);
3072 * Fetch AUX CH registers 0x202 - 0x207 which contain
3073 * link status information
3076 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3078 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3079 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3082 static bool intel_dp_get_y_cord_status(struct intel_dp
*intel_dp
)
3084 uint8_t psr_caps
= 0;
3086 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_PSR_CAPS
, &psr_caps
) != 1)
3088 return psr_caps
& DP_PSR2_SU_Y_COORDINATE_REQUIRED
;
3091 static bool intel_dp_get_colorimetry_status(struct intel_dp
*intel_dp
)
3095 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DPRX_FEATURE_ENUMERATION_LIST
,
3098 return dprx
& DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
;
3101 static bool intel_dp_get_alpm_status(struct intel_dp
*intel_dp
)
3103 uint8_t alpm_caps
= 0;
3105 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_RECEIVER_ALPM_CAP
,
3108 return alpm_caps
& DP_ALPM_CAP
;
3111 /* These are source-specific values. */
3113 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3115 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3116 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3118 if (IS_GEN9_LP(dev_priv
))
3119 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3120 else if (INTEL_GEN(dev_priv
) >= 9) {
3121 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3122 return intel_ddi_dp_voltage_max(encoder
);
3123 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3124 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3125 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3126 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3127 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3128 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3130 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3134 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3136 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3137 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3139 if (INTEL_GEN(dev_priv
) >= 9) {
3140 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3142 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3144 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3146 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3148 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3150 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3152 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3153 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3155 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3157 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3159 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3162 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3164 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3165 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3167 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3169 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3171 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3174 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3176 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3177 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3179 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3182 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3184 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3187 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3189 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3191 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3193 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3196 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3201 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3203 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3204 unsigned long demph_reg_value
, preemph_reg_value
,
3205 uniqtranscale_reg_value
;
3206 uint8_t train_set
= intel_dp
->train_set
[0];
3208 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3209 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3210 preemph_reg_value
= 0x0004000;
3211 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3213 demph_reg_value
= 0x2B405555;
3214 uniqtranscale_reg_value
= 0x552AB83A;
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3217 demph_reg_value
= 0x2B404040;
3218 uniqtranscale_reg_value
= 0x5548B83A;
3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3221 demph_reg_value
= 0x2B245555;
3222 uniqtranscale_reg_value
= 0x5560B83A;
3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3225 demph_reg_value
= 0x2B405555;
3226 uniqtranscale_reg_value
= 0x5598DA3A;
3232 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3233 preemph_reg_value
= 0x0002000;
3234 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3236 demph_reg_value
= 0x2B404040;
3237 uniqtranscale_reg_value
= 0x5552B83A;
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3240 demph_reg_value
= 0x2B404848;
3241 uniqtranscale_reg_value
= 0x5580B83A;
3243 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3244 demph_reg_value
= 0x2B404040;
3245 uniqtranscale_reg_value
= 0x55ADDA3A;
3251 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3252 preemph_reg_value
= 0x0000000;
3253 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3255 demph_reg_value
= 0x2B305555;
3256 uniqtranscale_reg_value
= 0x5570B83A;
3258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3259 demph_reg_value
= 0x2B2B4040;
3260 uniqtranscale_reg_value
= 0x55ADDA3A;
3266 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3267 preemph_reg_value
= 0x0006000;
3268 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3270 demph_reg_value
= 0x1B405555;
3271 uniqtranscale_reg_value
= 0x55ADDA3A;
3281 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3282 uniqtranscale_reg_value
, 0);
3287 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3289 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3290 u32 deemph_reg_value
, margin_reg_value
;
3291 bool uniq_trans_scale
= false;
3292 uint8_t train_set
= intel_dp
->train_set
[0];
3294 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3295 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3296 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3298 deemph_reg_value
= 128;
3299 margin_reg_value
= 52;
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3302 deemph_reg_value
= 128;
3303 margin_reg_value
= 77;
3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3306 deemph_reg_value
= 128;
3307 margin_reg_value
= 102;
3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3310 deemph_reg_value
= 128;
3311 margin_reg_value
= 154;
3312 uniq_trans_scale
= true;
3318 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3319 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3321 deemph_reg_value
= 85;
3322 margin_reg_value
= 78;
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3325 deemph_reg_value
= 85;
3326 margin_reg_value
= 116;
3328 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3329 deemph_reg_value
= 85;
3330 margin_reg_value
= 154;
3336 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3337 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3339 deemph_reg_value
= 64;
3340 margin_reg_value
= 104;
3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3343 deemph_reg_value
= 64;
3344 margin_reg_value
= 154;
3350 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3351 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3353 deemph_reg_value
= 43;
3354 margin_reg_value
= 154;
3364 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3365 margin_reg_value
, uniq_trans_scale
);
3371 gen4_signal_levels(uint8_t train_set
)
3373 uint32_t signal_levels
= 0;
3375 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3376 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3378 signal_levels
|= DP_VOLTAGE_0_4
;
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3381 signal_levels
|= DP_VOLTAGE_0_6
;
3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3384 signal_levels
|= DP_VOLTAGE_0_8
;
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3387 signal_levels
|= DP_VOLTAGE_1_2
;
3390 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3391 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3393 signal_levels
|= DP_PRE_EMPHASIS_0
;
3395 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3396 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3398 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3399 signal_levels
|= DP_PRE_EMPHASIS_6
;
3401 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3402 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3405 return signal_levels
;
3408 /* Gen6's DP voltage swing and pre-emphasis control */
3410 gen6_edp_signal_levels(uint8_t train_set
)
3412 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3413 DP_TRAIN_PRE_EMPHASIS_MASK
);
3414 switch (signal_levels
) {
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3417 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3419 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3421 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3422 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3424 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3425 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3428 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3430 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3431 "0x%x\n", signal_levels
);
3432 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3436 /* Gen7's DP voltage swing and pre-emphasis control */
3438 gen7_edp_signal_levels(uint8_t train_set
)
3440 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3441 DP_TRAIN_PRE_EMPHASIS_MASK
);
3442 switch (signal_levels
) {
3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3444 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3445 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3446 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3448 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3451 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3452 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3453 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3456 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3458 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3461 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3462 "0x%x\n", signal_levels
);
3463 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3468 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3470 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3471 enum port port
= intel_dig_port
->port
;
3472 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3473 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3474 uint32_t signal_levels
, mask
= 0;
3475 uint8_t train_set
= intel_dp
->train_set
[0];
3477 if (HAS_DDI(dev_priv
)) {
3478 signal_levels
= ddi_signal_levels(intel_dp
);
3480 if (IS_GEN9_LP(dev_priv
) || IS_CANNONLAKE(dev_priv
))
3483 mask
= DDI_BUF_EMP_MASK
;
3484 } else if (IS_CHERRYVIEW(dev_priv
)) {
3485 signal_levels
= chv_signal_levels(intel_dp
);
3486 } else if (IS_VALLEYVIEW(dev_priv
)) {
3487 signal_levels
= vlv_signal_levels(intel_dp
);
3488 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3489 signal_levels
= gen7_edp_signal_levels(train_set
);
3490 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3491 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3492 signal_levels
= gen6_edp_signal_levels(train_set
);
3493 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3495 signal_levels
= gen4_signal_levels(train_set
);
3496 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3500 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3502 DRM_DEBUG_KMS("Using vswing level %d\n",
3503 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3504 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3505 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3506 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3508 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3510 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3511 POSTING_READ(intel_dp
->output_reg
);
3515 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3516 uint8_t dp_train_pat
)
3518 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3519 struct drm_i915_private
*dev_priv
=
3520 to_i915(intel_dig_port
->base
.base
.dev
);
3522 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3524 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3525 POSTING_READ(intel_dp
->output_reg
);
3528 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3530 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3531 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3532 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3533 enum port port
= intel_dig_port
->port
;
3536 if (!HAS_DDI(dev_priv
))
3539 val
= I915_READ(DP_TP_CTL(port
));
3540 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3541 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3542 I915_WRITE(DP_TP_CTL(port
), val
);
3545 * On PORT_A we can have only eDP in SST mode. There the only reason
3546 * we need to set idle transmission mode is to work around a HW issue
3547 * where we enable the pipe while not in idle link-training mode.
3548 * In this case there is requirement to wait for a minimum number of
3549 * idle patterns to be sent.
3554 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3555 DP_TP_STATUS_IDLE_DONE
,
3556 DP_TP_STATUS_IDLE_DONE
,
3558 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3562 intel_dp_link_down(struct intel_dp
*intel_dp
)
3564 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3565 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3566 enum port port
= intel_dig_port
->port
;
3567 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3568 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3569 uint32_t DP
= intel_dp
->DP
;
3571 if (WARN_ON(HAS_DDI(dev_priv
)))
3574 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3577 DRM_DEBUG_KMS("\n");
3579 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3580 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3581 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3582 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3584 if (IS_CHERRYVIEW(dev_priv
))
3585 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3587 DP
&= ~DP_LINK_TRAIN_MASK
;
3588 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3590 I915_WRITE(intel_dp
->output_reg
, DP
);
3591 POSTING_READ(intel_dp
->output_reg
);
3593 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3594 I915_WRITE(intel_dp
->output_reg
, DP
);
3595 POSTING_READ(intel_dp
->output_reg
);
3598 * HW workaround for IBX, we need to move the port
3599 * to transcoder A after disabling it to allow the
3600 * matching HDMI port to be enabled on transcoder A.
3602 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3604 * We get CPU/PCH FIFO underruns on the other pipe when
3605 * doing the workaround. Sweep them under the rug.
3607 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3608 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3610 /* always enable with pattern 1 (as per spec) */
3611 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3612 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3613 I915_WRITE(intel_dp
->output_reg
, DP
);
3614 POSTING_READ(intel_dp
->output_reg
);
3617 I915_WRITE(intel_dp
->output_reg
, DP
);
3618 POSTING_READ(intel_dp
->output_reg
);
3620 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3621 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3622 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3625 msleep(intel_dp
->panel_power_down_delay
);
3629 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3631 intel_dp
->active_pipe
= INVALID_PIPE
;
3632 pps_unlock(intel_dp
);
3637 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3639 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3640 sizeof(intel_dp
->dpcd
)) < 0)
3641 return false; /* aux transfer failed */
3643 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3645 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3649 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3651 struct drm_i915_private
*dev_priv
=
3652 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3654 /* this function is meant to be called only once */
3655 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3657 if (!intel_dp_read_dpcd(intel_dp
))
3660 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
3661 drm_dp_is_branch(intel_dp
->dpcd
));
3663 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3664 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3665 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3667 /* Check if the panel supports PSR */
3668 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3670 sizeof(intel_dp
->psr_dpcd
));
3671 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3672 dev_priv
->psr
.sink_support
= true;
3673 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3676 if (INTEL_GEN(dev_priv
) >= 9 &&
3677 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3678 uint8_t frame_sync_cap
;
3680 dev_priv
->psr
.sink_support
= true;
3681 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3682 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3683 &frame_sync_cap
) != 1)
3685 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3686 /* PSR2 needs frame sync as well */
3687 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3688 DRM_DEBUG_KMS("PSR2 %s on sink",
3689 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3691 if (dev_priv
->psr
.psr2_support
) {
3692 dev_priv
->psr
.y_cord_support
=
3693 intel_dp_get_y_cord_status(intel_dp
);
3694 dev_priv
->psr
.colorimetry_support
=
3695 intel_dp_get_colorimetry_status(intel_dp
);
3696 dev_priv
->psr
.alpm
=
3697 intel_dp_get_alpm_status(intel_dp
);
3702 /* Read the eDP Display control capabilities registers */
3703 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3704 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3705 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3706 sizeof(intel_dp
->edp_dpcd
))
3707 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3708 intel_dp
->edp_dpcd
);
3710 /* Intermediate frequency support */
3711 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3712 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3715 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3716 sink_rates
, sizeof(sink_rates
));
3718 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3719 int val
= le16_to_cpu(sink_rates
[i
]);
3724 /* Value read multiplied by 200kHz gives the per-lane
3725 * link rate in kHz. The source rates are, however,
3726 * stored in terms of LS_Clk kHz. The full conversion
3727 * back to symbols is
3728 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3730 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3732 intel_dp
->num_sink_rates
= i
;
3735 if (intel_dp
->num_sink_rates
)
3736 intel_dp
->use_rate_select
= true;
3738 intel_dp_set_sink_rates(intel_dp
);
3740 intel_dp_set_common_rates(intel_dp
);
3747 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3751 if (!intel_dp_read_dpcd(intel_dp
))
3754 /* Don't clobber cached eDP rates. */
3755 if (!is_edp(intel_dp
)) {
3756 intel_dp_set_sink_rates(intel_dp
);
3757 intel_dp_set_common_rates(intel_dp
);
3760 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &sink_count
) <= 0)
3764 * Sink count can change between short pulse hpd hence
3765 * a member variable in intel_dp will track any changes
3766 * between short pulse interrupts.
3768 intel_dp
->sink_count
= DP_GET_SINK_COUNT(sink_count
);
3771 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3772 * a dongle is present but no display. Unless we require to know
3773 * if a dongle is present or not, we don't need to update
3774 * downstream port information. So, an early return here saves
3775 * time from performing other operations which are not required.
3777 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3780 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3781 return true; /* native DP sink */
3783 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3784 return true; /* no per-port downstream info */
3786 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3787 intel_dp
->downstream_ports
,
3788 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3789 return false; /* downstream port status fetch failed */
3795 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3799 if (!i915
.enable_dp_mst
)
3802 if (!intel_dp
->can_mst
)
3805 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3808 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
3811 return mstm_cap
& DP_MST_CAP
;
3815 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3817 if (!i915
.enable_dp_mst
)
3820 if (!intel_dp
->can_mst
)
3823 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3825 if (intel_dp
->is_mst
)
3826 DRM_DEBUG_KMS("Sink is MST capable\n");
3828 DRM_DEBUG_KMS("Sink is not MST capable\n");
3830 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3834 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3836 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3837 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3838 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3844 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3845 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3850 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3851 buf
& ~DP_TEST_SINK_START
) < 0) {
3852 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3858 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3860 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3861 DP_TEST_SINK_MISC
, &buf
) < 0) {
3865 count
= buf
& DP_TEST_COUNT_MASK
;
3866 } while (--attempts
&& count
);
3868 if (attempts
== 0) {
3869 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3874 hsw_enable_ips(intel_crtc
);
3878 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3880 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3881 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3882 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3886 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3889 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3892 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3895 if (buf
& DP_TEST_SINK_START
) {
3896 ret
= intel_dp_sink_crc_stop(intel_dp
);
3901 hsw_disable_ips(intel_crtc
);
3903 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3904 buf
| DP_TEST_SINK_START
) < 0) {
3905 hsw_enable_ips(intel_crtc
);
3909 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3913 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3915 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3916 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3917 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3922 ret
= intel_dp_sink_crc_start(intel_dp
);
3927 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3929 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3930 DP_TEST_SINK_MISC
, &buf
) < 0) {
3934 count
= buf
& DP_TEST_COUNT_MASK
;
3936 } while (--attempts
&& count
== 0);
3938 if (attempts
== 0) {
3939 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3944 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3950 intel_dp_sink_crc_stop(intel_dp
);
3955 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3957 return drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
3958 sink_irq_vector
) == 1;
3962 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3966 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3968 sink_irq_vector
, 14);
3975 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3978 int min_lane_count
= 1;
3979 int link_rate_index
, test_link_rate
;
3980 uint8_t test_lane_count
, test_link_bw
;
3984 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3985 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
3989 DRM_DEBUG_KMS("Lane count read failed\n");
3992 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
3993 /* Validate the requested lane count */
3994 if (test_lane_count
< min_lane_count
||
3995 test_lane_count
> intel_dp
->max_link_lane_count
)
3998 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4001 DRM_DEBUG_KMS("Link Rate read failed\n");
4004 /* Validate the requested link rate */
4005 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4006 link_rate_index
= intel_dp_rate_index(intel_dp
->common_rates
,
4007 intel_dp
->num_common_rates
,
4009 if (link_rate_index
< 0)
4012 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4013 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4018 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4020 uint8_t test_pattern
;
4022 __be16 h_width
, v_height
;
4025 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4026 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4029 DRM_DEBUG_KMS("Test pattern read failed\n");
4032 if (test_pattern
!= DP_COLOR_RAMP
)
4035 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4038 DRM_DEBUG_KMS("H Width read failed\n");
4042 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4045 DRM_DEBUG_KMS("V Height read failed\n");
4049 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4052 DRM_DEBUG_KMS("TEST MISC read failed\n");
4055 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4057 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4059 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4060 case DP_TEST_BIT_DEPTH_6
:
4061 intel_dp
->compliance
.test_data
.bpc
= 6;
4063 case DP_TEST_BIT_DEPTH_8
:
4064 intel_dp
->compliance
.test_data
.bpc
= 8;
4070 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4071 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4072 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4073 /* Set test active flag here so userspace doesn't interrupt things */
4074 intel_dp
->compliance
.test_active
= 1;
4079 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4081 uint8_t test_result
= DP_TEST_ACK
;
4082 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4083 struct drm_connector
*connector
= &intel_connector
->base
;
4085 if (intel_connector
->detect_edid
== NULL
||
4086 connector
->edid_corrupt
||
4087 intel_dp
->aux
.i2c_defer_count
> 6) {
4088 /* Check EDID read for NACKs, DEFERs and corruption
4089 * (DP CTS 1.2 Core r1.1)
4090 * 4.2.2.4 : Failed EDID read, I2C_NAK
4091 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4092 * 4.2.2.6 : EDID corruption detected
4093 * Use failsafe mode for all cases
4095 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4096 intel_dp
->aux
.i2c_defer_count
> 0)
4097 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4098 intel_dp
->aux
.i2c_nack_count
,
4099 intel_dp
->aux
.i2c_defer_count
);
4100 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4102 struct edid
*block
= intel_connector
->detect_edid
;
4104 /* We have to write the checksum
4105 * of the last block read
4107 block
+= intel_connector
->detect_edid
->extensions
;
4109 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4110 block
->checksum
) <= 0)
4111 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4113 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4114 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4117 /* Set test active flag here so userspace doesn't interrupt things */
4118 intel_dp
->compliance
.test_active
= 1;
4123 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4125 uint8_t test_result
= DP_TEST_NAK
;
4129 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4131 uint8_t response
= DP_TEST_NAK
;
4132 uint8_t request
= 0;
4135 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4137 DRM_DEBUG_KMS("Could not read test request from sink\n");
4142 case DP_TEST_LINK_TRAINING
:
4143 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4144 response
= intel_dp_autotest_link_training(intel_dp
);
4146 case DP_TEST_LINK_VIDEO_PATTERN
:
4147 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4148 response
= intel_dp_autotest_video_pattern(intel_dp
);
4150 case DP_TEST_LINK_EDID_READ
:
4151 DRM_DEBUG_KMS("EDID test requested\n");
4152 response
= intel_dp_autotest_edid(intel_dp
);
4154 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4155 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4156 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4159 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4163 if (response
& DP_TEST_ACK
)
4164 intel_dp
->compliance
.test_type
= request
;
4167 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4169 DRM_DEBUG_KMS("Could not write test response to sink\n");
4173 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4177 if (intel_dp
->is_mst
) {
4182 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4186 /* check link status - esi[10] = 0x200c */
4187 if (intel_dp
->active_mst_links
&&
4188 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4189 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4190 intel_dp_start_link_train(intel_dp
);
4191 intel_dp_stop_link_train(intel_dp
);
4194 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4195 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4198 for (retry
= 0; retry
< 3; retry
++) {
4200 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4201 DP_SINK_COUNT_ESI
+1,
4208 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4210 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4218 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4219 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4220 intel_dp
->is_mst
= false;
4221 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4222 /* send a hotplug event */
4223 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4230 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
4232 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4233 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4234 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4236 /* Suppress underruns caused by re-training */
4237 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4238 if (crtc
->config
->has_pch_encoder
)
4239 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4240 intel_crtc_pch_transcoder(crtc
), false);
4242 intel_dp_start_link_train(intel_dp
);
4243 intel_dp_stop_link_train(intel_dp
);
4245 /* Keep underrun reporting disabled until things are stable */
4246 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4248 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4249 if (crtc
->config
->has_pch_encoder
)
4250 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4251 intel_crtc_pch_transcoder(crtc
), true);
4255 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4257 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4258 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4259 u8 link_status
[DP_LINK_STATUS_SIZE
];
4261 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4263 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4264 DRM_ERROR("Failed to get link status\n");
4268 if (!intel_encoder
->base
.crtc
)
4271 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4275 * Validate the cached values of intel_dp->link_rate and
4276 * intel_dp->lane_count before attempting to retrain.
4278 if (!intel_dp_link_params_valid(intel_dp
))
4281 /* Retrain if Channel EQ or CR not ok */
4282 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4283 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4284 intel_encoder
->base
.name
);
4286 intel_dp_retrain_link(intel_dp
);
4291 * According to DP spec
4294 * 2. Configure link according to Receiver Capabilities
4295 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4296 * 4. Check link status on receipt of hot-plug interrupt
4298 * intel_dp_short_pulse - handles short pulse interrupts
4299 * when full detection is not required.
4300 * Returns %true if short pulse is handled and full detection
4301 * is NOT required and %false otherwise.
4304 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4306 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4307 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4308 u8 sink_irq_vector
= 0;
4309 u8 old_sink_count
= intel_dp
->sink_count
;
4313 * Clearing compliance test variables to allow capturing
4314 * of values for next automated test request.
4316 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4319 * Now read the DPCD to see if it's actually running
4320 * If the current value of sink count doesn't match with
4321 * the value that was stored earlier or dpcd read failed
4322 * we need to do full detection
4324 ret
= intel_dp_get_dpcd(intel_dp
);
4326 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4327 /* No need to proceed if we are going to do full detect */
4331 /* Try to read the source of the interrupt */
4332 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4333 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4334 sink_irq_vector
!= 0) {
4335 /* Clear interrupt source */
4336 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4337 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4340 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4341 intel_dp_handle_test_request(intel_dp
);
4342 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4343 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4346 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4347 intel_dp_check_link_status(intel_dp
);
4348 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4349 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4350 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4351 /* Send a Hotplug Uevent to userspace to start modeset */
4352 drm_kms_helper_hotplug_event(intel_encoder
->base
.dev
);
4358 /* XXX this is probably wrong for multiple downstream ports */
4359 static enum drm_connector_status
4360 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4362 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4363 uint8_t *dpcd
= intel_dp
->dpcd
;
4367 lspcon_resume(lspcon
);
4369 if (!intel_dp_get_dpcd(intel_dp
))
4370 return connector_status_disconnected
;
4372 if (is_edp(intel_dp
))
4373 return connector_status_connected
;
4375 /* if there's no downstream port, we're done */
4376 if (!drm_dp_is_branch(dpcd
))
4377 return connector_status_connected
;
4379 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4380 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4381 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4383 return intel_dp
->sink_count
?
4384 connector_status_connected
: connector_status_disconnected
;
4387 if (intel_dp_can_mst(intel_dp
))
4388 return connector_status_connected
;
4390 /* If no HPD, poke DDC gently */
4391 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4392 return connector_status_connected
;
4394 /* Well we tried, say unknown for unreliable port types */
4395 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4396 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4397 if (type
== DP_DS_PORT_TYPE_VGA
||
4398 type
== DP_DS_PORT_TYPE_NON_EDID
)
4399 return connector_status_unknown
;
4401 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4402 DP_DWN_STRM_PORT_TYPE_MASK
;
4403 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4404 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4405 return connector_status_unknown
;
4408 /* Anything else is out of spec, warn and ignore */
4409 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4410 return connector_status_disconnected
;
4413 static enum drm_connector_status
4414 edp_detect(struct intel_dp
*intel_dp
)
4416 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4417 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4418 enum drm_connector_status status
;
4420 status
= intel_panel_detect(dev_priv
);
4421 if (status
== connector_status_unknown
)
4422 status
= connector_status_connected
;
4427 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4428 struct intel_digital_port
*port
)
4432 switch (port
->port
) {
4434 bit
= SDE_PORTB_HOTPLUG
;
4437 bit
= SDE_PORTC_HOTPLUG
;
4440 bit
= SDE_PORTD_HOTPLUG
;
4443 MISSING_CASE(port
->port
);
4447 return I915_READ(SDEISR
) & bit
;
4450 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4451 struct intel_digital_port
*port
)
4455 switch (port
->port
) {
4457 bit
= SDE_PORTB_HOTPLUG_CPT
;
4460 bit
= SDE_PORTC_HOTPLUG_CPT
;
4463 bit
= SDE_PORTD_HOTPLUG_CPT
;
4466 MISSING_CASE(port
->port
);
4470 return I915_READ(SDEISR
) & bit
;
4473 static bool spt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4474 struct intel_digital_port
*port
)
4478 switch (port
->port
) {
4480 bit
= SDE_PORTA_HOTPLUG_SPT
;
4483 bit
= SDE_PORTE_HOTPLUG_SPT
;
4486 return cpt_digital_port_connected(dev_priv
, port
);
4489 return I915_READ(SDEISR
) & bit
;
4492 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4493 struct intel_digital_port
*port
)
4497 switch (port
->port
) {
4499 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4502 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4505 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4508 MISSING_CASE(port
->port
);
4512 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4515 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4516 struct intel_digital_port
*port
)
4520 switch (port
->port
) {
4522 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4525 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4528 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4531 MISSING_CASE(port
->port
);
4535 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4538 static bool ilk_digital_port_connected(struct drm_i915_private
*dev_priv
,
4539 struct intel_digital_port
*port
)
4541 if (port
->port
== PORT_A
)
4542 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4544 return ibx_digital_port_connected(dev_priv
, port
);
4547 static bool snb_digital_port_connected(struct drm_i915_private
*dev_priv
,
4548 struct intel_digital_port
*port
)
4550 if (port
->port
== PORT_A
)
4551 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4553 return cpt_digital_port_connected(dev_priv
, port
);
4556 static bool ivb_digital_port_connected(struct drm_i915_private
*dev_priv
,
4557 struct intel_digital_port
*port
)
4559 if (port
->port
== PORT_A
)
4560 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
4562 return cpt_digital_port_connected(dev_priv
, port
);
4565 static bool bdw_digital_port_connected(struct drm_i915_private
*dev_priv
,
4566 struct intel_digital_port
*port
)
4568 if (port
->port
== PORT_A
)
4569 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
4571 return cpt_digital_port_connected(dev_priv
, port
);
4574 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4575 struct intel_digital_port
*intel_dig_port
)
4577 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4581 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4584 bit
= BXT_DE_PORT_HP_DDIA
;
4587 bit
= BXT_DE_PORT_HP_DDIB
;
4590 bit
= BXT_DE_PORT_HP_DDIC
;
4597 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4601 * intel_digital_port_connected - is the specified port connected?
4602 * @dev_priv: i915 private structure
4603 * @port: the port to test
4605 * Return %true if @port is connected, %false otherwise.
4607 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4608 struct intel_digital_port
*port
)
4610 if (HAS_GMCH_DISPLAY(dev_priv
)) {
4611 if (IS_GM45(dev_priv
))
4612 return gm45_digital_port_connected(dev_priv
, port
);
4614 return g4x_digital_port_connected(dev_priv
, port
);
4617 if (IS_GEN5(dev_priv
))
4618 return ilk_digital_port_connected(dev_priv
, port
);
4619 else if (IS_GEN6(dev_priv
))
4620 return snb_digital_port_connected(dev_priv
, port
);
4621 else if (IS_GEN7(dev_priv
))
4622 return ivb_digital_port_connected(dev_priv
, port
);
4623 else if (IS_GEN8(dev_priv
))
4624 return bdw_digital_port_connected(dev_priv
, port
);
4625 else if (IS_GEN9_LP(dev_priv
))
4626 return bxt_digital_port_connected(dev_priv
, port
);
4628 return spt_digital_port_connected(dev_priv
, port
);
4631 static struct edid
*
4632 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4634 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4636 /* use cached edid if we have one */
4637 if (intel_connector
->edid
) {
4639 if (IS_ERR(intel_connector
->edid
))
4642 return drm_edid_duplicate(intel_connector
->edid
);
4644 return drm_get_edid(&intel_connector
->base
,
4645 &intel_dp
->aux
.ddc
);
4649 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4651 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4654 intel_dp_unset_edid(intel_dp
);
4655 edid
= intel_dp_get_edid(intel_dp
);
4656 intel_connector
->detect_edid
= edid
;
4658 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4662 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4664 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4666 kfree(intel_connector
->detect_edid
);
4667 intel_connector
->detect_edid
= NULL
;
4669 intel_dp
->has_audio
= false;
4673 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4675 struct drm_connector
*connector
= &intel_connector
->base
;
4676 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4677 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4678 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4679 struct drm_device
*dev
= connector
->dev
;
4680 enum drm_connector_status status
;
4681 u8 sink_irq_vector
= 0;
4683 WARN_ON(!drm_modeset_is_locked(&connector
->dev
->mode_config
.connection_mutex
));
4685 intel_display_power_get(to_i915(dev
), intel_dp
->aux_power_domain
);
4687 /* Can't disconnect eDP, but you can close the lid... */
4688 if (is_edp(intel_dp
))
4689 status
= edp_detect(intel_dp
);
4690 else if (intel_digital_port_connected(to_i915(dev
),
4691 dp_to_dig_port(intel_dp
)))
4692 status
= intel_dp_detect_dpcd(intel_dp
);
4694 status
= connector_status_disconnected
;
4696 if (status
== connector_status_disconnected
) {
4697 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4699 if (intel_dp
->is_mst
) {
4700 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4702 intel_dp
->mst_mgr
.mst_state
);
4703 intel_dp
->is_mst
= false;
4704 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4711 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4712 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4714 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4715 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4716 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4718 if (intel_dp
->reset_link_params
) {
4719 /* Initial max link lane count */
4720 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
4722 /* Initial max link rate */
4723 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
4725 intel_dp
->reset_link_params
= false;
4728 intel_dp_print_rates(intel_dp
);
4730 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4731 drm_dp_is_branch(intel_dp
->dpcd
));
4733 intel_dp_configure_mst(intel_dp
);
4735 if (intel_dp
->is_mst
) {
4737 * If we are in MST mode then this connector
4738 * won't appear connected or have anything
4741 status
= connector_status_disconnected
;
4745 * If display is now connected check links status,
4746 * there has been known issues of link loss triggerring
4749 * Some sinks (eg. ASUS PB287Q) seem to perform some
4750 * weird HPD ping pong during modesets. So we can apparently
4751 * end up with HPD going low during a modeset, and then
4752 * going back up soon after. And once that happens we must
4753 * retrain the link to get a picture. That's in case no
4754 * userspace component reacted to intermittent HPD dip.
4756 intel_dp_check_link_status(intel_dp
);
4760 * Clearing NACK and defer counts to get their exact values
4761 * while reading EDID which are required by Compliance tests
4762 * 4.2.2.4 and 4.2.2.5
4764 intel_dp
->aux
.i2c_nack_count
= 0;
4765 intel_dp
->aux
.i2c_defer_count
= 0;
4767 intel_dp_set_edid(intel_dp
);
4768 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4769 status
= connector_status_connected
;
4770 intel_dp
->detect_done
= true;
4772 /* Try to read the source of the interrupt */
4773 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4774 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4775 sink_irq_vector
!= 0) {
4776 /* Clear interrupt source */
4777 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4778 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4781 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4782 intel_dp_handle_test_request(intel_dp
);
4783 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4784 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4788 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4789 intel_dp_unset_edid(intel_dp
);
4791 intel_display_power_put(to_i915(dev
), intel_dp
->aux_power_domain
);
4796 intel_dp_detect(struct drm_connector
*connector
,
4797 struct drm_modeset_acquire_ctx
*ctx
,
4800 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4801 int status
= connector
->status
;
4803 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4804 connector
->base
.id
, connector
->name
);
4806 /* If full detect is not performed yet, do a full detect */
4807 if (!intel_dp
->detect_done
)
4808 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4810 intel_dp
->detect_done
= false;
4816 intel_dp_force(struct drm_connector
*connector
)
4818 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4819 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4820 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4822 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4823 connector
->base
.id
, connector
->name
);
4824 intel_dp_unset_edid(intel_dp
);
4826 if (connector
->status
!= connector_status_connected
)
4829 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4831 intel_dp_set_edid(intel_dp
);
4833 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4835 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4836 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4839 static int intel_dp_get_modes(struct drm_connector
*connector
)
4841 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4844 edid
= intel_connector
->detect_edid
;
4846 int ret
= intel_connector_update_modes(connector
, edid
);
4851 /* if eDP has no EDID, fall back to fixed mode */
4852 if (is_edp(intel_attached_dp(connector
)) &&
4853 intel_connector
->panel
.fixed_mode
) {
4854 struct drm_display_mode
*mode
;
4856 mode
= drm_mode_duplicate(connector
->dev
,
4857 intel_connector
->panel
.fixed_mode
);
4859 drm_mode_probed_add(connector
, mode
);
4868 intel_dp_connector_register(struct drm_connector
*connector
)
4870 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4873 ret
= intel_connector_register(connector
);
4877 i915_debugfs_connector_add(connector
);
4879 DRM_DEBUG_KMS("registering %s bus for %s\n",
4880 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4882 intel_dp
->aux
.dev
= connector
->kdev
;
4883 return drm_dp_aux_register(&intel_dp
->aux
);
4887 intel_dp_connector_unregister(struct drm_connector
*connector
)
4889 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4890 intel_connector_unregister(connector
);
4894 intel_dp_connector_destroy(struct drm_connector
*connector
)
4896 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4898 kfree(intel_connector
->detect_edid
);
4900 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4901 kfree(intel_connector
->edid
);
4903 /* Can't call is_edp() since the encoder may have been destroyed
4905 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4906 intel_panel_fini(&intel_connector
->panel
);
4908 drm_connector_cleanup(connector
);
4912 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4914 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4915 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4917 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4918 if (is_edp(intel_dp
)) {
4919 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4921 * vdd might still be enabled do to the delayed vdd off.
4922 * Make sure vdd is actually turned off here.
4925 edp_panel_vdd_off_sync(intel_dp
);
4926 pps_unlock(intel_dp
);
4928 if (intel_dp
->edp_notifier
.notifier_call
) {
4929 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4930 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4934 intel_dp_aux_fini(intel_dp
);
4936 drm_encoder_cleanup(encoder
);
4937 kfree(intel_dig_port
);
4940 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4942 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4944 if (!is_edp(intel_dp
))
4948 * vdd might still be enabled do to the delayed vdd off.
4949 * Make sure vdd is actually turned off here.
4951 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4953 edp_panel_vdd_off_sync(intel_dp
);
4954 pps_unlock(intel_dp
);
4957 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4959 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4960 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4961 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4963 lockdep_assert_held(&dev_priv
->pps_mutex
);
4965 if (!edp_have_panel_vdd(intel_dp
))
4969 * The VDD bit needs a power domain reference, so if the bit is
4970 * already enabled when we boot or resume, grab this reference and
4971 * schedule a vdd off, so we don't hold on to the reference
4974 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4975 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4977 edp_panel_vdd_schedule_off(intel_dp
);
4980 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
4982 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4984 if ((intel_dp
->DP
& DP_PORT_EN
) == 0)
4985 return INVALID_PIPE
;
4987 if (IS_CHERRYVIEW(dev_priv
))
4988 return DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
4990 return PORT_TO_PIPE(intel_dp
->DP
);
4993 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4995 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4996 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4997 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4999 if (!HAS_DDI(dev_priv
))
5000 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5003 lspcon_resume(lspcon
);
5005 intel_dp
->reset_link_params
= true;
5009 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5010 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5012 if (is_edp(intel_dp
)) {
5013 /* Reinit the power sequencer, in case BIOS did something with it. */
5014 intel_dp_pps_init(encoder
->dev
, intel_dp
);
5015 intel_edp_panel_vdd_sanitize(intel_dp
);
5018 pps_unlock(intel_dp
);
5021 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5022 .force
= intel_dp_force
,
5023 .fill_modes
= drm_helper_probe_single_connector_modes
,
5024 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
5025 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
5026 .late_register
= intel_dp_connector_register
,
5027 .early_unregister
= intel_dp_connector_unregister
,
5028 .destroy
= intel_dp_connector_destroy
,
5029 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5030 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5033 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5034 .detect_ctx
= intel_dp_detect
,
5035 .get_modes
= intel_dp_get_modes
,
5036 .mode_valid
= intel_dp_mode_valid
,
5037 .atomic_check
= intel_digital_connector_atomic_check
,
5040 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5041 .reset
= intel_dp_encoder_reset
,
5042 .destroy
= intel_dp_encoder_destroy
,
5046 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5048 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5049 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
5050 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5051 enum irqreturn ret
= IRQ_NONE
;
5053 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
5054 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
5055 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
5057 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5059 * vdd off can generate a long pulse on eDP which
5060 * would require vdd on to handle it, and thus we
5061 * would end up in an endless cycle of
5062 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5064 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5065 port_name(intel_dig_port
->port
));
5069 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5070 port_name(intel_dig_port
->port
),
5071 long_hpd
? "long" : "short");
5074 intel_dp
->reset_link_params
= true;
5075 intel_dp
->detect_done
= false;
5079 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5081 if (intel_dp
->is_mst
) {
5082 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5084 * If we were in MST mode, and device is not
5085 * there, get out of MST mode
5087 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5088 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5089 intel_dp
->is_mst
= false;
5090 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5092 intel_dp
->detect_done
= false;
5097 if (!intel_dp
->is_mst
) {
5098 if (!intel_dp_short_pulse(intel_dp
)) {
5099 intel_dp
->detect_done
= false;
5107 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5112 /* check the VBT to see whether the eDP is on another port */
5113 bool intel_dp_is_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5116 * eDP not supported on g4x. so bail out early just
5117 * for a bit extra safety in case the VBT is bonkers.
5119 if (INTEL_GEN(dev_priv
) < 5)
5122 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5125 return intel_bios_is_port_edp(dev_priv
, port
);
5129 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5131 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5133 intel_attach_force_audio_property(connector
);
5134 intel_attach_broadcast_rgb_property(connector
);
5136 if (is_edp(intel_dp
)) {
5137 u32 allowed_scalers
;
5139 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
5140 if (!HAS_GMCH_DISPLAY(dev_priv
))
5141 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
5143 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
5145 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
5150 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5152 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5153 intel_dp
->last_power_on
= jiffies
;
5154 intel_dp
->last_backlight_off
= jiffies
;
5158 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
5159 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5161 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5162 struct pps_registers regs
;
5164 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5166 /* Workaround: Need to write PP_CONTROL with the unlock key as
5167 * the very first thing. */
5168 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5170 pp_on
= I915_READ(regs
.pp_on
);
5171 pp_off
= I915_READ(regs
.pp_off
);
5172 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
)) {
5173 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5174 pp_div
= I915_READ(regs
.pp_div
);
5177 /* Pull timing values out of registers */
5178 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5179 PANEL_POWER_UP_DELAY_SHIFT
;
5181 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5182 PANEL_LIGHT_ON_DELAY_SHIFT
;
5184 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5185 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5187 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5188 PANEL_POWER_DOWN_DELAY_SHIFT
;
5190 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) {
5191 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5192 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5194 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5195 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5200 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5202 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5204 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5208 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
5209 struct intel_dp
*intel_dp
)
5211 struct edp_power_seq hw
;
5212 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5214 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
5216 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5217 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5218 DRM_ERROR("PPS state mismatch\n");
5219 intel_pps_dump_state("sw", sw
);
5220 intel_pps_dump_state("hw", &hw
);
5225 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5226 struct intel_dp
*intel_dp
)
5228 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5229 struct edp_power_seq cur
, vbt
, spec
,
5230 *final
= &intel_dp
->pps_delays
;
5232 lockdep_assert_held(&dev_priv
->pps_mutex
);
5234 /* already initialized? */
5235 if (final
->t11_t12
!= 0)
5238 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
5240 intel_pps_dump_state("cur", &cur
);
5242 vbt
= dev_priv
->vbt
.edp
.pps
;
5243 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5244 * of 500ms appears to be too short. Ocassionally the panel
5245 * just fails to power back on. Increasing the delay to 800ms
5246 * seems sufficient to avoid this problem.
5248 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
5249 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 800 * 10);
5250 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5253 /* T11_T12 delay is special and actually in units of 100ms, but zero
5254 * based in the hw (so we need to add 100 ms). But the sw vbt
5255 * table multiplies it with 1000 to make it in units of 100usec,
5257 vbt
.t11_t12
+= 100 * 10;
5259 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5260 * our hw here, which are all in 100usec. */
5261 spec
.t1_t3
= 210 * 10;
5262 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5263 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5264 spec
.t10
= 500 * 10;
5265 /* This one is special and actually in units of 100ms, but zero
5266 * based in the hw (so we need to add 100 ms). But the sw vbt
5267 * table multiplies it with 1000 to make it in units of 100usec,
5269 spec
.t11_t12
= (510 + 100) * 10;
5271 intel_pps_dump_state("vbt", &vbt
);
5273 /* Use the max of the register settings and vbt. If both are
5274 * unset, fall back to the spec limits. */
5275 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5277 max(cur.field, vbt.field))
5278 assign_final(t1_t3
);
5282 assign_final(t11_t12
);
5285 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5286 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5287 intel_dp
->backlight_on_delay
= get_delay(t8
);
5288 intel_dp
->backlight_off_delay
= get_delay(t9
);
5289 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5290 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5293 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5294 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5295 intel_dp
->panel_power_cycle_delay
);
5297 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5298 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5301 * We override the HW backlight delays to 1 because we do manual waits
5302 * on them. For T8, even BSpec recommends doing it. For T9, if we
5303 * don't do this, we'll end up waiting for the backlight off delay
5304 * twice: once when we do the manual sleep, and once when we disable
5305 * the panel and wait for the PP_STATUS bit to become zero.
5312 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5313 struct intel_dp
*intel_dp
,
5314 bool force_disable_vdd
)
5316 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5317 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5318 int div
= dev_priv
->rawclk_freq
/ 1000;
5319 struct pps_registers regs
;
5320 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5321 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5323 lockdep_assert_held(&dev_priv
->pps_mutex
);
5325 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5328 * On some VLV machines the BIOS can leave the VDD
5329 * enabled even on power seqeuencers which aren't
5330 * hooked up to any port. This would mess up the
5331 * power domain tracking the first time we pick
5332 * one of these power sequencers for use since
5333 * edp_panel_vdd_on() would notice that the VDD was
5334 * already on and therefore wouldn't grab the power
5335 * domain reference. Disable VDD first to avoid this.
5336 * This also avoids spuriously turning the VDD on as
5337 * soon as the new power seqeuencer gets initialized.
5339 if (force_disable_vdd
) {
5340 u32 pp
= ironlake_get_pp_control(intel_dp
);
5342 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5344 if (pp
& EDP_FORCE_VDD
)
5345 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5347 pp
&= ~EDP_FORCE_VDD
;
5349 I915_WRITE(regs
.pp_ctrl
, pp
);
5352 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5353 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5354 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5355 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5356 /* Compute the divisor for the pp clock, simply match the Bspec
5358 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) {
5359 pp_div
= I915_READ(regs
.pp_ctrl
);
5360 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5361 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5362 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5364 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5365 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5366 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5369 /* Haswell doesn't have any port selection bits for the panel
5370 * power sequencer any more. */
5371 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5372 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5373 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5375 port_sel
= PANEL_PORT_SELECT_DPA
;
5377 port_sel
= PANEL_PORT_SELECT_DPD
;
5382 I915_WRITE(regs
.pp_on
, pp_on
);
5383 I915_WRITE(regs
.pp_off
, pp_off
);
5384 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
))
5385 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5387 I915_WRITE(regs
.pp_div
, pp_div
);
5389 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5390 I915_READ(regs
.pp_on
),
5391 I915_READ(regs
.pp_off
),
5392 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) ?
5393 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5394 I915_READ(regs
.pp_div
));
5397 static void intel_dp_pps_init(struct drm_device
*dev
,
5398 struct intel_dp
*intel_dp
)
5400 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5402 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5403 vlv_initial_power_sequencer_setup(intel_dp
);
5405 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5406 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
5411 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5412 * @dev_priv: i915 device
5413 * @crtc_state: a pointer to the active intel_crtc_state
5414 * @refresh_rate: RR to be programmed
5416 * This function gets called when refresh rate (RR) has to be changed from
5417 * one frequency to another. Switches can be between high and low RR
5418 * supported by the panel or to any other RR based on media playback (in
5419 * this case, RR value needs to be passed from user space).
5421 * The caller of this function needs to take a lock on dev_priv->drrs.
5423 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5424 struct intel_crtc_state
*crtc_state
,
5427 struct intel_encoder
*encoder
;
5428 struct intel_digital_port
*dig_port
= NULL
;
5429 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5430 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5431 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5433 if (refresh_rate
<= 0) {
5434 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5438 if (intel_dp
== NULL
) {
5439 DRM_DEBUG_KMS("DRRS not supported.\n");
5444 * FIXME: This needs proper synchronization with psr state for some
5445 * platforms that cannot have PSR and DRRS enabled at the same time.
5448 dig_port
= dp_to_dig_port(intel_dp
);
5449 encoder
= &dig_port
->base
;
5450 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5453 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5457 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5458 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5462 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5464 index
= DRRS_LOW_RR
;
5466 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5468 "DRRS requested for previously set RR...ignoring\n");
5472 if (!crtc_state
->base
.active
) {
5473 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5477 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5480 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5483 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5487 DRM_ERROR("Unsupported refreshrate type\n");
5489 } else if (INTEL_GEN(dev_priv
) > 6) {
5490 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5493 val
= I915_READ(reg
);
5494 if (index
> DRRS_HIGH_RR
) {
5495 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5496 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5498 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5500 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5501 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5503 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5505 I915_WRITE(reg
, val
);
5508 dev_priv
->drrs
.refresh_rate_type
= index
;
5510 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5514 * intel_edp_drrs_enable - init drrs struct if supported
5515 * @intel_dp: DP struct
5516 * @crtc_state: A pointer to the active crtc state.
5518 * Initializes frontbuffer_bits and drrs.dp
5520 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5521 struct intel_crtc_state
*crtc_state
)
5523 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5524 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5526 if (!crtc_state
->has_drrs
) {
5527 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5531 mutex_lock(&dev_priv
->drrs
.mutex
);
5532 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5533 DRM_ERROR("DRRS already enabled\n");
5537 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5539 dev_priv
->drrs
.dp
= intel_dp
;
5542 mutex_unlock(&dev_priv
->drrs
.mutex
);
5546 * intel_edp_drrs_disable - Disable DRRS
5547 * @intel_dp: DP struct
5548 * @old_crtc_state: Pointer to old crtc_state.
5551 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5552 struct intel_crtc_state
*old_crtc_state
)
5554 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5555 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5557 if (!old_crtc_state
->has_drrs
)
5560 mutex_lock(&dev_priv
->drrs
.mutex
);
5561 if (!dev_priv
->drrs
.dp
) {
5562 mutex_unlock(&dev_priv
->drrs
.mutex
);
5566 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5567 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5568 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5570 dev_priv
->drrs
.dp
= NULL
;
5571 mutex_unlock(&dev_priv
->drrs
.mutex
);
5573 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5576 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5578 struct drm_i915_private
*dev_priv
=
5579 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5580 struct intel_dp
*intel_dp
;
5582 mutex_lock(&dev_priv
->drrs
.mutex
);
5584 intel_dp
= dev_priv
->drrs
.dp
;
5590 * The delayed work can race with an invalidate hence we need to
5594 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5597 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5598 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5600 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5601 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5605 mutex_unlock(&dev_priv
->drrs
.mutex
);
5609 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5610 * @dev_priv: i915 device
5611 * @frontbuffer_bits: frontbuffer plane tracking bits
5613 * This function gets called everytime rendering on the given planes start.
5614 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5616 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5618 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5619 unsigned int frontbuffer_bits
)
5621 struct drm_crtc
*crtc
;
5624 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5627 cancel_delayed_work(&dev_priv
->drrs
.work
);
5629 mutex_lock(&dev_priv
->drrs
.mutex
);
5630 if (!dev_priv
->drrs
.dp
) {
5631 mutex_unlock(&dev_priv
->drrs
.mutex
);
5635 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5636 pipe
= to_intel_crtc(crtc
)->pipe
;
5638 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5639 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5641 /* invalidate means busy screen hence upclock */
5642 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5643 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5644 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5646 mutex_unlock(&dev_priv
->drrs
.mutex
);
5650 * intel_edp_drrs_flush - Restart Idleness DRRS
5651 * @dev_priv: i915 device
5652 * @frontbuffer_bits: frontbuffer plane tracking bits
5654 * This function gets called every time rendering on the given planes has
5655 * completed or flip on a crtc is completed. So DRRS should be upclocked
5656 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5657 * if no other planes are dirty.
5659 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5661 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5662 unsigned int frontbuffer_bits
)
5664 struct drm_crtc
*crtc
;
5667 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5670 cancel_delayed_work(&dev_priv
->drrs
.work
);
5672 mutex_lock(&dev_priv
->drrs
.mutex
);
5673 if (!dev_priv
->drrs
.dp
) {
5674 mutex_unlock(&dev_priv
->drrs
.mutex
);
5678 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5679 pipe
= to_intel_crtc(crtc
)->pipe
;
5681 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5682 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5684 /* flush means busy screen hence upclock */
5685 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5686 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5687 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5690 * flush also means no more activity hence schedule downclock, if all
5691 * other fbs are quiescent too
5693 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5694 schedule_delayed_work(&dev_priv
->drrs
.work
,
5695 msecs_to_jiffies(1000));
5696 mutex_unlock(&dev_priv
->drrs
.mutex
);
5700 * DOC: Display Refresh Rate Switching (DRRS)
5702 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5703 * which enables swtching between low and high refresh rates,
5704 * dynamically, based on the usage scenario. This feature is applicable
5705 * for internal panels.
5707 * Indication that the panel supports DRRS is given by the panel EDID, which
5708 * would list multiple refresh rates for one resolution.
5710 * DRRS is of 2 types - static and seamless.
5711 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5712 * (may appear as a blink on screen) and is used in dock-undock scenario.
5713 * Seamless DRRS involves changing RR without any visual effect to the user
5714 * and can be used during normal system usage. This is done by programming
5715 * certain registers.
5717 * Support for static/seamless DRRS may be indicated in the VBT based on
5718 * inputs from the panel spec.
5720 * DRRS saves power by switching to low RR based on usage scenarios.
5722 * The implementation is based on frontbuffer tracking implementation. When
5723 * there is a disturbance on the screen triggered by user activity or a periodic
5724 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5725 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5728 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5729 * and intel_edp_drrs_flush() are called.
5731 * DRRS can be further extended to support other internal panels and also
5732 * the scenario of video playback wherein RR is set based on the rate
5733 * requested by userspace.
5737 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5738 * @intel_connector: eDP connector
5739 * @fixed_mode: preferred mode of panel
5741 * This function is called only once at driver load to initialize basic
5745 * Downclock mode if panel supports it, else return NULL.
5746 * DRRS support is determined by the presence of downclock mode (apart
5747 * from VBT setting).
5749 static struct drm_display_mode
*
5750 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5751 struct drm_display_mode
*fixed_mode
)
5753 struct drm_connector
*connector
= &intel_connector
->base
;
5754 struct drm_device
*dev
= connector
->dev
;
5755 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5756 struct drm_display_mode
*downclock_mode
= NULL
;
5758 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5759 mutex_init(&dev_priv
->drrs
.mutex
);
5761 if (INTEL_GEN(dev_priv
) <= 6) {
5762 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5766 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5767 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5771 downclock_mode
= intel_find_panel_downclock
5772 (dev_priv
, fixed_mode
, connector
);
5774 if (!downclock_mode
) {
5775 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5779 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5781 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5782 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5783 return downclock_mode
;
5786 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5787 struct intel_connector
*intel_connector
)
5789 struct drm_connector
*connector
= &intel_connector
->base
;
5790 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5791 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5792 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5793 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5794 struct drm_display_mode
*fixed_mode
= NULL
;
5795 struct drm_display_mode
*downclock_mode
= NULL
;
5797 struct drm_display_mode
*scan
;
5799 enum pipe pipe
= INVALID_PIPE
;
5801 if (!is_edp(intel_dp
))
5805 * On IBX/CPT we may get here with LVDS already registered. Since the
5806 * driver uses the only internal power sequencer available for both
5807 * eDP and LVDS bail out early in this case to prevent interfering
5808 * with an already powered-on LVDS power sequencer.
5810 if (intel_get_lvds_encoder(dev
)) {
5811 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5812 DRM_INFO("LVDS was detected, not registering eDP\n");
5819 intel_dp_init_panel_power_timestamps(intel_dp
);
5820 intel_dp_pps_init(dev
, intel_dp
);
5821 intel_edp_panel_vdd_sanitize(intel_dp
);
5823 pps_unlock(intel_dp
);
5825 /* Cache DPCD and EDID for edp. */
5826 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5829 /* if this fails, presume the device is a ghost */
5830 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5834 mutex_lock(&dev
->mode_config
.mutex
);
5835 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5837 if (drm_add_edid_modes(connector
, edid
)) {
5838 drm_mode_connector_update_edid_property(connector
,
5840 drm_edid_to_eld(connector
, edid
);
5843 edid
= ERR_PTR(-EINVAL
);
5846 edid
= ERR_PTR(-ENOENT
);
5848 intel_connector
->edid
= edid
;
5850 /* prefer fixed mode from EDID if available */
5851 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5852 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5853 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5854 downclock_mode
= intel_dp_drrs_init(
5855 intel_connector
, fixed_mode
);
5860 /* fallback to VBT if available for eDP */
5861 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5862 fixed_mode
= drm_mode_duplicate(dev
,
5863 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5865 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5866 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5867 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5870 mutex_unlock(&dev
->mode_config
.mutex
);
5872 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5873 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5874 register_reboot_notifier(&intel_dp
->edp_notifier
);
5877 * Figure out the current pipe for the initial backlight setup.
5878 * If the current pipe isn't valid, try the PPS pipe, and if that
5879 * fails just assume pipe A.
5881 pipe
= vlv_active_pipe(intel_dp
);
5883 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5884 pipe
= intel_dp
->pps_pipe
;
5886 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5889 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5893 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5894 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5895 intel_panel_setup_backlight(connector
, pipe
);
5900 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5902 * vdd might still be enabled do to the delayed vdd off.
5903 * Make sure vdd is actually turned off here.
5906 edp_panel_vdd_off_sync(intel_dp
);
5907 pps_unlock(intel_dp
);
5912 /* Set up the hotplug pin and aux power domain. */
5914 intel_dp_init_connector_port_info(struct intel_digital_port
*intel_dig_port
)
5916 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
5917 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5919 switch (intel_dig_port
->port
) {
5921 encoder
->hpd_pin
= HPD_PORT_A
;
5922 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_A
;
5925 encoder
->hpd_pin
= HPD_PORT_B
;
5926 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_B
;
5929 encoder
->hpd_pin
= HPD_PORT_C
;
5930 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_C
;
5933 encoder
->hpd_pin
= HPD_PORT_D
;
5934 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5937 encoder
->hpd_pin
= HPD_PORT_E
;
5939 /* FIXME: Check VBT for actual wiring of PORT E */
5940 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5943 MISSING_CASE(intel_dig_port
->port
);
5947 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
5949 struct intel_connector
*intel_connector
;
5950 struct drm_connector
*connector
;
5952 intel_connector
= container_of(work
, typeof(*intel_connector
),
5953 modeset_retry_work
);
5954 connector
= &intel_connector
->base
;
5955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
5958 /* Grab the locks before changing connector property*/
5959 mutex_lock(&connector
->dev
->mode_config
.mutex
);
5960 /* Set connector link status to BAD and send a Uevent to notify
5961 * userspace to do a modeset.
5963 drm_mode_connector_set_link_status_property(connector
,
5964 DRM_MODE_LINK_STATUS_BAD
);
5965 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
5966 /* Send Hotplug uevent so userspace can reprobe */
5967 drm_kms_helper_hotplug_event(connector
->dev
);
5971 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5972 struct intel_connector
*intel_connector
)
5974 struct drm_connector
*connector
= &intel_connector
->base
;
5975 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5976 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5977 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5978 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5979 enum port port
= intel_dig_port
->port
;
5982 /* Initialize the work for modeset in case of link train failure */
5983 INIT_WORK(&intel_connector
->modeset_retry_work
,
5984 intel_dp_modeset_retry_work_fn
);
5986 if (WARN(intel_dig_port
->max_lanes
< 1,
5987 "Not enough lanes (%d) for DP on port %c\n",
5988 intel_dig_port
->max_lanes
, port_name(port
)))
5991 intel_dp_set_source_rates(intel_dp
);
5993 intel_dp
->reset_link_params
= true;
5994 intel_dp
->pps_pipe
= INVALID_PIPE
;
5995 intel_dp
->active_pipe
= INVALID_PIPE
;
5997 /* intel_dp vfuncs */
5998 if (INTEL_GEN(dev_priv
) >= 9)
5999 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
6000 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6001 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
6002 else if (HAS_PCH_SPLIT(dev_priv
))
6003 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
6005 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
6007 if (INTEL_GEN(dev_priv
) >= 9)
6008 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
6010 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
6012 if (HAS_DDI(dev_priv
))
6013 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6015 /* Preserve the current hw state. */
6016 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6017 intel_dp
->attached_connector
= intel_connector
;
6019 if (intel_dp_is_edp(dev_priv
, port
))
6020 type
= DRM_MODE_CONNECTOR_eDP
;
6022 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6024 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6025 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6028 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6029 * for DP the encoder type can be set by the caller to
6030 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6032 if (type
== DRM_MODE_CONNECTOR_eDP
)
6033 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6035 /* eDP only on port B and/or C on vlv/chv */
6036 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6037 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
6040 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6041 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6044 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6045 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6047 connector
->interlace_allowed
= true;
6048 connector
->doublescan_allowed
= 0;
6050 intel_dp_init_connector_port_info(intel_dig_port
);
6052 intel_dp_aux_init(intel_dp
);
6054 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6055 edp_panel_vdd_work
);
6057 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6059 if (HAS_DDI(dev_priv
))
6060 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6062 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6064 /* init MST on ports that can support it */
6065 if (HAS_DP_MST(dev_priv
) && !is_edp(intel_dp
) &&
6066 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
6067 intel_dp_mst_encoder_init(intel_dig_port
,
6068 intel_connector
->base
.base
.id
);
6070 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6071 intel_dp_aux_fini(intel_dp
);
6072 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6076 intel_dp_add_properties(intel_dp
, connector
);
6078 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6079 * 0xd. Failure to do so will result in spurious interrupts being
6080 * generated on the port when a cable is not attached.
6082 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
6083 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6084 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6090 drm_connector_cleanup(connector
);
6095 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6096 i915_reg_t output_reg
,
6099 struct intel_digital_port
*intel_dig_port
;
6100 struct intel_encoder
*intel_encoder
;
6101 struct drm_encoder
*encoder
;
6102 struct intel_connector
*intel_connector
;
6104 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6105 if (!intel_dig_port
)
6108 intel_connector
= intel_connector_alloc();
6109 if (!intel_connector
)
6110 goto err_connector_alloc
;
6112 intel_encoder
= &intel_dig_port
->base
;
6113 encoder
= &intel_encoder
->base
;
6115 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6116 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6117 "DP %c", port_name(port
)))
6118 goto err_encoder_init
;
6120 intel_encoder
->compute_config
= intel_dp_compute_config
;
6121 intel_encoder
->disable
= intel_disable_dp
;
6122 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6123 intel_encoder
->get_config
= intel_dp_get_config
;
6124 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6125 if (IS_CHERRYVIEW(dev_priv
)) {
6126 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6127 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6128 intel_encoder
->enable
= vlv_enable_dp
;
6129 intel_encoder
->post_disable
= chv_post_disable_dp
;
6130 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6131 } else if (IS_VALLEYVIEW(dev_priv
)) {
6132 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6133 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6134 intel_encoder
->enable
= vlv_enable_dp
;
6135 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6137 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6138 intel_encoder
->enable
= g4x_enable_dp
;
6139 if (INTEL_GEN(dev_priv
) >= 5)
6140 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6143 intel_dig_port
->port
= port
;
6144 intel_dig_port
->dp
.output_reg
= output_reg
;
6145 intel_dig_port
->max_lanes
= 4;
6147 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6148 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6149 if (IS_CHERRYVIEW(dev_priv
)) {
6151 intel_encoder
->crtc_mask
= 1 << 2;
6153 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6155 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6157 intel_encoder
->cloneable
= 0;
6158 intel_encoder
->port
= port
;
6160 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6161 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6163 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6164 goto err_init_connector
;
6169 drm_encoder_cleanup(encoder
);
6171 kfree(intel_connector
);
6172 err_connector_alloc
:
6173 kfree(intel_dig_port
);
6177 void intel_dp_mst_suspend(struct drm_device
*dev
)
6179 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6183 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6184 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6186 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6189 if (intel_dig_port
->dp
.is_mst
)
6190 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6194 void intel_dp_mst_resume(struct drm_device
*dev
)
6196 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6199 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6200 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6203 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6206 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6208 intel_dp_check_mst_status(&intel_dig_port
->dp
);