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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44 };
45
46 static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51 };
52
53 static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58 };
59
60 static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65 };
66
67 /**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74 static bool is_edp(struct intel_dp *intel_dp)
75 {
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
79 }
80
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
82 {
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
86 }
87
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89 {
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 }
92
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94 static void edp_panel_vdd_on(struct intel_dp *intel_dp);
95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
96
97 static int
98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
99 {
100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
113 break;
114 default:
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121 }
122
123 /*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
140 static int
141 intel_dp_link_required(int pixel_clock, int bpp)
142 {
143 return (pixel_clock * bpp + 9) / 10;
144 }
145
146 static int
147 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148 {
149 return (max_link_clock * max_lanes * 8) / 10;
150 }
151
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155 {
156 struct intel_dp *intel_dp = intel_attached_dp(connector);
157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
161
162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
164 return MODE_PANEL;
165
166 if (mode->vdisplay > fixed_mode->vdisplay)
167 return MODE_PANEL;
168
169 target_clock = fixed_mode->clock;
170 }
171
172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
179 return MODE_CLOCK_HIGH;
180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
187 return MODE_OK;
188 }
189
190 static uint32_t
191 pack_aux(uint8_t *src, int src_bytes)
192 {
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201 }
202
203 static void
204 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205 {
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211 }
212
213 /* hrawclock is 1/4 the FSB frequency */
214 static int
215 intel_hrawclk(struct drm_device *dev)
216 {
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245 }
246
247 static void
248 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251 static void
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256 static enum pipe
257 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258 {
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282 }
283
284 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285 {
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292 }
293
294 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295 {
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302 }
303
304 static bool edp_have_panel_power(struct intel_dp *intel_dp)
305 {
306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
307 struct drm_i915_private *dev_priv = dev->dev_private;
308
309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
310 }
311
312 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
313 {
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
318 }
319
320 static void
321 intel_dp_check_edp(struct intel_dp *intel_dp)
322 {
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (!is_edp(intel_dp))
327 return;
328
329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
332 I915_READ(_pp_stat_reg(intel_dp)),
333 I915_READ(_pp_ctrl_reg(intel_dp)));
334 }
335 }
336
337 static uint32_t
338 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
339 {
340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
341 struct drm_device *dev = intel_dig_port->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
344 uint32_t status;
345 bool done;
346
347 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
348 if (has_aux_irq)
349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
350 msecs_to_jiffies_timeout(10));
351 else
352 done = wait_for_atomic(C, 10) == 0;
353 if (!done)
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 has_aux_irq);
356 #undef C
357
358 return status;
359 }
360
361 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
362 {
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365
366 /*
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
369 */
370 return index ? 0 : intel_hrawclk(dev) / 2;
371 }
372
373 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
374 {
375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
376 struct drm_device *dev = intel_dig_port->base.base.dev;
377
378 if (index)
379 return 0;
380
381 if (intel_dig_port->port == PORT_A) {
382 if (IS_GEN6(dev) || IS_GEN7(dev))
383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
384 else
385 return 225; /* eDP input clock at 450Mhz */
386 } else {
387 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 }
389 }
390
391 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392 {
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (intel_dig_port->port == PORT_A) {
398 if (index)
399 return 0;
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
401 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
402 /* Workaround for non-ULT HSW */
403 switch (index) {
404 case 0: return 63;
405 case 1: return 72;
406 default: return 0;
407 }
408 } else {
409 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
410 }
411 }
412
413 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414 {
415 return index ? 0 : 100;
416 }
417
418 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
419 bool has_aux_irq,
420 int send_bytes,
421 uint32_t aux_clock_divider)
422 {
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct drm_device *dev = intel_dig_port->base.base.dev;
425 uint32_t precharge, timeout;
426
427 if (IS_GEN6(dev))
428 precharge = 3;
429 else
430 precharge = 5;
431
432 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
433 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
434 else
435 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
436
437 return DP_AUX_CH_CTL_SEND_BUSY |
438 DP_AUX_CH_CTL_DONE |
439 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
440 DP_AUX_CH_CTL_TIME_OUT_ERROR |
441 timeout |
442 DP_AUX_CH_CTL_RECEIVE_ERROR |
443 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
444 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
445 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
446 }
447
448 static int
449 intel_dp_aux_ch(struct intel_dp *intel_dp,
450 uint8_t *send, int send_bytes,
451 uint8_t *recv, int recv_size)
452 {
453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
454 struct drm_device *dev = intel_dig_port->base.base.dev;
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
457 uint32_t ch_data = ch_ctl + 4;
458 uint32_t aux_clock_divider;
459 int i, ret, recv_bytes;
460 uint32_t status;
461 int try, clock = 0;
462 bool has_aux_irq = true;
463
464 /* dp aux is extremely sensitive to irq latency, hence request the
465 * lowest possible wakeup latency and so prevent the cpu from going into
466 * deep sleep states.
467 */
468 pm_qos_update_request(&dev_priv->pm_qos, 0);
469
470 intel_dp_check_edp(intel_dp);
471
472 intel_aux_display_runtime_get(dev_priv);
473
474 /* Try to wait for any previous AUX channel activity */
475 for (try = 0; try < 3; try++) {
476 status = I915_READ_NOTRACE(ch_ctl);
477 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
478 break;
479 msleep(1);
480 }
481
482 if (try == 3) {
483 WARN(1, "dp_aux_ch not started status 0x%08x\n",
484 I915_READ(ch_ctl));
485 ret = -EBUSY;
486 goto out;
487 }
488
489 /* Only 5 data registers! */
490 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
491 ret = -E2BIG;
492 goto out;
493 }
494
495 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
496 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
497 has_aux_irq,
498 send_bytes,
499 aux_clock_divider);
500
501 /* Must try at least 3 times according to DP spec */
502 for (try = 0; try < 5; try++) {
503 /* Load the send data into the aux channel data registers */
504 for (i = 0; i < send_bytes; i += 4)
505 I915_WRITE(ch_data + i,
506 pack_aux(send + i, send_bytes - i));
507
508 /* Send the command and wait for it to complete */
509 I915_WRITE(ch_ctl, send_ctl);
510
511 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
512
513 /* Clear done status and any errors */
514 I915_WRITE(ch_ctl,
515 status |
516 DP_AUX_CH_CTL_DONE |
517 DP_AUX_CH_CTL_TIME_OUT_ERROR |
518 DP_AUX_CH_CTL_RECEIVE_ERROR);
519
520 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
521 DP_AUX_CH_CTL_RECEIVE_ERROR))
522 continue;
523 if (status & DP_AUX_CH_CTL_DONE)
524 break;
525 }
526 if (status & DP_AUX_CH_CTL_DONE)
527 break;
528 }
529
530 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
531 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
532 ret = -EBUSY;
533 goto out;
534 }
535
536 /* Check for timeout or receive error.
537 * Timeouts occur when the sink is not connected
538 */
539 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
540 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
541 ret = -EIO;
542 goto out;
543 }
544
545 /* Timeouts occur when the device isn't connected, so they're
546 * "normal" -- don't fill the kernel log with these */
547 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
548 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
549 ret = -ETIMEDOUT;
550 goto out;
551 }
552
553 /* Unload any bytes sent back from the other side */
554 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
555 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
556 if (recv_bytes > recv_size)
557 recv_bytes = recv_size;
558
559 for (i = 0; i < recv_bytes; i += 4)
560 unpack_aux(I915_READ(ch_data + i),
561 recv + i, recv_bytes - i);
562
563 ret = recv_bytes;
564 out:
565 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
566 intel_aux_display_runtime_put(dev_priv);
567
568 return ret;
569 }
570
571 /* Write data to the aux channel in native mode */
572 static int
573 intel_dp_aux_native_write(struct intel_dp *intel_dp,
574 uint16_t address, uint8_t *send, int send_bytes)
575 {
576 int ret;
577 uint8_t msg[20];
578 int msg_bytes;
579 uint8_t ack;
580
581 if (WARN_ON(send_bytes > 16))
582 return -E2BIG;
583
584 intel_dp_check_edp(intel_dp);
585 msg[0] = DP_AUX_NATIVE_WRITE << 4;
586 msg[1] = address >> 8;
587 msg[2] = address & 0xff;
588 msg[3] = send_bytes - 1;
589 memcpy(&msg[4], send, send_bytes);
590 msg_bytes = send_bytes + 4;
591 for (;;) {
592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
593 if (ret < 0)
594 return ret;
595 ack >>= 4;
596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
597 break;
598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
599 udelay(100);
600 else
601 return -EIO;
602 }
603 return send_bytes;
604 }
605
606 /* Write a single byte to the aux channel in native mode */
607 static int
608 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
609 uint16_t address, uint8_t byte)
610 {
611 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
612 }
613
614 /* read bytes from a native aux channel */
615 static int
616 intel_dp_aux_native_read(struct intel_dp *intel_dp,
617 uint16_t address, uint8_t *recv, int recv_bytes)
618 {
619 uint8_t msg[4];
620 int msg_bytes;
621 uint8_t reply[20];
622 int reply_bytes;
623 uint8_t ack;
624 int ret;
625
626 if (WARN_ON(recv_bytes > 19))
627 return -E2BIG;
628
629 intel_dp_check_edp(intel_dp);
630 msg[0] = DP_AUX_NATIVE_READ << 4;
631 msg[1] = address >> 8;
632 msg[2] = address & 0xff;
633 msg[3] = recv_bytes - 1;
634
635 msg_bytes = 4;
636 reply_bytes = recv_bytes + 1;
637
638 for (;;) {
639 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
640 reply, reply_bytes);
641 if (ret == 0)
642 return -EPROTO;
643 if (ret < 0)
644 return ret;
645 ack = reply[0] >> 4;
646 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
647 memcpy(recv, reply + 1, ret - 1);
648 return ret - 1;
649 }
650 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
651 udelay(100);
652 else
653 return -EIO;
654 }
655 }
656
657 static int
658 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
659 uint8_t write_byte, uint8_t *read_byte)
660 {
661 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
662 struct intel_dp *intel_dp = container_of(adapter,
663 struct intel_dp,
664 adapter);
665 uint16_t address = algo_data->address;
666 uint8_t msg[5];
667 uint8_t reply[2];
668 unsigned retry;
669 int msg_bytes;
670 int reply_bytes;
671 int ret;
672
673 edp_panel_vdd_on(intel_dp);
674 intel_dp_check_edp(intel_dp);
675 /* Set up the command byte */
676 if (mode & MODE_I2C_READ)
677 msg[0] = DP_AUX_I2C_READ << 4;
678 else
679 msg[0] = DP_AUX_I2C_WRITE << 4;
680
681 if (!(mode & MODE_I2C_STOP))
682 msg[0] |= DP_AUX_I2C_MOT << 4;
683
684 msg[1] = address >> 8;
685 msg[2] = address;
686
687 switch (mode) {
688 case MODE_I2C_WRITE:
689 msg[3] = 0;
690 msg[4] = write_byte;
691 msg_bytes = 5;
692 reply_bytes = 1;
693 break;
694 case MODE_I2C_READ:
695 msg[3] = 0;
696 msg_bytes = 4;
697 reply_bytes = 2;
698 break;
699 default:
700 msg_bytes = 3;
701 reply_bytes = 1;
702 break;
703 }
704
705 /*
706 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
707 * required to retry at least seven times upon receiving AUX_DEFER
708 * before giving up the AUX transaction.
709 */
710 for (retry = 0; retry < 7; retry++) {
711 ret = intel_dp_aux_ch(intel_dp,
712 msg, msg_bytes,
713 reply, reply_bytes);
714 if (ret < 0) {
715 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
716 goto out;
717 }
718
719 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
720 case DP_AUX_NATIVE_REPLY_ACK:
721 /* I2C-over-AUX Reply field is only valid
722 * when paired with AUX ACK.
723 */
724 break;
725 case DP_AUX_NATIVE_REPLY_NACK:
726 DRM_DEBUG_KMS("aux_ch native nack\n");
727 ret = -EREMOTEIO;
728 goto out;
729 case DP_AUX_NATIVE_REPLY_DEFER:
730 /*
731 * For now, just give more slack to branch devices. We
732 * could check the DPCD for I2C bit rate capabilities,
733 * and if available, adjust the interval. We could also
734 * be more careful with DP-to-Legacy adapters where a
735 * long legacy cable may force very low I2C bit rates.
736 */
737 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
738 DP_DWN_STRM_PORT_PRESENT)
739 usleep_range(500, 600);
740 else
741 usleep_range(300, 400);
742 continue;
743 default:
744 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
745 reply[0]);
746 ret = -EREMOTEIO;
747 goto out;
748 }
749
750 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
751 case DP_AUX_I2C_REPLY_ACK:
752 if (mode == MODE_I2C_READ) {
753 *read_byte = reply[1];
754 }
755 ret = reply_bytes - 1;
756 goto out;
757 case DP_AUX_I2C_REPLY_NACK:
758 DRM_DEBUG_KMS("aux_i2c nack\n");
759 ret = -EREMOTEIO;
760 goto out;
761 case DP_AUX_I2C_REPLY_DEFER:
762 DRM_DEBUG_KMS("aux_i2c defer\n");
763 udelay(100);
764 break;
765 default:
766 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
767 ret = -EREMOTEIO;
768 goto out;
769 }
770 }
771
772 DRM_ERROR("too many retries, giving up\n");
773 ret = -EREMOTEIO;
774
775 out:
776 edp_panel_vdd_off(intel_dp, false);
777 return ret;
778 }
779
780 static void
781 intel_dp_connector_unregister(struct intel_connector *intel_connector)
782 {
783 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
784
785 sysfs_remove_link(&intel_connector->base.kdev->kobj,
786 intel_dp->adapter.dev.kobj.name);
787 intel_connector_unregister(intel_connector);
788 }
789
790 static int
791 intel_dp_i2c_init(struct intel_dp *intel_dp,
792 struct intel_connector *intel_connector, const char *name)
793 {
794 int ret;
795
796 DRM_DEBUG_KMS("i2c_init %s\n", name);
797 intel_dp->algo.running = false;
798 intel_dp->algo.address = 0;
799 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
800
801 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
802 intel_dp->adapter.owner = THIS_MODULE;
803 intel_dp->adapter.class = I2C_CLASS_DDC;
804 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
805 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
806 intel_dp->adapter.algo_data = &intel_dp->algo;
807 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
808
809 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
810 if (ret < 0)
811 return ret;
812
813 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
814 &intel_dp->adapter.dev.kobj,
815 intel_dp->adapter.dev.kobj.name);
816
817 if (ret < 0)
818 i2c_del_adapter(&intel_dp->adapter);
819
820 return ret;
821 }
822
823 static void
824 intel_dp_set_clock(struct intel_encoder *encoder,
825 struct intel_crtc_config *pipe_config, int link_bw)
826 {
827 struct drm_device *dev = encoder->base.dev;
828 const struct dp_link_dpll *divisor = NULL;
829 int i, count = 0;
830
831 if (IS_G4X(dev)) {
832 divisor = gen4_dpll;
833 count = ARRAY_SIZE(gen4_dpll);
834 } else if (IS_HASWELL(dev)) {
835 /* Haswell has special-purpose DP DDI clocks. */
836 } else if (HAS_PCH_SPLIT(dev)) {
837 divisor = pch_dpll;
838 count = ARRAY_SIZE(pch_dpll);
839 } else if (IS_VALLEYVIEW(dev)) {
840 divisor = vlv_dpll;
841 count = ARRAY_SIZE(vlv_dpll);
842 }
843
844 if (divisor && count) {
845 for (i = 0; i < count; i++) {
846 if (link_bw == divisor[i].link_bw) {
847 pipe_config->dpll = divisor[i].dpll;
848 pipe_config->clock_set = true;
849 break;
850 }
851 }
852 }
853 }
854
855 bool
856 intel_dp_compute_config(struct intel_encoder *encoder,
857 struct intel_crtc_config *pipe_config)
858 {
859 struct drm_device *dev = encoder->base.dev;
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
862 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
863 enum port port = dp_to_dig_port(intel_dp)->port;
864 struct intel_crtc *intel_crtc = encoder->new_crtc;
865 struct intel_connector *intel_connector = intel_dp->attached_connector;
866 int lane_count, clock;
867 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
868 /* Conveniently, the link BW constants become indices with a shift...*/
869 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
870 int bpp, mode_rate;
871 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
872 int link_avail, link_clock;
873
874 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
875 pipe_config->has_pch_encoder = true;
876
877 pipe_config->has_dp_encoder = true;
878
879 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
880 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
881 adjusted_mode);
882 if (!HAS_PCH_SPLIT(dev))
883 intel_gmch_panel_fitting(intel_crtc, pipe_config,
884 intel_connector->panel.fitting_mode);
885 else
886 intel_pch_panel_fitting(intel_crtc, pipe_config,
887 intel_connector->panel.fitting_mode);
888 }
889
890 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
891 return false;
892
893 DRM_DEBUG_KMS("DP link computation with max lane count %i "
894 "max bw %02x pixel clock %iKHz\n",
895 max_lane_count, bws[max_clock],
896 adjusted_mode->crtc_clock);
897
898 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
899 * bpc in between. */
900 bpp = pipe_config->pipe_bpp;
901 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
902 dev_priv->vbt.edp_bpp < bpp) {
903 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
904 dev_priv->vbt.edp_bpp);
905 bpp = dev_priv->vbt.edp_bpp;
906 }
907
908 for (; bpp >= 6*3; bpp -= 2*3) {
909 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
910 bpp);
911
912 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
913 for (clock = 0; clock <= max_clock; clock++) {
914 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
915 link_avail = intel_dp_max_data_rate(link_clock,
916 lane_count);
917
918 if (mode_rate <= link_avail) {
919 goto found;
920 }
921 }
922 }
923 }
924
925 return false;
926
927 found:
928 if (intel_dp->color_range_auto) {
929 /*
930 * See:
931 * CEA-861-E - 5.1 Default Encoding Parameters
932 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
933 */
934 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
935 intel_dp->color_range = DP_COLOR_RANGE_16_235;
936 else
937 intel_dp->color_range = 0;
938 }
939
940 if (intel_dp->color_range)
941 pipe_config->limited_color_range = true;
942
943 intel_dp->link_bw = bws[clock];
944 intel_dp->lane_count = lane_count;
945 pipe_config->pipe_bpp = bpp;
946 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
947
948 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
949 intel_dp->link_bw, intel_dp->lane_count,
950 pipe_config->port_clock, bpp);
951 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
952 mode_rate, link_avail);
953
954 intel_link_compute_m_n(bpp, lane_count,
955 adjusted_mode->crtc_clock,
956 pipe_config->port_clock,
957 &pipe_config->dp_m_n);
958
959 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
960
961 return true;
962 }
963
964 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
965 {
966 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
967 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
968 struct drm_device *dev = crtc->base.dev;
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 u32 dpa_ctl;
971
972 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
973 dpa_ctl = I915_READ(DP_A);
974 dpa_ctl &= ~DP_PLL_FREQ_MASK;
975
976 if (crtc->config.port_clock == 162000) {
977 /* For a long time we've carried around a ILK-DevA w/a for the
978 * 160MHz clock. If we're really unlucky, it's still required.
979 */
980 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
981 dpa_ctl |= DP_PLL_FREQ_160MHZ;
982 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
983 } else {
984 dpa_ctl |= DP_PLL_FREQ_270MHZ;
985 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
986 }
987
988 I915_WRITE(DP_A, dpa_ctl);
989
990 POSTING_READ(DP_A);
991 udelay(500);
992 }
993
994 static void intel_dp_mode_set(struct intel_encoder *encoder)
995 {
996 struct drm_device *dev = encoder->base.dev;
997 struct drm_i915_private *dev_priv = dev->dev_private;
998 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
999 enum port port = dp_to_dig_port(intel_dp)->port;
1000 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1001 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1002
1003 /*
1004 * There are four kinds of DP registers:
1005 *
1006 * IBX PCH
1007 * SNB CPU
1008 * IVB CPU
1009 * CPT PCH
1010 *
1011 * IBX PCH and CPU are the same for almost everything,
1012 * except that the CPU DP PLL is configured in this
1013 * register
1014 *
1015 * CPT PCH is quite different, having many bits moved
1016 * to the TRANS_DP_CTL register instead. That
1017 * configuration happens (oddly) in ironlake_pch_enable
1018 */
1019
1020 /* Preserve the BIOS-computed detected bit. This is
1021 * supposed to be read-only.
1022 */
1023 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1024
1025 /* Handle DP bits in common between all three register formats */
1026 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1027 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1028
1029 if (intel_dp->has_audio) {
1030 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1031 pipe_name(crtc->pipe));
1032 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1033 intel_write_eld(&encoder->base, adjusted_mode);
1034 }
1035
1036 /* Split out the IBX/CPU vs CPT settings */
1037
1038 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1039 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1040 intel_dp->DP |= DP_SYNC_HS_HIGH;
1041 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1042 intel_dp->DP |= DP_SYNC_VS_HIGH;
1043 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1044
1045 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1046 intel_dp->DP |= DP_ENHANCED_FRAMING;
1047
1048 intel_dp->DP |= crtc->pipe << 29;
1049 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1050 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1051 intel_dp->DP |= intel_dp->color_range;
1052
1053 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1054 intel_dp->DP |= DP_SYNC_HS_HIGH;
1055 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1056 intel_dp->DP |= DP_SYNC_VS_HIGH;
1057 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1058
1059 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1060 intel_dp->DP |= DP_ENHANCED_FRAMING;
1061
1062 if (crtc->pipe == 1)
1063 intel_dp->DP |= DP_PIPEB_SELECT;
1064 } else {
1065 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1066 }
1067
1068 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1069 ironlake_set_pll_cpu_edp(intel_dp);
1070 }
1071
1072 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1073 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1074
1075 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1076 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1077
1078 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1079 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1080
1081 static void wait_panel_status(struct intel_dp *intel_dp,
1082 u32 mask,
1083 u32 value)
1084 {
1085 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 u32 pp_stat_reg, pp_ctrl_reg;
1088
1089 pp_stat_reg = _pp_stat_reg(intel_dp);
1090 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1091
1092 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1093 mask, value,
1094 I915_READ(pp_stat_reg),
1095 I915_READ(pp_ctrl_reg));
1096
1097 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1098 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1099 I915_READ(pp_stat_reg),
1100 I915_READ(pp_ctrl_reg));
1101 }
1102
1103 DRM_DEBUG_KMS("Wait complete\n");
1104 }
1105
1106 static void wait_panel_on(struct intel_dp *intel_dp)
1107 {
1108 DRM_DEBUG_KMS("Wait for panel power on\n");
1109 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1110 }
1111
1112 static void wait_panel_off(struct intel_dp *intel_dp)
1113 {
1114 DRM_DEBUG_KMS("Wait for panel power off time\n");
1115 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1116 }
1117
1118 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1119 {
1120 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1121
1122 /* When we disable the VDD override bit last we have to do the manual
1123 * wait. */
1124 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1125 intel_dp->panel_power_cycle_delay);
1126
1127 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1128 }
1129
1130 static void wait_backlight_on(struct intel_dp *intel_dp)
1131 {
1132 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1133 intel_dp->backlight_on_delay);
1134 }
1135
1136 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1137 {
1138 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1139 intel_dp->backlight_off_delay);
1140 }
1141
1142 /* Read the current pp_control value, unlocking the register if it
1143 * is locked
1144 */
1145
1146 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1147 {
1148 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 u32 control;
1151
1152 control = I915_READ(_pp_ctrl_reg(intel_dp));
1153 control &= ~PANEL_UNLOCK_MASK;
1154 control |= PANEL_UNLOCK_REGS;
1155 return control;
1156 }
1157
1158 static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1159 {
1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 pp;
1163 u32 pp_stat_reg, pp_ctrl_reg;
1164
1165 if (!is_edp(intel_dp))
1166 return;
1167
1168 WARN(intel_dp->want_panel_vdd,
1169 "eDP VDD already requested on\n");
1170
1171 intel_dp->want_panel_vdd = true;
1172
1173 if (edp_have_panel_vdd(intel_dp))
1174 return;
1175
1176 intel_runtime_pm_get(dev_priv);
1177
1178 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1179
1180 if (!edp_have_panel_power(intel_dp))
1181 wait_panel_power_cycle(intel_dp);
1182
1183 pp = ironlake_get_pp_control(intel_dp);
1184 pp |= EDP_FORCE_VDD;
1185
1186 pp_stat_reg = _pp_stat_reg(intel_dp);
1187 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1188
1189 I915_WRITE(pp_ctrl_reg, pp);
1190 POSTING_READ(pp_ctrl_reg);
1191 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1192 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1193 /*
1194 * If the panel wasn't on, delay before accessing aux channel
1195 */
1196 if (!edp_have_panel_power(intel_dp)) {
1197 DRM_DEBUG_KMS("eDP was not running\n");
1198 msleep(intel_dp->panel_power_up_delay);
1199 }
1200 }
1201
1202 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1203 {
1204 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u32 pp;
1207 u32 pp_stat_reg, pp_ctrl_reg;
1208
1209 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1210
1211 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1212 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1213
1214 pp = ironlake_get_pp_control(intel_dp);
1215 pp &= ~EDP_FORCE_VDD;
1216
1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1218 pp_stat_reg = _pp_stat_reg(intel_dp);
1219
1220 I915_WRITE(pp_ctrl_reg, pp);
1221 POSTING_READ(pp_ctrl_reg);
1222
1223 /* Make sure sequencer is idle before allowing subsequent activity */
1224 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1225 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1226
1227 if ((pp & POWER_TARGET_ON) == 0)
1228 intel_dp->last_power_cycle = jiffies;
1229
1230 intel_runtime_pm_put(dev_priv);
1231 }
1232 }
1233
1234 static void edp_panel_vdd_work(struct work_struct *__work)
1235 {
1236 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1237 struct intel_dp, panel_vdd_work);
1238 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1239
1240 mutex_lock(&dev->mode_config.mutex);
1241 edp_panel_vdd_off_sync(intel_dp);
1242 mutex_unlock(&dev->mode_config.mutex);
1243 }
1244
1245 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1246 {
1247 if (!is_edp(intel_dp))
1248 return;
1249
1250 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1251
1252 intel_dp->want_panel_vdd = false;
1253
1254 if (sync) {
1255 edp_panel_vdd_off_sync(intel_dp);
1256 } else {
1257 /*
1258 * Queue the timer to fire a long
1259 * time from now (relative to the power down delay)
1260 * to keep the panel power up across a sequence of operations
1261 */
1262 schedule_delayed_work(&intel_dp->panel_vdd_work,
1263 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1264 }
1265 }
1266
1267 void intel_edp_panel_on(struct intel_dp *intel_dp)
1268 {
1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 u32 pp;
1272 u32 pp_ctrl_reg;
1273
1274 if (!is_edp(intel_dp))
1275 return;
1276
1277 DRM_DEBUG_KMS("Turn eDP power on\n");
1278
1279 if (edp_have_panel_power(intel_dp)) {
1280 DRM_DEBUG_KMS("eDP power already on\n");
1281 return;
1282 }
1283
1284 wait_panel_power_cycle(intel_dp);
1285
1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1287 pp = ironlake_get_pp_control(intel_dp);
1288 if (IS_GEN5(dev)) {
1289 /* ILK workaround: disable reset around power sequence */
1290 pp &= ~PANEL_POWER_RESET;
1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
1293 }
1294
1295 pp |= POWER_TARGET_ON;
1296 if (!IS_GEN5(dev))
1297 pp |= PANEL_POWER_RESET;
1298
1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
1301
1302 wait_panel_on(intel_dp);
1303 intel_dp->last_power_on = jiffies;
1304
1305 if (IS_GEN5(dev)) {
1306 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1307 I915_WRITE(pp_ctrl_reg, pp);
1308 POSTING_READ(pp_ctrl_reg);
1309 }
1310 }
1311
1312 void intel_edp_panel_off(struct intel_dp *intel_dp)
1313 {
1314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 u32 pp;
1317 u32 pp_ctrl_reg;
1318
1319 if (!is_edp(intel_dp))
1320 return;
1321
1322 DRM_DEBUG_KMS("Turn eDP power off\n");
1323
1324 edp_wait_backlight_off(intel_dp);
1325
1326 pp = ironlake_get_pp_control(intel_dp);
1327 /* We need to switch off panel power _and_ force vdd, for otherwise some
1328 * panels get very unhappy and cease to work. */
1329 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1330 EDP_BLC_ENABLE);
1331
1332 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1333
1334 I915_WRITE(pp_ctrl_reg, pp);
1335 POSTING_READ(pp_ctrl_reg);
1336
1337 intel_dp->last_power_cycle = jiffies;
1338 wait_panel_off(intel_dp);
1339 }
1340
1341 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1342 {
1343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1344 struct drm_device *dev = intel_dig_port->base.base.dev;
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 u32 pp;
1347 u32 pp_ctrl_reg;
1348
1349 if (!is_edp(intel_dp))
1350 return;
1351
1352 DRM_DEBUG_KMS("\n");
1353 /*
1354 * If we enable the backlight right away following a panel power
1355 * on, we may see slight flicker as the panel syncs with the eDP
1356 * link. So delay a bit to make sure the image is solid before
1357 * allowing it to appear.
1358 */
1359 wait_backlight_on(intel_dp);
1360 pp = ironlake_get_pp_control(intel_dp);
1361 pp |= EDP_BLC_ENABLE;
1362
1363 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1364
1365 I915_WRITE(pp_ctrl_reg, pp);
1366 POSTING_READ(pp_ctrl_reg);
1367
1368 intel_panel_enable_backlight(intel_dp->attached_connector);
1369 }
1370
1371 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1372 {
1373 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 u32 pp;
1376 u32 pp_ctrl_reg;
1377
1378 if (!is_edp(intel_dp))
1379 return;
1380
1381 intel_panel_disable_backlight(intel_dp->attached_connector);
1382
1383 DRM_DEBUG_KMS("\n");
1384 pp = ironlake_get_pp_control(intel_dp);
1385 pp &= ~EDP_BLC_ENABLE;
1386
1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1388
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
1391 intel_dp->last_backlight_off = jiffies;
1392 }
1393
1394 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1395 {
1396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1397 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1398 struct drm_device *dev = crtc->dev;
1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 u32 dpa_ctl;
1401
1402 assert_pipe_disabled(dev_priv,
1403 to_intel_crtc(crtc)->pipe);
1404
1405 DRM_DEBUG_KMS("\n");
1406 dpa_ctl = I915_READ(DP_A);
1407 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1408 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1409
1410 /* We don't adjust intel_dp->DP while tearing down the link, to
1411 * facilitate link retraining (e.g. after hotplug). Hence clear all
1412 * enable bits here to ensure that we don't enable too much. */
1413 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1414 intel_dp->DP |= DP_PLL_ENABLE;
1415 I915_WRITE(DP_A, intel_dp->DP);
1416 POSTING_READ(DP_A);
1417 udelay(200);
1418 }
1419
1420 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1421 {
1422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1423 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1424 struct drm_device *dev = crtc->dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 u32 dpa_ctl;
1427
1428 assert_pipe_disabled(dev_priv,
1429 to_intel_crtc(crtc)->pipe);
1430
1431 dpa_ctl = I915_READ(DP_A);
1432 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1433 "dp pll off, should be on\n");
1434 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1435
1436 /* We can't rely on the value tracked for the DP register in
1437 * intel_dp->DP because link_down must not change that (otherwise link
1438 * re-training will fail. */
1439 dpa_ctl &= ~DP_PLL_ENABLE;
1440 I915_WRITE(DP_A, dpa_ctl);
1441 POSTING_READ(DP_A);
1442 udelay(200);
1443 }
1444
1445 /* If the sink supports it, try to set the power state appropriately */
1446 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1447 {
1448 int ret, i;
1449
1450 /* Should have a valid DPCD by this point */
1451 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1452 return;
1453
1454 if (mode != DRM_MODE_DPMS_ON) {
1455 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1456 DP_SET_POWER_D3);
1457 if (ret != 1)
1458 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1459 } else {
1460 /*
1461 * When turning on, we need to retry for 1ms to give the sink
1462 * time to wake up.
1463 */
1464 for (i = 0; i < 3; i++) {
1465 ret = intel_dp_aux_native_write_1(intel_dp,
1466 DP_SET_POWER,
1467 DP_SET_POWER_D0);
1468 if (ret == 1)
1469 break;
1470 msleep(1);
1471 }
1472 }
1473 }
1474
1475 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1476 enum pipe *pipe)
1477 {
1478 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1479 enum port port = dp_to_dig_port(intel_dp)->port;
1480 struct drm_device *dev = encoder->base.dev;
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 enum intel_display_power_domain power_domain;
1483 u32 tmp;
1484
1485 power_domain = intel_display_port_power_domain(encoder);
1486 if (!intel_display_power_enabled(dev_priv, power_domain))
1487 return false;
1488
1489 tmp = I915_READ(intel_dp->output_reg);
1490
1491 if (!(tmp & DP_PORT_EN))
1492 return false;
1493
1494 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1495 *pipe = PORT_TO_PIPE_CPT(tmp);
1496 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1497 *pipe = PORT_TO_PIPE(tmp);
1498 } else {
1499 u32 trans_sel;
1500 u32 trans_dp;
1501 int i;
1502
1503 switch (intel_dp->output_reg) {
1504 case PCH_DP_B:
1505 trans_sel = TRANS_DP_PORT_SEL_B;
1506 break;
1507 case PCH_DP_C:
1508 trans_sel = TRANS_DP_PORT_SEL_C;
1509 break;
1510 case PCH_DP_D:
1511 trans_sel = TRANS_DP_PORT_SEL_D;
1512 break;
1513 default:
1514 return true;
1515 }
1516
1517 for_each_pipe(i) {
1518 trans_dp = I915_READ(TRANS_DP_CTL(i));
1519 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1520 *pipe = i;
1521 return true;
1522 }
1523 }
1524
1525 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1526 intel_dp->output_reg);
1527 }
1528
1529 return true;
1530 }
1531
1532 static void intel_dp_get_config(struct intel_encoder *encoder,
1533 struct intel_crtc_config *pipe_config)
1534 {
1535 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1536 u32 tmp, flags = 0;
1537 struct drm_device *dev = encoder->base.dev;
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 enum port port = dp_to_dig_port(intel_dp)->port;
1540 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1541 int dotclock;
1542
1543 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1544 tmp = I915_READ(intel_dp->output_reg);
1545 if (tmp & DP_SYNC_HS_HIGH)
1546 flags |= DRM_MODE_FLAG_PHSYNC;
1547 else
1548 flags |= DRM_MODE_FLAG_NHSYNC;
1549
1550 if (tmp & DP_SYNC_VS_HIGH)
1551 flags |= DRM_MODE_FLAG_PVSYNC;
1552 else
1553 flags |= DRM_MODE_FLAG_NVSYNC;
1554 } else {
1555 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1556 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1557 flags |= DRM_MODE_FLAG_PHSYNC;
1558 else
1559 flags |= DRM_MODE_FLAG_NHSYNC;
1560
1561 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1562 flags |= DRM_MODE_FLAG_PVSYNC;
1563 else
1564 flags |= DRM_MODE_FLAG_NVSYNC;
1565 }
1566
1567 pipe_config->adjusted_mode.flags |= flags;
1568
1569 pipe_config->has_dp_encoder = true;
1570
1571 intel_dp_get_m_n(crtc, pipe_config);
1572
1573 if (port == PORT_A) {
1574 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1575 pipe_config->port_clock = 162000;
1576 else
1577 pipe_config->port_clock = 270000;
1578 }
1579
1580 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1581 &pipe_config->dp_m_n);
1582
1583 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1584 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1585
1586 pipe_config->adjusted_mode.crtc_clock = dotclock;
1587
1588 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1589 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1590 /*
1591 * This is a big fat ugly hack.
1592 *
1593 * Some machines in UEFI boot mode provide us a VBT that has 18
1594 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1595 * unknown we fail to light up. Yet the same BIOS boots up with
1596 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1597 * max, not what it tells us to use.
1598 *
1599 * Note: This will still be broken if the eDP panel is not lit
1600 * up by the BIOS, and thus we can't get the mode at module
1601 * load.
1602 */
1603 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1604 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1605 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1606 }
1607 }
1608
1609 static bool is_edp_psr(struct drm_device *dev)
1610 {
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612
1613 return dev_priv->psr.sink_support;
1614 }
1615
1616 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1617 {
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620 if (!HAS_PSR(dev))
1621 return false;
1622
1623 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1624 }
1625
1626 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1627 struct edp_vsc_psr *vsc_psr)
1628 {
1629 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1630 struct drm_device *dev = dig_port->base.base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1633 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1634 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1635 uint32_t *data = (uint32_t *) vsc_psr;
1636 unsigned int i;
1637
1638 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1639 the video DIP being updated before program video DIP data buffer
1640 registers for DIP being updated. */
1641 I915_WRITE(ctl_reg, 0);
1642 POSTING_READ(ctl_reg);
1643
1644 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1645 if (i < sizeof(struct edp_vsc_psr))
1646 I915_WRITE(data_reg + i, *data++);
1647 else
1648 I915_WRITE(data_reg + i, 0);
1649 }
1650
1651 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1652 POSTING_READ(ctl_reg);
1653 }
1654
1655 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1656 {
1657 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659 struct edp_vsc_psr psr_vsc;
1660
1661 if (intel_dp->psr_setup_done)
1662 return;
1663
1664 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1665 memset(&psr_vsc, 0, sizeof(psr_vsc));
1666 psr_vsc.sdp_header.HB0 = 0;
1667 psr_vsc.sdp_header.HB1 = 0x7;
1668 psr_vsc.sdp_header.HB2 = 0x2;
1669 psr_vsc.sdp_header.HB3 = 0x8;
1670 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1671
1672 /* Avoid continuous PSR exit by masking memup and hpd */
1673 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1674 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1675
1676 intel_dp->psr_setup_done = true;
1677 }
1678
1679 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1680 {
1681 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 uint32_t aux_clock_divider;
1684 int precharge = 0x3;
1685 int msg_size = 5; /* Header(4) + Message(1) */
1686
1687 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1688
1689 /* Enable PSR in sink */
1690 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1691 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1692 DP_PSR_ENABLE &
1693 ~DP_PSR_MAIN_LINK_ACTIVE);
1694 else
1695 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1696 DP_PSR_ENABLE |
1697 DP_PSR_MAIN_LINK_ACTIVE);
1698
1699 /* Setup AUX registers */
1700 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1701 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1702 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1703 DP_AUX_CH_CTL_TIME_OUT_400us |
1704 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1705 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1706 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1707 }
1708
1709 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1710 {
1711 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713 uint32_t max_sleep_time = 0x1f;
1714 uint32_t idle_frames = 1;
1715 uint32_t val = 0x0;
1716 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1717
1718 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1719 val |= EDP_PSR_LINK_STANDBY;
1720 val |= EDP_PSR_TP2_TP3_TIME_0us;
1721 val |= EDP_PSR_TP1_TIME_0us;
1722 val |= EDP_PSR_SKIP_AUX_EXIT;
1723 } else
1724 val |= EDP_PSR_LINK_DISABLE;
1725
1726 I915_WRITE(EDP_PSR_CTL(dev), val |
1727 IS_BROADWELL(dev) ? 0 : link_entry_time |
1728 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1729 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1730 EDP_PSR_ENABLE);
1731 }
1732
1733 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1734 {
1735 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1736 struct drm_device *dev = dig_port->base.base.dev;
1737 struct drm_i915_private *dev_priv = dev->dev_private;
1738 struct drm_crtc *crtc = dig_port->base.base.crtc;
1739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1740 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1741 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1742
1743 dev_priv->psr.source_ok = false;
1744
1745 if (!HAS_PSR(dev)) {
1746 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1747 return false;
1748 }
1749
1750 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1751 (dig_port->port != PORT_A)) {
1752 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1753 return false;
1754 }
1755
1756 if (!i915.enable_psr) {
1757 DRM_DEBUG_KMS("PSR disable by flag\n");
1758 return false;
1759 }
1760
1761 crtc = dig_port->base.base.crtc;
1762 if (crtc == NULL) {
1763 DRM_DEBUG_KMS("crtc not active for PSR\n");
1764 return false;
1765 }
1766
1767 intel_crtc = to_intel_crtc(crtc);
1768 if (!intel_crtc_active(crtc)) {
1769 DRM_DEBUG_KMS("crtc not active for PSR\n");
1770 return false;
1771 }
1772
1773 obj = to_intel_framebuffer(crtc->fb)->obj;
1774 if (obj->tiling_mode != I915_TILING_X ||
1775 obj->fence_reg == I915_FENCE_REG_NONE) {
1776 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1777 return false;
1778 }
1779
1780 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1781 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1782 return false;
1783 }
1784
1785 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1786 S3D_ENABLE) {
1787 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1788 return false;
1789 }
1790
1791 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1792 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1793 return false;
1794 }
1795
1796 dev_priv->psr.source_ok = true;
1797 return true;
1798 }
1799
1800 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1801 {
1802 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1803
1804 if (!intel_edp_psr_match_conditions(intel_dp) ||
1805 intel_edp_is_psr_enabled(dev))
1806 return;
1807
1808 /* Setup PSR once */
1809 intel_edp_psr_setup(intel_dp);
1810
1811 /* Enable PSR on the panel */
1812 intel_edp_psr_enable_sink(intel_dp);
1813
1814 /* Enable PSR on the host */
1815 intel_edp_psr_enable_source(intel_dp);
1816 }
1817
1818 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1819 {
1820 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1821
1822 if (intel_edp_psr_match_conditions(intel_dp) &&
1823 !intel_edp_is_psr_enabled(dev))
1824 intel_edp_psr_do_enable(intel_dp);
1825 }
1826
1827 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1828 {
1829 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831
1832 if (!intel_edp_is_psr_enabled(dev))
1833 return;
1834
1835 I915_WRITE(EDP_PSR_CTL(dev),
1836 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1837
1838 /* Wait till PSR is idle */
1839 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1840 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1841 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1842 }
1843
1844 void intel_edp_psr_update(struct drm_device *dev)
1845 {
1846 struct intel_encoder *encoder;
1847 struct intel_dp *intel_dp = NULL;
1848
1849 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1850 if (encoder->type == INTEL_OUTPUT_EDP) {
1851 intel_dp = enc_to_intel_dp(&encoder->base);
1852
1853 if (!is_edp_psr(dev))
1854 return;
1855
1856 if (!intel_edp_psr_match_conditions(intel_dp))
1857 intel_edp_psr_disable(intel_dp);
1858 else
1859 if (!intel_edp_is_psr_enabled(dev))
1860 intel_edp_psr_do_enable(intel_dp);
1861 }
1862 }
1863
1864 static void intel_disable_dp(struct intel_encoder *encoder)
1865 {
1866 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1867 enum port port = dp_to_dig_port(intel_dp)->port;
1868 struct drm_device *dev = encoder->base.dev;
1869
1870 /* Make sure the panel is off before trying to change the mode. But also
1871 * ensure that we have vdd while we switch off the panel. */
1872 edp_panel_vdd_on(intel_dp);
1873 intel_edp_backlight_off(intel_dp);
1874 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1875 intel_edp_panel_off(intel_dp);
1876 edp_panel_vdd_off(intel_dp, true);
1877
1878 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1879 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1880 intel_dp_link_down(intel_dp);
1881 }
1882
1883 static void intel_post_disable_dp(struct intel_encoder *encoder)
1884 {
1885 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1886 enum port port = dp_to_dig_port(intel_dp)->port;
1887 struct drm_device *dev = encoder->base.dev;
1888
1889 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1890 intel_dp_link_down(intel_dp);
1891 if (!IS_VALLEYVIEW(dev))
1892 ironlake_edp_pll_off(intel_dp);
1893 }
1894 }
1895
1896 static void intel_enable_dp(struct intel_encoder *encoder)
1897 {
1898 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1899 struct drm_device *dev = encoder->base.dev;
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1902
1903 if (WARN_ON(dp_reg & DP_PORT_EN))
1904 return;
1905
1906 edp_panel_vdd_on(intel_dp);
1907 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1908 intel_dp_start_link_train(intel_dp);
1909 intel_edp_panel_on(intel_dp);
1910 edp_panel_vdd_off(intel_dp, true);
1911 intel_dp_complete_link_train(intel_dp);
1912 intel_dp_stop_link_train(intel_dp);
1913 }
1914
1915 static void g4x_enable_dp(struct intel_encoder *encoder)
1916 {
1917 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1918
1919 intel_enable_dp(encoder);
1920 intel_edp_backlight_on(intel_dp);
1921 }
1922
1923 static void vlv_enable_dp(struct intel_encoder *encoder)
1924 {
1925 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1926
1927 intel_edp_backlight_on(intel_dp);
1928 }
1929
1930 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1931 {
1932 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1933 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1934
1935 if (dport->port == PORT_A)
1936 ironlake_edp_pll_on(intel_dp);
1937 }
1938
1939 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1940 {
1941 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1942 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1943 struct drm_device *dev = encoder->base.dev;
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1946 enum dpio_channel port = vlv_dport_to_channel(dport);
1947 int pipe = intel_crtc->pipe;
1948 struct edp_power_seq power_seq;
1949 u32 val;
1950
1951 mutex_lock(&dev_priv->dpio_lock);
1952
1953 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1954 val = 0;
1955 if (pipe)
1956 val |= (1<<21);
1957 else
1958 val &= ~(1<<21);
1959 val |= 0x001000c4;
1960 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1961 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1962 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1963
1964 mutex_unlock(&dev_priv->dpio_lock);
1965
1966 /* init power sequencer on this pipe and port */
1967 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1968 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1969 &power_seq);
1970
1971 intel_enable_dp(encoder);
1972
1973 vlv_wait_port_ready(dev_priv, dport);
1974 }
1975
1976 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1977 {
1978 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1979 struct drm_device *dev = encoder->base.dev;
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1981 struct intel_crtc *intel_crtc =
1982 to_intel_crtc(encoder->base.crtc);
1983 enum dpio_channel port = vlv_dport_to_channel(dport);
1984 int pipe = intel_crtc->pipe;
1985
1986 /* Program Tx lane resets to default */
1987 mutex_lock(&dev_priv->dpio_lock);
1988 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1989 DPIO_PCS_TX_LANE2_RESET |
1990 DPIO_PCS_TX_LANE1_RESET);
1991 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1992 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1993 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1994 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1995 DPIO_PCS_CLK_SOFT_RESET);
1996
1997 /* Fix up inter-pair skew failure */
1998 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2000 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2001 mutex_unlock(&dev_priv->dpio_lock);
2002 }
2003
2004 /*
2005 * Native read with retry for link status and receiver capability reads for
2006 * cases where the sink may still be asleep.
2007 */
2008 static bool
2009 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2010 uint8_t *recv, int recv_bytes)
2011 {
2012 int ret, i;
2013
2014 /*
2015 * Sinks are *supposed* to come up within 1ms from an off state,
2016 * but we're also supposed to retry 3 times per the spec.
2017 */
2018 for (i = 0; i < 3; i++) {
2019 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2020 recv_bytes);
2021 if (ret == recv_bytes)
2022 return true;
2023 msleep(1);
2024 }
2025
2026 return false;
2027 }
2028
2029 /*
2030 * Fetch AUX CH registers 0x202 - 0x207 which contain
2031 * link status information
2032 */
2033 static bool
2034 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2035 {
2036 return intel_dp_aux_native_read_retry(intel_dp,
2037 DP_LANE0_1_STATUS,
2038 link_status,
2039 DP_LINK_STATUS_SIZE);
2040 }
2041
2042 /*
2043 * These are source-specific values; current Intel hardware supports
2044 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2045 */
2046
2047 static uint8_t
2048 intel_dp_voltage_max(struct intel_dp *intel_dp)
2049 {
2050 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2051 enum port port = dp_to_dig_port(intel_dp)->port;
2052
2053 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2054 return DP_TRAIN_VOLTAGE_SWING_1200;
2055 else if (IS_GEN7(dev) && port == PORT_A)
2056 return DP_TRAIN_VOLTAGE_SWING_800;
2057 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2058 return DP_TRAIN_VOLTAGE_SWING_1200;
2059 else
2060 return DP_TRAIN_VOLTAGE_SWING_800;
2061 }
2062
2063 static uint8_t
2064 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2065 {
2066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2067 enum port port = dp_to_dig_port(intel_dp)->port;
2068
2069 if (IS_BROADWELL(dev)) {
2070 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2071 case DP_TRAIN_VOLTAGE_SWING_400:
2072 case DP_TRAIN_VOLTAGE_SWING_600:
2073 return DP_TRAIN_PRE_EMPHASIS_6;
2074 case DP_TRAIN_VOLTAGE_SWING_800:
2075 return DP_TRAIN_PRE_EMPHASIS_3_5;
2076 case DP_TRAIN_VOLTAGE_SWING_1200:
2077 default:
2078 return DP_TRAIN_PRE_EMPHASIS_0;
2079 }
2080 } else if (IS_HASWELL(dev)) {
2081 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2082 case DP_TRAIN_VOLTAGE_SWING_400:
2083 return DP_TRAIN_PRE_EMPHASIS_9_5;
2084 case DP_TRAIN_VOLTAGE_SWING_600:
2085 return DP_TRAIN_PRE_EMPHASIS_6;
2086 case DP_TRAIN_VOLTAGE_SWING_800:
2087 return DP_TRAIN_PRE_EMPHASIS_3_5;
2088 case DP_TRAIN_VOLTAGE_SWING_1200:
2089 default:
2090 return DP_TRAIN_PRE_EMPHASIS_0;
2091 }
2092 } else if (IS_VALLEYVIEW(dev)) {
2093 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2094 case DP_TRAIN_VOLTAGE_SWING_400:
2095 return DP_TRAIN_PRE_EMPHASIS_9_5;
2096 case DP_TRAIN_VOLTAGE_SWING_600:
2097 return DP_TRAIN_PRE_EMPHASIS_6;
2098 case DP_TRAIN_VOLTAGE_SWING_800:
2099 return DP_TRAIN_PRE_EMPHASIS_3_5;
2100 case DP_TRAIN_VOLTAGE_SWING_1200:
2101 default:
2102 return DP_TRAIN_PRE_EMPHASIS_0;
2103 }
2104 } else if (IS_GEN7(dev) && port == PORT_A) {
2105 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2106 case DP_TRAIN_VOLTAGE_SWING_400:
2107 return DP_TRAIN_PRE_EMPHASIS_6;
2108 case DP_TRAIN_VOLTAGE_SWING_600:
2109 case DP_TRAIN_VOLTAGE_SWING_800:
2110 return DP_TRAIN_PRE_EMPHASIS_3_5;
2111 default:
2112 return DP_TRAIN_PRE_EMPHASIS_0;
2113 }
2114 } else {
2115 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2116 case DP_TRAIN_VOLTAGE_SWING_400:
2117 return DP_TRAIN_PRE_EMPHASIS_6;
2118 case DP_TRAIN_VOLTAGE_SWING_600:
2119 return DP_TRAIN_PRE_EMPHASIS_6;
2120 case DP_TRAIN_VOLTAGE_SWING_800:
2121 return DP_TRAIN_PRE_EMPHASIS_3_5;
2122 case DP_TRAIN_VOLTAGE_SWING_1200:
2123 default:
2124 return DP_TRAIN_PRE_EMPHASIS_0;
2125 }
2126 }
2127 }
2128
2129 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2130 {
2131 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2134 struct intel_crtc *intel_crtc =
2135 to_intel_crtc(dport->base.base.crtc);
2136 unsigned long demph_reg_value, preemph_reg_value,
2137 uniqtranscale_reg_value;
2138 uint8_t train_set = intel_dp->train_set[0];
2139 enum dpio_channel port = vlv_dport_to_channel(dport);
2140 int pipe = intel_crtc->pipe;
2141
2142 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2143 case DP_TRAIN_PRE_EMPHASIS_0:
2144 preemph_reg_value = 0x0004000;
2145 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2146 case DP_TRAIN_VOLTAGE_SWING_400:
2147 demph_reg_value = 0x2B405555;
2148 uniqtranscale_reg_value = 0x552AB83A;
2149 break;
2150 case DP_TRAIN_VOLTAGE_SWING_600:
2151 demph_reg_value = 0x2B404040;
2152 uniqtranscale_reg_value = 0x5548B83A;
2153 break;
2154 case DP_TRAIN_VOLTAGE_SWING_800:
2155 demph_reg_value = 0x2B245555;
2156 uniqtranscale_reg_value = 0x5560B83A;
2157 break;
2158 case DP_TRAIN_VOLTAGE_SWING_1200:
2159 demph_reg_value = 0x2B405555;
2160 uniqtranscale_reg_value = 0x5598DA3A;
2161 break;
2162 default:
2163 return 0;
2164 }
2165 break;
2166 case DP_TRAIN_PRE_EMPHASIS_3_5:
2167 preemph_reg_value = 0x0002000;
2168 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2169 case DP_TRAIN_VOLTAGE_SWING_400:
2170 demph_reg_value = 0x2B404040;
2171 uniqtranscale_reg_value = 0x5552B83A;
2172 break;
2173 case DP_TRAIN_VOLTAGE_SWING_600:
2174 demph_reg_value = 0x2B404848;
2175 uniqtranscale_reg_value = 0x5580B83A;
2176 break;
2177 case DP_TRAIN_VOLTAGE_SWING_800:
2178 demph_reg_value = 0x2B404040;
2179 uniqtranscale_reg_value = 0x55ADDA3A;
2180 break;
2181 default:
2182 return 0;
2183 }
2184 break;
2185 case DP_TRAIN_PRE_EMPHASIS_6:
2186 preemph_reg_value = 0x0000000;
2187 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2188 case DP_TRAIN_VOLTAGE_SWING_400:
2189 demph_reg_value = 0x2B305555;
2190 uniqtranscale_reg_value = 0x5570B83A;
2191 break;
2192 case DP_TRAIN_VOLTAGE_SWING_600:
2193 demph_reg_value = 0x2B2B4040;
2194 uniqtranscale_reg_value = 0x55ADDA3A;
2195 break;
2196 default:
2197 return 0;
2198 }
2199 break;
2200 case DP_TRAIN_PRE_EMPHASIS_9_5:
2201 preemph_reg_value = 0x0006000;
2202 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2203 case DP_TRAIN_VOLTAGE_SWING_400:
2204 demph_reg_value = 0x1B405555;
2205 uniqtranscale_reg_value = 0x55ADDA3A;
2206 break;
2207 default:
2208 return 0;
2209 }
2210 break;
2211 default:
2212 return 0;
2213 }
2214
2215 mutex_lock(&dev_priv->dpio_lock);
2216 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2217 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2218 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2219 uniqtranscale_reg_value);
2220 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2221 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2222 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2223 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2224 mutex_unlock(&dev_priv->dpio_lock);
2225
2226 return 0;
2227 }
2228
2229 static void
2230 intel_get_adjust_train(struct intel_dp *intel_dp,
2231 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2232 {
2233 uint8_t v = 0;
2234 uint8_t p = 0;
2235 int lane;
2236 uint8_t voltage_max;
2237 uint8_t preemph_max;
2238
2239 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2240 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2241 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2242
2243 if (this_v > v)
2244 v = this_v;
2245 if (this_p > p)
2246 p = this_p;
2247 }
2248
2249 voltage_max = intel_dp_voltage_max(intel_dp);
2250 if (v >= voltage_max)
2251 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2252
2253 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2254 if (p >= preemph_max)
2255 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2256
2257 for (lane = 0; lane < 4; lane++)
2258 intel_dp->train_set[lane] = v | p;
2259 }
2260
2261 static uint32_t
2262 intel_gen4_signal_levels(uint8_t train_set)
2263 {
2264 uint32_t signal_levels = 0;
2265
2266 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2267 case DP_TRAIN_VOLTAGE_SWING_400:
2268 default:
2269 signal_levels |= DP_VOLTAGE_0_4;
2270 break;
2271 case DP_TRAIN_VOLTAGE_SWING_600:
2272 signal_levels |= DP_VOLTAGE_0_6;
2273 break;
2274 case DP_TRAIN_VOLTAGE_SWING_800:
2275 signal_levels |= DP_VOLTAGE_0_8;
2276 break;
2277 case DP_TRAIN_VOLTAGE_SWING_1200:
2278 signal_levels |= DP_VOLTAGE_1_2;
2279 break;
2280 }
2281 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2282 case DP_TRAIN_PRE_EMPHASIS_0:
2283 default:
2284 signal_levels |= DP_PRE_EMPHASIS_0;
2285 break;
2286 case DP_TRAIN_PRE_EMPHASIS_3_5:
2287 signal_levels |= DP_PRE_EMPHASIS_3_5;
2288 break;
2289 case DP_TRAIN_PRE_EMPHASIS_6:
2290 signal_levels |= DP_PRE_EMPHASIS_6;
2291 break;
2292 case DP_TRAIN_PRE_EMPHASIS_9_5:
2293 signal_levels |= DP_PRE_EMPHASIS_9_5;
2294 break;
2295 }
2296 return signal_levels;
2297 }
2298
2299 /* Gen6's DP voltage swing and pre-emphasis control */
2300 static uint32_t
2301 intel_gen6_edp_signal_levels(uint8_t train_set)
2302 {
2303 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2304 DP_TRAIN_PRE_EMPHASIS_MASK);
2305 switch (signal_levels) {
2306 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2307 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2308 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2309 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2310 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2311 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2312 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2313 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2314 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2315 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2316 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2317 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2318 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2319 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2320 default:
2321 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2322 "0x%x\n", signal_levels);
2323 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2324 }
2325 }
2326
2327 /* Gen7's DP voltage swing and pre-emphasis control */
2328 static uint32_t
2329 intel_gen7_edp_signal_levels(uint8_t train_set)
2330 {
2331 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2332 DP_TRAIN_PRE_EMPHASIS_MASK);
2333 switch (signal_levels) {
2334 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2335 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2336 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2337 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2338 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2339 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2340
2341 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2342 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2343 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2344 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2345
2346 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2347 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2348 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2349 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2350
2351 default:
2352 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2353 "0x%x\n", signal_levels);
2354 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2355 }
2356 }
2357
2358 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2359 static uint32_t
2360 intel_hsw_signal_levels(uint8_t train_set)
2361 {
2362 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2363 DP_TRAIN_PRE_EMPHASIS_MASK);
2364 switch (signal_levels) {
2365 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2366 return DDI_BUF_EMP_400MV_0DB_HSW;
2367 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2368 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2369 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2370 return DDI_BUF_EMP_400MV_6DB_HSW;
2371 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2372 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2373
2374 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2375 return DDI_BUF_EMP_600MV_0DB_HSW;
2376 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2377 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2378 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2379 return DDI_BUF_EMP_600MV_6DB_HSW;
2380
2381 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2382 return DDI_BUF_EMP_800MV_0DB_HSW;
2383 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2384 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2385 default:
2386 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2387 "0x%x\n", signal_levels);
2388 return DDI_BUF_EMP_400MV_0DB_HSW;
2389 }
2390 }
2391
2392 static uint32_t
2393 intel_bdw_signal_levels(uint8_t train_set)
2394 {
2395 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2396 DP_TRAIN_PRE_EMPHASIS_MASK);
2397 switch (signal_levels) {
2398 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2399 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2400 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2401 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2402 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2403 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2404
2405 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2406 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2407 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2408 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2409 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2410 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2411
2412 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2413 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2414 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2415 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2416
2417 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2418 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2419
2420 default:
2421 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2422 "0x%x\n", signal_levels);
2423 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2424 }
2425 }
2426
2427 /* Properly updates "DP" with the correct signal levels. */
2428 static void
2429 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2430 {
2431 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2432 enum port port = intel_dig_port->port;
2433 struct drm_device *dev = intel_dig_port->base.base.dev;
2434 uint32_t signal_levels, mask;
2435 uint8_t train_set = intel_dp->train_set[0];
2436
2437 if (IS_BROADWELL(dev)) {
2438 signal_levels = intel_bdw_signal_levels(train_set);
2439 mask = DDI_BUF_EMP_MASK;
2440 } else if (IS_HASWELL(dev)) {
2441 signal_levels = intel_hsw_signal_levels(train_set);
2442 mask = DDI_BUF_EMP_MASK;
2443 } else if (IS_VALLEYVIEW(dev)) {
2444 signal_levels = intel_vlv_signal_levels(intel_dp);
2445 mask = 0;
2446 } else if (IS_GEN7(dev) && port == PORT_A) {
2447 signal_levels = intel_gen7_edp_signal_levels(train_set);
2448 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2449 } else if (IS_GEN6(dev) && port == PORT_A) {
2450 signal_levels = intel_gen6_edp_signal_levels(train_set);
2451 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2452 } else {
2453 signal_levels = intel_gen4_signal_levels(train_set);
2454 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2455 }
2456
2457 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2458
2459 *DP = (*DP & ~mask) | signal_levels;
2460 }
2461
2462 static bool
2463 intel_dp_set_link_train(struct intel_dp *intel_dp,
2464 uint32_t *DP,
2465 uint8_t dp_train_pat)
2466 {
2467 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2468 struct drm_device *dev = intel_dig_port->base.base.dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 enum port port = intel_dig_port->port;
2471 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2472 int ret, len;
2473
2474 if (HAS_DDI(dev)) {
2475 uint32_t temp = I915_READ(DP_TP_CTL(port));
2476
2477 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2478 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2479 else
2480 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2481
2482 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2483 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2484 case DP_TRAINING_PATTERN_DISABLE:
2485 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2486
2487 break;
2488 case DP_TRAINING_PATTERN_1:
2489 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2490 break;
2491 case DP_TRAINING_PATTERN_2:
2492 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2493 break;
2494 case DP_TRAINING_PATTERN_3:
2495 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2496 break;
2497 }
2498 I915_WRITE(DP_TP_CTL(port), temp);
2499
2500 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2501 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2502
2503 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2504 case DP_TRAINING_PATTERN_DISABLE:
2505 *DP |= DP_LINK_TRAIN_OFF_CPT;
2506 break;
2507 case DP_TRAINING_PATTERN_1:
2508 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2509 break;
2510 case DP_TRAINING_PATTERN_2:
2511 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2512 break;
2513 case DP_TRAINING_PATTERN_3:
2514 DRM_ERROR("DP training pattern 3 not supported\n");
2515 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2516 break;
2517 }
2518
2519 } else {
2520 *DP &= ~DP_LINK_TRAIN_MASK;
2521
2522 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2523 case DP_TRAINING_PATTERN_DISABLE:
2524 *DP |= DP_LINK_TRAIN_OFF;
2525 break;
2526 case DP_TRAINING_PATTERN_1:
2527 *DP |= DP_LINK_TRAIN_PAT_1;
2528 break;
2529 case DP_TRAINING_PATTERN_2:
2530 *DP |= DP_LINK_TRAIN_PAT_2;
2531 break;
2532 case DP_TRAINING_PATTERN_3:
2533 DRM_ERROR("DP training pattern 3 not supported\n");
2534 *DP |= DP_LINK_TRAIN_PAT_2;
2535 break;
2536 }
2537 }
2538
2539 I915_WRITE(intel_dp->output_reg, *DP);
2540 POSTING_READ(intel_dp->output_reg);
2541
2542 buf[0] = dp_train_pat;
2543 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2544 DP_TRAINING_PATTERN_DISABLE) {
2545 /* don't write DP_TRAINING_LANEx_SET on disable */
2546 len = 1;
2547 } else {
2548 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2549 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2550 len = intel_dp->lane_count + 1;
2551 }
2552
2553 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2554 buf, len);
2555
2556 return ret == len;
2557 }
2558
2559 static bool
2560 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2561 uint8_t dp_train_pat)
2562 {
2563 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2564 intel_dp_set_signal_levels(intel_dp, DP);
2565 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2566 }
2567
2568 static bool
2569 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2570 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2571 {
2572 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2573 struct drm_device *dev = intel_dig_port->base.base.dev;
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575 int ret;
2576
2577 intel_get_adjust_train(intel_dp, link_status);
2578 intel_dp_set_signal_levels(intel_dp, DP);
2579
2580 I915_WRITE(intel_dp->output_reg, *DP);
2581 POSTING_READ(intel_dp->output_reg);
2582
2583 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2584 intel_dp->train_set,
2585 intel_dp->lane_count);
2586
2587 return ret == intel_dp->lane_count;
2588 }
2589
2590 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2591 {
2592 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2593 struct drm_device *dev = intel_dig_port->base.base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 enum port port = intel_dig_port->port;
2596 uint32_t val;
2597
2598 if (!HAS_DDI(dev))
2599 return;
2600
2601 val = I915_READ(DP_TP_CTL(port));
2602 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2603 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2604 I915_WRITE(DP_TP_CTL(port), val);
2605
2606 /*
2607 * On PORT_A we can have only eDP in SST mode. There the only reason
2608 * we need to set idle transmission mode is to work around a HW issue
2609 * where we enable the pipe while not in idle link-training mode.
2610 * In this case there is requirement to wait for a minimum number of
2611 * idle patterns to be sent.
2612 */
2613 if (port == PORT_A)
2614 return;
2615
2616 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2617 1))
2618 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2619 }
2620
2621 /* Enable corresponding port and start training pattern 1 */
2622 void
2623 intel_dp_start_link_train(struct intel_dp *intel_dp)
2624 {
2625 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2626 struct drm_device *dev = encoder->dev;
2627 int i;
2628 uint8_t voltage;
2629 int voltage_tries, loop_tries;
2630 uint32_t DP = intel_dp->DP;
2631 uint8_t link_config[2];
2632
2633 if (HAS_DDI(dev))
2634 intel_ddi_prepare_link_retrain(encoder);
2635
2636 /* Write the link configuration data */
2637 link_config[0] = intel_dp->link_bw;
2638 link_config[1] = intel_dp->lane_count;
2639 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2640 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2641 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2642
2643 link_config[0] = 0;
2644 link_config[1] = DP_SET_ANSI_8B10B;
2645 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2646
2647 DP |= DP_PORT_EN;
2648
2649 /* clock recovery */
2650 if (!intel_dp_reset_link_train(intel_dp, &DP,
2651 DP_TRAINING_PATTERN_1 |
2652 DP_LINK_SCRAMBLING_DISABLE)) {
2653 DRM_ERROR("failed to enable link training\n");
2654 return;
2655 }
2656
2657 voltage = 0xff;
2658 voltage_tries = 0;
2659 loop_tries = 0;
2660 for (;;) {
2661 uint8_t link_status[DP_LINK_STATUS_SIZE];
2662
2663 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2664 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2665 DRM_ERROR("failed to get link status\n");
2666 break;
2667 }
2668
2669 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2670 DRM_DEBUG_KMS("clock recovery OK\n");
2671 break;
2672 }
2673
2674 /* Check to see if we've tried the max voltage */
2675 for (i = 0; i < intel_dp->lane_count; i++)
2676 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2677 break;
2678 if (i == intel_dp->lane_count) {
2679 ++loop_tries;
2680 if (loop_tries == 5) {
2681 DRM_ERROR("too many full retries, give up\n");
2682 break;
2683 }
2684 intel_dp_reset_link_train(intel_dp, &DP,
2685 DP_TRAINING_PATTERN_1 |
2686 DP_LINK_SCRAMBLING_DISABLE);
2687 voltage_tries = 0;
2688 continue;
2689 }
2690
2691 /* Check to see if we've tried the same voltage 5 times */
2692 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2693 ++voltage_tries;
2694 if (voltage_tries == 5) {
2695 DRM_ERROR("too many voltage retries, give up\n");
2696 break;
2697 }
2698 } else
2699 voltage_tries = 0;
2700 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2701
2702 /* Update training set as requested by target */
2703 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2704 DRM_ERROR("failed to update link training\n");
2705 break;
2706 }
2707 }
2708
2709 intel_dp->DP = DP;
2710 }
2711
2712 void
2713 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2714 {
2715 bool channel_eq = false;
2716 int tries, cr_tries;
2717 uint32_t DP = intel_dp->DP;
2718 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2719
2720 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2721 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2722 training_pattern = DP_TRAINING_PATTERN_3;
2723
2724 /* channel equalization */
2725 if (!intel_dp_set_link_train(intel_dp, &DP,
2726 training_pattern |
2727 DP_LINK_SCRAMBLING_DISABLE)) {
2728 DRM_ERROR("failed to start channel equalization\n");
2729 return;
2730 }
2731
2732 tries = 0;
2733 cr_tries = 0;
2734 channel_eq = false;
2735 for (;;) {
2736 uint8_t link_status[DP_LINK_STATUS_SIZE];
2737
2738 if (cr_tries > 5) {
2739 DRM_ERROR("failed to train DP, aborting\n");
2740 break;
2741 }
2742
2743 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2744 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2745 DRM_ERROR("failed to get link status\n");
2746 break;
2747 }
2748
2749 /* Make sure clock is still ok */
2750 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2751 intel_dp_start_link_train(intel_dp);
2752 intel_dp_set_link_train(intel_dp, &DP,
2753 training_pattern |
2754 DP_LINK_SCRAMBLING_DISABLE);
2755 cr_tries++;
2756 continue;
2757 }
2758
2759 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2760 channel_eq = true;
2761 break;
2762 }
2763
2764 /* Try 5 times, then try clock recovery if that fails */
2765 if (tries > 5) {
2766 intel_dp_link_down(intel_dp);
2767 intel_dp_start_link_train(intel_dp);
2768 intel_dp_set_link_train(intel_dp, &DP,
2769 training_pattern |
2770 DP_LINK_SCRAMBLING_DISABLE);
2771 tries = 0;
2772 cr_tries++;
2773 continue;
2774 }
2775
2776 /* Update training set as requested by target */
2777 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2778 DRM_ERROR("failed to update link training\n");
2779 break;
2780 }
2781 ++tries;
2782 }
2783
2784 intel_dp_set_idle_link_train(intel_dp);
2785
2786 intel_dp->DP = DP;
2787
2788 if (channel_eq)
2789 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2790
2791 }
2792
2793 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2794 {
2795 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2796 DP_TRAINING_PATTERN_DISABLE);
2797 }
2798
2799 static void
2800 intel_dp_link_down(struct intel_dp *intel_dp)
2801 {
2802 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2803 enum port port = intel_dig_port->port;
2804 struct drm_device *dev = intel_dig_port->base.base.dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc =
2807 to_intel_crtc(intel_dig_port->base.base.crtc);
2808 uint32_t DP = intel_dp->DP;
2809
2810 /*
2811 * DDI code has a strict mode set sequence and we should try to respect
2812 * it, otherwise we might hang the machine in many different ways. So we
2813 * really should be disabling the port only on a complete crtc_disable
2814 * sequence. This function is just called under two conditions on DDI
2815 * code:
2816 * - Link train failed while doing crtc_enable, and on this case we
2817 * really should respect the mode set sequence and wait for a
2818 * crtc_disable.
2819 * - Someone turned the monitor off and intel_dp_check_link_status
2820 * called us. We don't need to disable the whole port on this case, so
2821 * when someone turns the monitor on again,
2822 * intel_ddi_prepare_link_retrain will take care of redoing the link
2823 * train.
2824 */
2825 if (HAS_DDI(dev))
2826 return;
2827
2828 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2829 return;
2830
2831 DRM_DEBUG_KMS("\n");
2832
2833 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2834 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2835 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2836 } else {
2837 DP &= ~DP_LINK_TRAIN_MASK;
2838 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2839 }
2840 POSTING_READ(intel_dp->output_reg);
2841
2842 /* We don't really know why we're doing this */
2843 intel_wait_for_vblank(dev, intel_crtc->pipe);
2844
2845 if (HAS_PCH_IBX(dev) &&
2846 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2847 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2848
2849 /* Hardware workaround: leaving our transcoder select
2850 * set to transcoder B while it's off will prevent the
2851 * corresponding HDMI output on transcoder A.
2852 *
2853 * Combine this with another hardware workaround:
2854 * transcoder select bit can only be cleared while the
2855 * port is enabled.
2856 */
2857 DP &= ~DP_PIPEB_SELECT;
2858 I915_WRITE(intel_dp->output_reg, DP);
2859
2860 /* Changes to enable or select take place the vblank
2861 * after being written.
2862 */
2863 if (WARN_ON(crtc == NULL)) {
2864 /* We should never try to disable a port without a crtc
2865 * attached. For paranoia keep the code around for a
2866 * bit. */
2867 POSTING_READ(intel_dp->output_reg);
2868 msleep(50);
2869 } else
2870 intel_wait_for_vblank(dev, intel_crtc->pipe);
2871 }
2872
2873 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2874 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2875 POSTING_READ(intel_dp->output_reg);
2876 msleep(intel_dp->panel_power_down_delay);
2877 }
2878
2879 static bool
2880 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2881 {
2882 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2883 struct drm_device *dev = dig_port->base.base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885
2886 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2887
2888 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2889 sizeof(intel_dp->dpcd)) == 0)
2890 return false; /* aux transfer failed */
2891
2892 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2893 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2894 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2895
2896 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2897 return false; /* DPCD not present */
2898
2899 /* Check if the panel supports PSR */
2900 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2901 if (is_edp(intel_dp)) {
2902 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2903 intel_dp->psr_dpcd,
2904 sizeof(intel_dp->psr_dpcd));
2905 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2906 dev_priv->psr.sink_support = true;
2907 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2908 }
2909 }
2910
2911 /* Training Pattern 3 support */
2912 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2913 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2914 intel_dp->use_tps3 = true;
2915 DRM_DEBUG_KMS("Displayport TPS3 supported");
2916 } else
2917 intel_dp->use_tps3 = false;
2918
2919 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2920 DP_DWN_STRM_PORT_PRESENT))
2921 return true; /* native DP sink */
2922
2923 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2924 return true; /* no per-port downstream info */
2925
2926 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2927 intel_dp->downstream_ports,
2928 DP_MAX_DOWNSTREAM_PORTS) == 0)
2929 return false; /* downstream port status fetch failed */
2930
2931 return true;
2932 }
2933
2934 static void
2935 intel_dp_probe_oui(struct intel_dp *intel_dp)
2936 {
2937 u8 buf[3];
2938
2939 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2940 return;
2941
2942 edp_panel_vdd_on(intel_dp);
2943
2944 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2945 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2946 buf[0], buf[1], buf[2]);
2947
2948 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2949 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2950 buf[0], buf[1], buf[2]);
2951
2952 edp_panel_vdd_off(intel_dp, false);
2953 }
2954
2955 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2956 {
2957 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2958 struct drm_device *dev = intel_dig_port->base.base.dev;
2959 struct intel_crtc *intel_crtc =
2960 to_intel_crtc(intel_dig_port->base.base.crtc);
2961 u8 buf[1];
2962
2963 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2964 return -EAGAIN;
2965
2966 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2967 return -ENOTTY;
2968
2969 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2970 DP_TEST_SINK_START))
2971 return -EAGAIN;
2972
2973 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2974 intel_wait_for_vblank(dev, intel_crtc->pipe);
2975 intel_wait_for_vblank(dev, intel_crtc->pipe);
2976
2977 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2978 return -EAGAIN;
2979
2980 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2981 return 0;
2982 }
2983
2984 static bool
2985 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2986 {
2987 int ret;
2988
2989 ret = intel_dp_aux_native_read_retry(intel_dp,
2990 DP_DEVICE_SERVICE_IRQ_VECTOR,
2991 sink_irq_vector, 1);
2992 if (!ret)
2993 return false;
2994
2995 return true;
2996 }
2997
2998 static void
2999 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3000 {
3001 /* NAK by default */
3002 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
3003 }
3004
3005 /*
3006 * According to DP spec
3007 * 5.1.2:
3008 * 1. Read DPCD
3009 * 2. Configure link according to Receiver Capabilities
3010 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3011 * 4. Check link status on receipt of hot-plug interrupt
3012 */
3013
3014 void
3015 intel_dp_check_link_status(struct intel_dp *intel_dp)
3016 {
3017 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3018 u8 sink_irq_vector;
3019 u8 link_status[DP_LINK_STATUS_SIZE];
3020
3021 if (!intel_encoder->connectors_active)
3022 return;
3023
3024 if (WARN_ON(!intel_encoder->base.crtc))
3025 return;
3026
3027 /* Try to read receiver status if the link appears to be up */
3028 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3029 return;
3030 }
3031
3032 /* Now read the DPCD to see if it's actually running */
3033 if (!intel_dp_get_dpcd(intel_dp)) {
3034 return;
3035 }
3036
3037 /* Try to read the source of the interrupt */
3038 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3039 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3040 /* Clear interrupt source */
3041 intel_dp_aux_native_write_1(intel_dp,
3042 DP_DEVICE_SERVICE_IRQ_VECTOR,
3043 sink_irq_vector);
3044
3045 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3046 intel_dp_handle_test_request(intel_dp);
3047 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3048 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3049 }
3050
3051 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3052 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3053 drm_get_encoder_name(&intel_encoder->base));
3054 intel_dp_start_link_train(intel_dp);
3055 intel_dp_complete_link_train(intel_dp);
3056 intel_dp_stop_link_train(intel_dp);
3057 }
3058 }
3059
3060 /* XXX this is probably wrong for multiple downstream ports */
3061 static enum drm_connector_status
3062 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3063 {
3064 uint8_t *dpcd = intel_dp->dpcd;
3065 uint8_t type;
3066
3067 if (!intel_dp_get_dpcd(intel_dp))
3068 return connector_status_disconnected;
3069
3070 /* if there's no downstream port, we're done */
3071 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3072 return connector_status_connected;
3073
3074 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3076 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3077 uint8_t reg;
3078 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
3079 &reg, 1))
3080 return connector_status_unknown;
3081 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3082 : connector_status_disconnected;
3083 }
3084
3085 /* If no HPD, poke DDC gently */
3086 if (drm_probe_ddc(&intel_dp->adapter))
3087 return connector_status_connected;
3088
3089 /* Well we tried, say unknown for unreliable port types */
3090 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3091 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3092 if (type == DP_DS_PORT_TYPE_VGA ||
3093 type == DP_DS_PORT_TYPE_NON_EDID)
3094 return connector_status_unknown;
3095 } else {
3096 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3097 DP_DWN_STRM_PORT_TYPE_MASK;
3098 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3099 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3100 return connector_status_unknown;
3101 }
3102
3103 /* Anything else is out of spec, warn and ignore */
3104 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3105 return connector_status_disconnected;
3106 }
3107
3108 static enum drm_connector_status
3109 ironlake_dp_detect(struct intel_dp *intel_dp)
3110 {
3111 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3114 enum drm_connector_status status;
3115
3116 /* Can't disconnect eDP, but you can close the lid... */
3117 if (is_edp(intel_dp)) {
3118 status = intel_panel_detect(dev);
3119 if (status == connector_status_unknown)
3120 status = connector_status_connected;
3121 return status;
3122 }
3123
3124 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3125 return connector_status_disconnected;
3126
3127 return intel_dp_detect_dpcd(intel_dp);
3128 }
3129
3130 static enum drm_connector_status
3131 g4x_dp_detect(struct intel_dp *intel_dp)
3132 {
3133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3136 uint32_t bit;
3137
3138 /* Can't disconnect eDP, but you can close the lid... */
3139 if (is_edp(intel_dp)) {
3140 enum drm_connector_status status;
3141
3142 status = intel_panel_detect(dev);
3143 if (status == connector_status_unknown)
3144 status = connector_status_connected;
3145 return status;
3146 }
3147
3148 if (IS_VALLEYVIEW(dev)) {
3149 switch (intel_dig_port->port) {
3150 case PORT_B:
3151 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3152 break;
3153 case PORT_C:
3154 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3155 break;
3156 case PORT_D:
3157 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3158 break;
3159 default:
3160 return connector_status_unknown;
3161 }
3162 } else {
3163 switch (intel_dig_port->port) {
3164 case PORT_B:
3165 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3166 break;
3167 case PORT_C:
3168 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3169 break;
3170 case PORT_D:
3171 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3172 break;
3173 default:
3174 return connector_status_unknown;
3175 }
3176 }
3177
3178 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3179 return connector_status_disconnected;
3180
3181 return intel_dp_detect_dpcd(intel_dp);
3182 }
3183
3184 static struct edid *
3185 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3186 {
3187 struct intel_connector *intel_connector = to_intel_connector(connector);
3188
3189 /* use cached edid if we have one */
3190 if (intel_connector->edid) {
3191 /* invalid edid */
3192 if (IS_ERR(intel_connector->edid))
3193 return NULL;
3194
3195 return drm_edid_duplicate(intel_connector->edid);
3196 }
3197
3198 return drm_get_edid(connector, adapter);
3199 }
3200
3201 static int
3202 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3203 {
3204 struct intel_connector *intel_connector = to_intel_connector(connector);
3205
3206 /* use cached edid if we have one */
3207 if (intel_connector->edid) {
3208 /* invalid edid */
3209 if (IS_ERR(intel_connector->edid))
3210 return 0;
3211
3212 return intel_connector_update_modes(connector,
3213 intel_connector->edid);
3214 }
3215
3216 return intel_ddc_get_modes(connector, adapter);
3217 }
3218
3219 static enum drm_connector_status
3220 intel_dp_detect(struct drm_connector *connector, bool force)
3221 {
3222 struct intel_dp *intel_dp = intel_attached_dp(connector);
3223 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3224 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3225 struct drm_device *dev = connector->dev;
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 enum drm_connector_status status;
3228 enum intel_display_power_domain power_domain;
3229 struct edid *edid = NULL;
3230
3231 intel_runtime_pm_get(dev_priv);
3232
3233 power_domain = intel_display_port_power_domain(intel_encoder);
3234 intel_display_power_get(dev_priv, power_domain);
3235
3236 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3237 connector->base.id, drm_get_connector_name(connector));
3238
3239 intel_dp->has_audio = false;
3240
3241 if (HAS_PCH_SPLIT(dev))
3242 status = ironlake_dp_detect(intel_dp);
3243 else
3244 status = g4x_dp_detect(intel_dp);
3245
3246 if (status != connector_status_connected)
3247 goto out;
3248
3249 intel_dp_probe_oui(intel_dp);
3250
3251 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3252 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3253 } else {
3254 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3255 if (edid) {
3256 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3257 kfree(edid);
3258 }
3259 }
3260
3261 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3262 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3263 status = connector_status_connected;
3264
3265 out:
3266 intel_display_power_put(dev_priv, power_domain);
3267
3268 intel_runtime_pm_put(dev_priv);
3269
3270 return status;
3271 }
3272
3273 static int intel_dp_get_modes(struct drm_connector *connector)
3274 {
3275 struct intel_dp *intel_dp = intel_attached_dp(connector);
3276 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3277 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3278 struct intel_connector *intel_connector = to_intel_connector(connector);
3279 struct drm_device *dev = connector->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 enum intel_display_power_domain power_domain;
3282 int ret;
3283
3284 /* We should parse the EDID data and find out if it has an audio sink
3285 */
3286
3287 power_domain = intel_display_port_power_domain(intel_encoder);
3288 intel_display_power_get(dev_priv, power_domain);
3289
3290 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3291 intel_display_power_put(dev_priv, power_domain);
3292 if (ret)
3293 return ret;
3294
3295 /* if eDP has no EDID, fall back to fixed mode */
3296 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3297 struct drm_display_mode *mode;
3298 mode = drm_mode_duplicate(dev,
3299 intel_connector->panel.fixed_mode);
3300 if (mode) {
3301 drm_mode_probed_add(connector, mode);
3302 return 1;
3303 }
3304 }
3305 return 0;
3306 }
3307
3308 static bool
3309 intel_dp_detect_audio(struct drm_connector *connector)
3310 {
3311 struct intel_dp *intel_dp = intel_attached_dp(connector);
3312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3313 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3314 struct drm_device *dev = connector->dev;
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 enum intel_display_power_domain power_domain;
3317 struct edid *edid;
3318 bool has_audio = false;
3319
3320 power_domain = intel_display_port_power_domain(intel_encoder);
3321 intel_display_power_get(dev_priv, power_domain);
3322
3323 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3324 if (edid) {
3325 has_audio = drm_detect_monitor_audio(edid);
3326 kfree(edid);
3327 }
3328
3329 intel_display_power_put(dev_priv, power_domain);
3330
3331 return has_audio;
3332 }
3333
3334 static int
3335 intel_dp_set_property(struct drm_connector *connector,
3336 struct drm_property *property,
3337 uint64_t val)
3338 {
3339 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3340 struct intel_connector *intel_connector = to_intel_connector(connector);
3341 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3342 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3343 int ret;
3344
3345 ret = drm_object_property_set_value(&connector->base, property, val);
3346 if (ret)
3347 return ret;
3348
3349 if (property == dev_priv->force_audio_property) {
3350 int i = val;
3351 bool has_audio;
3352
3353 if (i == intel_dp->force_audio)
3354 return 0;
3355
3356 intel_dp->force_audio = i;
3357
3358 if (i == HDMI_AUDIO_AUTO)
3359 has_audio = intel_dp_detect_audio(connector);
3360 else
3361 has_audio = (i == HDMI_AUDIO_ON);
3362
3363 if (has_audio == intel_dp->has_audio)
3364 return 0;
3365
3366 intel_dp->has_audio = has_audio;
3367 goto done;
3368 }
3369
3370 if (property == dev_priv->broadcast_rgb_property) {
3371 bool old_auto = intel_dp->color_range_auto;
3372 uint32_t old_range = intel_dp->color_range;
3373
3374 switch (val) {
3375 case INTEL_BROADCAST_RGB_AUTO:
3376 intel_dp->color_range_auto = true;
3377 break;
3378 case INTEL_BROADCAST_RGB_FULL:
3379 intel_dp->color_range_auto = false;
3380 intel_dp->color_range = 0;
3381 break;
3382 case INTEL_BROADCAST_RGB_LIMITED:
3383 intel_dp->color_range_auto = false;
3384 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3385 break;
3386 default:
3387 return -EINVAL;
3388 }
3389
3390 if (old_auto == intel_dp->color_range_auto &&
3391 old_range == intel_dp->color_range)
3392 return 0;
3393
3394 goto done;
3395 }
3396
3397 if (is_edp(intel_dp) &&
3398 property == connector->dev->mode_config.scaling_mode_property) {
3399 if (val == DRM_MODE_SCALE_NONE) {
3400 DRM_DEBUG_KMS("no scaling not supported\n");
3401 return -EINVAL;
3402 }
3403
3404 if (intel_connector->panel.fitting_mode == val) {
3405 /* the eDP scaling property is not changed */
3406 return 0;
3407 }
3408 intel_connector->panel.fitting_mode = val;
3409
3410 goto done;
3411 }
3412
3413 return -EINVAL;
3414
3415 done:
3416 if (intel_encoder->base.crtc)
3417 intel_crtc_restore_mode(intel_encoder->base.crtc);
3418
3419 return 0;
3420 }
3421
3422 static void
3423 intel_dp_connector_destroy(struct drm_connector *connector)
3424 {
3425 struct intel_connector *intel_connector = to_intel_connector(connector);
3426
3427 if (!IS_ERR_OR_NULL(intel_connector->edid))
3428 kfree(intel_connector->edid);
3429
3430 /* Can't call is_edp() since the encoder may have been destroyed
3431 * already. */
3432 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3433 intel_panel_fini(&intel_connector->panel);
3434
3435 drm_connector_cleanup(connector);
3436 kfree(connector);
3437 }
3438
3439 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3440 {
3441 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3442 struct intel_dp *intel_dp = &intel_dig_port->dp;
3443 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3444
3445 i2c_del_adapter(&intel_dp->adapter);
3446 drm_encoder_cleanup(encoder);
3447 if (is_edp(intel_dp)) {
3448 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3449 mutex_lock(&dev->mode_config.mutex);
3450 edp_panel_vdd_off_sync(intel_dp);
3451 mutex_unlock(&dev->mode_config.mutex);
3452 }
3453 kfree(intel_dig_port);
3454 }
3455
3456 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3457 .dpms = intel_connector_dpms,
3458 .detect = intel_dp_detect,
3459 .fill_modes = drm_helper_probe_single_connector_modes,
3460 .set_property = intel_dp_set_property,
3461 .destroy = intel_dp_connector_destroy,
3462 };
3463
3464 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3465 .get_modes = intel_dp_get_modes,
3466 .mode_valid = intel_dp_mode_valid,
3467 .best_encoder = intel_best_encoder,
3468 };
3469
3470 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3471 .destroy = intel_dp_encoder_destroy,
3472 };
3473
3474 static void
3475 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3476 {
3477 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3478
3479 intel_dp_check_link_status(intel_dp);
3480 }
3481
3482 /* Return which DP Port should be selected for Transcoder DP control */
3483 int
3484 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3485 {
3486 struct drm_device *dev = crtc->dev;
3487 struct intel_encoder *intel_encoder;
3488 struct intel_dp *intel_dp;
3489
3490 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3491 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3492
3493 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3494 intel_encoder->type == INTEL_OUTPUT_EDP)
3495 return intel_dp->output_reg;
3496 }
3497
3498 return -1;
3499 }
3500
3501 /* check the VBT to see whether the eDP is on DP-D port */
3502 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3503 {
3504 struct drm_i915_private *dev_priv = dev->dev_private;
3505 union child_device_config *p_child;
3506 int i;
3507 static const short port_mapping[] = {
3508 [PORT_B] = PORT_IDPB,
3509 [PORT_C] = PORT_IDPC,
3510 [PORT_D] = PORT_IDPD,
3511 };
3512
3513 if (port == PORT_A)
3514 return true;
3515
3516 if (!dev_priv->vbt.child_dev_num)
3517 return false;
3518
3519 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3520 p_child = dev_priv->vbt.child_dev + i;
3521
3522 if (p_child->common.dvo_port == port_mapping[port] &&
3523 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3524 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3525 return true;
3526 }
3527 return false;
3528 }
3529
3530 static void
3531 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3532 {
3533 struct intel_connector *intel_connector = to_intel_connector(connector);
3534
3535 intel_attach_force_audio_property(connector);
3536 intel_attach_broadcast_rgb_property(connector);
3537 intel_dp->color_range_auto = true;
3538
3539 if (is_edp(intel_dp)) {
3540 drm_mode_create_scaling_mode_property(connector->dev);
3541 drm_object_attach_property(
3542 &connector->base,
3543 connector->dev->mode_config.scaling_mode_property,
3544 DRM_MODE_SCALE_ASPECT);
3545 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3546 }
3547 }
3548
3549 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3550 {
3551 intel_dp->last_power_cycle = jiffies;
3552 intel_dp->last_power_on = jiffies;
3553 intel_dp->last_backlight_off = jiffies;
3554 }
3555
3556 static void
3557 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3558 struct intel_dp *intel_dp,
3559 struct edp_power_seq *out)
3560 {
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 struct edp_power_seq cur, vbt, spec, final;
3563 u32 pp_on, pp_off, pp_div, pp;
3564 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3565
3566 if (HAS_PCH_SPLIT(dev)) {
3567 pp_ctrl_reg = PCH_PP_CONTROL;
3568 pp_on_reg = PCH_PP_ON_DELAYS;
3569 pp_off_reg = PCH_PP_OFF_DELAYS;
3570 pp_div_reg = PCH_PP_DIVISOR;
3571 } else {
3572 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3573
3574 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3575 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3576 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3577 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3578 }
3579
3580 /* Workaround: Need to write PP_CONTROL with the unlock key as
3581 * the very first thing. */
3582 pp = ironlake_get_pp_control(intel_dp);
3583 I915_WRITE(pp_ctrl_reg, pp);
3584
3585 pp_on = I915_READ(pp_on_reg);
3586 pp_off = I915_READ(pp_off_reg);
3587 pp_div = I915_READ(pp_div_reg);
3588
3589 /* Pull timing values out of registers */
3590 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3591 PANEL_POWER_UP_DELAY_SHIFT;
3592
3593 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3594 PANEL_LIGHT_ON_DELAY_SHIFT;
3595
3596 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3597 PANEL_LIGHT_OFF_DELAY_SHIFT;
3598
3599 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3600 PANEL_POWER_DOWN_DELAY_SHIFT;
3601
3602 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3603 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3604
3605 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3606 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3607
3608 vbt = dev_priv->vbt.edp_pps;
3609
3610 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3611 * our hw here, which are all in 100usec. */
3612 spec.t1_t3 = 210 * 10;
3613 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3614 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3615 spec.t10 = 500 * 10;
3616 /* This one is special and actually in units of 100ms, but zero
3617 * based in the hw (so we need to add 100 ms). But the sw vbt
3618 * table multiplies it with 1000 to make it in units of 100usec,
3619 * too. */
3620 spec.t11_t12 = (510 + 100) * 10;
3621
3622 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3623 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3624
3625 /* Use the max of the register settings and vbt. If both are
3626 * unset, fall back to the spec limits. */
3627 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3628 spec.field : \
3629 max(cur.field, vbt.field))
3630 assign_final(t1_t3);
3631 assign_final(t8);
3632 assign_final(t9);
3633 assign_final(t10);
3634 assign_final(t11_t12);
3635 #undef assign_final
3636
3637 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3638 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3639 intel_dp->backlight_on_delay = get_delay(t8);
3640 intel_dp->backlight_off_delay = get_delay(t9);
3641 intel_dp->panel_power_down_delay = get_delay(t10);
3642 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3643 #undef get_delay
3644
3645 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3646 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3647 intel_dp->panel_power_cycle_delay);
3648
3649 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3650 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3651
3652 if (out)
3653 *out = final;
3654 }
3655
3656 static void
3657 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3658 struct intel_dp *intel_dp,
3659 struct edp_power_seq *seq)
3660 {
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 u32 pp_on, pp_off, pp_div, port_sel = 0;
3663 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3664 int pp_on_reg, pp_off_reg, pp_div_reg;
3665
3666 if (HAS_PCH_SPLIT(dev)) {
3667 pp_on_reg = PCH_PP_ON_DELAYS;
3668 pp_off_reg = PCH_PP_OFF_DELAYS;
3669 pp_div_reg = PCH_PP_DIVISOR;
3670 } else {
3671 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3672
3673 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3674 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3675 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3676 }
3677
3678 /*
3679 * And finally store the new values in the power sequencer. The
3680 * backlight delays are set to 1 because we do manual waits on them. For
3681 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3682 * we'll end up waiting for the backlight off delay twice: once when we
3683 * do the manual sleep, and once when we disable the panel and wait for
3684 * the PP_STATUS bit to become zero.
3685 */
3686 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3687 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3688 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3689 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3690 /* Compute the divisor for the pp clock, simply match the Bspec
3691 * formula. */
3692 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3693 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3694 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3695
3696 /* Haswell doesn't have any port selection bits for the panel
3697 * power sequencer any more. */
3698 if (IS_VALLEYVIEW(dev)) {
3699 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3700 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3701 else
3702 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3703 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3704 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3705 port_sel = PANEL_PORT_SELECT_DPA;
3706 else
3707 port_sel = PANEL_PORT_SELECT_DPD;
3708 }
3709
3710 pp_on |= port_sel;
3711
3712 I915_WRITE(pp_on_reg, pp_on);
3713 I915_WRITE(pp_off_reg, pp_off);
3714 I915_WRITE(pp_div_reg, pp_div);
3715
3716 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3717 I915_READ(pp_on_reg),
3718 I915_READ(pp_off_reg),
3719 I915_READ(pp_div_reg));
3720 }
3721
3722 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3723 struct intel_connector *intel_connector,
3724 struct edp_power_seq *power_seq)
3725 {
3726 struct drm_connector *connector = &intel_connector->base;
3727 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3728 struct drm_device *dev = intel_dig_port->base.base.dev;
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 struct drm_display_mode *fixed_mode = NULL;
3731 bool has_dpcd;
3732 struct drm_display_mode *scan;
3733 struct edid *edid;
3734
3735 if (!is_edp(intel_dp))
3736 return true;
3737
3738 /* Cache DPCD and EDID for edp. */
3739 edp_panel_vdd_on(intel_dp);
3740 has_dpcd = intel_dp_get_dpcd(intel_dp);
3741 edp_panel_vdd_off(intel_dp, false);
3742
3743 if (has_dpcd) {
3744 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3745 dev_priv->no_aux_handshake =
3746 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3747 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3748 } else {
3749 /* if this fails, presume the device is a ghost */
3750 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3751 return false;
3752 }
3753
3754 /* We now know it's not a ghost, init power sequence regs. */
3755 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3756
3757 edid = drm_get_edid(connector, &intel_dp->adapter);
3758 if (edid) {
3759 if (drm_add_edid_modes(connector, edid)) {
3760 drm_mode_connector_update_edid_property(connector,
3761 edid);
3762 drm_edid_to_eld(connector, edid);
3763 } else {
3764 kfree(edid);
3765 edid = ERR_PTR(-EINVAL);
3766 }
3767 } else {
3768 edid = ERR_PTR(-ENOENT);
3769 }
3770 intel_connector->edid = edid;
3771
3772 /* prefer fixed mode from EDID if available */
3773 list_for_each_entry(scan, &connector->probed_modes, head) {
3774 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3775 fixed_mode = drm_mode_duplicate(dev, scan);
3776 break;
3777 }
3778 }
3779
3780 /* fallback to VBT if available for eDP */
3781 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3782 fixed_mode = drm_mode_duplicate(dev,
3783 dev_priv->vbt.lfp_lvds_vbt_mode);
3784 if (fixed_mode)
3785 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3786 }
3787
3788 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3789 intel_panel_setup_backlight(connector);
3790
3791 return true;
3792 }
3793
3794 bool
3795 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3796 struct intel_connector *intel_connector)
3797 {
3798 struct drm_connector *connector = &intel_connector->base;
3799 struct intel_dp *intel_dp = &intel_dig_port->dp;
3800 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3801 struct drm_device *dev = intel_encoder->base.dev;
3802 struct drm_i915_private *dev_priv = dev->dev_private;
3803 enum port port = intel_dig_port->port;
3804 struct edp_power_seq power_seq = { 0 };
3805 const char *name = NULL;
3806 int type, error;
3807
3808 /* intel_dp vfuncs */
3809 if (IS_VALLEYVIEW(dev))
3810 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3811 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3812 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3813 else if (HAS_PCH_SPLIT(dev))
3814 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3815 else
3816 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3817
3818 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3819
3820 /* Preserve the current hw state. */
3821 intel_dp->DP = I915_READ(intel_dp->output_reg);
3822 intel_dp->attached_connector = intel_connector;
3823
3824 if (intel_dp_is_edp(dev, port))
3825 type = DRM_MODE_CONNECTOR_eDP;
3826 else
3827 type = DRM_MODE_CONNECTOR_DisplayPort;
3828
3829 /*
3830 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3831 * for DP the encoder type can be set by the caller to
3832 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3833 */
3834 if (type == DRM_MODE_CONNECTOR_eDP)
3835 intel_encoder->type = INTEL_OUTPUT_EDP;
3836
3837 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3838 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3839 port_name(port));
3840
3841 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3842 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3843
3844 connector->interlace_allowed = true;
3845 connector->doublescan_allowed = 0;
3846
3847 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3848 edp_panel_vdd_work);
3849
3850 intel_connector_attach_encoder(intel_connector, intel_encoder);
3851 drm_sysfs_connector_add(connector);
3852
3853 if (HAS_DDI(dev))
3854 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3855 else
3856 intel_connector->get_hw_state = intel_connector_get_hw_state;
3857 intel_connector->unregister = intel_dp_connector_unregister;
3858
3859 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3860 if (HAS_DDI(dev)) {
3861 switch (intel_dig_port->port) {
3862 case PORT_A:
3863 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3864 break;
3865 case PORT_B:
3866 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3867 break;
3868 case PORT_C:
3869 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3870 break;
3871 case PORT_D:
3872 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3873 break;
3874 default:
3875 BUG();
3876 }
3877 }
3878
3879 /* Set up the DDC bus. */
3880 switch (port) {
3881 case PORT_A:
3882 intel_encoder->hpd_pin = HPD_PORT_A;
3883 name = "DPDDC-A";
3884 break;
3885 case PORT_B:
3886 intel_encoder->hpd_pin = HPD_PORT_B;
3887 name = "DPDDC-B";
3888 break;
3889 case PORT_C:
3890 intel_encoder->hpd_pin = HPD_PORT_C;
3891 name = "DPDDC-C";
3892 break;
3893 case PORT_D:
3894 intel_encoder->hpd_pin = HPD_PORT_D;
3895 name = "DPDDC-D";
3896 break;
3897 default:
3898 BUG();
3899 }
3900
3901 if (is_edp(intel_dp)) {
3902 intel_dp_init_panel_power_timestamps(intel_dp);
3903 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3904 }
3905
3906 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3907 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3908 error, port_name(port));
3909
3910 intel_dp->psr_setup_done = false;
3911
3912 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3913 i2c_del_adapter(&intel_dp->adapter);
3914 if (is_edp(intel_dp)) {
3915 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3916 mutex_lock(&dev->mode_config.mutex);
3917 edp_panel_vdd_off_sync(intel_dp);
3918 mutex_unlock(&dev->mode_config.mutex);
3919 }
3920 drm_sysfs_connector_remove(connector);
3921 drm_connector_cleanup(connector);
3922 return false;
3923 }
3924
3925 intel_dp_add_properties(intel_dp, connector);
3926
3927 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3928 * 0xd. Failure to do so will result in spurious interrupts being
3929 * generated on the port when a cable is not attached.
3930 */
3931 if (IS_G4X(dev) && !IS_GM45(dev)) {
3932 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3933 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3934 }
3935
3936 return true;
3937 }
3938
3939 void
3940 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3941 {
3942 struct intel_digital_port *intel_dig_port;
3943 struct intel_encoder *intel_encoder;
3944 struct drm_encoder *encoder;
3945 struct intel_connector *intel_connector;
3946
3947 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3948 if (!intel_dig_port)
3949 return;
3950
3951 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3952 if (!intel_connector) {
3953 kfree(intel_dig_port);
3954 return;
3955 }
3956
3957 intel_encoder = &intel_dig_port->base;
3958 encoder = &intel_encoder->base;
3959
3960 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3961 DRM_MODE_ENCODER_TMDS);
3962
3963 intel_encoder->compute_config = intel_dp_compute_config;
3964 intel_encoder->mode_set = intel_dp_mode_set;
3965 intel_encoder->disable = intel_disable_dp;
3966 intel_encoder->post_disable = intel_post_disable_dp;
3967 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3968 intel_encoder->get_config = intel_dp_get_config;
3969 if (IS_VALLEYVIEW(dev)) {
3970 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3971 intel_encoder->pre_enable = vlv_pre_enable_dp;
3972 intel_encoder->enable = vlv_enable_dp;
3973 } else {
3974 intel_encoder->pre_enable = g4x_pre_enable_dp;
3975 intel_encoder->enable = g4x_enable_dp;
3976 }
3977
3978 intel_dig_port->port = port;
3979 intel_dig_port->dp.output_reg = output_reg;
3980
3981 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3982 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3983 intel_encoder->cloneable = 0;
3984 intel_encoder->hot_plug = intel_dp_hot_plug;
3985
3986 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3987 drm_encoder_cleanup(encoder);
3988 kfree(intel_dig_port);
3989 kfree(intel_connector);
3990 }
3991 }
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