2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(const uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
293 static void pps_lock(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
297 struct drm_device
*dev
= encoder
->base
.dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 enum intel_display_power_domain power_domain
;
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
305 power_domain
= intel_display_port_power_domain(encoder
);
306 intel_display_power_get(dev_priv
, power_domain
);
308 mutex_lock(&dev_priv
->pps_mutex
);
311 static void pps_unlock(struct intel_dp
*intel_dp
)
313 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
314 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
315 struct drm_device
*dev
= encoder
->base
.dev
;
316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 enum intel_display_power_domain power_domain
;
319 mutex_unlock(&dev_priv
->pps_mutex
);
321 power_domain
= intel_display_port_power_domain(encoder
);
322 intel_display_power_put(dev_priv
, power_domain
);
326 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
328 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
329 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
331 struct intel_encoder
*encoder
;
332 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
333 struct edp_power_seq power_seq
;
335 lockdep_assert_held(&dev_priv
->pps_mutex
);
337 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
338 return intel_dp
->pps_pipe
;
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
344 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
346 struct intel_dp
*tmp
;
348 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
351 tmp
= enc_to_intel_dp(&encoder
->base
);
353 if (tmp
->pps_pipe
!= INVALID_PIPE
)
354 pipes
&= ~(1 << tmp
->pps_pipe
);
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
361 if (WARN_ON(pipes
== 0))
364 intel_dp
->pps_pipe
= ffs(pipes
) - 1;
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp
->pps_pipe
),
368 port_name(intel_dig_port
->port
));
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
372 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
375 return intel_dp
->pps_pipe
;
378 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
381 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
387 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
393 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
400 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
402 vlv_pipe_check pipe_check
)
406 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
407 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
408 PANEL_PORT_SELECT_MASK
;
410 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
413 if (!pipe_check(dev_priv
, pipe
))
423 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
425 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
426 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
428 struct edp_power_seq power_seq
;
429 enum port port
= intel_dig_port
->port
;
431 lockdep_assert_held(&dev_priv
->pps_mutex
);
433 /* try to find a pipe with this port selected */
434 /* first pick one where the panel is on */
435 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
439 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
440 vlv_pipe_has_vdd_on
);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
443 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
456 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
457 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
461 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
463 struct drm_device
*dev
= dev_priv
->dev
;
464 struct intel_encoder
*encoder
;
466 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
479 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
480 struct intel_dp
*intel_dp
;
482 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
485 intel_dp
= enc_to_intel_dp(&encoder
->base
);
486 intel_dp
->pps_pipe
= INVALID_PIPE
;
490 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
492 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
494 if (HAS_PCH_SPLIT(dev
))
495 return PCH_PP_CONTROL
;
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
500 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
502 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
504 if (HAS_PCH_SPLIT(dev
))
505 return PCH_PP_STATUS
;
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
510 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
515 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
517 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
520 u32 pp_ctrl_reg
, pp_div_reg
;
522 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
527 if (IS_VALLEYVIEW(dev
)) {
528 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
530 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
531 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
532 pp_div
= I915_READ(pp_div_reg
);
533 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
537 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
538 msleep(intel_dp
->panel_power_cycle_delay
);
541 pps_unlock(intel_dp
);
546 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
548 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
551 lockdep_assert_held(&dev_priv
->pps_mutex
);
553 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
556 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
558 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
561 lockdep_assert_held(&dev_priv
->pps_mutex
);
563 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
567 intel_dp_check_edp(struct intel_dp
*intel_dp
)
569 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
572 if (!is_edp(intel_dp
))
575 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
578 I915_READ(_pp_stat_reg(intel_dp
)),
579 I915_READ(_pp_ctrl_reg(intel_dp
)));
584 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
586 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
587 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
589 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
593 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
595 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
596 msecs_to_jiffies_timeout(10));
598 done
= wait_for_atomic(C
, 10) == 0;
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
609 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
610 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
616 return index
? 0 : intel_hrawclk(dev
) / 2;
619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
621 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
622 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
627 if (intel_dig_port
->port
== PORT_A
) {
628 if (IS_GEN6(dev
) || IS_GEN7(dev
))
629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
631 return 225; /* eDP input clock at 450Mhz */
633 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
639 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
640 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
643 if (intel_dig_port
->port
== PORT_A
) {
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
647 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
648 /* Workaround for non-ULT HSW */
655 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
661 return index
? 0 : 100;
664 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
667 * SKL doesn't need us to program the AUX clock divider (Hardware will
668 * derive the clock from CDCLK automatically). We still implement the
669 * get_aux_clock_divider vfunc to plug-in into the existing code.
671 return index
? 0 : 1;
674 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
677 uint32_t aux_clock_divider
)
679 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
680 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
681 uint32_t precharge
, timeout
;
688 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
689 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
691 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
693 return DP_AUX_CH_CTL_SEND_BUSY
|
695 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
696 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
698 DP_AUX_CH_CTL_RECEIVE_ERROR
|
699 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
700 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
701 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
704 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
709 return DP_AUX_CH_CTL_SEND_BUSY
|
711 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
712 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
713 DP_AUX_CH_CTL_TIME_OUT_1600us
|
714 DP_AUX_CH_CTL_RECEIVE_ERROR
|
715 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
716 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
720 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
721 const uint8_t *send
, int send_bytes
,
722 uint8_t *recv
, int recv_size
)
724 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
725 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
727 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
728 uint32_t ch_data
= ch_ctl
+ 4;
729 uint32_t aux_clock_divider
;
730 int i
, ret
, recv_bytes
;
733 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
739 * We will be called with VDD already enabled for dpcd/edid/oui reads.
740 * In such cases we want to leave VDD enabled and it's up to upper layers
741 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
744 vdd
= edp_panel_vdd_on(intel_dp
);
746 /* dp aux is extremely sensitive to irq latency, hence request the
747 * lowest possible wakeup latency and so prevent the cpu from going into
750 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
752 intel_dp_check_edp(intel_dp
);
754 intel_aux_display_runtime_get(dev_priv
);
756 /* Try to wait for any previous AUX channel activity */
757 for (try = 0; try < 3; try++) {
758 status
= I915_READ_NOTRACE(ch_ctl
);
759 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
765 WARN(1, "dp_aux_ch not started status 0x%08x\n",
771 /* Only 5 data registers! */
772 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
777 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
778 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
783 /* Must try at least 3 times according to DP spec */
784 for (try = 0; try < 5; try++) {
785 /* Load the send data into the aux channel data registers */
786 for (i
= 0; i
< send_bytes
; i
+= 4)
787 I915_WRITE(ch_data
+ i
,
788 pack_aux(send
+ i
, send_bytes
- i
));
790 /* Send the command and wait for it to complete */
791 I915_WRITE(ch_ctl
, send_ctl
);
793 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
795 /* Clear done status and any errors */
799 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
800 DP_AUX_CH_CTL_RECEIVE_ERROR
);
802 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
803 DP_AUX_CH_CTL_RECEIVE_ERROR
))
805 if (status
& DP_AUX_CH_CTL_DONE
)
808 if (status
& DP_AUX_CH_CTL_DONE
)
812 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
813 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
818 /* Check for timeout or receive error.
819 * Timeouts occur when the sink is not connected
821 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
822 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
827 /* Timeouts occur when the device isn't connected, so they're
828 * "normal" -- don't fill the kernel log with these */
829 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
830 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
835 /* Unload any bytes sent back from the other side */
836 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
837 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
838 if (recv_bytes
> recv_size
)
839 recv_bytes
= recv_size
;
841 for (i
= 0; i
< recv_bytes
; i
+= 4)
842 unpack_aux(I915_READ(ch_data
+ i
),
843 recv
+ i
, recv_bytes
- i
);
847 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
848 intel_aux_display_runtime_put(dev_priv
);
851 edp_panel_vdd_off(intel_dp
, false);
853 pps_unlock(intel_dp
);
858 #define BARE_ADDRESS_SIZE 3
859 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
861 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
863 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
864 uint8_t txbuf
[20], rxbuf
[20];
865 size_t txsize
, rxsize
;
868 txbuf
[0] = msg
->request
<< 4;
869 txbuf
[1] = msg
->address
>> 8;
870 txbuf
[2] = msg
->address
& 0xff;
871 txbuf
[3] = msg
->size
- 1;
873 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
874 case DP_AUX_NATIVE_WRITE
:
875 case DP_AUX_I2C_WRITE
:
876 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
879 if (WARN_ON(txsize
> 20))
882 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
884 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
886 msg
->reply
= rxbuf
[0] >> 4;
888 /* Return payload size. */
893 case DP_AUX_NATIVE_READ
:
894 case DP_AUX_I2C_READ
:
895 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
896 rxsize
= msg
->size
+ 1;
898 if (WARN_ON(rxsize
> 20))
901 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
903 msg
->reply
= rxbuf
[0] >> 4;
905 * Assume happy day, and copy the data. The caller is
906 * expected to check msg->reply before touching it.
908 * Return payload size.
911 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
924 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
926 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
927 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
928 enum port port
= intel_dig_port
->port
;
929 const char *name
= NULL
;
934 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
938 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
942 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
946 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
954 * The AUX_CTL register is usually DP_CTL + 0x10.
956 * On Haswell and Broadwell though:
957 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
958 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
960 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
962 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
963 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
965 intel_dp
->aux
.name
= name
;
966 intel_dp
->aux
.dev
= dev
->dev
;
967 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
969 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
970 connector
->base
.kdev
->kobj
.name
);
972 ret
= drm_dp_aux_register(&intel_dp
->aux
);
974 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
979 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
980 &intel_dp
->aux
.ddc
.dev
.kobj
,
981 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
983 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
984 drm_dp_aux_unregister(&intel_dp
->aux
);
989 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
991 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
993 if (!intel_connector
->mst_port
)
994 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
995 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
996 intel_connector_unregister(intel_connector
);
1000 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
1003 case DP_LINK_BW_1_62
:
1004 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1006 case DP_LINK_BW_2_7
:
1007 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1009 case DP_LINK_BW_5_4
:
1010 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1016 intel_dp_set_clock(struct intel_encoder
*encoder
,
1017 struct intel_crtc_config
*pipe_config
, int link_bw
)
1019 struct drm_device
*dev
= encoder
->base
.dev
;
1020 const struct dp_link_dpll
*divisor
= NULL
;
1024 divisor
= gen4_dpll
;
1025 count
= ARRAY_SIZE(gen4_dpll
);
1026 } else if (HAS_PCH_SPLIT(dev
)) {
1028 count
= ARRAY_SIZE(pch_dpll
);
1029 } else if (IS_CHERRYVIEW(dev
)) {
1031 count
= ARRAY_SIZE(chv_dpll
);
1032 } else if (IS_VALLEYVIEW(dev
)) {
1034 count
= ARRAY_SIZE(vlv_dpll
);
1037 if (divisor
&& count
) {
1038 for (i
= 0; i
< count
; i
++) {
1039 if (link_bw
== divisor
[i
].link_bw
) {
1040 pipe_config
->dpll
= divisor
[i
].dpll
;
1041 pipe_config
->clock_set
= true;
1049 intel_dp_compute_config(struct intel_encoder
*encoder
,
1050 struct intel_crtc_config
*pipe_config
)
1052 struct drm_device
*dev
= encoder
->base
.dev
;
1053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1054 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1055 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1056 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1057 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1058 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1059 int lane_count
, clock
;
1060 int min_lane_count
= 1;
1061 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1062 /* Conveniently, the link BW constants become indices with a shift...*/
1064 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1066 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1067 int link_avail
, link_clock
;
1069 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1070 pipe_config
->has_pch_encoder
= true;
1072 pipe_config
->has_dp_encoder
= true;
1073 pipe_config
->has_drrs
= false;
1074 pipe_config
->has_audio
= intel_dp
->has_audio
;
1076 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1077 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1079 if (!HAS_PCH_SPLIT(dev
))
1080 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1081 intel_connector
->panel
.fitting_mode
);
1083 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1084 intel_connector
->panel
.fitting_mode
);
1087 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1090 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1091 "max bw %02x pixel clock %iKHz\n",
1092 max_lane_count
, bws
[max_clock
],
1093 adjusted_mode
->crtc_clock
);
1095 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1096 * bpc in between. */
1097 bpp
= pipe_config
->pipe_bpp
;
1098 if (is_edp(intel_dp
)) {
1099 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1100 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1101 dev_priv
->vbt
.edp_bpp
);
1102 bpp
= dev_priv
->vbt
.edp_bpp
;
1106 * Use the maximum clock and number of lanes the eDP panel
1107 * advertizes being capable of. The panels are generally
1108 * designed to support only a single clock and lane
1109 * configuration, and typically these values correspond to the
1110 * native resolution of the panel.
1112 min_lane_count
= max_lane_count
;
1113 min_clock
= max_clock
;
1116 for (; bpp
>= 6*3; bpp
-= 2*3) {
1117 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1120 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1121 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1122 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1123 link_avail
= intel_dp_max_data_rate(link_clock
,
1126 if (mode_rate
<= link_avail
) {
1136 if (intel_dp
->color_range_auto
) {
1139 * CEA-861-E - 5.1 Default Encoding Parameters
1140 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1142 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1143 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1145 intel_dp
->color_range
= 0;
1148 if (intel_dp
->color_range
)
1149 pipe_config
->limited_color_range
= true;
1151 intel_dp
->link_bw
= bws
[clock
];
1152 intel_dp
->lane_count
= lane_count
;
1153 pipe_config
->pipe_bpp
= bpp
;
1154 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1156 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1157 intel_dp
->link_bw
, intel_dp
->lane_count
,
1158 pipe_config
->port_clock
, bpp
);
1159 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1160 mode_rate
, link_avail
);
1162 intel_link_compute_m_n(bpp
, lane_count
,
1163 adjusted_mode
->crtc_clock
,
1164 pipe_config
->port_clock
,
1165 &pipe_config
->dp_m_n
);
1167 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1168 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1169 pipe_config
->has_drrs
= true;
1170 intel_link_compute_m_n(bpp
, lane_count
,
1171 intel_connector
->panel
.downclock_mode
->clock
,
1172 pipe_config
->port_clock
,
1173 &pipe_config
->dp_m2_n2
);
1176 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1177 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1179 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1184 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1186 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1187 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1188 struct drm_device
*dev
= crtc
->base
.dev
;
1189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1192 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1193 dpa_ctl
= I915_READ(DP_A
);
1194 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1196 if (crtc
->config
.port_clock
== 162000) {
1197 /* For a long time we've carried around a ILK-DevA w/a for the
1198 * 160MHz clock. If we're really unlucky, it's still required.
1200 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1201 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1202 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1204 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1205 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1208 I915_WRITE(DP_A
, dpa_ctl
);
1214 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1216 struct drm_device
*dev
= encoder
->base
.dev
;
1217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1218 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1219 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1220 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1221 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1224 * There are four kinds of DP registers:
1231 * IBX PCH and CPU are the same for almost everything,
1232 * except that the CPU DP PLL is configured in this
1235 * CPT PCH is quite different, having many bits moved
1236 * to the TRANS_DP_CTL register instead. That
1237 * configuration happens (oddly) in ironlake_pch_enable
1240 /* Preserve the BIOS-computed detected bit. This is
1241 * supposed to be read-only.
1243 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1245 /* Handle DP bits in common between all three register formats */
1246 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1247 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1249 if (crtc
->config
.has_audio
) {
1250 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1251 pipe_name(crtc
->pipe
));
1252 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1253 intel_write_eld(&encoder
->base
, adjusted_mode
);
1256 /* Split out the IBX/CPU vs CPT settings */
1258 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1259 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1260 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1261 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1262 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1263 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1265 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1266 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1268 intel_dp
->DP
|= crtc
->pipe
<< 29;
1269 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1270 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1271 intel_dp
->DP
|= intel_dp
->color_range
;
1273 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1274 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1275 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1276 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1277 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1279 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1280 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1282 if (!IS_CHERRYVIEW(dev
)) {
1283 if (crtc
->pipe
== 1)
1284 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1286 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1289 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1293 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1294 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1296 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1297 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1299 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1300 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1302 static void wait_panel_status(struct intel_dp
*intel_dp
,
1306 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1308 u32 pp_stat_reg
, pp_ctrl_reg
;
1310 lockdep_assert_held(&dev_priv
->pps_mutex
);
1312 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1313 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1315 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1317 I915_READ(pp_stat_reg
),
1318 I915_READ(pp_ctrl_reg
));
1320 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1321 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1322 I915_READ(pp_stat_reg
),
1323 I915_READ(pp_ctrl_reg
));
1326 DRM_DEBUG_KMS("Wait complete\n");
1329 static void wait_panel_on(struct intel_dp
*intel_dp
)
1331 DRM_DEBUG_KMS("Wait for panel power on\n");
1332 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1335 static void wait_panel_off(struct intel_dp
*intel_dp
)
1337 DRM_DEBUG_KMS("Wait for panel power off time\n");
1338 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1341 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1343 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1345 /* When we disable the VDD override bit last we have to do the manual
1347 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1348 intel_dp
->panel_power_cycle_delay
);
1350 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1353 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1355 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1356 intel_dp
->backlight_on_delay
);
1359 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1361 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1362 intel_dp
->backlight_off_delay
);
1365 /* Read the current pp_control value, unlocking the register if it
1369 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1371 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1375 lockdep_assert_held(&dev_priv
->pps_mutex
);
1377 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1378 control
&= ~PANEL_UNLOCK_MASK
;
1379 control
|= PANEL_UNLOCK_REGS
;
1384 * Must be paired with edp_panel_vdd_off().
1385 * Must hold pps_mutex around the whole on/off sequence.
1386 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1388 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1390 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1391 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1392 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1394 enum intel_display_power_domain power_domain
;
1396 u32 pp_stat_reg
, pp_ctrl_reg
;
1397 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1399 lockdep_assert_held(&dev_priv
->pps_mutex
);
1401 if (!is_edp(intel_dp
))
1404 intel_dp
->want_panel_vdd
= true;
1406 if (edp_have_panel_vdd(intel_dp
))
1407 return need_to_disable
;
1409 power_domain
= intel_display_port_power_domain(intel_encoder
);
1410 intel_display_power_get(dev_priv
, power_domain
);
1412 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1414 if (!edp_have_panel_power(intel_dp
))
1415 wait_panel_power_cycle(intel_dp
);
1417 pp
= ironlake_get_pp_control(intel_dp
);
1418 pp
|= EDP_FORCE_VDD
;
1420 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1421 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1423 I915_WRITE(pp_ctrl_reg
, pp
);
1424 POSTING_READ(pp_ctrl_reg
);
1425 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1426 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1428 * If the panel wasn't on, delay before accessing aux channel
1430 if (!edp_have_panel_power(intel_dp
)) {
1431 DRM_DEBUG_KMS("eDP was not running\n");
1432 msleep(intel_dp
->panel_power_up_delay
);
1435 return need_to_disable
;
1439 * Must be paired with intel_edp_panel_vdd_off() or
1440 * intel_edp_panel_off().
1441 * Nested calls to these functions are not allowed since
1442 * we drop the lock. Caller must use some higher level
1443 * locking to prevent nested calls from other threads.
1445 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1449 if (!is_edp(intel_dp
))
1453 vdd
= edp_panel_vdd_on(intel_dp
);
1454 pps_unlock(intel_dp
);
1456 WARN(!vdd
, "eDP VDD already requested on\n");
1459 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1461 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1463 struct intel_digital_port
*intel_dig_port
=
1464 dp_to_dig_port(intel_dp
);
1465 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1466 enum intel_display_power_domain power_domain
;
1468 u32 pp_stat_reg
, pp_ctrl_reg
;
1470 lockdep_assert_held(&dev_priv
->pps_mutex
);
1472 WARN_ON(intel_dp
->want_panel_vdd
);
1474 if (!edp_have_panel_vdd(intel_dp
))
1477 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1479 pp
= ironlake_get_pp_control(intel_dp
);
1480 pp
&= ~EDP_FORCE_VDD
;
1482 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1483 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1485 I915_WRITE(pp_ctrl_reg
, pp
);
1486 POSTING_READ(pp_ctrl_reg
);
1488 /* Make sure sequencer is idle before allowing subsequent activity */
1489 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1490 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1492 if ((pp
& POWER_TARGET_ON
) == 0)
1493 intel_dp
->last_power_cycle
= jiffies
;
1495 power_domain
= intel_display_port_power_domain(intel_encoder
);
1496 intel_display_power_put(dev_priv
, power_domain
);
1499 static void edp_panel_vdd_work(struct work_struct
*__work
)
1501 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1502 struct intel_dp
, panel_vdd_work
);
1505 if (!intel_dp
->want_panel_vdd
)
1506 edp_panel_vdd_off_sync(intel_dp
);
1507 pps_unlock(intel_dp
);
1510 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1512 unsigned long delay
;
1515 * Queue the timer to fire a long time from now (relative to the power
1516 * down delay) to keep the panel power up across a sequence of
1519 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1520 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1524 * Must be paired with edp_panel_vdd_on().
1525 * Must hold pps_mutex around the whole on/off sequence.
1526 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1528 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1530 struct drm_i915_private
*dev_priv
=
1531 intel_dp_to_dev(intel_dp
)->dev_private
;
1533 lockdep_assert_held(&dev_priv
->pps_mutex
);
1535 if (!is_edp(intel_dp
))
1538 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1540 intel_dp
->want_panel_vdd
= false;
1543 edp_panel_vdd_off_sync(intel_dp
);
1545 edp_panel_vdd_schedule_off(intel_dp
);
1549 * Must be paired with intel_edp_panel_vdd_on().
1550 * Nested calls to these functions are not allowed since
1551 * we drop the lock. Caller must use some higher level
1552 * locking to prevent nested calls from other threads.
1554 static void intel_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1556 if (!is_edp(intel_dp
))
1560 edp_panel_vdd_off(intel_dp
, sync
);
1561 pps_unlock(intel_dp
);
1564 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1566 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1571 if (!is_edp(intel_dp
))
1574 DRM_DEBUG_KMS("Turn eDP power on\n");
1578 if (edp_have_panel_power(intel_dp
)) {
1579 DRM_DEBUG_KMS("eDP power already on\n");
1583 wait_panel_power_cycle(intel_dp
);
1585 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1586 pp
= ironlake_get_pp_control(intel_dp
);
1588 /* ILK workaround: disable reset around power sequence */
1589 pp
&= ~PANEL_POWER_RESET
;
1590 I915_WRITE(pp_ctrl_reg
, pp
);
1591 POSTING_READ(pp_ctrl_reg
);
1594 pp
|= POWER_TARGET_ON
;
1596 pp
|= PANEL_POWER_RESET
;
1598 I915_WRITE(pp_ctrl_reg
, pp
);
1599 POSTING_READ(pp_ctrl_reg
);
1601 wait_panel_on(intel_dp
);
1602 intel_dp
->last_power_on
= jiffies
;
1605 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1606 I915_WRITE(pp_ctrl_reg
, pp
);
1607 POSTING_READ(pp_ctrl_reg
);
1611 pps_unlock(intel_dp
);
1614 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1616 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1617 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1618 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1620 enum intel_display_power_domain power_domain
;
1624 if (!is_edp(intel_dp
))
1627 DRM_DEBUG_KMS("Turn eDP power off\n");
1631 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1633 pp
= ironlake_get_pp_control(intel_dp
);
1634 /* We need to switch off panel power _and_ force vdd, for otherwise some
1635 * panels get very unhappy and cease to work. */
1636 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1639 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1641 intel_dp
->want_panel_vdd
= false;
1643 I915_WRITE(pp_ctrl_reg
, pp
);
1644 POSTING_READ(pp_ctrl_reg
);
1646 intel_dp
->last_power_cycle
= jiffies
;
1647 wait_panel_off(intel_dp
);
1649 /* We got a reference when we enabled the VDD. */
1650 power_domain
= intel_display_port_power_domain(intel_encoder
);
1651 intel_display_power_put(dev_priv
, power_domain
);
1653 pps_unlock(intel_dp
);
1656 /* Enable backlight in the panel power control. */
1657 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1659 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1660 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1666 * If we enable the backlight right away following a panel power
1667 * on, we may see slight flicker as the panel syncs with the eDP
1668 * link. So delay a bit to make sure the image is solid before
1669 * allowing it to appear.
1671 wait_backlight_on(intel_dp
);
1675 pp
= ironlake_get_pp_control(intel_dp
);
1676 pp
|= EDP_BLC_ENABLE
;
1678 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1680 I915_WRITE(pp_ctrl_reg
, pp
);
1681 POSTING_READ(pp_ctrl_reg
);
1683 pps_unlock(intel_dp
);
1686 /* Enable backlight PWM and backlight PP control. */
1687 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1689 if (!is_edp(intel_dp
))
1692 DRM_DEBUG_KMS("\n");
1694 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1695 _intel_edp_backlight_on(intel_dp
);
1698 /* Disable backlight in the panel power control. */
1699 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1701 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1706 if (!is_edp(intel_dp
))
1711 pp
= ironlake_get_pp_control(intel_dp
);
1712 pp
&= ~EDP_BLC_ENABLE
;
1714 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1716 I915_WRITE(pp_ctrl_reg
, pp
);
1717 POSTING_READ(pp_ctrl_reg
);
1719 pps_unlock(intel_dp
);
1721 intel_dp
->last_backlight_off
= jiffies
;
1722 edp_wait_backlight_off(intel_dp
);
1725 /* Disable backlight PP control and backlight PWM. */
1726 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1728 if (!is_edp(intel_dp
))
1731 DRM_DEBUG_KMS("\n");
1733 _intel_edp_backlight_off(intel_dp
);
1734 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1738 * Hook for controlling the panel power control backlight through the bl_power
1739 * sysfs attribute. Take care to handle multiple calls.
1741 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1744 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1748 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1749 pps_unlock(intel_dp
);
1751 if (is_enabled
== enable
)
1754 DRM_DEBUG_KMS("panel power control backlight %s\n",
1755 enable
? "enable" : "disable");
1758 _intel_edp_backlight_on(intel_dp
);
1760 _intel_edp_backlight_off(intel_dp
);
1763 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1765 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1766 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1767 struct drm_device
*dev
= crtc
->dev
;
1768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 assert_pipe_disabled(dev_priv
,
1772 to_intel_crtc(crtc
)->pipe
);
1774 DRM_DEBUG_KMS("\n");
1775 dpa_ctl
= I915_READ(DP_A
);
1776 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1777 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1779 /* We don't adjust intel_dp->DP while tearing down the link, to
1780 * facilitate link retraining (e.g. after hotplug). Hence clear all
1781 * enable bits here to ensure that we don't enable too much. */
1782 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1783 intel_dp
->DP
|= DP_PLL_ENABLE
;
1784 I915_WRITE(DP_A
, intel_dp
->DP
);
1789 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1791 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1792 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1793 struct drm_device
*dev
= crtc
->dev
;
1794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1797 assert_pipe_disabled(dev_priv
,
1798 to_intel_crtc(crtc
)->pipe
);
1800 dpa_ctl
= I915_READ(DP_A
);
1801 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1802 "dp pll off, should be on\n");
1803 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1805 /* We can't rely on the value tracked for the DP register in
1806 * intel_dp->DP because link_down must not change that (otherwise link
1807 * re-training will fail. */
1808 dpa_ctl
&= ~DP_PLL_ENABLE
;
1809 I915_WRITE(DP_A
, dpa_ctl
);
1814 /* If the sink supports it, try to set the power state appropriately */
1815 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1819 /* Should have a valid DPCD by this point */
1820 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1823 if (mode
!= DRM_MODE_DPMS_ON
) {
1824 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1828 * When turning on, we need to retry for 1ms to give the sink
1831 for (i
= 0; i
< 3; i
++) {
1832 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1841 DRM_DEBUG_KMS("failed to %s sink power state\n",
1842 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1845 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1848 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1849 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1850 struct drm_device
*dev
= encoder
->base
.dev
;
1851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1852 enum intel_display_power_domain power_domain
;
1855 power_domain
= intel_display_port_power_domain(encoder
);
1856 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1859 tmp
= I915_READ(intel_dp
->output_reg
);
1861 if (!(tmp
& DP_PORT_EN
))
1864 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1865 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1866 } else if (IS_CHERRYVIEW(dev
)) {
1867 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1868 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1869 *pipe
= PORT_TO_PIPE(tmp
);
1875 switch (intel_dp
->output_reg
) {
1877 trans_sel
= TRANS_DP_PORT_SEL_B
;
1880 trans_sel
= TRANS_DP_PORT_SEL_C
;
1883 trans_sel
= TRANS_DP_PORT_SEL_D
;
1889 for_each_pipe(dev_priv
, i
) {
1890 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1891 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1897 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1898 intel_dp
->output_reg
);
1904 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1905 struct intel_crtc_config
*pipe_config
)
1907 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1909 struct drm_device
*dev
= encoder
->base
.dev
;
1910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1911 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1912 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1915 tmp
= I915_READ(intel_dp
->output_reg
);
1916 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1917 pipe_config
->has_audio
= true;
1919 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1920 if (tmp
& DP_SYNC_HS_HIGH
)
1921 flags
|= DRM_MODE_FLAG_PHSYNC
;
1923 flags
|= DRM_MODE_FLAG_NHSYNC
;
1925 if (tmp
& DP_SYNC_VS_HIGH
)
1926 flags
|= DRM_MODE_FLAG_PVSYNC
;
1928 flags
|= DRM_MODE_FLAG_NVSYNC
;
1930 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1931 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1932 flags
|= DRM_MODE_FLAG_PHSYNC
;
1934 flags
|= DRM_MODE_FLAG_NHSYNC
;
1936 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1937 flags
|= DRM_MODE_FLAG_PVSYNC
;
1939 flags
|= DRM_MODE_FLAG_NVSYNC
;
1942 pipe_config
->adjusted_mode
.flags
|= flags
;
1944 pipe_config
->has_dp_encoder
= true;
1946 intel_dp_get_m_n(crtc
, pipe_config
);
1948 if (port
== PORT_A
) {
1949 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1950 pipe_config
->port_clock
= 162000;
1952 pipe_config
->port_clock
= 270000;
1955 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1956 &pipe_config
->dp_m_n
);
1958 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1959 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1961 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1963 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1964 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1966 * This is a big fat ugly hack.
1968 * Some machines in UEFI boot mode provide us a VBT that has 18
1969 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1970 * unknown we fail to light up. Yet the same BIOS boots up with
1971 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1972 * max, not what it tells us to use.
1974 * Note: This will still be broken if the eDP panel is not lit
1975 * up by the BIOS, and thus we can't get the mode at module
1978 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1979 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1980 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1984 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1986 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1989 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1996 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1999 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
2000 struct edp_vsc_psr
*vsc_psr
)
2002 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2003 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2005 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
2006 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
2007 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
2008 uint32_t *data
= (uint32_t *) vsc_psr
;
2011 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2012 the video DIP being updated before program video DIP data buffer
2013 registers for DIP being updated. */
2014 I915_WRITE(ctl_reg
, 0);
2015 POSTING_READ(ctl_reg
);
2017 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
2018 if (i
< sizeof(struct edp_vsc_psr
))
2019 I915_WRITE(data_reg
+ i
, *data
++);
2021 I915_WRITE(data_reg
+ i
, 0);
2024 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
2025 POSTING_READ(ctl_reg
);
2028 static void intel_edp_psr_setup_vsc(struct intel_dp
*intel_dp
)
2030 struct edp_vsc_psr psr_vsc
;
2032 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2033 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
2034 psr_vsc
.sdp_header
.HB0
= 0;
2035 psr_vsc
.sdp_header
.HB1
= 0x7;
2036 psr_vsc
.sdp_header
.HB2
= 0x2;
2037 psr_vsc
.sdp_header
.HB3
= 0x8;
2038 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
2041 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2043 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2044 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2046 uint32_t aux_clock_divider
;
2047 int precharge
= 0x3;
2048 bool only_standby
= false;
2049 static const uint8_t aux_msg
[] = {
2050 [0] = DP_AUX_NATIVE_WRITE
<< 4,
2051 [1] = DP_SET_POWER
>> 8,
2052 [2] = DP_SET_POWER
& 0xff,
2054 [4] = DP_SET_POWER_D0
,
2058 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
2060 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2062 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2063 only_standby
= true;
2065 /* Enable PSR in sink */
2066 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2067 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2068 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2070 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2071 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2073 /* Setup AUX registers */
2074 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
2075 I915_WRITE(EDP_PSR_AUX_DATA1(dev
) + i
,
2076 pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
2078 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2079 DP_AUX_CH_CTL_TIME_OUT_400us
|
2080 (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2081 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2082 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2085 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2087 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2088 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2090 uint32_t max_sleep_time
= 0x1f;
2091 uint32_t idle_frames
= 1;
2093 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2094 bool only_standby
= false;
2096 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2097 only_standby
= true;
2099 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2100 val
|= EDP_PSR_LINK_STANDBY
;
2101 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2102 val
|= EDP_PSR_TP1_TIME_0us
;
2103 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2104 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2106 val
|= EDP_PSR_LINK_DISABLE
;
2108 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2109 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2110 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2111 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2115 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2117 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2118 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2120 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2121 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2123 lockdep_assert_held(&dev_priv
->psr
.lock
);
2124 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2125 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2127 dev_priv
->psr
.source_ok
= false;
2129 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2130 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2134 if (!i915
.enable_psr
) {
2135 DRM_DEBUG_KMS("PSR disable by flag\n");
2139 /* Below limitations aren't valid for Broadwell */
2140 if (IS_BROADWELL(dev
))
2143 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2145 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2149 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2150 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2155 dev_priv
->psr
.source_ok
= true;
2159 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2161 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2162 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2165 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2166 WARN_ON(dev_priv
->psr
.active
);
2167 lockdep_assert_held(&dev_priv
->psr
.lock
);
2169 /* Enable/Re-enable PSR on the host */
2170 intel_edp_psr_enable_source(intel_dp
);
2172 dev_priv
->psr
.active
= true;
2175 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2177 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2180 if (!HAS_PSR(dev
)) {
2181 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2185 if (!is_edp_psr(intel_dp
)) {
2186 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2190 mutex_lock(&dev_priv
->psr
.lock
);
2191 if (dev_priv
->psr
.enabled
) {
2192 DRM_DEBUG_KMS("PSR already in use\n");
2196 if (!intel_edp_psr_match_conditions(intel_dp
))
2199 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2201 intel_edp_psr_setup_vsc(intel_dp
);
2203 /* Avoid continuous PSR exit by masking memup and hpd */
2204 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
2205 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
2207 /* Enable PSR on the panel */
2208 intel_edp_psr_enable_sink(intel_dp
);
2210 dev_priv
->psr
.enabled
= intel_dp
;
2212 mutex_unlock(&dev_priv
->psr
.lock
);
2215 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2217 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2220 mutex_lock(&dev_priv
->psr
.lock
);
2221 if (!dev_priv
->psr
.enabled
) {
2222 mutex_unlock(&dev_priv
->psr
.lock
);
2226 if (dev_priv
->psr
.active
) {
2227 I915_WRITE(EDP_PSR_CTL(dev
),
2228 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2230 /* Wait till PSR is idle */
2231 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2232 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2233 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2235 dev_priv
->psr
.active
= false;
2237 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2240 dev_priv
->psr
.enabled
= NULL
;
2241 mutex_unlock(&dev_priv
->psr
.lock
);
2243 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2246 static void intel_edp_psr_work(struct work_struct
*work
)
2248 struct drm_i915_private
*dev_priv
=
2249 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2250 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2252 /* We have to make sure PSR is ready for re-enable
2253 * otherwise it keeps disabled until next full enable/disable cycle.
2254 * PSR might take some time to get fully disabled
2255 * and be ready for re-enable.
2257 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv
->dev
)) &
2258 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
2259 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2263 mutex_lock(&dev_priv
->psr
.lock
);
2264 intel_dp
= dev_priv
->psr
.enabled
;
2270 * The delayed work can race with an invalidate hence we need to
2271 * recheck. Since psr_flush first clears this and then reschedules we
2272 * won't ever miss a flush when bailing out here.
2274 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2277 intel_edp_psr_do_enable(intel_dp
);
2279 mutex_unlock(&dev_priv
->psr
.lock
);
2282 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2286 if (dev_priv
->psr
.active
) {
2287 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2289 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2291 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2293 dev_priv
->psr
.active
= false;
2298 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2299 unsigned frontbuffer_bits
)
2301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2302 struct drm_crtc
*crtc
;
2305 mutex_lock(&dev_priv
->psr
.lock
);
2306 if (!dev_priv
->psr
.enabled
) {
2307 mutex_unlock(&dev_priv
->psr
.lock
);
2311 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2312 pipe
= to_intel_crtc(crtc
)->pipe
;
2314 intel_edp_psr_do_exit(dev
);
2316 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2318 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2319 mutex_unlock(&dev_priv
->psr
.lock
);
2322 void intel_edp_psr_flush(struct drm_device
*dev
,
2323 unsigned frontbuffer_bits
)
2325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2326 struct drm_crtc
*crtc
;
2329 mutex_lock(&dev_priv
->psr
.lock
);
2330 if (!dev_priv
->psr
.enabled
) {
2331 mutex_unlock(&dev_priv
->psr
.lock
);
2335 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2336 pipe
= to_intel_crtc(crtc
)->pipe
;
2337 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2340 * On Haswell sprite plane updates don't result in a psr invalidating
2341 * signal in the hardware. Which means we need to manually fake this in
2342 * software for all flushes, not just when we've seen a preceding
2343 * invalidation through frontbuffer rendering.
2345 if (IS_HASWELL(dev
) &&
2346 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2347 intel_edp_psr_do_exit(dev
);
2349 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2350 schedule_delayed_work(&dev_priv
->psr
.work
,
2351 msecs_to_jiffies(100));
2352 mutex_unlock(&dev_priv
->psr
.lock
);
2355 void intel_edp_psr_init(struct drm_device
*dev
)
2357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2359 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2360 mutex_init(&dev_priv
->psr
.lock
);
2363 static void intel_disable_dp(struct intel_encoder
*encoder
)
2365 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2366 struct drm_device
*dev
= encoder
->base
.dev
;
2368 /* Make sure the panel is off before trying to change the mode. But also
2369 * ensure that we have vdd while we switch off the panel. */
2370 intel_edp_panel_vdd_on(intel_dp
);
2371 intel_edp_backlight_off(intel_dp
);
2372 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2373 intel_edp_panel_off(intel_dp
);
2375 /* disable the port before the pipe on g4x */
2376 if (INTEL_INFO(dev
)->gen
< 5)
2377 intel_dp_link_down(intel_dp
);
2380 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2382 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2383 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2385 intel_dp_link_down(intel_dp
);
2387 ironlake_edp_pll_off(intel_dp
);
2390 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2392 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2394 intel_dp_link_down(intel_dp
);
2397 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2399 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2400 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2401 struct drm_device
*dev
= encoder
->base
.dev
;
2402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2403 struct intel_crtc
*intel_crtc
=
2404 to_intel_crtc(encoder
->base
.crtc
);
2405 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2406 enum pipe pipe
= intel_crtc
->pipe
;
2409 intel_dp_link_down(intel_dp
);
2411 mutex_lock(&dev_priv
->dpio_lock
);
2413 /* Propagate soft reset to data lane reset */
2414 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2415 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2416 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2418 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2419 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2420 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2422 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2423 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2424 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2426 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2427 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2428 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2430 mutex_unlock(&dev_priv
->dpio_lock
);
2434 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2436 uint8_t dp_train_pat
)
2438 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2439 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2441 enum port port
= intel_dig_port
->port
;
2444 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2446 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2447 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2449 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2451 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2452 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2453 case DP_TRAINING_PATTERN_DISABLE
:
2454 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2457 case DP_TRAINING_PATTERN_1
:
2458 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2460 case DP_TRAINING_PATTERN_2
:
2461 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2463 case DP_TRAINING_PATTERN_3
:
2464 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2467 I915_WRITE(DP_TP_CTL(port
), temp
);
2469 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2470 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2472 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2473 case DP_TRAINING_PATTERN_DISABLE
:
2474 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2476 case DP_TRAINING_PATTERN_1
:
2477 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2479 case DP_TRAINING_PATTERN_2
:
2480 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2482 case DP_TRAINING_PATTERN_3
:
2483 DRM_ERROR("DP training pattern 3 not supported\n");
2484 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2489 if (IS_CHERRYVIEW(dev
))
2490 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2492 *DP
&= ~DP_LINK_TRAIN_MASK
;
2494 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2495 case DP_TRAINING_PATTERN_DISABLE
:
2496 *DP
|= DP_LINK_TRAIN_OFF
;
2498 case DP_TRAINING_PATTERN_1
:
2499 *DP
|= DP_LINK_TRAIN_PAT_1
;
2501 case DP_TRAINING_PATTERN_2
:
2502 *DP
|= DP_LINK_TRAIN_PAT_2
;
2504 case DP_TRAINING_PATTERN_3
:
2505 if (IS_CHERRYVIEW(dev
)) {
2506 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2508 DRM_ERROR("DP training pattern 3 not supported\n");
2509 *DP
|= DP_LINK_TRAIN_PAT_2
;
2516 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2518 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2521 intel_dp
->DP
|= DP_PORT_EN
;
2523 /* enable with pattern 1 (as per spec) */
2524 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2525 DP_TRAINING_PATTERN_1
);
2527 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2528 POSTING_READ(intel_dp
->output_reg
);
2531 static void intel_enable_dp(struct intel_encoder
*encoder
)
2533 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2534 struct drm_device
*dev
= encoder
->base
.dev
;
2535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2536 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2538 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2541 intel_dp_enable_port(intel_dp
);
2542 intel_edp_panel_vdd_on(intel_dp
);
2543 intel_edp_panel_on(intel_dp
);
2544 intel_edp_panel_vdd_off(intel_dp
, true);
2545 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2546 intel_dp_start_link_train(intel_dp
);
2547 intel_dp_complete_link_train(intel_dp
);
2548 intel_dp_stop_link_train(intel_dp
);
2551 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2553 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2555 intel_enable_dp(encoder
);
2556 intel_edp_backlight_on(intel_dp
);
2559 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2561 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2563 intel_edp_backlight_on(intel_dp
);
2566 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2568 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2569 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2571 intel_dp_prepare(encoder
);
2573 /* Only ilk+ has port A */
2574 if (dport
->port
== PORT_A
) {
2575 ironlake_set_pll_cpu_edp(intel_dp
);
2576 ironlake_edp_pll_on(intel_dp
);
2580 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2584 struct intel_encoder
*encoder
;
2586 lockdep_assert_held(&dev_priv
->pps_mutex
);
2588 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2590 struct intel_dp
*intel_dp
;
2593 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2596 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2597 port
= dp_to_dig_port(intel_dp
)->port
;
2599 if (intel_dp
->pps_pipe
!= pipe
)
2602 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2603 pipe_name(pipe
), port_name(port
));
2605 /* make sure vdd is off before we steal it */
2606 edp_panel_vdd_off_sync(intel_dp
);
2608 intel_dp
->pps_pipe
= INVALID_PIPE
;
2612 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2614 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2615 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2616 struct drm_device
*dev
= encoder
->base
.dev
;
2617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2618 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2619 struct edp_power_seq power_seq
;
2621 lockdep_assert_held(&dev_priv
->pps_mutex
);
2623 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2627 * If another power sequencer was being used on this
2628 * port previously make sure to turn off vdd there while
2629 * we still have control of it.
2631 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2632 edp_panel_vdd_off_sync(intel_dp
);
2635 * We may be stealing the power
2636 * sequencer from another port.
2638 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2640 /* now it's all ours */
2641 intel_dp
->pps_pipe
= crtc
->pipe
;
2643 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2644 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2646 /* init power sequencer on this pipe and port */
2647 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2648 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2652 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2654 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2655 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2656 struct drm_device
*dev
= encoder
->base
.dev
;
2657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2658 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2659 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2660 int pipe
= intel_crtc
->pipe
;
2663 mutex_lock(&dev_priv
->dpio_lock
);
2665 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2672 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2673 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2674 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2676 mutex_unlock(&dev_priv
->dpio_lock
);
2678 if (is_edp(intel_dp
)) {
2680 vlv_init_panel_power_sequencer(intel_dp
);
2681 pps_unlock(intel_dp
);
2684 intel_enable_dp(encoder
);
2686 vlv_wait_port_ready(dev_priv
, dport
);
2689 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2691 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2692 struct drm_device
*dev
= encoder
->base
.dev
;
2693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2694 struct intel_crtc
*intel_crtc
=
2695 to_intel_crtc(encoder
->base
.crtc
);
2696 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2697 int pipe
= intel_crtc
->pipe
;
2699 intel_dp_prepare(encoder
);
2701 /* Program Tx lane resets to default */
2702 mutex_lock(&dev_priv
->dpio_lock
);
2703 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2704 DPIO_PCS_TX_LANE2_RESET
|
2705 DPIO_PCS_TX_LANE1_RESET
);
2706 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2707 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2708 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2709 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2710 DPIO_PCS_CLK_SOFT_RESET
);
2712 /* Fix up inter-pair skew failure */
2713 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2714 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2715 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2716 mutex_unlock(&dev_priv
->dpio_lock
);
2719 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2721 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2722 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2723 struct drm_device
*dev
= encoder
->base
.dev
;
2724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2725 struct intel_crtc
*intel_crtc
=
2726 to_intel_crtc(encoder
->base
.crtc
);
2727 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2728 int pipe
= intel_crtc
->pipe
;
2732 mutex_lock(&dev_priv
->dpio_lock
);
2734 /* Deassert soft data lane reset*/
2735 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2736 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2737 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2739 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2740 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2741 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2743 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2744 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2745 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2747 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2748 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2749 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2751 /* Program Tx lane latency optimal setting*/
2752 for (i
= 0; i
< 4; i
++) {
2753 /* Set the latency optimal bit */
2754 data
= (i
== 1) ? 0x0 : 0x6;
2755 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2756 data
<< DPIO_FRC_LATENCY_SHFIT
);
2758 /* Set the upar bit */
2759 data
= (i
== 1) ? 0x0 : 0x1;
2760 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2761 data
<< DPIO_UPAR_SHIFT
);
2764 /* Data lane stagger programming */
2765 /* FIXME: Fix up value only after power analysis */
2767 mutex_unlock(&dev_priv
->dpio_lock
);
2769 if (is_edp(intel_dp
)) {
2771 vlv_init_panel_power_sequencer(intel_dp
);
2772 pps_unlock(intel_dp
);
2775 intel_enable_dp(encoder
);
2777 vlv_wait_port_ready(dev_priv
, dport
);
2780 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2782 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2783 struct drm_device
*dev
= encoder
->base
.dev
;
2784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2785 struct intel_crtc
*intel_crtc
=
2786 to_intel_crtc(encoder
->base
.crtc
);
2787 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2788 enum pipe pipe
= intel_crtc
->pipe
;
2791 intel_dp_prepare(encoder
);
2793 mutex_lock(&dev_priv
->dpio_lock
);
2795 /* program left/right clock distribution */
2796 if (pipe
!= PIPE_B
) {
2797 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2798 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2800 val
|= CHV_BUFLEFTENA1_FORCE
;
2802 val
|= CHV_BUFRIGHTENA1_FORCE
;
2803 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2805 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2806 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2808 val
|= CHV_BUFLEFTENA2_FORCE
;
2810 val
|= CHV_BUFRIGHTENA2_FORCE
;
2811 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2814 /* program clock channel usage */
2815 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2816 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2818 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2820 val
|= CHV_PCS_USEDCLKCHANNEL
;
2821 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2823 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2824 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2826 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2828 val
|= CHV_PCS_USEDCLKCHANNEL
;
2829 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2832 * This a a bit weird since generally CL
2833 * matches the pipe, but here we need to
2834 * pick the CL based on the port.
2836 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2838 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2840 val
|= CHV_CMN_USEDCLKCHANNEL
;
2841 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2843 mutex_unlock(&dev_priv
->dpio_lock
);
2847 * Native read with retry for link status and receiver capability reads for
2848 * cases where the sink may still be asleep.
2850 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2851 * supposed to retry 3 times per the spec.
2854 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2855 void *buffer
, size_t size
)
2860 for (i
= 0; i
< 3; i
++) {
2861 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2871 * Fetch AUX CH registers 0x202 - 0x207 which contain
2872 * link status information
2875 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2877 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2880 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2883 /* These are source-specific values. */
2885 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2887 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2888 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2890 if (INTEL_INFO(dev
)->gen
>= 9)
2891 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2892 else if (IS_VALLEYVIEW(dev
))
2893 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2894 else if (IS_GEN7(dev
) && port
== PORT_A
)
2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2896 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2903 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2905 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2906 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2908 if (INTEL_INFO(dev
)->gen
>= 9) {
2909 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2911 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2913 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2915 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2917 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2919 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2920 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2922 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2923 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2924 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2926 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2929 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2931 } else if (IS_VALLEYVIEW(dev
)) {
2932 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2943 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2944 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2946 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2951 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2954 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2956 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2958 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2960 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2968 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2970 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2972 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2973 struct intel_crtc
*intel_crtc
=
2974 to_intel_crtc(dport
->base
.base
.crtc
);
2975 unsigned long demph_reg_value
, preemph_reg_value
,
2976 uniqtranscale_reg_value
;
2977 uint8_t train_set
= intel_dp
->train_set
[0];
2978 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2979 int pipe
= intel_crtc
->pipe
;
2981 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2982 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2983 preemph_reg_value
= 0x0004000;
2984 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2986 demph_reg_value
= 0x2B405555;
2987 uniqtranscale_reg_value
= 0x552AB83A;
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2990 demph_reg_value
= 0x2B404040;
2991 uniqtranscale_reg_value
= 0x5548B83A;
2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2994 demph_reg_value
= 0x2B245555;
2995 uniqtranscale_reg_value
= 0x5560B83A;
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2998 demph_reg_value
= 0x2B405555;
2999 uniqtranscale_reg_value
= 0x5598DA3A;
3005 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3006 preemph_reg_value
= 0x0002000;
3007 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3009 demph_reg_value
= 0x2B404040;
3010 uniqtranscale_reg_value
= 0x5552B83A;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3013 demph_reg_value
= 0x2B404848;
3014 uniqtranscale_reg_value
= 0x5580B83A;
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3017 demph_reg_value
= 0x2B404040;
3018 uniqtranscale_reg_value
= 0x55ADDA3A;
3024 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3025 preemph_reg_value
= 0x0000000;
3026 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3028 demph_reg_value
= 0x2B305555;
3029 uniqtranscale_reg_value
= 0x5570B83A;
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3032 demph_reg_value
= 0x2B2B4040;
3033 uniqtranscale_reg_value
= 0x55ADDA3A;
3039 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3040 preemph_reg_value
= 0x0006000;
3041 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3043 demph_reg_value
= 0x1B405555;
3044 uniqtranscale_reg_value
= 0x55ADDA3A;
3054 mutex_lock(&dev_priv
->dpio_lock
);
3055 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3056 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3057 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3058 uniqtranscale_reg_value
);
3059 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3060 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3061 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3062 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3063 mutex_unlock(&dev_priv
->dpio_lock
);
3068 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3070 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3072 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3073 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3074 u32 deemph_reg_value
, margin_reg_value
, val
;
3075 uint8_t train_set
= intel_dp
->train_set
[0];
3076 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3077 enum pipe pipe
= intel_crtc
->pipe
;
3080 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3081 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3082 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3084 deemph_reg_value
= 128;
3085 margin_reg_value
= 52;
3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3088 deemph_reg_value
= 128;
3089 margin_reg_value
= 77;
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3092 deemph_reg_value
= 128;
3093 margin_reg_value
= 102;
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3096 deemph_reg_value
= 128;
3097 margin_reg_value
= 154;
3098 /* FIXME extra to set for 1200 */
3104 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3105 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3107 deemph_reg_value
= 85;
3108 margin_reg_value
= 78;
3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3111 deemph_reg_value
= 85;
3112 margin_reg_value
= 116;
3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3115 deemph_reg_value
= 85;
3116 margin_reg_value
= 154;
3122 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3123 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3125 deemph_reg_value
= 64;
3126 margin_reg_value
= 104;
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3129 deemph_reg_value
= 64;
3130 margin_reg_value
= 154;
3136 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3137 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3139 deemph_reg_value
= 43;
3140 margin_reg_value
= 154;
3150 mutex_lock(&dev_priv
->dpio_lock
);
3152 /* Clear calc init */
3153 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3154 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3155 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3157 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3158 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3159 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3161 /* Program swing deemph */
3162 for (i
= 0; i
< 4; i
++) {
3163 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3164 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3165 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3166 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3169 /* Program swing margin */
3170 for (i
= 0; i
< 4; i
++) {
3171 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3172 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3173 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3174 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3177 /* Disable unique transition scale */
3178 for (i
= 0; i
< 4; i
++) {
3179 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3180 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3181 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3184 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3185 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3186 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3187 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3190 * The document said it needs to set bit 27 for ch0 and bit 26
3191 * for ch1. Might be a typo in the doc.
3192 * For now, for this unique transition scale selection, set bit
3193 * 27 for ch0 and ch1.
3195 for (i
= 0; i
< 4; i
++) {
3196 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3197 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3198 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3201 for (i
= 0; i
< 4; i
++) {
3202 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3203 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3204 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3205 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3209 /* Start swing calculation */
3210 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3211 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3212 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3214 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3215 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3216 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3219 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3220 val
|= DPIO_LRC_BYPASS
;
3221 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3223 mutex_unlock(&dev_priv
->dpio_lock
);
3229 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3230 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3235 uint8_t voltage_max
;
3236 uint8_t preemph_max
;
3238 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3239 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3240 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3248 voltage_max
= intel_dp_voltage_max(intel_dp
);
3249 if (v
>= voltage_max
)
3250 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3252 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3253 if (p
>= preemph_max
)
3254 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3256 for (lane
= 0; lane
< 4; lane
++)
3257 intel_dp
->train_set
[lane
] = v
| p
;
3261 intel_gen4_signal_levels(uint8_t train_set
)
3263 uint32_t signal_levels
= 0;
3265 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3268 signal_levels
|= DP_VOLTAGE_0_4
;
3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3271 signal_levels
|= DP_VOLTAGE_0_6
;
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3274 signal_levels
|= DP_VOLTAGE_0_8
;
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3277 signal_levels
|= DP_VOLTAGE_1_2
;
3280 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3281 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3283 signal_levels
|= DP_PRE_EMPHASIS_0
;
3285 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3286 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3288 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3289 signal_levels
|= DP_PRE_EMPHASIS_6
;
3291 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3292 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3295 return signal_levels
;
3298 /* Gen6's DP voltage swing and pre-emphasis control */
3300 intel_gen6_edp_signal_levels(uint8_t train_set
)
3302 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3303 DP_TRAIN_PRE_EMPHASIS_MASK
);
3304 switch (signal_levels
) {
3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3307 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3309 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3312 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3315 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3318 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3320 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3321 "0x%x\n", signal_levels
);
3322 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3326 /* Gen7's DP voltage swing and pre-emphasis control */
3328 intel_gen7_edp_signal_levels(uint8_t train_set
)
3330 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3331 DP_TRAIN_PRE_EMPHASIS_MASK
);
3332 switch (signal_levels
) {
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3334 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3336 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3338 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3341 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3343 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3346 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3347 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3348 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3351 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3352 "0x%x\n", signal_levels
);
3353 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3357 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3359 intel_hsw_signal_levels(uint8_t train_set
)
3361 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3362 DP_TRAIN_PRE_EMPHASIS_MASK
);
3363 switch (signal_levels
) {
3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3365 return DDI_BUF_TRANS_SELECT(0);
3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3367 return DDI_BUF_TRANS_SELECT(1);
3368 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3369 return DDI_BUF_TRANS_SELECT(2);
3370 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3371 return DDI_BUF_TRANS_SELECT(3);
3373 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3374 return DDI_BUF_TRANS_SELECT(4);
3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3376 return DDI_BUF_TRANS_SELECT(5);
3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3378 return DDI_BUF_TRANS_SELECT(6);
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3381 return DDI_BUF_TRANS_SELECT(7);
3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3383 return DDI_BUF_TRANS_SELECT(8);
3385 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3386 "0x%x\n", signal_levels
);
3387 return DDI_BUF_TRANS_SELECT(0);
3391 /* Properly updates "DP" with the correct signal levels. */
3393 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3396 enum port port
= intel_dig_port
->port
;
3397 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3398 uint32_t signal_levels
, mask
;
3399 uint8_t train_set
= intel_dp
->train_set
[0];
3401 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3402 signal_levels
= intel_hsw_signal_levels(train_set
);
3403 mask
= DDI_BUF_EMP_MASK
;
3404 } else if (IS_CHERRYVIEW(dev
)) {
3405 signal_levels
= intel_chv_signal_levels(intel_dp
);
3407 } else if (IS_VALLEYVIEW(dev
)) {
3408 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3410 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3411 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3412 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3413 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3414 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3415 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3417 signal_levels
= intel_gen4_signal_levels(train_set
);
3418 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3421 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3423 *DP
= (*DP
& ~mask
) | signal_levels
;
3427 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3429 uint8_t dp_train_pat
)
3431 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3432 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3434 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3437 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3439 I915_WRITE(intel_dp
->output_reg
, *DP
);
3440 POSTING_READ(intel_dp
->output_reg
);
3442 buf
[0] = dp_train_pat
;
3443 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3444 DP_TRAINING_PATTERN_DISABLE
) {
3445 /* don't write DP_TRAINING_LANEx_SET on disable */
3448 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3449 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3450 len
= intel_dp
->lane_count
+ 1;
3453 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3460 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3461 uint8_t dp_train_pat
)
3463 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3464 intel_dp_set_signal_levels(intel_dp
, DP
);
3465 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3469 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3470 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3472 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3473 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3477 intel_get_adjust_train(intel_dp
, link_status
);
3478 intel_dp_set_signal_levels(intel_dp
, DP
);
3480 I915_WRITE(intel_dp
->output_reg
, *DP
);
3481 POSTING_READ(intel_dp
->output_reg
);
3483 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3484 intel_dp
->train_set
, intel_dp
->lane_count
);
3486 return ret
== intel_dp
->lane_count
;
3489 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3491 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3492 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3494 enum port port
= intel_dig_port
->port
;
3500 val
= I915_READ(DP_TP_CTL(port
));
3501 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3502 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3503 I915_WRITE(DP_TP_CTL(port
), val
);
3506 * On PORT_A we can have only eDP in SST mode. There the only reason
3507 * we need to set idle transmission mode is to work around a HW issue
3508 * where we enable the pipe while not in idle link-training mode.
3509 * In this case there is requirement to wait for a minimum number of
3510 * idle patterns to be sent.
3515 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3517 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3520 /* Enable corresponding port and start training pattern 1 */
3522 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3524 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3525 struct drm_device
*dev
= encoder
->dev
;
3528 int voltage_tries
, loop_tries
;
3529 uint32_t DP
= intel_dp
->DP
;
3530 uint8_t link_config
[2];
3533 intel_ddi_prepare_link_retrain(encoder
);
3535 /* Write the link configuration data */
3536 link_config
[0] = intel_dp
->link_bw
;
3537 link_config
[1] = intel_dp
->lane_count
;
3538 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3539 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3540 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3543 link_config
[1] = DP_SET_ANSI_8B10B
;
3544 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3548 /* clock recovery */
3549 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3550 DP_TRAINING_PATTERN_1
|
3551 DP_LINK_SCRAMBLING_DISABLE
)) {
3552 DRM_ERROR("failed to enable link training\n");
3560 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3562 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3563 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3564 DRM_ERROR("failed to get link status\n");
3568 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3569 DRM_DEBUG_KMS("clock recovery OK\n");
3573 /* Check to see if we've tried the max voltage */
3574 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3575 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3577 if (i
== intel_dp
->lane_count
) {
3579 if (loop_tries
== 5) {
3580 DRM_ERROR("too many full retries, give up\n");
3583 intel_dp_reset_link_train(intel_dp
, &DP
,
3584 DP_TRAINING_PATTERN_1
|
3585 DP_LINK_SCRAMBLING_DISABLE
);
3590 /* Check to see if we've tried the same voltage 5 times */
3591 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3593 if (voltage_tries
== 5) {
3594 DRM_ERROR("too many voltage retries, give up\n");
3599 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3601 /* Update training set as requested by target */
3602 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3603 DRM_ERROR("failed to update link training\n");
3612 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3614 bool channel_eq
= false;
3615 int tries
, cr_tries
;
3616 uint32_t DP
= intel_dp
->DP
;
3617 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3619 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3620 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3621 training_pattern
= DP_TRAINING_PATTERN_3
;
3623 /* channel equalization */
3624 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3626 DP_LINK_SCRAMBLING_DISABLE
)) {
3627 DRM_ERROR("failed to start channel equalization\n");
3635 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3638 DRM_ERROR("failed to train DP, aborting\n");
3642 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3643 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3644 DRM_ERROR("failed to get link status\n");
3648 /* Make sure clock is still ok */
3649 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3650 intel_dp_start_link_train(intel_dp
);
3651 intel_dp_set_link_train(intel_dp
, &DP
,
3653 DP_LINK_SCRAMBLING_DISABLE
);
3658 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3663 /* Try 5 times, then try clock recovery if that fails */
3665 intel_dp_link_down(intel_dp
);
3666 intel_dp_start_link_train(intel_dp
);
3667 intel_dp_set_link_train(intel_dp
, &DP
,
3669 DP_LINK_SCRAMBLING_DISABLE
);
3675 /* Update training set as requested by target */
3676 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3677 DRM_ERROR("failed to update link training\n");
3683 intel_dp_set_idle_link_train(intel_dp
);
3688 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3692 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3694 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3695 DP_TRAINING_PATTERN_DISABLE
);
3699 intel_dp_link_down(struct intel_dp
*intel_dp
)
3701 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3702 enum port port
= intel_dig_port
->port
;
3703 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3705 struct intel_crtc
*intel_crtc
=
3706 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3707 uint32_t DP
= intel_dp
->DP
;
3709 if (WARN_ON(HAS_DDI(dev
)))
3712 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3715 DRM_DEBUG_KMS("\n");
3717 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3718 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3719 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3721 if (IS_CHERRYVIEW(dev
))
3722 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3724 DP
&= ~DP_LINK_TRAIN_MASK
;
3725 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3727 POSTING_READ(intel_dp
->output_reg
);
3729 if (HAS_PCH_IBX(dev
) &&
3730 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3731 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3733 /* Hardware workaround: leaving our transcoder select
3734 * set to transcoder B while it's off will prevent the
3735 * corresponding HDMI output on transcoder A.
3737 * Combine this with another hardware workaround:
3738 * transcoder select bit can only be cleared while the
3741 DP
&= ~DP_PIPEB_SELECT
;
3742 I915_WRITE(intel_dp
->output_reg
, DP
);
3744 /* Changes to enable or select take place the vblank
3745 * after being written.
3747 if (WARN_ON(crtc
== NULL
)) {
3748 /* We should never try to disable a port without a crtc
3749 * attached. For paranoia keep the code around for a
3751 POSTING_READ(intel_dp
->output_reg
);
3754 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3757 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3758 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3759 POSTING_READ(intel_dp
->output_reg
);
3760 msleep(intel_dp
->panel_power_down_delay
);
3764 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3766 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3767 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3770 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3771 sizeof(intel_dp
->dpcd
)) < 0)
3772 return false; /* aux transfer failed */
3774 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3776 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3777 return false; /* DPCD not present */
3779 /* Check if the panel supports PSR */
3780 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3781 if (is_edp(intel_dp
)) {
3782 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3784 sizeof(intel_dp
->psr_dpcd
));
3785 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3786 dev_priv
->psr
.sink_support
= true;
3787 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3791 /* Training Pattern 3 support */
3792 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3793 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3794 intel_dp
->use_tps3
= true;
3795 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3797 intel_dp
->use_tps3
= false;
3799 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3800 DP_DWN_STRM_PORT_PRESENT
))
3801 return true; /* native DP sink */
3803 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3804 return true; /* no per-port downstream info */
3806 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3807 intel_dp
->downstream_ports
,
3808 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3809 return false; /* downstream port status fetch failed */
3815 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3819 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3822 intel_edp_panel_vdd_on(intel_dp
);
3824 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3825 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3826 buf
[0], buf
[1], buf
[2]);
3828 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3829 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3830 buf
[0], buf
[1], buf
[2]);
3832 intel_edp_panel_vdd_off(intel_dp
, false);
3836 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3840 if (!intel_dp
->can_mst
)
3843 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3846 intel_edp_panel_vdd_on(intel_dp
);
3847 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3848 if (buf
[0] & DP_MST_CAP
) {
3849 DRM_DEBUG_KMS("Sink is MST capable\n");
3850 intel_dp
->is_mst
= true;
3852 DRM_DEBUG_KMS("Sink is not MST capable\n");
3853 intel_dp
->is_mst
= false;
3856 intel_edp_panel_vdd_off(intel_dp
, false);
3858 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3859 return intel_dp
->is_mst
;
3862 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3864 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3865 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3866 struct intel_crtc
*intel_crtc
=
3867 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3872 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3875 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3878 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3881 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3882 buf
| DP_TEST_SINK_START
) < 0)
3885 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3887 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
3890 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3891 DP_TEST_SINK_MISC
, &buf
) < 0)
3893 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3894 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
3896 if (attempts
== 0) {
3897 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3901 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3904 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3906 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3907 buf
& ~DP_TEST_SINK_START
) < 0)
3914 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3916 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3917 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3918 sink_irq_vector
, 1) == 1;
3922 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3926 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3928 sink_irq_vector
, 14);
3936 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3938 /* NAK by default */
3939 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3943 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3947 if (intel_dp
->is_mst
) {
3952 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3956 /* check link status - esi[10] = 0x200c */
3957 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3958 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3959 intel_dp_start_link_train(intel_dp
);
3960 intel_dp_complete_link_train(intel_dp
);
3961 intel_dp_stop_link_train(intel_dp
);
3964 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3965 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3968 for (retry
= 0; retry
< 3; retry
++) {
3970 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3971 DP_SINK_COUNT_ESI
+1,
3978 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3980 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3988 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3989 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3990 intel_dp
->is_mst
= false;
3991 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3992 /* send a hotplug event */
3993 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4000 * According to DP spec
4003 * 2. Configure link according to Receiver Capabilities
4004 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4005 * 4. Check link status on receipt of hot-plug interrupt
4008 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4010 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4011 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4013 u8 link_status
[DP_LINK_STATUS_SIZE
];
4015 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4017 if (!intel_encoder
->connectors_active
)
4020 if (WARN_ON(!intel_encoder
->base
.crtc
))
4023 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4026 /* Try to read receiver status if the link appears to be up */
4027 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4031 /* Now read the DPCD to see if it's actually running */
4032 if (!intel_dp_get_dpcd(intel_dp
)) {
4036 /* Try to read the source of the interrupt */
4037 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4038 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4039 /* Clear interrupt source */
4040 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4041 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4044 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4045 intel_dp_handle_test_request(intel_dp
);
4046 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4047 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4050 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4051 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4052 intel_encoder
->base
.name
);
4053 intel_dp_start_link_train(intel_dp
);
4054 intel_dp_complete_link_train(intel_dp
);
4055 intel_dp_stop_link_train(intel_dp
);
4059 /* XXX this is probably wrong for multiple downstream ports */
4060 static enum drm_connector_status
4061 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4063 uint8_t *dpcd
= intel_dp
->dpcd
;
4066 if (!intel_dp_get_dpcd(intel_dp
))
4067 return connector_status_disconnected
;
4069 /* if there's no downstream port, we're done */
4070 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4071 return connector_status_connected
;
4073 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4074 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4075 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4078 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4080 return connector_status_unknown
;
4082 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4083 : connector_status_disconnected
;
4086 /* If no HPD, poke DDC gently */
4087 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4088 return connector_status_connected
;
4090 /* Well we tried, say unknown for unreliable port types */
4091 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4092 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4093 if (type
== DP_DS_PORT_TYPE_VGA
||
4094 type
== DP_DS_PORT_TYPE_NON_EDID
)
4095 return connector_status_unknown
;
4097 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4098 DP_DWN_STRM_PORT_TYPE_MASK
;
4099 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4100 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4101 return connector_status_unknown
;
4104 /* Anything else is out of spec, warn and ignore */
4105 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4106 return connector_status_disconnected
;
4109 static enum drm_connector_status
4110 edp_detect(struct intel_dp
*intel_dp
)
4112 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4113 enum drm_connector_status status
;
4115 status
= intel_panel_detect(dev
);
4116 if (status
== connector_status_unknown
)
4117 status
= connector_status_connected
;
4122 static enum drm_connector_status
4123 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4125 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4127 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4129 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4130 return connector_status_disconnected
;
4132 return intel_dp_detect_dpcd(intel_dp
);
4135 static int g4x_digital_port_connected(struct drm_device
*dev
,
4136 struct intel_digital_port
*intel_dig_port
)
4138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4141 if (IS_VALLEYVIEW(dev
)) {
4142 switch (intel_dig_port
->port
) {
4144 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4147 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4150 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4156 switch (intel_dig_port
->port
) {
4158 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4161 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4164 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4171 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4176 static enum drm_connector_status
4177 g4x_dp_detect(struct intel_dp
*intel_dp
)
4179 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4180 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4183 /* Can't disconnect eDP, but you can close the lid... */
4184 if (is_edp(intel_dp
)) {
4185 enum drm_connector_status status
;
4187 status
= intel_panel_detect(dev
);
4188 if (status
== connector_status_unknown
)
4189 status
= connector_status_connected
;
4193 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4195 return connector_status_unknown
;
4197 return connector_status_disconnected
;
4199 return intel_dp_detect_dpcd(intel_dp
);
4202 static struct edid
*
4203 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4205 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4207 /* use cached edid if we have one */
4208 if (intel_connector
->edid
) {
4210 if (IS_ERR(intel_connector
->edid
))
4213 return drm_edid_duplicate(intel_connector
->edid
);
4215 return drm_get_edid(&intel_connector
->base
,
4216 &intel_dp
->aux
.ddc
);
4220 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4222 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4225 edid
= intel_dp_get_edid(intel_dp
);
4226 intel_connector
->detect_edid
= edid
;
4228 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4229 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4231 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4235 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4237 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4239 kfree(intel_connector
->detect_edid
);
4240 intel_connector
->detect_edid
= NULL
;
4242 intel_dp
->has_audio
= false;
4245 static enum intel_display_power_domain
4246 intel_dp_power_get(struct intel_dp
*dp
)
4248 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4249 enum intel_display_power_domain power_domain
;
4251 power_domain
= intel_display_port_power_domain(encoder
);
4252 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4254 return power_domain
;
4258 intel_dp_power_put(struct intel_dp
*dp
,
4259 enum intel_display_power_domain power_domain
)
4261 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4262 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4265 static enum drm_connector_status
4266 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4268 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4269 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4270 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4271 struct drm_device
*dev
= connector
->dev
;
4272 enum drm_connector_status status
;
4273 enum intel_display_power_domain power_domain
;
4276 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4277 connector
->base
.id
, connector
->name
);
4278 intel_dp_unset_edid(intel_dp
);
4280 if (intel_dp
->is_mst
) {
4281 /* MST devices are disconnected from a monitor POV */
4282 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4283 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4284 return connector_status_disconnected
;
4287 power_domain
= intel_dp_power_get(intel_dp
);
4289 /* Can't disconnect eDP, but you can close the lid... */
4290 if (is_edp(intel_dp
))
4291 status
= edp_detect(intel_dp
);
4292 else if (HAS_PCH_SPLIT(dev
))
4293 status
= ironlake_dp_detect(intel_dp
);
4295 status
= g4x_dp_detect(intel_dp
);
4296 if (status
!= connector_status_connected
)
4299 intel_dp_probe_oui(intel_dp
);
4301 ret
= intel_dp_probe_mst(intel_dp
);
4303 /* if we are in MST mode then this connector
4304 won't appear connected or have anything with EDID on it */
4305 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4306 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4307 status
= connector_status_disconnected
;
4311 intel_dp_set_edid(intel_dp
);
4313 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4314 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4315 status
= connector_status_connected
;
4318 intel_dp_power_put(intel_dp
, power_domain
);
4323 intel_dp_force(struct drm_connector
*connector
)
4325 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4326 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4327 enum intel_display_power_domain power_domain
;
4329 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4330 connector
->base
.id
, connector
->name
);
4331 intel_dp_unset_edid(intel_dp
);
4333 if (connector
->status
!= connector_status_connected
)
4336 power_domain
= intel_dp_power_get(intel_dp
);
4338 intel_dp_set_edid(intel_dp
);
4340 intel_dp_power_put(intel_dp
, power_domain
);
4342 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4343 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4346 static int intel_dp_get_modes(struct drm_connector
*connector
)
4348 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4351 edid
= intel_connector
->detect_edid
;
4353 int ret
= intel_connector_update_modes(connector
, edid
);
4358 /* if eDP has no EDID, fall back to fixed mode */
4359 if (is_edp(intel_attached_dp(connector
)) &&
4360 intel_connector
->panel
.fixed_mode
) {
4361 struct drm_display_mode
*mode
;
4363 mode
= drm_mode_duplicate(connector
->dev
,
4364 intel_connector
->panel
.fixed_mode
);
4366 drm_mode_probed_add(connector
, mode
);
4375 intel_dp_detect_audio(struct drm_connector
*connector
)
4377 bool has_audio
= false;
4380 edid
= to_intel_connector(connector
)->detect_edid
;
4382 has_audio
= drm_detect_monitor_audio(edid
);
4388 intel_dp_set_property(struct drm_connector
*connector
,
4389 struct drm_property
*property
,
4392 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4393 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4394 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4395 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4398 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4402 if (property
== dev_priv
->force_audio_property
) {
4406 if (i
== intel_dp
->force_audio
)
4409 intel_dp
->force_audio
= i
;
4411 if (i
== HDMI_AUDIO_AUTO
)
4412 has_audio
= intel_dp_detect_audio(connector
);
4414 has_audio
= (i
== HDMI_AUDIO_ON
);
4416 if (has_audio
== intel_dp
->has_audio
)
4419 intel_dp
->has_audio
= has_audio
;
4423 if (property
== dev_priv
->broadcast_rgb_property
) {
4424 bool old_auto
= intel_dp
->color_range_auto
;
4425 uint32_t old_range
= intel_dp
->color_range
;
4428 case INTEL_BROADCAST_RGB_AUTO
:
4429 intel_dp
->color_range_auto
= true;
4431 case INTEL_BROADCAST_RGB_FULL
:
4432 intel_dp
->color_range_auto
= false;
4433 intel_dp
->color_range
= 0;
4435 case INTEL_BROADCAST_RGB_LIMITED
:
4436 intel_dp
->color_range_auto
= false;
4437 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4443 if (old_auto
== intel_dp
->color_range_auto
&&
4444 old_range
== intel_dp
->color_range
)
4450 if (is_edp(intel_dp
) &&
4451 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4452 if (val
== DRM_MODE_SCALE_NONE
) {
4453 DRM_DEBUG_KMS("no scaling not supported\n");
4457 if (intel_connector
->panel
.fitting_mode
== val
) {
4458 /* the eDP scaling property is not changed */
4461 intel_connector
->panel
.fitting_mode
= val
;
4469 if (intel_encoder
->base
.crtc
)
4470 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4476 intel_dp_connector_destroy(struct drm_connector
*connector
)
4478 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4480 kfree(intel_connector
->detect_edid
);
4482 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4483 kfree(intel_connector
->edid
);
4485 /* Can't call is_edp() since the encoder may have been destroyed
4487 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4488 intel_panel_fini(&intel_connector
->panel
);
4490 drm_connector_cleanup(connector
);
4494 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4496 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4497 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4499 drm_dp_aux_unregister(&intel_dp
->aux
);
4500 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4501 drm_encoder_cleanup(encoder
);
4502 if (is_edp(intel_dp
)) {
4503 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4505 * vdd might still be enabled do to the delayed vdd off.
4506 * Make sure vdd is actually turned off here.
4509 edp_panel_vdd_off_sync(intel_dp
);
4510 pps_unlock(intel_dp
);
4512 if (intel_dp
->edp_notifier
.notifier_call
) {
4513 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4514 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4517 kfree(intel_dig_port
);
4520 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4522 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4524 if (!is_edp(intel_dp
))
4528 * vdd might still be enabled do to the delayed vdd off.
4529 * Make sure vdd is actually turned off here.
4532 edp_panel_vdd_off_sync(intel_dp
);
4533 pps_unlock(intel_dp
);
4536 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4538 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4541 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4542 .dpms
= intel_connector_dpms
,
4543 .detect
= intel_dp_detect
,
4544 .force
= intel_dp_force
,
4545 .fill_modes
= drm_helper_probe_single_connector_modes
,
4546 .set_property
= intel_dp_set_property
,
4547 .destroy
= intel_dp_connector_destroy
,
4550 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4551 .get_modes
= intel_dp_get_modes
,
4552 .mode_valid
= intel_dp_mode_valid
,
4553 .best_encoder
= intel_best_encoder
,
4556 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4557 .reset
= intel_dp_encoder_reset
,
4558 .destroy
= intel_dp_encoder_destroy
,
4562 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4568 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4570 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4571 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4572 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4574 enum intel_display_power_domain power_domain
;
4577 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4578 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4580 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4581 port_name(intel_dig_port
->port
),
4582 long_hpd
? "long" : "short");
4584 power_domain
= intel_display_port_power_domain(intel_encoder
);
4585 intel_display_power_get(dev_priv
, power_domain
);
4589 if (HAS_PCH_SPLIT(dev
)) {
4590 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4593 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4597 if (!intel_dp_get_dpcd(intel_dp
)) {
4601 intel_dp_probe_oui(intel_dp
);
4603 if (!intel_dp_probe_mst(intel_dp
))
4607 if (intel_dp
->is_mst
) {
4608 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4612 if (!intel_dp
->is_mst
) {
4614 * we'll check the link status via the normal hot plug path later -
4615 * but for short hpds we should check it now
4617 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4618 intel_dp_check_link_status(intel_dp
);
4619 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4625 /* if we were in MST mode, and device is not there get out of MST mode */
4626 if (intel_dp
->is_mst
) {
4627 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4628 intel_dp
->is_mst
= false;
4629 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4632 intel_display_power_put(dev_priv
, power_domain
);
4637 /* Return which DP Port should be selected for Transcoder DP control */
4639 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4641 struct drm_device
*dev
= crtc
->dev
;
4642 struct intel_encoder
*intel_encoder
;
4643 struct intel_dp
*intel_dp
;
4645 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4646 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4648 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4649 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4650 return intel_dp
->output_reg
;
4656 /* check the VBT to see whether the eDP is on DP-D port */
4657 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4660 union child_device_config
*p_child
;
4662 static const short port_mapping
[] = {
4663 [PORT_B
] = PORT_IDPB
,
4664 [PORT_C
] = PORT_IDPC
,
4665 [PORT_D
] = PORT_IDPD
,
4671 if (!dev_priv
->vbt
.child_dev_num
)
4674 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4675 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4677 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4678 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4679 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4686 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4688 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4690 intel_attach_force_audio_property(connector
);
4691 intel_attach_broadcast_rgb_property(connector
);
4692 intel_dp
->color_range_auto
= true;
4694 if (is_edp(intel_dp
)) {
4695 drm_mode_create_scaling_mode_property(connector
->dev
);
4696 drm_object_attach_property(
4698 connector
->dev
->mode_config
.scaling_mode_property
,
4699 DRM_MODE_SCALE_ASPECT
);
4700 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4704 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4706 intel_dp
->last_power_cycle
= jiffies
;
4707 intel_dp
->last_power_on
= jiffies
;
4708 intel_dp
->last_backlight_off
= jiffies
;
4712 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4713 struct intel_dp
*intel_dp
,
4714 struct edp_power_seq
*out
)
4716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4717 struct edp_power_seq cur
, vbt
, spec
, final
;
4718 u32 pp_on
, pp_off
, pp_div
, pp
;
4719 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4721 lockdep_assert_held(&dev_priv
->pps_mutex
);
4723 if (HAS_PCH_SPLIT(dev
)) {
4724 pp_ctrl_reg
= PCH_PP_CONTROL
;
4725 pp_on_reg
= PCH_PP_ON_DELAYS
;
4726 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4727 pp_div_reg
= PCH_PP_DIVISOR
;
4729 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4731 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4732 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4733 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4734 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4737 /* Workaround: Need to write PP_CONTROL with the unlock key as
4738 * the very first thing. */
4739 pp
= ironlake_get_pp_control(intel_dp
);
4740 I915_WRITE(pp_ctrl_reg
, pp
);
4742 pp_on
= I915_READ(pp_on_reg
);
4743 pp_off
= I915_READ(pp_off_reg
);
4744 pp_div
= I915_READ(pp_div_reg
);
4746 /* Pull timing values out of registers */
4747 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4748 PANEL_POWER_UP_DELAY_SHIFT
;
4750 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4751 PANEL_LIGHT_ON_DELAY_SHIFT
;
4753 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4754 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4756 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4757 PANEL_POWER_DOWN_DELAY_SHIFT
;
4759 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4760 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4762 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4763 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4765 vbt
= dev_priv
->vbt
.edp_pps
;
4767 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4768 * our hw here, which are all in 100usec. */
4769 spec
.t1_t3
= 210 * 10;
4770 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4771 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4772 spec
.t10
= 500 * 10;
4773 /* This one is special and actually in units of 100ms, but zero
4774 * based in the hw (so we need to add 100 ms). But the sw vbt
4775 * table multiplies it with 1000 to make it in units of 100usec,
4777 spec
.t11_t12
= (510 + 100) * 10;
4779 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4780 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4782 /* Use the max of the register settings and vbt. If both are
4783 * unset, fall back to the spec limits. */
4784 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4786 max(cur.field, vbt.field))
4787 assign_final(t1_t3
);
4791 assign_final(t11_t12
);
4794 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4795 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4796 intel_dp
->backlight_on_delay
= get_delay(t8
);
4797 intel_dp
->backlight_off_delay
= get_delay(t9
);
4798 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4799 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4802 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4803 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4804 intel_dp
->panel_power_cycle_delay
);
4806 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4807 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4814 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4815 struct intel_dp
*intel_dp
,
4816 struct edp_power_seq
*seq
)
4818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4819 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4820 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4821 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4822 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4824 lockdep_assert_held(&dev_priv
->pps_mutex
);
4826 if (HAS_PCH_SPLIT(dev
)) {
4827 pp_on_reg
= PCH_PP_ON_DELAYS
;
4828 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4829 pp_div_reg
= PCH_PP_DIVISOR
;
4831 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4833 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4834 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4835 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4839 * And finally store the new values in the power sequencer. The
4840 * backlight delays are set to 1 because we do manual waits on them. For
4841 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4842 * we'll end up waiting for the backlight off delay twice: once when we
4843 * do the manual sleep, and once when we disable the panel and wait for
4844 * the PP_STATUS bit to become zero.
4846 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4847 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4848 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4849 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4850 /* Compute the divisor for the pp clock, simply match the Bspec
4852 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4853 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4854 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4856 /* Haswell doesn't have any port selection bits for the panel
4857 * power sequencer any more. */
4858 if (IS_VALLEYVIEW(dev
)) {
4859 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4860 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4862 port_sel
= PANEL_PORT_SELECT_DPA
;
4864 port_sel
= PANEL_PORT_SELECT_DPD
;
4869 I915_WRITE(pp_on_reg
, pp_on
);
4870 I915_WRITE(pp_off_reg
, pp_off
);
4871 I915_WRITE(pp_div_reg
, pp_div
);
4873 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4874 I915_READ(pp_on_reg
),
4875 I915_READ(pp_off_reg
),
4876 I915_READ(pp_div_reg
));
4879 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4882 struct intel_encoder
*encoder
;
4883 struct intel_dp
*intel_dp
= NULL
;
4884 struct intel_crtc_config
*config
= NULL
;
4885 struct intel_crtc
*intel_crtc
= NULL
;
4886 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4888 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4890 if (refresh_rate
<= 0) {
4891 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4895 if (intel_connector
== NULL
) {
4896 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4901 * FIXME: This needs proper synchronization with psr state. But really
4902 * hard to tell without seeing the user of this function of this code.
4903 * Check locking and ordering once that lands.
4905 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4906 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4910 encoder
= intel_attached_encoder(&intel_connector
->base
);
4911 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4912 intel_crtc
= encoder
->new_crtc
;
4915 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4919 config
= &intel_crtc
->config
;
4921 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4922 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4926 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4927 index
= DRRS_LOW_RR
;
4929 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4931 "DRRS requested for previously set RR...ignoring\n");
4935 if (!intel_crtc
->active
) {
4936 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4940 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4941 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4942 val
= I915_READ(reg
);
4943 if (index
> DRRS_HIGH_RR
) {
4944 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4945 intel_dp_set_m_n(intel_crtc
);
4947 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4949 I915_WRITE(reg
, val
);
4953 * mutex taken to ensure that there is no race between differnt
4954 * drrs calls trying to update refresh rate. This scenario may occur
4955 * in future when idleness detection based DRRS in kernel and
4956 * possible calls from user space to set differnt RR are made.
4959 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4961 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4963 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4965 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4968 static struct drm_display_mode
*
4969 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4970 struct intel_connector
*intel_connector
,
4971 struct drm_display_mode
*fixed_mode
)
4973 struct drm_connector
*connector
= &intel_connector
->base
;
4974 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4975 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4977 struct drm_display_mode
*downclock_mode
= NULL
;
4979 if (INTEL_INFO(dev
)->gen
<= 6) {
4980 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4984 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4985 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4989 downclock_mode
= intel_find_panel_downclock
4990 (dev
, fixed_mode
, connector
);
4992 if (!downclock_mode
) {
4993 DRM_DEBUG_KMS("DRRS not supported\n");
4997 dev_priv
->drrs
.connector
= intel_connector
;
4999 mutex_init(&intel_dp
->drrs_state
.mutex
);
5001 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
5003 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
5004 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5005 return downclock_mode
;
5008 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
5010 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5012 struct intel_dp
*intel_dp
;
5013 enum intel_display_power_domain power_domain
;
5015 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
5018 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5022 if (!edp_have_panel_vdd(intel_dp
))
5025 * The VDD bit needs a power domain reference, so if the bit is
5026 * already enabled when we boot or resume, grab this reference and
5027 * schedule a vdd off, so we don't hold on to the reference
5030 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5031 power_domain
= intel_display_port_power_domain(intel_encoder
);
5032 intel_display_power_get(dev_priv
, power_domain
);
5034 edp_panel_vdd_schedule_off(intel_dp
);
5036 pps_unlock(intel_dp
);
5039 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5040 struct intel_connector
*intel_connector
,
5041 struct edp_power_seq
*power_seq
)
5043 struct drm_connector
*connector
= &intel_connector
->base
;
5044 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5045 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5046 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5048 struct drm_display_mode
*fixed_mode
= NULL
;
5049 struct drm_display_mode
*downclock_mode
= NULL
;
5051 struct drm_display_mode
*scan
;
5054 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
5056 if (!is_edp(intel_dp
))
5059 intel_edp_panel_vdd_sanitize(intel_encoder
);
5061 /* Cache DPCD and EDID for edp. */
5062 intel_edp_panel_vdd_on(intel_dp
);
5063 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5064 intel_edp_panel_vdd_off(intel_dp
, false);
5067 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5068 dev_priv
->no_aux_handshake
=
5069 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5070 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5072 /* if this fails, presume the device is a ghost */
5073 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5077 /* We now know it's not a ghost, init power sequence regs. */
5079 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
5080 pps_unlock(intel_dp
);
5082 mutex_lock(&dev
->mode_config
.mutex
);
5083 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5085 if (drm_add_edid_modes(connector
, edid
)) {
5086 drm_mode_connector_update_edid_property(connector
,
5088 drm_edid_to_eld(connector
, edid
);
5091 edid
= ERR_PTR(-EINVAL
);
5094 edid
= ERR_PTR(-ENOENT
);
5096 intel_connector
->edid
= edid
;
5098 /* prefer fixed mode from EDID if available */
5099 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5100 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5101 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5102 downclock_mode
= intel_dp_drrs_init(
5104 intel_connector
, fixed_mode
);
5109 /* fallback to VBT if available for eDP */
5110 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5111 fixed_mode
= drm_mode_duplicate(dev
,
5112 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5114 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5116 mutex_unlock(&dev
->mode_config
.mutex
);
5118 if (IS_VALLEYVIEW(dev
)) {
5119 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5120 register_reboot_notifier(&intel_dp
->edp_notifier
);
5123 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5124 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5125 intel_panel_setup_backlight(connector
);
5131 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5132 struct intel_connector
*intel_connector
)
5134 struct drm_connector
*connector
= &intel_connector
->base
;
5135 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5136 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5137 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5139 enum port port
= intel_dig_port
->port
;
5140 struct edp_power_seq power_seq
= { 0 };
5143 intel_dp
->pps_pipe
= INVALID_PIPE
;
5145 /* intel_dp vfuncs */
5146 if (INTEL_INFO(dev
)->gen
>= 9)
5147 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5148 else if (IS_VALLEYVIEW(dev
))
5149 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5150 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5151 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5152 else if (HAS_PCH_SPLIT(dev
))
5153 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5155 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5157 if (INTEL_INFO(dev
)->gen
>= 9)
5158 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5160 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5162 /* Preserve the current hw state. */
5163 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5164 intel_dp
->attached_connector
= intel_connector
;
5166 if (intel_dp_is_edp(dev
, port
))
5167 type
= DRM_MODE_CONNECTOR_eDP
;
5169 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5172 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5173 * for DP the encoder type can be set by the caller to
5174 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5176 if (type
== DRM_MODE_CONNECTOR_eDP
)
5177 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5179 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5180 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5183 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5184 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5186 connector
->interlace_allowed
= true;
5187 connector
->doublescan_allowed
= 0;
5189 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5190 edp_panel_vdd_work
);
5192 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5193 drm_connector_register(connector
);
5196 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5198 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5199 intel_connector
->unregister
= intel_dp_connector_unregister
;
5201 /* Set up the hotplug pin. */
5204 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5207 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5210 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5213 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5219 if (is_edp(intel_dp
)) {
5221 if (IS_VALLEYVIEW(dev
)) {
5222 vlv_initial_power_sequencer_setup(intel_dp
);
5224 intel_dp_init_panel_power_timestamps(intel_dp
);
5225 intel_dp_init_panel_power_sequencer(dev
, intel_dp
,
5228 pps_unlock(intel_dp
);
5231 intel_dp_aux_init(intel_dp
, intel_connector
);
5233 /* init MST on ports that can support it */
5234 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5235 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5236 intel_dp_mst_encoder_init(intel_dig_port
,
5237 intel_connector
->base
.base
.id
);
5241 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
5242 drm_dp_aux_unregister(&intel_dp
->aux
);
5243 if (is_edp(intel_dp
)) {
5244 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5246 * vdd might still be enabled do to the delayed vdd off.
5247 * Make sure vdd is actually turned off here.
5250 edp_panel_vdd_off_sync(intel_dp
);
5251 pps_unlock(intel_dp
);
5253 drm_connector_unregister(connector
);
5254 drm_connector_cleanup(connector
);
5258 intel_dp_add_properties(intel_dp
, connector
);
5260 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5261 * 0xd. Failure to do so will result in spurious interrupts being
5262 * generated on the port when a cable is not attached.
5264 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5265 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5266 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5273 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5276 struct intel_digital_port
*intel_dig_port
;
5277 struct intel_encoder
*intel_encoder
;
5278 struct drm_encoder
*encoder
;
5279 struct intel_connector
*intel_connector
;
5281 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5282 if (!intel_dig_port
)
5285 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5286 if (!intel_connector
) {
5287 kfree(intel_dig_port
);
5291 intel_encoder
= &intel_dig_port
->base
;
5292 encoder
= &intel_encoder
->base
;
5294 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5295 DRM_MODE_ENCODER_TMDS
);
5297 intel_encoder
->compute_config
= intel_dp_compute_config
;
5298 intel_encoder
->disable
= intel_disable_dp
;
5299 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5300 intel_encoder
->get_config
= intel_dp_get_config
;
5301 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5302 if (IS_CHERRYVIEW(dev
)) {
5303 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5304 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5305 intel_encoder
->enable
= vlv_enable_dp
;
5306 intel_encoder
->post_disable
= chv_post_disable_dp
;
5307 } else if (IS_VALLEYVIEW(dev
)) {
5308 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5309 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5310 intel_encoder
->enable
= vlv_enable_dp
;
5311 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5313 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5314 intel_encoder
->enable
= g4x_enable_dp
;
5315 if (INTEL_INFO(dev
)->gen
>= 5)
5316 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5319 intel_dig_port
->port
= port
;
5320 intel_dig_port
->dp
.output_reg
= output_reg
;
5322 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5323 if (IS_CHERRYVIEW(dev
)) {
5325 intel_encoder
->crtc_mask
= 1 << 2;
5327 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5329 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5331 intel_encoder
->cloneable
= 0;
5332 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5334 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5335 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5337 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5338 drm_encoder_cleanup(encoder
);
5339 kfree(intel_dig_port
);
5340 kfree(intel_connector
);
5344 void intel_dp_mst_suspend(struct drm_device
*dev
)
5346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5350 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5351 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5352 if (!intel_dig_port
)
5355 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5356 if (!intel_dig_port
->dp
.can_mst
)
5358 if (intel_dig_port
->dp
.is_mst
)
5359 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5364 void intel_dp_mst_resume(struct drm_device
*dev
)
5366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5369 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5370 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5371 if (!intel_dig_port
)
5373 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5376 if (!intel_dig_port
->dp
.can_mst
)
5379 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5381 intel_dp_check_mst_status(&intel_dig_port
->dp
);