2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
194 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
196 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
197 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
198 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
199 int max_dotclk
= dev_priv
->max_dotclk_freq
;
202 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
204 if (type
!= DP_DS_PORT_TYPE_VGA
)
207 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
208 intel_dp
->downstream_ports
);
210 if (ds_max_dotclk
!= 0)
211 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
216 static enum drm_mode_status
217 intel_dp_mode_valid(struct drm_connector
*connector
,
218 struct drm_display_mode
*mode
)
220 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
221 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
222 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
223 int target_clock
= mode
->clock
;
224 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
227 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
229 if (is_edp(intel_dp
) && fixed_mode
) {
230 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
233 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
236 target_clock
= fixed_mode
->clock
;
239 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
240 max_lanes
= intel_dp_max_lane_count(intel_dp
);
242 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
243 mode_rate
= intel_dp_link_required(target_clock
, 18);
245 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
246 return MODE_CLOCK_HIGH
;
248 if (mode
->clock
< 10000)
249 return MODE_CLOCK_LOW
;
251 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
252 return MODE_H_ILLEGAL
;
257 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
264 for (i
= 0; i
< src_bytes
; i
++)
265 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
269 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
274 for (i
= 0; i
< dst_bytes
; i
++)
275 dst
[i
] = src
>> ((3-i
) * 8);
279 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
280 struct intel_dp
*intel_dp
);
282 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
283 struct intel_dp
*intel_dp
);
285 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
287 static void pps_lock(struct intel_dp
*intel_dp
)
289 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
290 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
291 struct drm_device
*dev
= encoder
->base
.dev
;
292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
293 enum intel_display_power_domain power_domain
;
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
299 power_domain
= intel_display_port_aux_power_domain(encoder
);
300 intel_display_power_get(dev_priv
, power_domain
);
302 mutex_lock(&dev_priv
->pps_mutex
);
305 static void pps_unlock(struct intel_dp
*intel_dp
)
307 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
308 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
309 struct drm_device
*dev
= encoder
->base
.dev
;
310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
311 enum intel_display_power_domain power_domain
;
313 mutex_unlock(&dev_priv
->pps_mutex
);
315 power_domain
= intel_display_port_aux_power_domain(encoder
);
316 intel_display_power_put(dev_priv
, power_domain
);
320 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
323 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
324 struct drm_i915_private
*dev_priv
= to_i915(dev
);
325 enum pipe pipe
= intel_dp
->pps_pipe
;
326 bool pll_enabled
, release_cl_override
= false;
327 enum dpio_phy phy
= DPIO_PHY(pipe
);
328 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
331 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe
), port_name(intel_dig_port
->port
));
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
342 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
343 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
344 DP
|= DP_PORT_WIDTH(1);
345 DP
|= DP_LINK_TRAIN_PAT_1
;
347 if (IS_CHERRYVIEW(dev
))
348 DP
|= DP_PIPE_SELECT_CHV(pipe
);
349 else if (pipe
== PIPE_B
)
350 DP
|= DP_PIPEB_SELECT
;
352 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
359 release_cl_override
= IS_CHERRYVIEW(dev
) &&
360 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
362 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
363 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
376 I915_WRITE(intel_dp
->output_reg
, DP
);
377 POSTING_READ(intel_dp
->output_reg
);
379 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
386 vlv_force_pll_off(dev
, pipe
);
388 if (release_cl_override
)
389 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
394 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
396 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
397 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
398 struct drm_i915_private
*dev_priv
= to_i915(dev
);
399 struct intel_encoder
*encoder
;
400 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
403 lockdep_assert_held(&dev_priv
->pps_mutex
);
405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp
));
408 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
409 return intel_dp
->pps_pipe
;
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
415 for_each_intel_encoder(dev
, encoder
) {
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
457 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
459 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
460 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
461 struct drm_i915_private
*dev_priv
= to_i915(dev
);
463 lockdep_assert_held(&dev_priv
->pps_mutex
);
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp
));
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
473 if (!intel_dp
->pps_reset
)
476 intel_dp
->pps_reset
= false;
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
482 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
487 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
490 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
493 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
499 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
502 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
509 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
511 vlv_pipe_check pipe_check
)
515 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
516 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
517 PANEL_PORT_SELECT_MASK
;
519 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
522 if (!pipe_check(dev_priv
, pipe
))
532 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
534 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
535 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
536 struct drm_i915_private
*dev_priv
= to_i915(dev
);
537 enum port port
= intel_dig_port
->port
;
539 lockdep_assert_held(&dev_priv
->pps_mutex
);
541 /* try to find a pipe with this port selected */
542 /* first pick one where the panel is on */
543 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
547 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
548 vlv_pipe_has_vdd_on
);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
551 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
564 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
565 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
568 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
570 struct drm_device
*dev
= &dev_priv
->drm
;
571 struct intel_encoder
*encoder
;
573 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
587 for_each_intel_encoder(dev
, encoder
) {
588 struct intel_dp
*intel_dp
;
590 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
593 intel_dp
= enc_to_intel_dp(&encoder
->base
);
595 intel_dp
->pps_reset
= true;
597 intel_dp
->pps_pipe
= INVALID_PIPE
;
601 struct pps_registers
{
609 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
610 struct intel_dp
*intel_dp
,
611 struct pps_registers
*regs
)
615 memset(regs
, 0, sizeof(*regs
));
617 if (IS_BROXTON(dev_priv
))
618 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
619 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
620 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
622 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
623 regs
->pp_stat
= PP_STATUS(pps_idx
);
624 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
625 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
626 if (!IS_BROXTON(dev_priv
))
627 regs
->pp_div
= PP_DIVISOR(pps_idx
);
631 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
633 struct pps_registers regs
;
635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
642 _pp_stat_reg(struct intel_dp
*intel_dp
)
644 struct pps_registers regs
;
646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
657 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
659 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
660 struct drm_i915_private
*dev_priv
= to_i915(dev
);
662 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
667 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
668 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
669 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
672 pp_ctrl_reg
= PP_CONTROL(pipe
);
673 pp_div_reg
= PP_DIVISOR(pipe
);
674 pp_div
= I915_READ(pp_div_reg
);
675 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
679 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
680 msleep(intel_dp
->panel_power_cycle_delay
);
683 pps_unlock(intel_dp
);
688 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
690 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
691 struct drm_i915_private
*dev_priv
= to_i915(dev
);
693 lockdep_assert_held(&dev_priv
->pps_mutex
);
695 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
696 intel_dp
->pps_pipe
== INVALID_PIPE
)
699 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
702 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
704 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
705 struct drm_i915_private
*dev_priv
= to_i915(dev
);
707 lockdep_assert_held(&dev_priv
->pps_mutex
);
709 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
710 intel_dp
->pps_pipe
== INVALID_PIPE
)
713 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
717 intel_dp_check_edp(struct intel_dp
*intel_dp
)
719 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
722 if (!is_edp(intel_dp
))
725 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
728 I915_READ(_pp_stat_reg(intel_dp
)),
729 I915_READ(_pp_ctrl_reg(intel_dp
)));
734 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
736 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
737 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
739 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
743 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
745 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
746 msecs_to_jiffies_timeout(10));
748 done
= wait_for(C
, 10) == 0;
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
757 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
759 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
760 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
766 * The clock divider is based off the hrawclk, and would like to run at
767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
769 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
772 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
774 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
775 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
785 if (intel_dig_port
->port
== PORT_A
)
786 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
788 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
791 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
793 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
794 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
796 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
797 /* Workaround for non-ULT HSW */
805 return ilk_get_aux_clock_divider(intel_dp
, index
);
808 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
815 return index
? 0 : 1;
818 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
821 uint32_t aux_clock_divider
)
823 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
824 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
825 uint32_t precharge
, timeout
;
832 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
833 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
835 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
837 return DP_AUX_CH_CTL_SEND_BUSY
|
839 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
840 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
842 DP_AUX_CH_CTL_RECEIVE_ERROR
|
843 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
844 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
845 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
848 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
853 return DP_AUX_CH_CTL_SEND_BUSY
|
855 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
856 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
857 DP_AUX_CH_CTL_TIME_OUT_1600us
|
858 DP_AUX_CH_CTL_RECEIVE_ERROR
|
859 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
860 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
861 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
865 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
866 const uint8_t *send
, int send_bytes
,
867 uint8_t *recv
, int recv_size
)
869 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
870 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
871 struct drm_i915_private
*dev_priv
= to_i915(dev
);
872 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
873 uint32_t aux_clock_divider
;
874 int i
, ret
, recv_bytes
;
877 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
883 * We will be called with VDD already enabled for dpcd/edid/oui reads.
884 * In such cases we want to leave VDD enabled and it's up to upper layers
885 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
888 vdd
= edp_panel_vdd_on(intel_dp
);
890 /* dp aux is extremely sensitive to irq latency, hence request the
891 * lowest possible wakeup latency and so prevent the cpu from going into
894 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
896 intel_dp_check_edp(intel_dp
);
898 /* Try to wait for any previous AUX channel activity */
899 for (try = 0; try < 3; try++) {
900 status
= I915_READ_NOTRACE(ch_ctl
);
901 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
907 static u32 last_status
= -1;
908 const u32 status
= I915_READ(ch_ctl
);
910 if (status
!= last_status
) {
911 WARN(1, "dp_aux_ch not started status 0x%08x\n",
913 last_status
= status
;
920 /* Only 5 data registers! */
921 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
926 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
927 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
932 /* Must try at least 3 times according to DP spec */
933 for (try = 0; try < 5; try++) {
934 /* Load the send data into the aux channel data registers */
935 for (i
= 0; i
< send_bytes
; i
+= 4)
936 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
937 intel_dp_pack_aux(send
+ i
,
940 /* Send the command and wait for it to complete */
941 I915_WRITE(ch_ctl
, send_ctl
);
943 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
945 /* Clear done status and any errors */
949 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
950 DP_AUX_CH_CTL_RECEIVE_ERROR
);
952 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
955 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
956 * 400us delay required for errors and timeouts
957 * Timeout errors from the HW already meet this
958 * requirement so skip to next iteration
960 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
961 usleep_range(400, 500);
964 if (status
& DP_AUX_CH_CTL_DONE
)
969 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
970 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
976 /* Check for timeout or receive error.
977 * Timeouts occur when the sink is not connected
979 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
980 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
985 /* Timeouts occur when the device isn't connected, so they're
986 * "normal" -- don't fill the kernel log with these */
987 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
988 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
993 /* Unload any bytes sent back from the other side */
994 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
995 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
998 * By BSpec: "Message sizes of 0 or >20 are not allowed."
999 * We have no idea of what happened so we return -EBUSY so
1000 * drm layer takes care for the necessary retries.
1002 if (recv_bytes
== 0 || recv_bytes
> 20) {
1003 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1006 * FIXME: This patch was created on top of a series that
1007 * organize the retries at drm level. There EBUSY should
1008 * also take care for 1ms wait before retrying.
1009 * That aux retries re-org is still needed and after that is
1010 * merged we remove this sleep from here.
1012 usleep_range(1000, 1500);
1017 if (recv_bytes
> recv_size
)
1018 recv_bytes
= recv_size
;
1020 for (i
= 0; i
< recv_bytes
; i
+= 4)
1021 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1022 recv
+ i
, recv_bytes
- i
);
1026 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1029 edp_panel_vdd_off(intel_dp
, false);
1031 pps_unlock(intel_dp
);
1036 #define BARE_ADDRESS_SIZE 3
1037 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1039 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1041 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1042 uint8_t txbuf
[20], rxbuf
[20];
1043 size_t txsize
, rxsize
;
1046 txbuf
[0] = (msg
->request
<< 4) |
1047 ((msg
->address
>> 16) & 0xf);
1048 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1049 txbuf
[2] = msg
->address
& 0xff;
1050 txbuf
[3] = msg
->size
- 1;
1052 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1053 case DP_AUX_NATIVE_WRITE
:
1054 case DP_AUX_I2C_WRITE
:
1055 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1056 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1057 rxsize
= 2; /* 0 or 1 data bytes */
1059 if (WARN_ON(txsize
> 20))
1062 WARN_ON(!msg
->buffer
!= !msg
->size
);
1065 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1067 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1069 msg
->reply
= rxbuf
[0] >> 4;
1072 /* Number of bytes written in a short write. */
1073 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1075 /* Return payload size. */
1081 case DP_AUX_NATIVE_READ
:
1082 case DP_AUX_I2C_READ
:
1083 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1084 rxsize
= msg
->size
+ 1;
1086 if (WARN_ON(rxsize
> 20))
1089 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1091 msg
->reply
= rxbuf
[0] >> 4;
1093 * Assume happy day, and copy the data. The caller is
1094 * expected to check msg->reply before touching it.
1096 * Return payload size.
1099 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1111 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1114 const struct ddi_vbt_port_info
*info
=
1115 &dev_priv
->vbt
.ddi_port_info
[port
];
1118 if (!info
->alternate_aux_channel
) {
1119 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1120 port_name(port
), port_name(port
));
1124 switch (info
->alternate_aux_channel
) {
1138 MISSING_CASE(info
->alternate_aux_channel
);
1143 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1144 port_name(aux_port
), port_name(port
));
1149 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1156 return DP_AUX_CH_CTL(port
);
1159 return DP_AUX_CH_CTL(PORT_B
);
1163 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1164 enum port port
, int index
)
1170 return DP_AUX_CH_DATA(port
, index
);
1173 return DP_AUX_CH_DATA(PORT_B
, index
);
1177 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1182 return DP_AUX_CH_CTL(port
);
1186 return PCH_DP_AUX_CH_CTL(port
);
1189 return DP_AUX_CH_CTL(PORT_A
);
1193 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1194 enum port port
, int index
)
1198 return DP_AUX_CH_DATA(port
, index
);
1202 return PCH_DP_AUX_CH_DATA(port
, index
);
1205 return DP_AUX_CH_DATA(PORT_A
, index
);
1209 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1217 return DP_AUX_CH_CTL(port
);
1220 return DP_AUX_CH_CTL(PORT_A
);
1224 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1225 enum port port
, int index
)
1232 return DP_AUX_CH_DATA(port
, index
);
1235 return DP_AUX_CH_DATA(PORT_A
, index
);
1239 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1242 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1243 return skl_aux_ctl_reg(dev_priv
, port
);
1244 else if (HAS_PCH_SPLIT(dev_priv
))
1245 return ilk_aux_ctl_reg(dev_priv
, port
);
1247 return g4x_aux_ctl_reg(dev_priv
, port
);
1250 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1251 enum port port
, int index
)
1253 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1254 return skl_aux_data_reg(dev_priv
, port
, index
);
1255 else if (HAS_PCH_SPLIT(dev_priv
))
1256 return ilk_aux_data_reg(dev_priv
, port
, index
);
1258 return g4x_aux_data_reg(dev_priv
, port
, index
);
1261 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1263 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1264 enum port port
= intel_aux_port(dev_priv
,
1265 dp_to_dig_port(intel_dp
)->port
);
1268 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1269 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1270 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1274 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1276 kfree(intel_dp
->aux
.name
);
1280 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1282 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1283 enum port port
= intel_dig_port
->port
;
1285 intel_aux_reg_init(intel_dp
);
1286 drm_dp_aux_init(&intel_dp
->aux
);
1288 /* Failure to allocate our preferred name is not critical */
1289 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1290 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1294 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1296 if (intel_dp
->num_sink_rates
) {
1297 *sink_rates
= intel_dp
->sink_rates
;
1298 return intel_dp
->num_sink_rates
;
1301 *sink_rates
= default_rates
;
1303 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1306 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1308 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1309 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1311 /* WaDisableHBR2:skl */
1312 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1315 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1316 (INTEL_INFO(dev
)->gen
>= 9))
1323 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1325 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1326 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1329 if (IS_BROXTON(dev
)) {
1330 *source_rates
= bxt_rates
;
1331 size
= ARRAY_SIZE(bxt_rates
);
1332 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1333 *source_rates
= skl_rates
;
1334 size
= ARRAY_SIZE(skl_rates
);
1336 *source_rates
= default_rates
;
1337 size
= ARRAY_SIZE(default_rates
);
1340 /* This depends on the fact that 5.4 is last value in the array */
1341 if (!intel_dp_source_supports_hbr2(intel_dp
))
1348 intel_dp_set_clock(struct intel_encoder
*encoder
,
1349 struct intel_crtc_state
*pipe_config
)
1351 struct drm_device
*dev
= encoder
->base
.dev
;
1352 const struct dp_link_dpll
*divisor
= NULL
;
1356 divisor
= gen4_dpll
;
1357 count
= ARRAY_SIZE(gen4_dpll
);
1358 } else if (HAS_PCH_SPLIT(dev
)) {
1360 count
= ARRAY_SIZE(pch_dpll
);
1361 } else if (IS_CHERRYVIEW(dev
)) {
1363 count
= ARRAY_SIZE(chv_dpll
);
1364 } else if (IS_VALLEYVIEW(dev
)) {
1366 count
= ARRAY_SIZE(vlv_dpll
);
1369 if (divisor
&& count
) {
1370 for (i
= 0; i
< count
; i
++) {
1371 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1372 pipe_config
->dpll
= divisor
[i
].dpll
;
1373 pipe_config
->clock_set
= true;
1380 static int intersect_rates(const int *source_rates
, int source_len
,
1381 const int *sink_rates
, int sink_len
,
1384 int i
= 0, j
= 0, k
= 0;
1386 while (i
< source_len
&& j
< sink_len
) {
1387 if (source_rates
[i
] == sink_rates
[j
]) {
1388 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1390 common_rates
[k
] = source_rates
[i
];
1394 } else if (source_rates
[i
] < sink_rates
[j
]) {
1403 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1406 const int *source_rates
, *sink_rates
;
1407 int source_len
, sink_len
;
1409 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1410 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1412 return intersect_rates(source_rates
, source_len
,
1413 sink_rates
, sink_len
,
1417 static void snprintf_int_array(char *str
, size_t len
,
1418 const int *array
, int nelem
)
1424 for (i
= 0; i
< nelem
; i
++) {
1425 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1433 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1435 const int *source_rates
, *sink_rates
;
1436 int source_len
, sink_len
, common_len
;
1437 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1438 char str
[128]; /* FIXME: too big for stack? */
1440 if ((drm_debug
& DRM_UT_KMS
) == 0)
1443 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1444 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1445 DRM_DEBUG_KMS("source rates: %s\n", str
);
1447 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1448 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1449 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1451 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1452 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1453 DRM_DEBUG_KMS("common rates: %s\n", str
);
1456 static void intel_dp_print_hw_revision(struct intel_dp
*intel_dp
)
1461 if ((drm_debug
& DRM_UT_KMS
) == 0)
1464 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1465 DP_DWN_STRM_PORT_PRESENT
))
1468 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_HW_REV
, &rev
, 1);
1472 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev
& 0xf0) >> 4, rev
& 0xf);
1475 static void intel_dp_print_sw_revision(struct intel_dp
*intel_dp
)
1480 if ((drm_debug
& DRM_UT_KMS
) == 0)
1483 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1484 DP_DWN_STRM_PORT_PRESENT
))
1487 len
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_SW_REV
, &rev
, 2);
1491 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev
[0], rev
[1]);
1494 static int rate_to_index(int find
, const int *rates
)
1498 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1499 if (find
== rates
[i
])
1506 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1508 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1511 len
= intel_dp_common_rates(intel_dp
, rates
);
1512 if (WARN_ON(len
<= 0))
1515 return rates
[len
- 1];
1518 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1520 return rate_to_index(rate
, intel_dp
->sink_rates
);
1523 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1524 uint8_t *link_bw
, uint8_t *rate_select
)
1526 if (intel_dp
->num_sink_rates
) {
1529 intel_dp_rate_select(intel_dp
, port_clock
);
1531 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1536 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1537 struct intel_crtc_state
*pipe_config
)
1541 bpp
= pipe_config
->pipe_bpp
;
1542 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1545 bpp
= min(bpp
, 3*bpc
);
1551 intel_dp_compute_config(struct intel_encoder
*encoder
,
1552 struct intel_crtc_state
*pipe_config
,
1553 struct drm_connector_state
*conn_state
)
1555 struct drm_device
*dev
= encoder
->base
.dev
;
1556 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1557 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1558 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1559 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1560 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1561 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1562 int lane_count
, clock
;
1563 int min_lane_count
= 1;
1564 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1565 /* Conveniently, the link BW constants become indices with a shift...*/
1569 int link_avail
, link_clock
;
1570 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1572 uint8_t link_bw
, rate_select
;
1574 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1576 /* No common link rates between source and sink */
1577 WARN_ON(common_len
<= 0);
1579 max_clock
= common_len
- 1;
1581 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1582 pipe_config
->has_pch_encoder
= true;
1584 pipe_config
->has_drrs
= false;
1585 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1587 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1588 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1591 if (INTEL_INFO(dev
)->gen
>= 9) {
1593 ret
= skl_update_scaler_crtc(pipe_config
);
1598 if (HAS_GMCH_DISPLAY(dev
))
1599 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1600 intel_connector
->panel
.fitting_mode
);
1602 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1603 intel_connector
->panel
.fitting_mode
);
1606 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1609 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1610 "max bw %d pixel clock %iKHz\n",
1611 max_lane_count
, common_rates
[max_clock
],
1612 adjusted_mode
->crtc_clock
);
1614 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1615 * bpc in between. */
1616 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1617 if (is_edp(intel_dp
)) {
1619 /* Get bpp from vbt only for panels that dont have bpp in edid */
1620 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1621 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1622 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1623 dev_priv
->vbt
.edp
.bpp
);
1624 bpp
= dev_priv
->vbt
.edp
.bpp
;
1628 * Use the maximum clock and number of lanes the eDP panel
1629 * advertizes being capable of. The panels are generally
1630 * designed to support only a single clock and lane
1631 * configuration, and typically these values correspond to the
1632 * native resolution of the panel.
1634 min_lane_count
= max_lane_count
;
1635 min_clock
= max_clock
;
1638 for (; bpp
>= 6*3; bpp
-= 2*3) {
1639 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1642 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1643 for (lane_count
= min_lane_count
;
1644 lane_count
<= max_lane_count
;
1647 link_clock
= common_rates
[clock
];
1648 link_avail
= intel_dp_max_data_rate(link_clock
,
1651 if (mode_rate
<= link_avail
) {
1661 if (intel_dp
->color_range_auto
) {
1664 * CEA-861-E - 5.1 Default Encoding Parameters
1665 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1667 pipe_config
->limited_color_range
=
1668 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1670 pipe_config
->limited_color_range
=
1671 intel_dp
->limited_color_range
;
1674 pipe_config
->lane_count
= lane_count
;
1676 pipe_config
->pipe_bpp
= bpp
;
1677 pipe_config
->port_clock
= common_rates
[clock
];
1679 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1680 &link_bw
, &rate_select
);
1682 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1683 link_bw
, rate_select
, pipe_config
->lane_count
,
1684 pipe_config
->port_clock
, bpp
);
1685 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1686 mode_rate
, link_avail
);
1688 intel_link_compute_m_n(bpp
, lane_count
,
1689 adjusted_mode
->crtc_clock
,
1690 pipe_config
->port_clock
,
1691 &pipe_config
->dp_m_n
);
1693 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1694 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1695 pipe_config
->has_drrs
= true;
1696 intel_link_compute_m_n(bpp
, lane_count
,
1697 intel_connector
->panel
.downclock_mode
->clock
,
1698 pipe_config
->port_clock
,
1699 &pipe_config
->dp_m2_n2
);
1703 * DPLL0 VCO may need to be adjusted to get the correct
1704 * clock for eDP. This will affect cdclk as well.
1706 if (is_edp(intel_dp
) &&
1707 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1710 switch (pipe_config
->port_clock
/ 2) {
1720 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1724 intel_dp_set_clock(encoder
, pipe_config
);
1729 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1730 int link_rate
, uint8_t lane_count
,
1733 intel_dp
->link_rate
= link_rate
;
1734 intel_dp
->lane_count
= lane_count
;
1735 intel_dp
->link_mst
= link_mst
;
1738 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1739 struct intel_crtc_state
*pipe_config
)
1741 struct drm_device
*dev
= encoder
->base
.dev
;
1742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1743 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1744 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1745 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1746 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1748 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1749 pipe_config
->lane_count
,
1750 intel_crtc_has_type(pipe_config
,
1751 INTEL_OUTPUT_DP_MST
));
1754 * There are four kinds of DP registers:
1761 * IBX PCH and CPU are the same for almost everything,
1762 * except that the CPU DP PLL is configured in this
1765 * CPT PCH is quite different, having many bits moved
1766 * to the TRANS_DP_CTL register instead. That
1767 * configuration happens (oddly) in ironlake_pch_enable
1770 /* Preserve the BIOS-computed detected bit. This is
1771 * supposed to be read-only.
1773 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1775 /* Handle DP bits in common between all three register formats */
1776 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1777 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1779 /* Split out the IBX/CPU vs CPT settings */
1781 if (IS_GEN7(dev
) && port
== PORT_A
) {
1782 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1783 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1784 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1785 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1786 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1788 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1789 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1791 intel_dp
->DP
|= crtc
->pipe
<< 29;
1792 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1795 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1797 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1798 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1799 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1801 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1802 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1804 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1805 !IS_CHERRYVIEW(dev
) && pipe_config
->limited_color_range
)
1806 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1808 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1809 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1810 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1811 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1812 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1814 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1815 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1817 if (IS_CHERRYVIEW(dev
))
1818 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1819 else if (crtc
->pipe
== PIPE_B
)
1820 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1824 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1825 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1827 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1828 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1830 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1831 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1833 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1834 struct intel_dp
*intel_dp
);
1836 static void wait_panel_status(struct intel_dp
*intel_dp
,
1840 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1841 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1842 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1844 lockdep_assert_held(&dev_priv
->pps_mutex
);
1846 intel_pps_verify_state(dev_priv
, intel_dp
);
1848 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1849 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1851 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1853 I915_READ(pp_stat_reg
),
1854 I915_READ(pp_ctrl_reg
));
1856 if (intel_wait_for_register(dev_priv
,
1857 pp_stat_reg
, mask
, value
,
1859 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1860 I915_READ(pp_stat_reg
),
1861 I915_READ(pp_ctrl_reg
));
1863 DRM_DEBUG_KMS("Wait complete\n");
1866 static void wait_panel_on(struct intel_dp
*intel_dp
)
1868 DRM_DEBUG_KMS("Wait for panel power on\n");
1869 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1872 static void wait_panel_off(struct intel_dp
*intel_dp
)
1874 DRM_DEBUG_KMS("Wait for panel power off time\n");
1875 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1878 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1880 ktime_t panel_power_on_time
;
1881 s64 panel_power_off_duration
;
1883 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1885 /* take the difference of currrent time and panel power off time
1886 * and then make panel wait for t11_t12 if needed. */
1887 panel_power_on_time
= ktime_get_boottime();
1888 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1890 /* When we disable the VDD override bit last we have to do the manual
1892 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1893 wait_remaining_ms_from_jiffies(jiffies
,
1894 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1896 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1899 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1901 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1902 intel_dp
->backlight_on_delay
);
1905 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1907 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1908 intel_dp
->backlight_off_delay
);
1911 /* Read the current pp_control value, unlocking the register if it
1915 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1917 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1918 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1921 lockdep_assert_held(&dev_priv
->pps_mutex
);
1923 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1924 if (WARN_ON(!HAS_DDI(dev_priv
) &&
1925 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
1926 control
&= ~PANEL_UNLOCK_MASK
;
1927 control
|= PANEL_UNLOCK_REGS
;
1933 * Must be paired with edp_panel_vdd_off().
1934 * Must hold pps_mutex around the whole on/off sequence.
1935 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1937 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1939 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1940 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1941 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1942 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1943 enum intel_display_power_domain power_domain
;
1945 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1946 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1948 lockdep_assert_held(&dev_priv
->pps_mutex
);
1950 if (!is_edp(intel_dp
))
1953 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1954 intel_dp
->want_panel_vdd
= true;
1956 if (edp_have_panel_vdd(intel_dp
))
1957 return need_to_disable
;
1959 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1960 intel_display_power_get(dev_priv
, power_domain
);
1962 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1963 port_name(intel_dig_port
->port
));
1965 if (!edp_have_panel_power(intel_dp
))
1966 wait_panel_power_cycle(intel_dp
);
1968 pp
= ironlake_get_pp_control(intel_dp
);
1969 pp
|= EDP_FORCE_VDD
;
1971 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1972 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1974 I915_WRITE(pp_ctrl_reg
, pp
);
1975 POSTING_READ(pp_ctrl_reg
);
1976 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1977 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1979 * If the panel wasn't on, delay before accessing aux channel
1981 if (!edp_have_panel_power(intel_dp
)) {
1982 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1983 port_name(intel_dig_port
->port
));
1984 msleep(intel_dp
->panel_power_up_delay
);
1987 return need_to_disable
;
1991 * Must be paired with intel_edp_panel_vdd_off() or
1992 * intel_edp_panel_off().
1993 * Nested calls to these functions are not allowed since
1994 * we drop the lock. Caller must use some higher level
1995 * locking to prevent nested calls from other threads.
1997 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2001 if (!is_edp(intel_dp
))
2005 vdd
= edp_panel_vdd_on(intel_dp
);
2006 pps_unlock(intel_dp
);
2008 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2009 port_name(dp_to_dig_port(intel_dp
)->port
));
2012 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2014 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2015 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2016 struct intel_digital_port
*intel_dig_port
=
2017 dp_to_dig_port(intel_dp
);
2018 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2019 enum intel_display_power_domain power_domain
;
2021 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2023 lockdep_assert_held(&dev_priv
->pps_mutex
);
2025 WARN_ON(intel_dp
->want_panel_vdd
);
2027 if (!edp_have_panel_vdd(intel_dp
))
2030 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2031 port_name(intel_dig_port
->port
));
2033 pp
= ironlake_get_pp_control(intel_dp
);
2034 pp
&= ~EDP_FORCE_VDD
;
2036 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2037 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2039 I915_WRITE(pp_ctrl_reg
, pp
);
2040 POSTING_READ(pp_ctrl_reg
);
2042 /* Make sure sequencer is idle before allowing subsequent activity */
2043 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2044 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2046 if ((pp
& PANEL_POWER_ON
) == 0)
2047 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2049 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2050 intel_display_power_put(dev_priv
, power_domain
);
2053 static void edp_panel_vdd_work(struct work_struct
*__work
)
2055 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2056 struct intel_dp
, panel_vdd_work
);
2059 if (!intel_dp
->want_panel_vdd
)
2060 edp_panel_vdd_off_sync(intel_dp
);
2061 pps_unlock(intel_dp
);
2064 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2066 unsigned long delay
;
2069 * Queue the timer to fire a long time from now (relative to the power
2070 * down delay) to keep the panel power up across a sequence of
2073 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2074 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2078 * Must be paired with edp_panel_vdd_on().
2079 * Must hold pps_mutex around the whole on/off sequence.
2080 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2082 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2084 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2086 lockdep_assert_held(&dev_priv
->pps_mutex
);
2088 if (!is_edp(intel_dp
))
2091 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2092 port_name(dp_to_dig_port(intel_dp
)->port
));
2094 intel_dp
->want_panel_vdd
= false;
2097 edp_panel_vdd_off_sync(intel_dp
);
2099 edp_panel_vdd_schedule_off(intel_dp
);
2102 static void edp_panel_on(struct intel_dp
*intel_dp
)
2104 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2105 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2107 i915_reg_t pp_ctrl_reg
;
2109 lockdep_assert_held(&dev_priv
->pps_mutex
);
2111 if (!is_edp(intel_dp
))
2114 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2115 port_name(dp_to_dig_port(intel_dp
)->port
));
2117 if (WARN(edp_have_panel_power(intel_dp
),
2118 "eDP port %c panel power already on\n",
2119 port_name(dp_to_dig_port(intel_dp
)->port
)))
2122 wait_panel_power_cycle(intel_dp
);
2124 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2125 pp
= ironlake_get_pp_control(intel_dp
);
2127 /* ILK workaround: disable reset around power sequence */
2128 pp
&= ~PANEL_POWER_RESET
;
2129 I915_WRITE(pp_ctrl_reg
, pp
);
2130 POSTING_READ(pp_ctrl_reg
);
2133 pp
|= PANEL_POWER_ON
;
2135 pp
|= PANEL_POWER_RESET
;
2137 I915_WRITE(pp_ctrl_reg
, pp
);
2138 POSTING_READ(pp_ctrl_reg
);
2140 wait_panel_on(intel_dp
);
2141 intel_dp
->last_power_on
= jiffies
;
2144 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2145 I915_WRITE(pp_ctrl_reg
, pp
);
2146 POSTING_READ(pp_ctrl_reg
);
2150 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2152 if (!is_edp(intel_dp
))
2156 edp_panel_on(intel_dp
);
2157 pps_unlock(intel_dp
);
2161 static void edp_panel_off(struct intel_dp
*intel_dp
)
2163 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2164 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2165 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2166 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2167 enum intel_display_power_domain power_domain
;
2169 i915_reg_t pp_ctrl_reg
;
2171 lockdep_assert_held(&dev_priv
->pps_mutex
);
2173 if (!is_edp(intel_dp
))
2176 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2177 port_name(dp_to_dig_port(intel_dp
)->port
));
2179 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2180 port_name(dp_to_dig_port(intel_dp
)->port
));
2182 pp
= ironlake_get_pp_control(intel_dp
);
2183 /* We need to switch off panel power _and_ force vdd, for otherwise some
2184 * panels get very unhappy and cease to work. */
2185 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2188 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2190 intel_dp
->want_panel_vdd
= false;
2192 I915_WRITE(pp_ctrl_reg
, pp
);
2193 POSTING_READ(pp_ctrl_reg
);
2195 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2196 wait_panel_off(intel_dp
);
2198 /* We got a reference when we enabled the VDD. */
2199 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2200 intel_display_power_put(dev_priv
, power_domain
);
2203 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2205 if (!is_edp(intel_dp
))
2209 edp_panel_off(intel_dp
);
2210 pps_unlock(intel_dp
);
2213 /* Enable backlight in the panel power control. */
2214 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2216 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2217 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2218 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2220 i915_reg_t pp_ctrl_reg
;
2223 * If we enable the backlight right away following a panel power
2224 * on, we may see slight flicker as the panel syncs with the eDP
2225 * link. So delay a bit to make sure the image is solid before
2226 * allowing it to appear.
2228 wait_backlight_on(intel_dp
);
2232 pp
= ironlake_get_pp_control(intel_dp
);
2233 pp
|= EDP_BLC_ENABLE
;
2235 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2237 I915_WRITE(pp_ctrl_reg
, pp
);
2238 POSTING_READ(pp_ctrl_reg
);
2240 pps_unlock(intel_dp
);
2243 /* Enable backlight PWM and backlight PP control. */
2244 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2246 if (!is_edp(intel_dp
))
2249 DRM_DEBUG_KMS("\n");
2251 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2252 _intel_edp_backlight_on(intel_dp
);
2255 /* Disable backlight in the panel power control. */
2256 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2258 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2259 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2261 i915_reg_t pp_ctrl_reg
;
2263 if (!is_edp(intel_dp
))
2268 pp
= ironlake_get_pp_control(intel_dp
);
2269 pp
&= ~EDP_BLC_ENABLE
;
2271 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2273 I915_WRITE(pp_ctrl_reg
, pp
);
2274 POSTING_READ(pp_ctrl_reg
);
2276 pps_unlock(intel_dp
);
2278 intel_dp
->last_backlight_off
= jiffies
;
2279 edp_wait_backlight_off(intel_dp
);
2282 /* Disable backlight PP control and backlight PWM. */
2283 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2285 if (!is_edp(intel_dp
))
2288 DRM_DEBUG_KMS("\n");
2290 _intel_edp_backlight_off(intel_dp
);
2291 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2295 * Hook for controlling the panel power control backlight through the bl_power
2296 * sysfs attribute. Take care to handle multiple calls.
2298 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2301 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2305 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2306 pps_unlock(intel_dp
);
2308 if (is_enabled
== enable
)
2311 DRM_DEBUG_KMS("panel power control backlight %s\n",
2312 enable
? "enable" : "disable");
2315 _intel_edp_backlight_on(intel_dp
);
2317 _intel_edp_backlight_off(intel_dp
);
2320 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2322 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2323 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2324 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2326 I915_STATE_WARN(cur_state
!= state
,
2327 "DP port %c state assertion failure (expected %s, current %s)\n",
2328 port_name(dig_port
->port
),
2329 onoff(state
), onoff(cur_state
));
2331 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2333 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2335 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2337 I915_STATE_WARN(cur_state
!= state
,
2338 "eDP PLL state assertion failure (expected %s, current %s)\n",
2339 onoff(state
), onoff(cur_state
));
2341 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2342 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2344 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2345 struct intel_crtc_state
*pipe_config
)
2347 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2348 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2350 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2351 assert_dp_port_disabled(intel_dp
);
2352 assert_edp_pll_disabled(dev_priv
);
2354 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2355 pipe_config
->port_clock
);
2357 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2359 if (pipe_config
->port_clock
== 162000)
2360 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2362 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2364 I915_WRITE(DP_A
, intel_dp
->DP
);
2369 * [DevILK] Work around required when enabling DP PLL
2370 * while a pipe is enabled going to FDI:
2371 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2372 * 2. Program DP PLL enable
2374 if (IS_GEN5(dev_priv
))
2375 intel_wait_for_vblank_if_active(&dev_priv
->drm
, !crtc
->pipe
);
2377 intel_dp
->DP
|= DP_PLL_ENABLE
;
2379 I915_WRITE(DP_A
, intel_dp
->DP
);
2384 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2386 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2387 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2388 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2390 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2391 assert_dp_port_disabled(intel_dp
);
2392 assert_edp_pll_enabled(dev_priv
);
2394 DRM_DEBUG_KMS("disabling eDP PLL\n");
2396 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2398 I915_WRITE(DP_A
, intel_dp
->DP
);
2403 /* If the sink supports it, try to set the power state appropriately */
2404 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2408 /* Should have a valid DPCD by this point */
2409 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2412 if (mode
!= DRM_MODE_DPMS_ON
) {
2413 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2417 * When turning on, we need to retry for 1ms to give the sink
2420 for (i
= 0; i
< 3; i
++) {
2421 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2430 DRM_DEBUG_KMS("failed to %s sink power state\n",
2431 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2434 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2437 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2438 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2439 struct drm_device
*dev
= encoder
->base
.dev
;
2440 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2441 enum intel_display_power_domain power_domain
;
2445 power_domain
= intel_display_port_power_domain(encoder
);
2446 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2451 tmp
= I915_READ(intel_dp
->output_reg
);
2453 if (!(tmp
& DP_PORT_EN
))
2456 if (IS_GEN7(dev
) && port
== PORT_A
) {
2457 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2458 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2461 for_each_pipe(dev_priv
, p
) {
2462 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2463 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2471 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2472 i915_mmio_reg_offset(intel_dp
->output_reg
));
2473 } else if (IS_CHERRYVIEW(dev
)) {
2474 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2476 *pipe
= PORT_TO_PIPE(tmp
);
2482 intel_display_power_put(dev_priv
, power_domain
);
2487 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2488 struct intel_crtc_state
*pipe_config
)
2490 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2492 struct drm_device
*dev
= encoder
->base
.dev
;
2493 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2494 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2495 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2497 tmp
= I915_READ(intel_dp
->output_reg
);
2499 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2501 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2502 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2504 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2505 flags
|= DRM_MODE_FLAG_PHSYNC
;
2507 flags
|= DRM_MODE_FLAG_NHSYNC
;
2509 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2510 flags
|= DRM_MODE_FLAG_PVSYNC
;
2512 flags
|= DRM_MODE_FLAG_NVSYNC
;
2514 if (tmp
& DP_SYNC_HS_HIGH
)
2515 flags
|= DRM_MODE_FLAG_PHSYNC
;
2517 flags
|= DRM_MODE_FLAG_NHSYNC
;
2519 if (tmp
& DP_SYNC_VS_HIGH
)
2520 flags
|= DRM_MODE_FLAG_PVSYNC
;
2522 flags
|= DRM_MODE_FLAG_NVSYNC
;
2525 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2527 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2528 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2529 pipe_config
->limited_color_range
= true;
2531 pipe_config
->lane_count
=
2532 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2534 intel_dp_get_m_n(crtc
, pipe_config
);
2536 if (port
== PORT_A
) {
2537 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2538 pipe_config
->port_clock
= 162000;
2540 pipe_config
->port_clock
= 270000;
2543 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2544 intel_dotclock_calculate(pipe_config
->port_clock
,
2545 &pipe_config
->dp_m_n
);
2547 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2548 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2550 * This is a big fat ugly hack.
2552 * Some machines in UEFI boot mode provide us a VBT that has 18
2553 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2554 * unknown we fail to light up. Yet the same BIOS boots up with
2555 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2556 * max, not what it tells us to use.
2558 * Note: This will still be broken if the eDP panel is not lit
2559 * up by the BIOS, and thus we can't get the mode at module
2562 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2563 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2564 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2568 static void intel_disable_dp(struct intel_encoder
*encoder
,
2569 struct intel_crtc_state
*old_crtc_state
,
2570 struct drm_connector_state
*old_conn_state
)
2572 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2573 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2575 if (old_crtc_state
->has_audio
)
2576 intel_audio_codec_disable(encoder
);
2578 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2579 intel_psr_disable(intel_dp
);
2581 /* Make sure the panel is off before trying to change the mode. But also
2582 * ensure that we have vdd while we switch off the panel. */
2583 intel_edp_panel_vdd_on(intel_dp
);
2584 intel_edp_backlight_off(intel_dp
);
2585 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2586 intel_edp_panel_off(intel_dp
);
2588 /* disable the port before the pipe on g4x */
2589 if (INTEL_GEN(dev_priv
) < 5)
2590 intel_dp_link_down(intel_dp
);
2593 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2594 struct intel_crtc_state
*old_crtc_state
,
2595 struct drm_connector_state
*old_conn_state
)
2597 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2598 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2600 intel_dp_link_down(intel_dp
);
2602 /* Only ilk+ has port A */
2604 ironlake_edp_pll_off(intel_dp
);
2607 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2608 struct intel_crtc_state
*old_crtc_state
,
2609 struct drm_connector_state
*old_conn_state
)
2611 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2613 intel_dp_link_down(intel_dp
);
2616 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2617 struct intel_crtc_state
*old_crtc_state
,
2618 struct drm_connector_state
*old_conn_state
)
2620 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2621 struct drm_device
*dev
= encoder
->base
.dev
;
2622 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2624 intel_dp_link_down(intel_dp
);
2626 mutex_lock(&dev_priv
->sb_lock
);
2628 /* Assert data lane reset */
2629 chv_data_lane_soft_reset(encoder
, true);
2631 mutex_unlock(&dev_priv
->sb_lock
);
2635 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2637 uint8_t dp_train_pat
)
2639 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2640 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2641 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2642 enum port port
= intel_dig_port
->port
;
2644 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2645 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2646 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2649 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2651 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2652 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2654 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2656 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2657 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2658 case DP_TRAINING_PATTERN_DISABLE
:
2659 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2662 case DP_TRAINING_PATTERN_1
:
2663 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2665 case DP_TRAINING_PATTERN_2
:
2666 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2668 case DP_TRAINING_PATTERN_3
:
2669 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2672 I915_WRITE(DP_TP_CTL(port
), temp
);
2674 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2675 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2676 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2678 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2679 case DP_TRAINING_PATTERN_DISABLE
:
2680 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2682 case DP_TRAINING_PATTERN_1
:
2683 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2685 case DP_TRAINING_PATTERN_2
:
2686 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2688 case DP_TRAINING_PATTERN_3
:
2689 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2690 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2695 if (IS_CHERRYVIEW(dev
))
2696 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2698 *DP
&= ~DP_LINK_TRAIN_MASK
;
2700 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2701 case DP_TRAINING_PATTERN_DISABLE
:
2702 *DP
|= DP_LINK_TRAIN_OFF
;
2704 case DP_TRAINING_PATTERN_1
:
2705 *DP
|= DP_LINK_TRAIN_PAT_1
;
2707 case DP_TRAINING_PATTERN_2
:
2708 *DP
|= DP_LINK_TRAIN_PAT_2
;
2710 case DP_TRAINING_PATTERN_3
:
2711 if (IS_CHERRYVIEW(dev
)) {
2712 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2714 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2715 *DP
|= DP_LINK_TRAIN_PAT_2
;
2722 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2723 struct intel_crtc_state
*old_crtc_state
)
2725 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2726 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2728 /* enable with pattern 1 (as per spec) */
2730 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2733 * Magic for VLV/CHV. We _must_ first set up the register
2734 * without actually enabling the port, and then do another
2735 * write to enable the port. Otherwise link training will
2736 * fail when the power sequencer is freshly used for this port.
2738 intel_dp
->DP
|= DP_PORT_EN
;
2739 if (old_crtc_state
->has_audio
)
2740 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2742 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2743 POSTING_READ(intel_dp
->output_reg
);
2746 static void intel_enable_dp(struct intel_encoder
*encoder
,
2747 struct intel_crtc_state
*pipe_config
)
2749 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2750 struct drm_device
*dev
= encoder
->base
.dev
;
2751 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2752 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2753 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2754 enum pipe pipe
= crtc
->pipe
;
2756 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2761 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2762 vlv_init_panel_power_sequencer(intel_dp
);
2764 intel_dp_enable_port(intel_dp
, pipe_config
);
2766 edp_panel_vdd_on(intel_dp
);
2767 edp_panel_on(intel_dp
);
2768 edp_panel_vdd_off(intel_dp
, true);
2770 pps_unlock(intel_dp
);
2772 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2773 unsigned int lane_mask
= 0x0;
2775 if (IS_CHERRYVIEW(dev
))
2776 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2778 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2782 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2783 intel_dp_start_link_train(intel_dp
);
2784 intel_dp_stop_link_train(intel_dp
);
2786 if (pipe_config
->has_audio
) {
2787 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2789 intel_audio_codec_enable(encoder
);
2793 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2794 struct intel_crtc_state
*pipe_config
,
2795 struct drm_connector_state
*conn_state
)
2797 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2799 intel_enable_dp(encoder
, pipe_config
);
2800 intel_edp_backlight_on(intel_dp
);
2803 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2804 struct intel_crtc_state
*pipe_config
,
2805 struct drm_connector_state
*conn_state
)
2807 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2809 intel_edp_backlight_on(intel_dp
);
2810 intel_psr_enable(intel_dp
);
2813 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2814 struct intel_crtc_state
*pipe_config
,
2815 struct drm_connector_state
*conn_state
)
2817 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2818 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2820 intel_dp_prepare(encoder
, pipe_config
);
2822 /* Only ilk+ has port A */
2824 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2827 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2829 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2830 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2831 enum pipe pipe
= intel_dp
->pps_pipe
;
2832 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2834 edp_panel_vdd_off_sync(intel_dp
);
2837 * VLV seems to get confused when multiple power seqeuencers
2838 * have the same port selected (even if only one has power/vdd
2839 * enabled). The failure manifests as vlv_wait_port_ready() failing
2840 * CHV on the other hand doesn't seem to mind having the same port
2841 * selected in multiple power seqeuencers, but let's clear the
2842 * port select always when logically disconnecting a power sequencer
2845 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2846 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2847 I915_WRITE(pp_on_reg
, 0);
2848 POSTING_READ(pp_on_reg
);
2850 intel_dp
->pps_pipe
= INVALID_PIPE
;
2853 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2856 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2857 struct intel_encoder
*encoder
;
2859 lockdep_assert_held(&dev_priv
->pps_mutex
);
2861 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2864 for_each_intel_encoder(dev
, encoder
) {
2865 struct intel_dp
*intel_dp
;
2868 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2871 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2872 port
= dp_to_dig_port(intel_dp
)->port
;
2874 if (intel_dp
->pps_pipe
!= pipe
)
2877 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2878 pipe_name(pipe
), port_name(port
));
2880 WARN(encoder
->base
.crtc
,
2881 "stealing pipe %c power sequencer from active eDP port %c\n",
2882 pipe_name(pipe
), port_name(port
));
2884 /* make sure vdd is off before we steal it */
2885 vlv_detach_power_sequencer(intel_dp
);
2889 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2891 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2892 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2893 struct drm_device
*dev
= encoder
->base
.dev
;
2894 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2895 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2897 lockdep_assert_held(&dev_priv
->pps_mutex
);
2899 if (!is_edp(intel_dp
))
2902 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2906 * If another power sequencer was being used on this
2907 * port previously make sure to turn off vdd there while
2908 * we still have control of it.
2910 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2911 vlv_detach_power_sequencer(intel_dp
);
2914 * We may be stealing the power
2915 * sequencer from another port.
2917 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2919 /* now it's all ours */
2920 intel_dp
->pps_pipe
= crtc
->pipe
;
2922 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2923 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2925 /* init power sequencer on this pipe and port */
2926 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2927 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2930 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
2931 struct intel_crtc_state
*pipe_config
,
2932 struct drm_connector_state
*conn_state
)
2934 vlv_phy_pre_encoder_enable(encoder
);
2936 intel_enable_dp(encoder
, pipe_config
);
2939 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2940 struct intel_crtc_state
*pipe_config
,
2941 struct drm_connector_state
*conn_state
)
2943 intel_dp_prepare(encoder
, pipe_config
);
2945 vlv_phy_pre_pll_enable(encoder
);
2948 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
2949 struct intel_crtc_state
*pipe_config
,
2950 struct drm_connector_state
*conn_state
)
2952 chv_phy_pre_encoder_enable(encoder
);
2954 intel_enable_dp(encoder
, pipe_config
);
2956 /* Second common lane will stay alive on its own now */
2957 chv_phy_release_cl2_override(encoder
);
2960 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
2961 struct intel_crtc_state
*pipe_config
,
2962 struct drm_connector_state
*conn_state
)
2964 intel_dp_prepare(encoder
, pipe_config
);
2966 chv_phy_pre_pll_enable(encoder
);
2969 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
2970 struct intel_crtc_state
*pipe_config
,
2971 struct drm_connector_state
*conn_state
)
2973 chv_phy_post_pll_disable(encoder
);
2977 * Fetch AUX CH registers 0x202 - 0x207 which contain
2978 * link status information
2981 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2983 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2984 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2987 /* These are source-specific values. */
2989 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2991 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2992 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2993 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2995 if (IS_BROXTON(dev
))
2996 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2997 else if (INTEL_INFO(dev
)->gen
>= 9) {
2998 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2999 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3000 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3001 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3002 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3003 else if (IS_GEN7(dev
) && port
== PORT_A
)
3004 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3005 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
3006 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3008 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3012 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3014 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3015 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3017 if (INTEL_INFO(dev
)->gen
>= 9) {
3018 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3026 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3028 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3030 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3031 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3033 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3035 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3037 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3040 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3042 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
3043 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3045 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3049 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3052 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3054 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3055 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3057 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3060 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3062 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3065 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3067 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3069 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3071 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3074 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3079 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3081 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3082 unsigned long demph_reg_value
, preemph_reg_value
,
3083 uniqtranscale_reg_value
;
3084 uint8_t train_set
= intel_dp
->train_set
[0];
3086 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3087 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3088 preemph_reg_value
= 0x0004000;
3089 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3091 demph_reg_value
= 0x2B405555;
3092 uniqtranscale_reg_value
= 0x552AB83A;
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3095 demph_reg_value
= 0x2B404040;
3096 uniqtranscale_reg_value
= 0x5548B83A;
3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3099 demph_reg_value
= 0x2B245555;
3100 uniqtranscale_reg_value
= 0x5560B83A;
3102 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3103 demph_reg_value
= 0x2B405555;
3104 uniqtranscale_reg_value
= 0x5598DA3A;
3110 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3111 preemph_reg_value
= 0x0002000;
3112 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3114 demph_reg_value
= 0x2B404040;
3115 uniqtranscale_reg_value
= 0x5552B83A;
3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3118 demph_reg_value
= 0x2B404848;
3119 uniqtranscale_reg_value
= 0x5580B83A;
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3122 demph_reg_value
= 0x2B404040;
3123 uniqtranscale_reg_value
= 0x55ADDA3A;
3129 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3130 preemph_reg_value
= 0x0000000;
3131 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3133 demph_reg_value
= 0x2B305555;
3134 uniqtranscale_reg_value
= 0x5570B83A;
3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3137 demph_reg_value
= 0x2B2B4040;
3138 uniqtranscale_reg_value
= 0x55ADDA3A;
3144 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3145 preemph_reg_value
= 0x0006000;
3146 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3148 demph_reg_value
= 0x1B405555;
3149 uniqtranscale_reg_value
= 0x55ADDA3A;
3159 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3160 uniqtranscale_reg_value
, 0);
3165 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3167 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3168 u32 deemph_reg_value
, margin_reg_value
;
3169 bool uniq_trans_scale
= false;
3170 uint8_t train_set
= intel_dp
->train_set
[0];
3172 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3173 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3174 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3176 deemph_reg_value
= 128;
3177 margin_reg_value
= 52;
3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3180 deemph_reg_value
= 128;
3181 margin_reg_value
= 77;
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3184 deemph_reg_value
= 128;
3185 margin_reg_value
= 102;
3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3188 deemph_reg_value
= 128;
3189 margin_reg_value
= 154;
3190 uniq_trans_scale
= true;
3196 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3197 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3199 deemph_reg_value
= 85;
3200 margin_reg_value
= 78;
3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3203 deemph_reg_value
= 85;
3204 margin_reg_value
= 116;
3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3207 deemph_reg_value
= 85;
3208 margin_reg_value
= 154;
3214 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3215 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3217 deemph_reg_value
= 64;
3218 margin_reg_value
= 104;
3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3221 deemph_reg_value
= 64;
3222 margin_reg_value
= 154;
3228 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3229 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3231 deemph_reg_value
= 43;
3232 margin_reg_value
= 154;
3242 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3243 margin_reg_value
, uniq_trans_scale
);
3249 gen4_signal_levels(uint8_t train_set
)
3251 uint32_t signal_levels
= 0;
3253 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3256 signal_levels
|= DP_VOLTAGE_0_4
;
3258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3259 signal_levels
|= DP_VOLTAGE_0_6
;
3261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3262 signal_levels
|= DP_VOLTAGE_0_8
;
3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3265 signal_levels
|= DP_VOLTAGE_1_2
;
3268 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3269 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3271 signal_levels
|= DP_PRE_EMPHASIS_0
;
3273 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3274 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3276 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3277 signal_levels
|= DP_PRE_EMPHASIS_6
;
3279 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3280 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3283 return signal_levels
;
3286 /* Gen6's DP voltage swing and pre-emphasis control */
3288 gen6_edp_signal_levels(uint8_t train_set
)
3290 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3291 DP_TRAIN_PRE_EMPHASIS_MASK
);
3292 switch (signal_levels
) {
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3295 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3297 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3298 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3300 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3303 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3306 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3308 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3309 "0x%x\n", signal_levels
);
3310 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3314 /* Gen7's DP voltage swing and pre-emphasis control */
3316 gen7_edp_signal_levels(uint8_t train_set
)
3318 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3319 DP_TRAIN_PRE_EMPHASIS_MASK
);
3320 switch (signal_levels
) {
3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3322 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3324 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3326 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3328 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3329 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3331 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3334 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3336 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3339 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3340 "0x%x\n", signal_levels
);
3341 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3346 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3348 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3349 enum port port
= intel_dig_port
->port
;
3350 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3351 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3352 uint32_t signal_levels
, mask
= 0;
3353 uint8_t train_set
= intel_dp
->train_set
[0];
3356 signal_levels
= ddi_signal_levels(intel_dp
);
3358 if (IS_BROXTON(dev
))
3361 mask
= DDI_BUF_EMP_MASK
;
3362 } else if (IS_CHERRYVIEW(dev
)) {
3363 signal_levels
= chv_signal_levels(intel_dp
);
3364 } else if (IS_VALLEYVIEW(dev
)) {
3365 signal_levels
= vlv_signal_levels(intel_dp
);
3366 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3367 signal_levels
= gen7_edp_signal_levels(train_set
);
3368 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3369 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3370 signal_levels
= gen6_edp_signal_levels(train_set
);
3371 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3373 signal_levels
= gen4_signal_levels(train_set
);
3374 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3378 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3380 DRM_DEBUG_KMS("Using vswing level %d\n",
3381 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3382 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3383 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3384 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3386 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3388 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3389 POSTING_READ(intel_dp
->output_reg
);
3393 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3394 uint8_t dp_train_pat
)
3396 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3397 struct drm_i915_private
*dev_priv
=
3398 to_i915(intel_dig_port
->base
.base
.dev
);
3400 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3402 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3403 POSTING_READ(intel_dp
->output_reg
);
3406 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3408 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3409 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3410 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3411 enum port port
= intel_dig_port
->port
;
3417 val
= I915_READ(DP_TP_CTL(port
));
3418 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3419 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3420 I915_WRITE(DP_TP_CTL(port
), val
);
3423 * On PORT_A we can have only eDP in SST mode. There the only reason
3424 * we need to set idle transmission mode is to work around a HW issue
3425 * where we enable the pipe while not in idle link-training mode.
3426 * In this case there is requirement to wait for a minimum number of
3427 * idle patterns to be sent.
3432 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3433 DP_TP_STATUS_IDLE_DONE
,
3434 DP_TP_STATUS_IDLE_DONE
,
3436 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3440 intel_dp_link_down(struct intel_dp
*intel_dp
)
3442 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3443 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3444 enum port port
= intel_dig_port
->port
;
3445 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3446 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3447 uint32_t DP
= intel_dp
->DP
;
3449 if (WARN_ON(HAS_DDI(dev
)))
3452 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3455 DRM_DEBUG_KMS("\n");
3457 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3458 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3459 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3460 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3462 if (IS_CHERRYVIEW(dev
))
3463 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3465 DP
&= ~DP_LINK_TRAIN_MASK
;
3466 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3468 I915_WRITE(intel_dp
->output_reg
, DP
);
3469 POSTING_READ(intel_dp
->output_reg
);
3471 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3472 I915_WRITE(intel_dp
->output_reg
, DP
);
3473 POSTING_READ(intel_dp
->output_reg
);
3476 * HW workaround for IBX, we need to move the port
3477 * to transcoder A after disabling it to allow the
3478 * matching HDMI port to be enabled on transcoder A.
3480 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3482 * We get CPU/PCH FIFO underruns on the other pipe when
3483 * doing the workaround. Sweep them under the rug.
3485 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3486 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3488 /* always enable with pattern 1 (as per spec) */
3489 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3490 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3491 I915_WRITE(intel_dp
->output_reg
, DP
);
3492 POSTING_READ(intel_dp
->output_reg
);
3495 I915_WRITE(intel_dp
->output_reg
, DP
);
3496 POSTING_READ(intel_dp
->output_reg
);
3498 intel_wait_for_vblank_if_active(&dev_priv
->drm
, PIPE_A
);
3499 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3500 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3503 msleep(intel_dp
->panel_power_down_delay
);
3509 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3511 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3512 sizeof(intel_dp
->dpcd
)) < 0)
3513 return false; /* aux transfer failed */
3515 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3517 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3521 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3523 struct drm_i915_private
*dev_priv
=
3524 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3526 /* this function is meant to be called only once */
3527 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3529 if (!intel_dp_read_dpcd(intel_dp
))
3532 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3533 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3534 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3536 /* Check if the panel supports PSR */
3537 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3539 sizeof(intel_dp
->psr_dpcd
));
3540 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3541 dev_priv
->psr
.sink_support
= true;
3542 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3545 if (INTEL_GEN(dev_priv
) >= 9 &&
3546 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3547 uint8_t frame_sync_cap
;
3549 dev_priv
->psr
.sink_support
= true;
3550 drm_dp_dpcd_read(&intel_dp
->aux
,
3551 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3552 &frame_sync_cap
, 1);
3553 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3554 /* PSR2 needs frame sync as well */
3555 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3556 DRM_DEBUG_KMS("PSR2 %s on sink",
3557 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3560 /* Read the eDP Display control capabilities registers */
3561 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3562 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3563 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3564 sizeof(intel_dp
->edp_dpcd
))
3565 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3566 intel_dp
->edp_dpcd
);
3568 /* Intermediate frequency support */
3569 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3570 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3573 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3574 sink_rates
, sizeof(sink_rates
));
3576 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3577 int val
= le16_to_cpu(sink_rates
[i
]);
3582 /* Value read is in kHz while drm clock is saved in deca-kHz */
3583 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3585 intel_dp
->num_sink_rates
= i
;
3593 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3595 if (!intel_dp_read_dpcd(intel_dp
))
3598 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3599 &intel_dp
->sink_count
, 1) < 0)
3603 * Sink count can change between short pulse hpd hence
3604 * a member variable in intel_dp will track any changes
3605 * between short pulse interrupts.
3607 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3610 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3611 * a dongle is present but no display. Unless we require to know
3612 * if a dongle is present or not, we don't need to update
3613 * downstream port information. So, an early return here saves
3614 * time from performing other operations which are not required.
3616 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3619 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3620 DP_DWN_STRM_PORT_PRESENT
))
3621 return true; /* native DP sink */
3623 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3624 return true; /* no per-port downstream info */
3626 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3627 intel_dp
->downstream_ports
,
3628 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3629 return false; /* downstream port status fetch failed */
3635 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3639 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3642 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3643 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3644 buf
[0], buf
[1], buf
[2]);
3646 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3647 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3648 buf
[0], buf
[1], buf
[2]);
3652 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3656 if (!i915
.enable_dp_mst
)
3659 if (!intel_dp
->can_mst
)
3662 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3665 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1) != 1)
3668 return buf
[0] & DP_MST_CAP
;
3672 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3674 if (!i915
.enable_dp_mst
)
3677 if (!intel_dp
->can_mst
)
3680 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3682 if (intel_dp
->is_mst
)
3683 DRM_DEBUG_KMS("Sink is MST capable\n");
3685 DRM_DEBUG_KMS("Sink is not MST capable\n");
3687 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3691 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3693 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3694 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3695 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3701 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3702 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3707 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3708 buf
& ~DP_TEST_SINK_START
) < 0) {
3709 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3715 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3717 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3718 DP_TEST_SINK_MISC
, &buf
) < 0) {
3722 count
= buf
& DP_TEST_COUNT_MASK
;
3723 } while (--attempts
&& count
);
3725 if (attempts
== 0) {
3726 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3731 hsw_enable_ips(intel_crtc
);
3735 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3737 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3738 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3739 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3743 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3746 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3749 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3752 if (buf
& DP_TEST_SINK_START
) {
3753 ret
= intel_dp_sink_crc_stop(intel_dp
);
3758 hsw_disable_ips(intel_crtc
);
3760 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3761 buf
| DP_TEST_SINK_START
) < 0) {
3762 hsw_enable_ips(intel_crtc
);
3766 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3770 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3772 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3773 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3774 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3779 ret
= intel_dp_sink_crc_start(intel_dp
);
3784 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3786 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3787 DP_TEST_SINK_MISC
, &buf
) < 0) {
3791 count
= buf
& DP_TEST_COUNT_MASK
;
3793 } while (--attempts
&& count
== 0);
3795 if (attempts
== 0) {
3796 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3801 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3807 intel_dp_sink_crc_stop(intel_dp
);
3812 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3814 return drm_dp_dpcd_read(&intel_dp
->aux
,
3815 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3816 sink_irq_vector
, 1) == 1;
3820 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3824 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3826 sink_irq_vector
, 14);
3833 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3835 uint8_t test_result
= DP_TEST_ACK
;
3839 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3841 uint8_t test_result
= DP_TEST_NAK
;
3845 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3847 uint8_t test_result
= DP_TEST_NAK
;
3848 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3849 struct drm_connector
*connector
= &intel_connector
->base
;
3851 if (intel_connector
->detect_edid
== NULL
||
3852 connector
->edid_corrupt
||
3853 intel_dp
->aux
.i2c_defer_count
> 6) {
3854 /* Check EDID read for NACKs, DEFERs and corruption
3855 * (DP CTS 1.2 Core r1.1)
3856 * 4.2.2.4 : Failed EDID read, I2C_NAK
3857 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3858 * 4.2.2.6 : EDID corruption detected
3859 * Use failsafe mode for all cases
3861 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3862 intel_dp
->aux
.i2c_defer_count
> 0)
3863 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3864 intel_dp
->aux
.i2c_nack_count
,
3865 intel_dp
->aux
.i2c_defer_count
);
3866 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3868 struct edid
*block
= intel_connector
->detect_edid
;
3870 /* We have to write the checksum
3871 * of the last block read
3873 block
+= intel_connector
->detect_edid
->extensions
;
3875 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3876 DP_TEST_EDID_CHECKSUM
,
3879 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3881 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3882 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3885 /* Set test active flag here so userspace doesn't interrupt things */
3886 intel_dp
->compliance_test_active
= 1;
3891 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3893 uint8_t test_result
= DP_TEST_NAK
;
3897 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3899 uint8_t response
= DP_TEST_NAK
;
3903 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3905 DRM_DEBUG_KMS("Could not read test request from sink\n");
3910 case DP_TEST_LINK_TRAINING
:
3911 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3912 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3913 response
= intel_dp_autotest_link_training(intel_dp
);
3915 case DP_TEST_LINK_VIDEO_PATTERN
:
3916 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3917 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3918 response
= intel_dp_autotest_video_pattern(intel_dp
);
3920 case DP_TEST_LINK_EDID_READ
:
3921 DRM_DEBUG_KMS("EDID test requested\n");
3922 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3923 response
= intel_dp_autotest_edid(intel_dp
);
3925 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3926 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3927 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3928 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3931 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3936 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3940 DRM_DEBUG_KMS("Could not write test response to sink\n");
3944 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3948 if (intel_dp
->is_mst
) {
3953 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3957 /* check link status - esi[10] = 0x200c */
3958 if (intel_dp
->active_mst_links
&&
3959 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3960 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3961 intel_dp_start_link_train(intel_dp
);
3962 intel_dp_stop_link_train(intel_dp
);
3965 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3966 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3969 for (retry
= 0; retry
< 3; retry
++) {
3971 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3972 DP_SINK_COUNT_ESI
+1,
3979 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3981 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3989 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3990 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3991 intel_dp
->is_mst
= false;
3992 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3993 /* send a hotplug event */
3994 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4001 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4003 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4004 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4005 u8 link_status
[DP_LINK_STATUS_SIZE
];
4007 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4009 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4010 DRM_ERROR("Failed to get link status\n");
4014 if (!intel_encoder
->base
.crtc
)
4017 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4020 /* if link training is requested we should perform it always */
4021 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
4022 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
4023 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4024 intel_encoder
->base
.name
);
4025 intel_dp_start_link_train(intel_dp
);
4026 intel_dp_stop_link_train(intel_dp
);
4031 * According to DP spec
4034 * 2. Configure link according to Receiver Capabilities
4035 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4036 * 4. Check link status on receipt of hot-plug interrupt
4038 * intel_dp_short_pulse - handles short pulse interrupts
4039 * when full detection is not required.
4040 * Returns %true if short pulse is handled and full detection
4041 * is NOT required and %false otherwise.
4044 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4046 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4047 u8 sink_irq_vector
= 0;
4048 u8 old_sink_count
= intel_dp
->sink_count
;
4052 * Clearing compliance test variables to allow capturing
4053 * of values for next automated test request.
4055 intel_dp
->compliance_test_active
= 0;
4056 intel_dp
->compliance_test_type
= 0;
4057 intel_dp
->compliance_test_data
= 0;
4060 * Now read the DPCD to see if it's actually running
4061 * If the current value of sink count doesn't match with
4062 * the value that was stored earlier or dpcd read failed
4063 * we need to do full detection
4065 ret
= intel_dp_get_dpcd(intel_dp
);
4067 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4068 /* No need to proceed if we are going to do full detect */
4072 /* Try to read the source of the interrupt */
4073 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4074 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4075 sink_irq_vector
!= 0) {
4076 /* Clear interrupt source */
4077 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4078 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4081 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4082 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4083 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4084 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4087 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4088 intel_dp_check_link_status(intel_dp
);
4089 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4094 /* XXX this is probably wrong for multiple downstream ports */
4095 static enum drm_connector_status
4096 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4098 uint8_t *dpcd
= intel_dp
->dpcd
;
4101 if (!intel_dp_get_dpcd(intel_dp
))
4102 return connector_status_disconnected
;
4104 if (is_edp(intel_dp
))
4105 return connector_status_connected
;
4107 /* if there's no downstream port, we're done */
4108 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4109 return connector_status_connected
;
4111 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4112 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4113 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4115 return intel_dp
->sink_count
?
4116 connector_status_connected
: connector_status_disconnected
;
4119 if (intel_dp_can_mst(intel_dp
))
4120 return connector_status_connected
;
4122 /* If no HPD, poke DDC gently */
4123 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4124 return connector_status_connected
;
4126 /* Well we tried, say unknown for unreliable port types */
4127 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4128 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4129 if (type
== DP_DS_PORT_TYPE_VGA
||
4130 type
== DP_DS_PORT_TYPE_NON_EDID
)
4131 return connector_status_unknown
;
4133 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4134 DP_DWN_STRM_PORT_TYPE_MASK
;
4135 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4136 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4137 return connector_status_unknown
;
4140 /* Anything else is out of spec, warn and ignore */
4141 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4142 return connector_status_disconnected
;
4145 static enum drm_connector_status
4146 edp_detect(struct intel_dp
*intel_dp
)
4148 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4149 enum drm_connector_status status
;
4151 status
= intel_panel_detect(dev
);
4152 if (status
== connector_status_unknown
)
4153 status
= connector_status_connected
;
4158 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4159 struct intel_digital_port
*port
)
4163 switch (port
->port
) {
4167 bit
= SDE_PORTB_HOTPLUG
;
4170 bit
= SDE_PORTC_HOTPLUG
;
4173 bit
= SDE_PORTD_HOTPLUG
;
4176 MISSING_CASE(port
->port
);
4180 return I915_READ(SDEISR
) & bit
;
4183 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4184 struct intel_digital_port
*port
)
4188 switch (port
->port
) {
4192 bit
= SDE_PORTB_HOTPLUG_CPT
;
4195 bit
= SDE_PORTC_HOTPLUG_CPT
;
4198 bit
= SDE_PORTD_HOTPLUG_CPT
;
4201 bit
= SDE_PORTE_HOTPLUG_SPT
;
4204 MISSING_CASE(port
->port
);
4208 return I915_READ(SDEISR
) & bit
;
4211 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4212 struct intel_digital_port
*port
)
4216 switch (port
->port
) {
4218 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4221 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4224 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4227 MISSING_CASE(port
->port
);
4231 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4234 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4235 struct intel_digital_port
*port
)
4239 switch (port
->port
) {
4241 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4244 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4247 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4250 MISSING_CASE(port
->port
);
4254 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4257 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4258 struct intel_digital_port
*intel_dig_port
)
4260 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4264 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4267 bit
= BXT_DE_PORT_HP_DDIA
;
4270 bit
= BXT_DE_PORT_HP_DDIB
;
4273 bit
= BXT_DE_PORT_HP_DDIC
;
4280 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4284 * intel_digital_port_connected - is the specified port connected?
4285 * @dev_priv: i915 private structure
4286 * @port: the port to test
4288 * Return %true if @port is connected, %false otherwise.
4290 static bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4291 struct intel_digital_port
*port
)
4293 if (HAS_PCH_IBX(dev_priv
))
4294 return ibx_digital_port_connected(dev_priv
, port
);
4295 else if (HAS_PCH_SPLIT(dev_priv
))
4296 return cpt_digital_port_connected(dev_priv
, port
);
4297 else if (IS_BROXTON(dev_priv
))
4298 return bxt_digital_port_connected(dev_priv
, port
);
4299 else if (IS_GM45(dev_priv
))
4300 return gm45_digital_port_connected(dev_priv
, port
);
4302 return g4x_digital_port_connected(dev_priv
, port
);
4305 static struct edid
*
4306 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4308 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4310 /* use cached edid if we have one */
4311 if (intel_connector
->edid
) {
4313 if (IS_ERR(intel_connector
->edid
))
4316 return drm_edid_duplicate(intel_connector
->edid
);
4318 return drm_get_edid(&intel_connector
->base
,
4319 &intel_dp
->aux
.ddc
);
4323 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4325 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4328 intel_dp_unset_edid(intel_dp
);
4329 edid
= intel_dp_get_edid(intel_dp
);
4330 intel_connector
->detect_edid
= edid
;
4332 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4333 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4335 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4339 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4341 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4343 kfree(intel_connector
->detect_edid
);
4344 intel_connector
->detect_edid
= NULL
;
4346 intel_dp
->has_audio
= false;
4349 static enum drm_connector_status
4350 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4352 struct drm_connector
*connector
= &intel_connector
->base
;
4353 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4354 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4355 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4356 struct drm_device
*dev
= connector
->dev
;
4357 enum drm_connector_status status
;
4358 enum intel_display_power_domain power_domain
;
4359 u8 sink_irq_vector
= 0;
4361 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4362 intel_display_power_get(to_i915(dev
), power_domain
);
4364 /* Can't disconnect eDP, but you can close the lid... */
4365 if (is_edp(intel_dp
))
4366 status
= edp_detect(intel_dp
);
4367 else if (intel_digital_port_connected(to_i915(dev
),
4368 dp_to_dig_port(intel_dp
)))
4369 status
= intel_dp_detect_dpcd(intel_dp
);
4371 status
= connector_status_disconnected
;
4373 if (status
== connector_status_disconnected
) {
4374 intel_dp
->compliance_test_active
= 0;
4375 intel_dp
->compliance_test_type
= 0;
4376 intel_dp
->compliance_test_data
= 0;
4378 if (intel_dp
->is_mst
) {
4379 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4381 intel_dp
->mst_mgr
.mst_state
);
4382 intel_dp
->is_mst
= false;
4383 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4390 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4391 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4393 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4394 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4395 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4397 intel_dp_print_rates(intel_dp
);
4399 intel_dp_probe_oui(intel_dp
);
4401 intel_dp_print_hw_revision(intel_dp
);
4402 intel_dp_print_sw_revision(intel_dp
);
4404 intel_dp_configure_mst(intel_dp
);
4406 if (intel_dp
->is_mst
) {
4408 * If we are in MST mode then this connector
4409 * won't appear connected or have anything
4412 status
= connector_status_disconnected
;
4414 } else if (connector
->status
== connector_status_connected
) {
4416 * If display was connected already and is still connected
4417 * check links status, there has been known issues of
4418 * link loss triggerring long pulse!!!!
4420 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4421 intel_dp_check_link_status(intel_dp
);
4422 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4427 * Clearing NACK and defer counts to get their exact values
4428 * while reading EDID which are required by Compliance tests
4429 * 4.2.2.4 and 4.2.2.5
4431 intel_dp
->aux
.i2c_nack_count
= 0;
4432 intel_dp
->aux
.i2c_defer_count
= 0;
4434 intel_dp_set_edid(intel_dp
);
4435 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4436 status
= connector_status_connected
;
4437 intel_dp
->detect_done
= true;
4439 /* Try to read the source of the interrupt */
4440 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4441 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4442 sink_irq_vector
!= 0) {
4443 /* Clear interrupt source */
4444 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4445 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4448 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4449 intel_dp_handle_test_request(intel_dp
);
4450 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4451 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4455 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4456 intel_dp_unset_edid(intel_dp
);
4458 intel_display_power_put(to_i915(dev
), power_domain
);
4462 static enum drm_connector_status
4463 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4465 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4466 enum drm_connector_status status
= connector
->status
;
4468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4469 connector
->base
.id
, connector
->name
);
4471 /* If full detect is not performed yet, do a full detect */
4472 if (!intel_dp
->detect_done
)
4473 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4475 intel_dp
->detect_done
= false;
4481 intel_dp_force(struct drm_connector
*connector
)
4483 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4484 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4485 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4486 enum intel_display_power_domain power_domain
;
4488 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4489 connector
->base
.id
, connector
->name
);
4490 intel_dp_unset_edid(intel_dp
);
4492 if (connector
->status
!= connector_status_connected
)
4495 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4496 intel_display_power_get(dev_priv
, power_domain
);
4498 intel_dp_set_edid(intel_dp
);
4500 intel_display_power_put(dev_priv
, power_domain
);
4502 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4503 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4506 static int intel_dp_get_modes(struct drm_connector
*connector
)
4508 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4511 edid
= intel_connector
->detect_edid
;
4513 int ret
= intel_connector_update_modes(connector
, edid
);
4518 /* if eDP has no EDID, fall back to fixed mode */
4519 if (is_edp(intel_attached_dp(connector
)) &&
4520 intel_connector
->panel
.fixed_mode
) {
4521 struct drm_display_mode
*mode
;
4523 mode
= drm_mode_duplicate(connector
->dev
,
4524 intel_connector
->panel
.fixed_mode
);
4526 drm_mode_probed_add(connector
, mode
);
4535 intel_dp_detect_audio(struct drm_connector
*connector
)
4537 bool has_audio
= false;
4540 edid
= to_intel_connector(connector
)->detect_edid
;
4542 has_audio
= drm_detect_monitor_audio(edid
);
4548 intel_dp_set_property(struct drm_connector
*connector
,
4549 struct drm_property
*property
,
4552 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
4553 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4554 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4555 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4558 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4562 if (property
== dev_priv
->force_audio_property
) {
4566 if (i
== intel_dp
->force_audio
)
4569 intel_dp
->force_audio
= i
;
4571 if (i
== HDMI_AUDIO_AUTO
)
4572 has_audio
= intel_dp_detect_audio(connector
);
4574 has_audio
= (i
== HDMI_AUDIO_ON
);
4576 if (has_audio
== intel_dp
->has_audio
)
4579 intel_dp
->has_audio
= has_audio
;
4583 if (property
== dev_priv
->broadcast_rgb_property
) {
4584 bool old_auto
= intel_dp
->color_range_auto
;
4585 bool old_range
= intel_dp
->limited_color_range
;
4588 case INTEL_BROADCAST_RGB_AUTO
:
4589 intel_dp
->color_range_auto
= true;
4591 case INTEL_BROADCAST_RGB_FULL
:
4592 intel_dp
->color_range_auto
= false;
4593 intel_dp
->limited_color_range
= false;
4595 case INTEL_BROADCAST_RGB_LIMITED
:
4596 intel_dp
->color_range_auto
= false;
4597 intel_dp
->limited_color_range
= true;
4603 if (old_auto
== intel_dp
->color_range_auto
&&
4604 old_range
== intel_dp
->limited_color_range
)
4610 if (is_edp(intel_dp
) &&
4611 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4612 if (val
== DRM_MODE_SCALE_NONE
) {
4613 DRM_DEBUG_KMS("no scaling not supported\n");
4616 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4617 val
== DRM_MODE_SCALE_CENTER
) {
4618 DRM_DEBUG_KMS("centering not supported\n");
4622 if (intel_connector
->panel
.fitting_mode
== val
) {
4623 /* the eDP scaling property is not changed */
4626 intel_connector
->panel
.fitting_mode
= val
;
4634 if (intel_encoder
->base
.crtc
)
4635 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4641 intel_dp_connector_register(struct drm_connector
*connector
)
4643 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4646 ret
= intel_connector_register(connector
);
4650 i915_debugfs_connector_add(connector
);
4652 DRM_DEBUG_KMS("registering %s bus for %s\n",
4653 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4655 intel_dp
->aux
.dev
= connector
->kdev
;
4656 return drm_dp_aux_register(&intel_dp
->aux
);
4660 intel_dp_connector_unregister(struct drm_connector
*connector
)
4662 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4663 intel_connector_unregister(connector
);
4667 intel_dp_connector_destroy(struct drm_connector
*connector
)
4669 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4671 kfree(intel_connector
->detect_edid
);
4673 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4674 kfree(intel_connector
->edid
);
4676 /* Can't call is_edp() since the encoder may have been destroyed
4678 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4679 intel_panel_fini(&intel_connector
->panel
);
4681 drm_connector_cleanup(connector
);
4685 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4687 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4688 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4690 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4691 if (is_edp(intel_dp
)) {
4692 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4694 * vdd might still be enabled do to the delayed vdd off.
4695 * Make sure vdd is actually turned off here.
4698 edp_panel_vdd_off_sync(intel_dp
);
4699 pps_unlock(intel_dp
);
4701 if (intel_dp
->edp_notifier
.notifier_call
) {
4702 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4703 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4707 intel_dp_aux_fini(intel_dp
);
4709 drm_encoder_cleanup(encoder
);
4710 kfree(intel_dig_port
);
4713 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4715 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4717 if (!is_edp(intel_dp
))
4721 * vdd might still be enabled do to the delayed vdd off.
4722 * Make sure vdd is actually turned off here.
4724 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4726 edp_panel_vdd_off_sync(intel_dp
);
4727 pps_unlock(intel_dp
);
4730 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4732 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4733 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4734 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4735 enum intel_display_power_domain power_domain
;
4737 lockdep_assert_held(&dev_priv
->pps_mutex
);
4739 if (!edp_have_panel_vdd(intel_dp
))
4743 * The VDD bit needs a power domain reference, so if the bit is
4744 * already enabled when we boot or resume, grab this reference and
4745 * schedule a vdd off, so we don't hold on to the reference
4748 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4749 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4750 intel_display_power_get(dev_priv
, power_domain
);
4752 edp_panel_vdd_schedule_off(intel_dp
);
4755 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4757 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4758 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4760 if (!HAS_DDI(dev_priv
))
4761 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4763 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4768 /* Reinit the power sequencer, in case BIOS did something with it. */
4769 intel_dp_pps_init(encoder
->dev
, intel_dp
);
4770 intel_edp_panel_vdd_sanitize(intel_dp
);
4772 pps_unlock(intel_dp
);
4775 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4776 .dpms
= drm_atomic_helper_connector_dpms
,
4777 .detect
= intel_dp_detect
,
4778 .force
= intel_dp_force
,
4779 .fill_modes
= drm_helper_probe_single_connector_modes
,
4780 .set_property
= intel_dp_set_property
,
4781 .atomic_get_property
= intel_connector_atomic_get_property
,
4782 .late_register
= intel_dp_connector_register
,
4783 .early_unregister
= intel_dp_connector_unregister
,
4784 .destroy
= intel_dp_connector_destroy
,
4785 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4786 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4789 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4790 .get_modes
= intel_dp_get_modes
,
4791 .mode_valid
= intel_dp_mode_valid
,
4794 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4795 .reset
= intel_dp_encoder_reset
,
4796 .destroy
= intel_dp_encoder_destroy
,
4800 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4802 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4803 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4804 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4805 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4806 enum intel_display_power_domain power_domain
;
4807 enum irqreturn ret
= IRQ_NONE
;
4809 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4810 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4811 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
4813 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4815 * vdd off can generate a long pulse on eDP which
4816 * would require vdd on to handle it, and thus we
4817 * would end up in an endless cycle of
4818 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4820 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4821 port_name(intel_dig_port
->port
));
4825 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4826 port_name(intel_dig_port
->port
),
4827 long_hpd
? "long" : "short");
4830 intel_dp
->detect_done
= false;
4834 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4835 intel_display_power_get(dev_priv
, power_domain
);
4837 if (intel_dp
->is_mst
) {
4838 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4840 * If we were in MST mode, and device is not
4841 * there, get out of MST mode
4843 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4844 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4845 intel_dp
->is_mst
= false;
4846 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4848 intel_dp
->detect_done
= false;
4853 if (!intel_dp
->is_mst
) {
4854 if (!intel_dp_short_pulse(intel_dp
)) {
4855 intel_dp
->detect_done
= false;
4863 intel_display_power_put(dev_priv
, power_domain
);
4868 /* check the VBT to see whether the eDP is on another port */
4869 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4871 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4874 * eDP not supported on g4x. so bail out early just
4875 * for a bit extra safety in case the VBT is bonkers.
4877 if (INTEL_INFO(dev
)->gen
< 5)
4883 return intel_bios_is_port_edp(dev_priv
, port
);
4887 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4889 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4891 intel_attach_force_audio_property(connector
);
4892 intel_attach_broadcast_rgb_property(connector
);
4893 intel_dp
->color_range_auto
= true;
4895 if (is_edp(intel_dp
)) {
4896 drm_mode_create_scaling_mode_property(connector
->dev
);
4897 drm_object_attach_property(
4899 connector
->dev
->mode_config
.scaling_mode_property
,
4900 DRM_MODE_SCALE_ASPECT
);
4901 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4905 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4907 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4908 intel_dp
->last_power_on
= jiffies
;
4909 intel_dp
->last_backlight_off
= jiffies
;
4913 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4914 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4916 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4917 struct pps_registers regs
;
4919 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4921 /* Workaround: Need to write PP_CONTROL with the unlock key as
4922 * the very first thing. */
4923 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4925 pp_on
= I915_READ(regs
.pp_on
);
4926 pp_off
= I915_READ(regs
.pp_off
);
4927 if (!IS_BROXTON(dev_priv
)) {
4928 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4929 pp_div
= I915_READ(regs
.pp_div
);
4932 /* Pull timing values out of registers */
4933 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4934 PANEL_POWER_UP_DELAY_SHIFT
;
4936 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4937 PANEL_LIGHT_ON_DELAY_SHIFT
;
4939 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4940 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4942 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4943 PANEL_POWER_DOWN_DELAY_SHIFT
;
4945 if (IS_BROXTON(dev_priv
)) {
4946 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4947 BXT_POWER_CYCLE_DELAY_SHIFT
;
4949 seq
->t11_t12
= (tmp
- 1) * 1000;
4953 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4954 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4959 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
4961 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4963 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
4967 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
4968 struct intel_dp
*intel_dp
)
4970 struct edp_power_seq hw
;
4971 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
4973 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
4975 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
4976 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
4977 DRM_ERROR("PPS state mismatch\n");
4978 intel_pps_dump_state("sw", sw
);
4979 intel_pps_dump_state("hw", &hw
);
4984 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4985 struct intel_dp
*intel_dp
)
4987 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4988 struct edp_power_seq cur
, vbt
, spec
,
4989 *final
= &intel_dp
->pps_delays
;
4991 lockdep_assert_held(&dev_priv
->pps_mutex
);
4993 /* already initialized? */
4994 if (final
->t11_t12
!= 0)
4997 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
4999 intel_pps_dump_state("cur", &cur
);
5001 vbt
= dev_priv
->vbt
.edp
.pps
;
5003 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5004 * our hw here, which are all in 100usec. */
5005 spec
.t1_t3
= 210 * 10;
5006 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5007 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5008 spec
.t10
= 500 * 10;
5009 /* This one is special and actually in units of 100ms, but zero
5010 * based in the hw (so we need to add 100 ms). But the sw vbt
5011 * table multiplies it with 1000 to make it in units of 100usec,
5013 spec
.t11_t12
= (510 + 100) * 10;
5015 intel_pps_dump_state("vbt", &vbt
);
5017 /* Use the max of the register settings and vbt. If both are
5018 * unset, fall back to the spec limits. */
5019 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5021 max(cur.field, vbt.field))
5022 assign_final(t1_t3
);
5026 assign_final(t11_t12
);
5029 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5030 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5031 intel_dp
->backlight_on_delay
= get_delay(t8
);
5032 intel_dp
->backlight_off_delay
= get_delay(t9
);
5033 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5034 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5037 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5038 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5039 intel_dp
->panel_power_cycle_delay
);
5041 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5042 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5045 * We override the HW backlight delays to 1 because we do manual waits
5046 * on them. For T8, even BSpec recommends doing it. For T9, if we
5047 * don't do this, we'll end up waiting for the backlight off delay
5048 * twice: once when we do the manual sleep, and once when we disable
5049 * the panel and wait for the PP_STATUS bit to become zero.
5056 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5057 struct intel_dp
*intel_dp
)
5059 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5060 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5061 int div
= dev_priv
->rawclk_freq
/ 1000;
5062 struct pps_registers regs
;
5063 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5064 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5066 lockdep_assert_held(&dev_priv
->pps_mutex
);
5068 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5070 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5071 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5072 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5073 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5074 /* Compute the divisor for the pp clock, simply match the Bspec
5076 if (IS_BROXTON(dev
)) {
5077 pp_div
= I915_READ(regs
.pp_ctrl
);
5078 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5079 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5080 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5082 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5083 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5084 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5087 /* Haswell doesn't have any port selection bits for the panel
5088 * power sequencer any more. */
5089 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5090 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5091 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5093 port_sel
= PANEL_PORT_SELECT_DPA
;
5095 port_sel
= PANEL_PORT_SELECT_DPD
;
5100 I915_WRITE(regs
.pp_on
, pp_on
);
5101 I915_WRITE(regs
.pp_off
, pp_off
);
5102 if (IS_BROXTON(dev
))
5103 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5105 I915_WRITE(regs
.pp_div
, pp_div
);
5107 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5108 I915_READ(regs
.pp_on
),
5109 I915_READ(regs
.pp_off
),
5111 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5112 I915_READ(regs
.pp_div
));
5115 static void intel_dp_pps_init(struct drm_device
*dev
,
5116 struct intel_dp
*intel_dp
)
5118 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5119 vlv_initial_power_sequencer_setup(intel_dp
);
5121 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5122 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5127 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5128 * @dev_priv: i915 device
5129 * @crtc_state: a pointer to the active intel_crtc_state
5130 * @refresh_rate: RR to be programmed
5132 * This function gets called when refresh rate (RR) has to be changed from
5133 * one frequency to another. Switches can be between high and low RR
5134 * supported by the panel or to any other RR based on media playback (in
5135 * this case, RR value needs to be passed from user space).
5137 * The caller of this function needs to take a lock on dev_priv->drrs.
5139 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5140 struct intel_crtc_state
*crtc_state
,
5143 struct intel_encoder
*encoder
;
5144 struct intel_digital_port
*dig_port
= NULL
;
5145 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5147 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5149 if (refresh_rate
<= 0) {
5150 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5154 if (intel_dp
== NULL
) {
5155 DRM_DEBUG_KMS("DRRS not supported.\n");
5160 * FIXME: This needs proper synchronization with psr state for some
5161 * platforms that cannot have PSR and DRRS enabled at the same time.
5164 dig_port
= dp_to_dig_port(intel_dp
);
5165 encoder
= &dig_port
->base
;
5166 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5169 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5173 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5174 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5178 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5180 index
= DRRS_LOW_RR
;
5182 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5184 "DRRS requested for previously set RR...ignoring\n");
5188 if (!crtc_state
->base
.active
) {
5189 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5193 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5196 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5199 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5203 DRM_ERROR("Unsupported refreshrate type\n");
5205 } else if (INTEL_GEN(dev_priv
) > 6) {
5206 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5209 val
= I915_READ(reg
);
5210 if (index
> DRRS_HIGH_RR
) {
5211 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5212 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5214 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5216 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5217 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5219 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5221 I915_WRITE(reg
, val
);
5224 dev_priv
->drrs
.refresh_rate_type
= index
;
5226 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5230 * intel_edp_drrs_enable - init drrs struct if supported
5231 * @intel_dp: DP struct
5232 * @crtc_state: A pointer to the active crtc state.
5234 * Initializes frontbuffer_bits and drrs.dp
5236 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5237 struct intel_crtc_state
*crtc_state
)
5239 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5240 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5242 if (!crtc_state
->has_drrs
) {
5243 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5247 mutex_lock(&dev_priv
->drrs
.mutex
);
5248 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5249 DRM_ERROR("DRRS already enabled\n");
5253 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5255 dev_priv
->drrs
.dp
= intel_dp
;
5258 mutex_unlock(&dev_priv
->drrs
.mutex
);
5262 * intel_edp_drrs_disable - Disable DRRS
5263 * @intel_dp: DP struct
5264 * @old_crtc_state: Pointer to old crtc_state.
5267 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5268 struct intel_crtc_state
*old_crtc_state
)
5270 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5271 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5273 if (!old_crtc_state
->has_drrs
)
5276 mutex_lock(&dev_priv
->drrs
.mutex
);
5277 if (!dev_priv
->drrs
.dp
) {
5278 mutex_unlock(&dev_priv
->drrs
.mutex
);
5282 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5283 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5284 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5286 dev_priv
->drrs
.dp
= NULL
;
5287 mutex_unlock(&dev_priv
->drrs
.mutex
);
5289 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5292 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5294 struct drm_i915_private
*dev_priv
=
5295 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5296 struct intel_dp
*intel_dp
;
5298 mutex_lock(&dev_priv
->drrs
.mutex
);
5300 intel_dp
= dev_priv
->drrs
.dp
;
5306 * The delayed work can race with an invalidate hence we need to
5310 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5313 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5314 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5316 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5317 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5321 mutex_unlock(&dev_priv
->drrs
.mutex
);
5325 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5326 * @dev_priv: i915 device
5327 * @frontbuffer_bits: frontbuffer plane tracking bits
5329 * This function gets called everytime rendering on the given planes start.
5330 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5332 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5334 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5335 unsigned int frontbuffer_bits
)
5337 struct drm_crtc
*crtc
;
5340 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5343 cancel_delayed_work(&dev_priv
->drrs
.work
);
5345 mutex_lock(&dev_priv
->drrs
.mutex
);
5346 if (!dev_priv
->drrs
.dp
) {
5347 mutex_unlock(&dev_priv
->drrs
.mutex
);
5351 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5352 pipe
= to_intel_crtc(crtc
)->pipe
;
5354 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5355 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5357 /* invalidate means busy screen hence upclock */
5358 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5359 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5360 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5362 mutex_unlock(&dev_priv
->drrs
.mutex
);
5366 * intel_edp_drrs_flush - Restart Idleness DRRS
5367 * @dev_priv: i915 device
5368 * @frontbuffer_bits: frontbuffer plane tracking bits
5370 * This function gets called every time rendering on the given planes has
5371 * completed or flip on a crtc is completed. So DRRS should be upclocked
5372 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5373 * if no other planes are dirty.
5375 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5377 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5378 unsigned int frontbuffer_bits
)
5380 struct drm_crtc
*crtc
;
5383 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5386 cancel_delayed_work(&dev_priv
->drrs
.work
);
5388 mutex_lock(&dev_priv
->drrs
.mutex
);
5389 if (!dev_priv
->drrs
.dp
) {
5390 mutex_unlock(&dev_priv
->drrs
.mutex
);
5394 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5395 pipe
= to_intel_crtc(crtc
)->pipe
;
5397 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5398 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5400 /* flush means busy screen hence upclock */
5401 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5402 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5403 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5406 * flush also means no more activity hence schedule downclock, if all
5407 * other fbs are quiescent too
5409 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5410 schedule_delayed_work(&dev_priv
->drrs
.work
,
5411 msecs_to_jiffies(1000));
5412 mutex_unlock(&dev_priv
->drrs
.mutex
);
5416 * DOC: Display Refresh Rate Switching (DRRS)
5418 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5419 * which enables swtching between low and high refresh rates,
5420 * dynamically, based on the usage scenario. This feature is applicable
5421 * for internal panels.
5423 * Indication that the panel supports DRRS is given by the panel EDID, which
5424 * would list multiple refresh rates for one resolution.
5426 * DRRS is of 2 types - static and seamless.
5427 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5428 * (may appear as a blink on screen) and is used in dock-undock scenario.
5429 * Seamless DRRS involves changing RR without any visual effect to the user
5430 * and can be used during normal system usage. This is done by programming
5431 * certain registers.
5433 * Support for static/seamless DRRS may be indicated in the VBT based on
5434 * inputs from the panel spec.
5436 * DRRS saves power by switching to low RR based on usage scenarios.
5438 * The implementation is based on frontbuffer tracking implementation. When
5439 * there is a disturbance on the screen triggered by user activity or a periodic
5440 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5441 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5444 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5445 * and intel_edp_drrs_flush() are called.
5447 * DRRS can be further extended to support other internal panels and also
5448 * the scenario of video playback wherein RR is set based on the rate
5449 * requested by userspace.
5453 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5454 * @intel_connector: eDP connector
5455 * @fixed_mode: preferred mode of panel
5457 * This function is called only once at driver load to initialize basic
5461 * Downclock mode if panel supports it, else return NULL.
5462 * DRRS support is determined by the presence of downclock mode (apart
5463 * from VBT setting).
5465 static struct drm_display_mode
*
5466 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5467 struct drm_display_mode
*fixed_mode
)
5469 struct drm_connector
*connector
= &intel_connector
->base
;
5470 struct drm_device
*dev
= connector
->dev
;
5471 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5472 struct drm_display_mode
*downclock_mode
= NULL
;
5474 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5475 mutex_init(&dev_priv
->drrs
.mutex
);
5477 if (INTEL_INFO(dev
)->gen
<= 6) {
5478 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5482 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5483 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5487 downclock_mode
= intel_find_panel_downclock
5488 (dev
, fixed_mode
, connector
);
5490 if (!downclock_mode
) {
5491 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5495 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5497 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5498 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5499 return downclock_mode
;
5502 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5503 struct intel_connector
*intel_connector
)
5505 struct drm_connector
*connector
= &intel_connector
->base
;
5506 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5507 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5508 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5509 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5510 struct drm_display_mode
*fixed_mode
= NULL
;
5511 struct drm_display_mode
*downclock_mode
= NULL
;
5513 struct drm_display_mode
*scan
;
5515 enum pipe pipe
= INVALID_PIPE
;
5517 if (!is_edp(intel_dp
))
5521 * On IBX/CPT we may get here with LVDS already registered. Since the
5522 * driver uses the only internal power sequencer available for both
5523 * eDP and LVDS bail out early in this case to prevent interfering
5524 * with an already powered-on LVDS power sequencer.
5526 if (intel_get_lvds_encoder(dev
)) {
5527 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5528 DRM_INFO("LVDS was detected, not registering eDP\n");
5535 intel_dp_init_panel_power_timestamps(intel_dp
);
5536 intel_dp_pps_init(dev
, intel_dp
);
5537 intel_edp_panel_vdd_sanitize(intel_dp
);
5539 pps_unlock(intel_dp
);
5541 /* Cache DPCD and EDID for edp. */
5542 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5545 /* if this fails, presume the device is a ghost */
5546 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5550 mutex_lock(&dev
->mode_config
.mutex
);
5551 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5553 if (drm_add_edid_modes(connector
, edid
)) {
5554 drm_mode_connector_update_edid_property(connector
,
5556 drm_edid_to_eld(connector
, edid
);
5559 edid
= ERR_PTR(-EINVAL
);
5562 edid
= ERR_PTR(-ENOENT
);
5564 intel_connector
->edid
= edid
;
5566 /* prefer fixed mode from EDID if available */
5567 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5568 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5569 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5570 downclock_mode
= intel_dp_drrs_init(
5571 intel_connector
, fixed_mode
);
5576 /* fallback to VBT if available for eDP */
5577 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5578 fixed_mode
= drm_mode_duplicate(dev
,
5579 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5581 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5582 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5583 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5586 mutex_unlock(&dev
->mode_config
.mutex
);
5588 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5589 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5590 register_reboot_notifier(&intel_dp
->edp_notifier
);
5593 * Figure out the current pipe for the initial backlight setup.
5594 * If the current pipe isn't valid, try the PPS pipe, and if that
5595 * fails just assume pipe A.
5597 if (IS_CHERRYVIEW(dev
))
5598 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5600 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5602 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5603 pipe
= intel_dp
->pps_pipe
;
5605 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5608 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5612 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5613 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5614 intel_panel_setup_backlight(connector
, pipe
);
5619 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5621 * vdd might still be enabled do to the delayed vdd off.
5622 * Make sure vdd is actually turned off here.
5625 edp_panel_vdd_off_sync(intel_dp
);
5626 pps_unlock(intel_dp
);
5632 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5633 struct intel_connector
*intel_connector
)
5635 struct drm_connector
*connector
= &intel_connector
->base
;
5636 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5637 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5638 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5639 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5640 enum port port
= intel_dig_port
->port
;
5643 if (WARN(intel_dig_port
->max_lanes
< 1,
5644 "Not enough lanes (%d) for DP on port %c\n",
5645 intel_dig_port
->max_lanes
, port_name(port
)))
5648 intel_dp
->pps_pipe
= INVALID_PIPE
;
5650 /* intel_dp vfuncs */
5651 if (INTEL_INFO(dev
)->gen
>= 9)
5652 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5653 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5654 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5655 else if (HAS_PCH_SPLIT(dev
))
5656 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5658 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5660 if (INTEL_INFO(dev
)->gen
>= 9)
5661 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5663 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5666 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5668 /* Preserve the current hw state. */
5669 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5670 intel_dp
->attached_connector
= intel_connector
;
5672 if (intel_dp_is_edp(dev
, port
))
5673 type
= DRM_MODE_CONNECTOR_eDP
;
5675 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5678 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5679 * for DP the encoder type can be set by the caller to
5680 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5682 if (type
== DRM_MODE_CONNECTOR_eDP
)
5683 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5685 /* eDP only on port B and/or C on vlv/chv */
5686 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5687 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5690 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5691 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5694 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5695 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5697 connector
->interlace_allowed
= true;
5698 connector
->doublescan_allowed
= 0;
5700 intel_dp_aux_init(intel_dp
);
5702 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5703 edp_panel_vdd_work
);
5705 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5708 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5710 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5712 /* Set up the hotplug pin. */
5715 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5718 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5719 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5720 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5723 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5726 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5729 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5735 /* init MST on ports that can support it */
5736 if (HAS_DP_MST(dev
) && !is_edp(intel_dp
) &&
5737 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5738 intel_dp_mst_encoder_init(intel_dig_port
,
5739 intel_connector
->base
.base
.id
);
5741 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5742 intel_dp_aux_fini(intel_dp
);
5743 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5747 intel_dp_add_properties(intel_dp
, connector
);
5749 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5750 * 0xd. Failure to do so will result in spurious interrupts being
5751 * generated on the port when a cable is not attached.
5753 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5754 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5755 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5761 drm_connector_cleanup(connector
);
5766 bool intel_dp_init(struct drm_device
*dev
,
5767 i915_reg_t output_reg
,
5770 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5771 struct intel_digital_port
*intel_dig_port
;
5772 struct intel_encoder
*intel_encoder
;
5773 struct drm_encoder
*encoder
;
5774 struct intel_connector
*intel_connector
;
5776 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5777 if (!intel_dig_port
)
5780 intel_connector
= intel_connector_alloc();
5781 if (!intel_connector
)
5782 goto err_connector_alloc
;
5784 intel_encoder
= &intel_dig_port
->base
;
5785 encoder
= &intel_encoder
->base
;
5787 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5788 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5789 goto err_encoder_init
;
5791 intel_encoder
->compute_config
= intel_dp_compute_config
;
5792 intel_encoder
->disable
= intel_disable_dp
;
5793 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5794 intel_encoder
->get_config
= intel_dp_get_config
;
5795 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5796 if (IS_CHERRYVIEW(dev
)) {
5797 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5798 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5799 intel_encoder
->enable
= vlv_enable_dp
;
5800 intel_encoder
->post_disable
= chv_post_disable_dp
;
5801 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5802 } else if (IS_VALLEYVIEW(dev
)) {
5803 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5804 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5805 intel_encoder
->enable
= vlv_enable_dp
;
5806 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5808 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5809 intel_encoder
->enable
= g4x_enable_dp
;
5810 if (INTEL_INFO(dev
)->gen
>= 5)
5811 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5814 intel_dig_port
->port
= port
;
5815 intel_dig_port
->dp
.output_reg
= output_reg
;
5816 intel_dig_port
->max_lanes
= 4;
5818 intel_encoder
->type
= INTEL_OUTPUT_DP
;
5819 if (IS_CHERRYVIEW(dev
)) {
5821 intel_encoder
->crtc_mask
= 1 << 2;
5823 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5825 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5827 intel_encoder
->cloneable
= 0;
5829 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5830 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5832 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5833 goto err_init_connector
;
5838 drm_encoder_cleanup(encoder
);
5840 kfree(intel_connector
);
5841 err_connector_alloc
:
5842 kfree(intel_dig_port
);
5846 void intel_dp_mst_suspend(struct drm_device
*dev
)
5848 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5852 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5853 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5855 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5858 if (intel_dig_port
->dp
.is_mst
)
5859 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5863 void intel_dp_mst_resume(struct drm_device
*dev
)
5865 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5868 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5869 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5872 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5875 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5877 intel_dp_check_mst_status(&intel_dig_port
->dp
);