2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp
*intel_dp
)
50 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
52 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
55 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
57 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
59 return intel_dig_port
->base
.base
.dev
;
62 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
64 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
67 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
70 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
72 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
74 switch (max_link_bw
) {
78 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw
= DP_LINK_BW_2_7
;
82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
84 max_link_bw
= DP_LINK_BW_1_62
;
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
96 * 270000 * 1 * 8 / 10 == 216000
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
108 intel_dp_link_required(int pixel_clock
, int bpp
)
110 return (pixel_clock
* bpp
+ 9) / 10;
114 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
116 return (max_link_clock
* max_lanes
* 8) / 10;
120 intel_dp_mode_valid(struct drm_connector
*connector
,
121 struct drm_display_mode
*mode
)
123 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
124 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
125 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
126 int target_clock
= mode
->clock
;
127 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
129 if (is_edp(intel_dp
) && fixed_mode
) {
130 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
133 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
136 target_clock
= fixed_mode
->clock
;
139 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
140 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
142 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
143 mode_rate
= intel_dp_link_required(target_clock
, 18);
145 if (mode_rate
> max_rate
)
146 return MODE_CLOCK_HIGH
;
148 if (mode
->clock
< 10000)
149 return MODE_CLOCK_LOW
;
151 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
152 return MODE_H_ILLEGAL
;
158 pack_aux(uint8_t *src
, int src_bytes
)
165 for (i
= 0; i
< src_bytes
; i
++)
166 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
171 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
176 for (i
= 0; i
< dst_bytes
; i
++)
177 dst
[i
] = src
>> ((3-i
) * 8);
180 /* hrawclock is 1/4 the FSB frequency */
182 intel_hrawclk(struct drm_device
*dev
)
184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev
))
191 clkcfg
= I915_READ(CLKCFG
);
192 switch (clkcfg
& CLKCFG_FSB_MASK
) {
201 case CLKCFG_FSB_1067
:
203 case CLKCFG_FSB_1333
:
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600
:
207 case CLKCFG_FSB_1600_ALT
:
214 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
216 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
221 return (I915_READ(pp_stat_reg
) & PP_ON
) != 0;
224 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
226 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
230 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
231 return (I915_READ(pp_ctrl_reg
) & EDP_FORCE_VDD
) != 0;
235 intel_dp_check_edp(struct intel_dp
*intel_dp
)
237 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 u32 pp_stat_reg
, pp_ctrl_reg
;
241 if (!is_edp(intel_dp
))
244 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
245 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
247 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
250 I915_READ(pp_stat_reg
),
251 I915_READ(pp_ctrl_reg
));
256 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
258 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
259 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
261 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
265 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
267 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
268 msecs_to_jiffies_timeout(10));
270 done
= wait_for_atomic(C
, 10) == 0;
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
280 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
281 uint8_t *send
, int send_bytes
,
282 uint8_t *recv
, int recv_size
)
284 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
285 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
287 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
288 uint32_t ch_data
= ch_ctl
+ 4;
289 int i
, ret
, recv_bytes
;
291 uint32_t aux_clock_divider
;
293 bool has_aux_irq
= INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
);
295 /* dp aux is extremely sensitive to irq latency, hence request the
296 * lowest possible wakeup latency and so prevent the cpu from going into
299 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
301 intel_dp_check_edp(intel_dp
);
302 /* The clock divider is based off the hrawclk,
303 * and would like to run at 2MHz. So, take the
304 * hrawclk value and divide by 2 and use that
306 * Note that PCH attached eDP panels should use a 125MHz input
309 if (IS_VALLEYVIEW(dev
)) {
310 aux_clock_divider
= 100;
311 } else if (intel_dig_port
->port
== PORT_A
) {
313 aux_clock_divider
= DIV_ROUND_CLOSEST(
314 intel_ddi_get_cdclk_freq(dev_priv
), 2000);
315 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
316 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
318 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
319 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
320 /* Workaround for non-ULT HSW */
321 aux_clock_divider
= 74;
322 } else if (HAS_PCH_SPLIT(dev
)) {
323 aux_clock_divider
= DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
325 aux_clock_divider
= intel_hrawclk(dev
) / 2;
333 /* Try to wait for any previous AUX channel activity */
334 for (try = 0; try < 3; try++) {
335 status
= I915_READ_NOTRACE(ch_ctl
);
336 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
342 WARN(1, "dp_aux_ch not started status 0x%08x\n",
348 /* Must try at least 3 times according to DP spec */
349 for (try = 0; try < 5; try++) {
350 /* Load the send data into the aux channel data registers */
351 for (i
= 0; i
< send_bytes
; i
+= 4)
352 I915_WRITE(ch_data
+ i
,
353 pack_aux(send
+ i
, send_bytes
- i
));
355 /* Send the command and wait for it to complete */
357 DP_AUX_CH_CTL_SEND_BUSY
|
358 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
359 DP_AUX_CH_CTL_TIME_OUT_400us
|
360 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
361 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
362 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
364 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
365 DP_AUX_CH_CTL_RECEIVE_ERROR
);
367 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
369 /* Clear done status and any errors */
373 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
374 DP_AUX_CH_CTL_RECEIVE_ERROR
);
376 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
377 DP_AUX_CH_CTL_RECEIVE_ERROR
))
379 if (status
& DP_AUX_CH_CTL_DONE
)
383 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
384 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
389 /* Check for timeout or receive error.
390 * Timeouts occur when the sink is not connected
392 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
393 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
398 /* Timeouts occur when the device isn't connected, so they're
399 * "normal" -- don't fill the kernel log with these */
400 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
401 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
406 /* Unload any bytes sent back from the other side */
407 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
408 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
409 if (recv_bytes
> recv_size
)
410 recv_bytes
= recv_size
;
412 for (i
= 0; i
< recv_bytes
; i
+= 4)
413 unpack_aux(I915_READ(ch_data
+ i
),
414 recv
+ i
, recv_bytes
- i
);
418 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
423 /* Write data to the aux channel in native mode */
425 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
426 uint16_t address
, uint8_t *send
, int send_bytes
)
433 intel_dp_check_edp(intel_dp
);
436 msg
[0] = AUX_NATIVE_WRITE
<< 4;
437 msg
[1] = address
>> 8;
438 msg
[2] = address
& 0xff;
439 msg
[3] = send_bytes
- 1;
440 memcpy(&msg
[4], send
, send_bytes
);
441 msg_bytes
= send_bytes
+ 4;
443 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
446 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
448 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
456 /* Write a single byte to the aux channel in native mode */
458 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
459 uint16_t address
, uint8_t byte
)
461 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
464 /* read bytes from a native aux channel */
466 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
467 uint16_t address
, uint8_t *recv
, int recv_bytes
)
476 intel_dp_check_edp(intel_dp
);
477 msg
[0] = AUX_NATIVE_READ
<< 4;
478 msg
[1] = address
>> 8;
479 msg
[2] = address
& 0xff;
480 msg
[3] = recv_bytes
- 1;
483 reply_bytes
= recv_bytes
+ 1;
486 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
493 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
494 memcpy(recv
, reply
+ 1, ret
- 1);
497 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
505 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
506 uint8_t write_byte
, uint8_t *read_byte
)
508 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
509 struct intel_dp
*intel_dp
= container_of(adapter
,
512 uint16_t address
= algo_data
->address
;
520 intel_dp_check_edp(intel_dp
);
521 /* Set up the command byte */
522 if (mode
& MODE_I2C_READ
)
523 msg
[0] = AUX_I2C_READ
<< 4;
525 msg
[0] = AUX_I2C_WRITE
<< 4;
527 if (!(mode
& MODE_I2C_STOP
))
528 msg
[0] |= AUX_I2C_MOT
<< 4;
530 msg
[1] = address
>> 8;
551 for (retry
= 0; retry
< 5; retry
++) {
552 ret
= intel_dp_aux_ch(intel_dp
,
556 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
560 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
561 case AUX_NATIVE_REPLY_ACK
:
562 /* I2C-over-AUX Reply field is only valid
563 * when paired with AUX ACK.
566 case AUX_NATIVE_REPLY_NACK
:
567 DRM_DEBUG_KMS("aux_ch native nack\n");
569 case AUX_NATIVE_REPLY_DEFER
:
573 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
578 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
579 case AUX_I2C_REPLY_ACK
:
580 if (mode
== MODE_I2C_READ
) {
581 *read_byte
= reply
[1];
583 return reply_bytes
- 1;
584 case AUX_I2C_REPLY_NACK
:
585 DRM_DEBUG_KMS("aux_i2c nack\n");
587 case AUX_I2C_REPLY_DEFER
:
588 DRM_DEBUG_KMS("aux_i2c defer\n");
592 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
597 DRM_ERROR("too many retries, giving up\n");
602 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
603 struct intel_connector
*intel_connector
, const char *name
)
607 DRM_DEBUG_KMS("i2c_init %s\n", name
);
608 intel_dp
->algo
.running
= false;
609 intel_dp
->algo
.address
= 0;
610 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
612 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
613 intel_dp
->adapter
.owner
= THIS_MODULE
;
614 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
615 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
616 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
617 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
618 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
620 ironlake_edp_panel_vdd_on(intel_dp
);
621 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
622 ironlake_edp_panel_vdd_off(intel_dp
, false);
627 intel_dp_set_clock(struct intel_encoder
*encoder
,
628 struct intel_crtc_config
*pipe_config
, int link_bw
)
630 struct drm_device
*dev
= encoder
->base
.dev
;
633 if (link_bw
== DP_LINK_BW_1_62
) {
634 pipe_config
->dpll
.p1
= 2;
635 pipe_config
->dpll
.p2
= 10;
636 pipe_config
->dpll
.n
= 2;
637 pipe_config
->dpll
.m1
= 23;
638 pipe_config
->dpll
.m2
= 8;
640 pipe_config
->dpll
.p1
= 1;
641 pipe_config
->dpll
.p2
= 10;
642 pipe_config
->dpll
.n
= 1;
643 pipe_config
->dpll
.m1
= 14;
644 pipe_config
->dpll
.m2
= 2;
646 pipe_config
->clock_set
= true;
647 } else if (IS_HASWELL(dev
)) {
648 /* Haswell has special-purpose DP DDI clocks. */
649 } else if (HAS_PCH_SPLIT(dev
)) {
650 if (link_bw
== DP_LINK_BW_1_62
) {
651 pipe_config
->dpll
.n
= 1;
652 pipe_config
->dpll
.p1
= 2;
653 pipe_config
->dpll
.p2
= 10;
654 pipe_config
->dpll
.m1
= 12;
655 pipe_config
->dpll
.m2
= 9;
657 pipe_config
->dpll
.n
= 2;
658 pipe_config
->dpll
.p1
= 1;
659 pipe_config
->dpll
.p2
= 10;
660 pipe_config
->dpll
.m1
= 14;
661 pipe_config
->dpll
.m2
= 8;
663 pipe_config
->clock_set
= true;
664 } else if (IS_VALLEYVIEW(dev
)) {
665 /* FIXME: Need to figure out optimized DP clocks for vlv. */
670 intel_dp_compute_config(struct intel_encoder
*encoder
,
671 struct intel_crtc_config
*pipe_config
)
673 struct drm_device
*dev
= encoder
->base
.dev
;
674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
675 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
676 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
677 enum port port
= dp_to_dig_port(intel_dp
)->port
;
678 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
679 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
680 int lane_count
, clock
;
681 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
682 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
684 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
685 int link_avail
, link_clock
;
687 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
688 pipe_config
->has_pch_encoder
= true;
690 pipe_config
->has_dp_encoder
= true;
692 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
693 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
695 if (!HAS_PCH_SPLIT(dev
))
696 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
697 intel_connector
->panel
.fitting_mode
);
699 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
700 intel_connector
->panel
.fitting_mode
);
703 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
706 DRM_DEBUG_KMS("DP link computation with max lane count %i "
707 "max bw %02x pixel clock %iKHz\n",
708 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
710 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
712 bpp
= pipe_config
->pipe_bpp
;
713 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
)
714 bpp
= min_t(int, bpp
, dev_priv
->vbt
.edp_bpp
);
716 for (; bpp
>= 6*3; bpp
-= 2*3) {
717 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
719 for (clock
= 0; clock
<= max_clock
; clock
++) {
720 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
721 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
722 link_avail
= intel_dp_max_data_rate(link_clock
,
725 if (mode_rate
<= link_avail
) {
735 if (intel_dp
->color_range_auto
) {
738 * CEA-861-E - 5.1 Default Encoding Parameters
739 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
741 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
742 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
744 intel_dp
->color_range
= 0;
747 if (intel_dp
->color_range
)
748 pipe_config
->limited_color_range
= true;
750 intel_dp
->link_bw
= bws
[clock
];
751 intel_dp
->lane_count
= lane_count
;
752 pipe_config
->pipe_bpp
= bpp
;
753 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
755 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
756 intel_dp
->link_bw
, intel_dp
->lane_count
,
757 pipe_config
->port_clock
, bpp
);
758 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
759 mode_rate
, link_avail
);
761 intel_link_compute_m_n(bpp
, lane_count
,
762 adjusted_mode
->clock
, pipe_config
->port_clock
,
763 &pipe_config
->dp_m_n
);
765 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
770 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
772 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
773 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
774 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
775 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
777 * Check for DPCD version > 1.1 and enhanced framing support
779 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
780 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
781 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
785 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
787 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
788 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
789 struct drm_device
*dev
= crtc
->base
.dev
;
790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
793 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
794 dpa_ctl
= I915_READ(DP_A
);
795 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
797 if (crtc
->config
.port_clock
== 162000) {
798 /* For a long time we've carried around a ILK-DevA w/a for the
799 * 160MHz clock. If we're really unlucky, it's still required.
801 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
802 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
803 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
805 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
806 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
809 I915_WRITE(DP_A
, dpa_ctl
);
816 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
817 struct drm_display_mode
*adjusted_mode
)
819 struct drm_device
*dev
= encoder
->dev
;
820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
821 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
822 enum port port
= dp_to_dig_port(intel_dp
)->port
;
823 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
826 * There are four kinds of DP registers:
833 * IBX PCH and CPU are the same for almost everything,
834 * except that the CPU DP PLL is configured in this
837 * CPT PCH is quite different, having many bits moved
838 * to the TRANS_DP_CTL register instead. That
839 * configuration happens (oddly) in ironlake_pch_enable
842 /* Preserve the BIOS-computed detected bit. This is
843 * supposed to be read-only.
845 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
847 /* Handle DP bits in common between all three register formats */
848 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
849 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
851 if (intel_dp
->has_audio
) {
852 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
853 pipe_name(crtc
->pipe
));
854 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
855 intel_write_eld(encoder
, adjusted_mode
);
858 intel_dp_init_link_config(intel_dp
);
860 /* Split out the IBX/CPU vs CPT settings */
862 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
863 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
864 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
865 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
866 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
867 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
869 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
870 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
872 intel_dp
->DP
|= crtc
->pipe
<< 29;
873 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
874 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
875 intel_dp
->DP
|= intel_dp
->color_range
;
877 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
878 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
879 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
880 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
881 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
883 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
884 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
887 intel_dp
->DP
|= DP_PIPEB_SELECT
;
889 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
892 if (port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
893 ironlake_set_pll_cpu_edp(intel_dp
);
896 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
897 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
899 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
900 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
902 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
903 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
905 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
909 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
911 u32 pp_stat_reg
, pp_ctrl_reg
;
913 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
914 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
916 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
918 I915_READ(pp_stat_reg
),
919 I915_READ(pp_ctrl_reg
));
921 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
922 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
923 I915_READ(pp_stat_reg
),
924 I915_READ(pp_ctrl_reg
));
928 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
930 DRM_DEBUG_KMS("Wait for panel power on\n");
931 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
934 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
936 DRM_DEBUG_KMS("Wait for panel power off time\n");
937 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
940 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
942 DRM_DEBUG_KMS("Wait for panel power cycle\n");
943 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
947 /* Read the current pp_control value, unlocking the register if it
951 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
953 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
958 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
959 control
= I915_READ(pp_ctrl_reg
);
961 control
&= ~PANEL_UNLOCK_MASK
;
962 control
|= PANEL_UNLOCK_REGS
;
966 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
968 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
971 u32 pp_stat_reg
, pp_ctrl_reg
;
973 if (!is_edp(intel_dp
))
975 DRM_DEBUG_KMS("Turn eDP VDD on\n");
977 WARN(intel_dp
->want_panel_vdd
,
978 "eDP VDD already requested on\n");
980 intel_dp
->want_panel_vdd
= true;
982 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
983 DRM_DEBUG_KMS("eDP VDD already on\n");
987 if (!ironlake_edp_have_panel_power(intel_dp
))
988 ironlake_wait_panel_power_cycle(intel_dp
);
990 pp
= ironlake_get_pp_control(intel_dp
);
993 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
994 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
996 I915_WRITE(pp_ctrl_reg
, pp
);
997 POSTING_READ(pp_ctrl_reg
);
998 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
999 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1001 * If the panel wasn't on, delay before accessing aux channel
1003 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1004 DRM_DEBUG_KMS("eDP was not running\n");
1005 msleep(intel_dp
->panel_power_up_delay
);
1009 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1011 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1014 u32 pp_stat_reg
, pp_ctrl_reg
;
1016 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1018 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1019 pp
= ironlake_get_pp_control(intel_dp
);
1020 pp
&= ~EDP_FORCE_VDD
;
1022 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
1023 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1025 I915_WRITE(pp_ctrl_reg
, pp
);
1026 POSTING_READ(pp_ctrl_reg
);
1028 /* Make sure sequencer is idle before allowing subsequent activity */
1029 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1030 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1031 msleep(intel_dp
->panel_power_down_delay
);
1035 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1037 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1038 struct intel_dp
, panel_vdd_work
);
1039 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1041 mutex_lock(&dev
->mode_config
.mutex
);
1042 ironlake_panel_vdd_off_sync(intel_dp
);
1043 mutex_unlock(&dev
->mode_config
.mutex
);
1046 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1048 if (!is_edp(intel_dp
))
1051 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1052 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1054 intel_dp
->want_panel_vdd
= false;
1057 ironlake_panel_vdd_off_sync(intel_dp
);
1060 * Queue the timer to fire a long
1061 * time from now (relative to the power down delay)
1062 * to keep the panel power up across a sequence of operations
1064 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1065 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1069 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1071 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1076 if (!is_edp(intel_dp
))
1079 DRM_DEBUG_KMS("Turn eDP power on\n");
1081 if (ironlake_edp_have_panel_power(intel_dp
)) {
1082 DRM_DEBUG_KMS("eDP power already on\n");
1086 ironlake_wait_panel_power_cycle(intel_dp
);
1088 pp
= ironlake_get_pp_control(intel_dp
);
1090 /* ILK workaround: disable reset around power sequence */
1091 pp
&= ~PANEL_POWER_RESET
;
1092 I915_WRITE(PCH_PP_CONTROL
, pp
);
1093 POSTING_READ(PCH_PP_CONTROL
);
1096 pp
|= POWER_TARGET_ON
;
1098 pp
|= PANEL_POWER_RESET
;
1100 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1102 I915_WRITE(pp_ctrl_reg
, pp
);
1103 POSTING_READ(pp_ctrl_reg
);
1105 ironlake_wait_panel_on(intel_dp
);
1108 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1109 I915_WRITE(PCH_PP_CONTROL
, pp
);
1110 POSTING_READ(PCH_PP_CONTROL
);
1114 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1116 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1121 if (!is_edp(intel_dp
))
1124 DRM_DEBUG_KMS("Turn eDP power off\n");
1126 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1128 pp
= ironlake_get_pp_control(intel_dp
);
1129 /* We need to switch off panel power _and_ force vdd, for otherwise some
1130 * panels get very unhappy and cease to work. */
1131 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1133 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1135 I915_WRITE(pp_ctrl_reg
, pp
);
1136 POSTING_READ(pp_ctrl_reg
);
1138 intel_dp
->want_panel_vdd
= false;
1140 ironlake_wait_panel_off(intel_dp
);
1143 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1145 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1146 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1148 int pipe
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
)->pipe
;
1152 if (!is_edp(intel_dp
))
1155 DRM_DEBUG_KMS("\n");
1157 * If we enable the backlight right away following a panel power
1158 * on, we may see slight flicker as the panel syncs with the eDP
1159 * link. So delay a bit to make sure the image is solid before
1160 * allowing it to appear.
1162 msleep(intel_dp
->backlight_on_delay
);
1163 pp
= ironlake_get_pp_control(intel_dp
);
1164 pp
|= EDP_BLC_ENABLE
;
1166 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1168 I915_WRITE(pp_ctrl_reg
, pp
);
1169 POSTING_READ(pp_ctrl_reg
);
1171 intel_panel_enable_backlight(dev
, pipe
);
1174 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1176 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1181 if (!is_edp(intel_dp
))
1184 intel_panel_disable_backlight(dev
);
1186 DRM_DEBUG_KMS("\n");
1187 pp
= ironlake_get_pp_control(intel_dp
);
1188 pp
&= ~EDP_BLC_ENABLE
;
1190 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1192 I915_WRITE(pp_ctrl_reg
, pp
);
1193 POSTING_READ(pp_ctrl_reg
);
1194 msleep(intel_dp
->backlight_off_delay
);
1197 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1199 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1200 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1201 struct drm_device
*dev
= crtc
->dev
;
1202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1205 assert_pipe_disabled(dev_priv
,
1206 to_intel_crtc(crtc
)->pipe
);
1208 DRM_DEBUG_KMS("\n");
1209 dpa_ctl
= I915_READ(DP_A
);
1210 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1211 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1213 /* We don't adjust intel_dp->DP while tearing down the link, to
1214 * facilitate link retraining (e.g. after hotplug). Hence clear all
1215 * enable bits here to ensure that we don't enable too much. */
1216 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1217 intel_dp
->DP
|= DP_PLL_ENABLE
;
1218 I915_WRITE(DP_A
, intel_dp
->DP
);
1223 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1225 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1226 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1227 struct drm_device
*dev
= crtc
->dev
;
1228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1231 assert_pipe_disabled(dev_priv
,
1232 to_intel_crtc(crtc
)->pipe
);
1234 dpa_ctl
= I915_READ(DP_A
);
1235 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1236 "dp pll off, should be on\n");
1237 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1239 /* We can't rely on the value tracked for the DP register in
1240 * intel_dp->DP because link_down must not change that (otherwise link
1241 * re-training will fail. */
1242 dpa_ctl
&= ~DP_PLL_ENABLE
;
1243 I915_WRITE(DP_A
, dpa_ctl
);
1248 /* If the sink supports it, try to set the power state appropriately */
1249 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1253 /* Should have a valid DPCD by this point */
1254 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1257 if (mode
!= DRM_MODE_DPMS_ON
) {
1258 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1261 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1264 * When turning on, we need to retry for 1ms to give the sink
1267 for (i
= 0; i
< 3; i
++) {
1268 ret
= intel_dp_aux_native_write_1(intel_dp
,
1278 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1281 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1282 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1283 struct drm_device
*dev
= encoder
->base
.dev
;
1284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1285 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1287 if (!(tmp
& DP_PORT_EN
))
1290 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1291 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1292 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1293 *pipe
= PORT_TO_PIPE(tmp
);
1299 switch (intel_dp
->output_reg
) {
1301 trans_sel
= TRANS_DP_PORT_SEL_B
;
1304 trans_sel
= TRANS_DP_PORT_SEL_C
;
1307 trans_sel
= TRANS_DP_PORT_SEL_D
;
1314 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1315 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1321 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1322 intel_dp
->output_reg
);
1328 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1329 struct intel_crtc_config
*pipe_config
)
1331 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1333 struct drm_device
*dev
= encoder
->base
.dev
;
1334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1335 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1336 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1338 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1339 tmp
= I915_READ(intel_dp
->output_reg
);
1340 if (tmp
& DP_SYNC_HS_HIGH
)
1341 flags
|= DRM_MODE_FLAG_PHSYNC
;
1343 flags
|= DRM_MODE_FLAG_NHSYNC
;
1345 if (tmp
& DP_SYNC_VS_HIGH
)
1346 flags
|= DRM_MODE_FLAG_PVSYNC
;
1348 flags
|= DRM_MODE_FLAG_NVSYNC
;
1350 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1351 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1352 flags
|= DRM_MODE_FLAG_PHSYNC
;
1354 flags
|= DRM_MODE_FLAG_NHSYNC
;
1356 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1357 flags
|= DRM_MODE_FLAG_PVSYNC
;
1359 flags
|= DRM_MODE_FLAG_NVSYNC
;
1362 pipe_config
->adjusted_mode
.flags
|= flags
;
1365 static void intel_disable_dp(struct intel_encoder
*encoder
)
1367 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1368 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1369 struct drm_device
*dev
= encoder
->base
.dev
;
1371 /* Make sure the panel is off before trying to change the mode. But also
1372 * ensure that we have vdd while we switch off the panel. */
1373 ironlake_edp_panel_vdd_on(intel_dp
);
1374 ironlake_edp_backlight_off(intel_dp
);
1375 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1376 ironlake_edp_panel_off(intel_dp
);
1378 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1379 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1380 intel_dp_link_down(intel_dp
);
1383 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1385 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1386 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1387 struct drm_device
*dev
= encoder
->base
.dev
;
1389 if (port
== PORT_A
|| IS_VALLEYVIEW(dev
)) {
1390 intel_dp_link_down(intel_dp
);
1391 if (!IS_VALLEYVIEW(dev
))
1392 ironlake_edp_pll_off(intel_dp
);
1396 static void intel_enable_dp(struct intel_encoder
*encoder
)
1398 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1399 struct drm_device
*dev
= encoder
->base
.dev
;
1400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1401 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1403 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1406 ironlake_edp_panel_vdd_on(intel_dp
);
1407 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1408 intel_dp_start_link_train(intel_dp
);
1409 ironlake_edp_panel_on(intel_dp
);
1410 ironlake_edp_panel_vdd_off(intel_dp
, true);
1411 intel_dp_complete_link_train(intel_dp
);
1412 intel_dp_stop_link_train(intel_dp
);
1413 ironlake_edp_backlight_on(intel_dp
);
1415 if (IS_VALLEYVIEW(dev
)) {
1416 struct intel_digital_port
*dport
=
1417 enc_to_dig_port(&encoder
->base
);
1418 int channel
= vlv_dport_to_channel(dport
);
1420 vlv_wait_port_ready(dev_priv
, channel
);
1424 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1426 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1427 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1428 struct drm_device
*dev
= encoder
->base
.dev
;
1429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1431 if (dport
->port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
1432 ironlake_edp_pll_on(intel_dp
);
1434 if (IS_VALLEYVIEW(dev
)) {
1435 struct intel_crtc
*intel_crtc
=
1436 to_intel_crtc(encoder
->base
.crtc
);
1437 int port
= vlv_dport_to_channel(dport
);
1438 int pipe
= intel_crtc
->pipe
;
1441 val
= vlv_dpio_read(dev_priv
, DPIO_DATA_LANE_A(port
));
1448 vlv_dpio_write(dev_priv
, DPIO_DATA_CHANNEL(port
), val
);
1450 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF0(port
),
1452 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF8(port
),
1457 static void intel_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1459 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1460 struct drm_device
*dev
= encoder
->base
.dev
;
1461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1462 int port
= vlv_dport_to_channel(dport
);
1464 if (!IS_VALLEYVIEW(dev
))
1467 /* Program Tx lane resets to default */
1468 vlv_dpio_write(dev_priv
, DPIO_PCS_TX(port
),
1469 DPIO_PCS_TX_LANE2_RESET
|
1470 DPIO_PCS_TX_LANE1_RESET
);
1471 vlv_dpio_write(dev_priv
, DPIO_PCS_CLK(port
),
1472 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1473 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1474 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1475 DPIO_PCS_CLK_SOFT_RESET
);
1477 /* Fix up inter-pair skew failure */
1478 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER1(port
), 0x00750f00);
1479 vlv_dpio_write(dev_priv
, DPIO_TX_CTL(port
), 0x00001500);
1480 vlv_dpio_write(dev_priv
, DPIO_TX_LANE(port
), 0x40400000);
1484 * Native read with retry for link status and receiver capability reads for
1485 * cases where the sink may still be asleep.
1488 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1489 uint8_t *recv
, int recv_bytes
)
1494 * Sinks are *supposed* to come up within 1ms from an off state,
1495 * but we're also supposed to retry 3 times per the spec.
1497 for (i
= 0; i
< 3; i
++) {
1498 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1500 if (ret
== recv_bytes
)
1509 * Fetch AUX CH registers 0x202 - 0x207 which contain
1510 * link status information
1513 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1515 return intel_dp_aux_native_read_retry(intel_dp
,
1518 DP_LINK_STATUS_SIZE
);
1522 static char *voltage_names
[] = {
1523 "0.4V", "0.6V", "0.8V", "1.2V"
1525 static char *pre_emph_names
[] = {
1526 "0dB", "3.5dB", "6dB", "9.5dB"
1528 static char *link_train_names
[] = {
1529 "pattern 1", "pattern 2", "idle", "off"
1534 * These are source-specific values; current Intel hardware supports
1535 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1539 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1541 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1542 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1544 if (IS_VALLEYVIEW(dev
))
1545 return DP_TRAIN_VOLTAGE_SWING_1200
;
1546 else if (IS_GEN7(dev
) && port
== PORT_A
)
1547 return DP_TRAIN_VOLTAGE_SWING_800
;
1548 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
1549 return DP_TRAIN_VOLTAGE_SWING_1200
;
1551 return DP_TRAIN_VOLTAGE_SWING_800
;
1555 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1557 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1558 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1561 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1562 case DP_TRAIN_VOLTAGE_SWING_400
:
1563 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1564 case DP_TRAIN_VOLTAGE_SWING_600
:
1565 return DP_TRAIN_PRE_EMPHASIS_6
;
1566 case DP_TRAIN_VOLTAGE_SWING_800
:
1567 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1568 case DP_TRAIN_VOLTAGE_SWING_1200
:
1570 return DP_TRAIN_PRE_EMPHASIS_0
;
1572 } else if (IS_VALLEYVIEW(dev
)) {
1573 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1574 case DP_TRAIN_VOLTAGE_SWING_400
:
1575 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1576 case DP_TRAIN_VOLTAGE_SWING_600
:
1577 return DP_TRAIN_PRE_EMPHASIS_6
;
1578 case DP_TRAIN_VOLTAGE_SWING_800
:
1579 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1580 case DP_TRAIN_VOLTAGE_SWING_1200
:
1582 return DP_TRAIN_PRE_EMPHASIS_0
;
1584 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
1585 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1586 case DP_TRAIN_VOLTAGE_SWING_400
:
1587 return DP_TRAIN_PRE_EMPHASIS_6
;
1588 case DP_TRAIN_VOLTAGE_SWING_600
:
1589 case DP_TRAIN_VOLTAGE_SWING_800
:
1590 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1592 return DP_TRAIN_PRE_EMPHASIS_0
;
1595 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1596 case DP_TRAIN_VOLTAGE_SWING_400
:
1597 return DP_TRAIN_PRE_EMPHASIS_6
;
1598 case DP_TRAIN_VOLTAGE_SWING_600
:
1599 return DP_TRAIN_PRE_EMPHASIS_6
;
1600 case DP_TRAIN_VOLTAGE_SWING_800
:
1601 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1602 case DP_TRAIN_VOLTAGE_SWING_1200
:
1604 return DP_TRAIN_PRE_EMPHASIS_0
;
1609 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
1611 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1613 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1614 unsigned long demph_reg_value
, preemph_reg_value
,
1615 uniqtranscale_reg_value
;
1616 uint8_t train_set
= intel_dp
->train_set
[0];
1617 int port
= vlv_dport_to_channel(dport
);
1619 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1620 case DP_TRAIN_PRE_EMPHASIS_0
:
1621 preemph_reg_value
= 0x0004000;
1622 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1623 case DP_TRAIN_VOLTAGE_SWING_400
:
1624 demph_reg_value
= 0x2B405555;
1625 uniqtranscale_reg_value
= 0x552AB83A;
1627 case DP_TRAIN_VOLTAGE_SWING_600
:
1628 demph_reg_value
= 0x2B404040;
1629 uniqtranscale_reg_value
= 0x5548B83A;
1631 case DP_TRAIN_VOLTAGE_SWING_800
:
1632 demph_reg_value
= 0x2B245555;
1633 uniqtranscale_reg_value
= 0x5560B83A;
1635 case DP_TRAIN_VOLTAGE_SWING_1200
:
1636 demph_reg_value
= 0x2B405555;
1637 uniqtranscale_reg_value
= 0x5598DA3A;
1643 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1644 preemph_reg_value
= 0x0002000;
1645 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1646 case DP_TRAIN_VOLTAGE_SWING_400
:
1647 demph_reg_value
= 0x2B404040;
1648 uniqtranscale_reg_value
= 0x5552B83A;
1650 case DP_TRAIN_VOLTAGE_SWING_600
:
1651 demph_reg_value
= 0x2B404848;
1652 uniqtranscale_reg_value
= 0x5580B83A;
1654 case DP_TRAIN_VOLTAGE_SWING_800
:
1655 demph_reg_value
= 0x2B404040;
1656 uniqtranscale_reg_value
= 0x55ADDA3A;
1662 case DP_TRAIN_PRE_EMPHASIS_6
:
1663 preemph_reg_value
= 0x0000000;
1664 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1665 case DP_TRAIN_VOLTAGE_SWING_400
:
1666 demph_reg_value
= 0x2B305555;
1667 uniqtranscale_reg_value
= 0x5570B83A;
1669 case DP_TRAIN_VOLTAGE_SWING_600
:
1670 demph_reg_value
= 0x2B2B4040;
1671 uniqtranscale_reg_value
= 0x55ADDA3A;
1677 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1678 preemph_reg_value
= 0x0006000;
1679 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1680 case DP_TRAIN_VOLTAGE_SWING_400
:
1681 demph_reg_value
= 0x1B405555;
1682 uniqtranscale_reg_value
= 0x55ADDA3A;
1692 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
), 0x00000000);
1693 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL4(port
), demph_reg_value
);
1694 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL2(port
),
1695 uniqtranscale_reg_value
);
1696 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL3(port
), 0x0C782040);
1697 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER0(port
), 0x00030000);
1698 vlv_dpio_write(dev_priv
, DPIO_PCS_CTL_OVER1(port
), preemph_reg_value
);
1699 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
), 0x80000000);
1705 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1710 uint8_t voltage_max
;
1711 uint8_t preemph_max
;
1713 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1714 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
1715 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
1723 voltage_max
= intel_dp_voltage_max(intel_dp
);
1724 if (v
>= voltage_max
)
1725 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1727 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1728 if (p
>= preemph_max
)
1729 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1731 for (lane
= 0; lane
< 4; lane
++)
1732 intel_dp
->train_set
[lane
] = v
| p
;
1736 intel_gen4_signal_levels(uint8_t train_set
)
1738 uint32_t signal_levels
= 0;
1740 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1741 case DP_TRAIN_VOLTAGE_SWING_400
:
1743 signal_levels
|= DP_VOLTAGE_0_4
;
1745 case DP_TRAIN_VOLTAGE_SWING_600
:
1746 signal_levels
|= DP_VOLTAGE_0_6
;
1748 case DP_TRAIN_VOLTAGE_SWING_800
:
1749 signal_levels
|= DP_VOLTAGE_0_8
;
1751 case DP_TRAIN_VOLTAGE_SWING_1200
:
1752 signal_levels
|= DP_VOLTAGE_1_2
;
1755 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1756 case DP_TRAIN_PRE_EMPHASIS_0
:
1758 signal_levels
|= DP_PRE_EMPHASIS_0
;
1760 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1761 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1763 case DP_TRAIN_PRE_EMPHASIS_6
:
1764 signal_levels
|= DP_PRE_EMPHASIS_6
;
1766 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1767 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1770 return signal_levels
;
1773 /* Gen6's DP voltage swing and pre-emphasis control */
1775 intel_gen6_edp_signal_levels(uint8_t train_set
)
1777 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1778 DP_TRAIN_PRE_EMPHASIS_MASK
);
1779 switch (signal_levels
) {
1780 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1781 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1782 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1783 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1784 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1785 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1786 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1787 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1788 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1789 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1790 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1791 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1792 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1793 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1795 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1796 "0x%x\n", signal_levels
);
1797 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1801 /* Gen7's DP voltage swing and pre-emphasis control */
1803 intel_gen7_edp_signal_levels(uint8_t train_set
)
1805 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1806 DP_TRAIN_PRE_EMPHASIS_MASK
);
1807 switch (signal_levels
) {
1808 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1809 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1810 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1811 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1812 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1813 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1815 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1816 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1817 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1818 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1820 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1821 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1822 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1823 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1826 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1827 "0x%x\n", signal_levels
);
1828 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1832 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1834 intel_hsw_signal_levels(uint8_t train_set
)
1836 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1837 DP_TRAIN_PRE_EMPHASIS_MASK
);
1838 switch (signal_levels
) {
1839 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1840 return DDI_BUF_EMP_400MV_0DB_HSW
;
1841 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1842 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1843 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1844 return DDI_BUF_EMP_400MV_6DB_HSW
;
1845 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1846 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1848 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1849 return DDI_BUF_EMP_600MV_0DB_HSW
;
1850 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1851 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1852 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1853 return DDI_BUF_EMP_600MV_6DB_HSW
;
1855 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1856 return DDI_BUF_EMP_800MV_0DB_HSW
;
1857 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1858 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1860 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1861 "0x%x\n", signal_levels
);
1862 return DDI_BUF_EMP_400MV_0DB_HSW
;
1866 /* Properly updates "DP" with the correct signal levels. */
1868 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
1870 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1871 enum port port
= intel_dig_port
->port
;
1872 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1873 uint32_t signal_levels
, mask
;
1874 uint8_t train_set
= intel_dp
->train_set
[0];
1877 signal_levels
= intel_hsw_signal_levels(train_set
);
1878 mask
= DDI_BUF_EMP_MASK
;
1879 } else if (IS_VALLEYVIEW(dev
)) {
1880 signal_levels
= intel_vlv_signal_levels(intel_dp
);
1882 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
1883 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
1884 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
1885 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
1886 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
1887 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
1889 signal_levels
= intel_gen4_signal_levels(train_set
);
1890 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
1893 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
1895 *DP
= (*DP
& ~mask
) | signal_levels
;
1899 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1900 uint32_t dp_reg_value
,
1901 uint8_t dp_train_pat
)
1903 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1904 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1906 enum port port
= intel_dig_port
->port
;
1910 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
1912 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1913 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1915 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1917 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1918 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1919 case DP_TRAINING_PATTERN_DISABLE
:
1920 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1923 case DP_TRAINING_PATTERN_1
:
1924 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1926 case DP_TRAINING_PATTERN_2
:
1927 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1929 case DP_TRAINING_PATTERN_3
:
1930 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1933 I915_WRITE(DP_TP_CTL(port
), temp
);
1935 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
1936 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1938 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1939 case DP_TRAINING_PATTERN_DISABLE
:
1940 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1942 case DP_TRAINING_PATTERN_1
:
1943 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1945 case DP_TRAINING_PATTERN_2
:
1946 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1948 case DP_TRAINING_PATTERN_3
:
1949 DRM_ERROR("DP training pattern 3 not supported\n");
1950 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1955 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1957 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1958 case DP_TRAINING_PATTERN_DISABLE
:
1959 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1961 case DP_TRAINING_PATTERN_1
:
1962 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1964 case DP_TRAINING_PATTERN_2
:
1965 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1967 case DP_TRAINING_PATTERN_3
:
1968 DRM_ERROR("DP training pattern 3 not supported\n");
1969 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1974 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1975 POSTING_READ(intel_dp
->output_reg
);
1977 intel_dp_aux_native_write_1(intel_dp
,
1978 DP_TRAINING_PATTERN_SET
,
1981 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1982 DP_TRAINING_PATTERN_DISABLE
) {
1983 ret
= intel_dp_aux_native_write(intel_dp
,
1984 DP_TRAINING_LANE0_SET
,
1985 intel_dp
->train_set
,
1986 intel_dp
->lane_count
);
1987 if (ret
!= intel_dp
->lane_count
)
1994 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
1996 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1997 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1999 enum port port
= intel_dig_port
->port
;
2005 val
= I915_READ(DP_TP_CTL(port
));
2006 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2007 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2008 I915_WRITE(DP_TP_CTL(port
), val
);
2011 * On PORT_A we can have only eDP in SST mode. There the only reason
2012 * we need to set idle transmission mode is to work around a HW issue
2013 * where we enable the pipe while not in idle link-training mode.
2014 * In this case there is requirement to wait for a minimum number of
2015 * idle patterns to be sent.
2020 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2022 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2025 /* Enable corresponding port and start training pattern 1 */
2027 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2029 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2030 struct drm_device
*dev
= encoder
->dev
;
2033 bool clock_recovery
= false;
2034 int voltage_tries
, loop_tries
;
2035 uint32_t DP
= intel_dp
->DP
;
2038 intel_ddi_prepare_link_retrain(encoder
);
2040 /* Write the link configuration data */
2041 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
2042 intel_dp
->link_configuration
,
2043 DP_LINK_CONFIGURATION_SIZE
);
2047 memset(intel_dp
->train_set
, 0, 4);
2051 clock_recovery
= false;
2053 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2054 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2056 intel_dp_set_signal_levels(intel_dp
, &DP
);
2058 /* Set training pattern 1 */
2059 if (!intel_dp_set_link_train(intel_dp
, DP
,
2060 DP_TRAINING_PATTERN_1
|
2061 DP_LINK_SCRAMBLING_DISABLE
))
2064 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2065 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2066 DRM_ERROR("failed to get link status\n");
2070 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2071 DRM_DEBUG_KMS("clock recovery OK\n");
2072 clock_recovery
= true;
2076 /* Check to see if we've tried the max voltage */
2077 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2078 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2080 if (i
== intel_dp
->lane_count
) {
2082 if (loop_tries
== 5) {
2083 DRM_DEBUG_KMS("too many full retries, give up\n");
2086 memset(intel_dp
->train_set
, 0, 4);
2091 /* Check to see if we've tried the same voltage 5 times */
2092 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2094 if (voltage_tries
== 5) {
2095 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2100 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2102 /* Compute new intel_dp->train_set as requested by target */
2103 intel_get_adjust_train(intel_dp
, link_status
);
2110 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2112 bool channel_eq
= false;
2113 int tries
, cr_tries
;
2114 uint32_t DP
= intel_dp
->DP
;
2116 /* channel equalization */
2121 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2124 DRM_ERROR("failed to train DP, aborting\n");
2125 intel_dp_link_down(intel_dp
);
2129 intel_dp_set_signal_levels(intel_dp
, &DP
);
2131 /* channel eq pattern */
2132 if (!intel_dp_set_link_train(intel_dp
, DP
,
2133 DP_TRAINING_PATTERN_2
|
2134 DP_LINK_SCRAMBLING_DISABLE
))
2137 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2138 if (!intel_dp_get_link_status(intel_dp
, link_status
))
2141 /* Make sure clock is still ok */
2142 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2143 intel_dp_start_link_train(intel_dp
);
2148 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2153 /* Try 5 times, then try clock recovery if that fails */
2155 intel_dp_link_down(intel_dp
);
2156 intel_dp_start_link_train(intel_dp
);
2162 /* Compute new intel_dp->train_set as requested by target */
2163 intel_get_adjust_train(intel_dp
, link_status
);
2167 intel_dp_set_idle_link_train(intel_dp
);
2172 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2176 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2178 intel_dp_set_link_train(intel_dp
, intel_dp
->DP
,
2179 DP_TRAINING_PATTERN_DISABLE
);
2183 intel_dp_link_down(struct intel_dp
*intel_dp
)
2185 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2186 enum port port
= intel_dig_port
->port
;
2187 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2189 struct intel_crtc
*intel_crtc
=
2190 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2191 uint32_t DP
= intel_dp
->DP
;
2194 * DDI code has a strict mode set sequence and we should try to respect
2195 * it, otherwise we might hang the machine in many different ways. So we
2196 * really should be disabling the port only on a complete crtc_disable
2197 * sequence. This function is just called under two conditions on DDI
2199 * - Link train failed while doing crtc_enable, and on this case we
2200 * really should respect the mode set sequence and wait for a
2202 * - Someone turned the monitor off and intel_dp_check_link_status
2203 * called us. We don't need to disable the whole port on this case, so
2204 * when someone turns the monitor on again,
2205 * intel_ddi_prepare_link_retrain will take care of redoing the link
2211 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2214 DRM_DEBUG_KMS("\n");
2216 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2217 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2218 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2220 DP
&= ~DP_LINK_TRAIN_MASK
;
2221 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2223 POSTING_READ(intel_dp
->output_reg
);
2225 /* We don't really know why we're doing this */
2226 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2228 if (HAS_PCH_IBX(dev
) &&
2229 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2230 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2232 /* Hardware workaround: leaving our transcoder select
2233 * set to transcoder B while it's off will prevent the
2234 * corresponding HDMI output on transcoder A.
2236 * Combine this with another hardware workaround:
2237 * transcoder select bit can only be cleared while the
2240 DP
&= ~DP_PIPEB_SELECT
;
2241 I915_WRITE(intel_dp
->output_reg
, DP
);
2243 /* Changes to enable or select take place the vblank
2244 * after being written.
2246 if (WARN_ON(crtc
== NULL
)) {
2247 /* We should never try to disable a port without a crtc
2248 * attached. For paranoia keep the code around for a
2250 POSTING_READ(intel_dp
->output_reg
);
2253 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2256 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2257 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2258 POSTING_READ(intel_dp
->output_reg
);
2259 msleep(intel_dp
->panel_power_down_delay
);
2263 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2265 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2267 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2268 sizeof(intel_dp
->dpcd
)) == 0)
2269 return false; /* aux transfer failed */
2271 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2272 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2273 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2275 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2276 return false; /* DPCD not present */
2278 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2279 DP_DWN_STRM_PORT_PRESENT
))
2280 return true; /* native DP sink */
2282 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2283 return true; /* no per-port downstream info */
2285 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2286 intel_dp
->downstream_ports
,
2287 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2288 return false; /* downstream port status fetch failed */
2294 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2298 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2301 ironlake_edp_panel_vdd_on(intel_dp
);
2303 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2304 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2305 buf
[0], buf
[1], buf
[2]);
2307 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2308 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2309 buf
[0], buf
[1], buf
[2]);
2311 ironlake_edp_panel_vdd_off(intel_dp
, false);
2315 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2319 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2320 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2321 sink_irq_vector
, 1);
2329 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2331 /* NAK by default */
2332 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2336 * According to DP spec
2339 * 2. Configure link according to Receiver Capabilities
2340 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2341 * 4. Check link status on receipt of hot-plug interrupt
2345 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2347 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2349 u8 link_status
[DP_LINK_STATUS_SIZE
];
2351 if (!intel_encoder
->connectors_active
)
2354 if (WARN_ON(!intel_encoder
->base
.crtc
))
2357 /* Try to read receiver status if the link appears to be up */
2358 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2359 intel_dp_link_down(intel_dp
);
2363 /* Now read the DPCD to see if it's actually running */
2364 if (!intel_dp_get_dpcd(intel_dp
)) {
2365 intel_dp_link_down(intel_dp
);
2369 /* Try to read the source of the interrupt */
2370 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2371 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2372 /* Clear interrupt source */
2373 intel_dp_aux_native_write_1(intel_dp
,
2374 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2377 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2378 intel_dp_handle_test_request(intel_dp
);
2379 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2380 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2383 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2384 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2385 drm_get_encoder_name(&intel_encoder
->base
));
2386 intel_dp_start_link_train(intel_dp
);
2387 intel_dp_complete_link_train(intel_dp
);
2388 intel_dp_stop_link_train(intel_dp
);
2392 /* XXX this is probably wrong for multiple downstream ports */
2393 static enum drm_connector_status
2394 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2396 uint8_t *dpcd
= intel_dp
->dpcd
;
2400 if (!intel_dp_get_dpcd(intel_dp
))
2401 return connector_status_disconnected
;
2403 /* if there's no downstream port, we're done */
2404 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2405 return connector_status_connected
;
2407 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2408 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2411 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2413 return connector_status_unknown
;
2414 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2415 : connector_status_disconnected
;
2418 /* If no HPD, poke DDC gently */
2419 if (drm_probe_ddc(&intel_dp
->adapter
))
2420 return connector_status_connected
;
2422 /* Well we tried, say unknown for unreliable port types */
2423 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2424 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2425 return connector_status_unknown
;
2427 /* Anything else is out of spec, warn and ignore */
2428 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2429 return connector_status_disconnected
;
2432 static enum drm_connector_status
2433 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2435 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2437 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2438 enum drm_connector_status status
;
2440 /* Can't disconnect eDP, but you can close the lid... */
2441 if (is_edp(intel_dp
)) {
2442 status
= intel_panel_detect(dev
);
2443 if (status
== connector_status_unknown
)
2444 status
= connector_status_connected
;
2448 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
2449 return connector_status_disconnected
;
2451 return intel_dp_detect_dpcd(intel_dp
);
2454 static enum drm_connector_status
2455 g4x_dp_detect(struct intel_dp
*intel_dp
)
2457 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2459 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2462 /* Can't disconnect eDP, but you can close the lid... */
2463 if (is_edp(intel_dp
)) {
2464 enum drm_connector_status status
;
2466 status
= intel_panel_detect(dev
);
2467 if (status
== connector_status_unknown
)
2468 status
= connector_status_connected
;
2472 switch (intel_dig_port
->port
) {
2474 bit
= PORTB_HOTPLUG_LIVE_STATUS
;
2477 bit
= PORTC_HOTPLUG_LIVE_STATUS
;
2480 bit
= PORTD_HOTPLUG_LIVE_STATUS
;
2483 return connector_status_unknown
;
2486 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2487 return connector_status_disconnected
;
2489 return intel_dp_detect_dpcd(intel_dp
);
2492 static struct edid
*
2493 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2495 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2497 /* use cached edid if we have one */
2498 if (intel_connector
->edid
) {
2503 if (IS_ERR(intel_connector
->edid
))
2506 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2507 edid
= kmemdup(intel_connector
->edid
, size
, GFP_KERNEL
);
2514 return drm_get_edid(connector
, adapter
);
2518 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2520 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2522 /* use cached edid if we have one */
2523 if (intel_connector
->edid
) {
2525 if (IS_ERR(intel_connector
->edid
))
2528 return intel_connector_update_modes(connector
,
2529 intel_connector
->edid
);
2532 return intel_ddc_get_modes(connector
, adapter
);
2535 static enum drm_connector_status
2536 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2538 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2539 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2540 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2541 struct drm_device
*dev
= connector
->dev
;
2542 enum drm_connector_status status
;
2543 struct edid
*edid
= NULL
;
2545 intel_dp
->has_audio
= false;
2547 if (HAS_PCH_SPLIT(dev
))
2548 status
= ironlake_dp_detect(intel_dp
);
2550 status
= g4x_dp_detect(intel_dp
);
2552 if (status
!= connector_status_connected
)
2555 intel_dp_probe_oui(intel_dp
);
2557 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2558 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2560 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2562 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2567 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
2568 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2569 return connector_status_connected
;
2572 static int intel_dp_get_modes(struct drm_connector
*connector
)
2574 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2575 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2576 struct drm_device
*dev
= connector
->dev
;
2579 /* We should parse the EDID data and find out if it has an audio sink
2582 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2586 /* if eDP has no EDID, fall back to fixed mode */
2587 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2588 struct drm_display_mode
*mode
;
2589 mode
= drm_mode_duplicate(dev
,
2590 intel_connector
->panel
.fixed_mode
);
2592 drm_mode_probed_add(connector
, mode
);
2600 intel_dp_detect_audio(struct drm_connector
*connector
)
2602 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2604 bool has_audio
= false;
2606 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2608 has_audio
= drm_detect_monitor_audio(edid
);
2616 intel_dp_set_property(struct drm_connector
*connector
,
2617 struct drm_property
*property
,
2620 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2621 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2622 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
2623 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2626 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
2630 if (property
== dev_priv
->force_audio_property
) {
2634 if (i
== intel_dp
->force_audio
)
2637 intel_dp
->force_audio
= i
;
2639 if (i
== HDMI_AUDIO_AUTO
)
2640 has_audio
= intel_dp_detect_audio(connector
);
2642 has_audio
= (i
== HDMI_AUDIO_ON
);
2644 if (has_audio
== intel_dp
->has_audio
)
2647 intel_dp
->has_audio
= has_audio
;
2651 if (property
== dev_priv
->broadcast_rgb_property
) {
2652 bool old_auto
= intel_dp
->color_range_auto
;
2653 uint32_t old_range
= intel_dp
->color_range
;
2656 case INTEL_BROADCAST_RGB_AUTO
:
2657 intel_dp
->color_range_auto
= true;
2659 case INTEL_BROADCAST_RGB_FULL
:
2660 intel_dp
->color_range_auto
= false;
2661 intel_dp
->color_range
= 0;
2663 case INTEL_BROADCAST_RGB_LIMITED
:
2664 intel_dp
->color_range_auto
= false;
2665 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
2671 if (old_auto
== intel_dp
->color_range_auto
&&
2672 old_range
== intel_dp
->color_range
)
2678 if (is_edp(intel_dp
) &&
2679 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
2680 if (val
== DRM_MODE_SCALE_NONE
) {
2681 DRM_DEBUG_KMS("no scaling not supported\n");
2685 if (intel_connector
->panel
.fitting_mode
== val
) {
2686 /* the eDP scaling property is not changed */
2689 intel_connector
->panel
.fitting_mode
= val
;
2697 if (intel_encoder
->base
.crtc
)
2698 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
2704 intel_dp_connector_destroy(struct drm_connector
*connector
)
2706 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2708 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
2709 kfree(intel_connector
->edid
);
2711 /* Can't call is_edp() since the encoder may have been destroyed
2713 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
2714 intel_panel_fini(&intel_connector
->panel
);
2716 drm_sysfs_connector_remove(connector
);
2717 drm_connector_cleanup(connector
);
2721 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2723 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2724 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2725 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2727 i2c_del_adapter(&intel_dp
->adapter
);
2728 drm_encoder_cleanup(encoder
);
2729 if (is_edp(intel_dp
)) {
2730 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2731 mutex_lock(&dev
->mode_config
.mutex
);
2732 ironlake_panel_vdd_off_sync(intel_dp
);
2733 mutex_unlock(&dev
->mode_config
.mutex
);
2735 kfree(intel_dig_port
);
2738 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2739 .mode_set
= intel_dp_mode_set
,
2742 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2743 .dpms
= intel_connector_dpms
,
2744 .detect
= intel_dp_detect
,
2745 .fill_modes
= drm_helper_probe_single_connector_modes
,
2746 .set_property
= intel_dp_set_property
,
2747 .destroy
= intel_dp_connector_destroy
,
2750 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2751 .get_modes
= intel_dp_get_modes
,
2752 .mode_valid
= intel_dp_mode_valid
,
2753 .best_encoder
= intel_best_encoder
,
2756 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2757 .destroy
= intel_dp_encoder_destroy
,
2761 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2763 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2765 intel_dp_check_link_status(intel_dp
);
2768 /* Return which DP Port should be selected for Transcoder DP control */
2770 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2772 struct drm_device
*dev
= crtc
->dev
;
2773 struct intel_encoder
*intel_encoder
;
2774 struct intel_dp
*intel_dp
;
2776 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2777 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2779 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2780 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2781 return intel_dp
->output_reg
;
2787 /* check the VBT to see whether the eDP is on DP-D port */
2788 bool intel_dpd_is_edp(struct drm_device
*dev
)
2790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2791 struct child_device_config
*p_child
;
2794 if (!dev_priv
->vbt
.child_dev_num
)
2797 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
2798 p_child
= dev_priv
->vbt
.child_dev
+ i
;
2800 if (p_child
->dvo_port
== PORT_IDPD
&&
2801 p_child
->device_type
== DEVICE_TYPE_eDP
)
2808 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2810 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2812 intel_attach_force_audio_property(connector
);
2813 intel_attach_broadcast_rgb_property(connector
);
2814 intel_dp
->color_range_auto
= true;
2816 if (is_edp(intel_dp
)) {
2817 drm_mode_create_scaling_mode_property(connector
->dev
);
2818 drm_object_attach_property(
2820 connector
->dev
->mode_config
.scaling_mode_property
,
2821 DRM_MODE_SCALE_ASPECT
);
2822 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
2827 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
2828 struct intel_dp
*intel_dp
,
2829 struct edp_power_seq
*out
)
2831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2832 struct edp_power_seq cur
, vbt
, spec
, final
;
2833 u32 pp_on
, pp_off
, pp_div
, pp
;
2834 int pp_control_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
2836 if (HAS_PCH_SPLIT(dev
)) {
2837 pp_control_reg
= PCH_PP_CONTROL
;
2838 pp_on_reg
= PCH_PP_ON_DELAYS
;
2839 pp_off_reg
= PCH_PP_OFF_DELAYS
;
2840 pp_div_reg
= PCH_PP_DIVISOR
;
2842 pp_control_reg
= PIPEA_PP_CONTROL
;
2843 pp_on_reg
= PIPEA_PP_ON_DELAYS
;
2844 pp_off_reg
= PIPEA_PP_OFF_DELAYS
;
2845 pp_div_reg
= PIPEA_PP_DIVISOR
;
2848 /* Workaround: Need to write PP_CONTROL with the unlock key as
2849 * the very first thing. */
2850 pp
= ironlake_get_pp_control(intel_dp
);
2851 I915_WRITE(pp_control_reg
, pp
);
2853 pp_on
= I915_READ(pp_on_reg
);
2854 pp_off
= I915_READ(pp_off_reg
);
2855 pp_div
= I915_READ(pp_div_reg
);
2857 /* Pull timing values out of registers */
2858 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2859 PANEL_POWER_UP_DELAY_SHIFT
;
2861 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2862 PANEL_LIGHT_ON_DELAY_SHIFT
;
2864 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2865 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2867 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2868 PANEL_POWER_DOWN_DELAY_SHIFT
;
2870 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2871 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2873 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2874 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2876 vbt
= dev_priv
->vbt
.edp_pps
;
2878 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2879 * our hw here, which are all in 100usec. */
2880 spec
.t1_t3
= 210 * 10;
2881 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
2882 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
2883 spec
.t10
= 500 * 10;
2884 /* This one is special and actually in units of 100ms, but zero
2885 * based in the hw (so we need to add 100 ms). But the sw vbt
2886 * table multiplies it with 1000 to make it in units of 100usec,
2888 spec
.t11_t12
= (510 + 100) * 10;
2890 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2891 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2893 /* Use the max of the register settings and vbt. If both are
2894 * unset, fall back to the spec limits. */
2895 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2897 max(cur.field, vbt.field))
2898 assign_final(t1_t3
);
2902 assign_final(t11_t12
);
2905 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2906 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2907 intel_dp
->backlight_on_delay
= get_delay(t8
);
2908 intel_dp
->backlight_off_delay
= get_delay(t9
);
2909 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2910 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2913 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2914 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2915 intel_dp
->panel_power_cycle_delay
);
2917 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2918 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2925 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
2926 struct intel_dp
*intel_dp
,
2927 struct edp_power_seq
*seq
)
2929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
2931 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
2932 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
2934 if (HAS_PCH_SPLIT(dev
)) {
2935 pp_on_reg
= PCH_PP_ON_DELAYS
;
2936 pp_off_reg
= PCH_PP_OFF_DELAYS
;
2937 pp_div_reg
= PCH_PP_DIVISOR
;
2939 pp_on_reg
= PIPEA_PP_ON_DELAYS
;
2940 pp_off_reg
= PIPEA_PP_OFF_DELAYS
;
2941 pp_div_reg
= PIPEA_PP_DIVISOR
;
2944 /* And finally store the new values in the power sequencer. */
2945 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
2946 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
2947 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
2948 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
2949 /* Compute the divisor for the pp clock, simply match the Bspec
2951 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
2952 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
2953 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
2955 /* Haswell doesn't have any port selection bits for the panel
2956 * power sequencer any more. */
2957 if (IS_VALLEYVIEW(dev
)) {
2958 port_sel
= I915_READ(pp_on_reg
) & 0xc0000000;
2959 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
2960 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
2961 port_sel
= PANEL_POWER_PORT_DP_A
;
2963 port_sel
= PANEL_POWER_PORT_DP_D
;
2968 I915_WRITE(pp_on_reg
, pp_on
);
2969 I915_WRITE(pp_off_reg
, pp_off
);
2970 I915_WRITE(pp_div_reg
, pp_div
);
2972 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2973 I915_READ(pp_on_reg
),
2974 I915_READ(pp_off_reg
),
2975 I915_READ(pp_div_reg
));
2978 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
2979 struct intel_connector
*intel_connector
)
2981 struct drm_connector
*connector
= &intel_connector
->base
;
2982 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2983 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2985 struct drm_display_mode
*fixed_mode
= NULL
;
2986 struct edp_power_seq power_seq
= { 0 };
2988 struct drm_display_mode
*scan
;
2991 if (!is_edp(intel_dp
))
2994 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2996 /* Cache DPCD and EDID for edp. */
2997 ironlake_edp_panel_vdd_on(intel_dp
);
2998 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
2999 ironlake_edp_panel_vdd_off(intel_dp
, false);
3002 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3003 dev_priv
->no_aux_handshake
=
3004 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3005 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3007 /* if this fails, presume the device is a ghost */
3008 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3012 /* We now know it's not a ghost, init power sequence regs. */
3013 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
3016 ironlake_edp_panel_vdd_on(intel_dp
);
3017 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
3019 if (drm_add_edid_modes(connector
, edid
)) {
3020 drm_mode_connector_update_edid_property(connector
,
3022 drm_edid_to_eld(connector
, edid
);
3025 edid
= ERR_PTR(-EINVAL
);
3028 edid
= ERR_PTR(-ENOENT
);
3030 intel_connector
->edid
= edid
;
3032 /* prefer fixed mode from EDID if available */
3033 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
3034 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
3035 fixed_mode
= drm_mode_duplicate(dev
, scan
);
3040 /* fallback to VBT if available for eDP */
3041 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
3042 fixed_mode
= drm_mode_duplicate(dev
,
3043 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
3045 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
3048 ironlake_edp_panel_vdd_off(intel_dp
, false);
3050 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
3051 intel_panel_setup_backlight(connector
);
3057 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
3058 struct intel_connector
*intel_connector
)
3060 struct drm_connector
*connector
= &intel_connector
->base
;
3061 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3062 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3063 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3065 enum port port
= intel_dig_port
->port
;
3066 const char *name
= NULL
;
3069 /* Preserve the current hw state. */
3070 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
3071 intel_dp
->attached_connector
= intel_connector
;
3073 type
= DRM_MODE_CONNECTOR_DisplayPort
;
3075 * FIXME : We need to initialize built-in panels before external panels.
3076 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3080 type
= DRM_MODE_CONNECTOR_eDP
;
3083 if (IS_VALLEYVIEW(dev
))
3084 type
= DRM_MODE_CONNECTOR_eDP
;
3087 if (HAS_PCH_SPLIT(dev
) && intel_dpd_is_edp(dev
))
3088 type
= DRM_MODE_CONNECTOR_eDP
;
3090 default: /* silence GCC warning */
3095 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3096 * for DP the encoder type can be set by the caller to
3097 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3099 if (type
== DRM_MODE_CONNECTOR_eDP
)
3100 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
3102 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3103 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
3106 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
3107 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
3109 connector
->interlace_allowed
= true;
3110 connector
->doublescan_allowed
= 0;
3112 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
3113 ironlake_panel_vdd_work
);
3115 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3116 drm_sysfs_connector_add(connector
);
3119 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3121 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3123 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
3125 switch (intel_dig_port
->port
) {
3127 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
3130 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
3133 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
3136 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
3143 /* Set up the DDC bus. */
3146 intel_encoder
->hpd_pin
= HPD_PORT_A
;
3150 intel_encoder
->hpd_pin
= HPD_PORT_B
;
3154 intel_encoder
->hpd_pin
= HPD_PORT_C
;
3158 intel_encoder
->hpd_pin
= HPD_PORT_D
;
3165 error
= intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
3166 WARN(error
, "intel_dp_i2c_init failed with error %d for port %c\n",
3167 error
, port_name(port
));
3169 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
3170 i2c_del_adapter(&intel_dp
->adapter
);
3171 if (is_edp(intel_dp
)) {
3172 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3173 mutex_lock(&dev
->mode_config
.mutex
);
3174 ironlake_panel_vdd_off_sync(intel_dp
);
3175 mutex_unlock(&dev
->mode_config
.mutex
);
3177 drm_sysfs_connector_remove(connector
);
3178 drm_connector_cleanup(connector
);
3182 intel_dp_add_properties(intel_dp
, connector
);
3184 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3185 * 0xd. Failure to do so will result in spurious interrupts being
3186 * generated on the port when a cable is not attached.
3188 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
3189 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3190 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3197 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
3199 struct intel_digital_port
*intel_dig_port
;
3200 struct intel_encoder
*intel_encoder
;
3201 struct drm_encoder
*encoder
;
3202 struct intel_connector
*intel_connector
;
3204 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
3205 if (!intel_dig_port
)
3208 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
3209 if (!intel_connector
) {
3210 kfree(intel_dig_port
);
3214 intel_encoder
= &intel_dig_port
->base
;
3215 encoder
= &intel_encoder
->base
;
3217 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
3218 DRM_MODE_ENCODER_TMDS
);
3219 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
3221 intel_encoder
->compute_config
= intel_dp_compute_config
;
3222 intel_encoder
->enable
= intel_enable_dp
;
3223 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
3224 intel_encoder
->disable
= intel_disable_dp
;
3225 intel_encoder
->post_disable
= intel_post_disable_dp
;
3226 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
3227 intel_encoder
->get_config
= intel_dp_get_config
;
3228 if (IS_VALLEYVIEW(dev
))
3229 intel_encoder
->pre_pll_enable
= intel_dp_pre_pll_enable
;
3231 intel_dig_port
->port
= port
;
3232 intel_dig_port
->dp
.output_reg
= output_reg
;
3234 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3235 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3236 intel_encoder
->cloneable
= false;
3237 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
3239 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
3240 drm_encoder_cleanup(encoder
);
3241 kfree(intel_dig_port
);
3242 kfree(intel_connector
);