2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll
[] = {
48 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
50 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
53 static const struct dp_link_dpll pch_dpll
[] = {
55 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
57 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
60 static const struct dp_link_dpll vlv_dpll
[] = {
62 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
64 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp
*intel_dp
)
76 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
78 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
81 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
83 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
85 return intel_dig_port
->base
.base
.dev
;
88 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
90 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
93 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
94 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
97 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
99 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
100 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
102 switch (max_link_bw
) {
103 case DP_LINK_BW_1_62
:
106 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
107 if ((IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) &&
108 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
109 max_link_bw
= DP_LINK_BW_5_4
;
111 max_link_bw
= DP_LINK_BW_2_7
;
114 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw
= DP_LINK_BW_1_62
;
123 * The units on the numbers in the next two are... bizarre. Examples will
124 * make it clearer; this one parallels an example in the eDP spec.
126 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 * 270000 * 1 * 8 / 10 == 216000
130 * The actual data capacity of that configuration is 2.16Gbit/s, so the
131 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
132 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
133 * 119000. At 18bpp that's 2142000 kilobits per second.
135 * Thus the strange-looking division by 10 in intel_dp_link_required, to
136 * get the result in decakilobits instead of kilobits.
140 intel_dp_link_required(int pixel_clock
, int bpp
)
142 return (pixel_clock
* bpp
+ 9) / 10;
146 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
148 return (max_link_clock
* max_lanes
* 8) / 10;
151 static enum drm_mode_status
152 intel_dp_mode_valid(struct drm_connector
*connector
,
153 struct drm_display_mode
*mode
)
155 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
156 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
157 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
158 int target_clock
= mode
->clock
;
159 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
161 if (is_edp(intel_dp
) && fixed_mode
) {
162 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
165 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
168 target_clock
= fixed_mode
->clock
;
171 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
172 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
174 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
175 mode_rate
= intel_dp_link_required(target_clock
, 18);
177 if (mode_rate
> max_rate
)
178 return MODE_CLOCK_HIGH
;
180 if (mode
->clock
< 10000)
181 return MODE_CLOCK_LOW
;
183 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
184 return MODE_H_ILLEGAL
;
190 pack_aux(uint8_t *src
, int src_bytes
)
197 for (i
= 0; i
< src_bytes
; i
++)
198 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
203 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
208 for (i
= 0; i
< dst_bytes
; i
++)
209 dst
[i
] = src
>> ((3-i
) * 8);
212 /* hrawclock is 1/4 the FSB frequency */
214 intel_hrawclk(struct drm_device
*dev
)
216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
219 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
220 if (IS_VALLEYVIEW(dev
))
223 clkcfg
= I915_READ(CLKCFG
);
224 switch (clkcfg
& CLKCFG_FSB_MASK
) {
233 case CLKCFG_FSB_1067
:
235 case CLKCFG_FSB_1333
:
237 /* these two are just a guess; one of them might be right */
238 case CLKCFG_FSB_1600
:
239 case CLKCFG_FSB_1600_ALT
:
247 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
248 struct intel_dp
*intel_dp
,
249 struct edp_power_seq
*out
);
251 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
252 struct intel_dp
*intel_dp
,
253 struct edp_power_seq
*out
);
256 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
258 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
259 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
260 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
262 enum port port
= intel_dig_port
->port
;
265 /* modeset should have pipe */
267 return to_intel_crtc(crtc
)->pipe
;
269 /* init time, try to find a pipe with this port selected */
270 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
271 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
272 PANEL_PORT_SELECT_MASK
;
273 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
275 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
283 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
285 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
287 if (HAS_PCH_SPLIT(dev
))
288 return PCH_PP_CONTROL
;
290 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
293 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
295 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
297 if (HAS_PCH_SPLIT(dev
))
298 return PCH_PP_STATUS
;
300 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
303 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
305 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
308 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
311 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
313 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 return (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
320 intel_dp_check_edp(struct intel_dp
*intel_dp
)
322 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
325 if (!is_edp(intel_dp
))
328 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
329 WARN(1, "eDP powered off while attempting aux channel communication.\n");
330 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
331 I915_READ(_pp_stat_reg(intel_dp
)),
332 I915_READ(_pp_ctrl_reg(intel_dp
)));
337 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
339 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
340 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
346 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
348 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
349 msecs_to_jiffies_timeout(10));
351 done
= wait_for_atomic(C
, 10) == 0;
353 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
360 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
362 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
363 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
366 * The clock divider is based off the hrawclk, and would like to run at
367 * 2MHz. So, take the hrawclk value and divide by 2 and use that
369 return index
? 0 : intel_hrawclk(dev
) / 2;
372 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
374 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
375 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
380 if (intel_dig_port
->port
== PORT_A
) {
381 if (IS_GEN6(dev
) || IS_GEN7(dev
))
382 return 200; /* SNB & IVB eDP input clock at 400Mhz */
384 return 225; /* eDP input clock at 450Mhz */
386 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
390 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
392 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
393 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
396 if (intel_dig_port
->port
== PORT_A
) {
399 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
400 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
401 /* Workaround for non-ULT HSW */
408 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
412 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
414 return index
? 0 : 100;
417 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
420 uint32_t aux_clock_divider
)
422 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
423 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
424 uint32_t precharge
, timeout
;
431 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
432 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
434 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
436 return DP_AUX_CH_CTL_SEND_BUSY
|
438 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
439 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
441 DP_AUX_CH_CTL_RECEIVE_ERROR
|
442 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
443 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
444 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
448 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
449 uint8_t *send
, int send_bytes
,
450 uint8_t *recv
, int recv_size
)
452 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
453 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
455 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
456 uint32_t ch_data
= ch_ctl
+ 4;
457 uint32_t aux_clock_divider
;
458 int i
, ret
, recv_bytes
;
461 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
463 /* dp aux is extremely sensitive to irq latency, hence request the
464 * lowest possible wakeup latency and so prevent the cpu from going into
467 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
469 intel_dp_check_edp(intel_dp
);
471 intel_aux_display_runtime_get(dev_priv
);
473 /* Try to wait for any previous AUX channel activity */
474 for (try = 0; try < 3; try++) {
475 status
= I915_READ_NOTRACE(ch_ctl
);
476 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
482 WARN(1, "dp_aux_ch not started status 0x%08x\n",
488 /* Only 5 data registers! */
489 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
494 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
495 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
500 /* Must try at least 3 times according to DP spec */
501 for (try = 0; try < 5; try++) {
502 /* Load the send data into the aux channel data registers */
503 for (i
= 0; i
< send_bytes
; i
+= 4)
504 I915_WRITE(ch_data
+ i
,
505 pack_aux(send
+ i
, send_bytes
- i
));
507 /* Send the command and wait for it to complete */
508 I915_WRITE(ch_ctl
, send_ctl
);
510 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
512 /* Clear done status and any errors */
516 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
517 DP_AUX_CH_CTL_RECEIVE_ERROR
);
519 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
520 DP_AUX_CH_CTL_RECEIVE_ERROR
))
522 if (status
& DP_AUX_CH_CTL_DONE
)
525 if (status
& DP_AUX_CH_CTL_DONE
)
529 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
530 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
535 /* Check for timeout or receive error.
536 * Timeouts occur when the sink is not connected
538 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
539 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
544 /* Timeouts occur when the device isn't connected, so they're
545 * "normal" -- don't fill the kernel log with these */
546 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
547 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
552 /* Unload any bytes sent back from the other side */
553 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
554 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
555 if (recv_bytes
> recv_size
)
556 recv_bytes
= recv_size
;
558 for (i
= 0; i
< recv_bytes
; i
+= 4)
559 unpack_aux(I915_READ(ch_data
+ i
),
560 recv
+ i
, recv_bytes
- i
);
564 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
565 intel_aux_display_runtime_put(dev_priv
);
570 /* Write data to the aux channel in native mode */
572 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
573 uint16_t address
, uint8_t *send
, int send_bytes
)
581 if (WARN_ON(send_bytes
> 16))
584 intel_dp_check_edp(intel_dp
);
585 msg
[0] = DP_AUX_NATIVE_WRITE
<< 4;
586 msg
[1] = address
>> 8;
587 msg
[2] = address
& 0xff;
588 msg
[3] = send_bytes
- 1;
589 memcpy(&msg
[4], send
, send_bytes
);
590 msg_bytes
= send_bytes
+ 4;
591 for (retry
= 0; retry
< 7; retry
++) {
592 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
596 if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_ACK
)
598 else if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_DEFER
)
599 usleep_range(400, 500);
604 DRM_ERROR("too many retries, giving up\n");
608 /* Write a single byte to the aux channel in native mode */
610 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
611 uint16_t address
, uint8_t byte
)
613 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
616 /* read bytes from a native aux channel */
618 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
619 uint16_t address
, uint8_t *recv
, int recv_bytes
)
629 if (WARN_ON(recv_bytes
> 19))
632 intel_dp_check_edp(intel_dp
);
633 msg
[0] = DP_AUX_NATIVE_READ
<< 4;
634 msg
[1] = address
>> 8;
635 msg
[2] = address
& 0xff;
636 msg
[3] = recv_bytes
- 1;
639 reply_bytes
= recv_bytes
+ 1;
641 for (retry
= 0; retry
< 7; retry
++) {
642 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
649 if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_ACK
) {
650 memcpy(recv
, reply
+ 1, ret
- 1);
653 else if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_DEFER
)
654 usleep_range(400, 500);
659 DRM_ERROR("too many retries, giving up\n");
664 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
665 uint8_t write_byte
, uint8_t *read_byte
)
667 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
668 struct intel_dp
*intel_dp
= container_of(adapter
,
671 uint16_t address
= algo_data
->address
;
679 intel_edp_panel_vdd_on(intel_dp
);
680 intel_dp_check_edp(intel_dp
);
681 /* Set up the command byte */
682 if (mode
& MODE_I2C_READ
)
683 msg
[0] = DP_AUX_I2C_READ
<< 4;
685 msg
[0] = DP_AUX_I2C_WRITE
<< 4;
687 if (!(mode
& MODE_I2C_STOP
))
688 msg
[0] |= DP_AUX_I2C_MOT
<< 4;
690 msg
[1] = address
>> 8;
712 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
713 * required to retry at least seven times upon receiving AUX_DEFER
714 * before giving up the AUX transaction.
716 for (retry
= 0; retry
< 7; retry
++) {
717 ret
= intel_dp_aux_ch(intel_dp
,
721 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
725 switch ((reply
[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK
) {
726 case DP_AUX_NATIVE_REPLY_ACK
:
727 /* I2C-over-AUX Reply field is only valid
728 * when paired with AUX ACK.
731 case DP_AUX_NATIVE_REPLY_NACK
:
732 DRM_DEBUG_KMS("aux_ch native nack\n");
735 case DP_AUX_NATIVE_REPLY_DEFER
:
737 * For now, just give more slack to branch devices. We
738 * could check the DPCD for I2C bit rate capabilities,
739 * and if available, adjust the interval. We could also
740 * be more careful with DP-to-Legacy adapters where a
741 * long legacy cable may force very low I2C bit rates.
743 if (intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
744 DP_DWN_STRM_PORT_PRESENT
)
745 usleep_range(500, 600);
747 usleep_range(300, 400);
750 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
756 switch ((reply
[0] >> 4) & DP_AUX_I2C_REPLY_MASK
) {
757 case DP_AUX_I2C_REPLY_ACK
:
758 if (mode
== MODE_I2C_READ
) {
759 *read_byte
= reply
[1];
761 ret
= reply_bytes
- 1;
763 case DP_AUX_I2C_REPLY_NACK
:
764 DRM_DEBUG_KMS("aux_i2c nack\n");
767 case DP_AUX_I2C_REPLY_DEFER
:
768 DRM_DEBUG_KMS("aux_i2c defer\n");
772 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
778 DRM_ERROR("too many retries, giving up\n");
782 edp_panel_vdd_off(intel_dp
, false);
787 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
789 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
791 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
792 intel_dp
->adapter
.dev
.kobj
.name
);
793 intel_connector_unregister(intel_connector
);
797 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
798 struct intel_connector
*intel_connector
, const char *name
)
802 DRM_DEBUG_KMS("i2c_init %s\n", name
);
803 intel_dp
->algo
.running
= false;
804 intel_dp
->algo
.address
= 0;
805 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
807 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
808 intel_dp
->adapter
.owner
= THIS_MODULE
;
809 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
810 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
811 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
812 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
813 intel_dp
->adapter
.dev
.parent
= intel_connector
->base
.dev
->dev
;
815 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
819 ret
= sysfs_create_link(&intel_connector
->base
.kdev
->kobj
,
820 &intel_dp
->adapter
.dev
.kobj
,
821 intel_dp
->adapter
.dev
.kobj
.name
);
824 i2c_del_adapter(&intel_dp
->adapter
);
830 intel_dp_set_clock(struct intel_encoder
*encoder
,
831 struct intel_crtc_config
*pipe_config
, int link_bw
)
833 struct drm_device
*dev
= encoder
->base
.dev
;
834 const struct dp_link_dpll
*divisor
= NULL
;
839 count
= ARRAY_SIZE(gen4_dpll
);
840 } else if (IS_HASWELL(dev
)) {
841 /* Haswell has special-purpose DP DDI clocks. */
842 } else if (HAS_PCH_SPLIT(dev
)) {
844 count
= ARRAY_SIZE(pch_dpll
);
845 } else if (IS_VALLEYVIEW(dev
)) {
847 count
= ARRAY_SIZE(vlv_dpll
);
850 if (divisor
&& count
) {
851 for (i
= 0; i
< count
; i
++) {
852 if (link_bw
== divisor
[i
].link_bw
) {
853 pipe_config
->dpll
= divisor
[i
].dpll
;
854 pipe_config
->clock_set
= true;
862 intel_dp_compute_config(struct intel_encoder
*encoder
,
863 struct intel_crtc_config
*pipe_config
)
865 struct drm_device
*dev
= encoder
->base
.dev
;
866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
867 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
868 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
869 enum port port
= dp_to_dig_port(intel_dp
)->port
;
870 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
871 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
872 int lane_count
, clock
;
873 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
874 /* Conveniently, the link BW constants become indices with a shift...*/
875 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
877 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
878 int link_avail
, link_clock
;
880 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
881 pipe_config
->has_pch_encoder
= true;
883 pipe_config
->has_dp_encoder
= true;
885 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
886 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
888 if (!HAS_PCH_SPLIT(dev
))
889 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
890 intel_connector
->panel
.fitting_mode
);
892 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
893 intel_connector
->panel
.fitting_mode
);
896 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
899 DRM_DEBUG_KMS("DP link computation with max lane count %i "
900 "max bw %02x pixel clock %iKHz\n",
901 max_lane_count
, bws
[max_clock
],
902 adjusted_mode
->crtc_clock
);
904 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
906 bpp
= pipe_config
->pipe_bpp
;
907 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
908 dev_priv
->vbt
.edp_bpp
< bpp
) {
909 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
910 dev_priv
->vbt
.edp_bpp
);
911 bpp
= dev_priv
->vbt
.edp_bpp
;
914 for (; bpp
>= 6*3; bpp
-= 2*3) {
915 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
918 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
919 for (clock
= 0; clock
<= max_clock
; clock
++) {
920 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
921 link_avail
= intel_dp_max_data_rate(link_clock
,
924 if (mode_rate
<= link_avail
) {
934 if (intel_dp
->color_range_auto
) {
937 * CEA-861-E - 5.1 Default Encoding Parameters
938 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
940 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
941 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
943 intel_dp
->color_range
= 0;
946 if (intel_dp
->color_range
)
947 pipe_config
->limited_color_range
= true;
949 intel_dp
->link_bw
= bws
[clock
];
950 intel_dp
->lane_count
= lane_count
;
951 pipe_config
->pipe_bpp
= bpp
;
952 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
954 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
955 intel_dp
->link_bw
, intel_dp
->lane_count
,
956 pipe_config
->port_clock
, bpp
);
957 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
958 mode_rate
, link_avail
);
960 intel_link_compute_m_n(bpp
, lane_count
,
961 adjusted_mode
->crtc_clock
,
962 pipe_config
->port_clock
,
963 &pipe_config
->dp_m_n
);
965 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
970 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
972 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
973 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
974 struct drm_device
*dev
= crtc
->base
.dev
;
975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
978 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
979 dpa_ctl
= I915_READ(DP_A
);
980 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
982 if (crtc
->config
.port_clock
== 162000) {
983 /* For a long time we've carried around a ILK-DevA w/a for the
984 * 160MHz clock. If we're really unlucky, it's still required.
986 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
987 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
988 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
990 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
991 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
994 I915_WRITE(DP_A
, dpa_ctl
);
1000 static void intel_dp_mode_set(struct intel_encoder
*encoder
)
1002 struct drm_device
*dev
= encoder
->base
.dev
;
1003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1004 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1005 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1006 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1007 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1010 * There are four kinds of DP registers:
1017 * IBX PCH and CPU are the same for almost everything,
1018 * except that the CPU DP PLL is configured in this
1021 * CPT PCH is quite different, having many bits moved
1022 * to the TRANS_DP_CTL register instead. That
1023 * configuration happens (oddly) in ironlake_pch_enable
1026 /* Preserve the BIOS-computed detected bit. This is
1027 * supposed to be read-only.
1029 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1031 /* Handle DP bits in common between all three register formats */
1032 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1033 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1035 if (intel_dp
->has_audio
) {
1036 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1037 pipe_name(crtc
->pipe
));
1038 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1039 intel_write_eld(&encoder
->base
, adjusted_mode
);
1042 /* Split out the IBX/CPU vs CPT settings */
1044 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1045 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1046 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1047 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1048 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1049 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1051 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1052 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1054 intel_dp
->DP
|= crtc
->pipe
<< 29;
1055 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1056 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1057 intel_dp
->DP
|= intel_dp
->color_range
;
1059 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1060 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1061 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1062 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1063 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1065 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1066 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1068 if (crtc
->pipe
== 1)
1069 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1071 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1074 if (port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
1075 ironlake_set_pll_cpu_edp(intel_dp
);
1078 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1079 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1081 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1082 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1084 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1085 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1087 static void wait_panel_status(struct intel_dp
*intel_dp
,
1091 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1093 u32 pp_stat_reg
, pp_ctrl_reg
;
1095 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1096 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1098 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1100 I915_READ(pp_stat_reg
),
1101 I915_READ(pp_ctrl_reg
));
1103 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1104 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1105 I915_READ(pp_stat_reg
),
1106 I915_READ(pp_ctrl_reg
));
1109 DRM_DEBUG_KMS("Wait complete\n");
1112 static void wait_panel_on(struct intel_dp
*intel_dp
)
1114 DRM_DEBUG_KMS("Wait for panel power on\n");
1115 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1118 static void wait_panel_off(struct intel_dp
*intel_dp
)
1120 DRM_DEBUG_KMS("Wait for panel power off time\n");
1121 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1124 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1126 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1128 /* When we disable the VDD override bit last we have to do the manual
1130 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1131 intel_dp
->panel_power_cycle_delay
);
1133 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1136 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1138 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1139 intel_dp
->backlight_on_delay
);
1142 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1144 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1145 intel_dp
->backlight_off_delay
);
1148 /* Read the current pp_control value, unlocking the register if it
1152 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1154 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1158 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1159 control
&= ~PANEL_UNLOCK_MASK
;
1160 control
|= PANEL_UNLOCK_REGS
;
1164 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1166 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 u32 pp_stat_reg
, pp_ctrl_reg
;
1171 if (!is_edp(intel_dp
))
1174 WARN(intel_dp
->want_panel_vdd
,
1175 "eDP VDD already requested on\n");
1177 intel_dp
->want_panel_vdd
= true;
1179 if (edp_have_panel_vdd(intel_dp
))
1182 intel_runtime_pm_get(dev_priv
);
1184 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1186 if (!edp_have_panel_power(intel_dp
))
1187 wait_panel_power_cycle(intel_dp
);
1189 pp
= ironlake_get_pp_control(intel_dp
);
1190 pp
|= EDP_FORCE_VDD
;
1192 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1193 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1195 I915_WRITE(pp_ctrl_reg
, pp
);
1196 POSTING_READ(pp_ctrl_reg
);
1197 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1198 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1200 * If the panel wasn't on, delay before accessing aux channel
1202 if (!edp_have_panel_power(intel_dp
)) {
1203 DRM_DEBUG_KMS("eDP was not running\n");
1204 msleep(intel_dp
->panel_power_up_delay
);
1208 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1210 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1213 u32 pp_stat_reg
, pp_ctrl_reg
;
1215 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1217 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1218 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1220 pp
= ironlake_get_pp_control(intel_dp
);
1221 pp
&= ~EDP_FORCE_VDD
;
1223 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1224 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1226 I915_WRITE(pp_ctrl_reg
, pp
);
1227 POSTING_READ(pp_ctrl_reg
);
1229 /* Make sure sequencer is idle before allowing subsequent activity */
1230 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1231 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1233 if ((pp
& POWER_TARGET_ON
) == 0)
1234 intel_dp
->last_power_cycle
= jiffies
;
1236 intel_runtime_pm_put(dev_priv
);
1240 static void edp_panel_vdd_work(struct work_struct
*__work
)
1242 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1243 struct intel_dp
, panel_vdd_work
);
1244 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1246 mutex_lock(&dev
->mode_config
.mutex
);
1247 edp_panel_vdd_off_sync(intel_dp
);
1248 mutex_unlock(&dev
->mode_config
.mutex
);
1251 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1253 if (!is_edp(intel_dp
))
1256 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1258 intel_dp
->want_panel_vdd
= false;
1261 edp_panel_vdd_off_sync(intel_dp
);
1264 * Queue the timer to fire a long
1265 * time from now (relative to the power down delay)
1266 * to keep the panel power up across a sequence of operations
1268 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1269 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1273 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1275 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1280 if (!is_edp(intel_dp
))
1283 DRM_DEBUG_KMS("Turn eDP power on\n");
1285 if (edp_have_panel_power(intel_dp
)) {
1286 DRM_DEBUG_KMS("eDP power already on\n");
1290 wait_panel_power_cycle(intel_dp
);
1292 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1293 pp
= ironlake_get_pp_control(intel_dp
);
1295 /* ILK workaround: disable reset around power sequence */
1296 pp
&= ~PANEL_POWER_RESET
;
1297 I915_WRITE(pp_ctrl_reg
, pp
);
1298 POSTING_READ(pp_ctrl_reg
);
1301 pp
|= POWER_TARGET_ON
;
1303 pp
|= PANEL_POWER_RESET
;
1305 I915_WRITE(pp_ctrl_reg
, pp
);
1306 POSTING_READ(pp_ctrl_reg
);
1308 wait_panel_on(intel_dp
);
1309 intel_dp
->last_power_on
= jiffies
;
1312 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1313 I915_WRITE(pp_ctrl_reg
, pp
);
1314 POSTING_READ(pp_ctrl_reg
);
1318 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1320 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1325 if (!is_edp(intel_dp
))
1328 DRM_DEBUG_KMS("Turn eDP power off\n");
1330 edp_wait_backlight_off(intel_dp
);
1332 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1334 pp
= ironlake_get_pp_control(intel_dp
);
1335 /* We need to switch off panel power _and_ force vdd, for otherwise some
1336 * panels get very unhappy and cease to work. */
1337 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1340 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1342 intel_dp
->want_panel_vdd
= false;
1344 I915_WRITE(pp_ctrl_reg
, pp
);
1345 POSTING_READ(pp_ctrl_reg
);
1347 intel_dp
->last_power_cycle
= jiffies
;
1348 wait_panel_off(intel_dp
);
1350 /* We got a reference when we enabled the VDD. */
1351 intel_runtime_pm_put(dev_priv
);
1354 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1356 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1357 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1362 if (!is_edp(intel_dp
))
1365 DRM_DEBUG_KMS("\n");
1367 * If we enable the backlight right away following a panel power
1368 * on, we may see slight flicker as the panel syncs with the eDP
1369 * link. So delay a bit to make sure the image is solid before
1370 * allowing it to appear.
1372 wait_backlight_on(intel_dp
);
1373 pp
= ironlake_get_pp_control(intel_dp
);
1374 pp
|= EDP_BLC_ENABLE
;
1376 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1378 I915_WRITE(pp_ctrl_reg
, pp
);
1379 POSTING_READ(pp_ctrl_reg
);
1381 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1384 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1386 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1391 if (!is_edp(intel_dp
))
1394 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1396 DRM_DEBUG_KMS("\n");
1397 pp
= ironlake_get_pp_control(intel_dp
);
1398 pp
&= ~EDP_BLC_ENABLE
;
1400 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1402 I915_WRITE(pp_ctrl_reg
, pp
);
1403 POSTING_READ(pp_ctrl_reg
);
1404 intel_dp
->last_backlight_off
= jiffies
;
1407 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1409 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1410 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1411 struct drm_device
*dev
= crtc
->dev
;
1412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1415 assert_pipe_disabled(dev_priv
,
1416 to_intel_crtc(crtc
)->pipe
);
1418 DRM_DEBUG_KMS("\n");
1419 dpa_ctl
= I915_READ(DP_A
);
1420 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1421 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1423 /* We don't adjust intel_dp->DP while tearing down the link, to
1424 * facilitate link retraining (e.g. after hotplug). Hence clear all
1425 * enable bits here to ensure that we don't enable too much. */
1426 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1427 intel_dp
->DP
|= DP_PLL_ENABLE
;
1428 I915_WRITE(DP_A
, intel_dp
->DP
);
1433 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1435 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1436 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1437 struct drm_device
*dev
= crtc
->dev
;
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1441 assert_pipe_disabled(dev_priv
,
1442 to_intel_crtc(crtc
)->pipe
);
1444 dpa_ctl
= I915_READ(DP_A
);
1445 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1446 "dp pll off, should be on\n");
1447 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1449 /* We can't rely on the value tracked for the DP register in
1450 * intel_dp->DP because link_down must not change that (otherwise link
1451 * re-training will fail. */
1452 dpa_ctl
&= ~DP_PLL_ENABLE
;
1453 I915_WRITE(DP_A
, dpa_ctl
);
1458 /* If the sink supports it, try to set the power state appropriately */
1459 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1463 /* Should have a valid DPCD by this point */
1464 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1467 if (mode
!= DRM_MODE_DPMS_ON
) {
1468 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1471 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1474 * When turning on, we need to retry for 1ms to give the sink
1477 for (i
= 0; i
< 3; i
++) {
1478 ret
= intel_dp_aux_native_write_1(intel_dp
,
1488 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1491 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1492 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1493 struct drm_device
*dev
= encoder
->base
.dev
;
1494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1495 enum intel_display_power_domain power_domain
;
1498 power_domain
= intel_display_port_power_domain(encoder
);
1499 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1502 tmp
= I915_READ(intel_dp
->output_reg
);
1504 if (!(tmp
& DP_PORT_EN
))
1507 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1508 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1509 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1510 *pipe
= PORT_TO_PIPE(tmp
);
1516 switch (intel_dp
->output_reg
) {
1518 trans_sel
= TRANS_DP_PORT_SEL_B
;
1521 trans_sel
= TRANS_DP_PORT_SEL_C
;
1524 trans_sel
= TRANS_DP_PORT_SEL_D
;
1531 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1532 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1538 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1539 intel_dp
->output_reg
);
1545 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1546 struct intel_crtc_config
*pipe_config
)
1548 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1550 struct drm_device
*dev
= encoder
->base
.dev
;
1551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1552 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1553 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1556 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1557 tmp
= I915_READ(intel_dp
->output_reg
);
1558 if (tmp
& DP_SYNC_HS_HIGH
)
1559 flags
|= DRM_MODE_FLAG_PHSYNC
;
1561 flags
|= DRM_MODE_FLAG_NHSYNC
;
1563 if (tmp
& DP_SYNC_VS_HIGH
)
1564 flags
|= DRM_MODE_FLAG_PVSYNC
;
1566 flags
|= DRM_MODE_FLAG_NVSYNC
;
1568 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1569 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1570 flags
|= DRM_MODE_FLAG_PHSYNC
;
1572 flags
|= DRM_MODE_FLAG_NHSYNC
;
1574 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1575 flags
|= DRM_MODE_FLAG_PVSYNC
;
1577 flags
|= DRM_MODE_FLAG_NVSYNC
;
1580 pipe_config
->adjusted_mode
.flags
|= flags
;
1582 pipe_config
->has_dp_encoder
= true;
1584 intel_dp_get_m_n(crtc
, pipe_config
);
1586 if (port
== PORT_A
) {
1587 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1588 pipe_config
->port_clock
= 162000;
1590 pipe_config
->port_clock
= 270000;
1593 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1594 &pipe_config
->dp_m_n
);
1596 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1597 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1599 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1601 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1602 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1604 * This is a big fat ugly hack.
1606 * Some machines in UEFI boot mode provide us a VBT that has 18
1607 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1608 * unknown we fail to light up. Yet the same BIOS boots up with
1609 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1610 * max, not what it tells us to use.
1612 * Note: This will still be broken if the eDP panel is not lit
1613 * up by the BIOS, and thus we can't get the mode at module
1616 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1617 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1618 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1622 static bool is_edp_psr(struct drm_device
*dev
)
1624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1626 return dev_priv
->psr
.sink_support
;
1629 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1636 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1639 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1640 struct edp_vsc_psr
*vsc_psr
)
1642 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1643 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1645 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1646 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1647 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1648 uint32_t *data
= (uint32_t *) vsc_psr
;
1651 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1652 the video DIP being updated before program video DIP data buffer
1653 registers for DIP being updated. */
1654 I915_WRITE(ctl_reg
, 0);
1655 POSTING_READ(ctl_reg
);
1657 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1658 if (i
< sizeof(struct edp_vsc_psr
))
1659 I915_WRITE(data_reg
+ i
, *data
++);
1661 I915_WRITE(data_reg
+ i
, 0);
1664 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1665 POSTING_READ(ctl_reg
);
1668 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1670 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1672 struct edp_vsc_psr psr_vsc
;
1674 if (intel_dp
->psr_setup_done
)
1677 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1678 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1679 psr_vsc
.sdp_header
.HB0
= 0;
1680 psr_vsc
.sdp_header
.HB1
= 0x7;
1681 psr_vsc
.sdp_header
.HB2
= 0x2;
1682 psr_vsc
.sdp_header
.HB3
= 0x8;
1683 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1685 /* Avoid continuous PSR exit by masking memup and hpd */
1686 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1687 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1689 intel_dp
->psr_setup_done
= true;
1692 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1694 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1696 uint32_t aux_clock_divider
;
1697 int precharge
= 0x3;
1698 int msg_size
= 5; /* Header(4) + Message(1) */
1700 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1702 /* Enable PSR in sink */
1703 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1704 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1706 ~DP_PSR_MAIN_LINK_ACTIVE
);
1708 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1710 DP_PSR_MAIN_LINK_ACTIVE
);
1712 /* Setup AUX registers */
1713 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1714 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1715 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1716 DP_AUX_CH_CTL_TIME_OUT_400us
|
1717 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1718 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1719 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1722 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1724 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1726 uint32_t max_sleep_time
= 0x1f;
1727 uint32_t idle_frames
= 1;
1729 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1731 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1732 val
|= EDP_PSR_LINK_STANDBY
;
1733 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1734 val
|= EDP_PSR_TP1_TIME_0us
;
1735 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1737 val
|= EDP_PSR_LINK_DISABLE
;
1739 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1740 IS_BROADWELL(dev
) ? 0 : link_entry_time
|
1741 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1742 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1746 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1748 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1749 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1751 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1752 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1753 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1754 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1756 dev_priv
->psr
.source_ok
= false;
1758 if (!HAS_PSR(dev
)) {
1759 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1763 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1764 (dig_port
->port
!= PORT_A
)) {
1765 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1769 if (!i915
.enable_psr
) {
1770 DRM_DEBUG_KMS("PSR disable by flag\n");
1774 crtc
= dig_port
->base
.base
.crtc
;
1776 DRM_DEBUG_KMS("crtc not active for PSR\n");
1780 intel_crtc
= to_intel_crtc(crtc
);
1781 if (!intel_crtc_active(crtc
)) {
1782 DRM_DEBUG_KMS("crtc not active for PSR\n");
1786 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1787 if (obj
->tiling_mode
!= I915_TILING_X
||
1788 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1789 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1793 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1794 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1798 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1800 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1804 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1805 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1809 dev_priv
->psr
.source_ok
= true;
1813 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1815 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1817 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1818 intel_edp_is_psr_enabled(dev
))
1821 /* Setup PSR once */
1822 intel_edp_psr_setup(intel_dp
);
1824 /* Enable PSR on the panel */
1825 intel_edp_psr_enable_sink(intel_dp
);
1827 /* Enable PSR on the host */
1828 intel_edp_psr_enable_source(intel_dp
);
1831 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1833 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1835 if (intel_edp_psr_match_conditions(intel_dp
) &&
1836 !intel_edp_is_psr_enabled(dev
))
1837 intel_edp_psr_do_enable(intel_dp
);
1840 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1842 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1845 if (!intel_edp_is_psr_enabled(dev
))
1848 I915_WRITE(EDP_PSR_CTL(dev
),
1849 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1851 /* Wait till PSR is idle */
1852 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1853 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1854 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1857 void intel_edp_psr_update(struct drm_device
*dev
)
1859 struct intel_encoder
*encoder
;
1860 struct intel_dp
*intel_dp
= NULL
;
1862 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1863 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1864 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1866 if (!is_edp_psr(dev
))
1869 if (!intel_edp_psr_match_conditions(intel_dp
))
1870 intel_edp_psr_disable(intel_dp
);
1872 if (!intel_edp_is_psr_enabled(dev
))
1873 intel_edp_psr_do_enable(intel_dp
);
1877 static void intel_disable_dp(struct intel_encoder
*encoder
)
1879 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1880 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1881 struct drm_device
*dev
= encoder
->base
.dev
;
1883 /* Make sure the panel is off before trying to change the mode. But also
1884 * ensure that we have vdd while we switch off the panel. */
1885 intel_edp_panel_vdd_on(intel_dp
);
1886 intel_edp_backlight_off(intel_dp
);
1887 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1888 intel_edp_panel_off(intel_dp
);
1890 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1891 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1892 intel_dp_link_down(intel_dp
);
1895 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1897 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1898 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1899 struct drm_device
*dev
= encoder
->base
.dev
;
1901 if (port
== PORT_A
|| IS_VALLEYVIEW(dev
)) {
1902 intel_dp_link_down(intel_dp
);
1903 if (!IS_VALLEYVIEW(dev
))
1904 ironlake_edp_pll_off(intel_dp
);
1908 static void intel_enable_dp(struct intel_encoder
*encoder
)
1910 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1911 struct drm_device
*dev
= encoder
->base
.dev
;
1912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1913 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1915 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1918 intel_edp_panel_vdd_on(intel_dp
);
1919 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1920 intel_dp_start_link_train(intel_dp
);
1921 intel_edp_panel_on(intel_dp
);
1922 edp_panel_vdd_off(intel_dp
, true);
1923 intel_dp_complete_link_train(intel_dp
);
1924 intel_dp_stop_link_train(intel_dp
);
1927 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1929 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1931 intel_enable_dp(encoder
);
1932 intel_edp_backlight_on(intel_dp
);
1935 static void vlv_enable_dp(struct intel_encoder
*encoder
)
1937 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1939 intel_edp_backlight_on(intel_dp
);
1942 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
1944 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1945 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1947 if (dport
->port
== PORT_A
)
1948 ironlake_edp_pll_on(intel_dp
);
1951 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
1953 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1954 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1955 struct drm_device
*dev
= encoder
->base
.dev
;
1956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1957 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1958 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1959 int pipe
= intel_crtc
->pipe
;
1960 struct edp_power_seq power_seq
;
1963 mutex_lock(&dev_priv
->dpio_lock
);
1965 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1972 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1973 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1974 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1976 mutex_unlock(&dev_priv
->dpio_lock
);
1978 if (is_edp(intel_dp
)) {
1979 /* init power sequencer on this pipe and port */
1980 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
1981 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
1985 intel_enable_dp(encoder
);
1987 vlv_wait_port_ready(dev_priv
, dport
);
1990 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1992 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1993 struct drm_device
*dev
= encoder
->base
.dev
;
1994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1995 struct intel_crtc
*intel_crtc
=
1996 to_intel_crtc(encoder
->base
.crtc
);
1997 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1998 int pipe
= intel_crtc
->pipe
;
2000 /* Program Tx lane resets to default */
2001 mutex_lock(&dev_priv
->dpio_lock
);
2002 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2003 DPIO_PCS_TX_LANE2_RESET
|
2004 DPIO_PCS_TX_LANE1_RESET
);
2005 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2006 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2007 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2008 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2009 DPIO_PCS_CLK_SOFT_RESET
);
2011 /* Fix up inter-pair skew failure */
2012 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2013 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2014 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2015 mutex_unlock(&dev_priv
->dpio_lock
);
2019 * Native read with retry for link status and receiver capability reads for
2020 * cases where the sink may still be asleep.
2023 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
2024 uint8_t *recv
, int recv_bytes
)
2029 * Sinks are *supposed* to come up within 1ms from an off state,
2030 * but we're also supposed to retry 3 times per the spec.
2032 for (i
= 0; i
< 3; i
++) {
2033 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
2035 if (ret
== recv_bytes
)
2044 * Fetch AUX CH registers 0x202 - 0x207 which contain
2045 * link status information
2048 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2050 return intel_dp_aux_native_read_retry(intel_dp
,
2053 DP_LINK_STATUS_SIZE
);
2057 * These are source-specific values; current Intel hardware supports
2058 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2062 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2064 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2065 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2067 if (IS_VALLEYVIEW(dev
) || IS_BROADWELL(dev
))
2068 return DP_TRAIN_VOLTAGE_SWING_1200
;
2069 else if (IS_GEN7(dev
) && port
== PORT_A
)
2070 return DP_TRAIN_VOLTAGE_SWING_800
;
2071 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2072 return DP_TRAIN_VOLTAGE_SWING_1200
;
2074 return DP_TRAIN_VOLTAGE_SWING_800
;
2078 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2080 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2081 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2083 if (IS_BROADWELL(dev
)) {
2084 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2085 case DP_TRAIN_VOLTAGE_SWING_400
:
2086 case DP_TRAIN_VOLTAGE_SWING_600
:
2087 return DP_TRAIN_PRE_EMPHASIS_6
;
2088 case DP_TRAIN_VOLTAGE_SWING_800
:
2089 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2090 case DP_TRAIN_VOLTAGE_SWING_1200
:
2092 return DP_TRAIN_PRE_EMPHASIS_0
;
2094 } else if (IS_HASWELL(dev
)) {
2095 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2096 case DP_TRAIN_VOLTAGE_SWING_400
:
2097 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2098 case DP_TRAIN_VOLTAGE_SWING_600
:
2099 return DP_TRAIN_PRE_EMPHASIS_6
;
2100 case DP_TRAIN_VOLTAGE_SWING_800
:
2101 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2102 case DP_TRAIN_VOLTAGE_SWING_1200
:
2104 return DP_TRAIN_PRE_EMPHASIS_0
;
2106 } else if (IS_VALLEYVIEW(dev
)) {
2107 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2108 case DP_TRAIN_VOLTAGE_SWING_400
:
2109 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2110 case DP_TRAIN_VOLTAGE_SWING_600
:
2111 return DP_TRAIN_PRE_EMPHASIS_6
;
2112 case DP_TRAIN_VOLTAGE_SWING_800
:
2113 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2114 case DP_TRAIN_VOLTAGE_SWING_1200
:
2116 return DP_TRAIN_PRE_EMPHASIS_0
;
2118 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2119 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2120 case DP_TRAIN_VOLTAGE_SWING_400
:
2121 return DP_TRAIN_PRE_EMPHASIS_6
;
2122 case DP_TRAIN_VOLTAGE_SWING_600
:
2123 case DP_TRAIN_VOLTAGE_SWING_800
:
2124 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2126 return DP_TRAIN_PRE_EMPHASIS_0
;
2129 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2130 case DP_TRAIN_VOLTAGE_SWING_400
:
2131 return DP_TRAIN_PRE_EMPHASIS_6
;
2132 case DP_TRAIN_VOLTAGE_SWING_600
:
2133 return DP_TRAIN_PRE_EMPHASIS_6
;
2134 case DP_TRAIN_VOLTAGE_SWING_800
:
2135 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2136 case DP_TRAIN_VOLTAGE_SWING_1200
:
2138 return DP_TRAIN_PRE_EMPHASIS_0
;
2143 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2145 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2147 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2148 struct intel_crtc
*intel_crtc
=
2149 to_intel_crtc(dport
->base
.base
.crtc
);
2150 unsigned long demph_reg_value
, preemph_reg_value
,
2151 uniqtranscale_reg_value
;
2152 uint8_t train_set
= intel_dp
->train_set
[0];
2153 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2154 int pipe
= intel_crtc
->pipe
;
2156 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2157 case DP_TRAIN_PRE_EMPHASIS_0
:
2158 preemph_reg_value
= 0x0004000;
2159 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2160 case DP_TRAIN_VOLTAGE_SWING_400
:
2161 demph_reg_value
= 0x2B405555;
2162 uniqtranscale_reg_value
= 0x552AB83A;
2164 case DP_TRAIN_VOLTAGE_SWING_600
:
2165 demph_reg_value
= 0x2B404040;
2166 uniqtranscale_reg_value
= 0x5548B83A;
2168 case DP_TRAIN_VOLTAGE_SWING_800
:
2169 demph_reg_value
= 0x2B245555;
2170 uniqtranscale_reg_value
= 0x5560B83A;
2172 case DP_TRAIN_VOLTAGE_SWING_1200
:
2173 demph_reg_value
= 0x2B405555;
2174 uniqtranscale_reg_value
= 0x5598DA3A;
2180 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2181 preemph_reg_value
= 0x0002000;
2182 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2183 case DP_TRAIN_VOLTAGE_SWING_400
:
2184 demph_reg_value
= 0x2B404040;
2185 uniqtranscale_reg_value
= 0x5552B83A;
2187 case DP_TRAIN_VOLTAGE_SWING_600
:
2188 demph_reg_value
= 0x2B404848;
2189 uniqtranscale_reg_value
= 0x5580B83A;
2191 case DP_TRAIN_VOLTAGE_SWING_800
:
2192 demph_reg_value
= 0x2B404040;
2193 uniqtranscale_reg_value
= 0x55ADDA3A;
2199 case DP_TRAIN_PRE_EMPHASIS_6
:
2200 preemph_reg_value
= 0x0000000;
2201 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2202 case DP_TRAIN_VOLTAGE_SWING_400
:
2203 demph_reg_value
= 0x2B305555;
2204 uniqtranscale_reg_value
= 0x5570B83A;
2206 case DP_TRAIN_VOLTAGE_SWING_600
:
2207 demph_reg_value
= 0x2B2B4040;
2208 uniqtranscale_reg_value
= 0x55ADDA3A;
2214 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2215 preemph_reg_value
= 0x0006000;
2216 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2217 case DP_TRAIN_VOLTAGE_SWING_400
:
2218 demph_reg_value
= 0x1B405555;
2219 uniqtranscale_reg_value
= 0x55ADDA3A;
2229 mutex_lock(&dev_priv
->dpio_lock
);
2230 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2231 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2232 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2233 uniqtranscale_reg_value
);
2234 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2235 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2236 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2237 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2238 mutex_unlock(&dev_priv
->dpio_lock
);
2244 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2245 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2250 uint8_t voltage_max
;
2251 uint8_t preemph_max
;
2253 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2254 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2255 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2263 voltage_max
= intel_dp_voltage_max(intel_dp
);
2264 if (v
>= voltage_max
)
2265 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2267 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2268 if (p
>= preemph_max
)
2269 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2271 for (lane
= 0; lane
< 4; lane
++)
2272 intel_dp
->train_set
[lane
] = v
| p
;
2276 intel_gen4_signal_levels(uint8_t train_set
)
2278 uint32_t signal_levels
= 0;
2280 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2281 case DP_TRAIN_VOLTAGE_SWING_400
:
2283 signal_levels
|= DP_VOLTAGE_0_4
;
2285 case DP_TRAIN_VOLTAGE_SWING_600
:
2286 signal_levels
|= DP_VOLTAGE_0_6
;
2288 case DP_TRAIN_VOLTAGE_SWING_800
:
2289 signal_levels
|= DP_VOLTAGE_0_8
;
2291 case DP_TRAIN_VOLTAGE_SWING_1200
:
2292 signal_levels
|= DP_VOLTAGE_1_2
;
2295 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2296 case DP_TRAIN_PRE_EMPHASIS_0
:
2298 signal_levels
|= DP_PRE_EMPHASIS_0
;
2300 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2301 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2303 case DP_TRAIN_PRE_EMPHASIS_6
:
2304 signal_levels
|= DP_PRE_EMPHASIS_6
;
2306 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2307 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2310 return signal_levels
;
2313 /* Gen6's DP voltage swing and pre-emphasis control */
2315 intel_gen6_edp_signal_levels(uint8_t train_set
)
2317 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2318 DP_TRAIN_PRE_EMPHASIS_MASK
);
2319 switch (signal_levels
) {
2320 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2321 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2322 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2323 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2324 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2325 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2326 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2327 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2328 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2329 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2330 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2331 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2332 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2333 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2335 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2336 "0x%x\n", signal_levels
);
2337 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2341 /* Gen7's DP voltage swing and pre-emphasis control */
2343 intel_gen7_edp_signal_levels(uint8_t train_set
)
2345 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2346 DP_TRAIN_PRE_EMPHASIS_MASK
);
2347 switch (signal_levels
) {
2348 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2349 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2350 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2351 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2352 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2353 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2355 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2356 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2357 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2358 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2360 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2361 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2362 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2363 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2366 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2367 "0x%x\n", signal_levels
);
2368 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2372 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2374 intel_hsw_signal_levels(uint8_t train_set
)
2376 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2377 DP_TRAIN_PRE_EMPHASIS_MASK
);
2378 switch (signal_levels
) {
2379 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2380 return DDI_BUF_EMP_400MV_0DB_HSW
;
2381 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2382 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2383 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2384 return DDI_BUF_EMP_400MV_6DB_HSW
;
2385 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2386 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2388 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2389 return DDI_BUF_EMP_600MV_0DB_HSW
;
2390 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2391 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2392 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2393 return DDI_BUF_EMP_600MV_6DB_HSW
;
2395 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2396 return DDI_BUF_EMP_800MV_0DB_HSW
;
2397 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2398 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2400 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2401 "0x%x\n", signal_levels
);
2402 return DDI_BUF_EMP_400MV_0DB_HSW
;
2407 intel_bdw_signal_levels(uint8_t train_set
)
2409 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2410 DP_TRAIN_PRE_EMPHASIS_MASK
);
2411 switch (signal_levels
) {
2412 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2413 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2414 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2415 return DDI_BUF_EMP_400MV_3_5DB_BDW
; /* Sel1 */
2416 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2417 return DDI_BUF_EMP_400MV_6DB_BDW
; /* Sel2 */
2419 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2420 return DDI_BUF_EMP_600MV_0DB_BDW
; /* Sel3 */
2421 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2422 return DDI_BUF_EMP_600MV_3_5DB_BDW
; /* Sel4 */
2423 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2424 return DDI_BUF_EMP_600MV_6DB_BDW
; /* Sel5 */
2426 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2427 return DDI_BUF_EMP_800MV_0DB_BDW
; /* Sel6 */
2428 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2429 return DDI_BUF_EMP_800MV_3_5DB_BDW
; /* Sel7 */
2431 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2432 return DDI_BUF_EMP_1200MV_0DB_BDW
; /* Sel8 */
2435 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2436 "0x%x\n", signal_levels
);
2437 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2441 /* Properly updates "DP" with the correct signal levels. */
2443 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2445 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2446 enum port port
= intel_dig_port
->port
;
2447 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2448 uint32_t signal_levels
, mask
;
2449 uint8_t train_set
= intel_dp
->train_set
[0];
2451 if (IS_BROADWELL(dev
)) {
2452 signal_levels
= intel_bdw_signal_levels(train_set
);
2453 mask
= DDI_BUF_EMP_MASK
;
2454 } else if (IS_HASWELL(dev
)) {
2455 signal_levels
= intel_hsw_signal_levels(train_set
);
2456 mask
= DDI_BUF_EMP_MASK
;
2457 } else if (IS_VALLEYVIEW(dev
)) {
2458 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2460 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2461 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2462 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2463 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2464 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2465 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2467 signal_levels
= intel_gen4_signal_levels(train_set
);
2468 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2471 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2473 *DP
= (*DP
& ~mask
) | signal_levels
;
2477 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2479 uint8_t dp_train_pat
)
2481 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2482 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2484 enum port port
= intel_dig_port
->port
;
2485 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2489 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2491 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2492 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2494 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2496 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2497 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2498 case DP_TRAINING_PATTERN_DISABLE
:
2499 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2502 case DP_TRAINING_PATTERN_1
:
2503 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2505 case DP_TRAINING_PATTERN_2
:
2506 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2508 case DP_TRAINING_PATTERN_3
:
2509 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2512 I915_WRITE(DP_TP_CTL(port
), temp
);
2514 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2515 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2517 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2518 case DP_TRAINING_PATTERN_DISABLE
:
2519 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2521 case DP_TRAINING_PATTERN_1
:
2522 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2524 case DP_TRAINING_PATTERN_2
:
2525 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2527 case DP_TRAINING_PATTERN_3
:
2528 DRM_ERROR("DP training pattern 3 not supported\n");
2529 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2534 *DP
&= ~DP_LINK_TRAIN_MASK
;
2536 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2537 case DP_TRAINING_PATTERN_DISABLE
:
2538 *DP
|= DP_LINK_TRAIN_OFF
;
2540 case DP_TRAINING_PATTERN_1
:
2541 *DP
|= DP_LINK_TRAIN_PAT_1
;
2543 case DP_TRAINING_PATTERN_2
:
2544 *DP
|= DP_LINK_TRAIN_PAT_2
;
2546 case DP_TRAINING_PATTERN_3
:
2547 DRM_ERROR("DP training pattern 3 not supported\n");
2548 *DP
|= DP_LINK_TRAIN_PAT_2
;
2553 I915_WRITE(intel_dp
->output_reg
, *DP
);
2554 POSTING_READ(intel_dp
->output_reg
);
2556 buf
[0] = dp_train_pat
;
2557 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2558 DP_TRAINING_PATTERN_DISABLE
) {
2559 /* don't write DP_TRAINING_LANEx_SET on disable */
2562 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2563 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
2564 len
= intel_dp
->lane_count
+ 1;
2567 ret
= intel_dp_aux_native_write(intel_dp
, DP_TRAINING_PATTERN_SET
,
2574 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2575 uint8_t dp_train_pat
)
2577 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
2578 intel_dp_set_signal_levels(intel_dp
, DP
);
2579 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
2583 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2584 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2586 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2587 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 intel_get_adjust_train(intel_dp
, link_status
);
2592 intel_dp_set_signal_levels(intel_dp
, DP
);
2594 I915_WRITE(intel_dp
->output_reg
, *DP
);
2595 POSTING_READ(intel_dp
->output_reg
);
2597 ret
= intel_dp_aux_native_write(intel_dp
, DP_TRAINING_LANE0_SET
,
2598 intel_dp
->train_set
,
2599 intel_dp
->lane_count
);
2601 return ret
== intel_dp
->lane_count
;
2604 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2606 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2607 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2609 enum port port
= intel_dig_port
->port
;
2615 val
= I915_READ(DP_TP_CTL(port
));
2616 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2617 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2618 I915_WRITE(DP_TP_CTL(port
), val
);
2621 * On PORT_A we can have only eDP in SST mode. There the only reason
2622 * we need to set idle transmission mode is to work around a HW issue
2623 * where we enable the pipe while not in idle link-training mode.
2624 * In this case there is requirement to wait for a minimum number of
2625 * idle patterns to be sent.
2630 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2632 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2635 /* Enable corresponding port and start training pattern 1 */
2637 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2639 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2640 struct drm_device
*dev
= encoder
->dev
;
2643 int voltage_tries
, loop_tries
;
2644 uint32_t DP
= intel_dp
->DP
;
2645 uint8_t link_config
[2];
2648 intel_ddi_prepare_link_retrain(encoder
);
2650 /* Write the link configuration data */
2651 link_config
[0] = intel_dp
->link_bw
;
2652 link_config
[1] = intel_dp
->lane_count
;
2653 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2654 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
2655 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
, link_config
, 2);
2658 link_config
[1] = DP_SET_ANSI_8B10B
;
2659 intel_dp_aux_native_write(intel_dp
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
2663 /* clock recovery */
2664 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
2665 DP_TRAINING_PATTERN_1
|
2666 DP_LINK_SCRAMBLING_DISABLE
)) {
2667 DRM_ERROR("failed to enable link training\n");
2675 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2677 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2678 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2679 DRM_ERROR("failed to get link status\n");
2683 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2684 DRM_DEBUG_KMS("clock recovery OK\n");
2688 /* Check to see if we've tried the max voltage */
2689 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2690 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2692 if (i
== intel_dp
->lane_count
) {
2694 if (loop_tries
== 5) {
2695 DRM_ERROR("too many full retries, give up\n");
2698 intel_dp_reset_link_train(intel_dp
, &DP
,
2699 DP_TRAINING_PATTERN_1
|
2700 DP_LINK_SCRAMBLING_DISABLE
);
2705 /* Check to see if we've tried the same voltage 5 times */
2706 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2708 if (voltage_tries
== 5) {
2709 DRM_ERROR("too many voltage retries, give up\n");
2714 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2716 /* Update training set as requested by target */
2717 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2718 DRM_ERROR("failed to update link training\n");
2727 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2729 bool channel_eq
= false;
2730 int tries
, cr_tries
;
2731 uint32_t DP
= intel_dp
->DP
;
2732 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
2734 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2735 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
2736 training_pattern
= DP_TRAINING_PATTERN_3
;
2738 /* channel equalization */
2739 if (!intel_dp_set_link_train(intel_dp
, &DP
,
2741 DP_LINK_SCRAMBLING_DISABLE
)) {
2742 DRM_ERROR("failed to start channel equalization\n");
2750 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2753 DRM_ERROR("failed to train DP, aborting\n");
2757 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2758 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2759 DRM_ERROR("failed to get link status\n");
2763 /* Make sure clock is still ok */
2764 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2765 intel_dp_start_link_train(intel_dp
);
2766 intel_dp_set_link_train(intel_dp
, &DP
,
2768 DP_LINK_SCRAMBLING_DISABLE
);
2773 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2778 /* Try 5 times, then try clock recovery if that fails */
2780 intel_dp_link_down(intel_dp
);
2781 intel_dp_start_link_train(intel_dp
);
2782 intel_dp_set_link_train(intel_dp
, &DP
,
2784 DP_LINK_SCRAMBLING_DISABLE
);
2790 /* Update training set as requested by target */
2791 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2792 DRM_ERROR("failed to update link training\n");
2798 intel_dp_set_idle_link_train(intel_dp
);
2803 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2807 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2809 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2810 DP_TRAINING_PATTERN_DISABLE
);
2814 intel_dp_link_down(struct intel_dp
*intel_dp
)
2816 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2817 enum port port
= intel_dig_port
->port
;
2818 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2820 struct intel_crtc
*intel_crtc
=
2821 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2822 uint32_t DP
= intel_dp
->DP
;
2825 * DDI code has a strict mode set sequence and we should try to respect
2826 * it, otherwise we might hang the machine in many different ways. So we
2827 * really should be disabling the port only on a complete crtc_disable
2828 * sequence. This function is just called under two conditions on DDI
2830 * - Link train failed while doing crtc_enable, and on this case we
2831 * really should respect the mode set sequence and wait for a
2833 * - Someone turned the monitor off and intel_dp_check_link_status
2834 * called us. We don't need to disable the whole port on this case, so
2835 * when someone turns the monitor on again,
2836 * intel_ddi_prepare_link_retrain will take care of redoing the link
2842 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2845 DRM_DEBUG_KMS("\n");
2847 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2848 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2849 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2851 DP
&= ~DP_LINK_TRAIN_MASK
;
2852 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2854 POSTING_READ(intel_dp
->output_reg
);
2856 /* We don't really know why we're doing this */
2857 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2859 if (HAS_PCH_IBX(dev
) &&
2860 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2861 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2863 /* Hardware workaround: leaving our transcoder select
2864 * set to transcoder B while it's off will prevent the
2865 * corresponding HDMI output on transcoder A.
2867 * Combine this with another hardware workaround:
2868 * transcoder select bit can only be cleared while the
2871 DP
&= ~DP_PIPEB_SELECT
;
2872 I915_WRITE(intel_dp
->output_reg
, DP
);
2874 /* Changes to enable or select take place the vblank
2875 * after being written.
2877 if (WARN_ON(crtc
== NULL
)) {
2878 /* We should never try to disable a port without a crtc
2879 * attached. For paranoia keep the code around for a
2881 POSTING_READ(intel_dp
->output_reg
);
2884 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2887 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2888 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2889 POSTING_READ(intel_dp
->output_reg
);
2890 msleep(intel_dp
->panel_power_down_delay
);
2894 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2896 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2897 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2900 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2902 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2903 sizeof(intel_dp
->dpcd
)) == 0)
2904 return false; /* aux transfer failed */
2906 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2907 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2908 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2910 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2911 return false; /* DPCD not present */
2913 /* Check if the panel supports PSR */
2914 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
2915 if (is_edp(intel_dp
)) {
2916 intel_dp_aux_native_read_retry(intel_dp
, DP_PSR_SUPPORT
,
2918 sizeof(intel_dp
->psr_dpcd
));
2919 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
2920 dev_priv
->psr
.sink_support
= true;
2921 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2925 /* Training Pattern 3 support */
2926 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
2927 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
2928 intel_dp
->use_tps3
= true;
2929 DRM_DEBUG_KMS("Displayport TPS3 supported");
2931 intel_dp
->use_tps3
= false;
2933 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2934 DP_DWN_STRM_PORT_PRESENT
))
2935 return true; /* native DP sink */
2937 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2938 return true; /* no per-port downstream info */
2940 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2941 intel_dp
->downstream_ports
,
2942 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2943 return false; /* downstream port status fetch failed */
2949 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2953 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2956 intel_edp_panel_vdd_on(intel_dp
);
2958 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2959 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2960 buf
[0], buf
[1], buf
[2]);
2962 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2963 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2964 buf
[0], buf
[1], buf
[2]);
2966 edp_panel_vdd_off(intel_dp
, false);
2969 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
2971 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2972 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2973 struct intel_crtc
*intel_crtc
=
2974 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2977 if (!intel_dp_aux_native_read(intel_dp
, DP_TEST_SINK_MISC
, buf
, 1))
2980 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
2983 if (!intel_dp_aux_native_write_1(intel_dp
, DP_TEST_SINK
,
2984 DP_TEST_SINK_START
))
2987 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2988 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2989 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2991 if (!intel_dp_aux_native_read(intel_dp
, DP_TEST_CRC_R_CR
, crc
, 6))
2994 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_SINK
, 0);
2999 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3003 ret
= intel_dp_aux_native_read_retry(intel_dp
,
3004 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3005 sink_irq_vector
, 1);
3013 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3015 /* NAK by default */
3016 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3020 * According to DP spec
3023 * 2. Configure link according to Receiver Capabilities
3024 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3025 * 4. Check link status on receipt of hot-plug interrupt
3029 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3031 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3033 u8 link_status
[DP_LINK_STATUS_SIZE
];
3035 if (!intel_encoder
->connectors_active
)
3038 if (WARN_ON(!intel_encoder
->base
.crtc
))
3041 /* Try to read receiver status if the link appears to be up */
3042 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3046 /* Now read the DPCD to see if it's actually running */
3047 if (!intel_dp_get_dpcd(intel_dp
)) {
3051 /* Try to read the source of the interrupt */
3052 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3053 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3054 /* Clear interrupt source */
3055 intel_dp_aux_native_write_1(intel_dp
,
3056 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3059 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3060 intel_dp_handle_test_request(intel_dp
);
3061 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3062 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3065 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3066 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3067 drm_get_encoder_name(&intel_encoder
->base
));
3068 intel_dp_start_link_train(intel_dp
);
3069 intel_dp_complete_link_train(intel_dp
);
3070 intel_dp_stop_link_train(intel_dp
);
3074 /* XXX this is probably wrong for multiple downstream ports */
3075 static enum drm_connector_status
3076 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3078 uint8_t *dpcd
= intel_dp
->dpcd
;
3081 if (!intel_dp_get_dpcd(intel_dp
))
3082 return connector_status_disconnected
;
3084 /* if there's no downstream port, we're done */
3085 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3086 return connector_status_connected
;
3088 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3089 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3090 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3092 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
3094 return connector_status_unknown
;
3095 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3096 : connector_status_disconnected
;
3099 /* If no HPD, poke DDC gently */
3100 if (drm_probe_ddc(&intel_dp
->adapter
))
3101 return connector_status_connected
;
3103 /* Well we tried, say unknown for unreliable port types */
3104 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3105 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3106 if (type
== DP_DS_PORT_TYPE_VGA
||
3107 type
== DP_DS_PORT_TYPE_NON_EDID
)
3108 return connector_status_unknown
;
3110 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3111 DP_DWN_STRM_PORT_TYPE_MASK
;
3112 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3113 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3114 return connector_status_unknown
;
3117 /* Anything else is out of spec, warn and ignore */
3118 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3119 return connector_status_disconnected
;
3122 static enum drm_connector_status
3123 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3125 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3127 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3128 enum drm_connector_status status
;
3130 /* Can't disconnect eDP, but you can close the lid... */
3131 if (is_edp(intel_dp
)) {
3132 status
= intel_panel_detect(dev
);
3133 if (status
== connector_status_unknown
)
3134 status
= connector_status_connected
;
3138 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3139 return connector_status_disconnected
;
3141 return intel_dp_detect_dpcd(intel_dp
);
3144 static enum drm_connector_status
3145 g4x_dp_detect(struct intel_dp
*intel_dp
)
3147 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3149 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3152 /* Can't disconnect eDP, but you can close the lid... */
3153 if (is_edp(intel_dp
)) {
3154 enum drm_connector_status status
;
3156 status
= intel_panel_detect(dev
);
3157 if (status
== connector_status_unknown
)
3158 status
= connector_status_connected
;
3162 if (IS_VALLEYVIEW(dev
)) {
3163 switch (intel_dig_port
->port
) {
3165 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3168 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3171 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3174 return connector_status_unknown
;
3177 switch (intel_dig_port
->port
) {
3179 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3182 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3185 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3188 return connector_status_unknown
;
3192 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3193 return connector_status_disconnected
;
3195 return intel_dp_detect_dpcd(intel_dp
);
3198 static struct edid
*
3199 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3201 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3203 /* use cached edid if we have one */
3204 if (intel_connector
->edid
) {
3206 if (IS_ERR(intel_connector
->edid
))
3209 return drm_edid_duplicate(intel_connector
->edid
);
3212 return drm_get_edid(connector
, adapter
);
3216 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3218 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3220 /* use cached edid if we have one */
3221 if (intel_connector
->edid
) {
3223 if (IS_ERR(intel_connector
->edid
))
3226 return intel_connector_update_modes(connector
,
3227 intel_connector
->edid
);
3230 return intel_ddc_get_modes(connector
, adapter
);
3233 static enum drm_connector_status
3234 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3236 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3237 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3238 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3239 struct drm_device
*dev
= connector
->dev
;
3240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 enum drm_connector_status status
;
3242 enum intel_display_power_domain power_domain
;
3243 struct edid
*edid
= NULL
;
3245 intel_runtime_pm_get(dev_priv
);
3247 power_domain
= intel_display_port_power_domain(intel_encoder
);
3248 intel_display_power_get(dev_priv
, power_domain
);
3250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3251 connector
->base
.id
, drm_get_connector_name(connector
));
3253 intel_dp
->has_audio
= false;
3255 if (HAS_PCH_SPLIT(dev
))
3256 status
= ironlake_dp_detect(intel_dp
);
3258 status
= g4x_dp_detect(intel_dp
);
3260 if (status
!= connector_status_connected
)
3263 intel_dp_probe_oui(intel_dp
);
3265 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3266 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3268 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
3270 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3275 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3276 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3277 status
= connector_status_connected
;
3280 intel_display_power_put(dev_priv
, power_domain
);
3282 intel_runtime_pm_put(dev_priv
);
3287 static int intel_dp_get_modes(struct drm_connector
*connector
)
3289 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3290 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3291 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3292 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3293 struct drm_device
*dev
= connector
->dev
;
3294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3295 enum intel_display_power_domain power_domain
;
3298 /* We should parse the EDID data and find out if it has an audio sink
3301 power_domain
= intel_display_port_power_domain(intel_encoder
);
3302 intel_display_power_get(dev_priv
, power_domain
);
3304 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
3305 intel_display_power_put(dev_priv
, power_domain
);
3309 /* if eDP has no EDID, fall back to fixed mode */
3310 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3311 struct drm_display_mode
*mode
;
3312 mode
= drm_mode_duplicate(dev
,
3313 intel_connector
->panel
.fixed_mode
);
3315 drm_mode_probed_add(connector
, mode
);
3323 intel_dp_detect_audio(struct drm_connector
*connector
)
3325 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3326 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3327 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3328 struct drm_device
*dev
= connector
->dev
;
3329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3330 enum intel_display_power_domain power_domain
;
3332 bool has_audio
= false;
3334 power_domain
= intel_display_port_power_domain(intel_encoder
);
3335 intel_display_power_get(dev_priv
, power_domain
);
3337 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
3339 has_audio
= drm_detect_monitor_audio(edid
);
3343 intel_display_power_put(dev_priv
, power_domain
);
3349 intel_dp_set_property(struct drm_connector
*connector
,
3350 struct drm_property
*property
,
3353 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3354 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3355 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3356 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3359 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3363 if (property
== dev_priv
->force_audio_property
) {
3367 if (i
== intel_dp
->force_audio
)
3370 intel_dp
->force_audio
= i
;
3372 if (i
== HDMI_AUDIO_AUTO
)
3373 has_audio
= intel_dp_detect_audio(connector
);
3375 has_audio
= (i
== HDMI_AUDIO_ON
);
3377 if (has_audio
== intel_dp
->has_audio
)
3380 intel_dp
->has_audio
= has_audio
;
3384 if (property
== dev_priv
->broadcast_rgb_property
) {
3385 bool old_auto
= intel_dp
->color_range_auto
;
3386 uint32_t old_range
= intel_dp
->color_range
;
3389 case INTEL_BROADCAST_RGB_AUTO
:
3390 intel_dp
->color_range_auto
= true;
3392 case INTEL_BROADCAST_RGB_FULL
:
3393 intel_dp
->color_range_auto
= false;
3394 intel_dp
->color_range
= 0;
3396 case INTEL_BROADCAST_RGB_LIMITED
:
3397 intel_dp
->color_range_auto
= false;
3398 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3404 if (old_auto
== intel_dp
->color_range_auto
&&
3405 old_range
== intel_dp
->color_range
)
3411 if (is_edp(intel_dp
) &&
3412 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3413 if (val
== DRM_MODE_SCALE_NONE
) {
3414 DRM_DEBUG_KMS("no scaling not supported\n");
3418 if (intel_connector
->panel
.fitting_mode
== val
) {
3419 /* the eDP scaling property is not changed */
3422 intel_connector
->panel
.fitting_mode
= val
;
3430 if (intel_encoder
->base
.crtc
)
3431 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3437 intel_dp_connector_destroy(struct drm_connector
*connector
)
3439 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3441 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3442 kfree(intel_connector
->edid
);
3444 /* Can't call is_edp() since the encoder may have been destroyed
3446 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3447 intel_panel_fini(&intel_connector
->panel
);
3449 drm_connector_cleanup(connector
);
3453 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3455 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3456 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3457 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3459 i2c_del_adapter(&intel_dp
->adapter
);
3460 drm_encoder_cleanup(encoder
);
3461 if (is_edp(intel_dp
)) {
3462 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3463 mutex_lock(&dev
->mode_config
.mutex
);
3464 edp_panel_vdd_off_sync(intel_dp
);
3465 mutex_unlock(&dev
->mode_config
.mutex
);
3467 kfree(intel_dig_port
);
3470 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3471 .dpms
= intel_connector_dpms
,
3472 .detect
= intel_dp_detect
,
3473 .fill_modes
= drm_helper_probe_single_connector_modes
,
3474 .set_property
= intel_dp_set_property
,
3475 .destroy
= intel_dp_connector_destroy
,
3478 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3479 .get_modes
= intel_dp_get_modes
,
3480 .mode_valid
= intel_dp_mode_valid
,
3481 .best_encoder
= intel_best_encoder
,
3484 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3485 .destroy
= intel_dp_encoder_destroy
,
3489 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3491 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3493 intel_dp_check_link_status(intel_dp
);
3496 /* Return which DP Port should be selected for Transcoder DP control */
3498 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3500 struct drm_device
*dev
= crtc
->dev
;
3501 struct intel_encoder
*intel_encoder
;
3502 struct intel_dp
*intel_dp
;
3504 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3505 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3507 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3508 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3509 return intel_dp
->output_reg
;
3515 /* check the VBT to see whether the eDP is on DP-D port */
3516 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
3518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3519 union child_device_config
*p_child
;
3521 static const short port_mapping
[] = {
3522 [PORT_B
] = PORT_IDPB
,
3523 [PORT_C
] = PORT_IDPC
,
3524 [PORT_D
] = PORT_IDPD
,
3530 if (!dev_priv
->vbt
.child_dev_num
)
3533 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3534 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3536 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
3537 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
3538 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
3545 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3547 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3549 intel_attach_force_audio_property(connector
);
3550 intel_attach_broadcast_rgb_property(connector
);
3551 intel_dp
->color_range_auto
= true;
3553 if (is_edp(intel_dp
)) {
3554 drm_mode_create_scaling_mode_property(connector
->dev
);
3555 drm_object_attach_property(
3557 connector
->dev
->mode_config
.scaling_mode_property
,
3558 DRM_MODE_SCALE_ASPECT
);
3559 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3563 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
3565 intel_dp
->last_power_cycle
= jiffies
;
3566 intel_dp
->last_power_on
= jiffies
;
3567 intel_dp
->last_backlight_off
= jiffies
;
3571 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3572 struct intel_dp
*intel_dp
,
3573 struct edp_power_seq
*out
)
3575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3576 struct edp_power_seq cur
, vbt
, spec
, final
;
3577 u32 pp_on
, pp_off
, pp_div
, pp
;
3578 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3580 if (HAS_PCH_SPLIT(dev
)) {
3581 pp_ctrl_reg
= PCH_PP_CONTROL
;
3582 pp_on_reg
= PCH_PP_ON_DELAYS
;
3583 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3584 pp_div_reg
= PCH_PP_DIVISOR
;
3586 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3588 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3589 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3590 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3591 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3594 /* Workaround: Need to write PP_CONTROL with the unlock key as
3595 * the very first thing. */
3596 pp
= ironlake_get_pp_control(intel_dp
);
3597 I915_WRITE(pp_ctrl_reg
, pp
);
3599 pp_on
= I915_READ(pp_on_reg
);
3600 pp_off
= I915_READ(pp_off_reg
);
3601 pp_div
= I915_READ(pp_div_reg
);
3603 /* Pull timing values out of registers */
3604 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3605 PANEL_POWER_UP_DELAY_SHIFT
;
3607 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3608 PANEL_LIGHT_ON_DELAY_SHIFT
;
3610 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3611 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3613 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3614 PANEL_POWER_DOWN_DELAY_SHIFT
;
3616 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3617 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3619 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3620 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3622 vbt
= dev_priv
->vbt
.edp_pps
;
3624 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3625 * our hw here, which are all in 100usec. */
3626 spec
.t1_t3
= 210 * 10;
3627 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3628 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3629 spec
.t10
= 500 * 10;
3630 /* This one is special and actually in units of 100ms, but zero
3631 * based in the hw (so we need to add 100 ms). But the sw vbt
3632 * table multiplies it with 1000 to make it in units of 100usec,
3634 spec
.t11_t12
= (510 + 100) * 10;
3636 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3637 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3639 /* Use the max of the register settings and vbt. If both are
3640 * unset, fall back to the spec limits. */
3641 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3643 max(cur.field, vbt.field))
3644 assign_final(t1_t3
);
3648 assign_final(t11_t12
);
3651 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3652 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3653 intel_dp
->backlight_on_delay
= get_delay(t8
);
3654 intel_dp
->backlight_off_delay
= get_delay(t9
);
3655 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3656 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3659 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3660 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3661 intel_dp
->panel_power_cycle_delay
);
3663 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3664 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3671 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3672 struct intel_dp
*intel_dp
,
3673 struct edp_power_seq
*seq
)
3675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3676 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3677 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3678 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3680 if (HAS_PCH_SPLIT(dev
)) {
3681 pp_on_reg
= PCH_PP_ON_DELAYS
;
3682 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3683 pp_div_reg
= PCH_PP_DIVISOR
;
3685 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3687 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3688 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3689 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3693 * And finally store the new values in the power sequencer. The
3694 * backlight delays are set to 1 because we do manual waits on them. For
3695 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3696 * we'll end up waiting for the backlight off delay twice: once when we
3697 * do the manual sleep, and once when we disable the panel and wait for
3698 * the PP_STATUS bit to become zero.
3700 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3701 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
3702 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3703 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3704 /* Compute the divisor for the pp clock, simply match the Bspec
3706 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3707 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3708 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3710 /* Haswell doesn't have any port selection bits for the panel
3711 * power sequencer any more. */
3712 if (IS_VALLEYVIEW(dev
)) {
3713 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3714 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3716 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3717 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3718 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
3719 port_sel
= PANEL_PORT_SELECT_DPA
;
3721 port_sel
= PANEL_PORT_SELECT_DPD
;
3726 I915_WRITE(pp_on_reg
, pp_on
);
3727 I915_WRITE(pp_off_reg
, pp_off
);
3728 I915_WRITE(pp_div_reg
, pp_div
);
3730 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3731 I915_READ(pp_on_reg
),
3732 I915_READ(pp_off_reg
),
3733 I915_READ(pp_div_reg
));
3736 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
3737 struct intel_connector
*intel_connector
,
3738 struct edp_power_seq
*power_seq
)
3740 struct drm_connector
*connector
= &intel_connector
->base
;
3741 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3742 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3744 struct drm_display_mode
*fixed_mode
= NULL
;
3746 struct drm_display_mode
*scan
;
3749 if (!is_edp(intel_dp
))
3752 /* Cache DPCD and EDID for edp. */
3753 intel_edp_panel_vdd_on(intel_dp
);
3754 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
3755 edp_panel_vdd_off(intel_dp
, false);
3758 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3759 dev_priv
->no_aux_handshake
=
3760 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3761 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3763 /* if this fails, presume the device is a ghost */
3764 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3768 /* We now know it's not a ghost, init power sequence regs. */
3769 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
3771 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
3773 if (drm_add_edid_modes(connector
, edid
)) {
3774 drm_mode_connector_update_edid_property(connector
,
3776 drm_edid_to_eld(connector
, edid
);
3779 edid
= ERR_PTR(-EINVAL
);
3782 edid
= ERR_PTR(-ENOENT
);
3784 intel_connector
->edid
= edid
;
3786 /* prefer fixed mode from EDID if available */
3787 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
3788 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
3789 fixed_mode
= drm_mode_duplicate(dev
, scan
);
3794 /* fallback to VBT if available for eDP */
3795 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
3796 fixed_mode
= drm_mode_duplicate(dev
,
3797 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
3799 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
3802 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
3803 intel_panel_setup_backlight(connector
);
3809 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
3810 struct intel_connector
*intel_connector
)
3812 struct drm_connector
*connector
= &intel_connector
->base
;
3813 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3814 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3815 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3817 enum port port
= intel_dig_port
->port
;
3818 struct edp_power_seq power_seq
= { 0 };
3819 const char *name
= NULL
;
3822 /* intel_dp vfuncs */
3823 if (IS_VALLEYVIEW(dev
))
3824 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
3825 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3826 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
3827 else if (HAS_PCH_SPLIT(dev
))
3828 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
3830 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
3832 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
3834 /* Preserve the current hw state. */
3835 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
3836 intel_dp
->attached_connector
= intel_connector
;
3838 if (intel_dp_is_edp(dev
, port
))
3839 type
= DRM_MODE_CONNECTOR_eDP
;
3841 type
= DRM_MODE_CONNECTOR_DisplayPort
;
3844 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3845 * for DP the encoder type can be set by the caller to
3846 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3848 if (type
== DRM_MODE_CONNECTOR_eDP
)
3849 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
3851 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3852 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
3855 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
3856 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
3858 connector
->interlace_allowed
= true;
3859 connector
->doublescan_allowed
= 0;
3861 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
3862 edp_panel_vdd_work
);
3864 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3865 drm_sysfs_connector_add(connector
);
3868 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3870 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3871 intel_connector
->unregister
= intel_dp_connector_unregister
;
3873 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
3875 switch (intel_dig_port
->port
) {
3877 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
3880 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
3883 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
3886 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
3893 /* Set up the DDC bus. */
3896 intel_encoder
->hpd_pin
= HPD_PORT_A
;
3900 intel_encoder
->hpd_pin
= HPD_PORT_B
;
3904 intel_encoder
->hpd_pin
= HPD_PORT_C
;
3908 intel_encoder
->hpd_pin
= HPD_PORT_D
;
3915 if (is_edp(intel_dp
)) {
3916 intel_dp_init_panel_power_timestamps(intel_dp
);
3917 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
3920 error
= intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
3921 WARN(error
, "intel_dp_i2c_init failed with error %d for port %c\n",
3922 error
, port_name(port
));
3924 intel_dp
->psr_setup_done
= false;
3926 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
3927 i2c_del_adapter(&intel_dp
->adapter
);
3928 if (is_edp(intel_dp
)) {
3929 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3930 mutex_lock(&dev
->mode_config
.mutex
);
3931 edp_panel_vdd_off_sync(intel_dp
);
3932 mutex_unlock(&dev
->mode_config
.mutex
);
3934 drm_sysfs_connector_remove(connector
);
3935 drm_connector_cleanup(connector
);
3939 intel_dp_add_properties(intel_dp
, connector
);
3941 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3942 * 0xd. Failure to do so will result in spurious interrupts being
3943 * generated on the port when a cable is not attached.
3945 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
3946 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3947 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3954 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
3956 struct intel_digital_port
*intel_dig_port
;
3957 struct intel_encoder
*intel_encoder
;
3958 struct drm_encoder
*encoder
;
3959 struct intel_connector
*intel_connector
;
3961 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3962 if (!intel_dig_port
)
3965 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
3966 if (!intel_connector
) {
3967 kfree(intel_dig_port
);
3971 intel_encoder
= &intel_dig_port
->base
;
3972 encoder
= &intel_encoder
->base
;
3974 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
3975 DRM_MODE_ENCODER_TMDS
);
3977 intel_encoder
->compute_config
= intel_dp_compute_config
;
3978 intel_encoder
->mode_set
= intel_dp_mode_set
;
3979 intel_encoder
->disable
= intel_disable_dp
;
3980 intel_encoder
->post_disable
= intel_post_disable_dp
;
3981 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
3982 intel_encoder
->get_config
= intel_dp_get_config
;
3983 if (IS_VALLEYVIEW(dev
)) {
3984 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
3985 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
3986 intel_encoder
->enable
= vlv_enable_dp
;
3988 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
3989 intel_encoder
->enable
= g4x_enable_dp
;
3992 intel_dig_port
->port
= port
;
3993 intel_dig_port
->dp
.output_reg
= output_reg
;
3995 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3996 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3997 intel_encoder
->cloneable
= 0;
3998 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4000 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4001 drm_encoder_cleanup(encoder
);
4002 kfree(intel_dig_port
);
4003 kfree(intel_connector
);