2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_dp_helper.h>
38 #include <drm/drm_edid.h>
39 #include <drm/drm_hdcp.h>
40 #include <drm/drm_probe_helper.h>
41 #include "intel_drv.h"
42 #include <drm/i915_drm.h>
45 #define DP_DPRX_ESI_LEN 14
47 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
48 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
49 #define DP_DSC_MIN_SUPPORTED_BPC 8
50 #define DP_DSC_MAX_SUPPORTED_BPC 10
52 /* DP DSC throughput values used for slice count calculations KPixels/s */
53 #define DP_DSC_PEAK_PIXEL_RATE 2720000
54 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
55 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
57 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
58 #define DP_DSC_FEC_OVERHEAD_FACTOR 976
60 /* Compliance test status bits */
61 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
62 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
63 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
64 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
71 static const struct dp_link_dpll g4x_dpll
[] = {
73 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
75 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
78 static const struct dp_link_dpll pch_dpll
[] = {
80 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
82 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
85 static const struct dp_link_dpll vlv_dpll
[] = {
87 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
89 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
93 * CHV supports eDP 1.4 that have more link rates.
94 * Below only provides the fixed rate but exclude variable rate.
96 static const struct dp_link_dpll chv_dpll
[] = {
98 * CHV requires to program fractional division for m2.
99 * m2 is stored in fixed point format using formula below
100 * (m2_int << 22) | m2_fraction
102 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
103 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
104 { 270000, /* m2_int = 27, m2_fraction = 0 */
105 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
108 /* Constants for DP DSC configurations */
109 static const u8 valid_dsc_bpp
[] = {6, 8, 10, 12, 15};
111 /* With Single pipe configuration, HW is capable of supporting maximum
112 * of 4 slices per line.
114 static const u8 valid_dsc_slicecount
[] = {1, 2, 4};
117 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
118 * @intel_dp: DP struct
120 * If a CPU or PCH DP output is attached to an eDP panel, this function
121 * will return true, and false otherwise.
123 bool intel_dp_is_edp(struct intel_dp
*intel_dp
)
125 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
127 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
130 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
132 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
135 static void intel_dp_link_down(struct intel_encoder
*encoder
,
136 const struct intel_crtc_state
*old_crtc_state
);
137 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
138 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
139 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
140 const struct intel_crtc_state
*crtc_state
);
141 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
143 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
145 /* update sink rates from dpcd */
146 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
148 static const int dp_rates
[] = {
149 162000, 270000, 540000, 810000
153 max_rate
= drm_dp_bw_code_to_link_rate(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
155 for (i
= 0; i
< ARRAY_SIZE(dp_rates
); i
++) {
156 if (dp_rates
[i
] > max_rate
)
158 intel_dp
->sink_rates
[i
] = dp_rates
[i
];
161 intel_dp
->num_sink_rates
= i
;
164 /* Get length of rates array potentially limited by max_rate. */
165 static int intel_dp_rate_limit_len(const int *rates
, int len
, int max_rate
)
169 /* Limit results by potentially reduced max rate */
170 for (i
= 0; i
< len
; i
++) {
171 if (rates
[len
- i
- 1] <= max_rate
)
178 /* Get length of common rates array potentially limited by max_rate. */
179 static int intel_dp_common_len_rate_limit(const struct intel_dp
*intel_dp
,
182 return intel_dp_rate_limit_len(intel_dp
->common_rates
,
183 intel_dp
->num_common_rates
, max_rate
);
186 /* Theoretical max between source and sink */
187 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
189 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
192 static int intel_dp_get_fia_supported_lane_count(struct intel_dp
*intel_dp
)
194 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
195 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
196 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, dig_port
->base
.port
);
199 if (tc_port
== PORT_TC_NONE
|| dig_port
->tc_type
!= TC_PORT_TYPEC
)
202 lane_info
= (I915_READ(PORT_TX_DFLEXDPSP
) &
203 DP_LANE_ASSIGNMENT_MASK(tc_port
)) >>
204 DP_LANE_ASSIGNMENT_SHIFT(tc_port
);
208 MISSING_CASE(lane_info
);
222 /* Theoretical max between source and sink */
223 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
225 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
226 int source_max
= intel_dig_port
->max_lanes
;
227 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
228 int fia_max
= intel_dp_get_fia_supported_lane_count(intel_dp
);
230 return min3(source_max
, sink_max
, fia_max
);
233 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
235 return intel_dp
->max_link_lane_count
;
239 intel_dp_link_required(int pixel_clock
, int bpp
)
241 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
242 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
246 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
248 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
249 * link rate that is generally expressed in Gbps. Since, 8 bits of data
250 * is transmitted every LS_Clk per lane, there is no need to account for
251 * the channel encoding that is done in the PHY layer here.
254 return max_link_clock
* max_lanes
;
258 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
260 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
261 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
262 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
263 int max_dotclk
= dev_priv
->max_dotclk_freq
;
266 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
268 if (type
!= DP_DS_PORT_TYPE_VGA
)
271 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
272 intel_dp
->downstream_ports
);
274 if (ds_max_dotclk
!= 0)
275 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
280 static int cnl_max_source_rate(struct intel_dp
*intel_dp
)
282 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
283 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
284 enum port port
= dig_port
->base
.port
;
286 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
288 /* Low voltage SKUs are limited to max of 5.4G */
289 if (voltage
== VOLTAGE_INFO_0_85V
)
292 /* For this SKU 8.1G is supported in all ports */
293 if (IS_CNL_WITH_PORT_F(dev_priv
))
296 /* For other SKUs, max rate on ports A and D is 5.4G */
297 if (port
== PORT_A
|| port
== PORT_D
)
303 static int icl_max_source_rate(struct intel_dp
*intel_dp
)
305 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
306 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
307 enum port port
= dig_port
->base
.port
;
309 if (intel_port_is_combophy(dev_priv
, port
) &&
310 !intel_dp_is_edp(intel_dp
))
317 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
319 /* The values must be in increasing order */
320 static const int cnl_rates
[] = {
321 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
323 static const int bxt_rates
[] = {
324 162000, 216000, 243000, 270000, 324000, 432000, 540000
326 static const int skl_rates
[] = {
327 162000, 216000, 270000, 324000, 432000, 540000
329 static const int hsw_rates
[] = {
330 162000, 270000, 540000
332 static const int g4x_rates
[] = {
335 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
337 const struct ddi_vbt_port_info
*info
=
338 &dev_priv
->vbt
.ddi_port_info
[dig_port
->base
.port
];
339 const int *source_rates
;
340 int size
, max_rate
= 0, vbt_max_rate
= info
->dp_max_link_rate
;
342 /* This should only be done once */
343 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
345 if (INTEL_GEN(dev_priv
) >= 10) {
346 source_rates
= cnl_rates
;
347 size
= ARRAY_SIZE(cnl_rates
);
348 if (IS_GEN(dev_priv
, 10))
349 max_rate
= cnl_max_source_rate(intel_dp
);
351 max_rate
= icl_max_source_rate(intel_dp
);
352 } else if (IS_GEN9_LP(dev_priv
)) {
353 source_rates
= bxt_rates
;
354 size
= ARRAY_SIZE(bxt_rates
);
355 } else if (IS_GEN9_BC(dev_priv
)) {
356 source_rates
= skl_rates
;
357 size
= ARRAY_SIZE(skl_rates
);
358 } else if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
359 IS_BROADWELL(dev_priv
)) {
360 source_rates
= hsw_rates
;
361 size
= ARRAY_SIZE(hsw_rates
);
363 source_rates
= g4x_rates
;
364 size
= ARRAY_SIZE(g4x_rates
);
367 if (max_rate
&& vbt_max_rate
)
368 max_rate
= min(max_rate
, vbt_max_rate
);
369 else if (vbt_max_rate
)
370 max_rate
= vbt_max_rate
;
373 size
= intel_dp_rate_limit_len(source_rates
, size
, max_rate
);
375 intel_dp
->source_rates
= source_rates
;
376 intel_dp
->num_source_rates
= size
;
379 static int intersect_rates(const int *source_rates
, int source_len
,
380 const int *sink_rates
, int sink_len
,
383 int i
= 0, j
= 0, k
= 0;
385 while (i
< source_len
&& j
< sink_len
) {
386 if (source_rates
[i
] == sink_rates
[j
]) {
387 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
389 common_rates
[k
] = source_rates
[i
];
393 } else if (source_rates
[i
] < sink_rates
[j
]) {
402 /* return index of rate in rates array, or -1 if not found */
403 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
407 for (i
= 0; i
< len
; i
++)
408 if (rate
== rates
[i
])
414 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
416 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
418 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
419 intel_dp
->num_source_rates
,
420 intel_dp
->sink_rates
,
421 intel_dp
->num_sink_rates
,
422 intel_dp
->common_rates
);
424 /* Paranoia, there should always be something in common. */
425 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
426 intel_dp
->common_rates
[0] = 162000;
427 intel_dp
->num_common_rates
= 1;
431 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
, int link_rate
,
435 * FIXME: we need to synchronize the current link parameters with
436 * hardware readout. Currently fast link training doesn't work on
439 if (link_rate
== 0 ||
440 link_rate
> intel_dp
->max_link_rate
)
443 if (lane_count
== 0 ||
444 lane_count
> intel_dp_max_lane_count(intel_dp
))
450 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp
*intel_dp
,
454 const struct drm_display_mode
*fixed_mode
=
455 intel_dp
->attached_connector
->panel
.fixed_mode
;
456 int mode_rate
, max_rate
;
458 mode_rate
= intel_dp_link_required(fixed_mode
->clock
, 18);
459 max_rate
= intel_dp_max_data_rate(link_rate
, lane_count
);
460 if (mode_rate
> max_rate
)
466 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
467 int link_rate
, u8 lane_count
)
471 index
= intel_dp_rate_index(intel_dp
->common_rates
,
472 intel_dp
->num_common_rates
,
475 if (intel_dp_is_edp(intel_dp
) &&
476 !intel_dp_can_link_train_fallback_for_edp(intel_dp
,
477 intel_dp
->common_rates
[index
- 1],
479 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
482 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
483 intel_dp
->max_link_lane_count
= lane_count
;
484 } else if (lane_count
> 1) {
485 if (intel_dp_is_edp(intel_dp
) &&
486 !intel_dp_can_link_train_fallback_for_edp(intel_dp
,
487 intel_dp_max_common_rate(intel_dp
),
489 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
492 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
493 intel_dp
->max_link_lane_count
= lane_count
>> 1;
495 DRM_ERROR("Link Training Unsuccessful\n");
502 static enum drm_mode_status
503 intel_dp_mode_valid(struct drm_connector
*connector
,
504 struct drm_display_mode
*mode
)
506 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
507 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
508 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
509 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
510 int target_clock
= mode
->clock
;
511 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
513 u16 dsc_max_output_bpp
= 0;
514 u8 dsc_slice_count
= 0;
516 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
517 return MODE_NO_DBLESCAN
;
519 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
521 if (intel_dp_is_edp(intel_dp
) && fixed_mode
) {
522 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
525 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
528 target_clock
= fixed_mode
->clock
;
531 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
532 max_lanes
= intel_dp_max_lane_count(intel_dp
);
534 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
535 mode_rate
= intel_dp_link_required(target_clock
, 18);
538 * Output bpp is stored in 6.4 format so right shift by 4 to get the
539 * integer value since we support only integer values of bpp.
541 if ((INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) &&
542 drm_dp_sink_supports_dsc(intel_dp
->dsc_dpcd
)) {
543 if (intel_dp_is_edp(intel_dp
)) {
545 drm_edp_dsc_sink_output_bpp(intel_dp
->dsc_dpcd
) >> 4;
547 drm_dp_dsc_sink_max_slice_count(intel_dp
->dsc_dpcd
,
549 } else if (drm_dp_sink_supports_fec(intel_dp
->fec_capable
)) {
551 intel_dp_dsc_get_output_bpp(max_link_clock
,
554 mode
->hdisplay
) >> 4;
556 intel_dp_dsc_get_slice_count(intel_dp
,
562 if ((mode_rate
> max_rate
&& !(dsc_max_output_bpp
&& dsc_slice_count
)) ||
563 target_clock
> max_dotclk
)
564 return MODE_CLOCK_HIGH
;
566 if (mode
->clock
< 10000)
567 return MODE_CLOCK_LOW
;
569 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
570 return MODE_H_ILLEGAL
;
575 u32
intel_dp_pack_aux(const u8
*src
, int src_bytes
)
582 for (i
= 0; i
< src_bytes
; i
++)
583 v
|= ((u32
)src
[i
]) << ((3 - i
) * 8);
587 static void intel_dp_unpack_aux(u32 src
, u8
*dst
, int dst_bytes
)
592 for (i
= 0; i
< dst_bytes
; i
++)
593 dst
[i
] = src
>> ((3-i
) * 8);
597 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
599 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
600 bool force_disable_vdd
);
602 intel_dp_pps_init(struct intel_dp
*intel_dp
);
604 static intel_wakeref_t
605 pps_lock(struct intel_dp
*intel_dp
)
607 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
608 intel_wakeref_t wakeref
;
611 * See intel_power_sequencer_reset() why we need
612 * a power domain reference here.
614 wakeref
= intel_display_power_get(dev_priv
,
615 intel_aux_power_domain(dp_to_dig_port(intel_dp
)));
617 mutex_lock(&dev_priv
->pps_mutex
);
622 static intel_wakeref_t
623 pps_unlock(struct intel_dp
*intel_dp
, intel_wakeref_t wakeref
)
625 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
627 mutex_unlock(&dev_priv
->pps_mutex
);
628 intel_display_power_put(dev_priv
,
629 intel_aux_power_domain(dp_to_dig_port(intel_dp
)),
634 #define with_pps_lock(dp, wf) \
635 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
638 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
640 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
641 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
642 enum pipe pipe
= intel_dp
->pps_pipe
;
643 bool pll_enabled
, release_cl_override
= false;
644 enum dpio_phy phy
= DPIO_PHY(pipe
);
645 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
648 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
649 "skipping pipe %c power sequencer kick due to port %c being active\n",
650 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
)))
653 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
654 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
656 /* Preserve the BIOS-computed detected bit. This is
657 * supposed to be read-only.
659 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
660 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
661 DP
|= DP_PORT_WIDTH(1);
662 DP
|= DP_LINK_TRAIN_PAT_1
;
664 if (IS_CHERRYVIEW(dev_priv
))
665 DP
|= DP_PIPE_SEL_CHV(pipe
);
667 DP
|= DP_PIPE_SEL(pipe
);
669 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
672 * The DPLL for the pipe must be enabled for this to work.
673 * So enable temporarily it if it's not already enabled.
676 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
677 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
679 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
680 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
681 DRM_ERROR("Failed to force on pll for pipe %c!\n",
688 * Similar magic as in intel_dp_enable_port().
689 * We _must_ do this port enable + disable trick
690 * to make this power sequencer lock onto the port.
691 * Otherwise even VDD force bit won't work.
693 I915_WRITE(intel_dp
->output_reg
, DP
);
694 POSTING_READ(intel_dp
->output_reg
);
696 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
697 POSTING_READ(intel_dp
->output_reg
);
699 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
700 POSTING_READ(intel_dp
->output_reg
);
703 vlv_force_pll_off(dev_priv
, pipe
);
705 if (release_cl_override
)
706 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
710 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
712 struct intel_encoder
*encoder
;
713 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
716 * We don't have power sequencer currently.
717 * Pick one that's not used by other ports.
719 for_each_intel_dp(&dev_priv
->drm
, encoder
) {
720 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
722 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
723 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
724 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
726 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
727 pipes
&= ~(1 << intel_dp
->pps_pipe
);
729 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
731 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
732 pipes
&= ~(1 << intel_dp
->active_pipe
);
739 return ffs(pipes
) - 1;
743 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
745 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
746 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
749 lockdep_assert_held(&dev_priv
->pps_mutex
);
751 /* We should never land here with regular DP ports */
752 WARN_ON(!intel_dp_is_edp(intel_dp
));
754 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
755 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
757 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
758 return intel_dp
->pps_pipe
;
760 pipe
= vlv_find_free_pps(dev_priv
);
763 * Didn't find one. This should not happen since there
764 * are two power sequencers and up to two eDP ports.
766 if (WARN_ON(pipe
== INVALID_PIPE
))
769 vlv_steal_power_sequencer(dev_priv
, pipe
);
770 intel_dp
->pps_pipe
= pipe
;
772 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
773 pipe_name(intel_dp
->pps_pipe
),
774 port_name(intel_dig_port
->base
.port
));
776 /* init power sequencer on this pipe and port */
777 intel_dp_init_panel_power_sequencer(intel_dp
);
778 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
781 * Even vdd force doesn't work until we've made
782 * the power sequencer lock in on the port.
784 vlv_power_sequencer_kick(intel_dp
);
786 return intel_dp
->pps_pipe
;
790 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
792 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
793 int backlight_controller
= dev_priv
->vbt
.backlight
.controller
;
795 lockdep_assert_held(&dev_priv
->pps_mutex
);
797 /* We should never land here with regular DP ports */
798 WARN_ON(!intel_dp_is_edp(intel_dp
));
800 if (!intel_dp
->pps_reset
)
801 return backlight_controller
;
803 intel_dp
->pps_reset
= false;
806 * Only the HW needs to be reprogrammed, the SW state is fixed and
807 * has been setup during connector init.
809 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
811 return backlight_controller
;
814 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
817 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
820 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
823 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
826 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
829 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
836 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
838 vlv_pipe_check pipe_check
)
842 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
843 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
844 PANEL_PORT_SELECT_MASK
;
846 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
849 if (!pipe_check(dev_priv
, pipe
))
859 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
861 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
862 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
863 enum port port
= intel_dig_port
->base
.port
;
865 lockdep_assert_held(&dev_priv
->pps_mutex
);
867 /* try to find a pipe with this port selected */
868 /* first pick one where the panel is on */
869 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
871 /* didn't find one? pick one where vdd is on */
872 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
873 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
874 vlv_pipe_has_vdd_on
);
875 /* didn't find one? pick one with just the correct port */
876 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
877 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
880 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
881 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
882 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
887 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
888 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
890 intel_dp_init_panel_power_sequencer(intel_dp
);
891 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
894 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
896 struct intel_encoder
*encoder
;
898 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
899 !IS_GEN9_LP(dev_priv
)))
903 * We can't grab pps_mutex here due to deadlock with power_domain
904 * mutex when power_domain functions are called while holding pps_mutex.
905 * That also means that in order to use pps_pipe the code needs to
906 * hold both a power domain reference and pps_mutex, and the power domain
907 * reference get/put must be done while _not_ holding pps_mutex.
908 * pps_{lock,unlock}() do these steps in the correct order, so one
909 * should use them always.
912 for_each_intel_dp(&dev_priv
->drm
, encoder
) {
913 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
915 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
917 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
920 if (IS_GEN9_LP(dev_priv
))
921 intel_dp
->pps_reset
= true;
923 intel_dp
->pps_pipe
= INVALID_PIPE
;
927 struct pps_registers
{
935 static void intel_pps_get_registers(struct intel_dp
*intel_dp
,
936 struct pps_registers
*regs
)
938 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
941 memset(regs
, 0, sizeof(*regs
));
943 if (IS_GEN9_LP(dev_priv
))
944 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
945 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
946 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
948 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
949 regs
->pp_stat
= PP_STATUS(pps_idx
);
950 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
951 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
953 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
954 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
) ||
955 HAS_PCH_ICP(dev_priv
))
956 regs
->pp_div
= INVALID_MMIO_REG
;
958 regs
->pp_div
= PP_DIVISOR(pps_idx
);
962 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
964 struct pps_registers regs
;
966 intel_pps_get_registers(intel_dp
, ®s
);
972 _pp_stat_reg(struct intel_dp
*intel_dp
)
974 struct pps_registers regs
;
976 intel_pps_get_registers(intel_dp
, ®s
);
981 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
982 This function only applicable when panel PM state is not to be tracked */
983 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
986 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
988 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
989 intel_wakeref_t wakeref
;
991 if (!intel_dp_is_edp(intel_dp
) || code
!= SYS_RESTART
)
994 with_pps_lock(intel_dp
, wakeref
) {
995 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
996 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
997 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
1000 pp_ctrl_reg
= PP_CONTROL(pipe
);
1001 pp_div_reg
= PP_DIVISOR(pipe
);
1002 pp_div
= I915_READ(pp_div_reg
);
1003 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
1005 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1006 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
1007 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
);
1008 msleep(intel_dp
->panel_power_cycle_delay
);
1015 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
1017 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1019 lockdep_assert_held(&dev_priv
->pps_mutex
);
1021 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1022 intel_dp
->pps_pipe
== INVALID_PIPE
)
1025 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
1028 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
1030 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1032 lockdep_assert_held(&dev_priv
->pps_mutex
);
1034 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
1035 intel_dp
->pps_pipe
== INVALID_PIPE
)
1038 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
1042 intel_dp_check_edp(struct intel_dp
*intel_dp
)
1044 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1046 if (!intel_dp_is_edp(intel_dp
))
1049 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
1050 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1051 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1052 I915_READ(_pp_stat_reg(intel_dp
)),
1053 I915_READ(_pp_ctrl_reg(intel_dp
)));
1058 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
)
1060 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1061 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
1065 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1066 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
1067 msecs_to_jiffies_timeout(10));
1069 /* just trace the final value */
1070 trace_i915_reg_rw(false, ch_ctl
, status
, sizeof(status
), true);
1073 DRM_ERROR("dp aux hw did not signal timeout!\n");
1079 static u32
g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1081 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1087 * The clock divider is based off the hrawclk, and would like to run at
1088 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1090 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
1093 static u32
ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1095 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1096 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1102 * The clock divider is based off the cdclk or PCH rawclk, and would
1103 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1104 * divide by 2000 and use that
1106 if (dig_port
->aux_ch
== AUX_CH_A
)
1107 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
1109 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
1112 static u32
hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1114 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1115 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1117 if (dig_port
->aux_ch
!= AUX_CH_A
&& HAS_PCH_LPT_H(dev_priv
)) {
1118 /* Workaround for non-ULT HSW */
1126 return ilk_get_aux_clock_divider(intel_dp
, index
);
1129 static u32
skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
1132 * SKL doesn't need us to program the AUX clock divider (Hardware will
1133 * derive the clock from CDCLK automatically). We still implement the
1134 * get_aux_clock_divider vfunc to plug-in into the existing code.
1136 return index
? 0 : 1;
1139 static u32
g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1141 u32 aux_clock_divider
)
1143 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1144 struct drm_i915_private
*dev_priv
=
1145 to_i915(intel_dig_port
->base
.base
.dev
);
1146 u32 precharge
, timeout
;
1148 if (IS_GEN(dev_priv
, 6))
1153 if (IS_BROADWELL(dev_priv
))
1154 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1156 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1158 return DP_AUX_CH_CTL_SEND_BUSY
|
1159 DP_AUX_CH_CTL_DONE
|
1160 DP_AUX_CH_CTL_INTERRUPT
|
1161 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1163 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1164 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1165 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1166 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1169 static u32
skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1173 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1176 ret
= DP_AUX_CH_CTL_SEND_BUSY
|
1177 DP_AUX_CH_CTL_DONE
|
1178 DP_AUX_CH_CTL_INTERRUPT
|
1179 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1180 DP_AUX_CH_CTL_TIME_OUT_MAX
|
1181 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1182 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1183 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1184 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1186 if (intel_dig_port
->tc_type
== TC_PORT_TBT
)
1187 ret
|= DP_AUX_CH_CTL_TBT_IO
;
1193 intel_dp_aux_xfer(struct intel_dp
*intel_dp
,
1194 const u8
*send
, int send_bytes
,
1195 u8
*recv
, int recv_size
,
1196 u32 aux_send_ctl_flags
)
1198 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1199 struct drm_i915_private
*dev_priv
=
1200 to_i915(intel_dig_port
->base
.base
.dev
);
1201 i915_reg_t ch_ctl
, ch_data
[5];
1202 u32 aux_clock_divider
;
1203 intel_wakeref_t wakeref
;
1204 int i
, ret
, recv_bytes
;
1209 ch_ctl
= intel_dp
->aux_ch_ctl_reg(intel_dp
);
1210 for (i
= 0; i
< ARRAY_SIZE(ch_data
); i
++)
1211 ch_data
[i
] = intel_dp
->aux_ch_data_reg(intel_dp
, i
);
1213 wakeref
= pps_lock(intel_dp
);
1216 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1217 * In such cases we want to leave VDD enabled and it's up to upper layers
1218 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1221 vdd
= edp_panel_vdd_on(intel_dp
);
1223 /* dp aux is extremely sensitive to irq latency, hence request the
1224 * lowest possible wakeup latency and so prevent the cpu from going into
1225 * deep sleep states.
1227 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1229 intel_dp_check_edp(intel_dp
);
1231 /* Try to wait for any previous AUX channel activity */
1232 for (try = 0; try < 3; try++) {
1233 status
= I915_READ_NOTRACE(ch_ctl
);
1234 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1238 /* just trace the final value */
1239 trace_i915_reg_rw(false, ch_ctl
, status
, sizeof(status
), true);
1242 static u32 last_status
= -1;
1243 const u32 status
= I915_READ(ch_ctl
);
1245 if (status
!= last_status
) {
1246 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1248 last_status
= status
;
1255 /* Only 5 data registers! */
1256 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1261 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1262 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1266 send_ctl
|= aux_send_ctl_flags
;
1268 /* Must try at least 3 times according to DP spec */
1269 for (try = 0; try < 5; try++) {
1270 /* Load the send data into the aux channel data registers */
1271 for (i
= 0; i
< send_bytes
; i
+= 4)
1272 I915_WRITE(ch_data
[i
>> 2],
1273 intel_dp_pack_aux(send
+ i
,
1276 /* Send the command and wait for it to complete */
1277 I915_WRITE(ch_ctl
, send_ctl
);
1279 status
= intel_dp_aux_wait_done(intel_dp
);
1281 /* Clear done status and any errors */
1284 DP_AUX_CH_CTL_DONE
|
1285 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1286 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1288 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1289 * 400us delay required for errors and timeouts
1290 * Timeout errors from the HW already meet this
1291 * requirement so skip to next iteration
1293 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1296 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1297 usleep_range(400, 500);
1300 if (status
& DP_AUX_CH_CTL_DONE
)
1305 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1306 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1312 /* Check for timeout or receive error.
1313 * Timeouts occur when the sink is not connected
1315 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1316 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1321 /* Timeouts occur when the device isn't connected, so they're
1322 * "normal" -- don't fill the kernel log with these */
1323 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1324 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1329 /* Unload any bytes sent back from the other side */
1330 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1331 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1334 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1335 * We have no idea of what happened so we return -EBUSY so
1336 * drm layer takes care for the necessary retries.
1338 if (recv_bytes
== 0 || recv_bytes
> 20) {
1339 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1345 if (recv_bytes
> recv_size
)
1346 recv_bytes
= recv_size
;
1348 for (i
= 0; i
< recv_bytes
; i
+= 4)
1349 intel_dp_unpack_aux(I915_READ(ch_data
[i
>> 2]),
1350 recv
+ i
, recv_bytes
- i
);
1354 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1357 edp_panel_vdd_off(intel_dp
, false);
1359 pps_unlock(intel_dp
, wakeref
);
1364 #define BARE_ADDRESS_SIZE 3
1365 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1368 intel_dp_aux_header(u8 txbuf
[HEADER_SIZE
],
1369 const struct drm_dp_aux_msg
*msg
)
1371 txbuf
[0] = (msg
->request
<< 4) | ((msg
->address
>> 16) & 0xf);
1372 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1373 txbuf
[2] = msg
->address
& 0xff;
1374 txbuf
[3] = msg
->size
- 1;
1378 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1380 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1381 u8 txbuf
[20], rxbuf
[20];
1382 size_t txsize
, rxsize
;
1385 intel_dp_aux_header(txbuf
, msg
);
1387 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1388 case DP_AUX_NATIVE_WRITE
:
1389 case DP_AUX_I2C_WRITE
:
1390 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1391 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1392 rxsize
= 2; /* 0 or 1 data bytes */
1394 if (WARN_ON(txsize
> 20))
1397 WARN_ON(!msg
->buffer
!= !msg
->size
);
1400 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1402 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1405 msg
->reply
= rxbuf
[0] >> 4;
1408 /* Number of bytes written in a short write. */
1409 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1411 /* Return payload size. */
1417 case DP_AUX_NATIVE_READ
:
1418 case DP_AUX_I2C_READ
:
1419 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1420 rxsize
= msg
->size
+ 1;
1422 if (WARN_ON(rxsize
> 20))
1425 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, txsize
,
1428 msg
->reply
= rxbuf
[0] >> 4;
1430 * Assume happy day, and copy the data. The caller is
1431 * expected to check msg->reply before touching it.
1433 * Return payload size.
1436 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1449 static i915_reg_t
g4x_aux_ctl_reg(struct intel_dp
*intel_dp
)
1451 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1452 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1453 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1459 return DP_AUX_CH_CTL(aux_ch
);
1461 MISSING_CASE(aux_ch
);
1462 return DP_AUX_CH_CTL(AUX_CH_B
);
1466 static i915_reg_t
g4x_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1468 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1469 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1470 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1476 return DP_AUX_CH_DATA(aux_ch
, index
);
1478 MISSING_CASE(aux_ch
);
1479 return DP_AUX_CH_DATA(AUX_CH_B
, index
);
1483 static i915_reg_t
ilk_aux_ctl_reg(struct intel_dp
*intel_dp
)
1485 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1486 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1487 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1491 return DP_AUX_CH_CTL(aux_ch
);
1495 return PCH_DP_AUX_CH_CTL(aux_ch
);
1497 MISSING_CASE(aux_ch
);
1498 return DP_AUX_CH_CTL(AUX_CH_A
);
1502 static i915_reg_t
ilk_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1504 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1505 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1506 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1510 return DP_AUX_CH_DATA(aux_ch
, index
);
1514 return PCH_DP_AUX_CH_DATA(aux_ch
, index
);
1516 MISSING_CASE(aux_ch
);
1517 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1521 static i915_reg_t
skl_aux_ctl_reg(struct intel_dp
*intel_dp
)
1523 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1524 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1525 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1534 return DP_AUX_CH_CTL(aux_ch
);
1536 MISSING_CASE(aux_ch
);
1537 return DP_AUX_CH_CTL(AUX_CH_A
);
1541 static i915_reg_t
skl_aux_data_reg(struct intel_dp
*intel_dp
, int index
)
1543 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1544 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1545 enum aux_ch aux_ch
= dig_port
->aux_ch
;
1554 return DP_AUX_CH_DATA(aux_ch
, index
);
1556 MISSING_CASE(aux_ch
);
1557 return DP_AUX_CH_DATA(AUX_CH_A
, index
);
1562 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1564 kfree(intel_dp
->aux
.name
);
1568 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1570 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1571 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1572 struct intel_encoder
*encoder
= &dig_port
->base
;
1574 if (INTEL_GEN(dev_priv
) >= 9) {
1575 intel_dp
->aux_ch_ctl_reg
= skl_aux_ctl_reg
;
1576 intel_dp
->aux_ch_data_reg
= skl_aux_data_reg
;
1577 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1578 intel_dp
->aux_ch_ctl_reg
= ilk_aux_ctl_reg
;
1579 intel_dp
->aux_ch_data_reg
= ilk_aux_data_reg
;
1581 intel_dp
->aux_ch_ctl_reg
= g4x_aux_ctl_reg
;
1582 intel_dp
->aux_ch_data_reg
= g4x_aux_data_reg
;
1585 if (INTEL_GEN(dev_priv
) >= 9)
1586 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
1587 else if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
1588 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
1589 else if (HAS_PCH_SPLIT(dev_priv
))
1590 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
1592 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
1594 if (INTEL_GEN(dev_priv
) >= 9)
1595 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
1597 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
1599 drm_dp_aux_init(&intel_dp
->aux
);
1601 /* Failure to allocate our preferred name is not critical */
1602 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c",
1603 port_name(encoder
->port
));
1604 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1607 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1609 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1611 return max_rate
>= 540000;
1614 bool intel_dp_source_supports_hbr3(struct intel_dp
*intel_dp
)
1616 int max_rate
= intel_dp
->source_rates
[intel_dp
->num_source_rates
- 1];
1618 return max_rate
>= 810000;
1622 intel_dp_set_clock(struct intel_encoder
*encoder
,
1623 struct intel_crtc_state
*pipe_config
)
1625 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1626 const struct dp_link_dpll
*divisor
= NULL
;
1629 if (IS_G4X(dev_priv
)) {
1631 count
= ARRAY_SIZE(g4x_dpll
);
1632 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1634 count
= ARRAY_SIZE(pch_dpll
);
1635 } else if (IS_CHERRYVIEW(dev_priv
)) {
1637 count
= ARRAY_SIZE(chv_dpll
);
1638 } else if (IS_VALLEYVIEW(dev_priv
)) {
1640 count
= ARRAY_SIZE(vlv_dpll
);
1643 if (divisor
&& count
) {
1644 for (i
= 0; i
< count
; i
++) {
1645 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1646 pipe_config
->dpll
= divisor
[i
].dpll
;
1647 pipe_config
->clock_set
= true;
1654 static void snprintf_int_array(char *str
, size_t len
,
1655 const int *array
, int nelem
)
1661 for (i
= 0; i
< nelem
; i
++) {
1662 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1670 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1672 char str
[128]; /* FIXME: too big for stack? */
1674 if ((drm_debug
& DRM_UT_KMS
) == 0)
1677 snprintf_int_array(str
, sizeof(str
),
1678 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1679 DRM_DEBUG_KMS("source rates: %s\n", str
);
1681 snprintf_int_array(str
, sizeof(str
),
1682 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1683 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1685 snprintf_int_array(str
, sizeof(str
),
1686 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1687 DRM_DEBUG_KMS("common rates: %s\n", str
);
1691 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1695 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1696 if (WARN_ON(len
<= 0))
1699 return intel_dp
->common_rates
[len
- 1];
1702 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1704 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1705 intel_dp
->num_sink_rates
, rate
);
1713 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1714 u8
*link_bw
, u8
*rate_select
)
1716 /* eDP 1.4 rate select method. */
1717 if (intel_dp
->use_rate_select
) {
1720 intel_dp_rate_select(intel_dp
, port_clock
);
1722 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1727 struct link_config_limits
{
1728 int min_clock
, max_clock
;
1729 int min_lane_count
, max_lane_count
;
1730 int min_bpp
, max_bpp
;
1733 static bool intel_dp_source_supports_fec(struct intel_dp
*intel_dp
,
1734 const struct intel_crtc_state
*pipe_config
)
1736 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1738 return INTEL_GEN(dev_priv
) >= 11 &&
1739 pipe_config
->cpu_transcoder
!= TRANSCODER_A
;
1742 static bool intel_dp_supports_fec(struct intel_dp
*intel_dp
,
1743 const struct intel_crtc_state
*pipe_config
)
1745 return intel_dp_source_supports_fec(intel_dp
, pipe_config
) &&
1746 drm_dp_sink_supports_fec(intel_dp
->fec_capable
);
1749 static bool intel_dp_source_supports_dsc(struct intel_dp
*intel_dp
,
1750 const struct intel_crtc_state
*pipe_config
)
1752 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1754 return INTEL_GEN(dev_priv
) >= 10 &&
1755 pipe_config
->cpu_transcoder
!= TRANSCODER_A
;
1758 static bool intel_dp_supports_dsc(struct intel_dp
*intel_dp
,
1759 const struct intel_crtc_state
*pipe_config
)
1761 if (!intel_dp_is_edp(intel_dp
) && !pipe_config
->fec_enable
)
1764 return intel_dp_source_supports_dsc(intel_dp
, pipe_config
) &&
1765 drm_dp_sink_supports_dsc(intel_dp
->dsc_dpcd
);
1768 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1769 struct intel_crtc_state
*pipe_config
)
1771 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
1772 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1775 bpp
= pipe_config
->pipe_bpp
;
1776 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1779 bpp
= min(bpp
, 3*bpc
);
1781 if (intel_dp_is_edp(intel_dp
)) {
1782 /* Get bpp from vbt only for panels that dont have bpp in edid */
1783 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1784 dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
) {
1785 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1786 dev_priv
->vbt
.edp
.bpp
);
1787 bpp
= dev_priv
->vbt
.edp
.bpp
;
1794 /* Adjust link config limits based on compliance test requests. */
1796 intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp
,
1797 struct intel_crtc_state
*pipe_config
,
1798 struct link_config_limits
*limits
)
1800 /* For DP Compliance we override the computed bpp for the pipe */
1801 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1802 int bpp
= 3 * intel_dp
->compliance
.test_data
.bpc
;
1804 limits
->min_bpp
= limits
->max_bpp
= bpp
;
1805 pipe_config
->dither_force_disable
= bpp
== 6 * 3;
1807 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp
);
1810 /* Use values requested by Compliance Test Request */
1811 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1814 /* Validate the compliance test data since max values
1815 * might have changed due to link train fallback.
1817 if (intel_dp_link_params_valid(intel_dp
, intel_dp
->compliance
.test_link_rate
,
1818 intel_dp
->compliance
.test_lane_count
)) {
1819 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1820 intel_dp
->num_common_rates
,
1821 intel_dp
->compliance
.test_link_rate
);
1823 limits
->min_clock
= limits
->max_clock
= index
;
1824 limits
->min_lane_count
= limits
->max_lane_count
=
1825 intel_dp
->compliance
.test_lane_count
;
1830 /* Optimize link config in order: max bpp, min clock, min lanes */
1832 intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp
,
1833 struct intel_crtc_state
*pipe_config
,
1834 const struct link_config_limits
*limits
)
1836 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1837 int bpp
, clock
, lane_count
;
1838 int mode_rate
, link_clock
, link_avail
;
1840 for (bpp
= limits
->max_bpp
; bpp
>= limits
->min_bpp
; bpp
-= 2 * 3) {
1841 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1844 for (clock
= limits
->min_clock
; clock
<= limits
->max_clock
; clock
++) {
1845 for (lane_count
= limits
->min_lane_count
;
1846 lane_count
<= limits
->max_lane_count
;
1848 link_clock
= intel_dp
->common_rates
[clock
];
1849 link_avail
= intel_dp_max_data_rate(link_clock
,
1852 if (mode_rate
<= link_avail
) {
1853 pipe_config
->lane_count
= lane_count
;
1854 pipe_config
->pipe_bpp
= bpp
;
1855 pipe_config
->port_clock
= link_clock
;
1866 /* Optimize link config in order: max bpp, min lanes, min clock */
1868 intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp
,
1869 struct intel_crtc_state
*pipe_config
,
1870 const struct link_config_limits
*limits
)
1872 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1873 int bpp
, clock
, lane_count
;
1874 int mode_rate
, link_clock
, link_avail
;
1876 for (bpp
= limits
->max_bpp
; bpp
>= limits
->min_bpp
; bpp
-= 2 * 3) {
1877 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1880 for (lane_count
= limits
->min_lane_count
;
1881 lane_count
<= limits
->max_lane_count
;
1883 for (clock
= limits
->min_clock
; clock
<= limits
->max_clock
; clock
++) {
1884 link_clock
= intel_dp
->common_rates
[clock
];
1885 link_avail
= intel_dp_max_data_rate(link_clock
,
1888 if (mode_rate
<= link_avail
) {
1889 pipe_config
->lane_count
= lane_count
;
1890 pipe_config
->pipe_bpp
= bpp
;
1891 pipe_config
->port_clock
= link_clock
;
1902 static int intel_dp_dsc_compute_bpp(struct intel_dp
*intel_dp
, u8 dsc_max_bpc
)
1905 u8 dsc_bpc
[3] = {0};
1907 num_bpc
= drm_dp_dsc_sink_supported_input_bpcs(intel_dp
->dsc_dpcd
,
1909 for (i
= 0; i
< num_bpc
; i
++) {
1910 if (dsc_max_bpc
>= dsc_bpc
[i
])
1911 return dsc_bpc
[i
] * 3;
1917 static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp
,
1918 struct intel_crtc_state
*pipe_config
,
1919 struct drm_connector_state
*conn_state
,
1920 struct link_config_limits
*limits
)
1922 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1923 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1924 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1929 if (!intel_dp_supports_dsc(intel_dp
, pipe_config
))
1932 dsc_max_bpc
= min_t(u8
, DP_DSC_MAX_SUPPORTED_BPC
,
1933 conn_state
->max_requested_bpc
);
1935 pipe_bpp
= intel_dp_dsc_compute_bpp(intel_dp
, dsc_max_bpc
);
1936 if (pipe_bpp
< DP_DSC_MIN_SUPPORTED_BPC
* 3) {
1937 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1942 * For now enable DSC for max bpp, max link rate, max lane count.
1943 * Optimize this later for the minimum possible link rate/lane count
1944 * with DSC enabled for the requested mode.
1946 pipe_config
->pipe_bpp
= pipe_bpp
;
1947 pipe_config
->port_clock
= intel_dp
->common_rates
[limits
->max_clock
];
1948 pipe_config
->lane_count
= limits
->max_lane_count
;
1950 if (intel_dp_is_edp(intel_dp
)) {
1951 pipe_config
->dsc_params
.compressed_bpp
=
1952 min_t(u16
, drm_edp_dsc_sink_output_bpp(intel_dp
->dsc_dpcd
) >> 4,
1953 pipe_config
->pipe_bpp
);
1954 pipe_config
->dsc_params
.slice_count
=
1955 drm_dp_dsc_sink_max_slice_count(intel_dp
->dsc_dpcd
,
1958 u16 dsc_max_output_bpp
;
1959 u8 dsc_dp_slice_count
;
1961 dsc_max_output_bpp
=
1962 intel_dp_dsc_get_output_bpp(pipe_config
->port_clock
,
1963 pipe_config
->lane_count
,
1964 adjusted_mode
->crtc_clock
,
1965 adjusted_mode
->crtc_hdisplay
);
1966 dsc_dp_slice_count
=
1967 intel_dp_dsc_get_slice_count(intel_dp
,
1968 adjusted_mode
->crtc_clock
,
1969 adjusted_mode
->crtc_hdisplay
);
1970 if (!dsc_max_output_bpp
|| !dsc_dp_slice_count
) {
1971 DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1974 pipe_config
->dsc_params
.compressed_bpp
= min_t(u16
,
1975 dsc_max_output_bpp
>> 4,
1976 pipe_config
->pipe_bpp
);
1977 pipe_config
->dsc_params
.slice_count
= dsc_dp_slice_count
;
1980 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1981 * is greater than the maximum Cdclock and if slice count is even
1982 * then we need to use 2 VDSC instances.
1984 if (adjusted_mode
->crtc_clock
> dev_priv
->max_cdclk_freq
) {
1985 if (pipe_config
->dsc_params
.slice_count
> 1) {
1986 pipe_config
->dsc_params
.dsc_split
= true;
1988 DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1993 ret
= intel_dp_compute_dsc_params(intel_dp
, pipe_config
);
1995 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1996 "Compressed BPP = %d\n",
1997 pipe_config
->pipe_bpp
,
1998 pipe_config
->dsc_params
.compressed_bpp
);
2002 pipe_config
->dsc_params
.compression_enable
= true;
2003 DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2004 "Compressed Bpp = %d Slice Count = %d\n",
2005 pipe_config
->pipe_bpp
,
2006 pipe_config
->dsc_params
.compressed_bpp
,
2007 pipe_config
->dsc_params
.slice_count
);
2013 intel_dp_compute_link_config(struct intel_encoder
*encoder
,
2014 struct intel_crtc_state
*pipe_config
,
2015 struct drm_connector_state
*conn_state
)
2017 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
2018 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2019 struct link_config_limits limits
;
2023 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
2024 intel_dp
->max_link_rate
);
2026 /* No common link rates between source and sink */
2027 WARN_ON(common_len
<= 0);
2029 limits
.min_clock
= 0;
2030 limits
.max_clock
= common_len
- 1;
2032 limits
.min_lane_count
= 1;
2033 limits
.max_lane_count
= intel_dp_max_lane_count(intel_dp
);
2035 limits
.min_bpp
= 6 * 3;
2036 limits
.max_bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
2038 if (intel_dp_is_edp(intel_dp
) && intel_dp
->edp_dpcd
[0] < DP_EDP_14
) {
2040 * Use the maximum clock and number of lanes the eDP panel
2041 * advertizes being capable of. The eDP 1.3 and earlier panels
2042 * are generally designed to support only a single clock and
2043 * lane configuration, and typically these values correspond to
2044 * the native resolution of the panel. With eDP 1.4 rate select
2045 * and DSC, this is decreasingly the case, and we need to be
2046 * able to select less than maximum link config.
2048 limits
.min_lane_count
= limits
.max_lane_count
;
2049 limits
.min_clock
= limits
.max_clock
;
2052 intel_dp_adjust_compliance_config(intel_dp
, pipe_config
, &limits
);
2054 DRM_DEBUG_KMS("DP link computation with max lane count %i "
2055 "max rate %d max bpp %d pixel clock %iKHz\n",
2056 limits
.max_lane_count
,
2057 intel_dp
->common_rates
[limits
.max_clock
],
2058 limits
.max_bpp
, adjusted_mode
->crtc_clock
);
2060 if (intel_dp_is_edp(intel_dp
))
2062 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2063 * section A.1: "It is recommended that the minimum number of
2064 * lanes be used, using the minimum link rate allowed for that
2065 * lane configuration."
2067 * Note that we use the max clock and lane count for eDP 1.3 and
2068 * earlier, and fast vs. wide is irrelevant.
2070 ret
= intel_dp_compute_link_config_fast(intel_dp
, pipe_config
,
2073 /* Optimize for slow and wide. */
2074 ret
= intel_dp_compute_link_config_wide(intel_dp
, pipe_config
,
2077 /* enable compression if the mode doesn't fit available BW */
2078 DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp
->force_dsc_en
);
2079 if (ret
|| intel_dp
->force_dsc_en
) {
2080 ret
= intel_dp_dsc_compute_config(intel_dp
, pipe_config
,
2081 conn_state
, &limits
);
2086 if (pipe_config
->dsc_params
.compression_enable
) {
2087 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2088 pipe_config
->lane_count
, pipe_config
->port_clock
,
2089 pipe_config
->pipe_bpp
,
2090 pipe_config
->dsc_params
.compressed_bpp
);
2092 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2093 intel_dp_link_required(adjusted_mode
->crtc_clock
,
2094 pipe_config
->dsc_params
.compressed_bpp
),
2095 intel_dp_max_data_rate(pipe_config
->port_clock
,
2096 pipe_config
->lane_count
));
2098 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2099 pipe_config
->lane_count
, pipe_config
->port_clock
,
2100 pipe_config
->pipe_bpp
);
2102 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2103 intel_dp_link_required(adjusted_mode
->crtc_clock
,
2104 pipe_config
->pipe_bpp
),
2105 intel_dp_max_data_rate(pipe_config
->port_clock
,
2106 pipe_config
->lane_count
));
2112 intel_dp_compute_config(struct intel_encoder
*encoder
,
2113 struct intel_crtc_state
*pipe_config
,
2114 struct drm_connector_state
*conn_state
)
2116 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2117 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
2118 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2119 struct intel_lspcon
*lspcon
= enc_to_intel_lspcon(&encoder
->base
);
2120 enum port port
= encoder
->port
;
2121 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2122 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
2123 struct intel_digital_connector_state
*intel_conn_state
=
2124 to_intel_digital_connector_state(conn_state
);
2125 bool constant_n
= drm_dp_has_quirk(&intel_dp
->desc
,
2126 DP_DPCD_QUIRK_CONSTANT_N
);
2129 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
2130 pipe_config
->has_pch_encoder
= true;
2132 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
2134 lspcon_ycbcr420_config(&intel_connector
->base
, pipe_config
);
2136 pipe_config
->has_drrs
= false;
2137 if (IS_G4X(dev_priv
) || port
== PORT_A
)
2138 pipe_config
->has_audio
= false;
2139 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
2140 pipe_config
->has_audio
= intel_dp
->has_audio
;
2142 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
2144 if (intel_dp_is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2145 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
2148 if (INTEL_GEN(dev_priv
) >= 9) {
2149 ret
= skl_update_scaler_crtc(pipe_config
);
2154 if (HAS_GMCH(dev_priv
))
2155 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
2156 conn_state
->scaling_mode
);
2158 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
2159 conn_state
->scaling_mode
);
2162 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2165 if (HAS_GMCH(dev_priv
) &&
2166 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2169 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2172 pipe_config
->fec_enable
= !intel_dp_is_edp(intel_dp
) &&
2173 intel_dp_supports_fec(intel_dp
, pipe_config
);
2175 ret
= intel_dp_compute_link_config(encoder
, pipe_config
, conn_state
);
2179 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
2182 * CEA-861-E - 5.1 Default Encoding Parameters
2183 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2185 pipe_config
->limited_color_range
=
2186 pipe_config
->pipe_bpp
!= 18 &&
2187 drm_default_rgb_quant_range(adjusted_mode
) ==
2188 HDMI_QUANTIZATION_RANGE_LIMITED
;
2190 pipe_config
->limited_color_range
=
2191 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
2194 if (!pipe_config
->dsc_params
.compression_enable
)
2195 intel_link_compute_m_n(pipe_config
->pipe_bpp
,
2196 pipe_config
->lane_count
,
2197 adjusted_mode
->crtc_clock
,
2198 pipe_config
->port_clock
,
2199 &pipe_config
->dp_m_n
,
2202 intel_link_compute_m_n(pipe_config
->dsc_params
.compressed_bpp
,
2203 pipe_config
->lane_count
,
2204 adjusted_mode
->crtc_clock
,
2205 pipe_config
->port_clock
,
2206 &pipe_config
->dp_m_n
,
2209 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
2210 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
2211 pipe_config
->has_drrs
= true;
2212 intel_link_compute_m_n(pipe_config
->pipe_bpp
,
2213 pipe_config
->lane_count
,
2214 intel_connector
->panel
.downclock_mode
->clock
,
2215 pipe_config
->port_clock
,
2216 &pipe_config
->dp_m2_n2
,
2220 if (!HAS_DDI(dev_priv
))
2221 intel_dp_set_clock(encoder
, pipe_config
);
2223 intel_psr_compute_config(intel_dp
, pipe_config
);
2228 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
2229 int link_rate
, u8 lane_count
,
2232 intel_dp
->link_trained
= false;
2233 intel_dp
->link_rate
= link_rate
;
2234 intel_dp
->lane_count
= lane_count
;
2235 intel_dp
->link_mst
= link_mst
;
2238 static void intel_dp_prepare(struct intel_encoder
*encoder
,
2239 const struct intel_crtc_state
*pipe_config
)
2241 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2242 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2243 enum port port
= encoder
->port
;
2244 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2245 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
2247 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
2248 pipe_config
->lane_count
,
2249 intel_crtc_has_type(pipe_config
,
2250 INTEL_OUTPUT_DP_MST
));
2253 * There are four kinds of DP registers:
2260 * IBX PCH and CPU are the same for almost everything,
2261 * except that the CPU DP PLL is configured in this
2264 * CPT PCH is quite different, having many bits moved
2265 * to the TRANS_DP_CTL register instead. That
2266 * configuration happens (oddly) in ironlake_pch_enable
2269 /* Preserve the BIOS-computed detected bit. This is
2270 * supposed to be read-only.
2272 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
2274 /* Handle DP bits in common between all three register formats */
2275 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
2276 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
2278 /* Split out the IBX/CPU vs CPT settings */
2280 if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
2281 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
2282 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
2283 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
2284 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
2285 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
2287 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2288 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2290 intel_dp
->DP
|= DP_PIPE_SEL_IVB(crtc
->pipe
);
2291 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2294 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
2296 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2297 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2298 trans_dp
|= TRANS_DP_ENH_FRAMING
;
2300 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
2301 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
2303 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
2304 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
2306 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
2307 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
2308 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
2309 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
2310 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
2312 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2313 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
2315 if (IS_CHERRYVIEW(dev_priv
))
2316 intel_dp
->DP
|= DP_PIPE_SEL_CHV(crtc
->pipe
);
2318 intel_dp
->DP
|= DP_PIPE_SEL(crtc
->pipe
);
2322 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2323 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2325 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2326 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2328 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2329 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2331 static void intel_pps_verify_state(struct intel_dp
*intel_dp
);
2333 static void wait_panel_status(struct intel_dp
*intel_dp
,
2337 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2338 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2340 lockdep_assert_held(&dev_priv
->pps_mutex
);
2342 intel_pps_verify_state(intel_dp
);
2344 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2345 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2347 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2349 I915_READ(pp_stat_reg
),
2350 I915_READ(pp_ctrl_reg
));
2352 if (intel_wait_for_register(dev_priv
,
2353 pp_stat_reg
, mask
, value
,
2355 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2356 I915_READ(pp_stat_reg
),
2357 I915_READ(pp_ctrl_reg
));
2359 DRM_DEBUG_KMS("Wait complete\n");
2362 static void wait_panel_on(struct intel_dp
*intel_dp
)
2364 DRM_DEBUG_KMS("Wait for panel power on\n");
2365 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
2368 static void wait_panel_off(struct intel_dp
*intel_dp
)
2370 DRM_DEBUG_KMS("Wait for panel power off time\n");
2371 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
2374 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
2376 ktime_t panel_power_on_time
;
2377 s64 panel_power_off_duration
;
2379 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2381 /* take the difference of currrent time and panel power off time
2382 * and then make panel wait for t11_t12 if needed. */
2383 panel_power_on_time
= ktime_get_boottime();
2384 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
2386 /* When we disable the VDD override bit last we have to do the manual
2388 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
2389 wait_remaining_ms_from_jiffies(jiffies
,
2390 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
2392 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2395 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2397 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2398 intel_dp
->backlight_on_delay
);
2401 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2403 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2404 intel_dp
->backlight_off_delay
);
2407 /* Read the current pp_control value, unlocking the register if it
2411 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2413 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2416 lockdep_assert_held(&dev_priv
->pps_mutex
);
2418 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2419 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2420 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2421 control
&= ~PANEL_UNLOCK_MASK
;
2422 control
|= PANEL_UNLOCK_REGS
;
2428 * Must be paired with edp_panel_vdd_off().
2429 * Must hold pps_mutex around the whole on/off sequence.
2430 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2432 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2434 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2435 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2437 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2438 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2440 lockdep_assert_held(&dev_priv
->pps_mutex
);
2442 if (!intel_dp_is_edp(intel_dp
))
2445 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2446 intel_dp
->want_panel_vdd
= true;
2448 if (edp_have_panel_vdd(intel_dp
))
2449 return need_to_disable
;
2451 intel_display_power_get(dev_priv
,
2452 intel_aux_power_domain(intel_dig_port
));
2454 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2455 port_name(intel_dig_port
->base
.port
));
2457 if (!edp_have_panel_power(intel_dp
))
2458 wait_panel_power_cycle(intel_dp
);
2460 pp
= ironlake_get_pp_control(intel_dp
);
2461 pp
|= EDP_FORCE_VDD
;
2463 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2464 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2466 I915_WRITE(pp_ctrl_reg
, pp
);
2467 POSTING_READ(pp_ctrl_reg
);
2468 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2469 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2471 * If the panel wasn't on, delay before accessing aux channel
2473 if (!edp_have_panel_power(intel_dp
)) {
2474 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2475 port_name(intel_dig_port
->base
.port
));
2476 msleep(intel_dp
->panel_power_up_delay
);
2479 return need_to_disable
;
2483 * Must be paired with intel_edp_panel_vdd_off() or
2484 * intel_edp_panel_off().
2485 * Nested calls to these functions are not allowed since
2486 * we drop the lock. Caller must use some higher level
2487 * locking to prevent nested calls from other threads.
2489 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2491 intel_wakeref_t wakeref
;
2494 if (!intel_dp_is_edp(intel_dp
))
2498 with_pps_lock(intel_dp
, wakeref
)
2499 vdd
= edp_panel_vdd_on(intel_dp
);
2500 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2501 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2504 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2506 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2507 struct intel_digital_port
*intel_dig_port
=
2508 dp_to_dig_port(intel_dp
);
2510 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2512 lockdep_assert_held(&dev_priv
->pps_mutex
);
2514 WARN_ON(intel_dp
->want_panel_vdd
);
2516 if (!edp_have_panel_vdd(intel_dp
))
2519 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2520 port_name(intel_dig_port
->base
.port
));
2522 pp
= ironlake_get_pp_control(intel_dp
);
2523 pp
&= ~EDP_FORCE_VDD
;
2525 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2526 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2528 I915_WRITE(pp_ctrl_reg
, pp
);
2529 POSTING_READ(pp_ctrl_reg
);
2531 /* Make sure sequencer is idle before allowing subsequent activity */
2532 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2533 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2535 if ((pp
& PANEL_POWER_ON
) == 0)
2536 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2538 intel_display_power_put_unchecked(dev_priv
,
2539 intel_aux_power_domain(intel_dig_port
));
2542 static void edp_panel_vdd_work(struct work_struct
*__work
)
2544 struct intel_dp
*intel_dp
=
2545 container_of(to_delayed_work(__work
),
2546 struct intel_dp
, panel_vdd_work
);
2547 intel_wakeref_t wakeref
;
2549 with_pps_lock(intel_dp
, wakeref
) {
2550 if (!intel_dp
->want_panel_vdd
)
2551 edp_panel_vdd_off_sync(intel_dp
);
2555 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2557 unsigned long delay
;
2560 * Queue the timer to fire a long time from now (relative to the power
2561 * down delay) to keep the panel power up across a sequence of
2564 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2565 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2569 * Must be paired with edp_panel_vdd_on().
2570 * Must hold pps_mutex around the whole on/off sequence.
2571 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2573 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2575 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2577 lockdep_assert_held(&dev_priv
->pps_mutex
);
2579 if (!intel_dp_is_edp(intel_dp
))
2582 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2583 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2585 intel_dp
->want_panel_vdd
= false;
2588 edp_panel_vdd_off_sync(intel_dp
);
2590 edp_panel_vdd_schedule_off(intel_dp
);
2593 static void edp_panel_on(struct intel_dp
*intel_dp
)
2595 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2597 i915_reg_t pp_ctrl_reg
;
2599 lockdep_assert_held(&dev_priv
->pps_mutex
);
2601 if (!intel_dp_is_edp(intel_dp
))
2604 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2605 port_name(dp_to_dig_port(intel_dp
)->base
.port
));
2607 if (WARN(edp_have_panel_power(intel_dp
),
2608 "eDP port %c panel power already on\n",
2609 port_name(dp_to_dig_port(intel_dp
)->base
.port
)))
2612 wait_panel_power_cycle(intel_dp
);
2614 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2615 pp
= ironlake_get_pp_control(intel_dp
);
2616 if (IS_GEN(dev_priv
, 5)) {
2617 /* ILK workaround: disable reset around power sequence */
2618 pp
&= ~PANEL_POWER_RESET
;
2619 I915_WRITE(pp_ctrl_reg
, pp
);
2620 POSTING_READ(pp_ctrl_reg
);
2623 pp
|= PANEL_POWER_ON
;
2624 if (!IS_GEN(dev_priv
, 5))
2625 pp
|= PANEL_POWER_RESET
;
2627 I915_WRITE(pp_ctrl_reg
, pp
);
2628 POSTING_READ(pp_ctrl_reg
);
2630 wait_panel_on(intel_dp
);
2631 intel_dp
->last_power_on
= jiffies
;
2633 if (IS_GEN(dev_priv
, 5)) {
2634 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2635 I915_WRITE(pp_ctrl_reg
, pp
);
2636 POSTING_READ(pp_ctrl_reg
);
2640 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2642 intel_wakeref_t wakeref
;
2644 if (!intel_dp_is_edp(intel_dp
))
2647 with_pps_lock(intel_dp
, wakeref
)
2648 edp_panel_on(intel_dp
);
2652 static void edp_panel_off(struct intel_dp
*intel_dp
)
2654 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2655 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2657 i915_reg_t pp_ctrl_reg
;
2659 lockdep_assert_held(&dev_priv
->pps_mutex
);
2661 if (!intel_dp_is_edp(intel_dp
))
2664 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2665 port_name(dig_port
->base
.port
));
2667 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2668 port_name(dig_port
->base
.port
));
2670 pp
= ironlake_get_pp_control(intel_dp
);
2671 /* We need to switch off panel power _and_ force vdd, for otherwise some
2672 * panels get very unhappy and cease to work. */
2673 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2676 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2678 intel_dp
->want_panel_vdd
= false;
2680 I915_WRITE(pp_ctrl_reg
, pp
);
2681 POSTING_READ(pp_ctrl_reg
);
2683 wait_panel_off(intel_dp
);
2684 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2686 /* We got a reference when we enabled the VDD. */
2687 intel_display_power_put_unchecked(dev_priv
, intel_aux_power_domain(dig_port
));
2690 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2692 intel_wakeref_t wakeref
;
2694 if (!intel_dp_is_edp(intel_dp
))
2697 with_pps_lock(intel_dp
, wakeref
)
2698 edp_panel_off(intel_dp
);
2701 /* Enable backlight in the panel power control. */
2702 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2704 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2705 intel_wakeref_t wakeref
;
2708 * If we enable the backlight right away following a panel power
2709 * on, we may see slight flicker as the panel syncs with the eDP
2710 * link. So delay a bit to make sure the image is solid before
2711 * allowing it to appear.
2713 wait_backlight_on(intel_dp
);
2715 with_pps_lock(intel_dp
, wakeref
) {
2716 i915_reg_t pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2719 pp
= ironlake_get_pp_control(intel_dp
);
2720 pp
|= EDP_BLC_ENABLE
;
2722 I915_WRITE(pp_ctrl_reg
, pp
);
2723 POSTING_READ(pp_ctrl_reg
);
2727 /* Enable backlight PWM and backlight PP control. */
2728 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2729 const struct drm_connector_state
*conn_state
)
2731 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2733 if (!intel_dp_is_edp(intel_dp
))
2736 DRM_DEBUG_KMS("\n");
2738 intel_panel_enable_backlight(crtc_state
, conn_state
);
2739 _intel_edp_backlight_on(intel_dp
);
2742 /* Disable backlight in the panel power control. */
2743 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2745 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
2746 intel_wakeref_t wakeref
;
2748 if (!intel_dp_is_edp(intel_dp
))
2751 with_pps_lock(intel_dp
, wakeref
) {
2752 i915_reg_t pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2755 pp
= ironlake_get_pp_control(intel_dp
);
2756 pp
&= ~EDP_BLC_ENABLE
;
2758 I915_WRITE(pp_ctrl_reg
, pp
);
2759 POSTING_READ(pp_ctrl_reg
);
2762 intel_dp
->last_backlight_off
= jiffies
;
2763 edp_wait_backlight_off(intel_dp
);
2766 /* Disable backlight PP control and backlight PWM. */
2767 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2769 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2771 if (!intel_dp_is_edp(intel_dp
))
2774 DRM_DEBUG_KMS("\n");
2776 _intel_edp_backlight_off(intel_dp
);
2777 intel_panel_disable_backlight(old_conn_state
);
2781 * Hook for controlling the panel power control backlight through the bl_power
2782 * sysfs attribute. Take care to handle multiple calls.
2784 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2787 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2788 intel_wakeref_t wakeref
;
2792 with_pps_lock(intel_dp
, wakeref
)
2793 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2794 if (is_enabled
== enable
)
2797 DRM_DEBUG_KMS("panel power control backlight %s\n",
2798 enable
? "enable" : "disable");
2801 _intel_edp_backlight_on(intel_dp
);
2803 _intel_edp_backlight_off(intel_dp
);
2806 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2808 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2809 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2810 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2812 I915_STATE_WARN(cur_state
!= state
,
2813 "DP port %c state assertion failure (expected %s, current %s)\n",
2814 port_name(dig_port
->base
.port
),
2815 onoff(state
), onoff(cur_state
));
2817 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2819 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2821 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2823 I915_STATE_WARN(cur_state
!= state
,
2824 "eDP PLL state assertion failure (expected %s, current %s)\n",
2825 onoff(state
), onoff(cur_state
));
2827 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2828 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2830 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2831 const struct intel_crtc_state
*pipe_config
)
2833 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2834 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2836 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2837 assert_dp_port_disabled(intel_dp
);
2838 assert_edp_pll_disabled(dev_priv
);
2840 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2841 pipe_config
->port_clock
);
2843 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2845 if (pipe_config
->port_clock
== 162000)
2846 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2848 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2850 I915_WRITE(DP_A
, intel_dp
->DP
);
2855 * [DevILK] Work around required when enabling DP PLL
2856 * while a pipe is enabled going to FDI:
2857 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2858 * 2. Program DP PLL enable
2860 if (IS_GEN(dev_priv
, 5))
2861 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2863 intel_dp
->DP
|= DP_PLL_ENABLE
;
2865 I915_WRITE(DP_A
, intel_dp
->DP
);
2870 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
,
2871 const struct intel_crtc_state
*old_crtc_state
)
2873 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
2874 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2876 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2877 assert_dp_port_disabled(intel_dp
);
2878 assert_edp_pll_enabled(dev_priv
);
2880 DRM_DEBUG_KMS("disabling eDP PLL\n");
2882 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2884 I915_WRITE(DP_A
, intel_dp
->DP
);
2889 static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp
)
2892 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2893 * be capable of signalling downstream hpd with a long pulse.
2894 * Whether or not that means D3 is safe to use is not clear,
2895 * but let's assume so until proven otherwise.
2897 * FIXME should really check all downstream ports...
2899 return intel_dp
->dpcd
[DP_DPCD_REV
] == 0x11 &&
2900 intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
&&
2901 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
;
2904 void intel_dp_sink_set_decompression_state(struct intel_dp
*intel_dp
,
2905 const struct intel_crtc_state
*crtc_state
,
2910 if (!crtc_state
->dsc_params
.compression_enable
)
2913 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_DSC_ENABLE
,
2914 enable
? DP_DECOMPRESSION_EN
: 0);
2916 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2917 enable
? "enable" : "disable");
2920 /* If the sink supports it, try to set the power state appropriately */
2921 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2925 /* Should have a valid DPCD by this point */
2926 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2929 if (mode
!= DRM_MODE_DPMS_ON
) {
2930 if (downstream_hpd_needs_d0(intel_dp
))
2933 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2936 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2939 * When turning on, we need to retry for 1ms to give the sink
2942 for (i
= 0; i
< 3; i
++) {
2943 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2950 if (ret
== 1 && lspcon
->active
)
2951 lspcon_wait_pcon_mode(lspcon
);
2955 DRM_DEBUG_KMS("failed to %s sink power state\n",
2956 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2959 static bool cpt_dp_port_selected(struct drm_i915_private
*dev_priv
,
2960 enum port port
, enum pipe
*pipe
)
2964 for_each_pipe(dev_priv
, p
) {
2965 u32 val
= I915_READ(TRANS_DP_CTL(p
));
2967 if ((val
& TRANS_DP_PORT_SEL_MASK
) == TRANS_DP_PORT_SEL(port
)) {
2973 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port
));
2975 /* must initialize pipe to something for the asserts */
2981 bool intel_dp_port_enabled(struct drm_i915_private
*dev_priv
,
2982 i915_reg_t dp_reg
, enum port port
,
2988 val
= I915_READ(dp_reg
);
2990 ret
= val
& DP_PORT_EN
;
2992 /* asserts want to know the pipe even if the port is disabled */
2993 if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
)
2994 *pipe
= (val
& DP_PIPE_SEL_MASK_IVB
) >> DP_PIPE_SEL_SHIFT_IVB
;
2995 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
2996 ret
&= cpt_dp_port_selected(dev_priv
, port
, pipe
);
2997 else if (IS_CHERRYVIEW(dev_priv
))
2998 *pipe
= (val
& DP_PIPE_SEL_MASK_CHV
) >> DP_PIPE_SEL_SHIFT_CHV
;
3000 *pipe
= (val
& DP_PIPE_SEL_MASK
) >> DP_PIPE_SEL_SHIFT
;
3005 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
3008 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3009 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3010 intel_wakeref_t wakeref
;
3013 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
3014 encoder
->power_domain
);
3018 ret
= intel_dp_port_enabled(dev_priv
, intel_dp
->output_reg
,
3019 encoder
->port
, pipe
);
3021 intel_display_power_put(dev_priv
, encoder
->power_domain
, wakeref
);
3026 static void intel_dp_get_config(struct intel_encoder
*encoder
,
3027 struct intel_crtc_state
*pipe_config
)
3029 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3030 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3032 enum port port
= encoder
->port
;
3033 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
3035 if (encoder
->type
== INTEL_OUTPUT_EDP
)
3036 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_EDP
);
3038 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_DP
);
3040 tmp
= I915_READ(intel_dp
->output_reg
);
3042 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
3044 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
3045 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
3047 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
3048 flags
|= DRM_MODE_FLAG_PHSYNC
;
3050 flags
|= DRM_MODE_FLAG_NHSYNC
;
3052 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
3053 flags
|= DRM_MODE_FLAG_PVSYNC
;
3055 flags
|= DRM_MODE_FLAG_NVSYNC
;
3057 if (tmp
& DP_SYNC_HS_HIGH
)
3058 flags
|= DRM_MODE_FLAG_PHSYNC
;
3060 flags
|= DRM_MODE_FLAG_NHSYNC
;
3062 if (tmp
& DP_SYNC_VS_HIGH
)
3063 flags
|= DRM_MODE_FLAG_PVSYNC
;
3065 flags
|= DRM_MODE_FLAG_NVSYNC
;
3068 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
3070 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
3071 pipe_config
->limited_color_range
= true;
3073 pipe_config
->lane_count
=
3074 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
3076 intel_dp_get_m_n(crtc
, pipe_config
);
3078 if (port
== PORT_A
) {
3079 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
3080 pipe_config
->port_clock
= 162000;
3082 pipe_config
->port_clock
= 270000;
3085 pipe_config
->base
.adjusted_mode
.crtc_clock
=
3086 intel_dotclock_calculate(pipe_config
->port_clock
,
3087 &pipe_config
->dp_m_n
);
3089 if (intel_dp_is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
3090 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
3092 * This is a big fat ugly hack.
3094 * Some machines in UEFI boot mode provide us a VBT that has 18
3095 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3096 * unknown we fail to light up. Yet the same BIOS boots up with
3097 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3098 * max, not what it tells us to use.
3100 * Note: This will still be broken if the eDP panel is not lit
3101 * up by the BIOS, and thus we can't get the mode at module
3104 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3105 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
3106 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
3110 static void intel_disable_dp(struct intel_encoder
*encoder
,
3111 const struct intel_crtc_state
*old_crtc_state
,
3112 const struct drm_connector_state
*old_conn_state
)
3114 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3116 intel_dp
->link_trained
= false;
3118 if (old_crtc_state
->has_audio
)
3119 intel_audio_codec_disable(encoder
,
3120 old_crtc_state
, old_conn_state
);
3122 /* Make sure the panel is off before trying to change the mode. But also
3123 * ensure that we have vdd while we switch off the panel. */
3124 intel_edp_panel_vdd_on(intel_dp
);
3125 intel_edp_backlight_off(old_conn_state
);
3126 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
3127 intel_edp_panel_off(intel_dp
);
3130 static void g4x_disable_dp(struct intel_encoder
*encoder
,
3131 const struct intel_crtc_state
*old_crtc_state
,
3132 const struct drm_connector_state
*old_conn_state
)
3134 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
3137 static void vlv_disable_dp(struct intel_encoder
*encoder
,
3138 const struct intel_crtc_state
*old_crtc_state
,
3139 const struct drm_connector_state
*old_conn_state
)
3141 intel_disable_dp(encoder
, old_crtc_state
, old_conn_state
);
3144 static void g4x_post_disable_dp(struct intel_encoder
*encoder
,
3145 const struct intel_crtc_state
*old_crtc_state
,
3146 const struct drm_connector_state
*old_conn_state
)
3148 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3149 enum port port
= encoder
->port
;
3152 * Bspec does not list a specific disable sequence for g4x DP.
3153 * Follow the ilk+ sequence (disable pipe before the port) for
3154 * g4x DP as it does not suffer from underruns like the normal
3155 * g4x modeset sequence (disable pipe after the port).
3157 intel_dp_link_down(encoder
, old_crtc_state
);
3159 /* Only ilk+ has port A */
3161 ironlake_edp_pll_off(intel_dp
, old_crtc_state
);
3164 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
3165 const struct intel_crtc_state
*old_crtc_state
,
3166 const struct drm_connector_state
*old_conn_state
)
3168 intel_dp_link_down(encoder
, old_crtc_state
);
3171 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
3172 const struct intel_crtc_state
*old_crtc_state
,
3173 const struct drm_connector_state
*old_conn_state
)
3175 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3177 intel_dp_link_down(encoder
, old_crtc_state
);
3179 mutex_lock(&dev_priv
->sb_lock
);
3181 /* Assert data lane reset */
3182 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
3184 mutex_unlock(&dev_priv
->sb_lock
);
3188 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3192 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3193 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3194 enum port port
= intel_dig_port
->base
.port
;
3195 u8 train_pat_mask
= drm_dp_training_pattern_mask(intel_dp
->dpcd
);
3197 if (dp_train_pat
& train_pat_mask
)
3198 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3199 dp_train_pat
& train_pat_mask
);
3201 if (HAS_DDI(dev_priv
)) {
3202 u32 temp
= I915_READ(DP_TP_CTL(port
));
3204 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
3205 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
3207 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
3209 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3210 switch (dp_train_pat
& train_pat_mask
) {
3211 case DP_TRAINING_PATTERN_DISABLE
:
3212 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
3215 case DP_TRAINING_PATTERN_1
:
3216 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
3218 case DP_TRAINING_PATTERN_2
:
3219 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
3221 case DP_TRAINING_PATTERN_3
:
3222 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
3224 case DP_TRAINING_PATTERN_4
:
3225 temp
|= DP_TP_CTL_LINK_TRAIN_PAT4
;
3228 I915_WRITE(DP_TP_CTL(port
), temp
);
3230 } else if ((IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) ||
3231 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3232 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3234 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3235 case DP_TRAINING_PATTERN_DISABLE
:
3236 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
3238 case DP_TRAINING_PATTERN_1
:
3239 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
3241 case DP_TRAINING_PATTERN_2
:
3242 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3244 case DP_TRAINING_PATTERN_3
:
3245 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3246 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3251 *DP
&= ~DP_LINK_TRAIN_MASK
;
3253 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3254 case DP_TRAINING_PATTERN_DISABLE
:
3255 *DP
|= DP_LINK_TRAIN_OFF
;
3257 case DP_TRAINING_PATTERN_1
:
3258 *DP
|= DP_LINK_TRAIN_PAT_1
;
3260 case DP_TRAINING_PATTERN_2
:
3261 *DP
|= DP_LINK_TRAIN_PAT_2
;
3263 case DP_TRAINING_PATTERN_3
:
3264 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3265 *DP
|= DP_LINK_TRAIN_PAT_2
;
3271 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
3272 const struct intel_crtc_state
*old_crtc_state
)
3274 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3276 /* enable with pattern 1 (as per spec) */
3278 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
3281 * Magic for VLV/CHV. We _must_ first set up the register
3282 * without actually enabling the port, and then do another
3283 * write to enable the port. Otherwise link training will
3284 * fail when the power sequencer is freshly used for this port.
3286 intel_dp
->DP
|= DP_PORT_EN
;
3287 if (old_crtc_state
->has_audio
)
3288 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
3290 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3291 POSTING_READ(intel_dp
->output_reg
);
3294 static void intel_enable_dp(struct intel_encoder
*encoder
,
3295 const struct intel_crtc_state
*pipe_config
,
3296 const struct drm_connector_state
*conn_state
)
3298 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3299 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3300 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
3301 u32 dp_reg
= I915_READ(intel_dp
->output_reg
);
3302 enum pipe pipe
= crtc
->pipe
;
3303 intel_wakeref_t wakeref
;
3305 if (WARN_ON(dp_reg
& DP_PORT_EN
))
3308 with_pps_lock(intel_dp
, wakeref
) {
3309 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3310 vlv_init_panel_power_sequencer(encoder
, pipe_config
);
3312 intel_dp_enable_port(intel_dp
, pipe_config
);
3314 edp_panel_vdd_on(intel_dp
);
3315 edp_panel_on(intel_dp
);
3316 edp_panel_vdd_off(intel_dp
, true);
3319 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3320 unsigned int lane_mask
= 0x0;
3322 if (IS_CHERRYVIEW(dev_priv
))
3323 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
3325 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
3329 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
3330 intel_dp_start_link_train(intel_dp
);
3331 intel_dp_stop_link_train(intel_dp
);
3333 if (pipe_config
->has_audio
) {
3334 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3336 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
3340 static void g4x_enable_dp(struct intel_encoder
*encoder
,
3341 const struct intel_crtc_state
*pipe_config
,
3342 const struct drm_connector_state
*conn_state
)
3344 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3345 intel_edp_backlight_on(pipe_config
, conn_state
);
3348 static void vlv_enable_dp(struct intel_encoder
*encoder
,
3349 const struct intel_crtc_state
*pipe_config
,
3350 const struct drm_connector_state
*conn_state
)
3352 intel_edp_backlight_on(pipe_config
, conn_state
);
3355 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
3356 const struct intel_crtc_state
*pipe_config
,
3357 const struct drm_connector_state
*conn_state
)
3359 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3360 enum port port
= encoder
->port
;
3362 intel_dp_prepare(encoder
, pipe_config
);
3364 /* Only ilk+ has port A */
3366 ironlake_edp_pll_on(intel_dp
, pipe_config
);
3369 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
3371 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3372 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
3373 enum pipe pipe
= intel_dp
->pps_pipe
;
3374 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
3376 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3378 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
3381 edp_panel_vdd_off_sync(intel_dp
);
3384 * VLV seems to get confused when multiple power sequencers
3385 * have the same port selected (even if only one has power/vdd
3386 * enabled). The failure manifests as vlv_wait_port_ready() failing
3387 * CHV on the other hand doesn't seem to mind having the same port
3388 * selected in multiple power sequencers, but let's clear the
3389 * port select always when logically disconnecting a power sequencer
3392 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3393 pipe_name(pipe
), port_name(intel_dig_port
->base
.port
));
3394 I915_WRITE(pp_on_reg
, 0);
3395 POSTING_READ(pp_on_reg
);
3397 intel_dp
->pps_pipe
= INVALID_PIPE
;
3400 static void vlv_steal_power_sequencer(struct drm_i915_private
*dev_priv
,
3403 struct intel_encoder
*encoder
;
3405 lockdep_assert_held(&dev_priv
->pps_mutex
);
3407 for_each_intel_dp(&dev_priv
->drm
, encoder
) {
3408 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3409 enum port port
= encoder
->port
;
3411 WARN(intel_dp
->active_pipe
== pipe
,
3412 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3413 pipe_name(pipe
), port_name(port
));
3415 if (intel_dp
->pps_pipe
!= pipe
)
3418 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3419 pipe_name(pipe
), port_name(port
));
3421 /* make sure vdd is off before we steal it */
3422 vlv_detach_power_sequencer(intel_dp
);
3426 static void vlv_init_panel_power_sequencer(struct intel_encoder
*encoder
,
3427 const struct intel_crtc_state
*crtc_state
)
3429 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3430 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3431 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3433 lockdep_assert_held(&dev_priv
->pps_mutex
);
3435 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3437 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3438 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3440 * If another power sequencer was being used on this
3441 * port previously make sure to turn off vdd there while
3442 * we still have control of it.
3444 vlv_detach_power_sequencer(intel_dp
);
3448 * We may be stealing the power
3449 * sequencer from another port.
3451 vlv_steal_power_sequencer(dev_priv
, crtc
->pipe
);
3453 intel_dp
->active_pipe
= crtc
->pipe
;
3455 if (!intel_dp_is_edp(intel_dp
))
3458 /* now it's all ours */
3459 intel_dp
->pps_pipe
= crtc
->pipe
;
3461 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3462 pipe_name(intel_dp
->pps_pipe
), port_name(encoder
->port
));
3464 /* init power sequencer on this pipe and port */
3465 intel_dp_init_panel_power_sequencer(intel_dp
);
3466 intel_dp_init_panel_power_sequencer_registers(intel_dp
, true);
3469 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3470 const struct intel_crtc_state
*pipe_config
,
3471 const struct drm_connector_state
*conn_state
)
3473 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
3475 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3478 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3479 const struct intel_crtc_state
*pipe_config
,
3480 const struct drm_connector_state
*conn_state
)
3482 intel_dp_prepare(encoder
, pipe_config
);
3484 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
3487 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3488 const struct intel_crtc_state
*pipe_config
,
3489 const struct drm_connector_state
*conn_state
)
3491 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
3493 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3495 /* Second common lane will stay alive on its own now */
3496 chv_phy_release_cl2_override(encoder
);
3499 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3500 const struct intel_crtc_state
*pipe_config
,
3501 const struct drm_connector_state
*conn_state
)
3503 intel_dp_prepare(encoder
, pipe_config
);
3505 chv_phy_pre_pll_enable(encoder
, pipe_config
);
3508 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3509 const struct intel_crtc_state
*old_crtc_state
,
3510 const struct drm_connector_state
*old_conn_state
)
3512 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
3516 * Fetch AUX CH registers 0x202 - 0x207 which contain
3517 * link status information
3520 intel_dp_get_link_status(struct intel_dp
*intel_dp
, u8 link_status
[DP_LINK_STATUS_SIZE
])
3522 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3523 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3526 /* These are source-specific values. */
3528 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3530 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3531 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3532 enum port port
= encoder
->port
;
3534 if (HAS_DDI(dev_priv
))
3535 return intel_ddi_dp_voltage_max(encoder
);
3536 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3537 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3538 else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
)
3539 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3540 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3541 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3543 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3547 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, u8 voltage_swing
)
3549 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3550 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3551 enum port port
= encoder
->port
;
3553 if (HAS_DDI(dev_priv
)) {
3554 return intel_ddi_dp_pre_emphasis_max(encoder
, voltage_swing
);
3555 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3556 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3557 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3558 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3559 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3560 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3561 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3562 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3565 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3567 } else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
3568 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3569 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3570 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3571 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3572 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3573 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3575 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3578 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3579 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3580 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3581 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3582 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3583 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3584 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3585 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3587 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3592 static u32
vlv_signal_levels(struct intel_dp
*intel_dp
)
3594 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3595 unsigned long demph_reg_value
, preemph_reg_value
,
3596 uniqtranscale_reg_value
;
3597 u8 train_set
= intel_dp
->train_set
[0];
3599 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3600 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3601 preemph_reg_value
= 0x0004000;
3602 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3603 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3604 demph_reg_value
= 0x2B405555;
3605 uniqtranscale_reg_value
= 0x552AB83A;
3607 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3608 demph_reg_value
= 0x2B404040;
3609 uniqtranscale_reg_value
= 0x5548B83A;
3611 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3612 demph_reg_value
= 0x2B245555;
3613 uniqtranscale_reg_value
= 0x5560B83A;
3615 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3616 demph_reg_value
= 0x2B405555;
3617 uniqtranscale_reg_value
= 0x5598DA3A;
3623 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3624 preemph_reg_value
= 0x0002000;
3625 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3626 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3627 demph_reg_value
= 0x2B404040;
3628 uniqtranscale_reg_value
= 0x5552B83A;
3630 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3631 demph_reg_value
= 0x2B404848;
3632 uniqtranscale_reg_value
= 0x5580B83A;
3634 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3635 demph_reg_value
= 0x2B404040;
3636 uniqtranscale_reg_value
= 0x55ADDA3A;
3642 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3643 preemph_reg_value
= 0x0000000;
3644 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3645 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3646 demph_reg_value
= 0x2B305555;
3647 uniqtranscale_reg_value
= 0x5570B83A;
3649 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3650 demph_reg_value
= 0x2B2B4040;
3651 uniqtranscale_reg_value
= 0x55ADDA3A;
3657 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3658 preemph_reg_value
= 0x0006000;
3659 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3660 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3661 demph_reg_value
= 0x1B405555;
3662 uniqtranscale_reg_value
= 0x55ADDA3A;
3672 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3673 uniqtranscale_reg_value
, 0);
3678 static u32
chv_signal_levels(struct intel_dp
*intel_dp
)
3680 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3681 u32 deemph_reg_value
, margin_reg_value
;
3682 bool uniq_trans_scale
= false;
3683 u8 train_set
= intel_dp
->train_set
[0];
3685 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3686 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3687 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3688 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3689 deemph_reg_value
= 128;
3690 margin_reg_value
= 52;
3692 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3693 deemph_reg_value
= 128;
3694 margin_reg_value
= 77;
3696 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3697 deemph_reg_value
= 128;
3698 margin_reg_value
= 102;
3700 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3701 deemph_reg_value
= 128;
3702 margin_reg_value
= 154;
3703 uniq_trans_scale
= true;
3709 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3710 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3711 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3712 deemph_reg_value
= 85;
3713 margin_reg_value
= 78;
3715 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3716 deemph_reg_value
= 85;
3717 margin_reg_value
= 116;
3719 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3720 deemph_reg_value
= 85;
3721 margin_reg_value
= 154;
3727 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3728 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3729 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3730 deemph_reg_value
= 64;
3731 margin_reg_value
= 104;
3733 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3734 deemph_reg_value
= 64;
3735 margin_reg_value
= 154;
3741 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3742 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3743 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3744 deemph_reg_value
= 43;
3745 margin_reg_value
= 154;
3755 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3756 margin_reg_value
, uniq_trans_scale
);
3762 g4x_signal_levels(u8 train_set
)
3764 u32 signal_levels
= 0;
3766 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3767 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3769 signal_levels
|= DP_VOLTAGE_0_4
;
3771 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3772 signal_levels
|= DP_VOLTAGE_0_6
;
3774 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3775 signal_levels
|= DP_VOLTAGE_0_8
;
3777 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3778 signal_levels
|= DP_VOLTAGE_1_2
;
3781 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3782 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3784 signal_levels
|= DP_PRE_EMPHASIS_0
;
3786 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3787 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3789 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3790 signal_levels
|= DP_PRE_EMPHASIS_6
;
3792 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3793 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3796 return signal_levels
;
3799 /* SNB CPU eDP voltage swing and pre-emphasis control */
3801 snb_cpu_edp_signal_levels(u8 train_set
)
3803 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3804 DP_TRAIN_PRE_EMPHASIS_MASK
);
3805 switch (signal_levels
) {
3806 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3807 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3808 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3809 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3810 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3811 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3812 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3813 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3814 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3815 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3816 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3817 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3818 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3819 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3821 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3822 "0x%x\n", signal_levels
);
3823 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3827 /* IVB CPU eDP voltage swing and pre-emphasis control */
3829 ivb_cpu_edp_signal_levels(u8 train_set
)
3831 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3832 DP_TRAIN_PRE_EMPHASIS_MASK
);
3833 switch (signal_levels
) {
3834 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3835 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3836 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3837 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3838 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3839 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3841 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3842 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3843 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3844 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3846 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3847 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3849 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3852 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3853 "0x%x\n", signal_levels
);
3854 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3859 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3861 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3862 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3863 enum port port
= intel_dig_port
->base
.port
;
3864 u32 signal_levels
, mask
= 0;
3865 u8 train_set
= intel_dp
->train_set
[0];
3867 if (IS_GEN9_LP(dev_priv
) || INTEL_GEN(dev_priv
) >= 10) {
3868 signal_levels
= bxt_signal_levels(intel_dp
);
3869 } else if (HAS_DDI(dev_priv
)) {
3870 signal_levels
= ddi_signal_levels(intel_dp
);
3871 mask
= DDI_BUF_EMP_MASK
;
3872 } else if (IS_CHERRYVIEW(dev_priv
)) {
3873 signal_levels
= chv_signal_levels(intel_dp
);
3874 } else if (IS_VALLEYVIEW(dev_priv
)) {
3875 signal_levels
= vlv_signal_levels(intel_dp
);
3876 } else if (IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) {
3877 signal_levels
= ivb_cpu_edp_signal_levels(train_set
);
3878 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3879 } else if (IS_GEN(dev_priv
, 6) && port
== PORT_A
) {
3880 signal_levels
= snb_cpu_edp_signal_levels(train_set
);
3881 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3883 signal_levels
= g4x_signal_levels(train_set
);
3884 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3888 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3890 DRM_DEBUG_KMS("Using vswing level %d\n",
3891 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3892 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3893 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3894 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3896 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3898 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3899 POSTING_READ(intel_dp
->output_reg
);
3903 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3906 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3907 struct drm_i915_private
*dev_priv
=
3908 to_i915(intel_dig_port
->base
.base
.dev
);
3910 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3912 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3913 POSTING_READ(intel_dp
->output_reg
);
3916 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3918 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
3919 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3920 enum port port
= intel_dig_port
->base
.port
;
3923 if (!HAS_DDI(dev_priv
))
3926 val
= I915_READ(DP_TP_CTL(port
));
3927 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3928 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3929 I915_WRITE(DP_TP_CTL(port
), val
);
3932 * On PORT_A we can have only eDP in SST mode. There the only reason
3933 * we need to set idle transmission mode is to work around a HW issue
3934 * where we enable the pipe while not in idle link-training mode.
3935 * In this case there is requirement to wait for a minimum number of
3936 * idle patterns to be sent.
3941 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3942 DP_TP_STATUS_IDLE_DONE
,
3943 DP_TP_STATUS_IDLE_DONE
,
3945 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3949 intel_dp_link_down(struct intel_encoder
*encoder
,
3950 const struct intel_crtc_state
*old_crtc_state
)
3952 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3953 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
3954 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
3955 enum port port
= encoder
->port
;
3956 u32 DP
= intel_dp
->DP
;
3958 if (WARN_ON(HAS_DDI(dev_priv
)))
3961 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3964 DRM_DEBUG_KMS("\n");
3966 if ((IS_IVYBRIDGE(dev_priv
) && port
== PORT_A
) ||
3967 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3968 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3969 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3971 DP
&= ~DP_LINK_TRAIN_MASK
;
3972 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3974 I915_WRITE(intel_dp
->output_reg
, DP
);
3975 POSTING_READ(intel_dp
->output_reg
);
3977 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3978 I915_WRITE(intel_dp
->output_reg
, DP
);
3979 POSTING_READ(intel_dp
->output_reg
);
3982 * HW workaround for IBX, we need to move the port
3983 * to transcoder A after disabling it to allow the
3984 * matching HDMI port to be enabled on transcoder A.
3986 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3988 * We get CPU/PCH FIFO underruns on the other pipe when
3989 * doing the workaround. Sweep them under the rug.
3991 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3992 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3994 /* always enable with pattern 1 (as per spec) */
3995 DP
&= ~(DP_PIPE_SEL_MASK
| DP_LINK_TRAIN_MASK
);
3996 DP
|= DP_PORT_EN
| DP_PIPE_SEL(PIPE_A
) |
3997 DP_LINK_TRAIN_PAT_1
;
3998 I915_WRITE(intel_dp
->output_reg
, DP
);
3999 POSTING_READ(intel_dp
->output_reg
);
4002 I915_WRITE(intel_dp
->output_reg
, DP
);
4003 POSTING_READ(intel_dp
->output_reg
);
4005 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
4006 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
4007 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
4010 msleep(intel_dp
->panel_power_down_delay
);
4014 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
4015 intel_wakeref_t wakeref
;
4017 with_pps_lock(intel_dp
, wakeref
)
4018 intel_dp
->active_pipe
= INVALID_PIPE
;
4023 intel_dp_extended_receiver_capabilities(struct intel_dp
*intel_dp
)
4028 * Prior to DP1.3 the bit represented by
4029 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4030 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4031 * the true capability of the panel. The only way to check is to
4032 * then compare 0000h and 2200h.
4034 if (!(intel_dp
->dpcd
[DP_TRAINING_AUX_RD_INTERVAL
] &
4035 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT
))
4038 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DP13_DPCD_REV
,
4039 &dpcd_ext
, sizeof(dpcd_ext
)) != sizeof(dpcd_ext
)) {
4040 DRM_ERROR("DPCD failed read at extended capabilities\n");
4044 if (intel_dp
->dpcd
[DP_DPCD_REV
] > dpcd_ext
[DP_DPCD_REV
]) {
4045 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4049 if (!memcmp(intel_dp
->dpcd
, dpcd_ext
, sizeof(dpcd_ext
)))
4052 DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4053 (int)sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
4055 memcpy(intel_dp
->dpcd
, dpcd_ext
, sizeof(dpcd_ext
));
4059 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
4061 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
4062 sizeof(intel_dp
->dpcd
)) < 0)
4063 return false; /* aux transfer failed */
4065 intel_dp_extended_receiver_capabilities(intel_dp
);
4067 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
4069 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
4072 static void intel_dp_get_dsc_sink_cap(struct intel_dp
*intel_dp
)
4075 * Clear the cached register set to avoid using stale values
4076 * for the sinks that do not support DSC.
4078 memset(intel_dp
->dsc_dpcd
, 0, sizeof(intel_dp
->dsc_dpcd
));
4080 /* Clear fec_capable to avoid using stale values */
4081 intel_dp
->fec_capable
= 0;
4083 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4084 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x14 ||
4085 intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
4086 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DSC_SUPPORT
,
4088 sizeof(intel_dp
->dsc_dpcd
)) < 0)
4089 DRM_ERROR("Failed to read DPCD register 0x%x\n",
4092 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4093 (int)sizeof(intel_dp
->dsc_dpcd
),
4094 intel_dp
->dsc_dpcd
);
4096 /* FEC is supported only on DP 1.4 */
4097 if (!intel_dp_is_edp(intel_dp
) &&
4098 drm_dp_dpcd_readb(&intel_dp
->aux
, DP_FEC_CAPABILITY
,
4099 &intel_dp
->fec_capable
) < 0)
4100 DRM_ERROR("Failed to read FEC DPCD register\n");
4102 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp
->fec_capable
);
4107 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
4109 struct drm_i915_private
*dev_priv
=
4110 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
4112 /* this function is meant to be called only once */
4113 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
4115 if (!intel_dp_read_dpcd(intel_dp
))
4118 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4119 drm_dp_is_branch(intel_dp
->dpcd
));
4121 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4122 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4123 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4126 * Read the eDP display control registers.
4128 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4129 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4130 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4131 * method). The display control registers should read zero if they're
4132 * not supported anyway.
4134 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
4135 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
4136 sizeof(intel_dp
->edp_dpcd
))
4137 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
4138 intel_dp
->edp_dpcd
);
4141 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4142 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4144 intel_psr_init_dpcd(intel_dp
);
4146 /* Read the eDP 1.4+ supported link rates. */
4147 if (intel_dp
->edp_dpcd
[0] >= DP_EDP_14
) {
4148 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
4151 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
4152 sink_rates
, sizeof(sink_rates
));
4154 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
4155 int val
= le16_to_cpu(sink_rates
[i
]);
4160 /* Value read multiplied by 200kHz gives the per-lane
4161 * link rate in kHz. The source rates are, however,
4162 * stored in terms of LS_Clk kHz. The full conversion
4163 * back to symbols is
4164 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4166 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
4168 intel_dp
->num_sink_rates
= i
;
4172 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4173 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4175 if (intel_dp
->num_sink_rates
)
4176 intel_dp
->use_rate_select
= true;
4178 intel_dp_set_sink_rates(intel_dp
);
4180 intel_dp_set_common_rates(intel_dp
);
4182 /* Read the eDP DSC DPCD registers */
4183 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
4184 intel_dp_get_dsc_sink_cap(intel_dp
);
4191 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
4193 if (!intel_dp_read_dpcd(intel_dp
))
4196 /* Don't clobber cached eDP rates. */
4197 if (!intel_dp_is_edp(intel_dp
)) {
4198 intel_dp_set_sink_rates(intel_dp
);
4199 intel_dp_set_common_rates(intel_dp
);
4203 * Some eDP panels do not set a valid value for sink count, that is why
4204 * it don't care about read it here and in intel_edp_init_dpcd().
4206 if (!intel_dp_is_edp(intel_dp
)) {
4210 r
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &count
);
4215 * Sink count can change between short pulse hpd hence
4216 * a member variable in intel_dp will track any changes
4217 * between short pulse interrupts.
4219 intel_dp
->sink_count
= DP_GET_SINK_COUNT(count
);
4222 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4223 * a dongle is present but no display. Unless we require to know
4224 * if a dongle is present or not, we don't need to update
4225 * downstream port information. So, an early return here saves
4226 * time from performing other operations which are not required.
4228 if (!intel_dp
->sink_count
)
4232 if (!drm_dp_is_branch(intel_dp
->dpcd
))
4233 return true; /* native DP sink */
4235 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
4236 return true; /* no per-port downstream info */
4238 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
4239 intel_dp
->downstream_ports
,
4240 DP_MAX_DOWNSTREAM_PORTS
) < 0)
4241 return false; /* downstream port status fetch failed */
4247 intel_dp_sink_can_mst(struct intel_dp
*intel_dp
)
4251 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
4254 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
4257 return mstm_cap
& DP_MST_CAP
;
4261 intel_dp_can_mst(struct intel_dp
*intel_dp
)
4263 return i915_modparams
.enable_dp_mst
&&
4264 intel_dp
->can_mst
&&
4265 intel_dp_sink_can_mst(intel_dp
);
4269 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
4271 struct intel_encoder
*encoder
=
4272 &dp_to_dig_port(intel_dp
)->base
;
4273 bool sink_can_mst
= intel_dp_sink_can_mst(intel_dp
);
4275 DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4276 port_name(encoder
->port
), yesno(intel_dp
->can_mst
),
4277 yesno(sink_can_mst
), yesno(i915_modparams
.enable_dp_mst
));
4279 if (!intel_dp
->can_mst
)
4282 intel_dp
->is_mst
= sink_can_mst
&&
4283 i915_modparams
.enable_dp_mst
;
4285 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4290 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4292 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT_ESI
,
4293 sink_irq_vector
, DP_DPRX_ESI_LEN
) ==
4297 u16
intel_dp_dsc_get_output_bpp(int link_clock
, u8 lane_count
,
4298 int mode_clock
, int mode_hdisplay
)
4300 u16 bits_per_pixel
, max_bpp_small_joiner_ram
;
4304 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4305 * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4306 * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4307 * for MST -> TimeSlotsPerMTP has to be calculated
4309 bits_per_pixel
= (link_clock
* lane_count
* 8 *
4310 DP_DSC_FEC_OVERHEAD_FACTOR
) /
4313 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4314 max_bpp_small_joiner_ram
= DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER
/
4318 * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4319 * check, output bpp from small joiner RAM check)
4321 bits_per_pixel
= min(bits_per_pixel
, max_bpp_small_joiner_ram
);
4323 /* Error out if the max bpp is less than smallest allowed valid bpp */
4324 if (bits_per_pixel
< valid_dsc_bpp
[0]) {
4325 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel
);
4329 /* Find the nearest match in the array of known BPPs from VESA */
4330 for (i
= 0; i
< ARRAY_SIZE(valid_dsc_bpp
) - 1; i
++) {
4331 if (bits_per_pixel
< valid_dsc_bpp
[i
+ 1])
4334 bits_per_pixel
= valid_dsc_bpp
[i
];
4337 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4338 * fractional part is 0
4340 return bits_per_pixel
<< 4;
4343 u8
intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp
,
4347 u8 min_slice_count
, i
;
4348 int max_slice_width
;
4350 if (mode_clock
<= DP_DSC_PEAK_PIXEL_RATE
)
4351 min_slice_count
= DIV_ROUND_UP(mode_clock
,
4352 DP_DSC_MAX_ENC_THROUGHPUT_0
);
4354 min_slice_count
= DIV_ROUND_UP(mode_clock
,
4355 DP_DSC_MAX_ENC_THROUGHPUT_1
);
4357 max_slice_width
= drm_dp_dsc_sink_max_slice_width(intel_dp
->dsc_dpcd
);
4358 if (max_slice_width
< DP_DSC_MIN_SLICE_WIDTH_VALUE
) {
4359 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4363 /* Also take into account max slice width */
4364 min_slice_count
= min_t(u8
, min_slice_count
,
4365 DIV_ROUND_UP(mode_hdisplay
,
4368 /* Find the closest match to the valid slice count values */
4369 for (i
= 0; i
< ARRAY_SIZE(valid_dsc_slicecount
); i
++) {
4370 if (valid_dsc_slicecount
[i
] >
4371 drm_dp_dsc_sink_max_slice_count(intel_dp
->dsc_dpcd
,
4374 if (min_slice_count
<= valid_dsc_slicecount
[i
])
4375 return valid_dsc_slicecount
[i
];
4378 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count
);
4382 static u8
intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4386 u8 test_lane_count
, test_link_bw
;
4390 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4391 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4395 DRM_DEBUG_KMS("Lane count read failed\n");
4398 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4400 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4403 DRM_DEBUG_KMS("Link Rate read failed\n");
4406 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4408 /* Validate the requested link rate and lane count */
4409 if (!intel_dp_link_params_valid(intel_dp
, test_link_rate
,
4413 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4414 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4419 static u8
intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4423 __be16 h_width
, v_height
;
4426 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4427 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4430 DRM_DEBUG_KMS("Test pattern read failed\n");
4433 if (test_pattern
!= DP_COLOR_RAMP
)
4436 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4439 DRM_DEBUG_KMS("H Width read failed\n");
4443 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4446 DRM_DEBUG_KMS("V Height read failed\n");
4450 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4453 DRM_DEBUG_KMS("TEST MISC read failed\n");
4456 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4458 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4460 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4461 case DP_TEST_BIT_DEPTH_6
:
4462 intel_dp
->compliance
.test_data
.bpc
= 6;
4464 case DP_TEST_BIT_DEPTH_8
:
4465 intel_dp
->compliance
.test_data
.bpc
= 8;
4471 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4472 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4473 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4474 /* Set test active flag here so userspace doesn't interrupt things */
4475 intel_dp
->compliance
.test_active
= 1;
4480 static u8
intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4482 u8 test_result
= DP_TEST_ACK
;
4483 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4484 struct drm_connector
*connector
= &intel_connector
->base
;
4486 if (intel_connector
->detect_edid
== NULL
||
4487 connector
->edid_corrupt
||
4488 intel_dp
->aux
.i2c_defer_count
> 6) {
4489 /* Check EDID read for NACKs, DEFERs and corruption
4490 * (DP CTS 1.2 Core r1.1)
4491 * 4.2.2.4 : Failed EDID read, I2C_NAK
4492 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4493 * 4.2.2.6 : EDID corruption detected
4494 * Use failsafe mode for all cases
4496 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4497 intel_dp
->aux
.i2c_defer_count
> 0)
4498 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4499 intel_dp
->aux
.i2c_nack_count
,
4500 intel_dp
->aux
.i2c_defer_count
);
4501 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4503 struct edid
*block
= intel_connector
->detect_edid
;
4505 /* We have to write the checksum
4506 * of the last block read
4508 block
+= intel_connector
->detect_edid
->extensions
;
4510 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4511 block
->checksum
) <= 0)
4512 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4514 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4515 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4518 /* Set test active flag here so userspace doesn't interrupt things */
4519 intel_dp
->compliance
.test_active
= 1;
4524 static u8
intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4526 u8 test_result
= DP_TEST_NAK
;
4530 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4532 u8 response
= DP_TEST_NAK
;
4536 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4538 DRM_DEBUG_KMS("Could not read test request from sink\n");
4543 case DP_TEST_LINK_TRAINING
:
4544 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4545 response
= intel_dp_autotest_link_training(intel_dp
);
4547 case DP_TEST_LINK_VIDEO_PATTERN
:
4548 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4549 response
= intel_dp_autotest_video_pattern(intel_dp
);
4551 case DP_TEST_LINK_EDID_READ
:
4552 DRM_DEBUG_KMS("EDID test requested\n");
4553 response
= intel_dp_autotest_edid(intel_dp
);
4555 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4556 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4557 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4560 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4564 if (response
& DP_TEST_ACK
)
4565 intel_dp
->compliance
.test_type
= request
;
4568 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4570 DRM_DEBUG_KMS("Could not write test response to sink\n");
4574 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4578 if (intel_dp
->is_mst
) {
4579 u8 esi
[DP_DPRX_ESI_LEN
] = { 0 };
4584 WARN_ON_ONCE(intel_dp
->active_mst_links
< 0);
4585 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4589 /* check link status - esi[10] = 0x200c */
4590 if (intel_dp
->active_mst_links
> 0 &&
4591 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4592 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4593 intel_dp_start_link_train(intel_dp
);
4594 intel_dp_stop_link_train(intel_dp
);
4597 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4598 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4601 for (retry
= 0; retry
< 3; retry
++) {
4603 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4604 DP_SINK_COUNT_ESI
+1,
4611 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4613 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4621 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4622 intel_dp
->is_mst
= false;
4623 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4631 intel_dp_needs_link_retrain(struct intel_dp
*intel_dp
)
4633 u8 link_status
[DP_LINK_STATUS_SIZE
];
4635 if (!intel_dp
->link_trained
)
4639 * While PSR source HW is enabled, it will control main-link sending
4640 * frames, enabling and disabling it so trying to do a retrain will fail
4641 * as the link would or not be on or it could mix training patterns
4642 * and frame data at the same time causing retrain to fail.
4643 * Also when exiting PSR, HW will retrain the link anyways fixing
4644 * any link status error.
4646 if (intel_psr_enabled(intel_dp
))
4649 if (!intel_dp_get_link_status(intel_dp
, link_status
))
4653 * Validate the cached values of intel_dp->link_rate and
4654 * intel_dp->lane_count before attempting to retrain.
4656 if (!intel_dp_link_params_valid(intel_dp
, intel_dp
->link_rate
,
4657 intel_dp
->lane_count
))
4660 /* Retrain if Channel EQ or CR not ok */
4661 return !drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
);
4664 int intel_dp_retrain_link(struct intel_encoder
*encoder
,
4665 struct drm_modeset_acquire_ctx
*ctx
)
4667 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4668 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
4669 struct intel_connector
*connector
= intel_dp
->attached_connector
;
4670 struct drm_connector_state
*conn_state
;
4671 struct intel_crtc_state
*crtc_state
;
4672 struct intel_crtc
*crtc
;
4675 /* FIXME handle the MST connectors as well */
4677 if (!connector
|| connector
->base
.status
!= connector_status_connected
)
4680 ret
= drm_modeset_lock(&dev_priv
->drm
.mode_config
.connection_mutex
,
4685 conn_state
= connector
->base
.state
;
4687 crtc
= to_intel_crtc(conn_state
->crtc
);
4691 ret
= drm_modeset_lock(&crtc
->base
.mutex
, ctx
);
4695 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
4697 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state
));
4699 if (!crtc_state
->base
.active
)
4702 if (conn_state
->commit
&&
4703 !try_wait_for_completion(&conn_state
->commit
->hw_done
))
4706 if (!intel_dp_needs_link_retrain(intel_dp
))
4709 /* Suppress underruns caused by re-training */
4710 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4711 if (crtc_state
->has_pch_encoder
)
4712 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4713 intel_crtc_pch_transcoder(crtc
), false);
4715 intel_dp_start_link_train(intel_dp
);
4716 intel_dp_stop_link_train(intel_dp
);
4718 /* Keep underrun reporting disabled until things are stable */
4719 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4721 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4722 if (crtc_state
->has_pch_encoder
)
4723 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4724 intel_crtc_pch_transcoder(crtc
), true);
4730 * If display is now connected check links status,
4731 * there has been known issues of link loss triggering
4734 * Some sinks (eg. ASUS PB287Q) seem to perform some
4735 * weird HPD ping pong during modesets. So we can apparently
4736 * end up with HPD going low during a modeset, and then
4737 * going back up soon after. And once that happens we must
4738 * retrain the link to get a picture. That's in case no
4739 * userspace component reacted to intermittent HPD dip.
4741 static bool intel_dp_hotplug(struct intel_encoder
*encoder
,
4742 struct intel_connector
*connector
)
4744 struct drm_modeset_acquire_ctx ctx
;
4748 changed
= intel_encoder_hotplug(encoder
, connector
);
4750 drm_modeset_acquire_init(&ctx
, 0);
4753 ret
= intel_dp_retrain_link(encoder
, &ctx
);
4755 if (ret
== -EDEADLK
) {
4756 drm_modeset_backoff(&ctx
);
4763 drm_modeset_drop_locks(&ctx
);
4764 drm_modeset_acquire_fini(&ctx
);
4765 WARN(ret
, "Acquiring modeset locks failed with %i\n", ret
);
4770 static void intel_dp_check_service_irq(struct intel_dp
*intel_dp
)
4774 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
4777 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4778 DP_DEVICE_SERVICE_IRQ_VECTOR
, &val
) != 1 || !val
)
4781 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
, val
);
4783 if (val
& DP_AUTOMATED_TEST_REQUEST
)
4784 intel_dp_handle_test_request(intel_dp
);
4786 if (val
& DP_CP_IRQ
)
4787 intel_hdcp_handle_cp_irq(intel_dp
->attached_connector
);
4789 if (val
& DP_SINK_SPECIFIC_IRQ
)
4790 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4794 * According to DP spec
4797 * 2. Configure link according to Receiver Capabilities
4798 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4799 * 4. Check link status on receipt of hot-plug interrupt
4801 * intel_dp_short_pulse - handles short pulse interrupts
4802 * when full detection is not required.
4803 * Returns %true if short pulse is handled and full detection
4804 * is NOT required and %false otherwise.
4807 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4809 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
4810 u8 old_sink_count
= intel_dp
->sink_count
;
4814 * Clearing compliance test variables to allow capturing
4815 * of values for next automated test request.
4817 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4820 * Now read the DPCD to see if it's actually running
4821 * If the current value of sink count doesn't match with
4822 * the value that was stored earlier or dpcd read failed
4823 * we need to do full detection
4825 ret
= intel_dp_get_dpcd(intel_dp
);
4827 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4828 /* No need to proceed if we are going to do full detect */
4832 intel_dp_check_service_irq(intel_dp
);
4834 /* Handle CEC interrupts, if any */
4835 drm_dp_cec_irq(&intel_dp
->aux
);
4837 /* defer to the hotplug work for link retraining if needed */
4838 if (intel_dp_needs_link_retrain(intel_dp
))
4841 intel_psr_short_pulse(intel_dp
);
4843 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4844 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4845 /* Send a Hotplug Uevent to userspace to start modeset */
4846 drm_kms_helper_hotplug_event(&dev_priv
->drm
);
4852 /* XXX this is probably wrong for multiple downstream ports */
4853 static enum drm_connector_status
4854 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4856 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4857 u8
*dpcd
= intel_dp
->dpcd
;
4861 lspcon_resume(lspcon
);
4863 if (!intel_dp_get_dpcd(intel_dp
))
4864 return connector_status_disconnected
;
4866 if (intel_dp_is_edp(intel_dp
))
4867 return connector_status_connected
;
4869 /* if there's no downstream port, we're done */
4870 if (!drm_dp_is_branch(dpcd
))
4871 return connector_status_connected
;
4873 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4874 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4875 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4877 return intel_dp
->sink_count
?
4878 connector_status_connected
: connector_status_disconnected
;
4881 if (intel_dp_can_mst(intel_dp
))
4882 return connector_status_connected
;
4884 /* If no HPD, poke DDC gently */
4885 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4886 return connector_status_connected
;
4888 /* Well we tried, say unknown for unreliable port types */
4889 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4890 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4891 if (type
== DP_DS_PORT_TYPE_VGA
||
4892 type
== DP_DS_PORT_TYPE_NON_EDID
)
4893 return connector_status_unknown
;
4895 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4896 DP_DWN_STRM_PORT_TYPE_MASK
;
4897 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4898 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4899 return connector_status_unknown
;
4902 /* Anything else is out of spec, warn and ignore */
4903 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4904 return connector_status_disconnected
;
4907 static enum drm_connector_status
4908 edp_detect(struct intel_dp
*intel_dp
)
4910 return connector_status_connected
;
4913 static bool ibx_digital_port_connected(struct intel_encoder
*encoder
)
4915 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4918 switch (encoder
->hpd_pin
) {
4920 bit
= SDE_PORTB_HOTPLUG
;
4923 bit
= SDE_PORTC_HOTPLUG
;
4926 bit
= SDE_PORTD_HOTPLUG
;
4929 MISSING_CASE(encoder
->hpd_pin
);
4933 return I915_READ(SDEISR
) & bit
;
4936 static bool cpt_digital_port_connected(struct intel_encoder
*encoder
)
4938 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4941 switch (encoder
->hpd_pin
) {
4943 bit
= SDE_PORTB_HOTPLUG_CPT
;
4946 bit
= SDE_PORTC_HOTPLUG_CPT
;
4949 bit
= SDE_PORTD_HOTPLUG_CPT
;
4952 MISSING_CASE(encoder
->hpd_pin
);
4956 return I915_READ(SDEISR
) & bit
;
4959 static bool spt_digital_port_connected(struct intel_encoder
*encoder
)
4961 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4964 switch (encoder
->hpd_pin
) {
4966 bit
= SDE_PORTA_HOTPLUG_SPT
;
4969 bit
= SDE_PORTE_HOTPLUG_SPT
;
4972 return cpt_digital_port_connected(encoder
);
4975 return I915_READ(SDEISR
) & bit
;
4978 static bool g4x_digital_port_connected(struct intel_encoder
*encoder
)
4980 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4983 switch (encoder
->hpd_pin
) {
4985 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4988 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4991 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4994 MISSING_CASE(encoder
->hpd_pin
);
4998 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
5001 static bool gm45_digital_port_connected(struct intel_encoder
*encoder
)
5003 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5006 switch (encoder
->hpd_pin
) {
5008 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
5011 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
5014 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
5017 MISSING_CASE(encoder
->hpd_pin
);
5021 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
5024 static bool ilk_digital_port_connected(struct intel_encoder
*encoder
)
5026 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5028 if (encoder
->hpd_pin
== HPD_PORT_A
)
5029 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
5031 return ibx_digital_port_connected(encoder
);
5034 static bool snb_digital_port_connected(struct intel_encoder
*encoder
)
5036 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5038 if (encoder
->hpd_pin
== HPD_PORT_A
)
5039 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
5041 return cpt_digital_port_connected(encoder
);
5044 static bool ivb_digital_port_connected(struct intel_encoder
*encoder
)
5046 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5048 if (encoder
->hpd_pin
== HPD_PORT_A
)
5049 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
5051 return cpt_digital_port_connected(encoder
);
5054 static bool bdw_digital_port_connected(struct intel_encoder
*encoder
)
5056 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5058 if (encoder
->hpd_pin
== HPD_PORT_A
)
5059 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
5061 return cpt_digital_port_connected(encoder
);
5064 static bool bxt_digital_port_connected(struct intel_encoder
*encoder
)
5066 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5069 switch (encoder
->hpd_pin
) {
5071 bit
= BXT_DE_PORT_HP_DDIA
;
5074 bit
= BXT_DE_PORT_HP_DDIB
;
5077 bit
= BXT_DE_PORT_HP_DDIC
;
5080 MISSING_CASE(encoder
->hpd_pin
);
5084 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
5087 static bool icl_combo_port_connected(struct drm_i915_private
*dev_priv
,
5088 struct intel_digital_port
*intel_dig_port
)
5090 enum port port
= intel_dig_port
->base
.port
;
5092 return I915_READ(SDEISR
) & SDE_DDI_HOTPLUG_ICP(port
);
5095 static const char *tc_type_name(enum tc_port_type type
)
5097 static const char * const names
[] = {
5098 [TC_PORT_UNKNOWN
] = "unknown",
5099 [TC_PORT_LEGACY
] = "legacy",
5100 [TC_PORT_TYPEC
] = "typec",
5101 [TC_PORT_TBT
] = "tbt",
5104 if (WARN_ON(type
>= ARRAY_SIZE(names
)))
5105 type
= TC_PORT_UNKNOWN
;
5110 static void icl_update_tc_port_type(struct drm_i915_private
*dev_priv
,
5111 struct intel_digital_port
*intel_dig_port
,
5112 bool is_legacy
, bool is_typec
, bool is_tbt
)
5114 enum port port
= intel_dig_port
->base
.port
;
5115 enum tc_port_type old_type
= intel_dig_port
->tc_type
;
5117 WARN_ON(is_legacy
+ is_typec
+ is_tbt
!= 1);
5120 intel_dig_port
->tc_type
= TC_PORT_LEGACY
;
5122 intel_dig_port
->tc_type
= TC_PORT_TYPEC
;
5124 intel_dig_port
->tc_type
= TC_PORT_TBT
;
5128 /* Types are not supposed to be changed at runtime. */
5129 WARN_ON(old_type
!= TC_PORT_UNKNOWN
&&
5130 old_type
!= intel_dig_port
->tc_type
);
5132 if (old_type
!= intel_dig_port
->tc_type
)
5133 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port
),
5134 tc_type_name(intel_dig_port
->tc_type
));
5138 * This function implements the first part of the Connect Flow described by our
5139 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5140 * lanes, EDID, etc) is done as needed in the typical places.
5142 * Unlike the other ports, type-C ports are not available to use as soon as we
5143 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5144 * display, USB, etc. As a result, handshaking through FIA is required around
5145 * connect and disconnect to cleanly transfer ownership with the controller and
5146 * set the type-C power state.
5148 * We could opt to only do the connect flow when we actually try to use the AUX
5149 * channels or do a modeset, then immediately run the disconnect flow after
5150 * usage, but there are some implications on this for a dynamic environment:
5151 * things may go away or change behind our backs. So for now our driver is
5152 * always trying to acquire ownership of the controller as soon as it gets an
5153 * interrupt (or polls state and sees a port is connected) and only gives it
5154 * back when it sees a disconnect. Implementation of a more fine-grained model
5155 * will require a lot of coordination with user space and thorough testing for
5156 * the extra possible cases.
5158 static bool icl_tc_phy_connect(struct drm_i915_private
*dev_priv
,
5159 struct intel_digital_port
*dig_port
)
5161 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, dig_port
->base
.port
);
5164 if (dig_port
->tc_type
!= TC_PORT_LEGACY
&&
5165 dig_port
->tc_type
!= TC_PORT_TYPEC
)
5168 val
= I915_READ(PORT_TX_DFLEXDPPMS
);
5169 if (!(val
& DP_PHY_MODE_STATUS_COMPLETED(tc_port
))) {
5170 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port
);
5171 WARN_ON(dig_port
->tc_legacy_port
);
5176 * This function may be called many times in a row without an HPD event
5177 * in between, so try to avoid the write when we can.
5179 val
= I915_READ(PORT_TX_DFLEXDPCSSS
);
5180 if (!(val
& DP_PHY_MODE_STATUS_NOT_SAFE(tc_port
))) {
5181 val
|= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port
);
5182 I915_WRITE(PORT_TX_DFLEXDPCSSS
, val
);
5186 * Now we have to re-check the live state, in case the port recently
5187 * became disconnected. Not necessary for legacy mode.
5189 if (dig_port
->tc_type
== TC_PORT_TYPEC
&&
5190 !(I915_READ(PORT_TX_DFLEXDPSP
) & TC_LIVE_STATE_TC(tc_port
))) {
5191 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port
);
5192 icl_tc_phy_disconnect(dev_priv
, dig_port
);
5200 * See the comment at the connect function. This implements the Disconnect
5203 void icl_tc_phy_disconnect(struct drm_i915_private
*dev_priv
,
5204 struct intel_digital_port
*dig_port
)
5206 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, dig_port
->base
.port
);
5208 if (dig_port
->tc_type
== TC_PORT_UNKNOWN
)
5212 * TBT disconnection flow is read the live status, what was done in
5215 if (dig_port
->tc_type
== TC_PORT_TYPEC
||
5216 dig_port
->tc_type
== TC_PORT_LEGACY
) {
5219 val
= I915_READ(PORT_TX_DFLEXDPCSSS
);
5220 val
&= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port
);
5221 I915_WRITE(PORT_TX_DFLEXDPCSSS
, val
);
5224 DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5225 port_name(dig_port
->base
.port
),
5226 tc_type_name(dig_port
->tc_type
));
5228 dig_port
->tc_type
= TC_PORT_UNKNOWN
;
5232 * The type-C ports are different because even when they are connected, they may
5233 * not be available/usable by the graphics driver: see the comment on
5234 * icl_tc_phy_connect(). So in our driver instead of adding the additional
5235 * concept of "usable" and make everything check for "connected and usable" we
5236 * define a port as "connected" when it is not only connected, but also when it
5237 * is usable by the rest of the driver. That maintains the old assumption that
5238 * connected ports are usable, and avoids exposing to the users objects they
5241 static bool icl_tc_port_connected(struct drm_i915_private
*dev_priv
,
5242 struct intel_digital_port
*intel_dig_port
)
5244 enum port port
= intel_dig_port
->base
.port
;
5245 enum tc_port tc_port
= intel_port_to_tc(dev_priv
, port
);
5246 bool is_legacy
, is_typec
, is_tbt
;
5250 * WARN if we got a legacy port HPD, but VBT didn't mark the port as
5251 * legacy. Treat the port as legacy from now on.
5253 if (WARN_ON(!intel_dig_port
->tc_legacy_port
&&
5254 I915_READ(SDEISR
) & SDE_TC_HOTPLUG_ICP(tc_port
)))
5255 intel_dig_port
->tc_legacy_port
= true;
5256 is_legacy
= intel_dig_port
->tc_legacy_port
;
5259 * The spec says we shouldn't be using the ISR bits for detecting
5260 * between TC and TBT. We should use DFLEXDPSP.
5262 dpsp
= I915_READ(PORT_TX_DFLEXDPSP
);
5263 is_typec
= dpsp
& TC_LIVE_STATE_TC(tc_port
);
5264 is_tbt
= dpsp
& TC_LIVE_STATE_TBT(tc_port
);
5266 if (!is_legacy
&& !is_typec
&& !is_tbt
) {
5267 icl_tc_phy_disconnect(dev_priv
, intel_dig_port
);
5272 icl_update_tc_port_type(dev_priv
, intel_dig_port
, is_legacy
, is_typec
,
5275 if (!icl_tc_phy_connect(dev_priv
, intel_dig_port
))
5281 static bool icl_digital_port_connected(struct intel_encoder
*encoder
)
5283 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5284 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
5286 if (intel_port_is_combophy(dev_priv
, encoder
->port
))
5287 return icl_combo_port_connected(dev_priv
, dig_port
);
5288 else if (intel_port_is_tc(dev_priv
, encoder
->port
))
5289 return icl_tc_port_connected(dev_priv
, dig_port
);
5291 MISSING_CASE(encoder
->hpd_pin
);
5297 * intel_digital_port_connected - is the specified port connected?
5298 * @encoder: intel_encoder
5300 * In cases where there's a connector physically connected but it can't be used
5301 * by our hardware we also return false, since the rest of the driver should
5302 * pretty much treat the port as disconnected. This is relevant for type-C
5303 * (starting on ICL) where there's ownership involved.
5305 * Return %true if port is connected, %false otherwise.
5307 bool intel_digital_port_connected(struct intel_encoder
*encoder
)
5309 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
5311 if (HAS_GMCH(dev_priv
)) {
5312 if (IS_GM45(dev_priv
))
5313 return gm45_digital_port_connected(encoder
);
5315 return g4x_digital_port_connected(encoder
);
5318 if (INTEL_GEN(dev_priv
) >= 11)
5319 return icl_digital_port_connected(encoder
);
5320 else if (IS_GEN(dev_priv
, 10) || IS_GEN9_BC(dev_priv
))
5321 return spt_digital_port_connected(encoder
);
5322 else if (IS_GEN9_LP(dev_priv
))
5323 return bxt_digital_port_connected(encoder
);
5324 else if (IS_GEN(dev_priv
, 8))
5325 return bdw_digital_port_connected(encoder
);
5326 else if (IS_GEN(dev_priv
, 7))
5327 return ivb_digital_port_connected(encoder
);
5328 else if (IS_GEN(dev_priv
, 6))
5329 return snb_digital_port_connected(encoder
);
5330 else if (IS_GEN(dev_priv
, 5))
5331 return ilk_digital_port_connected(encoder
);
5333 MISSING_CASE(INTEL_GEN(dev_priv
));
5337 static struct edid
*
5338 intel_dp_get_edid(struct intel_dp
*intel_dp
)
5340 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
5342 /* use cached edid if we have one */
5343 if (intel_connector
->edid
) {
5345 if (IS_ERR(intel_connector
->edid
))
5348 return drm_edid_duplicate(intel_connector
->edid
);
5350 return drm_get_edid(&intel_connector
->base
,
5351 &intel_dp
->aux
.ddc
);
5355 intel_dp_set_edid(struct intel_dp
*intel_dp
)
5357 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
5360 intel_dp_unset_edid(intel_dp
);
5361 edid
= intel_dp_get_edid(intel_dp
);
5362 intel_connector
->detect_edid
= edid
;
5364 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
5365 drm_dp_cec_set_edid(&intel_dp
->aux
, edid
);
5369 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
5371 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
5373 drm_dp_cec_unset_edid(&intel_dp
->aux
);
5374 kfree(intel_connector
->detect_edid
);
5375 intel_connector
->detect_edid
= NULL
;
5377 intel_dp
->has_audio
= false;
5381 intel_dp_detect(struct drm_connector
*connector
,
5382 struct drm_modeset_acquire_ctx
*ctx
,
5385 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5386 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5387 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5388 struct intel_encoder
*encoder
= &dig_port
->base
;
5389 enum drm_connector_status status
;
5390 enum intel_display_power_domain aux_domain
=
5391 intel_aux_power_domain(dig_port
);
5392 intel_wakeref_t wakeref
;
5394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5395 connector
->base
.id
, connector
->name
);
5396 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
5398 wakeref
= intel_display_power_get(dev_priv
, aux_domain
);
5400 /* Can't disconnect eDP */
5401 if (intel_dp_is_edp(intel_dp
))
5402 status
= edp_detect(intel_dp
);
5403 else if (intel_digital_port_connected(encoder
))
5404 status
= intel_dp_detect_dpcd(intel_dp
);
5406 status
= connector_status_disconnected
;
5408 if (status
== connector_status_disconnected
) {
5409 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
5410 memset(intel_dp
->dsc_dpcd
, 0, sizeof(intel_dp
->dsc_dpcd
));
5412 if (intel_dp
->is_mst
) {
5413 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5415 intel_dp
->mst_mgr
.mst_state
);
5416 intel_dp
->is_mst
= false;
5417 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5424 if (intel_dp
->reset_link_params
) {
5425 /* Initial max link lane count */
5426 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
5428 /* Initial max link rate */
5429 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
5431 intel_dp
->reset_link_params
= false;
5434 intel_dp_print_rates(intel_dp
);
5436 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5437 if (INTEL_GEN(dev_priv
) >= 11)
5438 intel_dp_get_dsc_sink_cap(intel_dp
);
5440 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
5441 drm_dp_is_branch(intel_dp
->dpcd
));
5443 intel_dp_configure_mst(intel_dp
);
5445 if (intel_dp
->is_mst
) {
5447 * If we are in MST mode then this connector
5448 * won't appear connected or have anything
5451 status
= connector_status_disconnected
;
5456 * Some external monitors do not signal loss of link synchronization
5457 * with an IRQ_HPD, so force a link status check.
5459 if (!intel_dp_is_edp(intel_dp
)) {
5462 ret
= intel_dp_retrain_link(encoder
, ctx
);
5464 intel_display_power_put(dev_priv
, aux_domain
, wakeref
);
5470 * Clearing NACK and defer counts to get their exact values
5471 * while reading EDID which are required by Compliance tests
5472 * 4.2.2.4 and 4.2.2.5
5474 intel_dp
->aux
.i2c_nack_count
= 0;
5475 intel_dp
->aux
.i2c_defer_count
= 0;
5477 intel_dp_set_edid(intel_dp
);
5478 if (intel_dp_is_edp(intel_dp
) ||
5479 to_intel_connector(connector
)->detect_edid
)
5480 status
= connector_status_connected
;
5482 intel_dp_check_service_irq(intel_dp
);
5485 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
5486 intel_dp_unset_edid(intel_dp
);
5488 intel_display_power_put(dev_priv
, aux_domain
, wakeref
);
5493 intel_dp_force(struct drm_connector
*connector
)
5495 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5496 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5497 struct intel_encoder
*intel_encoder
= &dig_port
->base
;
5498 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
5499 enum intel_display_power_domain aux_domain
=
5500 intel_aux_power_domain(dig_port
);
5501 intel_wakeref_t wakeref
;
5503 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5504 connector
->base
.id
, connector
->name
);
5505 intel_dp_unset_edid(intel_dp
);
5507 if (connector
->status
!= connector_status_connected
)
5510 wakeref
= intel_display_power_get(dev_priv
, aux_domain
);
5512 intel_dp_set_edid(intel_dp
);
5514 intel_display_power_put(dev_priv
, aux_domain
, wakeref
);
5517 static int intel_dp_get_modes(struct drm_connector
*connector
)
5519 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5522 edid
= intel_connector
->detect_edid
;
5524 int ret
= intel_connector_update_modes(connector
, edid
);
5529 /* if eDP has no EDID, fall back to fixed mode */
5530 if (intel_dp_is_edp(intel_attached_dp(connector
)) &&
5531 intel_connector
->panel
.fixed_mode
) {
5532 struct drm_display_mode
*mode
;
5534 mode
= drm_mode_duplicate(connector
->dev
,
5535 intel_connector
->panel
.fixed_mode
);
5537 drm_mode_probed_add(connector
, mode
);
5546 intel_dp_connector_register(struct drm_connector
*connector
)
5548 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5549 struct drm_device
*dev
= connector
->dev
;
5552 ret
= intel_connector_register(connector
);
5556 i915_debugfs_connector_add(connector
);
5558 DRM_DEBUG_KMS("registering %s bus for %s\n",
5559 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
5561 intel_dp
->aux
.dev
= connector
->kdev
;
5562 ret
= drm_dp_aux_register(&intel_dp
->aux
);
5564 drm_dp_cec_register_connector(&intel_dp
->aux
,
5565 connector
->name
, dev
->dev
);
5570 intel_dp_connector_unregister(struct drm_connector
*connector
)
5572 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
5574 drm_dp_cec_unregister_connector(&intel_dp
->aux
);
5575 drm_dp_aux_unregister(&intel_dp
->aux
);
5576 intel_connector_unregister(connector
);
5579 void intel_dp_encoder_flush_work(struct drm_encoder
*encoder
)
5581 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
5582 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5584 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5585 if (intel_dp_is_edp(intel_dp
)) {
5586 intel_wakeref_t wakeref
;
5588 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5590 * vdd might still be enabled do to the delayed vdd off.
5591 * Make sure vdd is actually turned off here.
5593 with_pps_lock(intel_dp
, wakeref
)
5594 edp_panel_vdd_off_sync(intel_dp
);
5596 if (intel_dp
->edp_notifier
.notifier_call
) {
5597 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
5598 intel_dp
->edp_notifier
.notifier_call
= NULL
;
5602 intel_dp_aux_fini(intel_dp
);
5605 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
5607 intel_dp_encoder_flush_work(encoder
);
5609 drm_encoder_cleanup(encoder
);
5610 kfree(enc_to_dig_port(encoder
));
5613 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
5615 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5616 intel_wakeref_t wakeref
;
5618 if (!intel_dp_is_edp(intel_dp
))
5622 * vdd might still be enabled do to the delayed vdd off.
5623 * Make sure vdd is actually turned off here.
5625 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5626 with_pps_lock(intel_dp
, wakeref
)
5627 edp_panel_vdd_off_sync(intel_dp
);
5630 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp
*hdcp
, int timeout
)
5634 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5635 ret
= wait_event_interruptible_timeout(hdcp
->cp_irq_queue
, C
,
5636 msecs_to_jiffies(timeout
));
5639 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5643 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port
,
5646 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_dig_port
->base
.base
);
5647 static const struct drm_dp_aux_msg msg
= {
5648 .request
= DP_AUX_NATIVE_WRITE
,
5649 .address
= DP_AUX_HDCP_AKSV
,
5650 .size
= DRM_HDCP_KSV_LEN
,
5652 u8 txbuf
[HEADER_SIZE
+ DRM_HDCP_KSV_LEN
] = {}, rxbuf
[2], reply
= 0;
5656 /* Output An first, that's easy */
5657 dpcd_ret
= drm_dp_dpcd_write(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_AN
,
5658 an
, DRM_HDCP_AN_LEN
);
5659 if (dpcd_ret
!= DRM_HDCP_AN_LEN
) {
5660 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5662 return dpcd_ret
>= 0 ? -EIO
: dpcd_ret
;
5666 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5667 * order to get it on the wire, we need to create the AUX header as if
5668 * we were writing the data, and then tickle the hardware to output the
5669 * data once the header is sent out.
5671 intel_dp_aux_header(txbuf
, &msg
);
5673 ret
= intel_dp_aux_xfer(intel_dp
, txbuf
, HEADER_SIZE
+ msg
.size
,
5674 rxbuf
, sizeof(rxbuf
),
5675 DP_AUX_CH_CTL_AUX_AKSV_SELECT
);
5677 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret
);
5679 } else if (ret
== 0) {
5680 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5684 reply
= (rxbuf
[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK
;
5685 if (reply
!= DP_AUX_NATIVE_REPLY_ACK
) {
5686 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5693 static int intel_dp_hdcp_read_bksv(struct intel_digital_port
*intel_dig_port
,
5697 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BKSV
, bksv
,
5699 if (ret
!= DRM_HDCP_KSV_LEN
) {
5700 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret
);
5701 return ret
>= 0 ? -EIO
: ret
;
5706 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port
,
5711 * For some reason the HDMI and DP HDCP specs call this register
5712 * definition by different names. In the HDMI spec, it's called BSTATUS,
5713 * but in DP it's called BINFO.
5715 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BINFO
,
5716 bstatus
, DRM_HDCP_BSTATUS_LEN
);
5717 if (ret
!= DRM_HDCP_BSTATUS_LEN
) {
5718 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5719 return ret
>= 0 ? -EIO
: ret
;
5725 int intel_dp_hdcp_read_bcaps(struct intel_digital_port
*intel_dig_port
,
5730 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BCAPS
,
5733 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret
);
5734 return ret
>= 0 ? -EIO
: ret
;
5741 int intel_dp_hdcp_repeater_present(struct intel_digital_port
*intel_dig_port
,
5742 bool *repeater_present
)
5747 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5751 *repeater_present
= bcaps
& DP_BCAPS_REPEATER_PRESENT
;
5756 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port
*intel_dig_port
,
5760 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_RI_PRIME
,
5761 ri_prime
, DRM_HDCP_RI_LEN
);
5762 if (ret
!= DRM_HDCP_RI_LEN
) {
5763 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret
);
5764 return ret
>= 0 ? -EIO
: ret
;
5770 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port
*intel_dig_port
,
5775 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5778 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5779 return ret
>= 0 ? -EIO
: ret
;
5781 *ksv_ready
= bstatus
& DP_BSTATUS_READY
;
5786 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port
*intel_dig_port
,
5787 int num_downstream
, u8
*ksv_fifo
)
5792 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5793 for (i
= 0; i
< num_downstream
; i
+= 3) {
5794 size_t len
= min(num_downstream
- i
, 3) * DRM_HDCP_KSV_LEN
;
5795 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5796 DP_AUX_HDCP_KSV_FIFO
,
5797 ksv_fifo
+ i
* DRM_HDCP_KSV_LEN
,
5800 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5802 return ret
>= 0 ? -EIO
: ret
;
5809 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port
*intel_dig_port
,
5814 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
5817 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5818 DP_AUX_HDCP_V_PRIME(i
), part
,
5819 DRM_HDCP_V_PRIME_PART_LEN
);
5820 if (ret
!= DRM_HDCP_V_PRIME_PART_LEN
) {
5821 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i
, ret
);
5822 return ret
>= 0 ? -EIO
: ret
;
5828 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port
*intel_dig_port
,
5831 /* Not used for single stream DisplayPort setups */
5836 bool intel_dp_hdcp_check_link(struct intel_digital_port
*intel_dig_port
)
5841 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
5844 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5848 return !(bstatus
& (DP_BSTATUS_LINK_FAILURE
| DP_BSTATUS_REAUTH_REQ
));
5852 int intel_dp_hdcp_capable(struct intel_digital_port
*intel_dig_port
,
5858 ret
= intel_dp_hdcp_read_bcaps(intel_dig_port
, &bcaps
);
5862 *hdcp_capable
= bcaps
& DP_BCAPS_HDCP_CAPABLE
;
5866 struct hdcp2_dp_errata_stream_type
{
5871 static struct hdcp2_dp_msg_data
{
5874 bool msg_detectable
;
5876 u32 timeout2
; /* Added for non_paired situation */
5877 } hdcp2_msg_data
[] = {
5878 {HDCP_2_2_AKE_INIT
, DP_HDCP_2_2_AKE_INIT_OFFSET
, false, 0, 0},
5879 {HDCP_2_2_AKE_SEND_CERT
, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET
,
5880 false, HDCP_2_2_CERT_TIMEOUT_MS
, 0},
5881 {HDCP_2_2_AKE_NO_STORED_KM
, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET
,
5883 {HDCP_2_2_AKE_STORED_KM
, DP_HDCP_2_2_AKE_STORED_KM_OFFSET
,
5885 {HDCP_2_2_AKE_SEND_HPRIME
, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET
,
5886 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS
,
5887 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS
},
5888 {HDCP_2_2_AKE_SEND_PAIRING_INFO
,
5889 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET
, true,
5890 HDCP_2_2_PAIRING_TIMEOUT_MS
, 0},
5891 {HDCP_2_2_LC_INIT
, DP_HDCP_2_2_LC_INIT_OFFSET
, false, 0, 0},
5892 {HDCP_2_2_LC_SEND_LPRIME
, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET
,
5893 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS
, 0},
5894 {HDCP_2_2_SKE_SEND_EKS
, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
, false,
5896 {HDCP_2_2_REP_SEND_RECVID_LIST
,
5897 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
, true,
5898 HDCP_2_2_RECVID_LIST_TIMEOUT_MS
, 0},
5899 {HDCP_2_2_REP_SEND_ACK
, DP_HDCP_2_2_REP_SEND_ACK_OFFSET
, false,
5901 {HDCP_2_2_REP_STREAM_MANAGE
,
5902 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET
, false,
5904 {HDCP_2_2_REP_STREAM_READY
, DP_HDCP_2_2_REP_STREAM_READY_OFFSET
,
5905 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS
, 0},
5906 /* local define to shovel this through the write_2_2 interface */
5907 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
5908 {HDCP_2_2_ERRATA_DP_STREAM_TYPE
,
5909 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET
, false,
5914 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port
*intel_dig_port
,
5919 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
5920 DP_HDCP_2_2_REG_RXSTATUS_OFFSET
, rx_status
,
5921 HDCP_2_2_DP_RXSTATUS_LEN
);
5922 if (ret
!= HDCP_2_2_DP_RXSTATUS_LEN
) {
5923 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret
);
5924 return ret
>= 0 ? -EIO
: ret
;
5931 int hdcp2_detect_msg_availability(struct intel_digital_port
*intel_dig_port
,
5932 u8 msg_id
, bool *msg_ready
)
5938 ret
= intel_dp_hdcp2_read_rx_status(intel_dig_port
, &rx_status
);
5943 case HDCP_2_2_AKE_SEND_HPRIME
:
5944 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status
))
5947 case HDCP_2_2_AKE_SEND_PAIRING_INFO
:
5948 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status
))
5951 case HDCP_2_2_REP_SEND_RECVID_LIST
:
5952 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status
))
5956 DRM_ERROR("Unidentified msg_id: %d\n", msg_id
);
5964 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port
*intel_dig_port
,
5965 struct hdcp2_dp_msg_data
*hdcp2_msg_data
)
5967 struct intel_dp
*dp
= &intel_dig_port
->dp
;
5968 struct intel_hdcp
*hdcp
= &dp
->attached_connector
->hdcp
;
5969 u8 msg_id
= hdcp2_msg_data
->msg_id
;
5971 bool msg_ready
= false;
5973 if (msg_id
== HDCP_2_2_AKE_SEND_HPRIME
&& !hdcp
->is_paired
)
5974 timeout
= hdcp2_msg_data
->timeout2
;
5976 timeout
= hdcp2_msg_data
->timeout
;
5979 * There is no way to detect the CERT, LPRIME and STREAM_READY
5980 * availability. So Wait for timeout and read the msg.
5982 if (!hdcp2_msg_data
->msg_detectable
) {
5987 * As we want to check the msg availability at timeout, Ignoring
5988 * the timeout at wait for CP_IRQ.
5990 intel_dp_hdcp_wait_for_cp_irq(hdcp
, timeout
);
5991 ret
= hdcp2_detect_msg_availability(intel_dig_port
,
5992 msg_id
, &msg_ready
);
5998 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
5999 hdcp2_msg_data
->msg_id
, ret
, timeout
);
6004 static struct hdcp2_dp_msg_data
*get_hdcp2_dp_msg_data(u8 msg_id
)
6008 for (i
= 0; i
< ARRAY_SIZE(hdcp2_msg_data
); i
++)
6009 if (hdcp2_msg_data
[i
].msg_id
== msg_id
)
6010 return &hdcp2_msg_data
[i
];
6016 int intel_dp_hdcp2_write_msg(struct intel_digital_port
*intel_dig_port
,
6017 void *buf
, size_t size
)
6019 struct intel_dp
*dp
= &intel_dig_port
->dp
;
6020 struct intel_hdcp
*hdcp
= &dp
->attached_connector
->hdcp
;
6021 unsigned int offset
;
6023 ssize_t ret
, bytes_to_write
, len
;
6024 struct hdcp2_dp_msg_data
*hdcp2_msg_data
;
6026 hdcp2_msg_data
= get_hdcp2_dp_msg_data(*byte
);
6027 if (!hdcp2_msg_data
)
6030 offset
= hdcp2_msg_data
->offset
;
6032 /* No msg_id in DP HDCP2.2 msgs */
6033 bytes_to_write
= size
- 1;
6036 hdcp
->cp_irq_count_cached
= atomic_read(&hdcp
->cp_irq_count
);
6038 while (bytes_to_write
) {
6039 len
= bytes_to_write
> DP_AUX_MAX_PAYLOAD_BYTES
?
6040 DP_AUX_MAX_PAYLOAD_BYTES
: bytes_to_write
;
6042 ret
= drm_dp_dpcd_write(&intel_dig_port
->dp
.aux
,
6043 offset
, (void *)byte
, len
);
6047 bytes_to_write
-= ret
;
6056 ssize_t
get_receiver_id_list_size(struct intel_digital_port
*intel_dig_port
)
6058 u8 rx_info
[HDCP_2_2_RXINFO_LEN
];
6062 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
6063 DP_HDCP_2_2_REG_RXINFO_OFFSET
,
6064 (void *)rx_info
, HDCP_2_2_RXINFO_LEN
);
6065 if (ret
!= HDCP_2_2_RXINFO_LEN
)
6066 return ret
>= 0 ? -EIO
: ret
;
6068 dev_cnt
= (HDCP_2_2_DEV_COUNT_HI(rx_info
[0]) << 4 |
6069 HDCP_2_2_DEV_COUNT_LO(rx_info
[1]));
6071 if (dev_cnt
> HDCP_2_2_MAX_DEVICE_COUNT
)
6072 dev_cnt
= HDCP_2_2_MAX_DEVICE_COUNT
;
6074 ret
= sizeof(struct hdcp2_rep_send_receiverid_list
) -
6075 HDCP_2_2_RECEIVER_IDS_MAX_LEN
+
6076 (dev_cnt
* HDCP_2_2_RECEIVER_ID_LEN
);
6082 int intel_dp_hdcp2_read_msg(struct intel_digital_port
*intel_dig_port
,
6083 u8 msg_id
, void *buf
, size_t size
)
6085 unsigned int offset
;
6087 ssize_t ret
, bytes_to_recv
, len
;
6088 struct hdcp2_dp_msg_data
*hdcp2_msg_data
;
6090 hdcp2_msg_data
= get_hdcp2_dp_msg_data(msg_id
);
6091 if (!hdcp2_msg_data
)
6093 offset
= hdcp2_msg_data
->offset
;
6095 ret
= intel_dp_hdcp2_wait_for_msg(intel_dig_port
, hdcp2_msg_data
);
6099 if (msg_id
== HDCP_2_2_REP_SEND_RECVID_LIST
) {
6100 ret
= get_receiver_id_list_size(intel_dig_port
);
6106 bytes_to_recv
= size
- 1;
6108 /* DP adaptation msgs has no msg_id */
6111 while (bytes_to_recv
) {
6112 len
= bytes_to_recv
> DP_AUX_MAX_PAYLOAD_BYTES
?
6113 DP_AUX_MAX_PAYLOAD_BYTES
: bytes_to_recv
;
6115 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
, offset
,
6118 DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id
, ret
);
6122 bytes_to_recv
-= ret
;
6133 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port
*intel_dig_port
,
6134 bool is_repeater
, u8 content_type
)
6136 struct hdcp2_dp_errata_stream_type stream_type_msg
;
6142 * Errata for DP: As Stream type is used for encryption, Receiver
6143 * should be communicated with stream type for the decryption of the
6145 * Repeater will be communicated with stream type as a part of it's
6146 * auth later in time.
6148 stream_type_msg
.msg_id
= HDCP_2_2_ERRATA_DP_STREAM_TYPE
;
6149 stream_type_msg
.stream_type
= content_type
;
6151 return intel_dp_hdcp2_write_msg(intel_dig_port
, &stream_type_msg
,
6152 sizeof(stream_type_msg
));
6156 int intel_dp_hdcp2_check_link(struct intel_digital_port
*intel_dig_port
)
6161 ret
= intel_dp_hdcp2_read_rx_status(intel_dig_port
, &rx_status
);
6165 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status
))
6166 ret
= HDCP_REAUTH_REQUEST
;
6167 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status
))
6168 ret
= HDCP_LINK_INTEGRITY_FAILURE
;
6169 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status
))
6170 ret
= HDCP_TOPOLOGY_CHANGE
;
6176 int intel_dp_hdcp2_capable(struct intel_digital_port
*intel_dig_port
,
6183 ret
= drm_dp_dpcd_read(&intel_dig_port
->dp
.aux
,
6184 DP_HDCP_2_2_REG_RX_CAPS_OFFSET
,
6185 rx_caps
, HDCP_2_2_RXCAPS_LEN
);
6186 if (ret
!= HDCP_2_2_RXCAPS_LEN
)
6187 return ret
>= 0 ? -EIO
: ret
;
6189 if (rx_caps
[0] == HDCP_2_2_RX_CAPS_VERSION_VAL
&&
6190 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps
[2]))
6196 static const struct intel_hdcp_shim intel_dp_hdcp_shim
= {
6197 .write_an_aksv
= intel_dp_hdcp_write_an_aksv
,
6198 .read_bksv
= intel_dp_hdcp_read_bksv
,
6199 .read_bstatus
= intel_dp_hdcp_read_bstatus
,
6200 .repeater_present
= intel_dp_hdcp_repeater_present
,
6201 .read_ri_prime
= intel_dp_hdcp_read_ri_prime
,
6202 .read_ksv_ready
= intel_dp_hdcp_read_ksv_ready
,
6203 .read_ksv_fifo
= intel_dp_hdcp_read_ksv_fifo
,
6204 .read_v_prime_part
= intel_dp_hdcp_read_v_prime_part
,
6205 .toggle_signalling
= intel_dp_hdcp_toggle_signalling
,
6206 .check_link
= intel_dp_hdcp_check_link
,
6207 .hdcp_capable
= intel_dp_hdcp_capable
,
6208 .write_2_2_msg
= intel_dp_hdcp2_write_msg
,
6209 .read_2_2_msg
= intel_dp_hdcp2_read_msg
,
6210 .config_stream_type
= intel_dp_hdcp2_config_stream_type
,
6211 .check_2_2_link
= intel_dp_hdcp2_check_link
,
6212 .hdcp_2_2_capable
= intel_dp_hdcp2_capable
,
6213 .protocol
= HDCP_PROTOCOL_DP
,
6216 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
6218 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6219 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
6221 lockdep_assert_held(&dev_priv
->pps_mutex
);
6223 if (!edp_have_panel_vdd(intel_dp
))
6227 * The VDD bit needs a power domain reference, so if the bit is
6228 * already enabled when we boot or resume, grab this reference and
6229 * schedule a vdd off, so we don't hold on to the reference
6232 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6233 intel_display_power_get(dev_priv
, intel_aux_power_domain(dig_port
));
6235 edp_panel_vdd_schedule_off(intel_dp
);
6238 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
6240 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6241 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
6244 if (intel_dp_port_enabled(dev_priv
, intel_dp
->output_reg
,
6245 encoder
->port
, &pipe
))
6248 return INVALID_PIPE
;
6251 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
6253 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
6254 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
6255 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
6256 intel_wakeref_t wakeref
;
6258 if (!HAS_DDI(dev_priv
))
6259 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6262 lspcon_resume(lspcon
);
6264 intel_dp
->reset_link_params
= true;
6266 with_pps_lock(intel_dp
, wakeref
) {
6267 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6268 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6270 if (intel_dp_is_edp(intel_dp
)) {
6272 * Reinit the power sequencer, in case BIOS did
6273 * something nasty with it.
6275 intel_dp_pps_init(intel_dp
);
6276 intel_edp_panel_vdd_sanitize(intel_dp
);
6281 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
6282 .force
= intel_dp_force
,
6283 .fill_modes
= drm_helper_probe_single_connector_modes
,
6284 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
6285 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
6286 .late_register
= intel_dp_connector_register
,
6287 .early_unregister
= intel_dp_connector_unregister
,
6288 .destroy
= intel_connector_destroy
,
6289 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
6290 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
6293 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
6294 .detect_ctx
= intel_dp_detect
,
6295 .get_modes
= intel_dp_get_modes
,
6296 .mode_valid
= intel_dp_mode_valid
,
6297 .atomic_check
= intel_digital_connector_atomic_check
,
6300 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
6301 .reset
= intel_dp_encoder_reset
,
6302 .destroy
= intel_dp_encoder_destroy
,
6306 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
6308 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
6309 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6310 enum irqreturn ret
= IRQ_NONE
;
6311 intel_wakeref_t wakeref
;
6313 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
6315 * vdd off can generate a long pulse on eDP which
6316 * would require vdd on to handle it, and thus we
6317 * would end up in an endless cycle of
6318 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6320 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
6321 port_name(intel_dig_port
->base
.port
));
6325 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
6326 port_name(intel_dig_port
->base
.port
),
6327 long_hpd
? "long" : "short");
6330 intel_dp
->reset_link_params
= true;
6334 wakeref
= intel_display_power_get(dev_priv
,
6335 intel_aux_power_domain(intel_dig_port
));
6337 if (intel_dp
->is_mst
) {
6338 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
6340 * If we were in MST mode, and device is not
6341 * there, get out of MST mode
6343 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6344 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
6345 intel_dp
->is_mst
= false;
6346 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
6352 if (!intel_dp
->is_mst
) {
6355 handled
= intel_dp_short_pulse(intel_dp
);
6364 intel_display_power_put(dev_priv
,
6365 intel_aux_power_domain(intel_dig_port
),
6371 /* check the VBT to see whether the eDP is on another port */
6372 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
)
6375 * eDP not supported on g4x. so bail out early just
6376 * for a bit extra safety in case the VBT is bonkers.
6378 if (INTEL_GEN(dev_priv
) < 5)
6381 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
6384 return intel_bios_is_port_edp(dev_priv
, port
);
6388 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
6390 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
6391 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
6393 if (!IS_G4X(dev_priv
) && port
!= PORT_A
)
6394 intel_attach_force_audio_property(connector
);
6396 intel_attach_broadcast_rgb_property(connector
);
6397 if (HAS_GMCH(dev_priv
))
6398 drm_connector_attach_max_bpc_property(connector
, 6, 10);
6399 else if (INTEL_GEN(dev_priv
) >= 5)
6400 drm_connector_attach_max_bpc_property(connector
, 6, 12);
6402 if (intel_dp_is_edp(intel_dp
)) {
6403 u32 allowed_scalers
;
6405 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
6406 if (!HAS_GMCH(dev_priv
))
6407 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
6409 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
6411 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
6416 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
6418 intel_dp
->panel_power_off_time
= ktime_get_boottime();
6419 intel_dp
->last_power_on
= jiffies
;
6420 intel_dp
->last_backlight_off
= jiffies
;
6424 intel_pps_readout_hw_state(struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
6426 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6427 u32 pp_on
, pp_off
, pp_ctl
;
6428 struct pps_registers regs
;
6430 intel_pps_get_registers(intel_dp
, ®s
);
6432 pp_ctl
= ironlake_get_pp_control(intel_dp
);
6434 /* Ensure PPS is unlocked */
6435 if (!HAS_DDI(dev_priv
))
6436 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
6438 pp_on
= I915_READ(regs
.pp_on
);
6439 pp_off
= I915_READ(regs
.pp_off
);
6441 /* Pull timing values out of registers */
6442 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
6443 PANEL_POWER_UP_DELAY_SHIFT
;
6445 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
6446 PANEL_LIGHT_ON_DELAY_SHIFT
;
6448 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
6449 PANEL_LIGHT_OFF_DELAY_SHIFT
;
6451 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
6452 PANEL_POWER_DOWN_DELAY_SHIFT
;
6454 if (i915_mmio_reg_valid(regs
.pp_div
)) {
6457 pp_div
= I915_READ(regs
.pp_div
);
6459 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
6460 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
6463 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
6464 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
6469 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
6471 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6473 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
6477 intel_pps_verify_state(struct intel_dp
*intel_dp
)
6479 struct edp_power_seq hw
;
6480 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
6482 intel_pps_readout_hw_state(intel_dp
, &hw
);
6484 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
6485 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
6486 DRM_ERROR("PPS state mismatch\n");
6487 intel_pps_dump_state("sw", sw
);
6488 intel_pps_dump_state("hw", &hw
);
6493 intel_dp_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
6495 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6496 struct edp_power_seq cur
, vbt
, spec
,
6497 *final
= &intel_dp
->pps_delays
;
6499 lockdep_assert_held(&dev_priv
->pps_mutex
);
6501 /* already initialized? */
6502 if (final
->t11_t12
!= 0)
6505 intel_pps_readout_hw_state(intel_dp
, &cur
);
6507 intel_pps_dump_state("cur", &cur
);
6509 vbt
= dev_priv
->vbt
.edp
.pps
;
6510 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6511 * of 500ms appears to be too short. Ocassionally the panel
6512 * just fails to power back on. Increasing the delay to 800ms
6513 * seems sufficient to avoid this problem.
6515 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
6516 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 1300 * 10);
6517 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6520 /* T11_T12 delay is special and actually in units of 100ms, but zero
6521 * based in the hw (so we need to add 100 ms). But the sw vbt
6522 * table multiplies it with 1000 to make it in units of 100usec,
6524 vbt
.t11_t12
+= 100 * 10;
6526 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6527 * our hw here, which are all in 100usec. */
6528 spec
.t1_t3
= 210 * 10;
6529 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
6530 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
6531 spec
.t10
= 500 * 10;
6532 /* This one is special and actually in units of 100ms, but zero
6533 * based in the hw (so we need to add 100 ms). But the sw vbt
6534 * table multiplies it with 1000 to make it in units of 100usec,
6536 spec
.t11_t12
= (510 + 100) * 10;
6538 intel_pps_dump_state("vbt", &vbt
);
6540 /* Use the max of the register settings and vbt. If both are
6541 * unset, fall back to the spec limits. */
6542 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
6544 max(cur.field, vbt.field))
6545 assign_final(t1_t3
);
6549 assign_final(t11_t12
);
6552 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
6553 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
6554 intel_dp
->backlight_on_delay
= get_delay(t8
);
6555 intel_dp
->backlight_off_delay
= get_delay(t9
);
6556 intel_dp
->panel_power_down_delay
= get_delay(t10
);
6557 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
6560 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6561 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
6562 intel_dp
->panel_power_cycle_delay
);
6564 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6565 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
6568 * We override the HW backlight delays to 1 because we do manual waits
6569 * on them. For T8, even BSpec recommends doing it. For T9, if we
6570 * don't do this, we'll end up waiting for the backlight off delay
6571 * twice: once when we do the manual sleep, and once when we disable
6572 * the panel and wait for the PP_STATUS bit to become zero.
6578 * HW has only a 100msec granularity for t11_t12 so round it up
6581 final
->t11_t12
= roundup(final
->t11_t12
, 100 * 10);
6585 intel_dp_init_panel_power_sequencer_registers(struct intel_dp
*intel_dp
,
6586 bool force_disable_vdd
)
6588 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6589 u32 pp_on
, pp_off
, port_sel
= 0;
6590 int div
= dev_priv
->rawclk_freq
/ 1000;
6591 struct pps_registers regs
;
6592 enum port port
= dp_to_dig_port(intel_dp
)->base
.port
;
6593 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
6595 lockdep_assert_held(&dev_priv
->pps_mutex
);
6597 intel_pps_get_registers(intel_dp
, ®s
);
6600 * On some VLV machines the BIOS can leave the VDD
6601 * enabled even on power sequencers which aren't
6602 * hooked up to any port. This would mess up the
6603 * power domain tracking the first time we pick
6604 * one of these power sequencers for use since
6605 * edp_panel_vdd_on() would notice that the VDD was
6606 * already on and therefore wouldn't grab the power
6607 * domain reference. Disable VDD first to avoid this.
6608 * This also avoids spuriously turning the VDD on as
6609 * soon as the new power sequencer gets initialized.
6611 if (force_disable_vdd
) {
6612 u32 pp
= ironlake_get_pp_control(intel_dp
);
6614 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
6616 if (pp
& EDP_FORCE_VDD
)
6617 DRM_DEBUG_KMS("VDD already on, disabling first\n");
6619 pp
&= ~EDP_FORCE_VDD
;
6621 I915_WRITE(regs
.pp_ctrl
, pp
);
6624 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
6625 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
6626 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
6627 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
6629 /* Haswell doesn't have any port selection bits for the panel
6630 * power sequencer any more. */
6631 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6632 port_sel
= PANEL_PORT_SELECT_VLV(port
);
6633 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
6636 port_sel
= PANEL_PORT_SELECT_DPA
;
6639 port_sel
= PANEL_PORT_SELECT_DPC
;
6642 port_sel
= PANEL_PORT_SELECT_DPD
;
6652 I915_WRITE(regs
.pp_on
, pp_on
);
6653 I915_WRITE(regs
.pp_off
, pp_off
);
6656 * Compute the divisor for the pp clock, simply match the Bspec formula.
6658 if (i915_mmio_reg_valid(regs
.pp_div
)) {
6661 pp_div
= ((100 * div
) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
6662 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000) <<
6663 PANEL_POWER_CYCLE_DELAY_SHIFT
);
6664 I915_WRITE(regs
.pp_div
, pp_div
);
6668 pp_ctl
= I915_READ(regs
.pp_ctrl
);
6669 pp_ctl
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
6670 pp_ctl
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000) <<
6671 BXT_POWER_CYCLE_DELAY_SHIFT
);
6672 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
6675 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6676 I915_READ(regs
.pp_on
),
6677 I915_READ(regs
.pp_off
),
6678 i915_mmio_reg_valid(regs
.pp_div
) ?
6679 I915_READ(regs
.pp_div
) :
6680 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
));
6683 static void intel_dp_pps_init(struct intel_dp
*intel_dp
)
6685 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6687 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6688 vlv_initial_power_sequencer_setup(intel_dp
);
6690 intel_dp_init_panel_power_sequencer(intel_dp
);
6691 intel_dp_init_panel_power_sequencer_registers(intel_dp
, false);
6696 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6697 * @dev_priv: i915 device
6698 * @crtc_state: a pointer to the active intel_crtc_state
6699 * @refresh_rate: RR to be programmed
6701 * This function gets called when refresh rate (RR) has to be changed from
6702 * one frequency to another. Switches can be between high and low RR
6703 * supported by the panel or to any other RR based on media playback (in
6704 * this case, RR value needs to be passed from user space).
6706 * The caller of this function needs to take a lock on dev_priv->drrs.
6708 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
6709 const struct intel_crtc_state
*crtc_state
,
6712 struct intel_encoder
*encoder
;
6713 struct intel_digital_port
*dig_port
= NULL
;
6714 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
6715 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6716 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
6718 if (refresh_rate
<= 0) {
6719 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6723 if (intel_dp
== NULL
) {
6724 DRM_DEBUG_KMS("DRRS not supported.\n");
6728 dig_port
= dp_to_dig_port(intel_dp
);
6729 encoder
= &dig_port
->base
;
6732 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6736 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
6737 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6741 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
6743 index
= DRRS_LOW_RR
;
6745 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
6747 "DRRS requested for previously set RR...ignoring\n");
6751 if (!crtc_state
->base
.active
) {
6752 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6756 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
6759 intel_dp_set_m_n(crtc_state
, M1_N1
);
6762 intel_dp_set_m_n(crtc_state
, M2_N2
);
6766 DRM_ERROR("Unsupported refreshrate type\n");
6768 } else if (INTEL_GEN(dev_priv
) > 6) {
6769 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
6772 val
= I915_READ(reg
);
6773 if (index
> DRRS_HIGH_RR
) {
6774 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6775 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
6777 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
6779 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6780 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
6782 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
6784 I915_WRITE(reg
, val
);
6787 dev_priv
->drrs
.refresh_rate_type
= index
;
6789 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
6793 * intel_edp_drrs_enable - init drrs struct if supported
6794 * @intel_dp: DP struct
6795 * @crtc_state: A pointer to the active crtc state.
6797 * Initializes frontbuffer_bits and drrs.dp
6799 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
6800 const struct intel_crtc_state
*crtc_state
)
6802 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6804 if (!crtc_state
->has_drrs
) {
6805 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6809 if (dev_priv
->psr
.enabled
) {
6810 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6814 mutex_lock(&dev_priv
->drrs
.mutex
);
6815 if (dev_priv
->drrs
.dp
) {
6816 DRM_DEBUG_KMS("DRRS already enabled\n");
6820 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
6822 dev_priv
->drrs
.dp
= intel_dp
;
6825 mutex_unlock(&dev_priv
->drrs
.mutex
);
6829 * intel_edp_drrs_disable - Disable DRRS
6830 * @intel_dp: DP struct
6831 * @old_crtc_state: Pointer to old crtc_state.
6834 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
6835 const struct intel_crtc_state
*old_crtc_state
)
6837 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
6839 if (!old_crtc_state
->has_drrs
)
6842 mutex_lock(&dev_priv
->drrs
.mutex
);
6843 if (!dev_priv
->drrs
.dp
) {
6844 mutex_unlock(&dev_priv
->drrs
.mutex
);
6848 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6849 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
6850 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6852 dev_priv
->drrs
.dp
= NULL
;
6853 mutex_unlock(&dev_priv
->drrs
.mutex
);
6855 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
6858 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
6860 struct drm_i915_private
*dev_priv
=
6861 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
6862 struct intel_dp
*intel_dp
;
6864 mutex_lock(&dev_priv
->drrs
.mutex
);
6866 intel_dp
= dev_priv
->drrs
.dp
;
6872 * The delayed work can race with an invalidate hence we need to
6876 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
6879 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
6880 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
6882 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6883 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
6887 mutex_unlock(&dev_priv
->drrs
.mutex
);
6891 * intel_edp_drrs_invalidate - Disable Idleness DRRS
6892 * @dev_priv: i915 device
6893 * @frontbuffer_bits: frontbuffer plane tracking bits
6895 * This function gets called everytime rendering on the given planes start.
6896 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6898 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6900 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
6901 unsigned int frontbuffer_bits
)
6903 struct drm_crtc
*crtc
;
6906 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
6909 cancel_delayed_work(&dev_priv
->drrs
.work
);
6911 mutex_lock(&dev_priv
->drrs
.mutex
);
6912 if (!dev_priv
->drrs
.dp
) {
6913 mutex_unlock(&dev_priv
->drrs
.mutex
);
6917 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6918 pipe
= to_intel_crtc(crtc
)->pipe
;
6920 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6921 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
6923 /* invalidate means busy screen hence upclock */
6924 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6925 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6926 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6928 mutex_unlock(&dev_priv
->drrs
.mutex
);
6932 * intel_edp_drrs_flush - Restart Idleness DRRS
6933 * @dev_priv: i915 device
6934 * @frontbuffer_bits: frontbuffer plane tracking bits
6936 * This function gets called every time rendering on the given planes has
6937 * completed or flip on a crtc is completed. So DRRS should be upclocked
6938 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6939 * if no other planes are dirty.
6941 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6943 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
6944 unsigned int frontbuffer_bits
)
6946 struct drm_crtc
*crtc
;
6949 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
6952 cancel_delayed_work(&dev_priv
->drrs
.work
);
6954 mutex_lock(&dev_priv
->drrs
.mutex
);
6955 if (!dev_priv
->drrs
.dp
) {
6956 mutex_unlock(&dev_priv
->drrs
.mutex
);
6960 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
6961 pipe
= to_intel_crtc(crtc
)->pipe
;
6963 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
6964 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
6966 /* flush means busy screen hence upclock */
6967 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
6968 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
6969 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
6972 * flush also means no more activity hence schedule downclock, if all
6973 * other fbs are quiescent too
6975 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
6976 schedule_delayed_work(&dev_priv
->drrs
.work
,
6977 msecs_to_jiffies(1000));
6978 mutex_unlock(&dev_priv
->drrs
.mutex
);
6982 * DOC: Display Refresh Rate Switching (DRRS)
6984 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6985 * which enables swtching between low and high refresh rates,
6986 * dynamically, based on the usage scenario. This feature is applicable
6987 * for internal panels.
6989 * Indication that the panel supports DRRS is given by the panel EDID, which
6990 * would list multiple refresh rates for one resolution.
6992 * DRRS is of 2 types - static and seamless.
6993 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6994 * (may appear as a blink on screen) and is used in dock-undock scenario.
6995 * Seamless DRRS involves changing RR without any visual effect to the user
6996 * and can be used during normal system usage. This is done by programming
6997 * certain registers.
6999 * Support for static/seamless DRRS may be indicated in the VBT based on
7000 * inputs from the panel spec.
7002 * DRRS saves power by switching to low RR based on usage scenarios.
7004 * The implementation is based on frontbuffer tracking implementation. When
7005 * there is a disturbance on the screen triggered by user activity or a periodic
7006 * system activity, DRRS is disabled (RR is changed to high RR). When there is
7007 * no movement on screen, after a timeout of 1 second, a switch to low RR is
7010 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7011 * and intel_edp_drrs_flush() are called.
7013 * DRRS can be further extended to support other internal panels and also
7014 * the scenario of video playback wherein RR is set based on the rate
7015 * requested by userspace.
7019 * intel_dp_drrs_init - Init basic DRRS work and mutex.
7020 * @connector: eDP connector
7021 * @fixed_mode: preferred mode of panel
7023 * This function is called only once at driver load to initialize basic
7027 * Downclock mode if panel supports it, else return NULL.
7028 * DRRS support is determined by the presence of downclock mode (apart
7029 * from VBT setting).
7031 static struct drm_display_mode
*
7032 intel_dp_drrs_init(struct intel_connector
*connector
,
7033 struct drm_display_mode
*fixed_mode
)
7035 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
7036 struct drm_display_mode
*downclock_mode
= NULL
;
7038 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
7039 mutex_init(&dev_priv
->drrs
.mutex
);
7041 if (INTEL_GEN(dev_priv
) <= 6) {
7042 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7046 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
7047 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7051 downclock_mode
= intel_find_panel_downclock(dev_priv
, fixed_mode
,
7054 if (!downclock_mode
) {
7055 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7059 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
7061 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
7062 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7063 return downclock_mode
;
7066 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
7067 struct intel_connector
*intel_connector
)
7069 struct drm_i915_private
*dev_priv
= dp_to_i915(intel_dp
);
7070 struct drm_device
*dev
= &dev_priv
->drm
;
7071 struct drm_connector
*connector
= &intel_connector
->base
;
7072 struct drm_display_mode
*fixed_mode
= NULL
;
7073 struct drm_display_mode
*downclock_mode
= NULL
;
7075 struct drm_display_mode
*scan
;
7076 enum pipe pipe
= INVALID_PIPE
;
7077 intel_wakeref_t wakeref
;
7080 if (!intel_dp_is_edp(intel_dp
))
7083 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
, edp_panel_vdd_work
);
7086 * On IBX/CPT we may get here with LVDS already registered. Since the
7087 * driver uses the only internal power sequencer available for both
7088 * eDP and LVDS bail out early in this case to prevent interfering
7089 * with an already powered-on LVDS power sequencer.
7091 if (intel_get_lvds_encoder(&dev_priv
->drm
)) {
7092 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
7093 DRM_INFO("LVDS was detected, not registering eDP\n");
7098 with_pps_lock(intel_dp
, wakeref
) {
7099 intel_dp_init_panel_power_timestamps(intel_dp
);
7100 intel_dp_pps_init(intel_dp
);
7101 intel_edp_panel_vdd_sanitize(intel_dp
);
7104 /* Cache DPCD and EDID for edp. */
7105 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
7108 /* if this fails, presume the device is a ghost */
7109 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7113 mutex_lock(&dev
->mode_config
.mutex
);
7114 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
7116 if (drm_add_edid_modes(connector
, edid
)) {
7117 drm_connector_update_edid_property(connector
,
7121 edid
= ERR_PTR(-EINVAL
);
7124 edid
= ERR_PTR(-ENOENT
);
7126 intel_connector
->edid
= edid
;
7128 /* prefer fixed mode from EDID if available */
7129 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
7130 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
7131 fixed_mode
= drm_mode_duplicate(dev
, scan
);
7132 downclock_mode
= intel_dp_drrs_init(
7133 intel_connector
, fixed_mode
);
7138 /* fallback to VBT if available for eDP */
7139 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
7140 fixed_mode
= drm_mode_duplicate(dev
,
7141 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
7143 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
7144 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
7145 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
7148 mutex_unlock(&dev
->mode_config
.mutex
);
7150 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
7151 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
7152 register_reboot_notifier(&intel_dp
->edp_notifier
);
7155 * Figure out the current pipe for the initial backlight setup.
7156 * If the current pipe isn't valid, try the PPS pipe, and if that
7157 * fails just assume pipe A.
7159 pipe
= vlv_active_pipe(intel_dp
);
7161 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
7162 pipe
= intel_dp
->pps_pipe
;
7164 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
7167 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7171 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
7172 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
7173 intel_panel_setup_backlight(connector
, pipe
);
7176 drm_connector_init_panel_orientation_property(
7177 connector
, fixed_mode
->hdisplay
, fixed_mode
->vdisplay
);
7182 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
7184 * vdd might still be enabled do to the delayed vdd off.
7185 * Make sure vdd is actually turned off here.
7187 with_pps_lock(intel_dp
, wakeref
)
7188 edp_panel_vdd_off_sync(intel_dp
);
7193 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
7195 struct intel_connector
*intel_connector
;
7196 struct drm_connector
*connector
;
7198 intel_connector
= container_of(work
, typeof(*intel_connector
),
7199 modeset_retry_work
);
7200 connector
= &intel_connector
->base
;
7201 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
7204 /* Grab the locks before changing connector property*/
7205 mutex_lock(&connector
->dev
->mode_config
.mutex
);
7206 /* Set connector link status to BAD and send a Uevent to notify
7207 * userspace to do a modeset.
7209 drm_connector_set_link_status_property(connector
,
7210 DRM_MODE_LINK_STATUS_BAD
);
7211 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
7212 /* Send Hotplug uevent so userspace can reprobe */
7213 drm_kms_helper_hotplug_event(connector
->dev
);
7217 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
7218 struct intel_connector
*intel_connector
)
7220 struct drm_connector
*connector
= &intel_connector
->base
;
7221 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
7222 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
7223 struct drm_device
*dev
= intel_encoder
->base
.dev
;
7224 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7225 enum port port
= intel_encoder
->port
;
7228 /* Initialize the work for modeset in case of link train failure */
7229 INIT_WORK(&intel_connector
->modeset_retry_work
,
7230 intel_dp_modeset_retry_work_fn
);
7232 if (WARN(intel_dig_port
->max_lanes
< 1,
7233 "Not enough lanes (%d) for DP on port %c\n",
7234 intel_dig_port
->max_lanes
, port_name(port
)))
7237 intel_dp_set_source_rates(intel_dp
);
7239 intel_dp
->reset_link_params
= true;
7240 intel_dp
->pps_pipe
= INVALID_PIPE
;
7241 intel_dp
->active_pipe
= INVALID_PIPE
;
7243 /* intel_dp vfuncs */
7244 if (HAS_DDI(dev_priv
))
7245 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
7247 /* Preserve the current hw state. */
7248 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
7249 intel_dp
->attached_connector
= intel_connector
;
7251 if (intel_dp_is_port_edp(dev_priv
, port
))
7252 type
= DRM_MODE_CONNECTOR_eDP
;
7254 type
= DRM_MODE_CONNECTOR_DisplayPort
;
7256 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
7257 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
7260 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7261 * for DP the encoder type can be set by the caller to
7262 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7264 if (type
== DRM_MODE_CONNECTOR_eDP
)
7265 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
7267 /* eDP only on port B and/or C on vlv/chv */
7268 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
7269 intel_dp_is_edp(intel_dp
) &&
7270 port
!= PORT_B
&& port
!= PORT_C
))
7273 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
7274 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
7277 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
7278 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
7280 if (!HAS_GMCH(dev_priv
))
7281 connector
->interlace_allowed
= true;
7282 connector
->doublescan_allowed
= 0;
7284 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
7286 intel_dp_aux_init(intel_dp
);
7288 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
7290 if (HAS_DDI(dev_priv
))
7291 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
7293 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
7295 /* init MST on ports that can support it */
7296 if (HAS_DP_MST(dev_priv
) && !intel_dp_is_edp(intel_dp
) &&
7297 (port
== PORT_B
|| port
== PORT_C
||
7298 port
== PORT_D
|| port
== PORT_F
))
7299 intel_dp_mst_encoder_init(intel_dig_port
,
7300 intel_connector
->base
.base
.id
);
7302 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
7303 intel_dp_aux_fini(intel_dp
);
7304 intel_dp_mst_encoder_cleanup(intel_dig_port
);
7308 intel_dp_add_properties(intel_dp
, connector
);
7310 if (is_hdcp_supported(dev_priv
, port
) && !intel_dp_is_edp(intel_dp
)) {
7311 int ret
= intel_hdcp_init(intel_connector
, &intel_dp_hdcp_shim
);
7313 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7316 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7317 * 0xd. Failure to do so will result in spurious interrupts being
7318 * generated on the port when a cable is not attached.
7320 if (IS_G45(dev_priv
)) {
7321 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
7322 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
7328 drm_connector_cleanup(connector
);
7333 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
7334 i915_reg_t output_reg
,
7337 struct intel_digital_port
*intel_dig_port
;
7338 struct intel_encoder
*intel_encoder
;
7339 struct drm_encoder
*encoder
;
7340 struct intel_connector
*intel_connector
;
7342 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
7343 if (!intel_dig_port
)
7346 intel_connector
= intel_connector_alloc();
7347 if (!intel_connector
)
7348 goto err_connector_alloc
;
7350 intel_encoder
= &intel_dig_port
->base
;
7351 encoder
= &intel_encoder
->base
;
7353 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
7354 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
7355 "DP %c", port_name(port
)))
7356 goto err_encoder_init
;
7358 intel_encoder
->hotplug
= intel_dp_hotplug
;
7359 intel_encoder
->compute_config
= intel_dp_compute_config
;
7360 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
7361 intel_encoder
->get_config
= intel_dp_get_config
;
7362 intel_encoder
->update_pipe
= intel_panel_update_backlight
;
7363 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
7364 if (IS_CHERRYVIEW(dev_priv
)) {
7365 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
7366 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
7367 intel_encoder
->enable
= vlv_enable_dp
;
7368 intel_encoder
->disable
= vlv_disable_dp
;
7369 intel_encoder
->post_disable
= chv_post_disable_dp
;
7370 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
7371 } else if (IS_VALLEYVIEW(dev_priv
)) {
7372 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
7373 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
7374 intel_encoder
->enable
= vlv_enable_dp
;
7375 intel_encoder
->disable
= vlv_disable_dp
;
7376 intel_encoder
->post_disable
= vlv_post_disable_dp
;
7378 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
7379 intel_encoder
->enable
= g4x_enable_dp
;
7380 intel_encoder
->disable
= g4x_disable_dp
;
7381 intel_encoder
->post_disable
= g4x_post_disable_dp
;
7384 intel_dig_port
->dp
.output_reg
= output_reg
;
7385 intel_dig_port
->max_lanes
= 4;
7387 intel_encoder
->type
= INTEL_OUTPUT_DP
;
7388 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
7389 if (IS_CHERRYVIEW(dev_priv
)) {
7391 intel_encoder
->crtc_mask
= 1 << 2;
7393 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
7395 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
7397 intel_encoder
->cloneable
= 0;
7398 intel_encoder
->port
= port
;
7400 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
7403 intel_infoframe_init(intel_dig_port
);
7405 intel_dig_port
->aux_ch
= intel_bios_port_aux_ch(dev_priv
, port
);
7406 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
7407 goto err_init_connector
;
7412 drm_encoder_cleanup(encoder
);
7414 kfree(intel_connector
);
7415 err_connector_alloc
:
7416 kfree(intel_dig_port
);
7420 void intel_dp_mst_suspend(struct drm_i915_private
*dev_priv
)
7422 struct intel_encoder
*encoder
;
7424 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7425 struct intel_dp
*intel_dp
;
7427 if (encoder
->type
!= INTEL_OUTPUT_DDI
)
7430 intel_dp
= enc_to_intel_dp(&encoder
->base
);
7432 if (!intel_dp
->can_mst
)
7435 if (intel_dp
->is_mst
)
7436 drm_dp_mst_topology_mgr_suspend(&intel_dp
->mst_mgr
);
7440 void intel_dp_mst_resume(struct drm_i915_private
*dev_priv
)
7442 struct intel_encoder
*encoder
;
7444 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7445 struct intel_dp
*intel_dp
;
7448 if (encoder
->type
!= INTEL_OUTPUT_DDI
)
7451 intel_dp
= enc_to_intel_dp(&encoder
->base
);
7453 if (!intel_dp
->can_mst
)
7456 ret
= drm_dp_mst_topology_mgr_resume(&intel_dp
->mst_mgr
);
7458 intel_dp
->is_mst
= false;
7459 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,