2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
49 static const struct dp_link_dpll gen4_dpll
[] = {
51 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
53 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
56 static const struct dp_link_dpll pch_dpll
[] = {
58 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
60 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
63 static const struct dp_link_dpll vlv_dpll
[] = {
65 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
67 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
74 static const struct dp_link_dpll chv_dpll
[] = {
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
80 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
82 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
83 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
84 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
85 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
87 /* Skylake supports following rates */
88 static const int gen9_rates
[] = { 162000, 216000, 270000,
89 324000, 432000, 540000 };
90 static const int default_rates
[] = { 162000, 270000, 540000 };
93 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
94 * @intel_dp: DP struct
96 * If a CPU or PCH DP output is attached to an eDP panel, this function
97 * will return true, and false otherwise.
99 static bool is_edp(struct intel_dp
*intel_dp
)
101 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
103 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
106 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
108 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
110 return intel_dig_port
->base
.base
.dev
;
113 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
115 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
118 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
119 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
120 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
121 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
122 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
126 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
128 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
129 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
131 switch (max_link_bw
) {
132 case DP_LINK_BW_1_62
:
135 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
136 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
137 /* WaDisableHBR2:skl */
138 max_link_bw
= DP_LINK_BW_2_7
;
139 else if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
140 INTEL_INFO(dev
)->gen
>= 8) &&
141 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
142 max_link_bw
= DP_LINK_BW_5_4
;
144 max_link_bw
= DP_LINK_BW_2_7
;
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw
= DP_LINK_BW_1_62
;
155 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
157 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
158 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
159 u8 source_max
, sink_max
;
162 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
163 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
166 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 return min(source_max
, sink_max
);
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 * 270000 * 1 * 8 / 10 == 216000
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 return (pixel_clock
* bpp
+ 9) / 10;
195 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
197 return (max_link_clock
* max_lanes
* 8) / 10;
200 static enum drm_mode_status
201 intel_dp_mode_valid(struct drm_connector
*connector
,
202 struct drm_display_mode
*mode
)
204 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
206 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
207 int target_clock
= mode
->clock
;
208 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
210 if (is_edp(intel_dp
) && fixed_mode
) {
211 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
214 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
217 target_clock
= fixed_mode
->clock
;
220 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
221 max_lanes
= intel_dp_max_lane_count(intel_dp
);
223 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
224 mode_rate
= intel_dp_link_required(target_clock
, 18);
226 if (mode_rate
> max_rate
)
227 return MODE_CLOCK_HIGH
;
229 if (mode
->clock
< 10000)
230 return MODE_CLOCK_LOW
;
232 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
233 return MODE_H_ILLEGAL
;
238 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
245 for (i
= 0; i
< src_bytes
; i
++)
246 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
250 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
255 for (i
= 0; i
< dst_bytes
; i
++)
256 dst
[i
] = src
>> ((3-i
) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev
))
270 clkcfg
= I915_READ(CLKCFG
);
271 switch (clkcfg
& CLKCFG_FSB_MASK
) {
280 case CLKCFG_FSB_1067
:
282 case CLKCFG_FSB_1333
:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600
:
286 case CLKCFG_FSB_1600_ALT
:
294 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
295 struct intel_dp
*intel_dp
);
297 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
298 struct intel_dp
*intel_dp
);
300 static void pps_lock(struct intel_dp
*intel_dp
)
302 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
303 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
304 struct drm_device
*dev
= encoder
->base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 enum intel_display_power_domain power_domain
;
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
312 power_domain
= intel_display_port_power_domain(encoder
);
313 intel_display_power_get(dev_priv
, power_domain
);
315 mutex_lock(&dev_priv
->pps_mutex
);
318 static void pps_unlock(struct intel_dp
*intel_dp
)
320 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
321 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
322 struct drm_device
*dev
= encoder
->base
.dev
;
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 enum intel_display_power_domain power_domain
;
326 mutex_unlock(&dev_priv
->pps_mutex
);
328 power_domain
= intel_display_port_power_domain(encoder
);
329 intel_display_power_put(dev_priv
, power_domain
);
333 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
338 enum pipe pipe
= intel_dp
->pps_pipe
;
342 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe
), port_name(intel_dig_port
->port
));
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
353 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
354 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
355 DP
|= DP_PORT_WIDTH(1);
356 DP
|= DP_LINK_TRAIN_PAT_1
;
358 if (IS_CHERRYVIEW(dev
))
359 DP
|= DP_PIPE_SELECT_CHV(pipe
);
360 else if (pipe
== PIPE_B
)
361 DP
|= DP_PIPEB_SELECT
;
363 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
370 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
371 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
379 I915_WRITE(intel_dp
->output_reg
, DP
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
385 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
386 POSTING_READ(intel_dp
->output_reg
);
389 vlv_force_pll_off(dev
, pipe
);
393 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 struct intel_encoder
*encoder
;
399 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
402 lockdep_assert_held(&dev_priv
->pps_mutex
);
404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp
));
407 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
408 return intel_dp
->pps_pipe
;
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
414 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
456 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
459 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
471 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
478 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
480 vlv_pipe_check pipe_check
)
484 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
485 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
486 PANEL_PORT_SELECT_MASK
;
488 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
491 if (!pipe_check(dev_priv
, pipe
))
501 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
504 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 enum port port
= intel_dig_port
->port
;
508 lockdep_assert_held(&dev_priv
->pps_mutex
);
510 /* try to find a pipe with this port selected */
511 /* first pick one where the panel is on */
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
517 vlv_pipe_has_vdd_on
);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
533 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
534 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
537 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
539 struct drm_device
*dev
= dev_priv
->dev
;
540 struct intel_encoder
*encoder
;
542 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
555 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
556 struct intel_dp
*intel_dp
;
558 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
561 intel_dp
= enc_to_intel_dp(&encoder
->base
);
562 intel_dp
->pps_pipe
= INVALID_PIPE
;
566 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
568 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
570 if (HAS_PCH_SPLIT(dev
))
571 return PCH_PP_CONTROL
;
573 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
576 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
578 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
580 if (HAS_PCH_SPLIT(dev
))
581 return PCH_PP_STATUS
;
583 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
586 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
587 This function only applicable when panel PM state is not to be tracked */
588 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
591 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
593 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
596 u32 pp_ctrl_reg
, pp_div_reg
;
598 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
603 if (IS_VALLEYVIEW(dev
)) {
604 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
606 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
607 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
608 pp_div
= I915_READ(pp_div_reg
);
609 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
611 /* 0x1F write to PP_DIV_REG sets max cycle delay */
612 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
613 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
614 msleep(intel_dp
->panel_power_cycle_delay
);
617 pps_unlock(intel_dp
);
622 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
624 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
627 lockdep_assert_held(&dev_priv
->pps_mutex
);
629 if (IS_VALLEYVIEW(dev
) &&
630 intel_dp
->pps_pipe
== INVALID_PIPE
)
633 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
636 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
638 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
641 lockdep_assert_held(&dev_priv
->pps_mutex
);
643 if (IS_VALLEYVIEW(dev
) &&
644 intel_dp
->pps_pipe
== INVALID_PIPE
)
647 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
651 intel_dp_check_edp(struct intel_dp
*intel_dp
)
653 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
656 if (!is_edp(intel_dp
))
659 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
660 WARN(1, "eDP powered off while attempting aux channel communication.\n");
661 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
662 I915_READ(_pp_stat_reg(intel_dp
)),
663 I915_READ(_pp_ctrl_reg(intel_dp
)));
668 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
670 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
671 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
673 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
677 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
679 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
680 msecs_to_jiffies_timeout(10));
682 done
= wait_for_atomic(C
, 10) == 0;
684 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
691 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
693 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
694 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
697 * The clock divider is based off the hrawclk, and would like to run at
698 * 2MHz. So, take the hrawclk value and divide by 2 and use that
700 return index
? 0 : intel_hrawclk(dev
) / 2;
703 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
705 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
706 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
711 if (intel_dig_port
->port
== PORT_A
) {
712 if (IS_GEN6(dev
) || IS_GEN7(dev
))
713 return 200; /* SNB & IVB eDP input clock at 400Mhz */
715 return 225; /* eDP input clock at 450Mhz */
717 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
721 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
723 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
724 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
727 if (intel_dig_port
->port
== PORT_A
) {
730 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
731 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
732 /* Workaround for non-ULT HSW */
739 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
743 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
745 return index
? 0 : 100;
748 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
751 * SKL doesn't need us to program the AUX clock divider (Hardware will
752 * derive the clock from CDCLK automatically). We still implement the
753 * get_aux_clock_divider vfunc to plug-in into the existing code.
755 return index
? 0 : 1;
758 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
761 uint32_t aux_clock_divider
)
763 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
764 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
765 uint32_t precharge
, timeout
;
772 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
773 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
775 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
777 return DP_AUX_CH_CTL_SEND_BUSY
|
779 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
780 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
782 DP_AUX_CH_CTL_RECEIVE_ERROR
|
783 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
784 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
785 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
788 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
793 return DP_AUX_CH_CTL_SEND_BUSY
|
795 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
796 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
797 DP_AUX_CH_CTL_TIME_OUT_1600us
|
798 DP_AUX_CH_CTL_RECEIVE_ERROR
|
799 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
800 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
804 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
805 const uint8_t *send
, int send_bytes
,
806 uint8_t *recv
, int recv_size
)
808 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
809 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
811 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
812 uint32_t ch_data
= ch_ctl
+ 4;
813 uint32_t aux_clock_divider
;
814 int i
, ret
, recv_bytes
;
817 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
823 * We will be called with VDD already enabled for dpcd/edid/oui reads.
824 * In such cases we want to leave VDD enabled and it's up to upper layers
825 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
828 vdd
= edp_panel_vdd_on(intel_dp
);
830 /* dp aux is extremely sensitive to irq latency, hence request the
831 * lowest possible wakeup latency and so prevent the cpu from going into
834 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
836 intel_dp_check_edp(intel_dp
);
838 intel_aux_display_runtime_get(dev_priv
);
840 /* Try to wait for any previous AUX channel activity */
841 for (try = 0; try < 3; try++) {
842 status
= I915_READ_NOTRACE(ch_ctl
);
843 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
849 WARN(1, "dp_aux_ch not started status 0x%08x\n",
855 /* Only 5 data registers! */
856 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
861 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
862 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
867 /* Must try at least 3 times according to DP spec */
868 for (try = 0; try < 5; try++) {
869 /* Load the send data into the aux channel data registers */
870 for (i
= 0; i
< send_bytes
; i
+= 4)
871 I915_WRITE(ch_data
+ i
,
872 intel_dp_pack_aux(send
+ i
,
875 /* Send the command and wait for it to complete */
876 I915_WRITE(ch_ctl
, send_ctl
);
878 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
880 /* Clear done status and any errors */
884 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
885 DP_AUX_CH_CTL_RECEIVE_ERROR
);
887 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
888 DP_AUX_CH_CTL_RECEIVE_ERROR
))
890 if (status
& DP_AUX_CH_CTL_DONE
)
893 if (status
& DP_AUX_CH_CTL_DONE
)
897 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
898 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
903 /* Check for timeout or receive error.
904 * Timeouts occur when the sink is not connected
906 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
907 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
912 /* Timeouts occur when the device isn't connected, so they're
913 * "normal" -- don't fill the kernel log with these */
914 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
915 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
920 /* Unload any bytes sent back from the other side */
921 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
922 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
923 if (recv_bytes
> recv_size
)
924 recv_bytes
= recv_size
;
926 for (i
= 0; i
< recv_bytes
; i
+= 4)
927 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
928 recv
+ i
, recv_bytes
- i
);
932 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
933 intel_aux_display_runtime_put(dev_priv
);
936 edp_panel_vdd_off(intel_dp
, false);
938 pps_unlock(intel_dp
);
943 #define BARE_ADDRESS_SIZE 3
944 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
946 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
948 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
949 uint8_t txbuf
[20], rxbuf
[20];
950 size_t txsize
, rxsize
;
953 txbuf
[0] = msg
->request
<< 4;
954 txbuf
[1] = msg
->address
>> 8;
955 txbuf
[2] = msg
->address
& 0xff;
956 txbuf
[3] = msg
->size
- 1;
958 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
959 case DP_AUX_NATIVE_WRITE
:
960 case DP_AUX_I2C_WRITE
:
961 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
964 if (WARN_ON(txsize
> 20))
967 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
969 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
971 msg
->reply
= rxbuf
[0] >> 4;
973 /* Return payload size. */
978 case DP_AUX_NATIVE_READ
:
979 case DP_AUX_I2C_READ
:
980 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
981 rxsize
= msg
->size
+ 1;
983 if (WARN_ON(rxsize
> 20))
986 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
988 msg
->reply
= rxbuf
[0] >> 4;
990 * Assume happy day, and copy the data. The caller is
991 * expected to check msg->reply before touching it.
993 * Return payload size.
996 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1009 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1011 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1012 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1013 enum port port
= intel_dig_port
->port
;
1014 const char *name
= NULL
;
1019 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1023 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1027 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1031 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1039 * The AUX_CTL register is usually DP_CTL + 0x10.
1041 * On Haswell and Broadwell though:
1042 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1043 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1045 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1047 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1048 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1050 intel_dp
->aux
.name
= name
;
1051 intel_dp
->aux
.dev
= dev
->dev
;
1052 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1054 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1055 connector
->base
.kdev
->kobj
.name
);
1057 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1059 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1064 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1065 &intel_dp
->aux
.ddc
.dev
.kobj
,
1066 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1068 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1069 drm_dp_aux_unregister(&intel_dp
->aux
);
1074 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1076 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1078 if (!intel_connector
->mst_port
)
1079 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1080 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1081 intel_connector_unregister(intel_connector
);
1085 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_clock
)
1089 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1090 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1091 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1093 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1094 switch (link_clock
/ 2) {
1096 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810
,
1100 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350
,
1104 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700
,
1108 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620
,
1111 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1112 results in CDCLK change. Need to handle the change of CDCLK by
1113 disabling pipes and re-enabling them */
1115 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080
,
1119 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160
,
1124 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1128 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1131 case DP_LINK_BW_1_62
:
1132 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1134 case DP_LINK_BW_2_7
:
1135 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1137 case DP_LINK_BW_5_4
:
1138 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1144 intel_read_sink_rates(struct intel_dp
*intel_dp
, int *sink_rates
)
1146 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1148 if (INTEL_INFO(dev
)->gen
>= 9 && intel_dp
->supported_rates
[0]) {
1150 * Receiver supports only main-link rate selection by
1151 * link rate table method, so read link rates from
1152 * supported_link_rates
1154 memcpy(sink_rates
, intel_dp
->supported_rates
,
1155 sizeof(intel_dp
->supported_rates
));
1157 return intel_dp
->num_supported_rates
;
1163 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1165 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1167 if (INTEL_INFO(dev
)->gen
>= 9) {
1168 *source_rates
= gen9_rates
;
1169 return ARRAY_SIZE(gen9_rates
);
1172 *source_rates
= default_rates
;
1174 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1178 intel_dp_set_clock(struct intel_encoder
*encoder
,
1179 struct intel_crtc_state
*pipe_config
, int link_bw
)
1181 struct drm_device
*dev
= encoder
->base
.dev
;
1182 const struct dp_link_dpll
*divisor
= NULL
;
1186 divisor
= gen4_dpll
;
1187 count
= ARRAY_SIZE(gen4_dpll
);
1188 } else if (HAS_PCH_SPLIT(dev
)) {
1190 count
= ARRAY_SIZE(pch_dpll
);
1191 } else if (IS_CHERRYVIEW(dev
)) {
1193 count
= ARRAY_SIZE(chv_dpll
);
1194 } else if (IS_VALLEYVIEW(dev
)) {
1196 count
= ARRAY_SIZE(vlv_dpll
);
1199 if (divisor
&& count
) {
1200 for (i
= 0; i
< count
; i
++) {
1201 if (link_bw
== divisor
[i
].link_bw
) {
1202 pipe_config
->dpll
= divisor
[i
].dpll
;
1203 pipe_config
->clock_set
= true;
1210 static int intel_supported_rates(const int *source_rates
, int source_len
,
1211 const int *sink_rates
, int sink_len
,
1212 int *supported_rates
)
1214 int i
= 0, j
= 0, k
= 0;
1216 /* For panels with edp version less than 1.4 */
1217 if (sink_len
== 0) {
1218 for (i
= 0; i
< source_len
; ++i
)
1219 supported_rates
[i
] = source_rates
[i
];
1223 /* For edp1.4 panels, find the common rates between source and sink */
1224 while (i
< source_len
&& j
< sink_len
) {
1225 if (source_rates
[i
] == sink_rates
[j
]) {
1226 supported_rates
[k
] = source_rates
[i
];
1230 } else if (source_rates
[i
] < sink_rates
[j
]) {
1239 static int rate_to_index(int find
, const int *rates
)
1243 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1244 if (find
== rates
[i
])
1251 intel_dp_compute_config(struct intel_encoder
*encoder
,
1252 struct intel_crtc_state
*pipe_config
)
1254 struct drm_device
*dev
= encoder
->base
.dev
;
1255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1256 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1257 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1258 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1259 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1260 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1261 int lane_count
, clock
;
1262 int min_lane_count
= 1;
1263 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1264 /* Conveniently, the link BW constants become indices with a shift...*/
1268 int link_avail
, link_clock
;
1270 int supported_rates
[8] = {0};
1271 const int *source_rates
;
1272 int source_len
, sink_len
, supported_len
;
1274 sink_len
= intel_read_sink_rates(intel_dp
, sink_rates
);
1276 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1278 supported_len
= intel_supported_rates(source_rates
, source_len
,
1279 sink_rates
, sink_len
, supported_rates
);
1281 /* No common link rates between source and sink */
1282 WARN_ON(supported_len
<= 0);
1284 max_clock
= supported_len
- 1;
1286 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1287 pipe_config
->has_pch_encoder
= true;
1289 pipe_config
->has_dp_encoder
= true;
1290 pipe_config
->has_drrs
= false;
1291 pipe_config
->has_audio
= intel_dp
->has_audio
;
1293 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1294 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1296 if (!HAS_PCH_SPLIT(dev
))
1297 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1298 intel_connector
->panel
.fitting_mode
);
1300 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1301 intel_connector
->panel
.fitting_mode
);
1304 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1307 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1308 "max bw %d pixel clock %iKHz\n",
1309 max_lane_count
, supported_rates
[max_clock
],
1310 adjusted_mode
->crtc_clock
);
1312 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1313 * bpc in between. */
1314 bpp
= pipe_config
->pipe_bpp
;
1315 if (is_edp(intel_dp
)) {
1316 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1317 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1318 dev_priv
->vbt
.edp_bpp
);
1319 bpp
= dev_priv
->vbt
.edp_bpp
;
1323 * Use the maximum clock and number of lanes the eDP panel
1324 * advertizes being capable of. The panels are generally
1325 * designed to support only a single clock and lane
1326 * configuration, and typically these values correspond to the
1327 * native resolution of the panel.
1329 min_lane_count
= max_lane_count
;
1330 min_clock
= max_clock
;
1333 for (; bpp
>= 6*3; bpp
-= 2*3) {
1334 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1337 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1338 for (lane_count
= min_lane_count
;
1339 lane_count
<= max_lane_count
;
1342 link_clock
= supported_rates
[clock
];
1343 link_avail
= intel_dp_max_data_rate(link_clock
,
1346 if (mode_rate
<= link_avail
) {
1356 if (intel_dp
->color_range_auto
) {
1359 * CEA-861-E - 5.1 Default Encoding Parameters
1360 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1362 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1363 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1365 intel_dp
->color_range
= 0;
1368 if (intel_dp
->color_range
)
1369 pipe_config
->limited_color_range
= true;
1371 intel_dp
->lane_count
= lane_count
;
1374 drm_dp_link_rate_to_bw_code(supported_rates
[clock
]);
1376 if (INTEL_INFO(dev
)->gen
>= 9 && intel_dp
->supported_rates
[0]) {
1377 intel_dp
->rate_select
=
1378 rate_to_index(supported_rates
[clock
], sink_rates
);
1379 intel_dp
->link_bw
= 0;
1382 pipe_config
->pipe_bpp
= bpp
;
1383 pipe_config
->port_clock
= supported_rates
[clock
];
1385 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1386 intel_dp
->link_bw
, intel_dp
->lane_count
,
1387 pipe_config
->port_clock
, bpp
);
1388 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1389 mode_rate
, link_avail
);
1391 intel_link_compute_m_n(bpp
, lane_count
,
1392 adjusted_mode
->crtc_clock
,
1393 pipe_config
->port_clock
,
1394 &pipe_config
->dp_m_n
);
1396 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1397 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1398 pipe_config
->has_drrs
= true;
1399 intel_link_compute_m_n(bpp
, lane_count
,
1400 intel_connector
->panel
.downclock_mode
->clock
,
1401 pipe_config
->port_clock
,
1402 &pipe_config
->dp_m2_n2
);
1405 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1406 skl_edp_set_pll_config(pipe_config
, supported_rates
[clock
]);
1407 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1408 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1410 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1415 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1417 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1418 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1419 struct drm_device
*dev
= crtc
->base
.dev
;
1420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1423 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1424 crtc
->config
->port_clock
);
1425 dpa_ctl
= I915_READ(DP_A
);
1426 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1428 if (crtc
->config
->port_clock
== 162000) {
1429 /* For a long time we've carried around a ILK-DevA w/a for the
1430 * 160MHz clock. If we're really unlucky, it's still required.
1432 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1433 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1434 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1436 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1437 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1440 I915_WRITE(DP_A
, dpa_ctl
);
1446 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1448 struct drm_device
*dev
= encoder
->base
.dev
;
1449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1450 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1451 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1452 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1453 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1456 * There are four kinds of DP registers:
1463 * IBX PCH and CPU are the same for almost everything,
1464 * except that the CPU DP PLL is configured in this
1467 * CPT PCH is quite different, having many bits moved
1468 * to the TRANS_DP_CTL register instead. That
1469 * configuration happens (oddly) in ironlake_pch_enable
1472 /* Preserve the BIOS-computed detected bit. This is
1473 * supposed to be read-only.
1475 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1477 /* Handle DP bits in common between all three register formats */
1478 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1479 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1481 if (crtc
->config
->has_audio
)
1482 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1484 /* Split out the IBX/CPU vs CPT settings */
1486 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1487 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1488 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1489 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1490 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1491 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1493 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1494 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1496 intel_dp
->DP
|= crtc
->pipe
<< 29;
1497 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1498 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1499 intel_dp
->DP
|= intel_dp
->color_range
;
1501 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1502 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1503 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1504 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1505 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1507 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1508 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1510 if (!IS_CHERRYVIEW(dev
)) {
1511 if (crtc
->pipe
== 1)
1512 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1514 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1517 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1521 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1522 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1524 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1525 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1527 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1528 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1530 static void wait_panel_status(struct intel_dp
*intel_dp
,
1534 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 u32 pp_stat_reg
, pp_ctrl_reg
;
1538 lockdep_assert_held(&dev_priv
->pps_mutex
);
1540 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1541 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1543 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1545 I915_READ(pp_stat_reg
),
1546 I915_READ(pp_ctrl_reg
));
1548 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1549 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1550 I915_READ(pp_stat_reg
),
1551 I915_READ(pp_ctrl_reg
));
1554 DRM_DEBUG_KMS("Wait complete\n");
1557 static void wait_panel_on(struct intel_dp
*intel_dp
)
1559 DRM_DEBUG_KMS("Wait for panel power on\n");
1560 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1563 static void wait_panel_off(struct intel_dp
*intel_dp
)
1565 DRM_DEBUG_KMS("Wait for panel power off time\n");
1566 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1569 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1571 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1573 /* When we disable the VDD override bit last we have to do the manual
1575 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1576 intel_dp
->panel_power_cycle_delay
);
1578 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1581 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1583 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1584 intel_dp
->backlight_on_delay
);
1587 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1589 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1590 intel_dp
->backlight_off_delay
);
1593 /* Read the current pp_control value, unlocking the register if it
1597 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1599 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1603 lockdep_assert_held(&dev_priv
->pps_mutex
);
1605 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1606 control
&= ~PANEL_UNLOCK_MASK
;
1607 control
|= PANEL_UNLOCK_REGS
;
1612 * Must be paired with edp_panel_vdd_off().
1613 * Must hold pps_mutex around the whole on/off sequence.
1614 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1616 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1618 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1619 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1620 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1622 enum intel_display_power_domain power_domain
;
1624 u32 pp_stat_reg
, pp_ctrl_reg
;
1625 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1627 lockdep_assert_held(&dev_priv
->pps_mutex
);
1629 if (!is_edp(intel_dp
))
1632 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1633 intel_dp
->want_panel_vdd
= true;
1635 if (edp_have_panel_vdd(intel_dp
))
1636 return need_to_disable
;
1638 power_domain
= intel_display_port_power_domain(intel_encoder
);
1639 intel_display_power_get(dev_priv
, power_domain
);
1641 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1642 port_name(intel_dig_port
->port
));
1644 if (!edp_have_panel_power(intel_dp
))
1645 wait_panel_power_cycle(intel_dp
);
1647 pp
= ironlake_get_pp_control(intel_dp
);
1648 pp
|= EDP_FORCE_VDD
;
1650 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1651 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1653 I915_WRITE(pp_ctrl_reg
, pp
);
1654 POSTING_READ(pp_ctrl_reg
);
1655 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1656 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1658 * If the panel wasn't on, delay before accessing aux channel
1660 if (!edp_have_panel_power(intel_dp
)) {
1661 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1662 port_name(intel_dig_port
->port
));
1663 msleep(intel_dp
->panel_power_up_delay
);
1666 return need_to_disable
;
1670 * Must be paired with intel_edp_panel_vdd_off() or
1671 * intel_edp_panel_off().
1672 * Nested calls to these functions are not allowed since
1673 * we drop the lock. Caller must use some higher level
1674 * locking to prevent nested calls from other threads.
1676 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1680 if (!is_edp(intel_dp
))
1684 vdd
= edp_panel_vdd_on(intel_dp
);
1685 pps_unlock(intel_dp
);
1687 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1688 port_name(dp_to_dig_port(intel_dp
)->port
));
1691 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1693 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1695 struct intel_digital_port
*intel_dig_port
=
1696 dp_to_dig_port(intel_dp
);
1697 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1698 enum intel_display_power_domain power_domain
;
1700 u32 pp_stat_reg
, pp_ctrl_reg
;
1702 lockdep_assert_held(&dev_priv
->pps_mutex
);
1704 WARN_ON(intel_dp
->want_panel_vdd
);
1706 if (!edp_have_panel_vdd(intel_dp
))
1709 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1710 port_name(intel_dig_port
->port
));
1712 pp
= ironlake_get_pp_control(intel_dp
);
1713 pp
&= ~EDP_FORCE_VDD
;
1715 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1716 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1718 I915_WRITE(pp_ctrl_reg
, pp
);
1719 POSTING_READ(pp_ctrl_reg
);
1721 /* Make sure sequencer is idle before allowing subsequent activity */
1722 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1723 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1725 if ((pp
& POWER_TARGET_ON
) == 0)
1726 intel_dp
->last_power_cycle
= jiffies
;
1728 power_domain
= intel_display_port_power_domain(intel_encoder
);
1729 intel_display_power_put(dev_priv
, power_domain
);
1732 static void edp_panel_vdd_work(struct work_struct
*__work
)
1734 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1735 struct intel_dp
, panel_vdd_work
);
1738 if (!intel_dp
->want_panel_vdd
)
1739 edp_panel_vdd_off_sync(intel_dp
);
1740 pps_unlock(intel_dp
);
1743 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1745 unsigned long delay
;
1748 * Queue the timer to fire a long time from now (relative to the power
1749 * down delay) to keep the panel power up across a sequence of
1752 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1753 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1757 * Must be paired with edp_panel_vdd_on().
1758 * Must hold pps_mutex around the whole on/off sequence.
1759 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1761 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1763 struct drm_i915_private
*dev_priv
=
1764 intel_dp_to_dev(intel_dp
)->dev_private
;
1766 lockdep_assert_held(&dev_priv
->pps_mutex
);
1768 if (!is_edp(intel_dp
))
1771 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1772 port_name(dp_to_dig_port(intel_dp
)->port
));
1774 intel_dp
->want_panel_vdd
= false;
1777 edp_panel_vdd_off_sync(intel_dp
);
1779 edp_panel_vdd_schedule_off(intel_dp
);
1782 static void edp_panel_on(struct intel_dp
*intel_dp
)
1784 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1789 lockdep_assert_held(&dev_priv
->pps_mutex
);
1791 if (!is_edp(intel_dp
))
1794 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1795 port_name(dp_to_dig_port(intel_dp
)->port
));
1797 if (WARN(edp_have_panel_power(intel_dp
),
1798 "eDP port %c panel power already on\n",
1799 port_name(dp_to_dig_port(intel_dp
)->port
)))
1802 wait_panel_power_cycle(intel_dp
);
1804 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1805 pp
= ironlake_get_pp_control(intel_dp
);
1807 /* ILK workaround: disable reset around power sequence */
1808 pp
&= ~PANEL_POWER_RESET
;
1809 I915_WRITE(pp_ctrl_reg
, pp
);
1810 POSTING_READ(pp_ctrl_reg
);
1813 pp
|= POWER_TARGET_ON
;
1815 pp
|= PANEL_POWER_RESET
;
1817 I915_WRITE(pp_ctrl_reg
, pp
);
1818 POSTING_READ(pp_ctrl_reg
);
1820 wait_panel_on(intel_dp
);
1821 intel_dp
->last_power_on
= jiffies
;
1824 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1825 I915_WRITE(pp_ctrl_reg
, pp
);
1826 POSTING_READ(pp_ctrl_reg
);
1830 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1832 if (!is_edp(intel_dp
))
1836 edp_panel_on(intel_dp
);
1837 pps_unlock(intel_dp
);
1841 static void edp_panel_off(struct intel_dp
*intel_dp
)
1843 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1844 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1845 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1847 enum intel_display_power_domain power_domain
;
1851 lockdep_assert_held(&dev_priv
->pps_mutex
);
1853 if (!is_edp(intel_dp
))
1856 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1857 port_name(dp_to_dig_port(intel_dp
)->port
));
1859 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1860 port_name(dp_to_dig_port(intel_dp
)->port
));
1862 pp
= ironlake_get_pp_control(intel_dp
);
1863 /* We need to switch off panel power _and_ force vdd, for otherwise some
1864 * panels get very unhappy and cease to work. */
1865 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1868 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1870 intel_dp
->want_panel_vdd
= false;
1872 I915_WRITE(pp_ctrl_reg
, pp
);
1873 POSTING_READ(pp_ctrl_reg
);
1875 intel_dp
->last_power_cycle
= jiffies
;
1876 wait_panel_off(intel_dp
);
1878 /* We got a reference when we enabled the VDD. */
1879 power_domain
= intel_display_port_power_domain(intel_encoder
);
1880 intel_display_power_put(dev_priv
, power_domain
);
1883 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1885 if (!is_edp(intel_dp
))
1889 edp_panel_off(intel_dp
);
1890 pps_unlock(intel_dp
);
1893 /* Enable backlight in the panel power control. */
1894 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1896 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1897 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1903 * If we enable the backlight right away following a panel power
1904 * on, we may see slight flicker as the panel syncs with the eDP
1905 * link. So delay a bit to make sure the image is solid before
1906 * allowing it to appear.
1908 wait_backlight_on(intel_dp
);
1912 pp
= ironlake_get_pp_control(intel_dp
);
1913 pp
|= EDP_BLC_ENABLE
;
1915 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1917 I915_WRITE(pp_ctrl_reg
, pp
);
1918 POSTING_READ(pp_ctrl_reg
);
1920 pps_unlock(intel_dp
);
1923 /* Enable backlight PWM and backlight PP control. */
1924 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1926 if (!is_edp(intel_dp
))
1929 DRM_DEBUG_KMS("\n");
1931 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1932 _intel_edp_backlight_on(intel_dp
);
1935 /* Disable backlight in the panel power control. */
1936 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1938 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1943 if (!is_edp(intel_dp
))
1948 pp
= ironlake_get_pp_control(intel_dp
);
1949 pp
&= ~EDP_BLC_ENABLE
;
1951 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1953 I915_WRITE(pp_ctrl_reg
, pp
);
1954 POSTING_READ(pp_ctrl_reg
);
1956 pps_unlock(intel_dp
);
1958 intel_dp
->last_backlight_off
= jiffies
;
1959 edp_wait_backlight_off(intel_dp
);
1962 /* Disable backlight PP control and backlight PWM. */
1963 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1965 if (!is_edp(intel_dp
))
1968 DRM_DEBUG_KMS("\n");
1970 _intel_edp_backlight_off(intel_dp
);
1971 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1975 * Hook for controlling the panel power control backlight through the bl_power
1976 * sysfs attribute. Take care to handle multiple calls.
1978 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1981 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1985 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1986 pps_unlock(intel_dp
);
1988 if (is_enabled
== enable
)
1991 DRM_DEBUG_KMS("panel power control backlight %s\n",
1992 enable
? "enable" : "disable");
1995 _intel_edp_backlight_on(intel_dp
);
1997 _intel_edp_backlight_off(intel_dp
);
2000 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2002 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2003 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2004 struct drm_device
*dev
= crtc
->dev
;
2005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2008 assert_pipe_disabled(dev_priv
,
2009 to_intel_crtc(crtc
)->pipe
);
2011 DRM_DEBUG_KMS("\n");
2012 dpa_ctl
= I915_READ(DP_A
);
2013 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2014 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2016 /* We don't adjust intel_dp->DP while tearing down the link, to
2017 * facilitate link retraining (e.g. after hotplug). Hence clear all
2018 * enable bits here to ensure that we don't enable too much. */
2019 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2020 intel_dp
->DP
|= DP_PLL_ENABLE
;
2021 I915_WRITE(DP_A
, intel_dp
->DP
);
2026 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2028 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2029 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2030 struct drm_device
*dev
= crtc
->dev
;
2031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2034 assert_pipe_disabled(dev_priv
,
2035 to_intel_crtc(crtc
)->pipe
);
2037 dpa_ctl
= I915_READ(DP_A
);
2038 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2039 "dp pll off, should be on\n");
2040 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2042 /* We can't rely on the value tracked for the DP register in
2043 * intel_dp->DP because link_down must not change that (otherwise link
2044 * re-training will fail. */
2045 dpa_ctl
&= ~DP_PLL_ENABLE
;
2046 I915_WRITE(DP_A
, dpa_ctl
);
2051 /* If the sink supports it, try to set the power state appropriately */
2052 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2056 /* Should have a valid DPCD by this point */
2057 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2060 if (mode
!= DRM_MODE_DPMS_ON
) {
2061 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2065 * When turning on, we need to retry for 1ms to give the sink
2068 for (i
= 0; i
< 3; i
++) {
2069 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2078 DRM_DEBUG_KMS("failed to %s sink power state\n",
2079 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2082 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2085 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2086 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2087 struct drm_device
*dev
= encoder
->base
.dev
;
2088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2089 enum intel_display_power_domain power_domain
;
2092 power_domain
= intel_display_port_power_domain(encoder
);
2093 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2096 tmp
= I915_READ(intel_dp
->output_reg
);
2098 if (!(tmp
& DP_PORT_EN
))
2101 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
2102 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2103 } else if (IS_CHERRYVIEW(dev
)) {
2104 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2105 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
2106 *pipe
= PORT_TO_PIPE(tmp
);
2112 switch (intel_dp
->output_reg
) {
2114 trans_sel
= TRANS_DP_PORT_SEL_B
;
2117 trans_sel
= TRANS_DP_PORT_SEL_C
;
2120 trans_sel
= TRANS_DP_PORT_SEL_D
;
2126 for_each_pipe(dev_priv
, i
) {
2127 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
2128 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
2134 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2135 intel_dp
->output_reg
);
2141 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2142 struct intel_crtc_state
*pipe_config
)
2144 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2146 struct drm_device
*dev
= encoder
->base
.dev
;
2147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2148 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2149 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2152 tmp
= I915_READ(intel_dp
->output_reg
);
2153 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
2154 pipe_config
->has_audio
= true;
2156 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
2157 if (tmp
& DP_SYNC_HS_HIGH
)
2158 flags
|= DRM_MODE_FLAG_PHSYNC
;
2160 flags
|= DRM_MODE_FLAG_NHSYNC
;
2162 if (tmp
& DP_SYNC_VS_HIGH
)
2163 flags
|= DRM_MODE_FLAG_PVSYNC
;
2165 flags
|= DRM_MODE_FLAG_NVSYNC
;
2167 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2168 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2169 flags
|= DRM_MODE_FLAG_PHSYNC
;
2171 flags
|= DRM_MODE_FLAG_NHSYNC
;
2173 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2174 flags
|= DRM_MODE_FLAG_PVSYNC
;
2176 flags
|= DRM_MODE_FLAG_NVSYNC
;
2179 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2181 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2182 tmp
& DP_COLOR_RANGE_16_235
)
2183 pipe_config
->limited_color_range
= true;
2185 pipe_config
->has_dp_encoder
= true;
2187 intel_dp_get_m_n(crtc
, pipe_config
);
2189 if (port
== PORT_A
) {
2190 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2191 pipe_config
->port_clock
= 162000;
2193 pipe_config
->port_clock
= 270000;
2196 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2197 &pipe_config
->dp_m_n
);
2199 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2200 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2202 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2204 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2205 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2207 * This is a big fat ugly hack.
2209 * Some machines in UEFI boot mode provide us a VBT that has 18
2210 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2211 * unknown we fail to light up. Yet the same BIOS boots up with
2212 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2213 * max, not what it tells us to use.
2215 * Note: This will still be broken if the eDP panel is not lit
2216 * up by the BIOS, and thus we can't get the mode at module
2219 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2220 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2221 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2225 static void intel_disable_dp(struct intel_encoder
*encoder
)
2227 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2228 struct drm_device
*dev
= encoder
->base
.dev
;
2229 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2231 if (crtc
->config
->has_audio
)
2232 intel_audio_codec_disable(encoder
);
2234 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2235 intel_psr_disable(intel_dp
);
2237 /* Make sure the panel is off before trying to change the mode. But also
2238 * ensure that we have vdd while we switch off the panel. */
2239 intel_edp_panel_vdd_on(intel_dp
);
2240 intel_edp_backlight_off(intel_dp
);
2241 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2242 intel_edp_panel_off(intel_dp
);
2244 /* disable the port before the pipe on g4x */
2245 if (INTEL_INFO(dev
)->gen
< 5)
2246 intel_dp_link_down(intel_dp
);
2249 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2251 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2252 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2254 intel_dp_link_down(intel_dp
);
2256 ironlake_edp_pll_off(intel_dp
);
2259 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2261 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2263 intel_dp_link_down(intel_dp
);
2266 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2268 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2269 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2270 struct drm_device
*dev
= encoder
->base
.dev
;
2271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2272 struct intel_crtc
*intel_crtc
=
2273 to_intel_crtc(encoder
->base
.crtc
);
2274 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2275 enum pipe pipe
= intel_crtc
->pipe
;
2278 intel_dp_link_down(intel_dp
);
2280 mutex_lock(&dev_priv
->dpio_lock
);
2282 /* Propagate soft reset to data lane reset */
2283 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2284 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2285 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2287 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2288 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2289 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2291 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2292 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2293 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2295 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2296 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2297 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2299 mutex_unlock(&dev_priv
->dpio_lock
);
2303 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2305 uint8_t dp_train_pat
)
2307 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2308 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2310 enum port port
= intel_dig_port
->port
;
2313 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2315 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2316 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2318 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2320 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2321 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2322 case DP_TRAINING_PATTERN_DISABLE
:
2323 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2326 case DP_TRAINING_PATTERN_1
:
2327 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2329 case DP_TRAINING_PATTERN_2
:
2330 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2332 case DP_TRAINING_PATTERN_3
:
2333 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2336 I915_WRITE(DP_TP_CTL(port
), temp
);
2338 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2339 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2341 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2342 case DP_TRAINING_PATTERN_DISABLE
:
2343 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2345 case DP_TRAINING_PATTERN_1
:
2346 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2348 case DP_TRAINING_PATTERN_2
:
2349 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2351 case DP_TRAINING_PATTERN_3
:
2352 DRM_ERROR("DP training pattern 3 not supported\n");
2353 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2358 if (IS_CHERRYVIEW(dev
))
2359 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2361 *DP
&= ~DP_LINK_TRAIN_MASK
;
2363 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2364 case DP_TRAINING_PATTERN_DISABLE
:
2365 *DP
|= DP_LINK_TRAIN_OFF
;
2367 case DP_TRAINING_PATTERN_1
:
2368 *DP
|= DP_LINK_TRAIN_PAT_1
;
2370 case DP_TRAINING_PATTERN_2
:
2371 *DP
|= DP_LINK_TRAIN_PAT_2
;
2373 case DP_TRAINING_PATTERN_3
:
2374 if (IS_CHERRYVIEW(dev
)) {
2375 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2377 DRM_ERROR("DP training pattern 3 not supported\n");
2378 *DP
|= DP_LINK_TRAIN_PAT_2
;
2385 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2387 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2390 /* enable with pattern 1 (as per spec) */
2391 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2392 DP_TRAINING_PATTERN_1
);
2394 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2395 POSTING_READ(intel_dp
->output_reg
);
2398 * Magic for VLV/CHV. We _must_ first set up the register
2399 * without actually enabling the port, and then do another
2400 * write to enable the port. Otherwise link training will
2401 * fail when the power sequencer is freshly used for this port.
2403 intel_dp
->DP
|= DP_PORT_EN
;
2405 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2406 POSTING_READ(intel_dp
->output_reg
);
2409 static void intel_enable_dp(struct intel_encoder
*encoder
)
2411 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2412 struct drm_device
*dev
= encoder
->base
.dev
;
2413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2414 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2415 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2417 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2422 if (IS_VALLEYVIEW(dev
))
2423 vlv_init_panel_power_sequencer(intel_dp
);
2425 intel_dp_enable_port(intel_dp
);
2427 edp_panel_vdd_on(intel_dp
);
2428 edp_panel_on(intel_dp
);
2429 edp_panel_vdd_off(intel_dp
, true);
2431 pps_unlock(intel_dp
);
2433 if (IS_VALLEYVIEW(dev
))
2434 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
));
2436 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2437 intel_dp_start_link_train(intel_dp
);
2438 intel_dp_complete_link_train(intel_dp
);
2439 intel_dp_stop_link_train(intel_dp
);
2441 if (crtc
->config
->has_audio
) {
2442 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2443 pipe_name(crtc
->pipe
));
2444 intel_audio_codec_enable(encoder
);
2448 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2450 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2452 intel_enable_dp(encoder
);
2453 intel_edp_backlight_on(intel_dp
);
2456 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2458 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2460 intel_edp_backlight_on(intel_dp
);
2461 intel_psr_enable(intel_dp
);
2464 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2466 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2467 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2469 intel_dp_prepare(encoder
);
2471 /* Only ilk+ has port A */
2472 if (dport
->port
== PORT_A
) {
2473 ironlake_set_pll_cpu_edp(intel_dp
);
2474 ironlake_edp_pll_on(intel_dp
);
2478 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2480 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2481 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2482 enum pipe pipe
= intel_dp
->pps_pipe
;
2483 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2485 edp_panel_vdd_off_sync(intel_dp
);
2488 * VLV seems to get confused when multiple power seqeuencers
2489 * have the same port selected (even if only one has power/vdd
2490 * enabled). The failure manifests as vlv_wait_port_ready() failing
2491 * CHV on the other hand doesn't seem to mind having the same port
2492 * selected in multiple power seqeuencers, but let's clear the
2493 * port select always when logically disconnecting a power sequencer
2496 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2497 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2498 I915_WRITE(pp_on_reg
, 0);
2499 POSTING_READ(pp_on_reg
);
2501 intel_dp
->pps_pipe
= INVALID_PIPE
;
2504 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2508 struct intel_encoder
*encoder
;
2510 lockdep_assert_held(&dev_priv
->pps_mutex
);
2512 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2515 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2517 struct intel_dp
*intel_dp
;
2520 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2523 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2524 port
= dp_to_dig_port(intel_dp
)->port
;
2526 if (intel_dp
->pps_pipe
!= pipe
)
2529 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2530 pipe_name(pipe
), port_name(port
));
2532 WARN(encoder
->connectors_active
,
2533 "stealing pipe %c power sequencer from active eDP port %c\n",
2534 pipe_name(pipe
), port_name(port
));
2536 /* make sure vdd is off before we steal it */
2537 vlv_detach_power_sequencer(intel_dp
);
2541 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2543 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2544 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2545 struct drm_device
*dev
= encoder
->base
.dev
;
2546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2549 lockdep_assert_held(&dev_priv
->pps_mutex
);
2551 if (!is_edp(intel_dp
))
2554 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2558 * If another power sequencer was being used on this
2559 * port previously make sure to turn off vdd there while
2560 * we still have control of it.
2562 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2563 vlv_detach_power_sequencer(intel_dp
);
2566 * We may be stealing the power
2567 * sequencer from another port.
2569 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2571 /* now it's all ours */
2572 intel_dp
->pps_pipe
= crtc
->pipe
;
2574 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2575 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2577 /* init power sequencer on this pipe and port */
2578 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2579 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2582 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2584 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2585 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2586 struct drm_device
*dev
= encoder
->base
.dev
;
2587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2588 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2589 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2590 int pipe
= intel_crtc
->pipe
;
2593 mutex_lock(&dev_priv
->dpio_lock
);
2595 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2602 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2603 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2604 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2606 mutex_unlock(&dev_priv
->dpio_lock
);
2608 intel_enable_dp(encoder
);
2611 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2613 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2614 struct drm_device
*dev
= encoder
->base
.dev
;
2615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2616 struct intel_crtc
*intel_crtc
=
2617 to_intel_crtc(encoder
->base
.crtc
);
2618 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2619 int pipe
= intel_crtc
->pipe
;
2621 intel_dp_prepare(encoder
);
2623 /* Program Tx lane resets to default */
2624 mutex_lock(&dev_priv
->dpio_lock
);
2625 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2626 DPIO_PCS_TX_LANE2_RESET
|
2627 DPIO_PCS_TX_LANE1_RESET
);
2628 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2629 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2630 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2631 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2632 DPIO_PCS_CLK_SOFT_RESET
);
2634 /* Fix up inter-pair skew failure */
2635 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2636 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2637 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2638 mutex_unlock(&dev_priv
->dpio_lock
);
2641 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2643 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2644 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2645 struct drm_device
*dev
= encoder
->base
.dev
;
2646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2647 struct intel_crtc
*intel_crtc
=
2648 to_intel_crtc(encoder
->base
.crtc
);
2649 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2650 int pipe
= intel_crtc
->pipe
;
2654 mutex_lock(&dev_priv
->dpio_lock
);
2656 /* allow hardware to manage TX FIFO reset source */
2657 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2658 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2659 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2661 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2662 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2663 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2665 /* Deassert soft data lane reset*/
2666 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2667 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2668 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2670 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2671 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2672 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2674 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2675 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2676 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2678 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2679 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2680 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2682 /* Program Tx lane latency optimal setting*/
2683 for (i
= 0; i
< 4; i
++) {
2684 /* Set the latency optimal bit */
2685 data
= (i
== 1) ? 0x0 : 0x6;
2686 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2687 data
<< DPIO_FRC_LATENCY_SHFIT
);
2689 /* Set the upar bit */
2690 data
= (i
== 1) ? 0x0 : 0x1;
2691 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2692 data
<< DPIO_UPAR_SHIFT
);
2695 /* Data lane stagger programming */
2696 /* FIXME: Fix up value only after power analysis */
2698 mutex_unlock(&dev_priv
->dpio_lock
);
2700 intel_enable_dp(encoder
);
2703 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2705 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2706 struct drm_device
*dev
= encoder
->base
.dev
;
2707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2708 struct intel_crtc
*intel_crtc
=
2709 to_intel_crtc(encoder
->base
.crtc
);
2710 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2711 enum pipe pipe
= intel_crtc
->pipe
;
2714 intel_dp_prepare(encoder
);
2716 mutex_lock(&dev_priv
->dpio_lock
);
2718 /* program left/right clock distribution */
2719 if (pipe
!= PIPE_B
) {
2720 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2721 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2723 val
|= CHV_BUFLEFTENA1_FORCE
;
2725 val
|= CHV_BUFRIGHTENA1_FORCE
;
2726 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2728 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2729 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2731 val
|= CHV_BUFLEFTENA2_FORCE
;
2733 val
|= CHV_BUFRIGHTENA2_FORCE
;
2734 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2737 /* program clock channel usage */
2738 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2739 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2741 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2743 val
|= CHV_PCS_USEDCLKCHANNEL
;
2744 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2746 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2747 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2749 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2751 val
|= CHV_PCS_USEDCLKCHANNEL
;
2752 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2755 * This a a bit weird since generally CL
2756 * matches the pipe, but here we need to
2757 * pick the CL based on the port.
2759 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2761 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2763 val
|= CHV_CMN_USEDCLKCHANNEL
;
2764 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2766 mutex_unlock(&dev_priv
->dpio_lock
);
2770 * Native read with retry for link status and receiver capability reads for
2771 * cases where the sink may still be asleep.
2773 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2774 * supposed to retry 3 times per the spec.
2777 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2778 void *buffer
, size_t size
)
2784 * Sometime we just get the same incorrect byte repeated
2785 * over the entire buffer. Doing just one throw away read
2786 * initially seems to "solve" it.
2788 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2790 for (i
= 0; i
< 3; i
++) {
2791 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2801 * Fetch AUX CH registers 0x202 - 0x207 which contain
2802 * link status information
2805 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2807 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2810 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2813 /* These are source-specific values. */
2815 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2817 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2819 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2821 if (INTEL_INFO(dev
)->gen
>= 9) {
2822 if (dev_priv
->vbt
.edp_low_vswing
&& port
== PORT_A
)
2823 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2824 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2825 } else if (IS_VALLEYVIEW(dev
))
2826 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2827 else if (IS_GEN7(dev
) && port
== PORT_A
)
2828 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2829 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2830 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2832 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2836 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2838 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2839 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2841 if (INTEL_INFO(dev
)->gen
>= 9) {
2842 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2843 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2844 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2846 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2847 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2848 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2850 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2852 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2854 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2855 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2856 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2857 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2858 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2859 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2860 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2861 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2862 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2864 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2866 } else if (IS_VALLEYVIEW(dev
)) {
2867 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2869 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2870 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2871 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2872 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2873 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2874 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2876 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2878 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2879 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2880 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2881 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2882 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2883 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2884 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2886 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2889 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2891 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2892 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2893 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2894 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2895 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2896 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2898 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2903 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2905 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2907 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2908 struct intel_crtc
*intel_crtc
=
2909 to_intel_crtc(dport
->base
.base
.crtc
);
2910 unsigned long demph_reg_value
, preemph_reg_value
,
2911 uniqtranscale_reg_value
;
2912 uint8_t train_set
= intel_dp
->train_set
[0];
2913 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2914 int pipe
= intel_crtc
->pipe
;
2916 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2917 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2918 preemph_reg_value
= 0x0004000;
2919 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2921 demph_reg_value
= 0x2B405555;
2922 uniqtranscale_reg_value
= 0x552AB83A;
2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2925 demph_reg_value
= 0x2B404040;
2926 uniqtranscale_reg_value
= 0x5548B83A;
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2929 demph_reg_value
= 0x2B245555;
2930 uniqtranscale_reg_value
= 0x5560B83A;
2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2933 demph_reg_value
= 0x2B405555;
2934 uniqtranscale_reg_value
= 0x5598DA3A;
2940 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2941 preemph_reg_value
= 0x0002000;
2942 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2944 demph_reg_value
= 0x2B404040;
2945 uniqtranscale_reg_value
= 0x5552B83A;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2948 demph_reg_value
= 0x2B404848;
2949 uniqtranscale_reg_value
= 0x5580B83A;
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2952 demph_reg_value
= 0x2B404040;
2953 uniqtranscale_reg_value
= 0x55ADDA3A;
2959 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2960 preemph_reg_value
= 0x0000000;
2961 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2963 demph_reg_value
= 0x2B305555;
2964 uniqtranscale_reg_value
= 0x5570B83A;
2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2967 demph_reg_value
= 0x2B2B4040;
2968 uniqtranscale_reg_value
= 0x55ADDA3A;
2974 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2975 preemph_reg_value
= 0x0006000;
2976 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2978 demph_reg_value
= 0x1B405555;
2979 uniqtranscale_reg_value
= 0x55ADDA3A;
2989 mutex_lock(&dev_priv
->dpio_lock
);
2990 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2991 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2992 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2993 uniqtranscale_reg_value
);
2994 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2995 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2996 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2997 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2998 mutex_unlock(&dev_priv
->dpio_lock
);
3003 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3005 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3007 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3008 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3009 u32 deemph_reg_value
, margin_reg_value
, val
;
3010 uint8_t train_set
= intel_dp
->train_set
[0];
3011 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3012 enum pipe pipe
= intel_crtc
->pipe
;
3015 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3016 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3017 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3019 deemph_reg_value
= 128;
3020 margin_reg_value
= 52;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3023 deemph_reg_value
= 128;
3024 margin_reg_value
= 77;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3027 deemph_reg_value
= 128;
3028 margin_reg_value
= 102;
3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3031 deemph_reg_value
= 128;
3032 margin_reg_value
= 154;
3033 /* FIXME extra to set for 1200 */
3039 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3040 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3042 deemph_reg_value
= 85;
3043 margin_reg_value
= 78;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3046 deemph_reg_value
= 85;
3047 margin_reg_value
= 116;
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3050 deemph_reg_value
= 85;
3051 margin_reg_value
= 154;
3057 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3058 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3060 deemph_reg_value
= 64;
3061 margin_reg_value
= 104;
3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3064 deemph_reg_value
= 64;
3065 margin_reg_value
= 154;
3071 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3072 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3074 deemph_reg_value
= 43;
3075 margin_reg_value
= 154;
3085 mutex_lock(&dev_priv
->dpio_lock
);
3087 /* Clear calc init */
3088 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3089 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3090 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3091 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3092 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3094 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3095 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3096 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3097 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3098 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3100 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3101 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3102 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3103 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3105 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3106 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3107 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3108 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3110 /* Program swing deemph */
3111 for (i
= 0; i
< 4; i
++) {
3112 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3113 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3114 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3115 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3118 /* Program swing margin */
3119 for (i
= 0; i
< 4; i
++) {
3120 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3121 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3122 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3123 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3126 /* Disable unique transition scale */
3127 for (i
= 0; i
< 4; i
++) {
3128 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3129 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3130 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3133 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3134 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3135 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3136 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3139 * The document said it needs to set bit 27 for ch0 and bit 26
3140 * for ch1. Might be a typo in the doc.
3141 * For now, for this unique transition scale selection, set bit
3142 * 27 for ch0 and ch1.
3144 for (i
= 0; i
< 4; i
++) {
3145 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3146 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3147 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3150 for (i
= 0; i
< 4; i
++) {
3151 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3152 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3153 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3154 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3158 /* Start swing calculation */
3159 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3160 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3161 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3163 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3164 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3165 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3168 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3169 val
|= DPIO_LRC_BYPASS
;
3170 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3172 mutex_unlock(&dev_priv
->dpio_lock
);
3178 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3179 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3184 uint8_t voltage_max
;
3185 uint8_t preemph_max
;
3187 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3188 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3189 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3197 voltage_max
= intel_dp_voltage_max(intel_dp
);
3198 if (v
>= voltage_max
)
3199 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3201 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3202 if (p
>= preemph_max
)
3203 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3205 for (lane
= 0; lane
< 4; lane
++)
3206 intel_dp
->train_set
[lane
] = v
| p
;
3210 intel_gen4_signal_levels(uint8_t train_set
)
3212 uint32_t signal_levels
= 0;
3214 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3217 signal_levels
|= DP_VOLTAGE_0_4
;
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3220 signal_levels
|= DP_VOLTAGE_0_6
;
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3223 signal_levels
|= DP_VOLTAGE_0_8
;
3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3226 signal_levels
|= DP_VOLTAGE_1_2
;
3229 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3230 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3232 signal_levels
|= DP_PRE_EMPHASIS_0
;
3234 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3235 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3237 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3238 signal_levels
|= DP_PRE_EMPHASIS_6
;
3240 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3241 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3244 return signal_levels
;
3247 /* Gen6's DP voltage swing and pre-emphasis control */
3249 intel_gen6_edp_signal_levels(uint8_t train_set
)
3251 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3252 DP_TRAIN_PRE_EMPHASIS_MASK
);
3253 switch (signal_levels
) {
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3256 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3258 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3261 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3264 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3267 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3269 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3270 "0x%x\n", signal_levels
);
3271 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3275 /* Gen7's DP voltage swing and pre-emphasis control */
3277 intel_gen7_edp_signal_levels(uint8_t train_set
)
3279 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3280 DP_TRAIN_PRE_EMPHASIS_MASK
);
3281 switch (signal_levels
) {
3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3283 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3285 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3287 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3290 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3292 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3295 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3297 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3300 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3301 "0x%x\n", signal_levels
);
3302 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3306 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3308 intel_hsw_signal_levels(uint8_t train_set
)
3310 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3311 DP_TRAIN_PRE_EMPHASIS_MASK
);
3312 switch (signal_levels
) {
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3314 return DDI_BUF_TRANS_SELECT(0);
3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3316 return DDI_BUF_TRANS_SELECT(1);
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3318 return DDI_BUF_TRANS_SELECT(2);
3319 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3320 return DDI_BUF_TRANS_SELECT(3);
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3323 return DDI_BUF_TRANS_SELECT(4);
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3325 return DDI_BUF_TRANS_SELECT(5);
3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3327 return DDI_BUF_TRANS_SELECT(6);
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3330 return DDI_BUF_TRANS_SELECT(7);
3331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3332 return DDI_BUF_TRANS_SELECT(8);
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3335 return DDI_BUF_TRANS_SELECT(9);
3337 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3338 "0x%x\n", signal_levels
);
3339 return DDI_BUF_TRANS_SELECT(0);
3343 /* Properly updates "DP" with the correct signal levels. */
3345 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3347 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3348 enum port port
= intel_dig_port
->port
;
3349 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3350 uint32_t signal_levels
, mask
;
3351 uint8_t train_set
= intel_dp
->train_set
[0];
3353 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3354 signal_levels
= intel_hsw_signal_levels(train_set
);
3355 mask
= DDI_BUF_EMP_MASK
;
3356 } else if (IS_CHERRYVIEW(dev
)) {
3357 signal_levels
= intel_chv_signal_levels(intel_dp
);
3359 } else if (IS_VALLEYVIEW(dev
)) {
3360 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3362 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3363 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3364 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3365 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3366 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3367 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3369 signal_levels
= intel_gen4_signal_levels(train_set
);
3370 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3373 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3375 *DP
= (*DP
& ~mask
) | signal_levels
;
3379 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3381 uint8_t dp_train_pat
)
3383 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3384 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3386 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3389 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3391 I915_WRITE(intel_dp
->output_reg
, *DP
);
3392 POSTING_READ(intel_dp
->output_reg
);
3394 buf
[0] = dp_train_pat
;
3395 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3396 DP_TRAINING_PATTERN_DISABLE
) {
3397 /* don't write DP_TRAINING_LANEx_SET on disable */
3400 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3401 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3402 len
= intel_dp
->lane_count
+ 1;
3405 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3412 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3413 uint8_t dp_train_pat
)
3415 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3416 intel_dp_set_signal_levels(intel_dp
, DP
);
3417 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3421 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3422 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3424 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3425 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3429 intel_get_adjust_train(intel_dp
, link_status
);
3430 intel_dp_set_signal_levels(intel_dp
, DP
);
3432 I915_WRITE(intel_dp
->output_reg
, *DP
);
3433 POSTING_READ(intel_dp
->output_reg
);
3435 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3436 intel_dp
->train_set
, intel_dp
->lane_count
);
3438 return ret
== intel_dp
->lane_count
;
3441 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3443 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3444 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3446 enum port port
= intel_dig_port
->port
;
3452 val
= I915_READ(DP_TP_CTL(port
));
3453 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3454 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3455 I915_WRITE(DP_TP_CTL(port
), val
);
3458 * On PORT_A we can have only eDP in SST mode. There the only reason
3459 * we need to set idle transmission mode is to work around a HW issue
3460 * where we enable the pipe while not in idle link-training mode.
3461 * In this case there is requirement to wait for a minimum number of
3462 * idle patterns to be sent.
3467 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3469 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3472 /* Enable corresponding port and start training pattern 1 */
3474 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3476 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3477 struct drm_device
*dev
= encoder
->dev
;
3480 int voltage_tries
, loop_tries
;
3481 uint32_t DP
= intel_dp
->DP
;
3482 uint8_t link_config
[2];
3485 intel_ddi_prepare_link_retrain(encoder
);
3487 /* Write the link configuration data */
3488 link_config
[0] = intel_dp
->link_bw
;
3489 link_config
[1] = intel_dp
->lane_count
;
3490 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3491 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3492 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3493 if (INTEL_INFO(dev
)->gen
>= 9 && intel_dp
->supported_rates
[0])
3494 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3495 &intel_dp
->rate_select
, 1);
3498 link_config
[1] = DP_SET_ANSI_8B10B
;
3499 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3503 /* clock recovery */
3504 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3505 DP_TRAINING_PATTERN_1
|
3506 DP_LINK_SCRAMBLING_DISABLE
)) {
3507 DRM_ERROR("failed to enable link training\n");
3515 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3517 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3518 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3519 DRM_ERROR("failed to get link status\n");
3523 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3524 DRM_DEBUG_KMS("clock recovery OK\n");
3528 /* Check to see if we've tried the max voltage */
3529 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3530 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3532 if (i
== intel_dp
->lane_count
) {
3534 if (loop_tries
== 5) {
3535 DRM_ERROR("too many full retries, give up\n");
3538 intel_dp_reset_link_train(intel_dp
, &DP
,
3539 DP_TRAINING_PATTERN_1
|
3540 DP_LINK_SCRAMBLING_DISABLE
);
3545 /* Check to see if we've tried the same voltage 5 times */
3546 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3548 if (voltage_tries
== 5) {
3549 DRM_ERROR("too many voltage retries, give up\n");
3554 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3556 /* Update training set as requested by target */
3557 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3558 DRM_ERROR("failed to update link training\n");
3567 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3569 bool channel_eq
= false;
3570 int tries
, cr_tries
;
3571 uint32_t DP
= intel_dp
->DP
;
3572 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3574 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3575 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3576 training_pattern
= DP_TRAINING_PATTERN_3
;
3578 /* channel equalization */
3579 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3581 DP_LINK_SCRAMBLING_DISABLE
)) {
3582 DRM_ERROR("failed to start channel equalization\n");
3590 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3593 DRM_ERROR("failed to train DP, aborting\n");
3597 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3598 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3599 DRM_ERROR("failed to get link status\n");
3603 /* Make sure clock is still ok */
3604 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3605 intel_dp_start_link_train(intel_dp
);
3606 intel_dp_set_link_train(intel_dp
, &DP
,
3608 DP_LINK_SCRAMBLING_DISABLE
);
3613 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3618 /* Try 5 times, then try clock recovery if that fails */
3620 intel_dp_start_link_train(intel_dp
);
3621 intel_dp_set_link_train(intel_dp
, &DP
,
3623 DP_LINK_SCRAMBLING_DISABLE
);
3629 /* Update training set as requested by target */
3630 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3631 DRM_ERROR("failed to update link training\n");
3637 intel_dp_set_idle_link_train(intel_dp
);
3642 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3646 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3648 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3649 DP_TRAINING_PATTERN_DISABLE
);
3653 intel_dp_link_down(struct intel_dp
*intel_dp
)
3655 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3656 enum port port
= intel_dig_port
->port
;
3657 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3659 uint32_t DP
= intel_dp
->DP
;
3661 if (WARN_ON(HAS_DDI(dev
)))
3664 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3667 DRM_DEBUG_KMS("\n");
3669 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3670 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3671 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3673 if (IS_CHERRYVIEW(dev
))
3674 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3676 DP
&= ~DP_LINK_TRAIN_MASK
;
3677 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3679 POSTING_READ(intel_dp
->output_reg
);
3681 if (HAS_PCH_IBX(dev
) &&
3682 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3683 /* Hardware workaround: leaving our transcoder select
3684 * set to transcoder B while it's off will prevent the
3685 * corresponding HDMI output on transcoder A.
3687 * Combine this with another hardware workaround:
3688 * transcoder select bit can only be cleared while the
3691 DP
&= ~DP_PIPEB_SELECT
;
3692 I915_WRITE(intel_dp
->output_reg
, DP
);
3693 POSTING_READ(intel_dp
->output_reg
);
3696 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3697 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3698 POSTING_READ(intel_dp
->output_reg
);
3699 msleep(intel_dp
->panel_power_down_delay
);
3703 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3705 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3706 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3710 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3711 sizeof(intel_dp
->dpcd
)) < 0)
3712 return false; /* aux transfer failed */
3714 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3716 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3717 return false; /* DPCD not present */
3719 /* Check if the panel supports PSR */
3720 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3721 if (is_edp(intel_dp
)) {
3722 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3724 sizeof(intel_dp
->psr_dpcd
));
3725 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3726 dev_priv
->psr
.sink_support
= true;
3727 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3731 /* Training Pattern 3 support, both source and sink */
3732 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3733 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3734 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3735 intel_dp
->use_tps3
= true;
3736 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3738 intel_dp
->use_tps3
= false;
3740 /* Intermediate frequency support */
3741 if (is_edp(intel_dp
) &&
3742 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3743 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3744 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3745 __le16 supported_rates
[DP_MAX_SUPPORTED_RATES
];
3748 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3749 DP_SUPPORTED_LINK_RATES
,
3751 sizeof(supported_rates
));
3753 for (i
= 0; i
< ARRAY_SIZE(supported_rates
); i
++) {
3754 int val
= le16_to_cpu(supported_rates
[i
]);
3759 intel_dp
->supported_rates
[i
] = val
* 200;
3761 intel_dp
->num_supported_rates
= i
;
3763 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3764 DP_DWN_STRM_PORT_PRESENT
))
3765 return true; /* native DP sink */
3767 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3768 return true; /* no per-port downstream info */
3770 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3771 intel_dp
->downstream_ports
,
3772 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3773 return false; /* downstream port status fetch failed */
3779 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3783 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3786 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3787 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3788 buf
[0], buf
[1], buf
[2]);
3790 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3791 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3792 buf
[0], buf
[1], buf
[2]);
3796 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3800 if (!intel_dp
->can_mst
)
3803 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3806 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3807 if (buf
[0] & DP_MST_CAP
) {
3808 DRM_DEBUG_KMS("Sink is MST capable\n");
3809 intel_dp
->is_mst
= true;
3811 DRM_DEBUG_KMS("Sink is not MST capable\n");
3812 intel_dp
->is_mst
= false;
3816 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3817 return intel_dp
->is_mst
;
3820 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3822 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3823 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3824 struct intel_crtc
*intel_crtc
=
3825 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3830 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3833 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3836 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3839 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3840 buf
| DP_TEST_SINK_START
) < 0)
3843 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3845 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
3848 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3849 DP_TEST_SINK_MISC
, &buf
) < 0)
3851 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3852 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
3854 if (attempts
== 0) {
3855 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3859 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3862 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3864 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3865 buf
& ~DP_TEST_SINK_START
) < 0)
3872 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3874 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3875 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3876 sink_irq_vector
, 1) == 1;
3880 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3884 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3886 sink_irq_vector
, 14);
3894 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3896 /* NAK by default */
3897 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3901 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3905 if (intel_dp
->is_mst
) {
3910 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3914 /* check link status - esi[10] = 0x200c */
3915 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3916 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3917 intel_dp_start_link_train(intel_dp
);
3918 intel_dp_complete_link_train(intel_dp
);
3919 intel_dp_stop_link_train(intel_dp
);
3922 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3923 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3926 for (retry
= 0; retry
< 3; retry
++) {
3928 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3929 DP_SINK_COUNT_ESI
+1,
3936 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3938 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3946 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3947 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3948 intel_dp
->is_mst
= false;
3949 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3950 /* send a hotplug event */
3951 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3958 * According to DP spec
3961 * 2. Configure link according to Receiver Capabilities
3962 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3963 * 4. Check link status on receipt of hot-plug interrupt
3966 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3968 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3969 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3971 u8 link_status
[DP_LINK_STATUS_SIZE
];
3973 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3975 if (!intel_encoder
->connectors_active
)
3978 if (WARN_ON(!intel_encoder
->base
.crtc
))
3981 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3984 /* Try to read receiver status if the link appears to be up */
3985 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3989 /* Now read the DPCD to see if it's actually running */
3990 if (!intel_dp_get_dpcd(intel_dp
)) {
3994 /* Try to read the source of the interrupt */
3995 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3996 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3997 /* Clear interrupt source */
3998 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3999 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4002 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4003 intel_dp_handle_test_request(intel_dp
);
4004 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4005 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4008 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4009 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4010 intel_encoder
->base
.name
);
4011 intel_dp_start_link_train(intel_dp
);
4012 intel_dp_complete_link_train(intel_dp
);
4013 intel_dp_stop_link_train(intel_dp
);
4017 /* XXX this is probably wrong for multiple downstream ports */
4018 static enum drm_connector_status
4019 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4021 uint8_t *dpcd
= intel_dp
->dpcd
;
4024 if (!intel_dp_get_dpcd(intel_dp
))
4025 return connector_status_disconnected
;
4027 /* if there's no downstream port, we're done */
4028 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4029 return connector_status_connected
;
4031 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4032 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4033 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4036 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4038 return connector_status_unknown
;
4040 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4041 : connector_status_disconnected
;
4044 /* If no HPD, poke DDC gently */
4045 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4046 return connector_status_connected
;
4048 /* Well we tried, say unknown for unreliable port types */
4049 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4050 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4051 if (type
== DP_DS_PORT_TYPE_VGA
||
4052 type
== DP_DS_PORT_TYPE_NON_EDID
)
4053 return connector_status_unknown
;
4055 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4056 DP_DWN_STRM_PORT_TYPE_MASK
;
4057 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4058 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4059 return connector_status_unknown
;
4062 /* Anything else is out of spec, warn and ignore */
4063 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4064 return connector_status_disconnected
;
4067 static enum drm_connector_status
4068 edp_detect(struct intel_dp
*intel_dp
)
4070 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4071 enum drm_connector_status status
;
4073 status
= intel_panel_detect(dev
);
4074 if (status
== connector_status_unknown
)
4075 status
= connector_status_connected
;
4080 static enum drm_connector_status
4081 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4083 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4085 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4087 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4088 return connector_status_disconnected
;
4090 return intel_dp_detect_dpcd(intel_dp
);
4093 static int g4x_digital_port_connected(struct drm_device
*dev
,
4094 struct intel_digital_port
*intel_dig_port
)
4096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4099 if (IS_VALLEYVIEW(dev
)) {
4100 switch (intel_dig_port
->port
) {
4102 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4105 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4108 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4114 switch (intel_dig_port
->port
) {
4116 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4119 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4122 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4129 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4134 static enum drm_connector_status
4135 g4x_dp_detect(struct intel_dp
*intel_dp
)
4137 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4138 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4141 /* Can't disconnect eDP, but you can close the lid... */
4142 if (is_edp(intel_dp
)) {
4143 enum drm_connector_status status
;
4145 status
= intel_panel_detect(dev
);
4146 if (status
== connector_status_unknown
)
4147 status
= connector_status_connected
;
4151 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4153 return connector_status_unknown
;
4155 return connector_status_disconnected
;
4157 return intel_dp_detect_dpcd(intel_dp
);
4160 static struct edid
*
4161 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4163 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4165 /* use cached edid if we have one */
4166 if (intel_connector
->edid
) {
4168 if (IS_ERR(intel_connector
->edid
))
4171 return drm_edid_duplicate(intel_connector
->edid
);
4173 return drm_get_edid(&intel_connector
->base
,
4174 &intel_dp
->aux
.ddc
);
4178 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4180 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4183 edid
= intel_dp_get_edid(intel_dp
);
4184 intel_connector
->detect_edid
= edid
;
4186 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4187 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4189 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4193 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4195 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4197 kfree(intel_connector
->detect_edid
);
4198 intel_connector
->detect_edid
= NULL
;
4200 intel_dp
->has_audio
= false;
4203 static enum intel_display_power_domain
4204 intel_dp_power_get(struct intel_dp
*dp
)
4206 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4207 enum intel_display_power_domain power_domain
;
4209 power_domain
= intel_display_port_power_domain(encoder
);
4210 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4212 return power_domain
;
4216 intel_dp_power_put(struct intel_dp
*dp
,
4217 enum intel_display_power_domain power_domain
)
4219 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4220 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4223 static enum drm_connector_status
4224 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4226 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4227 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4228 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4229 struct drm_device
*dev
= connector
->dev
;
4230 enum drm_connector_status status
;
4231 enum intel_display_power_domain power_domain
;
4234 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4235 connector
->base
.id
, connector
->name
);
4236 intel_dp_unset_edid(intel_dp
);
4238 if (intel_dp
->is_mst
) {
4239 /* MST devices are disconnected from a monitor POV */
4240 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4241 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4242 return connector_status_disconnected
;
4245 power_domain
= intel_dp_power_get(intel_dp
);
4247 /* Can't disconnect eDP, but you can close the lid... */
4248 if (is_edp(intel_dp
))
4249 status
= edp_detect(intel_dp
);
4250 else if (HAS_PCH_SPLIT(dev
))
4251 status
= ironlake_dp_detect(intel_dp
);
4253 status
= g4x_dp_detect(intel_dp
);
4254 if (status
!= connector_status_connected
)
4257 intel_dp_probe_oui(intel_dp
);
4259 ret
= intel_dp_probe_mst(intel_dp
);
4261 /* if we are in MST mode then this connector
4262 won't appear connected or have anything with EDID on it */
4263 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4264 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4265 status
= connector_status_disconnected
;
4269 intel_dp_set_edid(intel_dp
);
4271 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4272 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4273 status
= connector_status_connected
;
4276 intel_dp_power_put(intel_dp
, power_domain
);
4281 intel_dp_force(struct drm_connector
*connector
)
4283 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4284 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4285 enum intel_display_power_domain power_domain
;
4287 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4288 connector
->base
.id
, connector
->name
);
4289 intel_dp_unset_edid(intel_dp
);
4291 if (connector
->status
!= connector_status_connected
)
4294 power_domain
= intel_dp_power_get(intel_dp
);
4296 intel_dp_set_edid(intel_dp
);
4298 intel_dp_power_put(intel_dp
, power_domain
);
4300 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4301 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4304 static int intel_dp_get_modes(struct drm_connector
*connector
)
4306 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4309 edid
= intel_connector
->detect_edid
;
4311 int ret
= intel_connector_update_modes(connector
, edid
);
4316 /* if eDP has no EDID, fall back to fixed mode */
4317 if (is_edp(intel_attached_dp(connector
)) &&
4318 intel_connector
->panel
.fixed_mode
) {
4319 struct drm_display_mode
*mode
;
4321 mode
= drm_mode_duplicate(connector
->dev
,
4322 intel_connector
->panel
.fixed_mode
);
4324 drm_mode_probed_add(connector
, mode
);
4333 intel_dp_detect_audio(struct drm_connector
*connector
)
4335 bool has_audio
= false;
4338 edid
= to_intel_connector(connector
)->detect_edid
;
4340 has_audio
= drm_detect_monitor_audio(edid
);
4346 intel_dp_set_property(struct drm_connector
*connector
,
4347 struct drm_property
*property
,
4350 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4351 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4352 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4353 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4356 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4360 if (property
== dev_priv
->force_audio_property
) {
4364 if (i
== intel_dp
->force_audio
)
4367 intel_dp
->force_audio
= i
;
4369 if (i
== HDMI_AUDIO_AUTO
)
4370 has_audio
= intel_dp_detect_audio(connector
);
4372 has_audio
= (i
== HDMI_AUDIO_ON
);
4374 if (has_audio
== intel_dp
->has_audio
)
4377 intel_dp
->has_audio
= has_audio
;
4381 if (property
== dev_priv
->broadcast_rgb_property
) {
4382 bool old_auto
= intel_dp
->color_range_auto
;
4383 uint32_t old_range
= intel_dp
->color_range
;
4386 case INTEL_BROADCAST_RGB_AUTO
:
4387 intel_dp
->color_range_auto
= true;
4389 case INTEL_BROADCAST_RGB_FULL
:
4390 intel_dp
->color_range_auto
= false;
4391 intel_dp
->color_range
= 0;
4393 case INTEL_BROADCAST_RGB_LIMITED
:
4394 intel_dp
->color_range_auto
= false;
4395 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4401 if (old_auto
== intel_dp
->color_range_auto
&&
4402 old_range
== intel_dp
->color_range
)
4408 if (is_edp(intel_dp
) &&
4409 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4410 if (val
== DRM_MODE_SCALE_NONE
) {
4411 DRM_DEBUG_KMS("no scaling not supported\n");
4415 if (intel_connector
->panel
.fitting_mode
== val
) {
4416 /* the eDP scaling property is not changed */
4419 intel_connector
->panel
.fitting_mode
= val
;
4427 if (intel_encoder
->base
.crtc
)
4428 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4434 intel_dp_connector_destroy(struct drm_connector
*connector
)
4436 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4438 kfree(intel_connector
->detect_edid
);
4440 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4441 kfree(intel_connector
->edid
);
4443 /* Can't call is_edp() since the encoder may have been destroyed
4445 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4446 intel_panel_fini(&intel_connector
->panel
);
4448 drm_connector_cleanup(connector
);
4452 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4454 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4455 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4457 drm_dp_aux_unregister(&intel_dp
->aux
);
4458 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4459 if (is_edp(intel_dp
)) {
4460 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4462 * vdd might still be enabled do to the delayed vdd off.
4463 * Make sure vdd is actually turned off here.
4466 edp_panel_vdd_off_sync(intel_dp
);
4467 pps_unlock(intel_dp
);
4469 if (intel_dp
->edp_notifier
.notifier_call
) {
4470 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4471 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4474 drm_encoder_cleanup(encoder
);
4475 kfree(intel_dig_port
);
4478 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4480 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4482 if (!is_edp(intel_dp
))
4486 * vdd might still be enabled do to the delayed vdd off.
4487 * Make sure vdd is actually turned off here.
4489 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4491 edp_panel_vdd_off_sync(intel_dp
);
4492 pps_unlock(intel_dp
);
4495 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4497 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4498 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4500 enum intel_display_power_domain power_domain
;
4502 lockdep_assert_held(&dev_priv
->pps_mutex
);
4504 if (!edp_have_panel_vdd(intel_dp
))
4508 * The VDD bit needs a power domain reference, so if the bit is
4509 * already enabled when we boot or resume, grab this reference and
4510 * schedule a vdd off, so we don't hold on to the reference
4513 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4514 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4515 intel_display_power_get(dev_priv
, power_domain
);
4517 edp_panel_vdd_schedule_off(intel_dp
);
4520 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4522 struct intel_dp
*intel_dp
;
4524 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4527 intel_dp
= enc_to_intel_dp(encoder
);
4532 * Read out the current power sequencer assignment,
4533 * in case the BIOS did something with it.
4535 if (IS_VALLEYVIEW(encoder
->dev
))
4536 vlv_initial_power_sequencer_setup(intel_dp
);
4538 intel_edp_panel_vdd_sanitize(intel_dp
);
4540 pps_unlock(intel_dp
);
4543 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4544 .dpms
= intel_connector_dpms
,
4545 .detect
= intel_dp_detect
,
4546 .force
= intel_dp_force
,
4547 .fill_modes
= drm_helper_probe_single_connector_modes
,
4548 .set_property
= intel_dp_set_property
,
4549 .atomic_get_property
= intel_connector_atomic_get_property
,
4550 .destroy
= intel_dp_connector_destroy
,
4551 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4554 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4555 .get_modes
= intel_dp_get_modes
,
4556 .mode_valid
= intel_dp_mode_valid
,
4557 .best_encoder
= intel_best_encoder
,
4560 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4561 .reset
= intel_dp_encoder_reset
,
4562 .destroy
= intel_dp_encoder_destroy
,
4566 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4572 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4574 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4575 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4576 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4578 enum intel_display_power_domain power_domain
;
4579 enum irqreturn ret
= IRQ_NONE
;
4581 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4582 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4584 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4586 * vdd off can generate a long pulse on eDP which
4587 * would require vdd on to handle it, and thus we
4588 * would end up in an endless cycle of
4589 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4591 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4592 port_name(intel_dig_port
->port
));
4596 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4597 port_name(intel_dig_port
->port
),
4598 long_hpd
? "long" : "short");
4600 power_domain
= intel_display_port_power_domain(intel_encoder
);
4601 intel_display_power_get(dev_priv
, power_domain
);
4605 if (HAS_PCH_SPLIT(dev
)) {
4606 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4609 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4613 if (!intel_dp_get_dpcd(intel_dp
)) {
4617 intel_dp_probe_oui(intel_dp
);
4619 if (!intel_dp_probe_mst(intel_dp
))
4623 if (intel_dp
->is_mst
) {
4624 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4628 if (!intel_dp
->is_mst
) {
4630 * we'll check the link status via the normal hot plug path later -
4631 * but for short hpds we should check it now
4633 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4634 intel_dp_check_link_status(intel_dp
);
4635 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4643 /* if we were in MST mode, and device is not there get out of MST mode */
4644 if (intel_dp
->is_mst
) {
4645 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4646 intel_dp
->is_mst
= false;
4647 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4650 intel_display_power_put(dev_priv
, power_domain
);
4655 /* Return which DP Port should be selected for Transcoder DP control */
4657 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4659 struct drm_device
*dev
= crtc
->dev
;
4660 struct intel_encoder
*intel_encoder
;
4661 struct intel_dp
*intel_dp
;
4663 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4664 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4666 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4667 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4668 return intel_dp
->output_reg
;
4674 /* check the VBT to see whether the eDP is on DP-D port */
4675 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4678 union child_device_config
*p_child
;
4680 static const short port_mapping
[] = {
4681 [PORT_B
] = PORT_IDPB
,
4682 [PORT_C
] = PORT_IDPC
,
4683 [PORT_D
] = PORT_IDPD
,
4689 if (!dev_priv
->vbt
.child_dev_num
)
4692 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4693 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4695 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4696 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4697 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4704 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4706 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4708 intel_attach_force_audio_property(connector
);
4709 intel_attach_broadcast_rgb_property(connector
);
4710 intel_dp
->color_range_auto
= true;
4712 if (is_edp(intel_dp
)) {
4713 drm_mode_create_scaling_mode_property(connector
->dev
);
4714 drm_object_attach_property(
4716 connector
->dev
->mode_config
.scaling_mode_property
,
4717 DRM_MODE_SCALE_ASPECT
);
4718 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4722 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4724 intel_dp
->last_power_cycle
= jiffies
;
4725 intel_dp
->last_power_on
= jiffies
;
4726 intel_dp
->last_backlight_off
= jiffies
;
4730 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4731 struct intel_dp
*intel_dp
)
4733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4734 struct edp_power_seq cur
, vbt
, spec
,
4735 *final
= &intel_dp
->pps_delays
;
4736 u32 pp_on
, pp_off
, pp_div
, pp
;
4737 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4739 lockdep_assert_held(&dev_priv
->pps_mutex
);
4741 /* already initialized? */
4742 if (final
->t11_t12
!= 0)
4745 if (HAS_PCH_SPLIT(dev
)) {
4746 pp_ctrl_reg
= PCH_PP_CONTROL
;
4747 pp_on_reg
= PCH_PP_ON_DELAYS
;
4748 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4749 pp_div_reg
= PCH_PP_DIVISOR
;
4751 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4753 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4754 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4755 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4756 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4759 /* Workaround: Need to write PP_CONTROL with the unlock key as
4760 * the very first thing. */
4761 pp
= ironlake_get_pp_control(intel_dp
);
4762 I915_WRITE(pp_ctrl_reg
, pp
);
4764 pp_on
= I915_READ(pp_on_reg
);
4765 pp_off
= I915_READ(pp_off_reg
);
4766 pp_div
= I915_READ(pp_div_reg
);
4768 /* Pull timing values out of registers */
4769 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4770 PANEL_POWER_UP_DELAY_SHIFT
;
4772 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4773 PANEL_LIGHT_ON_DELAY_SHIFT
;
4775 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4776 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4778 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4779 PANEL_POWER_DOWN_DELAY_SHIFT
;
4781 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4782 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4784 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4785 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4787 vbt
= dev_priv
->vbt
.edp_pps
;
4789 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4790 * our hw here, which are all in 100usec. */
4791 spec
.t1_t3
= 210 * 10;
4792 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4793 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4794 spec
.t10
= 500 * 10;
4795 /* This one is special and actually in units of 100ms, but zero
4796 * based in the hw (so we need to add 100 ms). But the sw vbt
4797 * table multiplies it with 1000 to make it in units of 100usec,
4799 spec
.t11_t12
= (510 + 100) * 10;
4801 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4802 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4804 /* Use the max of the register settings and vbt. If both are
4805 * unset, fall back to the spec limits. */
4806 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4808 max(cur.field, vbt.field))
4809 assign_final(t1_t3
);
4813 assign_final(t11_t12
);
4816 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4817 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4818 intel_dp
->backlight_on_delay
= get_delay(t8
);
4819 intel_dp
->backlight_off_delay
= get_delay(t9
);
4820 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4821 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4824 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4825 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4826 intel_dp
->panel_power_cycle_delay
);
4828 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4829 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4833 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4834 struct intel_dp
*intel_dp
)
4836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4837 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4838 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4839 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4840 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4841 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4843 lockdep_assert_held(&dev_priv
->pps_mutex
);
4845 if (HAS_PCH_SPLIT(dev
)) {
4846 pp_on_reg
= PCH_PP_ON_DELAYS
;
4847 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4848 pp_div_reg
= PCH_PP_DIVISOR
;
4850 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4852 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4853 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4854 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4858 * And finally store the new values in the power sequencer. The
4859 * backlight delays are set to 1 because we do manual waits on them. For
4860 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4861 * we'll end up waiting for the backlight off delay twice: once when we
4862 * do the manual sleep, and once when we disable the panel and wait for
4863 * the PP_STATUS bit to become zero.
4865 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4866 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4867 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4868 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4869 /* Compute the divisor for the pp clock, simply match the Bspec
4871 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4872 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4873 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4875 /* Haswell doesn't have any port selection bits for the panel
4876 * power sequencer any more. */
4877 if (IS_VALLEYVIEW(dev
)) {
4878 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4879 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4881 port_sel
= PANEL_PORT_SELECT_DPA
;
4883 port_sel
= PANEL_PORT_SELECT_DPD
;
4888 I915_WRITE(pp_on_reg
, pp_on
);
4889 I915_WRITE(pp_off_reg
, pp_off
);
4890 I915_WRITE(pp_div_reg
, pp_div
);
4892 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4893 I915_READ(pp_on_reg
),
4894 I915_READ(pp_off_reg
),
4895 I915_READ(pp_div_reg
));
4899 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4901 * @refresh_rate: RR to be programmed
4903 * This function gets called when refresh rate (RR) has to be changed from
4904 * one frequency to another. Switches can be between high and low RR
4905 * supported by the panel or to any other RR based on media playback (in
4906 * this case, RR value needs to be passed from user space).
4908 * The caller of this function needs to take a lock on dev_priv->drrs.
4910 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4913 struct intel_encoder
*encoder
;
4914 struct intel_digital_port
*dig_port
= NULL
;
4915 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
4916 struct intel_crtc_state
*config
= NULL
;
4917 struct intel_crtc
*intel_crtc
= NULL
;
4919 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4921 if (refresh_rate
<= 0) {
4922 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4926 if (intel_dp
== NULL
) {
4927 DRM_DEBUG_KMS("DRRS not supported.\n");
4932 * FIXME: This needs proper synchronization with psr state for some
4933 * platforms that cannot have PSR and DRRS enabled at the same time.
4936 dig_port
= dp_to_dig_port(intel_dp
);
4937 encoder
= &dig_port
->base
;
4938 intel_crtc
= encoder
->new_crtc
;
4941 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4945 config
= intel_crtc
->config
;
4947 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
4948 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4952 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
4954 index
= DRRS_LOW_RR
;
4956 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
4958 "DRRS requested for previously set RR...ignoring\n");
4962 if (!intel_crtc
->active
) {
4963 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4967 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
4970 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4973 intel_dp_set_m_n(intel_crtc
, M2_N2
);
4977 DRM_ERROR("Unsupported refreshrate type\n");
4979 } else if (INTEL_INFO(dev
)->gen
> 6) {
4980 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
4981 val
= I915_READ(reg
);
4983 if (index
> DRRS_HIGH_RR
) {
4984 if (IS_VALLEYVIEW(dev
))
4985 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
4987 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4989 if (IS_VALLEYVIEW(dev
))
4990 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
4992 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4994 I915_WRITE(reg
, val
);
4997 dev_priv
->drrs
.refresh_rate_type
= index
;
4999 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5003 * intel_edp_drrs_enable - init drrs struct if supported
5004 * @intel_dp: DP struct
5006 * Initializes frontbuffer_bits and drrs.dp
5008 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5010 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5012 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5013 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5016 if (!intel_crtc
->config
->has_drrs
) {
5017 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5021 mutex_lock(&dev_priv
->drrs
.mutex
);
5022 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5023 DRM_ERROR("DRRS already enabled\n");
5027 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5029 dev_priv
->drrs
.dp
= intel_dp
;
5032 mutex_unlock(&dev_priv
->drrs
.mutex
);
5036 * intel_edp_drrs_disable - Disable DRRS
5037 * @intel_dp: DP struct
5040 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5042 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5044 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5045 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5046 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5048 if (!intel_crtc
->config
->has_drrs
)
5051 mutex_lock(&dev_priv
->drrs
.mutex
);
5052 if (!dev_priv
->drrs
.dp
) {
5053 mutex_unlock(&dev_priv
->drrs
.mutex
);
5057 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5058 intel_dp_set_drrs_state(dev_priv
->dev
,
5059 intel_dp
->attached_connector
->panel
.
5060 fixed_mode
->vrefresh
);
5062 dev_priv
->drrs
.dp
= NULL
;
5063 mutex_unlock(&dev_priv
->drrs
.mutex
);
5065 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5068 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5070 struct drm_i915_private
*dev_priv
=
5071 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5072 struct intel_dp
*intel_dp
;
5074 mutex_lock(&dev_priv
->drrs
.mutex
);
5076 intel_dp
= dev_priv
->drrs
.dp
;
5082 * The delayed work can race with an invalidate hence we need to
5086 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5089 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5090 intel_dp_set_drrs_state(dev_priv
->dev
,
5091 intel_dp
->attached_connector
->panel
.
5092 downclock_mode
->vrefresh
);
5096 mutex_unlock(&dev_priv
->drrs
.mutex
);
5100 * intel_edp_drrs_invalidate - Invalidate DRRS
5102 * @frontbuffer_bits: frontbuffer plane tracking bits
5104 * When there is a disturbance on screen (due to cursor movement/time
5105 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5108 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5110 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5111 unsigned frontbuffer_bits
)
5113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5114 struct drm_crtc
*crtc
;
5117 if (!dev_priv
->drrs
.dp
)
5120 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5122 mutex_lock(&dev_priv
->drrs
.mutex
);
5123 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5124 pipe
= to_intel_crtc(crtc
)->pipe
;
5126 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
) {
5127 intel_dp_set_drrs_state(dev_priv
->dev
,
5128 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5129 fixed_mode
->vrefresh
);
5132 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5134 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5135 mutex_unlock(&dev_priv
->drrs
.mutex
);
5139 * intel_edp_drrs_flush - Flush DRRS
5141 * @frontbuffer_bits: frontbuffer plane tracking bits
5143 * When there is no movement on screen, DRRS work can be scheduled.
5144 * This DRRS work is responsible for setting relevant registers after a
5145 * timeout of 1 second.
5147 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5149 void intel_edp_drrs_flush(struct drm_device
*dev
,
5150 unsigned frontbuffer_bits
)
5152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5153 struct drm_crtc
*crtc
;
5156 if (!dev_priv
->drrs
.dp
)
5159 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5161 mutex_lock(&dev_priv
->drrs
.mutex
);
5162 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5163 pipe
= to_intel_crtc(crtc
)->pipe
;
5164 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5166 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
&&
5167 !dev_priv
->drrs
.busy_frontbuffer_bits
)
5168 schedule_delayed_work(&dev_priv
->drrs
.work
,
5169 msecs_to_jiffies(1000));
5170 mutex_unlock(&dev_priv
->drrs
.mutex
);
5174 * DOC: Display Refresh Rate Switching (DRRS)
5176 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5177 * which enables swtching between low and high refresh rates,
5178 * dynamically, based on the usage scenario. This feature is applicable
5179 * for internal panels.
5181 * Indication that the panel supports DRRS is given by the panel EDID, which
5182 * would list multiple refresh rates for one resolution.
5184 * DRRS is of 2 types - static and seamless.
5185 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5186 * (may appear as a blink on screen) and is used in dock-undock scenario.
5187 * Seamless DRRS involves changing RR without any visual effect to the user
5188 * and can be used during normal system usage. This is done by programming
5189 * certain registers.
5191 * Support for static/seamless DRRS may be indicated in the VBT based on
5192 * inputs from the panel spec.
5194 * DRRS saves power by switching to low RR based on usage scenarios.
5197 * The implementation is based on frontbuffer tracking implementation.
5198 * When there is a disturbance on the screen triggered by user activity or a
5199 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5200 * When there is no movement on screen, after a timeout of 1 second, a switch
5201 * to low RR is made.
5202 * For integration with frontbuffer tracking code,
5203 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5205 * DRRS can be further extended to support other internal panels and also
5206 * the scenario of video playback wherein RR is set based on the rate
5207 * requested by userspace.
5211 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5212 * @intel_connector: eDP connector
5213 * @fixed_mode: preferred mode of panel
5215 * This function is called only once at driver load to initialize basic
5219 * Downclock mode if panel supports it, else return NULL.
5220 * DRRS support is determined by the presence of downclock mode (apart
5221 * from VBT setting).
5223 static struct drm_display_mode
*
5224 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5225 struct drm_display_mode
*fixed_mode
)
5227 struct drm_connector
*connector
= &intel_connector
->base
;
5228 struct drm_device
*dev
= connector
->dev
;
5229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5230 struct drm_display_mode
*downclock_mode
= NULL
;
5232 if (INTEL_INFO(dev
)->gen
<= 6) {
5233 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5237 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5238 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5242 downclock_mode
= intel_find_panel_downclock
5243 (dev
, fixed_mode
, connector
);
5245 if (!downclock_mode
) {
5246 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5250 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5252 mutex_init(&dev_priv
->drrs
.mutex
);
5254 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5256 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5257 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5258 return downclock_mode
;
5261 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5262 struct intel_connector
*intel_connector
)
5264 struct drm_connector
*connector
= &intel_connector
->base
;
5265 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5266 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5267 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5269 struct drm_display_mode
*fixed_mode
= NULL
;
5270 struct drm_display_mode
*downclock_mode
= NULL
;
5272 struct drm_display_mode
*scan
;
5274 enum pipe pipe
= INVALID_PIPE
;
5276 dev_priv
->drrs
.type
= DRRS_NOT_SUPPORTED
;
5278 if (!is_edp(intel_dp
))
5282 intel_edp_panel_vdd_sanitize(intel_dp
);
5283 pps_unlock(intel_dp
);
5285 /* Cache DPCD and EDID for edp. */
5286 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5289 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5290 dev_priv
->no_aux_handshake
=
5291 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5292 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5294 /* if this fails, presume the device is a ghost */
5295 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5299 /* We now know it's not a ghost, init power sequence regs. */
5301 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5302 pps_unlock(intel_dp
);
5304 mutex_lock(&dev
->mode_config
.mutex
);
5305 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5307 if (drm_add_edid_modes(connector
, edid
)) {
5308 drm_mode_connector_update_edid_property(connector
,
5310 drm_edid_to_eld(connector
, edid
);
5313 edid
= ERR_PTR(-EINVAL
);
5316 edid
= ERR_PTR(-ENOENT
);
5318 intel_connector
->edid
= edid
;
5320 /* prefer fixed mode from EDID if available */
5321 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5322 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5323 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5324 downclock_mode
= intel_dp_drrs_init(
5325 intel_connector
, fixed_mode
);
5330 /* fallback to VBT if available for eDP */
5331 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5332 fixed_mode
= drm_mode_duplicate(dev
,
5333 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5335 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5337 mutex_unlock(&dev
->mode_config
.mutex
);
5339 if (IS_VALLEYVIEW(dev
)) {
5340 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5341 register_reboot_notifier(&intel_dp
->edp_notifier
);
5344 * Figure out the current pipe for the initial backlight setup.
5345 * If the current pipe isn't valid, try the PPS pipe, and if that
5346 * fails just assume pipe A.
5348 if (IS_CHERRYVIEW(dev
))
5349 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5351 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5353 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5354 pipe
= intel_dp
->pps_pipe
;
5356 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5359 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5363 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5364 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5365 intel_panel_setup_backlight(connector
, pipe
);
5371 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5372 struct intel_connector
*intel_connector
)
5374 struct drm_connector
*connector
= &intel_connector
->base
;
5375 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5376 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5377 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5379 enum port port
= intel_dig_port
->port
;
5382 intel_dp
->pps_pipe
= INVALID_PIPE
;
5384 /* intel_dp vfuncs */
5385 if (INTEL_INFO(dev
)->gen
>= 9)
5386 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5387 else if (IS_VALLEYVIEW(dev
))
5388 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5389 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5390 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5391 else if (HAS_PCH_SPLIT(dev
))
5392 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5394 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5396 if (INTEL_INFO(dev
)->gen
>= 9)
5397 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5399 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5401 /* Preserve the current hw state. */
5402 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5403 intel_dp
->attached_connector
= intel_connector
;
5405 if (intel_dp_is_edp(dev
, port
))
5406 type
= DRM_MODE_CONNECTOR_eDP
;
5408 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5411 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5412 * for DP the encoder type can be set by the caller to
5413 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5415 if (type
== DRM_MODE_CONNECTOR_eDP
)
5416 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5418 /* eDP only on port B and/or C on vlv/chv */
5419 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5420 port
!= PORT_B
&& port
!= PORT_C
))
5423 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5424 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5427 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5428 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5430 connector
->interlace_allowed
= true;
5431 connector
->doublescan_allowed
= 0;
5433 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5434 edp_panel_vdd_work
);
5436 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5437 drm_connector_register(connector
);
5440 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5442 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5443 intel_connector
->unregister
= intel_dp_connector_unregister
;
5445 /* Set up the hotplug pin. */
5448 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5451 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5454 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5457 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5463 if (is_edp(intel_dp
)) {
5465 intel_dp_init_panel_power_timestamps(intel_dp
);
5466 if (IS_VALLEYVIEW(dev
))
5467 vlv_initial_power_sequencer_setup(intel_dp
);
5469 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5470 pps_unlock(intel_dp
);
5473 intel_dp_aux_init(intel_dp
, intel_connector
);
5475 /* init MST on ports that can support it */
5476 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
5477 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5478 intel_dp_mst_encoder_init(intel_dig_port
,
5479 intel_connector
->base
.base
.id
);
5483 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5484 drm_dp_aux_unregister(&intel_dp
->aux
);
5485 if (is_edp(intel_dp
)) {
5486 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5488 * vdd might still be enabled do to the delayed vdd off.
5489 * Make sure vdd is actually turned off here.
5492 edp_panel_vdd_off_sync(intel_dp
);
5493 pps_unlock(intel_dp
);
5495 drm_connector_unregister(connector
);
5496 drm_connector_cleanup(connector
);
5500 intel_dp_add_properties(intel_dp
, connector
);
5502 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5503 * 0xd. Failure to do so will result in spurious interrupts being
5504 * generated on the port when a cable is not attached.
5506 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5507 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5508 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5515 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5518 struct intel_digital_port
*intel_dig_port
;
5519 struct intel_encoder
*intel_encoder
;
5520 struct drm_encoder
*encoder
;
5521 struct intel_connector
*intel_connector
;
5523 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5524 if (!intel_dig_port
)
5527 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5528 if (!intel_connector
) {
5529 kfree(intel_dig_port
);
5533 intel_encoder
= &intel_dig_port
->base
;
5534 encoder
= &intel_encoder
->base
;
5536 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5537 DRM_MODE_ENCODER_TMDS
);
5539 intel_encoder
->compute_config
= intel_dp_compute_config
;
5540 intel_encoder
->disable
= intel_disable_dp
;
5541 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5542 intel_encoder
->get_config
= intel_dp_get_config
;
5543 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5544 if (IS_CHERRYVIEW(dev
)) {
5545 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5546 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5547 intel_encoder
->enable
= vlv_enable_dp
;
5548 intel_encoder
->post_disable
= chv_post_disable_dp
;
5549 } else if (IS_VALLEYVIEW(dev
)) {
5550 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5551 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5552 intel_encoder
->enable
= vlv_enable_dp
;
5553 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5555 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5556 intel_encoder
->enable
= g4x_enable_dp
;
5557 if (INTEL_INFO(dev
)->gen
>= 5)
5558 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5561 intel_dig_port
->port
= port
;
5562 intel_dig_port
->dp
.output_reg
= output_reg
;
5564 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5565 if (IS_CHERRYVIEW(dev
)) {
5567 intel_encoder
->crtc_mask
= 1 << 2;
5569 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5571 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5573 intel_encoder
->cloneable
= 0;
5574 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5576 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5577 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5579 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5580 drm_encoder_cleanup(encoder
);
5581 kfree(intel_dig_port
);
5582 kfree(intel_connector
);
5586 void intel_dp_mst_suspend(struct drm_device
*dev
)
5588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5592 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5593 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5594 if (!intel_dig_port
)
5597 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5598 if (!intel_dig_port
->dp
.can_mst
)
5600 if (intel_dig_port
->dp
.is_mst
)
5601 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5606 void intel_dp_mst_resume(struct drm_device
*dev
)
5608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5611 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5612 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5613 if (!intel_dig_port
)
5615 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5618 if (!intel_dig_port
->dp
.can_mst
)
5621 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5623 intel_dp_check_mst_status(&intel_dig_port
->dp
);