2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
294 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
298 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum port port
= intel_dig_port
->port
;
303 /* modeset should have pipe */
305 return to_intel_crtc(crtc
)->pipe
;
307 /* init time, try to find a pipe with this port selected */
308 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
309 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
310 PANEL_PORT_SELECT_MASK
;
311 if (port_sel
== PANEL_PORT_SELECT_VLV(port
))
319 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
323 if (HAS_PCH_SPLIT(dev
))
324 return PCH_PP_CONTROL
;
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
329 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
331 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
333 if (HAS_PCH_SPLIT(dev
))
334 return PCH_PP_STATUS
;
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
339 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
344 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
346 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
349 u32 pp_ctrl_reg
, pp_div_reg
;
350 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
352 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
355 if (IS_VALLEYVIEW(dev
)) {
356 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
357 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
358 pp_div
= I915_READ(pp_div_reg
);
359 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
363 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
364 msleep(intel_dp
->panel_power_cycle_delay
);
370 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
372 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
375 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
378 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
380 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
382 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
383 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
384 enum intel_display_power_domain power_domain
;
386 power_domain
= intel_display_port_power_domain(intel_encoder
);
387 return intel_display_power_enabled(dev_priv
, power_domain
) &&
388 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
392 intel_dp_check_edp(struct intel_dp
*intel_dp
)
394 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
397 if (!is_edp(intel_dp
))
400 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
403 I915_READ(_pp_stat_reg(intel_dp
)),
404 I915_READ(_pp_ctrl_reg(intel_dp
)));
409 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
411 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
412 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
414 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
418 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
420 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
421 msecs_to_jiffies_timeout(10));
423 done
= wait_for_atomic(C
, 10) == 0;
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
432 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
434 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
435 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
441 return index
? 0 : intel_hrawclk(dev
) / 2;
444 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
446 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
447 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
452 if (intel_dig_port
->port
== PORT_A
) {
453 if (IS_GEN6(dev
) || IS_GEN7(dev
))
454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
456 return 225; /* eDP input clock at 450Mhz */
458 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
462 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
464 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
465 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
468 if (intel_dig_port
->port
== PORT_A
) {
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
472 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
473 /* Workaround for non-ULT HSW */
480 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
484 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
486 return index
? 0 : 100;
489 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
492 uint32_t aux_clock_divider
)
494 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
495 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
496 uint32_t precharge
, timeout
;
503 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
504 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
506 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
508 return DP_AUX_CH_CTL_SEND_BUSY
|
510 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
511 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
513 DP_AUX_CH_CTL_RECEIVE_ERROR
|
514 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
515 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
516 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
520 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
521 uint8_t *send
, int send_bytes
,
522 uint8_t *recv
, int recv_size
)
524 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
525 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
527 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
528 uint32_t ch_data
= ch_ctl
+ 4;
529 uint32_t aux_clock_divider
;
530 int i
, ret
, recv_bytes
;
533 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
537 * We will be called with VDD already enabled for dpcd/edid/oui reads.
538 * In such cases we want to leave VDD enabled and it's up to upper layers
539 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
542 vdd
= edp_panel_vdd_on(intel_dp
);
544 /* dp aux is extremely sensitive to irq latency, hence request the
545 * lowest possible wakeup latency and so prevent the cpu from going into
548 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
550 intel_dp_check_edp(intel_dp
);
552 intel_aux_display_runtime_get(dev_priv
);
554 /* Try to wait for any previous AUX channel activity */
555 for (try = 0; try < 3; try++) {
556 status
= I915_READ_NOTRACE(ch_ctl
);
557 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
563 WARN(1, "dp_aux_ch not started status 0x%08x\n",
569 /* Only 5 data registers! */
570 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
575 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
576 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
581 /* Must try at least 3 times according to DP spec */
582 for (try = 0; try < 5; try++) {
583 /* Load the send data into the aux channel data registers */
584 for (i
= 0; i
< send_bytes
; i
+= 4)
585 I915_WRITE(ch_data
+ i
,
586 pack_aux(send
+ i
, send_bytes
- i
));
588 /* Send the command and wait for it to complete */
589 I915_WRITE(ch_ctl
, send_ctl
);
591 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
593 /* Clear done status and any errors */
597 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
598 DP_AUX_CH_CTL_RECEIVE_ERROR
);
600 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
601 DP_AUX_CH_CTL_RECEIVE_ERROR
))
603 if (status
& DP_AUX_CH_CTL_DONE
)
606 if (status
& DP_AUX_CH_CTL_DONE
)
610 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
611 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
616 /* Check for timeout or receive error.
617 * Timeouts occur when the sink is not connected
619 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
620 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
625 /* Timeouts occur when the device isn't connected, so they're
626 * "normal" -- don't fill the kernel log with these */
627 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
628 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
633 /* Unload any bytes sent back from the other side */
634 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
635 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
636 if (recv_bytes
> recv_size
)
637 recv_bytes
= recv_size
;
639 for (i
= 0; i
< recv_bytes
; i
+= 4)
640 unpack_aux(I915_READ(ch_data
+ i
),
641 recv
+ i
, recv_bytes
- i
);
645 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
646 intel_aux_display_runtime_put(dev_priv
);
649 edp_panel_vdd_off(intel_dp
, false);
654 #define BARE_ADDRESS_SIZE 3
655 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
657 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
659 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
660 uint8_t txbuf
[20], rxbuf
[20];
661 size_t txsize
, rxsize
;
664 txbuf
[0] = msg
->request
<< 4;
665 txbuf
[1] = msg
->address
>> 8;
666 txbuf
[2] = msg
->address
& 0xff;
667 txbuf
[3] = msg
->size
- 1;
669 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
670 case DP_AUX_NATIVE_WRITE
:
671 case DP_AUX_I2C_WRITE
:
672 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
675 if (WARN_ON(txsize
> 20))
678 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
680 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
682 msg
->reply
= rxbuf
[0] >> 4;
684 /* Return payload size. */
689 case DP_AUX_NATIVE_READ
:
690 case DP_AUX_I2C_READ
:
691 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
692 rxsize
= msg
->size
+ 1;
694 if (WARN_ON(rxsize
> 20))
697 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
699 msg
->reply
= rxbuf
[0] >> 4;
701 * Assume happy day, and copy the data. The caller is
702 * expected to check msg->reply before touching it.
704 * Return payload size.
707 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
720 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
722 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
723 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
724 enum port port
= intel_dig_port
->port
;
725 const char *name
= NULL
;
730 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
734 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
738 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
742 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
750 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
752 intel_dp
->aux
.name
= name
;
753 intel_dp
->aux
.dev
= dev
->dev
;
754 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
756 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
757 connector
->base
.kdev
->kobj
.name
);
759 ret
= drm_dp_aux_register(&intel_dp
->aux
);
761 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
766 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
767 &intel_dp
->aux
.ddc
.dev
.kobj
,
768 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
770 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
771 drm_dp_aux_unregister(&intel_dp
->aux
);
776 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
778 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
780 if (!intel_connector
->mst_port
)
781 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
782 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
783 intel_connector_unregister(intel_connector
);
787 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
790 case DP_LINK_BW_1_62
:
791 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
794 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
797 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
803 intel_dp_set_clock(struct intel_encoder
*encoder
,
804 struct intel_crtc_config
*pipe_config
, int link_bw
)
806 struct drm_device
*dev
= encoder
->base
.dev
;
807 const struct dp_link_dpll
*divisor
= NULL
;
812 count
= ARRAY_SIZE(gen4_dpll
);
813 } else if (HAS_PCH_SPLIT(dev
)) {
815 count
= ARRAY_SIZE(pch_dpll
);
816 } else if (IS_CHERRYVIEW(dev
)) {
818 count
= ARRAY_SIZE(chv_dpll
);
819 } else if (IS_VALLEYVIEW(dev
)) {
821 count
= ARRAY_SIZE(vlv_dpll
);
824 if (divisor
&& count
) {
825 for (i
= 0; i
< count
; i
++) {
826 if (link_bw
== divisor
[i
].link_bw
) {
827 pipe_config
->dpll
= divisor
[i
].dpll
;
828 pipe_config
->clock_set
= true;
836 intel_dp_compute_config(struct intel_encoder
*encoder
,
837 struct intel_crtc_config
*pipe_config
)
839 struct drm_device
*dev
= encoder
->base
.dev
;
840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
841 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
842 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
843 enum port port
= dp_to_dig_port(intel_dp
)->port
;
844 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
845 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
846 int lane_count
, clock
;
847 int min_lane_count
= 1;
848 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
849 /* Conveniently, the link BW constants become indices with a shift...*/
851 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
853 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
854 int link_avail
, link_clock
;
856 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
857 pipe_config
->has_pch_encoder
= true;
859 pipe_config
->has_dp_encoder
= true;
860 pipe_config
->has_drrs
= false;
861 pipe_config
->has_audio
= intel_dp
->has_audio
;
863 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
864 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
866 if (!HAS_PCH_SPLIT(dev
))
867 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
868 intel_connector
->panel
.fitting_mode
);
870 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
871 intel_connector
->panel
.fitting_mode
);
874 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
877 DRM_DEBUG_KMS("DP link computation with max lane count %i "
878 "max bw %02x pixel clock %iKHz\n",
879 max_lane_count
, bws
[max_clock
],
880 adjusted_mode
->crtc_clock
);
882 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
884 bpp
= pipe_config
->pipe_bpp
;
885 if (is_edp(intel_dp
)) {
886 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
887 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
888 dev_priv
->vbt
.edp_bpp
);
889 bpp
= dev_priv
->vbt
.edp_bpp
;
892 if (IS_BROADWELL(dev
)) {
893 /* Yes, it's an ugly hack. */
894 min_lane_count
= max_lane_count
;
895 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
897 } else if (dev_priv
->vbt
.edp_lanes
) {
898 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
900 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
904 if (dev_priv
->vbt
.edp_rate
) {
905 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
906 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
911 for (; bpp
>= 6*3; bpp
-= 2*3) {
912 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
915 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
916 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
917 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
918 link_avail
= intel_dp_max_data_rate(link_clock
,
921 if (mode_rate
<= link_avail
) {
931 if (intel_dp
->color_range_auto
) {
934 * CEA-861-E - 5.1 Default Encoding Parameters
935 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
937 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
938 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
940 intel_dp
->color_range
= 0;
943 if (intel_dp
->color_range
)
944 pipe_config
->limited_color_range
= true;
946 intel_dp
->link_bw
= bws
[clock
];
947 intel_dp
->lane_count
= lane_count
;
948 pipe_config
->pipe_bpp
= bpp
;
949 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
951 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
952 intel_dp
->link_bw
, intel_dp
->lane_count
,
953 pipe_config
->port_clock
, bpp
);
954 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
955 mode_rate
, link_avail
);
957 intel_link_compute_m_n(bpp
, lane_count
,
958 adjusted_mode
->crtc_clock
,
959 pipe_config
->port_clock
,
960 &pipe_config
->dp_m_n
);
962 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
963 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
964 pipe_config
->has_drrs
= true;
965 intel_link_compute_m_n(bpp
, lane_count
,
966 intel_connector
->panel
.downclock_mode
->clock
,
967 pipe_config
->port_clock
,
968 &pipe_config
->dp_m2_n2
);
971 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
972 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
974 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
979 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
981 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
982 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
983 struct drm_device
*dev
= crtc
->base
.dev
;
984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
988 dpa_ctl
= I915_READ(DP_A
);
989 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
991 if (crtc
->config
.port_clock
== 162000) {
992 /* For a long time we've carried around a ILK-DevA w/a for the
993 * 160MHz clock. If we're really unlucky, it's still required.
995 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
996 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
997 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
999 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1000 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1003 I915_WRITE(DP_A
, dpa_ctl
);
1009 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1011 struct drm_device
*dev
= encoder
->base
.dev
;
1012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1013 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1014 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1015 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1016 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1019 * There are four kinds of DP registers:
1026 * IBX PCH and CPU are the same for almost everything,
1027 * except that the CPU DP PLL is configured in this
1030 * CPT PCH is quite different, having many bits moved
1031 * to the TRANS_DP_CTL register instead. That
1032 * configuration happens (oddly) in ironlake_pch_enable
1035 /* Preserve the BIOS-computed detected bit. This is
1036 * supposed to be read-only.
1038 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1040 /* Handle DP bits in common between all three register formats */
1041 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1042 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1044 if (crtc
->config
.has_audio
) {
1045 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1046 pipe_name(crtc
->pipe
));
1047 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1048 intel_write_eld(&encoder
->base
, adjusted_mode
);
1051 /* Split out the IBX/CPU vs CPT settings */
1053 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1054 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1055 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1056 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1057 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1058 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1060 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1061 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1063 intel_dp
->DP
|= crtc
->pipe
<< 29;
1064 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1065 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1066 intel_dp
->DP
|= intel_dp
->color_range
;
1068 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1069 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1070 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1071 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1072 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1074 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1075 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1077 if (!IS_CHERRYVIEW(dev
)) {
1078 if (crtc
->pipe
== 1)
1079 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1081 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1084 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1088 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1089 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1091 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1092 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1094 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1095 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1097 static void wait_panel_status(struct intel_dp
*intel_dp
,
1101 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1103 u32 pp_stat_reg
, pp_ctrl_reg
;
1105 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1106 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1108 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1110 I915_READ(pp_stat_reg
),
1111 I915_READ(pp_ctrl_reg
));
1113 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1114 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1115 I915_READ(pp_stat_reg
),
1116 I915_READ(pp_ctrl_reg
));
1119 DRM_DEBUG_KMS("Wait complete\n");
1122 static void wait_panel_on(struct intel_dp
*intel_dp
)
1124 DRM_DEBUG_KMS("Wait for panel power on\n");
1125 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1128 static void wait_panel_off(struct intel_dp
*intel_dp
)
1130 DRM_DEBUG_KMS("Wait for panel power off time\n");
1131 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1134 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1136 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1138 /* When we disable the VDD override bit last we have to do the manual
1140 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1141 intel_dp
->panel_power_cycle_delay
);
1143 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1146 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1148 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1149 intel_dp
->backlight_on_delay
);
1152 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1154 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1155 intel_dp
->backlight_off_delay
);
1158 /* Read the current pp_control value, unlocking the register if it
1162 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1164 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1168 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1169 control
&= ~PANEL_UNLOCK_MASK
;
1170 control
|= PANEL_UNLOCK_REGS
;
1174 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1176 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1177 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1178 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 enum intel_display_power_domain power_domain
;
1182 u32 pp_stat_reg
, pp_ctrl_reg
;
1183 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1185 if (!is_edp(intel_dp
))
1188 intel_dp
->want_panel_vdd
= true;
1190 if (edp_have_panel_vdd(intel_dp
))
1191 return need_to_disable
;
1193 power_domain
= intel_display_port_power_domain(intel_encoder
);
1194 intel_display_power_get(dev_priv
, power_domain
);
1196 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1198 if (!edp_have_panel_power(intel_dp
))
1199 wait_panel_power_cycle(intel_dp
);
1201 pp
= ironlake_get_pp_control(intel_dp
);
1202 pp
|= EDP_FORCE_VDD
;
1204 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1205 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1207 I915_WRITE(pp_ctrl_reg
, pp
);
1208 POSTING_READ(pp_ctrl_reg
);
1209 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1210 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1212 * If the panel wasn't on, delay before accessing aux channel
1214 if (!edp_have_panel_power(intel_dp
)) {
1215 DRM_DEBUG_KMS("eDP was not running\n");
1216 msleep(intel_dp
->panel_power_up_delay
);
1219 return need_to_disable
;
1222 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1224 if (is_edp(intel_dp
)) {
1225 bool vdd
= edp_panel_vdd_on(intel_dp
);
1227 WARN(!vdd
, "eDP VDD already requested on\n");
1231 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1233 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1236 u32 pp_stat_reg
, pp_ctrl_reg
;
1238 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1240 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1241 struct intel_digital_port
*intel_dig_port
=
1242 dp_to_dig_port(intel_dp
);
1243 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1244 enum intel_display_power_domain power_domain
;
1246 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1248 pp
= ironlake_get_pp_control(intel_dp
);
1249 pp
&= ~EDP_FORCE_VDD
;
1251 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1252 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1254 I915_WRITE(pp_ctrl_reg
, pp
);
1255 POSTING_READ(pp_ctrl_reg
);
1257 /* Make sure sequencer is idle before allowing subsequent activity */
1258 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1259 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1261 if ((pp
& POWER_TARGET_ON
) == 0)
1262 intel_dp
->last_power_cycle
= jiffies
;
1264 power_domain
= intel_display_port_power_domain(intel_encoder
);
1265 intel_display_power_put(dev_priv
, power_domain
);
1269 static void edp_panel_vdd_work(struct work_struct
*__work
)
1271 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1272 struct intel_dp
, panel_vdd_work
);
1273 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1275 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
1276 edp_panel_vdd_off_sync(intel_dp
);
1277 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
1280 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1282 unsigned long delay
;
1285 * Queue the timer to fire a long time from now (relative to the power
1286 * down delay) to keep the panel power up across a sequence of
1289 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1290 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1293 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1295 if (!is_edp(intel_dp
))
1298 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1300 intel_dp
->want_panel_vdd
= false;
1303 edp_panel_vdd_off_sync(intel_dp
);
1305 edp_panel_vdd_schedule_off(intel_dp
);
1308 static void intel_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1310 edp_panel_vdd_off(intel_dp
, sync
);
1313 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1315 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1320 if (!is_edp(intel_dp
))
1323 DRM_DEBUG_KMS("Turn eDP power on\n");
1325 if (edp_have_panel_power(intel_dp
)) {
1326 DRM_DEBUG_KMS("eDP power already on\n");
1330 wait_panel_power_cycle(intel_dp
);
1332 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1333 pp
= ironlake_get_pp_control(intel_dp
);
1335 /* ILK workaround: disable reset around power sequence */
1336 pp
&= ~PANEL_POWER_RESET
;
1337 I915_WRITE(pp_ctrl_reg
, pp
);
1338 POSTING_READ(pp_ctrl_reg
);
1341 pp
|= POWER_TARGET_ON
;
1343 pp
|= PANEL_POWER_RESET
;
1345 I915_WRITE(pp_ctrl_reg
, pp
);
1346 POSTING_READ(pp_ctrl_reg
);
1348 wait_panel_on(intel_dp
);
1349 intel_dp
->last_power_on
= jiffies
;
1352 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1353 I915_WRITE(pp_ctrl_reg
, pp
);
1354 POSTING_READ(pp_ctrl_reg
);
1358 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1360 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1361 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1362 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1364 enum intel_display_power_domain power_domain
;
1368 if (!is_edp(intel_dp
))
1371 DRM_DEBUG_KMS("Turn eDP power off\n");
1373 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1375 pp
= ironlake_get_pp_control(intel_dp
);
1376 /* We need to switch off panel power _and_ force vdd, for otherwise some
1377 * panels get very unhappy and cease to work. */
1378 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1381 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1383 intel_dp
->want_panel_vdd
= false;
1385 I915_WRITE(pp_ctrl_reg
, pp
);
1386 POSTING_READ(pp_ctrl_reg
);
1388 intel_dp
->last_power_cycle
= jiffies
;
1389 wait_panel_off(intel_dp
);
1391 /* We got a reference when we enabled the VDD. */
1392 power_domain
= intel_display_port_power_domain(intel_encoder
);
1393 intel_display_power_put(dev_priv
, power_domain
);
1396 /* Enable backlight in the panel power control. */
1397 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1399 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1400 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1406 * If we enable the backlight right away following a panel power
1407 * on, we may see slight flicker as the panel syncs with the eDP
1408 * link. So delay a bit to make sure the image is solid before
1409 * allowing it to appear.
1411 wait_backlight_on(intel_dp
);
1412 pp
= ironlake_get_pp_control(intel_dp
);
1413 pp
|= EDP_BLC_ENABLE
;
1415 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1417 I915_WRITE(pp_ctrl_reg
, pp
);
1418 POSTING_READ(pp_ctrl_reg
);
1421 /* Enable backlight PWM and backlight PP control. */
1422 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1424 if (!is_edp(intel_dp
))
1427 DRM_DEBUG_KMS("\n");
1429 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1430 _intel_edp_backlight_on(intel_dp
);
1433 /* Disable backlight in the panel power control. */
1434 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1436 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1441 pp
= ironlake_get_pp_control(intel_dp
);
1442 pp
&= ~EDP_BLC_ENABLE
;
1444 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1446 I915_WRITE(pp_ctrl_reg
, pp
);
1447 POSTING_READ(pp_ctrl_reg
);
1448 intel_dp
->last_backlight_off
= jiffies
;
1450 edp_wait_backlight_off(intel_dp
);
1453 /* Disable backlight PP control and backlight PWM. */
1454 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1456 if (!is_edp(intel_dp
))
1459 DRM_DEBUG_KMS("\n");
1461 _intel_edp_backlight_off(intel_dp
);
1462 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1466 * Hook for controlling the panel power control backlight through the bl_power
1467 * sysfs attribute. Take care to handle multiple calls.
1469 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1472 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1473 bool is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1475 if (is_enabled
== enable
)
1478 DRM_DEBUG_KMS("\n");
1481 _intel_edp_backlight_on(intel_dp
);
1483 _intel_edp_backlight_off(intel_dp
);
1486 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1488 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1489 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1490 struct drm_device
*dev
= crtc
->dev
;
1491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1494 assert_pipe_disabled(dev_priv
,
1495 to_intel_crtc(crtc
)->pipe
);
1497 DRM_DEBUG_KMS("\n");
1498 dpa_ctl
= I915_READ(DP_A
);
1499 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1500 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1502 /* We don't adjust intel_dp->DP while tearing down the link, to
1503 * facilitate link retraining (e.g. after hotplug). Hence clear all
1504 * enable bits here to ensure that we don't enable too much. */
1505 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1506 intel_dp
->DP
|= DP_PLL_ENABLE
;
1507 I915_WRITE(DP_A
, intel_dp
->DP
);
1512 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1514 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1515 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1516 struct drm_device
*dev
= crtc
->dev
;
1517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1520 assert_pipe_disabled(dev_priv
,
1521 to_intel_crtc(crtc
)->pipe
);
1523 dpa_ctl
= I915_READ(DP_A
);
1524 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1525 "dp pll off, should be on\n");
1526 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1528 /* We can't rely on the value tracked for the DP register in
1529 * intel_dp->DP because link_down must not change that (otherwise link
1530 * re-training will fail. */
1531 dpa_ctl
&= ~DP_PLL_ENABLE
;
1532 I915_WRITE(DP_A
, dpa_ctl
);
1537 /* If the sink supports it, try to set the power state appropriately */
1538 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1542 /* Should have a valid DPCD by this point */
1543 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1546 if (mode
!= DRM_MODE_DPMS_ON
) {
1547 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1550 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1553 * When turning on, we need to retry for 1ms to give the sink
1556 for (i
= 0; i
< 3; i
++) {
1557 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1566 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1569 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1570 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1571 struct drm_device
*dev
= encoder
->base
.dev
;
1572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1573 enum intel_display_power_domain power_domain
;
1576 power_domain
= intel_display_port_power_domain(encoder
);
1577 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1580 tmp
= I915_READ(intel_dp
->output_reg
);
1582 if (!(tmp
& DP_PORT_EN
))
1585 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1586 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1587 } else if (IS_CHERRYVIEW(dev
)) {
1588 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1589 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1590 *pipe
= PORT_TO_PIPE(tmp
);
1596 switch (intel_dp
->output_reg
) {
1598 trans_sel
= TRANS_DP_PORT_SEL_B
;
1601 trans_sel
= TRANS_DP_PORT_SEL_C
;
1604 trans_sel
= TRANS_DP_PORT_SEL_D
;
1610 for_each_pipe(dev_priv
, i
) {
1611 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1612 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1618 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1619 intel_dp
->output_reg
);
1625 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1626 struct intel_crtc_config
*pipe_config
)
1628 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1630 struct drm_device
*dev
= encoder
->base
.dev
;
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1633 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1636 tmp
= I915_READ(intel_dp
->output_reg
);
1637 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1638 pipe_config
->has_audio
= true;
1640 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1641 if (tmp
& DP_SYNC_HS_HIGH
)
1642 flags
|= DRM_MODE_FLAG_PHSYNC
;
1644 flags
|= DRM_MODE_FLAG_NHSYNC
;
1646 if (tmp
& DP_SYNC_VS_HIGH
)
1647 flags
|= DRM_MODE_FLAG_PVSYNC
;
1649 flags
|= DRM_MODE_FLAG_NVSYNC
;
1651 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1652 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1653 flags
|= DRM_MODE_FLAG_PHSYNC
;
1655 flags
|= DRM_MODE_FLAG_NHSYNC
;
1657 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1658 flags
|= DRM_MODE_FLAG_PVSYNC
;
1660 flags
|= DRM_MODE_FLAG_NVSYNC
;
1663 pipe_config
->adjusted_mode
.flags
|= flags
;
1665 pipe_config
->has_dp_encoder
= true;
1667 intel_dp_get_m_n(crtc
, pipe_config
);
1669 if (port
== PORT_A
) {
1670 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1671 pipe_config
->port_clock
= 162000;
1673 pipe_config
->port_clock
= 270000;
1676 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1677 &pipe_config
->dp_m_n
);
1679 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1680 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1682 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1684 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1685 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1687 * This is a big fat ugly hack.
1689 * Some machines in UEFI boot mode provide us a VBT that has 18
1690 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1691 * unknown we fail to light up. Yet the same BIOS boots up with
1692 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1693 * max, not what it tells us to use.
1695 * Note: This will still be broken if the eDP panel is not lit
1696 * up by the BIOS, and thus we can't get the mode at module
1699 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1700 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1701 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1705 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1707 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1710 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1717 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1720 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1721 struct edp_vsc_psr
*vsc_psr
)
1723 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1724 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1726 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1727 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1728 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1729 uint32_t *data
= (uint32_t *) vsc_psr
;
1732 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1733 the video DIP being updated before program video DIP data buffer
1734 registers for DIP being updated. */
1735 I915_WRITE(ctl_reg
, 0);
1736 POSTING_READ(ctl_reg
);
1738 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1739 if (i
< sizeof(struct edp_vsc_psr
))
1740 I915_WRITE(data_reg
+ i
, *data
++);
1742 I915_WRITE(data_reg
+ i
, 0);
1745 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1746 POSTING_READ(ctl_reg
);
1749 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1751 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1753 struct edp_vsc_psr psr_vsc
;
1755 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1756 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1757 psr_vsc
.sdp_header
.HB0
= 0;
1758 psr_vsc
.sdp_header
.HB1
= 0x7;
1759 psr_vsc
.sdp_header
.HB2
= 0x2;
1760 psr_vsc
.sdp_header
.HB3
= 0x8;
1761 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1763 /* Avoid continuous PSR exit by masking memup and hpd */
1764 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1765 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1768 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1770 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1771 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1773 uint32_t aux_clock_divider
;
1774 int precharge
= 0x3;
1775 int msg_size
= 5; /* Header(4) + Message(1) */
1776 bool only_standby
= false;
1778 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1780 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1781 only_standby
= true;
1783 /* Enable PSR in sink */
1784 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
1785 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1786 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1788 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1789 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1791 /* Setup AUX registers */
1792 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1793 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1794 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1795 DP_AUX_CH_CTL_TIME_OUT_400us
|
1796 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1797 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1798 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1801 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1803 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1804 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1806 uint32_t max_sleep_time
= 0x1f;
1807 uint32_t idle_frames
= 1;
1809 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1810 bool only_standby
= false;
1812 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1813 only_standby
= true;
1815 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
1816 val
|= EDP_PSR_LINK_STANDBY
;
1817 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1818 val
|= EDP_PSR_TP1_TIME_0us
;
1819 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1820 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
1822 val
|= EDP_PSR_LINK_DISABLE
;
1824 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1825 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1826 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1827 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1831 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1833 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1834 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1836 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1837 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1839 lockdep_assert_held(&dev_priv
->psr
.lock
);
1840 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1841 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
1843 dev_priv
->psr
.source_ok
= false;
1845 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
1846 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1850 if (!i915
.enable_psr
) {
1851 DRM_DEBUG_KMS("PSR disable by flag\n");
1855 /* Below limitations aren't valid for Broadwell */
1856 if (IS_BROADWELL(dev
))
1859 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1861 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1865 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1866 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1871 dev_priv
->psr
.source_ok
= true;
1875 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1877 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1878 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1881 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1882 WARN_ON(dev_priv
->psr
.active
);
1883 lockdep_assert_held(&dev_priv
->psr
.lock
);
1885 /* Enable PSR on the panel */
1886 intel_edp_psr_enable_sink(intel_dp
);
1888 /* Enable PSR on the host */
1889 intel_edp_psr_enable_source(intel_dp
);
1891 dev_priv
->psr
.active
= true;
1894 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1896 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1899 if (!HAS_PSR(dev
)) {
1900 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1904 if (!is_edp_psr(intel_dp
)) {
1905 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1909 mutex_lock(&dev_priv
->psr
.lock
);
1910 if (dev_priv
->psr
.enabled
) {
1911 DRM_DEBUG_KMS("PSR already in use\n");
1912 mutex_unlock(&dev_priv
->psr
.lock
);
1916 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
1918 /* Setup PSR once */
1919 intel_edp_psr_setup(intel_dp
);
1921 if (intel_edp_psr_match_conditions(intel_dp
))
1922 dev_priv
->psr
.enabled
= intel_dp
;
1923 mutex_unlock(&dev_priv
->psr
.lock
);
1926 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1928 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1931 mutex_lock(&dev_priv
->psr
.lock
);
1932 if (!dev_priv
->psr
.enabled
) {
1933 mutex_unlock(&dev_priv
->psr
.lock
);
1937 if (dev_priv
->psr
.active
) {
1938 I915_WRITE(EDP_PSR_CTL(dev
),
1939 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1941 /* Wait till PSR is idle */
1942 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1943 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1944 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1946 dev_priv
->psr
.active
= false;
1948 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1951 dev_priv
->psr
.enabled
= NULL
;
1952 mutex_unlock(&dev_priv
->psr
.lock
);
1954 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
1957 static void intel_edp_psr_work(struct work_struct
*work
)
1959 struct drm_i915_private
*dev_priv
=
1960 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
1961 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
1963 mutex_lock(&dev_priv
->psr
.lock
);
1964 intel_dp
= dev_priv
->psr
.enabled
;
1970 * The delayed work can race with an invalidate hence we need to
1971 * recheck. Since psr_flush first clears this and then reschedules we
1972 * won't ever miss a flush when bailing out here.
1974 if (dev_priv
->psr
.busy_frontbuffer_bits
)
1977 intel_edp_psr_do_enable(intel_dp
);
1979 mutex_unlock(&dev_priv
->psr
.lock
);
1982 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
1984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 if (dev_priv
->psr
.active
) {
1987 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
1989 WARN_ON(!(val
& EDP_PSR_ENABLE
));
1991 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
1993 dev_priv
->psr
.active
= false;
1998 void intel_edp_psr_invalidate(struct drm_device
*dev
,
1999 unsigned frontbuffer_bits
)
2001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2002 struct drm_crtc
*crtc
;
2005 mutex_lock(&dev_priv
->psr
.lock
);
2006 if (!dev_priv
->psr
.enabled
) {
2007 mutex_unlock(&dev_priv
->psr
.lock
);
2011 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2012 pipe
= to_intel_crtc(crtc
)->pipe
;
2014 intel_edp_psr_do_exit(dev
);
2016 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2018 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2019 mutex_unlock(&dev_priv
->psr
.lock
);
2022 void intel_edp_psr_flush(struct drm_device
*dev
,
2023 unsigned frontbuffer_bits
)
2025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2026 struct drm_crtc
*crtc
;
2029 mutex_lock(&dev_priv
->psr
.lock
);
2030 if (!dev_priv
->psr
.enabled
) {
2031 mutex_unlock(&dev_priv
->psr
.lock
);
2035 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2036 pipe
= to_intel_crtc(crtc
)->pipe
;
2037 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2040 * On Haswell sprite plane updates don't result in a psr invalidating
2041 * signal in the hardware. Which means we need to manually fake this in
2042 * software for all flushes, not just when we've seen a preceding
2043 * invalidation through frontbuffer rendering.
2045 if (IS_HASWELL(dev
) &&
2046 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2047 intel_edp_psr_do_exit(dev
);
2049 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2050 schedule_delayed_work(&dev_priv
->psr
.work
,
2051 msecs_to_jiffies(100));
2052 mutex_unlock(&dev_priv
->psr
.lock
);
2055 void intel_edp_psr_init(struct drm_device
*dev
)
2057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2059 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2060 mutex_init(&dev_priv
->psr
.lock
);
2063 static void intel_disable_dp(struct intel_encoder
*encoder
)
2065 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2066 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2067 struct drm_device
*dev
= encoder
->base
.dev
;
2069 /* Make sure the panel is off before trying to change the mode. But also
2070 * ensure that we have vdd while we switch off the panel. */
2071 intel_edp_panel_vdd_on(intel_dp
);
2072 intel_edp_backlight_off(intel_dp
);
2073 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2074 intel_edp_panel_off(intel_dp
);
2076 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2077 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
2078 intel_dp_link_down(intel_dp
);
2081 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
2083 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2084 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2089 intel_dp_link_down(intel_dp
);
2090 ironlake_edp_pll_off(intel_dp
);
2093 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2095 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2097 intel_dp_link_down(intel_dp
);
2100 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2102 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2103 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2104 struct drm_device
*dev
= encoder
->base
.dev
;
2105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2106 struct intel_crtc
*intel_crtc
=
2107 to_intel_crtc(encoder
->base
.crtc
);
2108 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2109 enum pipe pipe
= intel_crtc
->pipe
;
2112 intel_dp_link_down(intel_dp
);
2114 mutex_lock(&dev_priv
->dpio_lock
);
2116 /* Propagate soft reset to data lane reset */
2117 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2118 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2119 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2121 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2122 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2123 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2125 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2126 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2127 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2129 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2130 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2131 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2133 mutex_unlock(&dev_priv
->dpio_lock
);
2136 static void intel_enable_dp(struct intel_encoder
*encoder
)
2138 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2139 struct drm_device
*dev
= encoder
->base
.dev
;
2140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2141 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2143 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2146 intel_edp_panel_vdd_on(intel_dp
);
2147 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2148 intel_dp_start_link_train(intel_dp
);
2149 intel_edp_panel_on(intel_dp
);
2150 intel_edp_panel_vdd_off(intel_dp
, true);
2151 intel_dp_complete_link_train(intel_dp
);
2152 intel_dp_stop_link_train(intel_dp
);
2155 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2157 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2159 intel_enable_dp(encoder
);
2160 intel_edp_backlight_on(intel_dp
);
2163 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2165 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2167 intel_edp_backlight_on(intel_dp
);
2170 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2172 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2173 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2175 intel_dp_prepare(encoder
);
2177 /* Only ilk+ has port A */
2178 if (dport
->port
== PORT_A
) {
2179 ironlake_set_pll_cpu_edp(intel_dp
);
2180 ironlake_edp_pll_on(intel_dp
);
2184 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2186 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2187 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2188 struct drm_device
*dev
= encoder
->base
.dev
;
2189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2190 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2191 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2192 int pipe
= intel_crtc
->pipe
;
2193 struct edp_power_seq power_seq
;
2196 mutex_lock(&dev_priv
->dpio_lock
);
2198 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2205 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2206 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2207 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2209 mutex_unlock(&dev_priv
->dpio_lock
);
2211 if (is_edp(intel_dp
)) {
2212 /* init power sequencer on this pipe and port */
2213 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2214 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2218 intel_enable_dp(encoder
);
2220 vlv_wait_port_ready(dev_priv
, dport
);
2223 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2225 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2226 struct drm_device
*dev
= encoder
->base
.dev
;
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2228 struct intel_crtc
*intel_crtc
=
2229 to_intel_crtc(encoder
->base
.crtc
);
2230 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2231 int pipe
= intel_crtc
->pipe
;
2233 intel_dp_prepare(encoder
);
2235 /* Program Tx lane resets to default */
2236 mutex_lock(&dev_priv
->dpio_lock
);
2237 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2238 DPIO_PCS_TX_LANE2_RESET
|
2239 DPIO_PCS_TX_LANE1_RESET
);
2240 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2241 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2242 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2243 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2244 DPIO_PCS_CLK_SOFT_RESET
);
2246 /* Fix up inter-pair skew failure */
2247 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2248 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2249 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2250 mutex_unlock(&dev_priv
->dpio_lock
);
2253 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2255 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2256 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2257 struct drm_device
*dev
= encoder
->base
.dev
;
2258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2259 struct edp_power_seq power_seq
;
2260 struct intel_crtc
*intel_crtc
=
2261 to_intel_crtc(encoder
->base
.crtc
);
2262 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2263 int pipe
= intel_crtc
->pipe
;
2267 mutex_lock(&dev_priv
->dpio_lock
);
2269 /* Deassert soft data lane reset*/
2270 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2271 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2272 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2274 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2275 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2276 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2278 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2279 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2280 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2282 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2283 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2284 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2286 /* Program Tx lane latency optimal setting*/
2287 for (i
= 0; i
< 4; i
++) {
2288 /* Set the latency optimal bit */
2289 data
= (i
== 1) ? 0x0 : 0x6;
2290 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2291 data
<< DPIO_FRC_LATENCY_SHFIT
);
2293 /* Set the upar bit */
2294 data
= (i
== 1) ? 0x0 : 0x1;
2295 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2296 data
<< DPIO_UPAR_SHIFT
);
2299 /* Data lane stagger programming */
2300 /* FIXME: Fix up value only after power analysis */
2302 mutex_unlock(&dev_priv
->dpio_lock
);
2304 if (is_edp(intel_dp
)) {
2305 /* init power sequencer on this pipe and port */
2306 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2307 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2311 intel_enable_dp(encoder
);
2313 vlv_wait_port_ready(dev_priv
, dport
);
2316 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2318 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2319 struct drm_device
*dev
= encoder
->base
.dev
;
2320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2321 struct intel_crtc
*intel_crtc
=
2322 to_intel_crtc(encoder
->base
.crtc
);
2323 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2324 enum pipe pipe
= intel_crtc
->pipe
;
2327 intel_dp_prepare(encoder
);
2329 mutex_lock(&dev_priv
->dpio_lock
);
2331 /* program left/right clock distribution */
2332 if (pipe
!= PIPE_B
) {
2333 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2334 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2336 val
|= CHV_BUFLEFTENA1_FORCE
;
2338 val
|= CHV_BUFRIGHTENA1_FORCE
;
2339 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2341 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2342 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2344 val
|= CHV_BUFLEFTENA2_FORCE
;
2346 val
|= CHV_BUFRIGHTENA2_FORCE
;
2347 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2350 /* program clock channel usage */
2351 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2352 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2354 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2356 val
|= CHV_PCS_USEDCLKCHANNEL
;
2357 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2359 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2360 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2362 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2364 val
|= CHV_PCS_USEDCLKCHANNEL
;
2365 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2368 * This a a bit weird since generally CL
2369 * matches the pipe, but here we need to
2370 * pick the CL based on the port.
2372 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2374 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2376 val
|= CHV_CMN_USEDCLKCHANNEL
;
2377 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2379 mutex_unlock(&dev_priv
->dpio_lock
);
2383 * Native read with retry for link status and receiver capability reads for
2384 * cases where the sink may still be asleep.
2386 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2387 * supposed to retry 3 times per the spec.
2390 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2391 void *buffer
, size_t size
)
2396 for (i
= 0; i
< 3; i
++) {
2397 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2407 * Fetch AUX CH registers 0x202 - 0x207 which contain
2408 * link status information
2411 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2413 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2416 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2419 /* These are source-specific values. */
2421 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2423 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2424 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2426 if (IS_VALLEYVIEW(dev
))
2427 return DP_TRAIN_VOLTAGE_SWING_1200
;
2428 else if (IS_GEN7(dev
) && port
== PORT_A
)
2429 return DP_TRAIN_VOLTAGE_SWING_800
;
2430 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2431 return DP_TRAIN_VOLTAGE_SWING_1200
;
2433 return DP_TRAIN_VOLTAGE_SWING_800
;
2437 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2439 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2440 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2442 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2443 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2444 case DP_TRAIN_VOLTAGE_SWING_400
:
2445 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2446 case DP_TRAIN_VOLTAGE_SWING_600
:
2447 return DP_TRAIN_PRE_EMPHASIS_6
;
2448 case DP_TRAIN_VOLTAGE_SWING_800
:
2449 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2450 case DP_TRAIN_VOLTAGE_SWING_1200
:
2452 return DP_TRAIN_PRE_EMPHASIS_0
;
2454 } else if (IS_VALLEYVIEW(dev
)) {
2455 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2456 case DP_TRAIN_VOLTAGE_SWING_400
:
2457 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2458 case DP_TRAIN_VOLTAGE_SWING_600
:
2459 return DP_TRAIN_PRE_EMPHASIS_6
;
2460 case DP_TRAIN_VOLTAGE_SWING_800
:
2461 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2462 case DP_TRAIN_VOLTAGE_SWING_1200
:
2464 return DP_TRAIN_PRE_EMPHASIS_0
;
2466 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2467 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2468 case DP_TRAIN_VOLTAGE_SWING_400
:
2469 return DP_TRAIN_PRE_EMPHASIS_6
;
2470 case DP_TRAIN_VOLTAGE_SWING_600
:
2471 case DP_TRAIN_VOLTAGE_SWING_800
:
2472 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2474 return DP_TRAIN_PRE_EMPHASIS_0
;
2477 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2478 case DP_TRAIN_VOLTAGE_SWING_400
:
2479 return DP_TRAIN_PRE_EMPHASIS_6
;
2480 case DP_TRAIN_VOLTAGE_SWING_600
:
2481 return DP_TRAIN_PRE_EMPHASIS_6
;
2482 case DP_TRAIN_VOLTAGE_SWING_800
:
2483 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2484 case DP_TRAIN_VOLTAGE_SWING_1200
:
2486 return DP_TRAIN_PRE_EMPHASIS_0
;
2491 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2493 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2495 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2496 struct intel_crtc
*intel_crtc
=
2497 to_intel_crtc(dport
->base
.base
.crtc
);
2498 unsigned long demph_reg_value
, preemph_reg_value
,
2499 uniqtranscale_reg_value
;
2500 uint8_t train_set
= intel_dp
->train_set
[0];
2501 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2502 int pipe
= intel_crtc
->pipe
;
2504 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2505 case DP_TRAIN_PRE_EMPHASIS_0
:
2506 preemph_reg_value
= 0x0004000;
2507 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2508 case DP_TRAIN_VOLTAGE_SWING_400
:
2509 demph_reg_value
= 0x2B405555;
2510 uniqtranscale_reg_value
= 0x552AB83A;
2512 case DP_TRAIN_VOLTAGE_SWING_600
:
2513 demph_reg_value
= 0x2B404040;
2514 uniqtranscale_reg_value
= 0x5548B83A;
2516 case DP_TRAIN_VOLTAGE_SWING_800
:
2517 demph_reg_value
= 0x2B245555;
2518 uniqtranscale_reg_value
= 0x5560B83A;
2520 case DP_TRAIN_VOLTAGE_SWING_1200
:
2521 demph_reg_value
= 0x2B405555;
2522 uniqtranscale_reg_value
= 0x5598DA3A;
2528 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2529 preemph_reg_value
= 0x0002000;
2530 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2531 case DP_TRAIN_VOLTAGE_SWING_400
:
2532 demph_reg_value
= 0x2B404040;
2533 uniqtranscale_reg_value
= 0x5552B83A;
2535 case DP_TRAIN_VOLTAGE_SWING_600
:
2536 demph_reg_value
= 0x2B404848;
2537 uniqtranscale_reg_value
= 0x5580B83A;
2539 case DP_TRAIN_VOLTAGE_SWING_800
:
2540 demph_reg_value
= 0x2B404040;
2541 uniqtranscale_reg_value
= 0x55ADDA3A;
2547 case DP_TRAIN_PRE_EMPHASIS_6
:
2548 preemph_reg_value
= 0x0000000;
2549 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2550 case DP_TRAIN_VOLTAGE_SWING_400
:
2551 demph_reg_value
= 0x2B305555;
2552 uniqtranscale_reg_value
= 0x5570B83A;
2554 case DP_TRAIN_VOLTAGE_SWING_600
:
2555 demph_reg_value
= 0x2B2B4040;
2556 uniqtranscale_reg_value
= 0x55ADDA3A;
2562 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2563 preemph_reg_value
= 0x0006000;
2564 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2565 case DP_TRAIN_VOLTAGE_SWING_400
:
2566 demph_reg_value
= 0x1B405555;
2567 uniqtranscale_reg_value
= 0x55ADDA3A;
2577 mutex_lock(&dev_priv
->dpio_lock
);
2578 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2579 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2580 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2581 uniqtranscale_reg_value
);
2582 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2583 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2584 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2585 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2586 mutex_unlock(&dev_priv
->dpio_lock
);
2591 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2593 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2595 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2596 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2597 u32 deemph_reg_value
, margin_reg_value
, val
;
2598 uint8_t train_set
= intel_dp
->train_set
[0];
2599 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2600 enum pipe pipe
= intel_crtc
->pipe
;
2603 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2604 case DP_TRAIN_PRE_EMPHASIS_0
:
2605 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2606 case DP_TRAIN_VOLTAGE_SWING_400
:
2607 deemph_reg_value
= 128;
2608 margin_reg_value
= 52;
2610 case DP_TRAIN_VOLTAGE_SWING_600
:
2611 deemph_reg_value
= 128;
2612 margin_reg_value
= 77;
2614 case DP_TRAIN_VOLTAGE_SWING_800
:
2615 deemph_reg_value
= 128;
2616 margin_reg_value
= 102;
2618 case DP_TRAIN_VOLTAGE_SWING_1200
:
2619 deemph_reg_value
= 128;
2620 margin_reg_value
= 154;
2621 /* FIXME extra to set for 1200 */
2627 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2628 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2629 case DP_TRAIN_VOLTAGE_SWING_400
:
2630 deemph_reg_value
= 85;
2631 margin_reg_value
= 78;
2633 case DP_TRAIN_VOLTAGE_SWING_600
:
2634 deemph_reg_value
= 85;
2635 margin_reg_value
= 116;
2637 case DP_TRAIN_VOLTAGE_SWING_800
:
2638 deemph_reg_value
= 85;
2639 margin_reg_value
= 154;
2645 case DP_TRAIN_PRE_EMPHASIS_6
:
2646 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2647 case DP_TRAIN_VOLTAGE_SWING_400
:
2648 deemph_reg_value
= 64;
2649 margin_reg_value
= 104;
2651 case DP_TRAIN_VOLTAGE_SWING_600
:
2652 deemph_reg_value
= 64;
2653 margin_reg_value
= 154;
2659 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2660 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2661 case DP_TRAIN_VOLTAGE_SWING_400
:
2662 deemph_reg_value
= 43;
2663 margin_reg_value
= 154;
2673 mutex_lock(&dev_priv
->dpio_lock
);
2675 /* Clear calc init */
2676 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2677 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2678 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2680 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2681 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2682 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2684 /* Program swing deemph */
2685 for (i
= 0; i
< 4; i
++) {
2686 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2687 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2688 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2689 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2692 /* Program swing margin */
2693 for (i
= 0; i
< 4; i
++) {
2694 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2695 val
&= ~DPIO_SWING_MARGIN000_MASK
;
2696 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
2697 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2700 /* Disable unique transition scale */
2701 for (i
= 0; i
< 4; i
++) {
2702 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2703 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2704 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2707 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
2708 == DP_TRAIN_PRE_EMPHASIS_0
) &&
2709 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
2710 == DP_TRAIN_VOLTAGE_SWING_1200
)) {
2713 * The document said it needs to set bit 27 for ch0 and bit 26
2714 * for ch1. Might be a typo in the doc.
2715 * For now, for this unique transition scale selection, set bit
2716 * 27 for ch0 and ch1.
2718 for (i
= 0; i
< 4; i
++) {
2719 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2720 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2721 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2724 for (i
= 0; i
< 4; i
++) {
2725 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2726 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2727 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2728 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2732 /* Start swing calculation */
2733 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2734 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2735 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2737 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2738 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2739 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2742 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
2743 val
|= DPIO_LRC_BYPASS
;
2744 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
2746 mutex_unlock(&dev_priv
->dpio_lock
);
2752 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2753 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2758 uint8_t voltage_max
;
2759 uint8_t preemph_max
;
2761 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2762 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2763 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2771 voltage_max
= intel_dp_voltage_max(intel_dp
);
2772 if (v
>= voltage_max
)
2773 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2775 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2776 if (p
>= preemph_max
)
2777 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2779 for (lane
= 0; lane
< 4; lane
++)
2780 intel_dp
->train_set
[lane
] = v
| p
;
2784 intel_gen4_signal_levels(uint8_t train_set
)
2786 uint32_t signal_levels
= 0;
2788 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2789 case DP_TRAIN_VOLTAGE_SWING_400
:
2791 signal_levels
|= DP_VOLTAGE_0_4
;
2793 case DP_TRAIN_VOLTAGE_SWING_600
:
2794 signal_levels
|= DP_VOLTAGE_0_6
;
2796 case DP_TRAIN_VOLTAGE_SWING_800
:
2797 signal_levels
|= DP_VOLTAGE_0_8
;
2799 case DP_TRAIN_VOLTAGE_SWING_1200
:
2800 signal_levels
|= DP_VOLTAGE_1_2
;
2803 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2804 case DP_TRAIN_PRE_EMPHASIS_0
:
2806 signal_levels
|= DP_PRE_EMPHASIS_0
;
2808 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2809 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2811 case DP_TRAIN_PRE_EMPHASIS_6
:
2812 signal_levels
|= DP_PRE_EMPHASIS_6
;
2814 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2815 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2818 return signal_levels
;
2821 /* Gen6's DP voltage swing and pre-emphasis control */
2823 intel_gen6_edp_signal_levels(uint8_t train_set
)
2825 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2826 DP_TRAIN_PRE_EMPHASIS_MASK
);
2827 switch (signal_levels
) {
2828 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2829 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2830 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2831 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2832 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2833 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2834 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2835 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2836 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2837 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2838 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2839 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2840 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2841 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2843 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2844 "0x%x\n", signal_levels
);
2845 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2849 /* Gen7's DP voltage swing and pre-emphasis control */
2851 intel_gen7_edp_signal_levels(uint8_t train_set
)
2853 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2854 DP_TRAIN_PRE_EMPHASIS_MASK
);
2855 switch (signal_levels
) {
2856 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2857 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2858 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2859 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2860 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2861 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2863 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2864 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2865 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2866 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2868 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2869 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2870 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2871 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2874 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2875 "0x%x\n", signal_levels
);
2876 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2880 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2882 intel_hsw_signal_levels(uint8_t train_set
)
2884 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2885 DP_TRAIN_PRE_EMPHASIS_MASK
);
2886 switch (signal_levels
) {
2887 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2888 return DDI_BUF_EMP_400MV_0DB_HSW
;
2889 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2890 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2891 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2892 return DDI_BUF_EMP_400MV_6DB_HSW
;
2893 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2894 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2896 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2897 return DDI_BUF_EMP_600MV_0DB_HSW
;
2898 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2899 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2900 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2901 return DDI_BUF_EMP_600MV_6DB_HSW
;
2903 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2904 return DDI_BUF_EMP_800MV_0DB_HSW
;
2905 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2906 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2908 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2909 "0x%x\n", signal_levels
);
2910 return DDI_BUF_EMP_400MV_0DB_HSW
;
2914 /* Properly updates "DP" with the correct signal levels. */
2916 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2918 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2919 enum port port
= intel_dig_port
->port
;
2920 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2921 uint32_t signal_levels
, mask
;
2922 uint8_t train_set
= intel_dp
->train_set
[0];
2924 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2925 signal_levels
= intel_hsw_signal_levels(train_set
);
2926 mask
= DDI_BUF_EMP_MASK
;
2927 } else if (IS_CHERRYVIEW(dev
)) {
2928 signal_levels
= intel_chv_signal_levels(intel_dp
);
2930 } else if (IS_VALLEYVIEW(dev
)) {
2931 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2933 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2934 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2935 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2936 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2937 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2938 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2940 signal_levels
= intel_gen4_signal_levels(train_set
);
2941 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2944 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2946 *DP
= (*DP
& ~mask
) | signal_levels
;
2950 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2952 uint8_t dp_train_pat
)
2954 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2955 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2957 enum port port
= intel_dig_port
->port
;
2958 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2962 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2964 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2965 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2967 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2969 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2970 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2971 case DP_TRAINING_PATTERN_DISABLE
:
2972 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2975 case DP_TRAINING_PATTERN_1
:
2976 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2978 case DP_TRAINING_PATTERN_2
:
2979 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2981 case DP_TRAINING_PATTERN_3
:
2982 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2985 I915_WRITE(DP_TP_CTL(port
), temp
);
2987 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2988 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2990 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2991 case DP_TRAINING_PATTERN_DISABLE
:
2992 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2994 case DP_TRAINING_PATTERN_1
:
2995 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2997 case DP_TRAINING_PATTERN_2
:
2998 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3000 case DP_TRAINING_PATTERN_3
:
3001 DRM_ERROR("DP training pattern 3 not supported\n");
3002 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3007 if (IS_CHERRYVIEW(dev
))
3008 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3010 *DP
&= ~DP_LINK_TRAIN_MASK
;
3012 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3013 case DP_TRAINING_PATTERN_DISABLE
:
3014 *DP
|= DP_LINK_TRAIN_OFF
;
3016 case DP_TRAINING_PATTERN_1
:
3017 *DP
|= DP_LINK_TRAIN_PAT_1
;
3019 case DP_TRAINING_PATTERN_2
:
3020 *DP
|= DP_LINK_TRAIN_PAT_2
;
3022 case DP_TRAINING_PATTERN_3
:
3023 if (IS_CHERRYVIEW(dev
)) {
3024 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
3026 DRM_ERROR("DP training pattern 3 not supported\n");
3027 *DP
|= DP_LINK_TRAIN_PAT_2
;
3033 I915_WRITE(intel_dp
->output_reg
, *DP
);
3034 POSTING_READ(intel_dp
->output_reg
);
3036 buf
[0] = dp_train_pat
;
3037 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3038 DP_TRAINING_PATTERN_DISABLE
) {
3039 /* don't write DP_TRAINING_LANEx_SET on disable */
3042 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3043 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3044 len
= intel_dp
->lane_count
+ 1;
3047 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3054 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3055 uint8_t dp_train_pat
)
3057 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3058 intel_dp_set_signal_levels(intel_dp
, DP
);
3059 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3063 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3064 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3066 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3067 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3071 intel_get_adjust_train(intel_dp
, link_status
);
3072 intel_dp_set_signal_levels(intel_dp
, DP
);
3074 I915_WRITE(intel_dp
->output_reg
, *DP
);
3075 POSTING_READ(intel_dp
->output_reg
);
3077 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3078 intel_dp
->train_set
, intel_dp
->lane_count
);
3080 return ret
== intel_dp
->lane_count
;
3083 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3085 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3086 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3088 enum port port
= intel_dig_port
->port
;
3094 val
= I915_READ(DP_TP_CTL(port
));
3095 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3096 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3097 I915_WRITE(DP_TP_CTL(port
), val
);
3100 * On PORT_A we can have only eDP in SST mode. There the only reason
3101 * we need to set idle transmission mode is to work around a HW issue
3102 * where we enable the pipe while not in idle link-training mode.
3103 * In this case there is requirement to wait for a minimum number of
3104 * idle patterns to be sent.
3109 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3111 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3114 /* Enable corresponding port and start training pattern 1 */
3116 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3118 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3119 struct drm_device
*dev
= encoder
->dev
;
3122 int voltage_tries
, loop_tries
;
3123 uint32_t DP
= intel_dp
->DP
;
3124 uint8_t link_config
[2];
3127 intel_ddi_prepare_link_retrain(encoder
);
3129 /* Write the link configuration data */
3130 link_config
[0] = intel_dp
->link_bw
;
3131 link_config
[1] = intel_dp
->lane_count
;
3132 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3133 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3134 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3137 link_config
[1] = DP_SET_ANSI_8B10B
;
3138 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3142 /* clock recovery */
3143 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3144 DP_TRAINING_PATTERN_1
|
3145 DP_LINK_SCRAMBLING_DISABLE
)) {
3146 DRM_ERROR("failed to enable link training\n");
3154 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3156 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3157 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3158 DRM_ERROR("failed to get link status\n");
3162 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3163 DRM_DEBUG_KMS("clock recovery OK\n");
3167 /* Check to see if we've tried the max voltage */
3168 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3169 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3171 if (i
== intel_dp
->lane_count
) {
3173 if (loop_tries
== 5) {
3174 DRM_ERROR("too many full retries, give up\n");
3177 intel_dp_reset_link_train(intel_dp
, &DP
,
3178 DP_TRAINING_PATTERN_1
|
3179 DP_LINK_SCRAMBLING_DISABLE
);
3184 /* Check to see if we've tried the same voltage 5 times */
3185 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3187 if (voltage_tries
== 5) {
3188 DRM_ERROR("too many voltage retries, give up\n");
3193 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3195 /* Update training set as requested by target */
3196 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3197 DRM_ERROR("failed to update link training\n");
3206 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3208 bool channel_eq
= false;
3209 int tries
, cr_tries
;
3210 uint32_t DP
= intel_dp
->DP
;
3211 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3213 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3214 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3215 training_pattern
= DP_TRAINING_PATTERN_3
;
3217 /* channel equalization */
3218 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3220 DP_LINK_SCRAMBLING_DISABLE
)) {
3221 DRM_ERROR("failed to start channel equalization\n");
3229 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3232 DRM_ERROR("failed to train DP, aborting\n");
3236 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3237 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3238 DRM_ERROR("failed to get link status\n");
3242 /* Make sure clock is still ok */
3243 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3244 intel_dp_start_link_train(intel_dp
);
3245 intel_dp_set_link_train(intel_dp
, &DP
,
3247 DP_LINK_SCRAMBLING_DISABLE
);
3252 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3257 /* Try 5 times, then try clock recovery if that fails */
3259 intel_dp_link_down(intel_dp
);
3260 intel_dp_start_link_train(intel_dp
);
3261 intel_dp_set_link_train(intel_dp
, &DP
,
3263 DP_LINK_SCRAMBLING_DISABLE
);
3269 /* Update training set as requested by target */
3270 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3271 DRM_ERROR("failed to update link training\n");
3277 intel_dp_set_idle_link_train(intel_dp
);
3282 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3286 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3288 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3289 DP_TRAINING_PATTERN_DISABLE
);
3293 intel_dp_link_down(struct intel_dp
*intel_dp
)
3295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3296 enum port port
= intel_dig_port
->port
;
3297 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3299 struct intel_crtc
*intel_crtc
=
3300 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3301 uint32_t DP
= intel_dp
->DP
;
3303 if (WARN_ON(HAS_DDI(dev
)))
3306 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3309 DRM_DEBUG_KMS("\n");
3311 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3312 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3313 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3315 if (IS_CHERRYVIEW(dev
))
3316 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3318 DP
&= ~DP_LINK_TRAIN_MASK
;
3319 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3321 POSTING_READ(intel_dp
->output_reg
);
3323 if (HAS_PCH_IBX(dev
) &&
3324 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3325 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3327 /* Hardware workaround: leaving our transcoder select
3328 * set to transcoder B while it's off will prevent the
3329 * corresponding HDMI output on transcoder A.
3331 * Combine this with another hardware workaround:
3332 * transcoder select bit can only be cleared while the
3335 DP
&= ~DP_PIPEB_SELECT
;
3336 I915_WRITE(intel_dp
->output_reg
, DP
);
3338 /* Changes to enable or select take place the vblank
3339 * after being written.
3341 if (WARN_ON(crtc
== NULL
)) {
3342 /* We should never try to disable a port without a crtc
3343 * attached. For paranoia keep the code around for a
3345 POSTING_READ(intel_dp
->output_reg
);
3348 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3351 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3352 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3353 POSTING_READ(intel_dp
->output_reg
);
3354 msleep(intel_dp
->panel_power_down_delay
);
3358 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3360 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3361 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3364 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
3366 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3367 sizeof(intel_dp
->dpcd
)) < 0)
3368 return false; /* aux transfer failed */
3370 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
3371 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
3372 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
3374 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3375 return false; /* DPCD not present */
3377 /* Check if the panel supports PSR */
3378 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3379 if (is_edp(intel_dp
)) {
3380 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3382 sizeof(intel_dp
->psr_dpcd
));
3383 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3384 dev_priv
->psr
.sink_support
= true;
3385 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3389 /* Training Pattern 3 support */
3390 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3391 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3392 intel_dp
->use_tps3
= true;
3393 DRM_DEBUG_KMS("Displayport TPS3 supported");
3395 intel_dp
->use_tps3
= false;
3397 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3398 DP_DWN_STRM_PORT_PRESENT
))
3399 return true; /* native DP sink */
3401 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3402 return true; /* no per-port downstream info */
3404 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3405 intel_dp
->downstream_ports
,
3406 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3407 return false; /* downstream port status fetch failed */
3413 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3417 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3420 intel_edp_panel_vdd_on(intel_dp
);
3422 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3423 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3424 buf
[0], buf
[1], buf
[2]);
3426 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3427 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3428 buf
[0], buf
[1], buf
[2]);
3430 intel_edp_panel_vdd_off(intel_dp
, false);
3434 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3438 if (!intel_dp
->can_mst
)
3441 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3444 intel_edp_panel_vdd_on(intel_dp
);
3445 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3446 if (buf
[0] & DP_MST_CAP
) {
3447 DRM_DEBUG_KMS("Sink is MST capable\n");
3448 intel_dp
->is_mst
= true;
3450 DRM_DEBUG_KMS("Sink is not MST capable\n");
3451 intel_dp
->is_mst
= false;
3454 intel_edp_panel_vdd_off(intel_dp
, false);
3456 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3457 return intel_dp
->is_mst
;
3460 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3462 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3463 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3464 struct intel_crtc
*intel_crtc
=
3465 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3468 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3471 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3474 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3475 DP_TEST_SINK_START
) < 0)
3478 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3479 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3480 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3482 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3485 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3490 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3492 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3493 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3494 sink_irq_vector
, 1) == 1;
3498 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3502 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3504 sink_irq_vector
, 14);
3512 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3514 /* NAK by default */
3515 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3519 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3523 if (intel_dp
->is_mst
) {
3528 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3532 /* check link status - esi[10] = 0x200c */
3533 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3534 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3535 intel_dp_start_link_train(intel_dp
);
3536 intel_dp_complete_link_train(intel_dp
);
3537 intel_dp_stop_link_train(intel_dp
);
3540 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3541 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3544 for (retry
= 0; retry
< 3; retry
++) {
3546 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3547 DP_SINK_COUNT_ESI
+1,
3554 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3556 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3564 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3565 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3566 intel_dp
->is_mst
= false;
3567 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3568 /* send a hotplug event */
3569 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3576 * According to DP spec
3579 * 2. Configure link according to Receiver Capabilities
3580 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3581 * 4. Check link status on receipt of hot-plug interrupt
3584 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3586 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3587 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3589 u8 link_status
[DP_LINK_STATUS_SIZE
];
3591 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3593 if (!intel_encoder
->connectors_active
)
3596 if (WARN_ON(!intel_encoder
->base
.crtc
))
3599 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3602 /* Try to read receiver status if the link appears to be up */
3603 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3607 /* Now read the DPCD to see if it's actually running */
3608 if (!intel_dp_get_dpcd(intel_dp
)) {
3612 /* Try to read the source of the interrupt */
3613 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3614 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3615 /* Clear interrupt source */
3616 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3617 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3620 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3621 intel_dp_handle_test_request(intel_dp
);
3622 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3623 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3626 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3627 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3628 intel_encoder
->base
.name
);
3629 intel_dp_start_link_train(intel_dp
);
3630 intel_dp_complete_link_train(intel_dp
);
3631 intel_dp_stop_link_train(intel_dp
);
3635 /* XXX this is probably wrong for multiple downstream ports */
3636 static enum drm_connector_status
3637 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3639 uint8_t *dpcd
= intel_dp
->dpcd
;
3642 if (!intel_dp_get_dpcd(intel_dp
))
3643 return connector_status_disconnected
;
3645 /* if there's no downstream port, we're done */
3646 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3647 return connector_status_connected
;
3649 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3650 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3651 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3654 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3656 return connector_status_unknown
;
3658 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3659 : connector_status_disconnected
;
3662 /* If no HPD, poke DDC gently */
3663 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3664 return connector_status_connected
;
3666 /* Well we tried, say unknown for unreliable port types */
3667 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3668 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3669 if (type
== DP_DS_PORT_TYPE_VGA
||
3670 type
== DP_DS_PORT_TYPE_NON_EDID
)
3671 return connector_status_unknown
;
3673 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3674 DP_DWN_STRM_PORT_TYPE_MASK
;
3675 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3676 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3677 return connector_status_unknown
;
3680 /* Anything else is out of spec, warn and ignore */
3681 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3682 return connector_status_disconnected
;
3685 static enum drm_connector_status
3686 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3688 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3690 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3691 enum drm_connector_status status
;
3693 /* Can't disconnect eDP, but you can close the lid... */
3694 if (is_edp(intel_dp
)) {
3695 status
= intel_panel_detect(dev
);
3696 if (status
== connector_status_unknown
)
3697 status
= connector_status_connected
;
3701 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3702 return connector_status_disconnected
;
3704 return intel_dp_detect_dpcd(intel_dp
);
3707 static enum drm_connector_status
3708 g4x_dp_detect(struct intel_dp
*intel_dp
)
3710 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3712 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3715 /* Can't disconnect eDP, but you can close the lid... */
3716 if (is_edp(intel_dp
)) {
3717 enum drm_connector_status status
;
3719 status
= intel_panel_detect(dev
);
3720 if (status
== connector_status_unknown
)
3721 status
= connector_status_connected
;
3725 if (IS_VALLEYVIEW(dev
)) {
3726 switch (intel_dig_port
->port
) {
3728 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3731 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3734 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3737 return connector_status_unknown
;
3740 switch (intel_dig_port
->port
) {
3742 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3745 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3748 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3751 return connector_status_unknown
;
3755 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3756 return connector_status_disconnected
;
3758 return intel_dp_detect_dpcd(intel_dp
);
3761 static struct edid
*
3762 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3764 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3766 /* use cached edid if we have one */
3767 if (intel_connector
->edid
) {
3769 if (IS_ERR(intel_connector
->edid
))
3772 return drm_edid_duplicate(intel_connector
->edid
);
3775 return drm_get_edid(connector
, adapter
);
3779 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3781 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3783 /* use cached edid if we have one */
3784 if (intel_connector
->edid
) {
3786 if (IS_ERR(intel_connector
->edid
))
3789 return intel_connector_update_modes(connector
,
3790 intel_connector
->edid
);
3793 return intel_ddc_get_modes(connector
, adapter
);
3796 static enum drm_connector_status
3797 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3799 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3800 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3801 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3802 struct drm_device
*dev
= connector
->dev
;
3803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3804 enum drm_connector_status status
;
3805 enum intel_display_power_domain power_domain
;
3806 struct edid
*edid
= NULL
;
3809 power_domain
= intel_display_port_power_domain(intel_encoder
);
3810 intel_display_power_get(dev_priv
, power_domain
);
3812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3813 connector
->base
.id
, connector
->name
);
3815 if (intel_dp
->is_mst
) {
3816 /* MST devices are disconnected from a monitor POV */
3817 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3818 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3819 status
= connector_status_disconnected
;
3823 intel_dp
->has_audio
= false;
3825 if (HAS_PCH_SPLIT(dev
))
3826 status
= ironlake_dp_detect(intel_dp
);
3828 status
= g4x_dp_detect(intel_dp
);
3830 if (status
!= connector_status_connected
)
3833 intel_dp_probe_oui(intel_dp
);
3835 ret
= intel_dp_probe_mst(intel_dp
);
3837 /* if we are in MST mode then this connector
3838 won't appear connected or have anything with EDID on it */
3839 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3840 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3841 status
= connector_status_disconnected
;
3845 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3846 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3848 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3850 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3855 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3856 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3857 status
= connector_status_connected
;
3860 intel_display_power_put(dev_priv
, power_domain
);
3864 static int intel_dp_get_modes(struct drm_connector
*connector
)
3866 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3867 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3868 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3869 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3870 struct drm_device
*dev
= connector
->dev
;
3871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3872 enum intel_display_power_domain power_domain
;
3875 /* We should parse the EDID data and find out if it has an audio sink
3878 power_domain
= intel_display_port_power_domain(intel_encoder
);
3879 intel_display_power_get(dev_priv
, power_domain
);
3881 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3882 intel_display_power_put(dev_priv
, power_domain
);
3886 /* if eDP has no EDID, fall back to fixed mode */
3887 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3888 struct drm_display_mode
*mode
;
3889 mode
= drm_mode_duplicate(dev
,
3890 intel_connector
->panel
.fixed_mode
);
3892 drm_mode_probed_add(connector
, mode
);
3900 intel_dp_detect_audio(struct drm_connector
*connector
)
3902 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3903 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3904 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3905 struct drm_device
*dev
= connector
->dev
;
3906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3907 enum intel_display_power_domain power_domain
;
3909 bool has_audio
= false;
3911 power_domain
= intel_display_port_power_domain(intel_encoder
);
3912 intel_display_power_get(dev_priv
, power_domain
);
3914 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3916 has_audio
= drm_detect_monitor_audio(edid
);
3920 intel_display_power_put(dev_priv
, power_domain
);
3926 intel_dp_set_property(struct drm_connector
*connector
,
3927 struct drm_property
*property
,
3930 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3931 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3932 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3933 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3936 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3940 if (property
== dev_priv
->force_audio_property
) {
3944 if (i
== intel_dp
->force_audio
)
3947 intel_dp
->force_audio
= i
;
3949 if (i
== HDMI_AUDIO_AUTO
)
3950 has_audio
= intel_dp_detect_audio(connector
);
3952 has_audio
= (i
== HDMI_AUDIO_ON
);
3954 if (has_audio
== intel_dp
->has_audio
)
3957 intel_dp
->has_audio
= has_audio
;
3961 if (property
== dev_priv
->broadcast_rgb_property
) {
3962 bool old_auto
= intel_dp
->color_range_auto
;
3963 uint32_t old_range
= intel_dp
->color_range
;
3966 case INTEL_BROADCAST_RGB_AUTO
:
3967 intel_dp
->color_range_auto
= true;
3969 case INTEL_BROADCAST_RGB_FULL
:
3970 intel_dp
->color_range_auto
= false;
3971 intel_dp
->color_range
= 0;
3973 case INTEL_BROADCAST_RGB_LIMITED
:
3974 intel_dp
->color_range_auto
= false;
3975 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3981 if (old_auto
== intel_dp
->color_range_auto
&&
3982 old_range
== intel_dp
->color_range
)
3988 if (is_edp(intel_dp
) &&
3989 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3990 if (val
== DRM_MODE_SCALE_NONE
) {
3991 DRM_DEBUG_KMS("no scaling not supported\n");
3995 if (intel_connector
->panel
.fitting_mode
== val
) {
3996 /* the eDP scaling property is not changed */
3999 intel_connector
->panel
.fitting_mode
= val
;
4007 if (intel_encoder
->base
.crtc
)
4008 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4014 intel_dp_connector_destroy(struct drm_connector
*connector
)
4016 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4018 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4019 kfree(intel_connector
->edid
);
4021 /* Can't call is_edp() since the encoder may have been destroyed
4023 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4024 intel_panel_fini(&intel_connector
->panel
);
4026 drm_connector_cleanup(connector
);
4030 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4032 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4033 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4034 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4036 drm_dp_aux_unregister(&intel_dp
->aux
);
4037 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4038 drm_encoder_cleanup(encoder
);
4039 if (is_edp(intel_dp
)) {
4040 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4041 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4042 edp_panel_vdd_off_sync(intel_dp
);
4043 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4044 if (intel_dp
->edp_notifier
.notifier_call
) {
4045 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4046 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4049 kfree(intel_dig_port
);
4052 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4054 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4056 if (!is_edp(intel_dp
))
4059 edp_panel_vdd_off_sync(intel_dp
);
4062 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4064 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4067 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4068 .dpms
= intel_connector_dpms
,
4069 .detect
= intel_dp_detect
,
4070 .fill_modes
= drm_helper_probe_single_connector_modes
,
4071 .set_property
= intel_dp_set_property
,
4072 .destroy
= intel_dp_connector_destroy
,
4075 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4076 .get_modes
= intel_dp_get_modes
,
4077 .mode_valid
= intel_dp_mode_valid
,
4078 .best_encoder
= intel_best_encoder
,
4081 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4082 .reset
= intel_dp_encoder_reset
,
4083 .destroy
= intel_dp_encoder_destroy
,
4087 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4093 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4095 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4096 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4097 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4099 enum intel_display_power_domain power_domain
;
4102 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4103 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4105 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4106 port_name(intel_dig_port
->port
),
4107 long_hpd
? "long" : "short");
4109 power_domain
= intel_display_port_power_domain(intel_encoder
);
4110 intel_display_power_get(dev_priv
, power_domain
);
4113 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4116 if (!intel_dp_get_dpcd(intel_dp
)) {
4120 intel_dp_probe_oui(intel_dp
);
4122 if (!intel_dp_probe_mst(intel_dp
))
4126 if (intel_dp
->is_mst
) {
4127 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4131 if (!intel_dp
->is_mst
) {
4133 * we'll check the link status via the normal hot plug path later -
4134 * but for short hpds we should check it now
4136 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4137 intel_dp_check_link_status(intel_dp
);
4138 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4144 /* if we were in MST mode, and device is not there get out of MST mode */
4145 if (intel_dp
->is_mst
) {
4146 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4147 intel_dp
->is_mst
= false;
4148 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4151 intel_display_power_put(dev_priv
, power_domain
);
4156 /* Return which DP Port should be selected for Transcoder DP control */
4158 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4160 struct drm_device
*dev
= crtc
->dev
;
4161 struct intel_encoder
*intel_encoder
;
4162 struct intel_dp
*intel_dp
;
4164 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4165 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4167 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4168 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4169 return intel_dp
->output_reg
;
4175 /* check the VBT to see whether the eDP is on DP-D port */
4176 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4179 union child_device_config
*p_child
;
4181 static const short port_mapping
[] = {
4182 [PORT_B
] = PORT_IDPB
,
4183 [PORT_C
] = PORT_IDPC
,
4184 [PORT_D
] = PORT_IDPD
,
4190 if (!dev_priv
->vbt
.child_dev_num
)
4193 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4194 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4196 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4197 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4198 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4205 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4207 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4209 intel_attach_force_audio_property(connector
);
4210 intel_attach_broadcast_rgb_property(connector
);
4211 intel_dp
->color_range_auto
= true;
4213 if (is_edp(intel_dp
)) {
4214 drm_mode_create_scaling_mode_property(connector
->dev
);
4215 drm_object_attach_property(
4217 connector
->dev
->mode_config
.scaling_mode_property
,
4218 DRM_MODE_SCALE_ASPECT
);
4219 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4223 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4225 intel_dp
->last_power_cycle
= jiffies
;
4226 intel_dp
->last_power_on
= jiffies
;
4227 intel_dp
->last_backlight_off
= jiffies
;
4231 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4232 struct intel_dp
*intel_dp
,
4233 struct edp_power_seq
*out
)
4235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4236 struct edp_power_seq cur
, vbt
, spec
, final
;
4237 u32 pp_on
, pp_off
, pp_div
, pp
;
4238 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4240 if (HAS_PCH_SPLIT(dev
)) {
4241 pp_ctrl_reg
= PCH_PP_CONTROL
;
4242 pp_on_reg
= PCH_PP_ON_DELAYS
;
4243 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4244 pp_div_reg
= PCH_PP_DIVISOR
;
4246 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4248 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4249 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4250 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4251 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4254 /* Workaround: Need to write PP_CONTROL with the unlock key as
4255 * the very first thing. */
4256 pp
= ironlake_get_pp_control(intel_dp
);
4257 I915_WRITE(pp_ctrl_reg
, pp
);
4259 pp_on
= I915_READ(pp_on_reg
);
4260 pp_off
= I915_READ(pp_off_reg
);
4261 pp_div
= I915_READ(pp_div_reg
);
4263 /* Pull timing values out of registers */
4264 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4265 PANEL_POWER_UP_DELAY_SHIFT
;
4267 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4268 PANEL_LIGHT_ON_DELAY_SHIFT
;
4270 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4271 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4273 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4274 PANEL_POWER_DOWN_DELAY_SHIFT
;
4276 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4277 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4279 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4280 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4282 vbt
= dev_priv
->vbt
.edp_pps
;
4284 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4285 * our hw here, which are all in 100usec. */
4286 spec
.t1_t3
= 210 * 10;
4287 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4288 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4289 spec
.t10
= 500 * 10;
4290 /* This one is special and actually in units of 100ms, but zero
4291 * based in the hw (so we need to add 100 ms). But the sw vbt
4292 * table multiplies it with 1000 to make it in units of 100usec,
4294 spec
.t11_t12
= (510 + 100) * 10;
4296 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4297 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4299 /* Use the max of the register settings and vbt. If both are
4300 * unset, fall back to the spec limits. */
4301 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4303 max(cur.field, vbt.field))
4304 assign_final(t1_t3
);
4308 assign_final(t11_t12
);
4311 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4312 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4313 intel_dp
->backlight_on_delay
= get_delay(t8
);
4314 intel_dp
->backlight_off_delay
= get_delay(t9
);
4315 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4316 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4319 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4320 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4321 intel_dp
->panel_power_cycle_delay
);
4323 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4324 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4331 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4332 struct intel_dp
*intel_dp
,
4333 struct edp_power_seq
*seq
)
4335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4336 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4337 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4338 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4339 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4341 if (HAS_PCH_SPLIT(dev
)) {
4342 pp_on_reg
= PCH_PP_ON_DELAYS
;
4343 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4344 pp_div_reg
= PCH_PP_DIVISOR
;
4346 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4348 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4349 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4350 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4354 * And finally store the new values in the power sequencer. The
4355 * backlight delays are set to 1 because we do manual waits on them. For
4356 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4357 * we'll end up waiting for the backlight off delay twice: once when we
4358 * do the manual sleep, and once when we disable the panel and wait for
4359 * the PP_STATUS bit to become zero.
4361 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4362 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4363 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4364 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4365 /* Compute the divisor for the pp clock, simply match the Bspec
4367 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4368 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4369 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4371 /* Haswell doesn't have any port selection bits for the panel
4372 * power sequencer any more. */
4373 if (IS_VALLEYVIEW(dev
)) {
4374 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4375 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4377 port_sel
= PANEL_PORT_SELECT_DPA
;
4379 port_sel
= PANEL_PORT_SELECT_DPD
;
4384 I915_WRITE(pp_on_reg
, pp_on
);
4385 I915_WRITE(pp_off_reg
, pp_off
);
4386 I915_WRITE(pp_div_reg
, pp_div
);
4388 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4389 I915_READ(pp_on_reg
),
4390 I915_READ(pp_off_reg
),
4391 I915_READ(pp_div_reg
));
4394 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4397 struct intel_encoder
*encoder
;
4398 struct intel_dp
*intel_dp
= NULL
;
4399 struct intel_crtc_config
*config
= NULL
;
4400 struct intel_crtc
*intel_crtc
= NULL
;
4401 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4403 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4405 if (refresh_rate
<= 0) {
4406 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4410 if (intel_connector
== NULL
) {
4411 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4416 * FIXME: This needs proper synchronization with psr state. But really
4417 * hard to tell without seeing the user of this function of this code.
4418 * Check locking and ordering once that lands.
4420 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4421 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4425 encoder
= intel_attached_encoder(&intel_connector
->base
);
4426 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4427 intel_crtc
= encoder
->new_crtc
;
4430 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4434 config
= &intel_crtc
->config
;
4436 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4437 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4441 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4442 index
= DRRS_LOW_RR
;
4444 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4446 "DRRS requested for previously set RR...ignoring\n");
4450 if (!intel_crtc
->active
) {
4451 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4455 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4456 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4457 val
= I915_READ(reg
);
4458 if (index
> DRRS_HIGH_RR
) {
4459 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4460 intel_dp_set_m_n(intel_crtc
);
4462 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4464 I915_WRITE(reg
, val
);
4468 * mutex taken to ensure that there is no race between differnt
4469 * drrs calls trying to update refresh rate. This scenario may occur
4470 * in future when idleness detection based DRRS in kernel and
4471 * possible calls from user space to set differnt RR are made.
4474 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4476 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4478 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4480 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4483 static struct drm_display_mode
*
4484 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4485 struct intel_connector
*intel_connector
,
4486 struct drm_display_mode
*fixed_mode
)
4488 struct drm_connector
*connector
= &intel_connector
->base
;
4489 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4490 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4492 struct drm_display_mode
*downclock_mode
= NULL
;
4494 if (INTEL_INFO(dev
)->gen
<= 6) {
4495 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4499 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4500 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4504 downclock_mode
= intel_find_panel_downclock
4505 (dev
, fixed_mode
, connector
);
4507 if (!downclock_mode
) {
4508 DRM_DEBUG_KMS("DRRS not supported\n");
4512 dev_priv
->drrs
.connector
= intel_connector
;
4514 mutex_init(&intel_dp
->drrs_state
.mutex
);
4516 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4518 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4519 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4520 return downclock_mode
;
4523 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
4525 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4527 struct intel_dp
*intel_dp
;
4528 enum intel_display_power_domain power_domain
;
4530 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4533 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4534 if (!edp_have_panel_vdd(intel_dp
))
4537 * The VDD bit needs a power domain reference, so if the bit is
4538 * already enabled when we boot or resume, grab this reference and
4539 * schedule a vdd off, so we don't hold on to the reference
4542 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4543 power_domain
= intel_display_port_power_domain(intel_encoder
);
4544 intel_display_power_get(dev_priv
, power_domain
);
4546 edp_panel_vdd_schedule_off(intel_dp
);
4549 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4550 struct intel_connector
*intel_connector
,
4551 struct edp_power_seq
*power_seq
)
4553 struct drm_connector
*connector
= &intel_connector
->base
;
4554 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4555 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4556 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4558 struct drm_display_mode
*fixed_mode
= NULL
;
4559 struct drm_display_mode
*downclock_mode
= NULL
;
4561 struct drm_display_mode
*scan
;
4564 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4566 if (!is_edp(intel_dp
))
4569 intel_edp_panel_vdd_sanitize(intel_encoder
);
4571 /* Cache DPCD and EDID for edp. */
4572 intel_edp_panel_vdd_on(intel_dp
);
4573 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4574 intel_edp_panel_vdd_off(intel_dp
, false);
4577 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4578 dev_priv
->no_aux_handshake
=
4579 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4580 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4582 /* if this fails, presume the device is a ghost */
4583 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4587 /* We now know it's not a ghost, init power sequence regs. */
4588 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4590 mutex_lock(&dev
->mode_config
.mutex
);
4591 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4593 if (drm_add_edid_modes(connector
, edid
)) {
4594 drm_mode_connector_update_edid_property(connector
,
4596 drm_edid_to_eld(connector
, edid
);
4599 edid
= ERR_PTR(-EINVAL
);
4602 edid
= ERR_PTR(-ENOENT
);
4604 intel_connector
->edid
= edid
;
4606 /* prefer fixed mode from EDID if available */
4607 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4608 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4609 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4610 downclock_mode
= intel_dp_drrs_init(
4612 intel_connector
, fixed_mode
);
4617 /* fallback to VBT if available for eDP */
4618 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4619 fixed_mode
= drm_mode_duplicate(dev
,
4620 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4622 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4624 mutex_unlock(&dev
->mode_config
.mutex
);
4626 if (IS_VALLEYVIEW(dev
)) {
4627 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4628 register_reboot_notifier(&intel_dp
->edp_notifier
);
4631 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4632 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
4633 intel_panel_setup_backlight(connector
);
4639 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4640 struct intel_connector
*intel_connector
)
4642 struct drm_connector
*connector
= &intel_connector
->base
;
4643 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4644 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4645 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4647 enum port port
= intel_dig_port
->port
;
4648 struct edp_power_seq power_seq
= { 0 };
4651 /* intel_dp vfuncs */
4652 if (IS_VALLEYVIEW(dev
))
4653 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4654 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4655 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4656 else if (HAS_PCH_SPLIT(dev
))
4657 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4659 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4661 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4663 /* Preserve the current hw state. */
4664 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4665 intel_dp
->attached_connector
= intel_connector
;
4667 if (intel_dp_is_edp(dev
, port
))
4668 type
= DRM_MODE_CONNECTOR_eDP
;
4670 type
= DRM_MODE_CONNECTOR_DisplayPort
;
4673 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4674 * for DP the encoder type can be set by the caller to
4675 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4677 if (type
== DRM_MODE_CONNECTOR_eDP
)
4678 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
4680 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4681 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
4684 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
4685 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
4687 connector
->interlace_allowed
= true;
4688 connector
->doublescan_allowed
= 0;
4690 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
4691 edp_panel_vdd_work
);
4693 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
4694 drm_connector_register(connector
);
4697 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
4699 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
4700 intel_connector
->unregister
= intel_dp_connector_unregister
;
4702 /* Set up the hotplug pin. */
4705 intel_encoder
->hpd_pin
= HPD_PORT_A
;
4708 intel_encoder
->hpd_pin
= HPD_PORT_B
;
4711 intel_encoder
->hpd_pin
= HPD_PORT_C
;
4714 intel_encoder
->hpd_pin
= HPD_PORT_D
;
4720 if (is_edp(intel_dp
)) {
4721 intel_dp_init_panel_power_timestamps(intel_dp
);
4722 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
4725 intel_dp_aux_init(intel_dp
, intel_connector
);
4727 /* init MST on ports that can support it */
4728 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4729 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
4730 intel_dp_mst_encoder_init(intel_dig_port
, intel_connector
->base
.base
.id
);
4734 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
4735 drm_dp_aux_unregister(&intel_dp
->aux
);
4736 if (is_edp(intel_dp
)) {
4737 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4738 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4739 edp_panel_vdd_off_sync(intel_dp
);
4740 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4742 drm_connector_unregister(connector
);
4743 drm_connector_cleanup(connector
);
4747 intel_dp_add_properties(intel_dp
, connector
);
4749 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4750 * 0xd. Failure to do so will result in spurious interrupts being
4751 * generated on the port when a cable is not attached.
4753 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
4754 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
4755 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
4762 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
4764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4765 struct intel_digital_port
*intel_dig_port
;
4766 struct intel_encoder
*intel_encoder
;
4767 struct drm_encoder
*encoder
;
4768 struct intel_connector
*intel_connector
;
4770 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
4771 if (!intel_dig_port
)
4774 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
4775 if (!intel_connector
) {
4776 kfree(intel_dig_port
);
4780 intel_encoder
= &intel_dig_port
->base
;
4781 encoder
= &intel_encoder
->base
;
4783 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4784 DRM_MODE_ENCODER_TMDS
);
4786 intel_encoder
->compute_config
= intel_dp_compute_config
;
4787 intel_encoder
->disable
= intel_disable_dp
;
4788 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4789 intel_encoder
->get_config
= intel_dp_get_config
;
4790 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
4791 if (IS_CHERRYVIEW(dev
)) {
4792 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
4793 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
4794 intel_encoder
->enable
= vlv_enable_dp
;
4795 intel_encoder
->post_disable
= chv_post_disable_dp
;
4796 } else if (IS_VALLEYVIEW(dev
)) {
4797 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4798 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4799 intel_encoder
->enable
= vlv_enable_dp
;
4800 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4802 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4803 intel_encoder
->enable
= g4x_enable_dp
;
4804 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4807 intel_dig_port
->port
= port
;
4808 intel_dig_port
->dp
.output_reg
= output_reg
;
4810 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4811 if (IS_CHERRYVIEW(dev
)) {
4813 intel_encoder
->crtc_mask
= 1 << 2;
4815 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
4817 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4819 intel_encoder
->cloneable
= 0;
4820 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4822 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
4823 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
4825 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4826 drm_encoder_cleanup(encoder
);
4827 kfree(intel_dig_port
);
4828 kfree(intel_connector
);
4832 void intel_dp_mst_suspend(struct drm_device
*dev
)
4834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4838 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4839 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4840 if (!intel_dig_port
)
4843 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4844 if (!intel_dig_port
->dp
.can_mst
)
4846 if (intel_dig_port
->dp
.is_mst
)
4847 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
4852 void intel_dp_mst_resume(struct drm_device
*dev
)
4854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4857 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4858 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4859 if (!intel_dig_port
)
4861 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4864 if (!intel_dig_port
->dp
.can_mst
)
4867 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
4869 intel_dp_check_mst_status(&intel_dig_port
->dp
);