2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 /* Compliance test status bits */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
48 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
57 static const struct dp_link_dpll gen4_dpll
[] = {
59 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
61 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
64 static const struct dp_link_dpll pch_dpll
[] = {
66 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
68 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
71 static const struct dp_link_dpll vlv_dpll
[] = {
73 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
75 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
79 * CHV supports eDP 1.4 that have more link rates.
80 * Below only provides the fixed rate but exclude variable rate.
82 static const struct dp_link_dpll chv_dpll
[] = {
84 * CHV requires to program fractional division for m2.
85 * m2 is stored in fixed point format using formula below
86 * (m2_int << 22) | m2_fraction
88 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
89 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
90 { 270000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
92 { 540000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
96 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
97 324000, 432000, 540000 };
98 static const int skl_rates
[] = { 162000, 216000, 270000,
99 324000, 432000, 540000 };
100 static const int cnl_rates
[] = { 162000, 216000, 270000,
101 324000, 432000, 540000,
103 static const int default_rates
[] = { 162000, 270000, 540000 };
106 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
107 * @intel_dp: DP struct
109 * If a CPU or PCH DP output is attached to an eDP panel, this function
110 * will return true, and false otherwise.
112 static bool is_edp(struct intel_dp
*intel_dp
)
114 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
116 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
119 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
121 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
123 return intel_dig_port
->base
.base
.dev
;
126 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
128 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
131 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
132 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
133 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
134 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
135 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
137 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
139 static int intel_dp_num_rates(u8 link_bw_code
)
141 switch (link_bw_code
) {
143 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
145 case DP_LINK_BW_1_62
:
154 /* update sink rates from dpcd */
155 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
159 num_rates
= intel_dp_num_rates(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
161 for (i
= 0; i
< num_rates
; i
++)
162 intel_dp
->sink_rates
[i
] = default_rates
[i
];
164 intel_dp
->num_sink_rates
= num_rates
;
167 /* Theoretical max between source and sink */
168 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
170 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
173 /* Theoretical max between source and sink */
174 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
176 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
177 int source_max
= intel_dig_port
->max_lanes
;
178 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
180 return min(source_max
, sink_max
);
183 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
185 return intel_dp
->max_link_lane_count
;
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
192 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
196 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
198 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
199 * link rate that is generally expressed in Gbps. Since, 8 bits of data
200 * is transmitted every LS_Clk per lane, there is no need to account for
201 * the channel encoding that is done in the PHY layer here.
204 return max_link_clock
* max_lanes
;
208 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
210 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
211 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
212 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
213 int max_dotclk
= dev_priv
->max_dotclk_freq
;
216 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
218 if (type
!= DP_DS_PORT_TYPE_VGA
)
221 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
222 intel_dp
->downstream_ports
);
224 if (ds_max_dotclk
!= 0)
225 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
231 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
233 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
234 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
235 enum port port
= dig_port
->port
;
236 const int *source_rates
;
240 /* This should only be done once */
241 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
243 if (IS_GEN9_LP(dev_priv
)) {
244 source_rates
= bxt_rates
;
245 size
= ARRAY_SIZE(bxt_rates
);
246 } else if (IS_CANNONLAKE(dev_priv
)) {
247 source_rates
= cnl_rates
;
248 size
= ARRAY_SIZE(cnl_rates
);
249 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
250 if (port
== PORT_A
|| port
== PORT_D
||
251 voltage
== VOLTAGE_INFO_0_85V
)
253 } else if (IS_GEN9_BC(dev_priv
)) {
254 source_rates
= skl_rates
;
255 size
= ARRAY_SIZE(skl_rates
);
257 source_rates
= default_rates
;
258 size
= ARRAY_SIZE(default_rates
);
261 /* This depends on the fact that 5.4 is last value in the array */
262 if (!intel_dp_source_supports_hbr2(intel_dp
))
265 intel_dp
->source_rates
= source_rates
;
266 intel_dp
->num_source_rates
= size
;
269 static int intersect_rates(const int *source_rates
, int source_len
,
270 const int *sink_rates
, int sink_len
,
273 int i
= 0, j
= 0, k
= 0;
275 while (i
< source_len
&& j
< sink_len
) {
276 if (source_rates
[i
] == sink_rates
[j
]) {
277 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
279 common_rates
[k
] = source_rates
[i
];
283 } else if (source_rates
[i
] < sink_rates
[j
]) {
292 /* return index of rate in rates array, or -1 if not found */
293 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
297 for (i
= 0; i
< len
; i
++)
298 if (rate
== rates
[i
])
304 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
306 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
308 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
309 intel_dp
->num_source_rates
,
310 intel_dp
->sink_rates
,
311 intel_dp
->num_sink_rates
,
312 intel_dp
->common_rates
);
314 /* Paranoia, there should always be something in common. */
315 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
316 intel_dp
->common_rates
[0] = default_rates
[0];
317 intel_dp
->num_common_rates
= 1;
321 /* get length of common rates potentially limited by max_rate */
322 static int intel_dp_common_len_rate_limit(struct intel_dp
*intel_dp
,
325 const int *common_rates
= intel_dp
->common_rates
;
326 int i
, common_len
= intel_dp
->num_common_rates
;
328 /* Limit results by potentially reduced max rate */
329 for (i
= 0; i
< common_len
; i
++) {
330 if (common_rates
[common_len
- i
- 1] <= max_rate
)
331 return common_len
- i
;
337 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
, int link_rate
,
341 * FIXME: we need to synchronize the current link parameters with
342 * hardware readout. Currently fast link training doesn't work on
345 if (link_rate
== 0 ||
346 link_rate
> intel_dp
->max_link_rate
)
349 if (lane_count
== 0 ||
350 lane_count
> intel_dp_max_lane_count(intel_dp
))
356 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
357 int link_rate
, uint8_t lane_count
)
361 index
= intel_dp_rate_index(intel_dp
->common_rates
,
362 intel_dp
->num_common_rates
,
365 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
366 intel_dp
->max_link_lane_count
= lane_count
;
367 } else if (lane_count
> 1) {
368 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
369 intel_dp
->max_link_lane_count
= lane_count
>> 1;
371 DRM_ERROR("Link Training Unsuccessful\n");
378 static enum drm_mode_status
379 intel_dp_mode_valid(struct drm_connector
*connector
,
380 struct drm_display_mode
*mode
)
382 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
383 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
384 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
385 int target_clock
= mode
->clock
;
386 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
389 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
391 if (is_edp(intel_dp
) && fixed_mode
) {
392 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
395 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
398 target_clock
= fixed_mode
->clock
;
401 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
402 max_lanes
= intel_dp_max_lane_count(intel_dp
);
404 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
405 mode_rate
= intel_dp_link_required(target_clock
, 18);
407 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
408 return MODE_CLOCK_HIGH
;
410 if (mode
->clock
< 10000)
411 return MODE_CLOCK_LOW
;
413 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
414 return MODE_H_ILLEGAL
;
419 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
426 for (i
= 0; i
< src_bytes
; i
++)
427 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
431 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
436 for (i
= 0; i
< dst_bytes
; i
++)
437 dst
[i
] = src
>> ((3-i
) * 8);
441 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
442 struct intel_dp
*intel_dp
);
444 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
445 struct intel_dp
*intel_dp
,
446 bool force_disable_vdd
);
448 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
450 static void pps_lock(struct intel_dp
*intel_dp
)
452 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
453 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
454 struct drm_device
*dev
= encoder
->base
.dev
;
455 struct drm_i915_private
*dev_priv
= to_i915(dev
);
458 * See vlv_power_sequencer_reset() why we need
459 * a power domain reference here.
461 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
463 mutex_lock(&dev_priv
->pps_mutex
);
466 static void pps_unlock(struct intel_dp
*intel_dp
)
468 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
469 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
470 struct drm_device
*dev
= encoder
->base
.dev
;
471 struct drm_i915_private
*dev_priv
= to_i915(dev
);
473 mutex_unlock(&dev_priv
->pps_mutex
);
475 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
479 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
481 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
482 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
483 enum pipe pipe
= intel_dp
->pps_pipe
;
484 bool pll_enabled
, release_cl_override
= false;
485 enum dpio_phy phy
= DPIO_PHY(pipe
);
486 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
489 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
490 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
491 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
494 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
495 pipe_name(pipe
), port_name(intel_dig_port
->port
));
497 /* Preserve the BIOS-computed detected bit. This is
498 * supposed to be read-only.
500 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
501 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
502 DP
|= DP_PORT_WIDTH(1);
503 DP
|= DP_LINK_TRAIN_PAT_1
;
505 if (IS_CHERRYVIEW(dev_priv
))
506 DP
|= DP_PIPE_SELECT_CHV(pipe
);
507 else if (pipe
== PIPE_B
)
508 DP
|= DP_PIPEB_SELECT
;
510 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
513 * The DPLL for the pipe must be enabled for this to work.
514 * So enable temporarily it if it's not already enabled.
517 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
518 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
520 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
521 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
522 DRM_ERROR("Failed to force on pll for pipe %c!\n",
529 * Similar magic as in intel_dp_enable_port().
530 * We _must_ do this port enable + disable trick
531 * to make this power seqeuencer lock onto the port.
532 * Otherwise even VDD force bit won't work.
534 I915_WRITE(intel_dp
->output_reg
, DP
);
535 POSTING_READ(intel_dp
->output_reg
);
537 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
538 POSTING_READ(intel_dp
->output_reg
);
540 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
541 POSTING_READ(intel_dp
->output_reg
);
544 vlv_force_pll_off(dev_priv
, pipe
);
546 if (release_cl_override
)
547 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
551 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
553 struct intel_encoder
*encoder
;
554 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
557 * We don't have power sequencer currently.
558 * Pick one that's not used by other ports.
560 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
561 struct intel_dp
*intel_dp
;
563 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
564 encoder
->type
!= INTEL_OUTPUT_EDP
)
567 intel_dp
= enc_to_intel_dp(&encoder
->base
);
569 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
570 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
571 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
573 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
574 pipes
&= ~(1 << intel_dp
->pps_pipe
);
576 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
578 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
579 pipes
&= ~(1 << intel_dp
->active_pipe
);
586 return ffs(pipes
) - 1;
590 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
592 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
593 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
594 struct drm_i915_private
*dev_priv
= to_i915(dev
);
597 lockdep_assert_held(&dev_priv
->pps_mutex
);
599 /* We should never land here with regular DP ports */
600 WARN_ON(!is_edp(intel_dp
));
602 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
603 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
605 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
606 return intel_dp
->pps_pipe
;
608 pipe
= vlv_find_free_pps(dev_priv
);
611 * Didn't find one. This should not happen since there
612 * are two power sequencers and up to two eDP ports.
614 if (WARN_ON(pipe
== INVALID_PIPE
))
617 vlv_steal_power_sequencer(dev
, pipe
);
618 intel_dp
->pps_pipe
= pipe
;
620 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
621 pipe_name(intel_dp
->pps_pipe
),
622 port_name(intel_dig_port
->port
));
624 /* init power sequencer on this pipe and port */
625 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
626 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
629 * Even vdd force doesn't work until we've made
630 * the power sequencer lock in on the port.
632 vlv_power_sequencer_kick(intel_dp
);
634 return intel_dp
->pps_pipe
;
638 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
640 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
641 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
642 struct drm_i915_private
*dev_priv
= to_i915(dev
);
644 lockdep_assert_held(&dev_priv
->pps_mutex
);
646 /* We should never land here with regular DP ports */
647 WARN_ON(!is_edp(intel_dp
));
650 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
651 * mapping needs to be retrieved from VBT, for now just hard-code to
652 * use instance #0 always.
654 if (!intel_dp
->pps_reset
)
657 intel_dp
->pps_reset
= false;
660 * Only the HW needs to be reprogrammed, the SW state is fixed and
661 * has been setup during connector init.
663 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
668 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
671 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
674 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
677 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
680 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
683 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
690 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
692 vlv_pipe_check pipe_check
)
696 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
697 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
698 PANEL_PORT_SELECT_MASK
;
700 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
703 if (!pipe_check(dev_priv
, pipe
))
713 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
715 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
716 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
717 struct drm_i915_private
*dev_priv
= to_i915(dev
);
718 enum port port
= intel_dig_port
->port
;
720 lockdep_assert_held(&dev_priv
->pps_mutex
);
722 /* try to find a pipe with this port selected */
723 /* first pick one where the panel is on */
724 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
726 /* didn't find one? pick one where vdd is on */
727 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
728 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
729 vlv_pipe_has_vdd_on
);
730 /* didn't find one? pick one with just the correct port */
731 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
732 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
735 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
736 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
737 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
742 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
743 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
745 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
746 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
749 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
751 struct drm_device
*dev
= &dev_priv
->drm
;
752 struct intel_encoder
*encoder
;
754 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
755 !IS_GEN9_LP(dev_priv
)))
759 * We can't grab pps_mutex here due to deadlock with power_domain
760 * mutex when power_domain functions are called while holding pps_mutex.
761 * That also means that in order to use pps_pipe the code needs to
762 * hold both a power domain reference and pps_mutex, and the power domain
763 * reference get/put must be done while _not_ holding pps_mutex.
764 * pps_{lock,unlock}() do these steps in the correct order, so one
765 * should use them always.
768 for_each_intel_encoder(dev
, encoder
) {
769 struct intel_dp
*intel_dp
;
771 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
772 encoder
->type
!= INTEL_OUTPUT_EDP
)
775 intel_dp
= enc_to_intel_dp(&encoder
->base
);
777 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
779 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
782 if (IS_GEN9_LP(dev_priv
))
783 intel_dp
->pps_reset
= true;
785 intel_dp
->pps_pipe
= INVALID_PIPE
;
789 struct pps_registers
{
797 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
798 struct intel_dp
*intel_dp
,
799 struct pps_registers
*regs
)
803 memset(regs
, 0, sizeof(*regs
));
805 if (IS_GEN9_LP(dev_priv
))
806 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
807 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
808 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
810 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
811 regs
->pp_stat
= PP_STATUS(pps_idx
);
812 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
813 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
814 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
))
815 regs
->pp_div
= PP_DIVISOR(pps_idx
);
819 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
821 struct pps_registers regs
;
823 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
830 _pp_stat_reg(struct intel_dp
*intel_dp
)
832 struct pps_registers regs
;
834 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
840 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
841 This function only applicable when panel PM state is not to be tracked */
842 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
845 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
847 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
848 struct drm_i915_private
*dev_priv
= to_i915(dev
);
850 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
855 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
856 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
857 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
860 pp_ctrl_reg
= PP_CONTROL(pipe
);
861 pp_div_reg
= PP_DIVISOR(pipe
);
862 pp_div
= I915_READ(pp_div_reg
);
863 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
865 /* 0x1F write to PP_DIV_REG sets max cycle delay */
866 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
867 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
868 msleep(intel_dp
->panel_power_cycle_delay
);
871 pps_unlock(intel_dp
);
876 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
878 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
879 struct drm_i915_private
*dev_priv
= to_i915(dev
);
881 lockdep_assert_held(&dev_priv
->pps_mutex
);
883 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
884 intel_dp
->pps_pipe
== INVALID_PIPE
)
887 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
890 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
892 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
893 struct drm_i915_private
*dev_priv
= to_i915(dev
);
895 lockdep_assert_held(&dev_priv
->pps_mutex
);
897 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
898 intel_dp
->pps_pipe
== INVALID_PIPE
)
901 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
905 intel_dp_check_edp(struct intel_dp
*intel_dp
)
907 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
908 struct drm_i915_private
*dev_priv
= to_i915(dev
);
910 if (!is_edp(intel_dp
))
913 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
914 WARN(1, "eDP powered off while attempting aux channel communication.\n");
915 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
916 I915_READ(_pp_stat_reg(intel_dp
)),
917 I915_READ(_pp_ctrl_reg(intel_dp
)));
922 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
924 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
925 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
926 struct drm_i915_private
*dev_priv
= to_i915(dev
);
927 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
931 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
933 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
934 msecs_to_jiffies_timeout(10));
936 done
= wait_for(C
, 10) == 0;
938 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
945 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
947 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
948 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
954 * The clock divider is based off the hrawclk, and would like to run at
955 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
957 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
960 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
962 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
963 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
969 * The clock divider is based off the cdclk or PCH rawclk, and would
970 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
971 * divide by 2000 and use that
973 if (intel_dig_port
->port
== PORT_A
)
974 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
976 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
979 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
981 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
982 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
984 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
985 /* Workaround for non-ULT HSW */
993 return ilk_get_aux_clock_divider(intel_dp
, index
);
996 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
999 * SKL doesn't need us to program the AUX clock divider (Hardware will
1000 * derive the clock from CDCLK automatically). We still implement the
1001 * get_aux_clock_divider vfunc to plug-in into the existing code.
1003 return index
? 0 : 1;
1006 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1009 uint32_t aux_clock_divider
)
1011 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1012 struct drm_i915_private
*dev_priv
=
1013 to_i915(intel_dig_port
->base
.base
.dev
);
1014 uint32_t precharge
, timeout
;
1016 if (IS_GEN6(dev_priv
))
1021 if (IS_BROADWELL(dev_priv
) && intel_dig_port
->port
== PORT_A
)
1022 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1024 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1026 return DP_AUX_CH_CTL_SEND_BUSY
|
1027 DP_AUX_CH_CTL_DONE
|
1028 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1029 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1031 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1032 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1033 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1034 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1037 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1042 return DP_AUX_CH_CTL_SEND_BUSY
|
1043 DP_AUX_CH_CTL_DONE
|
1044 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1045 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1046 DP_AUX_CH_CTL_TIME_OUT_1600us
|
1047 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1048 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1049 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1050 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1054 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
1055 const uint8_t *send
, int send_bytes
,
1056 uint8_t *recv
, int recv_size
)
1058 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1059 struct drm_i915_private
*dev_priv
=
1060 to_i915(intel_dig_port
->base
.base
.dev
);
1061 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
1062 uint32_t aux_clock_divider
;
1063 int i
, ret
, recv_bytes
;
1066 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1072 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1073 * In such cases we want to leave VDD enabled and it's up to upper layers
1074 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1077 vdd
= edp_panel_vdd_on(intel_dp
);
1079 /* dp aux is extremely sensitive to irq latency, hence request the
1080 * lowest possible wakeup latency and so prevent the cpu from going into
1081 * deep sleep states.
1083 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1085 intel_dp_check_edp(intel_dp
);
1087 /* Try to wait for any previous AUX channel activity */
1088 for (try = 0; try < 3; try++) {
1089 status
= I915_READ_NOTRACE(ch_ctl
);
1090 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1096 static u32 last_status
= -1;
1097 const u32 status
= I915_READ(ch_ctl
);
1099 if (status
!= last_status
) {
1100 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1102 last_status
= status
;
1109 /* Only 5 data registers! */
1110 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1115 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1116 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1121 /* Must try at least 3 times according to DP spec */
1122 for (try = 0; try < 5; try++) {
1123 /* Load the send data into the aux channel data registers */
1124 for (i
= 0; i
< send_bytes
; i
+= 4)
1125 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
1126 intel_dp_pack_aux(send
+ i
,
1129 /* Send the command and wait for it to complete */
1130 I915_WRITE(ch_ctl
, send_ctl
);
1132 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1134 /* Clear done status and any errors */
1137 DP_AUX_CH_CTL_DONE
|
1138 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1139 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1141 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1144 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1145 * 400us delay required for errors and timeouts
1146 * Timeout errors from the HW already meet this
1147 * requirement so skip to next iteration
1149 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1150 usleep_range(400, 500);
1153 if (status
& DP_AUX_CH_CTL_DONE
)
1158 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1159 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1165 /* Check for timeout or receive error.
1166 * Timeouts occur when the sink is not connected
1168 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1169 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1174 /* Timeouts occur when the device isn't connected, so they're
1175 * "normal" -- don't fill the kernel log with these */
1176 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1177 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1182 /* Unload any bytes sent back from the other side */
1183 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1184 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1187 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1188 * We have no idea of what happened so we return -EBUSY so
1189 * drm layer takes care for the necessary retries.
1191 if (recv_bytes
== 0 || recv_bytes
> 20) {
1192 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1195 * FIXME: This patch was created on top of a series that
1196 * organize the retries at drm level. There EBUSY should
1197 * also take care for 1ms wait before retrying.
1198 * That aux retries re-org is still needed and after that is
1199 * merged we remove this sleep from here.
1201 usleep_range(1000, 1500);
1206 if (recv_bytes
> recv_size
)
1207 recv_bytes
= recv_size
;
1209 for (i
= 0; i
< recv_bytes
; i
+= 4)
1210 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1211 recv
+ i
, recv_bytes
- i
);
1215 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1218 edp_panel_vdd_off(intel_dp
, false);
1220 pps_unlock(intel_dp
);
1225 #define BARE_ADDRESS_SIZE 3
1226 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1228 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1230 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1231 uint8_t txbuf
[20], rxbuf
[20];
1232 size_t txsize
, rxsize
;
1235 txbuf
[0] = (msg
->request
<< 4) |
1236 ((msg
->address
>> 16) & 0xf);
1237 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1238 txbuf
[2] = msg
->address
& 0xff;
1239 txbuf
[3] = msg
->size
- 1;
1241 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1242 case DP_AUX_NATIVE_WRITE
:
1243 case DP_AUX_I2C_WRITE
:
1244 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1245 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1246 rxsize
= 2; /* 0 or 1 data bytes */
1248 if (WARN_ON(txsize
> 20))
1251 WARN_ON(!msg
->buffer
!= !msg
->size
);
1254 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1256 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1258 msg
->reply
= rxbuf
[0] >> 4;
1261 /* Number of bytes written in a short write. */
1262 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1264 /* Return payload size. */
1270 case DP_AUX_NATIVE_READ
:
1271 case DP_AUX_I2C_READ
:
1272 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1273 rxsize
= msg
->size
+ 1;
1275 if (WARN_ON(rxsize
> 20))
1278 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1280 msg
->reply
= rxbuf
[0] >> 4;
1282 * Assume happy day, and copy the data. The caller is
1283 * expected to check msg->reply before touching it.
1285 * Return payload size.
1288 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1300 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1303 const struct ddi_vbt_port_info
*info
=
1304 &dev_priv
->vbt
.ddi_port_info
[port
];
1307 if (!info
->alternate_aux_channel
) {
1308 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1309 port_name(port
), port_name(port
));
1313 switch (info
->alternate_aux_channel
) {
1327 MISSING_CASE(info
->alternate_aux_channel
);
1332 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1333 port_name(aux_port
), port_name(port
));
1338 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1345 return DP_AUX_CH_CTL(port
);
1348 return DP_AUX_CH_CTL(PORT_B
);
1352 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1353 enum port port
, int index
)
1359 return DP_AUX_CH_DATA(port
, index
);
1362 return DP_AUX_CH_DATA(PORT_B
, index
);
1366 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1371 return DP_AUX_CH_CTL(port
);
1375 return PCH_DP_AUX_CH_CTL(port
);
1378 return DP_AUX_CH_CTL(PORT_A
);
1382 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1383 enum port port
, int index
)
1387 return DP_AUX_CH_DATA(port
, index
);
1391 return PCH_DP_AUX_CH_DATA(port
, index
);
1394 return DP_AUX_CH_DATA(PORT_A
, index
);
1398 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1406 return DP_AUX_CH_CTL(port
);
1409 return DP_AUX_CH_CTL(PORT_A
);
1413 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1414 enum port port
, int index
)
1421 return DP_AUX_CH_DATA(port
, index
);
1424 return DP_AUX_CH_DATA(PORT_A
, index
);
1428 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1431 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1432 return skl_aux_ctl_reg(dev_priv
, port
);
1433 else if (HAS_PCH_SPLIT(dev_priv
))
1434 return ilk_aux_ctl_reg(dev_priv
, port
);
1436 return g4x_aux_ctl_reg(dev_priv
, port
);
1439 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1440 enum port port
, int index
)
1442 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1443 return skl_aux_data_reg(dev_priv
, port
, index
);
1444 else if (HAS_PCH_SPLIT(dev_priv
))
1445 return ilk_aux_data_reg(dev_priv
, port
, index
);
1447 return g4x_aux_data_reg(dev_priv
, port
, index
);
1450 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1452 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1453 enum port port
= intel_aux_port(dev_priv
,
1454 dp_to_dig_port(intel_dp
)->port
);
1457 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1458 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1459 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1463 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1465 kfree(intel_dp
->aux
.name
);
1469 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1471 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1472 enum port port
= intel_dig_port
->port
;
1474 intel_aux_reg_init(intel_dp
);
1475 drm_dp_aux_init(&intel_dp
->aux
);
1477 /* Failure to allocate our preferred name is not critical */
1478 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1479 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1482 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1484 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1485 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1487 if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
1488 IS_BROADWELL(dev_priv
) || (INTEL_GEN(dev_priv
) >= 9))
1495 intel_dp_set_clock(struct intel_encoder
*encoder
,
1496 struct intel_crtc_state
*pipe_config
)
1498 struct drm_device
*dev
= encoder
->base
.dev
;
1499 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1500 const struct dp_link_dpll
*divisor
= NULL
;
1503 if (IS_G4X(dev_priv
)) {
1504 divisor
= gen4_dpll
;
1505 count
= ARRAY_SIZE(gen4_dpll
);
1506 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1508 count
= ARRAY_SIZE(pch_dpll
);
1509 } else if (IS_CHERRYVIEW(dev_priv
)) {
1511 count
= ARRAY_SIZE(chv_dpll
);
1512 } else if (IS_VALLEYVIEW(dev_priv
)) {
1514 count
= ARRAY_SIZE(vlv_dpll
);
1517 if (divisor
&& count
) {
1518 for (i
= 0; i
< count
; i
++) {
1519 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1520 pipe_config
->dpll
= divisor
[i
].dpll
;
1521 pipe_config
->clock_set
= true;
1528 static void snprintf_int_array(char *str
, size_t len
,
1529 const int *array
, int nelem
)
1535 for (i
= 0; i
< nelem
; i
++) {
1536 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1544 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1546 char str
[128]; /* FIXME: too big for stack? */
1548 if ((drm_debug
& DRM_UT_KMS
) == 0)
1551 snprintf_int_array(str
, sizeof(str
),
1552 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1553 DRM_DEBUG_KMS("source rates: %s\n", str
);
1555 snprintf_int_array(str
, sizeof(str
),
1556 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1557 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1559 snprintf_int_array(str
, sizeof(str
),
1560 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1561 DRM_DEBUG_KMS("common rates: %s\n", str
);
1565 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1569 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1570 if (WARN_ON(len
<= 0))
1573 return intel_dp
->common_rates
[len
- 1];
1576 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1578 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1579 intel_dp
->num_sink_rates
, rate
);
1587 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1588 uint8_t *link_bw
, uint8_t *rate_select
)
1590 /* eDP 1.4 rate select method. */
1591 if (intel_dp
->use_rate_select
) {
1594 intel_dp_rate_select(intel_dp
, port_clock
);
1596 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1601 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1602 struct intel_crtc_state
*pipe_config
)
1606 bpp
= pipe_config
->pipe_bpp
;
1607 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1610 bpp
= min(bpp
, 3*bpc
);
1612 /* For DP Compliance we override the computed bpp for the pipe */
1613 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1614 pipe_config
->pipe_bpp
= 3*intel_dp
->compliance
.test_data
.bpc
;
1615 pipe_config
->dither_force_disable
= pipe_config
->pipe_bpp
== 6*3;
1616 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1617 pipe_config
->pipe_bpp
);
1622 static bool intel_edp_compare_alt_mode(struct drm_display_mode
*m1
,
1623 struct drm_display_mode
*m2
)
1628 bres
= (m1
->hdisplay
== m2
->hdisplay
&&
1629 m1
->hsync_start
== m2
->hsync_start
&&
1630 m1
->hsync_end
== m2
->hsync_end
&&
1631 m1
->htotal
== m2
->htotal
&&
1632 m1
->vdisplay
== m2
->vdisplay
&&
1633 m1
->vsync_start
== m2
->vsync_start
&&
1634 m1
->vsync_end
== m2
->vsync_end
&&
1635 m1
->vtotal
== m2
->vtotal
);
1640 intel_dp_compute_config(struct intel_encoder
*encoder
,
1641 struct intel_crtc_state
*pipe_config
,
1642 struct drm_connector_state
*conn_state
)
1644 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1645 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1646 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1647 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1648 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1649 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1650 struct intel_digital_connector_state
*intel_conn_state
=
1651 to_intel_digital_connector_state(conn_state
);
1652 int lane_count
, clock
;
1653 int min_lane_count
= 1;
1654 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1655 /* Conveniently, the link BW constants become indices with a shift...*/
1659 int link_avail
, link_clock
;
1661 uint8_t link_bw
, rate_select
;
1662 bool reduce_m_n
= drm_dp_has_quirk(&intel_dp
->desc
,
1663 DP_DPCD_QUIRK_LIMITED_M_N
);
1665 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1666 intel_dp
->max_link_rate
);
1668 /* No common link rates between source and sink */
1669 WARN_ON(common_len
<= 0);
1671 max_clock
= common_len
- 1;
1673 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1674 pipe_config
->has_pch_encoder
= true;
1676 pipe_config
->has_drrs
= false;
1678 pipe_config
->has_audio
= false;
1679 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1680 pipe_config
->has_audio
= intel_dp
->has_audio
;
1682 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1684 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1685 struct drm_display_mode
*panel_mode
=
1686 intel_connector
->panel
.alt_fixed_mode
;
1687 struct drm_display_mode
*req_mode
= &pipe_config
->base
.mode
;
1689 if (!intel_edp_compare_alt_mode(req_mode
, panel_mode
))
1690 panel_mode
= intel_connector
->panel
.fixed_mode
;
1692 drm_mode_debug_printmodeline(panel_mode
);
1694 intel_fixed_panel_mode(panel_mode
, adjusted_mode
);
1696 if (INTEL_GEN(dev_priv
) >= 9) {
1698 ret
= skl_update_scaler_crtc(pipe_config
);
1703 if (HAS_GMCH_DISPLAY(dev_priv
))
1704 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1705 conn_state
->scaling_mode
);
1707 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1708 conn_state
->scaling_mode
);
1711 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1714 /* Use values requested by Compliance Test Request */
1715 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1718 /* Validate the compliance test data since max values
1719 * might have changed due to link train fallback.
1721 if (intel_dp_link_params_valid(intel_dp
, intel_dp
->compliance
.test_link_rate
,
1722 intel_dp
->compliance
.test_lane_count
)) {
1723 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1724 intel_dp
->num_common_rates
,
1725 intel_dp
->compliance
.test_link_rate
);
1727 min_clock
= max_clock
= index
;
1728 min_lane_count
= max_lane_count
= intel_dp
->compliance
.test_lane_count
;
1731 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1732 "max bw %d pixel clock %iKHz\n",
1733 max_lane_count
, intel_dp
->common_rates
[max_clock
],
1734 adjusted_mode
->crtc_clock
);
1736 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1737 * bpc in between. */
1738 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1739 if (is_edp(intel_dp
)) {
1741 /* Get bpp from vbt only for panels that dont have bpp in edid */
1742 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1743 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1744 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1745 dev_priv
->vbt
.edp
.bpp
);
1746 bpp
= dev_priv
->vbt
.edp
.bpp
;
1750 * Use the maximum clock and number of lanes the eDP panel
1751 * advertizes being capable of. The panels are generally
1752 * designed to support only a single clock and lane
1753 * configuration, and typically these values correspond to the
1754 * native resolution of the panel.
1756 min_lane_count
= max_lane_count
;
1757 min_clock
= max_clock
;
1760 for (; bpp
>= 6*3; bpp
-= 2*3) {
1761 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1764 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1765 for (lane_count
= min_lane_count
;
1766 lane_count
<= max_lane_count
;
1769 link_clock
= intel_dp
->common_rates
[clock
];
1770 link_avail
= intel_dp_max_data_rate(link_clock
,
1773 if (mode_rate
<= link_avail
) {
1783 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1786 * CEA-861-E - 5.1 Default Encoding Parameters
1787 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1789 pipe_config
->limited_color_range
=
1791 drm_default_rgb_quant_range(adjusted_mode
) ==
1792 HDMI_QUANTIZATION_RANGE_LIMITED
;
1794 pipe_config
->limited_color_range
=
1795 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1798 pipe_config
->lane_count
= lane_count
;
1800 pipe_config
->pipe_bpp
= bpp
;
1801 pipe_config
->port_clock
= intel_dp
->common_rates
[clock
];
1803 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1804 &link_bw
, &rate_select
);
1806 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1807 link_bw
, rate_select
, pipe_config
->lane_count
,
1808 pipe_config
->port_clock
, bpp
);
1809 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1810 mode_rate
, link_avail
);
1812 intel_link_compute_m_n(bpp
, lane_count
,
1813 adjusted_mode
->crtc_clock
,
1814 pipe_config
->port_clock
,
1815 &pipe_config
->dp_m_n
,
1818 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1819 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1820 pipe_config
->has_drrs
= true;
1821 intel_link_compute_m_n(bpp
, lane_count
,
1822 intel_connector
->panel
.downclock_mode
->clock
,
1823 pipe_config
->port_clock
,
1824 &pipe_config
->dp_m2_n2
,
1829 * DPLL0 VCO may need to be adjusted to get the correct
1830 * clock for eDP. This will affect cdclk as well.
1832 if (is_edp(intel_dp
) && IS_GEN9_BC(dev_priv
)) {
1835 switch (pipe_config
->port_clock
/ 2) {
1845 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk
.logical
.vco
= vco
;
1848 if (!HAS_DDI(dev_priv
))
1849 intel_dp_set_clock(encoder
, pipe_config
);
1854 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1855 int link_rate
, uint8_t lane_count
,
1858 intel_dp
->link_rate
= link_rate
;
1859 intel_dp
->lane_count
= lane_count
;
1860 intel_dp
->link_mst
= link_mst
;
1863 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1864 struct intel_crtc_state
*pipe_config
)
1866 struct drm_device
*dev
= encoder
->base
.dev
;
1867 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1868 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1869 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1870 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1871 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1873 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1874 pipe_config
->lane_count
,
1875 intel_crtc_has_type(pipe_config
,
1876 INTEL_OUTPUT_DP_MST
));
1879 * There are four kinds of DP registers:
1886 * IBX PCH and CPU are the same for almost everything,
1887 * except that the CPU DP PLL is configured in this
1890 * CPT PCH is quite different, having many bits moved
1891 * to the TRANS_DP_CTL register instead. That
1892 * configuration happens (oddly) in ironlake_pch_enable
1895 /* Preserve the BIOS-computed detected bit. This is
1896 * supposed to be read-only.
1898 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1900 /* Handle DP bits in common between all three register formats */
1901 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1902 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1904 /* Split out the IBX/CPU vs CPT settings */
1906 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1907 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1908 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1909 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1910 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1911 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1913 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1914 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1916 intel_dp
->DP
|= crtc
->pipe
<< 29;
1917 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1920 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1922 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1923 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1924 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1926 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1927 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1929 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
1930 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1932 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1933 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1934 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1935 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1936 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1938 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1939 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1941 if (IS_CHERRYVIEW(dev_priv
))
1942 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1943 else if (crtc
->pipe
== PIPE_B
)
1944 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1948 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1949 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1951 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1952 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1954 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1955 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1957 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1958 struct intel_dp
*intel_dp
);
1960 static void wait_panel_status(struct intel_dp
*intel_dp
,
1964 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1965 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1966 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1968 lockdep_assert_held(&dev_priv
->pps_mutex
);
1970 intel_pps_verify_state(dev_priv
, intel_dp
);
1972 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1973 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1975 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1977 I915_READ(pp_stat_reg
),
1978 I915_READ(pp_ctrl_reg
));
1980 if (intel_wait_for_register(dev_priv
,
1981 pp_stat_reg
, mask
, value
,
1983 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1984 I915_READ(pp_stat_reg
),
1985 I915_READ(pp_ctrl_reg
));
1987 DRM_DEBUG_KMS("Wait complete\n");
1990 static void wait_panel_on(struct intel_dp
*intel_dp
)
1992 DRM_DEBUG_KMS("Wait for panel power on\n");
1993 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1996 static void wait_panel_off(struct intel_dp
*intel_dp
)
1998 DRM_DEBUG_KMS("Wait for panel power off time\n");
1999 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
2002 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
2004 ktime_t panel_power_on_time
;
2005 s64 panel_power_off_duration
;
2007 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2009 /* take the difference of currrent time and panel power off time
2010 * and then make panel wait for t11_t12 if needed. */
2011 panel_power_on_time
= ktime_get_boottime();
2012 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
2014 /* When we disable the VDD override bit last we have to do the manual
2016 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
2017 wait_remaining_ms_from_jiffies(jiffies
,
2018 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
2020 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2023 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2025 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2026 intel_dp
->backlight_on_delay
);
2029 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2031 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2032 intel_dp
->backlight_off_delay
);
2035 /* Read the current pp_control value, unlocking the register if it
2039 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2041 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2042 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2045 lockdep_assert_held(&dev_priv
->pps_mutex
);
2047 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2048 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2049 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2050 control
&= ~PANEL_UNLOCK_MASK
;
2051 control
|= PANEL_UNLOCK_REGS
;
2057 * Must be paired with edp_panel_vdd_off().
2058 * Must hold pps_mutex around the whole on/off sequence.
2059 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2061 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2063 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2064 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2065 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2067 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2068 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2070 lockdep_assert_held(&dev_priv
->pps_mutex
);
2072 if (!is_edp(intel_dp
))
2075 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2076 intel_dp
->want_panel_vdd
= true;
2078 if (edp_have_panel_vdd(intel_dp
))
2079 return need_to_disable
;
2081 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2083 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2084 port_name(intel_dig_port
->port
));
2086 if (!edp_have_panel_power(intel_dp
))
2087 wait_panel_power_cycle(intel_dp
);
2089 pp
= ironlake_get_pp_control(intel_dp
);
2090 pp
|= EDP_FORCE_VDD
;
2092 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2093 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2095 I915_WRITE(pp_ctrl_reg
, pp
);
2096 POSTING_READ(pp_ctrl_reg
);
2097 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2098 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2100 * If the panel wasn't on, delay before accessing aux channel
2102 if (!edp_have_panel_power(intel_dp
)) {
2103 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2104 port_name(intel_dig_port
->port
));
2105 msleep(intel_dp
->panel_power_up_delay
);
2108 return need_to_disable
;
2112 * Must be paired with intel_edp_panel_vdd_off() or
2113 * intel_edp_panel_off().
2114 * Nested calls to these functions are not allowed since
2115 * we drop the lock. Caller must use some higher level
2116 * locking to prevent nested calls from other threads.
2118 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2122 if (!is_edp(intel_dp
))
2126 vdd
= edp_panel_vdd_on(intel_dp
);
2127 pps_unlock(intel_dp
);
2129 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2130 port_name(dp_to_dig_port(intel_dp
)->port
));
2133 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2135 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2136 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2137 struct intel_digital_port
*intel_dig_port
=
2138 dp_to_dig_port(intel_dp
);
2140 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2142 lockdep_assert_held(&dev_priv
->pps_mutex
);
2144 WARN_ON(intel_dp
->want_panel_vdd
);
2146 if (!edp_have_panel_vdd(intel_dp
))
2149 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2150 port_name(intel_dig_port
->port
));
2152 pp
= ironlake_get_pp_control(intel_dp
);
2153 pp
&= ~EDP_FORCE_VDD
;
2155 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2156 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2158 I915_WRITE(pp_ctrl_reg
, pp
);
2159 POSTING_READ(pp_ctrl_reg
);
2161 /* Make sure sequencer is idle before allowing subsequent activity */
2162 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2163 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2165 if ((pp
& PANEL_POWER_ON
) == 0)
2166 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2168 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2171 static void edp_panel_vdd_work(struct work_struct
*__work
)
2173 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2174 struct intel_dp
, panel_vdd_work
);
2177 if (!intel_dp
->want_panel_vdd
)
2178 edp_panel_vdd_off_sync(intel_dp
);
2179 pps_unlock(intel_dp
);
2182 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2184 unsigned long delay
;
2187 * Queue the timer to fire a long time from now (relative to the power
2188 * down delay) to keep the panel power up across a sequence of
2191 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2192 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2196 * Must be paired with edp_panel_vdd_on().
2197 * Must hold pps_mutex around the whole on/off sequence.
2198 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2200 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2202 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2204 lockdep_assert_held(&dev_priv
->pps_mutex
);
2206 if (!is_edp(intel_dp
))
2209 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2210 port_name(dp_to_dig_port(intel_dp
)->port
));
2212 intel_dp
->want_panel_vdd
= false;
2215 edp_panel_vdd_off_sync(intel_dp
);
2217 edp_panel_vdd_schedule_off(intel_dp
);
2220 static void edp_panel_on(struct intel_dp
*intel_dp
)
2222 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2223 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2225 i915_reg_t pp_ctrl_reg
;
2227 lockdep_assert_held(&dev_priv
->pps_mutex
);
2229 if (!is_edp(intel_dp
))
2232 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2233 port_name(dp_to_dig_port(intel_dp
)->port
));
2235 if (WARN(edp_have_panel_power(intel_dp
),
2236 "eDP port %c panel power already on\n",
2237 port_name(dp_to_dig_port(intel_dp
)->port
)))
2240 wait_panel_power_cycle(intel_dp
);
2242 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2243 pp
= ironlake_get_pp_control(intel_dp
);
2244 if (IS_GEN5(dev_priv
)) {
2245 /* ILK workaround: disable reset around power sequence */
2246 pp
&= ~PANEL_POWER_RESET
;
2247 I915_WRITE(pp_ctrl_reg
, pp
);
2248 POSTING_READ(pp_ctrl_reg
);
2251 pp
|= PANEL_POWER_ON
;
2252 if (!IS_GEN5(dev_priv
))
2253 pp
|= PANEL_POWER_RESET
;
2255 I915_WRITE(pp_ctrl_reg
, pp
);
2256 POSTING_READ(pp_ctrl_reg
);
2258 wait_panel_on(intel_dp
);
2259 intel_dp
->last_power_on
= jiffies
;
2261 if (IS_GEN5(dev_priv
)) {
2262 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2263 I915_WRITE(pp_ctrl_reg
, pp
);
2264 POSTING_READ(pp_ctrl_reg
);
2268 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2270 if (!is_edp(intel_dp
))
2274 edp_panel_on(intel_dp
);
2275 pps_unlock(intel_dp
);
2279 static void edp_panel_off(struct intel_dp
*intel_dp
)
2281 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2282 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2284 i915_reg_t pp_ctrl_reg
;
2286 lockdep_assert_held(&dev_priv
->pps_mutex
);
2288 if (!is_edp(intel_dp
))
2291 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2292 port_name(dp_to_dig_port(intel_dp
)->port
));
2294 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2295 port_name(dp_to_dig_port(intel_dp
)->port
));
2297 pp
= ironlake_get_pp_control(intel_dp
);
2298 /* We need to switch off panel power _and_ force vdd, for otherwise some
2299 * panels get very unhappy and cease to work. */
2300 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2303 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2305 intel_dp
->want_panel_vdd
= false;
2307 I915_WRITE(pp_ctrl_reg
, pp
);
2308 POSTING_READ(pp_ctrl_reg
);
2310 wait_panel_off(intel_dp
);
2311 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2313 /* We got a reference when we enabled the VDD. */
2314 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2317 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2319 if (!is_edp(intel_dp
))
2323 edp_panel_off(intel_dp
);
2324 pps_unlock(intel_dp
);
2327 /* Enable backlight in the panel power control. */
2328 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2330 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2331 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2332 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2334 i915_reg_t pp_ctrl_reg
;
2337 * If we enable the backlight right away following a panel power
2338 * on, we may see slight flicker as the panel syncs with the eDP
2339 * link. So delay a bit to make sure the image is solid before
2340 * allowing it to appear.
2342 wait_backlight_on(intel_dp
);
2346 pp
= ironlake_get_pp_control(intel_dp
);
2347 pp
|= EDP_BLC_ENABLE
;
2349 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2351 I915_WRITE(pp_ctrl_reg
, pp
);
2352 POSTING_READ(pp_ctrl_reg
);
2354 pps_unlock(intel_dp
);
2357 /* Enable backlight PWM and backlight PP control. */
2358 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2359 const struct drm_connector_state
*conn_state
)
2361 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2363 if (!is_edp(intel_dp
))
2366 DRM_DEBUG_KMS("\n");
2368 intel_panel_enable_backlight(crtc_state
, conn_state
);
2369 _intel_edp_backlight_on(intel_dp
);
2372 /* Disable backlight in the panel power control. */
2373 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2375 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2376 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2378 i915_reg_t pp_ctrl_reg
;
2380 if (!is_edp(intel_dp
))
2385 pp
= ironlake_get_pp_control(intel_dp
);
2386 pp
&= ~EDP_BLC_ENABLE
;
2388 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2390 I915_WRITE(pp_ctrl_reg
, pp
);
2391 POSTING_READ(pp_ctrl_reg
);
2393 pps_unlock(intel_dp
);
2395 intel_dp
->last_backlight_off
= jiffies
;
2396 edp_wait_backlight_off(intel_dp
);
2399 /* Disable backlight PP control and backlight PWM. */
2400 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2402 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2404 if (!is_edp(intel_dp
))
2407 DRM_DEBUG_KMS("\n");
2409 _intel_edp_backlight_off(intel_dp
);
2410 intel_panel_disable_backlight(old_conn_state
);
2414 * Hook for controlling the panel power control backlight through the bl_power
2415 * sysfs attribute. Take care to handle multiple calls.
2417 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2420 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2424 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2425 pps_unlock(intel_dp
);
2427 if (is_enabled
== enable
)
2430 DRM_DEBUG_KMS("panel power control backlight %s\n",
2431 enable
? "enable" : "disable");
2434 _intel_edp_backlight_on(intel_dp
);
2436 _intel_edp_backlight_off(intel_dp
);
2439 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2441 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2442 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2443 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2445 I915_STATE_WARN(cur_state
!= state
,
2446 "DP port %c state assertion failure (expected %s, current %s)\n",
2447 port_name(dig_port
->port
),
2448 onoff(state
), onoff(cur_state
));
2450 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2452 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2454 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2456 I915_STATE_WARN(cur_state
!= state
,
2457 "eDP PLL state assertion failure (expected %s, current %s)\n",
2458 onoff(state
), onoff(cur_state
));
2460 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2461 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2463 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2464 struct intel_crtc_state
*pipe_config
)
2466 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2467 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2469 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2470 assert_dp_port_disabled(intel_dp
);
2471 assert_edp_pll_disabled(dev_priv
);
2473 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2474 pipe_config
->port_clock
);
2476 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2478 if (pipe_config
->port_clock
== 162000)
2479 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2481 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2483 I915_WRITE(DP_A
, intel_dp
->DP
);
2488 * [DevILK] Work around required when enabling DP PLL
2489 * while a pipe is enabled going to FDI:
2490 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2491 * 2. Program DP PLL enable
2493 if (IS_GEN5(dev_priv
))
2494 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2496 intel_dp
->DP
|= DP_PLL_ENABLE
;
2498 I915_WRITE(DP_A
, intel_dp
->DP
);
2503 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2505 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2506 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2507 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2509 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2510 assert_dp_port_disabled(intel_dp
);
2511 assert_edp_pll_enabled(dev_priv
);
2513 DRM_DEBUG_KMS("disabling eDP PLL\n");
2515 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2517 I915_WRITE(DP_A
, intel_dp
->DP
);
2522 /* If the sink supports it, try to set the power state appropriately */
2523 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2527 /* Should have a valid DPCD by this point */
2528 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2531 if (mode
!= DRM_MODE_DPMS_ON
) {
2532 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2535 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2538 * When turning on, we need to retry for 1ms to give the sink
2541 for (i
= 0; i
< 3; i
++) {
2542 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2549 if (ret
== 1 && lspcon
->active
)
2550 lspcon_wait_pcon_mode(lspcon
);
2554 DRM_DEBUG_KMS("failed to %s sink power state\n",
2555 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2558 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2561 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2562 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2563 struct drm_device
*dev
= encoder
->base
.dev
;
2564 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2568 if (!intel_display_power_get_if_enabled(dev_priv
,
2569 encoder
->power_domain
))
2574 tmp
= I915_READ(intel_dp
->output_reg
);
2576 if (!(tmp
& DP_PORT_EN
))
2579 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2580 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2581 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2584 for_each_pipe(dev_priv
, p
) {
2585 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2586 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2594 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2595 i915_mmio_reg_offset(intel_dp
->output_reg
));
2596 } else if (IS_CHERRYVIEW(dev_priv
)) {
2597 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2599 *pipe
= PORT_TO_PIPE(tmp
);
2605 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2610 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2611 struct intel_crtc_state
*pipe_config
)
2613 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2615 struct drm_device
*dev
= encoder
->base
.dev
;
2616 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2617 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2618 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2620 tmp
= I915_READ(intel_dp
->output_reg
);
2622 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2624 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2625 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2627 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2628 flags
|= DRM_MODE_FLAG_PHSYNC
;
2630 flags
|= DRM_MODE_FLAG_NHSYNC
;
2632 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2633 flags
|= DRM_MODE_FLAG_PVSYNC
;
2635 flags
|= DRM_MODE_FLAG_NVSYNC
;
2637 if (tmp
& DP_SYNC_HS_HIGH
)
2638 flags
|= DRM_MODE_FLAG_PHSYNC
;
2640 flags
|= DRM_MODE_FLAG_NHSYNC
;
2642 if (tmp
& DP_SYNC_VS_HIGH
)
2643 flags
|= DRM_MODE_FLAG_PVSYNC
;
2645 flags
|= DRM_MODE_FLAG_NVSYNC
;
2648 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2650 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2651 pipe_config
->limited_color_range
= true;
2653 pipe_config
->lane_count
=
2654 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2656 intel_dp_get_m_n(crtc
, pipe_config
);
2658 if (port
== PORT_A
) {
2659 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2660 pipe_config
->port_clock
= 162000;
2662 pipe_config
->port_clock
= 270000;
2665 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2666 intel_dotclock_calculate(pipe_config
->port_clock
,
2667 &pipe_config
->dp_m_n
);
2669 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2670 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2672 * This is a big fat ugly hack.
2674 * Some machines in UEFI boot mode provide us a VBT that has 18
2675 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2676 * unknown we fail to light up. Yet the same BIOS boots up with
2677 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2678 * max, not what it tells us to use.
2680 * Note: This will still be broken if the eDP panel is not lit
2681 * up by the BIOS, and thus we can't get the mode at module
2684 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2685 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2686 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2690 static void intel_disable_dp(struct intel_encoder
*encoder
,
2691 struct intel_crtc_state
*old_crtc_state
,
2692 struct drm_connector_state
*old_conn_state
)
2694 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2695 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2697 if (old_crtc_state
->has_audio
)
2698 intel_audio_codec_disable(encoder
);
2700 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2701 intel_psr_disable(intel_dp
);
2703 /* Make sure the panel is off before trying to change the mode. But also
2704 * ensure that we have vdd while we switch off the panel. */
2705 intel_edp_panel_vdd_on(intel_dp
);
2706 intel_edp_backlight_off(old_conn_state
);
2707 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2708 intel_edp_panel_off(intel_dp
);
2710 /* disable the port before the pipe on g4x */
2711 if (INTEL_GEN(dev_priv
) < 5)
2712 intel_dp_link_down(intel_dp
);
2715 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2716 struct intel_crtc_state
*old_crtc_state
,
2717 struct drm_connector_state
*old_conn_state
)
2719 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2720 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2722 intel_dp_link_down(intel_dp
);
2724 /* Only ilk+ has port A */
2726 ironlake_edp_pll_off(intel_dp
);
2729 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2730 struct intel_crtc_state
*old_crtc_state
,
2731 struct drm_connector_state
*old_conn_state
)
2733 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2735 intel_dp_link_down(intel_dp
);
2738 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2739 struct intel_crtc_state
*old_crtc_state
,
2740 struct drm_connector_state
*old_conn_state
)
2742 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2743 struct drm_device
*dev
= encoder
->base
.dev
;
2744 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2746 intel_dp_link_down(intel_dp
);
2748 mutex_lock(&dev_priv
->sb_lock
);
2750 /* Assert data lane reset */
2751 chv_data_lane_soft_reset(encoder
, true);
2753 mutex_unlock(&dev_priv
->sb_lock
);
2757 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2759 uint8_t dp_train_pat
)
2761 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2762 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2763 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2764 enum port port
= intel_dig_port
->port
;
2766 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2767 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2768 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2770 if (HAS_DDI(dev_priv
)) {
2771 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2773 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2774 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2776 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2778 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2779 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2780 case DP_TRAINING_PATTERN_DISABLE
:
2781 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2784 case DP_TRAINING_PATTERN_1
:
2785 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2787 case DP_TRAINING_PATTERN_2
:
2788 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2790 case DP_TRAINING_PATTERN_3
:
2791 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2794 I915_WRITE(DP_TP_CTL(port
), temp
);
2796 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2797 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2798 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2800 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2801 case DP_TRAINING_PATTERN_DISABLE
:
2802 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2804 case DP_TRAINING_PATTERN_1
:
2805 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2807 case DP_TRAINING_PATTERN_2
:
2808 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2810 case DP_TRAINING_PATTERN_3
:
2811 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2812 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2817 if (IS_CHERRYVIEW(dev_priv
))
2818 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2820 *DP
&= ~DP_LINK_TRAIN_MASK
;
2822 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2823 case DP_TRAINING_PATTERN_DISABLE
:
2824 *DP
|= DP_LINK_TRAIN_OFF
;
2826 case DP_TRAINING_PATTERN_1
:
2827 *DP
|= DP_LINK_TRAIN_PAT_1
;
2829 case DP_TRAINING_PATTERN_2
:
2830 *DP
|= DP_LINK_TRAIN_PAT_2
;
2832 case DP_TRAINING_PATTERN_3
:
2833 if (IS_CHERRYVIEW(dev_priv
)) {
2834 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2836 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2837 *DP
|= DP_LINK_TRAIN_PAT_2
;
2844 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2845 struct intel_crtc_state
*old_crtc_state
)
2847 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2848 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2850 /* enable with pattern 1 (as per spec) */
2852 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2855 * Magic for VLV/CHV. We _must_ first set up the register
2856 * without actually enabling the port, and then do another
2857 * write to enable the port. Otherwise link training will
2858 * fail when the power sequencer is freshly used for this port.
2860 intel_dp
->DP
|= DP_PORT_EN
;
2861 if (old_crtc_state
->has_audio
)
2862 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2864 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2865 POSTING_READ(intel_dp
->output_reg
);
2868 static void intel_enable_dp(struct intel_encoder
*encoder
,
2869 struct intel_crtc_state
*pipe_config
,
2870 struct drm_connector_state
*conn_state
)
2872 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2873 struct drm_device
*dev
= encoder
->base
.dev
;
2874 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2875 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2876 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2877 enum pipe pipe
= crtc
->pipe
;
2879 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2884 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2885 vlv_init_panel_power_sequencer(intel_dp
);
2887 intel_dp_enable_port(intel_dp
, pipe_config
);
2889 edp_panel_vdd_on(intel_dp
);
2890 edp_panel_on(intel_dp
);
2891 edp_panel_vdd_off(intel_dp
, true);
2893 pps_unlock(intel_dp
);
2895 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2896 unsigned int lane_mask
= 0x0;
2898 if (IS_CHERRYVIEW(dev_priv
))
2899 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2901 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2905 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2906 intel_dp_start_link_train(intel_dp
);
2907 intel_dp_stop_link_train(intel_dp
);
2909 if (pipe_config
->has_audio
) {
2910 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2912 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
2916 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2917 struct intel_crtc_state
*pipe_config
,
2918 struct drm_connector_state
*conn_state
)
2920 intel_enable_dp(encoder
, pipe_config
, conn_state
);
2921 intel_edp_backlight_on(pipe_config
, conn_state
);
2924 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2925 struct intel_crtc_state
*pipe_config
,
2926 struct drm_connector_state
*conn_state
)
2928 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2930 intel_edp_backlight_on(pipe_config
, conn_state
);
2931 intel_psr_enable(intel_dp
);
2934 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2935 struct intel_crtc_state
*pipe_config
,
2936 struct drm_connector_state
*conn_state
)
2938 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2939 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2941 intel_dp_prepare(encoder
, pipe_config
);
2943 /* Only ilk+ has port A */
2945 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2948 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2950 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2951 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2952 enum pipe pipe
= intel_dp
->pps_pipe
;
2953 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2955 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
2957 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2960 edp_panel_vdd_off_sync(intel_dp
);
2963 * VLV seems to get confused when multiple power seqeuencers
2964 * have the same port selected (even if only one has power/vdd
2965 * enabled). The failure manifests as vlv_wait_port_ready() failing
2966 * CHV on the other hand doesn't seem to mind having the same port
2967 * selected in multiple power seqeuencers, but let's clear the
2968 * port select always when logically disconnecting a power sequencer
2971 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2972 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2973 I915_WRITE(pp_on_reg
, 0);
2974 POSTING_READ(pp_on_reg
);
2976 intel_dp
->pps_pipe
= INVALID_PIPE
;
2979 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2982 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2983 struct intel_encoder
*encoder
;
2985 lockdep_assert_held(&dev_priv
->pps_mutex
);
2987 for_each_intel_encoder(dev
, encoder
) {
2988 struct intel_dp
*intel_dp
;
2991 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
2992 encoder
->type
!= INTEL_OUTPUT_EDP
)
2995 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2996 port
= dp_to_dig_port(intel_dp
)->port
;
2998 WARN(intel_dp
->active_pipe
== pipe
,
2999 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3000 pipe_name(pipe
), port_name(port
));
3002 if (intel_dp
->pps_pipe
!= pipe
)
3005 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3006 pipe_name(pipe
), port_name(port
));
3008 /* make sure vdd is off before we steal it */
3009 vlv_detach_power_sequencer(intel_dp
);
3013 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
3015 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3016 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
3017 struct drm_device
*dev
= encoder
->base
.dev
;
3018 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3019 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
3021 lockdep_assert_held(&dev_priv
->pps_mutex
);
3023 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3025 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3026 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3028 * If another power sequencer was being used on this
3029 * port previously make sure to turn off vdd there while
3030 * we still have control of it.
3032 vlv_detach_power_sequencer(intel_dp
);
3036 * We may be stealing the power
3037 * sequencer from another port.
3039 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
3041 intel_dp
->active_pipe
= crtc
->pipe
;
3043 if (!is_edp(intel_dp
))
3046 /* now it's all ours */
3047 intel_dp
->pps_pipe
= crtc
->pipe
;
3049 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3050 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
3052 /* init power sequencer on this pipe and port */
3053 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
3054 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
3057 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3058 struct intel_crtc_state
*pipe_config
,
3059 struct drm_connector_state
*conn_state
)
3061 vlv_phy_pre_encoder_enable(encoder
);
3063 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3066 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3067 struct intel_crtc_state
*pipe_config
,
3068 struct drm_connector_state
*conn_state
)
3070 intel_dp_prepare(encoder
, pipe_config
);
3072 vlv_phy_pre_pll_enable(encoder
);
3075 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3076 struct intel_crtc_state
*pipe_config
,
3077 struct drm_connector_state
*conn_state
)
3079 chv_phy_pre_encoder_enable(encoder
);
3081 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3083 /* Second common lane will stay alive on its own now */
3084 chv_phy_release_cl2_override(encoder
);
3087 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3088 struct intel_crtc_state
*pipe_config
,
3089 struct drm_connector_state
*conn_state
)
3091 intel_dp_prepare(encoder
, pipe_config
);
3093 chv_phy_pre_pll_enable(encoder
);
3096 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3097 struct intel_crtc_state
*pipe_config
,
3098 struct drm_connector_state
*conn_state
)
3100 chv_phy_post_pll_disable(encoder
);
3104 * Fetch AUX CH registers 0x202 - 0x207 which contain
3105 * link status information
3108 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3110 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3111 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3114 static bool intel_dp_get_y_cord_status(struct intel_dp
*intel_dp
)
3116 uint8_t psr_caps
= 0;
3118 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_PSR_CAPS
, &psr_caps
) != 1)
3120 return psr_caps
& DP_PSR2_SU_Y_COORDINATE_REQUIRED
;
3123 static bool intel_dp_get_colorimetry_status(struct intel_dp
*intel_dp
)
3127 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DPRX_FEATURE_ENUMERATION_LIST
,
3130 return dprx
& DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
;
3133 static bool intel_dp_get_alpm_status(struct intel_dp
*intel_dp
)
3135 uint8_t alpm_caps
= 0;
3137 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_RECEIVER_ALPM_CAP
,
3140 return alpm_caps
& DP_ALPM_CAP
;
3143 /* These are source-specific values. */
3145 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3147 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3148 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3150 if (IS_GEN9_LP(dev_priv
))
3151 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3152 else if (INTEL_GEN(dev_priv
) >= 9) {
3153 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3154 return intel_ddi_dp_voltage_max(encoder
);
3155 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3156 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3157 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3158 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3159 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3160 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3162 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3166 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3168 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3169 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3171 if (INTEL_GEN(dev_priv
) >= 9) {
3172 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3174 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3176 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3178 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3180 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3182 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3184 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3185 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3187 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3189 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3191 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3194 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3196 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3197 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3199 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3201 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3203 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3206 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3208 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3209 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3211 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3214 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3216 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3219 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3221 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3223 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3225 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3228 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3233 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3235 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3236 unsigned long demph_reg_value
, preemph_reg_value
,
3237 uniqtranscale_reg_value
;
3238 uint8_t train_set
= intel_dp
->train_set
[0];
3240 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3241 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3242 preemph_reg_value
= 0x0004000;
3243 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3245 demph_reg_value
= 0x2B405555;
3246 uniqtranscale_reg_value
= 0x552AB83A;
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3249 demph_reg_value
= 0x2B404040;
3250 uniqtranscale_reg_value
= 0x5548B83A;
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3253 demph_reg_value
= 0x2B245555;
3254 uniqtranscale_reg_value
= 0x5560B83A;
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3257 demph_reg_value
= 0x2B405555;
3258 uniqtranscale_reg_value
= 0x5598DA3A;
3264 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3265 preemph_reg_value
= 0x0002000;
3266 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3267 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3268 demph_reg_value
= 0x2B404040;
3269 uniqtranscale_reg_value
= 0x5552B83A;
3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3272 demph_reg_value
= 0x2B404848;
3273 uniqtranscale_reg_value
= 0x5580B83A;
3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3276 demph_reg_value
= 0x2B404040;
3277 uniqtranscale_reg_value
= 0x55ADDA3A;
3283 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3284 preemph_reg_value
= 0x0000000;
3285 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3287 demph_reg_value
= 0x2B305555;
3288 uniqtranscale_reg_value
= 0x5570B83A;
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3291 demph_reg_value
= 0x2B2B4040;
3292 uniqtranscale_reg_value
= 0x55ADDA3A;
3298 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3299 preemph_reg_value
= 0x0006000;
3300 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3302 demph_reg_value
= 0x1B405555;
3303 uniqtranscale_reg_value
= 0x55ADDA3A;
3313 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3314 uniqtranscale_reg_value
, 0);
3319 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3321 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3322 u32 deemph_reg_value
, margin_reg_value
;
3323 bool uniq_trans_scale
= false;
3324 uint8_t train_set
= intel_dp
->train_set
[0];
3326 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3327 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3328 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3330 deemph_reg_value
= 128;
3331 margin_reg_value
= 52;
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3334 deemph_reg_value
= 128;
3335 margin_reg_value
= 77;
3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3338 deemph_reg_value
= 128;
3339 margin_reg_value
= 102;
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3342 deemph_reg_value
= 128;
3343 margin_reg_value
= 154;
3344 uniq_trans_scale
= true;
3350 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3351 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3353 deemph_reg_value
= 85;
3354 margin_reg_value
= 78;
3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3357 deemph_reg_value
= 85;
3358 margin_reg_value
= 116;
3360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3361 deemph_reg_value
= 85;
3362 margin_reg_value
= 154;
3368 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3369 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3370 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3371 deemph_reg_value
= 64;
3372 margin_reg_value
= 104;
3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3375 deemph_reg_value
= 64;
3376 margin_reg_value
= 154;
3382 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3383 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3385 deemph_reg_value
= 43;
3386 margin_reg_value
= 154;
3396 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3397 margin_reg_value
, uniq_trans_scale
);
3403 gen4_signal_levels(uint8_t train_set
)
3405 uint32_t signal_levels
= 0;
3407 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3410 signal_levels
|= DP_VOLTAGE_0_4
;
3412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3413 signal_levels
|= DP_VOLTAGE_0_6
;
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3416 signal_levels
|= DP_VOLTAGE_0_8
;
3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3419 signal_levels
|= DP_VOLTAGE_1_2
;
3422 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3423 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3425 signal_levels
|= DP_PRE_EMPHASIS_0
;
3427 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3428 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3430 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3431 signal_levels
|= DP_PRE_EMPHASIS_6
;
3433 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3434 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3437 return signal_levels
;
3440 /* Gen6's DP voltage swing and pre-emphasis control */
3442 gen6_edp_signal_levels(uint8_t train_set
)
3444 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3445 DP_TRAIN_PRE_EMPHASIS_MASK
);
3446 switch (signal_levels
) {
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3449 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3451 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3452 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3454 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3457 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3458 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3460 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3462 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3463 "0x%x\n", signal_levels
);
3464 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3468 /* Gen7's DP voltage swing and pre-emphasis control */
3470 gen7_edp_signal_levels(uint8_t train_set
)
3472 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3473 DP_TRAIN_PRE_EMPHASIS_MASK
);
3474 switch (signal_levels
) {
3475 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3476 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3478 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3479 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3480 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3482 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3483 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3484 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3485 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3488 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3490 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3493 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3494 "0x%x\n", signal_levels
);
3495 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3500 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3502 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3503 enum port port
= intel_dig_port
->port
;
3504 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3505 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3506 uint32_t signal_levels
, mask
= 0;
3507 uint8_t train_set
= intel_dp
->train_set
[0];
3509 if (HAS_DDI(dev_priv
)) {
3510 signal_levels
= ddi_signal_levels(intel_dp
);
3512 if (IS_GEN9_LP(dev_priv
) || IS_CANNONLAKE(dev_priv
))
3515 mask
= DDI_BUF_EMP_MASK
;
3516 } else if (IS_CHERRYVIEW(dev_priv
)) {
3517 signal_levels
= chv_signal_levels(intel_dp
);
3518 } else if (IS_VALLEYVIEW(dev_priv
)) {
3519 signal_levels
= vlv_signal_levels(intel_dp
);
3520 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3521 signal_levels
= gen7_edp_signal_levels(train_set
);
3522 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3523 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3524 signal_levels
= gen6_edp_signal_levels(train_set
);
3525 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3527 signal_levels
= gen4_signal_levels(train_set
);
3528 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3532 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3534 DRM_DEBUG_KMS("Using vswing level %d\n",
3535 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3536 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3537 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3538 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3540 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3542 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3543 POSTING_READ(intel_dp
->output_reg
);
3547 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3548 uint8_t dp_train_pat
)
3550 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3551 struct drm_i915_private
*dev_priv
=
3552 to_i915(intel_dig_port
->base
.base
.dev
);
3554 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3556 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3557 POSTING_READ(intel_dp
->output_reg
);
3560 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3562 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3563 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3564 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3565 enum port port
= intel_dig_port
->port
;
3568 if (!HAS_DDI(dev_priv
))
3571 val
= I915_READ(DP_TP_CTL(port
));
3572 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3573 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3574 I915_WRITE(DP_TP_CTL(port
), val
);
3577 * On PORT_A we can have only eDP in SST mode. There the only reason
3578 * we need to set idle transmission mode is to work around a HW issue
3579 * where we enable the pipe while not in idle link-training mode.
3580 * In this case there is requirement to wait for a minimum number of
3581 * idle patterns to be sent.
3586 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3587 DP_TP_STATUS_IDLE_DONE
,
3588 DP_TP_STATUS_IDLE_DONE
,
3590 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3594 intel_dp_link_down(struct intel_dp
*intel_dp
)
3596 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3597 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3598 enum port port
= intel_dig_port
->port
;
3599 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3600 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3601 uint32_t DP
= intel_dp
->DP
;
3603 if (WARN_ON(HAS_DDI(dev_priv
)))
3606 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3609 DRM_DEBUG_KMS("\n");
3611 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3612 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3613 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3614 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3616 if (IS_CHERRYVIEW(dev_priv
))
3617 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3619 DP
&= ~DP_LINK_TRAIN_MASK
;
3620 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3622 I915_WRITE(intel_dp
->output_reg
, DP
);
3623 POSTING_READ(intel_dp
->output_reg
);
3625 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3626 I915_WRITE(intel_dp
->output_reg
, DP
);
3627 POSTING_READ(intel_dp
->output_reg
);
3630 * HW workaround for IBX, we need to move the port
3631 * to transcoder A after disabling it to allow the
3632 * matching HDMI port to be enabled on transcoder A.
3634 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3636 * We get CPU/PCH FIFO underruns on the other pipe when
3637 * doing the workaround. Sweep them under the rug.
3639 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3640 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3642 /* always enable with pattern 1 (as per spec) */
3643 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3644 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3645 I915_WRITE(intel_dp
->output_reg
, DP
);
3646 POSTING_READ(intel_dp
->output_reg
);
3649 I915_WRITE(intel_dp
->output_reg
, DP
);
3650 POSTING_READ(intel_dp
->output_reg
);
3652 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3653 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3654 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3657 msleep(intel_dp
->panel_power_down_delay
);
3661 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3663 intel_dp
->active_pipe
= INVALID_PIPE
;
3664 pps_unlock(intel_dp
);
3669 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3671 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3672 sizeof(intel_dp
->dpcd
)) < 0)
3673 return false; /* aux transfer failed */
3675 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3677 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3681 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3683 struct drm_i915_private
*dev_priv
=
3684 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3686 /* this function is meant to be called only once */
3687 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3689 if (!intel_dp_read_dpcd(intel_dp
))
3692 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
3693 drm_dp_is_branch(intel_dp
->dpcd
));
3695 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3696 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3697 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3699 /* Check if the panel supports PSR */
3700 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3702 sizeof(intel_dp
->psr_dpcd
));
3703 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3704 dev_priv
->psr
.sink_support
= true;
3705 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3708 if (INTEL_GEN(dev_priv
) >= 9 &&
3709 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3710 uint8_t frame_sync_cap
;
3712 dev_priv
->psr
.sink_support
= true;
3713 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3714 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3715 &frame_sync_cap
) != 1)
3717 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3718 /* PSR2 needs frame sync as well */
3719 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3720 DRM_DEBUG_KMS("PSR2 %s on sink",
3721 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3723 if (dev_priv
->psr
.psr2_support
) {
3724 dev_priv
->psr
.y_cord_support
=
3725 intel_dp_get_y_cord_status(intel_dp
);
3726 dev_priv
->psr
.colorimetry_support
=
3727 intel_dp_get_colorimetry_status(intel_dp
);
3728 dev_priv
->psr
.alpm
=
3729 intel_dp_get_alpm_status(intel_dp
);
3735 * Read the eDP display control registers.
3737 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3738 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3739 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3740 * method). The display control registers should read zero if they're
3741 * not supported anyway.
3743 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3744 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3745 sizeof(intel_dp
->edp_dpcd
))
3746 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3747 intel_dp
->edp_dpcd
);
3749 /* Intermediate frequency support */
3750 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3751 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3754 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3755 sink_rates
, sizeof(sink_rates
));
3757 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3758 int val
= le16_to_cpu(sink_rates
[i
]);
3763 /* Value read multiplied by 200kHz gives the per-lane
3764 * link rate in kHz. The source rates are, however,
3765 * stored in terms of LS_Clk kHz. The full conversion
3766 * back to symbols is
3767 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3769 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3771 intel_dp
->num_sink_rates
= i
;
3774 if (intel_dp
->num_sink_rates
)
3775 intel_dp
->use_rate_select
= true;
3777 intel_dp_set_sink_rates(intel_dp
);
3779 intel_dp_set_common_rates(intel_dp
);
3786 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3790 if (!intel_dp_read_dpcd(intel_dp
))
3793 /* Don't clobber cached eDP rates. */
3794 if (!is_edp(intel_dp
)) {
3795 intel_dp_set_sink_rates(intel_dp
);
3796 intel_dp_set_common_rates(intel_dp
);
3799 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &sink_count
) <= 0)
3803 * Sink count can change between short pulse hpd hence
3804 * a member variable in intel_dp will track any changes
3805 * between short pulse interrupts.
3807 intel_dp
->sink_count
= DP_GET_SINK_COUNT(sink_count
);
3810 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3811 * a dongle is present but no display. Unless we require to know
3812 * if a dongle is present or not, we don't need to update
3813 * downstream port information. So, an early return here saves
3814 * time from performing other operations which are not required.
3816 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3819 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3820 return true; /* native DP sink */
3822 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3823 return true; /* no per-port downstream info */
3825 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3826 intel_dp
->downstream_ports
,
3827 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3828 return false; /* downstream port status fetch failed */
3834 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3838 if (!i915
.enable_dp_mst
)
3841 if (!intel_dp
->can_mst
)
3844 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3847 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
3850 return mstm_cap
& DP_MST_CAP
;
3854 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3856 if (!i915
.enable_dp_mst
)
3859 if (!intel_dp
->can_mst
)
3862 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3864 if (intel_dp
->is_mst
)
3865 DRM_DEBUG_KMS("Sink is MST capable\n");
3867 DRM_DEBUG_KMS("Sink is not MST capable\n");
3869 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3873 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3875 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3876 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3877 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3883 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3884 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3889 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3890 buf
& ~DP_TEST_SINK_START
) < 0) {
3891 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3897 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3899 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3900 DP_TEST_SINK_MISC
, &buf
) < 0) {
3904 count
= buf
& DP_TEST_COUNT_MASK
;
3905 } while (--attempts
&& count
);
3907 if (attempts
== 0) {
3908 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3913 hsw_enable_ips(intel_crtc
);
3917 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3919 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3920 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3921 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3925 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3928 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3931 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3934 if (buf
& DP_TEST_SINK_START
) {
3935 ret
= intel_dp_sink_crc_stop(intel_dp
);
3940 hsw_disable_ips(intel_crtc
);
3942 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3943 buf
| DP_TEST_SINK_START
) < 0) {
3944 hsw_enable_ips(intel_crtc
);
3948 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3952 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3954 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3955 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3956 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3961 ret
= intel_dp_sink_crc_start(intel_dp
);
3966 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3968 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3969 DP_TEST_SINK_MISC
, &buf
) < 0) {
3973 count
= buf
& DP_TEST_COUNT_MASK
;
3975 } while (--attempts
&& count
== 0);
3977 if (attempts
== 0) {
3978 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3983 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3989 intel_dp_sink_crc_stop(intel_dp
);
3994 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3996 return drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
3997 sink_irq_vector
) == 1;
4001 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4005 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
4007 sink_irq_vector
, 14);
4014 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4018 uint8_t test_lane_count
, test_link_bw
;
4022 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4023 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4027 DRM_DEBUG_KMS("Lane count read failed\n");
4030 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4032 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4035 DRM_DEBUG_KMS("Link Rate read failed\n");
4038 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4040 /* Validate the requested link rate and lane count */
4041 if (!intel_dp_link_params_valid(intel_dp
, test_link_rate
,
4045 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4046 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4051 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4053 uint8_t test_pattern
;
4055 __be16 h_width
, v_height
;
4058 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4059 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4062 DRM_DEBUG_KMS("Test pattern read failed\n");
4065 if (test_pattern
!= DP_COLOR_RAMP
)
4068 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4071 DRM_DEBUG_KMS("H Width read failed\n");
4075 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4078 DRM_DEBUG_KMS("V Height read failed\n");
4082 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4085 DRM_DEBUG_KMS("TEST MISC read failed\n");
4088 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4090 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4092 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4093 case DP_TEST_BIT_DEPTH_6
:
4094 intel_dp
->compliance
.test_data
.bpc
= 6;
4096 case DP_TEST_BIT_DEPTH_8
:
4097 intel_dp
->compliance
.test_data
.bpc
= 8;
4103 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4104 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4105 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4106 /* Set test active flag here so userspace doesn't interrupt things */
4107 intel_dp
->compliance
.test_active
= 1;
4112 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4114 uint8_t test_result
= DP_TEST_ACK
;
4115 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4116 struct drm_connector
*connector
= &intel_connector
->base
;
4118 if (intel_connector
->detect_edid
== NULL
||
4119 connector
->edid_corrupt
||
4120 intel_dp
->aux
.i2c_defer_count
> 6) {
4121 /* Check EDID read for NACKs, DEFERs and corruption
4122 * (DP CTS 1.2 Core r1.1)
4123 * 4.2.2.4 : Failed EDID read, I2C_NAK
4124 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4125 * 4.2.2.6 : EDID corruption detected
4126 * Use failsafe mode for all cases
4128 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4129 intel_dp
->aux
.i2c_defer_count
> 0)
4130 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4131 intel_dp
->aux
.i2c_nack_count
,
4132 intel_dp
->aux
.i2c_defer_count
);
4133 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4135 struct edid
*block
= intel_connector
->detect_edid
;
4137 /* We have to write the checksum
4138 * of the last block read
4140 block
+= intel_connector
->detect_edid
->extensions
;
4142 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4143 block
->checksum
) <= 0)
4144 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4146 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4147 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4150 /* Set test active flag here so userspace doesn't interrupt things */
4151 intel_dp
->compliance
.test_active
= 1;
4156 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4158 uint8_t test_result
= DP_TEST_NAK
;
4162 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4164 uint8_t response
= DP_TEST_NAK
;
4165 uint8_t request
= 0;
4168 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4170 DRM_DEBUG_KMS("Could not read test request from sink\n");
4175 case DP_TEST_LINK_TRAINING
:
4176 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4177 response
= intel_dp_autotest_link_training(intel_dp
);
4179 case DP_TEST_LINK_VIDEO_PATTERN
:
4180 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4181 response
= intel_dp_autotest_video_pattern(intel_dp
);
4183 case DP_TEST_LINK_EDID_READ
:
4184 DRM_DEBUG_KMS("EDID test requested\n");
4185 response
= intel_dp_autotest_edid(intel_dp
);
4187 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4188 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4189 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4192 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4196 if (response
& DP_TEST_ACK
)
4197 intel_dp
->compliance
.test_type
= request
;
4200 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4202 DRM_DEBUG_KMS("Could not write test response to sink\n");
4206 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4210 if (intel_dp
->is_mst
) {
4215 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4219 /* check link status - esi[10] = 0x200c */
4220 if (intel_dp
->active_mst_links
&&
4221 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4222 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4223 intel_dp_start_link_train(intel_dp
);
4224 intel_dp_stop_link_train(intel_dp
);
4227 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4228 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4231 for (retry
= 0; retry
< 3; retry
++) {
4233 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4234 DP_SINK_COUNT_ESI
+1,
4241 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4243 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4251 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4252 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4253 intel_dp
->is_mst
= false;
4254 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4255 /* send a hotplug event */
4256 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4263 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
4265 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4266 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4267 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4269 /* Suppress underruns caused by re-training */
4270 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4271 if (crtc
->config
->has_pch_encoder
)
4272 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4273 intel_crtc_pch_transcoder(crtc
), false);
4275 intel_dp_start_link_train(intel_dp
);
4276 intel_dp_stop_link_train(intel_dp
);
4278 /* Keep underrun reporting disabled until things are stable */
4279 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4281 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4282 if (crtc
->config
->has_pch_encoder
)
4283 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4284 intel_crtc_pch_transcoder(crtc
), true);
4288 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4290 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4291 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4292 u8 link_status
[DP_LINK_STATUS_SIZE
];
4294 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4296 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4297 DRM_ERROR("Failed to get link status\n");
4301 if (!intel_encoder
->base
.crtc
)
4304 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4308 * Validate the cached values of intel_dp->link_rate and
4309 * intel_dp->lane_count before attempting to retrain.
4311 if (!intel_dp_link_params_valid(intel_dp
, intel_dp
->link_rate
,
4312 intel_dp
->lane_count
))
4315 /* Retrain if Channel EQ or CR not ok */
4316 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4317 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4318 intel_encoder
->base
.name
);
4320 intel_dp_retrain_link(intel_dp
);
4325 * According to DP spec
4328 * 2. Configure link according to Receiver Capabilities
4329 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4330 * 4. Check link status on receipt of hot-plug interrupt
4332 * intel_dp_short_pulse - handles short pulse interrupts
4333 * when full detection is not required.
4334 * Returns %true if short pulse is handled and full detection
4335 * is NOT required and %false otherwise.
4338 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4340 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4341 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4342 u8 sink_irq_vector
= 0;
4343 u8 old_sink_count
= intel_dp
->sink_count
;
4347 * Clearing compliance test variables to allow capturing
4348 * of values for next automated test request.
4350 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4353 * Now read the DPCD to see if it's actually running
4354 * If the current value of sink count doesn't match with
4355 * the value that was stored earlier or dpcd read failed
4356 * we need to do full detection
4358 ret
= intel_dp_get_dpcd(intel_dp
);
4360 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4361 /* No need to proceed if we are going to do full detect */
4365 /* Try to read the source of the interrupt */
4366 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4367 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4368 sink_irq_vector
!= 0) {
4369 /* Clear interrupt source */
4370 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4371 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4374 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4375 intel_dp_handle_test_request(intel_dp
);
4376 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4377 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4380 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4381 intel_dp_check_link_status(intel_dp
);
4382 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4383 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4384 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4385 /* Send a Hotplug Uevent to userspace to start modeset */
4386 drm_kms_helper_hotplug_event(intel_encoder
->base
.dev
);
4392 /* XXX this is probably wrong for multiple downstream ports */
4393 static enum drm_connector_status
4394 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4396 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4397 uint8_t *dpcd
= intel_dp
->dpcd
;
4401 lspcon_resume(lspcon
);
4403 if (!intel_dp_get_dpcd(intel_dp
))
4404 return connector_status_disconnected
;
4406 if (is_edp(intel_dp
))
4407 return connector_status_connected
;
4409 /* if there's no downstream port, we're done */
4410 if (!drm_dp_is_branch(dpcd
))
4411 return connector_status_connected
;
4413 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4414 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4415 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4417 return intel_dp
->sink_count
?
4418 connector_status_connected
: connector_status_disconnected
;
4421 if (intel_dp_can_mst(intel_dp
))
4422 return connector_status_connected
;
4424 /* If no HPD, poke DDC gently */
4425 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4426 return connector_status_connected
;
4428 /* Well we tried, say unknown for unreliable port types */
4429 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4430 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4431 if (type
== DP_DS_PORT_TYPE_VGA
||
4432 type
== DP_DS_PORT_TYPE_NON_EDID
)
4433 return connector_status_unknown
;
4435 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4436 DP_DWN_STRM_PORT_TYPE_MASK
;
4437 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4438 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4439 return connector_status_unknown
;
4442 /* Anything else is out of spec, warn and ignore */
4443 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4444 return connector_status_disconnected
;
4447 static enum drm_connector_status
4448 edp_detect(struct intel_dp
*intel_dp
)
4450 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4451 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4452 enum drm_connector_status status
;
4454 status
= intel_panel_detect(dev_priv
);
4455 if (status
== connector_status_unknown
)
4456 status
= connector_status_connected
;
4461 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4462 struct intel_digital_port
*port
)
4466 switch (port
->port
) {
4468 bit
= SDE_PORTB_HOTPLUG
;
4471 bit
= SDE_PORTC_HOTPLUG
;
4474 bit
= SDE_PORTD_HOTPLUG
;
4477 MISSING_CASE(port
->port
);
4481 return I915_READ(SDEISR
) & bit
;
4484 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4485 struct intel_digital_port
*port
)
4489 switch (port
->port
) {
4491 bit
= SDE_PORTB_HOTPLUG_CPT
;
4494 bit
= SDE_PORTC_HOTPLUG_CPT
;
4497 bit
= SDE_PORTD_HOTPLUG_CPT
;
4500 MISSING_CASE(port
->port
);
4504 return I915_READ(SDEISR
) & bit
;
4507 static bool spt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4508 struct intel_digital_port
*port
)
4512 switch (port
->port
) {
4514 bit
= SDE_PORTA_HOTPLUG_SPT
;
4517 bit
= SDE_PORTE_HOTPLUG_SPT
;
4520 return cpt_digital_port_connected(dev_priv
, port
);
4523 return I915_READ(SDEISR
) & bit
;
4526 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4527 struct intel_digital_port
*port
)
4531 switch (port
->port
) {
4533 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4536 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4539 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4542 MISSING_CASE(port
->port
);
4546 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4549 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4550 struct intel_digital_port
*port
)
4554 switch (port
->port
) {
4556 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4559 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4562 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4565 MISSING_CASE(port
->port
);
4569 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4572 static bool ilk_digital_port_connected(struct drm_i915_private
*dev_priv
,
4573 struct intel_digital_port
*port
)
4575 if (port
->port
== PORT_A
)
4576 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4578 return ibx_digital_port_connected(dev_priv
, port
);
4581 static bool snb_digital_port_connected(struct drm_i915_private
*dev_priv
,
4582 struct intel_digital_port
*port
)
4584 if (port
->port
== PORT_A
)
4585 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG
;
4587 return cpt_digital_port_connected(dev_priv
, port
);
4590 static bool ivb_digital_port_connected(struct drm_i915_private
*dev_priv
,
4591 struct intel_digital_port
*port
)
4593 if (port
->port
== PORT_A
)
4594 return I915_READ(DEISR
) & DE_DP_A_HOTPLUG_IVB
;
4596 return cpt_digital_port_connected(dev_priv
, port
);
4599 static bool bdw_digital_port_connected(struct drm_i915_private
*dev_priv
,
4600 struct intel_digital_port
*port
)
4602 if (port
->port
== PORT_A
)
4603 return I915_READ(GEN8_DE_PORT_ISR
) & GEN8_PORT_DP_A_HOTPLUG
;
4605 return cpt_digital_port_connected(dev_priv
, port
);
4608 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4609 struct intel_digital_port
*intel_dig_port
)
4611 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4615 port
= intel_hpd_pin_to_port(intel_encoder
->hpd_pin
);
4618 bit
= BXT_DE_PORT_HP_DDIA
;
4621 bit
= BXT_DE_PORT_HP_DDIB
;
4624 bit
= BXT_DE_PORT_HP_DDIC
;
4631 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4635 * intel_digital_port_connected - is the specified port connected?
4636 * @dev_priv: i915 private structure
4637 * @port: the port to test
4639 * Return %true if @port is connected, %false otherwise.
4641 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4642 struct intel_digital_port
*port
)
4644 if (HAS_GMCH_DISPLAY(dev_priv
)) {
4645 if (IS_GM45(dev_priv
))
4646 return gm45_digital_port_connected(dev_priv
, port
);
4648 return g4x_digital_port_connected(dev_priv
, port
);
4651 if (IS_GEN5(dev_priv
))
4652 return ilk_digital_port_connected(dev_priv
, port
);
4653 else if (IS_GEN6(dev_priv
))
4654 return snb_digital_port_connected(dev_priv
, port
);
4655 else if (IS_GEN7(dev_priv
))
4656 return ivb_digital_port_connected(dev_priv
, port
);
4657 else if (IS_GEN8(dev_priv
))
4658 return bdw_digital_port_connected(dev_priv
, port
);
4659 else if (IS_GEN9_LP(dev_priv
))
4660 return bxt_digital_port_connected(dev_priv
, port
);
4662 return spt_digital_port_connected(dev_priv
, port
);
4665 static struct edid
*
4666 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4668 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4670 /* use cached edid if we have one */
4671 if (intel_connector
->edid
) {
4673 if (IS_ERR(intel_connector
->edid
))
4676 return drm_edid_duplicate(intel_connector
->edid
);
4678 return drm_get_edid(&intel_connector
->base
,
4679 &intel_dp
->aux
.ddc
);
4683 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4685 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4688 intel_dp_unset_edid(intel_dp
);
4689 edid
= intel_dp_get_edid(intel_dp
);
4690 intel_connector
->detect_edid
= edid
;
4692 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4696 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4698 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4700 kfree(intel_connector
->detect_edid
);
4701 intel_connector
->detect_edid
= NULL
;
4703 intel_dp
->has_audio
= false;
4707 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4709 struct drm_connector
*connector
= &intel_connector
->base
;
4710 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4711 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4712 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4713 struct drm_device
*dev
= connector
->dev
;
4714 enum drm_connector_status status
;
4715 u8 sink_irq_vector
= 0;
4717 WARN_ON(!drm_modeset_is_locked(&connector
->dev
->mode_config
.connection_mutex
));
4719 intel_display_power_get(to_i915(dev
), intel_dp
->aux_power_domain
);
4721 /* Can't disconnect eDP, but you can close the lid... */
4722 if (is_edp(intel_dp
))
4723 status
= edp_detect(intel_dp
);
4724 else if (intel_digital_port_connected(to_i915(dev
),
4725 dp_to_dig_port(intel_dp
)))
4726 status
= intel_dp_detect_dpcd(intel_dp
);
4728 status
= connector_status_disconnected
;
4730 if (status
== connector_status_disconnected
) {
4731 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4733 if (intel_dp
->is_mst
) {
4734 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4736 intel_dp
->mst_mgr
.mst_state
);
4737 intel_dp
->is_mst
= false;
4738 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4745 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4746 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4748 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4749 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4750 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4752 if (intel_dp
->reset_link_params
) {
4753 /* Initial max link lane count */
4754 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
4756 /* Initial max link rate */
4757 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
4759 intel_dp
->reset_link_params
= false;
4762 intel_dp_print_rates(intel_dp
);
4764 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4765 drm_dp_is_branch(intel_dp
->dpcd
));
4767 intel_dp_configure_mst(intel_dp
);
4769 if (intel_dp
->is_mst
) {
4771 * If we are in MST mode then this connector
4772 * won't appear connected or have anything
4775 status
= connector_status_disconnected
;
4779 * If display is now connected check links status,
4780 * there has been known issues of link loss triggerring
4783 * Some sinks (eg. ASUS PB287Q) seem to perform some
4784 * weird HPD ping pong during modesets. So we can apparently
4785 * end up with HPD going low during a modeset, and then
4786 * going back up soon after. And once that happens we must
4787 * retrain the link to get a picture. That's in case no
4788 * userspace component reacted to intermittent HPD dip.
4790 intel_dp_check_link_status(intel_dp
);
4794 * Clearing NACK and defer counts to get their exact values
4795 * while reading EDID which are required by Compliance tests
4796 * 4.2.2.4 and 4.2.2.5
4798 intel_dp
->aux
.i2c_nack_count
= 0;
4799 intel_dp
->aux
.i2c_defer_count
= 0;
4801 intel_dp_set_edid(intel_dp
);
4802 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4803 status
= connector_status_connected
;
4804 intel_dp
->detect_done
= true;
4806 /* Try to read the source of the interrupt */
4807 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4808 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4809 sink_irq_vector
!= 0) {
4810 /* Clear interrupt source */
4811 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4812 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4815 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4816 intel_dp_handle_test_request(intel_dp
);
4817 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4818 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4822 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4823 intel_dp_unset_edid(intel_dp
);
4825 intel_display_power_put(to_i915(dev
), intel_dp
->aux_power_domain
);
4830 intel_dp_detect(struct drm_connector
*connector
,
4831 struct drm_modeset_acquire_ctx
*ctx
,
4834 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4835 int status
= connector
->status
;
4837 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4838 connector
->base
.id
, connector
->name
);
4840 /* If full detect is not performed yet, do a full detect */
4841 if (!intel_dp
->detect_done
)
4842 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4844 intel_dp
->detect_done
= false;
4850 intel_dp_force(struct drm_connector
*connector
)
4852 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4853 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4854 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4856 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4857 connector
->base
.id
, connector
->name
);
4858 intel_dp_unset_edid(intel_dp
);
4860 if (connector
->status
!= connector_status_connected
)
4863 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4865 intel_dp_set_edid(intel_dp
);
4867 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4869 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4870 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4873 static int intel_dp_get_modes(struct drm_connector
*connector
)
4875 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4878 edid
= intel_connector
->detect_edid
;
4880 int ret
= intel_connector_update_modes(connector
, edid
);
4885 /* if eDP has no EDID, fall back to fixed mode */
4886 if (is_edp(intel_attached_dp(connector
)) &&
4887 intel_connector
->panel
.fixed_mode
) {
4888 struct drm_display_mode
*mode
;
4890 mode
= drm_mode_duplicate(connector
->dev
,
4891 intel_connector
->panel
.fixed_mode
);
4893 drm_mode_probed_add(connector
, mode
);
4902 intel_dp_connector_register(struct drm_connector
*connector
)
4904 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4907 ret
= intel_connector_register(connector
);
4911 i915_debugfs_connector_add(connector
);
4913 DRM_DEBUG_KMS("registering %s bus for %s\n",
4914 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4916 intel_dp
->aux
.dev
= connector
->kdev
;
4917 return drm_dp_aux_register(&intel_dp
->aux
);
4921 intel_dp_connector_unregister(struct drm_connector
*connector
)
4923 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4924 intel_connector_unregister(connector
);
4928 intel_dp_connector_destroy(struct drm_connector
*connector
)
4930 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4932 kfree(intel_connector
->detect_edid
);
4934 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4935 kfree(intel_connector
->edid
);
4937 /* Can't call is_edp() since the encoder may have been destroyed
4939 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4940 intel_panel_fini(&intel_connector
->panel
);
4942 drm_connector_cleanup(connector
);
4946 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4948 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4949 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4951 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4952 if (is_edp(intel_dp
)) {
4953 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4955 * vdd might still be enabled do to the delayed vdd off.
4956 * Make sure vdd is actually turned off here.
4959 edp_panel_vdd_off_sync(intel_dp
);
4960 pps_unlock(intel_dp
);
4962 if (intel_dp
->edp_notifier
.notifier_call
) {
4963 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4964 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4968 intel_dp_aux_fini(intel_dp
);
4970 drm_encoder_cleanup(encoder
);
4971 kfree(intel_dig_port
);
4974 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4976 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4978 if (!is_edp(intel_dp
))
4982 * vdd might still be enabled do to the delayed vdd off.
4983 * Make sure vdd is actually turned off here.
4985 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4987 edp_panel_vdd_off_sync(intel_dp
);
4988 pps_unlock(intel_dp
);
4991 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4993 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4994 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4995 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4997 lockdep_assert_held(&dev_priv
->pps_mutex
);
4999 if (!edp_have_panel_vdd(intel_dp
))
5003 * The VDD bit needs a power domain reference, so if the bit is
5004 * already enabled when we boot or resume, grab this reference and
5005 * schedule a vdd off, so we don't hold on to the reference
5008 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5009 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5011 edp_panel_vdd_schedule_off(intel_dp
);
5014 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
5016 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
5018 if ((intel_dp
->DP
& DP_PORT_EN
) == 0)
5019 return INVALID_PIPE
;
5021 if (IS_CHERRYVIEW(dev_priv
))
5022 return DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5024 return PORT_TO_PIPE(intel_dp
->DP
);
5027 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
5029 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
5030 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
5031 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
5033 if (!HAS_DDI(dev_priv
))
5034 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5037 lspcon_resume(lspcon
);
5039 intel_dp
->reset_link_params
= true;
5043 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5044 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5046 if (is_edp(intel_dp
)) {
5047 /* Reinit the power sequencer, in case BIOS did something with it. */
5048 intel_dp_pps_init(encoder
->dev
, intel_dp
);
5049 intel_edp_panel_vdd_sanitize(intel_dp
);
5052 pps_unlock(intel_dp
);
5055 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
5056 .force
= intel_dp_force
,
5057 .fill_modes
= drm_helper_probe_single_connector_modes
,
5058 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
5059 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
5060 .late_register
= intel_dp_connector_register
,
5061 .early_unregister
= intel_dp_connector_unregister
,
5062 .destroy
= intel_dp_connector_destroy
,
5063 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
5064 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5067 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5068 .detect_ctx
= intel_dp_detect
,
5069 .get_modes
= intel_dp_get_modes
,
5070 .mode_valid
= intel_dp_mode_valid
,
5071 .atomic_check
= intel_digital_connector_atomic_check
,
5074 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5075 .reset
= intel_dp_encoder_reset
,
5076 .destroy
= intel_dp_encoder_destroy
,
5080 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5082 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5083 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
5084 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5085 enum irqreturn ret
= IRQ_NONE
;
5087 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
5088 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
5089 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
5091 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5093 * vdd off can generate a long pulse on eDP which
5094 * would require vdd on to handle it, and thus we
5095 * would end up in an endless cycle of
5096 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5098 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5099 port_name(intel_dig_port
->port
));
5103 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5104 port_name(intel_dig_port
->port
),
5105 long_hpd
? "long" : "short");
5108 intel_dp
->reset_link_params
= true;
5109 intel_dp
->detect_done
= false;
5113 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5115 if (intel_dp
->is_mst
) {
5116 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5118 * If we were in MST mode, and device is not
5119 * there, get out of MST mode
5121 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5122 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5123 intel_dp
->is_mst
= false;
5124 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5126 intel_dp
->detect_done
= false;
5131 if (!intel_dp
->is_mst
) {
5132 if (!intel_dp_short_pulse(intel_dp
)) {
5133 intel_dp
->detect_done
= false;
5141 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5146 /* check the VBT to see whether the eDP is on another port */
5147 bool intel_dp_is_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5150 * eDP not supported on g4x. so bail out early just
5151 * for a bit extra safety in case the VBT is bonkers.
5153 if (INTEL_GEN(dev_priv
) < 5)
5156 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5159 return intel_bios_is_port_edp(dev_priv
, port
);
5163 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5165 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5167 intel_attach_force_audio_property(connector
);
5168 intel_attach_broadcast_rgb_property(connector
);
5170 if (is_edp(intel_dp
)) {
5171 u32 allowed_scalers
;
5173 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
5174 if (!HAS_GMCH_DISPLAY(dev_priv
))
5175 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
5177 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
5179 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
5184 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5186 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5187 intel_dp
->last_power_on
= jiffies
;
5188 intel_dp
->last_backlight_off
= jiffies
;
5192 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
5193 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5195 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5196 struct pps_registers regs
;
5198 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5200 /* Workaround: Need to write PP_CONTROL with the unlock key as
5201 * the very first thing. */
5202 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5204 pp_on
= I915_READ(regs
.pp_on
);
5205 pp_off
= I915_READ(regs
.pp_off
);
5206 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
)) {
5207 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5208 pp_div
= I915_READ(regs
.pp_div
);
5211 /* Pull timing values out of registers */
5212 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5213 PANEL_POWER_UP_DELAY_SHIFT
;
5215 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5216 PANEL_LIGHT_ON_DELAY_SHIFT
;
5218 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5219 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5221 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5222 PANEL_POWER_DOWN_DELAY_SHIFT
;
5224 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) {
5225 seq
->t11_t12
= ((pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5226 BXT_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5228 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5229 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5234 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5236 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5238 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5242 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
5243 struct intel_dp
*intel_dp
)
5245 struct edp_power_seq hw
;
5246 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5248 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
5250 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5251 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5252 DRM_ERROR("PPS state mismatch\n");
5253 intel_pps_dump_state("sw", sw
);
5254 intel_pps_dump_state("hw", &hw
);
5259 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5260 struct intel_dp
*intel_dp
)
5262 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5263 struct edp_power_seq cur
, vbt
, spec
,
5264 *final
= &intel_dp
->pps_delays
;
5266 lockdep_assert_held(&dev_priv
->pps_mutex
);
5268 /* already initialized? */
5269 if (final
->t11_t12
!= 0)
5272 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
5274 intel_pps_dump_state("cur", &cur
);
5276 vbt
= dev_priv
->vbt
.edp
.pps
;
5277 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5278 * of 500ms appears to be too short. Ocassionally the panel
5279 * just fails to power back on. Increasing the delay to 800ms
5280 * seems sufficient to avoid this problem.
5282 if (dev_priv
->quirks
& QUIRK_INCREASE_T12_DELAY
) {
5283 vbt
.t11_t12
= max_t(u16
, vbt
.t11_t12
, 1300 * 10);
5284 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5287 /* T11_T12 delay is special and actually in units of 100ms, but zero
5288 * based in the hw (so we need to add 100 ms). But the sw vbt
5289 * table multiplies it with 1000 to make it in units of 100usec,
5291 vbt
.t11_t12
+= 100 * 10;
5293 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5294 * our hw here, which are all in 100usec. */
5295 spec
.t1_t3
= 210 * 10;
5296 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5297 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5298 spec
.t10
= 500 * 10;
5299 /* This one is special and actually in units of 100ms, but zero
5300 * based in the hw (so we need to add 100 ms). But the sw vbt
5301 * table multiplies it with 1000 to make it in units of 100usec,
5303 spec
.t11_t12
= (510 + 100) * 10;
5305 intel_pps_dump_state("vbt", &vbt
);
5307 /* Use the max of the register settings and vbt. If both are
5308 * unset, fall back to the spec limits. */
5309 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5311 max(cur.field, vbt.field))
5312 assign_final(t1_t3
);
5316 assign_final(t11_t12
);
5319 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5320 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5321 intel_dp
->backlight_on_delay
= get_delay(t8
);
5322 intel_dp
->backlight_off_delay
= get_delay(t9
);
5323 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5324 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5327 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5328 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5329 intel_dp
->panel_power_cycle_delay
);
5331 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5332 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5335 * We override the HW backlight delays to 1 because we do manual waits
5336 * on them. For T8, even BSpec recommends doing it. For T9, if we
5337 * don't do this, we'll end up waiting for the backlight off delay
5338 * twice: once when we do the manual sleep, and once when we disable
5339 * the panel and wait for the PP_STATUS bit to become zero.
5346 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5347 struct intel_dp
*intel_dp
,
5348 bool force_disable_vdd
)
5350 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5351 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5352 int div
= dev_priv
->rawclk_freq
/ 1000;
5353 struct pps_registers regs
;
5354 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5355 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5357 lockdep_assert_held(&dev_priv
->pps_mutex
);
5359 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5362 * On some VLV machines the BIOS can leave the VDD
5363 * enabled even on power seqeuencers which aren't
5364 * hooked up to any port. This would mess up the
5365 * power domain tracking the first time we pick
5366 * one of these power sequencers for use since
5367 * edp_panel_vdd_on() would notice that the VDD was
5368 * already on and therefore wouldn't grab the power
5369 * domain reference. Disable VDD first to avoid this.
5370 * This also avoids spuriously turning the VDD on as
5371 * soon as the new power seqeuencer gets initialized.
5373 if (force_disable_vdd
) {
5374 u32 pp
= ironlake_get_pp_control(intel_dp
);
5376 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5378 if (pp
& EDP_FORCE_VDD
)
5379 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5381 pp
&= ~EDP_FORCE_VDD
;
5383 I915_WRITE(regs
.pp_ctrl
, pp
);
5386 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5387 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5388 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5389 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5390 /* Compute the divisor for the pp clock, simply match the Bspec
5392 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) {
5393 pp_div
= I915_READ(regs
.pp_ctrl
);
5394 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5395 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5396 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5398 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5399 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5400 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5403 /* Haswell doesn't have any port selection bits for the panel
5404 * power sequencer any more. */
5405 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5406 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5407 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5409 port_sel
= PANEL_PORT_SELECT_DPA
;
5411 port_sel
= PANEL_PORT_SELECT_DPD
;
5416 I915_WRITE(regs
.pp_on
, pp_on
);
5417 I915_WRITE(regs
.pp_off
, pp_off
);
5418 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
))
5419 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5421 I915_WRITE(regs
.pp_div
, pp_div
);
5423 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5424 I915_READ(regs
.pp_on
),
5425 I915_READ(regs
.pp_off
),
5426 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) ?
5427 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5428 I915_READ(regs
.pp_div
));
5431 static void intel_dp_pps_init(struct drm_device
*dev
,
5432 struct intel_dp
*intel_dp
)
5434 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5436 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5437 vlv_initial_power_sequencer_setup(intel_dp
);
5439 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5440 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
5445 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5446 * @dev_priv: i915 device
5447 * @crtc_state: a pointer to the active intel_crtc_state
5448 * @refresh_rate: RR to be programmed
5450 * This function gets called when refresh rate (RR) has to be changed from
5451 * one frequency to another. Switches can be between high and low RR
5452 * supported by the panel or to any other RR based on media playback (in
5453 * this case, RR value needs to be passed from user space).
5455 * The caller of this function needs to take a lock on dev_priv->drrs.
5457 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5458 struct intel_crtc_state
*crtc_state
,
5461 struct intel_encoder
*encoder
;
5462 struct intel_digital_port
*dig_port
= NULL
;
5463 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5465 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5467 if (refresh_rate
<= 0) {
5468 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5472 if (intel_dp
== NULL
) {
5473 DRM_DEBUG_KMS("DRRS not supported.\n");
5478 * FIXME: This needs proper synchronization with psr state for some
5479 * platforms that cannot have PSR and DRRS enabled at the same time.
5482 dig_port
= dp_to_dig_port(intel_dp
);
5483 encoder
= &dig_port
->base
;
5484 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5487 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5491 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5492 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5496 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5498 index
= DRRS_LOW_RR
;
5500 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5502 "DRRS requested for previously set RR...ignoring\n");
5506 if (!crtc_state
->base
.active
) {
5507 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5511 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5514 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5517 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5521 DRM_ERROR("Unsupported refreshrate type\n");
5523 } else if (INTEL_GEN(dev_priv
) > 6) {
5524 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5527 val
= I915_READ(reg
);
5528 if (index
> DRRS_HIGH_RR
) {
5529 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5530 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5532 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5534 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5535 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5537 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5539 I915_WRITE(reg
, val
);
5542 dev_priv
->drrs
.refresh_rate_type
= index
;
5544 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5548 * intel_edp_drrs_enable - init drrs struct if supported
5549 * @intel_dp: DP struct
5550 * @crtc_state: A pointer to the active crtc state.
5552 * Initializes frontbuffer_bits and drrs.dp
5554 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5555 struct intel_crtc_state
*crtc_state
)
5557 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5558 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5560 if (!crtc_state
->has_drrs
) {
5561 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5565 mutex_lock(&dev_priv
->drrs
.mutex
);
5566 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5567 DRM_ERROR("DRRS already enabled\n");
5571 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5573 dev_priv
->drrs
.dp
= intel_dp
;
5576 mutex_unlock(&dev_priv
->drrs
.mutex
);
5580 * intel_edp_drrs_disable - Disable DRRS
5581 * @intel_dp: DP struct
5582 * @old_crtc_state: Pointer to old crtc_state.
5585 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5586 struct intel_crtc_state
*old_crtc_state
)
5588 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5589 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5591 if (!old_crtc_state
->has_drrs
)
5594 mutex_lock(&dev_priv
->drrs
.mutex
);
5595 if (!dev_priv
->drrs
.dp
) {
5596 mutex_unlock(&dev_priv
->drrs
.mutex
);
5600 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5601 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5602 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5604 dev_priv
->drrs
.dp
= NULL
;
5605 mutex_unlock(&dev_priv
->drrs
.mutex
);
5607 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5610 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5612 struct drm_i915_private
*dev_priv
=
5613 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5614 struct intel_dp
*intel_dp
;
5616 mutex_lock(&dev_priv
->drrs
.mutex
);
5618 intel_dp
= dev_priv
->drrs
.dp
;
5624 * The delayed work can race with an invalidate hence we need to
5628 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5631 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5632 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5634 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5635 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5639 mutex_unlock(&dev_priv
->drrs
.mutex
);
5643 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5644 * @dev_priv: i915 device
5645 * @frontbuffer_bits: frontbuffer plane tracking bits
5647 * This function gets called everytime rendering on the given planes start.
5648 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5650 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5652 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5653 unsigned int frontbuffer_bits
)
5655 struct drm_crtc
*crtc
;
5658 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5661 cancel_delayed_work(&dev_priv
->drrs
.work
);
5663 mutex_lock(&dev_priv
->drrs
.mutex
);
5664 if (!dev_priv
->drrs
.dp
) {
5665 mutex_unlock(&dev_priv
->drrs
.mutex
);
5669 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5670 pipe
= to_intel_crtc(crtc
)->pipe
;
5672 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5673 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5675 /* invalidate means busy screen hence upclock */
5676 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5677 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5678 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5680 mutex_unlock(&dev_priv
->drrs
.mutex
);
5684 * intel_edp_drrs_flush - Restart Idleness DRRS
5685 * @dev_priv: i915 device
5686 * @frontbuffer_bits: frontbuffer plane tracking bits
5688 * This function gets called every time rendering on the given planes has
5689 * completed or flip on a crtc is completed. So DRRS should be upclocked
5690 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5691 * if no other planes are dirty.
5693 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5695 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5696 unsigned int frontbuffer_bits
)
5698 struct drm_crtc
*crtc
;
5701 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5704 cancel_delayed_work(&dev_priv
->drrs
.work
);
5706 mutex_lock(&dev_priv
->drrs
.mutex
);
5707 if (!dev_priv
->drrs
.dp
) {
5708 mutex_unlock(&dev_priv
->drrs
.mutex
);
5712 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5713 pipe
= to_intel_crtc(crtc
)->pipe
;
5715 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5716 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5718 /* flush means busy screen hence upclock */
5719 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5720 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5721 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5724 * flush also means no more activity hence schedule downclock, if all
5725 * other fbs are quiescent too
5727 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5728 schedule_delayed_work(&dev_priv
->drrs
.work
,
5729 msecs_to_jiffies(1000));
5730 mutex_unlock(&dev_priv
->drrs
.mutex
);
5734 * DOC: Display Refresh Rate Switching (DRRS)
5736 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5737 * which enables swtching between low and high refresh rates,
5738 * dynamically, based on the usage scenario. This feature is applicable
5739 * for internal panels.
5741 * Indication that the panel supports DRRS is given by the panel EDID, which
5742 * would list multiple refresh rates for one resolution.
5744 * DRRS is of 2 types - static and seamless.
5745 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5746 * (may appear as a blink on screen) and is used in dock-undock scenario.
5747 * Seamless DRRS involves changing RR without any visual effect to the user
5748 * and can be used during normal system usage. This is done by programming
5749 * certain registers.
5751 * Support for static/seamless DRRS may be indicated in the VBT based on
5752 * inputs from the panel spec.
5754 * DRRS saves power by switching to low RR based on usage scenarios.
5756 * The implementation is based on frontbuffer tracking implementation. When
5757 * there is a disturbance on the screen triggered by user activity or a periodic
5758 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5759 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5762 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5763 * and intel_edp_drrs_flush() are called.
5765 * DRRS can be further extended to support other internal panels and also
5766 * the scenario of video playback wherein RR is set based on the rate
5767 * requested by userspace.
5771 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5772 * @intel_connector: eDP connector
5773 * @fixed_mode: preferred mode of panel
5775 * This function is called only once at driver load to initialize basic
5779 * Downclock mode if panel supports it, else return NULL.
5780 * DRRS support is determined by the presence of downclock mode (apart
5781 * from VBT setting).
5783 static struct drm_display_mode
*
5784 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5785 struct drm_display_mode
*fixed_mode
)
5787 struct drm_connector
*connector
= &intel_connector
->base
;
5788 struct drm_device
*dev
= connector
->dev
;
5789 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5790 struct drm_display_mode
*downclock_mode
= NULL
;
5792 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5793 mutex_init(&dev_priv
->drrs
.mutex
);
5795 if (INTEL_GEN(dev_priv
) <= 6) {
5796 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5800 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5801 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5805 downclock_mode
= intel_find_panel_downclock
5806 (dev_priv
, fixed_mode
, connector
);
5808 if (!downclock_mode
) {
5809 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5813 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5815 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5816 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5817 return downclock_mode
;
5820 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5821 struct intel_connector
*intel_connector
)
5823 struct drm_connector
*connector
= &intel_connector
->base
;
5824 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5825 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5826 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5827 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5828 struct drm_display_mode
*fixed_mode
= NULL
;
5829 struct drm_display_mode
*alt_fixed_mode
= NULL
;
5830 struct drm_display_mode
*downclock_mode
= NULL
;
5832 struct drm_display_mode
*scan
;
5834 enum pipe pipe
= INVALID_PIPE
;
5836 if (!is_edp(intel_dp
))
5840 * On IBX/CPT we may get here with LVDS already registered. Since the
5841 * driver uses the only internal power sequencer available for both
5842 * eDP and LVDS bail out early in this case to prevent interfering
5843 * with an already powered-on LVDS power sequencer.
5845 if (intel_get_lvds_encoder(dev
)) {
5846 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5847 DRM_INFO("LVDS was detected, not registering eDP\n");
5854 intel_dp_init_panel_power_timestamps(intel_dp
);
5855 intel_dp_pps_init(dev
, intel_dp
);
5856 intel_edp_panel_vdd_sanitize(intel_dp
);
5858 pps_unlock(intel_dp
);
5860 /* Cache DPCD and EDID for edp. */
5861 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5864 /* if this fails, presume the device is a ghost */
5865 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5869 mutex_lock(&dev
->mode_config
.mutex
);
5870 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5872 if (drm_add_edid_modes(connector
, edid
)) {
5873 drm_mode_connector_update_edid_property(connector
,
5875 drm_edid_to_eld(connector
, edid
);
5878 edid
= ERR_PTR(-EINVAL
);
5881 edid
= ERR_PTR(-ENOENT
);
5883 intel_connector
->edid
= edid
;
5885 /* prefer fixed mode from EDID if available, save an alt mode also */
5886 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5887 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5888 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5889 downclock_mode
= intel_dp_drrs_init(
5890 intel_connector
, fixed_mode
);
5891 } else if (!alt_fixed_mode
) {
5892 alt_fixed_mode
= drm_mode_duplicate(dev
, scan
);
5896 /* fallback to VBT if available for eDP */
5897 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5898 fixed_mode
= drm_mode_duplicate(dev
,
5899 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5901 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5902 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5903 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5906 mutex_unlock(&dev
->mode_config
.mutex
);
5908 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5909 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5910 register_reboot_notifier(&intel_dp
->edp_notifier
);
5913 * Figure out the current pipe for the initial backlight setup.
5914 * If the current pipe isn't valid, try the PPS pipe, and if that
5915 * fails just assume pipe A.
5917 pipe
= vlv_active_pipe(intel_dp
);
5919 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5920 pipe
= intel_dp
->pps_pipe
;
5922 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5925 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5929 intel_panel_init(&intel_connector
->panel
, fixed_mode
, alt_fixed_mode
,
5931 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5932 intel_panel_setup_backlight(connector
, pipe
);
5937 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5939 * vdd might still be enabled do to the delayed vdd off.
5940 * Make sure vdd is actually turned off here.
5943 edp_panel_vdd_off_sync(intel_dp
);
5944 pps_unlock(intel_dp
);
5949 /* Set up the hotplug pin and aux power domain. */
5951 intel_dp_init_connector_port_info(struct intel_digital_port
*intel_dig_port
)
5953 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
5954 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5956 encoder
->hpd_pin
= intel_hpd_pin(intel_dig_port
->port
);
5958 switch (intel_dig_port
->port
) {
5960 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_A
;
5963 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_B
;
5966 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_C
;
5969 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5972 /* FIXME: Check VBT for actual wiring of PORT E */
5973 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5976 MISSING_CASE(intel_dig_port
->port
);
5980 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
5982 struct intel_connector
*intel_connector
;
5983 struct drm_connector
*connector
;
5985 intel_connector
= container_of(work
, typeof(*intel_connector
),
5986 modeset_retry_work
);
5987 connector
= &intel_connector
->base
;
5988 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
5991 /* Grab the locks before changing connector property*/
5992 mutex_lock(&connector
->dev
->mode_config
.mutex
);
5993 /* Set connector link status to BAD and send a Uevent to notify
5994 * userspace to do a modeset.
5996 drm_mode_connector_set_link_status_property(connector
,
5997 DRM_MODE_LINK_STATUS_BAD
);
5998 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
5999 /* Send Hotplug uevent so userspace can reprobe */
6000 drm_kms_helper_hotplug_event(connector
->dev
);
6004 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
6005 struct intel_connector
*intel_connector
)
6007 struct drm_connector
*connector
= &intel_connector
->base
;
6008 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
6009 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
6010 struct drm_device
*dev
= intel_encoder
->base
.dev
;
6011 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6012 enum port port
= intel_dig_port
->port
;
6015 /* Initialize the work for modeset in case of link train failure */
6016 INIT_WORK(&intel_connector
->modeset_retry_work
,
6017 intel_dp_modeset_retry_work_fn
);
6019 if (WARN(intel_dig_port
->max_lanes
< 1,
6020 "Not enough lanes (%d) for DP on port %c\n",
6021 intel_dig_port
->max_lanes
, port_name(port
)))
6024 intel_dp_set_source_rates(intel_dp
);
6026 intel_dp
->reset_link_params
= true;
6027 intel_dp
->pps_pipe
= INVALID_PIPE
;
6028 intel_dp
->active_pipe
= INVALID_PIPE
;
6030 /* intel_dp vfuncs */
6031 if (INTEL_GEN(dev_priv
) >= 9)
6032 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
6033 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6034 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
6035 else if (HAS_PCH_SPLIT(dev_priv
))
6036 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
6038 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
6040 if (INTEL_GEN(dev_priv
) >= 9)
6041 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
6043 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
6045 if (HAS_DDI(dev_priv
))
6046 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
6048 /* Preserve the current hw state. */
6049 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
6050 intel_dp
->attached_connector
= intel_connector
;
6052 if (intel_dp_is_edp(dev_priv
, port
))
6053 type
= DRM_MODE_CONNECTOR_eDP
;
6055 type
= DRM_MODE_CONNECTOR_DisplayPort
;
6057 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6058 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
6061 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6062 * for DP the encoder type can be set by the caller to
6063 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6065 if (type
== DRM_MODE_CONNECTOR_eDP
)
6066 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
6068 /* eDP only on port B and/or C on vlv/chv */
6069 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
6070 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
6073 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6074 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6077 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6078 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6080 connector
->interlace_allowed
= true;
6081 connector
->doublescan_allowed
= 0;
6083 intel_dp_init_connector_port_info(intel_dig_port
);
6085 intel_dp_aux_init(intel_dp
);
6087 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6088 edp_panel_vdd_work
);
6090 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6092 if (HAS_DDI(dev_priv
))
6093 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6095 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6097 /* init MST on ports that can support it */
6098 if (HAS_DP_MST(dev_priv
) && !is_edp(intel_dp
) &&
6099 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
6100 intel_dp_mst_encoder_init(intel_dig_port
,
6101 intel_connector
->base
.base
.id
);
6103 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6104 intel_dp_aux_fini(intel_dp
);
6105 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6109 intel_dp_add_properties(intel_dp
, connector
);
6111 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6112 * 0xd. Failure to do so will result in spurious interrupts being
6113 * generated on the port when a cable is not attached.
6115 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
6116 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6117 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6123 drm_connector_cleanup(connector
);
6128 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6129 i915_reg_t output_reg
,
6132 struct intel_digital_port
*intel_dig_port
;
6133 struct intel_encoder
*intel_encoder
;
6134 struct drm_encoder
*encoder
;
6135 struct intel_connector
*intel_connector
;
6137 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6138 if (!intel_dig_port
)
6141 intel_connector
= intel_connector_alloc();
6142 if (!intel_connector
)
6143 goto err_connector_alloc
;
6145 intel_encoder
= &intel_dig_port
->base
;
6146 encoder
= &intel_encoder
->base
;
6148 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6149 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6150 "DP %c", port_name(port
)))
6151 goto err_encoder_init
;
6153 intel_encoder
->compute_config
= intel_dp_compute_config
;
6154 intel_encoder
->disable
= intel_disable_dp
;
6155 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6156 intel_encoder
->get_config
= intel_dp_get_config
;
6157 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6158 if (IS_CHERRYVIEW(dev_priv
)) {
6159 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6160 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6161 intel_encoder
->enable
= vlv_enable_dp
;
6162 intel_encoder
->post_disable
= chv_post_disable_dp
;
6163 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6164 } else if (IS_VALLEYVIEW(dev_priv
)) {
6165 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6166 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6167 intel_encoder
->enable
= vlv_enable_dp
;
6168 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6170 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6171 intel_encoder
->enable
= g4x_enable_dp
;
6172 if (INTEL_GEN(dev_priv
) >= 5)
6173 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6176 intel_dig_port
->port
= port
;
6177 intel_dig_port
->dp
.output_reg
= output_reg
;
6178 intel_dig_port
->max_lanes
= 4;
6180 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6181 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6182 if (IS_CHERRYVIEW(dev_priv
)) {
6184 intel_encoder
->crtc_mask
= 1 << 2;
6186 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6188 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6190 intel_encoder
->cloneable
= 0;
6191 intel_encoder
->port
= port
;
6193 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6194 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6196 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6197 goto err_init_connector
;
6202 drm_encoder_cleanup(encoder
);
6204 kfree(intel_connector
);
6205 err_connector_alloc
:
6206 kfree(intel_dig_port
);
6210 void intel_dp_mst_suspend(struct drm_device
*dev
)
6212 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6216 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6217 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6219 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6222 if (intel_dig_port
->dp
.is_mst
)
6223 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6227 void intel_dp_mst_resume(struct drm_device
*dev
)
6229 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6232 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6233 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6236 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6239 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6241 intel_dp_check_mst_status(&intel_dig_port
->dp
);