2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
49 static const struct dp_link_dpll gen4_dpll
[] = {
51 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
53 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
56 static const struct dp_link_dpll pch_dpll
[] = {
58 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
60 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
63 static const struct dp_link_dpll vlv_dpll
[] = {
65 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
67 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
74 static const struct dp_link_dpll chv_dpll
[] = {
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
80 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
82 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
83 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
84 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
85 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
89 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
90 * @intel_dp: DP struct
92 * If a CPU or PCH DP output is attached to an eDP panel, this function
93 * will return true, and false otherwise.
95 static bool is_edp(struct intel_dp
*intel_dp
)
97 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
99 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
102 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
104 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
106 return intel_dig_port
->base
.base
.dev
;
109 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
111 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
114 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
115 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
116 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
117 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
118 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
122 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
124 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
125 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
127 switch (max_link_bw
) {
128 case DP_LINK_BW_1_62
:
131 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
132 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
133 INTEL_INFO(dev
)->gen
>= 8) &&
134 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
135 max_link_bw
= DP_LINK_BW_5_4
;
137 max_link_bw
= DP_LINK_BW_2_7
;
140 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
142 max_link_bw
= DP_LINK_BW_1_62
;
148 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
150 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
151 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
152 u8 source_max
, sink_max
;
155 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
156 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector
*connector
,
195 struct drm_display_mode
*mode
)
197 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
198 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
199 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
200 int target_clock
= mode
->clock
;
201 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
203 if (is_edp(intel_dp
) && fixed_mode
) {
204 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
207 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
210 target_clock
= fixed_mode
->clock
;
213 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
214 max_lanes
= intel_dp_max_lane_count(intel_dp
);
216 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
217 mode_rate
= intel_dp_link_required(target_clock
, 18);
219 if (mode_rate
> max_rate
)
220 return MODE_CLOCK_HIGH
;
222 if (mode
->clock
< 10000)
223 return MODE_CLOCK_LOW
;
225 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
226 return MODE_H_ILLEGAL
;
231 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
238 for (i
= 0; i
< src_bytes
; i
++)
239 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
243 void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
248 for (i
= 0; i
< dst_bytes
; i
++)
249 dst
[i
] = src
>> ((3-i
) * 8);
252 /* hrawclock is 1/4 the FSB frequency */
254 intel_hrawclk(struct drm_device
*dev
)
256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
259 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
260 if (IS_VALLEYVIEW(dev
))
263 clkcfg
= I915_READ(CLKCFG
);
264 switch (clkcfg
& CLKCFG_FSB_MASK
) {
273 case CLKCFG_FSB_1067
:
275 case CLKCFG_FSB_1333
:
277 /* these two are just a guess; one of them might be right */
278 case CLKCFG_FSB_1600
:
279 case CLKCFG_FSB_1600_ALT
:
287 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
288 struct intel_dp
*intel_dp
);
290 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
291 struct intel_dp
*intel_dp
);
293 static void pps_lock(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
297 struct drm_device
*dev
= encoder
->base
.dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 enum intel_display_power_domain power_domain
;
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
305 power_domain
= intel_display_port_power_domain(encoder
);
306 intel_display_power_get(dev_priv
, power_domain
);
308 mutex_lock(&dev_priv
->pps_mutex
);
311 static void pps_unlock(struct intel_dp
*intel_dp
)
313 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
314 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
315 struct drm_device
*dev
= encoder
->base
.dev
;
316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 enum intel_display_power_domain power_domain
;
319 mutex_unlock(&dev_priv
->pps_mutex
);
321 power_domain
= intel_display_port_power_domain(encoder
);
322 intel_display_power_put(dev_priv
, power_domain
);
326 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
328 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
329 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
331 enum pipe pipe
= intel_dp
->pps_pipe
;
335 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
336 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
337 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
340 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
341 pipe_name(pipe
), port_name(intel_dig_port
->port
));
343 /* Preserve the BIOS-computed detected bit. This is
344 * supposed to be read-only.
346 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
347 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
348 DP
|= DP_PORT_WIDTH(1);
349 DP
|= DP_LINK_TRAIN_PAT_1
;
351 if (IS_CHERRYVIEW(dev
))
352 DP
|= DP_PIPE_SELECT_CHV(pipe
);
353 else if (pipe
== PIPE_B
)
354 DP
|= DP_PIPEB_SELECT
;
356 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
359 * The DPLL for the pipe must be enabled for this to work.
360 * So enable temporarily it if it's not already enabled.
363 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
364 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
367 * Similar magic as in intel_dp_enable_port().
368 * We _must_ do this port enable + disable trick
369 * to make this power seqeuencer lock onto the port.
370 * Otherwise even VDD force bit won't work.
372 I915_WRITE(intel_dp
->output_reg
, DP
);
373 POSTING_READ(intel_dp
->output_reg
);
375 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
376 POSTING_READ(intel_dp
->output_reg
);
378 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
379 POSTING_READ(intel_dp
->output_reg
);
382 vlv_force_pll_off(dev
, pipe
);
386 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
388 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
389 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
391 struct intel_encoder
*encoder
;
392 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
395 lockdep_assert_held(&dev_priv
->pps_mutex
);
397 /* We should never land here with regular DP ports */
398 WARN_ON(!is_edp(intel_dp
));
400 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
401 return intel_dp
->pps_pipe
;
404 * We don't have power sequencer currently.
405 * Pick one that's not used by other ports.
407 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
409 struct intel_dp
*tmp
;
411 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
414 tmp
= enc_to_intel_dp(&encoder
->base
);
416 if (tmp
->pps_pipe
!= INVALID_PIPE
)
417 pipes
&= ~(1 << tmp
->pps_pipe
);
421 * Didn't find one. This should not happen since there
422 * are two power sequencers and up to two eDP ports.
424 if (WARN_ON(pipes
== 0))
427 pipe
= ffs(pipes
) - 1;
429 vlv_steal_power_sequencer(dev
, pipe
);
430 intel_dp
->pps_pipe
= pipe
;
432 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
433 pipe_name(intel_dp
->pps_pipe
),
434 port_name(intel_dig_port
->port
));
436 /* init power sequencer on this pipe and port */
437 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
438 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
441 * Even vdd force doesn't work until we've made
442 * the power sequencer lock in on the port.
444 vlv_power_sequencer_kick(intel_dp
);
446 return intel_dp
->pps_pipe
;
449 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
452 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
455 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
458 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
461 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
464 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
471 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
473 vlv_pipe_check pipe_check
)
477 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
478 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
479 PANEL_PORT_SELECT_MASK
;
481 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
484 if (!pipe_check(dev_priv
, pipe
))
494 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
496 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
497 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
499 enum port port
= intel_dig_port
->port
;
501 lockdep_assert_held(&dev_priv
->pps_mutex
);
503 /* try to find a pipe with this port selected */
504 /* first pick one where the panel is on */
505 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
507 /* didn't find one? pick one where vdd is on */
508 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
509 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
510 vlv_pipe_has_vdd_on
);
511 /* didn't find one? pick one with just the correct port */
512 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
513 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
516 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
517 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
518 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
523 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
524 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
526 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
527 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
530 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
532 struct drm_device
*dev
= dev_priv
->dev
;
533 struct intel_encoder
*encoder
;
535 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
539 * We can't grab pps_mutex here due to deadlock with power_domain
540 * mutex when power_domain functions are called while holding pps_mutex.
541 * That also means that in order to use pps_pipe the code needs to
542 * hold both a power domain reference and pps_mutex, and the power domain
543 * reference get/put must be done while _not_ holding pps_mutex.
544 * pps_{lock,unlock}() do these steps in the correct order, so one
545 * should use them always.
548 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
549 struct intel_dp
*intel_dp
;
551 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
554 intel_dp
= enc_to_intel_dp(&encoder
->base
);
555 intel_dp
->pps_pipe
= INVALID_PIPE
;
559 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
561 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
563 if (HAS_PCH_SPLIT(dev
))
564 return PCH_PP_CONTROL
;
566 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
569 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
571 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
573 if (HAS_PCH_SPLIT(dev
))
574 return PCH_PP_STATUS
;
576 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
579 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
580 This function only applicable when panel PM state is not to be tracked */
581 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
584 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
586 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
589 u32 pp_ctrl_reg
, pp_div_reg
;
591 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
596 if (IS_VALLEYVIEW(dev
)) {
597 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
599 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
600 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
601 pp_div
= I915_READ(pp_div_reg
);
602 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
604 /* 0x1F write to PP_DIV_REG sets max cycle delay */
605 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
606 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
607 msleep(intel_dp
->panel_power_cycle_delay
);
610 pps_unlock(intel_dp
);
615 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
617 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
620 lockdep_assert_held(&dev_priv
->pps_mutex
);
622 if (IS_VALLEYVIEW(dev
) &&
623 intel_dp
->pps_pipe
== INVALID_PIPE
)
626 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
629 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
631 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
634 lockdep_assert_held(&dev_priv
->pps_mutex
);
636 if (IS_VALLEYVIEW(dev
) &&
637 intel_dp
->pps_pipe
== INVALID_PIPE
)
640 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
644 intel_dp_check_edp(struct intel_dp
*intel_dp
)
646 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
649 if (!is_edp(intel_dp
))
652 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
653 WARN(1, "eDP powered off while attempting aux channel communication.\n");
654 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
655 I915_READ(_pp_stat_reg(intel_dp
)),
656 I915_READ(_pp_ctrl_reg(intel_dp
)));
661 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
663 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
664 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
670 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
672 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
673 msecs_to_jiffies_timeout(10));
675 done
= wait_for_atomic(C
, 10) == 0;
677 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
684 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
686 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
687 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
690 * The clock divider is based off the hrawclk, and would like to run at
691 * 2MHz. So, take the hrawclk value and divide by 2 and use that
693 return index
? 0 : intel_hrawclk(dev
) / 2;
696 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
698 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
699 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
704 if (intel_dig_port
->port
== PORT_A
) {
705 if (IS_GEN6(dev
) || IS_GEN7(dev
))
706 return 200; /* SNB & IVB eDP input clock at 400Mhz */
708 return 225; /* eDP input clock at 450Mhz */
710 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
714 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
716 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
717 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
720 if (intel_dig_port
->port
== PORT_A
) {
723 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
724 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
725 /* Workaround for non-ULT HSW */
732 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
736 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
738 return index
? 0 : 100;
741 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
744 * SKL doesn't need us to program the AUX clock divider (Hardware will
745 * derive the clock from CDCLK automatically). We still implement the
746 * get_aux_clock_divider vfunc to plug-in into the existing code.
748 return index
? 0 : 1;
751 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
754 uint32_t aux_clock_divider
)
756 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
757 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
758 uint32_t precharge
, timeout
;
765 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
766 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
768 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
770 return DP_AUX_CH_CTL_SEND_BUSY
|
772 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
773 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
775 DP_AUX_CH_CTL_RECEIVE_ERROR
|
776 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
777 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
778 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
781 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
786 return DP_AUX_CH_CTL_SEND_BUSY
|
788 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
789 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
790 DP_AUX_CH_CTL_TIME_OUT_1600us
|
791 DP_AUX_CH_CTL_RECEIVE_ERROR
|
792 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
793 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
797 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
798 const uint8_t *send
, int send_bytes
,
799 uint8_t *recv
, int recv_size
)
801 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
802 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
804 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
805 uint32_t ch_data
= ch_ctl
+ 4;
806 uint32_t aux_clock_divider
;
807 int i
, ret
, recv_bytes
;
810 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
816 * We will be called with VDD already enabled for dpcd/edid/oui reads.
817 * In such cases we want to leave VDD enabled and it's up to upper layers
818 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
821 vdd
= edp_panel_vdd_on(intel_dp
);
823 /* dp aux is extremely sensitive to irq latency, hence request the
824 * lowest possible wakeup latency and so prevent the cpu from going into
827 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
829 intel_dp_check_edp(intel_dp
);
831 intel_aux_display_runtime_get(dev_priv
);
833 /* Try to wait for any previous AUX channel activity */
834 for (try = 0; try < 3; try++) {
835 status
= I915_READ_NOTRACE(ch_ctl
);
836 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
842 WARN(1, "dp_aux_ch not started status 0x%08x\n",
848 /* Only 5 data registers! */
849 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
854 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
855 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
860 /* Must try at least 3 times according to DP spec */
861 for (try = 0; try < 5; try++) {
862 /* Load the send data into the aux channel data registers */
863 for (i
= 0; i
< send_bytes
; i
+= 4)
864 I915_WRITE(ch_data
+ i
,
865 intel_dp_pack_aux(send
+ i
,
868 /* Send the command and wait for it to complete */
869 I915_WRITE(ch_ctl
, send_ctl
);
871 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
873 /* Clear done status and any errors */
877 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
878 DP_AUX_CH_CTL_RECEIVE_ERROR
);
880 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
881 DP_AUX_CH_CTL_RECEIVE_ERROR
))
883 if (status
& DP_AUX_CH_CTL_DONE
)
886 if (status
& DP_AUX_CH_CTL_DONE
)
890 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
891 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
899 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
907 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
913 /* Unload any bytes sent back from the other side */
914 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
916 if (recv_bytes
> recv_size
)
917 recv_bytes
= recv_size
;
919 for (i
= 0; i
< recv_bytes
; i
+= 4)
920 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
921 recv
+ i
, recv_bytes
- i
);
925 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
926 intel_aux_display_runtime_put(dev_priv
);
929 edp_panel_vdd_off(intel_dp
, false);
931 pps_unlock(intel_dp
);
936 #define BARE_ADDRESS_SIZE 3
937 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
939 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
941 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
942 uint8_t txbuf
[20], rxbuf
[20];
943 size_t txsize
, rxsize
;
946 txbuf
[0] = msg
->request
<< 4;
947 txbuf
[1] = msg
->address
>> 8;
948 txbuf
[2] = msg
->address
& 0xff;
949 txbuf
[3] = msg
->size
- 1;
951 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
952 case DP_AUX_NATIVE_WRITE
:
953 case DP_AUX_I2C_WRITE
:
954 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
957 if (WARN_ON(txsize
> 20))
960 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
962 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
964 msg
->reply
= rxbuf
[0] >> 4;
966 /* Return payload size. */
971 case DP_AUX_NATIVE_READ
:
972 case DP_AUX_I2C_READ
:
973 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
974 rxsize
= msg
->size
+ 1;
976 if (WARN_ON(rxsize
> 20))
979 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
981 msg
->reply
= rxbuf
[0] >> 4;
983 * Assume happy day, and copy the data. The caller is
984 * expected to check msg->reply before touching it.
986 * Return payload size.
989 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1002 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1004 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1005 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1006 enum port port
= intel_dig_port
->port
;
1007 const char *name
= NULL
;
1012 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1016 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1020 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1024 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1032 * The AUX_CTL register is usually DP_CTL + 0x10.
1034 * On Haswell and Broadwell though:
1035 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1036 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1038 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1040 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1041 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1043 intel_dp
->aux
.name
= name
;
1044 intel_dp
->aux
.dev
= dev
->dev
;
1045 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1047 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1048 connector
->base
.kdev
->kobj
.name
);
1050 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1052 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1057 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1058 &intel_dp
->aux
.ddc
.dev
.kobj
,
1059 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1061 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1062 drm_dp_aux_unregister(&intel_dp
->aux
);
1067 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1069 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1071 if (!intel_connector
->mst_port
)
1072 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1073 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1074 intel_connector_unregister(intel_connector
);
1078 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_bw
)
1082 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1083 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1084 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1086 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1088 case DP_LINK_BW_1_62
:
1089 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810
,
1092 case DP_LINK_BW_2_7
:
1093 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350
,
1096 case DP_LINK_BW_5_4
:
1097 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700
,
1101 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1105 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1108 case DP_LINK_BW_1_62
:
1109 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1111 case DP_LINK_BW_2_7
:
1112 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1114 case DP_LINK_BW_5_4
:
1115 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1121 intel_dp_set_clock(struct intel_encoder
*encoder
,
1122 struct intel_crtc_state
*pipe_config
, int link_bw
)
1124 struct drm_device
*dev
= encoder
->base
.dev
;
1125 const struct dp_link_dpll
*divisor
= NULL
;
1129 divisor
= gen4_dpll
;
1130 count
= ARRAY_SIZE(gen4_dpll
);
1131 } else if (HAS_PCH_SPLIT(dev
)) {
1133 count
= ARRAY_SIZE(pch_dpll
);
1134 } else if (IS_CHERRYVIEW(dev
)) {
1136 count
= ARRAY_SIZE(chv_dpll
);
1137 } else if (IS_VALLEYVIEW(dev
)) {
1139 count
= ARRAY_SIZE(vlv_dpll
);
1142 if (divisor
&& count
) {
1143 for (i
= 0; i
< count
; i
++) {
1144 if (link_bw
== divisor
[i
].link_bw
) {
1145 pipe_config
->dpll
= divisor
[i
].dpll
;
1146 pipe_config
->clock_set
= true;
1154 intel_dp_compute_config(struct intel_encoder
*encoder
,
1155 struct intel_crtc_state
*pipe_config
)
1157 struct drm_device
*dev
= encoder
->base
.dev
;
1158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1159 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1160 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1161 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1162 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1163 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1164 int lane_count
, clock
;
1165 int min_lane_count
= 1;
1166 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1167 /* Conveniently, the link BW constants become indices with a shift...*/
1169 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1171 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1172 int link_avail
, link_clock
;
1174 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1175 pipe_config
->has_pch_encoder
= true;
1177 pipe_config
->has_dp_encoder
= true;
1178 pipe_config
->has_drrs
= false;
1179 pipe_config
->has_audio
= intel_dp
->has_audio
;
1181 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1182 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1184 if (!HAS_PCH_SPLIT(dev
))
1185 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1186 intel_connector
->panel
.fitting_mode
);
1188 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1189 intel_connector
->panel
.fitting_mode
);
1192 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1195 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1196 "max bw %02x pixel clock %iKHz\n",
1197 max_lane_count
, bws
[max_clock
],
1198 adjusted_mode
->crtc_clock
);
1200 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1201 * bpc in between. */
1202 bpp
= pipe_config
->pipe_bpp
;
1203 if (is_edp(intel_dp
)) {
1204 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1205 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1206 dev_priv
->vbt
.edp_bpp
);
1207 bpp
= dev_priv
->vbt
.edp_bpp
;
1211 * Use the maximum clock and number of lanes the eDP panel
1212 * advertizes being capable of. The panels are generally
1213 * designed to support only a single clock and lane
1214 * configuration, and typically these values correspond to the
1215 * native resolution of the panel.
1217 min_lane_count
= max_lane_count
;
1218 min_clock
= max_clock
;
1221 for (; bpp
>= 6*3; bpp
-= 2*3) {
1222 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1225 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1226 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1227 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1228 link_avail
= intel_dp_max_data_rate(link_clock
,
1231 if (mode_rate
<= link_avail
) {
1241 if (intel_dp
->color_range_auto
) {
1244 * CEA-861-E - 5.1 Default Encoding Parameters
1245 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1247 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1248 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1250 intel_dp
->color_range
= 0;
1253 if (intel_dp
->color_range
)
1254 pipe_config
->limited_color_range
= true;
1256 intel_dp
->link_bw
= bws
[clock
];
1257 intel_dp
->lane_count
= lane_count
;
1258 pipe_config
->pipe_bpp
= bpp
;
1259 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1261 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1262 intel_dp
->link_bw
, intel_dp
->lane_count
,
1263 pipe_config
->port_clock
, bpp
);
1264 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1265 mode_rate
, link_avail
);
1267 intel_link_compute_m_n(bpp
, lane_count
,
1268 adjusted_mode
->crtc_clock
,
1269 pipe_config
->port_clock
,
1270 &pipe_config
->dp_m_n
);
1272 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1273 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1274 pipe_config
->has_drrs
= true;
1275 intel_link_compute_m_n(bpp
, lane_count
,
1276 intel_connector
->panel
.downclock_mode
->clock
,
1277 pipe_config
->port_clock
,
1278 &pipe_config
->dp_m2_n2
);
1281 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1282 skl_edp_set_pll_config(pipe_config
, intel_dp
->link_bw
);
1283 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1284 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1286 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1291 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1293 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1294 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1295 struct drm_device
*dev
= crtc
->base
.dev
;
1296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1299 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1300 crtc
->config
->port_clock
);
1301 dpa_ctl
= I915_READ(DP_A
);
1302 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1304 if (crtc
->config
->port_clock
== 162000) {
1305 /* For a long time we've carried around a ILK-DevA w/a for the
1306 * 160MHz clock. If we're really unlucky, it's still required.
1308 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1309 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1310 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1312 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1313 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1316 I915_WRITE(DP_A
, dpa_ctl
);
1322 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1324 struct drm_device
*dev
= encoder
->base
.dev
;
1325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1326 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1327 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1328 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1329 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1332 * There are four kinds of DP registers:
1339 * IBX PCH and CPU are the same for almost everything,
1340 * except that the CPU DP PLL is configured in this
1343 * CPT PCH is quite different, having many bits moved
1344 * to the TRANS_DP_CTL register instead. That
1345 * configuration happens (oddly) in ironlake_pch_enable
1348 /* Preserve the BIOS-computed detected bit. This is
1349 * supposed to be read-only.
1351 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1353 /* Handle DP bits in common between all three register formats */
1354 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1355 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1357 if (crtc
->config
->has_audio
)
1358 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1360 /* Split out the IBX/CPU vs CPT settings */
1362 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1363 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1364 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1365 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1366 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1367 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1369 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1370 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1372 intel_dp
->DP
|= crtc
->pipe
<< 29;
1373 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1374 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1375 intel_dp
->DP
|= intel_dp
->color_range
;
1377 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1378 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1379 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1380 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1381 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1383 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1384 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1386 if (!IS_CHERRYVIEW(dev
)) {
1387 if (crtc
->pipe
== 1)
1388 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1390 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1393 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1397 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1398 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1400 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1401 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1403 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1404 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1406 static void wait_panel_status(struct intel_dp
*intel_dp
,
1410 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1412 u32 pp_stat_reg
, pp_ctrl_reg
;
1414 lockdep_assert_held(&dev_priv
->pps_mutex
);
1416 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1417 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1419 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1421 I915_READ(pp_stat_reg
),
1422 I915_READ(pp_ctrl_reg
));
1424 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1425 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1426 I915_READ(pp_stat_reg
),
1427 I915_READ(pp_ctrl_reg
));
1430 DRM_DEBUG_KMS("Wait complete\n");
1433 static void wait_panel_on(struct intel_dp
*intel_dp
)
1435 DRM_DEBUG_KMS("Wait for panel power on\n");
1436 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1439 static void wait_panel_off(struct intel_dp
*intel_dp
)
1441 DRM_DEBUG_KMS("Wait for panel power off time\n");
1442 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1445 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1447 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1449 /* When we disable the VDD override bit last we have to do the manual
1451 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1452 intel_dp
->panel_power_cycle_delay
);
1454 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1457 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1459 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1460 intel_dp
->backlight_on_delay
);
1463 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1465 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1466 intel_dp
->backlight_off_delay
);
1469 /* Read the current pp_control value, unlocking the register if it
1473 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1475 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1479 lockdep_assert_held(&dev_priv
->pps_mutex
);
1481 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1482 control
&= ~PANEL_UNLOCK_MASK
;
1483 control
|= PANEL_UNLOCK_REGS
;
1488 * Must be paired with edp_panel_vdd_off().
1489 * Must hold pps_mutex around the whole on/off sequence.
1490 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1492 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1494 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1495 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1496 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1498 enum intel_display_power_domain power_domain
;
1500 u32 pp_stat_reg
, pp_ctrl_reg
;
1501 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1503 lockdep_assert_held(&dev_priv
->pps_mutex
);
1505 if (!is_edp(intel_dp
))
1508 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1509 intel_dp
->want_panel_vdd
= true;
1511 if (edp_have_panel_vdd(intel_dp
))
1512 return need_to_disable
;
1514 power_domain
= intel_display_port_power_domain(intel_encoder
);
1515 intel_display_power_get(dev_priv
, power_domain
);
1517 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1518 port_name(intel_dig_port
->port
));
1520 if (!edp_have_panel_power(intel_dp
))
1521 wait_panel_power_cycle(intel_dp
);
1523 pp
= ironlake_get_pp_control(intel_dp
);
1524 pp
|= EDP_FORCE_VDD
;
1526 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1527 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1529 I915_WRITE(pp_ctrl_reg
, pp
);
1530 POSTING_READ(pp_ctrl_reg
);
1531 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1532 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1534 * If the panel wasn't on, delay before accessing aux channel
1536 if (!edp_have_panel_power(intel_dp
)) {
1537 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1538 port_name(intel_dig_port
->port
));
1539 msleep(intel_dp
->panel_power_up_delay
);
1542 return need_to_disable
;
1546 * Must be paired with intel_edp_panel_vdd_off() or
1547 * intel_edp_panel_off().
1548 * Nested calls to these functions are not allowed since
1549 * we drop the lock. Caller must use some higher level
1550 * locking to prevent nested calls from other threads.
1552 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1556 if (!is_edp(intel_dp
))
1560 vdd
= edp_panel_vdd_on(intel_dp
);
1561 pps_unlock(intel_dp
);
1563 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1564 port_name(dp_to_dig_port(intel_dp
)->port
));
1567 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1569 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1571 struct intel_digital_port
*intel_dig_port
=
1572 dp_to_dig_port(intel_dp
);
1573 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1574 enum intel_display_power_domain power_domain
;
1576 u32 pp_stat_reg
, pp_ctrl_reg
;
1578 lockdep_assert_held(&dev_priv
->pps_mutex
);
1580 WARN_ON(intel_dp
->want_panel_vdd
);
1582 if (!edp_have_panel_vdd(intel_dp
))
1585 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1586 port_name(intel_dig_port
->port
));
1588 pp
= ironlake_get_pp_control(intel_dp
);
1589 pp
&= ~EDP_FORCE_VDD
;
1591 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1592 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1594 I915_WRITE(pp_ctrl_reg
, pp
);
1595 POSTING_READ(pp_ctrl_reg
);
1597 /* Make sure sequencer is idle before allowing subsequent activity */
1598 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1599 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1601 if ((pp
& POWER_TARGET_ON
) == 0)
1602 intel_dp
->last_power_cycle
= jiffies
;
1604 power_domain
= intel_display_port_power_domain(intel_encoder
);
1605 intel_display_power_put(dev_priv
, power_domain
);
1608 static void edp_panel_vdd_work(struct work_struct
*__work
)
1610 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1611 struct intel_dp
, panel_vdd_work
);
1614 if (!intel_dp
->want_panel_vdd
)
1615 edp_panel_vdd_off_sync(intel_dp
);
1616 pps_unlock(intel_dp
);
1619 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1621 unsigned long delay
;
1624 * Queue the timer to fire a long time from now (relative to the power
1625 * down delay) to keep the panel power up across a sequence of
1628 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1629 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1633 * Must be paired with edp_panel_vdd_on().
1634 * Must hold pps_mutex around the whole on/off sequence.
1635 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1637 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1639 struct drm_i915_private
*dev_priv
=
1640 intel_dp_to_dev(intel_dp
)->dev_private
;
1642 lockdep_assert_held(&dev_priv
->pps_mutex
);
1644 if (!is_edp(intel_dp
))
1647 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1648 port_name(dp_to_dig_port(intel_dp
)->port
));
1650 intel_dp
->want_panel_vdd
= false;
1653 edp_panel_vdd_off_sync(intel_dp
);
1655 edp_panel_vdd_schedule_off(intel_dp
);
1658 static void edp_panel_on(struct intel_dp
*intel_dp
)
1660 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1665 lockdep_assert_held(&dev_priv
->pps_mutex
);
1667 if (!is_edp(intel_dp
))
1670 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1671 port_name(dp_to_dig_port(intel_dp
)->port
));
1673 if (WARN(edp_have_panel_power(intel_dp
),
1674 "eDP port %c panel power already on\n",
1675 port_name(dp_to_dig_port(intel_dp
)->port
)))
1678 wait_panel_power_cycle(intel_dp
);
1680 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1681 pp
= ironlake_get_pp_control(intel_dp
);
1683 /* ILK workaround: disable reset around power sequence */
1684 pp
&= ~PANEL_POWER_RESET
;
1685 I915_WRITE(pp_ctrl_reg
, pp
);
1686 POSTING_READ(pp_ctrl_reg
);
1689 pp
|= POWER_TARGET_ON
;
1691 pp
|= PANEL_POWER_RESET
;
1693 I915_WRITE(pp_ctrl_reg
, pp
);
1694 POSTING_READ(pp_ctrl_reg
);
1696 wait_panel_on(intel_dp
);
1697 intel_dp
->last_power_on
= jiffies
;
1700 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1701 I915_WRITE(pp_ctrl_reg
, pp
);
1702 POSTING_READ(pp_ctrl_reg
);
1706 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1708 if (!is_edp(intel_dp
))
1712 edp_panel_on(intel_dp
);
1713 pps_unlock(intel_dp
);
1717 static void edp_panel_off(struct intel_dp
*intel_dp
)
1719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1720 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1721 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1723 enum intel_display_power_domain power_domain
;
1727 lockdep_assert_held(&dev_priv
->pps_mutex
);
1729 if (!is_edp(intel_dp
))
1732 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1733 port_name(dp_to_dig_port(intel_dp
)->port
));
1735 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1736 port_name(dp_to_dig_port(intel_dp
)->port
));
1738 pp
= ironlake_get_pp_control(intel_dp
);
1739 /* We need to switch off panel power _and_ force vdd, for otherwise some
1740 * panels get very unhappy and cease to work. */
1741 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1744 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1746 intel_dp
->want_panel_vdd
= false;
1748 I915_WRITE(pp_ctrl_reg
, pp
);
1749 POSTING_READ(pp_ctrl_reg
);
1751 intel_dp
->last_power_cycle
= jiffies
;
1752 wait_panel_off(intel_dp
);
1754 /* We got a reference when we enabled the VDD. */
1755 power_domain
= intel_display_port_power_domain(intel_encoder
);
1756 intel_display_power_put(dev_priv
, power_domain
);
1759 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1761 if (!is_edp(intel_dp
))
1765 edp_panel_off(intel_dp
);
1766 pps_unlock(intel_dp
);
1769 /* Enable backlight in the panel power control. */
1770 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1772 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1773 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1779 * If we enable the backlight right away following a panel power
1780 * on, we may see slight flicker as the panel syncs with the eDP
1781 * link. So delay a bit to make sure the image is solid before
1782 * allowing it to appear.
1784 wait_backlight_on(intel_dp
);
1788 pp
= ironlake_get_pp_control(intel_dp
);
1789 pp
|= EDP_BLC_ENABLE
;
1791 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1793 I915_WRITE(pp_ctrl_reg
, pp
);
1794 POSTING_READ(pp_ctrl_reg
);
1796 pps_unlock(intel_dp
);
1799 /* Enable backlight PWM and backlight PP control. */
1800 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1802 if (!is_edp(intel_dp
))
1805 DRM_DEBUG_KMS("\n");
1807 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1808 _intel_edp_backlight_on(intel_dp
);
1811 /* Disable backlight in the panel power control. */
1812 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1814 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1819 if (!is_edp(intel_dp
))
1824 pp
= ironlake_get_pp_control(intel_dp
);
1825 pp
&= ~EDP_BLC_ENABLE
;
1827 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1829 I915_WRITE(pp_ctrl_reg
, pp
);
1830 POSTING_READ(pp_ctrl_reg
);
1832 pps_unlock(intel_dp
);
1834 intel_dp
->last_backlight_off
= jiffies
;
1835 edp_wait_backlight_off(intel_dp
);
1838 /* Disable backlight PP control and backlight PWM. */
1839 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1841 if (!is_edp(intel_dp
))
1844 DRM_DEBUG_KMS("\n");
1846 _intel_edp_backlight_off(intel_dp
);
1847 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1851 * Hook for controlling the panel power control backlight through the bl_power
1852 * sysfs attribute. Take care to handle multiple calls.
1854 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1857 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1861 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1862 pps_unlock(intel_dp
);
1864 if (is_enabled
== enable
)
1867 DRM_DEBUG_KMS("panel power control backlight %s\n",
1868 enable
? "enable" : "disable");
1871 _intel_edp_backlight_on(intel_dp
);
1873 _intel_edp_backlight_off(intel_dp
);
1876 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1878 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1879 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1880 struct drm_device
*dev
= crtc
->dev
;
1881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1884 assert_pipe_disabled(dev_priv
,
1885 to_intel_crtc(crtc
)->pipe
);
1887 DRM_DEBUG_KMS("\n");
1888 dpa_ctl
= I915_READ(DP_A
);
1889 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1890 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1892 /* We don't adjust intel_dp->DP while tearing down the link, to
1893 * facilitate link retraining (e.g. after hotplug). Hence clear all
1894 * enable bits here to ensure that we don't enable too much. */
1895 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1896 intel_dp
->DP
|= DP_PLL_ENABLE
;
1897 I915_WRITE(DP_A
, intel_dp
->DP
);
1902 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1904 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1905 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1906 struct drm_device
*dev
= crtc
->dev
;
1907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1910 assert_pipe_disabled(dev_priv
,
1911 to_intel_crtc(crtc
)->pipe
);
1913 dpa_ctl
= I915_READ(DP_A
);
1914 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1915 "dp pll off, should be on\n");
1916 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1918 /* We can't rely on the value tracked for the DP register in
1919 * intel_dp->DP because link_down must not change that (otherwise link
1920 * re-training will fail. */
1921 dpa_ctl
&= ~DP_PLL_ENABLE
;
1922 I915_WRITE(DP_A
, dpa_ctl
);
1927 /* If the sink supports it, try to set the power state appropriately */
1928 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1932 /* Should have a valid DPCD by this point */
1933 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1936 if (mode
!= DRM_MODE_DPMS_ON
) {
1937 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1941 * When turning on, we need to retry for 1ms to give the sink
1944 for (i
= 0; i
< 3; i
++) {
1945 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1954 DRM_DEBUG_KMS("failed to %s sink power state\n",
1955 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1958 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1961 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1962 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1963 struct drm_device
*dev
= encoder
->base
.dev
;
1964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1965 enum intel_display_power_domain power_domain
;
1968 power_domain
= intel_display_port_power_domain(encoder
);
1969 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1972 tmp
= I915_READ(intel_dp
->output_reg
);
1974 if (!(tmp
& DP_PORT_EN
))
1977 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1978 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1979 } else if (IS_CHERRYVIEW(dev
)) {
1980 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1981 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1982 *pipe
= PORT_TO_PIPE(tmp
);
1988 switch (intel_dp
->output_reg
) {
1990 trans_sel
= TRANS_DP_PORT_SEL_B
;
1993 trans_sel
= TRANS_DP_PORT_SEL_C
;
1996 trans_sel
= TRANS_DP_PORT_SEL_D
;
2002 for_each_pipe(dev_priv
, i
) {
2003 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
2004 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
2010 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2011 intel_dp
->output_reg
);
2017 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2018 struct intel_crtc_state
*pipe_config
)
2020 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2022 struct drm_device
*dev
= encoder
->base
.dev
;
2023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2024 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2025 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2028 tmp
= I915_READ(intel_dp
->output_reg
);
2029 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
2030 pipe_config
->has_audio
= true;
2032 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
2033 if (tmp
& DP_SYNC_HS_HIGH
)
2034 flags
|= DRM_MODE_FLAG_PHSYNC
;
2036 flags
|= DRM_MODE_FLAG_NHSYNC
;
2038 if (tmp
& DP_SYNC_VS_HIGH
)
2039 flags
|= DRM_MODE_FLAG_PVSYNC
;
2041 flags
|= DRM_MODE_FLAG_NVSYNC
;
2043 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2044 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2045 flags
|= DRM_MODE_FLAG_PHSYNC
;
2047 flags
|= DRM_MODE_FLAG_NHSYNC
;
2049 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2050 flags
|= DRM_MODE_FLAG_PVSYNC
;
2052 flags
|= DRM_MODE_FLAG_NVSYNC
;
2055 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2057 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2058 tmp
& DP_COLOR_RANGE_16_235
)
2059 pipe_config
->limited_color_range
= true;
2061 pipe_config
->has_dp_encoder
= true;
2063 intel_dp_get_m_n(crtc
, pipe_config
);
2065 if (port
== PORT_A
) {
2066 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2067 pipe_config
->port_clock
= 162000;
2069 pipe_config
->port_clock
= 270000;
2072 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2073 &pipe_config
->dp_m_n
);
2075 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2076 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2078 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2080 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2081 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2083 * This is a big fat ugly hack.
2085 * Some machines in UEFI boot mode provide us a VBT that has 18
2086 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2087 * unknown we fail to light up. Yet the same BIOS boots up with
2088 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2089 * max, not what it tells us to use.
2091 * Note: This will still be broken if the eDP panel is not lit
2092 * up by the BIOS, and thus we can't get the mode at module
2095 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2096 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2097 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2101 static void intel_disable_dp(struct intel_encoder
*encoder
)
2103 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2104 struct drm_device
*dev
= encoder
->base
.dev
;
2105 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2107 if (crtc
->config
->has_audio
)
2108 intel_audio_codec_disable(encoder
);
2110 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2111 intel_psr_disable(intel_dp
);
2113 /* Make sure the panel is off before trying to change the mode. But also
2114 * ensure that we have vdd while we switch off the panel. */
2115 intel_edp_panel_vdd_on(intel_dp
);
2116 intel_edp_backlight_off(intel_dp
);
2117 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2118 intel_edp_panel_off(intel_dp
);
2120 /* disable the port before the pipe on g4x */
2121 if (INTEL_INFO(dev
)->gen
< 5)
2122 intel_dp_link_down(intel_dp
);
2125 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2127 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2128 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2130 intel_dp_link_down(intel_dp
);
2132 ironlake_edp_pll_off(intel_dp
);
2135 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2137 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2139 intel_dp_link_down(intel_dp
);
2142 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2144 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2145 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2146 struct drm_device
*dev
= encoder
->base
.dev
;
2147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2148 struct intel_crtc
*intel_crtc
=
2149 to_intel_crtc(encoder
->base
.crtc
);
2150 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2151 enum pipe pipe
= intel_crtc
->pipe
;
2154 intel_dp_link_down(intel_dp
);
2156 mutex_lock(&dev_priv
->dpio_lock
);
2158 /* Propagate soft reset to data lane reset */
2159 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2160 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2161 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2163 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2164 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2165 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2167 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2168 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2169 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2171 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2172 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2173 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2175 mutex_unlock(&dev_priv
->dpio_lock
);
2179 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2181 uint8_t dp_train_pat
)
2183 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2184 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2186 enum port port
= intel_dig_port
->port
;
2189 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2191 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2192 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2194 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2196 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2197 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2198 case DP_TRAINING_PATTERN_DISABLE
:
2199 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2202 case DP_TRAINING_PATTERN_1
:
2203 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2205 case DP_TRAINING_PATTERN_2
:
2206 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2208 case DP_TRAINING_PATTERN_3
:
2209 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2212 I915_WRITE(DP_TP_CTL(port
), temp
);
2214 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2215 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2217 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2218 case DP_TRAINING_PATTERN_DISABLE
:
2219 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2221 case DP_TRAINING_PATTERN_1
:
2222 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2224 case DP_TRAINING_PATTERN_2
:
2225 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2227 case DP_TRAINING_PATTERN_3
:
2228 DRM_ERROR("DP training pattern 3 not supported\n");
2229 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2234 if (IS_CHERRYVIEW(dev
))
2235 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2237 *DP
&= ~DP_LINK_TRAIN_MASK
;
2239 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2240 case DP_TRAINING_PATTERN_DISABLE
:
2241 *DP
|= DP_LINK_TRAIN_OFF
;
2243 case DP_TRAINING_PATTERN_1
:
2244 *DP
|= DP_LINK_TRAIN_PAT_1
;
2246 case DP_TRAINING_PATTERN_2
:
2247 *DP
|= DP_LINK_TRAIN_PAT_2
;
2249 case DP_TRAINING_PATTERN_3
:
2250 if (IS_CHERRYVIEW(dev
)) {
2251 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2253 DRM_ERROR("DP training pattern 3 not supported\n");
2254 *DP
|= DP_LINK_TRAIN_PAT_2
;
2261 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2263 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2266 /* enable with pattern 1 (as per spec) */
2267 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2268 DP_TRAINING_PATTERN_1
);
2270 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2271 POSTING_READ(intel_dp
->output_reg
);
2274 * Magic for VLV/CHV. We _must_ first set up the register
2275 * without actually enabling the port, and then do another
2276 * write to enable the port. Otherwise link training will
2277 * fail when the power sequencer is freshly used for this port.
2279 intel_dp
->DP
|= DP_PORT_EN
;
2281 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2282 POSTING_READ(intel_dp
->output_reg
);
2285 static void intel_enable_dp(struct intel_encoder
*encoder
)
2287 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2288 struct drm_device
*dev
= encoder
->base
.dev
;
2289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2290 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2291 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2293 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2298 if (IS_VALLEYVIEW(dev
))
2299 vlv_init_panel_power_sequencer(intel_dp
);
2301 intel_dp_enable_port(intel_dp
);
2303 edp_panel_vdd_on(intel_dp
);
2304 edp_panel_on(intel_dp
);
2305 edp_panel_vdd_off(intel_dp
, true);
2307 pps_unlock(intel_dp
);
2309 if (IS_VALLEYVIEW(dev
))
2310 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
));
2312 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2313 intel_dp_start_link_train(intel_dp
);
2314 intel_dp_complete_link_train(intel_dp
);
2315 intel_dp_stop_link_train(intel_dp
);
2317 if (crtc
->config
->has_audio
) {
2318 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2319 pipe_name(crtc
->pipe
));
2320 intel_audio_codec_enable(encoder
);
2324 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2326 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2328 intel_enable_dp(encoder
);
2329 intel_edp_backlight_on(intel_dp
);
2332 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2334 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2336 intel_edp_backlight_on(intel_dp
);
2337 intel_psr_enable(intel_dp
);
2340 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2342 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2343 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2345 intel_dp_prepare(encoder
);
2347 /* Only ilk+ has port A */
2348 if (dport
->port
== PORT_A
) {
2349 ironlake_set_pll_cpu_edp(intel_dp
);
2350 ironlake_edp_pll_on(intel_dp
);
2354 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2356 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2357 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2358 enum pipe pipe
= intel_dp
->pps_pipe
;
2359 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2361 edp_panel_vdd_off_sync(intel_dp
);
2364 * VLV seems to get confused when multiple power seqeuencers
2365 * have the same port selected (even if only one has power/vdd
2366 * enabled). The failure manifests as vlv_wait_port_ready() failing
2367 * CHV on the other hand doesn't seem to mind having the same port
2368 * selected in multiple power seqeuencers, but let's clear the
2369 * port select always when logically disconnecting a power sequencer
2372 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2373 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2374 I915_WRITE(pp_on_reg
, 0);
2375 POSTING_READ(pp_on_reg
);
2377 intel_dp
->pps_pipe
= INVALID_PIPE
;
2380 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2384 struct intel_encoder
*encoder
;
2386 lockdep_assert_held(&dev_priv
->pps_mutex
);
2388 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2391 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2393 struct intel_dp
*intel_dp
;
2396 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2399 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2400 port
= dp_to_dig_port(intel_dp
)->port
;
2402 if (intel_dp
->pps_pipe
!= pipe
)
2405 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2406 pipe_name(pipe
), port_name(port
));
2408 WARN(encoder
->connectors_active
,
2409 "stealing pipe %c power sequencer from active eDP port %c\n",
2410 pipe_name(pipe
), port_name(port
));
2412 /* make sure vdd is off before we steal it */
2413 vlv_detach_power_sequencer(intel_dp
);
2417 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2419 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2420 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2421 struct drm_device
*dev
= encoder
->base
.dev
;
2422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2423 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2425 lockdep_assert_held(&dev_priv
->pps_mutex
);
2427 if (!is_edp(intel_dp
))
2430 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2434 * If another power sequencer was being used on this
2435 * port previously make sure to turn off vdd there while
2436 * we still have control of it.
2438 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2439 vlv_detach_power_sequencer(intel_dp
);
2442 * We may be stealing the power
2443 * sequencer from another port.
2445 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2447 /* now it's all ours */
2448 intel_dp
->pps_pipe
= crtc
->pipe
;
2450 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2451 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2453 /* init power sequencer on this pipe and port */
2454 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2455 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2458 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2460 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2461 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2462 struct drm_device
*dev
= encoder
->base
.dev
;
2463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2464 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2465 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2466 int pipe
= intel_crtc
->pipe
;
2469 mutex_lock(&dev_priv
->dpio_lock
);
2471 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2478 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2479 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2480 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2482 mutex_unlock(&dev_priv
->dpio_lock
);
2484 intel_enable_dp(encoder
);
2487 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2489 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2490 struct drm_device
*dev
= encoder
->base
.dev
;
2491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2492 struct intel_crtc
*intel_crtc
=
2493 to_intel_crtc(encoder
->base
.crtc
);
2494 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2495 int pipe
= intel_crtc
->pipe
;
2497 intel_dp_prepare(encoder
);
2499 /* Program Tx lane resets to default */
2500 mutex_lock(&dev_priv
->dpio_lock
);
2501 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2502 DPIO_PCS_TX_LANE2_RESET
|
2503 DPIO_PCS_TX_LANE1_RESET
);
2504 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2505 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2506 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2507 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2508 DPIO_PCS_CLK_SOFT_RESET
);
2510 /* Fix up inter-pair skew failure */
2511 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2512 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2513 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2514 mutex_unlock(&dev_priv
->dpio_lock
);
2517 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2519 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2520 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2521 struct drm_device
*dev
= encoder
->base
.dev
;
2522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2523 struct intel_crtc
*intel_crtc
=
2524 to_intel_crtc(encoder
->base
.crtc
);
2525 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2526 int pipe
= intel_crtc
->pipe
;
2530 mutex_lock(&dev_priv
->dpio_lock
);
2532 /* allow hardware to manage TX FIFO reset source */
2533 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2534 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2535 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2537 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2538 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2539 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2541 /* Deassert soft data lane reset*/
2542 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2543 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2544 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2546 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2547 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2548 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2550 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2551 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2552 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2554 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2555 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2556 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2558 /* Program Tx lane latency optimal setting*/
2559 for (i
= 0; i
< 4; i
++) {
2560 /* Set the latency optimal bit */
2561 data
= (i
== 1) ? 0x0 : 0x6;
2562 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2563 data
<< DPIO_FRC_LATENCY_SHFIT
);
2565 /* Set the upar bit */
2566 data
= (i
== 1) ? 0x0 : 0x1;
2567 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2568 data
<< DPIO_UPAR_SHIFT
);
2571 /* Data lane stagger programming */
2572 /* FIXME: Fix up value only after power analysis */
2574 mutex_unlock(&dev_priv
->dpio_lock
);
2576 intel_enable_dp(encoder
);
2579 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2581 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2582 struct drm_device
*dev
= encoder
->base
.dev
;
2583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2584 struct intel_crtc
*intel_crtc
=
2585 to_intel_crtc(encoder
->base
.crtc
);
2586 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2587 enum pipe pipe
= intel_crtc
->pipe
;
2590 intel_dp_prepare(encoder
);
2592 mutex_lock(&dev_priv
->dpio_lock
);
2594 /* program left/right clock distribution */
2595 if (pipe
!= PIPE_B
) {
2596 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2597 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2599 val
|= CHV_BUFLEFTENA1_FORCE
;
2601 val
|= CHV_BUFRIGHTENA1_FORCE
;
2602 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2604 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2605 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2607 val
|= CHV_BUFLEFTENA2_FORCE
;
2609 val
|= CHV_BUFRIGHTENA2_FORCE
;
2610 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2613 /* program clock channel usage */
2614 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2615 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2617 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2619 val
|= CHV_PCS_USEDCLKCHANNEL
;
2620 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2622 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2623 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2625 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2627 val
|= CHV_PCS_USEDCLKCHANNEL
;
2628 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2631 * This a a bit weird since generally CL
2632 * matches the pipe, but here we need to
2633 * pick the CL based on the port.
2635 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2637 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2639 val
|= CHV_CMN_USEDCLKCHANNEL
;
2640 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2642 mutex_unlock(&dev_priv
->dpio_lock
);
2646 * Native read with retry for link status and receiver capability reads for
2647 * cases where the sink may still be asleep.
2649 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2650 * supposed to retry 3 times per the spec.
2653 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2654 void *buffer
, size_t size
)
2660 * Sometime we just get the same incorrect byte repeated
2661 * over the entire buffer. Doing just one throw away read
2662 * initially seems to "solve" it.
2664 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2666 for (i
= 0; i
< 3; i
++) {
2667 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2677 * Fetch AUX CH registers 0x202 - 0x207 which contain
2678 * link status information
2681 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2683 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2686 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2689 /* These are source-specific values. */
2691 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2693 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2694 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2696 if (INTEL_INFO(dev
)->gen
>= 9)
2697 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2698 else if (IS_VALLEYVIEW(dev
))
2699 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2700 else if (IS_GEN7(dev
) && port
== PORT_A
)
2701 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2702 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2703 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2705 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2709 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2711 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2712 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2714 if (INTEL_INFO(dev
)->gen
>= 9) {
2715 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2716 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2717 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2718 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2719 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2720 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2721 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2723 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2725 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2726 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2727 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2728 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2729 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2730 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2731 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2732 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2733 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2735 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2737 } else if (IS_VALLEYVIEW(dev
)) {
2738 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2739 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2740 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2741 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2742 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2743 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2744 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2745 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2747 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2749 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2750 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2751 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2752 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2753 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2754 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2755 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2757 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2760 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2761 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2762 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2763 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2764 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2765 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2766 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2767 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2769 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2774 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2776 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2778 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2779 struct intel_crtc
*intel_crtc
=
2780 to_intel_crtc(dport
->base
.base
.crtc
);
2781 unsigned long demph_reg_value
, preemph_reg_value
,
2782 uniqtranscale_reg_value
;
2783 uint8_t train_set
= intel_dp
->train_set
[0];
2784 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2785 int pipe
= intel_crtc
->pipe
;
2787 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2788 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2789 preemph_reg_value
= 0x0004000;
2790 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2791 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2792 demph_reg_value
= 0x2B405555;
2793 uniqtranscale_reg_value
= 0x552AB83A;
2795 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2796 demph_reg_value
= 0x2B404040;
2797 uniqtranscale_reg_value
= 0x5548B83A;
2799 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2800 demph_reg_value
= 0x2B245555;
2801 uniqtranscale_reg_value
= 0x5560B83A;
2803 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2804 demph_reg_value
= 0x2B405555;
2805 uniqtranscale_reg_value
= 0x5598DA3A;
2811 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2812 preemph_reg_value
= 0x0002000;
2813 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2814 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2815 demph_reg_value
= 0x2B404040;
2816 uniqtranscale_reg_value
= 0x5552B83A;
2818 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2819 demph_reg_value
= 0x2B404848;
2820 uniqtranscale_reg_value
= 0x5580B83A;
2822 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2823 demph_reg_value
= 0x2B404040;
2824 uniqtranscale_reg_value
= 0x55ADDA3A;
2830 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2831 preemph_reg_value
= 0x0000000;
2832 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2833 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2834 demph_reg_value
= 0x2B305555;
2835 uniqtranscale_reg_value
= 0x5570B83A;
2837 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2838 demph_reg_value
= 0x2B2B4040;
2839 uniqtranscale_reg_value
= 0x55ADDA3A;
2845 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2846 preemph_reg_value
= 0x0006000;
2847 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2849 demph_reg_value
= 0x1B405555;
2850 uniqtranscale_reg_value
= 0x55ADDA3A;
2860 mutex_lock(&dev_priv
->dpio_lock
);
2861 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2862 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2863 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2864 uniqtranscale_reg_value
);
2865 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2866 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2867 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2868 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2869 mutex_unlock(&dev_priv
->dpio_lock
);
2874 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2876 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2878 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2879 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2880 u32 deemph_reg_value
, margin_reg_value
, val
;
2881 uint8_t train_set
= intel_dp
->train_set
[0];
2882 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2883 enum pipe pipe
= intel_crtc
->pipe
;
2886 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2887 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2888 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2889 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2890 deemph_reg_value
= 128;
2891 margin_reg_value
= 52;
2893 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2894 deemph_reg_value
= 128;
2895 margin_reg_value
= 77;
2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2898 deemph_reg_value
= 128;
2899 margin_reg_value
= 102;
2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2902 deemph_reg_value
= 128;
2903 margin_reg_value
= 154;
2904 /* FIXME extra to set for 1200 */
2910 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2911 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2913 deemph_reg_value
= 85;
2914 margin_reg_value
= 78;
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2917 deemph_reg_value
= 85;
2918 margin_reg_value
= 116;
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2921 deemph_reg_value
= 85;
2922 margin_reg_value
= 154;
2928 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2929 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2931 deemph_reg_value
= 64;
2932 margin_reg_value
= 104;
2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2935 deemph_reg_value
= 64;
2936 margin_reg_value
= 154;
2942 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2943 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2945 deemph_reg_value
= 43;
2946 margin_reg_value
= 154;
2956 mutex_lock(&dev_priv
->dpio_lock
);
2958 /* Clear calc init */
2959 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2960 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2961 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
2962 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
2963 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2965 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2966 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2967 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
2968 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
2969 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2971 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
2972 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
2973 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
2974 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
2976 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
2977 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
2978 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
2979 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
2981 /* Program swing deemph */
2982 for (i
= 0; i
< 4; i
++) {
2983 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2984 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2985 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2986 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2989 /* Program swing margin */
2990 for (i
= 0; i
< 4; i
++) {
2991 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2992 val
&= ~DPIO_SWING_MARGIN000_MASK
;
2993 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
2994 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2997 /* Disable unique transition scale */
2998 for (i
= 0; i
< 4; i
++) {
2999 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3000 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3001 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3004 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3005 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3006 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3007 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3010 * The document said it needs to set bit 27 for ch0 and bit 26
3011 * for ch1. Might be a typo in the doc.
3012 * For now, for this unique transition scale selection, set bit
3013 * 27 for ch0 and ch1.
3015 for (i
= 0; i
< 4; i
++) {
3016 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3017 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3018 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3021 for (i
= 0; i
< 4; i
++) {
3022 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3023 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3024 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3025 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3029 /* Start swing calculation */
3030 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3031 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3032 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3034 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3035 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3036 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3039 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3040 val
|= DPIO_LRC_BYPASS
;
3041 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3043 mutex_unlock(&dev_priv
->dpio_lock
);
3049 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3050 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3055 uint8_t voltage_max
;
3056 uint8_t preemph_max
;
3058 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3059 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3060 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3068 voltage_max
= intel_dp_voltage_max(intel_dp
);
3069 if (v
>= voltage_max
)
3070 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3072 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3073 if (p
>= preemph_max
)
3074 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3076 for (lane
= 0; lane
< 4; lane
++)
3077 intel_dp
->train_set
[lane
] = v
| p
;
3081 intel_gen4_signal_levels(uint8_t train_set
)
3083 uint32_t signal_levels
= 0;
3085 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3088 signal_levels
|= DP_VOLTAGE_0_4
;
3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3091 signal_levels
|= DP_VOLTAGE_0_6
;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3094 signal_levels
|= DP_VOLTAGE_0_8
;
3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3097 signal_levels
|= DP_VOLTAGE_1_2
;
3100 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3101 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3103 signal_levels
|= DP_PRE_EMPHASIS_0
;
3105 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3106 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3108 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3109 signal_levels
|= DP_PRE_EMPHASIS_6
;
3111 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3112 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3115 return signal_levels
;
3118 /* Gen6's DP voltage swing and pre-emphasis control */
3120 intel_gen6_edp_signal_levels(uint8_t train_set
)
3122 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3123 DP_TRAIN_PRE_EMPHASIS_MASK
);
3124 switch (signal_levels
) {
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3127 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3129 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3132 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3135 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3138 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3140 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3141 "0x%x\n", signal_levels
);
3142 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3146 /* Gen7's DP voltage swing and pre-emphasis control */
3148 intel_gen7_edp_signal_levels(uint8_t train_set
)
3150 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3151 DP_TRAIN_PRE_EMPHASIS_MASK
);
3152 switch (signal_levels
) {
3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3154 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3156 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3158 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3161 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3163 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3166 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3168 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3171 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3172 "0x%x\n", signal_levels
);
3173 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3177 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3179 intel_hsw_signal_levels(uint8_t train_set
)
3181 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3182 DP_TRAIN_PRE_EMPHASIS_MASK
);
3183 switch (signal_levels
) {
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3185 return DDI_BUF_TRANS_SELECT(0);
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3187 return DDI_BUF_TRANS_SELECT(1);
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3189 return DDI_BUF_TRANS_SELECT(2);
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3191 return DDI_BUF_TRANS_SELECT(3);
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3194 return DDI_BUF_TRANS_SELECT(4);
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3196 return DDI_BUF_TRANS_SELECT(5);
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3198 return DDI_BUF_TRANS_SELECT(6);
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3201 return DDI_BUF_TRANS_SELECT(7);
3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3203 return DDI_BUF_TRANS_SELECT(8);
3205 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3206 "0x%x\n", signal_levels
);
3207 return DDI_BUF_TRANS_SELECT(0);
3211 /* Properly updates "DP" with the correct signal levels. */
3213 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3215 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3216 enum port port
= intel_dig_port
->port
;
3217 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3218 uint32_t signal_levels
, mask
;
3219 uint8_t train_set
= intel_dp
->train_set
[0];
3221 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3222 signal_levels
= intel_hsw_signal_levels(train_set
);
3223 mask
= DDI_BUF_EMP_MASK
;
3224 } else if (IS_CHERRYVIEW(dev
)) {
3225 signal_levels
= intel_chv_signal_levels(intel_dp
);
3227 } else if (IS_VALLEYVIEW(dev
)) {
3228 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3230 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3231 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3232 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3233 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3234 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3235 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3237 signal_levels
= intel_gen4_signal_levels(train_set
);
3238 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3241 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3243 *DP
= (*DP
& ~mask
) | signal_levels
;
3247 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3249 uint8_t dp_train_pat
)
3251 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3252 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3254 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3257 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3259 I915_WRITE(intel_dp
->output_reg
, *DP
);
3260 POSTING_READ(intel_dp
->output_reg
);
3262 buf
[0] = dp_train_pat
;
3263 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3264 DP_TRAINING_PATTERN_DISABLE
) {
3265 /* don't write DP_TRAINING_LANEx_SET on disable */
3268 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3269 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3270 len
= intel_dp
->lane_count
+ 1;
3273 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3280 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3281 uint8_t dp_train_pat
)
3283 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3284 intel_dp_set_signal_levels(intel_dp
, DP
);
3285 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3289 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3290 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3292 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3293 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3297 intel_get_adjust_train(intel_dp
, link_status
);
3298 intel_dp_set_signal_levels(intel_dp
, DP
);
3300 I915_WRITE(intel_dp
->output_reg
, *DP
);
3301 POSTING_READ(intel_dp
->output_reg
);
3303 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3304 intel_dp
->train_set
, intel_dp
->lane_count
);
3306 return ret
== intel_dp
->lane_count
;
3309 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3311 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3312 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3314 enum port port
= intel_dig_port
->port
;
3320 val
= I915_READ(DP_TP_CTL(port
));
3321 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3322 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3323 I915_WRITE(DP_TP_CTL(port
), val
);
3326 * On PORT_A we can have only eDP in SST mode. There the only reason
3327 * we need to set idle transmission mode is to work around a HW issue
3328 * where we enable the pipe while not in idle link-training mode.
3329 * In this case there is requirement to wait for a minimum number of
3330 * idle patterns to be sent.
3335 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3337 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3340 /* Enable corresponding port and start training pattern 1 */
3342 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3344 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3345 struct drm_device
*dev
= encoder
->dev
;
3348 int voltage_tries
, loop_tries
;
3349 uint32_t DP
= intel_dp
->DP
;
3350 uint8_t link_config
[2];
3353 intel_ddi_prepare_link_retrain(encoder
);
3355 /* Write the link configuration data */
3356 link_config
[0] = intel_dp
->link_bw
;
3357 link_config
[1] = intel_dp
->lane_count
;
3358 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3359 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3360 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3363 link_config
[1] = DP_SET_ANSI_8B10B
;
3364 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3368 /* clock recovery */
3369 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3370 DP_TRAINING_PATTERN_1
|
3371 DP_LINK_SCRAMBLING_DISABLE
)) {
3372 DRM_ERROR("failed to enable link training\n");
3380 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3382 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3383 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3384 DRM_ERROR("failed to get link status\n");
3388 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3389 DRM_DEBUG_KMS("clock recovery OK\n");
3393 /* Check to see if we've tried the max voltage */
3394 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3395 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3397 if (i
== intel_dp
->lane_count
) {
3399 if (loop_tries
== 5) {
3400 DRM_ERROR("too many full retries, give up\n");
3403 intel_dp_reset_link_train(intel_dp
, &DP
,
3404 DP_TRAINING_PATTERN_1
|
3405 DP_LINK_SCRAMBLING_DISABLE
);
3410 /* Check to see if we've tried the same voltage 5 times */
3411 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3413 if (voltage_tries
== 5) {
3414 DRM_ERROR("too many voltage retries, give up\n");
3419 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3421 /* Update training set as requested by target */
3422 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3423 DRM_ERROR("failed to update link training\n");
3432 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3434 bool channel_eq
= false;
3435 int tries
, cr_tries
;
3436 uint32_t DP
= intel_dp
->DP
;
3437 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3439 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3440 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3441 training_pattern
= DP_TRAINING_PATTERN_3
;
3443 /* channel equalization */
3444 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3446 DP_LINK_SCRAMBLING_DISABLE
)) {
3447 DRM_ERROR("failed to start channel equalization\n");
3455 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3458 DRM_ERROR("failed to train DP, aborting\n");
3462 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3463 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3464 DRM_ERROR("failed to get link status\n");
3468 /* Make sure clock is still ok */
3469 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3470 intel_dp_start_link_train(intel_dp
);
3471 intel_dp_set_link_train(intel_dp
, &DP
,
3473 DP_LINK_SCRAMBLING_DISABLE
);
3478 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3483 /* Try 5 times, then try clock recovery if that fails */
3485 intel_dp_start_link_train(intel_dp
);
3486 intel_dp_set_link_train(intel_dp
, &DP
,
3488 DP_LINK_SCRAMBLING_DISABLE
);
3494 /* Update training set as requested by target */
3495 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3496 DRM_ERROR("failed to update link training\n");
3502 intel_dp_set_idle_link_train(intel_dp
);
3507 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3511 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3513 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3514 DP_TRAINING_PATTERN_DISABLE
);
3518 intel_dp_link_down(struct intel_dp
*intel_dp
)
3520 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3521 enum port port
= intel_dig_port
->port
;
3522 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3524 uint32_t DP
= intel_dp
->DP
;
3526 if (WARN_ON(HAS_DDI(dev
)))
3529 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3532 DRM_DEBUG_KMS("\n");
3534 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3535 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3536 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3538 if (IS_CHERRYVIEW(dev
))
3539 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3541 DP
&= ~DP_LINK_TRAIN_MASK
;
3542 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3544 POSTING_READ(intel_dp
->output_reg
);
3546 if (HAS_PCH_IBX(dev
) &&
3547 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3548 /* Hardware workaround: leaving our transcoder select
3549 * set to transcoder B while it's off will prevent the
3550 * corresponding HDMI output on transcoder A.
3552 * Combine this with another hardware workaround:
3553 * transcoder select bit can only be cleared while the
3556 DP
&= ~DP_PIPEB_SELECT
;
3557 I915_WRITE(intel_dp
->output_reg
, DP
);
3558 POSTING_READ(intel_dp
->output_reg
);
3561 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3562 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3563 POSTING_READ(intel_dp
->output_reg
);
3564 msleep(intel_dp
->panel_power_down_delay
);
3568 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3570 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3571 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3574 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3575 sizeof(intel_dp
->dpcd
)) < 0)
3576 return false; /* aux transfer failed */
3578 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3580 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3581 return false; /* DPCD not present */
3583 /* Check if the panel supports PSR */
3584 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3585 if (is_edp(intel_dp
)) {
3586 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3588 sizeof(intel_dp
->psr_dpcd
));
3589 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3590 dev_priv
->psr
.sink_support
= true;
3591 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3595 /* Training Pattern 3 support, both source and sink */
3596 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3597 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3598 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3599 intel_dp
->use_tps3
= true;
3600 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3602 intel_dp
->use_tps3
= false;
3604 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3605 DP_DWN_STRM_PORT_PRESENT
))
3606 return true; /* native DP sink */
3608 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3609 return true; /* no per-port downstream info */
3611 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3612 intel_dp
->downstream_ports
,
3613 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3614 return false; /* downstream port status fetch failed */
3620 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3624 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3627 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3628 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3629 buf
[0], buf
[1], buf
[2]);
3631 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3632 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3633 buf
[0], buf
[1], buf
[2]);
3637 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3641 if (!intel_dp
->can_mst
)
3644 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3647 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3648 if (buf
[0] & DP_MST_CAP
) {
3649 DRM_DEBUG_KMS("Sink is MST capable\n");
3650 intel_dp
->is_mst
= true;
3652 DRM_DEBUG_KMS("Sink is not MST capable\n");
3653 intel_dp
->is_mst
= false;
3657 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3658 return intel_dp
->is_mst
;
3661 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3663 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3664 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3665 struct intel_crtc
*intel_crtc
=
3666 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3671 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3674 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3677 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3680 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3681 buf
| DP_TEST_SINK_START
) < 0)
3684 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3686 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
3689 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3690 DP_TEST_SINK_MISC
, &buf
) < 0)
3692 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3693 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
3695 if (attempts
== 0) {
3696 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3700 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3703 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3705 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3706 buf
& ~DP_TEST_SINK_START
) < 0)
3713 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3715 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3716 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3717 sink_irq_vector
, 1) == 1;
3721 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3725 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3727 sink_irq_vector
, 14);
3735 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3737 /* NAK by default */
3738 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3742 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3746 if (intel_dp
->is_mst
) {
3751 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3755 /* check link status - esi[10] = 0x200c */
3756 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3757 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3758 intel_dp_start_link_train(intel_dp
);
3759 intel_dp_complete_link_train(intel_dp
);
3760 intel_dp_stop_link_train(intel_dp
);
3763 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3764 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3767 for (retry
= 0; retry
< 3; retry
++) {
3769 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3770 DP_SINK_COUNT_ESI
+1,
3777 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3779 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3787 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3788 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3789 intel_dp
->is_mst
= false;
3790 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3791 /* send a hotplug event */
3792 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3799 * According to DP spec
3802 * 2. Configure link according to Receiver Capabilities
3803 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3804 * 4. Check link status on receipt of hot-plug interrupt
3807 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3809 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3810 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3812 u8 link_status
[DP_LINK_STATUS_SIZE
];
3814 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3816 if (!intel_encoder
->connectors_active
)
3819 if (WARN_ON(!intel_encoder
->base
.crtc
))
3822 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3825 /* Try to read receiver status if the link appears to be up */
3826 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3830 /* Now read the DPCD to see if it's actually running */
3831 if (!intel_dp_get_dpcd(intel_dp
)) {
3835 /* Try to read the source of the interrupt */
3836 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3837 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3838 /* Clear interrupt source */
3839 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3840 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3843 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3844 intel_dp_handle_test_request(intel_dp
);
3845 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3846 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3849 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3850 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3851 intel_encoder
->base
.name
);
3852 intel_dp_start_link_train(intel_dp
);
3853 intel_dp_complete_link_train(intel_dp
);
3854 intel_dp_stop_link_train(intel_dp
);
3858 /* XXX this is probably wrong for multiple downstream ports */
3859 static enum drm_connector_status
3860 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3862 uint8_t *dpcd
= intel_dp
->dpcd
;
3865 if (!intel_dp_get_dpcd(intel_dp
))
3866 return connector_status_disconnected
;
3868 /* if there's no downstream port, we're done */
3869 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3870 return connector_status_connected
;
3872 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3873 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3874 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3877 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3879 return connector_status_unknown
;
3881 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3882 : connector_status_disconnected
;
3885 /* If no HPD, poke DDC gently */
3886 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3887 return connector_status_connected
;
3889 /* Well we tried, say unknown for unreliable port types */
3890 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3891 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3892 if (type
== DP_DS_PORT_TYPE_VGA
||
3893 type
== DP_DS_PORT_TYPE_NON_EDID
)
3894 return connector_status_unknown
;
3896 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3897 DP_DWN_STRM_PORT_TYPE_MASK
;
3898 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3899 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3900 return connector_status_unknown
;
3903 /* Anything else is out of spec, warn and ignore */
3904 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3905 return connector_status_disconnected
;
3908 static enum drm_connector_status
3909 edp_detect(struct intel_dp
*intel_dp
)
3911 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3912 enum drm_connector_status status
;
3914 status
= intel_panel_detect(dev
);
3915 if (status
== connector_status_unknown
)
3916 status
= connector_status_connected
;
3921 static enum drm_connector_status
3922 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3924 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3926 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3928 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3929 return connector_status_disconnected
;
3931 return intel_dp_detect_dpcd(intel_dp
);
3934 static int g4x_digital_port_connected(struct drm_device
*dev
,
3935 struct intel_digital_port
*intel_dig_port
)
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3940 if (IS_VALLEYVIEW(dev
)) {
3941 switch (intel_dig_port
->port
) {
3943 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3946 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3949 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3955 switch (intel_dig_port
->port
) {
3957 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3960 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3963 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3970 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3975 static enum drm_connector_status
3976 g4x_dp_detect(struct intel_dp
*intel_dp
)
3978 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3979 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3982 /* Can't disconnect eDP, but you can close the lid... */
3983 if (is_edp(intel_dp
)) {
3984 enum drm_connector_status status
;
3986 status
= intel_panel_detect(dev
);
3987 if (status
== connector_status_unknown
)
3988 status
= connector_status_connected
;
3992 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
3994 return connector_status_unknown
;
3996 return connector_status_disconnected
;
3998 return intel_dp_detect_dpcd(intel_dp
);
4001 static struct edid
*
4002 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4004 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4006 /* use cached edid if we have one */
4007 if (intel_connector
->edid
) {
4009 if (IS_ERR(intel_connector
->edid
))
4012 return drm_edid_duplicate(intel_connector
->edid
);
4014 return drm_get_edid(&intel_connector
->base
,
4015 &intel_dp
->aux
.ddc
);
4019 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4021 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4024 edid
= intel_dp_get_edid(intel_dp
);
4025 intel_connector
->detect_edid
= edid
;
4027 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4028 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4030 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4034 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4036 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4038 kfree(intel_connector
->detect_edid
);
4039 intel_connector
->detect_edid
= NULL
;
4041 intel_dp
->has_audio
= false;
4044 static enum intel_display_power_domain
4045 intel_dp_power_get(struct intel_dp
*dp
)
4047 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4048 enum intel_display_power_domain power_domain
;
4050 power_domain
= intel_display_port_power_domain(encoder
);
4051 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4053 return power_domain
;
4057 intel_dp_power_put(struct intel_dp
*dp
,
4058 enum intel_display_power_domain power_domain
)
4060 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4061 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4064 static enum drm_connector_status
4065 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4067 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4068 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4069 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4070 struct drm_device
*dev
= connector
->dev
;
4071 enum drm_connector_status status
;
4072 enum intel_display_power_domain power_domain
;
4075 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4076 connector
->base
.id
, connector
->name
);
4077 intel_dp_unset_edid(intel_dp
);
4079 if (intel_dp
->is_mst
) {
4080 /* MST devices are disconnected from a monitor POV */
4081 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4082 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4083 return connector_status_disconnected
;
4086 power_domain
= intel_dp_power_get(intel_dp
);
4088 /* Can't disconnect eDP, but you can close the lid... */
4089 if (is_edp(intel_dp
))
4090 status
= edp_detect(intel_dp
);
4091 else if (HAS_PCH_SPLIT(dev
))
4092 status
= ironlake_dp_detect(intel_dp
);
4094 status
= g4x_dp_detect(intel_dp
);
4095 if (status
!= connector_status_connected
)
4098 intel_dp_probe_oui(intel_dp
);
4100 ret
= intel_dp_probe_mst(intel_dp
);
4102 /* if we are in MST mode then this connector
4103 won't appear connected or have anything with EDID on it */
4104 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4105 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4106 status
= connector_status_disconnected
;
4110 intel_dp_set_edid(intel_dp
);
4112 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4113 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4114 status
= connector_status_connected
;
4117 intel_dp_power_put(intel_dp
, power_domain
);
4122 intel_dp_force(struct drm_connector
*connector
)
4124 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4125 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4126 enum intel_display_power_domain power_domain
;
4128 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4129 connector
->base
.id
, connector
->name
);
4130 intel_dp_unset_edid(intel_dp
);
4132 if (connector
->status
!= connector_status_connected
)
4135 power_domain
= intel_dp_power_get(intel_dp
);
4137 intel_dp_set_edid(intel_dp
);
4139 intel_dp_power_put(intel_dp
, power_domain
);
4141 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4142 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4145 static int intel_dp_get_modes(struct drm_connector
*connector
)
4147 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4150 edid
= intel_connector
->detect_edid
;
4152 int ret
= intel_connector_update_modes(connector
, edid
);
4157 /* if eDP has no EDID, fall back to fixed mode */
4158 if (is_edp(intel_attached_dp(connector
)) &&
4159 intel_connector
->panel
.fixed_mode
) {
4160 struct drm_display_mode
*mode
;
4162 mode
= drm_mode_duplicate(connector
->dev
,
4163 intel_connector
->panel
.fixed_mode
);
4165 drm_mode_probed_add(connector
, mode
);
4174 intel_dp_detect_audio(struct drm_connector
*connector
)
4176 bool has_audio
= false;
4179 edid
= to_intel_connector(connector
)->detect_edid
;
4181 has_audio
= drm_detect_monitor_audio(edid
);
4187 intel_dp_set_property(struct drm_connector
*connector
,
4188 struct drm_property
*property
,
4191 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4192 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4193 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4194 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4197 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4201 if (property
== dev_priv
->force_audio_property
) {
4205 if (i
== intel_dp
->force_audio
)
4208 intel_dp
->force_audio
= i
;
4210 if (i
== HDMI_AUDIO_AUTO
)
4211 has_audio
= intel_dp_detect_audio(connector
);
4213 has_audio
= (i
== HDMI_AUDIO_ON
);
4215 if (has_audio
== intel_dp
->has_audio
)
4218 intel_dp
->has_audio
= has_audio
;
4222 if (property
== dev_priv
->broadcast_rgb_property
) {
4223 bool old_auto
= intel_dp
->color_range_auto
;
4224 uint32_t old_range
= intel_dp
->color_range
;
4227 case INTEL_BROADCAST_RGB_AUTO
:
4228 intel_dp
->color_range_auto
= true;
4230 case INTEL_BROADCAST_RGB_FULL
:
4231 intel_dp
->color_range_auto
= false;
4232 intel_dp
->color_range
= 0;
4234 case INTEL_BROADCAST_RGB_LIMITED
:
4235 intel_dp
->color_range_auto
= false;
4236 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4242 if (old_auto
== intel_dp
->color_range_auto
&&
4243 old_range
== intel_dp
->color_range
)
4249 if (is_edp(intel_dp
) &&
4250 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4251 if (val
== DRM_MODE_SCALE_NONE
) {
4252 DRM_DEBUG_KMS("no scaling not supported\n");
4256 if (intel_connector
->panel
.fitting_mode
== val
) {
4257 /* the eDP scaling property is not changed */
4260 intel_connector
->panel
.fitting_mode
= val
;
4268 if (intel_encoder
->base
.crtc
)
4269 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4275 intel_dp_connector_destroy(struct drm_connector
*connector
)
4277 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4279 kfree(intel_connector
->detect_edid
);
4281 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4282 kfree(intel_connector
->edid
);
4284 /* Can't call is_edp() since the encoder may have been destroyed
4286 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4287 intel_panel_fini(&intel_connector
->panel
);
4289 drm_connector_cleanup(connector
);
4293 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4295 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4296 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4298 drm_dp_aux_unregister(&intel_dp
->aux
);
4299 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4300 if (is_edp(intel_dp
)) {
4301 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4303 * vdd might still be enabled do to the delayed vdd off.
4304 * Make sure vdd is actually turned off here.
4307 edp_panel_vdd_off_sync(intel_dp
);
4308 pps_unlock(intel_dp
);
4310 if (intel_dp
->edp_notifier
.notifier_call
) {
4311 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4312 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4315 drm_encoder_cleanup(encoder
);
4316 kfree(intel_dig_port
);
4319 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4321 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4323 if (!is_edp(intel_dp
))
4327 * vdd might still be enabled do to the delayed vdd off.
4328 * Make sure vdd is actually turned off here.
4330 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4332 edp_panel_vdd_off_sync(intel_dp
);
4333 pps_unlock(intel_dp
);
4336 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4338 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4339 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4341 enum intel_display_power_domain power_domain
;
4343 lockdep_assert_held(&dev_priv
->pps_mutex
);
4345 if (!edp_have_panel_vdd(intel_dp
))
4349 * The VDD bit needs a power domain reference, so if the bit is
4350 * already enabled when we boot or resume, grab this reference and
4351 * schedule a vdd off, so we don't hold on to the reference
4354 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4355 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4356 intel_display_power_get(dev_priv
, power_domain
);
4358 edp_panel_vdd_schedule_off(intel_dp
);
4361 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4363 struct intel_dp
*intel_dp
;
4365 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4368 intel_dp
= enc_to_intel_dp(encoder
);
4373 * Read out the current power sequencer assignment,
4374 * in case the BIOS did something with it.
4376 if (IS_VALLEYVIEW(encoder
->dev
))
4377 vlv_initial_power_sequencer_setup(intel_dp
);
4379 intel_edp_panel_vdd_sanitize(intel_dp
);
4381 pps_unlock(intel_dp
);
4384 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4385 .dpms
= intel_connector_dpms
,
4386 .detect
= intel_dp_detect
,
4387 .force
= intel_dp_force
,
4388 .fill_modes
= drm_helper_probe_single_connector_modes
,
4389 .set_property
= intel_dp_set_property
,
4390 .atomic_get_property
= intel_connector_atomic_get_property
,
4391 .destroy
= intel_dp_connector_destroy
,
4392 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4395 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4396 .get_modes
= intel_dp_get_modes
,
4397 .mode_valid
= intel_dp_mode_valid
,
4398 .best_encoder
= intel_best_encoder
,
4401 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4402 .reset
= intel_dp_encoder_reset
,
4403 .destroy
= intel_dp_encoder_destroy
,
4407 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4413 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4415 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4416 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4417 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4419 enum intel_display_power_domain power_domain
;
4420 enum irqreturn ret
= IRQ_NONE
;
4422 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4423 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4425 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4427 * vdd off can generate a long pulse on eDP which
4428 * would require vdd on to handle it, and thus we
4429 * would end up in an endless cycle of
4430 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4432 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4433 port_name(intel_dig_port
->port
));
4437 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4438 port_name(intel_dig_port
->port
),
4439 long_hpd
? "long" : "short");
4441 power_domain
= intel_display_port_power_domain(intel_encoder
);
4442 intel_display_power_get(dev_priv
, power_domain
);
4446 if (HAS_PCH_SPLIT(dev
)) {
4447 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4450 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4454 if (!intel_dp_get_dpcd(intel_dp
)) {
4458 intel_dp_probe_oui(intel_dp
);
4460 if (!intel_dp_probe_mst(intel_dp
))
4464 if (intel_dp
->is_mst
) {
4465 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4469 if (!intel_dp
->is_mst
) {
4471 * we'll check the link status via the normal hot plug path later -
4472 * but for short hpds we should check it now
4474 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4475 intel_dp_check_link_status(intel_dp
);
4476 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4484 /* if we were in MST mode, and device is not there get out of MST mode */
4485 if (intel_dp
->is_mst
) {
4486 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4487 intel_dp
->is_mst
= false;
4488 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4491 intel_display_power_put(dev_priv
, power_domain
);
4496 /* Return which DP Port should be selected for Transcoder DP control */
4498 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4500 struct drm_device
*dev
= crtc
->dev
;
4501 struct intel_encoder
*intel_encoder
;
4502 struct intel_dp
*intel_dp
;
4504 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4505 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4507 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4508 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4509 return intel_dp
->output_reg
;
4515 /* check the VBT to see whether the eDP is on DP-D port */
4516 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4519 union child_device_config
*p_child
;
4521 static const short port_mapping
[] = {
4522 [PORT_B
] = PORT_IDPB
,
4523 [PORT_C
] = PORT_IDPC
,
4524 [PORT_D
] = PORT_IDPD
,
4530 if (!dev_priv
->vbt
.child_dev_num
)
4533 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4534 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4536 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4537 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4538 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4545 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4547 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4549 intel_attach_force_audio_property(connector
);
4550 intel_attach_broadcast_rgb_property(connector
);
4551 intel_dp
->color_range_auto
= true;
4553 if (is_edp(intel_dp
)) {
4554 drm_mode_create_scaling_mode_property(connector
->dev
);
4555 drm_object_attach_property(
4557 connector
->dev
->mode_config
.scaling_mode_property
,
4558 DRM_MODE_SCALE_ASPECT
);
4559 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4563 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4565 intel_dp
->last_power_cycle
= jiffies
;
4566 intel_dp
->last_power_on
= jiffies
;
4567 intel_dp
->last_backlight_off
= jiffies
;
4571 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4572 struct intel_dp
*intel_dp
)
4574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4575 struct edp_power_seq cur
, vbt
, spec
,
4576 *final
= &intel_dp
->pps_delays
;
4577 u32 pp_on
, pp_off
, pp_div
, pp
;
4578 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4580 lockdep_assert_held(&dev_priv
->pps_mutex
);
4582 /* already initialized? */
4583 if (final
->t11_t12
!= 0)
4586 if (HAS_PCH_SPLIT(dev
)) {
4587 pp_ctrl_reg
= PCH_PP_CONTROL
;
4588 pp_on_reg
= PCH_PP_ON_DELAYS
;
4589 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4590 pp_div_reg
= PCH_PP_DIVISOR
;
4592 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4594 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4595 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4596 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4597 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4600 /* Workaround: Need to write PP_CONTROL with the unlock key as
4601 * the very first thing. */
4602 pp
= ironlake_get_pp_control(intel_dp
);
4603 I915_WRITE(pp_ctrl_reg
, pp
);
4605 pp_on
= I915_READ(pp_on_reg
);
4606 pp_off
= I915_READ(pp_off_reg
);
4607 pp_div
= I915_READ(pp_div_reg
);
4609 /* Pull timing values out of registers */
4610 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4611 PANEL_POWER_UP_DELAY_SHIFT
;
4613 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4614 PANEL_LIGHT_ON_DELAY_SHIFT
;
4616 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4617 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4619 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4620 PANEL_POWER_DOWN_DELAY_SHIFT
;
4622 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4623 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4625 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4626 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4628 vbt
= dev_priv
->vbt
.edp_pps
;
4630 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4631 * our hw here, which are all in 100usec. */
4632 spec
.t1_t3
= 210 * 10;
4633 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4634 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4635 spec
.t10
= 500 * 10;
4636 /* This one is special and actually in units of 100ms, but zero
4637 * based in the hw (so we need to add 100 ms). But the sw vbt
4638 * table multiplies it with 1000 to make it in units of 100usec,
4640 spec
.t11_t12
= (510 + 100) * 10;
4642 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4643 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4645 /* Use the max of the register settings and vbt. If both are
4646 * unset, fall back to the spec limits. */
4647 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4649 max(cur.field, vbt.field))
4650 assign_final(t1_t3
);
4654 assign_final(t11_t12
);
4657 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4658 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4659 intel_dp
->backlight_on_delay
= get_delay(t8
);
4660 intel_dp
->backlight_off_delay
= get_delay(t9
);
4661 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4662 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4665 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4666 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4667 intel_dp
->panel_power_cycle_delay
);
4669 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4670 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4674 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4675 struct intel_dp
*intel_dp
)
4677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4678 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4679 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4680 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4681 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4682 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4684 lockdep_assert_held(&dev_priv
->pps_mutex
);
4686 if (HAS_PCH_SPLIT(dev
)) {
4687 pp_on_reg
= PCH_PP_ON_DELAYS
;
4688 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4689 pp_div_reg
= PCH_PP_DIVISOR
;
4691 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4693 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4694 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4695 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4699 * And finally store the new values in the power sequencer. The
4700 * backlight delays are set to 1 because we do manual waits on them. For
4701 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4702 * we'll end up waiting for the backlight off delay twice: once when we
4703 * do the manual sleep, and once when we disable the panel and wait for
4704 * the PP_STATUS bit to become zero.
4706 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4707 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4708 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4709 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4710 /* Compute the divisor for the pp clock, simply match the Bspec
4712 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4713 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4714 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4716 /* Haswell doesn't have any port selection bits for the panel
4717 * power sequencer any more. */
4718 if (IS_VALLEYVIEW(dev
)) {
4719 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4720 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4722 port_sel
= PANEL_PORT_SELECT_DPA
;
4724 port_sel
= PANEL_PORT_SELECT_DPD
;
4729 I915_WRITE(pp_on_reg
, pp_on
);
4730 I915_WRITE(pp_off_reg
, pp_off
);
4731 I915_WRITE(pp_div_reg
, pp_div
);
4733 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4734 I915_READ(pp_on_reg
),
4735 I915_READ(pp_off_reg
),
4736 I915_READ(pp_div_reg
));
4739 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4742 struct intel_encoder
*encoder
;
4743 struct intel_digital_port
*dig_port
= NULL
;
4744 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
4745 struct intel_crtc_state
*config
= NULL
;
4746 struct intel_crtc
*intel_crtc
= NULL
;
4748 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4750 if (refresh_rate
<= 0) {
4751 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4755 if (intel_dp
== NULL
) {
4756 DRM_DEBUG_KMS("DRRS not supported.\n");
4761 * FIXME: This needs proper synchronization with psr state for some
4762 * platforms that cannot have PSR and DRRS enabled at the same time.
4765 dig_port
= dp_to_dig_port(intel_dp
);
4766 encoder
= &dig_port
->base
;
4767 intel_crtc
= encoder
->new_crtc
;
4770 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4774 config
= intel_crtc
->config
;
4776 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
4777 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4781 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
4783 index
= DRRS_LOW_RR
;
4785 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
4787 "DRRS requested for previously set RR...ignoring\n");
4791 if (!intel_crtc
->active
) {
4792 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4796 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4797 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
4798 val
= I915_READ(reg
);
4799 if (index
> DRRS_HIGH_RR
) {
4800 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4801 intel_dp_set_m_n(intel_crtc
);
4803 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4805 I915_WRITE(reg
, val
);
4808 dev_priv
->drrs
.refresh_rate_type
= index
;
4810 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4813 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
4815 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4817 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4818 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
4819 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4821 if (!intel_crtc
->config
->has_drrs
) {
4822 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4826 mutex_lock(&dev_priv
->drrs
.mutex
);
4827 if (WARN_ON(dev_priv
->drrs
.dp
)) {
4828 DRM_ERROR("DRRS already enabled\n");
4832 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
4834 dev_priv
->drrs
.dp
= intel_dp
;
4837 mutex_unlock(&dev_priv
->drrs
.mutex
);
4840 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
4842 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4844 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4845 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
4846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4848 if (!intel_crtc
->config
->has_drrs
)
4851 mutex_lock(&dev_priv
->drrs
.mutex
);
4852 if (!dev_priv
->drrs
.dp
) {
4853 mutex_unlock(&dev_priv
->drrs
.mutex
);
4857 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
4858 intel_dp_set_drrs_state(dev_priv
->dev
,
4859 intel_dp
->attached_connector
->panel
.
4860 fixed_mode
->vrefresh
);
4862 dev_priv
->drrs
.dp
= NULL
;
4863 mutex_unlock(&dev_priv
->drrs
.mutex
);
4865 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
4868 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
4870 struct drm_i915_private
*dev_priv
=
4871 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
4872 struct intel_dp
*intel_dp
;
4874 mutex_lock(&dev_priv
->drrs
.mutex
);
4876 intel_dp
= dev_priv
->drrs
.dp
;
4882 * The delayed work can race with an invalidate hence we need to
4886 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
4889 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
4890 intel_dp_set_drrs_state(dev_priv
->dev
,
4891 intel_dp
->attached_connector
->panel
.
4892 downclock_mode
->vrefresh
);
4896 mutex_unlock(&dev_priv
->drrs
.mutex
);
4899 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
4900 unsigned frontbuffer_bits
)
4902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4903 struct drm_crtc
*crtc
;
4906 if (!dev_priv
->drrs
.dp
)
4909 mutex_lock(&dev_priv
->drrs
.mutex
);
4910 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
4911 pipe
= to_intel_crtc(crtc
)->pipe
;
4913 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
) {
4914 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
4915 intel_dp_set_drrs_state(dev_priv
->dev
,
4916 dev_priv
->drrs
.dp
->attached_connector
->panel
.
4917 fixed_mode
->vrefresh
);
4920 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
4922 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
4923 mutex_unlock(&dev_priv
->drrs
.mutex
);
4926 void intel_edp_drrs_flush(struct drm_device
*dev
,
4927 unsigned frontbuffer_bits
)
4929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4930 struct drm_crtc
*crtc
;
4933 if (!dev_priv
->drrs
.dp
)
4936 mutex_lock(&dev_priv
->drrs
.mutex
);
4937 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
4938 pipe
= to_intel_crtc(crtc
)->pipe
;
4939 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
4941 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
4943 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
&&
4944 !dev_priv
->drrs
.busy_frontbuffer_bits
)
4945 schedule_delayed_work(&dev_priv
->drrs
.work
,
4946 msecs_to_jiffies(1000));
4947 mutex_unlock(&dev_priv
->drrs
.mutex
);
4950 static struct drm_display_mode
*
4951 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
4952 struct drm_display_mode
*fixed_mode
)
4954 struct drm_connector
*connector
= &intel_connector
->base
;
4955 struct drm_device
*dev
= connector
->dev
;
4956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4957 struct drm_display_mode
*downclock_mode
= NULL
;
4959 if (INTEL_INFO(dev
)->gen
<= 6) {
4960 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4964 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4965 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4969 downclock_mode
= intel_find_panel_downclock
4970 (dev
, fixed_mode
, connector
);
4972 if (!downclock_mode
) {
4973 DRM_DEBUG_KMS("DRRS not supported\n");
4977 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
4979 mutex_init(&dev_priv
->drrs
.mutex
);
4981 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
4983 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
4984 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4985 return downclock_mode
;
4988 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4989 struct intel_connector
*intel_connector
)
4991 struct drm_connector
*connector
= &intel_connector
->base
;
4992 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4993 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4994 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4996 struct drm_display_mode
*fixed_mode
= NULL
;
4997 struct drm_display_mode
*downclock_mode
= NULL
;
4999 struct drm_display_mode
*scan
;
5001 enum pipe pipe
= INVALID_PIPE
;
5003 dev_priv
->drrs
.type
= DRRS_NOT_SUPPORTED
;
5005 if (!is_edp(intel_dp
))
5009 intel_edp_panel_vdd_sanitize(intel_dp
);
5010 pps_unlock(intel_dp
);
5012 /* Cache DPCD and EDID for edp. */
5013 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5016 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5017 dev_priv
->no_aux_handshake
=
5018 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5019 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5021 /* if this fails, presume the device is a ghost */
5022 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5026 /* We now know it's not a ghost, init power sequence regs. */
5028 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5029 pps_unlock(intel_dp
);
5031 mutex_lock(&dev
->mode_config
.mutex
);
5032 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5034 if (drm_add_edid_modes(connector
, edid
)) {
5035 drm_mode_connector_update_edid_property(connector
,
5037 drm_edid_to_eld(connector
, edid
);
5040 edid
= ERR_PTR(-EINVAL
);
5043 edid
= ERR_PTR(-ENOENT
);
5045 intel_connector
->edid
= edid
;
5047 /* prefer fixed mode from EDID if available */
5048 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5049 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5050 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5051 downclock_mode
= intel_dp_drrs_init(
5052 intel_connector
, fixed_mode
);
5057 /* fallback to VBT if available for eDP */
5058 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5059 fixed_mode
= drm_mode_duplicate(dev
,
5060 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5062 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5064 mutex_unlock(&dev
->mode_config
.mutex
);
5066 if (IS_VALLEYVIEW(dev
)) {
5067 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5068 register_reboot_notifier(&intel_dp
->edp_notifier
);
5071 * Figure out the current pipe for the initial backlight setup.
5072 * If the current pipe isn't valid, try the PPS pipe, and if that
5073 * fails just assume pipe A.
5075 if (IS_CHERRYVIEW(dev
))
5076 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5078 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5080 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5081 pipe
= intel_dp
->pps_pipe
;
5083 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5086 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5090 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5091 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5092 intel_panel_setup_backlight(connector
, pipe
);
5098 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5099 struct intel_connector
*intel_connector
)
5101 struct drm_connector
*connector
= &intel_connector
->base
;
5102 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5103 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5104 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5106 enum port port
= intel_dig_port
->port
;
5109 intel_dp
->pps_pipe
= INVALID_PIPE
;
5111 /* intel_dp vfuncs */
5112 if (INTEL_INFO(dev
)->gen
>= 9)
5113 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5114 else if (IS_VALLEYVIEW(dev
))
5115 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5116 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5117 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5118 else if (HAS_PCH_SPLIT(dev
))
5119 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5121 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5123 if (INTEL_INFO(dev
)->gen
>= 9)
5124 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5126 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5128 /* Preserve the current hw state. */
5129 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5130 intel_dp
->attached_connector
= intel_connector
;
5132 if (intel_dp_is_edp(dev
, port
))
5133 type
= DRM_MODE_CONNECTOR_eDP
;
5135 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5138 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5139 * for DP the encoder type can be set by the caller to
5140 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5142 if (type
== DRM_MODE_CONNECTOR_eDP
)
5143 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5145 /* eDP only on port B and/or C on vlv/chv */
5146 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5147 port
!= PORT_B
&& port
!= PORT_C
))
5150 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5151 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5154 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5155 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5157 connector
->interlace_allowed
= true;
5158 connector
->doublescan_allowed
= 0;
5160 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5161 edp_panel_vdd_work
);
5163 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5164 drm_connector_register(connector
);
5167 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5169 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5170 intel_connector
->unregister
= intel_dp_connector_unregister
;
5172 /* Set up the hotplug pin. */
5175 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5178 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5181 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5184 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5190 if (is_edp(intel_dp
)) {
5192 intel_dp_init_panel_power_timestamps(intel_dp
);
5193 if (IS_VALLEYVIEW(dev
))
5194 vlv_initial_power_sequencer_setup(intel_dp
);
5196 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5197 pps_unlock(intel_dp
);
5200 intel_dp_aux_init(intel_dp
, intel_connector
);
5202 /* init MST on ports that can support it */
5203 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
5204 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5205 intel_dp_mst_encoder_init(intel_dig_port
,
5206 intel_connector
->base
.base
.id
);
5210 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5211 drm_dp_aux_unregister(&intel_dp
->aux
);
5212 if (is_edp(intel_dp
)) {
5213 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5215 * vdd might still be enabled do to the delayed vdd off.
5216 * Make sure vdd is actually turned off here.
5219 edp_panel_vdd_off_sync(intel_dp
);
5220 pps_unlock(intel_dp
);
5222 drm_connector_unregister(connector
);
5223 drm_connector_cleanup(connector
);
5227 intel_dp_add_properties(intel_dp
, connector
);
5229 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5230 * 0xd. Failure to do so will result in spurious interrupts being
5231 * generated on the port when a cable is not attached.
5233 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5234 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5235 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5242 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5245 struct intel_digital_port
*intel_dig_port
;
5246 struct intel_encoder
*intel_encoder
;
5247 struct drm_encoder
*encoder
;
5248 struct intel_connector
*intel_connector
;
5250 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5251 if (!intel_dig_port
)
5254 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5255 if (!intel_connector
) {
5256 kfree(intel_dig_port
);
5260 intel_encoder
= &intel_dig_port
->base
;
5261 encoder
= &intel_encoder
->base
;
5263 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5264 DRM_MODE_ENCODER_TMDS
);
5266 intel_encoder
->compute_config
= intel_dp_compute_config
;
5267 intel_encoder
->disable
= intel_disable_dp
;
5268 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5269 intel_encoder
->get_config
= intel_dp_get_config
;
5270 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5271 if (IS_CHERRYVIEW(dev
)) {
5272 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5273 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5274 intel_encoder
->enable
= vlv_enable_dp
;
5275 intel_encoder
->post_disable
= chv_post_disable_dp
;
5276 } else if (IS_VALLEYVIEW(dev
)) {
5277 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5278 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5279 intel_encoder
->enable
= vlv_enable_dp
;
5280 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5282 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5283 intel_encoder
->enable
= g4x_enable_dp
;
5284 if (INTEL_INFO(dev
)->gen
>= 5)
5285 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5288 intel_dig_port
->port
= port
;
5289 intel_dig_port
->dp
.output_reg
= output_reg
;
5291 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5292 if (IS_CHERRYVIEW(dev
)) {
5294 intel_encoder
->crtc_mask
= 1 << 2;
5296 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5298 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5300 intel_encoder
->cloneable
= 0;
5301 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5303 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5304 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5306 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5307 drm_encoder_cleanup(encoder
);
5308 kfree(intel_dig_port
);
5309 kfree(intel_connector
);
5313 void intel_dp_mst_suspend(struct drm_device
*dev
)
5315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5319 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5320 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5321 if (!intel_dig_port
)
5324 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5325 if (!intel_dig_port
->dp
.can_mst
)
5327 if (intel_dig_port
->dp
.is_mst
)
5328 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5333 void intel_dp_mst_resume(struct drm_device
*dev
)
5335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5338 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5339 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5340 if (!intel_dig_port
)
5342 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5345 if (!intel_dig_port
->dp
.can_mst
)
5348 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5350 intel_dp_check_mst_status(&intel_dig_port
->dp
);