2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp
*intel_dp
)
50 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
52 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp
*intel_dp
)
65 return intel_dp
->is_pch_edp
;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
76 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
79 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
81 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
83 return intel_dig_port
->base
.base
.dev
;
86 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
88 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
98 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
100 struct intel_dp
*intel_dp
;
105 intel_dp
= enc_to_intel_dp(encoder
);
107 return is_pch_edp(intel_dp
);
110 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
113 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
114 int *lane_num
, int *link_bw
)
116 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
118 *lane_num
= intel_dp
->lane_count
;
119 *link_bw
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
123 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
124 struct drm_display_mode
*mode
)
126 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
127 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
129 if (intel_connector
->panel
.fixed_mode
)
130 return intel_connector
->panel
.fixed_mode
->clock
;
136 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
138 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
140 switch (max_link_bw
) {
141 case DP_LINK_BW_1_62
:
145 max_link_bw
= DP_LINK_BW_1_62
;
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
157 * 270000 * 1 * 8 / 10 == 216000
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
169 intel_dp_link_required(int pixel_clock
, int bpp
)
171 return (pixel_clock
* bpp
+ 9) / 10;
175 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
177 return (max_link_clock
* max_lanes
* 8) / 10;
181 intel_dp_mode_valid(struct drm_connector
*connector
,
182 struct drm_display_mode
*mode
)
184 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
185 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
186 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
187 int target_clock
= mode
->clock
;
188 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
190 if (is_edp(intel_dp
) && fixed_mode
) {
191 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
194 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
198 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
199 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
201 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
202 mode_rate
= intel_dp_link_required(target_clock
, 18);
204 if (mode_rate
> max_rate
)
205 return MODE_CLOCK_HIGH
;
207 if (mode
->clock
< 10000)
208 return MODE_CLOCK_LOW
;
210 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
211 return MODE_H_ILLEGAL
;
217 pack_aux(uint8_t *src
, int src_bytes
)
224 for (i
= 0; i
< src_bytes
; i
++)
225 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
230 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
235 for (i
= 0; i
< dst_bytes
; i
++)
236 dst
[i
] = src
>> ((3-i
) * 8);
239 /* hrawclock is 1/4 the FSB frequency */
241 intel_hrawclk(struct drm_device
*dev
)
243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
246 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
247 if (IS_VALLEYVIEW(dev
))
250 clkcfg
= I915_READ(CLKCFG
);
251 switch (clkcfg
& CLKCFG_FSB_MASK
) {
260 case CLKCFG_FSB_1067
:
262 case CLKCFG_FSB_1333
:
264 /* these two are just a guess; one of them might be right */
265 case CLKCFG_FSB_1600
:
266 case CLKCFG_FSB_1600_ALT
:
273 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
275 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
278 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
281 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
283 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
286 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
290 intel_dp_check_edp(struct intel_dp
*intel_dp
)
292 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
295 if (!is_edp(intel_dp
))
297 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
298 WARN(1, "eDP powered off while attempting aux channel communication.\n");
299 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
300 I915_READ(PCH_PP_STATUS
),
301 I915_READ(PCH_PP_CONTROL
));
306 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
308 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
309 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
311 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
315 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
317 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
318 msecs_to_jiffies(10));
320 done
= wait_for_atomic(C
, 10) == 0;
322 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
330 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
331 uint8_t *send
, int send_bytes
,
332 uint8_t *recv
, int recv_size
)
334 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
335 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
337 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
338 uint32_t ch_data
= ch_ctl
+ 4;
339 int i
, ret
, recv_bytes
;
341 uint32_t aux_clock_divider
;
343 bool has_aux_irq
= INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
);
345 /* dp aux is extremely sensitive to irq latency, hence request the
346 * lowest possible wakeup latency and so prevent the cpu from going into
349 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
351 intel_dp_check_edp(intel_dp
);
352 /* The clock divider is based off the hrawclk,
353 * and would like to run at 2MHz. So, take the
354 * hrawclk value and divide by 2 and use that
356 * Note that PCH attached eDP panels should use a 125MHz input
359 if (is_cpu_edp(intel_dp
)) {
361 aux_clock_divider
= intel_ddi_get_cdclk_freq(dev_priv
) >> 1;
362 else if (IS_VALLEYVIEW(dev
))
363 aux_clock_divider
= 100;
364 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
365 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
367 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
368 } else if (HAS_PCH_SPLIT(dev
))
369 aux_clock_divider
= DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
371 aux_clock_divider
= intel_hrawclk(dev
) / 2;
378 /* Try to wait for any previous AUX channel activity */
379 for (try = 0; try < 3; try++) {
380 status
= I915_READ_NOTRACE(ch_ctl
);
381 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
387 WARN(1, "dp_aux_ch not started status 0x%08x\n",
393 /* Must try at least 3 times according to DP spec */
394 for (try = 0; try < 5; try++) {
395 /* Load the send data into the aux channel data registers */
396 for (i
= 0; i
< send_bytes
; i
+= 4)
397 I915_WRITE(ch_data
+ i
,
398 pack_aux(send
+ i
, send_bytes
- i
));
400 /* Send the command and wait for it to complete */
402 DP_AUX_CH_CTL_SEND_BUSY
|
403 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
404 DP_AUX_CH_CTL_TIME_OUT_400us
|
405 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
406 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
407 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
409 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
410 DP_AUX_CH_CTL_RECEIVE_ERROR
);
412 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
414 /* Clear done status and any errors */
418 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
419 DP_AUX_CH_CTL_RECEIVE_ERROR
);
421 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
422 DP_AUX_CH_CTL_RECEIVE_ERROR
))
424 if (status
& DP_AUX_CH_CTL_DONE
)
428 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
429 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
434 /* Check for timeout or receive error.
435 * Timeouts occur when the sink is not connected
437 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
438 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
443 /* Timeouts occur when the device isn't connected, so they're
444 * "normal" -- don't fill the kernel log with these */
445 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
446 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
451 /* Unload any bytes sent back from the other side */
452 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
453 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
454 if (recv_bytes
> recv_size
)
455 recv_bytes
= recv_size
;
457 for (i
= 0; i
< recv_bytes
; i
+= 4)
458 unpack_aux(I915_READ(ch_data
+ i
),
459 recv
+ i
, recv_bytes
- i
);
463 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
468 /* Write data to the aux channel in native mode */
470 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
471 uint16_t address
, uint8_t *send
, int send_bytes
)
478 intel_dp_check_edp(intel_dp
);
481 msg
[0] = AUX_NATIVE_WRITE
<< 4;
482 msg
[1] = address
>> 8;
483 msg
[2] = address
& 0xff;
484 msg
[3] = send_bytes
- 1;
485 memcpy(&msg
[4], send
, send_bytes
);
486 msg_bytes
= send_bytes
+ 4;
488 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
491 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
493 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
501 /* Write a single byte to the aux channel in native mode */
503 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
504 uint16_t address
, uint8_t byte
)
506 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
509 /* read bytes from a native aux channel */
511 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
512 uint16_t address
, uint8_t *recv
, int recv_bytes
)
521 intel_dp_check_edp(intel_dp
);
522 msg
[0] = AUX_NATIVE_READ
<< 4;
523 msg
[1] = address
>> 8;
524 msg
[2] = address
& 0xff;
525 msg
[3] = recv_bytes
- 1;
528 reply_bytes
= recv_bytes
+ 1;
531 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
538 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
539 memcpy(recv
, reply
+ 1, ret
- 1);
542 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
550 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
551 uint8_t write_byte
, uint8_t *read_byte
)
553 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
554 struct intel_dp
*intel_dp
= container_of(adapter
,
557 uint16_t address
= algo_data
->address
;
565 intel_dp_check_edp(intel_dp
);
566 /* Set up the command byte */
567 if (mode
& MODE_I2C_READ
)
568 msg
[0] = AUX_I2C_READ
<< 4;
570 msg
[0] = AUX_I2C_WRITE
<< 4;
572 if (!(mode
& MODE_I2C_STOP
))
573 msg
[0] |= AUX_I2C_MOT
<< 4;
575 msg
[1] = address
>> 8;
596 for (retry
= 0; retry
< 5; retry
++) {
597 ret
= intel_dp_aux_ch(intel_dp
,
601 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
605 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
606 case AUX_NATIVE_REPLY_ACK
:
607 /* I2C-over-AUX Reply field is only valid
608 * when paired with AUX ACK.
611 case AUX_NATIVE_REPLY_NACK
:
612 DRM_DEBUG_KMS("aux_ch native nack\n");
614 case AUX_NATIVE_REPLY_DEFER
:
618 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
623 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
624 case AUX_I2C_REPLY_ACK
:
625 if (mode
== MODE_I2C_READ
) {
626 *read_byte
= reply
[1];
628 return reply_bytes
- 1;
629 case AUX_I2C_REPLY_NACK
:
630 DRM_DEBUG_KMS("aux_i2c nack\n");
632 case AUX_I2C_REPLY_DEFER
:
633 DRM_DEBUG_KMS("aux_i2c defer\n");
637 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
642 DRM_ERROR("too many retries, giving up\n");
647 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
648 struct intel_connector
*intel_connector
, const char *name
)
652 DRM_DEBUG_KMS("i2c_init %s\n", name
);
653 intel_dp
->algo
.running
= false;
654 intel_dp
->algo
.address
= 0;
655 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
657 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
658 intel_dp
->adapter
.owner
= THIS_MODULE
;
659 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
660 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
661 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
662 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
663 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
665 ironlake_edp_panel_vdd_on(intel_dp
);
666 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
667 ironlake_edp_panel_vdd_off(intel_dp
, false);
672 intel_dp_compute_config(struct intel_encoder
*encoder
,
673 struct intel_crtc_config
*pipe_config
)
675 struct drm_device
*dev
= encoder
->base
.dev
;
676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
677 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
678 struct drm_display_mode
*mode
= &pipe_config
->requested_mode
;
679 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
680 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
681 int lane_count
, clock
;
682 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
683 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
685 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
686 int target_clock
, link_avail
, link_clock
;
688 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && !is_cpu_edp(intel_dp
))
689 pipe_config
->has_pch_encoder
= true;
691 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
692 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
694 intel_pch_panel_fitting(dev
,
695 intel_connector
->panel
.fitting_mode
,
696 mode
, adjusted_mode
);
698 /* We need to take the panel's fixed mode into account. */
699 target_clock
= adjusted_mode
->clock
;
701 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
705 "max bw %02x pixel clock %iKHz\n",
706 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
708 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
711 if (is_edp(intel_dp
) && dev_priv
->edp
.bpp
)
712 bpp
= min_t(int, bpp
, dev_priv
->edp
.bpp
);
714 for (; bpp
>= 6*3; bpp
-= 2*3) {
715 mode_rate
= intel_dp_link_required(target_clock
, bpp
);
717 for (clock
= 0; clock
<= max_clock
; clock
++) {
718 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
719 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
720 link_avail
= intel_dp_max_data_rate(link_clock
,
723 if (mode_rate
<= link_avail
) {
733 if (intel_dp
->color_range_auto
) {
736 * CEA-861-E - 5.1 Default Encoding Parameters
737 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
739 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
740 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
742 intel_dp
->color_range
= 0;
745 if (intel_dp
->color_range
)
746 pipe_config
->limited_color_range
= true;
748 intel_dp
->link_bw
= bws
[clock
];
749 intel_dp
->lane_count
= lane_count
;
750 adjusted_mode
->clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
751 pipe_config
->pipe_bpp
= bpp
;
753 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
754 intel_dp
->link_bw
, intel_dp
->lane_count
,
755 adjusted_mode
->clock
, bpp
);
756 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
757 mode_rate
, link_avail
);
763 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
764 struct drm_display_mode
*adjusted_mode
)
766 struct drm_device
*dev
= crtc
->dev
;
767 struct intel_encoder
*intel_encoder
;
768 struct intel_dp
*intel_dp
;
769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
770 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
772 struct intel_link_m_n m_n
;
773 int pipe
= intel_crtc
->pipe
;
774 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
777 * Find the lane count in the intel_encoder private
779 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
780 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
782 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
783 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
785 lane_count
= intel_dp
->lane_count
;
791 * Compute the GMCH and Link ratios. The '3' here is
792 * the number of bytes_per_pixel post-LUT, which we always
793 * set up for 8-bits of R/G/B, or 3 bytes total.
795 intel_link_compute_m_n(intel_crtc
->config
.pipe_bpp
, lane_count
,
796 mode
->clock
, adjusted_mode
->clock
, &m_n
);
799 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
),
800 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
801 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
802 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
803 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
804 } else if (HAS_PCH_SPLIT(dev
)) {
805 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
806 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
807 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
808 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
809 } else if (IS_VALLEYVIEW(dev
)) {
810 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
811 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
812 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
813 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
815 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
816 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
817 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
818 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
819 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
823 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
825 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
826 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
827 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
828 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
830 * Check for DPCD version > 1.1 and enhanced framing support
832 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
833 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
834 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
838 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
840 struct drm_device
*dev
= crtc
->dev
;
841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
844 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
845 dpa_ctl
= I915_READ(DP_A
);
846 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
848 if (clock
< 200000) {
849 /* For a long time we've carried around a ILK-DevA w/a for the
850 * 160MHz clock. If we're really unlucky, it's still required.
852 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
853 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
855 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
858 I915_WRITE(DP_A
, dpa_ctl
);
865 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
866 struct drm_display_mode
*adjusted_mode
)
868 struct drm_device
*dev
= encoder
->dev
;
869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
870 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
871 struct drm_crtc
*crtc
= encoder
->crtc
;
872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
875 * There are four kinds of DP registers:
882 * IBX PCH and CPU are the same for almost everything,
883 * except that the CPU DP PLL is configured in this
886 * CPT PCH is quite different, having many bits moved
887 * to the TRANS_DP_CTL register instead. That
888 * configuration happens (oddly) in ironlake_pch_enable
891 /* Preserve the BIOS-computed detected bit. This is
892 * supposed to be read-only.
894 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
896 /* Handle DP bits in common between all three register formats */
897 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
899 switch (intel_dp
->lane_count
) {
901 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
904 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
907 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
910 if (intel_dp
->has_audio
) {
911 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
912 pipe_name(intel_crtc
->pipe
));
913 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
914 intel_write_eld(encoder
, adjusted_mode
);
917 intel_dp_init_link_config(intel_dp
);
919 /* Split out the IBX/CPU vs CPT settings */
921 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
922 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
923 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
924 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
925 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
926 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
928 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
929 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
931 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
933 /* don't miss out required setting for eDP */
934 if (adjusted_mode
->clock
< 200000)
935 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
937 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
938 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
939 if (!HAS_PCH_SPLIT(dev
))
940 intel_dp
->DP
|= intel_dp
->color_range
;
942 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
943 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
944 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
945 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
946 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
948 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
949 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
951 if (intel_crtc
->pipe
== 1)
952 intel_dp
->DP
|= DP_PIPEB_SELECT
;
954 if (is_cpu_edp(intel_dp
)) {
955 /* don't miss out required setting for eDP */
956 if (adjusted_mode
->clock
< 200000)
957 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
959 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
962 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
965 if (is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
))
966 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
969 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
970 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
972 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
973 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
975 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
976 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
978 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
982 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
985 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
987 I915_READ(PCH_PP_STATUS
),
988 I915_READ(PCH_PP_CONTROL
));
990 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
991 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
992 I915_READ(PCH_PP_STATUS
),
993 I915_READ(PCH_PP_CONTROL
));
997 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
999 DRM_DEBUG_KMS("Wait for panel power on\n");
1000 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1003 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
1005 DRM_DEBUG_KMS("Wait for panel power off time\n");
1006 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1009 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1011 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1012 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1016 /* Read the current pp_control value, unlocking the register if it
1020 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
1022 u32 control
= I915_READ(PCH_PP_CONTROL
);
1024 control
&= ~PANEL_UNLOCK_MASK
;
1025 control
|= PANEL_UNLOCK_REGS
;
1029 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1031 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1035 if (!is_edp(intel_dp
))
1037 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1039 WARN(intel_dp
->want_panel_vdd
,
1040 "eDP VDD already requested on\n");
1042 intel_dp
->want_panel_vdd
= true;
1044 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1045 DRM_DEBUG_KMS("eDP VDD already on\n");
1049 if (!ironlake_edp_have_panel_power(intel_dp
))
1050 ironlake_wait_panel_power_cycle(intel_dp
);
1052 pp
= ironlake_get_pp_control(dev_priv
);
1053 pp
|= EDP_FORCE_VDD
;
1054 I915_WRITE(PCH_PP_CONTROL
, pp
);
1055 POSTING_READ(PCH_PP_CONTROL
);
1056 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1057 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1060 * If the panel wasn't on, delay before accessing aux channel
1062 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1063 DRM_DEBUG_KMS("eDP was not running\n");
1064 msleep(intel_dp
->panel_power_up_delay
);
1068 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1070 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1074 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1076 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1077 pp
= ironlake_get_pp_control(dev_priv
);
1078 pp
&= ~EDP_FORCE_VDD
;
1079 I915_WRITE(PCH_PP_CONTROL
, pp
);
1080 POSTING_READ(PCH_PP_CONTROL
);
1082 /* Make sure sequencer is idle before allowing subsequent activity */
1083 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1084 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1086 msleep(intel_dp
->panel_power_down_delay
);
1090 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1092 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1093 struct intel_dp
, panel_vdd_work
);
1094 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1096 mutex_lock(&dev
->mode_config
.mutex
);
1097 ironlake_panel_vdd_off_sync(intel_dp
);
1098 mutex_unlock(&dev
->mode_config
.mutex
);
1101 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1103 if (!is_edp(intel_dp
))
1106 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1107 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1109 intel_dp
->want_panel_vdd
= false;
1112 ironlake_panel_vdd_off_sync(intel_dp
);
1115 * Queue the timer to fire a long
1116 * time from now (relative to the power down delay)
1117 * to keep the panel power up across a sequence of operations
1119 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1120 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1124 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1126 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1130 if (!is_edp(intel_dp
))
1133 DRM_DEBUG_KMS("Turn eDP power on\n");
1135 if (ironlake_edp_have_panel_power(intel_dp
)) {
1136 DRM_DEBUG_KMS("eDP power already on\n");
1140 ironlake_wait_panel_power_cycle(intel_dp
);
1142 pp
= ironlake_get_pp_control(dev_priv
);
1144 /* ILK workaround: disable reset around power sequence */
1145 pp
&= ~PANEL_POWER_RESET
;
1146 I915_WRITE(PCH_PP_CONTROL
, pp
);
1147 POSTING_READ(PCH_PP_CONTROL
);
1150 pp
|= POWER_TARGET_ON
;
1152 pp
|= PANEL_POWER_RESET
;
1154 I915_WRITE(PCH_PP_CONTROL
, pp
);
1155 POSTING_READ(PCH_PP_CONTROL
);
1157 ironlake_wait_panel_on(intel_dp
);
1160 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1161 I915_WRITE(PCH_PP_CONTROL
, pp
);
1162 POSTING_READ(PCH_PP_CONTROL
);
1166 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1168 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1172 if (!is_edp(intel_dp
))
1175 DRM_DEBUG_KMS("Turn eDP power off\n");
1177 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1179 pp
= ironlake_get_pp_control(dev_priv
);
1180 /* We need to switch off panel power _and_ force vdd, for otherwise some
1181 * panels get very unhappy and cease to work. */
1182 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1183 I915_WRITE(PCH_PP_CONTROL
, pp
);
1184 POSTING_READ(PCH_PP_CONTROL
);
1186 intel_dp
->want_panel_vdd
= false;
1188 ironlake_wait_panel_off(intel_dp
);
1191 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1193 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1194 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1196 int pipe
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
)->pipe
;
1199 if (!is_edp(intel_dp
))
1202 DRM_DEBUG_KMS("\n");
1204 * If we enable the backlight right away following a panel power
1205 * on, we may see slight flicker as the panel syncs with the eDP
1206 * link. So delay a bit to make sure the image is solid before
1207 * allowing it to appear.
1209 msleep(intel_dp
->backlight_on_delay
);
1210 pp
= ironlake_get_pp_control(dev_priv
);
1211 pp
|= EDP_BLC_ENABLE
;
1212 I915_WRITE(PCH_PP_CONTROL
, pp
);
1213 POSTING_READ(PCH_PP_CONTROL
);
1215 intel_panel_enable_backlight(dev
, pipe
);
1218 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1220 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1224 if (!is_edp(intel_dp
))
1227 intel_panel_disable_backlight(dev
);
1229 DRM_DEBUG_KMS("\n");
1230 pp
= ironlake_get_pp_control(dev_priv
);
1231 pp
&= ~EDP_BLC_ENABLE
;
1232 I915_WRITE(PCH_PP_CONTROL
, pp
);
1233 POSTING_READ(PCH_PP_CONTROL
);
1234 msleep(intel_dp
->backlight_off_delay
);
1237 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1239 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1240 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1241 struct drm_device
*dev
= crtc
->dev
;
1242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1245 assert_pipe_disabled(dev_priv
,
1246 to_intel_crtc(crtc
)->pipe
);
1248 DRM_DEBUG_KMS("\n");
1249 dpa_ctl
= I915_READ(DP_A
);
1250 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1251 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1253 /* We don't adjust intel_dp->DP while tearing down the link, to
1254 * facilitate link retraining (e.g. after hotplug). Hence clear all
1255 * enable bits here to ensure that we don't enable too much. */
1256 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1257 intel_dp
->DP
|= DP_PLL_ENABLE
;
1258 I915_WRITE(DP_A
, intel_dp
->DP
);
1263 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1265 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1266 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1267 struct drm_device
*dev
= crtc
->dev
;
1268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1271 assert_pipe_disabled(dev_priv
,
1272 to_intel_crtc(crtc
)->pipe
);
1274 dpa_ctl
= I915_READ(DP_A
);
1275 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1276 "dp pll off, should be on\n");
1277 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1279 /* We can't rely on the value tracked for the DP register in
1280 * intel_dp->DP because link_down must not change that (otherwise link
1281 * re-training will fail. */
1282 dpa_ctl
&= ~DP_PLL_ENABLE
;
1283 I915_WRITE(DP_A
, dpa_ctl
);
1288 /* If the sink supports it, try to set the power state appropriately */
1289 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1293 /* Should have a valid DPCD by this point */
1294 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1297 if (mode
!= DRM_MODE_DPMS_ON
) {
1298 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1301 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1304 * When turning on, we need to retry for 1ms to give the sink
1307 for (i
= 0; i
< 3; i
++) {
1308 ret
= intel_dp_aux_native_write_1(intel_dp
,
1318 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1321 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1322 struct drm_device
*dev
= encoder
->base
.dev
;
1323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1324 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1326 if (!(tmp
& DP_PORT_EN
))
1329 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1330 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1331 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1332 *pipe
= PORT_TO_PIPE(tmp
);
1338 switch (intel_dp
->output_reg
) {
1340 trans_sel
= TRANS_DP_PORT_SEL_B
;
1343 trans_sel
= TRANS_DP_PORT_SEL_C
;
1346 trans_sel
= TRANS_DP_PORT_SEL_D
;
1353 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1354 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1360 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1361 intel_dp
->output_reg
);
1367 static void intel_disable_dp(struct intel_encoder
*encoder
)
1369 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1371 /* Make sure the panel is off before trying to change the mode. But also
1372 * ensure that we have vdd while we switch off the panel. */
1373 ironlake_edp_panel_vdd_on(intel_dp
);
1374 ironlake_edp_backlight_off(intel_dp
);
1375 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1376 ironlake_edp_panel_off(intel_dp
);
1378 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1379 if (!is_cpu_edp(intel_dp
))
1380 intel_dp_link_down(intel_dp
);
1383 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1385 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1387 if (is_cpu_edp(intel_dp
)) {
1388 intel_dp_link_down(intel_dp
);
1389 ironlake_edp_pll_off(intel_dp
);
1393 static void intel_enable_dp(struct intel_encoder
*encoder
)
1395 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1396 struct drm_device
*dev
= encoder
->base
.dev
;
1397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1398 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1400 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1403 ironlake_edp_panel_vdd_on(intel_dp
);
1404 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1405 intel_dp_start_link_train(intel_dp
);
1406 ironlake_edp_panel_on(intel_dp
);
1407 ironlake_edp_panel_vdd_off(intel_dp
, true);
1408 intel_dp_complete_link_train(intel_dp
);
1409 ironlake_edp_backlight_on(intel_dp
);
1412 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1414 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1416 if (is_cpu_edp(intel_dp
))
1417 ironlake_edp_pll_on(intel_dp
);
1421 * Native read with retry for link status and receiver capability reads for
1422 * cases where the sink may still be asleep.
1425 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1426 uint8_t *recv
, int recv_bytes
)
1431 * Sinks are *supposed* to come up within 1ms from an off state,
1432 * but we're also supposed to retry 3 times per the spec.
1434 for (i
= 0; i
< 3; i
++) {
1435 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1437 if (ret
== recv_bytes
)
1446 * Fetch AUX CH registers 0x202 - 0x207 which contain
1447 * link status information
1450 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1452 return intel_dp_aux_native_read_retry(intel_dp
,
1455 DP_LINK_STATUS_SIZE
);
1459 static char *voltage_names
[] = {
1460 "0.4V", "0.6V", "0.8V", "1.2V"
1462 static char *pre_emph_names
[] = {
1463 "0dB", "3.5dB", "6dB", "9.5dB"
1465 static char *link_train_names
[] = {
1466 "pattern 1", "pattern 2", "idle", "off"
1471 * These are source-specific values; current Intel hardware supports
1472 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1476 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1478 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1480 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1481 return DP_TRAIN_VOLTAGE_SWING_800
;
1482 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1483 return DP_TRAIN_VOLTAGE_SWING_1200
;
1485 return DP_TRAIN_VOLTAGE_SWING_800
;
1489 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1491 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1494 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1495 case DP_TRAIN_VOLTAGE_SWING_400
:
1496 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1497 case DP_TRAIN_VOLTAGE_SWING_600
:
1498 return DP_TRAIN_PRE_EMPHASIS_6
;
1499 case DP_TRAIN_VOLTAGE_SWING_800
:
1500 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1501 case DP_TRAIN_VOLTAGE_SWING_1200
:
1503 return DP_TRAIN_PRE_EMPHASIS_0
;
1505 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1506 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1507 case DP_TRAIN_VOLTAGE_SWING_400
:
1508 return DP_TRAIN_PRE_EMPHASIS_6
;
1509 case DP_TRAIN_VOLTAGE_SWING_600
:
1510 case DP_TRAIN_VOLTAGE_SWING_800
:
1511 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1513 return DP_TRAIN_PRE_EMPHASIS_0
;
1516 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1517 case DP_TRAIN_VOLTAGE_SWING_400
:
1518 return DP_TRAIN_PRE_EMPHASIS_6
;
1519 case DP_TRAIN_VOLTAGE_SWING_600
:
1520 return DP_TRAIN_PRE_EMPHASIS_6
;
1521 case DP_TRAIN_VOLTAGE_SWING_800
:
1522 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1523 case DP_TRAIN_VOLTAGE_SWING_1200
:
1525 return DP_TRAIN_PRE_EMPHASIS_0
;
1531 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1536 uint8_t voltage_max
;
1537 uint8_t preemph_max
;
1539 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1540 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
1541 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
1549 voltage_max
= intel_dp_voltage_max(intel_dp
);
1550 if (v
>= voltage_max
)
1551 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1553 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1554 if (p
>= preemph_max
)
1555 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1557 for (lane
= 0; lane
< 4; lane
++)
1558 intel_dp
->train_set
[lane
] = v
| p
;
1562 intel_gen4_signal_levels(uint8_t train_set
)
1564 uint32_t signal_levels
= 0;
1566 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1567 case DP_TRAIN_VOLTAGE_SWING_400
:
1569 signal_levels
|= DP_VOLTAGE_0_4
;
1571 case DP_TRAIN_VOLTAGE_SWING_600
:
1572 signal_levels
|= DP_VOLTAGE_0_6
;
1574 case DP_TRAIN_VOLTAGE_SWING_800
:
1575 signal_levels
|= DP_VOLTAGE_0_8
;
1577 case DP_TRAIN_VOLTAGE_SWING_1200
:
1578 signal_levels
|= DP_VOLTAGE_1_2
;
1581 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1582 case DP_TRAIN_PRE_EMPHASIS_0
:
1584 signal_levels
|= DP_PRE_EMPHASIS_0
;
1586 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1587 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1589 case DP_TRAIN_PRE_EMPHASIS_6
:
1590 signal_levels
|= DP_PRE_EMPHASIS_6
;
1592 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1593 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1596 return signal_levels
;
1599 /* Gen6's DP voltage swing and pre-emphasis control */
1601 intel_gen6_edp_signal_levels(uint8_t train_set
)
1603 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1604 DP_TRAIN_PRE_EMPHASIS_MASK
);
1605 switch (signal_levels
) {
1606 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1607 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1608 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1609 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1610 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1611 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1612 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1613 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1614 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1615 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1616 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1617 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1618 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1619 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1621 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1622 "0x%x\n", signal_levels
);
1623 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1627 /* Gen7's DP voltage swing and pre-emphasis control */
1629 intel_gen7_edp_signal_levels(uint8_t train_set
)
1631 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1632 DP_TRAIN_PRE_EMPHASIS_MASK
);
1633 switch (signal_levels
) {
1634 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1635 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1636 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1637 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1638 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1639 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1641 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1642 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1643 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1644 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1646 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1647 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1648 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1649 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1652 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1653 "0x%x\n", signal_levels
);
1654 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1658 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1660 intel_hsw_signal_levels(uint8_t train_set
)
1662 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1663 DP_TRAIN_PRE_EMPHASIS_MASK
);
1664 switch (signal_levels
) {
1665 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1666 return DDI_BUF_EMP_400MV_0DB_HSW
;
1667 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1668 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1669 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1670 return DDI_BUF_EMP_400MV_6DB_HSW
;
1671 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1672 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1674 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1675 return DDI_BUF_EMP_600MV_0DB_HSW
;
1676 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1677 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1678 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1679 return DDI_BUF_EMP_600MV_6DB_HSW
;
1681 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1682 return DDI_BUF_EMP_800MV_0DB_HSW
;
1683 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1684 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1686 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1687 "0x%x\n", signal_levels
);
1688 return DDI_BUF_EMP_400MV_0DB_HSW
;
1692 /* Properly updates "DP" with the correct signal levels. */
1694 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
1696 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1697 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1698 uint32_t signal_levels
, mask
;
1699 uint8_t train_set
= intel_dp
->train_set
[0];
1702 signal_levels
= intel_hsw_signal_levels(train_set
);
1703 mask
= DDI_BUF_EMP_MASK
;
1704 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1705 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
1706 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
1707 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1708 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
1709 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
1711 signal_levels
= intel_gen4_signal_levels(train_set
);
1712 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
1715 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
1717 *DP
= (*DP
& ~mask
) | signal_levels
;
1721 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1722 uint32_t dp_reg_value
,
1723 uint8_t dp_train_pat
)
1725 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1726 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1728 enum port port
= intel_dig_port
->port
;
1733 temp
= I915_READ(DP_TP_CTL(port
));
1735 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1736 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1738 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1740 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1741 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1742 case DP_TRAINING_PATTERN_DISABLE
:
1744 if (port
!= PORT_A
) {
1745 temp
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1746 I915_WRITE(DP_TP_CTL(port
), temp
);
1748 if (wait_for((I915_READ(DP_TP_STATUS(port
)) &
1749 DP_TP_STATUS_IDLE_DONE
), 1))
1750 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1752 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1755 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1758 case DP_TRAINING_PATTERN_1
:
1759 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1761 case DP_TRAINING_PATTERN_2
:
1762 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1764 case DP_TRAINING_PATTERN_3
:
1765 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1768 I915_WRITE(DP_TP_CTL(port
), temp
);
1770 } else if (HAS_PCH_CPT(dev
) &&
1771 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1772 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1774 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1775 case DP_TRAINING_PATTERN_DISABLE
:
1776 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1778 case DP_TRAINING_PATTERN_1
:
1779 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1781 case DP_TRAINING_PATTERN_2
:
1782 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1784 case DP_TRAINING_PATTERN_3
:
1785 DRM_ERROR("DP training pattern 3 not supported\n");
1786 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1791 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1793 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1794 case DP_TRAINING_PATTERN_DISABLE
:
1795 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1797 case DP_TRAINING_PATTERN_1
:
1798 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1800 case DP_TRAINING_PATTERN_2
:
1801 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1803 case DP_TRAINING_PATTERN_3
:
1804 DRM_ERROR("DP training pattern 3 not supported\n");
1805 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1810 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1811 POSTING_READ(intel_dp
->output_reg
);
1813 intel_dp_aux_native_write_1(intel_dp
,
1814 DP_TRAINING_PATTERN_SET
,
1817 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1818 DP_TRAINING_PATTERN_DISABLE
) {
1819 ret
= intel_dp_aux_native_write(intel_dp
,
1820 DP_TRAINING_LANE0_SET
,
1821 intel_dp
->train_set
,
1822 intel_dp
->lane_count
);
1823 if (ret
!= intel_dp
->lane_count
)
1830 /* Enable corresponding port and start training pattern 1 */
1832 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1834 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
1835 struct drm_device
*dev
= encoder
->dev
;
1838 bool clock_recovery
= false;
1839 int voltage_tries
, loop_tries
;
1840 uint32_t DP
= intel_dp
->DP
;
1843 intel_ddi_prepare_link_retrain(encoder
);
1845 /* Write the link configuration data */
1846 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1847 intel_dp
->link_configuration
,
1848 DP_LINK_CONFIGURATION_SIZE
);
1852 memset(intel_dp
->train_set
, 0, 4);
1856 clock_recovery
= false;
1858 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1859 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1861 intel_dp_set_signal_levels(intel_dp
, &DP
);
1863 /* Set training pattern 1 */
1864 if (!intel_dp_set_link_train(intel_dp
, DP
,
1865 DP_TRAINING_PATTERN_1
|
1866 DP_LINK_SCRAMBLING_DISABLE
))
1869 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
1870 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1871 DRM_ERROR("failed to get link status\n");
1875 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1876 DRM_DEBUG_KMS("clock recovery OK\n");
1877 clock_recovery
= true;
1881 /* Check to see if we've tried the max voltage */
1882 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1883 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1885 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1887 if (loop_tries
== 5) {
1888 DRM_DEBUG_KMS("too many full retries, give up\n");
1891 memset(intel_dp
->train_set
, 0, 4);
1896 /* Check to see if we've tried the same voltage 5 times */
1897 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1899 if (voltage_tries
== 5) {
1900 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1905 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1907 /* Compute new intel_dp->train_set as requested by target */
1908 intel_get_adjust_train(intel_dp
, link_status
);
1915 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1917 bool channel_eq
= false;
1918 int tries
, cr_tries
;
1919 uint32_t DP
= intel_dp
->DP
;
1921 /* channel equalization */
1926 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1929 DRM_ERROR("failed to train DP, aborting\n");
1930 intel_dp_link_down(intel_dp
);
1934 intel_dp_set_signal_levels(intel_dp
, &DP
);
1936 /* channel eq pattern */
1937 if (!intel_dp_set_link_train(intel_dp
, DP
,
1938 DP_TRAINING_PATTERN_2
|
1939 DP_LINK_SCRAMBLING_DISABLE
))
1942 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
1943 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1946 /* Make sure clock is still ok */
1947 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1948 intel_dp_start_link_train(intel_dp
);
1953 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
1958 /* Try 5 times, then try clock recovery if that fails */
1960 intel_dp_link_down(intel_dp
);
1961 intel_dp_start_link_train(intel_dp
);
1967 /* Compute new intel_dp->train_set as requested by target */
1968 intel_get_adjust_train(intel_dp
, link_status
);
1973 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1975 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
1979 intel_dp_link_down(struct intel_dp
*intel_dp
)
1981 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1982 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1984 struct intel_crtc
*intel_crtc
=
1985 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
1986 uint32_t DP
= intel_dp
->DP
;
1989 * DDI code has a strict mode set sequence and we should try to respect
1990 * it, otherwise we might hang the machine in many different ways. So we
1991 * really should be disabling the port only on a complete crtc_disable
1992 * sequence. This function is just called under two conditions on DDI
1994 * - Link train failed while doing crtc_enable, and on this case we
1995 * really should respect the mode set sequence and wait for a
1997 * - Someone turned the monitor off and intel_dp_check_link_status
1998 * called us. We don't need to disable the whole port on this case, so
1999 * when someone turns the monitor on again,
2000 * intel_ddi_prepare_link_retrain will take care of redoing the link
2006 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2009 DRM_DEBUG_KMS("\n");
2011 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
2012 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2013 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2015 DP
&= ~DP_LINK_TRAIN_MASK
;
2016 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2018 POSTING_READ(intel_dp
->output_reg
);
2020 /* We don't really know why we're doing this */
2021 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2023 if (HAS_PCH_IBX(dev
) &&
2024 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2025 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2027 /* Hardware workaround: leaving our transcoder select
2028 * set to transcoder B while it's off will prevent the
2029 * corresponding HDMI output on transcoder A.
2031 * Combine this with another hardware workaround:
2032 * transcoder select bit can only be cleared while the
2035 DP
&= ~DP_PIPEB_SELECT
;
2036 I915_WRITE(intel_dp
->output_reg
, DP
);
2038 /* Changes to enable or select take place the vblank
2039 * after being written.
2041 if (WARN_ON(crtc
== NULL
)) {
2042 /* We should never try to disable a port without a crtc
2043 * attached. For paranoia keep the code around for a
2045 POSTING_READ(intel_dp
->output_reg
);
2048 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2051 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2052 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2053 POSTING_READ(intel_dp
->output_reg
);
2054 msleep(intel_dp
->panel_power_down_delay
);
2058 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2060 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2062 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2063 sizeof(intel_dp
->dpcd
)) == 0)
2064 return false; /* aux transfer failed */
2066 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2067 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2068 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2070 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2071 return false; /* DPCD not present */
2073 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2074 DP_DWN_STRM_PORT_PRESENT
))
2075 return true; /* native DP sink */
2077 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2078 return true; /* no per-port downstream info */
2080 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2081 intel_dp
->downstream_ports
,
2082 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2083 return false; /* downstream port status fetch failed */
2089 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2093 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2096 ironlake_edp_panel_vdd_on(intel_dp
);
2098 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2099 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2100 buf
[0], buf
[1], buf
[2]);
2102 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2103 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2104 buf
[0], buf
[1], buf
[2]);
2106 ironlake_edp_panel_vdd_off(intel_dp
, false);
2110 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2114 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2115 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2116 sink_irq_vector
, 1);
2124 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2126 /* NAK by default */
2127 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2131 * According to DP spec
2134 * 2. Configure link according to Receiver Capabilities
2135 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2136 * 4. Check link status on receipt of hot-plug interrupt
2140 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2142 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2144 u8 link_status
[DP_LINK_STATUS_SIZE
];
2146 if (!intel_encoder
->connectors_active
)
2149 if (WARN_ON(!intel_encoder
->base
.crtc
))
2152 /* Try to read receiver status if the link appears to be up */
2153 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2154 intel_dp_link_down(intel_dp
);
2158 /* Now read the DPCD to see if it's actually running */
2159 if (!intel_dp_get_dpcd(intel_dp
)) {
2160 intel_dp_link_down(intel_dp
);
2164 /* Try to read the source of the interrupt */
2165 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2166 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2167 /* Clear interrupt source */
2168 intel_dp_aux_native_write_1(intel_dp
,
2169 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2172 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2173 intel_dp_handle_test_request(intel_dp
);
2174 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2175 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2178 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2179 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2180 drm_get_encoder_name(&intel_encoder
->base
));
2181 intel_dp_start_link_train(intel_dp
);
2182 intel_dp_complete_link_train(intel_dp
);
2186 /* XXX this is probably wrong for multiple downstream ports */
2187 static enum drm_connector_status
2188 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2190 uint8_t *dpcd
= intel_dp
->dpcd
;
2194 if (!intel_dp_get_dpcd(intel_dp
))
2195 return connector_status_disconnected
;
2197 /* if there's no downstream port, we're done */
2198 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2199 return connector_status_connected
;
2201 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2202 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2205 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2207 return connector_status_unknown
;
2208 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2209 : connector_status_disconnected
;
2212 /* If no HPD, poke DDC gently */
2213 if (drm_probe_ddc(&intel_dp
->adapter
))
2214 return connector_status_connected
;
2216 /* Well we tried, say unknown for unreliable port types */
2217 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2218 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2219 return connector_status_unknown
;
2221 /* Anything else is out of spec, warn and ignore */
2222 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2223 return connector_status_disconnected
;
2226 static enum drm_connector_status
2227 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2229 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2231 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2232 enum drm_connector_status status
;
2234 /* Can't disconnect eDP, but you can close the lid... */
2235 if (is_edp(intel_dp
)) {
2236 status
= intel_panel_detect(dev
);
2237 if (status
== connector_status_unknown
)
2238 status
= connector_status_connected
;
2242 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
2243 return connector_status_disconnected
;
2245 return intel_dp_detect_dpcd(intel_dp
);
2248 static enum drm_connector_status
2249 g4x_dp_detect(struct intel_dp
*intel_dp
)
2251 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2253 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2256 /* Can't disconnect eDP, but you can close the lid... */
2257 if (is_edp(intel_dp
)) {
2258 enum drm_connector_status status
;
2260 status
= intel_panel_detect(dev
);
2261 if (status
== connector_status_unknown
)
2262 status
= connector_status_connected
;
2266 switch (intel_dig_port
->port
) {
2268 bit
= PORTB_HOTPLUG_LIVE_STATUS
;
2271 bit
= PORTC_HOTPLUG_LIVE_STATUS
;
2274 bit
= PORTD_HOTPLUG_LIVE_STATUS
;
2277 return connector_status_unknown
;
2280 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2281 return connector_status_disconnected
;
2283 return intel_dp_detect_dpcd(intel_dp
);
2286 static struct edid
*
2287 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2289 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2291 /* use cached edid if we have one */
2292 if (intel_connector
->edid
) {
2297 if (IS_ERR(intel_connector
->edid
))
2300 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2301 edid
= kmalloc(size
, GFP_KERNEL
);
2305 memcpy(edid
, intel_connector
->edid
, size
);
2309 return drm_get_edid(connector
, adapter
);
2313 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2315 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2317 /* use cached edid if we have one */
2318 if (intel_connector
->edid
) {
2320 if (IS_ERR(intel_connector
->edid
))
2323 return intel_connector_update_modes(connector
,
2324 intel_connector
->edid
);
2327 return intel_ddc_get_modes(connector
, adapter
);
2330 static enum drm_connector_status
2331 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2333 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2334 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2335 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2336 struct drm_device
*dev
= connector
->dev
;
2337 enum drm_connector_status status
;
2338 struct edid
*edid
= NULL
;
2340 intel_dp
->has_audio
= false;
2342 if (HAS_PCH_SPLIT(dev
))
2343 status
= ironlake_dp_detect(intel_dp
);
2345 status
= g4x_dp_detect(intel_dp
);
2347 if (status
!= connector_status_connected
)
2350 intel_dp_probe_oui(intel_dp
);
2352 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2353 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2355 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2357 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2362 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
2363 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2364 return connector_status_connected
;
2367 static int intel_dp_get_modes(struct drm_connector
*connector
)
2369 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2370 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2371 struct drm_device
*dev
= connector
->dev
;
2374 /* We should parse the EDID data and find out if it has an audio sink
2377 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2381 /* if eDP has no EDID, fall back to fixed mode */
2382 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2383 struct drm_display_mode
*mode
;
2384 mode
= drm_mode_duplicate(dev
,
2385 intel_connector
->panel
.fixed_mode
);
2387 drm_mode_probed_add(connector
, mode
);
2395 intel_dp_detect_audio(struct drm_connector
*connector
)
2397 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2399 bool has_audio
= false;
2401 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2403 has_audio
= drm_detect_monitor_audio(edid
);
2411 intel_dp_set_property(struct drm_connector
*connector
,
2412 struct drm_property
*property
,
2415 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2416 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2417 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
2418 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2421 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
2425 if (property
== dev_priv
->force_audio_property
) {
2429 if (i
== intel_dp
->force_audio
)
2432 intel_dp
->force_audio
= i
;
2434 if (i
== HDMI_AUDIO_AUTO
)
2435 has_audio
= intel_dp_detect_audio(connector
);
2437 has_audio
= (i
== HDMI_AUDIO_ON
);
2439 if (has_audio
== intel_dp
->has_audio
)
2442 intel_dp
->has_audio
= has_audio
;
2446 if (property
== dev_priv
->broadcast_rgb_property
) {
2448 case INTEL_BROADCAST_RGB_AUTO
:
2449 intel_dp
->color_range_auto
= true;
2451 case INTEL_BROADCAST_RGB_FULL
:
2452 intel_dp
->color_range_auto
= false;
2453 intel_dp
->color_range
= 0;
2455 case INTEL_BROADCAST_RGB_LIMITED
:
2456 intel_dp
->color_range_auto
= false;
2457 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
2465 if (is_edp(intel_dp
) &&
2466 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
2467 if (val
== DRM_MODE_SCALE_NONE
) {
2468 DRM_DEBUG_KMS("no scaling not supported\n");
2472 if (intel_connector
->panel
.fitting_mode
== val
) {
2473 /* the eDP scaling property is not changed */
2476 intel_connector
->panel
.fitting_mode
= val
;
2484 if (intel_encoder
->base
.crtc
)
2485 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
2491 intel_dp_destroy(struct drm_connector
*connector
)
2493 struct drm_device
*dev
= connector
->dev
;
2494 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2495 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2497 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
2498 kfree(intel_connector
->edid
);
2500 if (is_edp(intel_dp
)) {
2501 intel_panel_destroy_backlight(dev
);
2502 intel_panel_fini(&intel_connector
->panel
);
2505 drm_sysfs_connector_remove(connector
);
2506 drm_connector_cleanup(connector
);
2510 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2512 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2513 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2515 i2c_del_adapter(&intel_dp
->adapter
);
2516 drm_encoder_cleanup(encoder
);
2517 if (is_edp(intel_dp
)) {
2518 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2519 ironlake_panel_vdd_off_sync(intel_dp
);
2521 kfree(intel_dig_port
);
2524 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2525 .mode_set
= intel_dp_mode_set
,
2528 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2529 .dpms
= intel_connector_dpms
,
2530 .detect
= intel_dp_detect
,
2531 .fill_modes
= drm_helper_probe_single_connector_modes
,
2532 .set_property
= intel_dp_set_property
,
2533 .destroy
= intel_dp_destroy
,
2536 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2537 .get_modes
= intel_dp_get_modes
,
2538 .mode_valid
= intel_dp_mode_valid
,
2539 .best_encoder
= intel_best_encoder
,
2542 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2543 .destroy
= intel_dp_encoder_destroy
,
2547 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2549 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2551 intel_dp_check_link_status(intel_dp
);
2554 /* Return which DP Port should be selected for Transcoder DP control */
2556 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2558 struct drm_device
*dev
= crtc
->dev
;
2559 struct intel_encoder
*intel_encoder
;
2560 struct intel_dp
*intel_dp
;
2562 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2563 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2565 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2566 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2567 return intel_dp
->output_reg
;
2573 /* check the VBT to see whether the eDP is on DP-D port */
2574 bool intel_dpd_is_edp(struct drm_device
*dev
)
2576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2577 struct child_device_config
*p_child
;
2580 if (!dev_priv
->child_dev_num
)
2583 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2584 p_child
= dev_priv
->child_dev
+ i
;
2586 if (p_child
->dvo_port
== PORT_IDPD
&&
2587 p_child
->device_type
== DEVICE_TYPE_eDP
)
2594 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2596 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2598 intel_attach_force_audio_property(connector
);
2599 intel_attach_broadcast_rgb_property(connector
);
2600 intel_dp
->color_range_auto
= true;
2602 if (is_edp(intel_dp
)) {
2603 drm_mode_create_scaling_mode_property(connector
->dev
);
2604 drm_object_attach_property(
2606 connector
->dev
->mode_config
.scaling_mode_property
,
2607 DRM_MODE_SCALE_ASPECT
);
2608 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
2613 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
2614 struct intel_dp
*intel_dp
,
2615 struct edp_power_seq
*out
)
2617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2618 struct edp_power_seq cur
, vbt
, spec
, final
;
2619 u32 pp_on
, pp_off
, pp_div
, pp
;
2621 /* Workaround: Need to write PP_CONTROL with the unlock key as
2622 * the very first thing. */
2623 pp
= ironlake_get_pp_control(dev_priv
);
2624 I915_WRITE(PCH_PP_CONTROL
, pp
);
2626 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2627 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2628 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2630 /* Pull timing values out of registers */
2631 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2632 PANEL_POWER_UP_DELAY_SHIFT
;
2634 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2635 PANEL_LIGHT_ON_DELAY_SHIFT
;
2637 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2638 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2640 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2641 PANEL_POWER_DOWN_DELAY_SHIFT
;
2643 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2644 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2646 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2647 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2649 vbt
= dev_priv
->edp
.pps
;
2651 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2652 * our hw here, which are all in 100usec. */
2653 spec
.t1_t3
= 210 * 10;
2654 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
2655 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
2656 spec
.t10
= 500 * 10;
2657 /* This one is special and actually in units of 100ms, but zero
2658 * based in the hw (so we need to add 100 ms). But the sw vbt
2659 * table multiplies it with 1000 to make it in units of 100usec,
2661 spec
.t11_t12
= (510 + 100) * 10;
2663 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2664 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2666 /* Use the max of the register settings and vbt. If both are
2667 * unset, fall back to the spec limits. */
2668 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2670 max(cur.field, vbt.field))
2671 assign_final(t1_t3
);
2675 assign_final(t11_t12
);
2678 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2679 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2680 intel_dp
->backlight_on_delay
= get_delay(t8
);
2681 intel_dp
->backlight_off_delay
= get_delay(t9
);
2682 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2683 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2686 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2687 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2688 intel_dp
->panel_power_cycle_delay
);
2690 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2691 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2698 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
2699 struct intel_dp
*intel_dp
,
2700 struct edp_power_seq
*seq
)
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2703 u32 pp_on
, pp_off
, pp_div
;
2705 /* And finally store the new values in the power sequencer. */
2706 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
2707 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
2708 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
2709 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
2710 /* Compute the divisor for the pp clock, simply match the Bspec
2712 pp_div
= ((100 * intel_pch_rawclk(dev
))/2 - 1)
2713 << PP_REFERENCE_DIVIDER_SHIFT
;
2714 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
2715 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
2717 /* Haswell doesn't have any port selection bits for the panel
2718 * power sequencer any more. */
2719 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
2720 if (is_cpu_edp(intel_dp
))
2721 pp_on
|= PANEL_POWER_PORT_DP_A
;
2723 pp_on
|= PANEL_POWER_PORT_DP_D
;
2726 I915_WRITE(PCH_PP_ON_DELAYS
, pp_on
);
2727 I915_WRITE(PCH_PP_OFF_DELAYS
, pp_off
);
2728 I915_WRITE(PCH_PP_DIVISOR
, pp_div
);
2730 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2731 I915_READ(PCH_PP_ON_DELAYS
),
2732 I915_READ(PCH_PP_OFF_DELAYS
),
2733 I915_READ(PCH_PP_DIVISOR
));
2737 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
2738 struct intel_connector
*intel_connector
)
2740 struct drm_connector
*connector
= &intel_connector
->base
;
2741 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2742 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2743 struct drm_device
*dev
= intel_encoder
->base
.dev
;
2744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2745 struct drm_display_mode
*fixed_mode
= NULL
;
2746 struct edp_power_seq power_seq
= { 0 };
2747 enum port port
= intel_dig_port
->port
;
2748 const char *name
= NULL
;
2751 /* Preserve the current hw state. */
2752 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2753 intel_dp
->attached_connector
= intel_connector
;
2755 if (HAS_PCH_SPLIT(dev
) && port
== PORT_D
)
2756 if (intel_dpd_is_edp(dev
))
2757 intel_dp
->is_pch_edp
= true;
2760 * FIXME : We need to initialize built-in panels before external panels.
2761 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2763 if (IS_VALLEYVIEW(dev
) && port
== PORT_C
) {
2764 type
= DRM_MODE_CONNECTOR_eDP
;
2765 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2766 } else if (port
== PORT_A
|| is_pch_edp(intel_dp
)) {
2767 type
= DRM_MODE_CONNECTOR_eDP
;
2768 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2770 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2771 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2774 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2777 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2778 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2780 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2781 connector
->interlace_allowed
= true;
2782 connector
->doublescan_allowed
= 0;
2784 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2785 ironlake_panel_vdd_work
);
2787 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2788 drm_sysfs_connector_add(connector
);
2791 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
2793 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2795 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
2797 switch (intel_dig_port
->port
) {
2799 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
2802 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
2805 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
2808 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
2815 /* Set up the DDC bus. */
2818 intel_encoder
->hpd_pin
= HPD_PORT_A
;
2822 intel_encoder
->hpd_pin
= HPD_PORT_B
;
2826 intel_encoder
->hpd_pin
= HPD_PORT_C
;
2830 intel_encoder
->hpd_pin
= HPD_PORT_D
;
2837 if (is_edp(intel_dp
))
2838 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2840 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2842 /* Cache DPCD and EDID for edp. */
2843 if (is_edp(intel_dp
)) {
2845 struct drm_display_mode
*scan
;
2848 ironlake_edp_panel_vdd_on(intel_dp
);
2849 ret
= intel_dp_get_dpcd(intel_dp
);
2850 ironlake_edp_panel_vdd_off(intel_dp
, false);
2853 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2854 dev_priv
->no_aux_handshake
=
2855 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2856 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2858 /* if this fails, presume the device is a ghost */
2859 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2860 intel_dp_encoder_destroy(&intel_encoder
->base
);
2861 intel_dp_destroy(connector
);
2865 /* We now know it's not a ghost, init power sequence regs. */
2866 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2869 ironlake_edp_panel_vdd_on(intel_dp
);
2870 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2872 if (drm_add_edid_modes(connector
, edid
)) {
2873 drm_mode_connector_update_edid_property(connector
, edid
);
2874 drm_edid_to_eld(connector
, edid
);
2877 edid
= ERR_PTR(-EINVAL
);
2880 edid
= ERR_PTR(-ENOENT
);
2882 intel_connector
->edid
= edid
;
2884 /* prefer fixed mode from EDID if available */
2885 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
2886 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2887 fixed_mode
= drm_mode_duplicate(dev
, scan
);
2892 /* fallback to VBT if available for eDP */
2893 if (!fixed_mode
&& dev_priv
->lfp_lvds_vbt_mode
) {
2894 fixed_mode
= drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2896 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2899 ironlake_edp_panel_vdd_off(intel_dp
, false);
2902 if (is_edp(intel_dp
)) {
2903 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
2904 intel_panel_setup_backlight(connector
);
2907 intel_dp_add_properties(intel_dp
, connector
);
2909 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2910 * 0xd. Failure to do so will result in spurious interrupts being
2911 * generated on the port when a cable is not attached.
2913 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2914 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2915 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
2920 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2922 struct intel_digital_port
*intel_dig_port
;
2923 struct intel_encoder
*intel_encoder
;
2924 struct drm_encoder
*encoder
;
2925 struct intel_connector
*intel_connector
;
2927 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
2928 if (!intel_dig_port
)
2931 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2932 if (!intel_connector
) {
2933 kfree(intel_dig_port
);
2937 intel_encoder
= &intel_dig_port
->base
;
2938 encoder
= &intel_encoder
->base
;
2940 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2941 DRM_MODE_ENCODER_TMDS
);
2942 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2944 intel_encoder
->compute_config
= intel_dp_compute_config
;
2945 intel_encoder
->enable
= intel_enable_dp
;
2946 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2947 intel_encoder
->disable
= intel_disable_dp
;
2948 intel_encoder
->post_disable
= intel_post_disable_dp
;
2949 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2951 intel_dig_port
->port
= port
;
2952 intel_dig_port
->dp
.output_reg
= output_reg
;
2954 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2955 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2956 intel_encoder
->cloneable
= false;
2957 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2959 intel_dp_init_connector(intel_dig_port
, intel_connector
);