2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll
[] = {
48 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
50 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
53 static const struct dp_link_dpll pch_dpll
[] = {
55 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
57 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
60 static const struct dp_link_dpll vlv_dpll
[] = {
62 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
64 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp
*intel_dp
)
76 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
78 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
81 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
83 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
85 return intel_dig_port
->base
.base
.dev
;
88 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
90 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
93 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
94 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
95 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
98 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
100 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
101 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
103 switch (max_link_bw
) {
104 case DP_LINK_BW_1_62
:
107 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) &&
109 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
110 max_link_bw
= DP_LINK_BW_5_4
;
112 max_link_bw
= DP_LINK_BW_2_7
;
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw
= DP_LINK_BW_1_62
;
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 * 270000 * 1 * 8 / 10 == 216000
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
141 intel_dp_link_required(int pixel_clock
, int bpp
)
143 return (pixel_clock
* bpp
+ 9) / 10;
147 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
149 return (max_link_clock
* max_lanes
* 8) / 10;
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector
*connector
,
154 struct drm_display_mode
*mode
)
156 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
157 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
158 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
159 int target_clock
= mode
->clock
;
160 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
162 if (is_edp(intel_dp
) && fixed_mode
) {
163 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
166 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
169 target_clock
= fixed_mode
->clock
;
172 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
173 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
175 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
176 mode_rate
= intel_dp_link_required(target_clock
, 18);
178 if (mode_rate
> max_rate
)
179 return MODE_CLOCK_HIGH
;
181 if (mode
->clock
< 10000)
182 return MODE_CLOCK_LOW
;
184 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
185 return MODE_H_ILLEGAL
;
191 pack_aux(uint8_t *src
, int src_bytes
)
198 for (i
= 0; i
< src_bytes
; i
++)
199 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
204 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
209 for (i
= 0; i
< dst_bytes
; i
++)
210 dst
[i
] = src
>> ((3-i
) * 8);
213 /* hrawclock is 1/4 the FSB frequency */
215 intel_hrawclk(struct drm_device
*dev
)
217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev
))
224 clkcfg
= I915_READ(CLKCFG
);
225 switch (clkcfg
& CLKCFG_FSB_MASK
) {
234 case CLKCFG_FSB_1067
:
236 case CLKCFG_FSB_1333
:
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600
:
240 case CLKCFG_FSB_1600_ALT
:
248 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
249 struct intel_dp
*intel_dp
,
250 struct edp_power_seq
*out
);
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
253 struct intel_dp
*intel_dp
,
254 struct edp_power_seq
*out
);
257 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
259 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
260 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
261 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
263 enum port port
= intel_dig_port
->port
;
266 /* modeset should have pipe */
268 return to_intel_crtc(crtc
)->pipe
;
270 /* init time, try to find a pipe with this port selected */
271 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
272 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
273 PANEL_PORT_SELECT_MASK
;
274 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
276 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
284 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
286 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
288 if (HAS_PCH_SPLIT(dev
))
289 return PCH_PP_CONTROL
;
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
294 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
296 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
298 if (HAS_PCH_SPLIT(dev
))
299 return PCH_PP_STATUS
;
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
304 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
306 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
312 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
314 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 return !dev_priv
->pm
.suspended
&&
318 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
322 intel_dp_check_edp(struct intel_dp
*intel_dp
)
324 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 if (!is_edp(intel_dp
))
330 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
333 I915_READ(_pp_stat_reg(intel_dp
)),
334 I915_READ(_pp_ctrl_reg(intel_dp
)));
339 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
341 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
342 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
344 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
348 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
350 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
351 msecs_to_jiffies_timeout(10));
353 done
= wait_for_atomic(C
, 10) == 0;
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
362 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
364 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
365 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
371 return index
? 0 : intel_hrawclk(dev
) / 2;
374 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
376 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
377 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
382 if (intel_dig_port
->port
== PORT_A
) {
383 if (IS_GEN6(dev
) || IS_GEN7(dev
))
384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
386 return 225; /* eDP input clock at 450Mhz */
388 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
392 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
394 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
395 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 if (intel_dig_port
->port
== PORT_A
) {
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
402 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
403 /* Workaround for non-ULT HSW */
410 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
414 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
416 return index
? 0 : 100;
419 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
422 uint32_t aux_clock_divider
)
424 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
425 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
426 uint32_t precharge
, timeout
;
433 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
434 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
436 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
438 return DP_AUX_CH_CTL_SEND_BUSY
|
440 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
441 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
443 DP_AUX_CH_CTL_RECEIVE_ERROR
|
444 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
445 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
446 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
450 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
451 uint8_t *send
, int send_bytes
,
452 uint8_t *recv
, int recv_size
)
454 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
455 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
457 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
458 uint32_t ch_data
= ch_ctl
+ 4;
459 uint32_t aux_clock_divider
;
460 int i
, ret
, recv_bytes
;
463 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
466 vdd
= _edp_panel_vdd_on(intel_dp
);
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
472 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
474 intel_dp_check_edp(intel_dp
);
476 intel_aux_display_runtime_get(dev_priv
);
478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
480 status
= I915_READ_NOTRACE(ch_ctl
);
481 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
499 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
500 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i
= 0; i
< send_bytes
; i
+= 4)
509 I915_WRITE(ch_data
+ i
,
510 pack_aux(send
+ i
, send_bytes
- i
));
512 /* Send the command and wait for it to complete */
513 I915_WRITE(ch_ctl
, send_ctl
);
515 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
517 /* Clear done status and any errors */
521 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
522 DP_AUX_CH_CTL_RECEIVE_ERROR
);
524 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
525 DP_AUX_CH_CTL_RECEIVE_ERROR
))
527 if (status
& DP_AUX_CH_CTL_DONE
)
530 if (status
& DP_AUX_CH_CTL_DONE
)
534 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
543 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
551 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
557 /* Unload any bytes sent back from the other side */
558 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
560 if (recv_bytes
> recv_size
)
561 recv_bytes
= recv_size
;
563 for (i
= 0; i
< recv_bytes
; i
+= 4)
564 unpack_aux(I915_READ(ch_data
+ i
),
565 recv
+ i
, recv_bytes
- i
);
569 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
570 intel_aux_display_runtime_put(dev_priv
);
573 edp_panel_vdd_off(intel_dp
, false);
578 #define BARE_ADDRESS_SIZE 3
579 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
581 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
583 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
584 uint8_t txbuf
[20], rxbuf
[20];
585 size_t txsize
, rxsize
;
588 txbuf
[0] = msg
->request
<< 4;
589 txbuf
[1] = msg
->address
>> 8;
590 txbuf
[2] = msg
->address
& 0xff;
591 txbuf
[3] = msg
->size
- 1;
593 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
594 case DP_AUX_NATIVE_WRITE
:
595 case DP_AUX_I2C_WRITE
:
596 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
599 if (WARN_ON(txsize
> 20))
602 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
604 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
606 msg
->reply
= rxbuf
[0] >> 4;
608 /* Return payload size. */
613 case DP_AUX_NATIVE_READ
:
614 case DP_AUX_I2C_READ
:
615 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
616 rxsize
= msg
->size
+ 1;
618 if (WARN_ON(rxsize
> 20))
621 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
623 msg
->reply
= rxbuf
[0] >> 4;
625 * Assume happy day, and copy the data. The caller is
626 * expected to check msg->reply before touching it.
628 * Return payload size.
631 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
644 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
646 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
647 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
648 enum port port
= intel_dig_port
->port
;
649 const char *name
= NULL
;
654 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
658 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
662 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
666 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
674 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
676 intel_dp
->aux
.name
= name
;
677 intel_dp
->aux
.dev
= dev
->dev
;
678 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
680 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
681 connector
->base
.kdev
->kobj
.name
);
683 ret
= drm_dp_aux_register_i2c_bus(&intel_dp
->aux
);
685 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
690 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
691 &intel_dp
->aux
.ddc
.dev
.kobj
,
692 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
694 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
695 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
700 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
702 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
704 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
705 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
706 intel_connector_unregister(intel_connector
);
710 intel_dp_set_clock(struct intel_encoder
*encoder
,
711 struct intel_crtc_config
*pipe_config
, int link_bw
)
713 struct drm_device
*dev
= encoder
->base
.dev
;
714 const struct dp_link_dpll
*divisor
= NULL
;
719 count
= ARRAY_SIZE(gen4_dpll
);
720 } else if (IS_HASWELL(dev
)) {
721 /* Haswell has special-purpose DP DDI clocks. */
722 } else if (HAS_PCH_SPLIT(dev
)) {
724 count
= ARRAY_SIZE(pch_dpll
);
725 } else if (IS_VALLEYVIEW(dev
)) {
727 count
= ARRAY_SIZE(vlv_dpll
);
730 if (divisor
&& count
) {
731 for (i
= 0; i
< count
; i
++) {
732 if (link_bw
== divisor
[i
].link_bw
) {
733 pipe_config
->dpll
= divisor
[i
].dpll
;
734 pipe_config
->clock_set
= true;
742 intel_dp_set_m2_n2(struct intel_crtc
*crtc
, struct intel_link_m_n
*m_n
)
744 struct drm_device
*dev
= crtc
->base
.dev
;
745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
746 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
748 I915_WRITE(PIPE_DATA_M2(transcoder
),
749 TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
750 I915_WRITE(PIPE_DATA_N2(transcoder
), m_n
->gmch_n
);
751 I915_WRITE(PIPE_LINK_M2(transcoder
), m_n
->link_m
);
752 I915_WRITE(PIPE_LINK_N2(transcoder
), m_n
->link_n
);
756 intel_dp_compute_config(struct intel_encoder
*encoder
,
757 struct intel_crtc_config
*pipe_config
)
759 struct drm_device
*dev
= encoder
->base
.dev
;
760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
761 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
762 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
763 enum port port
= dp_to_dig_port(intel_dp
)->port
;
764 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
765 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
766 int lane_count
, clock
;
767 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
768 /* Conveniently, the link BW constants become indices with a shift...*/
769 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
771 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
772 int link_avail
, link_clock
;
774 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
775 pipe_config
->has_pch_encoder
= true;
777 pipe_config
->has_dp_encoder
= true;
779 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
780 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
782 if (!HAS_PCH_SPLIT(dev
))
783 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
784 intel_connector
->panel
.fitting_mode
);
786 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
787 intel_connector
->panel
.fitting_mode
);
790 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
793 DRM_DEBUG_KMS("DP link computation with max lane count %i "
794 "max bw %02x pixel clock %iKHz\n",
795 max_lane_count
, bws
[max_clock
],
796 adjusted_mode
->crtc_clock
);
798 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
800 bpp
= pipe_config
->pipe_bpp
;
801 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
802 dev_priv
->vbt
.edp_bpp
< bpp
) {
803 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
804 dev_priv
->vbt
.edp_bpp
);
805 bpp
= dev_priv
->vbt
.edp_bpp
;
808 for (; bpp
>= 6*3; bpp
-= 2*3) {
809 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
812 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
813 for (clock
= 0; clock
<= max_clock
; clock
++) {
814 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
815 link_avail
= intel_dp_max_data_rate(link_clock
,
818 if (mode_rate
<= link_avail
) {
828 if (intel_dp
->color_range_auto
) {
831 * CEA-861-E - 5.1 Default Encoding Parameters
832 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
834 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
835 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
837 intel_dp
->color_range
= 0;
840 if (intel_dp
->color_range
)
841 pipe_config
->limited_color_range
= true;
843 intel_dp
->link_bw
= bws
[clock
];
844 intel_dp
->lane_count
= lane_count
;
845 pipe_config
->pipe_bpp
= bpp
;
846 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
848 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
849 intel_dp
->link_bw
, intel_dp
->lane_count
,
850 pipe_config
->port_clock
, bpp
);
851 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
852 mode_rate
, link_avail
);
854 intel_link_compute_m_n(bpp
, lane_count
,
855 adjusted_mode
->crtc_clock
,
856 pipe_config
->port_clock
,
857 &pipe_config
->dp_m_n
);
859 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
860 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
861 intel_link_compute_m_n(bpp
, lane_count
,
862 intel_connector
->panel
.downclock_mode
->clock
,
863 pipe_config
->port_clock
,
864 &pipe_config
->dp_m2_n2
);
867 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
872 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
874 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
875 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
876 struct drm_device
*dev
= crtc
->base
.dev
;
877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
880 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
881 dpa_ctl
= I915_READ(DP_A
);
882 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
884 if (crtc
->config
.port_clock
== 162000) {
885 /* For a long time we've carried around a ILK-DevA w/a for the
886 * 160MHz clock. If we're really unlucky, it's still required.
888 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
889 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
890 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
892 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
893 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
896 I915_WRITE(DP_A
, dpa_ctl
);
902 static void intel_dp_mode_set(struct intel_encoder
*encoder
)
904 struct drm_device
*dev
= encoder
->base
.dev
;
905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
906 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
907 enum port port
= dp_to_dig_port(intel_dp
)->port
;
908 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
909 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
912 * There are four kinds of DP registers:
919 * IBX PCH and CPU are the same for almost everything,
920 * except that the CPU DP PLL is configured in this
923 * CPT PCH is quite different, having many bits moved
924 * to the TRANS_DP_CTL register instead. That
925 * configuration happens (oddly) in ironlake_pch_enable
928 /* Preserve the BIOS-computed detected bit. This is
929 * supposed to be read-only.
931 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
933 /* Handle DP bits in common between all three register formats */
934 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
935 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
937 if (intel_dp
->has_audio
) {
938 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
939 pipe_name(crtc
->pipe
));
940 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
941 intel_write_eld(&encoder
->base
, adjusted_mode
);
944 /* Split out the IBX/CPU vs CPT settings */
946 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
947 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
948 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
949 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
950 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
951 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
953 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
954 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
956 intel_dp
->DP
|= crtc
->pipe
<< 29;
957 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
958 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
959 intel_dp
->DP
|= intel_dp
->color_range
;
961 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
962 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
963 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
964 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
965 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
967 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
968 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
971 intel_dp
->DP
|= DP_PIPEB_SELECT
;
973 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
976 if (port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
977 ironlake_set_pll_cpu_edp(intel_dp
);
980 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
981 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
983 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
984 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
986 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
987 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
989 static void wait_panel_status(struct intel_dp
*intel_dp
,
993 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
995 u32 pp_stat_reg
, pp_ctrl_reg
;
997 pp_stat_reg
= _pp_stat_reg(intel_dp
);
998 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1000 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1002 I915_READ(pp_stat_reg
),
1003 I915_READ(pp_ctrl_reg
));
1005 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1006 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1007 I915_READ(pp_stat_reg
),
1008 I915_READ(pp_ctrl_reg
));
1011 DRM_DEBUG_KMS("Wait complete\n");
1014 static void wait_panel_on(struct intel_dp
*intel_dp
)
1016 DRM_DEBUG_KMS("Wait for panel power on\n");
1017 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1020 static void wait_panel_off(struct intel_dp
*intel_dp
)
1022 DRM_DEBUG_KMS("Wait for panel power off time\n");
1023 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1026 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1028 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1030 /* When we disable the VDD override bit last we have to do the manual
1032 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1033 intel_dp
->panel_power_cycle_delay
);
1035 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1038 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1040 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1041 intel_dp
->backlight_on_delay
);
1044 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1046 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1047 intel_dp
->backlight_off_delay
);
1050 /* Read the current pp_control value, unlocking the register if it
1054 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1056 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1060 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1061 control
&= ~PANEL_UNLOCK_MASK
;
1062 control
|= PANEL_UNLOCK_REGS
;
1066 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1068 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1069 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1070 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1072 enum intel_display_power_domain power_domain
;
1074 u32 pp_stat_reg
, pp_ctrl_reg
;
1075 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1077 if (!is_edp(intel_dp
))
1080 intel_dp
->want_panel_vdd
= true;
1082 if (edp_have_panel_vdd(intel_dp
))
1083 return need_to_disable
;
1085 power_domain
= intel_display_port_power_domain(intel_encoder
);
1086 intel_display_power_get(dev_priv
, power_domain
);
1088 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1090 if (!edp_have_panel_power(intel_dp
))
1091 wait_panel_power_cycle(intel_dp
);
1093 pp
= ironlake_get_pp_control(intel_dp
);
1094 pp
|= EDP_FORCE_VDD
;
1096 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1097 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1099 I915_WRITE(pp_ctrl_reg
, pp
);
1100 POSTING_READ(pp_ctrl_reg
);
1101 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1102 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1104 * If the panel wasn't on, delay before accessing aux channel
1106 if (!edp_have_panel_power(intel_dp
)) {
1107 DRM_DEBUG_KMS("eDP was not running\n");
1108 msleep(intel_dp
->panel_power_up_delay
);
1111 return need_to_disable
;
1114 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1116 if (is_edp(intel_dp
)) {
1117 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1119 WARN(!vdd
, "eDP VDD already requested on\n");
1123 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1125 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1128 u32 pp_stat_reg
, pp_ctrl_reg
;
1130 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1132 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1133 struct intel_digital_port
*intel_dig_port
=
1134 dp_to_dig_port(intel_dp
);
1135 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1136 enum intel_display_power_domain power_domain
;
1138 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1140 pp
= ironlake_get_pp_control(intel_dp
);
1141 pp
&= ~EDP_FORCE_VDD
;
1143 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1144 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1146 I915_WRITE(pp_ctrl_reg
, pp
);
1147 POSTING_READ(pp_ctrl_reg
);
1149 /* Make sure sequencer is idle before allowing subsequent activity */
1150 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1151 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1153 if ((pp
& POWER_TARGET_ON
) == 0)
1154 intel_dp
->last_power_cycle
= jiffies
;
1156 power_domain
= intel_display_port_power_domain(intel_encoder
);
1157 intel_display_power_put(dev_priv
, power_domain
);
1161 static void edp_panel_vdd_work(struct work_struct
*__work
)
1163 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1164 struct intel_dp
, panel_vdd_work
);
1165 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1167 mutex_lock(&dev
->mode_config
.mutex
);
1168 edp_panel_vdd_off_sync(intel_dp
);
1169 mutex_unlock(&dev
->mode_config
.mutex
);
1172 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1174 if (!is_edp(intel_dp
))
1177 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1179 intel_dp
->want_panel_vdd
= false;
1182 edp_panel_vdd_off_sync(intel_dp
);
1185 * Queue the timer to fire a long
1186 * time from now (relative to the power down delay)
1187 * to keep the panel power up across a sequence of operations
1189 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1190 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1194 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1196 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1201 if (!is_edp(intel_dp
))
1204 DRM_DEBUG_KMS("Turn eDP power on\n");
1206 if (edp_have_panel_power(intel_dp
)) {
1207 DRM_DEBUG_KMS("eDP power already on\n");
1211 wait_panel_power_cycle(intel_dp
);
1213 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1214 pp
= ironlake_get_pp_control(intel_dp
);
1216 /* ILK workaround: disable reset around power sequence */
1217 pp
&= ~PANEL_POWER_RESET
;
1218 I915_WRITE(pp_ctrl_reg
, pp
);
1219 POSTING_READ(pp_ctrl_reg
);
1222 pp
|= POWER_TARGET_ON
;
1224 pp
|= PANEL_POWER_RESET
;
1226 I915_WRITE(pp_ctrl_reg
, pp
);
1227 POSTING_READ(pp_ctrl_reg
);
1229 wait_panel_on(intel_dp
);
1230 intel_dp
->last_power_on
= jiffies
;
1233 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1234 I915_WRITE(pp_ctrl_reg
, pp
);
1235 POSTING_READ(pp_ctrl_reg
);
1239 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1241 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1242 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1243 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1245 enum intel_display_power_domain power_domain
;
1249 if (!is_edp(intel_dp
))
1252 DRM_DEBUG_KMS("Turn eDP power off\n");
1254 edp_wait_backlight_off(intel_dp
);
1256 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1258 pp
= ironlake_get_pp_control(intel_dp
);
1259 /* We need to switch off panel power _and_ force vdd, for otherwise some
1260 * panels get very unhappy and cease to work. */
1261 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1264 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1266 intel_dp
->want_panel_vdd
= false;
1268 I915_WRITE(pp_ctrl_reg
, pp
);
1269 POSTING_READ(pp_ctrl_reg
);
1271 intel_dp
->last_power_cycle
= jiffies
;
1272 wait_panel_off(intel_dp
);
1274 /* We got a reference when we enabled the VDD. */
1275 power_domain
= intel_display_port_power_domain(intel_encoder
);
1276 intel_display_power_put(dev_priv
, power_domain
);
1279 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1281 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1282 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1287 if (!is_edp(intel_dp
))
1290 DRM_DEBUG_KMS("\n");
1292 * If we enable the backlight right away following a panel power
1293 * on, we may see slight flicker as the panel syncs with the eDP
1294 * link. So delay a bit to make sure the image is solid before
1295 * allowing it to appear.
1297 wait_backlight_on(intel_dp
);
1298 pp
= ironlake_get_pp_control(intel_dp
);
1299 pp
|= EDP_BLC_ENABLE
;
1301 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1303 I915_WRITE(pp_ctrl_reg
, pp
);
1304 POSTING_READ(pp_ctrl_reg
);
1306 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1309 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1311 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1316 if (!is_edp(intel_dp
))
1319 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1321 DRM_DEBUG_KMS("\n");
1322 pp
= ironlake_get_pp_control(intel_dp
);
1323 pp
&= ~EDP_BLC_ENABLE
;
1325 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1327 I915_WRITE(pp_ctrl_reg
, pp
);
1328 POSTING_READ(pp_ctrl_reg
);
1329 intel_dp
->last_backlight_off
= jiffies
;
1332 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1334 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1335 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1336 struct drm_device
*dev
= crtc
->dev
;
1337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1340 assert_pipe_disabled(dev_priv
,
1341 to_intel_crtc(crtc
)->pipe
);
1343 DRM_DEBUG_KMS("\n");
1344 dpa_ctl
= I915_READ(DP_A
);
1345 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1346 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1348 /* We don't adjust intel_dp->DP while tearing down the link, to
1349 * facilitate link retraining (e.g. after hotplug). Hence clear all
1350 * enable bits here to ensure that we don't enable too much. */
1351 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1352 intel_dp
->DP
|= DP_PLL_ENABLE
;
1353 I915_WRITE(DP_A
, intel_dp
->DP
);
1358 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1360 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1361 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1362 struct drm_device
*dev
= crtc
->dev
;
1363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1366 assert_pipe_disabled(dev_priv
,
1367 to_intel_crtc(crtc
)->pipe
);
1369 dpa_ctl
= I915_READ(DP_A
);
1370 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1371 "dp pll off, should be on\n");
1372 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1374 /* We can't rely on the value tracked for the DP register in
1375 * intel_dp->DP because link_down must not change that (otherwise link
1376 * re-training will fail. */
1377 dpa_ctl
&= ~DP_PLL_ENABLE
;
1378 I915_WRITE(DP_A
, dpa_ctl
);
1383 /* If the sink supports it, try to set the power state appropriately */
1384 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1388 /* Should have a valid DPCD by this point */
1389 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1392 if (mode
!= DRM_MODE_DPMS_ON
) {
1393 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1396 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1399 * When turning on, we need to retry for 1ms to give the sink
1402 for (i
= 0; i
< 3; i
++) {
1403 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1412 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1415 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1416 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1417 struct drm_device
*dev
= encoder
->base
.dev
;
1418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1419 enum intel_display_power_domain power_domain
;
1422 power_domain
= intel_display_port_power_domain(encoder
);
1423 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1426 tmp
= I915_READ(intel_dp
->output_reg
);
1428 if (!(tmp
& DP_PORT_EN
))
1431 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1432 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1433 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1434 *pipe
= PORT_TO_PIPE(tmp
);
1440 switch (intel_dp
->output_reg
) {
1442 trans_sel
= TRANS_DP_PORT_SEL_B
;
1445 trans_sel
= TRANS_DP_PORT_SEL_C
;
1448 trans_sel
= TRANS_DP_PORT_SEL_D
;
1455 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1456 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1462 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1463 intel_dp
->output_reg
);
1469 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1470 struct intel_crtc_config
*pipe_config
)
1472 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1474 struct drm_device
*dev
= encoder
->base
.dev
;
1475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1476 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1477 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1480 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1481 tmp
= I915_READ(intel_dp
->output_reg
);
1482 if (tmp
& DP_SYNC_HS_HIGH
)
1483 flags
|= DRM_MODE_FLAG_PHSYNC
;
1485 flags
|= DRM_MODE_FLAG_NHSYNC
;
1487 if (tmp
& DP_SYNC_VS_HIGH
)
1488 flags
|= DRM_MODE_FLAG_PVSYNC
;
1490 flags
|= DRM_MODE_FLAG_NVSYNC
;
1492 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1493 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1494 flags
|= DRM_MODE_FLAG_PHSYNC
;
1496 flags
|= DRM_MODE_FLAG_NHSYNC
;
1498 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1499 flags
|= DRM_MODE_FLAG_PVSYNC
;
1501 flags
|= DRM_MODE_FLAG_NVSYNC
;
1504 pipe_config
->adjusted_mode
.flags
|= flags
;
1506 pipe_config
->has_dp_encoder
= true;
1508 intel_dp_get_m_n(crtc
, pipe_config
);
1510 if (port
== PORT_A
) {
1511 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1512 pipe_config
->port_clock
= 162000;
1514 pipe_config
->port_clock
= 270000;
1517 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1518 &pipe_config
->dp_m_n
);
1520 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1521 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1523 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1525 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1526 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1528 * This is a big fat ugly hack.
1530 * Some machines in UEFI boot mode provide us a VBT that has 18
1531 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1532 * unknown we fail to light up. Yet the same BIOS boots up with
1533 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1534 * max, not what it tells us to use.
1536 * Note: This will still be broken if the eDP panel is not lit
1537 * up by the BIOS, and thus we can't get the mode at module
1540 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1541 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1542 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1546 static bool is_edp_psr(struct drm_device
*dev
)
1548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1550 return dev_priv
->psr
.sink_support
;
1553 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1560 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1563 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1564 struct edp_vsc_psr
*vsc_psr
)
1566 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1567 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1569 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1570 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1571 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1572 uint32_t *data
= (uint32_t *) vsc_psr
;
1575 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1576 the video DIP being updated before program video DIP data buffer
1577 registers for DIP being updated. */
1578 I915_WRITE(ctl_reg
, 0);
1579 POSTING_READ(ctl_reg
);
1581 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1582 if (i
< sizeof(struct edp_vsc_psr
))
1583 I915_WRITE(data_reg
+ i
, *data
++);
1585 I915_WRITE(data_reg
+ i
, 0);
1588 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1589 POSTING_READ(ctl_reg
);
1592 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1594 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1596 struct edp_vsc_psr psr_vsc
;
1598 if (intel_dp
->psr_setup_done
)
1601 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1602 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1603 psr_vsc
.sdp_header
.HB0
= 0;
1604 psr_vsc
.sdp_header
.HB1
= 0x7;
1605 psr_vsc
.sdp_header
.HB2
= 0x2;
1606 psr_vsc
.sdp_header
.HB3
= 0x8;
1607 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1609 /* Avoid continuous PSR exit by masking memup and hpd */
1610 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1611 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1613 intel_dp
->psr_setup_done
= true;
1616 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1618 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1620 uint32_t aux_clock_divider
;
1621 int precharge
= 0x3;
1622 int msg_size
= 5; /* Header(4) + Message(1) */
1624 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1626 /* Enable PSR in sink */
1627 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1628 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1629 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1631 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1632 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1634 /* Setup AUX registers */
1635 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1636 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1637 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1638 DP_AUX_CH_CTL_TIME_OUT_400us
|
1639 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1640 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1641 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1644 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1646 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1648 uint32_t max_sleep_time
= 0x1f;
1649 uint32_t idle_frames
= 1;
1651 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1653 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1654 val
|= EDP_PSR_LINK_STANDBY
;
1655 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1656 val
|= EDP_PSR_TP1_TIME_0us
;
1657 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1659 val
|= EDP_PSR_LINK_DISABLE
;
1661 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1662 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1663 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1664 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1668 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1670 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1671 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1673 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1674 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1675 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->primary
->fb
)->obj
;
1676 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1678 dev_priv
->psr
.source_ok
= false;
1680 if (!HAS_PSR(dev
)) {
1681 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1685 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1686 (dig_port
->port
!= PORT_A
)) {
1687 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1691 if (!i915
.enable_psr
) {
1692 DRM_DEBUG_KMS("PSR disable by flag\n");
1696 crtc
= dig_port
->base
.base
.crtc
;
1698 DRM_DEBUG_KMS("crtc not active for PSR\n");
1702 intel_crtc
= to_intel_crtc(crtc
);
1703 if (!intel_crtc_active(crtc
)) {
1704 DRM_DEBUG_KMS("crtc not active for PSR\n");
1708 obj
= to_intel_framebuffer(crtc
->primary
->fb
)->obj
;
1709 if (obj
->tiling_mode
!= I915_TILING_X
||
1710 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1711 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1715 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1716 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1720 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1722 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1726 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1727 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1731 dev_priv
->psr
.source_ok
= true;
1735 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1737 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1739 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1740 intel_edp_is_psr_enabled(dev
))
1743 /* Setup PSR once */
1744 intel_edp_psr_setup(intel_dp
);
1746 /* Enable PSR on the panel */
1747 intel_edp_psr_enable_sink(intel_dp
);
1749 /* Enable PSR on the host */
1750 intel_edp_psr_enable_source(intel_dp
);
1753 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1755 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1757 if (intel_edp_psr_match_conditions(intel_dp
) &&
1758 !intel_edp_is_psr_enabled(dev
))
1759 intel_edp_psr_do_enable(intel_dp
);
1762 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1764 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1767 if (!intel_edp_is_psr_enabled(dev
))
1770 I915_WRITE(EDP_PSR_CTL(dev
),
1771 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1773 /* Wait till PSR is idle */
1774 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1775 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1776 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1779 void intel_edp_psr_update(struct drm_device
*dev
)
1781 struct intel_encoder
*encoder
;
1782 struct intel_dp
*intel_dp
= NULL
;
1784 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1785 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1786 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1788 if (!is_edp_psr(dev
))
1791 if (!intel_edp_psr_match_conditions(intel_dp
))
1792 intel_edp_psr_disable(intel_dp
);
1794 if (!intel_edp_is_psr_enabled(dev
))
1795 intel_edp_psr_do_enable(intel_dp
);
1799 static void intel_disable_dp(struct intel_encoder
*encoder
)
1801 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1802 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1803 struct drm_device
*dev
= encoder
->base
.dev
;
1805 /* Make sure the panel is off before trying to change the mode. But also
1806 * ensure that we have vdd while we switch off the panel. */
1807 intel_edp_panel_vdd_on(intel_dp
);
1808 intel_edp_backlight_off(intel_dp
);
1809 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1810 intel_edp_panel_off(intel_dp
);
1812 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1813 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1814 intel_dp_link_down(intel_dp
);
1817 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
1819 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1820 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1825 intel_dp_link_down(intel_dp
);
1826 ironlake_edp_pll_off(intel_dp
);
1829 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
1831 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1833 intel_dp_link_down(intel_dp
);
1836 static void intel_enable_dp(struct intel_encoder
*encoder
)
1838 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1839 struct drm_device
*dev
= encoder
->base
.dev
;
1840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1841 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1843 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1846 intel_edp_panel_vdd_on(intel_dp
);
1847 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1848 intel_dp_start_link_train(intel_dp
);
1849 intel_edp_panel_on(intel_dp
);
1850 edp_panel_vdd_off(intel_dp
, true);
1851 intel_dp_complete_link_train(intel_dp
);
1852 intel_dp_stop_link_train(intel_dp
);
1855 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1857 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1859 intel_enable_dp(encoder
);
1860 intel_edp_backlight_on(intel_dp
);
1863 static void vlv_enable_dp(struct intel_encoder
*encoder
)
1865 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1867 intel_edp_backlight_on(intel_dp
);
1870 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
1872 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1873 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1875 if (dport
->port
== PORT_A
)
1876 ironlake_edp_pll_on(intel_dp
);
1879 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
1881 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1882 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1883 struct drm_device
*dev
= encoder
->base
.dev
;
1884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1885 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1886 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1887 int pipe
= intel_crtc
->pipe
;
1888 struct edp_power_seq power_seq
;
1891 mutex_lock(&dev_priv
->dpio_lock
);
1893 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1900 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1901 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1902 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1904 mutex_unlock(&dev_priv
->dpio_lock
);
1906 if (is_edp(intel_dp
)) {
1907 /* init power sequencer on this pipe and port */
1908 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
1909 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
1913 intel_enable_dp(encoder
);
1915 vlv_wait_port_ready(dev_priv
, dport
);
1918 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1920 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1921 struct drm_device
*dev
= encoder
->base
.dev
;
1922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1923 struct intel_crtc
*intel_crtc
=
1924 to_intel_crtc(encoder
->base
.crtc
);
1925 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1926 int pipe
= intel_crtc
->pipe
;
1928 /* Program Tx lane resets to default */
1929 mutex_lock(&dev_priv
->dpio_lock
);
1930 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1931 DPIO_PCS_TX_LANE2_RESET
|
1932 DPIO_PCS_TX_LANE1_RESET
);
1933 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
1934 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1935 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1936 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1937 DPIO_PCS_CLK_SOFT_RESET
);
1939 /* Fix up inter-pair skew failure */
1940 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
1941 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
1942 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
1943 mutex_unlock(&dev_priv
->dpio_lock
);
1947 * Native read with retry for link status and receiver capability reads for
1948 * cases where the sink may still be asleep.
1950 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1951 * supposed to retry 3 times per the spec.
1954 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
1955 void *buffer
, size_t size
)
1960 for (i
= 0; i
< 3; i
++) {
1961 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
1971 * Fetch AUX CH registers 0x202 - 0x207 which contain
1972 * link status information
1975 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1977 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
1980 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
1984 * These are source-specific values; current Intel hardware supports
1985 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1989 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1991 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1992 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1994 if (IS_VALLEYVIEW(dev
) || IS_BROADWELL(dev
))
1995 return DP_TRAIN_VOLTAGE_SWING_1200
;
1996 else if (IS_GEN7(dev
) && port
== PORT_A
)
1997 return DP_TRAIN_VOLTAGE_SWING_800
;
1998 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
1999 return DP_TRAIN_VOLTAGE_SWING_1200
;
2001 return DP_TRAIN_VOLTAGE_SWING_800
;
2005 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2007 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2008 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2010 if (IS_BROADWELL(dev
)) {
2011 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2012 case DP_TRAIN_VOLTAGE_SWING_400
:
2013 case DP_TRAIN_VOLTAGE_SWING_600
:
2014 return DP_TRAIN_PRE_EMPHASIS_6
;
2015 case DP_TRAIN_VOLTAGE_SWING_800
:
2016 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2017 case DP_TRAIN_VOLTAGE_SWING_1200
:
2019 return DP_TRAIN_PRE_EMPHASIS_0
;
2021 } else if (IS_HASWELL(dev
)) {
2022 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2023 case DP_TRAIN_VOLTAGE_SWING_400
:
2024 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2025 case DP_TRAIN_VOLTAGE_SWING_600
:
2026 return DP_TRAIN_PRE_EMPHASIS_6
;
2027 case DP_TRAIN_VOLTAGE_SWING_800
:
2028 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2029 case DP_TRAIN_VOLTAGE_SWING_1200
:
2031 return DP_TRAIN_PRE_EMPHASIS_0
;
2033 } else if (IS_VALLEYVIEW(dev
)) {
2034 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2035 case DP_TRAIN_VOLTAGE_SWING_400
:
2036 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2037 case DP_TRAIN_VOLTAGE_SWING_600
:
2038 return DP_TRAIN_PRE_EMPHASIS_6
;
2039 case DP_TRAIN_VOLTAGE_SWING_800
:
2040 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2041 case DP_TRAIN_VOLTAGE_SWING_1200
:
2043 return DP_TRAIN_PRE_EMPHASIS_0
;
2045 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2046 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2047 case DP_TRAIN_VOLTAGE_SWING_400
:
2048 return DP_TRAIN_PRE_EMPHASIS_6
;
2049 case DP_TRAIN_VOLTAGE_SWING_600
:
2050 case DP_TRAIN_VOLTAGE_SWING_800
:
2051 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2053 return DP_TRAIN_PRE_EMPHASIS_0
;
2056 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2057 case DP_TRAIN_VOLTAGE_SWING_400
:
2058 return DP_TRAIN_PRE_EMPHASIS_6
;
2059 case DP_TRAIN_VOLTAGE_SWING_600
:
2060 return DP_TRAIN_PRE_EMPHASIS_6
;
2061 case DP_TRAIN_VOLTAGE_SWING_800
:
2062 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2063 case DP_TRAIN_VOLTAGE_SWING_1200
:
2065 return DP_TRAIN_PRE_EMPHASIS_0
;
2070 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2072 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2074 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2075 struct intel_crtc
*intel_crtc
=
2076 to_intel_crtc(dport
->base
.base
.crtc
);
2077 unsigned long demph_reg_value
, preemph_reg_value
,
2078 uniqtranscale_reg_value
;
2079 uint8_t train_set
= intel_dp
->train_set
[0];
2080 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2081 int pipe
= intel_crtc
->pipe
;
2083 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2084 case DP_TRAIN_PRE_EMPHASIS_0
:
2085 preemph_reg_value
= 0x0004000;
2086 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2087 case DP_TRAIN_VOLTAGE_SWING_400
:
2088 demph_reg_value
= 0x2B405555;
2089 uniqtranscale_reg_value
= 0x552AB83A;
2091 case DP_TRAIN_VOLTAGE_SWING_600
:
2092 demph_reg_value
= 0x2B404040;
2093 uniqtranscale_reg_value
= 0x5548B83A;
2095 case DP_TRAIN_VOLTAGE_SWING_800
:
2096 demph_reg_value
= 0x2B245555;
2097 uniqtranscale_reg_value
= 0x5560B83A;
2099 case DP_TRAIN_VOLTAGE_SWING_1200
:
2100 demph_reg_value
= 0x2B405555;
2101 uniqtranscale_reg_value
= 0x5598DA3A;
2107 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2108 preemph_reg_value
= 0x0002000;
2109 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2110 case DP_TRAIN_VOLTAGE_SWING_400
:
2111 demph_reg_value
= 0x2B404040;
2112 uniqtranscale_reg_value
= 0x5552B83A;
2114 case DP_TRAIN_VOLTAGE_SWING_600
:
2115 demph_reg_value
= 0x2B404848;
2116 uniqtranscale_reg_value
= 0x5580B83A;
2118 case DP_TRAIN_VOLTAGE_SWING_800
:
2119 demph_reg_value
= 0x2B404040;
2120 uniqtranscale_reg_value
= 0x55ADDA3A;
2126 case DP_TRAIN_PRE_EMPHASIS_6
:
2127 preemph_reg_value
= 0x0000000;
2128 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2129 case DP_TRAIN_VOLTAGE_SWING_400
:
2130 demph_reg_value
= 0x2B305555;
2131 uniqtranscale_reg_value
= 0x5570B83A;
2133 case DP_TRAIN_VOLTAGE_SWING_600
:
2134 demph_reg_value
= 0x2B2B4040;
2135 uniqtranscale_reg_value
= 0x55ADDA3A;
2141 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2142 preemph_reg_value
= 0x0006000;
2143 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2144 case DP_TRAIN_VOLTAGE_SWING_400
:
2145 demph_reg_value
= 0x1B405555;
2146 uniqtranscale_reg_value
= 0x55ADDA3A;
2156 mutex_lock(&dev_priv
->dpio_lock
);
2157 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2158 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2159 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2160 uniqtranscale_reg_value
);
2161 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2162 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2163 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2164 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2165 mutex_unlock(&dev_priv
->dpio_lock
);
2171 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2172 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2177 uint8_t voltage_max
;
2178 uint8_t preemph_max
;
2180 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2181 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2182 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2190 voltage_max
= intel_dp_voltage_max(intel_dp
);
2191 if (v
>= voltage_max
)
2192 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2194 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2195 if (p
>= preemph_max
)
2196 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2198 for (lane
= 0; lane
< 4; lane
++)
2199 intel_dp
->train_set
[lane
] = v
| p
;
2203 intel_gen4_signal_levels(uint8_t train_set
)
2205 uint32_t signal_levels
= 0;
2207 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2208 case DP_TRAIN_VOLTAGE_SWING_400
:
2210 signal_levels
|= DP_VOLTAGE_0_4
;
2212 case DP_TRAIN_VOLTAGE_SWING_600
:
2213 signal_levels
|= DP_VOLTAGE_0_6
;
2215 case DP_TRAIN_VOLTAGE_SWING_800
:
2216 signal_levels
|= DP_VOLTAGE_0_8
;
2218 case DP_TRAIN_VOLTAGE_SWING_1200
:
2219 signal_levels
|= DP_VOLTAGE_1_2
;
2222 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2223 case DP_TRAIN_PRE_EMPHASIS_0
:
2225 signal_levels
|= DP_PRE_EMPHASIS_0
;
2227 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2228 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2230 case DP_TRAIN_PRE_EMPHASIS_6
:
2231 signal_levels
|= DP_PRE_EMPHASIS_6
;
2233 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2234 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2237 return signal_levels
;
2240 /* Gen6's DP voltage swing and pre-emphasis control */
2242 intel_gen6_edp_signal_levels(uint8_t train_set
)
2244 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2245 DP_TRAIN_PRE_EMPHASIS_MASK
);
2246 switch (signal_levels
) {
2247 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2248 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2249 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2250 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2251 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2252 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2253 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2254 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2255 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2256 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2257 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2258 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2259 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2260 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2262 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2263 "0x%x\n", signal_levels
);
2264 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2268 /* Gen7's DP voltage swing and pre-emphasis control */
2270 intel_gen7_edp_signal_levels(uint8_t train_set
)
2272 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2273 DP_TRAIN_PRE_EMPHASIS_MASK
);
2274 switch (signal_levels
) {
2275 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2276 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2277 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2278 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2279 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2280 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2282 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2283 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2284 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2285 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2287 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2288 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2289 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2290 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2293 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2294 "0x%x\n", signal_levels
);
2295 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2299 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2301 intel_hsw_signal_levels(uint8_t train_set
)
2303 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2304 DP_TRAIN_PRE_EMPHASIS_MASK
);
2305 switch (signal_levels
) {
2306 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2307 return DDI_BUF_EMP_400MV_0DB_HSW
;
2308 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2309 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2310 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2311 return DDI_BUF_EMP_400MV_6DB_HSW
;
2312 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2313 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2315 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2316 return DDI_BUF_EMP_600MV_0DB_HSW
;
2317 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2318 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2319 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2320 return DDI_BUF_EMP_600MV_6DB_HSW
;
2322 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2323 return DDI_BUF_EMP_800MV_0DB_HSW
;
2324 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2325 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2327 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2328 "0x%x\n", signal_levels
);
2329 return DDI_BUF_EMP_400MV_0DB_HSW
;
2334 intel_bdw_signal_levels(uint8_t train_set
)
2336 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2337 DP_TRAIN_PRE_EMPHASIS_MASK
);
2338 switch (signal_levels
) {
2339 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2340 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2341 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2342 return DDI_BUF_EMP_400MV_3_5DB_BDW
; /* Sel1 */
2343 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2344 return DDI_BUF_EMP_400MV_6DB_BDW
; /* Sel2 */
2346 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2347 return DDI_BUF_EMP_600MV_0DB_BDW
; /* Sel3 */
2348 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2349 return DDI_BUF_EMP_600MV_3_5DB_BDW
; /* Sel4 */
2350 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2351 return DDI_BUF_EMP_600MV_6DB_BDW
; /* Sel5 */
2353 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2354 return DDI_BUF_EMP_800MV_0DB_BDW
; /* Sel6 */
2355 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2356 return DDI_BUF_EMP_800MV_3_5DB_BDW
; /* Sel7 */
2358 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2359 return DDI_BUF_EMP_1200MV_0DB_BDW
; /* Sel8 */
2362 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2363 "0x%x\n", signal_levels
);
2364 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2368 /* Properly updates "DP" with the correct signal levels. */
2370 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2372 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2373 enum port port
= intel_dig_port
->port
;
2374 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2375 uint32_t signal_levels
, mask
;
2376 uint8_t train_set
= intel_dp
->train_set
[0];
2378 if (IS_BROADWELL(dev
)) {
2379 signal_levels
= intel_bdw_signal_levels(train_set
);
2380 mask
= DDI_BUF_EMP_MASK
;
2381 } else if (IS_HASWELL(dev
)) {
2382 signal_levels
= intel_hsw_signal_levels(train_set
);
2383 mask
= DDI_BUF_EMP_MASK
;
2384 } else if (IS_VALLEYVIEW(dev
)) {
2385 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2387 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2388 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2389 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2390 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2391 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2392 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2394 signal_levels
= intel_gen4_signal_levels(train_set
);
2395 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2398 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2400 *DP
= (*DP
& ~mask
) | signal_levels
;
2404 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2406 uint8_t dp_train_pat
)
2408 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2409 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2411 enum port port
= intel_dig_port
->port
;
2412 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2416 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2418 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2419 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2421 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2423 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2424 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2425 case DP_TRAINING_PATTERN_DISABLE
:
2426 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2429 case DP_TRAINING_PATTERN_1
:
2430 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2432 case DP_TRAINING_PATTERN_2
:
2433 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2435 case DP_TRAINING_PATTERN_3
:
2436 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2439 I915_WRITE(DP_TP_CTL(port
), temp
);
2441 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2442 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2444 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2445 case DP_TRAINING_PATTERN_DISABLE
:
2446 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2448 case DP_TRAINING_PATTERN_1
:
2449 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2451 case DP_TRAINING_PATTERN_2
:
2452 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2454 case DP_TRAINING_PATTERN_3
:
2455 DRM_ERROR("DP training pattern 3 not supported\n");
2456 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2461 *DP
&= ~DP_LINK_TRAIN_MASK
;
2463 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2464 case DP_TRAINING_PATTERN_DISABLE
:
2465 *DP
|= DP_LINK_TRAIN_OFF
;
2467 case DP_TRAINING_PATTERN_1
:
2468 *DP
|= DP_LINK_TRAIN_PAT_1
;
2470 case DP_TRAINING_PATTERN_2
:
2471 *DP
|= DP_LINK_TRAIN_PAT_2
;
2473 case DP_TRAINING_PATTERN_3
:
2474 DRM_ERROR("DP training pattern 3 not supported\n");
2475 *DP
|= DP_LINK_TRAIN_PAT_2
;
2480 I915_WRITE(intel_dp
->output_reg
, *DP
);
2481 POSTING_READ(intel_dp
->output_reg
);
2483 buf
[0] = dp_train_pat
;
2484 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2485 DP_TRAINING_PATTERN_DISABLE
) {
2486 /* don't write DP_TRAINING_LANEx_SET on disable */
2489 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2490 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
2491 len
= intel_dp
->lane_count
+ 1;
2494 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
2501 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2502 uint8_t dp_train_pat
)
2504 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
2505 intel_dp_set_signal_levels(intel_dp
, DP
);
2506 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
2510 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2511 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2513 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2514 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2518 intel_get_adjust_train(intel_dp
, link_status
);
2519 intel_dp_set_signal_levels(intel_dp
, DP
);
2521 I915_WRITE(intel_dp
->output_reg
, *DP
);
2522 POSTING_READ(intel_dp
->output_reg
);
2524 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
2525 intel_dp
->train_set
, intel_dp
->lane_count
);
2527 return ret
== intel_dp
->lane_count
;
2530 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2532 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2533 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2535 enum port port
= intel_dig_port
->port
;
2541 val
= I915_READ(DP_TP_CTL(port
));
2542 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2543 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2544 I915_WRITE(DP_TP_CTL(port
), val
);
2547 * On PORT_A we can have only eDP in SST mode. There the only reason
2548 * we need to set idle transmission mode is to work around a HW issue
2549 * where we enable the pipe while not in idle link-training mode.
2550 * In this case there is requirement to wait for a minimum number of
2551 * idle patterns to be sent.
2556 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2558 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2561 /* Enable corresponding port and start training pattern 1 */
2563 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2565 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2566 struct drm_device
*dev
= encoder
->dev
;
2569 int voltage_tries
, loop_tries
;
2570 uint32_t DP
= intel_dp
->DP
;
2571 uint8_t link_config
[2];
2574 intel_ddi_prepare_link_retrain(encoder
);
2576 /* Write the link configuration data */
2577 link_config
[0] = intel_dp
->link_bw
;
2578 link_config
[1] = intel_dp
->lane_count
;
2579 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2580 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
2581 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
2584 link_config
[1] = DP_SET_ANSI_8B10B
;
2585 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
2589 /* clock recovery */
2590 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
2591 DP_TRAINING_PATTERN_1
|
2592 DP_LINK_SCRAMBLING_DISABLE
)) {
2593 DRM_ERROR("failed to enable link training\n");
2601 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2603 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2604 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2605 DRM_ERROR("failed to get link status\n");
2609 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2610 DRM_DEBUG_KMS("clock recovery OK\n");
2614 /* Check to see if we've tried the max voltage */
2615 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2616 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2618 if (i
== intel_dp
->lane_count
) {
2620 if (loop_tries
== 5) {
2621 DRM_ERROR("too many full retries, give up\n");
2624 intel_dp_reset_link_train(intel_dp
, &DP
,
2625 DP_TRAINING_PATTERN_1
|
2626 DP_LINK_SCRAMBLING_DISABLE
);
2631 /* Check to see if we've tried the same voltage 5 times */
2632 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2634 if (voltage_tries
== 5) {
2635 DRM_ERROR("too many voltage retries, give up\n");
2640 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2642 /* Update training set as requested by target */
2643 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2644 DRM_ERROR("failed to update link training\n");
2653 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2655 bool channel_eq
= false;
2656 int tries
, cr_tries
;
2657 uint32_t DP
= intel_dp
->DP
;
2658 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
2660 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2661 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
2662 training_pattern
= DP_TRAINING_PATTERN_3
;
2664 /* channel equalization */
2665 if (!intel_dp_set_link_train(intel_dp
, &DP
,
2667 DP_LINK_SCRAMBLING_DISABLE
)) {
2668 DRM_ERROR("failed to start channel equalization\n");
2676 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2679 DRM_ERROR("failed to train DP, aborting\n");
2683 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2684 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2685 DRM_ERROR("failed to get link status\n");
2689 /* Make sure clock is still ok */
2690 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2691 intel_dp_start_link_train(intel_dp
);
2692 intel_dp_set_link_train(intel_dp
, &DP
,
2694 DP_LINK_SCRAMBLING_DISABLE
);
2699 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2704 /* Try 5 times, then try clock recovery if that fails */
2706 intel_dp_link_down(intel_dp
);
2707 intel_dp_start_link_train(intel_dp
);
2708 intel_dp_set_link_train(intel_dp
, &DP
,
2710 DP_LINK_SCRAMBLING_DISABLE
);
2716 /* Update training set as requested by target */
2717 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2718 DRM_ERROR("failed to update link training\n");
2724 intel_dp_set_idle_link_train(intel_dp
);
2729 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2733 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2735 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2736 DP_TRAINING_PATTERN_DISABLE
);
2740 intel_dp_link_down(struct intel_dp
*intel_dp
)
2742 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2743 enum port port
= intel_dig_port
->port
;
2744 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2746 struct intel_crtc
*intel_crtc
=
2747 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2748 uint32_t DP
= intel_dp
->DP
;
2751 * DDI code has a strict mode set sequence and we should try to respect
2752 * it, otherwise we might hang the machine in many different ways. So we
2753 * really should be disabling the port only on a complete crtc_disable
2754 * sequence. This function is just called under two conditions on DDI
2756 * - Link train failed while doing crtc_enable, and on this case we
2757 * really should respect the mode set sequence and wait for a
2759 * - Someone turned the monitor off and intel_dp_check_link_status
2760 * called us. We don't need to disable the whole port on this case, so
2761 * when someone turns the monitor on again,
2762 * intel_ddi_prepare_link_retrain will take care of redoing the link
2768 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2771 DRM_DEBUG_KMS("\n");
2773 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2774 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2775 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2777 DP
&= ~DP_LINK_TRAIN_MASK
;
2778 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2780 POSTING_READ(intel_dp
->output_reg
);
2782 if (HAS_PCH_IBX(dev
) &&
2783 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2784 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2786 /* Hardware workaround: leaving our transcoder select
2787 * set to transcoder B while it's off will prevent the
2788 * corresponding HDMI output on transcoder A.
2790 * Combine this with another hardware workaround:
2791 * transcoder select bit can only be cleared while the
2794 DP
&= ~DP_PIPEB_SELECT
;
2795 I915_WRITE(intel_dp
->output_reg
, DP
);
2797 /* Changes to enable or select take place the vblank
2798 * after being written.
2800 if (WARN_ON(crtc
== NULL
)) {
2801 /* We should never try to disable a port without a crtc
2802 * attached. For paranoia keep the code around for a
2804 POSTING_READ(intel_dp
->output_reg
);
2807 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2810 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2811 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2812 POSTING_READ(intel_dp
->output_reg
);
2813 msleep(intel_dp
->panel_power_down_delay
);
2817 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2819 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2820 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2823 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2825 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
2826 sizeof(intel_dp
->dpcd
)) < 0)
2827 return false; /* aux transfer failed */
2829 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2830 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2831 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2833 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2834 return false; /* DPCD not present */
2836 /* Check if the panel supports PSR */
2837 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
2838 if (is_edp(intel_dp
)) {
2839 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
2841 sizeof(intel_dp
->psr_dpcd
));
2842 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
2843 dev_priv
->psr
.sink_support
= true;
2844 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2848 /* Training Pattern 3 support */
2849 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
2850 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
2851 intel_dp
->use_tps3
= true;
2852 DRM_DEBUG_KMS("Displayport TPS3 supported");
2854 intel_dp
->use_tps3
= false;
2856 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2857 DP_DWN_STRM_PORT_PRESENT
))
2858 return true; /* native DP sink */
2860 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2861 return true; /* no per-port downstream info */
2863 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
2864 intel_dp
->downstream_ports
,
2865 DP_MAX_DOWNSTREAM_PORTS
) < 0)
2866 return false; /* downstream port status fetch failed */
2872 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2876 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2879 intel_edp_panel_vdd_on(intel_dp
);
2881 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
2882 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2883 buf
[0], buf
[1], buf
[2]);
2885 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
2886 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2887 buf
[0], buf
[1], buf
[2]);
2889 edp_panel_vdd_off(intel_dp
, false);
2892 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
2894 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2895 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2896 struct intel_crtc
*intel_crtc
=
2897 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2900 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
2903 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
2906 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
2907 DP_TEST_SINK_START
) < 0)
2910 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2911 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2912 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2914 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
2917 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
2922 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2924 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2925 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2926 sink_irq_vector
, 1) == 1;
2930 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2932 /* NAK by default */
2933 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2937 * According to DP spec
2940 * 2. Configure link according to Receiver Capabilities
2941 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2942 * 4. Check link status on receipt of hot-plug interrupt
2946 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2948 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2950 u8 link_status
[DP_LINK_STATUS_SIZE
];
2952 if (!intel_encoder
->connectors_active
)
2955 if (WARN_ON(!intel_encoder
->base
.crtc
))
2958 /* Try to read receiver status if the link appears to be up */
2959 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2963 /* Now read the DPCD to see if it's actually running */
2964 if (!intel_dp_get_dpcd(intel_dp
)) {
2968 /* Try to read the source of the interrupt */
2969 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2970 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2971 /* Clear interrupt source */
2972 drm_dp_dpcd_writeb(&intel_dp
->aux
,
2973 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2976 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2977 intel_dp_handle_test_request(intel_dp
);
2978 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2979 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2982 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2983 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2984 drm_get_encoder_name(&intel_encoder
->base
));
2985 intel_dp_start_link_train(intel_dp
);
2986 intel_dp_complete_link_train(intel_dp
);
2987 intel_dp_stop_link_train(intel_dp
);
2991 /* XXX this is probably wrong for multiple downstream ports */
2992 static enum drm_connector_status
2993 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2995 uint8_t *dpcd
= intel_dp
->dpcd
;
2998 if (!intel_dp_get_dpcd(intel_dp
))
2999 return connector_status_disconnected
;
3001 /* if there's no downstream port, we're done */
3002 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3003 return connector_status_connected
;
3005 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3006 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3007 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3010 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3012 return connector_status_unknown
;
3014 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3015 : connector_status_disconnected
;
3018 /* If no HPD, poke DDC gently */
3019 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3020 return connector_status_connected
;
3022 /* Well we tried, say unknown for unreliable port types */
3023 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3024 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3025 if (type
== DP_DS_PORT_TYPE_VGA
||
3026 type
== DP_DS_PORT_TYPE_NON_EDID
)
3027 return connector_status_unknown
;
3029 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3030 DP_DWN_STRM_PORT_TYPE_MASK
;
3031 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3032 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3033 return connector_status_unknown
;
3036 /* Anything else is out of spec, warn and ignore */
3037 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3038 return connector_status_disconnected
;
3041 static enum drm_connector_status
3042 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3044 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3046 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3047 enum drm_connector_status status
;
3049 /* Can't disconnect eDP, but you can close the lid... */
3050 if (is_edp(intel_dp
)) {
3051 status
= intel_panel_detect(dev
);
3052 if (status
== connector_status_unknown
)
3053 status
= connector_status_connected
;
3057 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3058 return connector_status_disconnected
;
3060 return intel_dp_detect_dpcd(intel_dp
);
3063 static enum drm_connector_status
3064 g4x_dp_detect(struct intel_dp
*intel_dp
)
3066 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3068 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3071 /* Can't disconnect eDP, but you can close the lid... */
3072 if (is_edp(intel_dp
)) {
3073 enum drm_connector_status status
;
3075 status
= intel_panel_detect(dev
);
3076 if (status
== connector_status_unknown
)
3077 status
= connector_status_connected
;
3081 if (IS_VALLEYVIEW(dev
)) {
3082 switch (intel_dig_port
->port
) {
3084 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3087 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3090 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3093 return connector_status_unknown
;
3096 switch (intel_dig_port
->port
) {
3098 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3101 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3104 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3107 return connector_status_unknown
;
3111 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3112 return connector_status_disconnected
;
3114 return intel_dp_detect_dpcd(intel_dp
);
3117 static struct edid
*
3118 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3120 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3122 /* use cached edid if we have one */
3123 if (intel_connector
->edid
) {
3125 if (IS_ERR(intel_connector
->edid
))
3128 return drm_edid_duplicate(intel_connector
->edid
);
3131 return drm_get_edid(connector
, adapter
);
3135 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3137 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3139 /* use cached edid if we have one */
3140 if (intel_connector
->edid
) {
3142 if (IS_ERR(intel_connector
->edid
))
3145 return intel_connector_update_modes(connector
,
3146 intel_connector
->edid
);
3149 return intel_ddc_get_modes(connector
, adapter
);
3152 static enum drm_connector_status
3153 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3155 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3156 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3157 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3158 struct drm_device
*dev
= connector
->dev
;
3159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3160 enum drm_connector_status status
;
3161 enum intel_display_power_domain power_domain
;
3162 struct edid
*edid
= NULL
;
3164 intel_runtime_pm_get(dev_priv
);
3166 power_domain
= intel_display_port_power_domain(intel_encoder
);
3167 intel_display_power_get(dev_priv
, power_domain
);
3169 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3170 connector
->base
.id
, drm_get_connector_name(connector
));
3172 intel_dp
->has_audio
= false;
3174 if (HAS_PCH_SPLIT(dev
))
3175 status
= ironlake_dp_detect(intel_dp
);
3177 status
= g4x_dp_detect(intel_dp
);
3179 if (status
!= connector_status_connected
)
3182 intel_dp_probe_oui(intel_dp
);
3184 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3185 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3187 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3189 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3194 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3195 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3196 status
= connector_status_connected
;
3199 intel_display_power_put(dev_priv
, power_domain
);
3201 intel_runtime_pm_put(dev_priv
);
3206 static int intel_dp_get_modes(struct drm_connector
*connector
)
3208 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3209 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3210 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3211 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3212 struct drm_device
*dev
= connector
->dev
;
3213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3214 enum intel_display_power_domain power_domain
;
3217 /* We should parse the EDID data and find out if it has an audio sink
3220 power_domain
= intel_display_port_power_domain(intel_encoder
);
3221 intel_display_power_get(dev_priv
, power_domain
);
3223 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3224 intel_display_power_put(dev_priv
, power_domain
);
3228 /* if eDP has no EDID, fall back to fixed mode */
3229 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3230 struct drm_display_mode
*mode
;
3231 mode
= drm_mode_duplicate(dev
,
3232 intel_connector
->panel
.fixed_mode
);
3234 drm_mode_probed_add(connector
, mode
);
3242 intel_dp_detect_audio(struct drm_connector
*connector
)
3244 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3245 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3246 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3247 struct drm_device
*dev
= connector
->dev
;
3248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3249 enum intel_display_power_domain power_domain
;
3251 bool has_audio
= false;
3253 power_domain
= intel_display_port_power_domain(intel_encoder
);
3254 intel_display_power_get(dev_priv
, power_domain
);
3256 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3258 has_audio
= drm_detect_monitor_audio(edid
);
3262 intel_display_power_put(dev_priv
, power_domain
);
3268 intel_dp_set_property(struct drm_connector
*connector
,
3269 struct drm_property
*property
,
3272 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3273 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3274 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3275 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3278 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3282 if (property
== dev_priv
->force_audio_property
) {
3286 if (i
== intel_dp
->force_audio
)
3289 intel_dp
->force_audio
= i
;
3291 if (i
== HDMI_AUDIO_AUTO
)
3292 has_audio
= intel_dp_detect_audio(connector
);
3294 has_audio
= (i
== HDMI_AUDIO_ON
);
3296 if (has_audio
== intel_dp
->has_audio
)
3299 intel_dp
->has_audio
= has_audio
;
3303 if (property
== dev_priv
->broadcast_rgb_property
) {
3304 bool old_auto
= intel_dp
->color_range_auto
;
3305 uint32_t old_range
= intel_dp
->color_range
;
3308 case INTEL_BROADCAST_RGB_AUTO
:
3309 intel_dp
->color_range_auto
= true;
3311 case INTEL_BROADCAST_RGB_FULL
:
3312 intel_dp
->color_range_auto
= false;
3313 intel_dp
->color_range
= 0;
3315 case INTEL_BROADCAST_RGB_LIMITED
:
3316 intel_dp
->color_range_auto
= false;
3317 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3323 if (old_auto
== intel_dp
->color_range_auto
&&
3324 old_range
== intel_dp
->color_range
)
3330 if (is_edp(intel_dp
) &&
3331 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3332 if (val
== DRM_MODE_SCALE_NONE
) {
3333 DRM_DEBUG_KMS("no scaling not supported\n");
3337 if (intel_connector
->panel
.fitting_mode
== val
) {
3338 /* the eDP scaling property is not changed */
3341 intel_connector
->panel
.fitting_mode
= val
;
3349 if (intel_encoder
->base
.crtc
)
3350 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3356 intel_dp_connector_destroy(struct drm_connector
*connector
)
3358 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3360 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3361 kfree(intel_connector
->edid
);
3363 /* Can't call is_edp() since the encoder may have been destroyed
3365 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3366 intel_panel_fini(&intel_connector
->panel
);
3368 drm_connector_cleanup(connector
);
3372 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3374 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3375 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3376 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3378 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
3379 drm_encoder_cleanup(encoder
);
3380 if (is_edp(intel_dp
)) {
3381 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3382 mutex_lock(&dev
->mode_config
.mutex
);
3383 edp_panel_vdd_off_sync(intel_dp
);
3384 mutex_unlock(&dev
->mode_config
.mutex
);
3386 kfree(intel_dig_port
);
3389 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3390 .dpms
= intel_connector_dpms
,
3391 .detect
= intel_dp_detect
,
3392 .fill_modes
= drm_helper_probe_single_connector_modes
,
3393 .set_property
= intel_dp_set_property
,
3394 .destroy
= intel_dp_connector_destroy
,
3397 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3398 .get_modes
= intel_dp_get_modes
,
3399 .mode_valid
= intel_dp_mode_valid
,
3400 .best_encoder
= intel_best_encoder
,
3403 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3404 .destroy
= intel_dp_encoder_destroy
,
3408 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3410 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3412 intel_dp_check_link_status(intel_dp
);
3415 /* Return which DP Port should be selected for Transcoder DP control */
3417 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3419 struct drm_device
*dev
= crtc
->dev
;
3420 struct intel_encoder
*intel_encoder
;
3421 struct intel_dp
*intel_dp
;
3423 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3424 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3426 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3427 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3428 return intel_dp
->output_reg
;
3434 /* check the VBT to see whether the eDP is on DP-D port */
3435 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
3437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3438 union child_device_config
*p_child
;
3440 static const short port_mapping
[] = {
3441 [PORT_B
] = PORT_IDPB
,
3442 [PORT_C
] = PORT_IDPC
,
3443 [PORT_D
] = PORT_IDPD
,
3449 if (!dev_priv
->vbt
.child_dev_num
)
3452 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3453 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3455 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
3456 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
3457 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
3464 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3466 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3468 intel_attach_force_audio_property(connector
);
3469 intel_attach_broadcast_rgb_property(connector
);
3470 intel_dp
->color_range_auto
= true;
3472 if (is_edp(intel_dp
)) {
3473 drm_mode_create_scaling_mode_property(connector
->dev
);
3474 drm_object_attach_property(
3476 connector
->dev
->mode_config
.scaling_mode_property
,
3477 DRM_MODE_SCALE_ASPECT
);
3478 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3482 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
3484 intel_dp
->last_power_cycle
= jiffies
;
3485 intel_dp
->last_power_on
= jiffies
;
3486 intel_dp
->last_backlight_off
= jiffies
;
3490 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3491 struct intel_dp
*intel_dp
,
3492 struct edp_power_seq
*out
)
3494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3495 struct edp_power_seq cur
, vbt
, spec
, final
;
3496 u32 pp_on
, pp_off
, pp_div
, pp
;
3497 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3499 if (HAS_PCH_SPLIT(dev
)) {
3500 pp_ctrl_reg
= PCH_PP_CONTROL
;
3501 pp_on_reg
= PCH_PP_ON_DELAYS
;
3502 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3503 pp_div_reg
= PCH_PP_DIVISOR
;
3505 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3507 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3508 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3509 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3510 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3513 /* Workaround: Need to write PP_CONTROL with the unlock key as
3514 * the very first thing. */
3515 pp
= ironlake_get_pp_control(intel_dp
);
3516 I915_WRITE(pp_ctrl_reg
, pp
);
3518 pp_on
= I915_READ(pp_on_reg
);
3519 pp_off
= I915_READ(pp_off_reg
);
3520 pp_div
= I915_READ(pp_div_reg
);
3522 /* Pull timing values out of registers */
3523 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3524 PANEL_POWER_UP_DELAY_SHIFT
;
3526 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3527 PANEL_LIGHT_ON_DELAY_SHIFT
;
3529 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3530 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3532 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3533 PANEL_POWER_DOWN_DELAY_SHIFT
;
3535 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3536 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3538 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3539 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3541 vbt
= dev_priv
->vbt
.edp_pps
;
3543 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3544 * our hw here, which are all in 100usec. */
3545 spec
.t1_t3
= 210 * 10;
3546 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3547 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3548 spec
.t10
= 500 * 10;
3549 /* This one is special and actually in units of 100ms, but zero
3550 * based in the hw (so we need to add 100 ms). But the sw vbt
3551 * table multiplies it with 1000 to make it in units of 100usec,
3553 spec
.t11_t12
= (510 + 100) * 10;
3555 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3556 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3558 /* Use the max of the register settings and vbt. If both are
3559 * unset, fall back to the spec limits. */
3560 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3562 max(cur.field, vbt.field))
3563 assign_final(t1_t3
);
3567 assign_final(t11_t12
);
3570 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3571 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3572 intel_dp
->backlight_on_delay
= get_delay(t8
);
3573 intel_dp
->backlight_off_delay
= get_delay(t9
);
3574 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3575 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3578 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3579 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3580 intel_dp
->panel_power_cycle_delay
);
3582 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3583 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3590 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3591 struct intel_dp
*intel_dp
,
3592 struct edp_power_seq
*seq
)
3594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3595 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3596 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3597 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3599 if (HAS_PCH_SPLIT(dev
)) {
3600 pp_on_reg
= PCH_PP_ON_DELAYS
;
3601 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3602 pp_div_reg
= PCH_PP_DIVISOR
;
3604 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3606 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3607 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3608 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3612 * And finally store the new values in the power sequencer. The
3613 * backlight delays are set to 1 because we do manual waits on them. For
3614 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3615 * we'll end up waiting for the backlight off delay twice: once when we
3616 * do the manual sleep, and once when we disable the panel and wait for
3617 * the PP_STATUS bit to become zero.
3619 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3620 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
3621 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3622 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3623 /* Compute the divisor for the pp clock, simply match the Bspec
3625 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3626 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3627 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3629 /* Haswell doesn't have any port selection bits for the panel
3630 * power sequencer any more. */
3631 if (IS_VALLEYVIEW(dev
)) {
3632 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3633 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3635 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3636 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3637 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
3638 port_sel
= PANEL_PORT_SELECT_DPA
;
3640 port_sel
= PANEL_PORT_SELECT_DPD
;
3645 I915_WRITE(pp_on_reg
, pp_on
);
3646 I915_WRITE(pp_off_reg
, pp_off
);
3647 I915_WRITE(pp_div_reg
, pp_div
);
3649 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3650 I915_READ(pp_on_reg
),
3651 I915_READ(pp_off_reg
),
3652 I915_READ(pp_div_reg
));
3655 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
3657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3658 struct intel_encoder
*encoder
;
3659 struct intel_dp
*intel_dp
= NULL
;
3660 struct intel_crtc_config
*config
= NULL
;
3661 struct intel_crtc
*intel_crtc
= NULL
;
3662 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
3664 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
3666 if (refresh_rate
<= 0) {
3667 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3671 if (intel_connector
== NULL
) {
3672 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3676 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
3677 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3681 encoder
= intel_attached_encoder(&intel_connector
->base
);
3682 intel_dp
= enc_to_intel_dp(&encoder
->base
);
3683 intel_crtc
= encoder
->new_crtc
;
3686 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3690 config
= &intel_crtc
->config
;
3692 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
3693 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3697 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
3698 index
= DRRS_LOW_RR
;
3700 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
3702 "DRRS requested for previously set RR...ignoring\n");
3706 if (!intel_crtc
->active
) {
3707 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3711 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
3712 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
3713 val
= I915_READ(reg
);
3714 if (index
> DRRS_HIGH_RR
) {
3715 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
3716 intel_dp_set_m2_n2(intel_crtc
, &config
->dp_m2_n2
);
3718 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
3720 I915_WRITE(reg
, val
);
3724 * mutex taken to ensure that there is no race between differnt
3725 * drrs calls trying to update refresh rate. This scenario may occur
3726 * in future when idleness detection based DRRS in kernel and
3727 * possible calls from user space to set differnt RR are made.
3730 mutex_lock(&intel_dp
->drrs_state
.mutex
);
3732 intel_dp
->drrs_state
.refresh_rate_type
= index
;
3734 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
3736 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
3739 static struct drm_display_mode
*
3740 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
3741 struct intel_connector
*intel_connector
,
3742 struct drm_display_mode
*fixed_mode
)
3744 struct drm_connector
*connector
= &intel_connector
->base
;
3745 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3746 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3748 struct drm_display_mode
*downclock_mode
= NULL
;
3750 if (INTEL_INFO(dev
)->gen
<= 6) {
3751 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3755 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
3756 DRM_INFO("VBT doesn't support DRRS\n");
3760 downclock_mode
= intel_find_panel_downclock
3761 (dev
, fixed_mode
, connector
);
3763 if (!downclock_mode
) {
3764 DRM_INFO("DRRS not supported\n");
3768 dev_priv
->drrs
.connector
= intel_connector
;
3770 mutex_init(&intel_dp
->drrs_state
.mutex
);
3772 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
3774 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
3775 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3776 return downclock_mode
;
3779 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
3780 struct intel_connector
*intel_connector
,
3781 struct edp_power_seq
*power_seq
)
3783 struct drm_connector
*connector
= &intel_connector
->base
;
3784 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3785 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3786 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3788 struct drm_display_mode
*fixed_mode
= NULL
;
3789 struct drm_display_mode
*downclock_mode
= NULL
;
3791 struct drm_display_mode
*scan
;
3794 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
3796 if (!is_edp(intel_dp
))
3799 /* The VDD bit needs a power domain reference, so if the bit is already
3800 * enabled when we boot, grab this reference. */
3801 if (edp_have_panel_vdd(intel_dp
)) {
3802 enum intel_display_power_domain power_domain
;
3803 power_domain
= intel_display_port_power_domain(intel_encoder
);
3804 intel_display_power_get(dev_priv
, power_domain
);
3807 /* Cache DPCD and EDID for edp. */
3808 intel_edp_panel_vdd_on(intel_dp
);
3809 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
3810 edp_panel_vdd_off(intel_dp
, false);
3813 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3814 dev_priv
->no_aux_handshake
=
3815 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3816 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3818 /* if this fails, presume the device is a ghost */
3819 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3823 /* We now know it's not a ghost, init power sequence regs. */
3824 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
3826 mutex_lock(&dev
->mode_config
.mutex
);
3827 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
3829 if (drm_add_edid_modes(connector
, edid
)) {
3830 drm_mode_connector_update_edid_property(connector
,
3832 drm_edid_to_eld(connector
, edid
);
3835 edid
= ERR_PTR(-EINVAL
);
3838 edid
= ERR_PTR(-ENOENT
);
3840 intel_connector
->edid
= edid
;
3842 /* prefer fixed mode from EDID if available */
3843 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
3844 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
3845 fixed_mode
= drm_mode_duplicate(dev
, scan
);
3846 downclock_mode
= intel_dp_drrs_init(
3848 intel_connector
, fixed_mode
);
3853 /* fallback to VBT if available for eDP */
3854 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
3855 fixed_mode
= drm_mode_duplicate(dev
,
3856 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
3858 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
3860 mutex_unlock(&dev
->mode_config
.mutex
);
3862 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
3863 intel_panel_setup_backlight(connector
);
3869 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
3870 struct intel_connector
*intel_connector
)
3872 struct drm_connector
*connector
= &intel_connector
->base
;
3873 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3874 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3875 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3877 enum port port
= intel_dig_port
->port
;
3878 struct edp_power_seq power_seq
= { 0 };
3881 /* intel_dp vfuncs */
3882 if (IS_VALLEYVIEW(dev
))
3883 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
3884 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3885 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
3886 else if (HAS_PCH_SPLIT(dev
))
3887 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
3889 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
3891 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
3893 /* Preserve the current hw state. */
3894 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
3895 intel_dp
->attached_connector
= intel_connector
;
3897 if (intel_dp_is_edp(dev
, port
))
3898 type
= DRM_MODE_CONNECTOR_eDP
;
3900 type
= DRM_MODE_CONNECTOR_DisplayPort
;
3903 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3904 * for DP the encoder type can be set by the caller to
3905 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3907 if (type
== DRM_MODE_CONNECTOR_eDP
)
3908 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
3910 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3911 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
3914 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
3915 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
3917 connector
->interlace_allowed
= true;
3918 connector
->doublescan_allowed
= 0;
3920 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
3921 edp_panel_vdd_work
);
3923 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3924 drm_sysfs_connector_add(connector
);
3927 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3929 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3930 intel_connector
->unregister
= intel_dp_connector_unregister
;
3932 /* Set up the hotplug pin. */
3935 intel_encoder
->hpd_pin
= HPD_PORT_A
;
3938 intel_encoder
->hpd_pin
= HPD_PORT_B
;
3941 intel_encoder
->hpd_pin
= HPD_PORT_C
;
3944 intel_encoder
->hpd_pin
= HPD_PORT_D
;
3950 if (is_edp(intel_dp
)) {
3951 intel_dp_init_panel_power_timestamps(intel_dp
);
3952 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
3955 intel_dp_aux_init(intel_dp
, intel_connector
);
3957 intel_dp
->psr_setup_done
= false;
3959 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
3960 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
3961 if (is_edp(intel_dp
)) {
3962 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3963 mutex_lock(&dev
->mode_config
.mutex
);
3964 edp_panel_vdd_off_sync(intel_dp
);
3965 mutex_unlock(&dev
->mode_config
.mutex
);
3967 drm_sysfs_connector_remove(connector
);
3968 drm_connector_cleanup(connector
);
3972 intel_dp_add_properties(intel_dp
, connector
);
3974 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3975 * 0xd. Failure to do so will result in spurious interrupts being
3976 * generated on the port when a cable is not attached.
3978 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
3979 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3980 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3987 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
3989 struct intel_digital_port
*intel_dig_port
;
3990 struct intel_encoder
*intel_encoder
;
3991 struct drm_encoder
*encoder
;
3992 struct intel_connector
*intel_connector
;
3994 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3995 if (!intel_dig_port
)
3998 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
3999 if (!intel_connector
) {
4000 kfree(intel_dig_port
);
4004 intel_encoder
= &intel_dig_port
->base
;
4005 encoder
= &intel_encoder
->base
;
4007 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4008 DRM_MODE_ENCODER_TMDS
);
4010 intel_encoder
->compute_config
= intel_dp_compute_config
;
4011 intel_encoder
->mode_set
= intel_dp_mode_set
;
4012 intel_encoder
->disable
= intel_disable_dp
;
4013 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4014 intel_encoder
->get_config
= intel_dp_get_config
;
4015 if (IS_VALLEYVIEW(dev
)) {
4016 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4017 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4018 intel_encoder
->enable
= vlv_enable_dp
;
4019 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4021 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4022 intel_encoder
->enable
= g4x_enable_dp
;
4023 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4026 intel_dig_port
->port
= port
;
4027 intel_dig_port
->dp
.output_reg
= output_reg
;
4029 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4030 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4031 intel_encoder
->cloneable
= 0;
4032 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4034 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4035 drm_encoder_cleanup(encoder
);
4036 kfree(intel_dig_port
);
4037 kfree(intel_connector
);