2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * __wait_for - magic wait macro
46 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
47 * important that we check the condition again after having timed out, since the
48 * timeout could be due to preemption or similar and we've never had a chance to
49 * check the condition before the timeout.
51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
52 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
53 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
57 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
59 /* Guarantee COND check prior to timeout */ \
69 usleep_range(wait__, wait__ * 2); \
70 if (wait__ < (Wmax)) \
76 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
78 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
80 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
81 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
84 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
87 #define _wait_for_atomic(COND, US, ATOMIC) \
89 int cpu, ret, timeout = (US) * 1000; \
91 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
94 cpu = smp_processor_id(); \
96 base = local_clock(); \
98 u64 now = local_clock(); \
101 /* Guarantee COND check prior to timeout */ \
107 if (now - base >= timeout) { \
114 if (unlikely(cpu != smp_processor_id())) { \
115 timeout -= now - base; \
116 cpu = smp_processor_id(); \
117 base = local_clock(); \
124 #define wait_for_us(COND, US) \
127 BUILD_BUG_ON(!__builtin_constant_p(US)); \
129 ret__ = _wait_for((COND), (US), 10, 10); \
131 ret__ = _wait_for_atomic((COND), (US), 0); \
135 #define wait_for_atomic_us(COND, US) \
137 BUILD_BUG_ON(!__builtin_constant_p(US)); \
138 BUILD_BUG_ON((US) > 50000); \
139 _wait_for_atomic((COND), (US), 1); \
142 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
144 #define KHz(x) (1000 * (x))
145 #define MHz(x) KHz(1000 * (x))
147 #define KBps(x) (1000 * (x))
148 #define MBps(x) KBps(1000 * (x))
149 #define GBps(x) ((u64)1000 * MBps((x)))
152 * Display related stuff
155 /* store information about an Ixxx DVO */
156 /* The i830->i865 use multiple DVOs with multiple i2cs */
157 /* the i915, i945 have a single sDVO i2c bus - which is different */
158 #define MAX_OUTPUTS 6
159 /* maximum connectors per crtcs in the mode set */
161 #define INTEL_I2C_BUS_DVO 1
162 #define INTEL_I2C_BUS_SDVO 2
164 /* these are outputs from the chip - integrated only
165 external chips are via DVO or SDVO output */
166 enum intel_output_type
{
167 INTEL_OUTPUT_UNUSED
= 0,
168 INTEL_OUTPUT_ANALOG
= 1,
169 INTEL_OUTPUT_DVO
= 2,
170 INTEL_OUTPUT_SDVO
= 3,
171 INTEL_OUTPUT_LVDS
= 4,
172 INTEL_OUTPUT_TVOUT
= 5,
173 INTEL_OUTPUT_HDMI
= 6,
175 INTEL_OUTPUT_EDP
= 8,
176 INTEL_OUTPUT_DSI
= 9,
177 INTEL_OUTPUT_DDI
= 10,
178 INTEL_OUTPUT_DP_MST
= 11,
181 #define INTEL_DVO_CHIP_NONE 0
182 #define INTEL_DVO_CHIP_LVDS 1
183 #define INTEL_DVO_CHIP_TMDS 2
184 #define INTEL_DVO_CHIP_TVOUT 4
186 #define INTEL_DSI_VIDEO_MODE 0
187 #define INTEL_DSI_COMMAND_MODE 1
189 struct intel_framebuffer
{
190 struct drm_framebuffer base
;
191 struct intel_rotation_info rot_info
;
193 /* for each plane in the normal GTT view */
197 /* for each plane in the rotated GTT view */
200 unsigned int pitch
; /* pixels */
205 struct drm_fb_helper helper
;
206 struct intel_framebuffer
*fb
;
207 struct i915_vma
*vma
;
208 unsigned long vma_flags
;
209 async_cookie_t cookie
;
213 struct intel_encoder
{
214 struct drm_encoder base
;
216 enum intel_output_type type
;
218 unsigned int cloneable
;
219 bool (*hotplug
)(struct intel_encoder
*encoder
,
220 struct intel_connector
*connector
);
221 enum intel_output_type (*compute_output_type
)(struct intel_encoder
*,
222 struct intel_crtc_state
*,
223 struct drm_connector_state
*);
224 bool (*compute_config
)(struct intel_encoder
*,
225 struct intel_crtc_state
*,
226 struct drm_connector_state
*);
227 void (*pre_pll_enable
)(struct intel_encoder
*,
228 const struct intel_crtc_state
*,
229 const struct drm_connector_state
*);
230 void (*pre_enable
)(struct intel_encoder
*,
231 const struct intel_crtc_state
*,
232 const struct drm_connector_state
*);
233 void (*enable
)(struct intel_encoder
*,
234 const struct intel_crtc_state
*,
235 const struct drm_connector_state
*);
236 void (*disable
)(struct intel_encoder
*,
237 const struct intel_crtc_state
*,
238 const struct drm_connector_state
*);
239 void (*post_disable
)(struct intel_encoder
*,
240 const struct intel_crtc_state
*,
241 const struct drm_connector_state
*);
242 void (*post_pll_disable
)(struct intel_encoder
*,
243 const struct intel_crtc_state
*,
244 const struct drm_connector_state
*);
245 /* Read out the current hw state of this connector, returning true if
246 * the encoder is active. If the encoder is enabled it also set the pipe
247 * it is connected to in the pipe parameter. */
248 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
249 /* Reconstructs the equivalent mode flags for the current hardware
250 * state. This must be called _after_ display->get_pipe_config has
251 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
252 * be set correctly before calling this function. */
253 void (*get_config
)(struct intel_encoder
*,
254 struct intel_crtc_state
*pipe_config
);
255 /* Returns a mask of power domains that need to be referenced as part
256 * of the hardware state readout code. */
257 u64 (*get_power_domains
)(struct intel_encoder
*encoder
);
259 * Called during system suspend after all pending requests for the
260 * encoder are flushed (for example for DP AUX transactions) and
261 * device interrupts are disabled.
263 void (*suspend
)(struct intel_encoder
*);
265 enum hpd_pin hpd_pin
;
266 enum intel_display_power_domain power_domain
;
267 /* for communication with audio component; protected by av_mutex */
268 const struct drm_connector
*audio_connector
;
272 struct drm_display_mode
*fixed_mode
;
273 struct drm_display_mode
*downclock_mode
;
282 bool combination_mode
; /* gen 2/4 only */
284 bool alternate_pwm_increment
; /* lpt+ */
287 bool util_pin_active_low
; /* bxt+ */
288 u8 controller
; /* bxt+ only */
289 struct pwm_device
*pwm
;
291 struct backlight_device
*device
;
293 /* Connector and platform specific backlight functions */
294 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
295 uint32_t (*get
)(struct intel_connector
*connector
);
296 void (*set
)(const struct drm_connector_state
*conn_state
, uint32_t level
);
297 void (*disable
)(const struct drm_connector_state
*conn_state
);
298 void (*enable
)(const struct intel_crtc_state
*crtc_state
,
299 const struct drm_connector_state
*conn_state
);
300 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
302 void (*power
)(struct intel_connector
*, bool enable
);
307 * This structure serves as a translation layer between the generic HDCP code
308 * and the bus-specific code. What that means is that HDCP over HDMI differs
309 * from HDCP over DP, so to account for these differences, we need to
310 * communicate with the receiver through this shim.
312 * For completeness, the 2 buses differ in the following ways:
314 * HDCP registers on the receiver are set via DP AUX for DP, and
315 * they are set via DDC for HDMI.
316 * - Receiver register offsets
317 * The offsets of the registers are different for DP vs. HDMI
318 * - Receiver register masks/offsets
319 * For instance, the ready bit for the KSV fifo is in a different
320 * place on DP vs HDMI
321 * - Receiver register names
322 * Seriously. In the DP spec, the 16-bit register containing
323 * downstream information is called BINFO, on HDMI it's called
324 * BSTATUS. To confuse matters further, DP has a BSTATUS register
325 * with a completely different definition.
327 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
328 * be read 3 keys at a time
330 * Since Aksv is hidden in hardware, there's different procedures
331 * to send it over DP AUX vs DDC
333 struct intel_hdcp_shim
{
334 /* Outputs the transmitter's An and Aksv values to the receiver. */
335 int (*write_an_aksv
)(struct intel_digital_port
*intel_dig_port
, u8
*an
);
337 /* Reads the receiver's key selection vector */
338 int (*read_bksv
)(struct intel_digital_port
*intel_dig_port
, u8
*bksv
);
341 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
342 * definitions are the same in the respective specs, but the names are
343 * different. Call it BSTATUS since that's the name the HDMI spec
344 * uses and it was there first.
346 int (*read_bstatus
)(struct intel_digital_port
*intel_dig_port
,
349 /* Determines whether a repeater is present downstream */
350 int (*repeater_present
)(struct intel_digital_port
*intel_dig_port
,
351 bool *repeater_present
);
353 /* Reads the receiver's Ri' value */
354 int (*read_ri_prime
)(struct intel_digital_port
*intel_dig_port
, u8
*ri
);
356 /* Determines if the receiver's KSV FIFO is ready for consumption */
357 int (*read_ksv_ready
)(struct intel_digital_port
*intel_dig_port
,
360 /* Reads the ksv fifo for num_downstream devices */
361 int (*read_ksv_fifo
)(struct intel_digital_port
*intel_dig_port
,
362 int num_downstream
, u8
*ksv_fifo
);
364 /* Reads a 32-bit part of V' from the receiver */
365 int (*read_v_prime_part
)(struct intel_digital_port
*intel_dig_port
,
368 /* Enables HDCP signalling on the port */
369 int (*toggle_signalling
)(struct intel_digital_port
*intel_dig_port
,
372 /* Ensures the link is still protected */
373 bool (*check_link
)(struct intel_digital_port
*intel_dig_port
);
375 /* Detects panel's hdcp capability. This is optional for HDMI. */
376 int (*hdcp_capable
)(struct intel_digital_port
*intel_dig_port
,
380 struct intel_connector
{
381 struct drm_connector base
;
383 * The fixed encoder this connector is connected to.
385 struct intel_encoder
*encoder
;
387 /* ACPI device id for ACPI and driver cooperation */
390 /* Reads out the current hw, returning true if the connector is enabled
391 * and active (i.e. dpms ON state). */
392 bool (*get_hw_state
)(struct intel_connector
*);
394 /* Panel info for eDP and LVDS */
395 struct intel_panel panel
;
397 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
399 struct edid
*detect_edid
;
401 /* since POLL and HPD connectors may use the same HPD line keep the native
402 state of connector->polled in case hotplug storm detection changes it */
405 void *port
; /* store this opaque as its illegal to dereference it */
407 struct intel_dp
*mst_port
;
409 /* Work struct to schedule a uevent on link train failure */
410 struct work_struct modeset_retry_work
;
412 const struct intel_hdcp_shim
*hdcp_shim
;
413 struct mutex hdcp_mutex
;
414 uint64_t hdcp_value
; /* protected by hdcp_mutex */
415 struct delayed_work hdcp_check_work
;
416 struct work_struct hdcp_prop_work
;
419 struct intel_digital_connector_state
{
420 struct drm_connector_state base
;
422 enum hdmi_force_audio force_audio
;
426 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
440 struct intel_atomic_state
{
441 struct drm_atomic_state base
;
445 * Logical state of cdclk (used for all scaling, watermark,
446 * etc. calculations and checks). This is computed as if all
447 * enabled crtcs were active.
449 struct intel_cdclk_state logical
;
452 * Actual state of cdclk, can be different from the logical
453 * state only when all crtc's are DPMS off.
455 struct intel_cdclk_state actual
;
458 bool dpll_set
, modeset
;
461 * Does this transaction change the pipes that are active? This mask
462 * tracks which CRTC's have changed their active state at the end of
463 * the transaction (not counting the temporary disable during modesets).
464 * This mask should only be non-zero when intel_state->modeset is true,
465 * but the converse is not necessarily true; simply changing a mode may
466 * not flip the final active status of any CRTC's
468 unsigned int active_pipe_changes
;
470 unsigned int active_crtcs
;
471 /* minimum acceptable cdclk for each pipe */
472 int min_cdclk
[I915_MAX_PIPES
];
473 /* minimum acceptable voltage level for each pipe */
474 u8 min_voltage_level
[I915_MAX_PIPES
];
476 struct intel_shared_dpll_state shared_dpll
[I915_NUM_PLLS
];
479 * Current watermarks can't be trusted during hardware readout, so
480 * don't bother calculating intermediate watermarks.
482 bool skip_intermediate_wm
;
485 struct skl_ddb_values wm_results
;
487 struct i915_sw_fence commit_ready
;
489 struct llist_node freed
;
492 struct intel_plane_state
{
493 struct drm_plane_state base
;
494 struct i915_vma
*vma
;
496 #define PLANE_HAS_FENCE BIT(0)
507 /* plane control register */
510 /* plane color control register */
515 * = -1 : not using a scaler
516 * >= 0 : using a scalers
518 * plane requiring a scaler:
519 * - During check_plane, its bit is set in
520 * crtc_state->scaler_state.scaler_users by calling helper function
521 * update_scaler_plane.
522 * - scaler_id indicates the scaler it got assigned.
524 * plane doesn't require a scaler:
525 * - this can happen when scaling is no more required or plane simply
527 * - During check_plane, corresponding bit is reset in
528 * crtc_state->scaler_state.scaler_users by calling helper function
529 * update_scaler_plane.
533 struct drm_intel_sprite_colorkey ckey
;
536 struct intel_initial_plane_config
{
537 struct intel_framebuffer
*fb
;
543 #define SKL_MIN_SRC_W 8
544 #define SKL_MAX_SRC_W 4096
545 #define SKL_MIN_SRC_H 8
546 #define SKL_MAX_SRC_H 4096
547 #define SKL_MIN_DST_W 8
548 #define SKL_MAX_DST_W 4096
549 #define SKL_MIN_DST_H 8
550 #define SKL_MAX_DST_H 4096
551 #define ICL_MAX_SRC_W 5120
552 #define ICL_MAX_SRC_H 4096
553 #define ICL_MAX_DST_W 5120
554 #define ICL_MAX_DST_H 4096
555 #define SKL_MIN_YUV_420_SRC_W 16
556 #define SKL_MIN_YUV_420_SRC_H 16
558 struct intel_scaler
{
563 struct intel_crtc_scaler_state
{
564 #define SKL_NUM_SCALERS 2
565 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
568 * scaler_users: keeps track of users requesting scalers on this crtc.
570 * If a bit is set, a user is using a scaler.
571 * Here user can be a plane or crtc as defined below:
572 * bits 0-30 - plane (bit position is index from drm_plane_index)
575 * Instead of creating a new index to cover planes and crtc, using
576 * existing drm_plane_index for planes which is well less than 31
577 * planes and bit 31 for crtc. This should be fine to cover all
580 * intel_atomic_setup_scalers will setup available scalers to users
581 * requesting scalers. It will gracefully fail if request exceeds
584 #define SKL_CRTC_INDEX 31
585 unsigned scaler_users
;
587 /* scaler used by crtc for panel fitting purpose */
591 /* drm_mode->private_flags */
592 #define I915_MODE_FLAG_INHERITED 1
593 /* Flag to get scanline using frame time stamps */
594 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
596 struct intel_pipe_wm
{
597 struct intel_wm_level wm
[5];
601 bool sprites_enabled
;
605 struct skl_plane_wm
{
606 struct skl_wm_level wm
[8];
607 struct skl_wm_level uv_wm
[8];
608 struct skl_wm_level trans_wm
;
613 struct skl_plane_wm planes
[I915_MAX_PLANES
];
620 VLV_WM_LEVEL_DDR_DVFS
,
624 struct vlv_wm_state
{
625 struct g4x_pipe_wm wm
[NUM_VLV_WM_LEVELS
];
626 struct g4x_sr_wm sr
[NUM_VLV_WM_LEVELS
];
631 struct vlv_fifo_state
{
632 u16 plane
[I915_MAX_PLANES
];
642 struct g4x_wm_state
{
643 struct g4x_pipe_wm wm
;
645 struct g4x_sr_wm hpll
;
651 struct intel_crtc_wm_state
{
655 * Intermediate watermarks; these can be
656 * programmed immediately since they satisfy
657 * both the current configuration we're
658 * switching away from and the new
659 * configuration we're switching to.
661 struct intel_pipe_wm intermediate
;
664 * Optimal watermarks, programmed post-vblank
665 * when this state is committed.
667 struct intel_pipe_wm optimal
;
671 /* gen9+ only needs 1-step wm programming */
672 struct skl_pipe_wm optimal
;
673 struct skl_ddb_entry ddb
;
677 /* "raw" watermarks (not inverted) */
678 struct g4x_pipe_wm raw
[NUM_VLV_WM_LEVELS
];
679 /* intermediate watermarks (inverted) */
680 struct vlv_wm_state intermediate
;
681 /* optimal watermarks (inverted) */
682 struct vlv_wm_state optimal
;
683 /* display FIFO split */
684 struct vlv_fifo_state fifo_state
;
688 /* "raw" watermarks */
689 struct g4x_pipe_wm raw
[NUM_G4X_WM_LEVELS
];
690 /* intermediate watermarks */
691 struct g4x_wm_state intermediate
;
692 /* optimal watermarks */
693 struct g4x_wm_state optimal
;
698 * Platforms with two-step watermark programming will need to
699 * update watermark programming post-vblank to switch from the
700 * safe intermediate watermarks to the optimal final
703 bool need_postvbl_update
;
706 struct intel_crtc_state
{
707 struct drm_crtc_state base
;
710 * quirks - bitfield with hw state readout quirks
712 * For various reasons the hw state readout code might not be able to
713 * completely faithfully read out the current state. These cases are
714 * tracked with quirk flags so that fastboot and state checker can act
717 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
718 unsigned long quirks
;
720 unsigned fb_bits
; /* framebuffers to flip */
721 bool update_pipe
; /* can a fast modeset be performed? */
723 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
724 bool fb_changed
; /* fb on any of the planes is changed */
725 bool fifo_changed
; /* FIFO split is changed */
727 /* Pipe source size (ie. panel fitter input size)
728 * All planes will be positioned inside this space,
729 * and get clipped at the edges. */
730 int pipe_src_w
, pipe_src_h
;
733 * Pipe pixel rate, adjusted for
734 * panel fitter/pipe scaler downscaling.
736 unsigned int pixel_rate
;
738 /* Whether to set up the PCH/FDI. Note that we never allow sharing
739 * between pch encoders and cpu encoders. */
740 bool has_pch_encoder
;
742 /* Are we sending infoframes on the attached port */
745 /* CPU Transcoder for the pipe. Currently this can only differ from the
746 * pipe on Haswell and later (where we have a special eDP transcoder)
747 * and Broxton (where we have special DSI transcoders). */
748 enum transcoder cpu_transcoder
;
751 * Use reduced/limited/broadcast rbg range, compressing from the full
752 * range fed into the crtcs.
754 bool limited_color_range
;
756 /* Bitmask of encoder types (enum intel_output_type)
757 * driven by the pipe.
759 unsigned int output_types
;
761 /* Whether we should send NULL infoframes. Required for audio. */
764 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
765 * has_dp_encoder is set. */
769 * Enable dithering, used when the selected pipe bpp doesn't match the
775 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
776 * compliance video pattern tests.
777 * Disable dither only if it is a compliance test request for
780 bool dither_force_disable
;
782 /* Controls for the clock computation, to override various stages. */
785 /* SDVO TV has a bunch of special case. To make multifunction encoders
786 * work correctly, we need to track this at runtime.*/
790 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
791 * required. This is set in the 2nd loop of calling encoder's
792 * ->compute_config if the first pick doesn't work out.
796 /* Settings for the intel dpll used on pretty much everything but
800 /* Selected dpll when shared or NULL. */
801 struct intel_shared_dpll
*shared_dpll
;
803 /* Actual register state of the dpll, for shared dpll cross-checking. */
804 struct intel_dpll_hw_state dpll_hw_state
;
806 /* DSI PLL registers */
812 struct intel_link_m_n dp_m_n
;
814 /* m2_n2 for eDP downclock */
815 struct intel_link_m_n dp_m2_n2
;
822 * Frequence the dpll for the port should run at. Differs from the
823 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
824 * already multiplied by pixel_multiplier.
828 /* Used by SDVO (and if we ever fix it, HDMI). */
829 unsigned pixel_multiplier
;
834 * Used by platforms having DP/HDMI PHY with programmable lane
835 * latency optimization.
837 uint8_t lane_lat_optim_mask
;
839 /* minimum acceptable voltage level */
840 u8 min_voltage_level
;
842 /* Panel fitter controls for gen2-gen4 + VLV */
846 u32 lvds_border_bits
;
849 /* Panel fitter placement and size for Ironlake+ */
857 /* FDI configuration, only valid if has_pch_encoder is set. */
859 struct intel_link_m_n fdi_m_n
;
862 bool ips_force_disable
;
870 struct intel_crtc_scaler_state scaler_state
;
872 /* w/a for waiting 2 vblanks during crtc enable */
873 enum pipe hsw_workaround_pipe
;
875 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
878 struct intel_crtc_wm_state wm
;
880 /* Gamma mode programmed on the pipe */
883 /* bitmask of visible planes (enum plane_id) */
887 /* HDMI scrambling status */
888 bool hdmi_scrambling
;
890 /* HDMI High TMDS char rate ratio */
891 bool hdmi_high_tmds_clock_ratio
;
893 /* output format is YCBCR 4:2:0 */
898 struct drm_crtc base
;
901 * Whether the crtc and the connected output pipeline is active. Implies
902 * that crtc->enabled is set, i.e. the current mode configuration has
903 * some outputs connected to this crtc.
907 unsigned long long enabled_power_domains
;
908 struct intel_overlay
*overlay
;
910 struct intel_crtc_state
*config
;
912 /* global reset count when the last flip was submitted */
913 unsigned int reset_count
;
915 /* Access to these should be protected by dev_priv->irq_lock. */
916 bool cpu_fifo_underrun_disabled
;
917 bool pch_fifo_underrun_disabled
;
919 /* per-pipe watermark state */
921 /* watermarks currently being used */
923 struct intel_pipe_wm ilk
;
924 struct vlv_wm_state vlv
;
925 struct g4x_wm_state g4x
;
932 unsigned start_vbl_count
;
933 ktime_t start_vbl_time
;
934 int min_vbl
, max_vbl
;
938 /* scalers available on this crtc */
943 struct drm_plane base
;
944 enum i9xx_plane_id i9xx_plane
;
951 uint32_t frontbuffer_bit
;
954 u32 base
, cntl
, size
;
958 * NOTE: Do not place new plane state fields here (e.g., when adding
959 * new plane properties). New runtime state should now be placed in
960 * the intel_plane_state structure and accessed via plane_state.
963 void (*update_plane
)(struct intel_plane
*plane
,
964 const struct intel_crtc_state
*crtc_state
,
965 const struct intel_plane_state
*plane_state
);
966 void (*disable_plane
)(struct intel_plane
*plane
,
967 struct intel_crtc
*crtc
);
968 bool (*get_hw_state
)(struct intel_plane
*plane
, enum pipe
*pipe
);
969 int (*check_plane
)(struct intel_plane
*plane
,
970 struct intel_crtc_state
*crtc_state
,
971 struct intel_plane_state
*state
);
974 struct intel_watermark_params
{
982 struct cxsr_latency
{
988 u16 display_hpll_disable
;
990 u16 cursor_hpll_disable
;
993 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
994 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
995 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
996 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
997 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
998 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
999 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1000 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1001 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1004 i915_reg_t hdmi_reg
;
1007 enum drm_dp_dual_mode_type type
;
1012 bool rgb_quant_range_selectable
;
1013 struct intel_connector
*attached_connector
;
1016 struct intel_dp_mst_encoder
;
1017 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1020 * enum link_m_n_set:
1021 * When platform provides two set of M_N registers for dp, we can
1022 * program them and switch between them incase of DRRS.
1023 * But When only one such register is provided, we have to program the
1024 * required divider value on that registers itself based on the DRRS state.
1026 * M1_N1 : Program dp_m_n on M1_N1 registers
1027 * dp_m2_n2 on M2_N2 registers (If supported)
1029 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1030 * M2_N2 registers are not supported
1034 /* Sets the m1_n1 and m2_n2 */
1039 struct intel_dp_compliance_data
{
1041 uint8_t video_pattern
;
1042 uint16_t hdisplay
, vdisplay
;
1046 struct intel_dp_compliance
{
1047 unsigned long test_type
;
1048 struct intel_dp_compliance_data test_data
;
1055 i915_reg_t output_reg
;
1064 bool reset_link_params
;
1066 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
1067 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
1068 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
1069 uint8_t edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
1071 int num_source_rates
;
1072 const int *source_rates
;
1073 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1075 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
1076 bool use_rate_select
;
1077 /* intersection of source and sink rates */
1078 int num_common_rates
;
1079 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1080 /* Max lane count for the current link */
1081 int max_link_lane_count
;
1082 /* Max rate for the current link */
1084 /* sink or branch descriptor */
1085 struct drm_dp_desc desc
;
1086 struct drm_dp_aux aux
;
1087 enum intel_display_power_domain aux_power_domain
;
1088 uint8_t train_set
[4];
1089 int panel_power_up_delay
;
1090 int panel_power_down_delay
;
1091 int panel_power_cycle_delay
;
1092 int backlight_on_delay
;
1093 int backlight_off_delay
;
1094 struct delayed_work panel_vdd_work
;
1095 bool want_panel_vdd
;
1096 unsigned long last_power_on
;
1097 unsigned long last_backlight_off
;
1098 ktime_t panel_power_off_time
;
1100 struct notifier_block edp_notifier
;
1103 * Pipe whose power sequencer is currently locked into
1104 * this port. Only relevant on VLV/CHV.
1108 * Pipe currently driving the port. Used for preventing
1109 * the use of the PPS for any pipe currentrly driving
1110 * external DP as that will mess things up on VLV.
1112 enum pipe active_pipe
;
1114 * Set if the sequencer may be reset due to a power transition,
1115 * requiring a reinitialization. Only relevant on BXT.
1118 struct edp_power_seq pps_delays
;
1120 bool can_mst
; /* this port supports mst */
1122 int active_mst_links
;
1123 /* connector directly attached - won't be use for modeset in mst world */
1124 struct intel_connector
*attached_connector
;
1126 /* mst connector list */
1127 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
1128 struct drm_dp_mst_topology_mgr mst_mgr
;
1130 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
1132 * This function returns the value we have to program the AUX_CTL
1133 * register with to kick off an AUX transaction.
1135 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
1138 uint32_t aux_clock_divider
);
1140 i915_reg_t (*aux_ch_ctl_reg
)(struct intel_dp
*dp
);
1141 i915_reg_t (*aux_ch_data_reg
)(struct intel_dp
*dp
, int index
);
1143 /* This is called before a link training is starterd */
1144 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
1146 /* Displayport compliance testing */
1147 struct intel_dp_compliance compliance
;
1150 struct intel_lspcon
{
1152 enum drm_lspcon_mode mode
;
1155 struct intel_digital_port
{
1156 struct intel_encoder base
;
1157 u32 saved_port_bits
;
1159 struct intel_hdmi hdmi
;
1160 struct intel_lspcon lspcon
;
1161 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
1162 bool release_cl2_override
;
1164 enum intel_display_power_domain ddi_io_power_domain
;
1166 void (*write_infoframe
)(struct drm_encoder
*encoder
,
1167 const struct intel_crtc_state
*crtc_state
,
1169 const void *frame
, ssize_t len
);
1170 void (*set_infoframes
)(struct drm_encoder
*encoder
,
1172 const struct intel_crtc_state
*crtc_state
,
1173 const struct drm_connector_state
*conn_state
);
1174 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
1175 const struct intel_crtc_state
*pipe_config
);
1178 struct intel_dp_mst_encoder
{
1179 struct intel_encoder base
;
1181 struct intel_digital_port
*primary
;
1182 struct intel_connector
*connector
;
1185 static inline enum dpio_channel
1186 vlv_dport_to_channel(struct intel_digital_port
*dport
)
1188 switch (dport
->base
.port
) {
1199 static inline enum dpio_phy
1200 vlv_dport_to_phy(struct intel_digital_port
*dport
)
1202 switch (dport
->base
.port
) {
1213 static inline enum dpio_channel
1214 vlv_pipe_to_channel(enum pipe pipe
)
1227 static inline struct intel_crtc
*
1228 intel_get_crtc_for_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1230 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1233 static inline struct intel_crtc
*
1234 intel_get_crtc_for_plane(struct drm_i915_private
*dev_priv
, enum i9xx_plane_id plane
)
1236 return dev_priv
->plane_to_crtc_mapping
[plane
];
1239 struct intel_load_detect_pipe
{
1240 struct drm_atomic_state
*restore_state
;
1243 static inline struct intel_encoder
*
1244 intel_attached_encoder(struct drm_connector
*connector
)
1246 return to_intel_connector(connector
)->encoder
;
1249 static inline struct intel_digital_port
*
1250 enc_to_dig_port(struct drm_encoder
*encoder
)
1252 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1254 switch (intel_encoder
->type
) {
1255 case INTEL_OUTPUT_DDI
:
1256 WARN_ON(!HAS_DDI(to_i915(encoder
->dev
)));
1257 case INTEL_OUTPUT_DP
:
1258 case INTEL_OUTPUT_EDP
:
1259 case INTEL_OUTPUT_HDMI
:
1260 return container_of(encoder
, struct intel_digital_port
,
1267 static inline struct intel_dp_mst_encoder
*
1268 enc_to_mst(struct drm_encoder
*encoder
)
1270 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1273 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1275 return &enc_to_dig_port(encoder
)->dp
;
1278 static inline struct intel_digital_port
*
1279 dp_to_dig_port(struct intel_dp
*intel_dp
)
1281 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1284 static inline struct intel_lspcon
*
1285 dp_to_lspcon(struct intel_dp
*intel_dp
)
1287 return &dp_to_dig_port(intel_dp
)->lspcon
;
1290 static inline struct intel_digital_port
*
1291 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1293 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1296 static inline struct intel_plane_state
*
1297 intel_atomic_get_new_plane_state(struct intel_atomic_state
*state
,
1298 struct intel_plane
*plane
)
1300 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state
->base
,
1304 static inline struct intel_crtc_state
*
1305 intel_atomic_get_old_crtc_state(struct intel_atomic_state
*state
,
1306 struct intel_crtc
*crtc
)
1308 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state
->base
,
1312 static inline struct intel_crtc_state
*
1313 intel_atomic_get_new_crtc_state(struct intel_atomic_state
*state
,
1314 struct intel_crtc
*crtc
)
1316 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state
->base
,
1320 /* intel_fifo_underrun.c */
1321 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1322 enum pipe pipe
, bool enable
);
1323 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1324 enum pipe pch_transcoder
,
1326 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1328 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1329 enum pipe pch_transcoder
);
1330 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1331 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1334 bool gen11_reset_one_iir(struct drm_i915_private
* const i915
,
1335 const unsigned int bank
,
1336 const unsigned int bit
);
1337 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1338 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1339 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1340 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1341 void gen11_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1342 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1343 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1344 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1346 static inline u32
gen6_sanitize_rps_pm_mask(const struct drm_i915_private
*i915
,
1349 return mask
& ~i915
->gt_pm
.rps
.pm_intrmsk_mbz
;
1352 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1353 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1354 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1357 * We only use drm_irq_uninstall() at unload and VT switch, so
1358 * this is the only thing we need to check.
1360 return dev_priv
->runtime_pm
.irqs_enabled
;
1363 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1364 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1366 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1368 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
);
1369 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1370 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1373 bool intel_crt_port_enabled(struct drm_i915_private
*dev_priv
,
1374 i915_reg_t adpa_reg
, enum pipe
*pipe
);
1375 void intel_crt_init(struct drm_i915_private
*dev_priv
);
1376 void intel_crt_reset(struct drm_encoder
*encoder
);
1379 void intel_ddi_fdi_post_disable(struct intel_encoder
*intel_encoder
,
1380 const struct intel_crtc_state
*old_crtc_state
,
1381 const struct drm_connector_state
*old_conn_state
);
1382 void hsw_fdi_link_train(struct intel_crtc
*crtc
,
1383 const struct intel_crtc_state
*crtc_state
);
1384 void intel_ddi_init(struct drm_i915_private
*dev_priv
, enum port port
);
1385 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1386 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state
*crtc_state
);
1387 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1388 enum transcoder cpu_transcoder
);
1389 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1390 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1391 void intel_ddi_set_pipe_settings(const struct intel_crtc_state
*crtc_state
);
1392 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1393 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1394 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1395 struct intel_crtc_state
*pipe_config
);
1397 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
*crtc_state
,
1399 void intel_ddi_compute_min_voltage_level(struct drm_i915_private
*dev_priv
,
1400 struct intel_crtc_state
*crtc_state
);
1401 u32
bxt_signal_levels(struct intel_dp
*intel_dp
);
1402 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1403 u8
intel_ddi_dp_voltage_max(struct intel_encoder
*encoder
);
1404 u8
intel_ddi_dp_pre_emphasis_max(struct intel_encoder
*encoder
,
1406 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder
*intel_encoder
,
1408 void icl_map_plls_to_ports(struct drm_crtc
*crtc
,
1409 struct intel_crtc_state
*crtc_state
,
1410 struct drm_atomic_state
*old_state
);
1411 void icl_unmap_plls_to_ports(struct drm_crtc
*crtc
,
1412 struct intel_crtc_state
*crtc_state
,
1413 struct drm_atomic_state
*old_state
);
1415 unsigned int intel_fb_align_height(const struct drm_framebuffer
*fb
,
1416 int plane
, unsigned int height
);
1419 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1420 void intel_audio_codec_enable(struct intel_encoder
*encoder
,
1421 const struct intel_crtc_state
*crtc_state
,
1422 const struct drm_connector_state
*conn_state
);
1423 void intel_audio_codec_disable(struct intel_encoder
*encoder
,
1424 const struct intel_crtc_state
*old_crtc_state
,
1425 const struct drm_connector_state
*old_conn_state
);
1426 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1427 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1428 void intel_audio_init(struct drm_i915_private
*dev_priv
);
1429 void intel_audio_deinit(struct drm_i915_private
*dev_priv
);
1432 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state
*crtc_state
);
1433 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1434 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1435 void cnl_init_cdclk(struct drm_i915_private
*dev_priv
);
1436 void cnl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1437 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1438 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1439 void icl_init_cdclk(struct drm_i915_private
*dev_priv
);
1440 void icl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1441 void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv
);
1442 void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
);
1443 void intel_update_cdclk(struct drm_i915_private
*dev_priv
);
1444 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1445 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state
*a
,
1446 const struct intel_cdclk_state
*b
);
1447 bool intel_cdclk_changed(const struct intel_cdclk_state
*a
,
1448 const struct intel_cdclk_state
*b
);
1449 void intel_set_cdclk(struct drm_i915_private
*dev_priv
,
1450 const struct intel_cdclk_state
*cdclk_state
);
1451 void intel_dump_cdclk_state(const struct intel_cdclk_state
*cdclk_state
,
1452 const char *context
);
1454 /* intel_display.c */
1455 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1456 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1457 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
);
1458 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1459 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
);
1460 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1461 const char *name
, u32 reg
, int ref_freq
);
1462 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
1463 const char *name
, u32 reg
);
1464 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
);
1465 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
);
1466 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1467 unsigned int intel_fb_xy_to_linear(int x
, int y
,
1468 const struct intel_plane_state
*state
,
1470 void intel_add_fb_offsets(int *x
, int *y
,
1471 const struct intel_plane_state
*state
, int plane
);
1472 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1473 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
);
1474 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1475 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1476 int intel_display_suspend(struct drm_device
*dev
);
1477 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
);
1478 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1479 int intel_connector_init(struct intel_connector
*);
1480 struct intel_connector
*intel_connector_alloc(void);
1481 void intel_connector_free(struct intel_connector
*connector
);
1482 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1483 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1484 struct intel_encoder
*encoder
);
1485 struct drm_display_mode
*
1486 intel_encoder_current_mode(struct intel_encoder
*encoder
);
1487 bool intel_port_is_tc(struct drm_i915_private
*dev_priv
, enum port port
);
1488 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
,
1491 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1492 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
1493 struct drm_file
*file_priv
);
1494 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1497 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1498 enum intel_output_type type
)
1500 return crtc_state
->output_types
& (1 << type
);
1503 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1505 return crtc_state
->output_types
&
1506 ((1 << INTEL_OUTPUT_DP
) |
1507 (1 << INTEL_OUTPUT_DP_MST
) |
1508 (1 << INTEL_OUTPUT_EDP
));
1511 intel_wait_for_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1513 drm_wait_one_vblank(&dev_priv
->drm
, pipe
);
1516 intel_wait_for_vblank_if_active(struct drm_i915_private
*dev_priv
, int pipe
)
1518 const struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1521 intel_wait_for_vblank(dev_priv
, pipe
);
1524 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1526 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1527 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1528 struct intel_digital_port
*dport
,
1529 unsigned int expected_mask
);
1530 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
1531 const struct drm_display_mode
*mode
,
1532 struct intel_load_detect_pipe
*old
,
1533 struct drm_modeset_acquire_ctx
*ctx
);
1534 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1535 struct intel_load_detect_pipe
*old
,
1536 struct drm_modeset_acquire_ctx
*ctx
);
1538 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
1539 unsigned int rotation
,
1541 unsigned long *out_flags
);
1542 void intel_unpin_fb_vma(struct i915_vma
*vma
, unsigned long flags
);
1543 struct drm_framebuffer
*
1544 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
1545 struct drm_mode_fb_cmd2
*mode_cmd
);
1546 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1547 struct drm_plane_state
*new_state
);
1548 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1549 struct drm_plane_state
*old_state
);
1550 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1551 const struct drm_plane_state
*state
,
1552 struct drm_property
*property
,
1554 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1555 struct drm_plane_state
*state
,
1556 struct drm_property
*property
,
1558 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
1559 struct drm_crtc_state
*crtc_state
,
1560 const struct intel_plane_state
*old_plane_state
,
1561 struct drm_plane_state
*plane_state
);
1563 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1566 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1567 const struct dpll
*dpll
);
1568 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1569 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1571 /* modesetting asserts */
1572 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1574 void assert_pll(struct drm_i915_private
*dev_priv
,
1575 enum pipe pipe
, bool state
);
1576 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1577 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1578 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1579 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1580 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1581 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1582 enum pipe pipe
, bool state
);
1583 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1584 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1585 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1586 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1587 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1588 u32
intel_compute_tile_offset(int *x
, int *y
,
1589 const struct intel_plane_state
*state
, int plane
);
1590 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1591 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1592 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1593 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1594 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1595 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1596 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1597 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1598 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1599 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1600 struct intel_crtc_state
*pipe_config
);
1601 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1602 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1603 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1604 struct dpll
*best_clock
);
1605 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1607 bool intel_crtc_active(struct intel_crtc
*crtc
);
1608 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state
*crtc_state
);
1609 void hsw_enable_ips(const struct intel_crtc_state
*crtc_state
);
1610 void hsw_disable_ips(const struct intel_crtc_state
*crtc_state
);
1611 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
);
1612 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1613 struct intel_crtc_state
*pipe_config
);
1614 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
1615 struct intel_crtc_state
*crtc_state
);
1617 u16
skl_scaler_calc_phase(int sub
, bool chroma_center
);
1618 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1619 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
1620 uint32_t pixel_format
);
1622 static inline u32
intel_plane_ggtt_offset(const struct intel_plane_state
*state
)
1624 return i915_ggtt_offset(state
->vma
);
1627 u32
glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state
,
1628 const struct intel_plane_state
*plane_state
);
1629 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
1630 const struct intel_plane_state
*plane_state
);
1631 u32
glk_color_ctl(const struct intel_plane_state
*plane_state
);
1632 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
1633 unsigned int rotation
);
1634 int skl_check_plane_surface(const struct intel_crtc_state
*crtc_state
,
1635 struct intel_plane_state
*plane_state
);
1636 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
);
1637 int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
);
1640 void intel_csr_ucode_init(struct drm_i915_private
*);
1641 void intel_csr_load_program(struct drm_i915_private
*);
1642 void intel_csr_ucode_fini(struct drm_i915_private
*);
1643 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1644 void intel_csr_ucode_resume(struct drm_i915_private
*);
1647 bool intel_dp_port_enabled(struct drm_i915_private
*dev_priv
,
1648 i915_reg_t dp_reg
, enum port port
,
1650 bool intel_dp_init(struct drm_i915_private
*dev_priv
, i915_reg_t output_reg
,
1652 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1653 struct intel_connector
*intel_connector
);
1654 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1655 int link_rate
, uint8_t lane_count
,
1657 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
1658 int link_rate
, uint8_t lane_count
);
1659 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1660 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1661 int intel_dp_retrain_link(struct intel_encoder
*encoder
,
1662 struct drm_modeset_acquire_ctx
*ctx
);
1663 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1664 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1665 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1666 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1667 int intel_dp_sink_crc(struct intel_dp
*intel_dp
,
1668 struct intel_crtc_state
*crtc_state
, u8
*crc
);
1669 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1670 struct intel_crtc_state
*pipe_config
,
1671 struct drm_connector_state
*conn_state
);
1672 bool intel_dp_is_edp(struct intel_dp
*intel_dp
);
1673 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
1674 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1676 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
1677 const struct drm_connector_state
*conn_state
);
1678 void intel_edp_backlight_off(const struct drm_connector_state
*conn_state
);
1679 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1680 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1681 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1682 void intel_dp_mst_suspend(struct drm_device
*dev
);
1683 void intel_dp_mst_resume(struct drm_device
*dev
);
1684 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1685 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
);
1686 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1687 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1688 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1689 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1690 void intel_plane_destroy(struct drm_plane
*plane
);
1691 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
1692 const struct intel_crtc_state
*crtc_state
);
1693 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
1694 const struct intel_crtc_state
*crtc_state
);
1695 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
1696 unsigned int frontbuffer_bits
);
1697 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
1698 unsigned int frontbuffer_bits
);
1701 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1702 uint8_t dp_train_pat
);
1704 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1705 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1707 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1709 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1710 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1711 uint8_t *link_bw
, uint8_t *rate_select
);
1712 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1713 bool intel_dp_source_supports_hbr3(struct intel_dp
*intel_dp
);
1715 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1717 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1719 return ~((1 << lane_count
) - 1) & 0xf;
1722 bool intel_dp_read_dpcd(struct intel_dp
*intel_dp
);
1723 int intel_dp_link_required(int pixel_clock
, int bpp
);
1724 int intel_dp_max_data_rate(int max_link_clock
, int max_lanes
);
1725 bool intel_digital_port_connected(struct intel_encoder
*encoder
);
1727 /* intel_dp_aux_backlight.c */
1728 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1730 /* intel_dp_mst.c */
1731 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1732 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1734 void intel_dsi_init(struct drm_i915_private
*dev_priv
);
1736 /* intel_dsi_dcs_backlight.c */
1737 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1740 void intel_dvo_init(struct drm_i915_private
*dev_priv
);
1741 /* intel_hotplug.c */
1742 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1743 bool intel_encoder_hotplug(struct intel_encoder
*encoder
,
1744 struct intel_connector
*connector
);
1746 /* legacy fbdev emulation in intel_fbdev.c */
1747 #ifdef CONFIG_DRM_FBDEV_EMULATION
1748 extern int intel_fbdev_init(struct drm_device
*dev
);
1749 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1750 extern void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
);
1751 extern void intel_fbdev_fini(struct drm_i915_private
*dev_priv
);
1752 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1753 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1754 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1756 static inline int intel_fbdev_init(struct drm_device
*dev
)
1761 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1765 static inline void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
)
1769 static inline void intel_fbdev_fini(struct drm_i915_private
*dev_priv
)
1773 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1777 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
1781 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1787 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1788 struct intel_atomic_state
*state
);
1789 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1790 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
1791 struct intel_crtc_state
*crtc_state
,
1792 struct intel_plane_state
*plane_state
);
1793 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1794 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1795 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1796 void intel_fbc_enable(struct intel_crtc
*crtc
,
1797 struct intel_crtc_state
*crtc_state
,
1798 struct intel_plane_state
*plane_state
);
1799 void intel_fbc_disable(struct intel_crtc
*crtc
);
1800 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1801 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1802 unsigned int frontbuffer_bits
,
1803 enum fb_op_origin origin
);
1804 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1805 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1806 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1807 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
);
1808 int intel_fbc_reset_underrun(struct drm_i915_private
*dev_priv
);
1811 void intel_hdmi_init(struct drm_i915_private
*dev_priv
, i915_reg_t hdmi_reg
,
1813 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1814 struct intel_connector
*intel_connector
);
1815 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1816 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1817 struct intel_crtc_state
*pipe_config
,
1818 struct drm_connector_state
*conn_state
);
1819 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder
*encoder
,
1820 struct drm_connector
*connector
,
1821 bool high_tmds_clock_ratio
,
1823 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
1824 void intel_infoframe_init(struct intel_digital_port
*intel_dig_port
);
1828 bool intel_lvds_port_enabled(struct drm_i915_private
*dev_priv
,
1829 i915_reg_t lvds_reg
, enum pipe
*pipe
);
1830 void intel_lvds_init(struct drm_i915_private
*dev_priv
);
1831 struct intel_encoder
*intel_get_lvds_encoder(struct drm_device
*dev
);
1832 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1836 int intel_connector_update_modes(struct drm_connector
*connector
,
1838 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1839 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1840 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1841 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1844 /* intel_overlay.c */
1845 void intel_setup_overlay(struct drm_i915_private
*dev_priv
);
1846 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
);
1847 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1848 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1849 struct drm_file
*file_priv
);
1850 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1851 struct drm_file
*file_priv
);
1852 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1856 int intel_panel_init(struct intel_panel
*panel
,
1857 struct drm_display_mode
*fixed_mode
,
1858 struct drm_display_mode
*downclock_mode
);
1859 void intel_panel_fini(struct intel_panel
*panel
);
1860 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1861 struct drm_display_mode
*adjusted_mode
);
1862 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1863 struct intel_crtc_state
*pipe_config
,
1865 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1866 struct intel_crtc_state
*pipe_config
,
1868 void intel_panel_set_backlight_acpi(const struct drm_connector_state
*conn_state
,
1869 u32 level
, u32 max
);
1870 int intel_panel_setup_backlight(struct drm_connector
*connector
,
1872 void intel_panel_enable_backlight(const struct intel_crtc_state
*crtc_state
,
1873 const struct drm_connector_state
*conn_state
);
1874 void intel_panel_disable_backlight(const struct drm_connector_state
*old_conn_state
);
1875 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1876 enum drm_connector_status
intel_panel_detect(struct drm_i915_private
*dev_priv
);
1877 extern struct drm_display_mode
*intel_find_panel_downclock(
1878 struct drm_i915_private
*dev_priv
,
1879 struct drm_display_mode
*fixed_mode
,
1880 struct drm_connector
*connector
);
1882 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1883 int intel_backlight_device_register(struct intel_connector
*connector
);
1884 void intel_backlight_device_unregister(struct intel_connector
*connector
);
1885 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1886 static inline int intel_backlight_device_register(struct intel_connector
*connector
)
1890 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
1893 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1896 void intel_hdcp_atomic_check(struct drm_connector
*connector
,
1897 struct drm_connector_state
*old_state
,
1898 struct drm_connector_state
*new_state
);
1899 int intel_hdcp_init(struct intel_connector
*connector
,
1900 const struct intel_hdcp_shim
*hdcp_shim
);
1901 int intel_hdcp_enable(struct intel_connector
*connector
);
1902 int intel_hdcp_disable(struct intel_connector
*connector
);
1903 int intel_hdcp_check_link(struct intel_connector
*connector
);
1904 bool is_hdcp_supported(struct drm_i915_private
*dev_priv
, enum port port
);
1907 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1908 void intel_psr_init_dpcd(struct intel_dp
*intel_dp
);
1909 void intel_psr_enable(struct intel_dp
*intel_dp
,
1910 const struct intel_crtc_state
*crtc_state
);
1911 void intel_psr_disable(struct intel_dp
*intel_dp
,
1912 const struct intel_crtc_state
*old_crtc_state
);
1913 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
1914 unsigned frontbuffer_bits
,
1915 enum fb_op_origin origin
);
1916 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
1917 unsigned frontbuffer_bits
,
1918 enum fb_op_origin origin
);
1919 void intel_psr_init(struct drm_i915_private
*dev_priv
);
1920 void intel_psr_compute_config(struct intel_dp
*intel_dp
,
1921 struct intel_crtc_state
*crtc_state
);
1922 void intel_psr_irq_control(struct drm_i915_private
*dev_priv
, bool debug
);
1923 void intel_psr_irq_handler(struct drm_i915_private
*dev_priv
, u32 psr_iir
);
1925 /* intel_runtime_pm.c */
1926 int intel_power_domains_init(struct drm_i915_private
*);
1927 void intel_power_domains_fini(struct drm_i915_private
*);
1928 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1929 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1930 void intel_power_domains_verify_state(struct drm_i915_private
*dev_priv
);
1931 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1932 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1933 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1935 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1937 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1938 enum intel_display_power_domain domain
);
1939 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1940 enum intel_display_power_domain domain
);
1941 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1942 enum intel_display_power_domain domain
);
1943 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1944 enum intel_display_power_domain domain
);
1945 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1946 enum intel_display_power_domain domain
);
1947 void icl_dbuf_slices_update(struct drm_i915_private
*dev_priv
,
1951 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1953 WARN_ONCE(dev_priv
->runtime_pm
.suspended
,
1954 "Device suspended during HW access\n");
1958 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1960 assert_rpm_device_not_suspended(dev_priv
);
1961 WARN_ONCE(!atomic_read(&dev_priv
->runtime_pm
.wakeref_count
),
1962 "RPM wakelock ref not held during HW access");
1966 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1967 * @dev_priv: i915 device instance
1969 * This function disable asserts that check if we hold an RPM wakelock
1970 * reference, while keeping the device-not-suspended checks still enabled.
1971 * It's meant to be used only in special circumstances where our rule about
1972 * the wakelock refcount wrt. the device power state doesn't hold. According
1973 * to this rule at any point where we access the HW or want to keep the HW in
1974 * an active state we must hold an RPM wakelock reference acquired via one of
1975 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1976 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1977 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1978 * users should avoid using this function.
1980 * Any calls to this function must have a symmetric call to
1981 * enable_rpm_wakeref_asserts().
1984 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1986 atomic_inc(&dev_priv
->runtime_pm
.wakeref_count
);
1990 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1991 * @dev_priv: i915 device instance
1993 * This function re-enables the RPM assert checks after disabling them with
1994 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1995 * circumstances otherwise its use should be avoided.
1997 * Any calls to this function must have a symmetric call to
1998 * disable_rpm_wakeref_asserts().
2001 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
2003 atomic_dec(&dev_priv
->runtime_pm
.wakeref_count
);
2006 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
2007 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
2008 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
2009 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
2011 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
2013 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
2014 bool override
, unsigned int mask
);
2015 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
2016 enum dpio_channel ch
, bool override
);
2020 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
);
2021 void intel_suspend_hw(struct drm_i915_private
*dev_priv
);
2022 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
);
2023 void intel_update_watermarks(struct intel_crtc
*crtc
);
2024 void intel_init_pm(struct drm_i915_private
*dev_priv
);
2025 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
2026 void intel_pm_setup(struct drm_i915_private
*dev_priv
);
2027 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
2028 void intel_gpu_ips_teardown(void);
2029 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
2030 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
2031 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
);
2032 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
2033 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
2034 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
);
2035 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
2036 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
2037 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
2038 void gen6_rps_boost(struct i915_request
*rq
, struct intel_rps_client
*rps
);
2039 void g4x_wm_get_hw_state(struct drm_device
*dev
);
2040 void vlv_wm_get_hw_state(struct drm_device
*dev
);
2041 void ilk_wm_get_hw_state(struct drm_device
*dev
);
2042 void skl_wm_get_hw_state(struct drm_device
*dev
);
2043 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2044 struct skl_ddb_allocation
*ddb
/* out */);
2045 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
2046 struct skl_pipe_wm
*out
);
2047 void g4x_wm_sanitize(struct drm_i915_private
*dev_priv
);
2048 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
);
2049 bool intel_can_enable_sagv(struct drm_atomic_state
*state
);
2050 int intel_enable_sagv(struct drm_i915_private
*dev_priv
);
2051 int intel_disable_sagv(struct drm_i915_private
*dev_priv
);
2052 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
2053 const struct skl_wm_level
*l2
);
2054 bool skl_ddb_allocation_overlaps(struct drm_i915_private
*dev_priv
,
2055 const struct skl_ddb_entry
**entries
,
2056 const struct skl_ddb_entry
*ddb
,
2058 bool ilk_disable_lp_wm(struct drm_device
*dev
);
2059 int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc
,
2060 struct intel_crtc_state
*cstate
);
2061 void intel_init_ipc(struct drm_i915_private
*dev_priv
);
2062 void intel_enable_ipc(struct drm_i915_private
*dev_priv
);
2065 bool intel_sdvo_port_enabled(struct drm_i915_private
*dev_priv
,
2066 i915_reg_t sdvo_reg
, enum pipe
*pipe
);
2067 bool intel_sdvo_init(struct drm_i915_private
*dev_priv
,
2068 i915_reg_t reg
, enum port port
);
2071 /* intel_sprite.c */
2072 bool intel_format_is_yuv(u32 format
);
2073 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
2075 struct intel_plane
*intel_sprite_plane_create(struct drm_i915_private
*dev_priv
,
2076 enum pipe pipe
, int plane
);
2077 int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev
, void *data
,
2078 struct drm_file
*file_priv
);
2079 void intel_pipe_update_start(const struct intel_crtc_state
*new_crtc_state
);
2080 void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state
);
2081 void skl_update_plane(struct intel_plane
*plane
,
2082 const struct intel_crtc_state
*crtc_state
,
2083 const struct intel_plane_state
*plane_state
);
2084 void skl_disable_plane(struct intel_plane
*plane
, struct intel_crtc
*crtc
);
2085 bool skl_plane_get_hw_state(struct intel_plane
*plane
, enum pipe
*pipe
);
2086 bool skl_plane_has_ccs(struct drm_i915_private
*dev_priv
,
2087 enum pipe pipe
, enum plane_id plane_id
);
2088 bool intel_format_is_yuv(uint32_t format
);
2089 bool skl_plane_has_planar(struct drm_i915_private
*dev_priv
,
2090 enum pipe pipe
, enum plane_id plane_id
);
2093 void intel_tv_init(struct drm_i915_private
*dev_priv
);
2095 /* intel_atomic.c */
2096 int intel_digital_connector_atomic_get_property(struct drm_connector
*connector
,
2097 const struct drm_connector_state
*state
,
2098 struct drm_property
*property
,
2100 int intel_digital_connector_atomic_set_property(struct drm_connector
*connector
,
2101 struct drm_connector_state
*state
,
2102 struct drm_property
*property
,
2104 int intel_digital_connector_atomic_check(struct drm_connector
*conn
,
2105 struct drm_connector_state
*new_state
);
2106 struct drm_connector_state
*
2107 intel_digital_connector_duplicate_state(struct drm_connector
*connector
);
2109 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
2110 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
2111 struct drm_crtc_state
*state
);
2112 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
2113 void intel_atomic_state_clear(struct drm_atomic_state
*);
2115 static inline struct intel_crtc_state
*
2116 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
2117 struct intel_crtc
*crtc
)
2119 struct drm_crtc_state
*crtc_state
;
2120 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
2121 if (IS_ERR(crtc_state
))
2122 return ERR_CAST(crtc_state
);
2124 return to_intel_crtc_state(crtc_state
);
2127 int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv
,
2128 struct intel_crtc
*intel_crtc
,
2129 struct intel_crtc_state
*crtc_state
);
2131 /* intel_atomic_plane.c */
2132 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
2133 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
2134 void intel_plane_destroy_state(struct drm_plane
*plane
,
2135 struct drm_plane_state
*state
);
2136 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
2137 int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state
,
2138 struct intel_crtc_state
*crtc_state
,
2139 const struct intel_plane_state
*old_plane_state
,
2140 struct intel_plane_state
*intel_state
);
2143 void intel_color_init(struct drm_crtc
*crtc
);
2144 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
2145 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
2146 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
2148 /* intel_lspcon.c */
2149 bool lspcon_init(struct intel_digital_port
*intel_dig_port
);
2150 void lspcon_resume(struct intel_lspcon
*lspcon
);
2151 void lspcon_wait_pcon_mode(struct intel_lspcon
*lspcon
);
2153 /* intel_pipe_crc.c */
2154 int intel_pipe_crc_create(struct drm_minor
*minor
);
2155 #ifdef CONFIG_DEBUG_FS
2156 int intel_crtc_set_crc_source(struct drm_crtc
*crtc
, const char *source_name
,
2157 size_t *values_cnt
);
2158 void intel_crtc_disable_pipe_crc(struct intel_crtc
*crtc
);
2159 void intel_crtc_enable_pipe_crc(struct intel_crtc
*crtc
);
2161 #define intel_crtc_set_crc_source NULL
2162 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc
*crtc
)
2166 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc
*crtc
)
2170 extern const struct file_operations i915_display_crc_ctl_fops
;
2171 #endif /* __INTEL_DRV_H__ */