drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__;                                                      \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 if (COND) {                                             \
  59                         ret__ = 0;                                      \
  60                         break;                                          \
  61                 }                                                       \
  62                 if (expired__) {                                        \
  63                         ret__ = -ETIMEDOUT;                             \
  64                         break;                                          \
  65                 }                                                       \
  66                 if ((W) && drm_can_sleep()) {                           \
  67                         usleep_range((W), (W)*2);                       \
  68                 } else {                                                \
  69                         cpu_relax();                                    \
  70                 }                                                       \
  71         }                                                               \
  72         ret__;                                                          \
  73 })
  74
  75 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  76
  77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  80 #else
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  82 #endif
  83
  84 #define _wait_for_atomic(COND, US, ATOMIC) \
  85 ({ \
  86         int cpu, ret, timeout = (US) * 1000; \
  87         u64 base; \
  88         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  89         BUILD_BUG_ON((US) > 50000); \
  90         if (!(ATOMIC)) { \
  91                 preempt_disable(); \
  92                 cpu = smp_processor_id(); \
  93         } \
  94         base = local_clock(); \
  95         for (;;) { \
  96                 u64 now = local_clock(); \
  97                 if (!(ATOMIC)) \
  98                         preempt_enable(); \
  99                 if (COND) { \
 100                         ret = 0; \
 101                         break; \
 102                 } \
 103                 if (now - base >= timeout) { \
 104                         ret = -ETIMEDOUT; \
 105                         break; \
 106                 } \
 107                 cpu_relax(); \
 108                 if (!(ATOMIC)) { \
 109                         preempt_disable(); \
 110                         if (unlikely(cpu != smp_processor_id())) { \
 111                                 timeout -= now - base; \
 112                                 cpu = smp_processor_id(); \
 113                                 base = local_clock(); \
 114                         } \
 115                 } \
 116         } \
 117         ret; \
 118 })
 119
 120 #define wait_for_us(COND, US) \
 121 ({ \
 122         int ret__; \
 123         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 124         if ((US) > 10) \
 125                 ret__ = _wait_for((COND), (US), 10); \
 126         else \
 127                 ret__ = _wait_for_atomic((COND), (US), 0); \
 128         ret__; \
 129 })
 130
 131 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 132 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 133
 134 #define KHz(x) (1000 * (x))
 135 #define MHz(x) KHz(1000 * (x))
 136
 137 /*
 138  * Display related stuff
 139  */
 140
 141 /* store information about an Ixxx DVO */
 142 /* The i830->i865 use multiple DVOs with multiple i2cs */
 143 /* the i915, i945 have a single sDVO i2c bus - which is different */
 144 #define MAX_OUTPUTS 6
 145 /* maximum connectors per crtcs in the mode set */
 146
 147 /* Maximum cursor sizes */
 148 #define GEN2_CURSOR_WIDTH 64
 149 #define GEN2_CURSOR_HEIGHT 64
 150 #define MAX_CURSOR_WIDTH 256
 151 #define MAX_CURSOR_HEIGHT 256
 152
 153 #define INTEL_I2C_BUS_DVO 1
 154 #define INTEL_I2C_BUS_SDVO 2
 155
 156 /* these are outputs from the chip - integrated only
 157    external chips are via DVO or SDVO output */
 158 enum intel_output_type {
 159         INTEL_OUTPUT_UNUSED = 0,
 160         INTEL_OUTPUT_ANALOG = 1,
 161         INTEL_OUTPUT_DVO = 2,
 162         INTEL_OUTPUT_SDVO = 3,
 163         INTEL_OUTPUT_LVDS = 4,
 164         INTEL_OUTPUT_TVOUT = 5,
 165         INTEL_OUTPUT_HDMI = 6,
 166         INTEL_OUTPUT_DP = 7,
 167         INTEL_OUTPUT_EDP = 8,
 168         INTEL_OUTPUT_DSI = 9,
 169         INTEL_OUTPUT_UNKNOWN = 10,
 170         INTEL_OUTPUT_DP_MST = 11,
 171 };
 172
 173 #define INTEL_DVO_CHIP_NONE 0
 174 #define INTEL_DVO_CHIP_LVDS 1
 175 #define INTEL_DVO_CHIP_TMDS 2
 176 #define INTEL_DVO_CHIP_TVOUT 4
 177
 178 #define INTEL_DSI_VIDEO_MODE    0
 179 #define INTEL_DSI_COMMAND_MODE  1
 180
 181 struct intel_framebuffer {
 182         struct drm_framebuffer base;
 183         struct drm_i915_gem_object *obj;
 184         struct intel_rotation_info rot_info;
 185
 186         /* for each plane in the normal GTT view */
 187         struct {
 188                 unsigned int x, y;
 189         } normal[2];
 190         /* for each plane in the rotated GTT view */
 191         struct {
 192                 unsigned int x, y;
 193                 unsigned int pitch; /* pixels */
 194         } rotated[2];
 195 };
 196
 197 struct intel_fbdev {
 198         struct drm_fb_helper helper;
 199         struct intel_framebuffer *fb;
 200         struct i915_vma *vma;
 201         async_cookie_t cookie;
 202         int preferred_bpp;
 203 };
 204
 205 struct intel_encoder {
 206         struct drm_encoder base;
 207
 208         enum intel_output_type type;
 209         enum port port;
 210         unsigned int cloneable;
 211         void (*hot_plug)(struct intel_encoder *);
 212         bool (*compute_config)(struct intel_encoder *,
 213                                struct intel_crtc_state *,
 214                                struct drm_connector_state *);
 215         void (*pre_pll_enable)(struct intel_encoder *,
 216                                struct intel_crtc_state *,
 217                                struct drm_connector_state *);
 218         void (*pre_enable)(struct intel_encoder *,
 219                            struct intel_crtc_state *,
 220                            struct drm_connector_state *);
 221         void (*enable)(struct intel_encoder *,
 222                        struct intel_crtc_state *,
 223                        struct drm_connector_state *);
 224         void (*disable)(struct intel_encoder *,
 225                         struct intel_crtc_state *,
 226                         struct drm_connector_state *);
 227         void (*post_disable)(struct intel_encoder *,
 228                              struct intel_crtc_state *,
 229                              struct drm_connector_state *);
 230         void (*post_pll_disable)(struct intel_encoder *,
 231                                  struct intel_crtc_state *,
 232                                  struct drm_connector_state *);
 233         /* Read out the current hw state of this connector, returning true if
 234          * the encoder is active. If the encoder is enabled it also set the pipe
 235          * it is connected to in the pipe parameter. */
 236         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 237         /* Reconstructs the equivalent mode flags for the current hardware
 238          * state. This must be called _after_ display->get_pipe_config has
 239          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 240          * be set correctly before calling this function. */
 241         void (*get_config)(struct intel_encoder *,
 242                            struct intel_crtc_state *pipe_config);
 243         /*
 244          * Called during system suspend after all pending requests for the
 245          * encoder are flushed (for example for DP AUX transactions) and
 246          * device interrupts are disabled.
 247          */
 248         void (*suspend)(struct intel_encoder *);
 249         int crtc_mask;
 250         enum hpd_pin hpd_pin;
 251         /* for communication with audio component; protected by av_mutex */
 252         const struct drm_connector *audio_connector;
 253 };
 254
 255 struct intel_panel {
 256         struct drm_display_mode *fixed_mode;
 257         struct drm_display_mode *downclock_mode;
 258         int fitting_mode;
 259
 260         /* backlight */
 261         struct {
 262                 bool present;
 263                 u32 level;
 264                 u32 min;
 265                 u32 max;
 266                 bool enabled;
 267                 bool combination_mode;  /* gen 2/4 only */
 268                 bool active_low_pwm;
 269                 bool alternate_pwm_increment;   /* lpt+ */
 270
 271                 /* PWM chip */
 272                 bool util_pin_active_low;       /* bxt+ */
 273                 u8 controller;          /* bxt+ only */
 274                 struct pwm_device *pwm;
 275
 276                 struct backlight_device *device;
 277
 278                 /* Connector and platform specific backlight functions */
 279                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 280                 uint32_t (*get)(struct intel_connector *connector);
 281                 void (*set)(struct intel_connector *connector, uint32_t level);
 282                 void (*disable)(struct intel_connector *connector);
 283                 void (*enable)(struct intel_connector *connector);
 284                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 285                                       uint32_t hz);
 286                 void (*power)(struct intel_connector *, bool enable);
 287         } backlight;
 288 };
 289
 290 struct intel_connector {
 291         struct drm_connector base;
 292         /*
 293          * The fixed encoder this connector is connected to.
 294          */
 295         struct intel_encoder *encoder;
 296
 297         /* ACPI device id for ACPI and driver cooperation */
 298         u32 acpi_device_id;
 299
 300         /* Reads out the current hw, returning true if the connector is enabled
 301          * and active (i.e. dpms ON state). */
 302         bool (*get_hw_state)(struct intel_connector *);
 303
 304         /* Panel info for eDP and LVDS */
 305         struct intel_panel panel;
 306
 307         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 308         struct edid *edid;
 309         struct edid *detect_edid;
 310
 311         /* since POLL and HPD connectors may use the same HPD line keep the native
 312            state of connector->polled in case hotplug storm detection changes it */
 313         u8 polled;
 314
 315         void *port; /* store this opaque as its illegal to dereference it */
 316
 317         struct intel_dp *mst_port;
 318 };
 319
 320 struct dpll {
 321         /* given values */
 322         int n;
 323         int m1, m2;
 324         int p1, p2;
 325         /* derived values */
 326         int     dot;
 327         int     vco;
 328         int     m;
 329         int     p;
 330 };
 331
 332 struct intel_atomic_state {
 333         struct drm_atomic_state base;
 334
 335         unsigned int cdclk;
 336
 337         /*
 338          * Calculated device cdclk, can be different from cdclk
 339          * only when all crtc's are DPMS off.
 340          */
 341         unsigned int dev_cdclk;
 342
 343         bool dpll_set, modeset;
 344
 345         /*
 346          * Does this transaction change the pipes that are active?  This mask
 347          * tracks which CRTC's have changed their active state at the end of
 348          * the transaction (not counting the temporary disable during modesets).
 349          * This mask should only be non-zero when intel_state->modeset is true,
 350          * but the converse is not necessarily true; simply changing a mode may
 351          * not flip the final active status of any CRTC's
 352          */
 353         unsigned int active_pipe_changes;
 354
 355         unsigned int active_crtcs;
 356         unsigned int min_pixclk[I915_MAX_PIPES];
 357
 358         /* SKL/KBL Only */
 359         unsigned int cdclk_pll_vco;
 360
 361         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 362
 363         /*
 364          * Current watermarks can't be trusted during hardware readout, so
 365          * don't bother calculating intermediate watermarks.
 366          */
 367         bool skip_intermediate_wm;
 368
 369         /* Gen9+ only */
 370         struct skl_wm_values wm_results;
 371
 372         struct i915_sw_fence commit_ready;
 373 };
 374
 375 struct intel_plane_state {
 376         struct drm_plane_state base;
 377         struct drm_rect clip;
 378
 379         struct {
 380                 u32 offset;
 381                 int x, y;
 382         } main;
 383         struct {
 384                 u32 offset;
 385                 int x, y;
 386         } aux;
 387
 388         /*
 389          * scaler_id
 390          *    = -1 : not using a scaler
 391          *    >=  0 : using a scalers
 392          *
 393          * plane requiring a scaler:
 394          *   - During check_plane, its bit is set in
 395          *     crtc_state->scaler_state.scaler_users by calling helper function
 396          *     update_scaler_plane.
 397          *   - scaler_id indicates the scaler it got assigned.
 398          *
 399          * plane doesn't require a scaler:
 400          *   - this can happen when scaling is no more required or plane simply
 401          *     got disabled.
 402          *   - During check_plane, corresponding bit is reset in
 403          *     crtc_state->scaler_state.scaler_users by calling helper function
 404          *     update_scaler_plane.
 405          */
 406         int scaler_id;
 407
 408         struct drm_intel_sprite_colorkey ckey;
 409 };
 410
 411 struct intel_initial_plane_config {
 412         struct intel_framebuffer *fb;
 413         unsigned int tiling;
 414         int size;
 415         u32 base;
 416 };
 417
 418 #define SKL_MIN_SRC_W 8
 419 #define SKL_MAX_SRC_W 4096
 420 #define SKL_MIN_SRC_H 8
 421 #define SKL_MAX_SRC_H 4096
 422 #define SKL_MIN_DST_W 8
 423 #define SKL_MAX_DST_W 4096
 424 #define SKL_MIN_DST_H 8
 425 #define SKL_MAX_DST_H 4096
 426
 427 struct intel_scaler {
 428         int in_use;
 429         uint32_t mode;
 430 };
 431
 432 struct intel_crtc_scaler_state {
 433 #define SKL_NUM_SCALERS 2
 434         struct intel_scaler scalers[SKL_NUM_SCALERS];
 435
 436         /*
 437          * scaler_users: keeps track of users requesting scalers on this crtc.
 438          *
 439          *     If a bit is set, a user is using a scaler.
 440          *     Here user can be a plane or crtc as defined below:
 441          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 442          *       bit 31    - crtc
 443          *
 444          * Instead of creating a new index to cover planes and crtc, using
 445          * existing drm_plane_index for planes which is well less than 31
 446          * planes and bit 31 for crtc. This should be fine to cover all
 447          * our platforms.
 448          *
 449          * intel_atomic_setup_scalers will setup available scalers to users
 450          * requesting scalers. It will gracefully fail if request exceeds
 451          * avilability.
 452          */
 453 #define SKL_CRTC_INDEX 31
 454         unsigned scaler_users;
 455
 456         /* scaler used by crtc for panel fitting purpose */
 457         int scaler_id;
 458 };
 459
 460 /* drm_mode->private_flags */
 461 #define I915_MODE_FLAG_INHERITED 1
 462
 463 struct intel_pipe_wm {
 464         struct intel_wm_level wm[5];
 465         struct intel_wm_level raw_wm[5];
 466         uint32_t linetime;
 467         bool fbc_wm_enabled;
 468         bool pipe_enabled;
 469         bool sprites_enabled;
 470         bool sprites_scaled;
 471 };
 472
 473 struct skl_plane_wm {
 474         struct skl_wm_level wm[8];
 475         struct skl_wm_level trans_wm;
 476 };
 477
 478 struct skl_pipe_wm {
 479         struct skl_plane_wm planes[I915_MAX_PLANES];
 480         uint32_t linetime;
 481 };
 482
 483 struct intel_crtc_wm_state {
 484         union {
 485                 struct {
 486                         /*
 487                          * Intermediate watermarks; these can be
 488                          * programmed immediately since they satisfy
 489                          * both the current configuration we're
 490                          * switching away from and the new
 491                          * configuration we're switching to.
 492                          */
 493                         struct intel_pipe_wm intermediate;
 494
 495                         /*
 496                          * Optimal watermarks, programmed post-vblank
 497                          * when this state is committed.
 498                          */
 499                         struct intel_pipe_wm optimal;
 500                 } ilk;
 501
 502                 struct {
 503                         /* gen9+ only needs 1-step wm programming */
 504                         struct skl_pipe_wm optimal;
 505                         struct skl_ddb_entry ddb;
 506                 } skl;
 507         };
 508
 509         /*
 510          * Platforms with two-step watermark programming will need to
 511          * update watermark programming post-vblank to switch from the
 512          * safe intermediate watermarks to the optimal final
 513          * watermarks.
 514          */
 515         bool need_postvbl_update;
 516 };
 517
 518 struct intel_crtc_state {
 519         struct drm_crtc_state base;
 520
 521         /**
 522          * quirks - bitfield with hw state readout quirks
 523          *
 524          * For various reasons the hw state readout code might not be able to
 525          * completely faithfully read out the current state. These cases are
 526          * tracked with quirk flags so that fastboot and state checker can act
 527          * accordingly.
 528          */
 529 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 530         unsigned long quirks;
 531
 532         unsigned fb_bits; /* framebuffers to flip */
 533         bool update_pipe; /* can a fast modeset be performed? */
 534         bool disable_cxsr;
 535         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 536         bool fb_changed; /* fb on any of the planes is changed */
 537
 538         /* Pipe source size (ie. panel fitter input size)
 539          * All planes will be positioned inside this space,
 540          * and get clipped at the edges. */
 541         int pipe_src_w, pipe_src_h;
 542
 543         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 544          * between pch encoders and cpu encoders. */
 545         bool has_pch_encoder;
 546
 547         /* Are we sending infoframes on the attached port */
 548         bool has_infoframe;
 549
 550         /* CPU Transcoder for the pipe. Currently this can only differ from the
 551          * pipe on Haswell and later (where we have a special eDP transcoder)
 552          * and Broxton (where we have special DSI transcoders). */
 553         enum transcoder cpu_transcoder;
 554
 555         /*
 556          * Use reduced/limited/broadcast rbg range, compressing from the full
 557          * range fed into the crtcs.
 558          */
 559         bool limited_color_range;
 560
 561         /* Bitmask of encoder types (enum intel_output_type)
 562          * driven by the pipe.
 563          */
 564         unsigned int output_types;
 565
 566         /* Whether we should send NULL infoframes. Required for audio. */
 567         bool has_hdmi_sink;
 568
 569         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 570          * has_dp_encoder is set. */
 571         bool has_audio;
 572
 573         /*
 574          * Enable dithering, used when the selected pipe bpp doesn't match the
 575          * plane bpp.
 576          */
 577         bool dither;
 578
 579         /* Controls for the clock computation, to override various stages. */
 580         bool clock_set;
 581
 582         /* SDVO TV has a bunch of special case. To make multifunction encoders
 583          * work correctly, we need to track this at runtime.*/
 584         bool sdvo_tv_clock;
 585
 586         /*
 587          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 588          * required. This is set in the 2nd loop of calling encoder's
 589          * ->compute_config if the first pick doesn't work out.
 590          */
 591         bool bw_constrained;
 592
 593         /* Settings for the intel dpll used on pretty much everything but
 594          * haswell. */
 595         struct dpll dpll;
 596
 597         /* Selected dpll when shared or NULL. */
 598         struct intel_shared_dpll *shared_dpll;
 599
 600         /* Actual register state of the dpll, for shared dpll cross-checking. */
 601         struct intel_dpll_hw_state dpll_hw_state;
 602
 603         /* DSI PLL registers */
 604         struct {
 605                 u32 ctrl, div;
 606         } dsi_pll;
 607
 608         int pipe_bpp;
 609         struct intel_link_m_n dp_m_n;
 610
 611         /* m2_n2 for eDP downclock */
 612         struct intel_link_m_n dp_m2_n2;
 613         bool has_drrs;
 614
 615         /*
 616          * Frequence the dpll for the port should run at. Differs from the
 617          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 618          * already multiplied by pixel_multiplier.
 619          */
 620         int port_clock;
 621
 622         /* Used by SDVO (and if we ever fix it, HDMI). */
 623         unsigned pixel_multiplier;
 624
 625         uint8_t lane_count;
 626
 627         /*
 628          * Used by platforms having DP/HDMI PHY with programmable lane
 629          * latency optimization.
 630          */
 631         uint8_t lane_lat_optim_mask;
 632
 633         /* Panel fitter controls for gen2-gen4 + VLV */
 634         struct {
 635                 u32 control;
 636                 u32 pgm_ratios;
 637                 u32 lvds_border_bits;
 638         } gmch_pfit;
 639
 640         /* Panel fitter placement and size for Ironlake+ */
 641         struct {
 642                 u32 pos;
 643                 u32 size;
 644                 bool enabled;
 645                 bool force_thru;
 646         } pch_pfit;
 647
 648         /* FDI configuration, only valid if has_pch_encoder is set. */
 649         int fdi_lanes;
 650         struct intel_link_m_n fdi_m_n;
 651
 652         bool ips_enabled;
 653
 654         bool enable_fbc;
 655
 656         bool double_wide;
 657
 658         int pbn;
 659
 660         struct intel_crtc_scaler_state scaler_state;
 661
 662         /* w/a for waiting 2 vblanks during crtc enable */
 663         enum pipe hsw_workaround_pipe;
 664
 665         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 666         bool disable_lp_wm;
 667
 668         struct intel_crtc_wm_state wm;
 669
 670         /* Gamma mode programmed on the pipe */
 671         uint32_t gamma_mode;
 672 };
 673
 674 struct vlv_wm_state {
 675         struct vlv_pipe_wm wm[3];
 676         struct vlv_sr_wm sr[3];
 677         uint8_t num_active_planes;
 678         uint8_t num_levels;
 679         uint8_t level;
 680         bool cxsr;
 681 };
 682
 683 struct intel_crtc {
 684         struct drm_crtc base;
 685         enum pipe pipe;
 686         enum plane plane;
 687         u8 lut_r[256], lut_g[256], lut_b[256];
 688         /*
 689          * Whether the crtc and the connected output pipeline is active. Implies
 690          * that crtc->enabled is set, i.e. the current mode configuration has
 691          * some outputs connected to this crtc.
 692          */
 693         bool active;
 694         bool lowfreq_avail;
 695         u8 plane_ids_mask;
 696         unsigned long enabled_power_domains;
 697         struct intel_overlay *overlay;
 698         struct intel_flip_work *flip_work;
 699
 700         atomic_t unpin_work_count;
 701
 702         /* Display surface base address adjustement for pageflips. Note that on
 703          * gen4+ this only adjusts up to a tile, offsets within a tile are
 704          * handled in the hw itself (with the TILEOFF register). */
 705         u32 dspaddr_offset;
 706         int adjusted_x;
 707         int adjusted_y;
 708
 709         uint32_t cursor_addr;
 710         uint32_t cursor_cntl;
 711         uint32_t cursor_size;
 712         uint32_t cursor_base;
 713
 714         struct intel_crtc_state *config;
 715
 716         /* global reset count when the last flip was submitted */
 717         unsigned int reset_count;
 718
 719         /* Access to these should be protected by dev_priv->irq_lock. */
 720         bool cpu_fifo_underrun_disabled;
 721         bool pch_fifo_underrun_disabled;
 722
 723         /* per-pipe watermark state */
 724         struct {
 725                 /* watermarks currently being used  */
 726                 union {
 727                         struct intel_pipe_wm ilk;
 728                 } active;
 729
 730                 /* allow CxSR on this pipe */
 731                 bool cxsr_allowed;
 732         } wm;
 733
 734         int scanline_offset;
 735
 736         struct {
 737                 unsigned start_vbl_count;
 738                 ktime_t start_vbl_time;
 739                 int min_vbl, max_vbl;
 740                 int scanline_start;
 741         } debug;
 742
 743         /* scalers available on this crtc */
 744         int num_scalers;
 745
 746         struct vlv_wm_state wm_state;
 747 };
 748
 749 struct intel_plane_wm_parameters {
 750         uint32_t horiz_pixels;
 751         uint32_t vert_pixels;
 752         /*
 753          *   For packed pixel formats:
 754          *     bytes_per_pixel - holds bytes per pixel
 755          *   For planar pixel formats:
 756          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 757          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 758          */
 759         uint8_t bytes_per_pixel;
 760         uint8_t y_bytes_per_pixel;
 761         bool enabled;
 762         bool scaled;
 763         u64 tiling;
 764         unsigned int rotation;
 765         uint16_t fifo_size;
 766 };
 767
 768 struct intel_plane {
 769         struct drm_plane base;
 770         u8 plane;
 771         enum plane_id id;
 772         enum pipe pipe;
 773         bool can_scale;
 774         int max_downscale;
 775         uint32_t frontbuffer_bit;
 776
 777         /* Since we need to change the watermarks before/after
 778          * enabling/disabling the planes, we need to store the parameters here
 779          * as the other pieces of the struct may not reflect the values we want
 780          * for the watermark calculations. Currently only Haswell uses this.
 781          */
 782         struct intel_plane_wm_parameters wm;
 783
 784         /*
 785          * NOTE: Do not place new plane state fields here (e.g., when adding
 786          * new plane properties).  New runtime state should now be placed in
 787          * the intel_plane_state structure and accessed via plane_state.
 788          */
 789
 790         void (*update_plane)(struct drm_plane *plane,
 791                              const struct intel_crtc_state *crtc_state,
 792                              const struct intel_plane_state *plane_state);
 793         void (*disable_plane)(struct drm_plane *plane,
 794                               struct drm_crtc *crtc);
 795         int (*check_plane)(struct drm_plane *plane,
 796                            struct intel_crtc_state *crtc_state,
 797                            struct intel_plane_state *state);
 798 };
 799
 800 struct intel_watermark_params {
 801         u16 fifo_size;
 802         u16 max_wm;
 803         u8 default_wm;
 804         u8 guard_size;
 805         u8 cacheline_size;
 806 };
 807
 808 struct cxsr_latency {
 809         bool is_desktop : 1;
 810         bool is_ddr3 : 1;
 811         u16 fsb_freq;
 812         u16 mem_freq;
 813         u16 display_sr;
 814         u16 display_hpll_disable;
 815         u16 cursor_sr;
 816         u16 cursor_hpll_disable;
 817 };
 818
 819 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 820 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 821 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 822 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 823 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 824 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 825 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 826 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 827 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 828
 829 struct intel_hdmi {
 830         i915_reg_t hdmi_reg;
 831         int ddc_bus;
 832         struct {
 833                 enum drm_dp_dual_mode_type type;
 834                 int max_tmds_clock;
 835         } dp_dual_mode;
 836         bool limited_color_range;
 837         bool color_range_auto;
 838         bool has_hdmi_sink;
 839         bool has_audio;
 840         enum hdmi_force_audio force_audio;
 841         bool rgb_quant_range_selectable;
 842         enum hdmi_picture_aspect aspect_ratio;
 843         struct intel_connector *attached_connector;
 844         void (*write_infoframe)(struct drm_encoder *encoder,
 845                                 const struct intel_crtc_state *crtc_state,
 846                                 enum hdmi_infoframe_type type,
 847                                 const void *frame, ssize_t len);
 848         void (*set_infoframes)(struct drm_encoder *encoder,
 849                                bool enable,
 850                                const struct intel_crtc_state *crtc_state,
 851                                const struct drm_connector_state *conn_state);
 852         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 853                                   const struct intel_crtc_state *pipe_config);
 854 };
 855
 856 struct intel_dp_mst_encoder;
 857 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 858
 859 /*
 860  * enum link_m_n_set:
 861  *      When platform provides two set of M_N registers for dp, we can
 862  *      program them and switch between them incase of DRRS.
 863  *      But When only one such register is provided, we have to program the
 864  *      required divider value on that registers itself based on the DRRS state.
 865  *
 866  * M1_N1        : Program dp_m_n on M1_N1 registers
 867  *                        dp_m2_n2 on M2_N2 registers (If supported)
 868  *
 869  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 870  *                        M2_N2 registers are not supported
 871  */
 872
 873 enum link_m_n_set {
 874         /* Sets the m1_n1 and m2_n2 */
 875         M1_N1 = 0,
 876         M2_N2
 877 };
 878
 879 struct intel_dp_desc {
 880         u8 oui[3];
 881         u8 device_id[6];
 882         u8 hw_rev;
 883         u8 sw_major_rev;
 884         u8 sw_minor_rev;
 885 } __packed;
 886
 887 struct intel_dp_compliance_data {
 888         unsigned long edid;
 889 };
 890
 891 struct intel_dp_compliance {
 892         unsigned long test_type;
 893         struct intel_dp_compliance_data test_data;
 894         bool test_active;
 895 };
 896
 897 struct intel_dp {
 898         i915_reg_t output_reg;
 899         i915_reg_t aux_ch_ctl_reg;
 900         i915_reg_t aux_ch_data_reg[5];
 901         uint32_t DP;
 902         int link_rate;
 903         uint8_t lane_count;
 904         uint8_t sink_count;
 905         bool link_mst;
 906         bool has_audio;
 907         bool detect_done;
 908         bool channel_eq_status;
 909         enum hdmi_force_audio force_audio;
 910         bool limited_color_range;
 911         bool color_range_auto;
 912         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 913         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 914         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 915         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 916         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 917         uint8_t num_sink_rates;
 918         int sink_rates[DP_MAX_SUPPORTED_RATES];
 919         /* Max lane count for the sink as per DPCD registers */
 920         uint8_t max_sink_lane_count;
 921         /* Max link BW for the sink as per DPCD registers */
 922         int max_sink_link_bw;
 923         /* sink or branch descriptor */
 924         struct intel_dp_desc desc;
 925         struct drm_dp_aux aux;
 926         uint8_t train_set[4];
 927         int panel_power_up_delay;
 928         int panel_power_down_delay;
 929         int panel_power_cycle_delay;
 930         int backlight_on_delay;
 931         int backlight_off_delay;
 932         struct delayed_work panel_vdd_work;
 933         bool want_panel_vdd;
 934         unsigned long last_power_on;
 935         unsigned long last_backlight_off;
 936         ktime_t panel_power_off_time;
 937
 938         struct notifier_block edp_notifier;
 939
 940         /*
 941          * Pipe whose power sequencer is currently locked into
 942          * this port. Only relevant on VLV/CHV.
 943          */
 944         enum pipe pps_pipe;
 945         /*
 946          * Set if the sequencer may be reset due to a power transition,
 947          * requiring a reinitialization. Only relevant on BXT.
 948          */
 949         bool pps_reset;
 950         struct edp_power_seq pps_delays;
 951
 952         bool can_mst; /* this port supports mst */
 953         bool is_mst;
 954         int active_mst_links;
 955         /* connector directly attached - won't be use for modeset in mst world */
 956         struct intel_connector *attached_connector;
 957
 958         /* mst connector list */
 959         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 960         struct drm_dp_mst_topology_mgr mst_mgr;
 961
 962         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 963         /*
 964          * This function returns the value we have to program the AUX_CTL
 965          * register with to kick off an AUX transaction.
 966          */
 967         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 968                                      bool has_aux_irq,
 969                                      int send_bytes,
 970                                      uint32_t aux_clock_divider);
 971
 972         /* This is called before a link training is starterd */
 973         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 974
 975         /* Displayport compliance testing */
 976         struct intel_dp_compliance compliance;
 977 };
 978
 979 struct intel_lspcon {
 980         bool active;
 981         enum drm_lspcon_mode mode;
 982         bool desc_valid;
 983 };
 984
 985 struct intel_digital_port {
 986         struct intel_encoder base;
 987         enum port port;
 988         u32 saved_port_bits;
 989         struct intel_dp dp;
 990         struct intel_hdmi hdmi;
 991         struct intel_lspcon lspcon;
 992         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 993         bool release_cl2_override;
 994         uint8_t max_lanes;
 995 };
 996
 997 struct intel_dp_mst_encoder {
 998         struct intel_encoder base;
 999         enum pipe pipe;
1000         struct intel_digital_port *primary;
1001         struct intel_connector *connector;
1002 };
1003
1004 static inline enum dpio_channel
1005 vlv_dport_to_channel(struct intel_digital_port *dport)
1006 {
1007         switch (dport->port) {
1008         case PORT_B:
1009         case PORT_D:
1010                 return DPIO_CH0;
1011         case PORT_C:
1012                 return DPIO_CH1;
1013         default:
1014                 BUG();
1015         }
1016 }
1017
1018 static inline enum dpio_phy
1019 vlv_dport_to_phy(struct intel_digital_port *dport)
1020 {
1021         switch (dport->port) {
1022         case PORT_B:
1023         case PORT_C:
1024                 return DPIO_PHY0;
1025         case PORT_D:
1026                 return DPIO_PHY1;
1027         default:
1028                 BUG();
1029         }
1030 }
1031
1032 static inline enum dpio_channel
1033 vlv_pipe_to_channel(enum pipe pipe)
1034 {
1035         switch (pipe) {
1036         case PIPE_A:
1037         case PIPE_C:
1038                 return DPIO_CH0;
1039         case PIPE_B:
1040                 return DPIO_CH1;
1041         default:
1042                 BUG();
1043         }
1044 }
1045
1046 static inline struct intel_crtc *
1047 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1048 {
1049         return dev_priv->pipe_to_crtc_mapping[pipe];
1050 }
1051
1052 static inline struct intel_crtc *
1053 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1054 {
1055         return dev_priv->plane_to_crtc_mapping[plane];
1056 }
1057
1058 struct intel_flip_work {
1059         struct work_struct unpin_work;
1060         struct work_struct mmio_work;
1061
1062         struct drm_crtc *crtc;
1063         struct drm_framebuffer *old_fb;
1064         struct drm_i915_gem_object *pending_flip_obj;
1065         struct drm_pending_vblank_event *event;
1066         atomic_t pending;
1067         u32 flip_count;
1068         u32 gtt_offset;
1069         struct drm_i915_gem_request *flip_queued_req;
1070         u32 flip_queued_vblank;
1071         u32 flip_ready_vblank;
1072         unsigned int rotation;
1073 };
1074
1075 struct intel_load_detect_pipe {
1076         struct drm_atomic_state *restore_state;
1077 };
1078
1079 static inline struct intel_encoder *
1080 intel_attached_encoder(struct drm_connector *connector)
1081 {
1082         return to_intel_connector(connector)->encoder;
1083 }
1084
1085 static inline struct intel_digital_port *
1086 enc_to_dig_port(struct drm_encoder *encoder)
1087 {
1088         return container_of(encoder, struct intel_digital_port, base.base);
1089 }
1090
1091 static inline struct intel_dp_mst_encoder *
1092 enc_to_mst(struct drm_encoder *encoder)
1093 {
1094         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1095 }
1096
1097 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1098 {
1099         return &enc_to_dig_port(encoder)->dp;
1100 }
1101
1102 static inline struct intel_digital_port *
1103 dp_to_dig_port(struct intel_dp *intel_dp)
1104 {
1105         return container_of(intel_dp, struct intel_digital_port, dp);
1106 }
1107
1108 static inline struct intel_lspcon *
1109 dp_to_lspcon(struct intel_dp *intel_dp)
1110 {
1111         return &dp_to_dig_port(intel_dp)->lspcon;
1112 }
1113
1114 static inline struct intel_digital_port *
1115 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1116 {
1117         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1118 }
1119
1120 /* intel_fifo_underrun.c */
1121 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1122                                            enum pipe pipe, bool enable);
1123 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1124                                            enum transcoder pch_transcoder,
1125                                            bool enable);
1126 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1127                                          enum pipe pipe);
1128 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1129                                          enum transcoder pch_transcoder);
1130 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1131 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1132
1133 /* i915_irq.c */
1134 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1135 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1136 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1137 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1138 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1139 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1140 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1141 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1142 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1143 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1144 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1145 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1146 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1147 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1148 {
1149         /*
1150          * We only use drm_irq_uninstall() at unload and VT switch, so
1151          * this is the only thing we need to check.
1152          */
1153         return dev_priv->pm.irqs_enabled;
1154 }
1155
1156 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1157 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1158                                      unsigned int pipe_mask);
1159 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1160                                      unsigned int pipe_mask);
1161 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1162 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1163 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1164
1165 /* intel_crt.c */
1166 void intel_crt_init(struct drm_i915_private *dev_priv);
1167 void intel_crt_reset(struct drm_encoder *encoder);
1168
1169 /* intel_ddi.c */
1170 void intel_ddi_clk_select(struct intel_encoder *encoder,
1171                           struct intel_shared_dpll *pll);
1172 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1173                                 struct intel_crtc_state *old_crtc_state,
1174                                 struct drm_connector_state *old_conn_state);
1175 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1176 void hsw_fdi_link_train(struct drm_crtc *crtc);
1177 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1178 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1179 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1180 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1181 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1182                                        enum transcoder cpu_transcoder);
1183 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1184 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1185 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1186                           struct intel_crtc_state *crtc_state);
1187 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1188 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1189 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1190 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1191                                  struct intel_crtc *intel_crtc);
1192 void intel_ddi_get_config(struct intel_encoder *encoder,
1193                           struct intel_crtc_state *pipe_config);
1194 struct intel_encoder *
1195 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1196
1197 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1198 void intel_ddi_clock_get(struct intel_encoder *encoder,
1199                          struct intel_crtc_state *pipe_config);
1200 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1201 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1202 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1203                                                   int clock);
1204 unsigned int intel_fb_align_height(struct drm_device *dev,
1205                                    unsigned int height,
1206                                    uint32_t pixel_format,
1207                                    uint64_t fb_format_modifier);
1208 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1209                               uint64_t fb_modifier, uint32_t pixel_format);
1210
1211 /* intel_audio.c */
1212 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1213 void intel_audio_codec_enable(struct intel_encoder *encoder,
1214                               const struct intel_crtc_state *crtc_state,
1215                               const struct drm_connector_state *conn_state);
1216 void intel_audio_codec_disable(struct intel_encoder *encoder);
1217 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1218 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1219
1220 /* intel_display.c */
1221 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1222 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1223 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1224 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1225                       const char *name, u32 reg, int ref_freq);
1226 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1227 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1228 extern const struct drm_plane_funcs intel_plane_funcs;
1229 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1230 unsigned int intel_fb_xy_to_linear(int x, int y,
1231                                    const struct intel_plane_state *state,
1232                                    int plane);
1233 void intel_add_fb_offsets(int *x, int *y,
1234                           const struct intel_plane_state *state, int plane);
1235 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1236 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1237 void intel_mark_busy(struct drm_i915_private *dev_priv);
1238 void intel_mark_idle(struct drm_i915_private *dev_priv);
1239 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1240 int intel_display_suspend(struct drm_device *dev);
1241 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1242 void intel_encoder_destroy(struct drm_encoder *encoder);
1243 int intel_connector_init(struct intel_connector *);
1244 struct intel_connector *intel_connector_alloc(void);
1245 bool intel_connector_get_hw_state(struct intel_connector *connector);
1246 void intel_connector_attach_encoder(struct intel_connector *connector,
1247                                     struct intel_encoder *encoder);
1248 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1249                                              struct drm_crtc *crtc);
1250 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1251 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1252                                 struct drm_file *file_priv);
1253 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1254                                              enum pipe pipe);
1255 static inline bool
1256 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1257                     enum intel_output_type type)
1258 {
1259         return crtc_state->output_types & (1 << type);
1260 }
1261 static inline bool
1262 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1263 {
1264         return crtc_state->output_types &
1265                 ((1 << INTEL_OUTPUT_DP) |
1266                  (1 << INTEL_OUTPUT_DP_MST) |
1267                  (1 << INTEL_OUTPUT_EDP));
1268 }
1269 static inline void
1270 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1271 {
1272         drm_wait_one_vblank(&dev_priv->drm, pipe);
1273 }
1274 static inline void
1275 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1276 {
1277         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1278
1279         if (crtc->active)
1280                 intel_wait_for_vblank(dev_priv, pipe);
1281 }
1282
1283 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1284
1285 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1286 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1287                          struct intel_digital_port *dport,
1288                          unsigned int expected_mask);
1289 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1290                                 struct drm_display_mode *mode,
1291                                 struct intel_load_detect_pipe *old,
1292                                 struct drm_modeset_acquire_ctx *ctx);
1293 void intel_release_load_detect_pipe(struct drm_connector *connector,
1294                                     struct intel_load_detect_pipe *old,
1295                                     struct drm_modeset_acquire_ctx *ctx);
1296 struct i915_vma *
1297 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1298 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1299 struct drm_framebuffer *
1300 __intel_framebuffer_create(struct drm_device *dev,
1301                            struct drm_mode_fb_cmd2 *mode_cmd,
1302                            struct drm_i915_gem_object *obj);
1303 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1304 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1305 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1306 int intel_prepare_plane_fb(struct drm_plane *plane,
1307                            struct drm_plane_state *new_state);
1308 void intel_cleanup_plane_fb(struct drm_plane *plane,
1309                             struct drm_plane_state *old_state);
1310 int intel_plane_atomic_get_property(struct drm_plane *plane,
1311                                     const struct drm_plane_state *state,
1312                                     struct drm_property *property,
1313                                     uint64_t *val);
1314 int intel_plane_atomic_set_property(struct drm_plane *plane,
1315                                     struct drm_plane_state *state,
1316                                     struct drm_property *property,
1317                                     uint64_t val);
1318 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1319                                     struct drm_plane_state *plane_state);
1320
1321 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1322                                uint64_t fb_modifier, unsigned int cpp);
1323
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1325                                     enum pipe pipe);
1326
1327 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1328                      const struct dpll *dpll);
1329 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1330 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1331
1332 /* modesetting asserts */
1333 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1334                            enum pipe pipe);
1335 void assert_pll(struct drm_i915_private *dev_priv,
1336                 enum pipe pipe, bool state);
1337 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1338 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1339 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1340 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1341 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1342 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1343                        enum pipe pipe, bool state);
1344 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1345 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1346 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1347 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1348 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1349 u32 intel_compute_tile_offset(int *x, int *y,
1350                               const struct intel_plane_state *state, int plane);
1351 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1352 void intel_finish_reset(struct drm_i915_private *dev_priv);
1353 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1354 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1355 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1356 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1357 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1358 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1359 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1360 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1361 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1362 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1363 unsigned int skl_cdclk_get_vco(unsigned int freq);
1364 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1365 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1366 void intel_dp_get_m_n(struct intel_crtc *crtc,
1367                       struct intel_crtc_state *pipe_config);
1368 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1369 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1370 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1371                         struct dpll *best_clock);
1372 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1373
1374 bool intel_crtc_active(struct intel_crtc *crtc);
1375 void hsw_enable_ips(struct intel_crtc *crtc);
1376 void hsw_disable_ips(struct intel_crtc *crtc);
1377 enum intel_display_power_domain
1378 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1379 enum intel_display_power_domain
1380 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1381 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1382                                  struct intel_crtc_state *pipe_config);
1383
1384 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1385 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1386
1387 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1388
1389 u32 skl_plane_ctl_format(uint32_t pixel_format);
1390 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1391 u32 skl_plane_ctl_rotation(unsigned int rotation);
1392 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1393                      unsigned int rotation);
1394 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1395
1396 /* intel_csr.c */
1397 void intel_csr_ucode_init(struct drm_i915_private *);
1398 void intel_csr_load_program(struct drm_i915_private *);
1399 void intel_csr_ucode_fini(struct drm_i915_private *);
1400 void intel_csr_ucode_suspend(struct drm_i915_private *);
1401 void intel_csr_ucode_resume(struct drm_i915_private *);
1402
1403 /* intel_dp.c */
1404 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1405                    enum port port);
1406 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1407                              struct intel_connector *intel_connector);
1408 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1409                               int link_rate, uint8_t lane_count,
1410                               bool link_mst);
1411 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1412                                             int link_rate, uint8_t lane_count);
1413 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1414 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1415 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1416 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1417 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1418 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1419 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1420 bool intel_dp_compute_config(struct intel_encoder *encoder,
1421                              struct intel_crtc_state *pipe_config,
1422                              struct drm_connector_state *conn_state);
1423 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1424 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1425                                   bool long_hpd);
1426 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1427 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1428 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1429 void intel_edp_panel_on(struct intel_dp *intel_dp);
1430 void intel_edp_panel_off(struct intel_dp *intel_dp);
1431 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1432 void intel_dp_mst_suspend(struct drm_device *dev);
1433 void intel_dp_mst_resume(struct drm_device *dev);
1434 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1435 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1436 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1437 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1438 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1439 void intel_plane_destroy(struct drm_plane *plane);
1440 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1441                            struct intel_crtc_state *crtc_state);
1442 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1443                            struct intel_crtc_state *crtc_state);
1444 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1445                                unsigned int frontbuffer_bits);
1446 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1447                           unsigned int frontbuffer_bits);
1448
1449 void
1450 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1451                                        uint8_t dp_train_pat);
1452 void
1453 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1454 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1455 uint8_t
1456 intel_dp_voltage_max(struct intel_dp *intel_dp);
1457 uint8_t
1458 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1459 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1460                            uint8_t *link_bw, uint8_t *rate_select);
1461 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1462 bool
1463 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1464
1465 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1466 {
1467         return ~((1 << lane_count) - 1) & 0xf;
1468 }
1469
1470 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1471 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1472                           struct intel_dp_desc *desc);
1473 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1474 int intel_dp_link_required(int pixel_clock, int bpp);
1475 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1476
1477 /* intel_dp_aux_backlight.c */
1478 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1479
1480 /* intel_dp_mst.c */
1481 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1482 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1483 /* intel_dsi.c */
1484 void intel_dsi_init(struct drm_i915_private *dev_priv);
1485
1486 /* intel_dsi_dcs_backlight.c */
1487 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1488
1489 /* intel_dvo.c */
1490 void intel_dvo_init(struct drm_i915_private *dev_priv);
1491 /* intel_hotplug.c */
1492 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1493
1494
1495 /* legacy fbdev emulation in intel_fbdev.c */
1496 #ifdef CONFIG_DRM_FBDEV_EMULATION
1497 extern int intel_fbdev_init(struct drm_device *dev);
1498 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1499 extern void intel_fbdev_fini(struct drm_device *dev);
1500 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1501 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1502 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1503 #else
1504 static inline int intel_fbdev_init(struct drm_device *dev)
1505 {
1506         return 0;
1507 }
1508
1509 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1510 {
1511 }
1512
1513 static inline void intel_fbdev_fini(struct drm_device *dev)
1514 {
1515 }
1516
1517 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1518 {
1519 }
1520
1521 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1522 {
1523 }
1524
1525 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1526 {
1527 }
1528 #endif
1529
1530 /* intel_fbc.c */
1531 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1532                            struct drm_atomic_state *state);
1533 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1534 void intel_fbc_pre_update(struct intel_crtc *crtc,
1535                           struct intel_crtc_state *crtc_state,
1536                           struct intel_plane_state *plane_state);
1537 void intel_fbc_post_update(struct intel_crtc *crtc);
1538 void intel_fbc_init(struct drm_i915_private *dev_priv);
1539 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1540 void intel_fbc_enable(struct intel_crtc *crtc,
1541                       struct intel_crtc_state *crtc_state,
1542                       struct intel_plane_state *plane_state);
1543 void intel_fbc_disable(struct intel_crtc *crtc);
1544 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1545 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1546                           unsigned int frontbuffer_bits,
1547                           enum fb_op_origin origin);
1548 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1549                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1550 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1551 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1552
1553 /* intel_hdmi.c */
1554 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1555                      enum port port);
1556 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1557                                struct intel_connector *intel_connector);
1558 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1559 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1560                                struct intel_crtc_state *pipe_config,
1561                                struct drm_connector_state *conn_state);
1562 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1563
1564
1565 /* intel_lvds.c */
1566 void intel_lvds_init(struct drm_i915_private *dev_priv);
1567 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1568 bool intel_is_dual_link_lvds(struct drm_device *dev);
1569
1570
1571 /* intel_modes.c */
1572 int intel_connector_update_modes(struct drm_connector *connector,
1573                                  struct edid *edid);
1574 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1575 void intel_attach_force_audio_property(struct drm_connector *connector);
1576 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1577 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1578
1579
1580 /* intel_overlay.c */
1581 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1582 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1583 int intel_overlay_switch_off(struct intel_overlay *overlay);
1584 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1585                                   struct drm_file *file_priv);
1586 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1587                               struct drm_file *file_priv);
1588 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1589
1590
1591 /* intel_panel.c */
1592 int intel_panel_init(struct intel_panel *panel,
1593                      struct drm_display_mode *fixed_mode,
1594                      struct drm_display_mode *downclock_mode);
1595 void intel_panel_fini(struct intel_panel *panel);
1596 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1597                             struct drm_display_mode *adjusted_mode);
1598 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1599                              struct intel_crtc_state *pipe_config,
1600                              int fitting_mode);
1601 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1602                               struct intel_crtc_state *pipe_config,
1603                               int fitting_mode);
1604 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1605                                     u32 level, u32 max);
1606 int intel_panel_setup_backlight(struct drm_connector *connector,
1607                                 enum pipe pipe);
1608 void intel_panel_enable_backlight(struct intel_connector *connector);
1609 void intel_panel_disable_backlight(struct intel_connector *connector);
1610 void intel_panel_destroy_backlight(struct drm_connector *connector);
1611 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1612 extern struct drm_display_mode *intel_find_panel_downclock(
1613                                 struct drm_device *dev,
1614                                 struct drm_display_mode *fixed_mode,
1615                                 struct drm_connector *connector);
1616
1617 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1618 int intel_backlight_device_register(struct intel_connector *connector);
1619 void intel_backlight_device_unregister(struct intel_connector *connector);
1620 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1621 static int intel_backlight_device_register(struct intel_connector *connector)
1622 {
1623         return 0;
1624 }
1625 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1626 {
1627 }
1628 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1629
1630
1631 /* intel_psr.c */
1632 void intel_psr_enable(struct intel_dp *intel_dp);
1633 void intel_psr_disable(struct intel_dp *intel_dp);
1634 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1635                           unsigned frontbuffer_bits);
1636 void intel_psr_flush(struct drm_i915_private *dev_priv,
1637                      unsigned frontbuffer_bits,
1638                      enum fb_op_origin origin);
1639 void intel_psr_init(struct drm_i915_private *dev_priv);
1640 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1641                                    unsigned frontbuffer_bits);
1642
1643 /* intel_runtime_pm.c */
1644 int intel_power_domains_init(struct drm_i915_private *);
1645 void intel_power_domains_fini(struct drm_i915_private *);
1646 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1647 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1648 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1649 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1650 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1651 const char *
1652 intel_display_power_domain_str(enum intel_display_power_domain domain);
1653
1654 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1655                                     enum intel_display_power_domain domain);
1656 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1657                                       enum intel_display_power_domain domain);
1658 void intel_display_power_get(struct drm_i915_private *dev_priv,
1659                              enum intel_display_power_domain domain);
1660 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1661                                         enum intel_display_power_domain domain);
1662 void intel_display_power_put(struct drm_i915_private *dev_priv,
1663                              enum intel_display_power_domain domain);
1664
1665 static inline void
1666 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1667 {
1668         WARN_ONCE(dev_priv->pm.suspended,
1669                   "Device suspended during HW access\n");
1670 }
1671
1672 static inline void
1673 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1674 {
1675         assert_rpm_device_not_suspended(dev_priv);
1676         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1677          * too much noise. */
1678         if (!atomic_read(&dev_priv->pm.wakeref_count))
1679                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1680 }
1681
1682 /**
1683  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1684  * @dev_priv: i915 device instance
1685  *
1686  * This function disable asserts that check if we hold an RPM wakelock
1687  * reference, while keeping the device-not-suspended checks still enabled.
1688  * It's meant to be used only in special circumstances where our rule about
1689  * the wakelock refcount wrt. the device power state doesn't hold. According
1690  * to this rule at any point where we access the HW or want to keep the HW in
1691  * an active state we must hold an RPM wakelock reference acquired via one of
1692  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1693  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1694  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1695  * users should avoid using this function.
1696  *
1697  * Any calls to this function must have a symmetric call to
1698  * enable_rpm_wakeref_asserts().
1699  */
1700 static inline void
1701 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1702 {
1703         atomic_inc(&dev_priv->pm.wakeref_count);
1704 }
1705
1706 /**
1707  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1708  * @dev_priv: i915 device instance
1709  *
1710  * This function re-enables the RPM assert checks after disabling them with
1711  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1712  * circumstances otherwise its use should be avoided.
1713  *
1714  * Any calls to this function must have a symmetric call to
1715  * disable_rpm_wakeref_asserts().
1716  */
1717 static inline void
1718 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1719 {
1720         atomic_dec(&dev_priv->pm.wakeref_count);
1721 }
1722
1723 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1724 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1725 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1726 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1727
1728 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1729
1730 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1731                              bool override, unsigned int mask);
1732 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1733                           enum dpio_channel ch, bool override);
1734
1735
1736 /* intel_pm.c */
1737 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1738 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1739 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1740 void intel_update_watermarks(struct intel_crtc *crtc);
1741 void intel_init_pm(struct drm_i915_private *dev_priv);
1742 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1743 void intel_pm_setup(struct drm_i915_private *dev_priv);
1744 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1745 void intel_gpu_ips_teardown(void);
1746 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1747 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1748 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1749 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1750 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1751 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1752 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1753 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1754 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1755 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1756 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1757                     struct intel_rps_client *rps,
1758                     unsigned long submitted);
1759 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1760 void vlv_wm_get_hw_state(struct drm_device *dev);
1761 void ilk_wm_get_hw_state(struct drm_device *dev);
1762 void skl_wm_get_hw_state(struct drm_device *dev);
1763 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1764                           struct skl_ddb_allocation *ddb /* out */);
1765 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1766                               struct skl_pipe_wm *out);
1767 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1768 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1769 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1770 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1771                          const struct skl_wm_level *l2);
1772 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1773                                  const struct skl_ddb_entry *ddb,
1774                                  int ignore);
1775 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1776 bool ilk_disable_lp_wm(struct drm_device *dev);
1777 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1778 static inline int intel_enable_rc6(void)
1779 {
1780         return i915.enable_rc6;
1781 }
1782
1783 /* intel_sdvo.c */
1784 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1785                      i915_reg_t reg, enum port port);
1786
1787
1788 /* intel_sprite.c */
1789 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1790                              int usecs);
1791 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1792                                               enum pipe pipe, int plane);
1793 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1794                               struct drm_file *file_priv);
1795 void intel_pipe_update_start(struct intel_crtc *crtc);
1796 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1797
1798 /* intel_tv.c */
1799 void intel_tv_init(struct drm_i915_private *dev_priv);
1800
1801 /* intel_atomic.c */
1802 int intel_connector_atomic_get_property(struct drm_connector *connector,
1803                                         const struct drm_connector_state *state,
1804                                         struct drm_property *property,
1805                                         uint64_t *val);
1806 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1807 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1808                                struct drm_crtc_state *state);
1809 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1810 void intel_atomic_state_clear(struct drm_atomic_state *);
1811 struct intel_shared_dpll_config *
1812 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1813
1814 static inline struct intel_crtc_state *
1815 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1816                             struct intel_crtc *crtc)
1817 {
1818         struct drm_crtc_state *crtc_state;
1819         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1820         if (IS_ERR(crtc_state))
1821                 return ERR_CAST(crtc_state);
1822
1823         return to_intel_crtc_state(crtc_state);
1824 }
1825
1826 static inline struct intel_crtc_state *
1827 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1828                                      struct intel_crtc *crtc)
1829 {
1830         struct drm_crtc_state *crtc_state;
1831
1832         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1833
1834         if (crtc_state)
1835                 return to_intel_crtc_state(crtc_state);
1836         else
1837                 return NULL;
1838 }
1839
1840 static inline struct intel_plane_state *
1841 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1842                                       struct intel_plane *plane)
1843 {
1844         struct drm_plane_state *plane_state;
1845
1846         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1847
1848         return to_intel_plane_state(plane_state);
1849 }
1850
1851 int intel_atomic_setup_scalers(struct drm_device *dev,
1852         struct intel_crtc *intel_crtc,
1853         struct intel_crtc_state *crtc_state);
1854
1855 /* intel_atomic_plane.c */
1856 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1857 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1858 void intel_plane_destroy_state(struct drm_plane *plane,
1859                                struct drm_plane_state *state);
1860 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1861
1862 /* intel_color.c */
1863 void intel_color_init(struct drm_crtc *crtc);
1864 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1865 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1866 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1867
1868 /* intel_lspcon.c */
1869 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1870 void lspcon_resume(struct intel_lspcon *lspcon);
1871 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1872
1873 /* intel_pipe_crc.c */
1874 int intel_pipe_crc_create(struct drm_minor *minor);
1875 void intel_pipe_crc_cleanup(struct drm_minor *minor);
1876 extern const struct file_operations i915_display_crc_ctl_fops;
1877 #endif /* __INTEL_DRV_H__ */