2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 * TODO: When modesetting has fully transitioned to atomic, the below
52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
55 #define _wait_for(COND, US, W) ({ \
56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
59 bool expired__ = time_after(jiffies, timeout__); \
68 if ((W) && drm_can_sleep()) { \
69 usleep_range((W), (W)*2); \
77 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #define _wait_for_atomic(COND, US, ATOMIC) \
88 int cpu, ret, timeout = (US) * 1000; \
90 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
91 BUILD_BUG_ON((US) > 50000); \
94 cpu = smp_processor_id(); \
96 base = local_clock(); \
98 u64 now = local_clock(); \
105 if (now - base >= timeout) { \
112 if (unlikely(cpu != smp_processor_id())) { \
113 timeout -= now - base; \
114 cpu = smp_processor_id(); \
115 base = local_clock(); \
122 #define wait_for_us(COND, US) \
125 BUILD_BUG_ON(!__builtin_constant_p(US)); \
127 ret__ = _wait_for((COND), (US), 10); \
129 ret__ = _wait_for_atomic((COND), (US), 0); \
133 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
134 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
136 #define KHz(x) (1000 * (x))
137 #define MHz(x) KHz(1000 * (x))
140 * Display related stuff
143 /* store information about an Ixxx DVO */
144 /* The i830->i865 use multiple DVOs with multiple i2cs */
145 /* the i915, i945 have a single sDVO i2c bus - which is different */
146 #define MAX_OUTPUTS 6
147 /* maximum connectors per crtcs in the mode set */
149 /* Maximum cursor sizes */
150 #define GEN2_CURSOR_WIDTH 64
151 #define GEN2_CURSOR_HEIGHT 64
152 #define MAX_CURSOR_WIDTH 256
153 #define MAX_CURSOR_HEIGHT 256
155 #define INTEL_I2C_BUS_DVO 1
156 #define INTEL_I2C_BUS_SDVO 2
158 /* these are outputs from the chip - integrated only
159 external chips are via DVO or SDVO output */
160 enum intel_output_type
{
161 INTEL_OUTPUT_UNUSED
= 0,
162 INTEL_OUTPUT_ANALOG
= 1,
163 INTEL_OUTPUT_DVO
= 2,
164 INTEL_OUTPUT_SDVO
= 3,
165 INTEL_OUTPUT_LVDS
= 4,
166 INTEL_OUTPUT_TVOUT
= 5,
167 INTEL_OUTPUT_HDMI
= 6,
169 INTEL_OUTPUT_EDP
= 8,
170 INTEL_OUTPUT_DSI
= 9,
171 INTEL_OUTPUT_UNKNOWN
= 10,
172 INTEL_OUTPUT_DP_MST
= 11,
175 #define INTEL_DVO_CHIP_NONE 0
176 #define INTEL_DVO_CHIP_LVDS 1
177 #define INTEL_DVO_CHIP_TMDS 2
178 #define INTEL_DVO_CHIP_TVOUT 4
180 #define INTEL_DSI_VIDEO_MODE 0
181 #define INTEL_DSI_COMMAND_MODE 1
183 struct intel_framebuffer
{
184 struct drm_framebuffer base
;
185 struct drm_i915_gem_object
*obj
;
186 struct intel_rotation_info rot_info
;
188 /* for each plane in the normal GTT view */
192 /* for each plane in the rotated GTT view */
195 unsigned int pitch
; /* pixels */
200 struct drm_fb_helper helper
;
201 struct intel_framebuffer
*fb
;
202 struct i915_vma
*vma
;
203 async_cookie_t cookie
;
207 struct intel_encoder
{
208 struct drm_encoder base
;
210 enum intel_output_type type
;
212 unsigned int cloneable
;
213 void (*hot_plug
)(struct intel_encoder
*);
214 bool (*compute_config
)(struct intel_encoder
*,
215 struct intel_crtc_state
*,
216 struct drm_connector_state
*);
217 void (*pre_pll_enable
)(struct intel_encoder
*,
218 struct intel_crtc_state
*,
219 struct drm_connector_state
*);
220 void (*pre_enable
)(struct intel_encoder
*,
221 struct intel_crtc_state
*,
222 struct drm_connector_state
*);
223 void (*enable
)(struct intel_encoder
*,
224 struct intel_crtc_state
*,
225 struct drm_connector_state
*);
226 void (*disable
)(struct intel_encoder
*,
227 struct intel_crtc_state
*,
228 struct drm_connector_state
*);
229 void (*post_disable
)(struct intel_encoder
*,
230 struct intel_crtc_state
*,
231 struct drm_connector_state
*);
232 void (*post_pll_disable
)(struct intel_encoder
*,
233 struct intel_crtc_state
*,
234 struct drm_connector_state
*);
235 /* Read out the current hw state of this connector, returning true if
236 * the encoder is active. If the encoder is enabled it also set the pipe
237 * it is connected to in the pipe parameter. */
238 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
239 /* Reconstructs the equivalent mode flags for the current hardware
240 * state. This must be called _after_ display->get_pipe_config has
241 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
242 * be set correctly before calling this function. */
243 void (*get_config
)(struct intel_encoder
*,
244 struct intel_crtc_state
*pipe_config
);
245 /* Returns a mask of power domains that need to be referenced as part
246 * of the hardware state readout code. */
247 u64 (*get_power_domains
)(struct intel_encoder
*encoder
);
249 * Called during system suspend after all pending requests for the
250 * encoder are flushed (for example for DP AUX transactions) and
251 * device interrupts are disabled.
253 void (*suspend
)(struct intel_encoder
*);
255 enum hpd_pin hpd_pin
;
256 enum intel_display_power_domain power_domain
;
257 /* for communication with audio component; protected by av_mutex */
258 const struct drm_connector
*audio_connector
;
262 struct drm_display_mode
*fixed_mode
;
263 struct drm_display_mode
*downclock_mode
;
273 bool combination_mode
; /* gen 2/4 only */
275 bool alternate_pwm_increment
; /* lpt+ */
278 bool util_pin_active_low
; /* bxt+ */
279 u8 controller
; /* bxt+ only */
280 struct pwm_device
*pwm
;
282 struct backlight_device
*device
;
284 /* Connector and platform specific backlight functions */
285 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
286 uint32_t (*get
)(struct intel_connector
*connector
);
287 void (*set
)(struct intel_connector
*connector
, uint32_t level
);
288 void (*disable
)(struct intel_connector
*connector
);
289 void (*enable
)(struct intel_connector
*connector
);
290 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
292 void (*power
)(struct intel_connector
*, bool enable
);
296 struct intel_connector
{
297 struct drm_connector base
;
299 * The fixed encoder this connector is connected to.
301 struct intel_encoder
*encoder
;
303 /* ACPI device id for ACPI and driver cooperation */
306 /* Reads out the current hw, returning true if the connector is enabled
307 * and active (i.e. dpms ON state). */
308 bool (*get_hw_state
)(struct intel_connector
*);
310 /* Panel info for eDP and LVDS */
311 struct intel_panel panel
;
313 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
315 struct edid
*detect_edid
;
317 /* since POLL and HPD connectors may use the same HPD line keep the native
318 state of connector->polled in case hotplug storm detection changes it */
321 void *port
; /* store this opaque as its illegal to dereference it */
323 struct intel_dp
*mst_port
;
338 struct intel_atomic_state
{
339 struct drm_atomic_state base
;
343 * Logical state of cdclk (used for all scaling, watermark,
344 * etc. calculations and checks). This is computed as if all
345 * enabled crtcs were active.
347 struct intel_cdclk_state logical
;
350 * Actual state of cdclk, can be different from the logical
351 * state only when all crtc's are DPMS off.
353 struct intel_cdclk_state actual
;
356 bool dpll_set
, modeset
;
359 * Does this transaction change the pipes that are active? This mask
360 * tracks which CRTC's have changed their active state at the end of
361 * the transaction (not counting the temporary disable during modesets).
362 * This mask should only be non-zero when intel_state->modeset is true,
363 * but the converse is not necessarily true; simply changing a mode may
364 * not flip the final active status of any CRTC's
366 unsigned int active_pipe_changes
;
368 unsigned int active_crtcs
;
369 unsigned int min_pixclk
[I915_MAX_PIPES
];
371 struct intel_shared_dpll_state shared_dpll
[I915_NUM_PLLS
];
374 * Current watermarks can't be trusted during hardware readout, so
375 * don't bother calculating intermediate watermarks.
377 bool skip_intermediate_wm
;
380 struct skl_wm_values wm_results
;
382 struct i915_sw_fence commit_ready
;
384 struct llist_node freed
;
387 struct intel_plane_state
{
388 struct drm_plane_state base
;
389 struct drm_rect clip
;
390 struct i915_vma
*vma
;
401 /* plane control register */
406 * = -1 : not using a scaler
407 * >= 0 : using a scalers
409 * plane requiring a scaler:
410 * - During check_plane, its bit is set in
411 * crtc_state->scaler_state.scaler_users by calling helper function
412 * update_scaler_plane.
413 * - scaler_id indicates the scaler it got assigned.
415 * plane doesn't require a scaler:
416 * - this can happen when scaling is no more required or plane simply
418 * - During check_plane, corresponding bit is reset in
419 * crtc_state->scaler_state.scaler_users by calling helper function
420 * update_scaler_plane.
424 struct drm_intel_sprite_colorkey ckey
;
427 struct intel_initial_plane_config
{
428 struct intel_framebuffer
*fb
;
434 #define SKL_MIN_SRC_W 8
435 #define SKL_MAX_SRC_W 4096
436 #define SKL_MIN_SRC_H 8
437 #define SKL_MAX_SRC_H 4096
438 #define SKL_MIN_DST_W 8
439 #define SKL_MAX_DST_W 4096
440 #define SKL_MIN_DST_H 8
441 #define SKL_MAX_DST_H 4096
443 struct intel_scaler
{
448 struct intel_crtc_scaler_state
{
449 #define SKL_NUM_SCALERS 2
450 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
453 * scaler_users: keeps track of users requesting scalers on this crtc.
455 * If a bit is set, a user is using a scaler.
456 * Here user can be a plane or crtc as defined below:
457 * bits 0-30 - plane (bit position is index from drm_plane_index)
460 * Instead of creating a new index to cover planes and crtc, using
461 * existing drm_plane_index for planes which is well less than 31
462 * planes and bit 31 for crtc. This should be fine to cover all
465 * intel_atomic_setup_scalers will setup available scalers to users
466 * requesting scalers. It will gracefully fail if request exceeds
469 #define SKL_CRTC_INDEX 31
470 unsigned scaler_users
;
472 /* scaler used by crtc for panel fitting purpose */
476 /* drm_mode->private_flags */
477 #define I915_MODE_FLAG_INHERITED 1
479 struct intel_pipe_wm
{
480 struct intel_wm_level wm
[5];
481 struct intel_wm_level raw_wm
[5];
485 bool sprites_enabled
;
489 struct skl_plane_wm
{
490 struct skl_wm_level wm
[8];
491 struct skl_wm_level trans_wm
;
495 struct skl_plane_wm planes
[I915_MAX_PLANES
];
502 VLV_WM_LEVEL_DDR_DVFS
,
506 struct vlv_wm_state
{
507 struct vlv_pipe_wm wm
[NUM_VLV_WM_LEVELS
];
508 struct vlv_sr_wm sr
[NUM_VLV_WM_LEVELS
];
513 struct vlv_fifo_state
{
514 u16 plane
[I915_MAX_PLANES
];
517 struct intel_crtc_wm_state
{
521 * Intermediate watermarks; these can be
522 * programmed immediately since they satisfy
523 * both the current configuration we're
524 * switching away from and the new
525 * configuration we're switching to.
527 struct intel_pipe_wm intermediate
;
530 * Optimal watermarks, programmed post-vblank
531 * when this state is committed.
533 struct intel_pipe_wm optimal
;
537 /* gen9+ only needs 1-step wm programming */
538 struct skl_pipe_wm optimal
;
539 struct skl_ddb_entry ddb
;
543 /* "raw" watermarks (not inverted) */
544 struct vlv_pipe_wm raw
[NUM_VLV_WM_LEVELS
];
545 /* intermediate watermarks (inverted) */
546 struct vlv_wm_state intermediate
;
547 /* optimal watermarks (inverted) */
548 struct vlv_wm_state optimal
;
549 /* display FIFO split */
550 struct vlv_fifo_state fifo_state
;
555 * Platforms with two-step watermark programming will need to
556 * update watermark programming post-vblank to switch from the
557 * safe intermediate watermarks to the optimal final
560 bool need_postvbl_update
;
563 struct intel_crtc_state
{
564 struct drm_crtc_state base
;
567 * quirks - bitfield with hw state readout quirks
569 * For various reasons the hw state readout code might not be able to
570 * completely faithfully read out the current state. These cases are
571 * tracked with quirk flags so that fastboot and state checker can act
574 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
575 unsigned long quirks
;
577 unsigned fb_bits
; /* framebuffers to flip */
578 bool update_pipe
; /* can a fast modeset be performed? */
580 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
581 bool fb_changed
; /* fb on any of the planes is changed */
582 bool fifo_changed
; /* FIFO split is changed */
584 /* Pipe source size (ie. panel fitter input size)
585 * All planes will be positioned inside this space,
586 * and get clipped at the edges. */
587 int pipe_src_w
, pipe_src_h
;
590 * Pipe pixel rate, adjusted for
591 * panel fitter/pipe scaler downscaling.
593 unsigned int pixel_rate
;
595 /* Whether to set up the PCH/FDI. Note that we never allow sharing
596 * between pch encoders and cpu encoders. */
597 bool has_pch_encoder
;
599 /* Are we sending infoframes on the attached port */
602 /* CPU Transcoder for the pipe. Currently this can only differ from the
603 * pipe on Haswell and later (where we have a special eDP transcoder)
604 * and Broxton (where we have special DSI transcoders). */
605 enum transcoder cpu_transcoder
;
608 * Use reduced/limited/broadcast rbg range, compressing from the full
609 * range fed into the crtcs.
611 bool limited_color_range
;
613 /* Bitmask of encoder types (enum intel_output_type)
614 * driven by the pipe.
616 unsigned int output_types
;
618 /* Whether we should send NULL infoframes. Required for audio. */
621 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
622 * has_dp_encoder is set. */
626 * Enable dithering, used when the selected pipe bpp doesn't match the
632 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
633 * compliance video pattern tests.
634 * Disable dither only if it is a compliance test request for
637 bool dither_force_disable
;
639 /* Controls for the clock computation, to override various stages. */
642 /* SDVO TV has a bunch of special case. To make multifunction encoders
643 * work correctly, we need to track this at runtime.*/
647 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
648 * required. This is set in the 2nd loop of calling encoder's
649 * ->compute_config if the first pick doesn't work out.
653 /* Settings for the intel dpll used on pretty much everything but
657 /* Selected dpll when shared or NULL. */
658 struct intel_shared_dpll
*shared_dpll
;
660 /* Actual register state of the dpll, for shared dpll cross-checking. */
661 struct intel_dpll_hw_state dpll_hw_state
;
663 /* DSI PLL registers */
669 struct intel_link_m_n dp_m_n
;
671 /* m2_n2 for eDP downclock */
672 struct intel_link_m_n dp_m2_n2
;
676 * Frequence the dpll for the port should run at. Differs from the
677 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
678 * already multiplied by pixel_multiplier.
682 /* Used by SDVO (and if we ever fix it, HDMI). */
683 unsigned pixel_multiplier
;
688 * Used by platforms having DP/HDMI PHY with programmable lane
689 * latency optimization.
691 uint8_t lane_lat_optim_mask
;
693 /* Panel fitter controls for gen2-gen4 + VLV */
697 u32 lvds_border_bits
;
700 /* Panel fitter placement and size for Ironlake+ */
708 /* FDI configuration, only valid if has_pch_encoder is set. */
710 struct intel_link_m_n fdi_m_n
;
720 struct intel_crtc_scaler_state scaler_state
;
722 /* w/a for waiting 2 vblanks during crtc enable */
723 enum pipe hsw_workaround_pipe
;
725 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
728 struct intel_crtc_wm_state wm
;
730 /* Gamma mode programmed on the pipe */
733 /* bitmask of visible planes (enum plane_id) */
736 /* HDMI scrambling status */
737 bool hdmi_scrambling
;
739 /* HDMI High TMDS char rate ratio */
740 bool hdmi_high_tmds_clock_ratio
;
744 struct drm_crtc base
;
747 u8 lut_r
[256], lut_g
[256], lut_b
[256];
749 * Whether the crtc and the connected output pipeline is active. Implies
750 * that crtc->enabled is set, i.e. the current mode configuration has
751 * some outputs connected to this crtc.
756 unsigned long long enabled_power_domains
;
757 struct intel_overlay
*overlay
;
758 struct intel_flip_work
*flip_work
;
760 atomic_t unpin_work_count
;
762 /* Display surface base address adjustement for pageflips. Note that on
763 * gen4+ this only adjusts up to a tile, offsets within a tile are
764 * handled in the hw itself (with the TILEOFF register). */
769 uint32_t cursor_addr
;
770 uint32_t cursor_cntl
;
771 uint32_t cursor_size
;
772 uint32_t cursor_base
;
774 struct intel_crtc_state
*config
;
776 /* global reset count when the last flip was submitted */
777 unsigned int reset_count
;
779 /* Access to these should be protected by dev_priv->irq_lock. */
780 bool cpu_fifo_underrun_disabled
;
781 bool pch_fifo_underrun_disabled
;
783 /* per-pipe watermark state */
785 /* watermarks currently being used */
787 struct intel_pipe_wm ilk
;
788 struct vlv_wm_state vlv
;
795 unsigned start_vbl_count
;
796 ktime_t start_vbl_time
;
797 int min_vbl
, max_vbl
;
801 /* scalers available on this crtc */
806 struct drm_plane base
;
812 uint32_t frontbuffer_bit
;
815 * NOTE: Do not place new plane state fields here (e.g., when adding
816 * new plane properties). New runtime state should now be placed in
817 * the intel_plane_state structure and accessed via plane_state.
820 void (*update_plane
)(struct drm_plane
*plane
,
821 const struct intel_crtc_state
*crtc_state
,
822 const struct intel_plane_state
*plane_state
);
823 void (*disable_plane
)(struct drm_plane
*plane
,
824 struct drm_crtc
*crtc
);
825 int (*check_plane
)(struct drm_plane
*plane
,
826 struct intel_crtc_state
*crtc_state
,
827 struct intel_plane_state
*state
);
830 struct intel_watermark_params
{
838 struct cxsr_latency
{
844 u16 display_hpll_disable
;
846 u16 cursor_hpll_disable
;
849 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
850 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
851 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
852 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
853 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
854 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
855 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
856 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
857 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
863 enum drm_dp_dual_mode_type type
;
866 bool limited_color_range
;
867 bool color_range_auto
;
870 enum hdmi_force_audio force_audio
;
871 bool rgb_quant_range_selectable
;
872 enum hdmi_picture_aspect aspect_ratio
;
873 struct intel_connector
*attached_connector
;
874 void (*write_infoframe
)(struct drm_encoder
*encoder
,
875 const struct intel_crtc_state
*crtc_state
,
876 enum hdmi_infoframe_type type
,
877 const void *frame
, ssize_t len
);
878 void (*set_infoframes
)(struct drm_encoder
*encoder
,
880 const struct intel_crtc_state
*crtc_state
,
881 const struct drm_connector_state
*conn_state
);
882 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
883 const struct intel_crtc_state
*pipe_config
);
886 struct intel_dp_mst_encoder
;
887 #define DP_MAX_DOWNSTREAM_PORTS 0x10
891 * When platform provides two set of M_N registers for dp, we can
892 * program them and switch between them incase of DRRS.
893 * But When only one such register is provided, we have to program the
894 * required divider value on that registers itself based on the DRRS state.
896 * M1_N1 : Program dp_m_n on M1_N1 registers
897 * dp_m2_n2 on M2_N2 registers (If supported)
899 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
900 * M2_N2 registers are not supported
904 /* Sets the m1_n1 and m2_n2 */
909 struct intel_dp_desc
{
917 struct intel_dp_compliance_data
{
919 uint8_t video_pattern
;
920 uint16_t hdisplay
, vdisplay
;
924 struct intel_dp_compliance
{
925 unsigned long test_type
;
926 struct intel_dp_compliance_data test_data
;
933 i915_reg_t output_reg
;
934 i915_reg_t aux_ch_ctl_reg
;
935 i915_reg_t aux_ch_data_reg
[5];
943 bool channel_eq_status
;
944 bool reset_link_params
;
945 enum hdmi_force_audio force_audio
;
946 bool limited_color_range
;
947 bool color_range_auto
;
948 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
949 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
950 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
951 uint8_t edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
953 int num_source_rates
;
954 const int *source_rates
;
955 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
957 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
958 bool use_rate_select
;
959 /* intersection of source and sink rates */
960 int num_common_rates
;
961 int common_rates
[DP_MAX_SUPPORTED_RATES
];
962 /* Max lane count for the sink as per DPCD registers */
963 uint8_t max_sink_lane_count
;
964 /* Max link BW for the sink as per DPCD registers */
965 int max_sink_link_rate
;
966 /* sink or branch descriptor */
967 struct intel_dp_desc desc
;
968 struct drm_dp_aux aux
;
969 enum intel_display_power_domain aux_power_domain
;
970 uint8_t train_set
[4];
971 int panel_power_up_delay
;
972 int panel_power_down_delay
;
973 int panel_power_cycle_delay
;
974 int backlight_on_delay
;
975 int backlight_off_delay
;
976 struct delayed_work panel_vdd_work
;
978 unsigned long last_power_on
;
979 unsigned long last_backlight_off
;
980 ktime_t panel_power_off_time
;
982 struct notifier_block edp_notifier
;
985 * Pipe whose power sequencer is currently locked into
986 * this port. Only relevant on VLV/CHV.
990 * Pipe currently driving the port. Used for preventing
991 * the use of the PPS for any pipe currentrly driving
992 * external DP as that will mess things up on VLV.
994 enum pipe active_pipe
;
996 * Set if the sequencer may be reset due to a power transition,
997 * requiring a reinitialization. Only relevant on BXT.
1000 struct edp_power_seq pps_delays
;
1002 bool can_mst
; /* this port supports mst */
1004 int active_mst_links
;
1005 /* connector directly attached - won't be use for modeset in mst world */
1006 struct intel_connector
*attached_connector
;
1008 /* mst connector list */
1009 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
1010 struct drm_dp_mst_topology_mgr mst_mgr
;
1012 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
1014 * This function returns the value we have to program the AUX_CTL
1015 * register with to kick off an AUX transaction.
1017 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
1020 uint32_t aux_clock_divider
);
1022 /* This is called before a link training is starterd */
1023 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
1025 /* Displayport compliance testing */
1026 struct intel_dp_compliance compliance
;
1029 struct intel_lspcon
{
1031 enum drm_lspcon_mode mode
;
1034 struct intel_digital_port
{
1035 struct intel_encoder base
;
1037 u32 saved_port_bits
;
1039 struct intel_hdmi hdmi
;
1040 struct intel_lspcon lspcon
;
1041 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
1042 bool release_cl2_override
;
1044 enum intel_display_power_domain ddi_io_power_domain
;
1047 struct intel_dp_mst_encoder
{
1048 struct intel_encoder base
;
1050 struct intel_digital_port
*primary
;
1051 struct intel_connector
*connector
;
1054 static inline enum dpio_channel
1055 vlv_dport_to_channel(struct intel_digital_port
*dport
)
1057 switch (dport
->port
) {
1068 static inline enum dpio_phy
1069 vlv_dport_to_phy(struct intel_digital_port
*dport
)
1071 switch (dport
->port
) {
1082 static inline enum dpio_channel
1083 vlv_pipe_to_channel(enum pipe pipe
)
1096 static inline struct intel_crtc
*
1097 intel_get_crtc_for_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1099 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1102 static inline struct intel_crtc
*
1103 intel_get_crtc_for_plane(struct drm_i915_private
*dev_priv
, enum plane plane
)
1105 return dev_priv
->plane_to_crtc_mapping
[plane
];
1108 struct intel_flip_work
{
1109 struct work_struct unpin_work
;
1110 struct work_struct mmio_work
;
1112 struct drm_crtc
*crtc
;
1113 struct i915_vma
*old_vma
;
1114 struct drm_framebuffer
*old_fb
;
1115 struct drm_i915_gem_object
*pending_flip_obj
;
1116 struct drm_pending_vblank_event
*event
;
1120 struct drm_i915_gem_request
*flip_queued_req
;
1121 u32 flip_queued_vblank
;
1122 u32 flip_ready_vblank
;
1123 unsigned int rotation
;
1126 struct intel_load_detect_pipe
{
1127 struct drm_atomic_state
*restore_state
;
1130 static inline struct intel_encoder
*
1131 intel_attached_encoder(struct drm_connector
*connector
)
1133 return to_intel_connector(connector
)->encoder
;
1136 static inline struct intel_digital_port
*
1137 enc_to_dig_port(struct drm_encoder
*encoder
)
1139 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1141 switch (intel_encoder
->type
) {
1142 case INTEL_OUTPUT_UNKNOWN
:
1143 WARN_ON(!HAS_DDI(to_i915(encoder
->dev
)));
1144 case INTEL_OUTPUT_DP
:
1145 case INTEL_OUTPUT_EDP
:
1146 case INTEL_OUTPUT_HDMI
:
1147 return container_of(encoder
, struct intel_digital_port
,
1154 static inline struct intel_dp_mst_encoder
*
1155 enc_to_mst(struct drm_encoder
*encoder
)
1157 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1160 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1162 return &enc_to_dig_port(encoder
)->dp
;
1165 static inline struct intel_digital_port
*
1166 dp_to_dig_port(struct intel_dp
*intel_dp
)
1168 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1171 static inline struct intel_lspcon
*
1172 dp_to_lspcon(struct intel_dp
*intel_dp
)
1174 return &dp_to_dig_port(intel_dp
)->lspcon
;
1177 static inline struct intel_digital_port
*
1178 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1180 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1183 /* intel_fifo_underrun.c */
1184 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1185 enum pipe pipe
, bool enable
);
1186 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1187 enum transcoder pch_transcoder
,
1189 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1191 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1192 enum transcoder pch_transcoder
);
1193 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1194 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1197 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1198 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1199 void gen6_reset_pm_iir(struct drm_i915_private
*dev_priv
, u32 mask
);
1200 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1201 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1202 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1203 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1204 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1205 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1206 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1208 static inline u32
gen6_sanitize_rps_pm_mask(const struct drm_i915_private
*i915
,
1211 return mask
& ~i915
->rps
.pm_intrmsk_mbz
;
1214 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1215 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1216 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1219 * We only use drm_irq_uninstall() at unload and VT switch, so
1220 * this is the only thing we need to check.
1222 return dev_priv
->pm
.irqs_enabled
;
1225 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1226 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1227 unsigned int pipe_mask
);
1228 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1229 unsigned int pipe_mask
);
1230 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
);
1231 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1232 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1235 void intel_crt_init(struct drm_i915_private
*dev_priv
);
1236 void intel_crt_reset(struct drm_encoder
*encoder
);
1239 void intel_ddi_fdi_post_disable(struct intel_encoder
*intel_encoder
,
1240 struct intel_crtc_state
*old_crtc_state
,
1241 struct drm_connector_state
*old_conn_state
);
1242 void hsw_fdi_link_train(struct intel_crtc
*crtc
,
1243 const struct intel_crtc_state
*crtc_state
);
1244 void intel_ddi_init(struct drm_i915_private
*dev_priv
, enum port port
);
1245 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1246 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1247 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state
*crtc_state
);
1248 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1249 enum transcoder cpu_transcoder
);
1250 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1251 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1252 struct intel_encoder
*
1253 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1254 void intel_ddi_set_pipe_settings(const struct intel_crtc_state
*crtc_state
);
1255 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1256 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1257 bool intel_ddi_is_audio_enabled(struct drm_i915_private
*dev_priv
,
1258 struct intel_crtc
*intel_crtc
);
1259 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1260 struct intel_crtc_state
*pipe_config
);
1262 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1263 struct intel_crtc_state
*pipe_config
);
1264 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
*crtc_state
,
1266 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1267 u8
intel_ddi_dp_voltage_max(struct intel_encoder
*encoder
);
1269 unsigned int intel_fb_align_height(const struct drm_framebuffer
*fb
,
1270 int plane
, unsigned int height
);
1273 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1274 void intel_audio_codec_enable(struct intel_encoder
*encoder
,
1275 const struct intel_crtc_state
*crtc_state
,
1276 const struct drm_connector_state
*conn_state
);
1277 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1278 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1279 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1280 void intel_audio_init(struct drm_i915_private
*dev_priv
);
1281 void intel_audio_deinit(struct drm_i915_private
*dev_priv
);
1284 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1285 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1286 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1287 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1288 void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv
);
1289 void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
);
1290 void intel_update_cdclk(struct drm_i915_private
*dev_priv
);
1291 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1292 bool intel_cdclk_state_compare(const struct intel_cdclk_state
*a
,
1293 const struct intel_cdclk_state
*b
);
1294 void intel_set_cdclk(struct drm_i915_private
*dev_priv
,
1295 const struct intel_cdclk_state
*cdclk_state
);
1297 /* intel_display.c */
1298 enum transcoder
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
);
1299 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1300 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
);
1301 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1302 const char *name
, u32 reg
, int ref_freq
);
1303 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
1304 const char *name
, u32 reg
);
1305 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
);
1306 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
);
1307 extern const struct drm_plane_funcs intel_plane_funcs
;
1308 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1309 unsigned int intel_fb_xy_to_linear(int x
, int y
,
1310 const struct intel_plane_state
*state
,
1312 void intel_add_fb_offsets(int *x
, int *y
,
1313 const struct intel_plane_state
*state
, int plane
);
1314 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1315 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
);
1316 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1317 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1318 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
1319 int intel_display_suspend(struct drm_device
*dev
);
1320 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
);
1321 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1322 int intel_connector_init(struct intel_connector
*);
1323 struct intel_connector
*intel_connector_alloc(void);
1324 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1325 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1326 struct intel_encoder
*encoder
);
1327 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1328 struct drm_crtc
*crtc
);
1329 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1330 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1331 struct drm_file
*file_priv
);
1332 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1335 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1336 enum intel_output_type type
)
1338 return crtc_state
->output_types
& (1 << type
);
1341 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1343 return crtc_state
->output_types
&
1344 ((1 << INTEL_OUTPUT_DP
) |
1345 (1 << INTEL_OUTPUT_DP_MST
) |
1346 (1 << INTEL_OUTPUT_EDP
));
1349 intel_wait_for_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1351 drm_wait_one_vblank(&dev_priv
->drm
, pipe
);
1354 intel_wait_for_vblank_if_active(struct drm_i915_private
*dev_priv
, int pipe
)
1356 const struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1359 intel_wait_for_vblank(dev_priv
, pipe
);
1362 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1364 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1365 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1366 struct intel_digital_port
*dport
,
1367 unsigned int expected_mask
);
1368 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1369 struct drm_display_mode
*mode
,
1370 struct intel_load_detect_pipe
*old
,
1371 struct drm_modeset_acquire_ctx
*ctx
);
1372 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1373 struct intel_load_detect_pipe
*old
,
1374 struct drm_modeset_acquire_ctx
*ctx
);
1376 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
);
1377 void intel_unpin_fb_vma(struct i915_vma
*vma
);
1378 struct drm_framebuffer
*
1379 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
1380 struct drm_mode_fb_cmd2
*mode_cmd
);
1381 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
);
1382 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
);
1383 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
);
1384 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1385 struct drm_plane_state
*new_state
);
1386 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1387 struct drm_plane_state
*old_state
);
1388 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1389 const struct drm_plane_state
*state
,
1390 struct drm_property
*property
,
1392 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1393 struct drm_plane_state
*state
,
1394 struct drm_property
*property
,
1396 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1397 struct drm_plane_state
*plane_state
);
1399 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1402 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1403 const struct dpll
*dpll
);
1404 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1405 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1407 /* modesetting asserts */
1408 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1410 void assert_pll(struct drm_i915_private
*dev_priv
,
1411 enum pipe pipe
, bool state
);
1412 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1413 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1414 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1415 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1416 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1417 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1418 enum pipe pipe
, bool state
);
1419 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1420 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1421 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1422 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1423 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1424 u32
intel_compute_tile_offset(int *x
, int *y
,
1425 const struct intel_plane_state
*state
, int plane
);
1426 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1427 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1428 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1429 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1430 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1431 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1432 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1433 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1434 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1435 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1436 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1437 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1438 struct intel_crtc_state
*pipe_config
);
1439 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1440 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1441 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1442 struct dpll
*best_clock
);
1443 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1445 bool intel_crtc_active(struct intel_crtc
*crtc
);
1446 void hsw_enable_ips(struct intel_crtc
*crtc
);
1447 void hsw_disable_ips(struct intel_crtc
*crtc
);
1448 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
);
1449 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1450 struct intel_crtc_state
*pipe_config
);
1452 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1453 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1455 static inline u32
intel_plane_ggtt_offset(const struct intel_plane_state
*state
)
1457 return i915_ggtt_offset(state
->vma
);
1460 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
1461 const struct intel_plane_state
*plane_state
);
1462 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
1463 unsigned int rotation
);
1464 int skl_check_plane_surface(struct intel_plane_state
*plane_state
);
1465 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
);
1468 void intel_csr_ucode_init(struct drm_i915_private
*);
1469 void intel_csr_load_program(struct drm_i915_private
*);
1470 void intel_csr_ucode_fini(struct drm_i915_private
*);
1471 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1472 void intel_csr_ucode_resume(struct drm_i915_private
*);
1475 bool intel_dp_init(struct drm_i915_private
*dev_priv
, i915_reg_t output_reg
,
1477 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1478 struct intel_connector
*intel_connector
);
1479 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1480 int link_rate
, uint8_t lane_count
,
1482 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
1483 int link_rate
, uint8_t lane_count
);
1484 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1485 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1486 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1487 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1488 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1489 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1490 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1491 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1492 struct intel_crtc_state
*pipe_config
,
1493 struct drm_connector_state
*conn_state
);
1494 bool intel_dp_is_edp(struct drm_i915_private
*dev_priv
, enum port port
);
1495 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1497 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1498 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1499 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1500 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1501 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1502 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1503 void intel_dp_mst_suspend(struct drm_device
*dev
);
1504 void intel_dp_mst_resume(struct drm_device
*dev
);
1505 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1506 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1507 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1508 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1509 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1510 void intel_plane_destroy(struct drm_plane
*plane
);
1511 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
1512 struct intel_crtc_state
*crtc_state
);
1513 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
1514 struct intel_crtc_state
*crtc_state
);
1515 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
1516 unsigned int frontbuffer_bits
);
1517 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
1518 unsigned int frontbuffer_bits
);
1521 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1522 uint8_t dp_train_pat
);
1524 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1525 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1527 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1529 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1530 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1531 uint8_t *link_bw
, uint8_t *rate_select
);
1532 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1534 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1536 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1538 return ~((1 << lane_count
) - 1) & 0xf;
1541 bool intel_dp_read_dpcd(struct intel_dp
*intel_dp
);
1542 bool __intel_dp_read_desc(struct intel_dp
*intel_dp
,
1543 struct intel_dp_desc
*desc
);
1544 bool intel_dp_read_desc(struct intel_dp
*intel_dp
);
1545 int intel_dp_link_required(int pixel_clock
, int bpp
);
1546 int intel_dp_max_data_rate(int max_link_clock
, int max_lanes
);
1547 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1548 struct intel_digital_port
*port
);
1550 /* intel_dp_aux_backlight.c */
1551 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1553 /* intel_dp_mst.c */
1554 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1555 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1557 void intel_dsi_init(struct drm_i915_private
*dev_priv
);
1559 /* intel_dsi_dcs_backlight.c */
1560 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1563 void intel_dvo_init(struct drm_i915_private
*dev_priv
);
1564 /* intel_hotplug.c */
1565 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1568 /* legacy fbdev emulation in intel_fbdev.c */
1569 #ifdef CONFIG_DRM_FBDEV_EMULATION
1570 extern int intel_fbdev_init(struct drm_device
*dev
);
1571 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1572 extern void intel_fbdev_fini(struct drm_device
*dev
);
1573 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1574 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1575 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1577 static inline int intel_fbdev_init(struct drm_device
*dev
)
1582 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1586 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1590 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1594 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
1598 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1604 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1605 struct drm_atomic_state
*state
);
1606 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1607 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
1608 struct intel_crtc_state
*crtc_state
,
1609 struct intel_plane_state
*plane_state
);
1610 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1611 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1612 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1613 void intel_fbc_enable(struct intel_crtc
*crtc
,
1614 struct intel_crtc_state
*crtc_state
,
1615 struct intel_plane_state
*plane_state
);
1616 void intel_fbc_disable(struct intel_crtc
*crtc
);
1617 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1618 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1619 unsigned int frontbuffer_bits
,
1620 enum fb_op_origin origin
);
1621 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1622 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1623 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1624 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
);
1627 void intel_hdmi_init(struct drm_i915_private
*dev_priv
, i915_reg_t hdmi_reg
,
1629 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1630 struct intel_connector
*intel_connector
);
1631 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1632 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1633 struct intel_crtc_state
*pipe_config
,
1634 struct drm_connector_state
*conn_state
);
1635 void intel_hdmi_handle_sink_scrambling(struct intel_encoder
*intel_encoder
,
1636 struct drm_connector
*connector
,
1637 bool high_tmds_clock_ratio
,
1639 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
1643 void intel_lvds_init(struct drm_i915_private
*dev_priv
);
1644 struct intel_encoder
*intel_get_lvds_encoder(struct drm_device
*dev
);
1645 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1649 int intel_connector_update_modes(struct drm_connector
*connector
,
1651 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1652 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1653 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1654 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1657 /* intel_overlay.c */
1658 void intel_setup_overlay(struct drm_i915_private
*dev_priv
);
1659 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
);
1660 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1661 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1662 struct drm_file
*file_priv
);
1663 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1664 struct drm_file
*file_priv
);
1665 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1669 int intel_panel_init(struct intel_panel
*panel
,
1670 struct drm_display_mode
*fixed_mode
,
1671 struct drm_display_mode
*downclock_mode
);
1672 void intel_panel_fini(struct intel_panel
*panel
);
1673 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1674 struct drm_display_mode
*adjusted_mode
);
1675 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1676 struct intel_crtc_state
*pipe_config
,
1678 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1679 struct intel_crtc_state
*pipe_config
,
1681 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1682 u32 level
, u32 max
);
1683 int intel_panel_setup_backlight(struct drm_connector
*connector
,
1685 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1686 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1687 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1688 enum drm_connector_status
intel_panel_detect(struct drm_i915_private
*dev_priv
);
1689 extern struct drm_display_mode
*intel_find_panel_downclock(
1690 struct drm_i915_private
*dev_priv
,
1691 struct drm_display_mode
*fixed_mode
,
1692 struct drm_connector
*connector
);
1694 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1695 int intel_backlight_device_register(struct intel_connector
*connector
);
1696 void intel_backlight_device_unregister(struct intel_connector
*connector
);
1697 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1698 static int intel_backlight_device_register(struct intel_connector
*connector
)
1702 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
1705 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1709 void intel_psr_enable(struct intel_dp
*intel_dp
);
1710 void intel_psr_disable(struct intel_dp
*intel_dp
);
1711 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
1712 unsigned frontbuffer_bits
);
1713 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
1714 unsigned frontbuffer_bits
,
1715 enum fb_op_origin origin
);
1716 void intel_psr_init(struct drm_i915_private
*dev_priv
);
1717 void intel_psr_single_frame_update(struct drm_i915_private
*dev_priv
,
1718 unsigned frontbuffer_bits
);
1720 /* intel_runtime_pm.c */
1721 int intel_power_domains_init(struct drm_i915_private
*);
1722 void intel_power_domains_fini(struct drm_i915_private
*);
1723 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1724 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1725 void intel_power_domains_verify_state(struct drm_i915_private
*dev_priv
);
1726 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1727 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1728 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1730 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1732 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1733 enum intel_display_power_domain domain
);
1734 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1735 enum intel_display_power_domain domain
);
1736 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1737 enum intel_display_power_domain domain
);
1738 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1739 enum intel_display_power_domain domain
);
1740 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1741 enum intel_display_power_domain domain
);
1744 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1746 WARN_ONCE(dev_priv
->pm
.suspended
,
1747 "Device suspended during HW access\n");
1751 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1753 assert_rpm_device_not_suspended(dev_priv
);
1754 WARN_ONCE(!atomic_read(&dev_priv
->pm
.wakeref_count
),
1755 "RPM wakelock ref not held during HW access");
1759 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1760 * @dev_priv: i915 device instance
1762 * This function disable asserts that check if we hold an RPM wakelock
1763 * reference, while keeping the device-not-suspended checks still enabled.
1764 * It's meant to be used only in special circumstances where our rule about
1765 * the wakelock refcount wrt. the device power state doesn't hold. According
1766 * to this rule at any point where we access the HW or want to keep the HW in
1767 * an active state we must hold an RPM wakelock reference acquired via one of
1768 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1769 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1770 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1771 * users should avoid using this function.
1773 * Any calls to this function must have a symmetric call to
1774 * enable_rpm_wakeref_asserts().
1777 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1779 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1783 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1784 * @dev_priv: i915 device instance
1786 * This function re-enables the RPM assert checks after disabling them with
1787 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1788 * circumstances otherwise its use should be avoided.
1790 * Any calls to this function must have a symmetric call to
1791 * disable_rpm_wakeref_asserts().
1794 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1796 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1799 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1800 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1801 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1802 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1804 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1806 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1807 bool override
, unsigned int mask
);
1808 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1809 enum dpio_channel ch
, bool override
);
1813 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
);
1814 void intel_suspend_hw(struct drm_i915_private
*dev_priv
);
1815 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
);
1816 void intel_update_watermarks(struct intel_crtc
*crtc
);
1817 void intel_init_pm(struct drm_i915_private
*dev_priv
);
1818 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1819 void intel_pm_setup(struct drm_i915_private
*dev_priv
);
1820 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1821 void intel_gpu_ips_teardown(void);
1822 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
1823 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
1824 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
);
1825 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
1826 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
);
1827 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
1828 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
);
1829 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1830 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1831 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1832 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1833 struct intel_rps_client
*rps
,
1834 unsigned long submitted
);
1835 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
);
1836 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1837 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1838 void skl_wm_get_hw_state(struct drm_device
*dev
);
1839 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1840 struct skl_ddb_allocation
*ddb
/* out */);
1841 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
1842 struct skl_pipe_wm
*out
);
1843 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
);
1844 bool intel_can_enable_sagv(struct drm_atomic_state
*state
);
1845 int intel_enable_sagv(struct drm_i915_private
*dev_priv
);
1846 int intel_disable_sagv(struct drm_i915_private
*dev_priv
);
1847 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
1848 const struct skl_wm_level
*l2
);
1849 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
**entries
,
1850 const struct skl_ddb_entry
*ddb
,
1852 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1853 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
);
1854 static inline int intel_enable_rc6(void)
1856 return i915
.enable_rc6
;
1860 bool intel_sdvo_init(struct drm_i915_private
*dev_priv
,
1861 i915_reg_t reg
, enum port port
);
1864 /* intel_sprite.c */
1865 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
1867 struct intel_plane
*intel_sprite_plane_create(struct drm_i915_private
*dev_priv
,
1868 enum pipe pipe
, int plane
);
1869 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1870 struct drm_file
*file_priv
);
1871 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1872 void intel_pipe_update_end(struct intel_crtc
*crtc
, struct intel_flip_work
*work
);
1875 void intel_tv_init(struct drm_i915_private
*dev_priv
);
1877 /* intel_atomic.c */
1878 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1879 const struct drm_connector_state
*state
,
1880 struct drm_property
*property
,
1882 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1883 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1884 struct drm_crtc_state
*state
);
1885 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1886 void intel_atomic_state_clear(struct drm_atomic_state
*);
1888 static inline struct intel_crtc_state
*
1889 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1890 struct intel_crtc
*crtc
)
1892 struct drm_crtc_state
*crtc_state
;
1893 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1894 if (IS_ERR(crtc_state
))
1895 return ERR_CAST(crtc_state
);
1897 return to_intel_crtc_state(crtc_state
);
1900 static inline struct intel_crtc_state
*
1901 intel_atomic_get_existing_crtc_state(struct drm_atomic_state
*state
,
1902 struct intel_crtc
*crtc
)
1904 struct drm_crtc_state
*crtc_state
;
1906 crtc_state
= drm_atomic_get_existing_crtc_state(state
, &crtc
->base
);
1909 return to_intel_crtc_state(crtc_state
);
1914 static inline struct intel_plane_state
*
1915 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1916 struct intel_plane
*plane
)
1918 struct drm_plane_state
*plane_state
;
1920 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1922 return to_intel_plane_state(plane_state
);
1925 int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv
,
1926 struct intel_crtc
*intel_crtc
,
1927 struct intel_crtc_state
*crtc_state
);
1929 /* intel_atomic_plane.c */
1930 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1931 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1932 void intel_plane_destroy_state(struct drm_plane
*plane
,
1933 struct drm_plane_state
*state
);
1934 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1935 int intel_plane_atomic_check_with_state(struct intel_crtc_state
*crtc_state
,
1936 struct intel_plane_state
*intel_state
);
1939 void intel_color_init(struct drm_crtc
*crtc
);
1940 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
1941 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
1942 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
1944 /* intel_lspcon.c */
1945 bool lspcon_init(struct intel_digital_port
*intel_dig_port
);
1946 void lspcon_resume(struct intel_lspcon
*lspcon
);
1947 void lspcon_wait_pcon_mode(struct intel_lspcon
*lspcon
);
1949 /* intel_pipe_crc.c */
1950 int intel_pipe_crc_create(struct drm_minor
*minor
);
1951 #ifdef CONFIG_DEBUG_FS
1952 int intel_crtc_set_crc_source(struct drm_crtc
*crtc
, const char *source_name
,
1953 size_t *values_cnt
);
1955 #define intel_crtc_set_crc_source NULL
1957 extern const struct file_operations i915_display_crc_ctl_fops
;
1958 #endif /* __INTEL_DRV_H__ */