drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__;                                                      \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 if (COND) {                                             \
  59                         ret__ = 0;                                      \
  60                         break;                                          \
  61                 }                                                       \
  62                 if (expired__) {                                        \
  63                         ret__ = -ETIMEDOUT;                             \
  64                         break;                                          \
  65                 }                                                       \
  66                 if ((W) && drm_can_sleep()) {                           \
  67                         usleep_range((W), (W)*2);                       \
  68                 } else {                                                \
  69                         cpu_relax();                                    \
  70                 }                                                       \
  71         }                                                               \
  72         ret__;                                                          \
  73 })
  74
  75 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  76
  77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  80 #else
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  82 #endif
  83
  84 #define _wait_for_atomic(COND, US, ATOMIC) \
  85 ({ \
  86         int cpu, ret, timeout = (US) * 1000; \
  87         u64 base; \
  88         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  89         BUILD_BUG_ON((US) > 50000); \
  90         if (!(ATOMIC)) { \
  91                 preempt_disable(); \
  92                 cpu = smp_processor_id(); \
  93         } \
  94         base = local_clock(); \
  95         for (;;) { \
  96                 u64 now = local_clock(); \
  97                 if (!(ATOMIC)) \
  98                         preempt_enable(); \
  99                 if (COND) { \
 100                         ret = 0; \
 101                         break; \
 102                 } \
 103                 if (now - base >= timeout) { \
 104                         ret = -ETIMEDOUT; \
 105                         break; \
 106                 } \
 107                 cpu_relax(); \
 108                 if (!(ATOMIC)) { \
 109                         preempt_disable(); \
 110                         if (unlikely(cpu != smp_processor_id())) { \
 111                                 timeout -= now - base; \
 112                                 cpu = smp_processor_id(); \
 113                                 base = local_clock(); \
 114                         } \
 115                 } \
 116         } \
 117         ret; \
 118 })
 119
 120 #define wait_for_us(COND, US) \
 121 ({ \
 122         int ret__; \
 123         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 124         if ((US) > 10) \
 125                 ret__ = _wait_for((COND), (US), 10); \
 126         else \
 127                 ret__ = _wait_for_atomic((COND), (US), 0); \
 128         ret__; \
 129 })
 130
 131 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 132 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 133
 134 #define KHz(x) (1000 * (x))
 135 #define MHz(x) KHz(1000 * (x))
 136
 137 /*
 138  * Display related stuff
 139  */
 140
 141 /* store information about an Ixxx DVO */
 142 /* The i830->i865 use multiple DVOs with multiple i2cs */
 143 /* the i915, i945 have a single sDVO i2c bus - which is different */
 144 #define MAX_OUTPUTS 6
 145 /* maximum connectors per crtcs in the mode set */
 146
 147 /* Maximum cursor sizes */
 148 #define GEN2_CURSOR_WIDTH 64
 149 #define GEN2_CURSOR_HEIGHT 64
 150 #define MAX_CURSOR_WIDTH 256
 151 #define MAX_CURSOR_HEIGHT 256
 152
 153 #define INTEL_I2C_BUS_DVO 1
 154 #define INTEL_I2C_BUS_SDVO 2
 155
 156 /* these are outputs from the chip - integrated only
 157    external chips are via DVO or SDVO output */
 158 enum intel_output_type {
 159         INTEL_OUTPUT_UNUSED = 0,
 160         INTEL_OUTPUT_ANALOG = 1,
 161         INTEL_OUTPUT_DVO = 2,
 162         INTEL_OUTPUT_SDVO = 3,
 163         INTEL_OUTPUT_LVDS = 4,
 164         INTEL_OUTPUT_TVOUT = 5,
 165         INTEL_OUTPUT_HDMI = 6,
 166         INTEL_OUTPUT_DP = 7,
 167         INTEL_OUTPUT_EDP = 8,
 168         INTEL_OUTPUT_DSI = 9,
 169         INTEL_OUTPUT_UNKNOWN = 10,
 170         INTEL_OUTPUT_DP_MST = 11,
 171 };
 172
 173 #define INTEL_DVO_CHIP_NONE 0
 174 #define INTEL_DVO_CHIP_LVDS 1
 175 #define INTEL_DVO_CHIP_TMDS 2
 176 #define INTEL_DVO_CHIP_TVOUT 4
 177
 178 #define INTEL_DSI_VIDEO_MODE    0
 179 #define INTEL_DSI_COMMAND_MODE  1
 180
 181 struct intel_framebuffer {
 182         struct drm_framebuffer base;
 183         struct drm_i915_gem_object *obj;
 184         struct intel_rotation_info rot_info;
 185
 186         /* for each plane in the normal GTT view */
 187         struct {
 188                 unsigned int x, y;
 189         } normal[2];
 190         /* for each plane in the rotated GTT view */
 191         struct {
 192                 unsigned int x, y;
 193                 unsigned int pitch; /* pixels */
 194         } rotated[2];
 195 };
 196
 197 struct intel_fbdev {
 198         struct drm_fb_helper helper;
 199         struct intel_framebuffer *fb;
 200         struct i915_vma *vma;
 201         async_cookie_t cookie;
 202         int preferred_bpp;
 203 };
 204
 205 struct intel_encoder {
 206         struct drm_encoder base;
 207
 208         enum intel_output_type type;
 209         enum port port;
 210         unsigned int cloneable;
 211         void (*hot_plug)(struct intel_encoder *);
 212         bool (*compute_config)(struct intel_encoder *,
 213                                struct intel_crtc_state *,
 214                                struct drm_connector_state *);
 215         void (*pre_pll_enable)(struct intel_encoder *,
 216                                struct intel_crtc_state *,
 217                                struct drm_connector_state *);
 218         void (*pre_enable)(struct intel_encoder *,
 219                            struct intel_crtc_state *,
 220                            struct drm_connector_state *);
 221         void (*enable)(struct intel_encoder *,
 222                        struct intel_crtc_state *,
 223                        struct drm_connector_state *);
 224         void (*disable)(struct intel_encoder *,
 225                         struct intel_crtc_state *,
 226                         struct drm_connector_state *);
 227         void (*post_disable)(struct intel_encoder *,
 228                              struct intel_crtc_state *,
 229                              struct drm_connector_state *);
 230         void (*post_pll_disable)(struct intel_encoder *,
 231                                  struct intel_crtc_state *,
 232                                  struct drm_connector_state *);
 233         /* Read out the current hw state of this connector, returning true if
 234          * the encoder is active. If the encoder is enabled it also set the pipe
 235          * it is connected to in the pipe parameter. */
 236         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 237         /* Reconstructs the equivalent mode flags for the current hardware
 238          * state. This must be called _after_ display->get_pipe_config has
 239          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 240          * be set correctly before calling this function. */
 241         void (*get_config)(struct intel_encoder *,
 242                            struct intel_crtc_state *pipe_config);
 243         /*
 244          * Called during system suspend after all pending requests for the
 245          * encoder are flushed (for example for DP AUX transactions) and
 246          * device interrupts are disabled.
 247          */
 248         void (*suspend)(struct intel_encoder *);
 249         int crtc_mask;
 250         enum hpd_pin hpd_pin;
 251         /* for communication with audio component; protected by av_mutex */
 252         const struct drm_connector *audio_connector;
 253 };
 254
 255 struct intel_panel {
 256         struct drm_display_mode *fixed_mode;
 257         struct drm_display_mode *downclock_mode;
 258         int fitting_mode;
 259
 260         /* backlight */
 261         struct {
 262                 bool present;
 263                 u32 level;
 264                 u32 min;
 265                 u32 max;
 266                 bool enabled;
 267                 bool combination_mode;  /* gen 2/4 only */
 268                 bool active_low_pwm;
 269                 bool alternate_pwm_increment;   /* lpt+ */
 270
 271                 /* PWM chip */
 272                 bool util_pin_active_low;       /* bxt+ */
 273                 u8 controller;          /* bxt+ only */
 274                 struct pwm_device *pwm;
 275
 276                 struct backlight_device *device;
 277
 278                 /* Connector and platform specific backlight functions */
 279                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 280                 uint32_t (*get)(struct intel_connector *connector);
 281                 void (*set)(struct intel_connector *connector, uint32_t level);
 282                 void (*disable)(struct intel_connector *connector);
 283                 void (*enable)(struct intel_connector *connector);
 284                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 285                                       uint32_t hz);
 286                 void (*power)(struct intel_connector *, bool enable);
 287         } backlight;
 288 };
 289
 290 struct intel_connector {
 291         struct drm_connector base;
 292         /*
 293          * The fixed encoder this connector is connected to.
 294          */
 295         struct intel_encoder *encoder;
 296
 297         /* Reads out the current hw, returning true if the connector is enabled
 298          * and active (i.e. dpms ON state). */
 299         bool (*get_hw_state)(struct intel_connector *);
 300
 301         /* Panel info for eDP and LVDS */
 302         struct intel_panel panel;
 303
 304         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 305         struct edid *edid;
 306         struct edid *detect_edid;
 307
 308         /* since POLL and HPD connectors may use the same HPD line keep the native
 309            state of connector->polled in case hotplug storm detection changes it */
 310         u8 polled;
 311
 312         void *port; /* store this opaque as its illegal to dereference it */
 313
 314         struct intel_dp *mst_port;
 315 };
 316
 317 struct dpll {
 318         /* given values */
 319         int n;
 320         int m1, m2;
 321         int p1, p2;
 322         /* derived values */
 323         int     dot;
 324         int     vco;
 325         int     m;
 326         int     p;
 327 };
 328
 329 struct intel_atomic_state {
 330         struct drm_atomic_state base;
 331
 332         unsigned int cdclk;
 333
 334         /*
 335          * Calculated device cdclk, can be different from cdclk
 336          * only when all crtc's are DPMS off.
 337          */
 338         unsigned int dev_cdclk;
 339
 340         bool dpll_set, modeset;
 341
 342         /*
 343          * Does this transaction change the pipes that are active?  This mask
 344          * tracks which CRTC's have changed their active state at the end of
 345          * the transaction (not counting the temporary disable during modesets).
 346          * This mask should only be non-zero when intel_state->modeset is true,
 347          * but the converse is not necessarily true; simply changing a mode may
 348          * not flip the final active status of any CRTC's
 349          */
 350         unsigned int active_pipe_changes;
 351
 352         unsigned int active_crtcs;
 353         unsigned int min_pixclk[I915_MAX_PIPES];
 354
 355         /* SKL/KBL Only */
 356         unsigned int cdclk_pll_vco;
 357
 358         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 359
 360         /*
 361          * Current watermarks can't be trusted during hardware readout, so
 362          * don't bother calculating intermediate watermarks.
 363          */
 364         bool skip_intermediate_wm;
 365
 366         /* Gen9+ only */
 367         struct skl_wm_values wm_results;
 368 };
 369
 370 struct intel_plane_state {
 371         struct drm_plane_state base;
 372         struct drm_rect clip;
 373
 374         struct {
 375                 u32 offset;
 376                 int x, y;
 377         } main;
 378         struct {
 379                 u32 offset;
 380                 int x, y;
 381         } aux;
 382
 383         /*
 384          * scaler_id
 385          *    = -1 : not using a scaler
 386          *    >=  0 : using a scalers
 387          *
 388          * plane requiring a scaler:
 389          *   - During check_plane, its bit is set in
 390          *     crtc_state->scaler_state.scaler_users by calling helper function
 391          *     update_scaler_plane.
 392          *   - scaler_id indicates the scaler it got assigned.
 393          *
 394          * plane doesn't require a scaler:
 395          *   - this can happen when scaling is no more required or plane simply
 396          *     got disabled.
 397          *   - During check_plane, corresponding bit is reset in
 398          *     crtc_state->scaler_state.scaler_users by calling helper function
 399          *     update_scaler_plane.
 400          */
 401         int scaler_id;
 402
 403         struct drm_intel_sprite_colorkey ckey;
 404
 405         /* async flip related structures */
 406         struct drm_i915_gem_request *wait_req;
 407 };
 408
 409 struct intel_initial_plane_config {
 410         struct intel_framebuffer *fb;
 411         unsigned int tiling;
 412         int size;
 413         u32 base;
 414 };
 415
 416 #define SKL_MIN_SRC_W 8
 417 #define SKL_MAX_SRC_W 4096
 418 #define SKL_MIN_SRC_H 8
 419 #define SKL_MAX_SRC_H 4096
 420 #define SKL_MIN_DST_W 8
 421 #define SKL_MAX_DST_W 4096
 422 #define SKL_MIN_DST_H 8
 423 #define SKL_MAX_DST_H 4096
 424
 425 struct intel_scaler {
 426         int in_use;
 427         uint32_t mode;
 428 };
 429
 430 struct intel_crtc_scaler_state {
 431 #define SKL_NUM_SCALERS 2
 432         struct intel_scaler scalers[SKL_NUM_SCALERS];
 433
 434         /*
 435          * scaler_users: keeps track of users requesting scalers on this crtc.
 436          *
 437          *     If a bit is set, a user is using a scaler.
 438          *     Here user can be a plane or crtc as defined below:
 439          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 440          *       bit 31    - crtc
 441          *
 442          * Instead of creating a new index to cover planes and crtc, using
 443          * existing drm_plane_index for planes which is well less than 31
 444          * planes and bit 31 for crtc. This should be fine to cover all
 445          * our platforms.
 446          *
 447          * intel_atomic_setup_scalers will setup available scalers to users
 448          * requesting scalers. It will gracefully fail if request exceeds
 449          * avilability.
 450          */
 451 #define SKL_CRTC_INDEX 31
 452         unsigned scaler_users;
 453
 454         /* scaler used by crtc for panel fitting purpose */
 455         int scaler_id;
 456 };
 457
 458 /* drm_mode->private_flags */
 459 #define I915_MODE_FLAG_INHERITED 1
 460
 461 struct intel_pipe_wm {
 462         struct intel_wm_level wm[5];
 463         struct intel_wm_level raw_wm[5];
 464         uint32_t linetime;
 465         bool fbc_wm_enabled;
 466         bool pipe_enabled;
 467         bool sprites_enabled;
 468         bool sprites_scaled;
 469 };
 470
 471 struct skl_plane_wm {
 472         struct skl_wm_level wm[8];
 473         struct skl_wm_level trans_wm;
 474 };
 475
 476 struct skl_pipe_wm {
 477         struct skl_plane_wm planes[I915_MAX_PLANES];
 478         uint32_t linetime;
 479 };
 480
 481 struct intel_crtc_wm_state {
 482         union {
 483                 struct {
 484                         /*
 485                          * Intermediate watermarks; these can be
 486                          * programmed immediately since they satisfy
 487                          * both the current configuration we're
 488                          * switching away from and the new
 489                          * configuration we're switching to.
 490                          */
 491                         struct intel_pipe_wm intermediate;
 492
 493                         /*
 494                          * Optimal watermarks, programmed post-vblank
 495                          * when this state is committed.
 496                          */
 497                         struct intel_pipe_wm optimal;
 498                 } ilk;
 499
 500                 struct {
 501                         /* gen9+ only needs 1-step wm programming */
 502                         struct skl_pipe_wm optimal;
 503                         struct skl_ddb_entry ddb;
 504
 505                         /* cached plane data rate */
 506                         unsigned plane_data_rate[I915_MAX_PLANES];
 507                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 508
 509                         /* minimum block allocation */
 510                         uint16_t minimum_blocks[I915_MAX_PLANES];
 511                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 512                 } skl;
 513         };
 514
 515         /*
 516          * Platforms with two-step watermark programming will need to
 517          * update watermark programming post-vblank to switch from the
 518          * safe intermediate watermarks to the optimal final
 519          * watermarks.
 520          */
 521         bool need_postvbl_update;
 522 };
 523
 524 struct intel_crtc_state {
 525         struct drm_crtc_state base;
 526
 527         /**
 528          * quirks - bitfield with hw state readout quirks
 529          *
 530          * For various reasons the hw state readout code might not be able to
 531          * completely faithfully read out the current state. These cases are
 532          * tracked with quirk flags so that fastboot and state checker can act
 533          * accordingly.
 534          */
 535 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 536         unsigned long quirks;
 537
 538         unsigned fb_bits; /* framebuffers to flip */
 539         bool update_pipe; /* can a fast modeset be performed? */
 540         bool disable_cxsr;
 541         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 542         bool fb_changed; /* fb on any of the planes is changed */
 543
 544         /* Pipe source size (ie. panel fitter input size)
 545          * All planes will be positioned inside this space,
 546          * and get clipped at the edges. */
 547         int pipe_src_w, pipe_src_h;
 548
 549         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 550          * between pch encoders and cpu encoders. */
 551         bool has_pch_encoder;
 552
 553         /* Are we sending infoframes on the attached port */
 554         bool has_infoframe;
 555
 556         /* CPU Transcoder for the pipe. Currently this can only differ from the
 557          * pipe on Haswell and later (where we have a special eDP transcoder)
 558          * and Broxton (where we have special DSI transcoders). */
 559         enum transcoder cpu_transcoder;
 560
 561         /*
 562          * Use reduced/limited/broadcast rbg range, compressing from the full
 563          * range fed into the crtcs.
 564          */
 565         bool limited_color_range;
 566
 567         /* Bitmask of encoder types (enum intel_output_type)
 568          * driven by the pipe.
 569          */
 570         unsigned int output_types;
 571
 572         /* Whether we should send NULL infoframes. Required for audio. */
 573         bool has_hdmi_sink;
 574
 575         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 576          * has_dp_encoder is set. */
 577         bool has_audio;
 578
 579         /*
 580          * Enable dithering, used when the selected pipe bpp doesn't match the
 581          * plane bpp.
 582          */
 583         bool dither;
 584
 585         /* Controls for the clock computation, to override various stages. */
 586         bool clock_set;
 587
 588         /* SDVO TV has a bunch of special case. To make multifunction encoders
 589          * work correctly, we need to track this at runtime.*/
 590         bool sdvo_tv_clock;
 591
 592         /*
 593          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 594          * required. This is set in the 2nd loop of calling encoder's
 595          * ->compute_config if the first pick doesn't work out.
 596          */
 597         bool bw_constrained;
 598
 599         /* Settings for the intel dpll used on pretty much everything but
 600          * haswell. */
 601         struct dpll dpll;
 602
 603         /* Selected dpll when shared or NULL. */
 604         struct intel_shared_dpll *shared_dpll;
 605
 606         /* Actual register state of the dpll, for shared dpll cross-checking. */
 607         struct intel_dpll_hw_state dpll_hw_state;
 608
 609         /* DSI PLL registers */
 610         struct {
 611                 u32 ctrl, div;
 612         } dsi_pll;
 613
 614         int pipe_bpp;
 615         struct intel_link_m_n dp_m_n;
 616
 617         /* m2_n2 for eDP downclock */
 618         struct intel_link_m_n dp_m2_n2;
 619         bool has_drrs;
 620
 621         /*
 622          * Frequence the dpll for the port should run at. Differs from the
 623          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 624          * already multiplied by pixel_multiplier.
 625          */
 626         int port_clock;
 627
 628         /* Used by SDVO (and if we ever fix it, HDMI). */
 629         unsigned pixel_multiplier;
 630
 631         uint8_t lane_count;
 632
 633         /*
 634          * Used by platforms having DP/HDMI PHY with programmable lane
 635          * latency optimization.
 636          */
 637         uint8_t lane_lat_optim_mask;
 638
 639         /* Panel fitter controls for gen2-gen4 + VLV */
 640         struct {
 641                 u32 control;
 642                 u32 pgm_ratios;
 643                 u32 lvds_border_bits;
 644         } gmch_pfit;
 645
 646         /* Panel fitter placement and size for Ironlake+ */
 647         struct {
 648                 u32 pos;
 649                 u32 size;
 650                 bool enabled;
 651                 bool force_thru;
 652         } pch_pfit;
 653
 654         /* FDI configuration, only valid if has_pch_encoder is set. */
 655         int fdi_lanes;
 656         struct intel_link_m_n fdi_m_n;
 657
 658         bool ips_enabled;
 659
 660         bool enable_fbc;
 661
 662         bool double_wide;
 663
 664         bool dp_encoder_is_mst;
 665         int pbn;
 666
 667         struct intel_crtc_scaler_state scaler_state;
 668
 669         /* w/a for waiting 2 vblanks during crtc enable */
 670         enum pipe hsw_workaround_pipe;
 671
 672         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 673         bool disable_lp_wm;
 674
 675         struct intel_crtc_wm_state wm;
 676
 677         /* Gamma mode programmed on the pipe */
 678         uint32_t gamma_mode;
 679 };
 680
 681 struct vlv_wm_state {
 682         struct vlv_pipe_wm wm[3];
 683         struct vlv_sr_wm sr[3];
 684         uint8_t num_active_planes;
 685         uint8_t num_levels;
 686         uint8_t level;
 687         bool cxsr;
 688 };
 689
 690 struct intel_crtc {
 691         struct drm_crtc base;
 692         enum pipe pipe;
 693         enum plane plane;
 694         u8 lut_r[256], lut_g[256], lut_b[256];
 695         /*
 696          * Whether the crtc and the connected output pipeline is active. Implies
 697          * that crtc->enabled is set, i.e. the current mode configuration has
 698          * some outputs connected to this crtc.
 699          */
 700         bool active;
 701         unsigned long enabled_power_domains;
 702         bool lowfreq_avail;
 703         struct intel_overlay *overlay;
 704         struct intel_flip_work *flip_work;
 705
 706         atomic_t unpin_work_count;
 707
 708         /* Display surface base address adjustement for pageflips. Note that on
 709          * gen4+ this only adjusts up to a tile, offsets within a tile are
 710          * handled in the hw itself (with the TILEOFF register). */
 711         u32 dspaddr_offset;
 712         int adjusted_x;
 713         int adjusted_y;
 714
 715         uint32_t cursor_addr;
 716         uint32_t cursor_cntl;
 717         uint32_t cursor_size;
 718         uint32_t cursor_base;
 719
 720         struct intel_crtc_state *config;
 721
 722         /* global reset count when the last flip was submitted */
 723         unsigned int reset_count;
 724
 725         /* Access to these should be protected by dev_priv->irq_lock. */
 726         bool cpu_fifo_underrun_disabled;
 727         bool pch_fifo_underrun_disabled;
 728
 729         /* per-pipe watermark state */
 730         struct {
 731                 /* watermarks currently being used  */
 732                 union {
 733                         struct intel_pipe_wm ilk;
 734                         struct skl_pipe_wm skl;
 735                 } active;
 736
 737                 /* allow CxSR on this pipe */
 738                 bool cxsr_allowed;
 739         } wm;
 740
 741         /* gen9+: ddb allocation currently being used */
 742         struct skl_ddb_entry hw_ddb;
 743
 744         int scanline_offset;
 745
 746         struct {
 747                 unsigned start_vbl_count;
 748                 ktime_t start_vbl_time;
 749                 int min_vbl, max_vbl;
 750                 int scanline_start;
 751         } debug;
 752
 753         /* scalers available on this crtc */
 754         int num_scalers;
 755
 756         struct vlv_wm_state wm_state;
 757 };
 758
 759 struct intel_plane_wm_parameters {
 760         uint32_t horiz_pixels;
 761         uint32_t vert_pixels;
 762         /*
 763          *   For packed pixel formats:
 764          *     bytes_per_pixel - holds bytes per pixel
 765          *   For planar pixel formats:
 766          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 767          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 768          */
 769         uint8_t bytes_per_pixel;
 770         uint8_t y_bytes_per_pixel;
 771         bool enabled;
 772         bool scaled;
 773         u64 tiling;
 774         unsigned int rotation;
 775         uint16_t fifo_size;
 776 };
 777
 778 struct intel_plane {
 779         struct drm_plane base;
 780         int plane;
 781         enum pipe pipe;
 782         bool can_scale;
 783         int max_downscale;
 784         uint32_t frontbuffer_bit;
 785
 786         /* Since we need to change the watermarks before/after
 787          * enabling/disabling the planes, we need to store the parameters here
 788          * as the other pieces of the struct may not reflect the values we want
 789          * for the watermark calculations. Currently only Haswell uses this.
 790          */
 791         struct intel_plane_wm_parameters wm;
 792
 793         /*
 794          * NOTE: Do not place new plane state fields here (e.g., when adding
 795          * new plane properties).  New runtime state should now be placed in
 796          * the intel_plane_state structure and accessed via plane_state.
 797          */
 798
 799         void (*update_plane)(struct drm_plane *plane,
 800                              const struct intel_crtc_state *crtc_state,
 801                              const struct intel_plane_state *plane_state);
 802         void (*disable_plane)(struct drm_plane *plane,
 803                               struct drm_crtc *crtc);
 804         int (*check_plane)(struct drm_plane *plane,
 805                            struct intel_crtc_state *crtc_state,
 806                            struct intel_plane_state *state);
 807 };
 808
 809 struct intel_watermark_params {
 810         u16 fifo_size;
 811         u16 max_wm;
 812         u8 default_wm;
 813         u8 guard_size;
 814         u8 cacheline_size;
 815 };
 816
 817 struct cxsr_latency {
 818         bool is_desktop : 1;
 819         bool is_ddr3 : 1;
 820         u16 fsb_freq;
 821         u16 mem_freq;
 822         u16 display_sr;
 823         u16 display_hpll_disable;
 824         u16 cursor_sr;
 825         u16 cursor_hpll_disable;
 826 };
 827
 828 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 829 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 830 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 831 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 832 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 833 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 834 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 835 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 836 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 837
 838 struct intel_hdmi {
 839         i915_reg_t hdmi_reg;
 840         int ddc_bus;
 841         struct {
 842                 enum drm_dp_dual_mode_type type;
 843                 int max_tmds_clock;
 844         } dp_dual_mode;
 845         bool limited_color_range;
 846         bool color_range_auto;
 847         bool has_hdmi_sink;
 848         bool has_audio;
 849         enum hdmi_force_audio force_audio;
 850         bool rgb_quant_range_selectable;
 851         enum hdmi_picture_aspect aspect_ratio;
 852         struct intel_connector *attached_connector;
 853         void (*write_infoframe)(struct drm_encoder *encoder,
 854                                 enum hdmi_infoframe_type type,
 855                                 const void *frame, ssize_t len);
 856         void (*set_infoframes)(struct drm_encoder *encoder,
 857                                bool enable,
 858                                const struct drm_display_mode *adjusted_mode);
 859         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 860                                   const struct intel_crtc_state *pipe_config);
 861 };
 862
 863 struct intel_dp_mst_encoder;
 864 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 865
 866 /*
 867  * enum link_m_n_set:
 868  *      When platform provides two set of M_N registers for dp, we can
 869  *      program them and switch between them incase of DRRS.
 870  *      But When only one such register is provided, we have to program the
 871  *      required divider value on that registers itself based on the DRRS state.
 872  *
 873  * M1_N1        : Program dp_m_n on M1_N1 registers
 874  *                        dp_m2_n2 on M2_N2 registers (If supported)
 875  *
 876  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 877  *                        M2_N2 registers are not supported
 878  */
 879
 880 enum link_m_n_set {
 881         /* Sets the m1_n1 and m2_n2 */
 882         M1_N1 = 0,
 883         M2_N2
 884 };
 885
 886 struct intel_dp {
 887         i915_reg_t output_reg;
 888         i915_reg_t aux_ch_ctl_reg;
 889         i915_reg_t aux_ch_data_reg[5];
 890         uint32_t DP;
 891         int link_rate;
 892         uint8_t lane_count;
 893         uint8_t sink_count;
 894         bool link_mst;
 895         bool has_audio;
 896         bool detect_done;
 897         bool channel_eq_status;
 898         enum hdmi_force_audio force_audio;
 899         bool limited_color_range;
 900         bool color_range_auto;
 901         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 902         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 903         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 904         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 905         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 906         uint8_t num_sink_rates;
 907         int sink_rates[DP_MAX_SUPPORTED_RATES];
 908         struct drm_dp_aux aux;
 909         uint8_t train_set[4];
 910         int panel_power_up_delay;
 911         int panel_power_down_delay;
 912         int panel_power_cycle_delay;
 913         int backlight_on_delay;
 914         int backlight_off_delay;
 915         struct delayed_work panel_vdd_work;
 916         bool want_panel_vdd;
 917         unsigned long last_power_on;
 918         unsigned long last_backlight_off;
 919         ktime_t panel_power_off_time;
 920
 921         struct notifier_block edp_notifier;
 922
 923         /*
 924          * Pipe whose power sequencer is currently locked into
 925          * this port. Only relevant on VLV/CHV.
 926          */
 927         enum pipe pps_pipe;
 928         /*
 929          * Set if the sequencer may be reset due to a power transition,
 930          * requiring a reinitialization. Only relevant on BXT.
 931          */
 932         bool pps_reset;
 933         struct edp_power_seq pps_delays;
 934
 935         bool can_mst; /* this port supports mst */
 936         bool is_mst;
 937         int active_mst_links;
 938         /* connector directly attached - won't be use for modeset in mst world */
 939         struct intel_connector *attached_connector;
 940
 941         /* mst connector list */
 942         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 943         struct drm_dp_mst_topology_mgr mst_mgr;
 944
 945         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 946         /*
 947          * This function returns the value we have to program the AUX_CTL
 948          * register with to kick off an AUX transaction.
 949          */
 950         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 951                                      bool has_aux_irq,
 952                                      int send_bytes,
 953                                      uint32_t aux_clock_divider);
 954
 955         /* This is called before a link training is starterd */
 956         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 957
 958         /* Displayport compliance testing */
 959         unsigned long compliance_test_type;
 960         unsigned long compliance_test_data;
 961         bool compliance_test_active;
 962 };
 963
 964 struct intel_lspcon {
 965         bool active;
 966         enum drm_lspcon_mode mode;
 967         struct drm_dp_aux *aux;
 968 };
 969
 970 struct intel_digital_port {
 971         struct intel_encoder base;
 972         enum port port;
 973         u32 saved_port_bits;
 974         struct intel_dp dp;
 975         struct intel_hdmi hdmi;
 976         struct intel_lspcon lspcon;
 977         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 978         bool release_cl2_override;
 979         uint8_t max_lanes;
 980 };
 981
 982 struct intel_dp_mst_encoder {
 983         struct intel_encoder base;
 984         enum pipe pipe;
 985         struct intel_digital_port *primary;
 986         struct intel_connector *connector;
 987 };
 988
 989 static inline enum dpio_channel
 990 vlv_dport_to_channel(struct intel_digital_port *dport)
 991 {
 992         switch (dport->port) {
 993         case PORT_B:
 994         case PORT_D:
 995                 return DPIO_CH0;
 996         case PORT_C:
 997                 return DPIO_CH1;
 998         default:
 999                 BUG();
1000         }
1001 }
1002
1003 static inline enum dpio_phy
1004 vlv_dport_to_phy(struct intel_digital_port *dport)
1005 {
1006         switch (dport->port) {
1007         case PORT_B:
1008         case PORT_C:
1009                 return DPIO_PHY0;
1010         case PORT_D:
1011                 return DPIO_PHY1;
1012         default:
1013                 BUG();
1014         }
1015 }
1016
1017 static inline enum dpio_channel
1018 vlv_pipe_to_channel(enum pipe pipe)
1019 {
1020         switch (pipe) {
1021         case PIPE_A:
1022         case PIPE_C:
1023                 return DPIO_CH0;
1024         case PIPE_B:
1025                 return DPIO_CH1;
1026         default:
1027                 BUG();
1028         }
1029 }
1030
1031 static inline struct drm_crtc *
1032 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1033 {
1034         struct drm_i915_private *dev_priv = to_i915(dev);
1035         return dev_priv->pipe_to_crtc_mapping[pipe];
1036 }
1037
1038 static inline struct drm_crtc *
1039 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1040 {
1041         struct drm_i915_private *dev_priv = to_i915(dev);
1042         return dev_priv->plane_to_crtc_mapping[plane];
1043 }
1044
1045 struct intel_flip_work {
1046         struct work_struct unpin_work;
1047         struct work_struct mmio_work;
1048
1049         struct drm_crtc *crtc;
1050         struct drm_framebuffer *old_fb;
1051         struct drm_i915_gem_object *pending_flip_obj;
1052         struct drm_pending_vblank_event *event;
1053         atomic_t pending;
1054         u32 flip_count;
1055         u32 gtt_offset;
1056         struct drm_i915_gem_request *flip_queued_req;
1057         u32 flip_queued_vblank;
1058         u32 flip_ready_vblank;
1059         unsigned int rotation;
1060 };
1061
1062 struct intel_load_detect_pipe {
1063         struct drm_atomic_state *restore_state;
1064 };
1065
1066 static inline struct intel_encoder *
1067 intel_attached_encoder(struct drm_connector *connector)
1068 {
1069         return to_intel_connector(connector)->encoder;
1070 }
1071
1072 static inline struct intel_digital_port *
1073 enc_to_dig_port(struct drm_encoder *encoder)
1074 {
1075         return container_of(encoder, struct intel_digital_port, base.base);
1076 }
1077
1078 static inline struct intel_dp_mst_encoder *
1079 enc_to_mst(struct drm_encoder *encoder)
1080 {
1081         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1082 }
1083
1084 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1085 {
1086         return &enc_to_dig_port(encoder)->dp;
1087 }
1088
1089 static inline struct intel_digital_port *
1090 dp_to_dig_port(struct intel_dp *intel_dp)
1091 {
1092         return container_of(intel_dp, struct intel_digital_port, dp);
1093 }
1094
1095 static inline struct intel_digital_port *
1096 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1097 {
1098         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1099 }
1100
1101 /*
1102  * Returns the number of planes for this pipe, ie the number of sprites + 1
1103  * (primary plane). This doesn't count the cursor plane then.
1104  */
1105 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1106 {
1107         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1108 }
1109
1110 /* intel_fifo_underrun.c */
1111 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1112                                            enum pipe pipe, bool enable);
1113 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1114                                            enum transcoder pch_transcoder,
1115                                            bool enable);
1116 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1117                                          enum pipe pipe);
1118 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1119                                          enum transcoder pch_transcoder);
1120 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1121 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1122
1123 /* i915_irq.c */
1124 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1125 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1126 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1127 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1128 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1129 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1130 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1131 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1132 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1133 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1134 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1135 {
1136         /*
1137          * We only use drm_irq_uninstall() at unload and VT switch, so
1138          * this is the only thing we need to check.
1139          */
1140         return dev_priv->pm.irqs_enabled;
1141 }
1142
1143 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1144 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1145                                      unsigned int pipe_mask);
1146 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1147                                      unsigned int pipe_mask);
1148
1149 /* intel_crt.c */
1150 void intel_crt_init(struct drm_device *dev);
1151 void intel_crt_reset(struct drm_encoder *encoder);
1152
1153 /* intel_ddi.c */
1154 void intel_ddi_clk_select(struct intel_encoder *encoder,
1155                           struct intel_shared_dpll *pll);
1156 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1157                                 struct intel_crtc_state *old_crtc_state,
1158                                 struct drm_connector_state *old_conn_state);
1159 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1160 void hsw_fdi_link_train(struct drm_crtc *crtc);
1161 void intel_ddi_init(struct drm_device *dev, enum port port);
1162 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1163 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1164 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1165 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1166                                        enum transcoder cpu_transcoder);
1167 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1168 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1169 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1170                           struct intel_crtc_state *crtc_state);
1171 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1172 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1173 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1174 void intel_ddi_get_config(struct intel_encoder *encoder,
1175                           struct intel_crtc_state *pipe_config);
1176 struct intel_encoder *
1177 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1178
1179 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1180 void intel_ddi_clock_get(struct intel_encoder *encoder,
1181                          struct intel_crtc_state *pipe_config);
1182 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1183 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1184 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1185                                                   int clock);
1186 unsigned int intel_fb_align_height(struct drm_device *dev,
1187                                    unsigned int height,
1188                                    uint32_t pixel_format,
1189                                    uint64_t fb_format_modifier);
1190 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1191                               uint64_t fb_modifier, uint32_t pixel_format);
1192
1193 /* intel_audio.c */
1194 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1195 void intel_audio_codec_enable(struct intel_encoder *encoder);
1196 void intel_audio_codec_disable(struct intel_encoder *encoder);
1197 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1198 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1199
1200 /* intel_display.c */
1201 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1202 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1203 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1204 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1205                       const char *name, u32 reg, int ref_freq);
1206 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1207 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1208 extern const struct drm_plane_funcs intel_plane_funcs;
1209 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1210 unsigned int intel_fb_xy_to_linear(int x, int y,
1211                                    const struct intel_plane_state *state,
1212                                    int plane);
1213 void intel_add_fb_offsets(int *x, int *y,
1214                           const struct intel_plane_state *state, int plane);
1215 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1216 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1217 void intel_mark_busy(struct drm_i915_private *dev_priv);
1218 void intel_mark_idle(struct drm_i915_private *dev_priv);
1219 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1220 int intel_display_suspend(struct drm_device *dev);
1221 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1222 void intel_encoder_destroy(struct drm_encoder *encoder);
1223 int intel_connector_init(struct intel_connector *);
1224 struct intel_connector *intel_connector_alloc(void);
1225 bool intel_connector_get_hw_state(struct intel_connector *connector);
1226 void intel_connector_attach_encoder(struct intel_connector *connector,
1227                                     struct intel_encoder *encoder);
1228 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1229                                              struct drm_crtc *crtc);
1230 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1231 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1232                                 struct drm_file *file_priv);
1233 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1234                                              enum pipe pipe);
1235 static inline bool
1236 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1237                     enum intel_output_type type)
1238 {
1239         return crtc_state->output_types & (1 << type);
1240 }
1241 static inline bool
1242 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1243 {
1244         return crtc_state->output_types &
1245                 ((1 << INTEL_OUTPUT_DP) |
1246                  (1 << INTEL_OUTPUT_DP_MST) |
1247                  (1 << INTEL_OUTPUT_EDP));
1248 }
1249 static inline void
1250 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1251 {
1252         drm_wait_one_vblank(dev, pipe);
1253 }
1254 static inline void
1255 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1256 {
1257         const struct intel_crtc *crtc =
1258                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1259
1260         if (crtc->active)
1261                 intel_wait_for_vblank(dev, pipe);
1262 }
1263
1264 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1265
1266 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1267 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1268                          struct intel_digital_port *dport,
1269                          unsigned int expected_mask);
1270 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1271                                 struct drm_display_mode *mode,
1272                                 struct intel_load_detect_pipe *old,
1273                                 struct drm_modeset_acquire_ctx *ctx);
1274 void intel_release_load_detect_pipe(struct drm_connector *connector,
1275                                     struct intel_load_detect_pipe *old,
1276                                     struct drm_modeset_acquire_ctx *ctx);
1277 struct i915_vma *
1278 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1279 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1280 struct drm_framebuffer *
1281 __intel_framebuffer_create(struct drm_device *dev,
1282                            struct drm_mode_fb_cmd2 *mode_cmd,
1283                            struct drm_i915_gem_object *obj);
1284 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1285 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1286 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1287 int intel_prepare_plane_fb(struct drm_plane *plane,
1288                            struct drm_plane_state *new_state);
1289 void intel_cleanup_plane_fb(struct drm_plane *plane,
1290                             struct drm_plane_state *old_state);
1291 int intel_plane_atomic_get_property(struct drm_plane *plane,
1292                                     const struct drm_plane_state *state,
1293                                     struct drm_property *property,
1294                                     uint64_t *val);
1295 int intel_plane_atomic_set_property(struct drm_plane *plane,
1296                                     struct drm_plane_state *state,
1297                                     struct drm_property *property,
1298                                     uint64_t val);
1299 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1300                                     struct drm_plane_state *plane_state);
1301
1302 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1303                                uint64_t fb_modifier, unsigned int cpp);
1304
1305 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1306                                     enum pipe pipe);
1307
1308 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1309                      const struct dpll *dpll);
1310 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1311 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1312
1313 /* modesetting asserts */
1314 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1315                            enum pipe pipe);
1316 void assert_pll(struct drm_i915_private *dev_priv,
1317                 enum pipe pipe, bool state);
1318 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1319 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1320 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1321 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1322 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1323 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1324                        enum pipe pipe, bool state);
1325 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1326 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1327 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1328 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1329 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1330 u32 intel_compute_tile_offset(int *x, int *y,
1331                               const struct intel_plane_state *state, int plane);
1332 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1333 void intel_finish_reset(struct drm_i915_private *dev_priv);
1334 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1335 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1336 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1337 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1338 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1339 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1340 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1341                             enum dpio_phy phy);
1342 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1343                               enum dpio_phy phy);
1344 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1345 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1346 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1347 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1348 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1349 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1350 unsigned int skl_cdclk_get_vco(unsigned int freq);
1351 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1352 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1353 void intel_dp_get_m_n(struct intel_crtc *crtc,
1354                       struct intel_crtc_state *pipe_config);
1355 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1356 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1357 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1358                         struct dpll *best_clock);
1359 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1360
1361 bool intel_crtc_active(struct drm_crtc *crtc);
1362 void hsw_enable_ips(struct intel_crtc *crtc);
1363 void hsw_disable_ips(struct intel_crtc *crtc);
1364 enum intel_display_power_domain
1365 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1366 enum intel_display_power_domain
1367 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1368 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1369                                  struct intel_crtc_state *pipe_config);
1370
1371 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1372 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1373
1374 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1375
1376 u32 skl_plane_ctl_format(uint32_t pixel_format);
1377 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1378 u32 skl_plane_ctl_rotation(unsigned int rotation);
1379 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1380                      unsigned int rotation);
1381 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1382
1383 /* intel_csr.c */
1384 void intel_csr_ucode_init(struct drm_i915_private *);
1385 void intel_csr_load_program(struct drm_i915_private *);
1386 void intel_csr_ucode_fini(struct drm_i915_private *);
1387 void intel_csr_ucode_suspend(struct drm_i915_private *);
1388 void intel_csr_ucode_resume(struct drm_i915_private *);
1389
1390 /* intel_dp.c */
1391 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1392 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1393                              struct intel_connector *intel_connector);
1394 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1395                               int link_rate, uint8_t lane_count,
1396                               bool link_mst);
1397 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1398 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1399 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1400 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1401 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1402 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1403 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1404 bool intel_dp_compute_config(struct intel_encoder *encoder,
1405                              struct intel_crtc_state *pipe_config,
1406                              struct drm_connector_state *conn_state);
1407 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1408 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1409                                   bool long_hpd);
1410 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1411 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1412 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1413 void intel_edp_panel_on(struct intel_dp *intel_dp);
1414 void intel_edp_panel_off(struct intel_dp *intel_dp);
1415 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1416 void intel_dp_mst_suspend(struct drm_device *dev);
1417 void intel_dp_mst_resume(struct drm_device *dev);
1418 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1419 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1420 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1421 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1422 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1423 void intel_plane_destroy(struct drm_plane *plane);
1424 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1425                            struct intel_crtc_state *crtc_state);
1426 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1427                            struct intel_crtc_state *crtc_state);
1428 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1429                                unsigned int frontbuffer_bits);
1430 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1431                           unsigned int frontbuffer_bits);
1432
1433 void
1434 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1435                                        uint8_t dp_train_pat);
1436 void
1437 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1438 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1439 uint8_t
1440 intel_dp_voltage_max(struct intel_dp *intel_dp);
1441 uint8_t
1442 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1443 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1444                            uint8_t *link_bw, uint8_t *rate_select);
1445 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1446 bool
1447 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1448
1449 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1450 {
1451         return ~((1 << lane_count) - 1) & 0xf;
1452 }
1453
1454 /* intel_dp_aux_backlight.c */
1455 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1456
1457 /* intel_dp_mst.c */
1458 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1459 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1460 /* intel_dsi.c */
1461 void intel_dsi_init(struct drm_device *dev);
1462
1463 /* intel_dsi_dcs_backlight.c */
1464 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1465
1466 /* intel_dvo.c */
1467 void intel_dvo_init(struct drm_device *dev);
1468 /* intel_hotplug.c */
1469 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1470
1471
1472 /* legacy fbdev emulation in intel_fbdev.c */
1473 #ifdef CONFIG_DRM_FBDEV_EMULATION
1474 extern int intel_fbdev_init(struct drm_device *dev);
1475 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1476 extern void intel_fbdev_fini(struct drm_device *dev);
1477 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1478 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1479 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1480 #else
1481 static inline int intel_fbdev_init(struct drm_device *dev)
1482 {
1483         return 0;
1484 }
1485
1486 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1487 {
1488 }
1489
1490 static inline void intel_fbdev_fini(struct drm_device *dev)
1491 {
1492 }
1493
1494 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1495 {
1496 }
1497
1498 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1499 {
1500 }
1501
1502 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1503 {
1504 }
1505 #endif
1506
1507 /* intel_fbc.c */
1508 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1509                            struct drm_atomic_state *state);
1510 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1511 void intel_fbc_pre_update(struct intel_crtc *crtc,
1512                           struct intel_crtc_state *crtc_state,
1513                           struct intel_plane_state *plane_state);
1514 void intel_fbc_post_update(struct intel_crtc *crtc);
1515 void intel_fbc_init(struct drm_i915_private *dev_priv);
1516 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1517 void intel_fbc_enable(struct intel_crtc *crtc,
1518                       struct intel_crtc_state *crtc_state,
1519                       struct intel_plane_state *plane_state);
1520 void intel_fbc_disable(struct intel_crtc *crtc);
1521 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1522 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1523                           unsigned int frontbuffer_bits,
1524                           enum fb_op_origin origin);
1525 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1526                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1527 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1528 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1529
1530 /* intel_hdmi.c */
1531 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1532 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1533                                struct intel_connector *intel_connector);
1534 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1535 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1536                                struct intel_crtc_state *pipe_config,
1537                                struct drm_connector_state *conn_state);
1538 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1539
1540
1541 /* intel_lvds.c */
1542 void intel_lvds_init(struct drm_device *dev);
1543 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1544 bool intel_is_dual_link_lvds(struct drm_device *dev);
1545
1546
1547 /* intel_modes.c */
1548 int intel_connector_update_modes(struct drm_connector *connector,
1549                                  struct edid *edid);
1550 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1551 void intel_attach_force_audio_property(struct drm_connector *connector);
1552 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1553 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1554
1555
1556 /* intel_overlay.c */
1557 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1558 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1559 int intel_overlay_switch_off(struct intel_overlay *overlay);
1560 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1561                                   struct drm_file *file_priv);
1562 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1563                               struct drm_file *file_priv);
1564 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1565
1566
1567 /* intel_panel.c */
1568 int intel_panel_init(struct intel_panel *panel,
1569                      struct drm_display_mode *fixed_mode,
1570                      struct drm_display_mode *downclock_mode);
1571 void intel_panel_fini(struct intel_panel *panel);
1572 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1573                             struct drm_display_mode *adjusted_mode);
1574 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1575                              struct intel_crtc_state *pipe_config,
1576                              int fitting_mode);
1577 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1578                               struct intel_crtc_state *pipe_config,
1579                               int fitting_mode);
1580 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1581                                     u32 level, u32 max);
1582 int intel_panel_setup_backlight(struct drm_connector *connector,
1583                                 enum pipe pipe);
1584 void intel_panel_enable_backlight(struct intel_connector *connector);
1585 void intel_panel_disable_backlight(struct intel_connector *connector);
1586 void intel_panel_destroy_backlight(struct drm_connector *connector);
1587 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1588 extern struct drm_display_mode *intel_find_panel_downclock(
1589                                 struct drm_device *dev,
1590                                 struct drm_display_mode *fixed_mode,
1591                                 struct drm_connector *connector);
1592
1593 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1594 int intel_backlight_device_register(struct intel_connector *connector);
1595 void intel_backlight_device_unregister(struct intel_connector *connector);
1596 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1597 static int intel_backlight_device_register(struct intel_connector *connector)
1598 {
1599         return 0;
1600 }
1601 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1602 {
1603 }
1604 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1605
1606
1607 /* intel_psr.c */
1608 void intel_psr_enable(struct intel_dp *intel_dp);
1609 void intel_psr_disable(struct intel_dp *intel_dp);
1610 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1611                           unsigned frontbuffer_bits);
1612 void intel_psr_flush(struct drm_i915_private *dev_priv,
1613                      unsigned frontbuffer_bits,
1614                      enum fb_op_origin origin);
1615 void intel_psr_init(struct drm_device *dev);
1616 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1617                                    unsigned frontbuffer_bits);
1618
1619 /* intel_runtime_pm.c */
1620 int intel_power_domains_init(struct drm_i915_private *);
1621 void intel_power_domains_fini(struct drm_i915_private *);
1622 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1623 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1624 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1625 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1626 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1627 const char *
1628 intel_display_power_domain_str(enum intel_display_power_domain domain);
1629
1630 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1631                                     enum intel_display_power_domain domain);
1632 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1633                                       enum intel_display_power_domain domain);
1634 void intel_display_power_get(struct drm_i915_private *dev_priv,
1635                              enum intel_display_power_domain domain);
1636 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1637                                         enum intel_display_power_domain domain);
1638 void intel_display_power_put(struct drm_i915_private *dev_priv,
1639                              enum intel_display_power_domain domain);
1640
1641 static inline void
1642 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1643 {
1644         WARN_ONCE(dev_priv->pm.suspended,
1645                   "Device suspended during HW access\n");
1646 }
1647
1648 static inline void
1649 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1650 {
1651         assert_rpm_device_not_suspended(dev_priv);
1652         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1653          * too much noise. */
1654         if (!atomic_read(&dev_priv->pm.wakeref_count))
1655                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1656 }
1657
1658 static inline int
1659 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1660 {
1661         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1662
1663         assert_rpm_wakelock_held(dev_priv);
1664
1665         return seq;
1666 }
1667
1668 static inline void
1669 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1670 {
1671         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1672                   "HW access outside of RPM atomic section\n");
1673 }
1674
1675 /**
1676  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1677  * @dev_priv: i915 device instance
1678  *
1679  * This function disable asserts that check if we hold an RPM wakelock
1680  * reference, while keeping the device-not-suspended checks still enabled.
1681  * It's meant to be used only in special circumstances where our rule about
1682  * the wakelock refcount wrt. the device power state doesn't hold. According
1683  * to this rule at any point where we access the HW or want to keep the HW in
1684  * an active state we must hold an RPM wakelock reference acquired via one of
1685  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1686  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1687  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1688  * users should avoid using this function.
1689  *
1690  * Any calls to this function must have a symmetric call to
1691  * enable_rpm_wakeref_asserts().
1692  */
1693 static inline void
1694 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1695 {
1696         atomic_inc(&dev_priv->pm.wakeref_count);
1697 }
1698
1699 /**
1700  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1701  * @dev_priv: i915 device instance
1702  *
1703  * This function re-enables the RPM assert checks after disabling them with
1704  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1705  * circumstances otherwise its use should be avoided.
1706  *
1707  * Any calls to this function must have a symmetric call to
1708  * disable_rpm_wakeref_asserts().
1709  */
1710 static inline void
1711 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1712 {
1713         atomic_dec(&dev_priv->pm.wakeref_count);
1714 }
1715
1716 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1717 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1718 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1719 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1720
1721 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1722
1723 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1724                              bool override, unsigned int mask);
1725 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1726                           enum dpio_channel ch, bool override);
1727
1728
1729 /* intel_pm.c */
1730 void intel_init_clock_gating(struct drm_device *dev);
1731 void intel_suspend_hw(struct drm_device *dev);
1732 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1733 void intel_update_watermarks(struct drm_crtc *crtc);
1734 void intel_init_pm(struct drm_device *dev);
1735 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1736 void intel_pm_setup(struct drm_device *dev);
1737 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1738 void intel_gpu_ips_teardown(void);
1739 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1740 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1741 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1742 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1743 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1744 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1745 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1746 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1747 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1748 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1749 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1750                     struct intel_rps_client *rps,
1751                     unsigned long submitted);
1752 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1753 void vlv_wm_get_hw_state(struct drm_device *dev);
1754 void ilk_wm_get_hw_state(struct drm_device *dev);
1755 void skl_wm_get_hw_state(struct drm_device *dev);
1756 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1757                           struct skl_ddb_allocation *ddb /* out */);
1758 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1759                               struct skl_pipe_wm *out);
1760 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1761 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1762 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1763 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1764                          const struct skl_wm_level *l2);
1765 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
1766                                const struct skl_ddb_allocation *new,
1767                                enum pipe pipe);
1768 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
1769                                  struct intel_crtc *intel_crtc);
1770 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
1771                          const struct skl_plane_wm *wm,
1772                          const struct skl_ddb_allocation *ddb);
1773 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
1774                         const struct skl_plane_wm *wm,
1775                         const struct skl_ddb_allocation *ddb,
1776                         int plane);
1777 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1778 bool ilk_disable_lp_wm(struct drm_device *dev);
1779 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1780 static inline int intel_enable_rc6(void)
1781 {
1782         return i915.enable_rc6;
1783 }
1784
1785 /* intel_sdvo.c */
1786 bool intel_sdvo_init(struct drm_device *dev,
1787                      i915_reg_t reg, enum port port);
1788
1789
1790 /* intel_sprite.c */
1791 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1792                              int usecs);
1793 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1794 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1795                               struct drm_file *file_priv);
1796 void intel_pipe_update_start(struct intel_crtc *crtc);
1797 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1798
1799 /* intel_tv.c */
1800 void intel_tv_init(struct drm_device *dev);
1801
1802 /* intel_atomic.c */
1803 int intel_connector_atomic_get_property(struct drm_connector *connector,
1804                                         const struct drm_connector_state *state,
1805                                         struct drm_property *property,
1806                                         uint64_t *val);
1807 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1808 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1809                                struct drm_crtc_state *state);
1810 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1811 void intel_atomic_state_clear(struct drm_atomic_state *);
1812 struct intel_shared_dpll_config *
1813 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1814
1815 static inline struct intel_crtc_state *
1816 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1817                             struct intel_crtc *crtc)
1818 {
1819         struct drm_crtc_state *crtc_state;
1820         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1821         if (IS_ERR(crtc_state))
1822                 return ERR_CAST(crtc_state);
1823
1824         return to_intel_crtc_state(crtc_state);
1825 }
1826
1827 static inline struct intel_plane_state *
1828 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1829                                       struct intel_plane *plane)
1830 {
1831         struct drm_plane_state *plane_state;
1832
1833         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1834
1835         return to_intel_plane_state(plane_state);
1836 }
1837
1838 int intel_atomic_setup_scalers(struct drm_device *dev,
1839         struct intel_crtc *intel_crtc,
1840         struct intel_crtc_state *crtc_state);
1841
1842 /* intel_atomic_plane.c */
1843 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1844 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1845 void intel_plane_destroy_state(struct drm_plane *plane,
1846                                struct drm_plane_state *state);
1847 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1848
1849 /* intel_color.c */
1850 void intel_color_init(struct drm_crtc *crtc);
1851 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1852 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1853 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1854
1855 /* intel_lspcon.c */
1856 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1857 void lspcon_resume(struct intel_lspcon *lspcon);
1858 #endif /* __INTEL_DRV_H__ */