2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 * TODO: When modesetting has fully transitioned to atomic, the below
52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
55 #define _wait_for(COND, US, W) ({ \
56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
59 bool expired__ = time_after(jiffies, timeout__); \
68 if ((W) && drm_can_sleep()) { \
69 usleep_range((W), (W)*2); \
77 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #define _wait_for_atomic(COND, US, ATOMIC) \
88 int cpu, ret, timeout = (US) * 1000; \
90 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
93 cpu = smp_processor_id(); \
95 base = local_clock(); \
97 u64 now = local_clock(); \
104 if (now - base >= timeout) { \
111 if (unlikely(cpu != smp_processor_id())) { \
112 timeout -= now - base; \
113 cpu = smp_processor_id(); \
114 base = local_clock(); \
121 #define wait_for_us(COND, US) \
124 BUILD_BUG_ON(!__builtin_constant_p(US)); \
126 ret__ = _wait_for((COND), (US), 10); \
128 ret__ = _wait_for_atomic((COND), (US), 0); \
132 #define wait_for_atomic_us(COND, US) \
134 BUILD_BUG_ON(!__builtin_constant_p(US)); \
135 BUILD_BUG_ON((US) > 50000); \
136 _wait_for_atomic((COND), (US), 1); \
139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
141 #define KHz(x) (1000 * (x))
142 #define MHz(x) KHz(1000 * (x))
145 * Display related stuff
148 /* store information about an Ixxx DVO */
149 /* The i830->i865 use multiple DVOs with multiple i2cs */
150 /* the i915, i945 have a single sDVO i2c bus - which is different */
151 #define MAX_OUTPUTS 6
152 /* maximum connectors per crtcs in the mode set */
154 /* Maximum cursor sizes */
155 #define GEN2_CURSOR_WIDTH 64
156 #define GEN2_CURSOR_HEIGHT 64
157 #define MAX_CURSOR_WIDTH 256
158 #define MAX_CURSOR_HEIGHT 256
160 #define INTEL_I2C_BUS_DVO 1
161 #define INTEL_I2C_BUS_SDVO 2
163 /* these are outputs from the chip - integrated only
164 external chips are via DVO or SDVO output */
165 enum intel_output_type
{
166 INTEL_OUTPUT_UNUSED
= 0,
167 INTEL_OUTPUT_ANALOG
= 1,
168 INTEL_OUTPUT_DVO
= 2,
169 INTEL_OUTPUT_SDVO
= 3,
170 INTEL_OUTPUT_LVDS
= 4,
171 INTEL_OUTPUT_TVOUT
= 5,
172 INTEL_OUTPUT_HDMI
= 6,
174 INTEL_OUTPUT_EDP
= 8,
175 INTEL_OUTPUT_DSI
= 9,
176 INTEL_OUTPUT_UNKNOWN
= 10,
177 INTEL_OUTPUT_DP_MST
= 11,
180 #define INTEL_DVO_CHIP_NONE 0
181 #define INTEL_DVO_CHIP_LVDS 1
182 #define INTEL_DVO_CHIP_TMDS 2
183 #define INTEL_DVO_CHIP_TVOUT 4
185 #define INTEL_DSI_VIDEO_MODE 0
186 #define INTEL_DSI_COMMAND_MODE 1
188 struct intel_framebuffer
{
189 struct drm_framebuffer base
;
190 struct drm_i915_gem_object
*obj
;
191 struct intel_rotation_info rot_info
;
193 /* for each plane in the normal GTT view */
197 /* for each plane in the rotated GTT view */
200 unsigned int pitch
; /* pixels */
205 struct drm_fb_helper helper
;
206 struct intel_framebuffer
*fb
;
207 struct i915_vma
*vma
;
208 async_cookie_t cookie
;
212 struct intel_encoder
{
213 struct drm_encoder base
;
215 enum intel_output_type type
;
217 unsigned int cloneable
;
218 void (*hot_plug
)(struct intel_encoder
*);
219 bool (*compute_config
)(struct intel_encoder
*,
220 struct intel_crtc_state
*,
221 struct drm_connector_state
*);
222 void (*pre_pll_enable
)(struct intel_encoder
*,
223 struct intel_crtc_state
*,
224 struct drm_connector_state
*);
225 void (*pre_enable
)(struct intel_encoder
*,
226 struct intel_crtc_state
*,
227 struct drm_connector_state
*);
228 void (*enable
)(struct intel_encoder
*,
229 struct intel_crtc_state
*,
230 struct drm_connector_state
*);
231 void (*disable
)(struct intel_encoder
*,
232 struct intel_crtc_state
*,
233 struct drm_connector_state
*);
234 void (*post_disable
)(struct intel_encoder
*,
235 struct intel_crtc_state
*,
236 struct drm_connector_state
*);
237 void (*post_pll_disable
)(struct intel_encoder
*,
238 struct intel_crtc_state
*,
239 struct drm_connector_state
*);
240 /* Read out the current hw state of this connector, returning true if
241 * the encoder is active. If the encoder is enabled it also set the pipe
242 * it is connected to in the pipe parameter. */
243 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
244 /* Reconstructs the equivalent mode flags for the current hardware
245 * state. This must be called _after_ display->get_pipe_config has
246 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
247 * be set correctly before calling this function. */
248 void (*get_config
)(struct intel_encoder
*,
249 struct intel_crtc_state
*pipe_config
);
250 /* Returns a mask of power domains that need to be referenced as part
251 * of the hardware state readout code. */
252 u64 (*get_power_domains
)(struct intel_encoder
*encoder
);
254 * Called during system suspend after all pending requests for the
255 * encoder are flushed (for example for DP AUX transactions) and
256 * device interrupts are disabled.
258 void (*suspend
)(struct intel_encoder
*);
260 enum hpd_pin hpd_pin
;
261 enum intel_display_power_domain power_domain
;
262 /* for communication with audio component; protected by av_mutex */
263 const struct drm_connector
*audio_connector
;
267 struct drm_display_mode
*fixed_mode
;
268 struct drm_display_mode
*alt_fixed_mode
;
269 struct drm_display_mode
*downclock_mode
;
278 bool combination_mode
; /* gen 2/4 only */
280 bool alternate_pwm_increment
; /* lpt+ */
283 bool util_pin_active_low
; /* bxt+ */
284 u8 controller
; /* bxt+ only */
285 struct pwm_device
*pwm
;
287 struct backlight_device
*device
;
289 /* Connector and platform specific backlight functions */
290 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
291 uint32_t (*get
)(struct intel_connector
*connector
);
292 void (*set
)(const struct drm_connector_state
*conn_state
, uint32_t level
);
293 void (*disable
)(const struct drm_connector_state
*conn_state
);
294 void (*enable
)(const struct intel_crtc_state
*crtc_state
,
295 const struct drm_connector_state
*conn_state
);
296 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
298 void (*power
)(struct intel_connector
*, bool enable
);
302 struct intel_connector
{
303 struct drm_connector base
;
305 * The fixed encoder this connector is connected to.
307 struct intel_encoder
*encoder
;
309 /* ACPI device id for ACPI and driver cooperation */
312 /* Reads out the current hw, returning true if the connector is enabled
313 * and active (i.e. dpms ON state). */
314 bool (*get_hw_state
)(struct intel_connector
*);
316 /* Panel info for eDP and LVDS */
317 struct intel_panel panel
;
319 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
321 struct edid
*detect_edid
;
323 /* since POLL and HPD connectors may use the same HPD line keep the native
324 state of connector->polled in case hotplug storm detection changes it */
327 void *port
; /* store this opaque as its illegal to dereference it */
329 struct intel_dp
*mst_port
;
331 /* Work struct to schedule a uevent on link train failure */
332 struct work_struct modeset_retry_work
;
335 struct intel_digital_connector_state
{
336 struct drm_connector_state base
;
338 enum hdmi_force_audio force_audio
;
342 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
356 struct intel_atomic_state
{
357 struct drm_atomic_state base
;
361 * Logical state of cdclk (used for all scaling, watermark,
362 * etc. calculations and checks). This is computed as if all
363 * enabled crtcs were active.
365 struct intel_cdclk_state logical
;
368 * Actual state of cdclk, can be different from the logical
369 * state only when all crtc's are DPMS off.
371 struct intel_cdclk_state actual
;
374 bool dpll_set
, modeset
;
377 * Does this transaction change the pipes that are active? This mask
378 * tracks which CRTC's have changed their active state at the end of
379 * the transaction (not counting the temporary disable during modesets).
380 * This mask should only be non-zero when intel_state->modeset is true,
381 * but the converse is not necessarily true; simply changing a mode may
382 * not flip the final active status of any CRTC's
384 unsigned int active_pipe_changes
;
386 unsigned int active_crtcs
;
387 unsigned int min_pixclk
[I915_MAX_PIPES
];
389 struct intel_shared_dpll_state shared_dpll
[I915_NUM_PLLS
];
392 * Current watermarks can't be trusted during hardware readout, so
393 * don't bother calculating intermediate watermarks.
395 bool skip_intermediate_wm
;
398 struct skl_wm_values wm_results
;
400 struct i915_sw_fence commit_ready
;
402 struct llist_node freed
;
405 struct intel_plane_state
{
406 struct drm_plane_state base
;
407 struct drm_rect clip
;
408 struct i915_vma
*vma
;
419 /* plane control register */
424 * = -1 : not using a scaler
425 * >= 0 : using a scalers
427 * plane requiring a scaler:
428 * - During check_plane, its bit is set in
429 * crtc_state->scaler_state.scaler_users by calling helper function
430 * update_scaler_plane.
431 * - scaler_id indicates the scaler it got assigned.
433 * plane doesn't require a scaler:
434 * - this can happen when scaling is no more required or plane simply
436 * - During check_plane, corresponding bit is reset in
437 * crtc_state->scaler_state.scaler_users by calling helper function
438 * update_scaler_plane.
442 struct drm_intel_sprite_colorkey ckey
;
445 struct intel_initial_plane_config
{
446 struct intel_framebuffer
*fb
;
452 #define SKL_MIN_SRC_W 8
453 #define SKL_MAX_SRC_W 4096
454 #define SKL_MIN_SRC_H 8
455 #define SKL_MAX_SRC_H 4096
456 #define SKL_MIN_DST_W 8
457 #define SKL_MAX_DST_W 4096
458 #define SKL_MIN_DST_H 8
459 #define SKL_MAX_DST_H 4096
461 struct intel_scaler
{
466 struct intel_crtc_scaler_state
{
467 #define SKL_NUM_SCALERS 2
468 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
471 * scaler_users: keeps track of users requesting scalers on this crtc.
473 * If a bit is set, a user is using a scaler.
474 * Here user can be a plane or crtc as defined below:
475 * bits 0-30 - plane (bit position is index from drm_plane_index)
478 * Instead of creating a new index to cover planes and crtc, using
479 * existing drm_plane_index for planes which is well less than 31
480 * planes and bit 31 for crtc. This should be fine to cover all
483 * intel_atomic_setup_scalers will setup available scalers to users
484 * requesting scalers. It will gracefully fail if request exceeds
487 #define SKL_CRTC_INDEX 31
488 unsigned scaler_users
;
490 /* scaler used by crtc for panel fitting purpose */
494 /* drm_mode->private_flags */
495 #define I915_MODE_FLAG_INHERITED 1
497 struct intel_pipe_wm
{
498 struct intel_wm_level wm
[5];
499 struct intel_wm_level raw_wm
[5];
503 bool sprites_enabled
;
507 struct skl_plane_wm
{
508 struct skl_wm_level wm
[8];
509 struct skl_wm_level trans_wm
;
513 struct skl_plane_wm planes
[I915_MAX_PLANES
];
520 VLV_WM_LEVEL_DDR_DVFS
,
524 struct vlv_wm_state
{
525 struct g4x_pipe_wm wm
[NUM_VLV_WM_LEVELS
];
526 struct g4x_sr_wm sr
[NUM_VLV_WM_LEVELS
];
531 struct vlv_fifo_state
{
532 u16 plane
[I915_MAX_PLANES
];
542 struct g4x_wm_state
{
543 struct g4x_pipe_wm wm
;
545 struct g4x_sr_wm hpll
;
551 struct intel_crtc_wm_state
{
555 * Intermediate watermarks; these can be
556 * programmed immediately since they satisfy
557 * both the current configuration we're
558 * switching away from and the new
559 * configuration we're switching to.
561 struct intel_pipe_wm intermediate
;
564 * Optimal watermarks, programmed post-vblank
565 * when this state is committed.
567 struct intel_pipe_wm optimal
;
571 /* gen9+ only needs 1-step wm programming */
572 struct skl_pipe_wm optimal
;
573 struct skl_ddb_entry ddb
;
577 /* "raw" watermarks (not inverted) */
578 struct g4x_pipe_wm raw
[NUM_VLV_WM_LEVELS
];
579 /* intermediate watermarks (inverted) */
580 struct vlv_wm_state intermediate
;
581 /* optimal watermarks (inverted) */
582 struct vlv_wm_state optimal
;
583 /* display FIFO split */
584 struct vlv_fifo_state fifo_state
;
588 /* "raw" watermarks */
589 struct g4x_pipe_wm raw
[NUM_G4X_WM_LEVELS
];
590 /* intermediate watermarks */
591 struct g4x_wm_state intermediate
;
592 /* optimal watermarks */
593 struct g4x_wm_state optimal
;
598 * Platforms with two-step watermark programming will need to
599 * update watermark programming post-vblank to switch from the
600 * safe intermediate watermarks to the optimal final
603 bool need_postvbl_update
;
606 struct intel_crtc_state
{
607 struct drm_crtc_state base
;
610 * quirks - bitfield with hw state readout quirks
612 * For various reasons the hw state readout code might not be able to
613 * completely faithfully read out the current state. These cases are
614 * tracked with quirk flags so that fastboot and state checker can act
617 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
618 unsigned long quirks
;
620 unsigned fb_bits
; /* framebuffers to flip */
621 bool update_pipe
; /* can a fast modeset be performed? */
623 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
624 bool fb_changed
; /* fb on any of the planes is changed */
625 bool fifo_changed
; /* FIFO split is changed */
627 /* Pipe source size (ie. panel fitter input size)
628 * All planes will be positioned inside this space,
629 * and get clipped at the edges. */
630 int pipe_src_w
, pipe_src_h
;
633 * Pipe pixel rate, adjusted for
634 * panel fitter/pipe scaler downscaling.
636 unsigned int pixel_rate
;
638 /* Whether to set up the PCH/FDI. Note that we never allow sharing
639 * between pch encoders and cpu encoders. */
640 bool has_pch_encoder
;
642 /* Are we sending infoframes on the attached port */
645 /* CPU Transcoder for the pipe. Currently this can only differ from the
646 * pipe on Haswell and later (where we have a special eDP transcoder)
647 * and Broxton (where we have special DSI transcoders). */
648 enum transcoder cpu_transcoder
;
651 * Use reduced/limited/broadcast rbg range, compressing from the full
652 * range fed into the crtcs.
654 bool limited_color_range
;
656 /* Bitmask of encoder types (enum intel_output_type)
657 * driven by the pipe.
659 unsigned int output_types
;
661 /* Whether we should send NULL infoframes. Required for audio. */
664 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
665 * has_dp_encoder is set. */
669 * Enable dithering, used when the selected pipe bpp doesn't match the
675 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
676 * compliance video pattern tests.
677 * Disable dither only if it is a compliance test request for
680 bool dither_force_disable
;
682 /* Controls for the clock computation, to override various stages. */
685 /* SDVO TV has a bunch of special case. To make multifunction encoders
686 * work correctly, we need to track this at runtime.*/
690 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
691 * required. This is set in the 2nd loop of calling encoder's
692 * ->compute_config if the first pick doesn't work out.
696 /* Settings for the intel dpll used on pretty much everything but
700 /* Selected dpll when shared or NULL. */
701 struct intel_shared_dpll
*shared_dpll
;
703 /* Actual register state of the dpll, for shared dpll cross-checking. */
704 struct intel_dpll_hw_state dpll_hw_state
;
706 /* DSI PLL registers */
712 struct intel_link_m_n dp_m_n
;
714 /* m2_n2 for eDP downclock */
715 struct intel_link_m_n dp_m2_n2
;
719 * Frequence the dpll for the port should run at. Differs from the
720 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
721 * already multiplied by pixel_multiplier.
725 /* Used by SDVO (and if we ever fix it, HDMI). */
726 unsigned pixel_multiplier
;
731 * Used by platforms having DP/HDMI PHY with programmable lane
732 * latency optimization.
734 uint8_t lane_lat_optim_mask
;
736 /* Panel fitter controls for gen2-gen4 + VLV */
740 u32 lvds_border_bits
;
743 /* Panel fitter placement and size for Ironlake+ */
751 /* FDI configuration, only valid if has_pch_encoder is set. */
753 struct intel_link_m_n fdi_m_n
;
763 struct intel_crtc_scaler_state scaler_state
;
765 /* w/a for waiting 2 vblanks during crtc enable */
766 enum pipe hsw_workaround_pipe
;
768 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
771 struct intel_crtc_wm_state wm
;
773 /* Gamma mode programmed on the pipe */
776 /* bitmask of visible planes (enum plane_id) */
779 /* HDMI scrambling status */
780 bool hdmi_scrambling
;
782 /* HDMI High TMDS char rate ratio */
783 bool hdmi_high_tmds_clock_ratio
;
785 /* output format is YCBCR 4:2:0 */
790 struct drm_crtc base
;
794 * Whether the crtc and the connected output pipeline is active. Implies
795 * that crtc->enabled is set, i.e. the current mode configuration has
796 * some outputs connected to this crtc.
801 unsigned long long enabled_power_domains
;
802 struct intel_overlay
*overlay
;
804 /* Display surface base address adjustement for pageflips. Note that on
805 * gen4+ this only adjusts up to a tile, offsets within a tile are
806 * handled in the hw itself (with the TILEOFF register). */
811 struct intel_crtc_state
*config
;
813 /* global reset count when the last flip was submitted */
814 unsigned int reset_count
;
816 /* Access to these should be protected by dev_priv->irq_lock. */
817 bool cpu_fifo_underrun_disabled
;
818 bool pch_fifo_underrun_disabled
;
820 /* per-pipe watermark state */
822 /* watermarks currently being used */
824 struct intel_pipe_wm ilk
;
825 struct vlv_wm_state vlv
;
826 struct g4x_wm_state g4x
;
833 unsigned start_vbl_count
;
834 ktime_t start_vbl_time
;
835 int min_vbl
, max_vbl
;
839 /* scalers available on this crtc */
844 struct drm_plane base
;
850 uint32_t frontbuffer_bit
;
853 u32 base
, cntl
, size
;
857 * NOTE: Do not place new plane state fields here (e.g., when adding
858 * new plane properties). New runtime state should now be placed in
859 * the intel_plane_state structure and accessed via plane_state.
862 void (*update_plane
)(struct intel_plane
*plane
,
863 const struct intel_crtc_state
*crtc_state
,
864 const struct intel_plane_state
*plane_state
);
865 void (*disable_plane
)(struct intel_plane
*plane
,
866 struct intel_crtc
*crtc
);
867 int (*check_plane
)(struct intel_plane
*plane
,
868 struct intel_crtc_state
*crtc_state
,
869 struct intel_plane_state
*state
);
872 struct intel_watermark_params
{
880 struct cxsr_latency
{
886 u16 display_hpll_disable
;
888 u16 cursor_hpll_disable
;
891 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
892 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
893 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
894 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
895 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
896 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
897 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
898 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
899 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
905 enum drm_dp_dual_mode_type type
;
910 bool rgb_quant_range_selectable
;
911 struct intel_connector
*attached_connector
;
914 struct intel_dp_mst_encoder
;
915 #define DP_MAX_DOWNSTREAM_PORTS 0x10
919 * When platform provides two set of M_N registers for dp, we can
920 * program them and switch between them incase of DRRS.
921 * But When only one such register is provided, we have to program the
922 * required divider value on that registers itself based on the DRRS state.
924 * M1_N1 : Program dp_m_n on M1_N1 registers
925 * dp_m2_n2 on M2_N2 registers (If supported)
927 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
928 * M2_N2 registers are not supported
932 /* Sets the m1_n1 and m2_n2 */
937 struct intel_dp_compliance_data
{
939 uint8_t video_pattern
;
940 uint16_t hdisplay
, vdisplay
;
944 struct intel_dp_compliance
{
945 unsigned long test_type
;
946 struct intel_dp_compliance_data test_data
;
953 i915_reg_t output_reg
;
954 i915_reg_t aux_ch_ctl_reg
;
955 i915_reg_t aux_ch_data_reg
[5];
963 bool channel_eq_status
;
964 bool reset_link_params
;
965 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
966 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
967 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
968 uint8_t edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
970 int num_source_rates
;
971 const int *source_rates
;
972 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
974 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
975 bool use_rate_select
;
976 /* intersection of source and sink rates */
977 int num_common_rates
;
978 int common_rates
[DP_MAX_SUPPORTED_RATES
];
979 /* Max lane count for the current link */
980 int max_link_lane_count
;
981 /* Max rate for the current link */
983 /* sink or branch descriptor */
984 struct drm_dp_desc desc
;
985 struct drm_dp_aux aux
;
986 enum intel_display_power_domain aux_power_domain
;
987 uint8_t train_set
[4];
988 int panel_power_up_delay
;
989 int panel_power_down_delay
;
990 int panel_power_cycle_delay
;
991 int backlight_on_delay
;
992 int backlight_off_delay
;
993 struct delayed_work panel_vdd_work
;
995 unsigned long last_power_on
;
996 unsigned long last_backlight_off
;
997 ktime_t panel_power_off_time
;
999 struct notifier_block edp_notifier
;
1002 * Pipe whose power sequencer is currently locked into
1003 * this port. Only relevant on VLV/CHV.
1007 * Pipe currently driving the port. Used for preventing
1008 * the use of the PPS for any pipe currentrly driving
1009 * external DP as that will mess things up on VLV.
1011 enum pipe active_pipe
;
1013 * Set if the sequencer may be reset due to a power transition,
1014 * requiring a reinitialization. Only relevant on BXT.
1017 struct edp_power_seq pps_delays
;
1019 bool can_mst
; /* this port supports mst */
1021 int active_mst_links
;
1022 /* connector directly attached - won't be use for modeset in mst world */
1023 struct intel_connector
*attached_connector
;
1025 /* mst connector list */
1026 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
1027 struct drm_dp_mst_topology_mgr mst_mgr
;
1029 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
1031 * This function returns the value we have to program the AUX_CTL
1032 * register with to kick off an AUX transaction.
1034 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
1037 uint32_t aux_clock_divider
);
1039 /* This is called before a link training is starterd */
1040 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
1042 /* Displayport compliance testing */
1043 struct intel_dp_compliance compliance
;
1046 struct intel_lspcon
{
1048 enum drm_lspcon_mode mode
;
1051 struct intel_digital_port
{
1052 struct intel_encoder base
;
1054 u32 saved_port_bits
;
1056 struct intel_hdmi hdmi
;
1057 struct intel_lspcon lspcon
;
1058 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
1059 bool release_cl2_override
;
1061 enum intel_display_power_domain ddi_io_power_domain
;
1063 void (*write_infoframe
)(struct drm_encoder
*encoder
,
1064 const struct intel_crtc_state
*crtc_state
,
1065 enum hdmi_infoframe_type type
,
1066 const void *frame
, ssize_t len
);
1067 void (*set_infoframes
)(struct drm_encoder
*encoder
,
1069 const struct intel_crtc_state
*crtc_state
,
1070 const struct drm_connector_state
*conn_state
);
1071 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
1072 const struct intel_crtc_state
*pipe_config
);
1075 struct intel_dp_mst_encoder
{
1076 struct intel_encoder base
;
1078 struct intel_digital_port
*primary
;
1079 struct intel_connector
*connector
;
1082 static inline enum dpio_channel
1083 vlv_dport_to_channel(struct intel_digital_port
*dport
)
1085 switch (dport
->port
) {
1096 static inline enum dpio_phy
1097 vlv_dport_to_phy(struct intel_digital_port
*dport
)
1099 switch (dport
->port
) {
1110 static inline enum dpio_channel
1111 vlv_pipe_to_channel(enum pipe pipe
)
1124 static inline struct intel_crtc
*
1125 intel_get_crtc_for_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1127 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1130 static inline struct intel_crtc
*
1131 intel_get_crtc_for_plane(struct drm_i915_private
*dev_priv
, enum plane plane
)
1133 return dev_priv
->plane_to_crtc_mapping
[plane
];
1136 struct intel_load_detect_pipe
{
1137 struct drm_atomic_state
*restore_state
;
1140 static inline struct intel_encoder
*
1141 intel_attached_encoder(struct drm_connector
*connector
)
1143 return to_intel_connector(connector
)->encoder
;
1146 static inline struct intel_digital_port
*
1147 enc_to_dig_port(struct drm_encoder
*encoder
)
1149 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1151 switch (intel_encoder
->type
) {
1152 case INTEL_OUTPUT_UNKNOWN
:
1153 WARN_ON(!HAS_DDI(to_i915(encoder
->dev
)));
1154 case INTEL_OUTPUT_DP
:
1155 case INTEL_OUTPUT_EDP
:
1156 case INTEL_OUTPUT_HDMI
:
1157 return container_of(encoder
, struct intel_digital_port
,
1164 static inline struct intel_dp_mst_encoder
*
1165 enc_to_mst(struct drm_encoder
*encoder
)
1167 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1170 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1172 return &enc_to_dig_port(encoder
)->dp
;
1175 static inline struct intel_digital_port
*
1176 dp_to_dig_port(struct intel_dp
*intel_dp
)
1178 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1181 static inline struct intel_lspcon
*
1182 dp_to_lspcon(struct intel_dp
*intel_dp
)
1184 return &dp_to_dig_port(intel_dp
)->lspcon
;
1187 static inline struct intel_digital_port
*
1188 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1190 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1193 /* intel_fifo_underrun.c */
1194 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1195 enum pipe pipe
, bool enable
);
1196 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1197 enum pipe pch_transcoder
,
1199 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1201 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1202 enum pipe pch_transcoder
);
1203 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1204 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1207 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1208 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1209 void gen6_reset_pm_iir(struct drm_i915_private
*dev_priv
, u32 mask
);
1210 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1211 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1212 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1213 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1214 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1215 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1216 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1218 static inline u32
gen6_sanitize_rps_pm_mask(const struct drm_i915_private
*i915
,
1221 return mask
& ~i915
->rps
.pm_intrmsk_mbz
;
1224 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1225 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1226 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1229 * We only use drm_irq_uninstall() at unload and VT switch, so
1230 * this is the only thing we need to check.
1232 return dev_priv
->pm
.irqs_enabled
;
1235 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1236 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1238 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1240 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
);
1241 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1242 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1245 void intel_crt_init(struct drm_i915_private
*dev_priv
);
1246 void intel_crt_reset(struct drm_encoder
*encoder
);
1249 void intel_ddi_fdi_post_disable(struct intel_encoder
*intel_encoder
,
1250 struct intel_crtc_state
*old_crtc_state
,
1251 struct drm_connector_state
*old_conn_state
);
1252 void hsw_fdi_link_train(struct intel_crtc
*crtc
,
1253 const struct intel_crtc_state
*crtc_state
);
1254 void intel_ddi_init(struct drm_i915_private
*dev_priv
, enum port port
);
1255 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1256 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1257 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state
*crtc_state
);
1258 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1259 enum transcoder cpu_transcoder
);
1260 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1261 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1262 struct intel_encoder
*
1263 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1264 void intel_ddi_set_pipe_settings(const struct intel_crtc_state
*crtc_state
);
1265 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1266 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1267 bool intel_ddi_is_audio_enabled(struct drm_i915_private
*dev_priv
,
1268 struct intel_crtc
*intel_crtc
);
1269 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1270 struct intel_crtc_state
*pipe_config
);
1272 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1273 struct intel_crtc_state
*pipe_config
);
1274 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
*crtc_state
,
1276 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1277 u8
intel_ddi_dp_voltage_max(struct intel_encoder
*encoder
);
1279 unsigned int intel_fb_align_height(const struct drm_framebuffer
*fb
,
1280 int plane
, unsigned int height
);
1283 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1284 void intel_audio_codec_enable(struct intel_encoder
*encoder
,
1285 const struct intel_crtc_state
*crtc_state
,
1286 const struct drm_connector_state
*conn_state
);
1287 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1288 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1289 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1290 void intel_audio_init(struct drm_i915_private
*dev_priv
);
1291 void intel_audio_deinit(struct drm_i915_private
*dev_priv
);
1294 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1295 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1296 void cnl_init_cdclk(struct drm_i915_private
*dev_priv
);
1297 void cnl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1298 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1299 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1300 void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv
);
1301 void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
);
1302 void intel_update_cdclk(struct drm_i915_private
*dev_priv
);
1303 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1304 bool intel_cdclk_state_compare(const struct intel_cdclk_state
*a
,
1305 const struct intel_cdclk_state
*b
);
1306 void intel_set_cdclk(struct drm_i915_private
*dev_priv
,
1307 const struct intel_cdclk_state
*cdclk_state
);
1309 /* intel_display.c */
1310 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1311 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1312 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
);
1313 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1314 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
);
1315 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1316 const char *name
, u32 reg
, int ref_freq
);
1317 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
1318 const char *name
, u32 reg
);
1319 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
);
1320 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
);
1321 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1322 unsigned int intel_fb_xy_to_linear(int x
, int y
,
1323 const struct intel_plane_state
*state
,
1325 void intel_add_fb_offsets(int *x
, int *y
,
1326 const struct intel_plane_state
*state
, int plane
);
1327 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1328 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
);
1329 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1330 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1331 int intel_display_suspend(struct drm_device
*dev
);
1332 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
);
1333 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1334 int intel_connector_init(struct intel_connector
*);
1335 struct intel_connector
*intel_connector_alloc(void);
1336 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1337 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1338 struct intel_encoder
*encoder
);
1339 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1340 struct drm_crtc
*crtc
);
1341 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1342 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1343 struct drm_file
*file_priv
);
1344 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1347 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1348 enum intel_output_type type
)
1350 return crtc_state
->output_types
& (1 << type
);
1353 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1355 return crtc_state
->output_types
&
1356 ((1 << INTEL_OUTPUT_DP
) |
1357 (1 << INTEL_OUTPUT_DP_MST
) |
1358 (1 << INTEL_OUTPUT_EDP
));
1361 intel_wait_for_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1363 drm_wait_one_vblank(&dev_priv
->drm
, pipe
);
1366 intel_wait_for_vblank_if_active(struct drm_i915_private
*dev_priv
, int pipe
)
1368 const struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1371 intel_wait_for_vblank(dev_priv
, pipe
);
1374 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1376 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1377 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1378 struct intel_digital_port
*dport
,
1379 unsigned int expected_mask
);
1380 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
1381 struct drm_display_mode
*mode
,
1382 struct intel_load_detect_pipe
*old
,
1383 struct drm_modeset_acquire_ctx
*ctx
);
1384 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1385 struct intel_load_detect_pipe
*old
,
1386 struct drm_modeset_acquire_ctx
*ctx
);
1388 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
);
1389 void intel_unpin_fb_vma(struct i915_vma
*vma
);
1390 struct drm_framebuffer
*
1391 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
1392 struct drm_mode_fb_cmd2
*mode_cmd
);
1393 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1394 struct drm_plane_state
*new_state
);
1395 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1396 struct drm_plane_state
*old_state
);
1397 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1398 const struct drm_plane_state
*state
,
1399 struct drm_property
*property
,
1401 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1402 struct drm_plane_state
*state
,
1403 struct drm_property
*property
,
1405 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1406 struct drm_plane_state
*plane_state
);
1408 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1411 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1412 const struct dpll
*dpll
);
1413 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1414 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1416 /* modesetting asserts */
1417 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1419 void assert_pll(struct drm_i915_private
*dev_priv
,
1420 enum pipe pipe
, bool state
);
1421 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1422 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1423 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1424 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1425 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1426 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1427 enum pipe pipe
, bool state
);
1428 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1429 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1430 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1431 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1432 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1433 u32
intel_compute_tile_offset(int *x
, int *y
,
1434 const struct intel_plane_state
*state
, int plane
);
1435 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1436 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1437 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1438 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1439 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1440 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1441 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1442 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1443 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1444 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1445 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1446 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1447 struct intel_crtc_state
*pipe_config
);
1448 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1449 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1450 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1451 struct dpll
*best_clock
);
1452 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1454 bool intel_crtc_active(struct intel_crtc
*crtc
);
1455 void hsw_enable_ips(struct intel_crtc
*crtc
);
1456 void hsw_disable_ips(struct intel_crtc
*crtc
);
1457 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
);
1458 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1459 struct intel_crtc_state
*pipe_config
);
1461 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1462 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1464 static inline u32
intel_plane_ggtt_offset(const struct intel_plane_state
*state
)
1466 return i915_ggtt_offset(state
->vma
);
1469 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
1470 const struct intel_plane_state
*plane_state
);
1471 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
1472 unsigned int rotation
);
1473 int skl_check_plane_surface(struct intel_plane_state
*plane_state
);
1474 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
);
1477 void intel_csr_ucode_init(struct drm_i915_private
*);
1478 void intel_csr_load_program(struct drm_i915_private
*);
1479 void intel_csr_ucode_fini(struct drm_i915_private
*);
1480 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1481 void intel_csr_ucode_resume(struct drm_i915_private
*);
1484 bool intel_dp_init(struct drm_i915_private
*dev_priv
, i915_reg_t output_reg
,
1486 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1487 struct intel_connector
*intel_connector
);
1488 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1489 int link_rate
, uint8_t lane_count
,
1491 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
1492 int link_rate
, uint8_t lane_count
);
1493 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1494 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1495 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1496 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1497 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1498 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1499 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1500 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1501 struct intel_crtc_state
*pipe_config
,
1502 struct drm_connector_state
*conn_state
);
1503 bool intel_dp_is_edp(struct intel_dp
*intel_dp
);
1504 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
1505 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1507 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
1508 const struct drm_connector_state
*conn_state
);
1509 void intel_edp_backlight_off(const struct drm_connector_state
*conn_state
);
1510 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1511 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1512 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1513 void intel_dp_mst_suspend(struct drm_device
*dev
);
1514 void intel_dp_mst_resume(struct drm_device
*dev
);
1515 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1516 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
);
1517 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1518 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1519 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1520 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1521 void intel_plane_destroy(struct drm_plane
*plane
);
1522 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
1523 struct intel_crtc_state
*crtc_state
);
1524 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
1525 struct intel_crtc_state
*crtc_state
);
1526 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
1527 unsigned int frontbuffer_bits
);
1528 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
1529 unsigned int frontbuffer_bits
);
1532 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1533 uint8_t dp_train_pat
);
1535 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1536 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1538 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1540 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1541 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1542 uint8_t *link_bw
, uint8_t *rate_select
);
1543 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1545 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1547 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1549 return ~((1 << lane_count
) - 1) & 0xf;
1552 bool intel_dp_read_dpcd(struct intel_dp
*intel_dp
);
1553 int intel_dp_link_required(int pixel_clock
, int bpp
);
1554 int intel_dp_max_data_rate(int max_link_clock
, int max_lanes
);
1555 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1556 struct intel_digital_port
*port
);
1558 /* intel_dp_aux_backlight.c */
1559 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1561 /* intel_dp_mst.c */
1562 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1563 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1565 void intel_dsi_init(struct drm_i915_private
*dev_priv
);
1567 /* intel_dsi_dcs_backlight.c */
1568 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1571 void intel_dvo_init(struct drm_i915_private
*dev_priv
);
1572 /* intel_hotplug.c */
1573 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1576 /* legacy fbdev emulation in intel_fbdev.c */
1577 #ifdef CONFIG_DRM_FBDEV_EMULATION
1578 extern int intel_fbdev_init(struct drm_device
*dev
);
1579 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1580 extern void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
);
1581 extern void intel_fbdev_fini(struct drm_i915_private
*dev_priv
);
1582 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1583 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1584 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1586 static inline int intel_fbdev_init(struct drm_device
*dev
)
1591 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1595 static inline void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
)
1599 static inline void intel_fbdev_fini(struct drm_i915_private
*dev_priv
)
1603 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1607 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
1611 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1617 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1618 struct drm_atomic_state
*state
);
1619 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1620 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
1621 struct intel_crtc_state
*crtc_state
,
1622 struct intel_plane_state
*plane_state
);
1623 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1624 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1625 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1626 void intel_fbc_enable(struct intel_crtc
*crtc
,
1627 struct intel_crtc_state
*crtc_state
,
1628 struct intel_plane_state
*plane_state
);
1629 void intel_fbc_disable(struct intel_crtc
*crtc
);
1630 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1631 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1632 unsigned int frontbuffer_bits
,
1633 enum fb_op_origin origin
);
1634 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1635 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1636 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1637 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
);
1640 void intel_hdmi_init(struct drm_i915_private
*dev_priv
, i915_reg_t hdmi_reg
,
1642 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1643 struct intel_connector
*intel_connector
);
1644 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1645 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1646 struct intel_crtc_state
*pipe_config
,
1647 struct drm_connector_state
*conn_state
);
1648 void intel_hdmi_handle_sink_scrambling(struct intel_encoder
*intel_encoder
,
1649 struct drm_connector
*connector
,
1650 bool high_tmds_clock_ratio
,
1652 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
1656 void intel_lvds_init(struct drm_i915_private
*dev_priv
);
1657 struct intel_encoder
*intel_get_lvds_encoder(struct drm_device
*dev
);
1658 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1662 int intel_connector_update_modes(struct drm_connector
*connector
,
1664 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1665 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1666 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1667 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1670 /* intel_overlay.c */
1671 void intel_setup_overlay(struct drm_i915_private
*dev_priv
);
1672 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
);
1673 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1674 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1675 struct drm_file
*file_priv
);
1676 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1677 struct drm_file
*file_priv
);
1678 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1682 int intel_panel_init(struct intel_panel
*panel
,
1683 struct drm_display_mode
*fixed_mode
,
1684 struct drm_display_mode
*alt_fixed_mode
,
1685 struct drm_display_mode
*downclock_mode
);
1686 void intel_panel_fini(struct intel_panel
*panel
);
1687 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1688 struct drm_display_mode
*adjusted_mode
);
1689 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1690 struct intel_crtc_state
*pipe_config
,
1692 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1693 struct intel_crtc_state
*pipe_config
,
1695 void intel_panel_set_backlight_acpi(const struct drm_connector_state
*conn_state
,
1696 u32 level
, u32 max
);
1697 int intel_panel_setup_backlight(struct drm_connector
*connector
,
1699 void intel_panel_enable_backlight(const struct intel_crtc_state
*crtc_state
,
1700 const struct drm_connector_state
*conn_state
);
1701 void intel_panel_disable_backlight(const struct drm_connector_state
*old_conn_state
);
1702 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1703 enum drm_connector_status
intel_panel_detect(struct drm_i915_private
*dev_priv
);
1704 extern struct drm_display_mode
*intel_find_panel_downclock(
1705 struct drm_i915_private
*dev_priv
,
1706 struct drm_display_mode
*fixed_mode
,
1707 struct drm_connector
*connector
);
1709 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1710 int intel_backlight_device_register(struct intel_connector
*connector
);
1711 void intel_backlight_device_unregister(struct intel_connector
*connector
);
1712 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1713 static int intel_backlight_device_register(struct intel_connector
*connector
)
1717 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
1720 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1724 void intel_psr_enable(struct intel_dp
*intel_dp
);
1725 void intel_psr_disable(struct intel_dp
*intel_dp
);
1726 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
1727 unsigned frontbuffer_bits
);
1728 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
1729 unsigned frontbuffer_bits
,
1730 enum fb_op_origin origin
);
1731 void intel_psr_init(struct drm_i915_private
*dev_priv
);
1732 void intel_psr_single_frame_update(struct drm_i915_private
*dev_priv
,
1733 unsigned frontbuffer_bits
);
1735 /* intel_runtime_pm.c */
1736 int intel_power_domains_init(struct drm_i915_private
*);
1737 void intel_power_domains_fini(struct drm_i915_private
*);
1738 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1739 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1740 void intel_power_domains_verify_state(struct drm_i915_private
*dev_priv
);
1741 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1742 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1743 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1745 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1747 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1748 enum intel_display_power_domain domain
);
1749 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1750 enum intel_display_power_domain domain
);
1751 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1752 enum intel_display_power_domain domain
);
1753 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1754 enum intel_display_power_domain domain
);
1755 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1756 enum intel_display_power_domain domain
);
1759 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1761 WARN_ONCE(dev_priv
->pm
.suspended
,
1762 "Device suspended during HW access\n");
1766 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1768 assert_rpm_device_not_suspended(dev_priv
);
1769 WARN_ONCE(!atomic_read(&dev_priv
->pm
.wakeref_count
),
1770 "RPM wakelock ref not held during HW access");
1774 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1775 * @dev_priv: i915 device instance
1777 * This function disable asserts that check if we hold an RPM wakelock
1778 * reference, while keeping the device-not-suspended checks still enabled.
1779 * It's meant to be used only in special circumstances where our rule about
1780 * the wakelock refcount wrt. the device power state doesn't hold. According
1781 * to this rule at any point where we access the HW or want to keep the HW in
1782 * an active state we must hold an RPM wakelock reference acquired via one of
1783 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1784 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1785 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1786 * users should avoid using this function.
1788 * Any calls to this function must have a symmetric call to
1789 * enable_rpm_wakeref_asserts().
1792 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1794 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1798 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1799 * @dev_priv: i915 device instance
1801 * This function re-enables the RPM assert checks after disabling them with
1802 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1803 * circumstances otherwise its use should be avoided.
1805 * Any calls to this function must have a symmetric call to
1806 * disable_rpm_wakeref_asserts().
1809 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1811 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1814 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1815 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1816 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1817 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1819 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1821 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1822 bool override
, unsigned int mask
);
1823 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1824 enum dpio_channel ch
, bool override
);
1828 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
);
1829 void intel_suspend_hw(struct drm_i915_private
*dev_priv
);
1830 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
);
1831 void intel_update_watermarks(struct intel_crtc
*crtc
);
1832 void intel_init_pm(struct drm_i915_private
*dev_priv
);
1833 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1834 void intel_pm_setup(struct drm_i915_private
*dev_priv
);
1835 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1836 void intel_gpu_ips_teardown(void);
1837 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
1838 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
1839 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
);
1840 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
1841 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
);
1842 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
1843 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
);
1844 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1845 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1846 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1847 void gen6_rps_boost(struct drm_i915_gem_request
*rq
,
1848 struct intel_rps_client
*rps
);
1849 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
);
1850 void g4x_wm_get_hw_state(struct drm_device
*dev
);
1851 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1852 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1853 void skl_wm_get_hw_state(struct drm_device
*dev
);
1854 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1855 struct skl_ddb_allocation
*ddb
/* out */);
1856 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
1857 struct skl_pipe_wm
*out
);
1858 void g4x_wm_sanitize(struct drm_i915_private
*dev_priv
);
1859 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
);
1860 bool intel_can_enable_sagv(struct drm_atomic_state
*state
);
1861 int intel_enable_sagv(struct drm_i915_private
*dev_priv
);
1862 int intel_disable_sagv(struct drm_i915_private
*dev_priv
);
1863 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
1864 const struct skl_wm_level
*l2
);
1865 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
**entries
,
1866 const struct skl_ddb_entry
*ddb
,
1868 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1869 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
);
1870 int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc
,
1871 struct intel_crtc_state
*cstate
);
1872 static inline int intel_enable_rc6(void)
1874 return i915
.enable_rc6
;
1878 bool intel_sdvo_init(struct drm_i915_private
*dev_priv
,
1879 i915_reg_t reg
, enum port port
);
1882 /* intel_sprite.c */
1883 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
1885 struct intel_plane
*intel_sprite_plane_create(struct drm_i915_private
*dev_priv
,
1886 enum pipe pipe
, int plane
);
1887 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1888 struct drm_file
*file_priv
);
1889 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1890 void intel_pipe_update_end(struct intel_crtc
*crtc
);
1893 void intel_tv_init(struct drm_i915_private
*dev_priv
);
1895 /* intel_atomic.c */
1896 int intel_digital_connector_atomic_get_property(struct drm_connector
*connector
,
1897 const struct drm_connector_state
*state
,
1898 struct drm_property
*property
,
1900 int intel_digital_connector_atomic_set_property(struct drm_connector
*connector
,
1901 struct drm_connector_state
*state
,
1902 struct drm_property
*property
,
1904 int intel_digital_connector_atomic_check(struct drm_connector
*conn
,
1905 struct drm_connector_state
*new_state
);
1906 struct drm_connector_state
*
1907 intel_digital_connector_duplicate_state(struct drm_connector
*connector
);
1909 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1910 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1911 struct drm_crtc_state
*state
);
1912 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1913 void intel_atomic_state_clear(struct drm_atomic_state
*);
1915 static inline struct intel_crtc_state
*
1916 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1917 struct intel_crtc
*crtc
)
1919 struct drm_crtc_state
*crtc_state
;
1920 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1921 if (IS_ERR(crtc_state
))
1922 return ERR_CAST(crtc_state
);
1924 return to_intel_crtc_state(crtc_state
);
1927 static inline struct intel_crtc_state
*
1928 intel_atomic_get_existing_crtc_state(struct drm_atomic_state
*state
,
1929 struct intel_crtc
*crtc
)
1931 struct drm_crtc_state
*crtc_state
;
1933 crtc_state
= drm_atomic_get_existing_crtc_state(state
, &crtc
->base
);
1936 return to_intel_crtc_state(crtc_state
);
1941 static inline struct intel_plane_state
*
1942 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1943 struct intel_plane
*plane
)
1945 struct drm_plane_state
*plane_state
;
1947 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1949 return to_intel_plane_state(plane_state
);
1952 int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv
,
1953 struct intel_crtc
*intel_crtc
,
1954 struct intel_crtc_state
*crtc_state
);
1956 /* intel_atomic_plane.c */
1957 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1958 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1959 void intel_plane_destroy_state(struct drm_plane
*plane
,
1960 struct drm_plane_state
*state
);
1961 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1962 int intel_plane_atomic_check_with_state(struct intel_crtc_state
*crtc_state
,
1963 struct intel_plane_state
*intel_state
);
1966 void intel_color_init(struct drm_crtc
*crtc
);
1967 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
1968 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
1969 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
1971 /* intel_lspcon.c */
1972 bool lspcon_init(struct intel_digital_port
*intel_dig_port
);
1973 void lspcon_resume(struct intel_lspcon
*lspcon
);
1974 void lspcon_wait_pcon_mode(struct intel_lspcon
*lspcon
);
1976 /* intel_pipe_crc.c */
1977 int intel_pipe_crc_create(struct drm_minor
*minor
);
1978 #ifdef CONFIG_DEBUG_FS
1979 int intel_crtc_set_crc_source(struct drm_crtc
*crtc
, const char *source_name
,
1980 size_t *values_cnt
);
1982 #define intel_crtc_set_crc_source NULL
1984 extern const struct file_operations i915_display_crc_ctl_fops
;
1985 #endif /* __INTEL_DRV_H__ */