drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__;                                                      \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 if (COND) {                                             \
  59                         ret__ = 0;                                      \
  60                         break;                                          \
  61                 }                                                       \
  62                 if (expired__) {                                        \
  63                         ret__ = -ETIMEDOUT;                             \
  64                         break;                                          \
  65                 }                                                       \
  66                 if ((W) && drm_can_sleep()) {                           \
  67                         usleep_range((W), (W)*2);                       \
  68                 } else {                                                \
  69                         cpu_relax();                                    \
  70                 }                                                       \
  71         }                                                               \
  72         ret__;                                                          \
  73 })
  74
  75 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  76
  77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  80 #else
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  82 #endif
  83
  84 #define _wait_for_atomic(COND, US, ATOMIC) \
  85 ({ \
  86         int cpu, ret, timeout = (US) * 1000; \
  87         u64 base; \
  88         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  89         BUILD_BUG_ON((US) > 50000); \
  90         if (!(ATOMIC)) { \
  91                 preempt_disable(); \
  92                 cpu = smp_processor_id(); \
  93         } \
  94         base = local_clock(); \
  95         for (;;) { \
  96                 u64 now = local_clock(); \
  97                 if (!(ATOMIC)) \
  98                         preempt_enable(); \
  99                 if (COND) { \
 100                         ret = 0; \
 101                         break; \
 102                 } \
 103                 if (now - base >= timeout) { \
 104                         ret = -ETIMEDOUT; \
 105                         break; \
 106                 } \
 107                 cpu_relax(); \
 108                 if (!(ATOMIC)) { \
 109                         preempt_disable(); \
 110                         if (unlikely(cpu != smp_processor_id())) { \
 111                                 timeout -= now - base; \
 112                                 cpu = smp_processor_id(); \
 113                                 base = local_clock(); \
 114                         } \
 115                 } \
 116         } \
 117         ret; \
 118 })
 119
 120 #define wait_for_us(COND, US) \
 121 ({ \
 122         int ret__; \
 123         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 124         if ((US) > 10) \
 125                 ret__ = _wait_for((COND), (US), 10); \
 126         else \
 127                 ret__ = _wait_for_atomic((COND), (US), 0); \
 128         ret__; \
 129 })
 130
 131 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 132 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 133
 134 #define KHz(x) (1000 * (x))
 135 #define MHz(x) KHz(1000 * (x))
 136
 137 /*
 138  * Display related stuff
 139  */
 140
 141 /* store information about an Ixxx DVO */
 142 /* The i830->i865 use multiple DVOs with multiple i2cs */
 143 /* the i915, i945 have a single sDVO i2c bus - which is different */
 144 #define MAX_OUTPUTS 6
 145 /* maximum connectors per crtcs in the mode set */
 146
 147 /* Maximum cursor sizes */
 148 #define GEN2_CURSOR_WIDTH 64
 149 #define GEN2_CURSOR_HEIGHT 64
 150 #define MAX_CURSOR_WIDTH 256
 151 #define MAX_CURSOR_HEIGHT 256
 152
 153 #define INTEL_I2C_BUS_DVO 1
 154 #define INTEL_I2C_BUS_SDVO 2
 155
 156 /* these are outputs from the chip - integrated only
 157    external chips are via DVO or SDVO output */
 158 enum intel_output_type {
 159         INTEL_OUTPUT_UNUSED = 0,
 160         INTEL_OUTPUT_ANALOG = 1,
 161         INTEL_OUTPUT_DVO = 2,
 162         INTEL_OUTPUT_SDVO = 3,
 163         INTEL_OUTPUT_LVDS = 4,
 164         INTEL_OUTPUT_TVOUT = 5,
 165         INTEL_OUTPUT_HDMI = 6,
 166         INTEL_OUTPUT_DP = 7,
 167         INTEL_OUTPUT_EDP = 8,
 168         INTEL_OUTPUT_DSI = 9,
 169         INTEL_OUTPUT_UNKNOWN = 10,
 170         INTEL_OUTPUT_DP_MST = 11,
 171 };
 172
 173 #define INTEL_DVO_CHIP_NONE 0
 174 #define INTEL_DVO_CHIP_LVDS 1
 175 #define INTEL_DVO_CHIP_TMDS 2
 176 #define INTEL_DVO_CHIP_TVOUT 4
 177
 178 #define INTEL_DSI_VIDEO_MODE    0
 179 #define INTEL_DSI_COMMAND_MODE  1
 180
 181 struct intel_framebuffer {
 182         struct drm_framebuffer base;
 183         struct drm_i915_gem_object *obj;
 184         struct intel_rotation_info rot_info;
 185
 186         /* for each plane in the normal GTT view */
 187         struct {
 188                 unsigned int x, y;
 189         } normal[2];
 190         /* for each plane in the rotated GTT view */
 191         struct {
 192                 unsigned int x, y;
 193                 unsigned int pitch; /* pixels */
 194         } rotated[2];
 195 };
 196
 197 struct intel_fbdev {
 198         struct drm_fb_helper helper;
 199         struct intel_framebuffer *fb;
 200         struct i915_vma *vma;
 201         async_cookie_t cookie;
 202         int preferred_bpp;
 203 };
 204
 205 struct intel_encoder {
 206         struct drm_encoder base;
 207
 208         enum intel_output_type type;
 209         enum port port;
 210         unsigned int cloneable;
 211         void (*hot_plug)(struct intel_encoder *);
 212         bool (*compute_config)(struct intel_encoder *,
 213                                struct intel_crtc_state *,
 214                                struct drm_connector_state *);
 215         void (*pre_pll_enable)(struct intel_encoder *,
 216                                struct intel_crtc_state *,
 217                                struct drm_connector_state *);
 218         void (*pre_enable)(struct intel_encoder *,
 219                            struct intel_crtc_state *,
 220                            struct drm_connector_state *);
 221         void (*enable)(struct intel_encoder *,
 222                        struct intel_crtc_state *,
 223                        struct drm_connector_state *);
 224         void (*disable)(struct intel_encoder *,
 225                         struct intel_crtc_state *,
 226                         struct drm_connector_state *);
 227         void (*post_disable)(struct intel_encoder *,
 228                              struct intel_crtc_state *,
 229                              struct drm_connector_state *);
 230         void (*post_pll_disable)(struct intel_encoder *,
 231                                  struct intel_crtc_state *,
 232                                  struct drm_connector_state *);
 233         /* Read out the current hw state of this connector, returning true if
 234          * the encoder is active. If the encoder is enabled it also set the pipe
 235          * it is connected to in the pipe parameter. */
 236         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 237         /* Reconstructs the equivalent mode flags for the current hardware
 238          * state. This must be called _after_ display->get_pipe_config has
 239          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 240          * be set correctly before calling this function. */
 241         void (*get_config)(struct intel_encoder *,
 242                            struct intel_crtc_state *pipe_config);
 243         /*
 244          * Called during system suspend after all pending requests for the
 245          * encoder are flushed (for example for DP AUX transactions) and
 246          * device interrupts are disabled.
 247          */
 248         void (*suspend)(struct intel_encoder *);
 249         int crtc_mask;
 250         enum hpd_pin hpd_pin;
 251         /* for communication with audio component; protected by av_mutex */
 252         const struct drm_connector *audio_connector;
 253 };
 254
 255 struct intel_panel {
 256         struct drm_display_mode *fixed_mode;
 257         struct drm_display_mode *downclock_mode;
 258         int fitting_mode;
 259
 260         /* backlight */
 261         struct {
 262                 bool present;
 263                 u32 level;
 264                 u32 min;
 265                 u32 max;
 266                 bool enabled;
 267                 bool combination_mode;  /* gen 2/4 only */
 268                 bool active_low_pwm;
 269                 bool alternate_pwm_increment;   /* lpt+ */
 270
 271                 /* PWM chip */
 272                 bool util_pin_active_low;       /* bxt+ */
 273                 u8 controller;          /* bxt+ only */
 274                 struct pwm_device *pwm;
 275
 276                 struct backlight_device *device;
 277
 278                 /* Connector and platform specific backlight functions */
 279                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 280                 uint32_t (*get)(struct intel_connector *connector);
 281                 void (*set)(struct intel_connector *connector, uint32_t level);
 282                 void (*disable)(struct intel_connector *connector);
 283                 void (*enable)(struct intel_connector *connector);
 284                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 285                                       uint32_t hz);
 286                 void (*power)(struct intel_connector *, bool enable);
 287         } backlight;
 288 };
 289
 290 struct intel_connector {
 291         struct drm_connector base;
 292         /*
 293          * The fixed encoder this connector is connected to.
 294          */
 295         struct intel_encoder *encoder;
 296
 297         /* Reads out the current hw, returning true if the connector is enabled
 298          * and active (i.e. dpms ON state). */
 299         bool (*get_hw_state)(struct intel_connector *);
 300
 301         /* Panel info for eDP and LVDS */
 302         struct intel_panel panel;
 303
 304         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 305         struct edid *edid;
 306         struct edid *detect_edid;
 307
 308         /* since POLL and HPD connectors may use the same HPD line keep the native
 309            state of connector->polled in case hotplug storm detection changes it */
 310         u8 polled;
 311
 312         void *port; /* store this opaque as its illegal to dereference it */
 313
 314         struct intel_dp *mst_port;
 315 };
 316
 317 struct dpll {
 318         /* given values */
 319         int n;
 320         int m1, m2;
 321         int p1, p2;
 322         /* derived values */
 323         int     dot;
 324         int     vco;
 325         int     m;
 326         int     p;
 327 };
 328
 329 struct intel_atomic_state {
 330         struct drm_atomic_state base;
 331
 332         unsigned int cdclk;
 333
 334         /*
 335          * Calculated device cdclk, can be different from cdclk
 336          * only when all crtc's are DPMS off.
 337          */
 338         unsigned int dev_cdclk;
 339
 340         bool dpll_set, modeset;
 341
 342         /*
 343          * Does this transaction change the pipes that are active?  This mask
 344          * tracks which CRTC's have changed their active state at the end of
 345          * the transaction (not counting the temporary disable during modesets).
 346          * This mask should only be non-zero when intel_state->modeset is true,
 347          * but the converse is not necessarily true; simply changing a mode may
 348          * not flip the final active status of any CRTC's
 349          */
 350         unsigned int active_pipe_changes;
 351
 352         unsigned int active_crtcs;
 353         unsigned int min_pixclk[I915_MAX_PIPES];
 354
 355         /* SKL/KBL Only */
 356         unsigned int cdclk_pll_vco;
 357
 358         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 359
 360         /*
 361          * Current watermarks can't be trusted during hardware readout, so
 362          * don't bother calculating intermediate watermarks.
 363          */
 364         bool skip_intermediate_wm;
 365
 366         /* Gen9+ only */
 367         struct skl_wm_values wm_results;
 368
 369         struct i915_sw_fence commit_ready;
 370 };
 371
 372 struct intel_plane_state {
 373         struct drm_plane_state base;
 374         struct drm_rect clip;
 375
 376         struct {
 377                 u32 offset;
 378                 int x, y;
 379         } main;
 380         struct {
 381                 u32 offset;
 382                 int x, y;
 383         } aux;
 384
 385         /*
 386          * scaler_id
 387          *    = -1 : not using a scaler
 388          *    >=  0 : using a scalers
 389          *
 390          * plane requiring a scaler:
 391          *   - During check_plane, its bit is set in
 392          *     crtc_state->scaler_state.scaler_users by calling helper function
 393          *     update_scaler_plane.
 394          *   - scaler_id indicates the scaler it got assigned.
 395          *
 396          * plane doesn't require a scaler:
 397          *   - this can happen when scaling is no more required or plane simply
 398          *     got disabled.
 399          *   - During check_plane, corresponding bit is reset in
 400          *     crtc_state->scaler_state.scaler_users by calling helper function
 401          *     update_scaler_plane.
 402          */
 403         int scaler_id;
 404
 405         struct drm_intel_sprite_colorkey ckey;
 406 };
 407
 408 struct intel_initial_plane_config {
 409         struct intel_framebuffer *fb;
 410         unsigned int tiling;
 411         int size;
 412         u32 base;
 413 };
 414
 415 #define SKL_MIN_SRC_W 8
 416 #define SKL_MAX_SRC_W 4096
 417 #define SKL_MIN_SRC_H 8
 418 #define SKL_MAX_SRC_H 4096
 419 #define SKL_MIN_DST_W 8
 420 #define SKL_MAX_DST_W 4096
 421 #define SKL_MIN_DST_H 8
 422 #define SKL_MAX_DST_H 4096
 423
 424 struct intel_scaler {
 425         int in_use;
 426         uint32_t mode;
 427 };
 428
 429 struct intel_crtc_scaler_state {
 430 #define SKL_NUM_SCALERS 2
 431         struct intel_scaler scalers[SKL_NUM_SCALERS];
 432
 433         /*
 434          * scaler_users: keeps track of users requesting scalers on this crtc.
 435          *
 436          *     If a bit is set, a user is using a scaler.
 437          *     Here user can be a plane or crtc as defined below:
 438          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 439          *       bit 31    - crtc
 440          *
 441          * Instead of creating a new index to cover planes and crtc, using
 442          * existing drm_plane_index for planes which is well less than 31
 443          * planes and bit 31 for crtc. This should be fine to cover all
 444          * our platforms.
 445          *
 446          * intel_atomic_setup_scalers will setup available scalers to users
 447          * requesting scalers. It will gracefully fail if request exceeds
 448          * avilability.
 449          */
 450 #define SKL_CRTC_INDEX 31
 451         unsigned scaler_users;
 452
 453         /* scaler used by crtc for panel fitting purpose */
 454         int scaler_id;
 455 };
 456
 457 /* drm_mode->private_flags */
 458 #define I915_MODE_FLAG_INHERITED 1
 459
 460 struct intel_pipe_wm {
 461         struct intel_wm_level wm[5];
 462         struct intel_wm_level raw_wm[5];
 463         uint32_t linetime;
 464         bool fbc_wm_enabled;
 465         bool pipe_enabled;
 466         bool sprites_enabled;
 467         bool sprites_scaled;
 468 };
 469
 470 struct skl_plane_wm {
 471         struct skl_wm_level wm[8];
 472         struct skl_wm_level trans_wm;
 473 };
 474
 475 struct skl_pipe_wm {
 476         struct skl_plane_wm planes[I915_MAX_PLANES];
 477         uint32_t linetime;
 478 };
 479
 480 struct intel_crtc_wm_state {
 481         union {
 482                 struct {
 483                         /*
 484                          * Intermediate watermarks; these can be
 485                          * programmed immediately since they satisfy
 486                          * both the current configuration we're
 487                          * switching away from and the new
 488                          * configuration we're switching to.
 489                          */
 490                         struct intel_pipe_wm intermediate;
 491
 492                         /*
 493                          * Optimal watermarks, programmed post-vblank
 494                          * when this state is committed.
 495                          */
 496                         struct intel_pipe_wm optimal;
 497                 } ilk;
 498
 499                 struct {
 500                         /* gen9+ only needs 1-step wm programming */
 501                         struct skl_pipe_wm optimal;
 502                         struct skl_ddb_entry ddb;
 503                 } skl;
 504         };
 505
 506         /*
 507          * Platforms with two-step watermark programming will need to
 508          * update watermark programming post-vblank to switch from the
 509          * safe intermediate watermarks to the optimal final
 510          * watermarks.
 511          */
 512         bool need_postvbl_update;
 513 };
 514
 515 struct intel_crtc_state {
 516         struct drm_crtc_state base;
 517
 518         /**
 519          * quirks - bitfield with hw state readout quirks
 520          *
 521          * For various reasons the hw state readout code might not be able to
 522          * completely faithfully read out the current state. These cases are
 523          * tracked with quirk flags so that fastboot and state checker can act
 524          * accordingly.
 525          */
 526 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 527         unsigned long quirks;
 528
 529         unsigned fb_bits; /* framebuffers to flip */
 530         bool update_pipe; /* can a fast modeset be performed? */
 531         bool disable_cxsr;
 532         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 533         bool fb_changed; /* fb on any of the planes is changed */
 534
 535         /* Pipe source size (ie. panel fitter input size)
 536          * All planes will be positioned inside this space,
 537          * and get clipped at the edges. */
 538         int pipe_src_w, pipe_src_h;
 539
 540         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 541          * between pch encoders and cpu encoders. */
 542         bool has_pch_encoder;
 543
 544         /* Are we sending infoframes on the attached port */
 545         bool has_infoframe;
 546
 547         /* CPU Transcoder for the pipe. Currently this can only differ from the
 548          * pipe on Haswell and later (where we have a special eDP transcoder)
 549          * and Broxton (where we have special DSI transcoders). */
 550         enum transcoder cpu_transcoder;
 551
 552         /*
 553          * Use reduced/limited/broadcast rbg range, compressing from the full
 554          * range fed into the crtcs.
 555          */
 556         bool limited_color_range;
 557
 558         /* Bitmask of encoder types (enum intel_output_type)
 559          * driven by the pipe.
 560          */
 561         unsigned int output_types;
 562
 563         /* Whether we should send NULL infoframes. Required for audio. */
 564         bool has_hdmi_sink;
 565
 566         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 567          * has_dp_encoder is set. */
 568         bool has_audio;
 569
 570         /*
 571          * Enable dithering, used when the selected pipe bpp doesn't match the
 572          * plane bpp.
 573          */
 574         bool dither;
 575
 576         /* Controls for the clock computation, to override various stages. */
 577         bool clock_set;
 578
 579         /* SDVO TV has a bunch of special case. To make multifunction encoders
 580          * work correctly, we need to track this at runtime.*/
 581         bool sdvo_tv_clock;
 582
 583         /*
 584          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 585          * required. This is set in the 2nd loop of calling encoder's
 586          * ->compute_config if the first pick doesn't work out.
 587          */
 588         bool bw_constrained;
 589
 590         /* Settings for the intel dpll used on pretty much everything but
 591          * haswell. */
 592         struct dpll dpll;
 593
 594         /* Selected dpll when shared or NULL. */
 595         struct intel_shared_dpll *shared_dpll;
 596
 597         /* Actual register state of the dpll, for shared dpll cross-checking. */
 598         struct intel_dpll_hw_state dpll_hw_state;
 599
 600         /* DSI PLL registers */
 601         struct {
 602                 u32 ctrl, div;
 603         } dsi_pll;
 604
 605         int pipe_bpp;
 606         struct intel_link_m_n dp_m_n;
 607
 608         /* m2_n2 for eDP downclock */
 609         struct intel_link_m_n dp_m2_n2;
 610         bool has_drrs;
 611
 612         /*
 613          * Frequence the dpll for the port should run at. Differs from the
 614          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 615          * already multiplied by pixel_multiplier.
 616          */
 617         int port_clock;
 618
 619         /* Used by SDVO (and if we ever fix it, HDMI). */
 620         unsigned pixel_multiplier;
 621
 622         uint8_t lane_count;
 623
 624         /*
 625          * Used by platforms having DP/HDMI PHY with programmable lane
 626          * latency optimization.
 627          */
 628         uint8_t lane_lat_optim_mask;
 629
 630         /* Panel fitter controls for gen2-gen4 + VLV */
 631         struct {
 632                 u32 control;
 633                 u32 pgm_ratios;
 634                 u32 lvds_border_bits;
 635         } gmch_pfit;
 636
 637         /* Panel fitter placement and size for Ironlake+ */
 638         struct {
 639                 u32 pos;
 640                 u32 size;
 641                 bool enabled;
 642                 bool force_thru;
 643         } pch_pfit;
 644
 645         /* FDI configuration, only valid if has_pch_encoder is set. */
 646         int fdi_lanes;
 647         struct intel_link_m_n fdi_m_n;
 648
 649         bool ips_enabled;
 650
 651         bool enable_fbc;
 652
 653         bool double_wide;
 654
 655         bool dp_encoder_is_mst;
 656         int pbn;
 657
 658         struct intel_crtc_scaler_state scaler_state;
 659
 660         /* w/a for waiting 2 vblanks during crtc enable */
 661         enum pipe hsw_workaround_pipe;
 662
 663         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 664         bool disable_lp_wm;
 665
 666         struct intel_crtc_wm_state wm;
 667
 668         /* Gamma mode programmed on the pipe */
 669         uint32_t gamma_mode;
 670 };
 671
 672 struct vlv_wm_state {
 673         struct vlv_pipe_wm wm[3];
 674         struct vlv_sr_wm sr[3];
 675         uint8_t num_active_planes;
 676         uint8_t num_levels;
 677         uint8_t level;
 678         bool cxsr;
 679 };
 680
 681 struct intel_crtc {
 682         struct drm_crtc base;
 683         enum pipe pipe;
 684         enum plane plane;
 685         u8 lut_r[256], lut_g[256], lut_b[256];
 686         /*
 687          * Whether the crtc and the connected output pipeline is active. Implies
 688          * that crtc->enabled is set, i.e. the current mode configuration has
 689          * some outputs connected to this crtc.
 690          */
 691         bool active;
 692         unsigned long enabled_power_domains;
 693         bool lowfreq_avail;
 694         struct intel_overlay *overlay;
 695         struct intel_flip_work *flip_work;
 696
 697         atomic_t unpin_work_count;
 698
 699         /* Display surface base address adjustement for pageflips. Note that on
 700          * gen4+ this only adjusts up to a tile, offsets within a tile are
 701          * handled in the hw itself (with the TILEOFF register). */
 702         u32 dspaddr_offset;
 703         int adjusted_x;
 704         int adjusted_y;
 705
 706         uint32_t cursor_addr;
 707         uint32_t cursor_cntl;
 708         uint32_t cursor_size;
 709         uint32_t cursor_base;
 710
 711         struct intel_crtc_state *config;
 712
 713         /* global reset count when the last flip was submitted */
 714         unsigned int reset_count;
 715
 716         /* Access to these should be protected by dev_priv->irq_lock. */
 717         bool cpu_fifo_underrun_disabled;
 718         bool pch_fifo_underrun_disabled;
 719
 720         /* per-pipe watermark state */
 721         struct {
 722                 /* watermarks currently being used  */
 723                 union {
 724                         struct intel_pipe_wm ilk;
 725                 } active;
 726
 727                 /* allow CxSR on this pipe */
 728                 bool cxsr_allowed;
 729         } wm;
 730
 731         /* gen9+: ddb allocation currently being used */
 732         struct skl_ddb_entry hw_ddb;
 733
 734         int scanline_offset;
 735
 736         struct {
 737                 unsigned start_vbl_count;
 738                 ktime_t start_vbl_time;
 739                 int min_vbl, max_vbl;
 740                 int scanline_start;
 741         } debug;
 742
 743         /* scalers available on this crtc */
 744         int num_scalers;
 745
 746         struct vlv_wm_state wm_state;
 747 };
 748
 749 struct intel_plane_wm_parameters {
 750         uint32_t horiz_pixels;
 751         uint32_t vert_pixels;
 752         /*
 753          *   For packed pixel formats:
 754          *     bytes_per_pixel - holds bytes per pixel
 755          *   For planar pixel formats:
 756          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 757          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 758          */
 759         uint8_t bytes_per_pixel;
 760         uint8_t y_bytes_per_pixel;
 761         bool enabled;
 762         bool scaled;
 763         u64 tiling;
 764         unsigned int rotation;
 765         uint16_t fifo_size;
 766 };
 767
 768 struct intel_plane {
 769         struct drm_plane base;
 770         int plane;
 771         enum pipe pipe;
 772         bool can_scale;
 773         int max_downscale;
 774         uint32_t frontbuffer_bit;
 775
 776         /* Since we need to change the watermarks before/after
 777          * enabling/disabling the planes, we need to store the parameters here
 778          * as the other pieces of the struct may not reflect the values we want
 779          * for the watermark calculations. Currently only Haswell uses this.
 780          */
 781         struct intel_plane_wm_parameters wm;
 782
 783         /*
 784          * NOTE: Do not place new plane state fields here (e.g., when adding
 785          * new plane properties).  New runtime state should now be placed in
 786          * the intel_plane_state structure and accessed via plane_state.
 787          */
 788
 789         void (*update_plane)(struct drm_plane *plane,
 790                              const struct intel_crtc_state *crtc_state,
 791                              const struct intel_plane_state *plane_state);
 792         void (*disable_plane)(struct drm_plane *plane,
 793                               struct drm_crtc *crtc);
 794         int (*check_plane)(struct drm_plane *plane,
 795                            struct intel_crtc_state *crtc_state,
 796                            struct intel_plane_state *state);
 797 };
 798
 799 struct intel_watermark_params {
 800         u16 fifo_size;
 801         u16 max_wm;
 802         u8 default_wm;
 803         u8 guard_size;
 804         u8 cacheline_size;
 805 };
 806
 807 struct cxsr_latency {
 808         bool is_desktop : 1;
 809         bool is_ddr3 : 1;
 810         u16 fsb_freq;
 811         u16 mem_freq;
 812         u16 display_sr;
 813         u16 display_hpll_disable;
 814         u16 cursor_sr;
 815         u16 cursor_hpll_disable;
 816 };
 817
 818 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 819 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 820 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 821 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 822 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 823 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 824 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 825 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 826 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 827
 828 struct intel_hdmi {
 829         i915_reg_t hdmi_reg;
 830         int ddc_bus;
 831         struct {
 832                 enum drm_dp_dual_mode_type type;
 833                 int max_tmds_clock;
 834         } dp_dual_mode;
 835         bool limited_color_range;
 836         bool color_range_auto;
 837         bool has_hdmi_sink;
 838         bool has_audio;
 839         enum hdmi_force_audio force_audio;
 840         bool rgb_quant_range_selectable;
 841         enum hdmi_picture_aspect aspect_ratio;
 842         struct intel_connector *attached_connector;
 843         void (*write_infoframe)(struct drm_encoder *encoder,
 844                                 enum hdmi_infoframe_type type,
 845                                 const void *frame, ssize_t len);
 846         void (*set_infoframes)(struct drm_encoder *encoder,
 847                                bool enable,
 848                                const struct drm_display_mode *adjusted_mode);
 849         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 850                                   const struct intel_crtc_state *pipe_config);
 851 };
 852
 853 struct intel_dp_mst_encoder;
 854 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 855
 856 /*
 857  * enum link_m_n_set:
 858  *      When platform provides two set of M_N registers for dp, we can
 859  *      program them and switch between them incase of DRRS.
 860  *      But When only one such register is provided, we have to program the
 861  *      required divider value on that registers itself based on the DRRS state.
 862  *
 863  * M1_N1        : Program dp_m_n on M1_N1 registers
 864  *                        dp_m2_n2 on M2_N2 registers (If supported)
 865  *
 866  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 867  *                        M2_N2 registers are not supported
 868  */
 869
 870 enum link_m_n_set {
 871         /* Sets the m1_n1 and m2_n2 */
 872         M1_N1 = 0,
 873         M2_N2
 874 };
 875
 876 struct intel_dp_desc {
 877         u8 oui[3];
 878         u8 device_id[6];
 879         u8 hw_rev;
 880         u8 sw_major_rev;
 881         u8 sw_minor_rev;
 882 } __packed;
 883
 884 struct intel_dp {
 885         i915_reg_t output_reg;
 886         i915_reg_t aux_ch_ctl_reg;
 887         i915_reg_t aux_ch_data_reg[5];
 888         uint32_t DP;
 889         int link_rate;
 890         uint8_t lane_count;
 891         uint8_t sink_count;
 892         bool link_mst;
 893         bool has_audio;
 894         bool detect_done;
 895         bool channel_eq_status;
 896         enum hdmi_force_audio force_audio;
 897         bool limited_color_range;
 898         bool color_range_auto;
 899         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 900         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 901         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 902         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 903         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 904         uint8_t num_sink_rates;
 905         int sink_rates[DP_MAX_SUPPORTED_RATES];
 906         /* sink or branch descriptor */
 907         struct intel_dp_desc desc;
 908         struct drm_dp_aux aux;
 909         uint8_t train_set[4];
 910         int panel_power_up_delay;
 911         int panel_power_down_delay;
 912         int panel_power_cycle_delay;
 913         int backlight_on_delay;
 914         int backlight_off_delay;
 915         struct delayed_work panel_vdd_work;
 916         bool want_panel_vdd;
 917         unsigned long last_power_on;
 918         unsigned long last_backlight_off;
 919         ktime_t panel_power_off_time;
 920
 921         struct notifier_block edp_notifier;
 922
 923         /*
 924          * Pipe whose power sequencer is currently locked into
 925          * this port. Only relevant on VLV/CHV.
 926          */
 927         enum pipe pps_pipe;
 928         /*
 929          * Set if the sequencer may be reset due to a power transition,
 930          * requiring a reinitialization. Only relevant on BXT.
 931          */
 932         bool pps_reset;
 933         struct edp_power_seq pps_delays;
 934
 935         bool can_mst; /* this port supports mst */
 936         bool is_mst;
 937         int active_mst_links;
 938         /* connector directly attached - won't be use for modeset in mst world */
 939         struct intel_connector *attached_connector;
 940
 941         /* mst connector list */
 942         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 943         struct drm_dp_mst_topology_mgr mst_mgr;
 944
 945         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 946         /*
 947          * This function returns the value we have to program the AUX_CTL
 948          * register with to kick off an AUX transaction.
 949          */
 950         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 951                                      bool has_aux_irq,
 952                                      int send_bytes,
 953                                      uint32_t aux_clock_divider);
 954
 955         /* This is called before a link training is starterd */
 956         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 957
 958         /* Displayport compliance testing */
 959         unsigned long compliance_test_type;
 960         unsigned long compliance_test_data;
 961         bool compliance_test_active;
 962 };
 963
 964 struct intel_lspcon {
 965         bool active;
 966         enum drm_lspcon_mode mode;
 967         bool desc_valid;
 968 };
 969
 970 struct intel_digital_port {
 971         struct intel_encoder base;
 972         enum port port;
 973         u32 saved_port_bits;
 974         struct intel_dp dp;
 975         struct intel_hdmi hdmi;
 976         struct intel_lspcon lspcon;
 977         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 978         bool release_cl2_override;
 979         uint8_t max_lanes;
 980 };
 981
 982 struct intel_dp_mst_encoder {
 983         struct intel_encoder base;
 984         enum pipe pipe;
 985         struct intel_digital_port *primary;
 986         struct intel_connector *connector;
 987 };
 988
 989 static inline enum dpio_channel
 990 vlv_dport_to_channel(struct intel_digital_port *dport)
 991 {
 992         switch (dport->port) {
 993         case PORT_B:
 994         case PORT_D:
 995                 return DPIO_CH0;
 996         case PORT_C:
 997                 return DPIO_CH1;
 998         default:
 999                 BUG();
1000         }
1001 }
1002
1003 static inline enum dpio_phy
1004 vlv_dport_to_phy(struct intel_digital_port *dport)
1005 {
1006         switch (dport->port) {
1007         case PORT_B:
1008         case PORT_C:
1009                 return DPIO_PHY0;
1010         case PORT_D:
1011                 return DPIO_PHY1;
1012         default:
1013                 BUG();
1014         }
1015 }
1016
1017 static inline enum dpio_channel
1018 vlv_pipe_to_channel(enum pipe pipe)
1019 {
1020         switch (pipe) {
1021         case PIPE_A:
1022         case PIPE_C:
1023                 return DPIO_CH0;
1024         case PIPE_B:
1025                 return DPIO_CH1;
1026         default:
1027                 BUG();
1028         }
1029 }
1030
1031 static inline struct drm_crtc *
1032 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1033 {
1034         struct drm_i915_private *dev_priv = to_i915(dev);
1035         return dev_priv->pipe_to_crtc_mapping[pipe];
1036 }
1037
1038 static inline struct drm_crtc *
1039 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1040 {
1041         struct drm_i915_private *dev_priv = to_i915(dev);
1042         return dev_priv->plane_to_crtc_mapping[plane];
1043 }
1044
1045 struct intel_flip_work {
1046         struct work_struct unpin_work;
1047         struct work_struct mmio_work;
1048
1049         struct drm_crtc *crtc;
1050         struct drm_framebuffer *old_fb;
1051         struct drm_i915_gem_object *pending_flip_obj;
1052         struct drm_pending_vblank_event *event;
1053         atomic_t pending;
1054         u32 flip_count;
1055         u32 gtt_offset;
1056         struct drm_i915_gem_request *flip_queued_req;
1057         u32 flip_queued_vblank;
1058         u32 flip_ready_vblank;
1059         unsigned int rotation;
1060 };
1061
1062 struct intel_load_detect_pipe {
1063         struct drm_atomic_state *restore_state;
1064 };
1065
1066 static inline struct intel_encoder *
1067 intel_attached_encoder(struct drm_connector *connector)
1068 {
1069         return to_intel_connector(connector)->encoder;
1070 }
1071
1072 static inline struct intel_digital_port *
1073 enc_to_dig_port(struct drm_encoder *encoder)
1074 {
1075         return container_of(encoder, struct intel_digital_port, base.base);
1076 }
1077
1078 static inline struct intel_dp_mst_encoder *
1079 enc_to_mst(struct drm_encoder *encoder)
1080 {
1081         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1082 }
1083
1084 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1085 {
1086         return &enc_to_dig_port(encoder)->dp;
1087 }
1088
1089 static inline struct intel_digital_port *
1090 dp_to_dig_port(struct intel_dp *intel_dp)
1091 {
1092         return container_of(intel_dp, struct intel_digital_port, dp);
1093 }
1094
1095 static inline struct intel_digital_port *
1096 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1097 {
1098         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1099 }
1100
1101 /* intel_fifo_underrun.c */
1102 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1103                                            enum pipe pipe, bool enable);
1104 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1105                                            enum transcoder pch_transcoder,
1106                                            bool enable);
1107 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1108                                          enum pipe pipe);
1109 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1110                                          enum transcoder pch_transcoder);
1111 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1112 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1113
1114 /* i915_irq.c */
1115 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1116 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1117 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1118 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1119 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1120 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1121 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1122 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1123 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1124 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1125 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1126 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1127 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1128 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1129 {
1130         /*
1131          * We only use drm_irq_uninstall() at unload and VT switch, so
1132          * this is the only thing we need to check.
1133          */
1134         return dev_priv->pm.irqs_enabled;
1135 }
1136
1137 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1138 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1139                                      unsigned int pipe_mask);
1140 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1141                                      unsigned int pipe_mask);
1142 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1143 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1144 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1145
1146 /* intel_crt.c */
1147 void intel_crt_init(struct drm_device *dev);
1148 void intel_crt_reset(struct drm_encoder *encoder);
1149
1150 /* intel_ddi.c */
1151 void intel_ddi_clk_select(struct intel_encoder *encoder,
1152                           struct intel_shared_dpll *pll);
1153 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1154                                 struct intel_crtc_state *old_crtc_state,
1155                                 struct drm_connector_state *old_conn_state);
1156 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1157 void hsw_fdi_link_train(struct drm_crtc *crtc);
1158 void intel_ddi_init(struct drm_device *dev, enum port port);
1159 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1160 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1161 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1162 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1163                                        enum transcoder cpu_transcoder);
1164 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1165 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1166 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1167                           struct intel_crtc_state *crtc_state);
1168 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1169 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1170 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1171 void intel_ddi_get_config(struct intel_encoder *encoder,
1172                           struct intel_crtc_state *pipe_config);
1173 struct intel_encoder *
1174 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1175
1176 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1177 void intel_ddi_clock_get(struct intel_encoder *encoder,
1178                          struct intel_crtc_state *pipe_config);
1179 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1180 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1181 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1182                                                   int clock);
1183 unsigned int intel_fb_align_height(struct drm_device *dev,
1184                                    unsigned int height,
1185                                    uint32_t pixel_format,
1186                                    uint64_t fb_format_modifier);
1187 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1188                               uint64_t fb_modifier, uint32_t pixel_format);
1189
1190 /* intel_audio.c */
1191 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1192 void intel_audio_codec_enable(struct intel_encoder *encoder);
1193 void intel_audio_codec_disable(struct intel_encoder *encoder);
1194 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1195 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1196
1197 /* intel_display.c */
1198 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1199 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1200 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1201 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1202                       const char *name, u32 reg, int ref_freq);
1203 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1204 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1205 extern const struct drm_plane_funcs intel_plane_funcs;
1206 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1207 unsigned int intel_fb_xy_to_linear(int x, int y,
1208                                    const struct intel_plane_state *state,
1209                                    int plane);
1210 void intel_add_fb_offsets(int *x, int *y,
1211                           const struct intel_plane_state *state, int plane);
1212 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1213 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1214 void intel_mark_busy(struct drm_i915_private *dev_priv);
1215 void intel_mark_idle(struct drm_i915_private *dev_priv);
1216 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1217 int intel_display_suspend(struct drm_device *dev);
1218 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1219 void intel_encoder_destroy(struct drm_encoder *encoder);
1220 int intel_connector_init(struct intel_connector *);
1221 struct intel_connector *intel_connector_alloc(void);
1222 bool intel_connector_get_hw_state(struct intel_connector *connector);
1223 void intel_connector_attach_encoder(struct intel_connector *connector,
1224                                     struct intel_encoder *encoder);
1225 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1226                                              struct drm_crtc *crtc);
1227 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1228 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1229                                 struct drm_file *file_priv);
1230 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1231                                              enum pipe pipe);
1232 static inline bool
1233 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1234                     enum intel_output_type type)
1235 {
1236         return crtc_state->output_types & (1 << type);
1237 }
1238 static inline bool
1239 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1240 {
1241         return crtc_state->output_types &
1242                 ((1 << INTEL_OUTPUT_DP) |
1243                  (1 << INTEL_OUTPUT_DP_MST) |
1244                  (1 << INTEL_OUTPUT_EDP));
1245 }
1246 static inline void
1247 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1248 {
1249         drm_wait_one_vblank(dev, pipe);
1250 }
1251 static inline void
1252 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1253 {
1254         const struct intel_crtc *crtc =
1255                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1256
1257         if (crtc->active)
1258                 intel_wait_for_vblank(dev, pipe);
1259 }
1260
1261 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1262
1263 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1264 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1265                          struct intel_digital_port *dport,
1266                          unsigned int expected_mask);
1267 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1268                                 struct drm_display_mode *mode,
1269                                 struct intel_load_detect_pipe *old,
1270                                 struct drm_modeset_acquire_ctx *ctx);
1271 void intel_release_load_detect_pipe(struct drm_connector *connector,
1272                                     struct intel_load_detect_pipe *old,
1273                                     struct drm_modeset_acquire_ctx *ctx);
1274 struct i915_vma *
1275 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1276 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1277 struct drm_framebuffer *
1278 __intel_framebuffer_create(struct drm_device *dev,
1279                            struct drm_mode_fb_cmd2 *mode_cmd,
1280                            struct drm_i915_gem_object *obj);
1281 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1282 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1283 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1284 int intel_prepare_plane_fb(struct drm_plane *plane,
1285                            struct drm_plane_state *new_state);
1286 void intel_cleanup_plane_fb(struct drm_plane *plane,
1287                             struct drm_plane_state *old_state);
1288 int intel_plane_atomic_get_property(struct drm_plane *plane,
1289                                     const struct drm_plane_state *state,
1290                                     struct drm_property *property,
1291                                     uint64_t *val);
1292 int intel_plane_atomic_set_property(struct drm_plane *plane,
1293                                     struct drm_plane_state *state,
1294                                     struct drm_property *property,
1295                                     uint64_t val);
1296 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1297                                     struct drm_plane_state *plane_state);
1298
1299 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1300                                uint64_t fb_modifier, unsigned int cpp);
1301
1302 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1303                                     enum pipe pipe);
1304
1305 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1306                      const struct dpll *dpll);
1307 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1308 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1309
1310 /* modesetting asserts */
1311 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1312                            enum pipe pipe);
1313 void assert_pll(struct drm_i915_private *dev_priv,
1314                 enum pipe pipe, bool state);
1315 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1316 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1317 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1318 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1319 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1320 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1321                        enum pipe pipe, bool state);
1322 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1323 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1324 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1325 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1326 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1327 u32 intel_compute_tile_offset(int *x, int *y,
1328                               const struct intel_plane_state *state, int plane);
1329 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1330 void intel_finish_reset(struct drm_i915_private *dev_priv);
1331 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1332 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1333 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1334 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1335 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1336 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1337 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1338 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1339 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1340 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1341 unsigned int skl_cdclk_get_vco(unsigned int freq);
1342 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1343 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1344 void intel_dp_get_m_n(struct intel_crtc *crtc,
1345                       struct intel_crtc_state *pipe_config);
1346 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1347 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1348 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1349                         struct dpll *best_clock);
1350 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1351
1352 bool intel_crtc_active(struct intel_crtc *crtc);
1353 void hsw_enable_ips(struct intel_crtc *crtc);
1354 void hsw_disable_ips(struct intel_crtc *crtc);
1355 enum intel_display_power_domain
1356 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1357 enum intel_display_power_domain
1358 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1359 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1360                                  struct intel_crtc_state *pipe_config);
1361
1362 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1363 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1364
1365 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1366
1367 u32 skl_plane_ctl_format(uint32_t pixel_format);
1368 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1369 u32 skl_plane_ctl_rotation(unsigned int rotation);
1370 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1371                      unsigned int rotation);
1372 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1373
1374 /* intel_csr.c */
1375 void intel_csr_ucode_init(struct drm_i915_private *);
1376 void intel_csr_load_program(struct drm_i915_private *);
1377 void intel_csr_ucode_fini(struct drm_i915_private *);
1378 void intel_csr_ucode_suspend(struct drm_i915_private *);
1379 void intel_csr_ucode_resume(struct drm_i915_private *);
1380
1381 /* intel_dp.c */
1382 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1383 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1384                              struct intel_connector *intel_connector);
1385 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1386                               int link_rate, uint8_t lane_count,
1387                               bool link_mst);
1388 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1389 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1390 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1391 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1392 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1393 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1394 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1395 bool intel_dp_compute_config(struct intel_encoder *encoder,
1396                              struct intel_crtc_state *pipe_config,
1397                              struct drm_connector_state *conn_state);
1398 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1399 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1400                                   bool long_hpd);
1401 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1402 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1403 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1404 void intel_edp_panel_on(struct intel_dp *intel_dp);
1405 void intel_edp_panel_off(struct intel_dp *intel_dp);
1406 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1407 void intel_dp_mst_suspend(struct drm_device *dev);
1408 void intel_dp_mst_resume(struct drm_device *dev);
1409 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1410 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1411 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1412 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1413 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1414 void intel_plane_destroy(struct drm_plane *plane);
1415 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1416                            struct intel_crtc_state *crtc_state);
1417 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1418                            struct intel_crtc_state *crtc_state);
1419 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1420                                unsigned int frontbuffer_bits);
1421 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1422                           unsigned int frontbuffer_bits);
1423
1424 void
1425 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1426                                        uint8_t dp_train_pat);
1427 void
1428 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1429 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1430 uint8_t
1431 intel_dp_voltage_max(struct intel_dp *intel_dp);
1432 uint8_t
1433 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1434 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1435                            uint8_t *link_bw, uint8_t *rate_select);
1436 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1437 bool
1438 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1439
1440 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1441 {
1442         return ~((1 << lane_count) - 1) & 0xf;
1443 }
1444
1445 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1446 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1447                           struct intel_dp_desc *desc);
1448 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1449
1450 /* intel_dp_aux_backlight.c */
1451 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1452
1453 /* intel_dp_mst.c */
1454 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1455 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1456 /* intel_dsi.c */
1457 void intel_dsi_init(struct drm_device *dev);
1458
1459 /* intel_dsi_dcs_backlight.c */
1460 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1461
1462 /* intel_dvo.c */
1463 void intel_dvo_init(struct drm_device *dev);
1464 /* intel_hotplug.c */
1465 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1466
1467
1468 /* legacy fbdev emulation in intel_fbdev.c */
1469 #ifdef CONFIG_DRM_FBDEV_EMULATION
1470 extern int intel_fbdev_init(struct drm_device *dev);
1471 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1472 extern void intel_fbdev_fini(struct drm_device *dev);
1473 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1474 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1475 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1476 #else
1477 static inline int intel_fbdev_init(struct drm_device *dev)
1478 {
1479         return 0;
1480 }
1481
1482 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1483 {
1484 }
1485
1486 static inline void intel_fbdev_fini(struct drm_device *dev)
1487 {
1488 }
1489
1490 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1491 {
1492 }
1493
1494 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1495 {
1496 }
1497
1498 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1499 {
1500 }
1501 #endif
1502
1503 /* intel_fbc.c */
1504 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1505                            struct drm_atomic_state *state);
1506 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1507 void intel_fbc_pre_update(struct intel_crtc *crtc,
1508                           struct intel_crtc_state *crtc_state,
1509                           struct intel_plane_state *plane_state);
1510 void intel_fbc_post_update(struct intel_crtc *crtc);
1511 void intel_fbc_init(struct drm_i915_private *dev_priv);
1512 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1513 void intel_fbc_enable(struct intel_crtc *crtc,
1514                       struct intel_crtc_state *crtc_state,
1515                       struct intel_plane_state *plane_state);
1516 void intel_fbc_disable(struct intel_crtc *crtc);
1517 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1518 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1519                           unsigned int frontbuffer_bits,
1520                           enum fb_op_origin origin);
1521 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1522                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1523 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1524 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1525
1526 /* intel_hdmi.c */
1527 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1528 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1529                                struct intel_connector *intel_connector);
1530 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1531 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1532                                struct intel_crtc_state *pipe_config,
1533                                struct drm_connector_state *conn_state);
1534 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1535
1536
1537 /* intel_lvds.c */
1538 void intel_lvds_init(struct drm_device *dev);
1539 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1540 bool intel_is_dual_link_lvds(struct drm_device *dev);
1541
1542
1543 /* intel_modes.c */
1544 int intel_connector_update_modes(struct drm_connector *connector,
1545                                  struct edid *edid);
1546 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1547 void intel_attach_force_audio_property(struct drm_connector *connector);
1548 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1549 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1550
1551
1552 /* intel_overlay.c */
1553 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1554 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1555 int intel_overlay_switch_off(struct intel_overlay *overlay);
1556 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1557                                   struct drm_file *file_priv);
1558 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1559                               struct drm_file *file_priv);
1560 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1561
1562
1563 /* intel_panel.c */
1564 int intel_panel_init(struct intel_panel *panel,
1565                      struct drm_display_mode *fixed_mode,
1566                      struct drm_display_mode *downclock_mode);
1567 void intel_panel_fini(struct intel_panel *panel);
1568 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1569                             struct drm_display_mode *adjusted_mode);
1570 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1571                              struct intel_crtc_state *pipe_config,
1572                              int fitting_mode);
1573 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1574                               struct intel_crtc_state *pipe_config,
1575                               int fitting_mode);
1576 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1577                                     u32 level, u32 max);
1578 int intel_panel_setup_backlight(struct drm_connector *connector,
1579                                 enum pipe pipe);
1580 void intel_panel_enable_backlight(struct intel_connector *connector);
1581 void intel_panel_disable_backlight(struct intel_connector *connector);
1582 void intel_panel_destroy_backlight(struct drm_connector *connector);
1583 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1584 extern struct drm_display_mode *intel_find_panel_downclock(
1585                                 struct drm_device *dev,
1586                                 struct drm_display_mode *fixed_mode,
1587                                 struct drm_connector *connector);
1588
1589 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1590 int intel_backlight_device_register(struct intel_connector *connector);
1591 void intel_backlight_device_unregister(struct intel_connector *connector);
1592 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1593 static int intel_backlight_device_register(struct intel_connector *connector)
1594 {
1595         return 0;
1596 }
1597 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1598 {
1599 }
1600 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1601
1602
1603 /* intel_psr.c */
1604 void intel_psr_enable(struct intel_dp *intel_dp);
1605 void intel_psr_disable(struct intel_dp *intel_dp);
1606 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1607                           unsigned frontbuffer_bits);
1608 void intel_psr_flush(struct drm_i915_private *dev_priv,
1609                      unsigned frontbuffer_bits,
1610                      enum fb_op_origin origin);
1611 void intel_psr_init(struct drm_device *dev);
1612 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1613                                    unsigned frontbuffer_bits);
1614
1615 /* intel_runtime_pm.c */
1616 int intel_power_domains_init(struct drm_i915_private *);
1617 void intel_power_domains_fini(struct drm_i915_private *);
1618 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1619 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1620 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1621 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1622 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1623 const char *
1624 intel_display_power_domain_str(enum intel_display_power_domain domain);
1625
1626 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1627                                     enum intel_display_power_domain domain);
1628 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1629                                       enum intel_display_power_domain domain);
1630 void intel_display_power_get(struct drm_i915_private *dev_priv,
1631                              enum intel_display_power_domain domain);
1632 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1633                                         enum intel_display_power_domain domain);
1634 void intel_display_power_put(struct drm_i915_private *dev_priv,
1635                              enum intel_display_power_domain domain);
1636
1637 static inline void
1638 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1639 {
1640         WARN_ONCE(dev_priv->pm.suspended,
1641                   "Device suspended during HW access\n");
1642 }
1643
1644 static inline void
1645 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1646 {
1647         assert_rpm_device_not_suspended(dev_priv);
1648         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1649          * too much noise. */
1650         if (!atomic_read(&dev_priv->pm.wakeref_count))
1651                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1652 }
1653
1654 /**
1655  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1656  * @dev_priv: i915 device instance
1657  *
1658  * This function disable asserts that check if we hold an RPM wakelock
1659  * reference, while keeping the device-not-suspended checks still enabled.
1660  * It's meant to be used only in special circumstances where our rule about
1661  * the wakelock refcount wrt. the device power state doesn't hold. According
1662  * to this rule at any point where we access the HW or want to keep the HW in
1663  * an active state we must hold an RPM wakelock reference acquired via one of
1664  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1665  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1666  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1667  * users should avoid using this function.
1668  *
1669  * Any calls to this function must have a symmetric call to
1670  * enable_rpm_wakeref_asserts().
1671  */
1672 static inline void
1673 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1674 {
1675         atomic_inc(&dev_priv->pm.wakeref_count);
1676 }
1677
1678 /**
1679  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1680  * @dev_priv: i915 device instance
1681  *
1682  * This function re-enables the RPM assert checks after disabling them with
1683  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1684  * circumstances otherwise its use should be avoided.
1685  *
1686  * Any calls to this function must have a symmetric call to
1687  * disable_rpm_wakeref_asserts().
1688  */
1689 static inline void
1690 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1691 {
1692         atomic_dec(&dev_priv->pm.wakeref_count);
1693 }
1694
1695 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1696 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1697 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1698 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1699
1700 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1701
1702 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1703                              bool override, unsigned int mask);
1704 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1705                           enum dpio_channel ch, bool override);
1706
1707
1708 /* intel_pm.c */
1709 void intel_init_clock_gating(struct drm_device *dev);
1710 void intel_suspend_hw(struct drm_device *dev);
1711 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1712 void intel_update_watermarks(struct intel_crtc *crtc);
1713 void intel_init_pm(struct drm_device *dev);
1714 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1715 void intel_pm_setup(struct drm_device *dev);
1716 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1717 void intel_gpu_ips_teardown(void);
1718 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1719 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1720 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1721 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1722 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1723 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1724 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1725 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1726 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1727 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1728 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1729                     struct intel_rps_client *rps,
1730                     unsigned long submitted);
1731 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1732 void vlv_wm_get_hw_state(struct drm_device *dev);
1733 void ilk_wm_get_hw_state(struct drm_device *dev);
1734 void skl_wm_get_hw_state(struct drm_device *dev);
1735 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1736                           struct skl_ddb_allocation *ddb /* out */);
1737 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1738                               struct skl_pipe_wm *out);
1739 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1740 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1741 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1742 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1743                          const struct skl_wm_level *l2);
1744 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
1745                                const struct skl_ddb_allocation *new,
1746                                enum pipe pipe);
1747 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
1748                                  struct intel_crtc *intel_crtc);
1749 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
1750                          const struct skl_plane_wm *wm,
1751                          const struct skl_ddb_allocation *ddb);
1752 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
1753                         const struct skl_plane_wm *wm,
1754                         const struct skl_ddb_allocation *ddb,
1755                         int plane);
1756 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1757 bool ilk_disable_lp_wm(struct drm_device *dev);
1758 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1759 static inline int intel_enable_rc6(void)
1760 {
1761         return i915.enable_rc6;
1762 }
1763
1764 /* intel_sdvo.c */
1765 bool intel_sdvo_init(struct drm_device *dev,
1766                      i915_reg_t reg, enum port port);
1767
1768
1769 /* intel_sprite.c */
1770 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1771                              int usecs);
1772 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1773                                               enum pipe pipe, int plane);
1774 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1775                               struct drm_file *file_priv);
1776 void intel_pipe_update_start(struct intel_crtc *crtc);
1777 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1778
1779 /* intel_tv.c */
1780 void intel_tv_init(struct drm_device *dev);
1781
1782 /* intel_atomic.c */
1783 int intel_connector_atomic_get_property(struct drm_connector *connector,
1784                                         const struct drm_connector_state *state,
1785                                         struct drm_property *property,
1786                                         uint64_t *val);
1787 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1788 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1789                                struct drm_crtc_state *state);
1790 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1791 void intel_atomic_state_clear(struct drm_atomic_state *);
1792 struct intel_shared_dpll_config *
1793 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1794
1795 static inline struct intel_crtc_state *
1796 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1797                             struct intel_crtc *crtc)
1798 {
1799         struct drm_crtc_state *crtc_state;
1800         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1801         if (IS_ERR(crtc_state))
1802                 return ERR_CAST(crtc_state);
1803
1804         return to_intel_crtc_state(crtc_state);
1805 }
1806
1807 static inline struct intel_plane_state *
1808 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1809                                       struct intel_plane *plane)
1810 {
1811         struct drm_plane_state *plane_state;
1812
1813         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1814
1815         return to_intel_plane_state(plane_state);
1816 }
1817
1818 int intel_atomic_setup_scalers(struct drm_device *dev,
1819         struct intel_crtc *intel_crtc,
1820         struct intel_crtc_state *crtc_state);
1821
1822 /* intel_atomic_plane.c */
1823 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1824 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1825 void intel_plane_destroy_state(struct drm_plane *plane,
1826                                struct drm_plane_state *state);
1827 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1828
1829 /* intel_color.c */
1830 void intel_color_init(struct drm_crtc *crtc);
1831 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1832 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1833 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1834
1835 /* intel_lspcon.c */
1836 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1837 void lspcon_resume(struct intel_lspcon *lspcon);
1838 #endif /* __INTEL_DRV_H__ */