drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic_us(COND, US) \
 133 ({ \
 134         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 135         BUILD_BUG_ON((US) > 50000); \
 136         _wait_for_atomic((COND), (US), 1); \
 137 })
 138
 139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 140
 141 #define KHz(x) (1000 * (x))
 142 #define MHz(x) KHz(1000 * (x))
 143
 144 /*
 145  * Display related stuff
 146  */
 147
 148 /* store information about an Ixxx DVO */
 149 /* The i830->i865 use multiple DVOs with multiple i2cs */
 150 /* the i915, i945 have a single sDVO i2c bus - which is different */
 151 #define MAX_OUTPUTS 6
 152 /* maximum connectors per crtcs in the mode set */
 153
 154 /* Maximum cursor sizes */
 155 #define GEN2_CURSOR_WIDTH 64
 156 #define GEN2_CURSOR_HEIGHT 64
 157 #define MAX_CURSOR_WIDTH 256
 158 #define MAX_CURSOR_HEIGHT 256
 159
 160 #define INTEL_I2C_BUS_DVO 1
 161 #define INTEL_I2C_BUS_SDVO 2
 162
 163 /* these are outputs from the chip - integrated only
 164    external chips are via DVO or SDVO output */
 165 enum intel_output_type {
 166         INTEL_OUTPUT_UNUSED = 0,
 167         INTEL_OUTPUT_ANALOG = 1,
 168         INTEL_OUTPUT_DVO = 2,
 169         INTEL_OUTPUT_SDVO = 3,
 170         INTEL_OUTPUT_LVDS = 4,
 171         INTEL_OUTPUT_TVOUT = 5,
 172         INTEL_OUTPUT_HDMI = 6,
 173         INTEL_OUTPUT_DP = 7,
 174         INTEL_OUTPUT_EDP = 8,
 175         INTEL_OUTPUT_DSI = 9,
 176         INTEL_OUTPUT_UNKNOWN = 10,
 177         INTEL_OUTPUT_DP_MST = 11,
 178 };
 179
 180 #define INTEL_DVO_CHIP_NONE 0
 181 #define INTEL_DVO_CHIP_LVDS 1
 182 #define INTEL_DVO_CHIP_TMDS 2
 183 #define INTEL_DVO_CHIP_TVOUT 4
 184
 185 #define INTEL_DSI_VIDEO_MODE    0
 186 #define INTEL_DSI_COMMAND_MODE  1
 187
 188 struct intel_framebuffer {
 189         struct drm_framebuffer base;
 190         struct drm_i915_gem_object *obj;
 191         struct intel_rotation_info rot_info;
 192
 193         /* for each plane in the normal GTT view */
 194         struct {
 195                 unsigned int x, y;
 196         } normal[2];
 197         /* for each plane in the rotated GTT view */
 198         struct {
 199                 unsigned int x, y;
 200                 unsigned int pitch; /* pixels */
 201         } rotated[2];
 202 };
 203
 204 struct intel_fbdev {
 205         struct drm_fb_helper helper;
 206         struct intel_framebuffer *fb;
 207         struct i915_vma *vma;
 208         async_cookie_t cookie;
 209         int preferred_bpp;
 210 };
 211
 212 struct intel_encoder {
 213         struct drm_encoder base;
 214
 215         enum intel_output_type type;
 216         enum port port;
 217         unsigned int cloneable;
 218         void (*hot_plug)(struct intel_encoder *);
 219         bool (*compute_config)(struct intel_encoder *,
 220                                struct intel_crtc_state *,
 221                                struct drm_connector_state *);
 222         void (*pre_pll_enable)(struct intel_encoder *,
 223                                const struct intel_crtc_state *,
 224                                const struct drm_connector_state *);
 225         void (*pre_enable)(struct intel_encoder *,
 226                            const struct intel_crtc_state *,
 227                            const struct drm_connector_state *);
 228         void (*enable)(struct intel_encoder *,
 229                        const struct intel_crtc_state *,
 230                        const struct drm_connector_state *);
 231         void (*disable)(struct intel_encoder *,
 232                         const struct intel_crtc_state *,
 233                         const struct drm_connector_state *);
 234         void (*post_disable)(struct intel_encoder *,
 235                              const struct intel_crtc_state *,
 236                              const struct drm_connector_state *);
 237         void (*post_pll_disable)(struct intel_encoder *,
 238                                  const struct intel_crtc_state *,
 239                                  const struct drm_connector_state *);
 240         /* Read out the current hw state of this connector, returning true if
 241          * the encoder is active. If the encoder is enabled it also set the pipe
 242          * it is connected to in the pipe parameter. */
 243         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 244         /* Reconstructs the equivalent mode flags for the current hardware
 245          * state. This must be called _after_ display->get_pipe_config has
 246          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 247          * be set correctly before calling this function. */
 248         void (*get_config)(struct intel_encoder *,
 249                            struct intel_crtc_state *pipe_config);
 250         /* Returns a mask of power domains that need to be referenced as part
 251          * of the hardware state readout code. */
 252         u64 (*get_power_domains)(struct intel_encoder *encoder);
 253         /*
 254          * Called during system suspend after all pending requests for the
 255          * encoder are flushed (for example for DP AUX transactions) and
 256          * device interrupts are disabled.
 257          */
 258         void (*suspend)(struct intel_encoder *);
 259         int crtc_mask;
 260         enum hpd_pin hpd_pin;
 261         enum intel_display_power_domain power_domain;
 262         /* for communication with audio component; protected by av_mutex */
 263         const struct drm_connector *audio_connector;
 264 };
 265
 266 struct intel_panel {
 267         struct drm_display_mode *fixed_mode;
 268         struct drm_display_mode *downclock_mode;
 269
 270         /* backlight */
 271         struct {
 272                 bool present;
 273                 u32 level;
 274                 u32 min;
 275                 u32 max;
 276                 bool enabled;
 277                 bool combination_mode;  /* gen 2/4 only */
 278                 bool active_low_pwm;
 279                 bool alternate_pwm_increment;   /* lpt+ */
 280
 281                 /* PWM chip */
 282                 bool util_pin_active_low;       /* bxt+ */
 283                 u8 controller;          /* bxt+ only */
 284                 struct pwm_device *pwm;
 285
 286                 struct backlight_device *device;
 287
 288                 /* Connector and platform specific backlight functions */
 289                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 290                 uint32_t (*get)(struct intel_connector *connector);
 291                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 292                 void (*disable)(const struct drm_connector_state *conn_state);
 293                 void (*enable)(const struct intel_crtc_state *crtc_state,
 294                                const struct drm_connector_state *conn_state);
 295                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 296                                       uint32_t hz);
 297                 void (*power)(struct intel_connector *, bool enable);
 298         } backlight;
 299 };
 300
 301 struct intel_connector {
 302         struct drm_connector base;
 303         /*
 304          * The fixed encoder this connector is connected to.
 305          */
 306         struct intel_encoder *encoder;
 307
 308         /* ACPI device id for ACPI and driver cooperation */
 309         u32 acpi_device_id;
 310
 311         /* Reads out the current hw, returning true if the connector is enabled
 312          * and active (i.e. dpms ON state). */
 313         bool (*get_hw_state)(struct intel_connector *);
 314
 315         /* Panel info for eDP and LVDS */
 316         struct intel_panel panel;
 317
 318         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 319         struct edid *edid;
 320         struct edid *detect_edid;
 321
 322         /* since POLL and HPD connectors may use the same HPD line keep the native
 323            state of connector->polled in case hotplug storm detection changes it */
 324         u8 polled;
 325
 326         void *port; /* store this opaque as its illegal to dereference it */
 327
 328         struct intel_dp *mst_port;
 329
 330         /* Work struct to schedule a uevent on link train failure */
 331         struct work_struct modeset_retry_work;
 332 };
 333
 334 struct intel_digital_connector_state {
 335         struct drm_connector_state base;
 336
 337         enum hdmi_force_audio force_audio;
 338         int broadcast_rgb;
 339 };
 340
 341 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 342
 343 struct dpll {
 344         /* given values */
 345         int n;
 346         int m1, m2;
 347         int p1, p2;
 348         /* derived values */
 349         int     dot;
 350         int     vco;
 351         int     m;
 352         int     p;
 353 };
 354
 355 struct intel_atomic_state {
 356         struct drm_atomic_state base;
 357
 358         struct {
 359                 /*
 360                  * Logical state of cdclk (used for all scaling, watermark,
 361                  * etc. calculations and checks). This is computed as if all
 362                  * enabled crtcs were active.
 363                  */
 364                 struct intel_cdclk_state logical;
 365
 366                 /*
 367                  * Actual state of cdclk, can be different from the logical
 368                  * state only when all crtc's are DPMS off.
 369                  */
 370                 struct intel_cdclk_state actual;
 371         } cdclk;
 372
 373         bool dpll_set, modeset;
 374
 375         /*
 376          * Does this transaction change the pipes that are active?  This mask
 377          * tracks which CRTC's have changed their active state at the end of
 378          * the transaction (not counting the temporary disable during modesets).
 379          * This mask should only be non-zero when intel_state->modeset is true,
 380          * but the converse is not necessarily true; simply changing a mode may
 381          * not flip the final active status of any CRTC's
 382          */
 383         unsigned int active_pipe_changes;
 384
 385         unsigned int active_crtcs;
 386         /* minimum acceptable cdclk for each pipe */
 387         int min_cdclk[I915_MAX_PIPES];
 388
 389         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 390
 391         /*
 392          * Current watermarks can't be trusted during hardware readout, so
 393          * don't bother calculating intermediate watermarks.
 394          */
 395         bool skip_intermediate_wm;
 396
 397         /* Gen9+ only */
 398         struct skl_wm_values wm_results;
 399
 400         struct i915_sw_fence commit_ready;
 401
 402         struct llist_node freed;
 403 };
 404
 405 struct intel_plane_state {
 406         struct drm_plane_state base;
 407         struct drm_rect clip;
 408         struct i915_vma *vma;
 409
 410         struct {
 411                 u32 offset;
 412                 int x, y;
 413         } main;
 414         struct {
 415                 u32 offset;
 416                 int x, y;
 417         } aux;
 418
 419         /* plane control register */
 420         u32 ctl;
 421
 422         /*
 423          * scaler_id
 424          *    = -1 : not using a scaler
 425          *    >=  0 : using a scalers
 426          *
 427          * plane requiring a scaler:
 428          *   - During check_plane, its bit is set in
 429          *     crtc_state->scaler_state.scaler_users by calling helper function
 430          *     update_scaler_plane.
 431          *   - scaler_id indicates the scaler it got assigned.
 432          *
 433          * plane doesn't require a scaler:
 434          *   - this can happen when scaling is no more required or plane simply
 435          *     got disabled.
 436          *   - During check_plane, corresponding bit is reset in
 437          *     crtc_state->scaler_state.scaler_users by calling helper function
 438          *     update_scaler_plane.
 439          */
 440         int scaler_id;
 441
 442         struct drm_intel_sprite_colorkey ckey;
 443 };
 444
 445 struct intel_initial_plane_config {
 446         struct intel_framebuffer *fb;
 447         unsigned int tiling;
 448         int size;
 449         u32 base;
 450 };
 451
 452 #define SKL_MIN_SRC_W 8
 453 #define SKL_MAX_SRC_W 4096
 454 #define SKL_MIN_SRC_H 8
 455 #define SKL_MAX_SRC_H 4096
 456 #define SKL_MIN_DST_W 8
 457 #define SKL_MAX_DST_W 4096
 458 #define SKL_MIN_DST_H 8
 459 #define SKL_MAX_DST_H 4096
 460
 461 struct intel_scaler {
 462         int in_use;
 463         uint32_t mode;
 464 };
 465
 466 struct intel_crtc_scaler_state {
 467 #define SKL_NUM_SCALERS 2
 468         struct intel_scaler scalers[SKL_NUM_SCALERS];
 469
 470         /*
 471          * scaler_users: keeps track of users requesting scalers on this crtc.
 472          *
 473          *     If a bit is set, a user is using a scaler.
 474          *     Here user can be a plane or crtc as defined below:
 475          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 476          *       bit 31    - crtc
 477          *
 478          * Instead of creating a new index to cover planes and crtc, using
 479          * existing drm_plane_index for planes which is well less than 31
 480          * planes and bit 31 for crtc. This should be fine to cover all
 481          * our platforms.
 482          *
 483          * intel_atomic_setup_scalers will setup available scalers to users
 484          * requesting scalers. It will gracefully fail if request exceeds
 485          * avilability.
 486          */
 487 #define SKL_CRTC_INDEX 31
 488         unsigned scaler_users;
 489
 490         /* scaler used by crtc for panel fitting purpose */
 491         int scaler_id;
 492 };
 493
 494 /* drm_mode->private_flags */
 495 #define I915_MODE_FLAG_INHERITED 1
 496 /* Flag to get scanline using frame time stamps */
 497 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 498
 499 struct intel_pipe_wm {
 500         struct intel_wm_level wm[5];
 501         uint32_t linetime;
 502         bool fbc_wm_enabled;
 503         bool pipe_enabled;
 504         bool sprites_enabled;
 505         bool sprites_scaled;
 506 };
 507
 508 struct skl_plane_wm {
 509         struct skl_wm_level wm[8];
 510         struct skl_wm_level trans_wm;
 511 };
 512
 513 struct skl_pipe_wm {
 514         struct skl_plane_wm planes[I915_MAX_PLANES];
 515         uint32_t linetime;
 516 };
 517
 518 enum vlv_wm_level {
 519         VLV_WM_LEVEL_PM2,
 520         VLV_WM_LEVEL_PM5,
 521         VLV_WM_LEVEL_DDR_DVFS,
 522         NUM_VLV_WM_LEVELS,
 523 };
 524
 525 struct vlv_wm_state {
 526         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 527         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 528         uint8_t num_levels;
 529         bool cxsr;
 530 };
 531
 532 struct vlv_fifo_state {
 533         u16 plane[I915_MAX_PLANES];
 534 };
 535
 536 enum g4x_wm_level {
 537         G4X_WM_LEVEL_NORMAL,
 538         G4X_WM_LEVEL_SR,
 539         G4X_WM_LEVEL_HPLL,
 540         NUM_G4X_WM_LEVELS,
 541 };
 542
 543 struct g4x_wm_state {
 544         struct g4x_pipe_wm wm;
 545         struct g4x_sr_wm sr;
 546         struct g4x_sr_wm hpll;
 547         bool cxsr;
 548         bool hpll_en;
 549         bool fbc_en;
 550 };
 551
 552 struct intel_crtc_wm_state {
 553         union {
 554                 struct {
 555                         /*
 556                          * Intermediate watermarks; these can be
 557                          * programmed immediately since they satisfy
 558                          * both the current configuration we're
 559                          * switching away from and the new
 560                          * configuration we're switching to.
 561                          */
 562                         struct intel_pipe_wm intermediate;
 563
 564                         /*
 565                          * Optimal watermarks, programmed post-vblank
 566                          * when this state is committed.
 567                          */
 568                         struct intel_pipe_wm optimal;
 569                 } ilk;
 570
 571                 struct {
 572                         /* gen9+ only needs 1-step wm programming */
 573                         struct skl_pipe_wm optimal;
 574                         struct skl_ddb_entry ddb;
 575                 } skl;
 576
 577                 struct {
 578                         /* "raw" watermarks (not inverted) */
 579                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 580                         /* intermediate watermarks (inverted) */
 581                         struct vlv_wm_state intermediate;
 582                         /* optimal watermarks (inverted) */
 583                         struct vlv_wm_state optimal;
 584                         /* display FIFO split */
 585                         struct vlv_fifo_state fifo_state;
 586                 } vlv;
 587
 588                 struct {
 589                         /* "raw" watermarks */
 590                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 591                         /* intermediate watermarks */
 592                         struct g4x_wm_state intermediate;
 593                         /* optimal watermarks */
 594                         struct g4x_wm_state optimal;
 595                 } g4x;
 596         };
 597
 598         /*
 599          * Platforms with two-step watermark programming will need to
 600          * update watermark programming post-vblank to switch from the
 601          * safe intermediate watermarks to the optimal final
 602          * watermarks.
 603          */
 604         bool need_postvbl_update;
 605 };
 606
 607 struct intel_crtc_state {
 608         struct drm_crtc_state base;
 609
 610         /**
 611          * quirks - bitfield with hw state readout quirks
 612          *
 613          * For various reasons the hw state readout code might not be able to
 614          * completely faithfully read out the current state. These cases are
 615          * tracked with quirk flags so that fastboot and state checker can act
 616          * accordingly.
 617          */
 618 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 619         unsigned long quirks;
 620
 621         unsigned fb_bits; /* framebuffers to flip */
 622         bool update_pipe; /* can a fast modeset be performed? */
 623         bool disable_cxsr;
 624         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 625         bool fb_changed; /* fb on any of the planes is changed */
 626         bool fifo_changed; /* FIFO split is changed */
 627
 628         /* Pipe source size (ie. panel fitter input size)
 629          * All planes will be positioned inside this space,
 630          * and get clipped at the edges. */
 631         int pipe_src_w, pipe_src_h;
 632
 633         /*
 634          * Pipe pixel rate, adjusted for
 635          * panel fitter/pipe scaler downscaling.
 636          */
 637         unsigned int pixel_rate;
 638
 639         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 640          * between pch encoders and cpu encoders. */
 641         bool has_pch_encoder;
 642
 643         /* Are we sending infoframes on the attached port */
 644         bool has_infoframe;
 645
 646         /* CPU Transcoder for the pipe. Currently this can only differ from the
 647          * pipe on Haswell and later (where we have a special eDP transcoder)
 648          * and Broxton (where we have special DSI transcoders). */
 649         enum transcoder cpu_transcoder;
 650
 651         /*
 652          * Use reduced/limited/broadcast rbg range, compressing from the full
 653          * range fed into the crtcs.
 654          */
 655         bool limited_color_range;
 656
 657         /* Bitmask of encoder types (enum intel_output_type)
 658          * driven by the pipe.
 659          */
 660         unsigned int output_types;
 661
 662         /* Whether we should send NULL infoframes. Required for audio. */
 663         bool has_hdmi_sink;
 664
 665         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 666          * has_dp_encoder is set. */
 667         bool has_audio;
 668
 669         /*
 670          * Enable dithering, used when the selected pipe bpp doesn't match the
 671          * plane bpp.
 672          */
 673         bool dither;
 674
 675         /*
 676          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 677          * compliance video pattern tests.
 678          * Disable dither only if it is a compliance test request for
 679          * 18bpp.
 680          */
 681         bool dither_force_disable;
 682
 683         /* Controls for the clock computation, to override various stages. */
 684         bool clock_set;
 685
 686         /* SDVO TV has a bunch of special case. To make multifunction encoders
 687          * work correctly, we need to track this at runtime.*/
 688         bool sdvo_tv_clock;
 689
 690         /*
 691          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 692          * required. This is set in the 2nd loop of calling encoder's
 693          * ->compute_config if the first pick doesn't work out.
 694          */
 695         bool bw_constrained;
 696
 697         /* Settings for the intel dpll used on pretty much everything but
 698          * haswell. */
 699         struct dpll dpll;
 700
 701         /* Selected dpll when shared or NULL. */
 702         struct intel_shared_dpll *shared_dpll;
 703
 704         /* Actual register state of the dpll, for shared dpll cross-checking. */
 705         struct intel_dpll_hw_state dpll_hw_state;
 706
 707         /* DSI PLL registers */
 708         struct {
 709                 u32 ctrl, div;
 710         } dsi_pll;
 711
 712         int pipe_bpp;
 713         struct intel_link_m_n dp_m_n;
 714
 715         /* m2_n2 for eDP downclock */
 716         struct intel_link_m_n dp_m2_n2;
 717         bool has_drrs;
 718
 719         bool has_psr;
 720         bool has_psr2;
 721
 722         /*
 723          * Frequence the dpll for the port should run at. Differs from the
 724          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 725          * already multiplied by pixel_multiplier.
 726          */
 727         int port_clock;
 728
 729         /* Used by SDVO (and if we ever fix it, HDMI). */
 730         unsigned pixel_multiplier;
 731
 732         uint8_t lane_count;
 733
 734         /*
 735          * Used by platforms having DP/HDMI PHY with programmable lane
 736          * latency optimization.
 737          */
 738         uint8_t lane_lat_optim_mask;
 739
 740         /* Panel fitter controls for gen2-gen4 + VLV */
 741         struct {
 742                 u32 control;
 743                 u32 pgm_ratios;
 744                 u32 lvds_border_bits;
 745         } gmch_pfit;
 746
 747         /* Panel fitter placement and size for Ironlake+ */
 748         struct {
 749                 u32 pos;
 750                 u32 size;
 751                 bool enabled;
 752                 bool force_thru;
 753         } pch_pfit;
 754
 755         /* FDI configuration, only valid if has_pch_encoder is set. */
 756         int fdi_lanes;
 757         struct intel_link_m_n fdi_m_n;
 758
 759         bool ips_enabled;
 760         bool ips_force_disable;
 761
 762         bool enable_fbc;
 763
 764         bool double_wide;
 765
 766         int pbn;
 767
 768         struct intel_crtc_scaler_state scaler_state;
 769
 770         /* w/a for waiting 2 vblanks during crtc enable */
 771         enum pipe hsw_workaround_pipe;
 772
 773         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 774         bool disable_lp_wm;
 775
 776         struct intel_crtc_wm_state wm;
 777
 778         /* Gamma mode programmed on the pipe */
 779         uint32_t gamma_mode;
 780
 781         /* bitmask of visible planes (enum plane_id) */
 782         u8 active_planes;
 783
 784         /* HDMI scrambling status */
 785         bool hdmi_scrambling;
 786
 787         /* HDMI High TMDS char rate ratio */
 788         bool hdmi_high_tmds_clock_ratio;
 789
 790         /* output format is YCBCR 4:2:0 */
 791         bool ycbcr420;
 792 };
 793
 794 struct intel_crtc {
 795         struct drm_crtc base;
 796         enum pipe pipe;
 797         enum plane plane;
 798         /*
 799          * Whether the crtc and the connected output pipeline is active. Implies
 800          * that crtc->enabled is set, i.e. the current mode configuration has
 801          * some outputs connected to this crtc.
 802          */
 803         bool active;
 804         u8 plane_ids_mask;
 805         unsigned long long enabled_power_domains;
 806         struct intel_overlay *overlay;
 807
 808         struct intel_crtc_state *config;
 809
 810         /* global reset count when the last flip was submitted */
 811         unsigned int reset_count;
 812
 813         /* Access to these should be protected by dev_priv->irq_lock. */
 814         bool cpu_fifo_underrun_disabled;
 815         bool pch_fifo_underrun_disabled;
 816
 817         /* per-pipe watermark state */
 818         struct {
 819                 /* watermarks currently being used  */
 820                 union {
 821                         struct intel_pipe_wm ilk;
 822                         struct vlv_wm_state vlv;
 823                         struct g4x_wm_state g4x;
 824                 } active;
 825         } wm;
 826
 827         int scanline_offset;
 828
 829         struct {
 830                 unsigned start_vbl_count;
 831                 ktime_t start_vbl_time;
 832                 int min_vbl, max_vbl;
 833                 int scanline_start;
 834         } debug;
 835
 836         /* scalers available on this crtc */
 837         int num_scalers;
 838 };
 839
 840 struct intel_plane {
 841         struct drm_plane base;
 842         u8 plane;
 843         enum plane_id id;
 844         enum pipe pipe;
 845         bool can_scale;
 846         int max_downscale;
 847         uint32_t frontbuffer_bit;
 848
 849         struct {
 850                 u32 base, cntl, size;
 851         } cursor;
 852
 853         /*
 854          * NOTE: Do not place new plane state fields here (e.g., when adding
 855          * new plane properties).  New runtime state should now be placed in
 856          * the intel_plane_state structure and accessed via plane_state.
 857          */
 858
 859         void (*update_plane)(struct intel_plane *plane,
 860                              const struct intel_crtc_state *crtc_state,
 861                              const struct intel_plane_state *plane_state);
 862         void (*disable_plane)(struct intel_plane *plane,
 863                               struct intel_crtc *crtc);
 864         bool (*get_hw_state)(struct intel_plane *plane);
 865         int (*check_plane)(struct intel_plane *plane,
 866                            struct intel_crtc_state *crtc_state,
 867                            struct intel_plane_state *state);
 868 };
 869
 870 struct intel_watermark_params {
 871         u16 fifo_size;
 872         u16 max_wm;
 873         u8 default_wm;
 874         u8 guard_size;
 875         u8 cacheline_size;
 876 };
 877
 878 struct cxsr_latency {
 879         bool is_desktop : 1;
 880         bool is_ddr3 : 1;
 881         u16 fsb_freq;
 882         u16 mem_freq;
 883         u16 display_sr;
 884         u16 display_hpll_disable;
 885         u16 cursor_sr;
 886         u16 cursor_hpll_disable;
 887 };
 888
 889 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 890 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 891 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 892 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 893 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 894 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 895 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 896 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 897 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 898
 899 struct intel_hdmi {
 900         i915_reg_t hdmi_reg;
 901         int ddc_bus;
 902         struct {
 903                 enum drm_dp_dual_mode_type type;
 904                 int max_tmds_clock;
 905         } dp_dual_mode;
 906         bool has_hdmi_sink;
 907         bool has_audio;
 908         bool rgb_quant_range_selectable;
 909         struct intel_connector *attached_connector;
 910 };
 911
 912 struct intel_dp_mst_encoder;
 913 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 914
 915 /*
 916  * enum link_m_n_set:
 917  *      When platform provides two set of M_N registers for dp, we can
 918  *      program them and switch between them incase of DRRS.
 919  *      But When only one such register is provided, we have to program the
 920  *      required divider value on that registers itself based on the DRRS state.
 921  *
 922  * M1_N1        : Program dp_m_n on M1_N1 registers
 923  *                        dp_m2_n2 on M2_N2 registers (If supported)
 924  *
 925  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 926  *                        M2_N2 registers are not supported
 927  */
 928
 929 enum link_m_n_set {
 930         /* Sets the m1_n1 and m2_n2 */
 931         M1_N1 = 0,
 932         M2_N2
 933 };
 934
 935 struct intel_dp_compliance_data {
 936         unsigned long edid;
 937         uint8_t video_pattern;
 938         uint16_t hdisplay, vdisplay;
 939         uint8_t bpc;
 940 };
 941
 942 struct intel_dp_compliance {
 943         unsigned long test_type;
 944         struct intel_dp_compliance_data test_data;
 945         bool test_active;
 946         int test_link_rate;
 947         u8 test_lane_count;
 948 };
 949
 950 struct intel_dp {
 951         i915_reg_t output_reg;
 952         i915_reg_t aux_ch_ctl_reg;
 953         i915_reg_t aux_ch_data_reg[5];
 954         uint32_t DP;
 955         int link_rate;
 956         uint8_t lane_count;
 957         uint8_t sink_count;
 958         bool link_mst;
 959         bool has_audio;
 960         bool detect_done;
 961         bool channel_eq_status;
 962         bool reset_link_params;
 963         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 964         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 965         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 966         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 967         /* source rates */
 968         int num_source_rates;
 969         const int *source_rates;
 970         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 971         int num_sink_rates;
 972         int sink_rates[DP_MAX_SUPPORTED_RATES];
 973         bool use_rate_select;
 974         /* intersection of source and sink rates */
 975         int num_common_rates;
 976         int common_rates[DP_MAX_SUPPORTED_RATES];
 977         /* Max lane count for the current link */
 978         int max_link_lane_count;
 979         /* Max rate for the current link */
 980         int max_link_rate;
 981         /* sink or branch descriptor */
 982         struct drm_dp_desc desc;
 983         struct drm_dp_aux aux;
 984         enum intel_display_power_domain aux_power_domain;
 985         uint8_t train_set[4];
 986         int panel_power_up_delay;
 987         int panel_power_down_delay;
 988         int panel_power_cycle_delay;
 989         int backlight_on_delay;
 990         int backlight_off_delay;
 991         struct delayed_work panel_vdd_work;
 992         bool want_panel_vdd;
 993         unsigned long last_power_on;
 994         unsigned long last_backlight_off;
 995         ktime_t panel_power_off_time;
 996
 997         struct notifier_block edp_notifier;
 998
 999         /*
1000          * Pipe whose power sequencer is currently locked into
1001          * this port. Only relevant on VLV/CHV.
1002          */
1003         enum pipe pps_pipe;
1004         /*
1005          * Pipe currently driving the port. Used for preventing
1006          * the use of the PPS for any pipe currentrly driving
1007          * external DP as that will mess things up on VLV.
1008          */
1009         enum pipe active_pipe;
1010         /*
1011          * Set if the sequencer may be reset due to a power transition,
1012          * requiring a reinitialization. Only relevant on BXT.
1013          */
1014         bool pps_reset;
1015         struct edp_power_seq pps_delays;
1016
1017         bool can_mst; /* this port supports mst */
1018         bool is_mst;
1019         int active_mst_links;
1020         /* connector directly attached - won't be use for modeset in mst world */
1021         struct intel_connector *attached_connector;
1022
1023         /* mst connector list */
1024         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1025         struct drm_dp_mst_topology_mgr mst_mgr;
1026
1027         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1028         /*
1029          * This function returns the value we have to program the AUX_CTL
1030          * register with to kick off an AUX transaction.
1031          */
1032         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1033                                      bool has_aux_irq,
1034                                      int send_bytes,
1035                                      uint32_t aux_clock_divider);
1036
1037         /* This is called before a link training is starterd */
1038         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1039
1040         /* Displayport compliance testing */
1041         struct intel_dp_compliance compliance;
1042 };
1043
1044 struct intel_lspcon {
1045         bool active;
1046         enum drm_lspcon_mode mode;
1047 };
1048
1049 struct intel_digital_port {
1050         struct intel_encoder base;
1051         enum port port;
1052         u32 saved_port_bits;
1053         struct intel_dp dp;
1054         struct intel_hdmi hdmi;
1055         struct intel_lspcon lspcon;
1056         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1057         bool release_cl2_override;
1058         uint8_t max_lanes;
1059         enum intel_display_power_domain ddi_io_power_domain;
1060
1061         void (*write_infoframe)(struct drm_encoder *encoder,
1062                                 const struct intel_crtc_state *crtc_state,
1063                                 unsigned int type,
1064                                 const void *frame, ssize_t len);
1065         void (*set_infoframes)(struct drm_encoder *encoder,
1066                                bool enable,
1067                                const struct intel_crtc_state *crtc_state,
1068                                const struct drm_connector_state *conn_state);
1069         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1070                                   const struct intel_crtc_state *pipe_config);
1071 };
1072
1073 struct intel_dp_mst_encoder {
1074         struct intel_encoder base;
1075         enum pipe pipe;
1076         struct intel_digital_port *primary;
1077         struct intel_connector *connector;
1078 };
1079
1080 static inline enum dpio_channel
1081 vlv_dport_to_channel(struct intel_digital_port *dport)
1082 {
1083         switch (dport->port) {
1084         case PORT_B:
1085         case PORT_D:
1086                 return DPIO_CH0;
1087         case PORT_C:
1088                 return DPIO_CH1;
1089         default:
1090                 BUG();
1091         }
1092 }
1093
1094 static inline enum dpio_phy
1095 vlv_dport_to_phy(struct intel_digital_port *dport)
1096 {
1097         switch (dport->port) {
1098         case PORT_B:
1099         case PORT_C:
1100                 return DPIO_PHY0;
1101         case PORT_D:
1102                 return DPIO_PHY1;
1103         default:
1104                 BUG();
1105         }
1106 }
1107
1108 static inline enum dpio_channel
1109 vlv_pipe_to_channel(enum pipe pipe)
1110 {
1111         switch (pipe) {
1112         case PIPE_A:
1113         case PIPE_C:
1114                 return DPIO_CH0;
1115         case PIPE_B:
1116                 return DPIO_CH1;
1117         default:
1118                 BUG();
1119         }
1120 }
1121
1122 static inline struct intel_crtc *
1123 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1124 {
1125         return dev_priv->pipe_to_crtc_mapping[pipe];
1126 }
1127
1128 static inline struct intel_crtc *
1129 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1130 {
1131         return dev_priv->plane_to_crtc_mapping[plane];
1132 }
1133
1134 struct intel_load_detect_pipe {
1135         struct drm_atomic_state *restore_state;
1136 };
1137
1138 static inline struct intel_encoder *
1139 intel_attached_encoder(struct drm_connector *connector)
1140 {
1141         return to_intel_connector(connector)->encoder;
1142 }
1143
1144 static inline struct intel_digital_port *
1145 enc_to_dig_port(struct drm_encoder *encoder)
1146 {
1147         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1148
1149         switch (intel_encoder->type) {
1150         case INTEL_OUTPUT_UNKNOWN:
1151                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1152         case INTEL_OUTPUT_DP:
1153         case INTEL_OUTPUT_EDP:
1154         case INTEL_OUTPUT_HDMI:
1155                 return container_of(encoder, struct intel_digital_port,
1156                                     base.base);
1157         default:
1158                 return NULL;
1159         }
1160 }
1161
1162 static inline struct intel_dp_mst_encoder *
1163 enc_to_mst(struct drm_encoder *encoder)
1164 {
1165         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1166 }
1167
1168 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1169 {
1170         return &enc_to_dig_port(encoder)->dp;
1171 }
1172
1173 static inline struct intel_digital_port *
1174 dp_to_dig_port(struct intel_dp *intel_dp)
1175 {
1176         return container_of(intel_dp, struct intel_digital_port, dp);
1177 }
1178
1179 static inline struct intel_lspcon *
1180 dp_to_lspcon(struct intel_dp *intel_dp)
1181 {
1182         return &dp_to_dig_port(intel_dp)->lspcon;
1183 }
1184
1185 static inline struct intel_digital_port *
1186 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1187 {
1188         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1189 }
1190
1191 static inline struct intel_plane_state *
1192 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1193                                  struct intel_plane *plane)
1194 {
1195         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1196                                                                    &plane->base));
1197 }
1198
1199 static inline struct intel_crtc_state *
1200 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1201                                 struct intel_crtc *crtc)
1202 {
1203         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1204                                                                  &crtc->base));
1205 }
1206
1207 static inline struct intel_crtc_state *
1208 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1209                                 struct intel_crtc *crtc)
1210 {
1211         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1212                                                                  &crtc->base));
1213 }
1214
1215 /* intel_fifo_underrun.c */
1216 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1217                                            enum pipe pipe, bool enable);
1218 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1219                                            enum pipe pch_transcoder,
1220                                            bool enable);
1221 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1222                                          enum pipe pipe);
1223 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1224                                          enum pipe pch_transcoder);
1225 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1226 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1227
1228 /* i915_irq.c */
1229 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1230 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1231 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1232 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1233 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1234 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1235 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1236
1237 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1238                                             u32 mask)
1239 {
1240         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1241 }
1242
1243 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1244 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1245 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1246 {
1247         /*
1248          * We only use drm_irq_uninstall() at unload and VT switch, so
1249          * this is the only thing we need to check.
1250          */
1251         return dev_priv->runtime_pm.irqs_enabled;
1252 }
1253
1254 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1255 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1256                                      u8 pipe_mask);
1257 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1258                                      u8 pipe_mask);
1259 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1260 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1261 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1262
1263 /* intel_crt.c */
1264 void intel_crt_init(struct drm_i915_private *dev_priv);
1265 void intel_crt_reset(struct drm_encoder *encoder);
1266
1267 /* intel_ddi.c */
1268 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1269                                 const struct intel_crtc_state *old_crtc_state,
1270                                 const struct drm_connector_state *old_conn_state);
1271 void hsw_fdi_link_train(struct intel_crtc *crtc,
1272                         const struct intel_crtc_state *crtc_state);
1273 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1274 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1275 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1276 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1277 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1278                                        enum transcoder cpu_transcoder);
1279 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1280 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1281 struct intel_encoder *
1282 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1283 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1284 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1285 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1286 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1287                                  struct intel_crtc *intel_crtc);
1288 void intel_ddi_get_config(struct intel_encoder *encoder,
1289                           struct intel_crtc_state *pipe_config);
1290
1291 void intel_ddi_clock_get(struct intel_encoder *encoder,
1292                          struct intel_crtc_state *pipe_config);
1293 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1294                                     bool state);
1295 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1296 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1297 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1298
1299 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1300                                    int plane, unsigned int height);
1301
1302 /* intel_audio.c */
1303 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1304 void intel_audio_codec_enable(struct intel_encoder *encoder,
1305                               const struct intel_crtc_state *crtc_state,
1306                               const struct drm_connector_state *conn_state);
1307 void intel_audio_codec_disable(struct intel_encoder *encoder);
1308 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1309 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1310 void intel_audio_init(struct drm_i915_private *dev_priv);
1311 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1312
1313 /* intel_cdclk.c */
1314 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1315 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1316 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1317 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1318 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1319 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1320 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1321 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1322 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1323 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1324 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1325 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1326                                const struct intel_cdclk_state *b);
1327 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1328                      const struct intel_cdclk_state *cdclk_state);
1329
1330 /* intel_display.c */
1331 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1332 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1333 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1334 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1335 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1336 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1337                       const char *name, u32 reg, int ref_freq);
1338 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1339                            const char *name, u32 reg);
1340 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1341 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1342 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1343 unsigned int intel_fb_xy_to_linear(int x, int y,
1344                                    const struct intel_plane_state *state,
1345                                    int plane);
1346 void intel_add_fb_offsets(int *x, int *y,
1347                           const struct intel_plane_state *state, int plane);
1348 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1349 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1350 void intel_mark_busy(struct drm_i915_private *dev_priv);
1351 void intel_mark_idle(struct drm_i915_private *dev_priv);
1352 int intel_display_suspend(struct drm_device *dev);
1353 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1354 void intel_encoder_destroy(struct drm_encoder *encoder);
1355 int intel_connector_init(struct intel_connector *);
1356 struct intel_connector *intel_connector_alloc(void);
1357 void intel_connector_free(struct intel_connector *connector);
1358 bool intel_connector_get_hw_state(struct intel_connector *connector);
1359 void intel_connector_attach_encoder(struct intel_connector *connector,
1360                                     struct intel_encoder *encoder);
1361 struct drm_display_mode *
1362 intel_encoder_current_mode(struct intel_encoder *encoder);
1363
1364 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1365 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1366                                 struct drm_file *file_priv);
1367 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1368                                              enum pipe pipe);
1369 static inline bool
1370 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1371                     enum intel_output_type type)
1372 {
1373         return crtc_state->output_types & (1 << type);
1374 }
1375 static inline bool
1376 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1377 {
1378         return crtc_state->output_types &
1379                 ((1 << INTEL_OUTPUT_DP) |
1380                  (1 << INTEL_OUTPUT_DP_MST) |
1381                  (1 << INTEL_OUTPUT_EDP));
1382 }
1383 static inline void
1384 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1385 {
1386         drm_wait_one_vblank(&dev_priv->drm, pipe);
1387 }
1388 static inline void
1389 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1390 {
1391         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1392
1393         if (crtc->active)
1394                 intel_wait_for_vblank(dev_priv, pipe);
1395 }
1396
1397 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1398
1399 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1400 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1401                          struct intel_digital_port *dport,
1402                          unsigned int expected_mask);
1403 int intel_get_load_detect_pipe(struct drm_connector *connector,
1404                                const struct drm_display_mode *mode,
1405                                struct intel_load_detect_pipe *old,
1406                                struct drm_modeset_acquire_ctx *ctx);
1407 void intel_release_load_detect_pipe(struct drm_connector *connector,
1408                                     struct intel_load_detect_pipe *old,
1409                                     struct drm_modeset_acquire_ctx *ctx);
1410 struct i915_vma *
1411 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1412 void intel_unpin_fb_vma(struct i915_vma *vma);
1413 struct drm_framebuffer *
1414 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1415                          struct drm_mode_fb_cmd2 *mode_cmd);
1416 int intel_prepare_plane_fb(struct drm_plane *plane,
1417                            struct drm_plane_state *new_state);
1418 void intel_cleanup_plane_fb(struct drm_plane *plane,
1419                             struct drm_plane_state *old_state);
1420 int intel_plane_atomic_get_property(struct drm_plane *plane,
1421                                     const struct drm_plane_state *state,
1422                                     struct drm_property *property,
1423                                     uint64_t *val);
1424 int intel_plane_atomic_set_property(struct drm_plane *plane,
1425                                     struct drm_plane_state *state,
1426                                     struct drm_property *property,
1427                                     uint64_t val);
1428 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1429                                     struct drm_crtc_state *crtc_state,
1430                                     const struct intel_plane_state *old_plane_state,
1431                                     struct drm_plane_state *plane_state);
1432
1433 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1434                                     enum pipe pipe);
1435
1436 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1437                      const struct dpll *dpll);
1438 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1439 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1440
1441 /* modesetting asserts */
1442 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1443                            enum pipe pipe);
1444 void assert_pll(struct drm_i915_private *dev_priv,
1445                 enum pipe pipe, bool state);
1446 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1447 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1448 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1449 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1450 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1451 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1452                        enum pipe pipe, bool state);
1453 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1454 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1455 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1456 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1457 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1458 u32 intel_compute_tile_offset(int *x, int *y,
1459                               const struct intel_plane_state *state, int plane);
1460 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1461 void intel_finish_reset(struct drm_i915_private *dev_priv);
1462 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1463 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1464 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1465 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1466 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1467 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1468 unsigned int skl_cdclk_get_vco(unsigned int freq);
1469 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1470 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1471 void intel_dp_get_m_n(struct intel_crtc *crtc,
1472                       struct intel_crtc_state *pipe_config);
1473 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1474 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1475 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1476                         struct dpll *best_clock);
1477 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1478
1479 bool intel_crtc_active(struct intel_crtc *crtc);
1480 void hsw_enable_ips(struct intel_crtc *crtc);
1481 void hsw_disable_ips(struct intel_crtc *crtc);
1482 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1483 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1484                                  struct intel_crtc_state *pipe_config);
1485
1486 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1487 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1488
1489 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1490 {
1491         return i915_ggtt_offset(state->vma);
1492 }
1493
1494 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1495                   const struct intel_plane_state *plane_state);
1496 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1497                      unsigned int rotation);
1498 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1499 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1500
1501 /* intel_csr.c */
1502 void intel_csr_ucode_init(struct drm_i915_private *);
1503 void intel_csr_load_program(struct drm_i915_private *);
1504 void intel_csr_ucode_fini(struct drm_i915_private *);
1505 void intel_csr_ucode_suspend(struct drm_i915_private *);
1506 void intel_csr_ucode_resume(struct drm_i915_private *);
1507
1508 /* intel_dp.c */
1509 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1510                    enum port port);
1511 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1512                              struct intel_connector *intel_connector);
1513 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1514                               int link_rate, uint8_t lane_count,
1515                               bool link_mst);
1516 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1517                                             int link_rate, uint8_t lane_count);
1518 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1519 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1520 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1521 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1522 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1523 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1524 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1525 bool intel_dp_compute_config(struct intel_encoder *encoder,
1526                              struct intel_crtc_state *pipe_config,
1527                              struct drm_connector_state *conn_state);
1528 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1529 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1530 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1531                                   bool long_hpd);
1532 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1533                             const struct drm_connector_state *conn_state);
1534 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1535 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1536 void intel_edp_panel_on(struct intel_dp *intel_dp);
1537 void intel_edp_panel_off(struct intel_dp *intel_dp);
1538 void intel_dp_mst_suspend(struct drm_device *dev);
1539 void intel_dp_mst_resume(struct drm_device *dev);
1540 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1541 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1542 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1543 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1544 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1545 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1546 void intel_plane_destroy(struct drm_plane *plane);
1547 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1548                            const struct intel_crtc_state *crtc_state);
1549 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1550                             const struct intel_crtc_state *crtc_state);
1551 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1552                                unsigned int frontbuffer_bits);
1553 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1554                           unsigned int frontbuffer_bits);
1555
1556 void
1557 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1558                                        uint8_t dp_train_pat);
1559 void
1560 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1561 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1562 uint8_t
1563 intel_dp_voltage_max(struct intel_dp *intel_dp);
1564 uint8_t
1565 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1566 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1567                            uint8_t *link_bw, uint8_t *rate_select);
1568 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1569 bool
1570 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1571
1572 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1573 {
1574         return ~((1 << lane_count) - 1) & 0xf;
1575 }
1576
1577 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1578 int intel_dp_link_required(int pixel_clock, int bpp);
1579 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1580 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1581                                   struct intel_digital_port *port);
1582
1583 /* intel_dp_aux_backlight.c */
1584 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1585
1586 /* intel_dp_mst.c */
1587 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1588 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1589 /* intel_dsi.c */
1590 void intel_dsi_init(struct drm_i915_private *dev_priv);
1591
1592 /* intel_dsi_dcs_backlight.c */
1593 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1594
1595 /* intel_dvo.c */
1596 void intel_dvo_init(struct drm_i915_private *dev_priv);
1597 /* intel_hotplug.c */
1598 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1599
1600
1601 /* legacy fbdev emulation in intel_fbdev.c */
1602 #ifdef CONFIG_DRM_FBDEV_EMULATION
1603 extern int intel_fbdev_init(struct drm_device *dev);
1604 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1605 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1606 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1607 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1608 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1609 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1610 #else
1611 static inline int intel_fbdev_init(struct drm_device *dev)
1612 {
1613         return 0;
1614 }
1615
1616 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1617 {
1618 }
1619
1620 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1621 {
1622 }
1623
1624 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1625 {
1626 }
1627
1628 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1629 {
1630 }
1631
1632 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1633 {
1634 }
1635
1636 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1637 {
1638 }
1639 #endif
1640
1641 /* intel_fbc.c */
1642 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1643                            struct drm_atomic_state *state);
1644 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1645 void intel_fbc_pre_update(struct intel_crtc *crtc,
1646                           struct intel_crtc_state *crtc_state,
1647                           struct intel_plane_state *plane_state);
1648 void intel_fbc_post_update(struct intel_crtc *crtc);
1649 void intel_fbc_init(struct drm_i915_private *dev_priv);
1650 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1651 void intel_fbc_enable(struct intel_crtc *crtc,
1652                       struct intel_crtc_state *crtc_state,
1653                       struct intel_plane_state *plane_state);
1654 void intel_fbc_disable(struct intel_crtc *crtc);
1655 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1656 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1657                           unsigned int frontbuffer_bits,
1658                           enum fb_op_origin origin);
1659 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1660                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1661 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1662 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1663
1664 /* intel_hdmi.c */
1665 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1666                      enum port port);
1667 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1668                                struct intel_connector *intel_connector);
1669 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1670 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1671                                struct intel_crtc_state *pipe_config,
1672                                struct drm_connector_state *conn_state);
1673 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1674                                        struct drm_connector *connector,
1675                                        bool high_tmds_clock_ratio,
1676                                        bool scrambling);
1677 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1678 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1679
1680
1681 /* intel_lvds.c */
1682 void intel_lvds_init(struct drm_i915_private *dev_priv);
1683 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1684 bool intel_is_dual_link_lvds(struct drm_device *dev);
1685
1686
1687 /* intel_modes.c */
1688 int intel_connector_update_modes(struct drm_connector *connector,
1689                                  struct edid *edid);
1690 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1691 void intel_attach_force_audio_property(struct drm_connector *connector);
1692 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1693 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1694
1695
1696 /* intel_overlay.c */
1697 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1698 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1699 int intel_overlay_switch_off(struct intel_overlay *overlay);
1700 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1701                                   struct drm_file *file_priv);
1702 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1703                               struct drm_file *file_priv);
1704 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1705
1706
1707 /* intel_panel.c */
1708 int intel_panel_init(struct intel_panel *panel,
1709                      struct drm_display_mode *fixed_mode,
1710                      struct drm_display_mode *downclock_mode);
1711 void intel_panel_fini(struct intel_panel *panel);
1712 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1713                             struct drm_display_mode *adjusted_mode);
1714 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1715                              struct intel_crtc_state *pipe_config,
1716                              int fitting_mode);
1717 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1718                               struct intel_crtc_state *pipe_config,
1719                               int fitting_mode);
1720 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1721                                     u32 level, u32 max);
1722 int intel_panel_setup_backlight(struct drm_connector *connector,
1723                                 enum pipe pipe);
1724 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1725                                   const struct drm_connector_state *conn_state);
1726 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1727 void intel_panel_destroy_backlight(struct drm_connector *connector);
1728 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1729 extern struct drm_display_mode *intel_find_panel_downclock(
1730                                 struct drm_i915_private *dev_priv,
1731                                 struct drm_display_mode *fixed_mode,
1732                                 struct drm_connector *connector);
1733
1734 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1735 int intel_backlight_device_register(struct intel_connector *connector);
1736 void intel_backlight_device_unregister(struct intel_connector *connector);
1737 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1738 static inline int intel_backlight_device_register(struct intel_connector *connector)
1739 {
1740         return 0;
1741 }
1742 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1743 {
1744 }
1745 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1746
1747
1748 /* intel_psr.c */
1749 void intel_psr_enable(struct intel_dp *intel_dp,
1750                       const struct intel_crtc_state *crtc_state);
1751 void intel_psr_disable(struct intel_dp *intel_dp,
1752                       const struct intel_crtc_state *old_crtc_state);
1753 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1754                           unsigned frontbuffer_bits);
1755 void intel_psr_flush(struct drm_i915_private *dev_priv,
1756                      unsigned frontbuffer_bits,
1757                      enum fb_op_origin origin);
1758 void intel_psr_init(struct drm_i915_private *dev_priv);
1759 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1760                                    unsigned frontbuffer_bits);
1761 void intel_psr_compute_config(struct intel_dp *intel_dp,
1762                               struct intel_crtc_state *crtc_state);
1763
1764 /* intel_runtime_pm.c */
1765 int intel_power_domains_init(struct drm_i915_private *);
1766 void intel_power_domains_fini(struct drm_i915_private *);
1767 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1768 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1769 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1770 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1771 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1772 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1773 const char *
1774 intel_display_power_domain_str(enum intel_display_power_domain domain);
1775
1776 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1777                                     enum intel_display_power_domain domain);
1778 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1779                                       enum intel_display_power_domain domain);
1780 void intel_display_power_get(struct drm_i915_private *dev_priv,
1781                              enum intel_display_power_domain domain);
1782 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1783                                         enum intel_display_power_domain domain);
1784 void intel_display_power_put(struct drm_i915_private *dev_priv,
1785                              enum intel_display_power_domain domain);
1786
1787 static inline void
1788 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1789 {
1790         WARN_ONCE(dev_priv->runtime_pm.suspended,
1791                   "Device suspended during HW access\n");
1792 }
1793
1794 static inline void
1795 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1796 {
1797         assert_rpm_device_not_suspended(dev_priv);
1798         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1799                   "RPM wakelock ref not held during HW access");
1800 }
1801
1802 /**
1803  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1804  * @dev_priv: i915 device instance
1805  *
1806  * This function disable asserts that check if we hold an RPM wakelock
1807  * reference, while keeping the device-not-suspended checks still enabled.
1808  * It's meant to be used only in special circumstances where our rule about
1809  * the wakelock refcount wrt. the device power state doesn't hold. According
1810  * to this rule at any point where we access the HW or want to keep the HW in
1811  * an active state we must hold an RPM wakelock reference acquired via one of
1812  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1813  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1814  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1815  * users should avoid using this function.
1816  *
1817  * Any calls to this function must have a symmetric call to
1818  * enable_rpm_wakeref_asserts().
1819  */
1820 static inline void
1821 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1822 {
1823         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1824 }
1825
1826 /**
1827  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1828  * @dev_priv: i915 device instance
1829  *
1830  * This function re-enables the RPM assert checks after disabling them with
1831  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1832  * circumstances otherwise its use should be avoided.
1833  *
1834  * Any calls to this function must have a symmetric call to
1835  * disable_rpm_wakeref_asserts().
1836  */
1837 static inline void
1838 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1839 {
1840         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1841 }
1842
1843 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1844 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1845 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1846 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1847
1848 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1849
1850 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1851                              bool override, unsigned int mask);
1852 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1853                           enum dpio_channel ch, bool override);
1854
1855
1856 /* intel_pm.c */
1857 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1858 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1859 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1860 void intel_update_watermarks(struct intel_crtc *crtc);
1861 void intel_init_pm(struct drm_i915_private *dev_priv);
1862 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1863 void intel_pm_setup(struct drm_i915_private *dev_priv);
1864 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1865 void intel_gpu_ips_teardown(void);
1866 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1867 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1868 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1869 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1870 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1871 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1872 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1873 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1874 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1875 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1876 void gen6_rps_boost(struct drm_i915_gem_request *rq,
1877                     struct intel_rps_client *rps);
1878 void g4x_wm_get_hw_state(struct drm_device *dev);
1879 void vlv_wm_get_hw_state(struct drm_device *dev);
1880 void ilk_wm_get_hw_state(struct drm_device *dev);
1881 void skl_wm_get_hw_state(struct drm_device *dev);
1882 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1883                           struct skl_ddb_allocation *ddb /* out */);
1884 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1885                               struct skl_pipe_wm *out);
1886 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1887 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1888 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1889 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1890 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1891 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1892                          const struct skl_wm_level *l2);
1893 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
1894                                  const struct skl_ddb_entry **entries,
1895                                  const struct skl_ddb_entry *ddb,
1896                                  int ignore);
1897 bool ilk_disable_lp_wm(struct drm_device *dev);
1898 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1899 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1900                                   struct intel_crtc_state *cstate);
1901 void intel_init_ipc(struct drm_i915_private *dev_priv);
1902 void intel_enable_ipc(struct drm_i915_private *dev_priv);
1903 static inline int intel_rc6_enabled(void)
1904 {
1905         return i915_modparams.enable_rc6;
1906 }
1907
1908 /* intel_sdvo.c */
1909 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1910                      i915_reg_t reg, enum port port);
1911
1912
1913 /* intel_sprite.c */
1914 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1915                              int usecs);
1916 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1917                                               enum pipe pipe, int plane);
1918 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1919                               struct drm_file *file_priv);
1920 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
1921 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
1922 void skl_update_plane(struct intel_plane *plane,
1923                       const struct intel_crtc_state *crtc_state,
1924                       const struct intel_plane_state *plane_state);
1925 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
1926 bool skl_plane_get_hw_state(struct intel_plane *plane);
1927
1928 /* intel_tv.c */
1929 void intel_tv_init(struct drm_i915_private *dev_priv);
1930
1931 /* intel_atomic.c */
1932 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1933                                                 const struct drm_connector_state *state,
1934                                                 struct drm_property *property,
1935                                                 uint64_t *val);
1936 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1937                                                 struct drm_connector_state *state,
1938                                                 struct drm_property *property,
1939                                                 uint64_t val);
1940 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1941                                          struct drm_connector_state *new_state);
1942 struct drm_connector_state *
1943 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1944
1945 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1946 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1947                                struct drm_crtc_state *state);
1948 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1949 void intel_atomic_state_clear(struct drm_atomic_state *);
1950
1951 static inline struct intel_crtc_state *
1952 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1953                             struct intel_crtc *crtc)
1954 {
1955         struct drm_crtc_state *crtc_state;
1956         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1957         if (IS_ERR(crtc_state))
1958                 return ERR_CAST(crtc_state);
1959
1960         return to_intel_crtc_state(crtc_state);
1961 }
1962
1963 static inline struct intel_crtc_state *
1964 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1965                                      struct intel_crtc *crtc)
1966 {
1967         struct drm_crtc_state *crtc_state;
1968
1969         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1970
1971         if (crtc_state)
1972                 return to_intel_crtc_state(crtc_state);
1973         else
1974                 return NULL;
1975 }
1976
1977 static inline struct intel_plane_state *
1978 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1979                                       struct intel_plane *plane)
1980 {
1981         struct drm_plane_state *plane_state;
1982
1983         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1984
1985         return to_intel_plane_state(plane_state);
1986 }
1987
1988 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1989                                struct intel_crtc *intel_crtc,
1990                                struct intel_crtc_state *crtc_state);
1991
1992 /* intel_atomic_plane.c */
1993 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1994 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1995 void intel_plane_destroy_state(struct drm_plane *plane,
1996                                struct drm_plane_state *state);
1997 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1998 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
1999                                         struct intel_crtc_state *crtc_state,
2000                                         const struct intel_plane_state *old_plane_state,
2001                                         struct intel_plane_state *intel_state);
2002
2003 /* intel_color.c */
2004 void intel_color_init(struct drm_crtc *crtc);
2005 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2006 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2007 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2008
2009 /* intel_lspcon.c */
2010 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2011 void lspcon_resume(struct intel_lspcon *lspcon);
2012 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2013
2014 /* intel_pipe_crc.c */
2015 int intel_pipe_crc_create(struct drm_minor *minor);
2016 #ifdef CONFIG_DEBUG_FS
2017 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2018                               size_t *values_cnt);
2019 #else
2020 #define intel_crtc_set_crc_source NULL
2021 #endif
2022 extern const struct file_operations i915_display_crc_ctl_fops;
2023 #endif /* __INTEL_DRV_H__ */